diff options
Diffstat (limited to 'include')
793 files changed, 14 insertions, 62504 deletions
diff --git a/include/asm-arm/arch-aaec2000/aaec2000.h b/include/asm-arm/arch-aaec2000/aaec2000.h deleted file mode 100644 index a6d1ee0980f2..000000000000 --- a/include/asm-arm/arch-aaec2000/aaec2000.h +++ /dev/null | |||
| @@ -1,207 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/aaec2000.h | ||
| 3 | * | ||
| 4 | * AAEC-2000 registers definition | ||
| 5 | * | ||
| 6 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_AAEC2000_H | ||
| 14 | #define __ASM_ARCH_AAEC2000_H | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 17 | #error You must include hardware.h not this file | ||
| 18 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
| 19 | |||
| 20 | /* Chip selects */ | ||
| 21 | #define AAEC_CS0 0x00000000 | ||
| 22 | #define AAEC_CS1 0x10000000 | ||
| 23 | #define AAEC_CS2 0x20000000 | ||
| 24 | #define AAEC_CS3 0x30000000 | ||
| 25 | |||
| 26 | /* Flash */ | ||
| 27 | #define AAEC_FLASH_BASE AAEC_CS0 | ||
| 28 | #define AAEC_FLASH_SIZE SZ_64M | ||
| 29 | |||
| 30 | /* Interrupt controller */ | ||
| 31 | #define IRQ_BASE __REG(0x80000500) | ||
| 32 | #define IRQ_INTSR __REG(0x80000500) /* Int Status Register */ | ||
| 33 | #define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */ | ||
| 34 | #define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */ | ||
| 35 | #define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */ | ||
| 36 | |||
| 37 | /* UART 1 */ | ||
| 38 | #define UART1_BASE __REG(0x80000600) | ||
| 39 | #define UART1_DR __REG(0x80000600) /* Data/FIFO Register */ | ||
| 40 | #define UART1_LCR __REG(0x80000604) /* Link Control Register */ | ||
| 41 | #define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */ | ||
| 42 | #define UART1_CR __REG(0x8000060c) /* Control Register */ | ||
| 43 | #define UART1_SR __REG(0x80000610) /* Status Register */ | ||
| 44 | #define UART1_INT __REG(0x80000614) /* Interrupt Status Register */ | ||
| 45 | #define UART1_INTM __REG(0x80000618) /* Interrupt Mask Register */ | ||
| 46 | #define UART1_INTRES __REG(0x8000061c) /* Int Result (masked status) Register */ | ||
| 47 | |||
| 48 | /* UART 2 */ | ||
| 49 | #define UART2_BASE __REG(0x80000700) | ||
| 50 | #define UART2_DR __REG(0x80000700) /* Data/FIFO Register */ | ||
| 51 | #define UART2_LCR __REG(0x80000704) /* Link Control Register */ | ||
| 52 | #define UART2_BRCR __REG(0x80000708) /* Baud Rate Control Register */ | ||
| 53 | #define UART2_CR __REG(0x8000070c) /* Control Register */ | ||
| 54 | #define UART2_SR __REG(0x80000710) /* Status Register */ | ||
| 55 | #define UART2_INT __REG(0x80000714) /* Interrupt Status Register */ | ||
| 56 | #define UART2_INTM __REG(0x80000718) /* Interrupt Mask Register */ | ||
| 57 | #define UART2_INTRES __REG(0x8000071c) /* Int Result (masked status) Register */ | ||
| 58 | |||
| 59 | /* UART 3 */ | ||
| 60 | #define UART3_BASE __REG(0x80000800) | ||
| 61 | #define UART3_DR __REG(0x80000800) /* Data/FIFO Register */ | ||
| 62 | #define UART3_LCR __REG(0x80000804) /* Link Control Register */ | ||
| 63 | #define UART3_BRCR __REG(0x80000808) /* Baud Rate Control Register */ | ||
| 64 | #define UART3_CR __REG(0x8000080c) /* Control Register */ | ||
| 65 | #define UART3_SR __REG(0x80000810) /* Status Register */ | ||
| 66 | #define UART3_INT __REG(0x80000814) /* Interrupt Status Register */ | ||
| 67 | #define UART3_INTM __REG(0x80000818) /* Interrupt Mask Register */ | ||
| 68 | #define UART3_INTRES __REG(0x8000081c) /* Int Result (masked status) Register */ | ||
| 69 | |||
| 70 | /* These are used in some places */ | ||
| 71 | #define _UART1_BASE __PREG(UART1_BASE) | ||
| 72 | #define _UART2_BASE __PREG(UART2_BASE) | ||
| 73 | #define _UART3_BASE __PREG(UART3_BASE) | ||
| 74 | |||
| 75 | /* UART Registers Offsets */ | ||
| 76 | #define UART_DR 0x00 | ||
| 77 | #define UART_LCR 0x04 | ||
| 78 | #define UART_BRCR 0x08 | ||
| 79 | #define UART_CR 0x0c | ||
| 80 | #define UART_SR 0x10 | ||
| 81 | #define UART_INT 0x14 | ||
| 82 | #define UART_INTM 0x18 | ||
| 83 | #define UART_INTRES 0x1c | ||
| 84 | |||
| 85 | /* UART_LCR Bitmask */ | ||
| 86 | #define UART_LCR_BRK (1 << 0) /* Send Break */ | ||
| 87 | #define UART_LCR_PEN (1 << 1) /* Parity Enable */ | ||
| 88 | #define UART_LCR_EP (1 << 2) /* Even/Odd Parity */ | ||
| 89 | #define UART_LCR_S2 (1 << 3) /* One/Two Stop bits */ | ||
| 90 | #define UART_LCR_FIFO (1 << 4) /* FIFO Enable */ | ||
| 91 | #define UART_LCR_WL5 (0 << 5) /* Word Length - 5 bits */ | ||
| 92 | #define UART_LCR_WL6 (1 << 5) /* Word Length - 6 bits */ | ||
| 93 | #define UART_LCR_WL7 (1 << 6) /* Word Length - 7 bits */ | ||
| 94 | #define UART_LCR_WL8 (1 << 7) /* Word Length - 8 bits */ | ||
| 95 | |||
| 96 | /* UART_CR Bitmask */ | ||
| 97 | #define UART_CR_EN (1 << 0) /* UART Enable */ | ||
| 98 | #define UART_CR_SIR (1 << 1) /* IrDA SIR Enable */ | ||
| 99 | #define UART_CR_SIRLP (1 << 2) /* Low Power IrDA Enable */ | ||
| 100 | #define UART_CR_RXP (1 << 3) /* Receive Pin Polarity */ | ||
| 101 | #define UART_CR_TXP (1 << 4) /* Transmit Pin Polarity */ | ||
| 102 | #define UART_CR_MXP (1 << 5) /* Modem Pin Polarity */ | ||
| 103 | #define UART_CR_LOOP (1 << 6) /* Loopback Mode */ | ||
| 104 | |||
| 105 | /* UART_SR Bitmask */ | ||
| 106 | #define UART_SR_CTS (1 << 0) /* Clear To Send Status */ | ||
| 107 | #define UART_SR_DSR (1 << 1) /* Data Set Ready Status */ | ||
| 108 | #define UART_SR_DCD (1 << 2) /* Data Carrier Detect Status */ | ||
| 109 | #define UART_SR_TxBSY (1 << 3) /* Transmitter Busy Status */ | ||
| 110 | #define UART_SR_RxFE (1 << 4) /* Receive FIFO Empty Status */ | ||
| 111 | #define UART_SR_TxFF (1 << 5) /* Transmit FIFO Full Status */ | ||
| 112 | #define UART_SR_RxFF (1 << 6) /* Receive FIFO Full Status */ | ||
| 113 | #define UART_SR_TxFE (1 << 7) /* Transmit FIFO Empty Status */ | ||
| 114 | |||
| 115 | /* UART_INT Bitmask */ | ||
| 116 | #define UART_INT_RIS (1 << 0) /* Rx Interrupt */ | ||
| 117 | #define UART_INT_TIS (1 << 1) /* Tx Interrupt */ | ||
| 118 | #define UART_INT_MIS (1 << 2) /* Modem Interrupt */ | ||
| 119 | #define UART_INT_RTIS (1 << 3) /* Receive Timeout Interrupt */ | ||
| 120 | |||
| 121 | /* Timer 1 */ | ||
| 122 | #define TIMER1_BASE __REG(0x80000c00) | ||
| 123 | #define TIMER1_LOAD __REG(0x80000c00) /* Timer 1 Load Register */ | ||
| 124 | #define TIMER1_VAL __REG(0x80000c04) /* Timer 1 Value Register */ | ||
| 125 | #define TIMER1_CTRL __REG(0x80000c08) /* Timer 1 Control Register */ | ||
| 126 | #define TIMER1_CLEAR __REG(0x80000c0c) /* Timer 1 Clear Register */ | ||
| 127 | |||
| 128 | /* Timer 2 */ | ||
| 129 | #define TIMER2_BASE __REG(0x80000d00) | ||
| 130 | #define TIMER2_LOAD __REG(0x80000d00) /* Timer 2 Load Register */ | ||
| 131 | #define TIMER2_VAL __REG(0x80000d04) /* Timer 2 Value Register */ | ||
| 132 | #define TIMER2_CTRL __REG(0x80000d08) /* Timer 2 Control Register */ | ||
| 133 | #define TIMER2_CLEAR __REG(0x80000d0c) /* Timer 2 Clear Register */ | ||
| 134 | |||
| 135 | /* Timer 3 */ | ||
| 136 | #define TIMER3_BASE __REG(0x80000e00) | ||
| 137 | #define TIMER3_LOAD __REG(0x80000e00) /* Timer 3 Load Register */ | ||
| 138 | #define TIMER3_VAL __REG(0x80000e04) /* Timer 3 Value Register */ | ||
| 139 | #define TIMER3_CTRL __REG(0x80000e08) /* Timer 3 Control Register */ | ||
| 140 | #define TIMER3_CLEAR __REG(0x80000e0c) /* Timer 3 Clear Register */ | ||
| 141 | |||
| 142 | /* Timer Control register bits */ | ||
| 143 | #define TIMER_CTRL_ENABLE (1 << 7) /* Enable (Start Timer) */ | ||
| 144 | #define TIMER_CTRL_PERIODIC (1 << 6) /* Periodic Running Mode */ | ||
| 145 | #define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */ | ||
| 146 | #define TIMER_CTRL_CLKSEL_508K (1 << 3) /* 508KHz Clock select (Timer 1, 2) */ | ||
| 147 | #define TIMER_CTRL_CLKSEL_2K (0 << 3) /* 2KHz Clock Select (Timer 1, 2) */ | ||
| 148 | |||
| 149 | /* Power and State Control */ | ||
| 150 | #define POWER_BASE __REG(0x80000400) | ||
| 151 | #define POWER_PWRSR __REG(0x80000400) /* Power Status Register */ | ||
| 152 | #define POWER_PWRCNT __REG(0x80000404) /* Power/Clock control */ | ||
| 153 | #define POWER_HALT __REG(0x80000408) /* Power Idle Mode */ | ||
| 154 | #define POWER_STDBY __REG(0x8000040c) /* Power Standby Mode */ | ||
| 155 | #define POWER_BLEOI __REG(0x80000410) /* Battery Low End of Interrupt */ | ||
| 156 | #define POWER_MCEOI __REG(0x80000414) /* Media Changed EoI */ | ||
| 157 | #define POWER_TEOI __REG(0x80000418) /* Tick EoI */ | ||
| 158 | #define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */ | ||
| 159 | #define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */ | ||
| 160 | |||
| 161 | /* GPIO Registers */ | ||
| 162 | #define AAEC_GPIO_PHYS 0x80000e00 | ||
| 163 | |||
| 164 | #define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00) | ||
| 165 | #define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04) | ||
| 166 | #define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08) | ||
| 167 | #define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c) | ||
| 168 | #define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10) | ||
| 169 | #define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14) | ||
| 170 | #define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18) | ||
| 171 | #define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c) | ||
| 172 | #define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20) | ||
| 173 | #define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24) | ||
| 174 | #define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28) | ||
| 175 | #define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c) | ||
| 176 | #define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30) | ||
| 177 | #define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34) | ||
| 178 | #define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38) | ||
| 179 | #define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c) | ||
| 180 | #define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40) | ||
| 181 | #define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44) | ||
| 182 | #define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48) | ||
| 183 | #define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c) | ||
| 184 | #define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50) | ||
| 185 | #define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54) | ||
| 186 | #define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58) | ||
| 187 | #define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c) | ||
| 188 | #define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60) | ||
| 189 | #define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64) | ||
| 190 | #define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68) | ||
| 191 | #define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c) | ||
| 192 | #define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70) | ||
| 193 | #define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74) | ||
| 194 | #define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78) | ||
| 195 | #define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c) | ||
| 196 | #define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80) | ||
| 197 | #define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84) | ||
| 198 | |||
| 199 | #define AAEC_GPIO_PINMUX_PE0CON (1 << 0) | ||
| 200 | #define AAEC_GPIO_PINMUX_PD0CON (1 << 1) | ||
| 201 | #define AAEC_GPIO_PINMUX_CODECON (1 << 2) | ||
| 202 | #define AAEC_GPIO_PINMUX_UART3CON (1 << 3) | ||
| 203 | |||
| 204 | /* LCD Controller */ | ||
| 205 | #define AAEC_CLCD_PHYS 0x80003000 | ||
| 206 | |||
| 207 | #endif /* __ARM_ARCH_AAEC2000_H */ | ||
diff --git a/include/asm-arm/arch-aaec2000/aaed2000.h b/include/asm-arm/arch-aaec2000/aaed2000.h deleted file mode 100644 index bc76d2badb91..000000000000 --- a/include/asm-arm/arch-aaec2000/aaed2000.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/aaed2000.h | ||
| 3 | * | ||
| 4 | * AAED-2000 specific bits definition | ||
| 5 | * | ||
| 6 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_AAED2000_H | ||
| 14 | #define __ASM_ARCH_AAED2000_H | ||
| 15 | |||
| 16 | /* External GPIOs. */ | ||
| 17 | |||
| 18 | #define EXT_GPIO_PBASE AAEC_CS3 | ||
| 19 | #define EXT_GPIO_VBASE 0xf8100000 | ||
| 20 | #define EXT_GPIO_LENGTH 0x00001000 | ||
| 21 | |||
| 22 | #define __ext_gpio_p2v(x) ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE) | ||
| 23 | #define __ext_gpio_v2p(x) ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE) | ||
| 24 | |||
| 25 | #define __EXT_GPIO_REG(x) (*((volatile u32 *)__ext_gpio_p2v(x))) | ||
| 26 | #define __EXT_GPIO_PREG(x) (__ext_gpio_v2p((u32)&(x))) | ||
| 27 | |||
| 28 | #define AAED_EXT_GPIO __EXT_GPIO_REG(EXT_GPIO_PBASE) | ||
| 29 | |||
| 30 | #define AAED_EGPIO_KBD_SCAN 0x00003fff /* Keyboard scan data */ | ||
| 31 | #define AAED_EGPIO_PWR_INT 0x00008fff /* Smart battery charger interrupt */ | ||
| 32 | #define AAED_EGPIO_SWITCHED 0x000f0000 /* DIP Switches */ | ||
| 33 | #define AAED_EGPIO_USB_VBUS 0x00400000 /* USB Vbus sense */ | ||
| 34 | #define AAED_EGPIO_LCD_PWR_EN 0x02000000 /* LCD and backlight PWR enable */ | ||
| 35 | #define AAED_EGPIO_nLED0 0x20000000 /* LED 0 */ | ||
| 36 | #define AAED_EGPIO_nLED1 0x20000000 /* LED 1 */ | ||
| 37 | #define AAED_EGPIO_nLED2 0x20000000 /* LED 2 */ | ||
| 38 | |||
| 39 | |||
| 40 | #endif /* __ARM_ARCH_AAED2000_H */ | ||
diff --git a/include/asm-arm/arch-aaec2000/debug-macro.S b/include/asm-arm/arch-aaec2000/debug-macro.S deleted file mode 100644 index 7b1fce021d8a..000000000000 --- a/include/asm-arm/arch-aaec2000/debug-macro.S +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-aaec2000/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include "hardware.h" | ||
| 13 | .macro addruart,rx | ||
| 14 | mrc p15, 0, \rx, c1, c0 | ||
| 15 | tst \rx, #1 @ MMU enabled? | ||
| 16 | moveq \rx, #0x80000000 @ physical | ||
| 17 | movne \rx, #io_p2v(0x80000000) @ virtual | ||
| 18 | orr \rx, \rx, #0x00000800 | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro senduart,rd,rx | ||
| 22 | str \rd, [\rx, #0] | ||
| 23 | .endm | ||
| 24 | |||
| 25 | .macro busyuart,rd,rx | ||
| 26 | 1002: ldr \rd, [\rx, #0x10] | ||
| 27 | tst \rd, #(1 << 7) | ||
| 28 | beq 1002b | ||
| 29 | .endm | ||
| 30 | |||
| 31 | .macro waituart,rd,rx | ||
| 32 | #if 0 | ||
| 33 | 1001: ldr \rd, [\rx, #0x10] | ||
| 34 | tst \rd, #(1 << 5) | ||
| 35 | beq 1001b | ||
| 36 | #endif | ||
| 37 | .endm | ||
diff --git a/include/asm-arm/arch-aaec2000/dma.h b/include/asm-arm/arch-aaec2000/dma.h deleted file mode 100644 index e100b1e526fe..000000000000 --- a/include/asm-arm/arch-aaec2000/dma.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
diff --git a/include/asm-arm/arch-aaec2000/entry-macro.S b/include/asm-arm/arch-aaec2000/entry-macro.S deleted file mode 100644 index 83fdf68f6b7c..000000000000 --- a/include/asm-arm/arch-aaec2000/entry-macro.S +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper for aaec-2000 based platforms | ||
| 5 | * | ||
| 6 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #include <asm/arch/irqs.h> | ||
| 14 | |||
| 15 | .macro disable_fiq | ||
| 16 | .endm | ||
| 17 | |||
| 18 | .macro get_irqnr_preamble, base, tmp | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 25 | mov r4, #0xf8000000 | ||
| 26 | add r4, r4, #0x00000500 | ||
| 27 | mov \base, r4 | ||
| 28 | ldr \irqstat, [\base, #0] | ||
| 29 | cmp \irqstat, #0 | ||
| 30 | bne 1001f | ||
| 31 | ldr \irqnr, =NR_IRQS+1 | ||
| 32 | b 1003f | ||
| 33 | 1001: mov \irqnr, #0 | ||
| 34 | 1002: ands \tmp, \irqstat, #1 | ||
| 35 | mov \irqstat, \irqstat, LSR #1 | ||
| 36 | add \irqnr, \irqnr, #1 | ||
| 37 | beq 1002b | ||
| 38 | sub \irqnr, \irqnr, #1 | ||
| 39 | 1003: | ||
| 40 | .endm | ||
diff --git a/include/asm-arm/arch-aaec2000/hardware.h b/include/asm-arm/arch-aaec2000/hardware.h deleted file mode 100644 index 153506fd06ed..000000000000 --- a/include/asm-arm/arch-aaec2000/hardware.h +++ /dev/null | |||
| @@ -1,50 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 12 | #define __ASM_ARCH_HARDWARE_H | ||
| 13 | |||
| 14 | #include <asm/sizes.h> | ||
| 15 | #include <asm/arch/aaec2000.h> | ||
| 16 | |||
| 17 | /* The kernel is loaded at physical address 0xf8000000. | ||
| 18 | * We map the IO space a bit after | ||
| 19 | */ | ||
| 20 | #define PIO_APB_BASE 0x80000000 | ||
| 21 | #define VIO_APB_BASE 0xf8000000 | ||
| 22 | #define IO_APB_LENGTH 0x2000 | ||
| 23 | #define PIO_AHB_BASE 0x80002000 | ||
| 24 | #define VIO_AHB_BASE 0xf8002000 | ||
| 25 | #define IO_AHB_LENGTH 0x2000 | ||
| 26 | |||
| 27 | #define VIO_BASE VIO_APB_BASE | ||
| 28 | #define PIO_BASE PIO_APB_BASE | ||
| 29 | |||
| 30 | #define io_p2v(x) ( (x) - PIO_BASE + VIO_BASE ) | ||
| 31 | #define io_v2p(x) ( (x) + PIO_BASE - VIO_BASE ) | ||
| 32 | |||
| 33 | #ifndef __ASSEMBLY__ | ||
| 34 | |||
| 35 | #include <asm/types.h> | ||
| 36 | |||
| 37 | /* FIXME: Is it needed to optimize this a la pxa ?? */ | ||
| 38 | #define __REG(x) (*((volatile u32 *)io_p2v(x))) | ||
| 39 | #define __PREG(x) (io_v2p((u32)&(x))) | ||
| 40 | |||
| 41 | #else /* __ASSEMBLY__ */ | ||
| 42 | |||
| 43 | #define __REG(x) io_p2v(x) | ||
| 44 | #define __PREG(x) io_v2p(x) | ||
| 45 | |||
| 46 | #endif | ||
| 47 | |||
| 48 | #include "aaec2000.h" | ||
| 49 | |||
| 50 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-aaec2000/io.h b/include/asm-arm/arch-aaec2000/io.h deleted file mode 100644 index bc2364ab8752..000000000000 --- a/include/asm-arm/arch-aaec2000/io.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/io.h | ||
| 3 | * | ||
| 4 | * Copied from asm/arch/sa1100/io.h | ||
| 5 | */ | ||
| 6 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 7 | #define __ASM_ARM_ARCH_IO_H | ||
| 8 | |||
| 9 | #include <asm/arch/hardware.h> | ||
| 10 | |||
| 11 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 12 | |||
| 13 | /* | ||
| 14 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
| 15 | * drivers out there that might just work if we fake them... | ||
| 16 | */ | ||
| 17 | #define __io(a) ((void __iomem *)(a)) | ||
| 18 | #define __mem_pci(a) (a) | ||
| 19 | |||
| 20 | #endif | ||
diff --git a/include/asm-arm/arch-aaec2000/irqs.h b/include/asm-arm/arch-aaec2000/irqs.h deleted file mode 100644 index de252220e806..000000000000 --- a/include/asm-arm/arch-aaec2000/irqs.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_IRQS_H | ||
| 12 | #define __ASM_ARCH_IRQS_H | ||
| 13 | |||
| 14 | |||
| 15 | #define INT_GPIOF0_FIQ 0 /* External GPIO Port F O Fast Interrupt Input */ | ||
| 16 | #define INT_BL_FIQ 1 /* Battery Low Fast Interrupt */ | ||
| 17 | #define INT_WE_FIQ 2 /* Watchdog Expired Fast Interrupt */ | ||
| 18 | #define INT_MV_FIQ 3 /* Media Changed Interrupt */ | ||
| 19 | #define INT_SC 4 /* Sound Codec Interrupt */ | ||
| 20 | #define INT_GPIO1 5 /* GPIO Port F Configurable Int 1 */ | ||
| 21 | #define INT_GPIO2 6 /* GPIO Port F Configurable Int 2 */ | ||
| 22 | #define INT_GPIO3 7 /* GPIO Port F Configurable Int 3 */ | ||
| 23 | #define INT_TMR1_OFL 8 /* Timer 1 Overflow Interrupt */ | ||
| 24 | #define INT_TMR2_OFL 9 /* Timer 2 Overflow Interrupt */ | ||
| 25 | #define INT_RTC_CM 10 /* RTC Compare Match Interrupt */ | ||
| 26 | #define INT_TICK 11 /* 64Hz Tick Interrupt */ | ||
| 27 | #define INT_UART1 12 /* UART1 Interrupt */ | ||
| 28 | #define INT_UART2 13 /* UART2 & Modem State Changed Interrupt */ | ||
| 29 | #define INT_LCD 14 /* LCD Interrupt */ | ||
| 30 | #define INT_SSI 15 /* SSI End of Transfer Interrupt */ | ||
| 31 | #define INT_UART3 16 /* UART3 Interrupt */ | ||
| 32 | #define INT_SCI 17 /* SCI Interrupt */ | ||
| 33 | #define INT_AAC 18 /* Advanced Audio Codec Interrupt */ | ||
| 34 | #define INT_MMC 19 /* MMC Interrupt */ | ||
| 35 | #define INT_USB 20 /* USB Interrupt */ | ||
| 36 | #define INT_DMA 21 /* DMA Interrupt */ | ||
| 37 | #define INT_TMR3_UOFL 22 /* Timer 3 Underflow Interrupt */ | ||
| 38 | #define INT_GPIO4 23 /* GPIO Port F Configurable Int 4 */ | ||
| 39 | #define INT_GPIO5 24 /* GPIO Port F Configurable Int 4 */ | ||
| 40 | #define INT_GPIO6 25 /* GPIO Port F Configurable Int 4 */ | ||
| 41 | #define INT_GPIO7 26 /* GPIO Port F Configurable Int 4 */ | ||
| 42 | #define INT_BMI 27 /* BMI Interrupt */ | ||
| 43 | |||
| 44 | #define NR_IRQS (INT_BMI + 1) | ||
| 45 | |||
| 46 | #endif /* __ASM_ARCH_IRQS_H */ | ||
diff --git a/include/asm-arm/arch-aaec2000/memory.h b/include/asm-arm/arch-aaec2000/memory.h deleted file mode 100644 index 9eceb4148922..000000000000 --- a/include/asm-arm/arch-aaec2000/memory.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 12 | #define __ASM_ARCH_MEMORY_H | ||
| 13 | |||
| 14 | |||
| 15 | #define PHYS_OFFSET UL(0xf0000000) | ||
| 16 | |||
| 17 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 18 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 19 | |||
| 20 | /* | ||
| 21 | * The nodes are the followings: | ||
| 22 | * | ||
| 23 | * node 0: 0xf000.0000 - 0xf3ff.ffff | ||
| 24 | * node 1: 0xf400.0000 - 0xf7ff.ffff | ||
| 25 | * node 2: 0xf800.0000 - 0xfbff.ffff | ||
| 26 | * node 3: 0xfc00.0000 - 0xffff.ffff | ||
| 27 | */ | ||
| 28 | #define NODE_MEM_SIZE_BITS 26 | ||
| 29 | |||
| 30 | #endif /* __ASM_ARCH_MEMORY_H */ | ||
diff --git a/include/asm-arm/arch-aaec2000/system.h b/include/asm-arm/arch-aaec2000/system.h deleted file mode 100644 index 08de97b407a8..000000000000 --- a/include/asm-arm/arch-aaec2000/system.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaed2000/system.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 12 | #define __ASM_ARCH_SYSTEM_H | ||
| 13 | |||
| 14 | static inline void arch_idle(void) | ||
| 15 | { | ||
| 16 | cpu_do_idle(); | ||
| 17 | } | ||
| 18 | |||
| 19 | static inline void arch_reset(char mode) | ||
| 20 | { | ||
| 21 | cpu_reset(0); | ||
| 22 | } | ||
| 23 | |||
| 24 | #endif /* __ASM_ARCH_SYSTEM_H */ | ||
diff --git a/include/asm-arm/arch-aaec2000/timex.h b/include/asm-arm/arch-aaec2000/timex.h deleted file mode 100644 index f5708b38fb7f..000000000000 --- a/include/asm-arm/arch-aaec2000/timex.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/timex.h | ||
| 3 | * | ||
| 4 | * AAEC-2000 Architecture timex specification | ||
| 5 | * | ||
| 6 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 14 | #define __ASM_ARCH_TIMEX_H | ||
| 15 | |||
| 16 | #define CLOCK_TICK_RATE 508000 | ||
| 17 | |||
| 18 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/include/asm-arm/arch-aaec2000/uncompress.h b/include/asm-arm/arch-aaec2000/uncompress.h deleted file mode 100644 index 300f4bf3bc74..000000000000 --- a/include/asm-arm/arch-aaec2000/uncompress.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
| 12 | #define __ASM_ARCH_UNCOMPRESS_H | ||
| 13 | |||
| 14 | #include "hardware.h" | ||
| 15 | |||
| 16 | #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) | ||
| 17 | |||
| 18 | static void putc(int c) | ||
| 19 | { | ||
| 20 | unsigned long serial_port; | ||
| 21 | do { | ||
| 22 | serial_port = _UART3_BASE; | ||
| 23 | if (UART(UART_CR) & UART_CR_EN) break; | ||
| 24 | serial_port = _UART1_BASE; | ||
| 25 | if (UART(UART_CR) & UART_CR_EN) break; | ||
| 26 | serial_port = _UART2_BASE; | ||
| 27 | if (UART(UART_CR) & UART_CR_EN) break; | ||
| 28 | return; | ||
| 29 | } while (0); | ||
| 30 | |||
| 31 | /* wait for space in the UART's transmitter */ | ||
| 32 | while ((UART(UART_SR) & UART_SR_TxFF)) | ||
| 33 | barrier(); | ||
| 34 | |||
| 35 | /* send the character out. */ | ||
| 36 | UART(UART_DR) = c; | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void flush(void) | ||
| 40 | { | ||
| 41 | } | ||
| 42 | |||
| 43 | #define arch_decomp_setup() | ||
| 44 | #define arch_decomp_wdog() | ||
| 45 | |||
| 46 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/include/asm-arm/arch-aaec2000/vmalloc.h b/include/asm-arm/arch-aaec2000/vmalloc.h deleted file mode 100644 index ecb991e2e4ff..000000000000 --- a/include/asm-arm/arch-aaec2000/vmalloc.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-aaec2000/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Nicolas Bellido Y Ortega | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_VMALLOC_H | ||
| 12 | #define __ASM_ARCH_VMALLOC_H | ||
| 13 | |||
| 14 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
| 15 | |||
| 16 | #endif /* __ASM_ARCH_VMALLOC_H */ | ||
diff --git a/include/asm-arm/arch-at91/at91_adc.h b/include/asm-arm/arch-at91/at91_adc.h deleted file mode 100644 index 6d71ea2637b1..000000000000 --- a/include/asm-arm/arch-at91/at91_adc.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_adc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Analog-to-Digital Converter (ADC) registers. | ||
| 7 | * Based on AT91SAM9260 datasheet revision D. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91_ADC_H | ||
| 16 | #define AT91_ADC_H | ||
| 17 | |||
| 18 | #define AT91_ADC_CR 0x00 /* Control Register */ | ||
| 19 | #define AT91_ADC_SWRST (1 << 0) /* Software Reset */ | ||
| 20 | #define AT91_ADC_START (1 << 1) /* Start Conversion */ | ||
| 21 | |||
| 22 | #define AT91_ADC_MR 0x04 /* Mode Register */ | ||
| 23 | #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ | ||
| 24 | #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ | ||
| 25 | #define AT91_ADC_TRGSEL_TC0 (0 << 1) | ||
| 26 | #define AT91_ADC_TRGSEL_TC1 (1 << 1) | ||
| 27 | #define AT91_ADC_TRGSEL_TC2 (2 << 1) | ||
| 28 | #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) | ||
| 29 | #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ | ||
| 30 | #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ | ||
| 31 | #define AT91_ADC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */ | ||
| 32 | #define AT91_ADC_PRESCAL_(x) ((x) << 8) | ||
| 33 | #define AT91_ADC_STARTUP (0x1f << 16) /* Startup Up Time */ | ||
| 34 | #define AT91_ADC_STARTUP_(x) ((x) << 16) | ||
| 35 | #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ | ||
| 36 | #define AT91_ADC_SHTIM_(x) ((x) << 24) | ||
| 37 | |||
| 38 | #define AT91_ADC_CHER 0x10 /* Channel Enable Register */ | ||
| 39 | #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ | ||
| 40 | #define AT91_ADC_CHSR 0x18 /* Channel Status Register */ | ||
| 41 | #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ | ||
| 42 | |||
| 43 | #define AT91_ADC_SR 0x1C /* Status Register */ | ||
| 44 | #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ | ||
| 45 | #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ | ||
| 46 | #define AT91_ADC_DRDY (1 << 16) /* Data Ready */ | ||
| 47 | #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ | ||
| 48 | #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ | ||
| 49 | #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ | ||
| 50 | |||
| 51 | #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ | ||
| 52 | #define AT91_ADC_LDATA (0x3ff) | ||
| 53 | |||
| 54 | #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ | ||
| 55 | #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ | ||
| 56 | #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ | ||
| 57 | |||
| 58 | #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ | ||
| 59 | #define AT91_ADC_DATA (0x3ff) | ||
| 60 | |||
| 61 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_aic.h b/include/asm-arm/arch-at91/at91_aic.h deleted file mode 100644 index df44c12a12d4..000000000000 --- a/include/asm-arm/arch-at91/at91_aic.h +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_aic.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Advanced Interrupt Controller (AIC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_AIC_H | ||
| 17 | #define AT91_AIC_H | ||
| 18 | |||
| 19 | #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ | ||
| 20 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ | ||
| 21 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ | ||
| 22 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) | ||
| 23 | #define AT91_AIC_SRCTYPE_FALLING (1 << 5) | ||
| 24 | #define AT91_AIC_SRCTYPE_HIGH (2 << 5) | ||
| 25 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) | ||
| 26 | |||
| 27 | #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ | ||
| 28 | #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ | ||
| 29 | #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ | ||
| 30 | #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ | ||
| 31 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ | ||
| 32 | |||
| 33 | #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ | ||
| 34 | #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ | ||
| 35 | #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ | ||
| 36 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ | ||
| 37 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ | ||
| 38 | |||
| 39 | #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ | ||
| 40 | #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ | ||
| 41 | #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ | ||
| 42 | #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ | ||
| 43 | #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ | ||
| 44 | #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ | ||
| 45 | #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ | ||
| 46 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ | ||
| 47 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ | ||
| 48 | |||
| 49 | #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ | ||
| 50 | #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ | ||
| 51 | #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ | ||
| 52 | |||
| 53 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h deleted file mode 100644 index 8019ffd0ad3b..000000000000 --- a/include/asm-arm/arch-at91/at91_dbgu.h +++ /dev/null | |||
| @@ -1,66 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_dbgu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Debug Unit (DBGU) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_DBGU_H | ||
| 17 | #define AT91_DBGU_H | ||
| 18 | |||
| 19 | #ifdef AT91_DBGU | ||
| 20 | #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ | ||
| 21 | #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ | ||
| 22 | #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ | ||
| 23 | #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ | ||
| 24 | #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ | ||
| 25 | #define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ | ||
| 26 | #define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ | ||
| 27 | #define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ | ||
| 28 | #define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ | ||
| 29 | #define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ | ||
| 30 | #define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ | ||
| 31 | |||
| 32 | #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ | ||
| 33 | #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ | ||
| 34 | #define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ | ||
| 35 | #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ | ||
| 36 | |||
| 37 | #endif /* AT91_DBGU */ | ||
| 38 | |||
| 39 | /* | ||
| 40 | * Some AT91 parts that don't have full DEBUG units still support the ID | ||
| 41 | * and extensions register. | ||
| 42 | */ | ||
| 43 | #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ | ||
| 44 | #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ | ||
| 45 | #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ | ||
| 46 | #define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ | ||
| 47 | #define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ | ||
| 48 | #define AT91_CIDR_SRAMSIZ_1K (1 << 16) | ||
| 49 | #define AT91_CIDR_SRAMSIZ_2K (2 << 16) | ||
| 50 | #define AT91_CIDR_SRAMSIZ_112K (4 << 16) | ||
| 51 | #define AT91_CIDR_SRAMSIZ_4K (5 << 16) | ||
| 52 | #define AT91_CIDR_SRAMSIZ_80K (6 << 16) | ||
| 53 | #define AT91_CIDR_SRAMSIZ_160K (7 << 16) | ||
| 54 | #define AT91_CIDR_SRAMSIZ_8K (8 << 16) | ||
| 55 | #define AT91_CIDR_SRAMSIZ_16K (9 << 16) | ||
| 56 | #define AT91_CIDR_SRAMSIZ_32K (10 << 16) | ||
| 57 | #define AT91_CIDR_SRAMSIZ_64K (11 << 16) | ||
| 58 | #define AT91_CIDR_SRAMSIZ_128K (12 << 16) | ||
| 59 | #define AT91_CIDR_SRAMSIZ_256K (13 << 16) | ||
| 60 | #define AT91_CIDR_SRAMSIZ_96K (14 << 16) | ||
| 61 | #define AT91_CIDR_SRAMSIZ_512K (15 << 16) | ||
| 62 | #define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ | ||
| 63 | #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ | ||
| 64 | #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ | ||
| 65 | |||
| 66 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h deleted file mode 100644 index 400ec10014b4..000000000000 --- a/include/asm-arm/arch-at91/at91_mci.h +++ /dev/null | |||
| @@ -1,113 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_mci.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * MultiMedia Card Interface (MCI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision F. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_MCI_H | ||
| 17 | #define AT91_MCI_H | ||
| 18 | |||
| 19 | #define AT91_MCI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ | ||
| 21 | #define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ | ||
| 22 | #define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ | ||
| 23 | #define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ | ||
| 24 | #define AT91_MCI_SWRST (1 << 7) /* Software Reset */ | ||
| 25 | |||
| 26 | #define AT91_MCI_MR 0x04 /* Mode Register */ | ||
| 27 | #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ | ||
| 28 | #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ | ||
| 29 | #define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ | ||
| 30 | #define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ | ||
| 31 | #define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ | ||
| 32 | #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ | ||
| 33 | #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ | ||
| 34 | #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ | ||
| 35 | |||
| 36 | #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ | ||
| 37 | #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ | ||
| 38 | #define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ | ||
| 39 | #define AT91_MCI_DTOMUL_1 (0 << 4) | ||
| 40 | #define AT91_MCI_DTOMUL_16 (1 << 4) | ||
| 41 | #define AT91_MCI_DTOMUL_128 (2 << 4) | ||
| 42 | #define AT91_MCI_DTOMUL_256 (3 << 4) | ||
| 43 | #define AT91_MCI_DTOMUL_1K (4 << 4) | ||
| 44 | #define AT91_MCI_DTOMUL_4K (5 << 4) | ||
| 45 | #define AT91_MCI_DTOMUL_64K (6 << 4) | ||
| 46 | #define AT91_MCI_DTOMUL_1M (7 << 4) | ||
| 47 | |||
| 48 | #define AT91_MCI_SDCR 0x0c /* SD Card Register */ | ||
| 49 | #define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ | ||
| 50 | #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ | ||
| 51 | |||
| 52 | #define AT91_MCI_ARGR 0x10 /* Argument Register */ | ||
| 53 | |||
| 54 | #define AT91_MCI_CMDR 0x14 /* Command Register */ | ||
| 55 | #define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ | ||
| 56 | #define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ | ||
| 57 | #define AT91_MCI_RSPTYP_NONE (0 << 6) | ||
| 58 | #define AT91_MCI_RSPTYP_48 (1 << 6) | ||
| 59 | #define AT91_MCI_RSPTYP_136 (2 << 6) | ||
| 60 | #define AT91_MCI_SPCMD (7 << 8) /* Special Command */ | ||
| 61 | #define AT91_MCI_SPCMD_NONE (0 << 8) | ||
| 62 | #define AT91_MCI_SPCMD_INIT (1 << 8) | ||
| 63 | #define AT91_MCI_SPCMD_SYNC (2 << 8) | ||
| 64 | #define AT91_MCI_SPCMD_ICMD (4 << 8) | ||
| 65 | #define AT91_MCI_SPCMD_IRESP (5 << 8) | ||
| 66 | #define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ | ||
| 67 | #define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ | ||
| 68 | #define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ | ||
| 69 | #define AT91_MCI_TRCMD_NONE (0 << 16) | ||
| 70 | #define AT91_MCI_TRCMD_START (1 << 16) | ||
| 71 | #define AT91_MCI_TRCMD_STOP (2 << 16) | ||
| 72 | #define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ | ||
| 73 | #define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ | ||
| 74 | #define AT91_MCI_TRTYP_BLOCK (0 << 19) | ||
| 75 | #define AT91_MCI_TRTYP_MULTIPLE (1 << 19) | ||
| 76 | #define AT91_MCI_TRTYP_STREAM (2 << 19) | ||
| 77 | |||
| 78 | #define AT91_MCI_BLKR 0x18 /* Block Register */ | ||
| 79 | #define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ | ||
| 80 | #define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ | ||
| 81 | |||
| 82 | #define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ | ||
| 83 | #define AT91_MCR_RDR 0x30 /* Receive Data Register */ | ||
| 84 | #define AT91_MCR_TDR 0x34 /* Transmit Data Register */ | ||
| 85 | |||
| 86 | #define AT91_MCI_SR 0x40 /* Status Register */ | ||
| 87 | #define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ | ||
| 88 | #define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ | ||
| 89 | #define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ | ||
| 90 | #define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ | ||
| 91 | #define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ | ||
| 92 | #define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ | ||
| 93 | #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ | ||
| 94 | #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ | ||
| 95 | #define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ | ||
| 96 | #define AT91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B */ | ||
| 97 | #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ | ||
| 98 | #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ | ||
| 99 | #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ | ||
| 100 | #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ | ||
| 101 | #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ | ||
| 102 | #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ | ||
| 103 | #define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ | ||
| 104 | #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ | ||
| 105 | #define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */ | ||
| 106 | #define AT91_MCI_OVRE (1 << 30) /* Overrun */ | ||
| 107 | #define AT91_MCI_UNRE (1 << 31) /* Underrun */ | ||
| 108 | |||
| 109 | #define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ | ||
| 110 | #define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ | ||
| 111 | #define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ | ||
| 112 | |||
| 113 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_pio.h b/include/asm-arm/arch-at91/at91_pio.h deleted file mode 100644 index 84c3866d309f..000000000000 --- a/include/asm-arm/arch-at91/at91_pio.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_pio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Parallel I/O Controller (PIO) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_PIO_H | ||
| 17 | #define AT91_PIO_H | ||
| 18 | |||
| 19 | #define PIO_PER 0x00 /* Enable Register */ | ||
| 20 | #define PIO_PDR 0x04 /* Disable Register */ | ||
| 21 | #define PIO_PSR 0x08 /* Status Register */ | ||
| 22 | #define PIO_OER 0x10 /* Output Enable Register */ | ||
| 23 | #define PIO_ODR 0x14 /* Output Disable Register */ | ||
| 24 | #define PIO_OSR 0x18 /* Output Status Register */ | ||
| 25 | #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ | ||
| 26 | #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ | ||
| 27 | #define PIO_IFSR 0x28 /* Glitch Input Filter Status */ | ||
| 28 | #define PIO_SODR 0x30 /* Set Output Data Register */ | ||
| 29 | #define PIO_CODR 0x34 /* Clear Output Data Register */ | ||
| 30 | #define PIO_ODSR 0x38 /* Output Data Status Register */ | ||
| 31 | #define PIO_PDSR 0x3c /* Pin Data Status Register */ | ||
| 32 | #define PIO_IER 0x40 /* Interrupt Enable Register */ | ||
| 33 | #define PIO_IDR 0x44 /* Interrupt Disable Register */ | ||
| 34 | #define PIO_IMR 0x48 /* Interrupt Mask Register */ | ||
| 35 | #define PIO_ISR 0x4c /* Interrupt Status Register */ | ||
| 36 | #define PIO_MDER 0x50 /* Multi-driver Enable Register */ | ||
| 37 | #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ | ||
| 38 | #define PIO_MDSR 0x58 /* Multi-driver Status Register */ | ||
| 39 | #define PIO_PUDR 0x60 /* Pull-up Disable Register */ | ||
| 40 | #define PIO_PUER 0x64 /* Pull-up Enable Register */ | ||
| 41 | #define PIO_PUSR 0x68 /* Pull-up Status Register */ | ||
| 42 | #define PIO_ASR 0x70 /* Peripheral A Select Register */ | ||
| 43 | #define PIO_BSR 0x74 /* Peripheral B Select Register */ | ||
| 44 | #define PIO_ABSR 0x78 /* AB Status Register */ | ||
| 45 | #define PIO_OWER 0xa0 /* Output Write Enable Register */ | ||
| 46 | #define PIO_OWDR 0xa4 /* Output Write Disable Register */ | ||
| 47 | #define PIO_OWSR 0xa8 /* Output Write Status Register */ | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_pit.h b/include/asm-arm/arch-at91/at91_pit.h deleted file mode 100644 index 5026325a5ae4..000000000000 --- a/include/asm-arm/arch-at91/at91_pit.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_pit.h | ||
| 3 | * | ||
| 4 | * Periodic Interval Timer (PIT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_PIT_H | ||
| 14 | #define AT91_PIT_H | ||
| 15 | |||
| 16 | #define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ | ||
| 17 | #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ | ||
| 18 | #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ | ||
| 19 | #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ | ||
| 20 | |||
| 21 | #define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ | ||
| 22 | #define AT91_PIT_PITS (1 << 0) /* Timer Status */ | ||
| 23 | |||
| 24 | #define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ | ||
| 25 | #define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ | ||
| 26 | #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ | ||
| 27 | #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h deleted file mode 100644 index 2001e81f2267..000000000000 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ /dev/null | |||
| @@ -1,111 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_pmc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Power Management Controller (PMC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_PMC_H | ||
| 17 | #define AT91_PMC_H | ||
| 18 | |||
| 19 | #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ | ||
| 20 | #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ | ||
| 21 | |||
| 22 | #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ | ||
| 23 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ | ||
| 24 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ | ||
| 25 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ | ||
| 26 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ | ||
| 27 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ | ||
| 28 | #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ | ||
| 29 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ | ||
| 30 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ | ||
| 31 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | ||
| 32 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ | ||
| 33 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ | ||
| 34 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ | ||
| 35 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ | ||
| 36 | |||
| 37 | #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ | ||
| 38 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | ||
| 39 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | ||
| 40 | |||
| 41 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ | ||
| 42 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ | ||
| 43 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ | ||
| 44 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ | ||
| 45 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ | ||
| 46 | |||
| 47 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ | ||
| 48 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | ||
| 49 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ | ||
| 50 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | ||
| 51 | |||
| 52 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | ||
| 53 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ | ||
| 54 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ | ||
| 55 | |||
| 56 | #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ | ||
| 57 | #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ | ||
| 58 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ | ||
| 59 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | ||
| 60 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | ||
| 61 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | ||
| 62 | #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ | ||
| 63 | #define AT91_PMC_USBDIV_1 (0 << 28) | ||
| 64 | #define AT91_PMC_USBDIV_2 (1 << 28) | ||
| 65 | #define AT91_PMC_USBDIV_4 (2 << 28) | ||
| 66 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ | ||
| 67 | |||
| 68 | #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ | ||
| 69 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ | ||
| 70 | #define AT91_PMC_CSS_SLOW (0 << 0) | ||
| 71 | #define AT91_PMC_CSS_MAIN (1 << 0) | ||
| 72 | #define AT91_PMC_CSS_PLLA (2 << 0) | ||
| 73 | #define AT91_PMC_CSS_PLLB (3 << 0) | ||
| 74 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ | ||
| 75 | #define AT91_PMC_PRES_1 (0 << 2) | ||
| 76 | #define AT91_PMC_PRES_2 (1 << 2) | ||
| 77 | #define AT91_PMC_PRES_4 (2 << 2) | ||
| 78 | #define AT91_PMC_PRES_8 (3 << 2) | ||
| 79 | #define AT91_PMC_PRES_16 (4 << 2) | ||
| 80 | #define AT91_PMC_PRES_32 (5 << 2) | ||
| 81 | #define AT91_PMC_PRES_64 (6 << 2) | ||
| 82 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ | ||
| 83 | #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ | ||
| 84 | #define AT91RM9200_PMC_MDIV_2 (1 << 8) | ||
| 85 | #define AT91RM9200_PMC_MDIV_3 (2 << 8) | ||
| 86 | #define AT91RM9200_PMC_MDIV_4 (3 << 8) | ||
| 87 | #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ | ||
| 88 | #define AT91SAM9_PMC_MDIV_2 (1 << 8) | ||
| 89 | #define AT91SAM9_PMC_MDIV_4 (2 << 8) | ||
| 90 | #define AT91SAM9_PMC_MDIV_6 (3 << 8) | ||
| 91 | #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ | ||
| 92 | #define AT91_PMC_PDIV_1 (0 << 12) | ||
| 93 | #define AT91_PMC_PDIV_2 (1 << 12) | ||
| 94 | |||
| 95 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ | ||
| 96 | |||
| 97 | #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ | ||
| 98 | #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ | ||
| 99 | #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ | ||
| 100 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ | ||
| 101 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | ||
| 102 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | ||
| 103 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | ||
| 104 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ | ||
| 105 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | ||
| 106 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | ||
| 107 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | ||
| 108 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | ||
| 109 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ | ||
| 110 | |||
| 111 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h deleted file mode 100644 index fb8d1618a231..000000000000 --- a/include/asm-arm/arch-at91/at91_rstc.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_rstc.h | ||
| 3 | * | ||
| 4 | * Reset Controller (RSTC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_RSTC_H | ||
| 14 | #define AT91_RSTC_H | ||
| 15 | |||
| 16 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ | ||
| 17 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | ||
| 18 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | ||
| 19 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | ||
| 20 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ | ||
| 21 | |||
| 22 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | ||
| 23 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | ||
| 24 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ | ||
| 25 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) | ||
| 26 | #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) | ||
| 27 | #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) | ||
| 28 | #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) | ||
| 29 | #define AT91_RSTC_RSTTYP_USER (4 << 8) | ||
| 30 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ | ||
| 31 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ | ||
| 32 | |||
| 33 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | ||
| 34 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ | ||
| 35 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ | ||
| 36 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_rtc.h b/include/asm-arm/arch-at91/at91_rtc.h deleted file mode 100644 index af9bd28174c0..000000000000 --- a/include/asm-arm/arch-at91/at91_rtc.h +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_rtc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Real Time Clock (RTC) - System peripheral registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_RTC_H | ||
| 17 | #define AT91_RTC_H | ||
| 18 | |||
| 19 | #define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ | ||
| 20 | #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ | ||
| 21 | #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ | ||
| 22 | #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ | ||
| 23 | #define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) | ||
| 24 | #define AT91_RTC_TIMEVSEL_HOUR (1 << 8) | ||
| 25 | #define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) | ||
| 26 | #define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) | ||
| 27 | #define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ | ||
| 28 | #define AT91_RTC_CALEVSEL_WEEK (0 << 16) | ||
| 29 | #define AT91_RTC_CALEVSEL_MONTH (1 << 16) | ||
| 30 | #define AT91_RTC_CALEVSEL_YEAR (2 << 16) | ||
| 31 | |||
| 32 | #define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ | ||
| 33 | #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ | ||
| 34 | |||
| 35 | #define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ | ||
| 36 | #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ | ||
| 37 | #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ | ||
| 38 | #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ | ||
| 39 | #define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ | ||
| 40 | |||
| 41 | #define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ | ||
| 42 | #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ | ||
| 43 | #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ | ||
| 44 | #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ | ||
| 45 | #define AT91_RTC_DAY (7 << 21) /* Current Day */ | ||
| 46 | #define AT91_RTC_DATE (0x3f << 24) /* Current Date */ | ||
| 47 | |||
| 48 | #define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ | ||
| 49 | #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ | ||
| 50 | #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ | ||
| 51 | #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ | ||
| 52 | |||
| 53 | #define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ | ||
| 54 | #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ | ||
| 55 | #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ | ||
| 56 | |||
| 57 | #define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ | ||
| 58 | #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ | ||
| 59 | #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ | ||
| 60 | #define AT91_RTC_SECEV (1 << 2) /* Second Event */ | ||
| 61 | #define AT91_RTC_TIMEV (1 << 3) /* Time Event */ | ||
| 62 | #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ | ||
| 63 | |||
| 64 | #define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ | ||
| 65 | #define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ | ||
| 66 | #define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ | ||
| 67 | #define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ | ||
| 68 | |||
| 69 | #define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ | ||
| 70 | #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ | ||
| 71 | #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ | ||
| 72 | #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ | ||
| 73 | #define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ | ||
| 74 | |||
| 75 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_rtt.h b/include/asm-arm/arch-at91/at91_rtt.h deleted file mode 100644 index 39a32633b275..000000000000 --- a/include/asm-arm/arch-at91/at91_rtt.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_rtt.h | ||
| 3 | * | ||
| 4 | * Real-time Timer (RTT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_RTT_H | ||
| 14 | #define AT91_RTT_H | ||
| 15 | |||
| 16 | #define AT91_RTT_MR 0x00 /* Real-time Mode Register */ | ||
| 17 | #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ | ||
| 18 | #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ | ||
| 19 | #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ | ||
| 20 | #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ | ||
| 21 | |||
| 22 | #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */ | ||
| 23 | #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ | ||
| 24 | |||
| 25 | #define AT91_RTT_VR 0x08 /* Real-time Value Register */ | ||
| 26 | #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ | ||
| 27 | |||
| 28 | #define AT91_RTT_SR 0x0c /* Real-time Status Register */ | ||
| 29 | #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ | ||
| 30 | #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ | ||
| 31 | |||
| 32 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_shdwc.h b/include/asm-arm/arch-at91/at91_shdwc.h deleted file mode 100644 index 581fa41d90e8..000000000000 --- a/include/asm-arm/arch-at91/at91_shdwc.h +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_shdwc.h | ||
| 3 | * | ||
| 4 | * Shutdown Controller (SHDWC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_SHDWC_H | ||
| 14 | #define AT91_SHDWC_H | ||
| 15 | |||
| 16 | #define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ | ||
| 17 | #define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ | ||
| 18 | #define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ | ||
| 19 | |||
| 20 | #define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ | ||
| 21 | #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ | ||
| 22 | #define AT91_SHDW_WKMODE0_NONE 0 | ||
| 23 | #define AT91_SHDW_WKMODE0_HIGH 1 | ||
| 24 | #define AT91_SHDW_WKMODE0_LOW 2 | ||
| 25 | #define AT91_SHDW_WKMODE0_ANYLEVEL 3 | ||
| 26 | #define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ | ||
| 27 | #define AT91_SHDW_CPTWK0_(x) ((x) << 4) | ||
| 28 | #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ | ||
| 29 | |||
| 30 | #define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ | ||
| 31 | #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ | ||
| 32 | #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ | ||
| 33 | #define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */ | ||
| 34 | |||
| 35 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_spi.h b/include/asm-arm/arch-at91/at91_spi.h deleted file mode 100644 index f9b9a8464997..000000000000 --- a/include/asm-arm/arch-at91/at91_spi.h +++ /dev/null | |||
| @@ -1,81 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_spi.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Serial Peripheral Interface (SPI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_SPI_H | ||
| 17 | #define AT91_SPI_H | ||
| 18 | |||
| 19 | #define AT91_SPI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ | ||
| 21 | #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ | ||
| 22 | #define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ | ||
| 23 | #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ | ||
| 24 | |||
| 25 | #define AT91_SPI_MR 0x04 /* Mode Register */ | ||
| 26 | #define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ | ||
| 27 | #define AT91_SPI_PS (1 << 1) /* Peripheral Select */ | ||
| 28 | #define AT91_SPI_PS_FIXED (0 << 1) | ||
| 29 | #define AT91_SPI_PS_VARIABLE (1 << 1) | ||
| 30 | #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ | ||
| 31 | #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ | ||
| 32 | #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ | ||
| 33 | #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ | ||
| 34 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 35 | #define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ | ||
| 36 | |||
| 37 | #define AT91_SPI_RDR 0x08 /* Receive Data Register */ | ||
| 38 | #define AT91_SPI_RD (0xffff << 0) /* Receive Data */ | ||
| 39 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 40 | |||
| 41 | #define AT91_SPI_TDR 0x0c /* Transmit Data Register */ | ||
| 42 | #define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ | ||
| 43 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 44 | #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ | ||
| 45 | |||
| 46 | #define AT91_SPI_SR 0x10 /* Status Register */ | ||
| 47 | #define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ | ||
| 48 | #define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ | ||
| 49 | #define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ | ||
| 50 | #define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ | ||
| 51 | #define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ | ||
| 52 | #define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ | ||
| 53 | #define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ | ||
| 54 | #define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ | ||
| 55 | #define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ | ||
| 56 | #define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ | ||
| 57 | #define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ | ||
| 58 | |||
| 59 | #define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ | ||
| 60 | #define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ | ||
| 61 | #define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ | ||
| 62 | |||
| 63 | #define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ | ||
| 64 | #define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ | ||
| 65 | #define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ | ||
| 66 | #define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ | ||
| 67 | #define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ | ||
| 68 | #define AT91_SPI_BITS_8 (0 << 4) | ||
| 69 | #define AT91_SPI_BITS_9 (1 << 4) | ||
| 70 | #define AT91_SPI_BITS_10 (2 << 4) | ||
| 71 | #define AT91_SPI_BITS_11 (3 << 4) | ||
| 72 | #define AT91_SPI_BITS_12 (4 << 4) | ||
| 73 | #define AT91_SPI_BITS_13 (5 << 4) | ||
| 74 | #define AT91_SPI_BITS_14 (6 << 4) | ||
| 75 | #define AT91_SPI_BITS_15 (7 << 4) | ||
| 76 | #define AT91_SPI_BITS_16 (8 << 4) | ||
| 77 | #define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ | ||
| 78 | #define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ | ||
| 79 | #define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ | ||
| 80 | |||
| 81 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_ssc.h b/include/asm-arm/arch-at91/at91_ssc.h deleted file mode 100644 index 0ecc73460b50..000000000000 --- a/include/asm-arm/arch-at91/at91_ssc.h +++ /dev/null | |||
| @@ -1,106 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_ssc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Serial Synchronous Controller (SSC) registers. | ||
| 7 | * Based on AT91RM9200 datasheet revision E. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91_SSC_H | ||
| 16 | #define AT91_SSC_H | ||
| 17 | |||
| 18 | #define AT91_SSC_CR 0x00 /* Control Register */ | ||
| 19 | #define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ | ||
| 20 | #define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */ | ||
| 21 | #define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */ | ||
| 22 | #define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */ | ||
| 23 | #define AT91_SSC_SWRST (1 << 15) /* Software Reset */ | ||
| 24 | |||
| 25 | #define AT91_SSC_CMR 0x04 /* Clock Mode Register */ | ||
| 26 | #define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */ | ||
| 27 | |||
| 28 | #define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */ | ||
| 29 | #define AT91_SSC_CKS (3 << 0) /* Clock Selection */ | ||
| 30 | #define AT91_SSC_CKS_DIV (0 << 0) | ||
| 31 | #define AT91_SSC_CKS_CLOCK (1 << 0) | ||
| 32 | #define AT91_SSC_CKS_PIN (2 << 0) | ||
| 33 | #define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */ | ||
| 34 | #define AT91_SSC_CKO_NONE (0 << 2) | ||
| 35 | #define AT91_SSC_CKO_CONTINUOUS (1 << 2) | ||
| 36 | #define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ | ||
| 37 | #define AT91_SSC_CKI_FALLING (0 << 5) | ||
| 38 | #define AT91_SSC_CK_RISING (1 << 5) | ||
| 39 | #define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ | ||
| 40 | #define AT91_SSC_CKG_NONE (0 << 6) | ||
| 41 | #define AT91_SSC_CKG_RFLOW (1 << 6) | ||
| 42 | #define AT91_SSC_CKG_RFHIGH (2 << 6) | ||
| 43 | #define AT91_SSC_START (0xf << 8) /* Start Selection */ | ||
| 44 | #define AT91_SSC_START_CONTINUOUS (0 << 8) | ||
| 45 | #define AT91_SSC_START_TX_RX (1 << 8) | ||
| 46 | #define AT91_SSC_START_LOW_RF (2 << 8) | ||
| 47 | #define AT91_SSC_START_HIGH_RF (3 << 8) | ||
| 48 | #define AT91_SSC_START_FALLING_RF (4 << 8) | ||
| 49 | #define AT91_SSC_START_RISING_RF (5 << 8) | ||
| 50 | #define AT91_SSC_START_LEVEL_RF (6 << 8) | ||
| 51 | #define AT91_SSC_START_EDGE_RF (7 << 8) | ||
| 52 | #define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ | ||
| 53 | #define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ | ||
| 54 | #define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ | ||
| 55 | |||
| 56 | #define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */ | ||
| 57 | #define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */ | ||
| 58 | #define AT91_SSC_LOOP (1 << 5) /* Loop Mode */ | ||
| 59 | #define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */ | ||
| 60 | #define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */ | ||
| 61 | #define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */ | ||
| 62 | #define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */ | ||
| 63 | #define AT91_SSC_FSOS_NONE (0 << 20) | ||
| 64 | #define AT91_SSC_FSOS_NEGATIVE (1 << 20) | ||
| 65 | #define AT91_SSC_FSOS_POSITIVE (2 << 20) | ||
| 66 | #define AT91_SSC_FSOS_LOW (3 << 20) | ||
| 67 | #define AT91_SSC_FSOS_HIGH (4 << 20) | ||
| 68 | #define AT91_SSC_FSOS_TOGGLE (5 << 20) | ||
| 69 | #define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */ | ||
| 70 | #define AT91_SSC_FSEDGE_POSITIVE (0 << 24) | ||
| 71 | #define AT91_SSC_FSEDGE_NEGATIVE (1 << 24) | ||
| 72 | |||
| 73 | #define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */ | ||
| 74 | #define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */ | ||
| 75 | #define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */ | ||
| 76 | #define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */ | ||
| 77 | |||
| 78 | #define AT91_SSC_RHR 0x20 /* Receive Holding Register */ | ||
| 79 | #define AT91_SSC_THR 0x24 /* Transmit Holding Register */ | ||
| 80 | #define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ | ||
| 81 | #define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ | ||
| 82 | |||
| 83 | #define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ | ||
| 84 | #define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ | ||
| 85 | |||
| 86 | #define AT91_SSC_SR 0x40 /* Status Register */ | ||
| 87 | #define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ | ||
| 88 | #define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ | ||
| 89 | #define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */ | ||
| 90 | #define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */ | ||
| 91 | #define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */ | ||
| 92 | #define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ | ||
| 93 | #define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ | ||
| 94 | #define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ | ||
| 95 | #define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ | ||
| 96 | #define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ | ||
| 97 | #define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ | ||
| 98 | #define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ | ||
| 99 | #define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ | ||
| 100 | #define AT91_SSC_RXENA (1 << 17) /* Receive Enable */ | ||
| 101 | |||
| 102 | #define AT91_SSC_IER 0x44 /* Interrupt Enable Register */ | ||
| 103 | #define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */ | ||
| 104 | #define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */ | ||
| 105 | |||
| 106 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_st.h b/include/asm-arm/arch-at91/at91_st.h deleted file mode 100644 index 30446e2ea772..000000000000 --- a/include/asm-arm/arch-at91/at91_st.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_st.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * System Timer (ST) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_ST_H | ||
| 17 | #define AT91_ST_H | ||
| 18 | |||
| 19 | #define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ | ||
| 20 | #define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ | ||
| 21 | |||
| 22 | #define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ | ||
| 23 | #define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ | ||
| 24 | |||
| 25 | #define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ | ||
| 26 | #define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ | ||
| 27 | #define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ | ||
| 28 | #define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ | ||
| 29 | |||
| 30 | #define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ | ||
| 31 | #define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ | ||
| 32 | |||
| 33 | #define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ | ||
| 34 | #define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ | ||
| 35 | #define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ | ||
| 36 | #define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ | ||
| 37 | #define AT91_ST_ALMS (1 << 3) /* Alarm Status */ | ||
| 38 | |||
| 39 | #define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ | ||
| 40 | #define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ | ||
| 41 | #define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ | ||
| 42 | |||
| 43 | #define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ | ||
| 44 | #define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ | ||
| 45 | |||
| 46 | #define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ | ||
| 47 | #define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_tc.h b/include/asm-arm/arch-at91/at91_tc.h deleted file mode 100644 index b85d3faeef5c..000000000000 --- a/include/asm-arm/arch-at91/at91_tc.h +++ /dev/null | |||
| @@ -1,146 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_tc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Timer/Counter Unit (TC) registers. | ||
| 7 | * Based on AT91RM9200 datasheet revision E. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91_TC_H | ||
| 16 | #define AT91_TC_H | ||
| 17 | |||
| 18 | #define AT91_TC_BCR 0xc0 /* TC Block Control Register */ | ||
| 19 | #define AT91_TC_SYNC (1 << 0) /* Synchro Command */ | ||
| 20 | |||
| 21 | #define AT91_TC_BMR 0xc4 /* TC Block Mode Register */ | ||
| 22 | #define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */ | ||
| 23 | #define AT91_TC_TC0XC0S_TCLK0 (0 << 0) | ||
| 24 | #define AT91_TC_TC0XC0S_NONE (1 << 0) | ||
| 25 | #define AT91_TC_TC0XC0S_TIOA1 (2 << 0) | ||
| 26 | #define AT91_TC_TC0XC0S_TIOA2 (3 << 0) | ||
| 27 | #define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */ | ||
| 28 | #define AT91_TC_TC1XC1S_TCLK1 (0 << 2) | ||
| 29 | #define AT91_TC_TC1XC1S_NONE (1 << 2) | ||
| 30 | #define AT91_TC_TC1XC1S_TIOA0 (2 << 2) | ||
| 31 | #define AT91_TC_TC1XC1S_TIOA2 (3 << 2) | ||
| 32 | #define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */ | ||
| 33 | #define AT91_TC_TC2XC2S_TCLK2 (0 << 4) | ||
| 34 | #define AT91_TC_TC2XC2S_NONE (1 << 4) | ||
| 35 | #define AT91_TC_TC2XC2S_TIOA0 (2 << 4) | ||
| 36 | #define AT91_TC_TC2XC2S_TIOA1 (3 << 4) | ||
| 37 | |||
| 38 | |||
| 39 | #define AT91_TC_CCR 0x00 /* Channel Control Register */ | ||
| 40 | #define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */ | ||
| 41 | #define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */ | ||
| 42 | #define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */ | ||
| 43 | |||
| 44 | #define AT91_TC_CMR 0x04 /* Channel Mode Register */ | ||
| 45 | #define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */ | ||
| 46 | #define AT91_TC_TIMER_CLOCK1 (0 << 0) | ||
| 47 | #define AT91_TC_TIMER_CLOCK2 (1 << 0) | ||
| 48 | #define AT91_TC_TIMER_CLOCK3 (2 << 0) | ||
| 49 | #define AT91_TC_TIMER_CLOCK4 (3 << 0) | ||
| 50 | #define AT91_TC_TIMER_CLOCK5 (4 << 0) | ||
| 51 | #define AT91_TC_XC0 (5 << 0) | ||
| 52 | #define AT91_TC_XC1 (6 << 0) | ||
| 53 | #define AT91_TC_XC2 (7 << 0) | ||
| 54 | #define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */ | ||
| 55 | #define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */ | ||
| 56 | #define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */ | ||
| 57 | #define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */ | ||
| 58 | #define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */ | ||
| 59 | #define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */ | ||
| 60 | #define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */ | ||
| 61 | #define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */ | ||
| 62 | #define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */ | ||
| 63 | #define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */ | ||
| 64 | |||
| 65 | #define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */ | ||
| 66 | #define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */ | ||
| 67 | #define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */ | ||
| 68 | #define AT91_TC_EEVTEDG_NONE (0 << 8) | ||
| 69 | #define AT91_TC_EEVTEDG_RISING (1 << 8) | ||
| 70 | #define AT91_TC_EEVTEDG_FALLING (2 << 8) | ||
| 71 | #define AT91_TC_EEVTEDG_BOTH (3 << 8) | ||
| 72 | #define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */ | ||
| 73 | #define AT91_TC_EEVT_TIOB (0 << 10) | ||
| 74 | #define AT91_TC_EEVT_XC0 (1 << 10) | ||
| 75 | #define AT91_TC_EEVT_XC1 (2 << 10) | ||
| 76 | #define AT91_TC_EEVT_XC2 (3 << 10) | ||
| 77 | #define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */ | ||
| 78 | #define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */ | ||
| 79 | #define AT91_TC_WAVESEL_UP (0 << 13) | ||
| 80 | #define AT91_TC_WAVESEL_UP_AUTO (2 << 13) | ||
| 81 | #define AT91_TC_WAVESEL_UPDOWN (1 << 13) | ||
| 82 | #define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13) | ||
| 83 | #define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */ | ||
| 84 | #define AT91_TC_ACPA_NONE (0 << 16) | ||
| 85 | #define AT91_TC_ACPA_SET (1 << 16) | ||
| 86 | #define AT91_TC_ACPA_CLEAR (2 << 16) | ||
| 87 | #define AT91_TC_ACPA_TOGGLE (3 << 16) | ||
| 88 | #define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */ | ||
| 89 | #define AT91_TC_ACPC_NONE (0 << 18) | ||
| 90 | #define AT91_TC_ACPC_SET (1 << 18) | ||
| 91 | #define AT91_TC_ACPC_CLEAR (2 << 18) | ||
| 92 | #define AT91_TC_ACPC_TOGGLE (3 << 18) | ||
| 93 | #define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */ | ||
| 94 | #define AT91_TC_AEEVT_NONE (0 << 20) | ||
| 95 | #define AT91_TC_AEEVT_SET (1 << 20) | ||
| 96 | #define AT91_TC_AEEVT_CLEAR (2 << 20) | ||
| 97 | #define AT91_TC_AEEVT_TOGGLE (3 << 20) | ||
| 98 | #define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */ | ||
| 99 | #define AT91_TC_ASWTRG_NONE (0 << 22) | ||
| 100 | #define AT91_TC_ASWTRG_SET (1 << 22) | ||
| 101 | #define AT91_TC_ASWTRG_CLEAR (2 << 22) | ||
| 102 | #define AT91_TC_ASWTRG_TOGGLE (3 << 22) | ||
| 103 | #define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */ | ||
| 104 | #define AT91_TC_BCPB_NONE (0 << 24) | ||
| 105 | #define AT91_TC_BCPB_SET (1 << 24) | ||
| 106 | #define AT91_TC_BCPB_CLEAR (2 << 24) | ||
| 107 | #define AT91_TC_BCPB_TOGGLE (3 << 24) | ||
| 108 | #define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */ | ||
| 109 | #define AT91_TC_BCPC_NONE (0 << 26) | ||
| 110 | #define AT91_TC_BCPC_SET (1 << 26) | ||
| 111 | #define AT91_TC_BCPC_CLEAR (2 << 26) | ||
| 112 | #define AT91_TC_BCPC_TOGGLE (3 << 26) | ||
| 113 | #define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */ | ||
| 114 | #define AT91_TC_BEEVT_NONE (0 << 28) | ||
| 115 | #define AT91_TC_BEEVT_SET (1 << 28) | ||
| 116 | #define AT91_TC_BEEVT_CLEAR (2 << 28) | ||
| 117 | #define AT91_TC_BEEVT_TOGGLE (3 << 28) | ||
| 118 | #define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */ | ||
| 119 | #define AT91_TC_BSWTRG_NONE (0 << 30) | ||
| 120 | #define AT91_TC_BSWTRG_SET (1 << 30) | ||
| 121 | #define AT91_TC_BSWTRG_CLEAR (2 << 30) | ||
| 122 | #define AT91_TC_BSWTRG_TOGGLE (3 << 30) | ||
| 123 | |||
| 124 | #define AT91_TC_CV 0x10 /* Counter Value */ | ||
| 125 | #define AT91_TC_RA 0x14 /* Register A */ | ||
| 126 | #define AT91_TC_RB 0x18 /* Register B */ | ||
| 127 | #define AT91_TC_RC 0x1c /* Register C */ | ||
| 128 | |||
| 129 | #define AT91_TC_SR 0x20 /* Status Register */ | ||
| 130 | #define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */ | ||
| 131 | #define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */ | ||
| 132 | #define AT91_TC_CPAS (1 << 2) /* RA Compare Status */ | ||
| 133 | #define AT91_TC_CPBS (1 << 3) /* RB Compare Status */ | ||
| 134 | #define AT91_TC_CPCS (1 << 4) /* RC Compare Status */ | ||
| 135 | #define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */ | ||
| 136 | #define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */ | ||
| 137 | #define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */ | ||
| 138 | #define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */ | ||
| 139 | #define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */ | ||
| 140 | #define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */ | ||
| 141 | |||
| 142 | #define AT91_TC_IER 0x24 /* Interrupt Enable Register */ | ||
| 143 | #define AT91_TC_IDR 0x28 /* Interrupt Disable Register */ | ||
| 144 | #define AT91_TC_IMR 0x2c /* Interrupt Mask Register */ | ||
| 145 | |||
| 146 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h deleted file mode 100644 index f9f2e3cd95c5..000000000000 --- a/include/asm-arm/arch-at91/at91_twi.h +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_twi.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Two-wire Interface (TWI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_TWI_H | ||
| 17 | #define AT91_TWI_H | ||
| 18 | |||
| 19 | #define AT91_TWI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_TWI_START (1 << 0) /* Send a Start Condition */ | ||
| 21 | #define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ | ||
| 22 | #define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ | ||
| 23 | #define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ | ||
| 24 | #define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */ | ||
| 25 | #define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */ | ||
| 26 | #define AT91_TWI_SWRST (1 << 7) /* Software Reset */ | ||
| 27 | |||
| 28 | #define AT91_TWI_MMR 0x04 /* Master Mode Register */ | ||
| 29 | #define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */ | ||
| 30 | #define AT91_TWI_IADRSZ_NO (0 << 8) | ||
| 31 | #define AT91_TWI_IADRSZ_1 (1 << 8) | ||
| 32 | #define AT91_TWI_IADRSZ_2 (2 << 8) | ||
| 33 | #define AT91_TWI_IADRSZ_3 (3 << 8) | ||
| 34 | #define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ | ||
| 35 | #define AT91_TWI_DADR (0x7f << 16) /* Device Address */ | ||
| 36 | |||
| 37 | #define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */ | ||
| 38 | #define AT91_TWI_SADR (0x7f << 16) /* Slave Address */ | ||
| 39 | |||
| 40 | #define AT91_TWI_IADR 0x0c /* Internal Address Register */ | ||
| 41 | |||
| 42 | #define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ | ||
| 43 | #define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */ | ||
| 44 | #define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */ | ||
| 45 | #define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */ | ||
| 46 | |||
| 47 | #define AT91_TWI_SR 0x20 /* Status Register */ | ||
| 48 | #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ | ||
| 49 | #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ | ||
| 50 | #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ | ||
| 51 | #define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */ | ||
| 52 | #define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */ | ||
| 53 | #define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */ | ||
| 54 | #define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ | ||
| 55 | #define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ | ||
| 56 | #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ | ||
| 57 | #define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */ | ||
| 58 | #define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */ | ||
| 59 | #define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */ | ||
| 60 | |||
| 61 | #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ | ||
| 62 | #define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ | ||
| 63 | #define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */ | ||
| 64 | #define AT91_TWI_RHR 0x30 /* Receive Holding Register */ | ||
| 65 | #define AT91_TWI_THR 0x34 /* Transmit Holding Register */ | ||
| 66 | |||
| 67 | #endif | ||
| 68 | |||
diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h deleted file mode 100644 index 1014e9bf181f..000000000000 --- a/include/asm-arm/arch-at91/at91_wdt.h +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_wdt.h | ||
| 3 | * | ||
| 4 | * Watchdog Timer (WDT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_WDT_H | ||
| 14 | #define AT91_WDT_H | ||
| 15 | |||
| 16 | #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ | ||
| 17 | #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ | ||
| 18 | #define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ | ||
| 19 | |||
| 20 | #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ | ||
| 21 | #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ | ||
| 22 | #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ | ||
| 23 | #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ | ||
| 24 | #define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ | ||
| 25 | #define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ | ||
| 26 | #define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ | ||
| 27 | #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ | ||
| 28 | #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ | ||
| 29 | |||
| 30 | #define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ | ||
| 31 | #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ | ||
| 32 | #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ | ||
| 33 | |||
| 34 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h deleted file mode 100644 index 6f14d9053ac7..000000000000 --- a/include/asm-arm/arch-at91/at91cap9.h +++ /dev/null | |||
| @@ -1,126 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91cap9.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> | ||
| 5 | * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> | ||
| 6 | * Copyright (C) 2007 Atmel Corporation. | ||
| 7 | * | ||
| 8 | * Common definitions. | ||
| 9 | * Based on AT91CAP9 datasheet revision B (Preliminary). | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License as published by | ||
| 13 | * the Free Software Foundation; either version 2 of the License, or | ||
| 14 | * (at your option) any later version. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef AT91CAP9_H | ||
| 18 | #define AT91CAP9_H | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Peripheral identifiers/interrupts. | ||
| 22 | */ | ||
| 23 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 24 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 25 | #define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */ | ||
| 26 | #define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */ | ||
| 27 | #define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */ | ||
| 28 | #define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */ | ||
| 29 | #define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */ | ||
| 30 | #define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */ | ||
| 31 | #define AT91CAP9_ID_US0 8 /* USART 0 */ | ||
| 32 | #define AT91CAP9_ID_US1 9 /* USART 1 */ | ||
| 33 | #define AT91CAP9_ID_US2 10 /* USART 2 */ | ||
| 34 | #define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */ | ||
| 35 | #define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */ | ||
| 36 | #define AT91CAP9_ID_CAN 13 /* CAN */ | ||
| 37 | #define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */ | ||
| 38 | #define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */ | ||
| 39 | #define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */ | ||
| 40 | #define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */ | ||
| 41 | #define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */ | ||
| 42 | #define AT91CAP9_ID_AC97C 19 /* AC97 Controller */ | ||
| 43 | #define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */ | ||
| 44 | #define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */ | ||
| 45 | #define AT91CAP9_ID_EMAC 22 /* Ethernet */ | ||
| 46 | #define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */ | ||
| 47 | #define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */ | ||
| 48 | #define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */ | ||
| 49 | #define AT91CAP9_ID_LCDC 26 /* LCD Controller */ | ||
| 50 | #define AT91CAP9_ID_DMA 27 /* DMA Controller */ | ||
| 51 | #define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */ | ||
| 52 | #define AT91CAP9_ID_UHP 29 /* USB Host Port */ | ||
| 53 | #define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 54 | #define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 55 | |||
| 56 | /* | ||
| 57 | * User Peripheral physical base addresses. | ||
| 58 | */ | ||
| 59 | #define AT91CAP9_BASE_UDPHS 0xfff78000 | ||
| 60 | #define AT91CAP9_BASE_TCB0 0xfff7c000 | ||
| 61 | #define AT91CAP9_BASE_TC0 0xfff7c000 | ||
| 62 | #define AT91CAP9_BASE_TC1 0xfff7c040 | ||
| 63 | #define AT91CAP9_BASE_TC2 0xfff7c080 | ||
| 64 | #define AT91CAP9_BASE_MCI0 0xfff80000 | ||
| 65 | #define AT91CAP9_BASE_MCI1 0xfff84000 | ||
| 66 | #define AT91CAP9_BASE_TWI 0xfff88000 | ||
| 67 | #define AT91CAP9_BASE_US0 0xfff8c000 | ||
| 68 | #define AT91CAP9_BASE_US1 0xfff90000 | ||
| 69 | #define AT91CAP9_BASE_US2 0xfff94000 | ||
| 70 | #define AT91CAP9_BASE_SSC0 0xfff98000 | ||
| 71 | #define AT91CAP9_BASE_SSC1 0xfff9c000 | ||
| 72 | #define AT91CAP9_BASE_AC97C 0xfffa0000 | ||
| 73 | #define AT91CAP9_BASE_SPI0 0xfffa4000 | ||
| 74 | #define AT91CAP9_BASE_SPI1 0xfffa8000 | ||
| 75 | #define AT91CAP9_BASE_CAN 0xfffac000 | ||
| 76 | #define AT91CAP9_BASE_PWMC 0xfffb8000 | ||
| 77 | #define AT91CAP9_BASE_EMAC 0xfffbc000 | ||
| 78 | #define AT91CAP9_BASE_ADC 0xfffc0000 | ||
| 79 | #define AT91CAP9_BASE_ISI 0xfffc4000 | ||
| 80 | #define AT91_BASE_SYS 0xffffe200 | ||
| 81 | |||
| 82 | /* | ||
| 83 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 84 | */ | ||
| 85 | #define AT91_ECC (0xffffe200 - AT91_BASE_SYS) | ||
| 86 | #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) | ||
| 87 | #define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) | ||
| 88 | #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) | ||
| 89 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | ||
| 90 | #define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) | ||
| 91 | #define AT91_DMA (0xffffec00 - AT91_BASE_SYS) | ||
| 92 | #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) | ||
| 93 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 94 | #define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) | ||
| 95 | #define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) | ||
| 96 | #define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) | ||
| 97 | #define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) | ||
| 98 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 99 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 100 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 101 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 102 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 103 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 104 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 105 | |||
| 106 | #define AT91_USART0 AT91CAP9_BASE_US0 | ||
| 107 | #define AT91_USART1 AT91CAP9_BASE_US1 | ||
| 108 | #define AT91_USART2 AT91CAP9_BASE_US2 | ||
| 109 | |||
| 110 | |||
| 111 | /* | ||
| 112 | * Internal Memory. | ||
| 113 | */ | ||
| 114 | #define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ | ||
| 115 | #define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */ | ||
| 116 | |||
| 117 | #define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 118 | #define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ | ||
| 119 | |||
| 120 | #define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ | ||
| 121 | #define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */ | ||
| 122 | #define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ | ||
| 123 | |||
| 124 | #define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 | ||
| 125 | |||
| 126 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91cap9_ddrsdr.h b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h deleted file mode 100644 index efdb23af1ee4..000000000000 --- a/include/asm-arm/arch-at91/at91cap9_ddrsdr.h +++ /dev/null | |||
| @@ -1,100 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91cap9_ddrsdr.h | ||
| 3 | * | ||
| 4 | * DDR/SDR Controller (DDRSDRC) - System peripherals registers. | ||
| 5 | * Based on AT91CAP9 datasheet revision B. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91CAP9_DDRSDR_H | ||
| 14 | #define AT91CAP9_DDRSDR_H | ||
| 15 | |||
| 16 | #define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */ | ||
| 17 | #define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ | ||
| 18 | #define AT91_DDRSDRC_MODE_NORMAL 0 | ||
| 19 | #define AT91_DDRSDRC_MODE_NOP 1 | ||
| 20 | #define AT91_DDRSDRC_MODE_PRECHARGE 2 | ||
| 21 | #define AT91_DDRSDRC_MODE_LMR 3 | ||
| 22 | #define AT91_DDRSDRC_MODE_REFRESH 4 | ||
| 23 | #define AT91_DDRSDRC_MODE_EXT_LMR 5 | ||
| 24 | #define AT91_DDRSDRC_MODE_DEEP 6 | ||
| 25 | |||
| 26 | #define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */ | ||
| 27 | #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
| 28 | |||
| 29 | #define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */ | ||
| 30 | #define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ | ||
| 31 | #define AT91_DDRSDRC_NC_SDR8 (0 << 0) | ||
| 32 | #define AT91_DDRSDRC_NC_SDR9 (1 << 0) | ||
| 33 | #define AT91_DDRSDRC_NC_SDR10 (2 << 0) | ||
| 34 | #define AT91_DDRSDRC_NC_SDR11 (3 << 0) | ||
| 35 | #define AT91_DDRSDRC_NC_DDR9 (0 << 0) | ||
| 36 | #define AT91_DDRSDRC_NC_DDR10 (1 << 0) | ||
| 37 | #define AT91_DDRSDRC_NC_DDR11 (2 << 0) | ||
| 38 | #define AT91_DDRSDRC_NC_DDR12 (3 << 0) | ||
| 39 | #define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ | ||
| 40 | #define AT91_DDRSDRC_NR_11 (0 << 2) | ||
| 41 | #define AT91_DDRSDRC_NR_12 (1 << 2) | ||
| 42 | #define AT91_DDRSDRC_NR_13 (2 << 2) | ||
| 43 | #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ | ||
| 44 | #define AT91_DDRSDRC_CAS_2 (2 << 4) | ||
| 45 | #define AT91_DDRSDRC_CAS_3 (3 << 4) | ||
| 46 | #define AT91_DDRSDRC_CAS_25 (6 << 4) | ||
| 47 | #define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ | ||
| 48 | #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ | ||
| 49 | |||
| 50 | #define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */ | ||
| 51 | #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ | ||
| 52 | #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ | ||
| 53 | #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ | ||
| 54 | #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ | ||
| 55 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ | ||
| 56 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ | ||
| 57 | #define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ | ||
| 58 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ | ||
| 59 | |||
| 60 | #define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */ | ||
| 61 | #define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ | ||
| 62 | #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ | ||
| 63 | #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ | ||
| 64 | #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ | ||
| 65 | |||
| 66 | #define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */ | ||
| 67 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ | ||
| 68 | #define AT91_DDRSDRC_LPCB_DISABLE 0 | ||
| 69 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 | ||
| 70 | #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 | ||
| 71 | #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 | ||
| 72 | #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ | ||
| 73 | #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
| 74 | #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
| 75 | #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ | ||
| 76 | #define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
| 77 | #define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
| 78 | #define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
| 79 | #define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
| 80 | |||
| 81 | #define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */ | ||
| 82 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ | ||
| 83 | #define AT91_DDRSDRC_MD_SDR 0 | ||
| 84 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | ||
| 85 | #define AT91_DDRSDRC_MD_DDR 2 | ||
| 86 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | ||
| 87 | |||
| 88 | #define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */ | ||
| 89 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ | ||
| 90 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ | ||
| 91 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ | ||
| 92 | #define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ | ||
| 93 | #define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ | ||
| 94 | #define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ | ||
| 95 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ | ||
| 96 | #define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ | ||
| 97 | #define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ | ||
| 98 | |||
| 99 | |||
| 100 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h deleted file mode 100644 index ddbd4873c842..000000000000 --- a/include/asm-arm/arch-at91/at91cap9_matrix.h +++ /dev/null | |||
| @@ -1,137 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91cap9_matrix.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> | ||
| 5 | * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> | ||
| 6 | * Copyright (C) 2006 Atmel Corporation. | ||
| 7 | * | ||
| 8 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 9 | * Based on AT91CAP9 datasheet revision B (Preliminary). | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License as published by | ||
| 13 | * the Free Software Foundation; either version 2 of the License, or | ||
| 14 | * (at your option) any later version. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef AT91CAP9_MATRIX_H | ||
| 18 | #define AT91CAP9_MATRIX_H | ||
| 19 | |||
| 20 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 21 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 22 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 23 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 24 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 25 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 26 | #define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ | ||
| 27 | #define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ | ||
| 28 | #define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ | ||
| 29 | #define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ | ||
| 30 | #define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ | ||
| 31 | #define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ | ||
| 32 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 33 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 34 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 35 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 36 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 37 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 38 | |||
| 39 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 40 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 41 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 42 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 43 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 44 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | ||
| 45 | #define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ | ||
| 46 | #define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ | ||
| 47 | #define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */ | ||
| 48 | #define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */ | ||
| 49 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 50 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 51 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 52 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 53 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 54 | #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ | ||
| 55 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 56 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 57 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 58 | |||
| 59 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 60 | #define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ | ||
| 61 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 62 | #define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ | ||
| 63 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 64 | #define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ | ||
| 65 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 66 | #define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ | ||
| 67 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 68 | #define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ | ||
| 69 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | ||
| 70 | #define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ | ||
| 71 | #define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ | ||
| 72 | #define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ | ||
| 73 | #define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ | ||
| 74 | #define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ | ||
| 75 | #define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */ | ||
| 76 | #define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */ | ||
| 77 | #define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */ | ||
| 78 | #define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */ | ||
| 79 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 80 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 81 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 82 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 83 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 84 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 85 | #define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ | ||
| 86 | #define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ | ||
| 87 | #define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ | ||
| 88 | #define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ | ||
| 89 | #define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ | ||
| 90 | #define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ | ||
| 91 | |||
| 92 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 93 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 94 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 95 | #define AT91_MATRIX_RCB2 (1 << 2) | ||
| 96 | #define AT91_MATRIX_RCB3 (1 << 3) | ||
| 97 | #define AT91_MATRIX_RCB4 (1 << 4) | ||
| 98 | #define AT91_MATRIX_RCB5 (1 << 5) | ||
| 99 | #define AT91_MATRIX_RCB6 (1 << 6) | ||
| 100 | #define AT91_MATRIX_RCB7 (1 << 7) | ||
| 101 | #define AT91_MATRIX_RCB8 (1 << 8) | ||
| 102 | #define AT91_MATRIX_RCB9 (1 << 9) | ||
| 103 | #define AT91_MATRIX_RCB10 (1 << 10) | ||
| 104 | #define AT91_MATRIX_RCB11 (1 << 11) | ||
| 105 | |||
| 106 | #define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */ | ||
| 107 | #define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */ | ||
| 108 | |||
| 109 | #define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */ | ||
| 110 | #define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */ | ||
| 111 | #define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */ | ||
| 112 | #define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */ | ||
| 113 | |||
| 114 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ | ||
| 115 | #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 116 | #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) | ||
| 117 | #define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1) | ||
| 118 | #define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 119 | #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) | ||
| 120 | #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 121 | #define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 122 | #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) | ||
| 123 | #define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4) | ||
| 124 | #define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 125 | #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) | ||
| 126 | #define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5) | ||
| 127 | #define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 128 | #define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */ | ||
| 129 | #define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 130 | #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) | ||
| 131 | #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) | ||
| 132 | |||
| 133 | #define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */ | ||
| 134 | #define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */ | ||
| 135 | #define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */ | ||
| 136 | |||
| 137 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h deleted file mode 100644 index e8fc0b1c33f4..000000000000 --- a/include/asm-arm/arch-at91/at91rm9200.h +++ /dev/null | |||
| @@ -1,115 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91rm9200.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Common definitions. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_H | ||
| 17 | #define AT91RM9200_H | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Peripheral identifiers/interrupts. | ||
| 21 | */ | ||
| 22 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 23 | #define AT91_ID_SYS 1 /* System Peripheral */ | ||
| 24 | #define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 25 | #define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 26 | #define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 27 | #define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ | ||
| 28 | #define AT91RM9200_ID_US0 6 /* USART 0 */ | ||
| 29 | #define AT91RM9200_ID_US1 7 /* USART 1 */ | ||
| 30 | #define AT91RM9200_ID_US2 8 /* USART 2 */ | ||
| 31 | #define AT91RM9200_ID_US3 9 /* USART 3 */ | ||
| 32 | #define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ | ||
| 33 | #define AT91RM9200_ID_UDP 11 /* USB Device Port */ | ||
| 34 | #define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ | ||
| 35 | #define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ | ||
| 36 | #define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
| 37 | #define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
| 38 | #define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ | ||
| 39 | #define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ | ||
| 40 | #define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ | ||
| 41 | #define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ | ||
| 42 | #define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ | ||
| 43 | #define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ | ||
| 44 | #define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ | ||
| 45 | #define AT91RM9200_ID_UHP 23 /* USB Host port */ | ||
| 46 | #define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ | ||
| 47 | #define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 48 | #define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 49 | #define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 50 | #define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ | ||
| 51 | #define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ | ||
| 52 | #define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ | ||
| 53 | #define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ | ||
| 54 | |||
| 55 | |||
| 56 | /* | ||
| 57 | * Peripheral physical base addresses. | ||
| 58 | */ | ||
| 59 | #define AT91RM9200_BASE_TCB0 0xfffa0000 | ||
| 60 | #define AT91RM9200_BASE_TC0 0xfffa0000 | ||
| 61 | #define AT91RM9200_BASE_TC1 0xfffa0040 | ||
| 62 | #define AT91RM9200_BASE_TC2 0xfffa0080 | ||
| 63 | #define AT91RM9200_BASE_TCB1 0xfffa4000 | ||
| 64 | #define AT91RM9200_BASE_TC3 0xfffa4000 | ||
| 65 | #define AT91RM9200_BASE_TC4 0xfffa4040 | ||
| 66 | #define AT91RM9200_BASE_TC5 0xfffa4080 | ||
| 67 | #define AT91RM9200_BASE_UDP 0xfffb0000 | ||
| 68 | #define AT91RM9200_BASE_MCI 0xfffb4000 | ||
| 69 | #define AT91RM9200_BASE_TWI 0xfffb8000 | ||
| 70 | #define AT91RM9200_BASE_EMAC 0xfffbc000 | ||
| 71 | #define AT91RM9200_BASE_US0 0xfffc0000 | ||
| 72 | #define AT91RM9200_BASE_US1 0xfffc4000 | ||
| 73 | #define AT91RM9200_BASE_US2 0xfffc8000 | ||
| 74 | #define AT91RM9200_BASE_US3 0xfffcc000 | ||
| 75 | #define AT91RM9200_BASE_SSC0 0xfffd0000 | ||
| 76 | #define AT91RM9200_BASE_SSC1 0xfffd4000 | ||
| 77 | #define AT91RM9200_BASE_SSC2 0xfffd8000 | ||
| 78 | #define AT91RM9200_BASE_SPI 0xfffe0000 | ||
| 79 | #define AT91_BASE_SYS 0xfffff000 | ||
| 80 | |||
| 81 | |||
| 82 | /* | ||
| 83 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 84 | */ | ||
| 85 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ | ||
| 86 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */ | ||
| 87 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */ | ||
| 88 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */ | ||
| 89 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */ | ||
| 90 | #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */ | ||
| 91 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ | ||
| 92 | #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ | ||
| 93 | #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ | ||
| 94 | #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ | ||
| 95 | |||
| 96 | #define AT91_USART0 AT91RM9200_BASE_US0 | ||
| 97 | #define AT91_USART1 AT91RM9200_BASE_US1 | ||
| 98 | #define AT91_USART2 AT91RM9200_BASE_US2 | ||
| 99 | #define AT91_USART3 AT91RM9200_BASE_US3 | ||
| 100 | |||
| 101 | #define AT91_MATRIX 0 /* not supported */ | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Internal Memory. | ||
| 105 | */ | ||
| 106 | #define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ | ||
| 107 | #define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ | ||
| 108 | |||
| 109 | #define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ | ||
| 110 | #define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ | ||
| 111 | |||
| 112 | #define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ | ||
| 113 | |||
| 114 | |||
| 115 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91rm9200_emac.h b/include/asm-arm/arch-at91/at91rm9200_emac.h deleted file mode 100644 index 0c417af5fe7f..000000000000 --- a/include/asm-arm/arch-at91/at91rm9200_emac.h +++ /dev/null | |||
| @@ -1,138 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91rm9200_emac.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Ethernet MAC registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_EMAC_H | ||
| 17 | #define AT91RM9200_EMAC_H | ||
| 18 | |||
| 19 | #define AT91_EMAC_CTL 0x00 /* Control Register */ | ||
| 20 | #define AT91_EMAC_LB (1 << 0) /* Loopback */ | ||
| 21 | #define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ | ||
| 22 | #define AT91_EMAC_RE (1 << 2) /* Receive Enable */ | ||
| 23 | #define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ | ||
| 24 | #define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ | ||
| 25 | #define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ | ||
| 26 | #define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ | ||
| 27 | #define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ | ||
| 28 | #define AT91_EMAC_BP (1 << 8) /* Back Pressure */ | ||
| 29 | |||
| 30 | #define AT91_EMAC_CFG 0x04 /* Configuration Register */ | ||
| 31 | #define AT91_EMAC_SPD (1 << 0) /* Speed */ | ||
| 32 | #define AT91_EMAC_FD (1 << 1) /* Full Duplex */ | ||
| 33 | #define AT91_EMAC_BR (1 << 2) /* Bit Rate */ | ||
| 34 | #define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ | ||
| 35 | #define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ | ||
| 36 | #define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ | ||
| 37 | #define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ | ||
| 38 | #define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ | ||
| 39 | #define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ | ||
| 40 | #define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ | ||
| 41 | #define AT91_EMAC_CLK_DIV8 (0 << 10) | ||
| 42 | #define AT91_EMAC_CLK_DIV16 (1 << 10) | ||
| 43 | #define AT91_EMAC_CLK_DIV32 (2 << 10) | ||
| 44 | #define AT91_EMAC_CLK_DIV64 (3 << 10) | ||
| 45 | #define AT91_EMAC_RTY (1 << 12) /* Retry Test */ | ||
| 46 | #define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ | ||
| 47 | |||
| 48 | #define AT91_EMAC_SR 0x08 /* Status Register */ | ||
| 49 | #define AT91_EMAC_SR_LINK (1 << 0) /* Link */ | ||
| 50 | #define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ | ||
| 51 | #define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ | ||
| 52 | |||
| 53 | #define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ | ||
| 54 | |||
| 55 | #define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ | ||
| 56 | #define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ | ||
| 57 | #define AT91_EMAC_NCRC (1 << 15) /* No CRC */ | ||
| 58 | |||
| 59 | #define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ | ||
| 60 | #define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ | ||
| 61 | #define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ | ||
| 62 | #define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ | ||
| 63 | #define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ | ||
| 64 | #define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ | ||
| 65 | #define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ | ||
| 66 | #define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ | ||
| 67 | |||
| 68 | #define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ | ||
| 69 | |||
| 70 | #define AT91_EMAC_RSR 0x20 /* Receive Status Register */ | ||
| 71 | #define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ | ||
| 72 | #define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ | ||
| 73 | #define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ | ||
| 74 | |||
| 75 | #define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ | ||
| 76 | #define AT91_EMAC_DONE (1 << 0) /* Management Done */ | ||
| 77 | #define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ | ||
| 78 | #define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ | ||
| 79 | #define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ | ||
| 80 | #define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ | ||
| 81 | #define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ | ||
| 82 | #define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ | ||
| 83 | #define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ | ||
| 84 | #define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ | ||
| 85 | #define AT91_EMAC_LINK (1 << 9) /* Link */ | ||
| 86 | #define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ | ||
| 87 | #define AT91_EMAC_ABT (1 << 11) /* Abort */ | ||
| 88 | |||
| 89 | #define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ | ||
| 90 | #define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ | ||
| 91 | #define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ | ||
| 92 | |||
| 93 | #define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ | ||
| 94 | #define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ | ||
| 95 | #define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ | ||
| 96 | #define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ | ||
| 97 | #define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ | ||
| 98 | #define AT91_EMAC_RW_W (1 << 28) | ||
| 99 | #define AT91_EMAC_RW_R (2 << 28) | ||
| 100 | #define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ | ||
| 101 | |||
| 102 | /* | ||
| 103 | * Statistics Registers. | ||
| 104 | */ | ||
| 105 | #define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ | ||
| 106 | #define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ | ||
| 107 | #define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ | ||
| 108 | #define AT91_EMAC_OK 0x4c /* Frames Received OK */ | ||
| 109 | #define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ | ||
| 110 | #define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ | ||
| 111 | #define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ | ||
| 112 | #define AT91_EMAC_LCOL 0x5c /* Late Collision */ | ||
| 113 | #define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ | ||
| 114 | #define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ | ||
| 115 | #define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ | ||
| 116 | #define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ | ||
| 117 | #define AT91_EMAC_ROV 0x70 /* Receive Overrun */ | ||
| 118 | #define AT91_EMAC_CDE 0x74 /* Code Error */ | ||
| 119 | #define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ | ||
| 120 | #define AT91_EMAC_RJB 0x7c /* Receive Jabber */ | ||
| 121 | #define AT91_EMAC_USF 0x80 /* Undersize Frame */ | ||
| 122 | #define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ | ||
| 123 | |||
| 124 | /* | ||
| 125 | * Address Registers. | ||
| 126 | */ | ||
| 127 | #define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ | ||
| 128 | #define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ | ||
| 129 | #define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ | ||
| 130 | #define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ | ||
| 131 | #define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ | ||
| 132 | #define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ | ||
| 133 | #define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ | ||
| 134 | #define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ | ||
| 135 | #define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ | ||
| 136 | #define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ | ||
| 137 | |||
| 138 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91rm9200_mc.h b/include/asm-arm/arch-at91/at91rm9200_mc.h deleted file mode 100644 index 24d012939cc4..000000000000 --- a/include/asm-arm/arch-at91/at91rm9200_mc.h +++ /dev/null | |||
| @@ -1,160 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91rm9200_mc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_MC_H | ||
| 17 | #define AT91RM9200_MC_H | ||
| 18 | |||
| 19 | /* Memory Controller */ | ||
| 20 | #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ | ||
| 21 | #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ | ||
| 22 | |||
| 23 | #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ | ||
| 24 | #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ | ||
| 25 | #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ | ||
| 26 | #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ | ||
| 27 | #define AT91_MC_ABTSZ_BYTE (0 << 8) | ||
| 28 | #define AT91_MC_ABTSZ_HALFWORD (1 << 8) | ||
| 29 | #define AT91_MC_ABTSZ_WORD (2 << 8) | ||
| 30 | #define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ | ||
| 31 | #define AT91_MC_ABTTYP_DATAREAD (0 << 10) | ||
| 32 | #define AT91_MC_ABTTYP_DATAWRITE (1 << 10) | ||
| 33 | #define AT91_MC_ABTTYP_FETCH (2 << 10) | ||
| 34 | #define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ | ||
| 35 | #define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ | ||
| 36 | #define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ | ||
| 37 | #define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ | ||
| 38 | #define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ | ||
| 39 | #define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ | ||
| 40 | #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ | ||
| 41 | #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ | ||
| 42 | |||
| 43 | #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ | ||
| 44 | |||
| 45 | #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ | ||
| 46 | #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ | ||
| 47 | #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ | ||
| 48 | #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ | ||
| 49 | #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ | ||
| 50 | |||
| 51 | /* External Bus Interface (EBI) registers */ | ||
| 52 | #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ | ||
| 53 | #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ | ||
| 54 | #define AT91_EBI_CS0A_SMC (0 << 0) | ||
| 55 | #define AT91_EBI_CS0A_BFC (1 << 0) | ||
| 56 | #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 57 | #define AT91_EBI_CS1A_SMC (0 << 1) | ||
| 58 | #define AT91_EBI_CS1A_SDRAMC (1 << 1) | ||
| 59 | #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ | ||
| 60 | #define AT91_EBI_CS3A_SMC (0 << 3) | ||
| 61 | #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 62 | #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ | ||
| 63 | #define AT91_EBI_CS4A_SMC (0 << 4) | ||
| 64 | #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) | ||
| 65 | #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ | ||
| 66 | #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ | ||
| 67 | |||
| 68 | /* Static Memory Controller (SMC) registers */ | ||
| 69 | #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ | ||
| 70 | #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ | ||
| 71 | #define AT91_SMC_NWS_(x) ((x) << 0) | ||
| 72 | #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ | ||
| 73 | #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ | ||
| 74 | #define AT91_SMC_TDF_(x) ((x) << 8) | ||
| 75 | #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ | ||
| 76 | #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ | ||
| 77 | #define AT91_SMC_DBW_16 (1 << 13) | ||
| 78 | #define AT91_SMC_DBW_8 (2 << 13) | ||
| 79 | #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ | ||
| 80 | #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ | ||
| 81 | #define AT91_SMC_ACSS_STD (0 << 16) | ||
| 82 | #define AT91_SMC_ACSS_1 (1 << 16) | ||
| 83 | #define AT91_SMC_ACSS_2 (2 << 16) | ||
| 84 | #define AT91_SMC_ACSS_3 (3 << 16) | ||
| 85 | #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ | ||
| 86 | #define AT91_SMC_RWSETUP_(x) ((x) << 24) | ||
| 87 | #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ | ||
| 88 | #define AT91_SMC_RWHOLD_(x) ((x) << 28) | ||
| 89 | |||
| 90 | /* SDRAM Controller registers */ | ||
| 91 | #define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ | ||
| 92 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 93 | #define AT91_SDRAMC_MODE_NORMAL (0 << 0) | ||
| 94 | #define AT91_SDRAMC_MODE_NOP (1 << 0) | ||
| 95 | #define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) | ||
| 96 | #define AT91_SDRAMC_MODE_LMR (3 << 0) | ||
| 97 | #define AT91_SDRAMC_MODE_REFRESH (4 << 0) | ||
| 98 | #define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ | ||
| 99 | #define AT91_SDRAMC_DBW_32 (0 << 4) | ||
| 100 | #define AT91_SDRAMC_DBW_16 (1 << 4) | ||
| 101 | |||
| 102 | #define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ | ||
| 103 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ | ||
| 104 | |||
| 105 | #define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ | ||
| 106 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 107 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 108 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 109 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 110 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 111 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 112 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 113 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 114 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 115 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 116 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 117 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 118 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 119 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 120 | #define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ | ||
| 121 | #define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ | ||
| 122 | #define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ | ||
| 123 | #define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ | ||
| 124 | #define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ | ||
| 125 | #define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ | ||
| 126 | |||
| 127 | #define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ | ||
| 128 | #define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ | ||
| 129 | #define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ | ||
| 130 | #define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ | ||
| 131 | #define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ | ||
| 132 | #define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ | ||
| 133 | |||
| 134 | /* Burst Flash Controller register */ | ||
| 135 | #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ | ||
| 136 | #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ | ||
| 137 | #define AT91_BFC_BFCOM_DISABLED (0 << 0) | ||
| 138 | #define AT91_BFC_BFCOM_ASYNC (1 << 0) | ||
| 139 | #define AT91_BFC_BFCOM_BURST (2 << 0) | ||
| 140 | #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ | ||
| 141 | #define AT91_BFC_BFCC_MCK (1 << 2) | ||
| 142 | #define AT91_BFC_BFCC_DIV2 (2 << 2) | ||
| 143 | #define AT91_BFC_BFCC_DIV4 (3 << 2) | ||
| 144 | #define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ | ||
| 145 | #define AT91_BFC_PAGES (7 << 8) /* Page Size */ | ||
| 146 | #define AT91_BFC_PAGES_NO_PAGE (0 << 8) | ||
| 147 | #define AT91_BFC_PAGES_16 (1 << 8) | ||
| 148 | #define AT91_BFC_PAGES_32 (2 << 8) | ||
| 149 | #define AT91_BFC_PAGES_64 (3 << 8) | ||
| 150 | #define AT91_BFC_PAGES_128 (4 << 8) | ||
| 151 | #define AT91_BFC_PAGES_256 (5 << 8) | ||
| 152 | #define AT91_BFC_PAGES_512 (6 << 8) | ||
| 153 | #define AT91_BFC_PAGES_1024 (7 << 8) | ||
| 154 | #define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ | ||
| 155 | #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ | ||
| 156 | #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ | ||
| 157 | #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ | ||
| 158 | #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ | ||
| 159 | |||
| 160 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h deleted file mode 100644 index 889872a3f2a9..000000000000 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ /dev/null | |||
| @@ -1,138 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9260.h | ||
| 3 | * | ||
| 4 | * (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9260 datasheet revision A (Preliminary). | ||
| 8 | * | ||
| 9 | * Includes also definitions for AT91SAM9XE and AT91SAM9G families | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License as published by | ||
| 13 | * the Free Software Foundation; either version 2 of the License, or | ||
| 14 | * (at your option) any later version. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef AT91SAM9260_H | ||
| 18 | #define AT91SAM9260_H | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Peripheral identifiers/interrupts. | ||
| 22 | */ | ||
| 23 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 24 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 25 | #define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 26 | #define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 27 | #define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 28 | #define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ | ||
| 29 | #define AT91SAM9260_ID_US0 6 /* USART 0 */ | ||
| 30 | #define AT91SAM9260_ID_US1 7 /* USART 1 */ | ||
| 31 | #define AT91SAM9260_ID_US2 8 /* USART 2 */ | ||
| 32 | #define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ | ||
| 33 | #define AT91SAM9260_ID_UDP 10 /* USB Device Port */ | ||
| 34 | #define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ | ||
| 35 | #define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
| 36 | #define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
| 37 | #define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ | ||
| 38 | #define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ | ||
| 39 | #define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ | ||
| 40 | #define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ | ||
| 41 | #define AT91SAM9260_ID_UHP 20 /* USB Host port */ | ||
| 42 | #define AT91SAM9260_ID_EMAC 21 /* Ethernet */ | ||
| 43 | #define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ | ||
| 44 | #define AT91SAM9260_ID_US3 23 /* USART 3 */ | ||
| 45 | #define AT91SAM9260_ID_US4 24 /* USART 4 */ | ||
| 46 | #define AT91SAM9260_ID_US5 25 /* USART 5 */ | ||
| 47 | #define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ | ||
| 48 | #define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ | ||
| 49 | #define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ | ||
| 50 | #define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 51 | #define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 52 | #define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 53 | |||
| 54 | |||
| 55 | /* | ||
| 56 | * User Peripheral physical base addresses. | ||
| 57 | */ | ||
| 58 | #define AT91SAM9260_BASE_TCB0 0xfffa0000 | ||
| 59 | #define AT91SAM9260_BASE_TC0 0xfffa0000 | ||
| 60 | #define AT91SAM9260_BASE_TC1 0xfffa0040 | ||
| 61 | #define AT91SAM9260_BASE_TC2 0xfffa0080 | ||
| 62 | #define AT91SAM9260_BASE_UDP 0xfffa4000 | ||
| 63 | #define AT91SAM9260_BASE_MCI 0xfffa8000 | ||
| 64 | #define AT91SAM9260_BASE_TWI 0xfffac000 | ||
| 65 | #define AT91SAM9260_BASE_US0 0xfffb0000 | ||
| 66 | #define AT91SAM9260_BASE_US1 0xfffb4000 | ||
| 67 | #define AT91SAM9260_BASE_US2 0xfffb8000 | ||
| 68 | #define AT91SAM9260_BASE_SSC 0xfffbc000 | ||
| 69 | #define AT91SAM9260_BASE_ISI 0xfffc0000 | ||
| 70 | #define AT91SAM9260_BASE_EMAC 0xfffc4000 | ||
| 71 | #define AT91SAM9260_BASE_SPI0 0xfffc8000 | ||
| 72 | #define AT91SAM9260_BASE_SPI1 0xfffcc000 | ||
| 73 | #define AT91SAM9260_BASE_US3 0xfffd0000 | ||
| 74 | #define AT91SAM9260_BASE_US4 0xfffd4000 | ||
| 75 | #define AT91SAM9260_BASE_US5 0xfffd8000 | ||
| 76 | #define AT91SAM9260_BASE_TCB1 0xfffdc000 | ||
| 77 | #define AT91SAM9260_BASE_TC3 0xfffdc000 | ||
| 78 | #define AT91SAM9260_BASE_TC4 0xfffdc040 | ||
| 79 | #define AT91SAM9260_BASE_TC5 0xfffdc080 | ||
| 80 | #define AT91SAM9260_BASE_ADC 0xfffe0000 | ||
| 81 | #define AT91_BASE_SYS 0xffffe800 | ||
| 82 | |||
| 83 | /* | ||
| 84 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 85 | */ | ||
| 86 | #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) | ||
| 87 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 88 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 89 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 90 | #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) | ||
| 91 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 92 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 93 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 94 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 95 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 96 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 97 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 98 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 99 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 100 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 101 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 102 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 103 | |||
| 104 | #define AT91_USART0 AT91SAM9260_BASE_US0 | ||
| 105 | #define AT91_USART1 AT91SAM9260_BASE_US1 | ||
| 106 | #define AT91_USART2 AT91SAM9260_BASE_US2 | ||
| 107 | #define AT91_USART3 AT91SAM9260_BASE_US3 | ||
| 108 | #define AT91_USART4 AT91SAM9260_BASE_US4 | ||
| 109 | #define AT91_USART5 AT91SAM9260_BASE_US5 | ||
| 110 | |||
| 111 | |||
| 112 | /* | ||
| 113 | * Internal Memory. | ||
| 114 | */ | ||
| 115 | #define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ | ||
| 116 | #define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 117 | |||
| 118 | #define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ | ||
| 119 | #define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ | ||
| 120 | #define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ | ||
| 121 | #define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ | ||
| 122 | |||
| 123 | #define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 124 | |||
| 125 | #define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ | ||
| 126 | #define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 127 | |||
| 128 | #define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ | ||
| 129 | #define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 130 | |||
| 131 | #define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ | ||
| 132 | #define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ | ||
| 133 | #define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ | ||
| 134 | #define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ | ||
| 135 | |||
| 136 | #define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 137 | |||
| 138 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h deleted file mode 100644 index a8e9fec6c735..000000000000 --- a/include/asm-arm/arch-at91/at91sam9260_matrix.h +++ /dev/null | |||
| @@ -1,78 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9260_matrix.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9260 datasheet revision B. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9260_MATRIX_H | ||
| 14 | #define AT91SAM9260_MATRIX_H | ||
| 15 | |||
| 16 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 17 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 18 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 19 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 20 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 21 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 22 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 23 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 24 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 25 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 26 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 27 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 28 | |||
| 29 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 30 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 31 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 32 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 33 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 34 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 35 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 36 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 37 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 38 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 39 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 40 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 41 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 42 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 43 | |||
| 44 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 45 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 46 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 47 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 48 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 49 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 50 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 51 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 52 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 53 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 54 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 55 | |||
| 56 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 57 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 58 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 59 | |||
| 60 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ | ||
| 61 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 62 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 63 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 64 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 65 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 66 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 67 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 68 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 69 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 70 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 71 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 72 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 73 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 74 | #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 75 | #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) | ||
| 76 | #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) | ||
| 77 | |||
| 78 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h deleted file mode 100644 index c7c4778dac49..000000000000 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ /dev/null | |||
| @@ -1,105 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9261.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9261 datasheet revision E. (Preliminary) | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9261_H | ||
| 16 | #define AT91SAM9261_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 26 | #define AT91SAM9261_ID_US0 6 /* USART 0 */ | ||
| 27 | #define AT91SAM9261_ID_US1 7 /* USART 1 */ | ||
| 28 | #define AT91SAM9261_ID_US2 8 /* USART 2 */ | ||
| 29 | #define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ | ||
| 30 | #define AT91SAM9261_ID_UDP 10 /* USB Device Port */ | ||
| 31 | #define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ | ||
| 32 | #define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
| 33 | #define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
| 34 | #define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
| 35 | #define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
| 36 | #define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ | ||
| 37 | #define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ | ||
| 38 | #define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ | ||
| 39 | #define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ | ||
| 40 | #define AT91SAM9261_ID_UHP 20 /* USB Host port */ | ||
| 41 | #define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ | ||
| 42 | #define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 43 | #define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 44 | #define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 45 | |||
| 46 | |||
| 47 | /* | ||
| 48 | * User Peripheral physical base addresses. | ||
| 49 | */ | ||
| 50 | #define AT91SAM9261_BASE_TCB0 0xfffa0000 | ||
| 51 | #define AT91SAM9261_BASE_TC0 0xfffa0000 | ||
| 52 | #define AT91SAM9261_BASE_TC1 0xfffa0040 | ||
| 53 | #define AT91SAM9261_BASE_TC2 0xfffa0080 | ||
| 54 | #define AT91SAM9261_BASE_UDP 0xfffa4000 | ||
| 55 | #define AT91SAM9261_BASE_MCI 0xfffa8000 | ||
| 56 | #define AT91SAM9261_BASE_TWI 0xfffac000 | ||
| 57 | #define AT91SAM9261_BASE_US0 0xfffb0000 | ||
| 58 | #define AT91SAM9261_BASE_US1 0xfffb4000 | ||
| 59 | #define AT91SAM9261_BASE_US2 0xfffb8000 | ||
| 60 | #define AT91SAM9261_BASE_SSC0 0xfffbc000 | ||
| 61 | #define AT91SAM9261_BASE_SSC1 0xfffc0000 | ||
| 62 | #define AT91SAM9261_BASE_SSC2 0xfffc4000 | ||
| 63 | #define AT91SAM9261_BASE_SPI0 0xfffc8000 | ||
| 64 | #define AT91SAM9261_BASE_SPI1 0xfffcc000 | ||
| 65 | #define AT91_BASE_SYS 0xffffea00 | ||
| 66 | |||
| 67 | |||
| 68 | /* | ||
| 69 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 70 | */ | ||
| 71 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 72 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 74 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 75 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 76 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 77 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 78 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 79 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 80 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 81 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 82 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 83 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 84 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 85 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 86 | |||
| 87 | #define AT91_USART0 AT91SAM9261_BASE_US0 | ||
| 88 | #define AT91_USART1 AT91SAM9261_BASE_US1 | ||
| 89 | #define AT91_USART2 AT91SAM9261_BASE_US2 | ||
| 90 | |||
| 91 | |||
| 92 | /* | ||
| 93 | * Internal Memory. | ||
| 94 | */ | ||
| 95 | #define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 96 | #define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ | ||
| 97 | |||
| 98 | #define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 99 | #define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 100 | |||
| 101 | #define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 102 | #define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ | ||
| 103 | |||
| 104 | |||
| 105 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9261_matrix.h b/include/asm-arm/arch-at91/at91sam9261_matrix.h deleted file mode 100644 index 6f072421be5b..000000000000 --- a/include/asm-arm/arch-at91/at91sam9261_matrix.h +++ /dev/null | |||
| @@ -1,62 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9261_matrix.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9261_MATRIX_H | ||
| 14 | #define AT91SAM9261_MATRIX_H | ||
| 15 | |||
| 16 | #define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ | ||
| 17 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 18 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 19 | |||
| 20 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ | ||
| 21 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ | ||
| 22 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ | ||
| 23 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ | ||
| 24 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ | ||
| 25 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 26 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 27 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 28 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 29 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 30 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 31 | |||
| 32 | #define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ | ||
| 33 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 34 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 35 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
| 36 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 37 | #define AT91_MATRIX_ITCM_64 (7 << 0) | ||
| 38 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 39 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 40 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
| 41 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 42 | #define AT91_MATRIX_DTCM_64 (7 << 4) | ||
| 43 | |||
| 44 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ | ||
| 45 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 46 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 47 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 48 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 49 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 50 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 51 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 52 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 53 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 54 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 55 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 56 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 57 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 58 | |||
| 59 | #define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ | ||
| 60 | #define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ | ||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h deleted file mode 100644 index 018a647311da..000000000000 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ /dev/null | |||
| @@ -1,127 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9263.h | ||
| 3 | * | ||
| 4 | * (C) 2007 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9263 datasheet revision B (Preliminary). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9263_H | ||
| 16 | #define AT91SAM9263_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ | ||
| 26 | #define AT91SAM9263_ID_US0 7 /* USART 0 */ | ||
| 27 | #define AT91SAM9263_ID_US1 8 /* USART 1 */ | ||
| 28 | #define AT91SAM9263_ID_US2 9 /* USART 2 */ | ||
| 29 | #define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ | ||
| 30 | #define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ | ||
| 31 | #define AT91SAM9263_ID_CAN 12 /* CAN */ | ||
| 32 | #define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ | ||
| 33 | #define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ | ||
| 34 | #define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ | ||
| 35 | #define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ | ||
| 36 | #define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ | ||
| 37 | #define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ | ||
| 38 | #define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ | ||
| 39 | #define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ | ||
| 40 | #define AT91SAM9263_ID_EMAC 21 /* Ethernet */ | ||
| 41 | #define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ | ||
| 42 | #define AT91SAM9263_ID_UDP 24 /* USB Device Port */ | ||
| 43 | #define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ | ||
| 44 | #define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ | ||
| 45 | #define AT91SAM9263_ID_DMA 27 /* DMA Controller */ | ||
| 46 | #define AT91SAM9263_ID_UHP 29 /* USB Host port */ | ||
| 47 | #define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 48 | #define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 49 | |||
| 50 | |||
| 51 | /* | ||
| 52 | * User Peripheral physical base addresses. | ||
| 53 | */ | ||
| 54 | #define AT91SAM9263_BASE_UDP 0xfff78000 | ||
| 55 | #define AT91SAM9263_BASE_TCB0 0xfff7c000 | ||
| 56 | #define AT91SAM9263_BASE_TC0 0xfff7c000 | ||
| 57 | #define AT91SAM9263_BASE_TC1 0xfff7c040 | ||
| 58 | #define AT91SAM9263_BASE_TC2 0xfff7c080 | ||
| 59 | #define AT91SAM9263_BASE_MCI0 0xfff80000 | ||
| 60 | #define AT91SAM9263_BASE_MCI1 0xfff84000 | ||
| 61 | #define AT91SAM9263_BASE_TWI 0xfff88000 | ||
| 62 | #define AT91SAM9263_BASE_US0 0xfff8c000 | ||
| 63 | #define AT91SAM9263_BASE_US1 0xfff90000 | ||
| 64 | #define AT91SAM9263_BASE_US2 0xfff94000 | ||
| 65 | #define AT91SAM9263_BASE_SSC0 0xfff98000 | ||
| 66 | #define AT91SAM9263_BASE_SSC1 0xfff9c000 | ||
| 67 | #define AT91SAM9263_BASE_AC97C 0xfffa0000 | ||
| 68 | #define AT91SAM9263_BASE_SPI0 0xfffa4000 | ||
| 69 | #define AT91SAM9263_BASE_SPI1 0xfffa8000 | ||
| 70 | #define AT91SAM9263_BASE_CAN 0xfffac000 | ||
| 71 | #define AT91SAM9263_BASE_PWMC 0xfffb8000 | ||
| 72 | #define AT91SAM9263_BASE_EMAC 0xfffbc000 | ||
| 73 | #define AT91SAM9263_BASE_ISI 0xfffc4000 | ||
| 74 | #define AT91SAM9263_BASE_2DGE 0xfffc8000 | ||
| 75 | #define AT91_BASE_SYS 0xffffe000 | ||
| 76 | |||
| 77 | /* | ||
| 78 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 79 | */ | ||
| 80 | #define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) | ||
| 81 | #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) | ||
| 82 | #define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) | ||
| 83 | #define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) | ||
| 84 | #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) | ||
| 85 | #define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) | ||
| 86 | #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) | ||
| 87 | #define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) | ||
| 88 | #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) | ||
| 89 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 90 | #define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) | ||
| 91 | #define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) | ||
| 92 | #define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) | ||
| 93 | #define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) | ||
| 94 | #define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) | ||
| 95 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 96 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 97 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 98 | #define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) | ||
| 99 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 100 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 101 | #define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) | ||
| 102 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | ||
| 103 | |||
| 104 | #define AT91_USART0 AT91SAM9263_BASE_US0 | ||
| 105 | #define AT91_USART1 AT91SAM9263_BASE_US1 | ||
| 106 | #define AT91_USART2 AT91SAM9263_BASE_US2 | ||
| 107 | |||
| 108 | #define AT91_SMC AT91_SMC0 | ||
| 109 | |||
| 110 | /* | ||
| 111 | * Internal Memory. | ||
| 112 | */ | ||
| 113 | #define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ | ||
| 114 | #define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ | ||
| 115 | |||
| 116 | #define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 117 | #define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ | ||
| 118 | |||
| 119 | #define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ | ||
| 120 | #define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ | ||
| 121 | |||
| 122 | #define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ | ||
| 123 | #define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ | ||
| 124 | #define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ | ||
| 125 | |||
| 126 | |||
| 127 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h deleted file mode 100644 index 72f6e668e414..000000000000 --- a/include/asm-arm/arch-at91/at91sam9263_matrix.h +++ /dev/null | |||
| @@ -1,129 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9263_matrix.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 7 | * Based on AT91SAM9263 datasheet revision B (Preliminary). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9263_MATRIX_H | ||
| 16 | #define AT91SAM9263_MATRIX_H | ||
| 17 | |||
| 18 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 19 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 20 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 21 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 22 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 23 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 24 | #define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ | ||
| 25 | #define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ | ||
| 26 | #define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ | ||
| 27 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 28 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 29 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 30 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 31 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 32 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 33 | |||
| 34 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 35 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 36 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 37 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 38 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 39 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | ||
| 40 | #define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ | ||
| 41 | #define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ | ||
| 42 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 43 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 44 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 45 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 46 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 47 | #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ | ||
| 48 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 49 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 50 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 51 | |||
| 52 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 53 | #define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ | ||
| 54 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 55 | #define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ | ||
| 56 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 57 | #define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ | ||
| 58 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 59 | #define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ | ||
| 60 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 61 | #define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ | ||
| 62 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | ||
| 63 | #define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ | ||
| 64 | #define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ | ||
| 65 | #define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ | ||
| 66 | #define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ | ||
| 67 | #define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ | ||
| 68 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 69 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 70 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 71 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 72 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 73 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 74 | #define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ | ||
| 75 | #define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ | ||
| 76 | #define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ | ||
| 77 | |||
| 78 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 79 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 80 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 81 | #define AT91_MATRIX_RCB2 (1 << 2) | ||
| 82 | #define AT91_MATRIX_RCB3 (1 << 3) | ||
| 83 | #define AT91_MATRIX_RCB4 (1 << 4) | ||
| 84 | #define AT91_MATRIX_RCB5 (1 << 5) | ||
| 85 | #define AT91_MATRIX_RCB6 (1 << 6) | ||
| 86 | #define AT91_MATRIX_RCB7 (1 << 7) | ||
| 87 | #define AT91_MATRIX_RCB8 (1 << 8) | ||
| 88 | |||
| 89 | #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ | ||
| 90 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 91 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 92 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
| 93 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 94 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 95 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 96 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
| 97 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 98 | |||
| 99 | #define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ | ||
| 100 | #define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 101 | #define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) | ||
| 102 | #define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) | ||
| 103 | #define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 104 | #define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) | ||
| 105 | #define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 106 | #define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 107 | #define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) | ||
| 108 | #define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) | ||
| 109 | #define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 110 | #define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) | ||
| 111 | #define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) | ||
| 112 | #define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 113 | #define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 114 | #define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) | ||
| 115 | #define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) | ||
| 116 | |||
| 117 | #define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ | ||
| 118 | #define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 119 | #define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) | ||
| 120 | #define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) | ||
| 121 | #define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 122 | #define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) | ||
| 123 | #define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) | ||
| 124 | #define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 125 | #define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 126 | #define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) | ||
| 127 | #define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) | ||
| 128 | |||
| 129 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h deleted file mode 100644 index d3b8b3da6b4d..000000000000 --- a/include/asm-arm/arch-at91/at91sam9_sdramc.h +++ /dev/null | |||
| @@ -1,83 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9_sdramc.h | ||
| 3 | * | ||
| 4 | * SDRAM Controllers (SDRAMC) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9_SDRAMC_H | ||
| 14 | #define AT91SAM9_SDRAMC_H | ||
| 15 | |||
| 16 | /* SDRAM Controller (SDRAMC) registers */ | ||
| 17 | #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ | ||
| 18 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 19 | #define AT91_SDRAMC_MODE_NORMAL 0 | ||
| 20 | #define AT91_SDRAMC_MODE_NOP 1 | ||
| 21 | #define AT91_SDRAMC_MODE_PRECHARGE 2 | ||
| 22 | #define AT91_SDRAMC_MODE_LMR 3 | ||
| 23 | #define AT91_SDRAMC_MODE_REFRESH 4 | ||
| 24 | #define AT91_SDRAMC_MODE_EXT_LMR 5 | ||
| 25 | #define AT91_SDRAMC_MODE_DEEP 6 | ||
| 26 | |||
| 27 | #define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ | ||
| 28 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
| 29 | |||
| 30 | #define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ | ||
| 31 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 32 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 33 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 34 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 35 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 36 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 37 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 38 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 39 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 40 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 41 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 42 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 43 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 44 | #define AT91_SDRAMC_CAS_1 (1 << 5) | ||
| 45 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 46 | #define AT91_SDRAMC_CAS_3 (3 << 5) | ||
| 47 | #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ | ||
| 48 | #define AT91_SDRAMC_DBW_32 (0 << 7) | ||
| 49 | #define AT91_SDRAMC_DBW_16 (1 << 7) | ||
| 50 | #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ | ||
| 51 | #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ | ||
| 52 | #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ | ||
| 53 | #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ | ||
| 54 | #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ | ||
| 55 | #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ | ||
| 56 | |||
| 57 | #define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ | ||
| 58 | #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ | ||
| 59 | #define AT91_SDRAMC_LPCB_DISABLE 0 | ||
| 60 | #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 | ||
| 61 | #define AT91_SDRAMC_LPCB_POWER_DOWN 2 | ||
| 62 | #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 | ||
| 63 | #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
| 64 | #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
| 65 | #define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ | ||
| 66 | #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
| 67 | #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
| 68 | #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
| 69 | #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
| 70 | |||
| 71 | #define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ | ||
| 72 | #define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ | ||
| 73 | #define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ | ||
| 74 | #define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ | ||
| 75 | #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ | ||
| 76 | |||
| 77 | #define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ | ||
| 78 | #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ | ||
| 79 | #define AT91_SDRAMC_MD_SDRAM 0 | ||
| 80 | #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 | ||
| 81 | |||
| 82 | |||
| 83 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h deleted file mode 100644 index 9e49eed31e50..000000000000 --- a/include/asm-arm/arch-at91/at91sam9_smc.h +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9_smc.h | ||
| 3 | * | ||
| 4 | * Static Memory Controllers (SMC) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9_SMC_H | ||
| 14 | #define AT91SAM9_SMC_H | ||
| 15 | |||
| 16 | #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
| 17 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | ||
| 18 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) | ||
| 19 | #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ | ||
| 20 | #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) | ||
| 21 | #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ | ||
| 22 | #define AT91_SMC_NRDSETUP_(x) ((x) << 16) | ||
| 23 | #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ | ||
| 24 | #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) | ||
| 25 | |||
| 26 | #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
| 27 | #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ | ||
| 28 | #define AT91_SMC_NWEPULSE_(x) ((x) << 0) | ||
| 29 | #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ | ||
| 30 | #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) | ||
| 31 | #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ | ||
| 32 | #define AT91_SMC_NRDPULSE_(x) ((x) << 16) | ||
| 33 | #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ | ||
| 34 | #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) | ||
| 35 | |||
| 36 | #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
| 37 | #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ | ||
| 38 | #define AT91_SMC_NWECYCLE_(x) ((x) << 0) | ||
| 39 | #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ | ||
| 40 | #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) | ||
| 41 | |||
| 42 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
| 43 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | ||
| 44 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | ||
| 45 | #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ | ||
| 46 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) | ||
| 47 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) | ||
| 48 | #define AT91_SMC_EXNWMODE_READY (3 << 4) | ||
| 49 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | ||
| 50 | #define AT91_SMC_BAT_SELECT (0 << 8) | ||
| 51 | #define AT91_SMC_BAT_WRITE (1 << 8) | ||
| 52 | #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ | ||
| 53 | #define AT91_SMC_DBW_8 (0 << 12) | ||
| 54 | #define AT91_SMC_DBW_16 (1 << 12) | ||
| 55 | #define AT91_SMC_DBW_32 (2 << 12) | ||
| 56 | #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ | ||
| 57 | #define AT91_SMC_TDF_(x) ((x) << 16) | ||
| 58 | #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ | ||
| 59 | #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ | ||
| 60 | #define AT91_SMC_PS (3 << 28) /* Page Size */ | ||
| 61 | #define AT91_SMC_PS_4 (0 << 28) | ||
| 62 | #define AT91_SMC_PS_8 (1 << 28) | ||
| 63 | #define AT91_SMC_PS_16 (2 << 28) | ||
| 64 | #define AT91_SMC_PS_32 (3 << 28) | ||
| 65 | |||
| 66 | #if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ | ||
| 67 | #define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
| 68 | #define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
| 69 | #define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
| 70 | #define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
| 71 | #endif | ||
| 72 | |||
| 73 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h deleted file mode 100644 index 622e56f81d42..000000000000 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ /dev/null | |||
| @@ -1,115 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9260.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Atmel Corporation | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9RL datasheet revision A. (Preliminary) | ||
| 8 | * | ||
| 9 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 10 | * License. See the file COPYING in the main directory of this archive for | ||
| 11 | * more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef AT91SAM9RL_H | ||
| 15 | #define AT91SAM9RL_H | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Peripheral identifiers/interrupts. | ||
| 19 | */ | ||
| 20 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 21 | #define AT91_ID_SYS 1 /* System Controller */ | ||
| 22 | #define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 23 | #define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 24 | #define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 25 | #define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ | ||
| 26 | #define AT91SAM9RL_ID_US0 6 /* USART 0 */ | ||
| 27 | #define AT91SAM9RL_ID_US1 7 /* USART 1 */ | ||
| 28 | #define AT91SAM9RL_ID_US2 8 /* USART 2 */ | ||
| 29 | #define AT91SAM9RL_ID_US3 9 /* USART 3 */ | ||
| 30 | #define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ | ||
| 31 | #define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ | ||
| 32 | #define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ | ||
| 33 | #define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ | ||
| 34 | #define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
| 35 | #define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
| 36 | #define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ | ||
| 37 | #define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ | ||
| 38 | #define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ | ||
| 39 | #define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ | ||
| 40 | #define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ | ||
| 41 | #define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ | ||
| 42 | #define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ | ||
| 43 | #define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ | ||
| 44 | #define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ | ||
| 45 | #define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 46 | |||
| 47 | |||
| 48 | /* | ||
| 49 | * User Peripheral physical base addresses. | ||
| 50 | */ | ||
| 51 | #define AT91SAM9RL_BASE_TCB0 0xfffa0000 | ||
| 52 | #define AT91SAM9RL_BASE_TC0 0xfffa0000 | ||
| 53 | #define AT91SAM9RL_BASE_TC1 0xfffa0040 | ||
| 54 | #define AT91SAM9RL_BASE_TC2 0xfffa0080 | ||
| 55 | #define AT91SAM9RL_BASE_MCI 0xfffa4000 | ||
| 56 | #define AT91SAM9RL_BASE_TWI0 0xfffa8000 | ||
| 57 | #define AT91SAM9RL_BASE_TWI1 0xfffac000 | ||
| 58 | #define AT91SAM9RL_BASE_US0 0xfffb0000 | ||
| 59 | #define AT91SAM9RL_BASE_US1 0xfffb4000 | ||
| 60 | #define AT91SAM9RL_BASE_US2 0xfffb8000 | ||
| 61 | #define AT91SAM9RL_BASE_US3 0xfffbc000 | ||
| 62 | #define AT91SAM9RL_BASE_SSC0 0xfffc0000 | ||
| 63 | #define AT91SAM9RL_BASE_SSC1 0xfffc4000 | ||
| 64 | #define AT91SAM9RL_BASE_PWMC 0xfffc8000 | ||
| 65 | #define AT91SAM9RL_BASE_SPI 0xfffcc000 | ||
| 66 | #define AT91SAM9RL_BASE_TSC 0xfffd0000 | ||
| 67 | #define AT91SAM9RL_BASE_UDPHS 0xfffd4000 | ||
| 68 | #define AT91SAM9RL_BASE_AC97C 0xfffd8000 | ||
| 69 | #define AT91_BASE_SYS 0xffffc000 | ||
| 70 | |||
| 71 | |||
| 72 | /* | ||
| 73 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 74 | */ | ||
| 75 | #define AT91_DMA (0xffffe600 - AT91_BASE_SYS) | ||
| 76 | #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) | ||
| 77 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 78 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 79 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 80 | #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) | ||
| 81 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 82 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 83 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 84 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 85 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 86 | #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) | ||
| 87 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 88 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 89 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 90 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 91 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 92 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 93 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) | ||
| 94 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | ||
| 95 | #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) | ||
| 96 | |||
| 97 | #define AT91_USART0 AT91SAM9RL_BASE_US0 | ||
| 98 | #define AT91_USART1 AT91SAM9RL_BASE_US1 | ||
| 99 | #define AT91_USART2 AT91SAM9RL_BASE_US2 | ||
| 100 | #define AT91_USART3 AT91SAM9RL_BASE_US3 | ||
| 101 | |||
| 102 | |||
| 103 | /* | ||
| 104 | * Internal Memory. | ||
| 105 | */ | ||
| 106 | #define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 107 | #define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ | ||
| 108 | |||
| 109 | #define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 110 | #define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ | ||
| 111 | |||
| 112 | #define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ | ||
| 113 | #define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ | ||
| 114 | |||
| 115 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h deleted file mode 100644 index 84224174e6a1..000000000000 --- a/include/asm-arm/arch-at91/at91sam9rl_matrix.h +++ /dev/null | |||
| @@ -1,96 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91sam9rl_matrix.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Atmel Corporation | ||
| 5 | * | ||
| 6 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 7 | * Based on AT91SAM9RL datasheet revision A. (Preliminary) | ||
| 8 | * | ||
| 9 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 10 | * License. See the file COPYING in the main directory of this archive for | ||
| 11 | * more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef AT91SAM9RL_MATRIX_H | ||
| 15 | #define AT91SAM9RL_MATRIX_H | ||
| 16 | |||
| 17 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 18 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 19 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 20 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 21 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 22 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 23 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 24 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 25 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 26 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 27 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 28 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 29 | |||
| 30 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 31 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 32 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 33 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 34 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 35 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | ||
| 36 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 37 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 38 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 39 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 40 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 41 | #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ | ||
| 42 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 43 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 44 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 45 | |||
| 46 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 47 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 48 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 49 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 50 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 51 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | ||
| 52 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 53 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 54 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 55 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 56 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 57 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 58 | |||
| 59 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 60 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 61 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 62 | #define AT91_MATRIX_RCB2 (1 << 2) | ||
| 63 | #define AT91_MATRIX_RCB3 (1 << 3) | ||
| 64 | #define AT91_MATRIX_RCB4 (1 << 4) | ||
| 65 | #define AT91_MATRIX_RCB5 (1 << 5) | ||
| 66 | |||
| 67 | #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ | ||
| 68 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 69 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 70 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
| 71 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 72 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 73 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 74 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
| 75 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 76 | |||
| 77 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ | ||
| 78 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 79 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 80 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 81 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 82 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 83 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 84 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 85 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 86 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 87 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 88 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 89 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 90 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 91 | #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 92 | #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) | ||
| 93 | #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) | ||
| 94 | |||
| 95 | |||
| 96 | #endif | ||
diff --git a/include/asm-arm/arch-at91/at91x40.h b/include/asm-arm/arch-at91/at91x40.h deleted file mode 100644 index 612203e0177f..000000000000 --- a/include/asm-arm/arch-at91/at91x40.h +++ /dev/null | |||
| @@ -1,55 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91x40.h | ||
| 3 | * | ||
| 4 | * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef AT91X40_H | ||
| 13 | #define AT91X40_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * IRQ list. | ||
| 17 | */ | ||
| 18 | #define AT91_ID_FIQ 0 /* FIQ */ | ||
| 19 | #define AT91_ID_SYS 1 /* System Peripheral */ | ||
| 20 | #define AT91X40_ID_USART0 2 /* USART port 0 */ | ||
| 21 | #define AT91X40_ID_USART1 3 /* USART port 1 */ | ||
| 22 | #define AT91X40_ID_TC0 4 /* Timer/Counter 0 */ | ||
| 23 | #define AT91X40_ID_TC1 5 /* Timer/Counter 1*/ | ||
| 24 | #define AT91X40_ID_TC2 6 /* Timer/Counter 2*/ | ||
| 25 | #define AT91X40_ID_WD 7 /* Watchdog? */ | ||
| 26 | #define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */ | ||
| 27 | |||
| 28 | #define AT91X40_ID_IRQ0 16 /* External IRQ 0 */ | ||
| 29 | #define AT91X40_ID_IRQ1 17 /* External IRQ 1 */ | ||
| 30 | #define AT91X40_ID_IRQ2 18 /* External IRQ 2 */ | ||
| 31 | |||
| 32 | /* | ||
| 33 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 34 | */ | ||
| 35 | #define AT91_BASE_SYS 0xffc00000 | ||
| 36 | |||
| 37 | #define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */ | ||
| 38 | #define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */ | ||
| 39 | #define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */ | ||
| 40 | #define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */ | ||
| 41 | #define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */ | ||
| 42 | #define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */ | ||
| 43 | #define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */ | ||
| 44 | #define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */ | ||
| 45 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ | ||
| 46 | |||
| 47 | /* | ||
| 48 | * The AT91x40 series doesn't have a debug unit like the other AT91 parts. | ||
| 49 | * But it does have a chip identify register and extension ID, so define at | ||
| 50 | * least these here. | ||
| 51 | */ | ||
| 52 | #define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ | ||
| 53 | #define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ | ||
| 54 | |||
| 55 | #endif /* AT91X40_H */ | ||
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h deleted file mode 100644 index 48bbd854f57d..000000000000 --- a/include/asm-arm/arch-at91/board.h +++ /dev/null | |||
| @@ -1,172 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/board.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 HP Labs | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * These are data structures found in platform_device.dev.platform_data, | ||
| 23 | * and describing board-specific data needed by drivers. For example, | ||
| 24 | * which pin is used for a given GPIO role. | ||
| 25 | * | ||
| 26 | * In 2.6, drivers should strongly avoid board-specific knowledge so | ||
| 27 | * that supporting new boards normally won't require driver patches. | ||
| 28 | * Most board-specific knowledge should be in arch/.../board-*.c files. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef __ASM_ARCH_BOARD_H | ||
| 32 | #define __ASM_ARCH_BOARD_H | ||
| 33 | |||
| 34 | #include <linux/mtd/partitions.h> | ||
| 35 | #include <linux/device.h> | ||
| 36 | #include <linux/i2c.h> | ||
| 37 | #include <linux/leds.h> | ||
| 38 | #include <linux/spi/spi.h> | ||
| 39 | #include <linux/usb/atmel_usba_udc.h> | ||
| 40 | |||
| 41 | /* USB Device */ | ||
| 42 | struct at91_udc_data { | ||
| 43 | u8 vbus_pin; /* high == host powering us */ | ||
| 44 | u8 pullup_pin; /* active == D+ pulled up */ | ||
| 45 | u8 pullup_active_low; /* true == pullup_pin is active low */ | ||
| 46 | }; | ||
| 47 | extern void __init at91_add_device_udc(struct at91_udc_data *data); | ||
| 48 | |||
| 49 | /* USB High Speed Device */ | ||
| 50 | extern void __init at91_add_device_usba(struct usba_platform_data *data); | ||
| 51 | |||
| 52 | /* Compact Flash */ | ||
| 53 | struct at91_cf_data { | ||
| 54 | u8 irq_pin; /* I/O IRQ */ | ||
| 55 | u8 det_pin; /* Card detect */ | ||
| 56 | u8 vcc_pin; /* power switching */ | ||
| 57 | u8 rst_pin; /* card reset */ | ||
| 58 | u8 chipselect; /* EBI Chip Select number */ | ||
| 59 | }; | ||
| 60 | extern void __init at91_add_device_cf(struct at91_cf_data *data); | ||
| 61 | |||
| 62 | /* MMC / SD */ | ||
| 63 | struct at91_mmc_data { | ||
| 64 | u8 det_pin; /* card detect IRQ */ | ||
| 65 | unsigned slot_b:1; /* uses Slot B */ | ||
| 66 | unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ | ||
| 67 | u8 wp_pin; /* (SD) writeprotect detect */ | ||
| 68 | u8 vcc_pin; /* power switching (high == on) */ | ||
| 69 | }; | ||
| 70 | extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); | ||
| 71 | |||
| 72 | /* Ethernet (EMAC & MACB) */ | ||
| 73 | struct at91_eth_data { | ||
| 74 | u32 phy_mask; | ||
| 75 | u8 phy_irq_pin; /* PHY IRQ */ | ||
| 76 | u8 is_rmii; /* using RMII interface? */ | ||
| 77 | }; | ||
| 78 | extern void __init at91_add_device_eth(struct at91_eth_data *data); | ||
| 79 | |||
| 80 | #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) | ||
| 81 | #define eth_platform_data at91_eth_data | ||
| 82 | #endif | ||
| 83 | |||
| 84 | /* USB Host */ | ||
| 85 | struct at91_usbh_data { | ||
| 86 | u8 ports; /* number of ports on root hub */ | ||
| 87 | u8 vbus_pin[]; /* port power-control pin */ | ||
| 88 | }; | ||
| 89 | extern void __init at91_add_device_usbh(struct at91_usbh_data *data); | ||
| 90 | |||
| 91 | /* NAND / SmartMedia */ | ||
| 92 | struct atmel_nand_data { | ||
| 93 | u8 enable_pin; /* chip enable */ | ||
| 94 | u8 det_pin; /* card detect */ | ||
| 95 | u8 rdy_pin; /* ready/busy */ | ||
| 96 | u8 ale; /* address line number connected to ALE */ | ||
| 97 | u8 cle; /* address line number connected to CLE */ | ||
| 98 | u8 bus_width_16; /* buswidth is 16 bit */ | ||
| 99 | struct mtd_partition* (*partition_info)(int, int*); | ||
| 100 | }; | ||
| 101 | extern void __init at91_add_device_nand(struct atmel_nand_data *data); | ||
| 102 | |||
| 103 | /* I2C*/ | ||
| 104 | extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices); | ||
| 105 | |||
| 106 | /* SPI */ | ||
| 107 | extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); | ||
| 108 | |||
| 109 | /* Serial */ | ||
| 110 | #define ATMEL_UART_CTS 0x01 | ||
| 111 | #define ATMEL_UART_RTS 0x02 | ||
| 112 | #define ATMEL_UART_DSR 0x04 | ||
| 113 | #define ATMEL_UART_DTR 0x08 | ||
| 114 | #define ATMEL_UART_DCD 0x10 | ||
| 115 | #define ATMEL_UART_RI 0x20 | ||
| 116 | |||
| 117 | extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins); | ||
| 118 | extern void __init at91_set_serial_console(unsigned portnr); | ||
| 119 | |||
| 120 | struct at91_uart_config { | ||
| 121 | unsigned short console_tty; /* tty number of serial console */ | ||
| 122 | unsigned short nr_tty; /* number of serial tty's */ | ||
| 123 | short tty_map[]; /* map UART to tty number */ | ||
| 124 | }; | ||
| 125 | extern struct platform_device *atmel_default_console_device; | ||
| 126 | extern void __init __deprecated at91_init_serial(struct at91_uart_config *config); | ||
| 127 | |||
| 128 | struct atmel_uart_data { | ||
| 129 | short use_dma_tx; /* use transmit DMA? */ | ||
| 130 | short use_dma_rx; /* use receive DMA? */ | ||
| 131 | void __iomem *regs; /* virtual base address, if any */ | ||
| 132 | }; | ||
| 133 | extern void __init at91_add_device_serial(void); | ||
| 134 | |||
| 135 | /* | ||
| 136 | * SSC -- accessed through ssc_request(id). Drivers don't bind to SSC | ||
| 137 | * platform devices. Their SSC ID is part of their configuration data, | ||
| 138 | * along with information about which SSC signals they should use. | ||
| 139 | */ | ||
| 140 | #define ATMEL_SSC_TK 0x01 | ||
| 141 | #define ATMEL_SSC_TF 0x02 | ||
| 142 | #define ATMEL_SSC_TD 0x04 | ||
| 143 | #define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD) | ||
| 144 | |||
| 145 | #define ATMEL_SSC_RK 0x10 | ||
| 146 | #define ATMEL_SSC_RF 0x20 | ||
| 147 | #define ATMEL_SSC_RD 0x40 | ||
| 148 | #define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD) | ||
| 149 | |||
| 150 | extern void __init at91_add_device_ssc(unsigned id, unsigned pins); | ||
| 151 | |||
| 152 | /* LCD Controller */ | ||
| 153 | struct atmel_lcdfb_info; | ||
| 154 | extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); | ||
| 155 | |||
| 156 | /* AC97 */ | ||
| 157 | struct atmel_ac97_data { | ||
| 158 | u8 reset_pin; /* reset */ | ||
| 159 | }; | ||
| 160 | extern void __init at91_add_device_ac97(struct atmel_ac97_data *data); | ||
| 161 | |||
| 162 | /* ISI */ | ||
| 163 | extern void __init at91_add_device_isi(void); | ||
| 164 | |||
| 165 | /* LEDs */ | ||
| 166 | extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); | ||
| 167 | extern void __init at91_gpio_leds(struct gpio_led *leds, int nr); | ||
| 168 | |||
| 169 | /* FIXME: this needs a better location, but gets stuff building again */ | ||
| 170 | extern int at91_suspend_entering_slow_clock(void); | ||
| 171 | |||
| 172 | #endif | ||
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h deleted file mode 100644 index f24b55c9083f..000000000000 --- a/include/asm-arm/arch-at91/cpu.h +++ /dev/null | |||
| @@ -1,103 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/cpu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_CPU_H | ||
| 14 | #define __ASM_ARCH_CPU_H | ||
| 15 | |||
| 16 | #include <asm/arch/hardware.h> | ||
| 17 | #include <asm/arch/at91_dbgu.h> | ||
| 18 | |||
| 19 | |||
| 20 | #define ARCH_ID_AT91RM9200 0x09290780 | ||
| 21 | #define ARCH_ID_AT91SAM9260 0x019803a0 | ||
| 22 | #define ARCH_ID_AT91SAM9261 0x019703a0 | ||
| 23 | #define ARCH_ID_AT91SAM9263 0x019607a0 | ||
| 24 | #define ARCH_ID_AT91SAM9G20 0x019905a0 | ||
| 25 | #define ARCH_ID_AT91SAM9RL64 0x019b03a0 | ||
| 26 | #define ARCH_ID_AT91CAP9 0x039A03A0 | ||
| 27 | |||
| 28 | #define ARCH_ID_AT91SAM9XE128 0x329973a0 | ||
| 29 | #define ARCH_ID_AT91SAM9XE256 0x329a93a0 | ||
| 30 | #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 | ||
| 31 | |||
| 32 | #define ARCH_ID_AT91M40800 0x14080044 | ||
| 33 | #define ARCH_ID_AT91R40807 0x44080746 | ||
| 34 | #define ARCH_ID_AT91M40807 0x14080745 | ||
| 35 | #define ARCH_ID_AT91R40008 0x44000840 | ||
| 36 | |||
| 37 | static inline unsigned long at91_cpu_identify(void) | ||
| 38 | { | ||
| 39 | return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); | ||
| 40 | } | ||
| 41 | |||
| 42 | |||
| 43 | #define ARCH_FAMILY_AT91X92 0x09200000 | ||
| 44 | #define ARCH_FAMILY_AT91SAM9 0x01900000 | ||
| 45 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 | ||
| 46 | |||
| 47 | static inline unsigned long at91_arch_identify(void) | ||
| 48 | { | ||
| 49 | return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH); | ||
| 50 | } | ||
| 51 | |||
| 52 | |||
| 53 | #ifdef CONFIG_ARCH_AT91RM9200 | ||
| 54 | #define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) | ||
| 55 | #else | ||
| 56 | #define cpu_is_at91rm9200() (0) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifdef CONFIG_ARCH_AT91SAM9260 | ||
| 60 | #define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE) | ||
| 61 | #define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe()) | ||
| 62 | #else | ||
| 63 | #define cpu_is_at91sam9xe() (0) | ||
| 64 | #define cpu_is_at91sam9260() (0) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifdef CONFIG_ARCH_AT91SAM9G20 | ||
| 68 | #define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20) | ||
| 69 | #else | ||
| 70 | #define cpu_is_at91sam9g20() (0) | ||
| 71 | #endif | ||
| 72 | |||
| 73 | #ifdef CONFIG_ARCH_AT91SAM9261 | ||
| 74 | #define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) | ||
| 75 | #else | ||
| 76 | #define cpu_is_at91sam9261() (0) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifdef CONFIG_ARCH_AT91SAM9263 | ||
| 80 | #define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) | ||
| 81 | #else | ||
| 82 | #define cpu_is_at91sam9263() (0) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | #ifdef CONFIG_ARCH_AT91SAM9RL | ||
| 86 | #define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) | ||
| 87 | #else | ||
| 88 | #define cpu_is_at91sam9rl() (0) | ||
| 89 | #endif | ||
| 90 | |||
| 91 | #ifdef CONFIG_ARCH_AT91CAP9 | ||
| 92 | #define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) | ||
| 93 | #else | ||
| 94 | #define cpu_is_at91cap9() (0) | ||
| 95 | #endif | ||
| 96 | |||
| 97 | /* | ||
| 98 | * Since this is ARM, we will never run on any AVR32 CPU. But these | ||
| 99 | * definitions may reduce clutter in common drivers. | ||
| 100 | */ | ||
| 101 | #define cpu_is_at32ap7000() (0) | ||
| 102 | |||
| 103 | #endif | ||
diff --git a/include/asm-arm/arch-at91/debug-macro.S b/include/asm-arm/arch-at91/debug-macro.S deleted file mode 100644 index ff28696b6d90..000000000000 --- a/include/asm-arm/arch-at91/debug-macro.S +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/debug-macro.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003-2005 SAN People | ||
| 5 | * | ||
| 6 | * Debugging macro include header | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | #include <asm/arch/at91_dbgu.h> | ||
| 16 | |||
| 17 | .macro addruart,rx | ||
| 18 | mrc p15, 0, \rx, c1, c0 | ||
| 19 | tst \rx, #1 @ MMU enabled? | ||
| 20 | ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) | ||
| 21 | ldrne \rx, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro senduart,rd,rx | ||
| 25 | strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register | ||
| 26 | .endm | ||
| 27 | |||
| 28 | .macro waituart,rd,rx | ||
| 29 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register | ||
| 30 | tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit | ||
| 31 | beq 1001b | ||
| 32 | .endm | ||
| 33 | |||
| 34 | .macro busyuart,rd,rx | ||
| 35 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register | ||
| 36 | tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete | ||
| 37 | beq 1001b | ||
| 38 | .endm | ||
| 39 | |||
diff --git a/include/asm-arm/arch-at91/dma.h b/include/asm-arm/arch-at91/dma.h deleted file mode 100644 index 774565412beb..000000000000 --- a/include/asm-arm/arch-at91/dma.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
diff --git a/include/asm-arm/arch-at91/entry-macro.S b/include/asm-arm/arch-at91/entry-macro.S deleted file mode 100644 index cbaf6050154a..000000000000 --- a/include/asm-arm/arch-at91/entry-macro.S +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/entry-macro.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003-2005 SAN People | ||
| 5 | * | ||
| 6 | * Low-level IRQ helper macros for AT91RM9200 platforms | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <asm/arch/hardware.h> | ||
| 14 | #include <asm/arch/at91_aic.h> | ||
| 15 | |||
| 16 | .macro disable_fiq | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro get_irqnr_preamble, base, tmp | ||
| 20 | ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 24 | .endm | ||
| 25 | |||
| 26 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 27 | ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) | ||
| 28 | ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number | ||
| 29 | teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt | ||
| 30 | streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now. | ||
| 31 | .endm | ||
| 32 | |||
diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h deleted file mode 100644 index 0a241e2fb672..000000000000 --- a/include/asm-arm/arch-at91/gpio.h +++ /dev/null | |||
| @@ -1,252 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/gpio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 HP Labs | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_AT91RM9200_GPIO_H | ||
| 14 | #define __ASM_ARCH_AT91RM9200_GPIO_H | ||
| 15 | |||
| 16 | #include <asm/irq.h> | ||
| 17 | |||
| 18 | #define PIN_BASE NR_AIC_IRQS | ||
| 19 | |||
| 20 | #define MAX_GPIO_BANKS 5 | ||
| 21 | |||
| 22 | /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ | ||
| 23 | |||
| 24 | #define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) | ||
| 25 | #define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) | ||
| 26 | #define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) | ||
| 27 | #define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) | ||
| 28 | #define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) | ||
| 29 | #define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) | ||
| 30 | #define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) | ||
| 31 | #define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) | ||
| 32 | #define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) | ||
| 33 | #define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) | ||
| 34 | #define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) | ||
| 35 | #define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) | ||
| 36 | #define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) | ||
| 37 | #define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) | ||
| 38 | #define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) | ||
| 39 | #define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) | ||
| 40 | #define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) | ||
| 41 | #define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) | ||
| 42 | #define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) | ||
| 43 | #define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) | ||
| 44 | #define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) | ||
| 45 | #define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) | ||
| 46 | #define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) | ||
| 47 | #define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) | ||
| 48 | #define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) | ||
| 49 | #define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) | ||
| 50 | #define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) | ||
| 51 | #define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) | ||
| 52 | #define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) | ||
| 53 | #define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) | ||
| 54 | #define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) | ||
| 55 | #define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) | ||
| 56 | |||
| 57 | #define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) | ||
| 58 | #define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) | ||
| 59 | #define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) | ||
| 60 | #define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) | ||
| 61 | #define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) | ||
| 62 | #define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) | ||
| 63 | #define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) | ||
| 64 | #define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) | ||
| 65 | #define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) | ||
| 66 | #define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) | ||
| 67 | #define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) | ||
| 68 | #define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) | ||
| 69 | #define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) | ||
| 70 | #define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) | ||
| 71 | #define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) | ||
| 72 | #define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) | ||
| 73 | #define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) | ||
| 74 | #define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) | ||
| 75 | #define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) | ||
| 76 | #define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) | ||
| 77 | #define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) | ||
| 78 | #define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) | ||
| 79 | #define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) | ||
| 80 | #define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) | ||
| 81 | #define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) | ||
| 82 | #define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) | ||
| 83 | #define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) | ||
| 84 | #define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) | ||
| 85 | #define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) | ||
| 86 | #define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) | ||
| 87 | #define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) | ||
| 88 | #define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) | ||
| 89 | |||
| 90 | #define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) | ||
| 91 | #define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) | ||
| 92 | #define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) | ||
| 93 | #define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) | ||
| 94 | #define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) | ||
| 95 | #define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) | ||
| 96 | #define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) | ||
| 97 | #define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) | ||
| 98 | #define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) | ||
| 99 | #define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) | ||
| 100 | #define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) | ||
| 101 | #define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) | ||
| 102 | #define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) | ||
| 103 | #define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) | ||
| 104 | #define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) | ||
| 105 | #define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) | ||
| 106 | #define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) | ||
| 107 | #define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) | ||
| 108 | #define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) | ||
| 109 | #define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) | ||
| 110 | #define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) | ||
| 111 | #define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) | ||
| 112 | #define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) | ||
| 113 | #define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) | ||
| 114 | #define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) | ||
| 115 | #define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) | ||
| 116 | #define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) | ||
| 117 | #define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) | ||
| 118 | #define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) | ||
| 119 | #define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) | ||
| 120 | #define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) | ||
| 121 | #define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) | ||
| 122 | |||
| 123 | #define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) | ||
| 124 | #define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) | ||
| 125 | #define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) | ||
| 126 | #define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) | ||
| 127 | #define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) | ||
| 128 | #define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) | ||
| 129 | #define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) | ||
| 130 | #define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) | ||
| 131 | #define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) | ||
| 132 | #define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) | ||
| 133 | #define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) | ||
| 134 | #define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) | ||
| 135 | #define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) | ||
| 136 | #define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) | ||
| 137 | #define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) | ||
| 138 | #define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) | ||
| 139 | #define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) | ||
| 140 | #define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) | ||
| 141 | #define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) | ||
| 142 | #define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) | ||
| 143 | #define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) | ||
| 144 | #define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) | ||
| 145 | #define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) | ||
| 146 | #define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) | ||
| 147 | #define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) | ||
| 148 | #define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) | ||
| 149 | #define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) | ||
| 150 | #define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) | ||
| 151 | #define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) | ||
| 152 | #define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) | ||
| 153 | #define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) | ||
| 154 | #define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) | ||
| 155 | |||
| 156 | #define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) | ||
| 157 | #define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) | ||
| 158 | #define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) | ||
| 159 | #define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) | ||
| 160 | #define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) | ||
| 161 | #define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) | ||
| 162 | #define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) | ||
| 163 | #define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) | ||
| 164 | #define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) | ||
| 165 | #define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) | ||
| 166 | #define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) | ||
| 167 | #define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) | ||
| 168 | #define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) | ||
| 169 | #define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) | ||
| 170 | #define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) | ||
| 171 | #define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) | ||
| 172 | #define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) | ||
| 173 | #define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) | ||
| 174 | #define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) | ||
| 175 | #define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) | ||
| 176 | #define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) | ||
| 177 | #define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) | ||
| 178 | #define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) | ||
| 179 | #define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) | ||
| 180 | #define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) | ||
| 181 | #define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) | ||
| 182 | #define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) | ||
| 183 | #define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) | ||
| 184 | #define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) | ||
| 185 | #define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) | ||
| 186 | #define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) | ||
| 187 | #define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) | ||
| 188 | |||
| 189 | #ifndef __ASSEMBLY__ | ||
| 190 | /* setup setup routines, called from board init or driver probe() */ | ||
| 191 | extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup); | ||
| 192 | extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup); | ||
| 193 | extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup); | ||
| 194 | extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup); | ||
| 195 | extern int __init_or_module at91_set_gpio_output(unsigned pin, int value); | ||
| 196 | extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on); | ||
| 197 | extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on); | ||
| 198 | |||
| 199 | /* callable at any time */ | ||
| 200 | extern int at91_set_gpio_value(unsigned pin, int value); | ||
| 201 | extern int at91_get_gpio_value(unsigned pin); | ||
| 202 | |||
| 203 | /* callable only from core power-management code */ | ||
| 204 | extern void at91_gpio_suspend(void); | ||
| 205 | extern void at91_gpio_resume(void); | ||
| 206 | |||
| 207 | /*-------------------------------------------------------------------------*/ | ||
| 208 | |||
| 209 | /* wrappers for "new style" GPIO calls. the old AT91-specfic ones should | ||
| 210 | * eventually be removed (along with this errno.h inclusion), and the | ||
| 211 | * gpio request/free calls should probably be implemented. | ||
| 212 | */ | ||
| 213 | |||
| 214 | #include <asm/errno.h> | ||
| 215 | |||
| 216 | static inline int gpio_request(unsigned gpio, const char *label) | ||
| 217 | { | ||
| 218 | return 0; | ||
| 219 | } | ||
| 220 | |||
| 221 | static inline void gpio_free(unsigned gpio) | ||
| 222 | { | ||
| 223 | } | ||
| 224 | |||
| 225 | extern int gpio_direction_input(unsigned gpio); | ||
| 226 | extern int gpio_direction_output(unsigned gpio, int value); | ||
| 227 | |||
| 228 | static inline int gpio_get_value(unsigned gpio) | ||
| 229 | { | ||
| 230 | return at91_get_gpio_value(gpio); | ||
| 231 | } | ||
| 232 | |||
| 233 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 234 | { | ||
| 235 | at91_set_gpio_value(gpio, value); | ||
| 236 | } | ||
| 237 | |||
| 238 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
| 239 | |||
| 240 | static inline int gpio_to_irq(unsigned gpio) | ||
| 241 | { | ||
| 242 | return gpio; | ||
| 243 | } | ||
| 244 | |||
| 245 | static inline int irq_to_gpio(unsigned irq) | ||
| 246 | { | ||
| 247 | return irq; | ||
| 248 | } | ||
| 249 | |||
| 250 | #endif /* __ASSEMBLY__ */ | ||
| 251 | |||
| 252 | #endif | ||
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h deleted file mode 100644 index 016a3a3f6633..000000000000 --- a/include/asm-arm/arch-at91/hardware.h +++ /dev/null | |||
| @@ -1,92 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * Copyright (C) 2003 ATMEL | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 15 | #define __ASM_ARCH_HARDWARE_H | ||
| 16 | |||
| 17 | #include <asm/sizes.h> | ||
| 18 | |||
| 19 | #if defined(CONFIG_ARCH_AT91RM9200) | ||
| 20 | #include <asm/arch/at91rm9200.h> | ||
| 21 | #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) | ||
| 22 | #include <asm/arch/at91sam9260.h> | ||
| 23 | #elif defined(CONFIG_ARCH_AT91SAM9261) | ||
| 24 | #include <asm/arch/at91sam9261.h> | ||
| 25 | #elif defined(CONFIG_ARCH_AT91SAM9263) | ||
| 26 | #include <asm/arch/at91sam9263.h> | ||
| 27 | #elif defined(CONFIG_ARCH_AT91SAM9RL) | ||
| 28 | #include <asm/arch/at91sam9rl.h> | ||
| 29 | #elif defined(CONFIG_ARCH_AT91CAP9) | ||
| 30 | #include <asm/arch/at91cap9.h> | ||
| 31 | #elif defined(CONFIG_ARCH_AT91X40) | ||
| 32 | #include <asm/arch/at91x40.h> | ||
| 33 | #else | ||
| 34 | #error "Unsupported AT91 processor" | ||
| 35 | #endif | ||
| 36 | |||
| 37 | |||
| 38 | #ifdef CONFIG_MMU | ||
| 39 | /* | ||
| 40 | * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF | ||
| 41 | * to 0xFEF78000 .. 0xFF000000. (544Kb) | ||
| 42 | */ | ||
| 43 | #define AT91_IO_PHYS_BASE 0xFFF78000 | ||
| 44 | #define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) | ||
| 45 | #else | ||
| 46 | /* | ||
| 47 | * Identity mapping for the non MMU case. | ||
| 48 | */ | ||
| 49 | #define AT91_IO_PHYS_BASE AT91_BASE_SYS | ||
| 50 | #define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) | ||
| 54 | |||
| 55 | /* Convert a physical IO address to virtual IO address */ | ||
| 56 | #define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) | ||
| 57 | |||
| 58 | /* | ||
| 59 | * Virtual to Physical Address mapping for IO devices. | ||
| 60 | */ | ||
| 61 | #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) | ||
| 62 | #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) | ||
| 63 | |||
| 64 | /* Internal SRAM is mapped below the IO devices */ | ||
| 65 | #define AT91_SRAM_MAX SZ_1M | ||
| 66 | #define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX) | ||
| 67 | |||
| 68 | /* Serial ports */ | ||
| 69 | #define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */ | ||
| 70 | |||
| 71 | /* External Memory Map */ | ||
| 72 | #define AT91_CHIPSELECT_0 0x10000000 | ||
| 73 | #define AT91_CHIPSELECT_1 0x20000000 | ||
| 74 | #define AT91_CHIPSELECT_2 0x30000000 | ||
| 75 | #define AT91_CHIPSELECT_3 0x40000000 | ||
| 76 | #define AT91_CHIPSELECT_4 0x50000000 | ||
| 77 | #define AT91_CHIPSELECT_5 0x60000000 | ||
| 78 | #define AT91_CHIPSELECT_6 0x70000000 | ||
| 79 | #define AT91_CHIPSELECT_7 0x80000000 | ||
| 80 | |||
| 81 | /* SDRAM */ | ||
| 82 | #ifdef CONFIG_DRAM_BASE | ||
| 83 | #define AT91_SDRAM_BASE CONFIG_DRAM_BASE | ||
| 84 | #else | ||
| 85 | #define AT91_SDRAM_BASE AT91_CHIPSELECT_1 | ||
| 86 | #endif | ||
| 87 | |||
| 88 | /* Clocks */ | ||
| 89 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | ||
| 90 | |||
| 91 | |||
| 92 | #endif | ||
diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h deleted file mode 100644 index f8beaa228467..000000000000 --- a/include/asm-arm/arch-at91/io.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_IO_H | ||
| 22 | #define __ASM_ARCH_IO_H | ||
| 23 | |||
| 24 | #define IO_SPACE_LIMIT 0xFFFFFFFF | ||
| 25 | |||
| 26 | #define __io(a) ((void __iomem *)(a)) | ||
| 27 | #define __mem_pci(a) (a) | ||
| 28 | |||
| 29 | |||
| 30 | #ifndef __ASSEMBLY__ | ||
| 31 | |||
| 32 | static inline unsigned int at91_sys_read(unsigned int reg_offset) | ||
| 33 | { | ||
| 34 | void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; | ||
| 35 | |||
| 36 | return __raw_readl(addr + reg_offset); | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) | ||
| 40 | { | ||
| 41 | void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; | ||
| 42 | |||
| 43 | __raw_writel(value, addr + reg_offset); | ||
| 44 | } | ||
| 45 | |||
| 46 | #endif | ||
| 47 | |||
| 48 | #endif | ||
diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h deleted file mode 100644 index 70b1216dce5d..000000000000 --- a/include/asm-arm/arch-at91/irqs.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_IRQS_H | ||
| 22 | #define __ASM_ARCH_IRQS_H | ||
| 23 | |||
| 24 | #include <asm/io.h> | ||
| 25 | #include <asm/arch/at91_aic.h> | ||
| 26 | |||
| 27 | #define NR_AIC_IRQS 32 | ||
| 28 | |||
| 29 | |||
| 30 | /* | ||
| 31 | * Acknowledge interrupt with AIC after interrupt has been handled. | ||
| 32 | * (by kernel/irq.c) | ||
| 33 | */ | ||
| 34 | #define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0) | ||
| 35 | |||
| 36 | |||
| 37 | /* | ||
| 38 | * IRQ interrupt symbols are the AT91xxx_ID_* symbols | ||
| 39 | * for IRQs handled directly through the AIC, or else the AT91_PIN_* | ||
| 40 | * symbols in gpio.h for ones handled indirectly as GPIOs. | ||
| 41 | * We make provision for 5 banks of GPIO. | ||
| 42 | */ | ||
| 43 | #define NR_IRQS (NR_AIC_IRQS + (5 * 32)) | ||
| 44 | |||
| 45 | /* FIQ is AIC source 0. */ | ||
| 46 | #define FIQ_START AT91_ID_FIQ | ||
| 47 | |||
| 48 | #endif | ||
diff --git a/include/asm-arm/arch-at91/memory.h b/include/asm-arm/arch-at91/memory.h deleted file mode 100644 index 904fbd60f0e4..000000000000 --- a/include/asm-arm/arch-at91/memory.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 22 | #define __ASM_ARCH_MEMORY_H | ||
| 23 | |||
| 24 | #include <asm/arch/hardware.h> | ||
| 25 | |||
| 26 | #define PHYS_OFFSET (AT91_SDRAM_BASE) | ||
| 27 | |||
| 28 | |||
| 29 | /* | ||
| 30 | * Virtual view <-> DMA view memory address translations | ||
| 31 | * virt_to_bus: Used to translate the virtual address to an | ||
| 32 | * address suitable to be passed to set_dma_addr | ||
| 33 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 34 | * to an address that the kernel can use. | ||
| 35 | */ | ||
| 36 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 37 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-at91/system.h b/include/asm-arm/arch-at91/system.h deleted file mode 100644 index c5e3d0357263..000000000000 --- a/include/asm-arm/arch-at91/system.h +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 22 | #define __ASM_ARCH_SYSTEM_H | ||
| 23 | |||
| 24 | #include <asm/arch/hardware.h> | ||
| 25 | #include <asm/arch/at91_st.h> | ||
| 26 | #include <asm/arch/at91_dbgu.h> | ||
| 27 | |||
| 28 | static inline void arch_idle(void) | ||
| 29 | { | ||
| 30 | /* | ||
| 31 | * Disable the processor clock. The processor will be automatically | ||
| 32 | * re-enabled by an interrupt or by a reset. | ||
| 33 | */ | ||
| 34 | // at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Set the processor (CP15) into 'Wait for Interrupt' mode. | ||
| 38 | * Unlike disabling the processor clock via the PMC (above) | ||
| 39 | * this allows the processor to be woken via JTAG. | ||
| 40 | */ | ||
| 41 | cpu_do_idle(); | ||
| 42 | } | ||
| 43 | |||
| 44 | void (*at91_arch_reset)(void); | ||
| 45 | |||
| 46 | static inline void arch_reset(char mode) | ||
| 47 | { | ||
| 48 | /* call the CPU-specific reset function */ | ||
| 49 | if (at91_arch_reset) | ||
| 50 | (at91_arch_reset)(); | ||
| 51 | } | ||
| 52 | |||
| 53 | #endif | ||
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h deleted file mode 100644 index 67c86a89828f..000000000000 --- a/include/asm-arm/arch-at91/timex.h +++ /dev/null | |||
| @@ -1,77 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 22 | #define __ASM_ARCH_TIMEX_H | ||
| 23 | |||
| 24 | #include <asm/arch/hardware.h> | ||
| 25 | |||
| 26 | #if defined(CONFIG_ARCH_AT91RM9200) | ||
| 27 | |||
| 28 | #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) | ||
| 29 | |||
| 30 | #elif defined(CONFIG_ARCH_AT91SAM9260) | ||
| 31 | |||
| 32 | #if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260) | ||
| 33 | #define AT91SAM9_MASTER_CLOCK 90000000 | ||
| 34 | #else | ||
| 35 | #define AT91SAM9_MASTER_CLOCK 99300000 | ||
| 36 | #endif | ||
| 37 | |||
| 38 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 39 | |||
| 40 | #elif defined(CONFIG_ARCH_AT91SAM9261) | ||
| 41 | |||
| 42 | #define AT91SAM9_MASTER_CLOCK 99300000 | ||
| 43 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 44 | |||
| 45 | #elif defined(CONFIG_ARCH_AT91SAM9263) | ||
| 46 | |||
| 47 | #if defined(CONFIG_MACH_USB_A9263) | ||
| 48 | #define AT91SAM9_MASTER_CLOCK 90000000 | ||
| 49 | #else | ||
| 50 | #define AT91SAM9_MASTER_CLOCK 99959500 | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 54 | |||
| 55 | #elif defined(CONFIG_ARCH_AT91SAM9RL) | ||
| 56 | |||
| 57 | #define AT91SAM9_MASTER_CLOCK 100000000 | ||
| 58 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 59 | |||
| 60 | #elif defined(CONFIG_ARCH_AT91SAM9G20) | ||
| 61 | |||
| 62 | #define AT91SAM9_MASTER_CLOCK 132096000 | ||
| 63 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 64 | |||
| 65 | #elif defined(CONFIG_ARCH_AT91CAP9) | ||
| 66 | |||
| 67 | #define AT91CAP9_MASTER_CLOCK 100000000 | ||
| 68 | #define CLOCK_TICK_RATE (AT91CAP9_MASTER_CLOCK/16) | ||
| 69 | |||
| 70 | #elif defined(CONFIG_ARCH_AT91X40) | ||
| 71 | |||
| 72 | #define AT91X40_MASTER_CLOCK 40000000 | ||
| 73 | #define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) | ||
| 74 | |||
| 75 | #endif | ||
| 76 | |||
| 77 | #endif | ||
diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h deleted file mode 100644 index f5636a8f6132..000000000000 --- a/include/asm-arm/arch-at91/uncompress.h +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
| 22 | #define __ASM_ARCH_UNCOMPRESS_H | ||
| 23 | |||
| 24 | #include <asm/io.h> | ||
| 25 | #include <linux/atmel_serial.h> | ||
| 26 | |||
| 27 | #if defined(CONFIG_AT91_EARLY_DBGU) | ||
| 28 | #define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS) | ||
| 29 | #elif defined(CONFIG_AT91_EARLY_USART0) | ||
| 30 | #define UART_OFFSET AT91_USART0 | ||
| 31 | #elif defined(CONFIG_AT91_EARLY_USART1) | ||
| 32 | #define UART_OFFSET AT91_USART1 | ||
| 33 | #elif defined(CONFIG_AT91_EARLY_USART2) | ||
| 34 | #define UART_OFFSET AT91_USART2 | ||
| 35 | #elif defined(CONFIG_AT91_EARLY_USART3) | ||
| 36 | #define UART_OFFSET AT91_USART3 | ||
| 37 | #elif defined(CONFIG_AT91_EARLY_USART4) | ||
| 38 | #define UART_OFFSET AT91_USART4 | ||
| 39 | #elif defined(CONFIG_AT91_EARLY_USART5) | ||
| 40 | #define UART_OFFSET AT91_USART5 | ||
| 41 | #endif | ||
| 42 | |||
| 43 | /* | ||
| 44 | * The following code assumes the serial port has already been | ||
| 45 | * initialized by the bootloader. If you didn't setup a port in | ||
| 46 | * your bootloader then nothing will appear (which might be desired). | ||
| 47 | * | ||
| 48 | * This does not append a newline | ||
| 49 | */ | ||
| 50 | static void putc(int c) | ||
| 51 | { | ||
| 52 | #ifdef UART_OFFSET | ||
| 53 | void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ | ||
| 54 | |||
| 55 | while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY)) | ||
| 56 | barrier(); | ||
| 57 | __raw_writel(c, sys + ATMEL_US_THR); | ||
| 58 | #endif | ||
| 59 | } | ||
| 60 | |||
| 61 | static inline void flush(void) | ||
| 62 | { | ||
| 63 | #ifdef UART_OFFSET | ||
| 64 | void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ | ||
| 65 | |||
| 66 | /* wait for transmission to complete */ | ||
| 67 | while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) | ||
| 68 | barrier(); | ||
| 69 | #endif | ||
| 70 | } | ||
| 71 | |||
| 72 | #define arch_decomp_setup() | ||
| 73 | |||
| 74 | #define arch_decomp_wdog() | ||
| 75 | |||
| 76 | #endif | ||
diff --git a/include/asm-arm/arch-at91/vmalloc.h b/include/asm-arm/arch-at91/vmalloc.h deleted file mode 100644 index bb05e70e932a..000000000000 --- a/include/asm-arm/arch-at91/vmalloc.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_VMALLOC_H | ||
| 22 | #define __ASM_ARCH_VMALLOC_H | ||
| 23 | |||
| 24 | #define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK) | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-arm/arch-cl7500/acornfb.h b/include/asm-arm/arch-cl7500/acornfb.h deleted file mode 100644 index aea6330c9745..000000000000 --- a/include/asm-arm/arch-cl7500/acornfb.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | #define acornfb_valid_pixrate(var) (var->pixclock >= 39325 && var->pixclock <= 40119) | ||
| 2 | |||
| 3 | static inline void | ||
| 4 | acornfb_vidc20_find_rates(struct vidc_timing *vidc, | ||
| 5 | struct fb_var_screeninfo *var) | ||
| 6 | { | ||
| 7 | u_int bandwidth; | ||
| 8 | |||
| 9 | vidc->control |= VIDC20_CTRL_PIX_CK; | ||
| 10 | |||
| 11 | /* Calculate bandwidth */ | ||
| 12 | bandwidth = var->pixclock * 8 / var->bits_per_pixel; | ||
| 13 | |||
| 14 | /* Encode bandwidth as VIDC20 setting */ | ||
| 15 | if (bandwidth > 16667*2) | ||
| 16 | vidc->control |= VIDC20_CTRL_FIFO_16; | ||
| 17 | else if (bandwidth > 13333*2) | ||
| 18 | vidc->control |= VIDC20_CTRL_FIFO_20; | ||
| 19 | else if (bandwidth > 11111*2) | ||
| 20 | vidc->control |= VIDC20_CTRL_FIFO_24; | ||
| 21 | else | ||
| 22 | vidc->control |= VIDC20_CTRL_FIFO_28; | ||
| 23 | |||
| 24 | vidc->pll_ctl = 0x2020; | ||
| 25 | } | ||
| 26 | |||
| 27 | #ifdef CONFIG_CHRONTEL_7003 | ||
| 28 | #define acornfb_default_control() VIDC20_CTRL_PIX_HCLK | ||
| 29 | #else | ||
| 30 | #define acornfb_default_control() VIDC20_CTRL_PIX_VCLK | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #define acornfb_default_econtrol() VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3) | VIDC20_ECTL_ECK | ||
diff --git a/include/asm-arm/arch-cl7500/debug-macro.S b/include/asm-arm/arch-cl7500/debug-macro.S deleted file mode 100644 index 9a2b67d24098..000000000000 --- a/include/asm-arm/arch-cl7500/debug-macro.S +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-cl7500/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mov \rx, #0xe0000000 | ||
| 16 | orr \rx, \rx, #0x00010000 | ||
| 17 | orr \rx, \rx, #0x00000be0 | ||
| 18 | .endm | ||
| 19 | |||
| 20 | #define UART_SHIFT 2 | ||
| 21 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-cl7500/dma.h b/include/asm-arm/arch-cl7500/dma.h deleted file mode 100644 index 591ed2551892..000000000000 --- a/include/asm-arm/arch-cl7500/dma.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-cl7500/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 Nexus Electronics Ltd. | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __ASM_ARCH_DMA_H | ||
| 8 | #define __ASM_ARCH_DMA_H | ||
| 9 | |||
| 10 | /* DMA is not yet implemented! It should be the same as acorn, copy over.. */ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * This is the maximum DMA address that can be DMAd to. | ||
| 14 | * There should not be more than (0xd0000000 - 0xc0000000) | ||
| 15 | * bytes of RAM. | ||
| 16 | */ | ||
| 17 | #define MAX_DMA_ADDRESS 0xd0000000 | ||
| 18 | |||
| 19 | #define DMA_S0 0 | ||
| 20 | |||
| 21 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-cl7500/entry-macro.S b/include/asm-arm/arch-cl7500/entry-macro.S deleted file mode 100644 index 5bd55557ccca..000000000000 --- a/include/asm-arm/arch-cl7500/entry-macro.S +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | #include <asm/arch/hardware.h> | ||
| 2 | #include <asm/hardware/entry-macro-iomd.S> | ||
| 3 | |||
| 4 | .equ ioc_base_high, IOC_BASE & 0xff000000 | ||
| 5 | .equ ioc_base_low, IOC_BASE & 0x00ff0000 | ||
| 6 | |||
| 7 | .macro get_irqnr_preamble, base, tmp | ||
| 8 | mov \base, #ioc_base_high @ point at IOC | ||
| 9 | .if ioc_base_low | ||
| 10 | orr \base, \base, #ioc_base_low | ||
| 11 | .endif | ||
| 12 | .endm | ||
| 13 | |||
| 14 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 15 | .endm | ||
| 16 | |||
diff --git a/include/asm-arm/arch-cl7500/hardware.h b/include/asm-arm/arch-cl7500/hardware.h deleted file mode 100644 index 1adfd18e6154..000000000000 --- a/include/asm-arm/arch-cl7500/hardware.h +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-cl7500/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996-1999 Russell King. | ||
| 5 | * Copyright (C) 1999 Nexus Electronics Ltd. | ||
| 6 | * | ||
| 7 | * This file contains the hardware definitions of the | ||
| 8 | * CL7500 evaluation board. | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 11 | #define __ASM_ARCH_HARDWARE_H | ||
| 12 | |||
| 13 | #include <asm/arch/memory.h> | ||
| 14 | #include <asm/hardware/iomd.h> | ||
| 15 | |||
| 16 | #ifdef __ASSEMBLY__ | ||
| 17 | #define IOMEM(x) x | ||
| 18 | #else | ||
| 19 | #define IOMEM(x) ((void __iomem *)(x)) | ||
| 20 | #endif | ||
| 21 | |||
| 22 | /* | ||
| 23 | * What hardware must be present | ||
| 24 | */ | ||
| 25 | #define HAS_IOMD | ||
| 26 | #define HAS_VIDC20 | ||
| 27 | |||
| 28 | /* Hardware addresses of major areas. | ||
| 29 | * *_START is the physical address | ||
| 30 | * *_SIZE is the size of the region | ||
| 31 | * *_BASE is the virtual address | ||
| 32 | */ | ||
| 33 | |||
| 34 | #define IO_START 0x03000000 /* I/O */ | ||
| 35 | #define IO_SIZE 0x01000000 | ||
| 36 | #define IO_BASE IOMEM(0xe0000000) | ||
| 37 | |||
| 38 | #define ISA_START 0x0c000000 /* ISA */ | ||
| 39 | #define ISA_SIZE 0x00010000 | ||
| 40 | #define ISA_BASE 0xe1000000 | ||
| 41 | |||
| 42 | #define FLASH_START 0x01000000 /* XXX */ | ||
| 43 | #define FLASH_SIZE 0x01000000 | ||
| 44 | #define FLASH_BASE 0xe2000000 | ||
| 45 | |||
| 46 | #define LED_START 0x0302B000 | ||
| 47 | #define LED_SIZE 0x00001000 | ||
| 48 | #define LED_BASE 0xe3000000 | ||
| 49 | #define LED_ADDRESS (LED_BASE + 0xa00) | ||
| 50 | |||
| 51 | /* Let's define SCREEN_START for CL7500, even though it's a lie. */ | ||
| 52 | #define SCREEN_START 0x02000000 /* VRAM */ | ||
| 53 | #define SCREEN_END 0xdfc00000 | ||
| 54 | #define SCREEN_BASE 0xdf800000 | ||
| 55 | |||
| 56 | #define VIDC_BASE (void __iomem *)0xe0400000 | ||
| 57 | #define IOMD_BASE IOMEM(0xe0200000) | ||
| 58 | #define IOC_BASE IOMEM(0xe0200000) | ||
| 59 | #define FLOPPYDMA_BASE IOMEM(0xe002a000) | ||
| 60 | #define PCIO_BASE IOMEM(0xe0010000) | ||
| 61 | |||
| 62 | #define vidc_writel(val) __raw_writel(val, VIDC_BASE) | ||
| 63 | |||
| 64 | /* in/out bias for the ISA slot region */ | ||
| 65 | #define ISASLOT_IO 0x80400000 | ||
| 66 | |||
| 67 | #endif | ||
diff --git a/include/asm-arm/arch-cl7500/io.h b/include/asm-arm/arch-cl7500/io.h deleted file mode 100644 index 80f9b19cac9e..000000000000 --- a/include/asm-arm/arch-cl7500/io.h +++ /dev/null | |||
| @@ -1,255 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-cl7500/io.h | ||
| 3 | * from linux/include/asm-arm/arch-rpc/io.h | ||
| 4 | * | ||
| 5 | * Copyright (C) 1997 Russell King | ||
| 6 | * | ||
| 7 | * Modifications: | ||
| 8 | * 06-Dec-1997 RMK Created. | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 11 | #define __ASM_ARM_ARCH_IO_H | ||
| 12 | |||
| 13 | #include <asm/arch/hardware.h> | ||
| 14 | |||
| 15 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 16 | |||
| 17 | /* | ||
| 18 | * GCC is totally crap at loading/storing data. We try to persuade it | ||
| 19 | * to do the right thing by using these whereever possible instead of | ||
| 20 | * the above. | ||
| 21 | */ | ||
| 22 | #define __arch_base_getb(b,o) \ | ||
| 23 | ({ \ | ||
| 24 | unsigned int v, r = (b); \ | ||
| 25 | __asm__ __volatile__( \ | ||
| 26 | "ldrb %0, [%1, %2]" \ | ||
| 27 | : "=r" (v) \ | ||
| 28 | : "r" (r), "Ir" (o)); \ | ||
| 29 | v; \ | ||
| 30 | }) | ||
| 31 | |||
| 32 | #define __arch_base_getl(b,o) \ | ||
| 33 | ({ \ | ||
| 34 | unsigned int v, r = (b); \ | ||
| 35 | __asm__ __volatile__( \ | ||
| 36 | "ldr %0, [%1, %2]" \ | ||
| 37 | : "=r" (v) \ | ||
| 38 | : "r" (r), "Ir" (o)); \ | ||
| 39 | v; \ | ||
| 40 | }) | ||
| 41 | |||
| 42 | #define __arch_base_putb(v,b,o) \ | ||
| 43 | ({ \ | ||
| 44 | unsigned int r = (b); \ | ||
| 45 | __asm__ __volatile__( \ | ||
| 46 | "strb %0, [%1, %2]" \ | ||
| 47 | : \ | ||
| 48 | : "r" (v), "r" (r), "Ir" (o)); \ | ||
| 49 | }) | ||
| 50 | |||
| 51 | #define __arch_base_putl(v,b,o) \ | ||
| 52 | ({ \ | ||
| 53 | unsigned int r = (b); \ | ||
| 54 | __asm__ __volatile__( \ | ||
| 55 | "str %0, [%1, %2]" \ | ||
| 56 | : \ | ||
| 57 | : "r" (v), "r" (r), "Ir" (o)); \ | ||
| 58 | }) | ||
| 59 | |||
| 60 | /* | ||
| 61 | * We use two different types of addressing - PC style addresses, and ARM | ||
| 62 | * addresses. PC style accesses the PC hardware with the normal PC IO | ||
| 63 | * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ | ||
| 64 | * and are translated to the start of IO. Note that all addresses are | ||
| 65 | * shifted left! | ||
| 66 | */ | ||
| 67 | #define __PORT_PCIO(x) (!((x) & 0x80000000)) | ||
| 68 | |||
| 69 | /* | ||
| 70 | * Dynamic IO functions - let the compiler | ||
| 71 | * optimize the expressions | ||
| 72 | */ | ||
| 73 | static inline void __outb (unsigned int value, unsigned int port) | ||
| 74 | { | ||
| 75 | unsigned long temp; | ||
| 76 | __asm__ __volatile__( | ||
| 77 | "tst %2, #0x80000000\n\t" | ||
| 78 | "mov %0, %4\n\t" | ||
| 79 | "addeq %0, %0, %3\n\t" | ||
| 80 | "strb %1, [%0, %2, lsl #2] @ outb" | ||
| 81 | : "=&r" (temp) | ||
| 82 | : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) | ||
| 83 | : "cc"); | ||
| 84 | } | ||
| 85 | |||
| 86 | static inline void __outw (unsigned int value, unsigned int port) | ||
| 87 | { | ||
| 88 | unsigned long temp; | ||
| 89 | __asm__ __volatile__( | ||
| 90 | "tst %2, #0x80000000\n\t" | ||
| 91 | "mov %0, %4\n\t" | ||
| 92 | "addeq %0, %0, %3\n\t" | ||
| 93 | "str %1, [%0, %2, lsl #2] @ outw" | ||
| 94 | : "=&r" (temp) | ||
| 95 | : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) | ||
| 96 | : "cc"); | ||
| 97 | } | ||
| 98 | |||
| 99 | static inline void __outl (unsigned int value, unsigned int port) | ||
| 100 | { | ||
| 101 | unsigned long temp; | ||
| 102 | __asm__ __volatile__( | ||
| 103 | "tst %2, #0x80000000\n\t" | ||
| 104 | "mov %0, %4\n\t" | ||
| 105 | "addeq %0, %0, %3\n\t" | ||
| 106 | "str %1, [%0, %2, lsl #2] @ outl" | ||
| 107 | : "=&r" (temp) | ||
| 108 | : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) | ||
| 109 | : "cc"); | ||
| 110 | } | ||
| 111 | |||
| 112 | #define DECLARE_DYN_IN(sz,fnsuffix,instr) \ | ||
| 113 | static inline unsigned sz __in##fnsuffix (unsigned int port) \ | ||
| 114 | { \ | ||
| 115 | unsigned long temp, value; \ | ||
| 116 | __asm__ __volatile__( \ | ||
| 117 | "tst %2, #0x80000000\n\t" \ | ||
| 118 | "mov %0, %4\n\t" \ | ||
| 119 | "addeq %0, %0, %3\n\t" \ | ||
| 120 | "ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \ | ||
| 121 | : "=&r" (temp), "=r" (value) \ | ||
| 122 | : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \ | ||
| 123 | : "cc"); \ | ||
| 124 | return (unsigned sz)value; \ | ||
| 125 | } | ||
| 126 | |||
| 127 | static inline unsigned int __ioaddr (unsigned int port) \ | ||
| 128 | { \ | ||
| 129 | if (__PORT_PCIO(port)) \ | ||
| 130 | return (unsigned int)(PCIO_BASE + (port << 2)); \ | ||
| 131 | else \ | ||
| 132 | return (unsigned int)(IO_BASE + (port << 2)); \ | ||
| 133 | } | ||
| 134 | |||
| 135 | #define DECLARE_IO(sz,fnsuffix,instr) \ | ||
| 136 | DECLARE_DYN_IN(sz,fnsuffix,instr) | ||
| 137 | |||
| 138 | DECLARE_IO(char,b,"b") | ||
| 139 | DECLARE_IO(short,w,"") | ||
| 140 | DECLARE_IO(int,l,"") | ||
| 141 | |||
| 142 | #undef DECLARE_IO | ||
| 143 | #undef DECLARE_DYN_IN | ||
| 144 | |||
| 145 | /* | ||
| 146 | * Constant address IO functions | ||
| 147 | * | ||
| 148 | * These have to be macros for the 'J' constraint to work - | ||
| 149 | * +/-4096 immediate operand. | ||
| 150 | */ | ||
| 151 | #define __outbc(value,port) \ | ||
| 152 | ({ \ | ||
| 153 | if (__PORT_PCIO((port))) \ | ||
| 154 | __asm__ __volatile__( \ | ||
| 155 | "strb %0, [%1, %2] @ outbc" \ | ||
| 156 | : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 157 | else \ | ||
| 158 | __asm__ __volatile__( \ | ||
| 159 | "strb %0, [%1, %2] @ outbc" \ | ||
| 160 | : : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 161 | }) | ||
| 162 | |||
| 163 | #define __inbc(port) \ | ||
| 164 | ({ \ | ||
| 165 | unsigned char result; \ | ||
| 166 | if (__PORT_PCIO((port))) \ | ||
| 167 | __asm__ __volatile__( \ | ||
| 168 | "ldrb %0, [%1, %2] @ inbc" \ | ||
| 169 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 170 | else \ | ||
| 171 | __asm__ __volatile__( \ | ||
| 172 | "ldrb %0, [%1, %2] @ inbc" \ | ||
| 173 | : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 174 | result; \ | ||
| 175 | }) | ||
| 176 | |||
| 177 | #define __outwc(value,port) \ | ||
| 178 | ({ \ | ||
| 179 | unsigned long v = value; \ | ||
| 180 | if (__PORT_PCIO((port))) \ | ||
| 181 | __asm__ __volatile__( \ | ||
| 182 | "str %0, [%1, %2] @ outwc" \ | ||
| 183 | : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 184 | else \ | ||
| 185 | __asm__ __volatile__( \ | ||
| 186 | "str %0, [%1, %2] @ outwc" \ | ||
| 187 | : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 188 | }) | ||
| 189 | |||
| 190 | #define __inwc(port) \ | ||
| 191 | ({ \ | ||
| 192 | unsigned short result; \ | ||
| 193 | if (__PORT_PCIO((port))) \ | ||
| 194 | __asm__ __volatile__( \ | ||
| 195 | "ldr %0, [%1, %2] @ inwc" \ | ||
| 196 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 197 | else \ | ||
| 198 | __asm__ __volatile__( \ | ||
| 199 | "ldr %0, [%1, %2] @ inwc" \ | ||
| 200 | : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 201 | result & 0xffff; \ | ||
| 202 | }) | ||
| 203 | |||
| 204 | #define __outlc(value,port) \ | ||
| 205 | ({ \ | ||
| 206 | unsigned long v = value; \ | ||
| 207 | if (__PORT_PCIO((port))) \ | ||
| 208 | __asm__ __volatile__( \ | ||
| 209 | "str %0, [%1, %2] @ outlc" \ | ||
| 210 | : : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 211 | else \ | ||
| 212 | __asm__ __volatile__( \ | ||
| 213 | "str %0, [%1, %2] @ outlc" \ | ||
| 214 | : : "r" (v), "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 215 | }) | ||
| 216 | |||
| 217 | #define __inlc(port) \ | ||
| 218 | ({ \ | ||
| 219 | unsigned long result; \ | ||
| 220 | if (__PORT_PCIO((port))) \ | ||
| 221 | __asm__ __volatile__( \ | ||
| 222 | "ldr %0, [%1, %2] @ inlc" \ | ||
| 223 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 224 | else \ | ||
| 225 | __asm__ __volatile__( \ | ||
| 226 | "ldr %0, [%1, %2] @ inlc" \ | ||
| 227 | : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 228 | result; \ | ||
| 229 | }) | ||
| 230 | |||
| 231 | #define __ioaddrc(port) \ | ||
| 232 | (__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2)) | ||
| 233 | |||
| 234 | #define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) | ||
| 235 | #define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) | ||
| 236 | #define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) | ||
| 237 | #define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) | ||
| 238 | #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) | ||
| 239 | #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) | ||
| 240 | #define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) | ||
| 241 | /* the following macro is deprecated */ | ||
| 242 | #define ioaddr(port) __ioaddr((port)) | ||
| 243 | |||
| 244 | #define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) | ||
| 245 | #define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) | ||
| 246 | |||
| 247 | #define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) | ||
| 248 | #define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) | ||
| 249 | |||
| 250 | /* | ||
| 251 | * 1:1 mapping for ioremapped regions. | ||
| 252 | */ | ||
| 253 | #define __mem_pci(x) (x) | ||
| 254 | |||
| 255 | #endif | ||
diff --git a/include/asm-arm/arch-cl7500/irq.h b/include/asm-arm/arch-cl7500/irq.h deleted file mode 100644 index 4b286331f3f8..000000000000 --- a/include/asm-arm/arch-cl7500/irq.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-cl7500/irq.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996 Russell King | ||
| 5 | * Copyright (C) 1999, 2001 Nexus Electronics Ltd. | ||
| 6 | * | ||
| 7 | * Changelog: | ||
| 8 | * 10-10-1996 RMK Brought up to date with arch-sa110eval | ||
| 9 | * 22-08-1998 RMK Restructured IRQ routines | ||
| 10 | * 11-08-1999 PJB Created ARM7500 version, derived from RiscPC code | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <asm/hardware/iomd.h> | ||
| 14 | #include <asm/io.h> | ||
| 15 | |||
| 16 | static inline int fixup_irq(unsigned int irq) | ||
| 17 | { | ||
| 18 | if (irq == IRQ_ISA) { | ||
| 19 | int isabits = *((volatile unsigned int *)0xe002b700); | ||
| 20 | if (isabits == 0) { | ||
| 21 | printk("Spurious ISA IRQ!\n"); | ||
| 22 | return irq; | ||
| 23 | } | ||
| 24 | irq = IRQ_ISA_BASE; | ||
| 25 | while (!(isabits & 1)) { | ||
| 26 | irq++; | ||
| 27 | isabits >>= 1; | ||
| 28 | } | ||
| 29 | } | ||
| 30 | |||
| 31 | return irq; | ||
| 32 | } | ||
diff --git a/include/asm-arm/arch-cl7500/irqs.h b/include/asm-arm/arch-cl7500/irqs.h deleted file mode 100644 index f20996eadf19..000000000000 --- a/include/asm-arm/arch-cl7500/irqs.h +++ /dev/null | |||
| @@ -1,66 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-cl7500/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 Nexus Electronics Ltd | ||
| 5 | */ | ||
| 6 | |||
| 7 | #define IRQ_INT2 0 | ||
| 8 | #define IRQ_INT1 2 | ||
| 9 | #define IRQ_VSYNCPULSE 3 | ||
| 10 | #define IRQ_POWERON 4 | ||
| 11 | #define IRQ_TIMER0 5 | ||
| 12 | #define IRQ_TIMER1 6 | ||
| 13 | #define IRQ_FORCE 7 | ||
| 14 | #define IRQ_INT8 8 | ||
| 15 | #define IRQ_ISA 9 | ||
| 16 | #define IRQ_INT6 10 | ||
| 17 | #define IRQ_INT5 11 | ||
| 18 | #define IRQ_INT4 12 | ||
| 19 | #define IRQ_INT3 13 | ||
| 20 | #define IRQ_KEYBOARDTX 14 | ||
| 21 | #define IRQ_KEYBOARDRX 15 | ||
| 22 | |||
| 23 | #define IRQ_DMA0 16 | ||
| 24 | #define IRQ_DMA1 17 | ||
| 25 | #define IRQ_DMA2 18 | ||
| 26 | #define IRQ_DMA3 19 | ||
| 27 | #define IRQ_DMAS0 20 | ||
| 28 | #define IRQ_DMAS1 21 | ||
| 29 | |||
| 30 | #define IRQ_IOP0 24 | ||
| 31 | #define IRQ_IOP1 25 | ||
| 32 | #define IRQ_IOP2 26 | ||
| 33 | #define IRQ_IOP3 27 | ||
| 34 | #define IRQ_IOP4 28 | ||
| 35 | #define IRQ_IOP5 29 | ||
| 36 | #define IRQ_IOP6 30 | ||
| 37 | #define IRQ_IOP7 31 | ||
| 38 | |||
| 39 | #define IRQ_MOUSERX 40 | ||
| 40 | #define IRQ_MOUSETX 41 | ||
| 41 | #define IRQ_ADC 42 | ||
| 42 | #define IRQ_EVENT1 43 | ||
| 43 | #define IRQ_EVENT2 44 | ||
| 44 | |||
| 45 | #define IRQ_ISA_BASE 48 | ||
| 46 | #define IRQ_ISA_3 48 | ||
| 47 | #define IRQ_ISA_4 49 | ||
| 48 | #define IRQ_ISA_5 50 | ||
| 49 | #define IRQ_ISA_7 51 | ||
| 50 | #define IRQ_ISA_9 52 | ||
| 51 | #define IRQ_ISA_10 53 | ||
| 52 | #define IRQ_ISA_11 54 | ||
| 53 | #define IRQ_ISA_14 55 | ||
| 54 | |||
| 55 | #define FIQ_INT9 0 | ||
| 56 | #define FIQ_INT5 1 | ||
| 57 | #define FIQ_INT6 4 | ||
| 58 | #define FIQ_INT8 6 | ||
| 59 | #define FIQ_FORCE 7 | ||
| 60 | |||
| 61 | /* | ||
| 62 | * This is the offset of the FIQ "IRQ" numbers | ||
| 63 | */ | ||
| 64 | #define FIQ_START 64 | ||
| 65 | |||
| 66 | #define IRQ_TIMER IRQ_TIMER0 | ||
diff --git a/include/asm-arm/arch-cl7500/memory.h b/include/asm-arm/arch-cl7500/memory.h deleted file mode 100644 index 3178140e24ca..000000000000 --- a/include/asm-arm/arch-cl7500/memory.h +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-cl7500/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 1996,1997,1998 Russell King. | ||
| 5 | * | ||
| 6 | * Changelog: | ||
| 7 | * 20-Oct-1996 RMK Created | ||
| 8 | * 31-Dec-1997 RMK Fixed definitions to reduce warnings | ||
| 9 | * 11-Jan-1998 RMK Uninlined to reduce hits on cache | ||
| 10 | * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt | ||
| 11 | * 21-Mar-1999 RMK Renamed to memory.h | ||
| 12 | * RMK Added TASK_SIZE and PAGE_OFFSET | ||
| 13 | */ | ||
| 14 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 15 | #define __ASM_ARCH_MEMORY_H | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Physical DRAM offset. | ||
| 19 | */ | ||
| 20 | #define PHYS_OFFSET UL(0x10000000) | ||
| 21 | |||
| 22 | /* | ||
| 23 | * These are exactly the same on the RiscPC as the | ||
| 24 | * physical memory view. | ||
| 25 | */ | ||
| 26 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 27 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 28 | |||
| 29 | /* | ||
| 30 | * Cache flushing area - ROM | ||
| 31 | */ | ||
| 32 | #define FLUSH_BASE_PHYS 0x00000000 | ||
| 33 | #define FLUSH_BASE 0xdf000000 | ||
| 34 | |||
| 35 | #endif | ||
diff --git a/include/asm-arm/arch-cl7500/system.h b/include/asm-arm/arch-cl7500/system.h deleted file mode 100644 index a9505d6a74d7..000000000000 --- a/include/asm-arm/arch-cl7500/system.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-cl7500/system.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 1999 Nexus Electronics Ltd. | ||
| 5 | */ | ||
| 6 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 7 | #define __ASM_ARCH_SYSTEM_H | ||
| 8 | |||
| 9 | #include <asm/hardware/iomd.h> | ||
| 10 | #include <asm/io.h> | ||
| 11 | |||
| 12 | static inline void arch_idle(void) | ||
| 13 | { | ||
| 14 | iomd_writeb(0, IOMD_SUSMODE); | ||
| 15 | } | ||
| 16 | |||
| 17 | #define arch_reset(mode) \ | ||
| 18 | do { \ | ||
| 19 | iomd_writeb(0, IOMD_ROMCR0); \ | ||
| 20 | cpu_reset(0); \ | ||
| 21 | } while (0) | ||
| 22 | |||
| 23 | #endif | ||
diff --git a/include/asm-arm/arch-cl7500/timex.h b/include/asm-arm/arch-cl7500/timex.h deleted file mode 100644 index 8a4175fc0106..000000000000 --- a/include/asm-arm/arch-cl7500/timex.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-cl7500/timex.h | ||
| 3 | * | ||
| 4 | * CL7500 architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 1999 Nexus Electronics Ltd | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * On the ARM7500, the clock ticks at 2MHz. | ||
| 11 | */ | ||
| 12 | #define CLOCK_TICK_RATE 2000000 | ||
| 13 | |||
diff --git a/include/asm-arm/arch-cl7500/uncompress.h b/include/asm-arm/arch-cl7500/uncompress.h deleted file mode 100644 index c437e0c88c3f..000000000000 --- a/include/asm-arm/arch-cl7500/uncompress.h +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-cl7500/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999, 2000 Nexus Electronics Ltd. | ||
| 5 | */ | ||
| 6 | #define BASE 0x03010000 | ||
| 7 | #define SERBASE (BASE + (0x2f8 << 2)) | ||
| 8 | |||
| 9 | static inline void putc(char c) | ||
| 10 | { | ||
| 11 | while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20)) | ||
| 12 | barrier(); | ||
| 13 | |||
| 14 | *((volatile unsigned int *)(SERBASE)) = c; | ||
| 15 | } | ||
| 16 | |||
| 17 | static inline void flush(void) | ||
| 18 | { | ||
| 19 | } | ||
| 20 | |||
| 21 | static __inline__ void arch_decomp_setup(void) | ||
| 22 | { | ||
| 23 | int baud = 3686400 / (9600 * 32); | ||
| 24 | |||
| 25 | *((volatile unsigned int *)(SERBASE + 0xC)) = 0x80; | ||
| 26 | *((volatile unsigned int *)(SERBASE + 0x0)) = baud & 0xff; | ||
| 27 | *((volatile unsigned int *)(SERBASE + 0x4)) = (baud & 0xff00) >> 8; | ||
| 28 | *((volatile unsigned int *)(SERBASE + 0xC)) = 3; /* 8 bits */ | ||
| 29 | *((volatile unsigned int *)(SERBASE + 0x10)) = 3; /* DTR, RTS */ | ||
| 30 | } | ||
| 31 | |||
| 32 | /* | ||
| 33 | * nothing to do | ||
| 34 | */ | ||
| 35 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-cl7500/vmalloc.h b/include/asm-arm/arch-cl7500/vmalloc.h deleted file mode 100644 index ba8d7a84456a..000000000000 --- a/include/asm-arm/arch-cl7500/vmalloc.h +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-cl7500/vmalloc.h | ||
| 3 | */ | ||
| 4 | #define VMALLOC_END (PAGE_OFFSET + 0x1c000000) | ||
diff --git a/include/asm-arm/arch-clps711x/autcpu12.h b/include/asm-arm/arch-clps711x/autcpu12.h deleted file mode 100644 index 1588a365f610..000000000000 --- a/include/asm-arm/arch-clps711x/autcpu12.h +++ /dev/null | |||
| @@ -1,78 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * AUTCPU12 specific defines | ||
| 3 | * | ||
| 4 | * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_AUTCPU12_H | ||
| 21 | #define __ASM_ARCH_AUTCPU12_H | ||
| 22 | |||
| 23 | /* | ||
| 24 | * The CS8900A ethernet chip has its I/O registers wired to chip select 2 | ||
| 25 | * (nCS2). This is the mapping for it. | ||
| 26 | */ | ||
| 27 | #define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE /* physical */ | ||
| 28 | #define AUTCPU12_VIRT_CS8900A (0xfe000000) /* virtual */ | ||
| 29 | |||
| 30 | /* | ||
| 31 | * The flash bank is wired to chip select 0 | ||
| 32 | */ | ||
| 33 | #define AUTCPU12_PHYS_FLASH CS0_PHYS_BASE /* physical */ | ||
| 34 | |||
| 35 | /* offset for device specific information structure */ | ||
| 36 | #define AUTCPU12_LCDINFO_OFFS (0x00010000) | ||
| 37 | /* | ||
| 38 | * Videomemory is the internal SRAM (CS 6) | ||
| 39 | */ | ||
| 40 | #define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE | ||
| 41 | #define AUTCPU12_VIRT_VIDEO (0xfd000000) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * All special IO's are tied to CS1 | ||
| 45 | */ | ||
| 46 | #define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */ | ||
| 47 | |||
| 48 | #define AUTCPU12_PHYS_NVRAM CS1_PHYS_BASE +0x02000000 /* physical */ | ||
| 49 | |||
| 50 | #define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */ | ||
| 51 | |||
| 52 | #define AUTCPU12_PHYS_SMC CS1_PHYS_BASE +0x06000000 /* physical */ | ||
| 53 | |||
| 54 | #define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */ | ||
| 55 | |||
| 56 | #define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */ | ||
| 57 | |||
| 58 | #define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */ | ||
| 59 | |||
| 60 | #define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */ | ||
| 61 | |||
| 62 | /* | ||
| 63 | * defines for smartmedia card access | ||
| 64 | */ | ||
| 65 | #define AUTCPU12_SMC_RDY (1<<2) | ||
| 66 | #define AUTCPU12_SMC_ALE (1<<3) | ||
| 67 | #define AUTCPU12_SMC_CLE (1<<4) | ||
| 68 | #define AUTCPU12_SMC_PORT_OFFSET PBDR | ||
| 69 | #define AUTCPU12_SMC_SELECT_OFFSET 0x10 | ||
| 70 | /* | ||
| 71 | * defines for lcd contrast | ||
| 72 | */ | ||
| 73 | #define AUTCPU12_DPOT_PORT_OFFSET PEDR | ||
| 74 | #define AUTCPU12_DPOT_CS (1<<0) | ||
| 75 | #define AUTCPU12_DPOT_CLK (1<<1) | ||
| 76 | #define AUTCPU12_DPOT_UD (1<<2) | ||
| 77 | |||
| 78 | #endif | ||
diff --git a/include/asm-arm/arch-clps711x/debug-macro.S b/include/asm-arm/arch-clps711x/debug-macro.S deleted file mode 100644 index bc0a5760722b..000000000000 --- a/include/asm-arm/arch-clps711x/debug-macro.S +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-clps711x/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <asm/hardware/clps7111.h> | ||
| 15 | |||
| 16 | .macro addruart,rx | ||
| 17 | mrc p15, 0, \rx, c1, c0 | ||
| 18 | tst \rx, #1 @ MMU enabled? | ||
| 19 | moveq \rx, #CLPS7111_PHYS_BASE | ||
| 20 | movne \rx, #CLPS7111_VIRT_BASE | ||
| 21 | #ifndef CONFIG_DEBUG_CLPS711X_UART2 | ||
| 22 | add \rx, \rx, #0x0000 @ UART1 | ||
| 23 | #else | ||
| 24 | add \rx, \rx, #0x1000 @ UART2 | ||
| 25 | #endif | ||
| 26 | .endm | ||
| 27 | |||
| 28 | .macro senduart,rd,rx | ||
| 29 | str \rd, [\rx, #0x0480] @ UARTDR | ||
| 30 | .endm | ||
| 31 | |||
| 32 | .macro waituart,rd,rx | ||
| 33 | 1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx | ||
| 34 | tst \rd, #1 << 11 @ UBUSYx | ||
| 35 | bne 1001b | ||
| 36 | .endm | ||
| 37 | |||
| 38 | .macro busyuart,rd,rx | ||
| 39 | tst \rx, #0x1000 @ UART2 does not have CTS here | ||
| 40 | bne 1002f | ||
| 41 | 1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx | ||
| 42 | tst \rd, #1 << 8 @ CTS | ||
| 43 | bne 1001b | ||
| 44 | 1002: | ||
| 45 | .endm | ||
| 46 | |||
diff --git a/include/asm-arm/arch-clps711x/dma.h b/include/asm-arm/arch-clps711x/dma.h deleted file mode 100644 index 610997938423..000000000000 --- a/include/asm-arm/arch-clps711x/dma.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997,1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
diff --git a/include/asm-arm/arch-clps711x/entry-macro.S b/include/asm-arm/arch-clps711x/entry-macro.S deleted file mode 100644 index 3554887cbccb..000000000000 --- a/include/asm-arm/arch-clps711x/entry-macro.S +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-clps711x/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for CLPS711X-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | #include <asm/hardware/clps7111.h> | ||
| 12 | |||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro get_irqnr_preamble, base, tmp | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | #if (INTSR2 - INTSR1) != (INTMR2 - INTMR1) | ||
| 23 | #error INTSR stride != INTMR stride | ||
| 24 | #endif | ||
| 25 | |||
| 26 | .macro get_irqnr_and_base, irqnr, stat, base, mask | ||
| 27 | mov \base, #CLPS7111_BASE | ||
| 28 | ldr \stat, [\base, #INTSR1] | ||
| 29 | ldr \mask, [\base, #INTMR1] | ||
| 30 | mov \irqnr, #4 | ||
| 31 | mov \mask, \mask, lsl #16 | ||
| 32 | and \stat, \stat, \mask, lsr #16 | ||
| 33 | movs \stat, \stat, lsr #4 | ||
| 34 | bne 1001f | ||
| 35 | |||
| 36 | add \base, \base, #INTSR2 - INTSR1 | ||
| 37 | ldr \stat, [\base, #INTSR1] | ||
| 38 | ldr \mask, [\base, #INTMR1] | ||
| 39 | mov \irqnr, #16 | ||
| 40 | mov \mask, \mask, lsl #16 | ||
| 41 | and \stat, \stat, \mask, lsr #16 | ||
| 42 | |||
| 43 | 1001: tst \stat, #255 | ||
| 44 | addeq \irqnr, \irqnr, #8 | ||
| 45 | moveq \stat, \stat, lsr #8 | ||
| 46 | tst \stat, #15 | ||
| 47 | addeq \irqnr, \irqnr, #4 | ||
| 48 | moveq \stat, \stat, lsr #4 | ||
| 49 | tst \stat, #3 | ||
| 50 | addeq \irqnr, \irqnr, #2 | ||
| 51 | moveq \stat, \stat, lsr #2 | ||
| 52 | tst \stat, #1 | ||
| 53 | addeq \irqnr, \irqnr, #1 | ||
| 54 | moveq \stat, \stat, lsr #1 | ||
| 55 | tst \stat, #1 @ bit 0 should be set | ||
| 56 | .endm | ||
| 57 | |||
| 58 | |||
diff --git a/include/asm-arm/arch-clps711x/hardware.h b/include/asm-arm/arch-clps711x/hardware.h deleted file mode 100644 index 0fdbe72fff2a..000000000000 --- a/include/asm-arm/arch-clps711x/hardware.h +++ /dev/null | |||
| @@ -1,237 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/hardware.h | ||
| 3 | * | ||
| 4 | * This file contains the hardware definitions of the Prospector P720T. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 23 | #define __ASM_ARCH_HARDWARE_H | ||
| 24 | |||
| 25 | |||
| 26 | #define CLPS7111_VIRT_BASE 0xff000000 | ||
| 27 | #define CLPS7111_BASE CLPS7111_VIRT_BASE | ||
| 28 | |||
| 29 | /* | ||
| 30 | * The physical addresses that the external chip select signals map to is | ||
| 31 | * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212 | ||
| 32 | * processors. CONFIG_EP72XX_BOOT_ROM is only available if these | ||
| 33 | * processors are in use. | ||
| 34 | */ | ||
| 35 | #ifndef CONFIG_EP72XX_ROM_BOOT | ||
| 36 | #define CS0_PHYS_BASE (0x00000000) | ||
| 37 | #define CS1_PHYS_BASE (0x10000000) | ||
| 38 | #define CS2_PHYS_BASE (0x20000000) | ||
| 39 | #define CS3_PHYS_BASE (0x30000000) | ||
| 40 | #define CS4_PHYS_BASE (0x40000000) | ||
| 41 | #define CS5_PHYS_BASE (0x50000000) | ||
| 42 | #define CS6_PHYS_BASE (0x60000000) | ||
| 43 | #define CS7_PHYS_BASE (0x70000000) | ||
| 44 | #else | ||
| 45 | #define CS0_PHYS_BASE (0x70000000) | ||
| 46 | #define CS1_PHYS_BASE (0x60000000) | ||
| 47 | #define CS2_PHYS_BASE (0x50000000) | ||
| 48 | #define CS3_PHYS_BASE (0x40000000) | ||
| 49 | #define CS4_PHYS_BASE (0x30000000) | ||
| 50 | #define CS5_PHYS_BASE (0x20000000) | ||
| 51 | #define CS6_PHYS_BASE (0x10000000) | ||
| 52 | #define CS7_PHYS_BASE (0x00000000) | ||
| 53 | #endif | ||
| 54 | |||
| 55 | #if defined (CONFIG_ARCH_EP7211) | ||
| 56 | |||
| 57 | #define EP7211_VIRT_BASE CLPS7111_VIRT_BASE | ||
| 58 | #define EP7211_BASE CLPS7111_VIRT_BASE | ||
| 59 | #include <asm/hardware/ep7211.h> | ||
| 60 | |||
| 61 | #elif defined (CONFIG_ARCH_EP7212) | ||
| 62 | |||
| 63 | #define EP7212_VIRT_BASE CLPS7111_VIRT_BASE | ||
| 64 | #define EP7212_BASE CLPS7111_VIRT_BASE | ||
| 65 | #include <asm/hardware/ep7212.h> | ||
| 66 | |||
| 67 | #endif | ||
| 68 | |||
| 69 | #define SYSPLD_VIRT_BASE 0xfe000000 | ||
| 70 | #define SYSPLD_BASE SYSPLD_VIRT_BASE | ||
| 71 | |||
| 72 | #ifndef __ASSEMBLER__ | ||
| 73 | |||
| 74 | #define PCIO_BASE IO_BASE | ||
| 75 | |||
| 76 | #endif | ||
| 77 | |||
| 78 | |||
| 79 | #if defined (CONFIG_ARCH_AUTCPU12) | ||
| 80 | |||
| 81 | #define CS89712_VIRT_BASE CLPS7111_VIRT_BASE | ||
| 82 | #define CS89712_BASE CLPS7111_VIRT_BASE | ||
| 83 | |||
| 84 | #include <asm/hardware/clps7111.h> | ||
| 85 | #include <asm/hardware/ep7212.h> | ||
| 86 | #include <asm/hardware/cs89712.h> | ||
| 87 | |||
| 88 | #endif | ||
| 89 | |||
| 90 | |||
| 91 | #if defined (CONFIG_ARCH_CDB89712) | ||
| 92 | |||
| 93 | #include <asm/hardware/clps7111.h> | ||
| 94 | #include <asm/hardware/ep7212.h> | ||
| 95 | #include <asm/hardware/cs89712.h> | ||
| 96 | |||
| 97 | /* dynamic ioremap() areas */ | ||
| 98 | #define FLASH_START 0x00000000 | ||
| 99 | #define FLASH_SIZE 0x800000 | ||
| 100 | #define FLASH_WIDTH 4 | ||
| 101 | |||
| 102 | #define SRAM_START 0x60000000 | ||
| 103 | #define SRAM_SIZE 0xc000 | ||
| 104 | #define SRAM_WIDTH 4 | ||
| 105 | |||
| 106 | #define BOOTROM_START 0x70000000 | ||
| 107 | #define BOOTROM_SIZE 0x80 | ||
| 108 | #define BOOTROM_WIDTH 4 | ||
| 109 | |||
| 110 | |||
| 111 | /* static cdb89712_map_io() areas */ | ||
| 112 | #define REGISTER_START 0x80000000 | ||
| 113 | #define REGISTER_SIZE 0x4000 | ||
| 114 | #define REGISTER_BASE 0xff000000 | ||
| 115 | |||
| 116 | #define ETHER_START 0x20000000 | ||
| 117 | #define ETHER_SIZE 0x1000 | ||
| 118 | #define ETHER_BASE 0xfe000000 | ||
| 119 | |||
| 120 | #endif | ||
| 121 | |||
| 122 | |||
| 123 | #if defined (CONFIG_ARCH_EDB7211) | ||
| 124 | |||
| 125 | /* | ||
| 126 | * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) | ||
| 127 | * and repeat across it. This is the mapping for it. | ||
| 128 | * | ||
| 129 | * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This | ||
| 130 | * was cause for much consternation and headscratching. This should probably | ||
| 131 | * be made a compile/run time kernel option. | ||
| 132 | */ | ||
| 133 | #define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */ | ||
| 134 | |||
| 135 | #define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */ | ||
| 136 | |||
| 137 | |||
| 138 | /* | ||
| 139 | * The CS8900A ethernet chip has its I/O registers wired to chip select 2 | ||
| 140 | * (nCS2). This is the mapping for it. | ||
| 141 | * | ||
| 142 | * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This | ||
| 143 | * was cause for much consternation and headscratching. This should probably | ||
| 144 | * be made a compile/run time kernel option. | ||
| 145 | */ | ||
| 146 | #define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */ | ||
| 147 | |||
| 148 | #define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */ | ||
| 149 | |||
| 150 | |||
| 151 | /* | ||
| 152 | * The two flash banks are wired to chip selects 0 and 1. This is the mapping | ||
| 153 | * for them. | ||
| 154 | * | ||
| 155 | * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running | ||
| 156 | * in jumpered boot mode. | ||
| 157 | */ | ||
| 158 | #define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */ | ||
| 159 | #define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */ | ||
| 160 | |||
| 161 | #define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */ | ||
| 162 | #define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */ | ||
| 163 | |||
| 164 | #endif /* CONFIG_ARCH_EDB7211 */ | ||
| 165 | |||
| 166 | |||
| 167 | /* | ||
| 168 | * Relevant bits in port D, which controls power to the various parts of | ||
| 169 | * the LCD on the EDB7211. | ||
| 170 | */ | ||
| 171 | #define EDB_PD1_LCD_DC_DC_EN (1<<1) | ||
| 172 | #define EDB_PD2_LCDEN (1<<2) | ||
| 173 | #define EDB_PD3_LCDBL (1<<3) | ||
| 174 | |||
| 175 | |||
| 176 | #if defined (CONFIG_ARCH_CEIVA) | ||
| 177 | |||
| 178 | #define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE | ||
| 179 | #define CEIVA_BASE CLPS7111_VIRT_BASE | ||
| 180 | |||
| 181 | #include <asm/hardware/clps7111.h> | ||
| 182 | #include <asm/hardware/ep7212.h> | ||
| 183 | |||
| 184 | |||
| 185 | /* | ||
| 186 | * The two flash banks are wired to chip selects 0 and 1. This is the mapping | ||
| 187 | * for them. | ||
| 188 | * | ||
| 189 | * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running | ||
| 190 | * in jumpered boot mode. | ||
| 191 | */ | ||
| 192 | #define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */ | ||
| 193 | #define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */ | ||
| 194 | |||
| 195 | #define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */ | ||
| 196 | #define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */ | ||
| 197 | |||
| 198 | #define CEIVA_FLASH_SIZE 0x100000 | ||
| 199 | #define CEIVA_FLASH_WIDTH 2 | ||
| 200 | |||
| 201 | #define SRAM_START 0x60000000 | ||
| 202 | #define SRAM_SIZE 0xc000 | ||
| 203 | #define SRAM_WIDTH 4 | ||
| 204 | |||
| 205 | #define BOOTROM_START 0x70000000 | ||
| 206 | #define BOOTROM_SIZE 0x80 | ||
| 207 | #define BOOTROM_WIDTH 4 | ||
| 208 | |||
| 209 | /* | ||
| 210 | * SED1355 LCD controller | ||
| 211 | */ | ||
| 212 | #define CEIVA_PHYS_SED1355 CS2_PHYS_BASE | ||
| 213 | #define CEIVA_VIRT_SED1355 (0xfc000000) | ||
| 214 | |||
| 215 | /* | ||
| 216 | * Relevant bits in port D, which controls power to the various parts of | ||
| 217 | * the LCD on the Ceiva Photo Max, and reset to the LCD controller. | ||
| 218 | */ | ||
| 219 | |||
| 220 | // Reset line to SED1355 (must be high to operate) | ||
| 221 | #define CEIVA_PD1_LCDRST (1<<1) | ||
| 222 | // LCD panel enable (set to one, to enable LCD) | ||
| 223 | #define CEIVA_PD4_LCDEN (1<<4) | ||
| 224 | // Backlight (set to one, to turn on backlight | ||
| 225 | #define CEIVA_PD5_LCDBL (1<<5) | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Relevant bits in port B, which report the status of the buttons. | ||
| 229 | */ | ||
| 230 | |||
| 231 | // White button | ||
| 232 | #define CEIVA_PB4_WHT_BTN (1<<4) | ||
| 233 | // Black button | ||
| 234 | #define CEIVA_PB0_BLK_BTN (1<<0) | ||
| 235 | #endif // #if defined (CONFIG_ARCH_CEIVA) | ||
| 236 | |||
| 237 | #endif | ||
diff --git a/include/asm-arm/arch-clps711x/io.h b/include/asm-arm/arch-clps711x/io.h deleted file mode 100644 index 2b84dac8b2fa..000000000000 --- a/include/asm-arm/arch-clps711x/io.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 21 | #define __ASM_ARM_ARCH_IO_H | ||
| 22 | |||
| 23 | #include <asm/arch/hardware.h> | ||
| 24 | |||
| 25 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 26 | |||
| 27 | #define __io(a) ((void __iomem *)(a)) | ||
| 28 | #define __mem_pci(a) (a) | ||
| 29 | |||
| 30 | /* | ||
| 31 | * We don't support ins[lb]/outs[lb]. Make them fault. | ||
| 32 | */ | ||
| 33 | #define __raw_readsb(p,d,l) do { *(int *)0 = 0; } while (0) | ||
| 34 | #define __raw_readsl(p,d,l) do { *(int *)0 = 0; } while (0) | ||
| 35 | #define __raw_writesb(p,d,l) do { *(int *)0 = 0; } while (0) | ||
| 36 | #define __raw_writesl(p,d,l) do { *(int *)0 = 0; } while (0) | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-clps711x/irqs.h b/include/asm-arm/arch-clps711x/irqs.h deleted file mode 100644 index 76025dc87637..000000000000 --- a/include/asm-arm/arch-clps711x/irqs.h +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Interrupts from INTSR1 | ||
| 23 | */ | ||
| 24 | #define IRQ_CSINT 4 | ||
| 25 | #define IRQ_EINT1 5 | ||
| 26 | #define IRQ_EINT2 6 | ||
| 27 | #define IRQ_EINT3 7 | ||
| 28 | #define IRQ_TC1OI 8 | ||
| 29 | #define IRQ_TC2OI 9 | ||
| 30 | #define IRQ_RTCMI 10 | ||
| 31 | #define IRQ_TINT 11 | ||
| 32 | #define IRQ_UTXINT1 12 | ||
| 33 | #define IRQ_URXINT1 13 | ||
| 34 | #define IRQ_UMSINT 14 | ||
| 35 | #define IRQ_SSEOTI 15 | ||
| 36 | |||
| 37 | #define INT1_IRQS (0x0000fff0) | ||
| 38 | #define INT1_ACK_IRQS (0x00004f10) | ||
| 39 | |||
| 40 | /* | ||
| 41 | * Interrupts from INTSR2 | ||
| 42 | */ | ||
| 43 | #define IRQ_KBDINT (16+0) /* bit 0 */ | ||
| 44 | #define IRQ_SS2RX (16+1) /* bit 1 */ | ||
| 45 | #define IRQ_SS2TX (16+2) /* bit 2 */ | ||
| 46 | #define IRQ_UTXINT2 (16+12) /* bit 12 */ | ||
| 47 | #define IRQ_URXINT2 (16+13) /* bit 13 */ | ||
| 48 | |||
| 49 | #define INT2_IRQS (0x30070000) | ||
| 50 | #define INT2_ACK_IRQS (0x00010000) | ||
| 51 | |||
| 52 | #define NR_IRQS 30 | ||
| 53 | |||
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h deleted file mode 100644 index 42768cc8bfb4..000000000000 --- a/include/asm-arm/arch-clps711x/memory.h +++ /dev/null | |||
| @@ -1,94 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 21 | #define __ASM_ARCH_MEMORY_H | ||
| 22 | |||
| 23 | |||
| 24 | /* | ||
| 25 | * Physical DRAM offset. | ||
| 26 | */ | ||
| 27 | #define PHYS_OFFSET UL(0xc0000000) | ||
| 28 | |||
| 29 | /* | ||
| 30 | * Virtual view <-> DMA view memory address translations | ||
| 31 | * virt_to_bus: Used to translate the virtual address to an | ||
| 32 | * address suitable to be passed to set_dma_addr | ||
| 33 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 34 | * to an address that the kernel can use. | ||
| 35 | */ | ||
| 36 | |||
| 37 | #if defined(CONFIG_ARCH_CDB89712) | ||
| 38 | |||
| 39 | #define __virt_to_bus(x) (x) | ||
| 40 | #define __bus_to_virt(x) (x) | ||
| 41 | |||
| 42 | #elif defined (CONFIG_ARCH_AUTCPU12) | ||
| 43 | |||
| 44 | #define __virt_to_bus(x) (x) | ||
| 45 | #define __bus_to_virt(x) (x) | ||
| 46 | |||
| 47 | #else | ||
| 48 | |||
| 49 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET) | ||
| 50 | #define __bus_to_virt(x) ((x) + PAGE_OFFSET) | ||
| 51 | |||
| 52 | #endif | ||
| 53 | |||
| 54 | |||
| 55 | /* | ||
| 56 | * Like the SA1100, the EDB7211 has a large gap between physical RAM | ||
| 57 | * banks. In 2.2, the Psion (CL-PS7110) port added custom support for | ||
| 58 | * discontiguous physical memory. In 2.4, we can use the standard | ||
| 59 | * Linux NUMA support. | ||
| 60 | * | ||
| 61 | * This is not necessary for EP7211 implementations with only one used | ||
| 62 | * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM. | ||
| 63 | */ | ||
| 64 | |||
| 65 | /* | ||
| 66 | * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 | ||
| 67 | * uses only one of the two banks (bank #1). However, even within | ||
| 68 | * bank #1, memory is discontiguous. | ||
| 69 | * | ||
| 70 | * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between | ||
| 71 | * them, so we use 24 for the node max shift to get 16MB node sizes. | ||
| 72 | */ | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Because of the wide memory address space between physical RAM banks on the | ||
| 76 | * SA1100, it's much more convenient to use Linux's NUMA support to implement | ||
| 77 | * our memory map representation. Assuming all memory nodes have equal access | ||
| 78 | * characteristics, we then have generic discontiguous memory support. | ||
| 79 | * | ||
| 80 | * Of course, all this isn't mandatory for SA1100 implementations with only | ||
| 81 | * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. | ||
| 82 | * | ||
| 83 | * The nodes are matched with the physical memory bank addresses which are | ||
| 84 | * incidentally the same as virtual addresses. | ||
| 85 | * | ||
| 86 | * node 0: 0xc0000000 - 0xc7ffffff | ||
| 87 | * node 1: 0xc8000000 - 0xcfffffff | ||
| 88 | * node 2: 0xd0000000 - 0xd7ffffff | ||
| 89 | * node 3: 0xd8000000 - 0xdfffffff | ||
| 90 | */ | ||
| 91 | #define NODE_MEM_SIZE_BITS 24 | ||
| 92 | |||
| 93 | #endif | ||
| 94 | |||
diff --git a/include/asm-arm/arch-clps711x/syspld.h b/include/asm-arm/arch-clps711x/syspld.h deleted file mode 100644 index 960578a22a8e..000000000000 --- a/include/asm-arm/arch-clps711x/syspld.h +++ /dev/null | |||
| @@ -1,121 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/syspld.h | ||
| 3 | * | ||
| 4 | * System Control PLD register definitions. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | #ifndef __ASM_ARCH_SYSPLD_H | ||
| 23 | #define __ASM_ARCH_SYSPLD_H | ||
| 24 | |||
| 25 | #define SYSPLD_PHYS_BASE (0x10000000) | ||
| 26 | |||
| 27 | #ifndef __ASSEMBLY__ | ||
| 28 | #include <asm/types.h> | ||
| 29 | |||
| 30 | #define SYSPLD_REG(type,off) (*(volatile type *)(SYSPLD_BASE + off)) | ||
| 31 | #else | ||
| 32 | #define SYSPLD_REG(type,off) (off) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #define PLD_INT SYSPLD_REG(u32, 0x000000) | ||
| 36 | #define PLD_INT_PENIRQ (1 << 5) | ||
| 37 | #define PLD_INT_UCB_IRQ (1 << 1) | ||
| 38 | #define PLD_INT_KBD_ATN (1 << 0) /* EINT1 */ | ||
| 39 | |||
| 40 | #define PLD_PWR SYSPLD_REG(u32, 0x000004) | ||
| 41 | #define PLD_PWR_EXT (1 << 5) | ||
| 42 | #define PLD_PWR_MODE (1 << 4) /* 1 = PWM, 0 = PFM */ | ||
| 43 | #define PLD_S4_ON (1 << 3) /* LCD bias voltage enable */ | ||
| 44 | #define PLD_S3_ON (1 << 2) /* LCD backlight enable */ | ||
| 45 | #define PLD_S2_ON (1 << 1) /* LCD 3V3 supply enable */ | ||
| 46 | #define PLD_S1_ON (1 << 0) /* LCD 3V supply enable */ | ||
| 47 | |||
| 48 | #define PLD_KBD SYSPLD_REG(u32, 0x000008) | ||
| 49 | #define PLD_KBD_WAKE (1 << 1) | ||
| 50 | #define PLD_KBD_EN (1 << 0) | ||
| 51 | |||
| 52 | #define PLD_SPI SYSPLD_REG(u32, 0x00000c) | ||
| 53 | #define PLD_SPI_EN (1 << 0) | ||
| 54 | |||
| 55 | #define PLD_IO SYSPLD_REG(u32, 0x000010) | ||
| 56 | #define PLD_IO_BOOTSEL (1 << 6) /* boot sel switch */ | ||
| 57 | #define PLD_IO_USER (1 << 5) /* user defined switch */ | ||
| 58 | #define PLD_IO_LED3 (1 << 4) | ||
| 59 | #define PLD_IO_LED2 (1 << 3) | ||
| 60 | #define PLD_IO_LED1 (1 << 2) | ||
| 61 | #define PLD_IO_LED0 (1 << 1) | ||
| 62 | #define PLD_IO_LEDEN (1 << 0) | ||
| 63 | |||
| 64 | #define PLD_IRDA SYSPLD_REG(u32, 0x000014) | ||
| 65 | #define PLD_IRDA_EN (1 << 0) | ||
| 66 | |||
| 67 | #define PLD_COM2 SYSPLD_REG(u32, 0x000018) | ||
| 68 | #define PLD_COM2_EN (1 << 0) | ||
| 69 | |||
| 70 | #define PLD_COM1 SYSPLD_REG(u32, 0x00001c) | ||
| 71 | #define PLD_COM1_EN (1 << 0) | ||
| 72 | |||
| 73 | #define PLD_AUD SYSPLD_REG(u32, 0x000020) | ||
| 74 | #define PLD_AUD_DIV1 (1 << 6) | ||
| 75 | #define PLD_AUD_DIV0 (1 << 5) | ||
| 76 | #define PLD_AUD_CLK_SEL1 (1 << 4) | ||
| 77 | #define PLD_AUD_CLK_SEL0 (1 << 3) | ||
| 78 | #define PLD_AUD_MIC_PWR (1 << 2) | ||
| 79 | #define PLD_AUD_MIC_GAIN (1 << 1) | ||
| 80 | #define PLD_AUD_CODEC_EN (1 << 0) | ||
| 81 | |||
| 82 | #define PLD_CF SYSPLD_REG(u32, 0x000024) | ||
| 83 | #define PLD_CF2_SLEEP (1 << 5) | ||
| 84 | #define PLD_CF1_SLEEP (1 << 4) | ||
| 85 | #define PLD_CF2_nPDREQ (1 << 3) | ||
| 86 | #define PLD_CF1_nPDREQ (1 << 2) | ||
| 87 | #define PLD_CF2_nIRQ (1 << 1) | ||
| 88 | #define PLD_CF1_nIRQ (1 << 0) | ||
| 89 | |||
| 90 | #define PLD_SDC SYSPLD_REG(u32, 0x000028) | ||
| 91 | #define PLD_SDC_INT_EN (1 << 2) | ||
| 92 | #define PLD_SDC_WP (1 << 1) | ||
| 93 | #define PLD_SDC_CD (1 << 0) | ||
| 94 | |||
| 95 | #define PLD_FPGA SYSPLD_REG(u32, 0x00002c) | ||
| 96 | |||
| 97 | #define PLD_CODEC SYSPLD_REG(u32, 0x400000) | ||
| 98 | #define PLD_CODEC_IRQ3 (1 << 4) | ||
| 99 | #define PLD_CODEC_IRQ2 (1 << 3) | ||
| 100 | #define PLD_CODEC_IRQ1 (1 << 2) | ||
| 101 | #define PLD_CODEC_EN (1 << 0) | ||
| 102 | |||
| 103 | #define PLD_BRITE SYSPLD_REG(u32, 0x400004) | ||
| 104 | #define PLD_BRITE_UP (1 << 1) | ||
| 105 | #define PLD_BRITE_DN (1 << 0) | ||
| 106 | |||
| 107 | #define PLD_LCDEN SYSPLD_REG(u32, 0x400008) | ||
| 108 | #define PLD_LCDEN_EN (1 << 0) | ||
| 109 | |||
| 110 | #define PLD_ID SYSPLD_REG(u32, 0x40000c) | ||
| 111 | |||
| 112 | #define PLD_TCH SYSPLD_REG(u32, 0x400010) | ||
| 113 | #define PLD_TCH_PENIRQ (1 << 1) | ||
| 114 | #define PLD_TCH_EN (1 << 0) | ||
| 115 | |||
| 116 | #define PLD_GPIO SYSPLD_REG(u32, 0x400014) | ||
| 117 | #define PLD_GPIO2 (1 << 2) | ||
| 118 | #define PLD_GPIO1 (1 << 1) | ||
| 119 | #define PLD_GPIO0 (1 << 0) | ||
| 120 | |||
| 121 | #endif | ||
diff --git a/include/asm-arm/arch-clps711x/system.h b/include/asm-arm/arch-clps711x/system.h deleted file mode 100644 index 1f561772bee4..000000000000 --- a/include/asm-arm/arch-clps711x/system.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 21 | #define __ASM_ARCH_SYSTEM_H | ||
| 22 | |||
| 23 | #include <asm/arch/hardware.h> | ||
| 24 | #include <asm/hardware/clps7111.h> | ||
| 25 | #include <asm/io.h> | ||
| 26 | |||
| 27 | static inline void arch_idle(void) | ||
| 28 | { | ||
| 29 | clps_writel(1, HALT); | ||
| 30 | __asm__ __volatile__( | ||
| 31 | "mov r0, r0\n\ | ||
| 32 | mov r0, r0"); | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline void arch_reset(char mode) | ||
| 36 | { | ||
| 37 | cpu_reset(0); | ||
| 38 | } | ||
| 39 | |||
| 40 | #endif | ||
diff --git a/include/asm-arm/arch-clps711x/time.h b/include/asm-arm/arch-clps711x/time.h deleted file mode 100644 index 5edaae1c61d3..000000000000 --- a/include/asm-arm/arch-clps711x/time.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/time.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #include <asm/leds.h> | ||
| 21 | #include <asm/hardware/clps7111.h> | ||
| 22 | |||
| 23 | extern void clps711x_setup_timer(void); | ||
| 24 | |||
| 25 | /* | ||
| 26 | * IRQ handler for the timer | ||
| 27 | */ | ||
| 28 | static irqreturn_t | ||
| 29 | p720t_timer_interrupt(int irq, void *dev_id) | ||
| 30 | { | ||
| 31 | struct pt_regs *regs = get_irq_regs(); | ||
| 32 | do_leds(); | ||
| 33 | do_timer(1); | ||
| 34 | #ifndef CONFIG_SMP | ||
| 35 | update_process_times(user_mode(regs)); | ||
| 36 | #endif | ||
| 37 | do_profile(regs); | ||
| 38 | return IRQ_HANDLED; | ||
| 39 | } | ||
| 40 | |||
| 41 | /* | ||
| 42 | * Set up timer interrupt, and return the current time in seconds. | ||
| 43 | */ | ||
| 44 | void __init time_init(void) | ||
| 45 | { | ||
| 46 | clps711x_setup_timer(); | ||
| 47 | timer_irq.handler = p720t_timer_interrupt; | ||
| 48 | setup_irq(IRQ_TC2OI, &timer_irq); | ||
| 49 | } | ||
diff --git a/include/asm-arm/arch-clps711x/timex.h b/include/asm-arm/arch-clps711x/timex.h deleted file mode 100644 index dcbb381da3dd..000000000000 --- a/include/asm-arm/arch-clps711x/timex.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/timex.h | ||
| 3 | * | ||
| 4 | * Prospector 720T architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define CLOCK_TICK_RATE 512000 | ||
diff --git a/include/asm-arm/arch-clps711x/uncompress.h b/include/asm-arm/arch-clps711x/uncompress.h deleted file mode 100644 index 8c5684ad086e..000000000000 --- a/include/asm-arm/arch-clps711x/uncompress.h +++ /dev/null | |||
| @@ -1,59 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #include <asm/arch/io.h> | ||
| 21 | #include <asm/arch/hardware.h> | ||
| 22 | #include <asm/hardware/clps7111.h> | ||
| 23 | |||
| 24 | #undef CLPS7111_BASE | ||
| 25 | #define CLPS7111_BASE CLPS7111_PHYS_BASE | ||
| 26 | |||
| 27 | #define __raw_readl(p) (*(unsigned long *)(p)) | ||
| 28 | #define __raw_writel(v,p) (*(unsigned long *)(p) = (v)) | ||
| 29 | |||
| 30 | #ifdef CONFIG_DEBUG_CLPS711X_UART2 | ||
| 31 | #define SYSFLGx SYSFLG2 | ||
| 32 | #define UARTDRx UARTDR2 | ||
| 33 | #else | ||
| 34 | #define SYSFLGx SYSFLG1 | ||
| 35 | #define UARTDRx UARTDR1 | ||
| 36 | #endif | ||
| 37 | |||
| 38 | /* | ||
| 39 | * This does not append a newline | ||
| 40 | */ | ||
| 41 | static inline void putc(int c) | ||
| 42 | { | ||
| 43 | while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) | ||
| 44 | barrier(); | ||
| 45 | clps_writel(c, UARTDRx); | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline void flush(void) | ||
| 49 | { | ||
| 50 | while (clps_readl(SYSFLGx) & SYSFLG_UBUSY) | ||
| 51 | barrier(); | ||
| 52 | } | ||
| 53 | |||
| 54 | /* | ||
| 55 | * nothing to do | ||
| 56 | */ | ||
| 57 | #define arch_decomp_setup() | ||
| 58 | |||
| 59 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-clps711x/vmalloc.h b/include/asm-arm/arch-clps711x/vmalloc.h deleted file mode 100644 index a5dfe96abc96..000000000000 --- a/include/asm-arm/arch-clps711x/vmalloc.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-clps711x/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
diff --git a/include/asm-arm/arch-davinci/clock.h b/include/asm-arm/arch-davinci/clock.h deleted file mode 100644 index cc168b7a14f2..000000000000 --- a/include/asm-arm/arch-davinci/clock.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-davinci/clock.h | ||
| 3 | * | ||
| 4 | * Clock control driver for DaVinci - header file | ||
| 5 | * | ||
| 6 | * Authors: Vladimir Barinov <source@mvista.com> | ||
| 7 | * | ||
| 8 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 9 | * the terms of the GNU General Public License version 2. This program | ||
| 10 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 11 | * or implied. | ||
| 12 | */ | ||
| 13 | #ifndef __ASM_ARCH_DAVINCI_CLOCK_H | ||
| 14 | #define __ASM_ARCH_DAVINCI_CLOCK_H | ||
| 15 | |||
| 16 | struct clk; | ||
| 17 | |||
| 18 | extern int clk_register(struct clk *clk); | ||
| 19 | extern void clk_unregister(struct clk *clk); | ||
| 20 | extern int davinci_clk_init(void); | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/include/asm-arm/arch-davinci/common.h b/include/asm-arm/arch-davinci/common.h deleted file mode 100644 index a97dfbb15e57..000000000000 --- a/include/asm-arm/arch-davinci/common.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Header for code common to all DaVinci machines. | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H | ||
| 13 | #define __ARCH_ARM_MACH_DAVINCI_COMMON_H | ||
| 14 | |||
| 15 | struct sys_timer; | ||
| 16 | |||
| 17 | extern struct sys_timer davinci_timer; | ||
| 18 | |||
| 19 | #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ | ||
diff --git a/include/asm-arm/arch-davinci/debug-macro.S b/include/asm-arm/arch-davinci/debug-macro.S deleted file mode 100644 index e6c0f0d5d062..000000000000 --- a/include/asm-arm/arch-davinci/debug-macro.S +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Debugging macro for DaVinci | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | .macro addruart, rx | ||
| 13 | mrc p15, 0, \rx, c1, c0 | ||
| 14 | tst \rx, #1 @ MMU enabled? | ||
| 15 | moveq \rx, #0x01000000 @ physical base address | ||
| 16 | movne \rx, #0xfe000000 @ virtual base | ||
| 17 | orr \rx, \rx, #0x00c20000 @ UART 0 | ||
| 18 | .endm | ||
| 19 | |||
| 20 | #define UART_SHIFT 2 | ||
| 21 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-davinci/dma.h b/include/asm-arm/arch-davinci/dma.h deleted file mode 100644 index 8e2f2d0ba667..000000000000 --- a/include/asm-arm/arch-davinci/dma.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci DMA definitions | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_DMA_H | ||
| 12 | #define __ASM_ARCH_DMA_H | ||
| 13 | |||
| 14 | #define MAX_DMA_ADDRESS 0xffffffff | ||
| 15 | |||
| 16 | #endif /* __ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-davinci/entry-macro.S b/include/asm-arm/arch-davinci/entry-macro.S deleted file mode 100644 index 3ebfcc5cb58e..000000000000 --- a/include/asm-arm/arch-davinci/entry-macro.S +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Low-level IRQ helper macros for TI DaVinci-based platforms | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #include <asm/arch/io.h> | ||
| 12 | #include <asm/arch/irqs.h> | ||
| 13 | |||
| 14 | .macro disable_fiq | ||
| 15 | .endm | ||
| 16 | |||
| 17 | .macro get_irqnr_preamble, base, tmp | ||
| 18 | ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 25 | ldr \tmp, [\base, #0x14] | ||
| 26 | mov \tmp, \tmp, lsr #2 | ||
| 27 | sub \irqnr, \tmp, #1 | ||
| 28 | cmp \tmp, #0 | ||
| 29 | .endm | ||
| 30 | |||
| 31 | .macro irq_prio_table | ||
| 32 | .endm | ||
diff --git a/include/asm-arm/arch-davinci/gpio.h b/include/asm-arm/arch-davinci/gpio.h deleted file mode 100644 index 54fda734649f..000000000000 --- a/include/asm-arm/arch-davinci/gpio.h +++ /dev/null | |||
| @@ -1,159 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * TI DaVinci GPIO Support | ||
| 3 | * | ||
| 4 | * Copyright (c) 2006 David Brownell | ||
| 5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __DAVINCI_GPIO_H | ||
| 14 | #define __DAVINCI_GPIO_H | ||
| 15 | |||
| 16 | #include <linux/io.h> | ||
| 17 | #include <asm/arch/hardware.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * basic gpio routines | ||
| 21 | * | ||
| 22 | * board-specific init should be done by arch/.../.../board-XXX.c (maybe | ||
| 23 | * initializing banks together) rather than boot loaders; kexec() won't | ||
| 24 | * go through boot loaders. | ||
| 25 | * | ||
| 26 | * the gpio clock will be turned on when gpios are used, and you may also | ||
| 27 | * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are | ||
| 28 | * used as gpios, not with other peripherals. | ||
| 29 | * | ||
| 30 | * GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe | ||
| 31 | * for later updates, code should write GPIO(N) or: | ||
| 32 | * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) | ||
| 33 | * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) | ||
| 34 | * | ||
| 35 | * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc | ||
| 36 | * for now, that's != GPIO(N) | ||
| 37 | */ | ||
| 38 | #define GPIO(X) (X) /* 0 <= X <= 70 */ | ||
| 39 | #define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */ | ||
| 40 | #define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */ | ||
| 41 | |||
| 42 | struct gpio_controller { | ||
| 43 | u32 dir; | ||
| 44 | u32 out_data; | ||
| 45 | u32 set_data; | ||
| 46 | u32 clr_data; | ||
| 47 | u32 in_data; | ||
| 48 | u32 set_rising; | ||
| 49 | u32 clr_rising; | ||
| 50 | u32 set_falling; | ||
| 51 | u32 clr_falling; | ||
| 52 | u32 intstat; | ||
| 53 | }; | ||
| 54 | |||
| 55 | /* The __gpio_to_controller() and __gpio_mask() functions inline to constants | ||
| 56 | * with constant parameters; or in outlined code they execute at runtime. | ||
| 57 | * | ||
| 58 | * You'd access the controller directly when reading or writing more than | ||
| 59 | * one gpio value at a time, and to support wired logic where the value | ||
| 60 | * being driven by the cpu need not match the value read back. | ||
| 61 | * | ||
| 62 | * These are NOT part of the cross-platform GPIO interface | ||
| 63 | */ | ||
| 64 | static inline struct gpio_controller *__iomem | ||
| 65 | __gpio_to_controller(unsigned gpio) | ||
| 66 | { | ||
| 67 | void *__iomem ptr; | ||
| 68 | |||
| 69 | if (gpio < 32) | ||
| 70 | ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); | ||
| 71 | else if (gpio < 64) | ||
| 72 | ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); | ||
| 73 | else if (gpio < DAVINCI_N_GPIO) | ||
| 74 | ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); | ||
| 75 | else | ||
| 76 | ptr = NULL; | ||
| 77 | return ptr; | ||
| 78 | } | ||
| 79 | |||
| 80 | static inline u32 __gpio_mask(unsigned gpio) | ||
| 81 | { | ||
| 82 | return 1 << (gpio % 32); | ||
| 83 | } | ||
| 84 | |||
| 85 | /* The get/set/clear functions will inline when called with constant | ||
| 86 | * parameters, for low-overhead bitbanging. Illegal constant parameters | ||
| 87 | * cause link-time errors. | ||
| 88 | * | ||
| 89 | * Otherwise, calls with variable parameters use outlined functions. | ||
| 90 | */ | ||
| 91 | extern int __error_inval_gpio(void); | ||
| 92 | |||
| 93 | extern void __gpio_set(unsigned gpio, int value); | ||
| 94 | extern int __gpio_get(unsigned gpio); | ||
| 95 | |||
| 96 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 97 | { | ||
| 98 | if (__builtin_constant_p(value)) { | ||
| 99 | struct gpio_controller *__iomem g; | ||
| 100 | u32 mask; | ||
| 101 | |||
| 102 | if (gpio >= DAVINCI_N_GPIO) | ||
| 103 | __error_inval_gpio(); | ||
| 104 | |||
| 105 | g = __gpio_to_controller(gpio); | ||
| 106 | mask = __gpio_mask(gpio); | ||
| 107 | if (value) | ||
| 108 | __raw_writel(mask, &g->set_data); | ||
| 109 | else | ||
| 110 | __raw_writel(mask, &g->clr_data); | ||
| 111 | return; | ||
| 112 | } | ||
| 113 | |||
| 114 | __gpio_set(gpio, value); | ||
| 115 | } | ||
| 116 | |||
| 117 | /* Returns zero or nonzero; works for gpios configured as inputs OR | ||
| 118 | * as outputs. | ||
| 119 | * | ||
| 120 | * NOTE: changes in reported values are synchronized to the GPIO clock. | ||
| 121 | * This is most easily seen after calling gpio_set_value() and then immediatly | ||
| 122 | * gpio_get_value(), where the gpio_get_value() would return the old value | ||
| 123 | * until the GPIO clock ticks and the new value gets latched. | ||
| 124 | */ | ||
| 125 | |||
| 126 | static inline int gpio_get_value(unsigned gpio) | ||
| 127 | { | ||
| 128 | struct gpio_controller *__iomem g; | ||
| 129 | |||
| 130 | if (!__builtin_constant_p(gpio)) | ||
| 131 | return __gpio_get(gpio); | ||
| 132 | |||
| 133 | if (gpio >= DAVINCI_N_GPIO) | ||
| 134 | return __error_inval_gpio(); | ||
| 135 | |||
| 136 | g = __gpio_to_controller(gpio); | ||
| 137 | return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data)); | ||
| 138 | } | ||
| 139 | |||
| 140 | /* powerup default direction is IN */ | ||
| 141 | extern int gpio_direction_input(unsigned gpio); | ||
| 142 | extern int gpio_direction_output(unsigned gpio, int value); | ||
| 143 | |||
| 144 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
| 145 | |||
| 146 | extern int gpio_request(unsigned gpio, const char *tag); | ||
| 147 | extern void gpio_free(unsigned gpio); | ||
| 148 | |||
| 149 | static inline int gpio_to_irq(unsigned gpio) | ||
| 150 | { | ||
| 151 | return DAVINCI_N_AINTC_IRQ + gpio; | ||
| 152 | } | ||
| 153 | |||
| 154 | static inline int irq_to_gpio(unsigned irq) | ||
| 155 | { | ||
| 156 | return irq - DAVINCI_N_AINTC_IRQ; | ||
| 157 | } | ||
| 158 | |||
| 159 | #endif /* __DAVINCI_GPIO_H */ | ||
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h deleted file mode 100644 index a2e8969afaca..000000000000 --- a/include/asm-arm/arch-davinci/hardware.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Common hardware definitions | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 12 | #define __ASM_ARCH_HARDWARE_H | ||
| 13 | |||
| 14 | /* | ||
| 15 | * Base register addresses | ||
| 16 | */ | ||
| 17 | #define DAVINCI_DMA_3PCC_BASE (0x01C00000) | ||
| 18 | #define DAVINCI_DMA_3PTC0_BASE (0x01C10000) | ||
| 19 | #define DAVINCI_DMA_3PTC1_BASE (0x01C10400) | ||
| 20 | #define DAVINCI_I2C_BASE (0x01C21000) | ||
| 21 | #define DAVINCI_PWM0_BASE (0x01C22000) | ||
| 22 | #define DAVINCI_PWM1_BASE (0x01C22400) | ||
| 23 | #define DAVINCI_PWM2_BASE (0x01C22800) | ||
| 24 | #define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) | ||
| 25 | #define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) | ||
| 26 | #define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) | ||
| 27 | #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) | ||
| 28 | #define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) | ||
| 29 | #define DAVINCI_IEEE1394_BASE (0x01C60000) | ||
| 30 | #define DAVINCI_USB_OTG_BASE (0x01C64000) | ||
| 31 | #define DAVINCI_CFC_ATA_BASE (0x01C66000) | ||
| 32 | #define DAVINCI_SPI_BASE (0x01C66800) | ||
| 33 | #define DAVINCI_GPIO_BASE (0x01C67000) | ||
| 34 | #define DAVINCI_UHPI_BASE (0x01C67800) | ||
| 35 | #define DAVINCI_VPSS_REGS_BASE (0x01C70000) | ||
| 36 | #define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) | ||
| 37 | #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) | ||
| 38 | #define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) | ||
| 39 | #define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) | ||
| 40 | #define DAVINCI_IMCOP_BASE (0x01CC0000) | ||
| 41 | #define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) | ||
| 42 | #define DAVINCI_VLYNQ_BASE (0x01E01000) | ||
| 43 | #define DAVINCI_MCBSP_BASE (0x01E02000) | ||
| 44 | #define DAVINCI_MMC_SD_BASE (0x01E10000) | ||
| 45 | #define DAVINCI_MS_BASE (0x01E20000) | ||
| 46 | #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) | ||
| 47 | #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) | ||
| 48 | #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) | ||
| 49 | #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) | ||
| 50 | #define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) | ||
| 51 | |||
| 52 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-davinci/i2c.h b/include/asm-arm/arch-davinci/i2c.h deleted file mode 100644 index e2f54168abd1..000000000000 --- a/include/asm-arm/arch-davinci/i2c.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci I2C controller platfrom_device info | ||
| 3 | * | ||
| 4 | * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_I2C_H | ||
| 13 | #define __ASM_ARCH_I2C_H | ||
| 14 | |||
| 15 | /* All frequencies are expressed in kHz */ | ||
| 16 | struct davinci_i2c_platform_data { | ||
| 17 | unsigned int bus_freq; /* standard bus frequency */ | ||
| 18 | unsigned int bus_delay; /* transaction delay */ | ||
| 19 | }; | ||
| 20 | |||
| 21 | #endif /* __ASM_ARCH_I2C_H */ | ||
diff --git a/include/asm-arm/arch-davinci/io.h b/include/asm-arm/arch-davinci/io.h deleted file mode 100644 index e7accb910864..000000000000 --- a/include/asm-arm/arch-davinci/io.h +++ /dev/null | |||
| @@ -1,79 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci IO address definitions | ||
| 3 | * | ||
| 4 | * Copied from include/asm/arm/arch-omap/io.h | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_IO_H | ||
| 12 | #define __ASM_ARCH_IO_H | ||
| 13 | |||
| 14 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 15 | |||
| 16 | /* | ||
| 17 | * ---------------------------------------------------------------------------- | ||
| 18 | * I/O mapping | ||
| 19 | * ---------------------------------------------------------------------------- | ||
| 20 | */ | ||
| 21 | #define IO_PHYS 0x01c00000 | ||
| 22 | #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ | ||
| 23 | #define IO_SIZE 0x00400000 | ||
| 24 | #define IO_VIRT (IO_PHYS + IO_OFFSET) | ||
| 25 | #define io_p2v(pa) ((pa) + IO_OFFSET) | ||
| 26 | #define io_v2p(va) ((va) - IO_OFFSET) | ||
| 27 | #define IO_ADDRESS(x) io_p2v(x) | ||
| 28 | |||
| 29 | /* | ||
| 30 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
| 31 | * drivers out there that might just work if we fake them... | ||
| 32 | */ | ||
| 33 | #define PCIO_BASE 0 | ||
| 34 | #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) | ||
| 35 | #define __mem_pci(a) (a) | ||
| 36 | #define __mem_isa(a) (a) | ||
| 37 | |||
| 38 | #ifndef __ASSEMBLER__ | ||
| 39 | |||
| 40 | /* | ||
| 41 | * Functions to access the DaVinci IO region | ||
| 42 | * | ||
| 43 | * NOTE: - Use davinci_read/write[bwl] for physical register addresses | ||
| 44 | * - Use __raw_read/write[bwl]() for virtual register addresses | ||
| 45 | * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses | ||
| 46 | * - DO NOT use hardcoded virtual addresses to allow changing the | ||
| 47 | * IO address space again if needed | ||
| 48 | */ | ||
| 49 | #define davinci_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) | ||
| 50 | #define davinci_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) | ||
| 51 | #define davinci_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) | ||
| 52 | |||
| 53 | #define davinci_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) | ||
| 54 | #define davinci_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) | ||
| 55 | #define davinci_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) | ||
| 56 | |||
| 57 | /* 16 bit uses LDRH/STRH, base +/- offset_8 */ | ||
| 58 | typedef struct { volatile u16 offset[256]; } __regbase16; | ||
| 59 | #define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ | ||
| 60 | ->offset[((vaddr)&0xff)>>1] | ||
| 61 | #define __REG16(paddr) __REGV16(io_p2v(paddr)) | ||
| 62 | |||
| 63 | /* 8/32 bit uses LDR/STR, base +/- offset_12 */ | ||
| 64 | typedef struct { volatile u8 offset[4096]; } __regbase8; | ||
| 65 | #define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ | ||
| 66 | ->offset[((vaddr)&4095)>>0] | ||
| 67 | #define __REG8(paddr) __REGV8(io_p2v(paddr)) | ||
| 68 | |||
| 69 | typedef struct { volatile u32 offset[4096]; } __regbase32; | ||
| 70 | #define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ | ||
| 71 | ->offset[((vaddr)&4095)>>2] | ||
| 72 | |||
| 73 | #define __REG(paddr) __REGV32(io_p2v(paddr)) | ||
| 74 | #else | ||
| 75 | |||
| 76 | #define __REG(x) (*((volatile unsigned long *)io_p2v(x))) | ||
| 77 | |||
| 78 | #endif /* __ASSEMBLER__ */ | ||
| 79 | #endif /* __ASM_ARCH_IO_H */ | ||
diff --git a/include/asm-arm/arch-davinci/irqs.h b/include/asm-arm/arch-davinci/irqs.h deleted file mode 100644 index f4c5ca6da9f4..000000000000 --- a/include/asm-arm/arch-davinci/irqs.h +++ /dev/null | |||
| @@ -1,105 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci interrupt controller definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Texas Instruments. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | * | ||
| 11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License along | ||
| 23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 25 | * | ||
| 26 | */ | ||
| 27 | #ifndef __ASM_ARCH_IRQS_H | ||
| 28 | #define __ASM_ARCH_IRQS_H | ||
| 29 | |||
| 30 | /* Base address */ | ||
| 31 | #define DAVINCI_ARM_INTC_BASE 0x01C48000 | ||
| 32 | |||
| 33 | /* Interrupt lines */ | ||
| 34 | #define IRQ_VDINT0 0 | ||
| 35 | #define IRQ_VDINT1 1 | ||
| 36 | #define IRQ_VDINT2 2 | ||
| 37 | #define IRQ_HISTINT 3 | ||
| 38 | #define IRQ_H3AINT 4 | ||
| 39 | #define IRQ_PRVUINT 5 | ||
| 40 | #define IRQ_RSZINT 6 | ||
| 41 | #define IRQ_VFOCINT 7 | ||
| 42 | #define IRQ_VENCINT 8 | ||
| 43 | #define IRQ_ASQINT 9 | ||
| 44 | #define IRQ_IMXINT 10 | ||
| 45 | #define IRQ_VLCDINT 11 | ||
| 46 | #define IRQ_USBINT 12 | ||
| 47 | #define IRQ_EMACINT 13 | ||
| 48 | |||
| 49 | #define IRQ_CCINT0 16 | ||
| 50 | #define IRQ_CCERRINT 17 | ||
| 51 | #define IRQ_TCERRINT0 18 | ||
| 52 | #define IRQ_TCERRINT 19 | ||
| 53 | #define IRQ_PSCIN 20 | ||
| 54 | |||
| 55 | #define IRQ_IDE 22 | ||
| 56 | #define IRQ_HPIINT 23 | ||
| 57 | #define IRQ_MBXINT 24 | ||
| 58 | #define IRQ_MBRINT 25 | ||
| 59 | #define IRQ_MMCINT 26 | ||
| 60 | #define IRQ_SDIOINT 27 | ||
| 61 | #define IRQ_MSINT 28 | ||
| 62 | #define IRQ_DDRINT 29 | ||
| 63 | #define IRQ_AEMIFINT 30 | ||
| 64 | #define IRQ_VLQINT 31 | ||
| 65 | #define IRQ_TINT0_TINT12 32 | ||
| 66 | #define IRQ_TINT0_TINT34 33 | ||
| 67 | #define IRQ_TINT1_TINT12 34 | ||
| 68 | #define IRQ_TINT1_TINT34 35 | ||
| 69 | #define IRQ_PWMINT0 36 | ||
| 70 | #define IRQ_PWMINT1 37 | ||
| 71 | #define IRQ_PWMINT2 38 | ||
| 72 | #define IRQ_I2C 39 | ||
| 73 | #define IRQ_UARTINT0 40 | ||
| 74 | #define IRQ_UARTINT1 41 | ||
| 75 | #define IRQ_UARTINT2 42 | ||
| 76 | #define IRQ_SPINT0 43 | ||
| 77 | #define IRQ_SPINT1 44 | ||
| 78 | |||
| 79 | #define IRQ_DSP2ARM0 46 | ||
| 80 | #define IRQ_DSP2ARM1 47 | ||
| 81 | #define IRQ_GPIO0 48 | ||
| 82 | #define IRQ_GPIO1 49 | ||
| 83 | #define IRQ_GPIO2 50 | ||
| 84 | #define IRQ_GPIO3 51 | ||
| 85 | #define IRQ_GPIO4 52 | ||
| 86 | #define IRQ_GPIO5 53 | ||
| 87 | #define IRQ_GPIO6 54 | ||
| 88 | #define IRQ_GPIO7 55 | ||
| 89 | #define IRQ_GPIOBNK0 56 | ||
| 90 | #define IRQ_GPIOBNK1 57 | ||
| 91 | #define IRQ_GPIOBNK2 58 | ||
| 92 | #define IRQ_GPIOBNK3 59 | ||
| 93 | #define IRQ_GPIOBNK4 60 | ||
| 94 | #define IRQ_COMMTX 61 | ||
| 95 | #define IRQ_COMMRX 62 | ||
| 96 | #define IRQ_EMUINT 63 | ||
| 97 | |||
| 98 | #define DAVINCI_N_AINTC_IRQ 64 | ||
| 99 | #define DAVINCI_N_GPIO 71 | ||
| 100 | |||
| 101 | #define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) | ||
| 102 | |||
| 103 | #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 | ||
| 104 | |||
| 105 | #endif /* __ASM_ARCH_IRQS_H */ | ||
diff --git a/include/asm-arm/arch-davinci/memory.h b/include/asm-arm/arch-davinci/memory.h deleted file mode 100644 index dd1625c23cf4..000000000000 --- a/include/asm-arm/arch-davinci/memory.h +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci memory space definitions | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 12 | #define __ASM_ARCH_MEMORY_H | ||
| 13 | |||
| 14 | /************************************************************************** | ||
| 15 | * Included Files | ||
| 16 | **************************************************************************/ | ||
| 17 | #include <asm/page.h> | ||
| 18 | #include <asm/sizes.h> | ||
| 19 | |||
| 20 | /************************************************************************** | ||
| 21 | * Definitions | ||
| 22 | **************************************************************************/ | ||
| 23 | #define DAVINCI_DDR_BASE 0x80000000 | ||
| 24 | #define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */ | ||
| 25 | |||
| 26 | #define PHYS_OFFSET DAVINCI_DDR_BASE | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Increase size of DMA-consistent memory region | ||
| 30 | */ | ||
| 31 | #define CONSISTENT_DMA_SIZE (14<<20) | ||
| 32 | |||
| 33 | #ifndef __ASSEMBLY__ | ||
| 34 | /* | ||
| 35 | * Restrict DMA-able region to workaround silicon bug. The bug | ||
| 36 | * restricts buffers available for DMA to video hardware to be | ||
| 37 | * below 128M | ||
| 38 | */ | ||
| 39 | static inline void | ||
| 40 | __arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) | ||
| 41 | { | ||
| 42 | unsigned int sz = (128<<20) >> PAGE_SHIFT; | ||
| 43 | |||
| 44 | if (node != 0) | ||
| 45 | sz = 0; | ||
| 46 | |||
| 47 | size[1] = size[0] - sz; | ||
| 48 | size[0] = sz; | ||
| 49 | } | ||
| 50 | |||
| 51 | #define arch_adjust_zones(node, zone_size, holes) \ | ||
| 52 | if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) | ||
| 53 | |||
| 54 | #define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) | ||
| 55 | |||
| 56 | #endif | ||
| 57 | |||
| 58 | /* | ||
| 59 | * Bus address is physical address | ||
| 60 | */ | ||
| 61 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 62 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 63 | |||
| 64 | #endif /* __ASM_ARCH_MEMORY_H */ | ||
diff --git a/include/asm-arm/arch-davinci/mux.h b/include/asm-arm/arch-davinci/mux.h deleted file mode 100644 index c24b6782804d..000000000000 --- a/include/asm-arm/arch-davinci/mux.h +++ /dev/null | |||
| @@ -1,55 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci pin multiplexing defines | ||
| 3 | * | ||
| 4 | * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_MUX_H | ||
| 12 | #define __ASM_ARCH_MUX_H | ||
| 13 | |||
| 14 | #define DAVINCI_MUX_AEAW0 0 | ||
| 15 | #define DAVINCI_MUX_AEAW1 1 | ||
| 16 | #define DAVINCI_MUX_AEAW2 2 | ||
| 17 | #define DAVINCI_MUX_AEAW3 3 | ||
| 18 | #define DAVINCI_MUX_AEAW4 4 | ||
| 19 | #define DAVINCI_MUX_AECS4 10 | ||
| 20 | #define DAVINCI_MUX_AECS5 11 | ||
| 21 | #define DAVINCI_MUX_VLYNQWD0 12 | ||
| 22 | #define DAVINCI_MUX_VLYNQWD1 13 | ||
| 23 | #define DAVINCI_MUX_VLSCREN 14 | ||
| 24 | #define DAVINCI_MUX_VLYNQEN 15 | ||
| 25 | #define DAVINCI_MUX_HDIREN 16 | ||
| 26 | #define DAVINCI_MUX_ATAEN 17 | ||
| 27 | #define DAVINCI_MUX_RGB666 22 | ||
| 28 | #define DAVINCI_MUX_RGB888 23 | ||
| 29 | #define DAVINCI_MUX_LOEEN 24 | ||
| 30 | #define DAVINCI_MUX_LFLDEN 25 | ||
| 31 | #define DAVINCI_MUX_CWEN 26 | ||
| 32 | #define DAVINCI_MUX_CFLDEN 27 | ||
| 33 | #define DAVINCI_MUX_HPIEN 29 | ||
| 34 | #define DAVINCI_MUX_1394EN 30 | ||
| 35 | #define DAVINCI_MUX_EMACEN 31 | ||
| 36 | |||
| 37 | #define DAVINCI_MUX_LEVEL2 32 | ||
| 38 | #define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) | ||
| 39 | #define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) | ||
| 40 | #define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) | ||
| 41 | #define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) | ||
| 42 | #define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) | ||
| 43 | #define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) | ||
| 44 | #define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) | ||
| 45 | #define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) | ||
| 46 | #define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) | ||
| 47 | #define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) | ||
| 48 | #define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) | ||
| 49 | #define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) | ||
| 50 | #define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) | ||
| 51 | #define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) | ||
| 52 | |||
| 53 | extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); | ||
| 54 | |||
| 55 | #endif /* __ASM_ARCH_MUX_H */ | ||
diff --git a/include/asm-arm/arch-davinci/psc.h b/include/asm-arm/arch-davinci/psc.h deleted file mode 100644 index 4977aa071e1e..000000000000 --- a/include/asm-arm/arch-davinci/psc.h +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci Power & Sleep Controller (PSC) defines | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Texas Instruments. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | * | ||
| 11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License along | ||
| 23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 25 | * | ||
| 26 | */ | ||
| 27 | #ifndef __ASM_ARCH_PSC_H | ||
| 28 | #define __ASM_ARCH_PSC_H | ||
| 29 | |||
| 30 | /* Power and Sleep Controller (PSC) Domains */ | ||
| 31 | #define DAVINCI_GPSC_ARMDOMAIN 0 | ||
| 32 | #define DAVINCI_GPSC_DSPDOMAIN 1 | ||
| 33 | |||
| 34 | #define DAVINCI_LPSC_VPSSMSTR 0 | ||
| 35 | #define DAVINCI_LPSC_VPSSSLV 1 | ||
| 36 | #define DAVINCI_LPSC_TPCC 2 | ||
| 37 | #define DAVINCI_LPSC_TPTC0 3 | ||
| 38 | #define DAVINCI_LPSC_TPTC1 4 | ||
| 39 | #define DAVINCI_LPSC_EMAC 5 | ||
| 40 | #define DAVINCI_LPSC_EMAC_WRAPPER 6 | ||
| 41 | #define DAVINCI_LPSC_MDIO 7 | ||
| 42 | #define DAVINCI_LPSC_IEEE1394 8 | ||
| 43 | #define DAVINCI_LPSC_USB 9 | ||
| 44 | #define DAVINCI_LPSC_ATA 10 | ||
| 45 | #define DAVINCI_LPSC_VLYNQ 11 | ||
| 46 | #define DAVINCI_LPSC_UHPI 12 | ||
| 47 | #define DAVINCI_LPSC_DDR_EMIF 13 | ||
| 48 | #define DAVINCI_LPSC_AEMIF 14 | ||
| 49 | #define DAVINCI_LPSC_MMC_SD 15 | ||
| 50 | #define DAVINCI_LPSC_MEMSTICK 16 | ||
| 51 | #define DAVINCI_LPSC_McBSP 17 | ||
| 52 | #define DAVINCI_LPSC_I2C 18 | ||
| 53 | #define DAVINCI_LPSC_UART0 19 | ||
| 54 | #define DAVINCI_LPSC_UART1 20 | ||
| 55 | #define DAVINCI_LPSC_UART2 21 | ||
| 56 | #define DAVINCI_LPSC_SPI 22 | ||
| 57 | #define DAVINCI_LPSC_PWM0 23 | ||
| 58 | #define DAVINCI_LPSC_PWM1 24 | ||
| 59 | #define DAVINCI_LPSC_PWM2 25 | ||
| 60 | #define DAVINCI_LPSC_GPIO 26 | ||
| 61 | #define DAVINCI_LPSC_TIMER0 27 | ||
| 62 | #define DAVINCI_LPSC_TIMER1 28 | ||
| 63 | #define DAVINCI_LPSC_TIMER2 29 | ||
| 64 | #define DAVINCI_LPSC_SYSTEM_SUBSYS 30 | ||
| 65 | #define DAVINCI_LPSC_ARM 31 | ||
| 66 | #define DAVINCI_LPSC_SCR2 32 | ||
| 67 | #define DAVINCI_LPSC_SCR3 33 | ||
| 68 | #define DAVINCI_LPSC_SCR4 34 | ||
| 69 | #define DAVINCI_LPSC_CROSSBAR 35 | ||
| 70 | #define DAVINCI_LPSC_CFG27 36 | ||
| 71 | #define DAVINCI_LPSC_CFG3 37 | ||
| 72 | #define DAVINCI_LPSC_CFG5 38 | ||
| 73 | #define DAVINCI_LPSC_GEM 39 | ||
| 74 | #define DAVINCI_LPSC_IMCOP 40 | ||
| 75 | |||
| 76 | #endif /* __ASM_ARCH_PSC_H */ | ||
diff --git a/include/asm-arm/arch-davinci/serial.h b/include/asm-arm/arch-davinci/serial.h deleted file mode 100644 index ed418ef76805..000000000000 --- a/include/asm-arm/arch-davinci/serial.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci serial device definitions | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_SERIAL_H | ||
| 12 | #define __ASM_ARCH_SERIAL_H | ||
| 13 | |||
| 14 | #include <asm/arch/io.h> | ||
| 15 | |||
| 16 | #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) | ||
| 17 | #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) | ||
| 18 | #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) | ||
| 19 | |||
| 20 | #endif /* __ASM_ARCH_SERIAL_H */ | ||
diff --git a/include/asm-arm/arch-davinci/system.h b/include/asm-arm/arch-davinci/system.h deleted file mode 100644 index 6713e4a44ee8..000000000000 --- a/include/asm-arm/arch-davinci/system.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci system defines | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 12 | #define __ASM_ARCH_SYSTEM_H | ||
| 13 | |||
| 14 | #include <asm/io.h> | ||
| 15 | #include <asm/arch/hardware.h> | ||
| 16 | |||
| 17 | extern void davinci_watchdog_reset(void); | ||
| 18 | |||
| 19 | static void arch_idle(void) | ||
| 20 | { | ||
| 21 | cpu_do_idle(); | ||
| 22 | } | ||
| 23 | |||
| 24 | static void arch_reset(char mode) | ||
| 25 | { | ||
| 26 | davinci_watchdog_reset(); | ||
| 27 | } | ||
| 28 | |||
| 29 | #endif /* __ASM_ARCH_SYSTEM_H */ | ||
diff --git a/include/asm-arm/arch-davinci/timex.h b/include/asm-arm/arch-davinci/timex.h deleted file mode 100644 index 52827567841d..000000000000 --- a/include/asm-arm/arch-davinci/timex.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci timer defines | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 12 | #define __ASM_ARCH_TIMEX_H | ||
| 13 | |||
| 14 | /* The source frequency for the timers is the 27MHz clock */ | ||
| 15 | #define CLOCK_TICK_RATE 27000000 | ||
| 16 | |||
| 17 | #endif /* __ASM_ARCH_TIMEX_H__ */ | ||
diff --git a/include/asm-arm/arch-davinci/uncompress.h b/include/asm-arm/arch-davinci/uncompress.h deleted file mode 100644 index f6d1570f7206..000000000000 --- a/include/asm-arm/arch-davinci/uncompress.h +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Serial port stubs for kernel decompress status messages | ||
| 3 | * | ||
| 4 | * Author: Anant Gole | ||
| 5 | * (C) Copyright (C) 2006, Texas Instruments, Inc | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public License | ||
| 8 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 9 | * kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/types.h> | ||
| 13 | #include <linux/serial_reg.h> | ||
| 14 | #include <asm/arch/serial.h> | ||
| 15 | |||
| 16 | /* PORT_16C550A, in polled non-fifo mode */ | ||
| 17 | |||
| 18 | static void putc(char c) | ||
| 19 | { | ||
| 20 | volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; | ||
| 21 | |||
| 22 | while (!(uart[UART_LSR] & UART_LSR_THRE)) | ||
| 23 | barrier(); | ||
| 24 | uart[UART_TX] = c; | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline void flush(void) | ||
| 28 | { | ||
| 29 | volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; | ||
| 30 | while (!(uart[UART_LSR] & UART_LSR_THRE)) | ||
| 31 | barrier(); | ||
| 32 | } | ||
| 33 | |||
| 34 | #define arch_decomp_setup() | ||
| 35 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-davinci/vmalloc.h b/include/asm-arm/arch-davinci/vmalloc.h deleted file mode 100644 index 9b47fa89b333..000000000000 --- a/include/asm-arm/arch-davinci/vmalloc.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DaVinci vmalloc definitions | ||
| 3 | * | ||
| 4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | #include <asm/memory.h> | ||
| 12 | #include <asm/arch/io.h> | ||
| 13 | |||
| 14 | /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ | ||
| 15 | #define VMALLOC_END (IO_VIRT - (2<<20)) | ||
diff --git a/include/asm-arm/arch-ebsa110/debug-macro.S b/include/asm-arm/arch-ebsa110/debug-macro.S deleted file mode 100644 index 9213bfe4831d..000000000000 --- a/include/asm-arm/arch-ebsa110/debug-macro.S +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-ebsa110/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | **/ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mov \rx, #0xf0000000 | ||
| 16 | orr \rx, \rx, #0x00000be0 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | #define UART_SHIFT 2 | ||
| 20 | #define FLOW_CONTROL | ||
| 21 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-ebsa110/dma.h b/include/asm-arm/arch-ebsa110/dma.h deleted file mode 100644 index c52f9e2ab0bb..000000000000 --- a/include/asm-arm/arch-ebsa110/dma.h +++ /dev/null | |||
| @@ -1,11 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa110/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997,1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * EBSA110 DMA definitions | ||
| 11 | */ | ||
diff --git a/include/asm-arm/arch-ebsa110/entry-macro.S b/include/asm-arm/arch-ebsa110/entry-macro.S deleted file mode 100644 index f242be5c49ba..000000000000 --- a/include/asm-arm/arch-ebsa110/entry-macro.S +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ebsa110/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for ebsa110 platform. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | |||
| 12 | |||
| 13 | #define IRQ_STAT 0xff000000 /* read */ | ||
| 14 | |||
| 15 | .macro disable_fiq | ||
| 16 | .endm | ||
| 17 | |||
| 18 | .macro get_irqnr_preamble, base, tmp | ||
| 19 | mov \base, #IRQ_STAT | ||
| 20 | .endm | ||
| 21 | |||
| 22 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 23 | .endm | ||
| 24 | |||
| 25 | .macro get_irqnr_and_base, irqnr, stat, base, tmp | ||
| 26 | ldrb \stat, [\base] @ get interrupts | ||
| 27 | mov \irqnr, #0 | ||
| 28 | tst \stat, #15 | ||
| 29 | addeq \irqnr, \irqnr, #4 | ||
| 30 | moveq \stat, \stat, lsr #4 | ||
| 31 | tst \stat, #3 | ||
| 32 | addeq \irqnr, \irqnr, #2 | ||
| 33 | moveq \stat, \stat, lsr #2 | ||
| 34 | tst \stat, #1 | ||
| 35 | addeq \irqnr, \irqnr, #1 | ||
| 36 | moveq \stat, \stat, lsr #1 | ||
| 37 | tst \stat, #1 @ bit 0 should be set | ||
| 38 | .endm | ||
| 39 | |||
diff --git a/include/asm-arm/arch-ebsa110/hardware.h b/include/asm-arm/arch-ebsa110/hardware.h deleted file mode 100644 index 3ce864def41e..000000000000 --- a/include/asm-arm/arch-ebsa110/hardware.h +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa110/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996-2000 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This file contains the hardware definitions of the EBSA-110. | ||
| 11 | */ | ||
| 12 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 13 | #define __ASM_ARCH_HARDWARE_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * The EBSA110 has a weird "ISA IO" region: | ||
| 17 | * | ||
| 18 | * Region 0 (addr = 0xf0000000 + io << 2) | ||
| 19 | * -------------------------------------------------------- | ||
| 20 | * Physical region IO region | ||
| 21 | * f0000fe0 - f0000ffc 3f8 - 3ff ttyS0 | ||
| 22 | * f0000e60 - f0000e64 398 - 399 | ||
| 23 | * f0000de0 - f0000dfc 378 - 37f lp0 | ||
| 24 | * f0000be0 - f0000bfc 2f8 - 2ff ttyS1 | ||
| 25 | * | ||
| 26 | * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1)) | ||
| 27 | * -------------------------------------------------------- | ||
| 28 | * Physical region IO region | ||
| 29 | * f00014f1 a79 pnp write data | ||
| 30 | * f00007c0 - f00007c1 3e0 - 3e1 pcmcia | ||
| 31 | * f00004f1 279 pnp address | ||
| 32 | * f0000440 - f000046c 220 - 236 eth0 | ||
| 33 | * f0000405 203 pnp read data | ||
| 34 | */ | ||
| 35 | |||
| 36 | #define ISAMEM_PHYS 0xe0000000 | ||
| 37 | #define ISAMEM_SIZE 0x10000000 | ||
| 38 | |||
| 39 | #define ISAIO_PHYS 0xf0000000 | ||
| 40 | #define ISAIO_SIZE PGDIR_SIZE | ||
| 41 | |||
| 42 | #define TRICK0_PHYS 0xf2000000 | ||
| 43 | #define TRICK1_PHYS 0xf2400000 | ||
| 44 | #define TRICK2_PHYS 0xf2800000 | ||
| 45 | #define TRICK3_PHYS 0xf2c00000 | ||
| 46 | #define TRICK4_PHYS 0xf3000000 | ||
| 47 | #define TRICK5_PHYS 0xf3400000 | ||
| 48 | #define TRICK6_PHYS 0xf3800000 | ||
| 49 | #define TRICK7_PHYS 0xf3c00000 | ||
| 50 | |||
| 51 | #define ISAMEM_BASE 0xe0000000 | ||
| 52 | #define ISAIO_BASE 0xf0000000 | ||
| 53 | |||
| 54 | #define PIT_BASE 0xfc000000 | ||
| 55 | #define SOFT_BASE 0xfd000000 | ||
| 56 | |||
| 57 | /* | ||
| 58 | * RAM definitions | ||
| 59 | */ | ||
| 60 | #define UNCACHEABLE_ADDR 0xff000000 /* IRQ_STAT */ | ||
| 61 | |||
| 62 | #endif | ||
| 63 | |||
diff --git a/include/asm-arm/arch-ebsa110/io.h b/include/asm-arm/arch-ebsa110/io.h deleted file mode 100644 index 44a4001de807..000000000000 --- a/include/asm-arm/arch-ebsa110/io.h +++ /dev/null | |||
| @@ -1,92 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa110/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997,1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * Modifications: | ||
| 11 | * 06-Dec-1997 RMK Created. | ||
| 12 | */ | ||
| 13 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 14 | #define __ASM_ARM_ARCH_IO_H | ||
| 15 | |||
| 16 | #define IO_SPACE_LIMIT 0xffff | ||
| 17 | |||
| 18 | u8 __inb8(unsigned int port); | ||
| 19 | void __outb8(u8 val, unsigned int port); | ||
| 20 | |||
| 21 | u8 __inb16(unsigned int port); | ||
| 22 | void __outb16(u8 val, unsigned int port); | ||
| 23 | |||
| 24 | u16 __inw(unsigned int port); | ||
| 25 | void __outw(u16 val, unsigned int port); | ||
| 26 | |||
| 27 | u32 __inl(unsigned int port); | ||
| 28 | void __outl(u32 val, unsigned int port); | ||
| 29 | |||
| 30 | u8 __readb(const volatile void __iomem *addr); | ||
| 31 | u16 __readw(const volatile void __iomem *addr); | ||
| 32 | u32 __readl(const volatile void __iomem *addr); | ||
| 33 | |||
| 34 | void __writeb(u8 val, void __iomem *addr); | ||
| 35 | void __writew(u16 val, void __iomem *addr); | ||
| 36 | void __writel(u32 val, void __iomem *addr); | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Argh, someone forgot the IOCS16 line. We therefore have to handle | ||
| 40 | * the byte stearing by selecting the correct byte IO functions here. | ||
| 41 | */ | ||
| 42 | #ifdef ISA_SIXTEEN_BIT_PERIPHERAL | ||
| 43 | #define inb(p) __inb16(p) | ||
| 44 | #define outb(v,p) __outb16(v,p) | ||
| 45 | #else | ||
| 46 | #define inb(p) __inb8(p) | ||
| 47 | #define outb(v,p) __outb8(v,p) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #define inw(p) __inw(p) | ||
| 51 | #define outw(v,p) __outw(v,p) | ||
| 52 | |||
| 53 | #define inl(p) __inl(p) | ||
| 54 | #define outl(v,p) __outl(v,p) | ||
| 55 | |||
| 56 | #define readb(b) __readb(b) | ||
| 57 | #define readw(b) __readw(b) | ||
| 58 | #define readl(b) __readl(b) | ||
| 59 | #define readb_relaxed(addr) readb(addr) | ||
| 60 | #define readw_relaxed(addr) readw(addr) | ||
| 61 | #define readl_relaxed(addr) readl(addr) | ||
| 62 | |||
| 63 | #define writeb(v,b) __writeb(v,b) | ||
| 64 | #define writew(v,b) __writew(v,b) | ||
| 65 | #define writel(v,b) __writel(v,b) | ||
| 66 | |||
| 67 | static inline void __iomem *__arch_ioremap(unsigned long cookie, size_t size, | ||
| 68 | unsigned int flags) | ||
| 69 | { | ||
| 70 | return (void __iomem *)cookie; | ||
| 71 | } | ||
| 72 | |||
| 73 | #define __arch_ioremap __arch_ioremap | ||
| 74 | #define __arch_iounmap(cookie) do { } while (0) | ||
| 75 | |||
| 76 | extern void insb(unsigned int port, void *buf, int sz); | ||
| 77 | extern void insw(unsigned int port, void *buf, int sz); | ||
| 78 | extern void insl(unsigned int port, void *buf, int sz); | ||
| 79 | |||
| 80 | extern void outsb(unsigned int port, const void *buf, int sz); | ||
| 81 | extern void outsw(unsigned int port, const void *buf, int sz); | ||
| 82 | extern void outsl(unsigned int port, const void *buf, int sz); | ||
| 83 | |||
| 84 | /* can't support writesb atm */ | ||
| 85 | extern void writesw(void __iomem *addr, const void *data, int wordlen); | ||
| 86 | extern void writesl(void __iomem *addr, const void *data, int longlen); | ||
| 87 | |||
| 88 | /* can't support readsb atm */ | ||
| 89 | extern void readsw(const void __iomem *addr, void *data, int wordlen); | ||
| 90 | extern void readsl(const void __iomem *addr, void *data, int longlen); | ||
| 91 | |||
| 92 | #endif | ||
diff --git a/include/asm-arm/arch-ebsa110/irqs.h b/include/asm-arm/arch-ebsa110/irqs.h deleted file mode 100644 index ded9bd9d7b8b..000000000000 --- a/include/asm-arm/arch-ebsa110/irqs.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa110/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #define NR_IRQS 8 | ||
| 12 | |||
| 13 | #define IRQ_EBSA110_PRINTER 0 | ||
| 14 | #define IRQ_EBSA110_COM1 1 | ||
| 15 | #define IRQ_EBSA110_COM2 2 | ||
| 16 | #define IRQ_EBSA110_ETHERNET 3 | ||
| 17 | #define IRQ_EBSA110_TIMER0 4 | ||
| 18 | #define IRQ_EBSA110_TIMER1 5 | ||
| 19 | #define IRQ_EBSA110_PCMCIA 6 | ||
| 20 | #define IRQ_EBSA110_IMMEDIATE 7 | ||
diff --git a/include/asm-arm/arch-ebsa110/memory.h b/include/asm-arm/arch-ebsa110/memory.h deleted file mode 100644 index c7c500e176d0..000000000000 --- a/include/asm-arm/arch-ebsa110/memory.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa110/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996-1999 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * Changelog: | ||
| 11 | * 20-Oct-1996 RMK Created | ||
| 12 | * 31-Dec-1997 RMK Fixed definitions to reduce warnings | ||
| 13 | * 21-Mar-1999 RMK Renamed to memory.h | ||
| 14 | * RMK Moved TASK_SIZE and PAGE_OFFSET here | ||
| 15 | */ | ||
| 16 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 17 | #define __ASM_ARCH_MEMORY_H | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Physical DRAM offset. | ||
| 21 | */ | ||
| 22 | #define PHYS_OFFSET UL(0x00000000) | ||
| 23 | |||
| 24 | /* | ||
| 25 | * We keep this 1:1 so that we don't interfere | ||
| 26 | * with the PCMCIA memory regions | ||
| 27 | */ | ||
| 28 | #define __virt_to_bus(x) (x) | ||
| 29 | #define __bus_to_virt(x) (x) | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Cache flushing area - SRAM | ||
| 33 | */ | ||
| 34 | #define FLUSH_BASE_PHYS 0x40000000 | ||
| 35 | #define FLUSH_BASE 0xdf000000 | ||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-ebsa110/system.h b/include/asm-arm/arch-ebsa110/system.h deleted file mode 100644 index d7c8fece0bc5..000000000000 --- a/include/asm-arm/arch-ebsa110/system.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa110/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996-2000 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 11 | #define __ASM_ARCH_SYSTEM_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * EBSA110 idling methodology: | ||
| 15 | * | ||
| 16 | * We can not execute the "wait for interrupt" instruction since that | ||
| 17 | * will stop our MCLK signal (which provides the clock for the glue | ||
| 18 | * logic, and therefore the timer interrupt). | ||
| 19 | * | ||
| 20 | * Instead, we spin, polling the IRQ_STAT register for the occurrence | ||
| 21 | * of any interrupt with core clock down to the memory clock. | ||
| 22 | */ | ||
| 23 | static inline void arch_idle(void) | ||
| 24 | { | ||
| 25 | const char *irq_stat = (char *)0xff000000; | ||
| 26 | |||
| 27 | /* disable clock switching */ | ||
| 28 | asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc"); | ||
| 29 | |||
| 30 | /* wait for an interrupt to occur */ | ||
| 31 | while (!*irq_stat); | ||
| 32 | |||
| 33 | /* enable clock switching */ | ||
| 34 | asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc"); | ||
| 35 | } | ||
| 36 | |||
| 37 | #define arch_reset(mode) cpu_reset(0x80000000) | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-ebsa110/timex.h b/include/asm-arm/arch-ebsa110/timex.h deleted file mode 100644 index 1e9ef045092b..000000000000 --- a/include/asm-arm/arch-ebsa110/timex.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa110/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997, 1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * EBSA110 architecture timex specifications | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * On the EBSA, the clock ticks at weird rates. | ||
| 15 | * This is therefore not used to calculate the | ||
| 16 | * divisor. | ||
| 17 | */ | ||
| 18 | #define CLOCK_TICK_RATE 47894000 | ||
| 19 | |||
diff --git a/include/asm-arm/arch-ebsa110/uncompress.h b/include/asm-arm/arch-ebsa110/uncompress.h deleted file mode 100644 index ae5b775eb0b7..000000000000 --- a/include/asm-arm/arch-ebsa110/uncompress.h +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa110/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996,1997,1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/serial_reg.h> | ||
| 12 | |||
| 13 | #define SERIAL_BASE ((unsigned char *)0xf0000be0) | ||
| 14 | |||
| 15 | /* | ||
| 16 | * This does not append a newline | ||
| 17 | */ | ||
| 18 | static inline void putc(int c) | ||
| 19 | { | ||
| 20 | unsigned char v, *base = SERIAL_BASE; | ||
| 21 | |||
| 22 | do { | ||
| 23 | v = base[UART_LSR << 2]; | ||
| 24 | barrier(); | ||
| 25 | } while (!(v & UART_LSR_THRE)); | ||
| 26 | |||
| 27 | base[UART_TX << 2] = c; | ||
| 28 | } | ||
| 29 | |||
| 30 | static inline void flush(void) | ||
| 31 | { | ||
| 32 | unsigned char v, *base = SERIAL_BASE; | ||
| 33 | |||
| 34 | do { | ||
| 35 | v = base[UART_LSR << 2]; | ||
| 36 | barrier(); | ||
| 37 | } while ((v & (UART_LSR_TEMT|UART_LSR_THRE)) != | ||
| 38 | (UART_LSR_TEMT|UART_LSR_THRE)); | ||
| 39 | } | ||
| 40 | |||
| 41 | /* | ||
| 42 | * nothing to do | ||
| 43 | */ | ||
| 44 | #define arch_decomp_setup() | ||
| 45 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-ebsa110/vmalloc.h b/include/asm-arm/arch-ebsa110/vmalloc.h deleted file mode 100644 index 26674ba4683c..000000000000 --- a/include/asm-arm/arch-ebsa110/vmalloc.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa110/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #define VMALLOC_END (PAGE_OFFSET + 0x1f000000) | ||
diff --git a/include/asm-arm/arch-ebsa285/debug-macro.S b/include/asm-arm/arch-ebsa285/debug-macro.S deleted file mode 100644 index b48cec4a0c45..000000000000 --- a/include/asm-arm/arch-ebsa285/debug-macro.S +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-ebsa285/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <asm/hardware/dec21285.h> | ||
| 15 | |||
| 16 | #ifndef CONFIG_DEBUG_DC21285_PORT | ||
| 17 | /* For NetWinder debugging */ | ||
| 18 | .macro addruart,rx | ||
| 19 | mrc p15, 0, \rx, c1, c0 | ||
| 20 | tst \rx, #1 @ MMU enabled? | ||
| 21 | moveq \rx, #0x7c000000 @ physical | ||
| 22 | movne \rx, #0xff000000 @ virtual | ||
| 23 | orr \rx, \rx, #0x000003f8 | ||
| 24 | .endm | ||
| 25 | |||
| 26 | #define UART_SHIFT 0 | ||
| 27 | #define FLOW_CONTROL | ||
| 28 | #include <asm/hardware/debug-8250.S> | ||
| 29 | |||
| 30 | #else | ||
| 31 | /* For EBSA285 debugging */ | ||
| 32 | .equ dc21285_high, ARMCSR_BASE & 0xff000000 | ||
| 33 | .equ dc21285_low, ARMCSR_BASE & 0x00ffffff | ||
| 34 | |||
| 35 | .macro addruart,rx | ||
| 36 | mrc p15, 0, \rx, c1, c0 | ||
| 37 | tst \rx, #1 @ MMU enabled? | ||
| 38 | moveq \rx, #0x42000000 | ||
| 39 | movne \rx, #dc21285_high | ||
| 40 | .if dc21285_low | ||
| 41 | orrne \rx, \rx, #dc21285_low | ||
| 42 | .endif | ||
| 43 | .endm | ||
| 44 | |||
| 45 | .macro senduart,rd,rx | ||
| 46 | str \rd, [\rx, #0x160] @ UARTDR | ||
| 47 | .endm | ||
| 48 | |||
| 49 | .macro busyuart,rd,rx | ||
| 50 | 1001: ldr \rd, [\rx, #0x178] @ UARTFLG | ||
| 51 | tst \rd, #1 << 3 | ||
| 52 | bne 1001b | ||
| 53 | .endm | ||
| 54 | |||
| 55 | .macro waituart,rd,rx | ||
| 56 | .endm | ||
| 57 | #endif | ||
diff --git a/include/asm-arm/arch-ebsa285/dma.h b/include/asm-arm/arch-ebsa285/dma.h deleted file mode 100644 index 0259ad45d33c..000000000000 --- a/include/asm-arm/arch-ebsa285/dma.h +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa285/dma.h | ||
| 3 | * | ||
| 4 | * Architecture DMA routines | ||
| 5 | * | ||
| 6 | * Copyright (C) 1998,1999 Russell King | ||
| 7 | * Copyright (C) 1998,1999 Philip Blundell | ||
| 8 | */ | ||
| 9 | #ifndef __ASM_ARCH_DMA_H | ||
| 10 | #define __ASM_ARCH_DMA_H | ||
| 11 | |||
| 12 | /* | ||
| 13 | * The 21285 has two internal DMA channels; we call these 8 and 9. | ||
| 14 | * On CATS hardware we have an additional eight ISA dma channels | ||
| 15 | * numbered 0..7. | ||
| 16 | */ | ||
| 17 | #define _ISA_DMA(x) (0+(x)) | ||
| 18 | #define _DC21285_DMA(x) (8+(x)) | ||
| 19 | |||
| 20 | #define MAX_DMA_CHANNELS 10 | ||
| 21 | |||
| 22 | #define DMA_FLOPPY _ISA_DMA(2) | ||
| 23 | #define DMA_ISA_CASCADE _ISA_DMA(4) | ||
| 24 | |||
| 25 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-ebsa285/entry-macro.S b/include/asm-arm/arch-ebsa285/entry-macro.S deleted file mode 100644 index e203c628d500..000000000000 --- a/include/asm-arm/arch-ebsa285/entry-macro.S +++ /dev/null | |||
| @@ -1,113 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ebsa285/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for footbridge-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | #include <asm/arch/irqs.h> | ||
| 12 | #include <asm/hardware/dec21285.h> | ||
| 13 | |||
| 14 | .equ dc21285_high, ARMCSR_BASE & 0xff000000 | ||
| 15 | .equ dc21285_low, ARMCSR_BASE & 0x00ffffff | ||
| 16 | |||
| 17 | .macro disable_fiq | ||
| 18 | .endm | ||
| 19 | |||
| 20 | .macro get_irqnr_preamble, base, tmp | ||
| 21 | mov \base, #dc21285_high | ||
| 22 | .if dc21285_low | ||
| 23 | orr \base, \base, #dc21285_low | ||
| 24 | .endif | ||
| 25 | .endm | ||
| 26 | |||
| 27 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 28 | .endm | ||
| 29 | |||
| 30 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 31 | ldr \irqstat, [\base, #0x180] @ get interrupts | ||
| 32 | |||
| 33 | mov \irqnr, #IRQ_SDRAMPARITY | ||
| 34 | tst \irqstat, #IRQ_MASK_SDRAMPARITY | ||
| 35 | bne 1001f | ||
| 36 | |||
| 37 | tst \irqstat, #IRQ_MASK_UART_RX | ||
| 38 | movne \irqnr, #IRQ_CONRX | ||
| 39 | bne 1001f | ||
| 40 | |||
| 41 | tst \irqstat, #IRQ_MASK_DMA1 | ||
| 42 | movne \irqnr, #IRQ_DMA1 | ||
| 43 | bne 1001f | ||
| 44 | |||
| 45 | tst \irqstat, #IRQ_MASK_DMA2 | ||
| 46 | movne \irqnr, #IRQ_DMA2 | ||
| 47 | bne 1001f | ||
| 48 | |||
| 49 | tst \irqstat, #IRQ_MASK_IN0 | ||
| 50 | movne \irqnr, #IRQ_IN0 | ||
| 51 | bne 1001f | ||
| 52 | |||
| 53 | tst \irqstat, #IRQ_MASK_IN1 | ||
| 54 | movne \irqnr, #IRQ_IN1 | ||
| 55 | bne 1001f | ||
| 56 | |||
| 57 | tst \irqstat, #IRQ_MASK_IN2 | ||
| 58 | movne \irqnr, #IRQ_IN2 | ||
| 59 | bne 1001f | ||
| 60 | |||
| 61 | tst \irqstat, #IRQ_MASK_IN3 | ||
| 62 | movne \irqnr, #IRQ_IN3 | ||
| 63 | bne 1001f | ||
| 64 | |||
| 65 | tst \irqstat, #IRQ_MASK_PCI | ||
| 66 | movne \irqnr, #IRQ_PCI | ||
| 67 | bne 1001f | ||
| 68 | |||
| 69 | tst \irqstat, #IRQ_MASK_DOORBELLHOST | ||
| 70 | movne \irqnr, #IRQ_DOORBELLHOST | ||
| 71 | bne 1001f | ||
| 72 | |||
| 73 | tst \irqstat, #IRQ_MASK_I2OINPOST | ||
| 74 | movne \irqnr, #IRQ_I2OINPOST | ||
| 75 | bne 1001f | ||
| 76 | |||
| 77 | tst \irqstat, #IRQ_MASK_TIMER1 | ||
| 78 | movne \irqnr, #IRQ_TIMER1 | ||
| 79 | bne 1001f | ||
| 80 | |||
| 81 | tst \irqstat, #IRQ_MASK_TIMER2 | ||
| 82 | movne \irqnr, #IRQ_TIMER2 | ||
| 83 | bne 1001f | ||
| 84 | |||
| 85 | tst \irqstat, #IRQ_MASK_TIMER3 | ||
| 86 | movne \irqnr, #IRQ_TIMER3 | ||
| 87 | bne 1001f | ||
| 88 | |||
| 89 | tst \irqstat, #IRQ_MASK_UART_TX | ||
| 90 | movne \irqnr, #IRQ_CONTX | ||
| 91 | bne 1001f | ||
| 92 | |||
| 93 | tst \irqstat, #IRQ_MASK_PCI_ABORT | ||
| 94 | movne \irqnr, #IRQ_PCI_ABORT | ||
| 95 | bne 1001f | ||
| 96 | |||
| 97 | tst \irqstat, #IRQ_MASK_PCI_SERR | ||
| 98 | movne \irqnr, #IRQ_PCI_SERR | ||
| 99 | bne 1001f | ||
| 100 | |||
| 101 | tst \irqstat, #IRQ_MASK_DISCARD_TIMER | ||
| 102 | movne \irqnr, #IRQ_DISCARD_TIMER | ||
| 103 | bne 1001f | ||
| 104 | |||
| 105 | tst \irqstat, #IRQ_MASK_PCI_DPERR | ||
| 106 | movne \irqnr, #IRQ_PCI_DPERR | ||
| 107 | bne 1001f | ||
| 108 | |||
| 109 | tst \irqstat, #IRQ_MASK_PCI_PERR | ||
| 110 | movne \irqnr, #IRQ_PCI_PERR | ||
| 111 | 1001: | ||
| 112 | .endm | ||
| 113 | |||
diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h deleted file mode 100644 index 74610c2c63d4..000000000000 --- a/include/asm-arm/arch-ebsa285/hardware.h +++ /dev/null | |||
| @@ -1,105 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa285/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1998-1999 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This file contains the hardware definitions of the EBSA-285. | ||
| 11 | */ | ||
| 12 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 13 | #define __ASM_ARCH_HARDWARE_H | ||
| 14 | |||
| 15 | #include <asm/arch/memory.h> | ||
| 16 | |||
| 17 | /* Virtual Physical Size | ||
| 18 | * 0xff800000 0x40000000 1MB X-Bus | ||
| 19 | * 0xff000000 0x7c000000 1MB PCI I/O space | ||
| 20 | * 0xfe000000 0x42000000 1MB CSR | ||
| 21 | * 0xfd000000 0x78000000 1MB Outbound write flush (not supported) | ||
| 22 | * 0xfc000000 0x79000000 1MB PCI IACK/special space | ||
| 23 | * 0xfb000000 0x7a000000 16MB PCI Config type 1 | ||
| 24 | * 0xfa000000 0x7b000000 16MB PCI Config type 0 | ||
| 25 | * 0xf9000000 0x50000000 1MB Cache flush | ||
| 26 | * 0xf0000000 0x80000000 16MB ISA memory | ||
| 27 | */ | ||
| 28 | #define XBUS_SIZE 0x00100000 | ||
| 29 | #define XBUS_BASE 0xff800000 | ||
| 30 | |||
| 31 | #define PCIO_SIZE 0x00100000 | ||
| 32 | #define PCIO_BASE 0xff000000 | ||
| 33 | |||
| 34 | #define ARMCSR_SIZE 0x00100000 | ||
| 35 | #define ARMCSR_BASE 0xfe000000 | ||
| 36 | |||
| 37 | #define WFLUSH_SIZE 0x00100000 | ||
| 38 | #define WFLUSH_BASE 0xfd000000 | ||
| 39 | |||
| 40 | #define PCIIACK_SIZE 0x00100000 | ||
| 41 | #define PCIIACK_BASE 0xfc000000 | ||
| 42 | |||
| 43 | #define PCICFG1_SIZE 0x01000000 | ||
| 44 | #define PCICFG1_BASE 0xfb000000 | ||
| 45 | |||
| 46 | #define PCICFG0_SIZE 0x01000000 | ||
| 47 | #define PCICFG0_BASE 0xfa000000 | ||
| 48 | |||
| 49 | #define PCIMEM_SIZE 0x01000000 | ||
| 50 | #define PCIMEM_BASE 0xf0000000 | ||
| 51 | |||
| 52 | #define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000)) | ||
| 53 | #define XBUS_LED_AMBER (1 << 0) | ||
| 54 | #define XBUS_LED_GREEN (1 << 1) | ||
| 55 | #define XBUS_LED_RED (1 << 2) | ||
| 56 | #define XBUS_LED_TOGGLE (1 << 8) | ||
| 57 | |||
| 58 | #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) | ||
| 59 | #define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) | ||
| 60 | #define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4)) | ||
| 61 | #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) | ||
| 62 | #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) | ||
| 63 | |||
| 64 | #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) | ||
| 65 | |||
| 66 | |||
| 67 | /* PIC irq control */ | ||
| 68 | #define PIC_LO 0x20 | ||
| 69 | #define PIC_MASK_LO 0x21 | ||
| 70 | #define PIC_HI 0xA0 | ||
| 71 | #define PIC_MASK_HI 0xA1 | ||
| 72 | |||
| 73 | /* GPIO pins */ | ||
| 74 | #define GPIO_CCLK 0x800 | ||
| 75 | #define GPIO_DSCLK 0x400 | ||
| 76 | #define GPIO_E2CLK 0x200 | ||
| 77 | #define GPIO_IOLOAD 0x100 | ||
| 78 | #define GPIO_RED_LED 0x080 | ||
| 79 | #define GPIO_WDTIMER 0x040 | ||
| 80 | #define GPIO_DATA 0x020 | ||
| 81 | #define GPIO_IOCLK 0x010 | ||
| 82 | #define GPIO_DONE 0x008 | ||
| 83 | #define GPIO_FAN 0x004 | ||
| 84 | #define GPIO_GREEN_LED 0x002 | ||
| 85 | #define GPIO_RESET 0x001 | ||
| 86 | |||
| 87 | /* CPLD pins */ | ||
| 88 | #define CPLD_DS_ENABLE 8 | ||
| 89 | #define CPLD_7111_DISABLE 4 | ||
| 90 | #define CPLD_UNMUTE 2 | ||
| 91 | #define CPLD_FLASH_WR_ENABLE 1 | ||
| 92 | |||
| 93 | #ifndef __ASSEMBLY__ | ||
| 94 | extern void gpio_modify_op(int mask, int set); | ||
| 95 | extern void gpio_modify_io(int mask, int in); | ||
| 96 | extern int gpio_read(void); | ||
| 97 | extern void cpld_modify(int mask, int set); | ||
| 98 | #endif | ||
| 99 | |||
| 100 | #define pcibios_assign_all_busses() 1 | ||
| 101 | |||
| 102 | #define PCIBIOS_MIN_IO 0x1000 | ||
| 103 | #define PCIBIOS_MIN_MEM 0x81000000 | ||
| 104 | |||
| 105 | #endif | ||
diff --git a/include/asm-arm/arch-ebsa285/io.h b/include/asm-arm/arch-ebsa285/io.h deleted file mode 100644 index e88c6e230387..000000000000 --- a/include/asm-arm/arch-ebsa285/io.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa285/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997-1999 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * Modifications: | ||
| 11 | * 06-12-1997 RMK Created. | ||
| 12 | * 07-04-1999 RMK Major cleanup | ||
| 13 | */ | ||
| 14 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 15 | #define __ASM_ARM_ARCH_IO_H | ||
| 16 | |||
| 17 | #include <asm/arch/hardware.h> | ||
| 18 | |||
| 19 | #define IO_SPACE_LIMIT 0xffff | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Translation of various region addresses to virtual addresses | ||
| 23 | */ | ||
| 24 | #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) | ||
| 25 | #if 1 | ||
| 26 | #define __mem_pci(a) (a) | ||
| 27 | #else | ||
| 28 | |||
| 29 | static inline void __iomem *___mem_pci(void __iomem *p) | ||
| 30 | { | ||
| 31 | unsigned long a = (unsigned long)p; | ||
| 32 | BUG_ON(a <= 0xc0000000 || a >= 0xe0000000); | ||
| 33 | return p; | ||
| 34 | } | ||
| 35 | |||
| 36 | #define __mem_pci(a) ___mem_pci(a) | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-ebsa285/irqs.h b/include/asm-arm/arch-ebsa285/irqs.h deleted file mode 100644 index 3e766f1cecf1..000000000000 --- a/include/asm-arm/arch-ebsa285/irqs.h +++ /dev/null | |||
| @@ -1,98 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa285/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1998 Russell King | ||
| 5 | * Copyright (C) 1998 Phil Blundell | ||
| 6 | * | ||
| 7 | * Changelog: | ||
| 8 | * 20-Jan-1998 RMK Started merge of EBSA286, CATS and NetWinder | ||
| 9 | * 01-Feb-1999 PJB ISA IRQs start at 0 not 16 | ||
| 10 | */ | ||
| 11 | #include <asm/mach-types.h> | ||
| 12 | |||
| 13 | #define NR_IRQS 36 | ||
| 14 | #define NR_DC21285_IRQS 16 | ||
| 15 | |||
| 16 | #define _ISA_IRQ(x) (0 + (x)) | ||
| 17 | #define _ISA_INR(x) ((x) - 0) | ||
| 18 | #define _DC21285_IRQ(x) (16 + (x)) | ||
| 19 | #define _DC21285_INR(x) ((x) - 16) | ||
| 20 | |||
| 21 | /* | ||
| 22 | * This is a list of all interrupts that the 21285 | ||
| 23 | * can generate and we handle. | ||
| 24 | */ | ||
| 25 | #define IRQ_CONRX _DC21285_IRQ(0) | ||
| 26 | #define IRQ_CONTX _DC21285_IRQ(1) | ||
| 27 | #define IRQ_TIMER1 _DC21285_IRQ(2) | ||
| 28 | #define IRQ_TIMER2 _DC21285_IRQ(3) | ||
| 29 | #define IRQ_TIMER3 _DC21285_IRQ(4) | ||
| 30 | #define IRQ_IN0 _DC21285_IRQ(5) | ||
| 31 | #define IRQ_IN1 _DC21285_IRQ(6) | ||
| 32 | #define IRQ_IN2 _DC21285_IRQ(7) | ||
| 33 | #define IRQ_IN3 _DC21285_IRQ(8) | ||
| 34 | #define IRQ_DOORBELLHOST _DC21285_IRQ(9) | ||
| 35 | #define IRQ_DMA1 _DC21285_IRQ(10) | ||
| 36 | #define IRQ_DMA2 _DC21285_IRQ(11) | ||
| 37 | #define IRQ_PCI _DC21285_IRQ(12) | ||
| 38 | #define IRQ_SDRAMPARITY _DC21285_IRQ(13) | ||
| 39 | #define IRQ_I2OINPOST _DC21285_IRQ(14) | ||
| 40 | #define IRQ_PCI_ABORT _DC21285_IRQ(15) | ||
| 41 | #define IRQ_PCI_SERR _DC21285_IRQ(16) | ||
| 42 | #define IRQ_DISCARD_TIMER _DC21285_IRQ(17) | ||
| 43 | #define IRQ_PCI_DPERR _DC21285_IRQ(18) | ||
| 44 | #define IRQ_PCI_PERR _DC21285_IRQ(19) | ||
| 45 | |||
| 46 | #define IRQ_ISA_TIMER _ISA_IRQ(0) | ||
| 47 | #define IRQ_ISA_KEYBOARD _ISA_IRQ(1) | ||
| 48 | #define IRQ_ISA_CASCADE _ISA_IRQ(2) | ||
| 49 | #define IRQ_ISA_UART2 _ISA_IRQ(3) | ||
| 50 | #define IRQ_ISA_UART _ISA_IRQ(4) | ||
| 51 | #define IRQ_ISA_FLOPPY _ISA_IRQ(6) | ||
| 52 | #define IRQ_ISA_PRINTER _ISA_IRQ(7) | ||
| 53 | #define IRQ_ISA_RTC_ALARM _ISA_IRQ(8) | ||
| 54 | #define IRQ_ISA_2 _ISA_IRQ(9) | ||
| 55 | #define IRQ_ISA_PS2MOUSE _ISA_IRQ(12) | ||
| 56 | #define IRQ_ISA_HARDDISK1 _ISA_IRQ(14) | ||
| 57 | #define IRQ_ISA_HARDDISK2 _ISA_IRQ(15) | ||
| 58 | |||
| 59 | #define IRQ_MASK_UART_RX (1 << 2) | ||
| 60 | #define IRQ_MASK_UART_TX (1 << 3) | ||
| 61 | #define IRQ_MASK_TIMER1 (1 << 4) | ||
| 62 | #define IRQ_MASK_TIMER2 (1 << 5) | ||
| 63 | #define IRQ_MASK_TIMER3 (1 << 6) | ||
| 64 | #define IRQ_MASK_IN0 (1 << 8) | ||
| 65 | #define IRQ_MASK_IN1 (1 << 9) | ||
| 66 | #define IRQ_MASK_IN2 (1 << 10) | ||
| 67 | #define IRQ_MASK_IN3 (1 << 11) | ||
| 68 | #define IRQ_MASK_DOORBELLHOST (1 << 15) | ||
| 69 | #define IRQ_MASK_DMA1 (1 << 16) | ||
| 70 | #define IRQ_MASK_DMA2 (1 << 17) | ||
| 71 | #define IRQ_MASK_PCI (1 << 18) | ||
| 72 | #define IRQ_MASK_SDRAMPARITY (1 << 24) | ||
| 73 | #define IRQ_MASK_I2OINPOST (1 << 25) | ||
| 74 | #define IRQ_MASK_PCI_ABORT ((1 << 29) | (1 << 30)) | ||
| 75 | #define IRQ_MASK_PCI_SERR (1 << 23) | ||
| 76 | #define IRQ_MASK_DISCARD_TIMER (1 << 27) | ||
| 77 | #define IRQ_MASK_PCI_DPERR (1 << 28) | ||
| 78 | #define IRQ_MASK_PCI_PERR (1 << 31) | ||
| 79 | |||
| 80 | /* | ||
| 81 | * Netwinder interrupt allocations | ||
| 82 | */ | ||
| 83 | #define IRQ_NETWINDER_ETHER10 IRQ_IN0 | ||
| 84 | #define IRQ_NETWINDER_ETHER100 IRQ_IN1 | ||
| 85 | #define IRQ_NETWINDER_VIDCOMP IRQ_IN2 | ||
| 86 | #define IRQ_NETWINDER_PS2MOUSE _ISA_IRQ(5) | ||
| 87 | #define IRQ_NETWINDER_IR _ISA_IRQ(6) | ||
| 88 | #define IRQ_NETWINDER_BUTTON _ISA_IRQ(10) | ||
| 89 | #define IRQ_NETWINDER_VGA _ISA_IRQ(11) | ||
| 90 | #define IRQ_NETWINDER_SOUND _ISA_IRQ(12) | ||
| 91 | |||
| 92 | #undef RTC_IRQ | ||
| 93 | #define RTC_IRQ IRQ_ISA_RTC_ALARM | ||
| 94 | #define I8042_KBD_IRQ IRQ_ISA_KEYBOARD | ||
| 95 | #define I8042_AUX_IRQ (machine_is_netwinder() ? IRQ_NETWINDER_PS2MOUSE : IRQ_ISA_PS2MOUSE) | ||
| 96 | #define IRQ_FLOPPYDISK IRQ_ISA_FLOPPY | ||
| 97 | |||
| 98 | #define irq_canonicalize(_i) (((_i) == IRQ_ISA_CASCADE) ? IRQ_ISA_2 : _i) | ||
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h deleted file mode 100644 index 9019a3bf5ab9..000000000000 --- a/include/asm-arm/arch-ebsa285/memory.h +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa285/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996-1999 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * Changelog: | ||
| 11 | * 20-Oct-1996 RMK Created | ||
| 12 | * 31-Dec-1997 RMK Fixed definitions to reduce warnings. | ||
| 13 | * 17-May-1998 DAG Added __virt_to_bus and __bus_to_virt functions. | ||
| 14 | * 21-Nov-1998 RMK Changed __virt_to_bus and __bus_to_virt to macros. | ||
| 15 | * 21-Mar-1999 RMK Added PAGE_OFFSET for co285 architecture. | ||
| 16 | * Renamed to memory.h | ||
| 17 | * Moved PAGE_OFFSET and TASK_SIZE here | ||
| 18 | */ | ||
| 19 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 20 | #define __ASM_ARCH_MEMORY_H | ||
| 21 | |||
| 22 | |||
| 23 | #if defined(CONFIG_FOOTBRIDGE_ADDIN) | ||
| 24 | /* | ||
| 25 | * If we may be using add-in footbridge mode, then we must | ||
| 26 | * use the out-of-line translation that makes use of the | ||
| 27 | * PCI BAR | ||
| 28 | */ | ||
| 29 | #ifndef __ASSEMBLY__ | ||
| 30 | extern unsigned long __virt_to_bus(unsigned long); | ||
| 31 | extern unsigned long __bus_to_virt(unsigned long); | ||
| 32 | #endif | ||
| 33 | |||
| 34 | #elif defined(CONFIG_FOOTBRIDGE_HOST) | ||
| 35 | |||
| 36 | #define __virt_to_bus(x) ((x) - 0xe0000000) | ||
| 37 | #define __bus_to_virt(x) ((x) + 0xe0000000) | ||
| 38 | |||
| 39 | #else | ||
| 40 | |||
| 41 | #error "Undefined footbridge mode" | ||
| 42 | |||
| 43 | #endif | ||
| 44 | |||
| 45 | /* Task size and page offset at 3GB */ | ||
| 46 | #define TASK_SIZE UL(0xbf000000) | ||
| 47 | #define PAGE_OFFSET UL(0xc0000000) | ||
| 48 | |||
| 49 | /* | ||
| 50 | * Cache flushing area. | ||
| 51 | */ | ||
| 52 | #define FLUSH_BASE 0xf9000000 | ||
| 53 | |||
| 54 | /* | ||
| 55 | * Physical DRAM offset. | ||
| 56 | */ | ||
| 57 | #define PHYS_OFFSET UL(0x00000000) | ||
| 58 | |||
| 59 | /* | ||
| 60 | * This decides where the kernel will search for a free chunk of vm | ||
| 61 | * space during mmap's. | ||
| 62 | */ | ||
| 63 | #define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3) | ||
| 64 | |||
| 65 | #define FLUSH_BASE_PHYS 0x50000000 | ||
| 66 | |||
| 67 | #endif | ||
diff --git a/include/asm-arm/arch-ebsa285/system.h b/include/asm-arm/arch-ebsa285/system.h deleted file mode 100644 index a720bf7ca123..000000000000 --- a/include/asm-arm/arch-ebsa285/system.h +++ /dev/null | |||
| @@ -1,69 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa285/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996-1999 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #include <asm/hardware/dec21285.h> | ||
| 11 | #include <asm/io.h> | ||
| 12 | #include <asm/arch/hardware.h> | ||
| 13 | #include <asm/leds.h> | ||
| 14 | #include <asm/mach-types.h> | ||
| 15 | |||
| 16 | static inline void arch_idle(void) | ||
| 17 | { | ||
| 18 | cpu_do_idle(); | ||
| 19 | } | ||
| 20 | |||
| 21 | static inline void arch_reset(char mode) | ||
| 22 | { | ||
| 23 | if (mode == 's') { | ||
| 24 | /* | ||
| 25 | * Jump into the ROM | ||
| 26 | */ | ||
| 27 | cpu_reset(0x41000000); | ||
| 28 | } else { | ||
| 29 | if (machine_is_netwinder()) { | ||
| 30 | /* open up the SuperIO chip | ||
| 31 | */ | ||
| 32 | outb(0x87, 0x370); | ||
| 33 | outb(0x87, 0x370); | ||
| 34 | |||
| 35 | /* aux function group 1 (logical device 7) | ||
| 36 | */ | ||
| 37 | outb(0x07, 0x370); | ||
| 38 | outb(0x07, 0x371); | ||
| 39 | |||
| 40 | /* set GP16 for WD-TIMER output | ||
| 41 | */ | ||
| 42 | outb(0xe6, 0x370); | ||
| 43 | outb(0x00, 0x371); | ||
| 44 | |||
| 45 | /* set a RED LED and toggle WD_TIMER for rebooting | ||
| 46 | */ | ||
| 47 | outb(0xc4, 0x338); | ||
| 48 | } else { | ||
| 49 | /* | ||
| 50 | * Force the watchdog to do a CPU reset. | ||
| 51 | * | ||
| 52 | * After making sure that the watchdog is disabled | ||
| 53 | * (so we can change the timer registers) we first | ||
| 54 | * enable the timer to autoreload itself. Next, the | ||
| 55 | * timer interval is set really short and any | ||
| 56 | * current interrupt request is cleared (so we can | ||
| 57 | * see an edge transition). Finally, TIMER4 is | ||
| 58 | * enabled as the watchdog. | ||
| 59 | */ | ||
| 60 | *CSR_SA110_CNTL &= ~(1 << 13); | ||
| 61 | *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE | | ||
| 62 | TIMER_CNTL_AUTORELOAD | | ||
| 63 | TIMER_CNTL_DIV16; | ||
| 64 | *CSR_TIMER4_LOAD = 0x2; | ||
| 65 | *CSR_TIMER4_CLR = 0; | ||
| 66 | *CSR_SA110_CNTL |= (1 << 13); | ||
| 67 | } | ||
| 68 | } | ||
| 69 | } | ||
diff --git a/include/asm-arm/arch-ebsa285/timex.h b/include/asm-arm/arch-ebsa285/timex.h deleted file mode 100644 index df60b3812d96..000000000000 --- a/include/asm-arm/arch-ebsa285/timex.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa285/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * EBSA285 architecture timex specifications | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * We assume a constant here; this satisfies the maths in linux/timex.h | ||
| 15 | * and linux/time.h. CLOCK_TICK_RATE is actually system dependent, but | ||
| 16 | * this must be a constant. | ||
| 17 | */ | ||
| 18 | #define CLOCK_TICK_RATE (50000000/16) | ||
diff --git a/include/asm-arm/arch-ebsa285/uncompress.h b/include/asm-arm/arch-ebsa285/uncompress.h deleted file mode 100644 index 86142c882b3a..000000000000 --- a/include/asm-arm/arch-ebsa285/uncompress.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa285/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996-1999 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #include <asm/mach-types.h> | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Note! This could cause problems on the NetWinder | ||
| 14 | */ | ||
| 15 | #define DC21285_BASE ((volatile unsigned int *)0x42000160) | ||
| 16 | #define SER0_BASE ((volatile unsigned char *)0x7c0003f8) | ||
| 17 | |||
| 18 | static inline void putc(char c) | ||
| 19 | { | ||
| 20 | if (machine_is_netwinder()) { | ||
| 21 | while ((SER0_BASE[5] & 0x60) != 0x60) | ||
| 22 | barrier(); | ||
| 23 | SER0_BASE[0] = c; | ||
| 24 | } else { | ||
| 25 | while (DC21285_BASE[6] & 8); | ||
| 26 | DC21285_BASE[0] = c; | ||
| 27 | } | ||
| 28 | } | ||
| 29 | |||
| 30 | static inline void flush(void) | ||
| 31 | { | ||
| 32 | } | ||
| 33 | |||
| 34 | /* | ||
| 35 | * nothing to do | ||
| 36 | */ | ||
| 37 | #define arch_decomp_setup() | ||
| 38 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h deleted file mode 100644 index e487d7e8c8a6..000000000000 --- a/include/asm-arm/arch-ebsa285/vmalloc.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ebsa285/vmalloc.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | #define VMALLOC_END (PAGE_OFFSET + 0x30000000) | ||
diff --git a/include/asm-arm/arch-ep93xx/debug-macro.S b/include/asm-arm/arch-ep93xx/debug-macro.S deleted file mode 100644 index 397565a0c671..000000000000 --- a/include/asm-arm/arch-ep93xx/debug-macro.S +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/debug-macro.S | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or (at | ||
| 10 | * your option) any later version. | ||
| 11 | */ | ||
| 12 | #include <asm/arch/ep93xx-regs.h> | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | ldreq \rx, =EP93XX_APB_PHYS_BASE @ Physical base | ||
| 18 | ldrne \rx, =EP93XX_APB_VIRT_BASE @ virtual base | ||
| 19 | orr \rx, \rx, #0x000c0000 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | #include <asm/hardware/debug-pl01x.S> | ||
diff --git a/include/asm-arm/arch-ep93xx/dma.h b/include/asm-arm/arch-ep93xx/dma.h deleted file mode 100644 index 898b3ab7fd46..000000000000 --- a/include/asm-arm/arch-ep93xx/dma.h +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/dma.h | ||
| 3 | */ | ||
diff --git a/include/asm-arm/arch-ep93xx/entry-macro.S b/include/asm-arm/arch-ep93xx/entry-macro.S deleted file mode 100644 index 241ec221a047..000000000000 --- a/include/asm-arm/arch-ep93xx/entry-macro.S +++ /dev/null | |||
| @@ -1,59 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/entry-macro.S | ||
| 3 | * IRQ demultiplexing for EP93xx | ||
| 4 | * | ||
| 5 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or (at | ||
| 10 | * your option) any later version. | ||
| 11 | */ | ||
| 12 | #include <asm/arch/ep93xx-regs.h> | ||
| 13 | |||
| 14 | .macro disable_fiq | ||
| 15 | .endm | ||
| 16 | |||
| 17 | .macro get_irqnr_preamble, base, tmp | ||
| 18 | .endm | ||
| 19 | |||
| 20 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 24 | ldr \base, =(EP93XX_AHB_VIRT_BASE) | ||
| 25 | orr \base, \base, #0x000b0000 | ||
| 26 | mov \irqnr, #0 | ||
| 27 | ldr \irqstat, [\base] @ lower 32 interrupts | ||
| 28 | cmp \irqstat, #0 | ||
| 29 | bne 1001f | ||
| 30 | |||
| 31 | eor \base, \base, #0x00070000 | ||
| 32 | ldr \irqstat, [\base] @ upper 32 interrupts | ||
| 33 | cmp \irqstat, #0 | ||
| 34 | beq 1002f | ||
| 35 | mov \irqnr, #0x20 | ||
| 36 | |||
| 37 | 1001: | ||
| 38 | movs \tmp, \irqstat, lsl #16 | ||
| 39 | movne \irqstat, \tmp | ||
| 40 | addeq \irqnr, \irqnr, #16 | ||
| 41 | |||
| 42 | movs \tmp, \irqstat, lsl #8 | ||
| 43 | movne \irqstat, \tmp | ||
| 44 | addeq \irqnr, \irqnr, #8 | ||
| 45 | |||
| 46 | movs \tmp, \irqstat, lsl #4 | ||
| 47 | movne \irqstat, \tmp | ||
| 48 | addeq \irqnr, \irqnr, #4 | ||
| 49 | |||
| 50 | movs \tmp, \irqstat, lsl #2 | ||
| 51 | movne \irqstat, \tmp | ||
| 52 | addeq \irqnr, \irqnr, #2 | ||
| 53 | |||
| 54 | movs \tmp, \irqstat, lsl #1 | ||
| 55 | addeq \irqnr, \irqnr, #1 | ||
| 56 | orrs \base, \base, #1 | ||
| 57 | |||
| 58 | 1002: | ||
| 59 | .endm | ||
diff --git a/include/asm-arm/arch-ep93xx/ep93xx-regs.h b/include/asm-arm/arch-ep93xx/ep93xx-regs.h deleted file mode 100644 index 625c6f0abc03..000000000000 --- a/include/asm-arm/arch-ep93xx/ep93xx-regs.h +++ /dev/null | |||
| @@ -1,133 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/ep93xx-regs.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_ARCH_EP93XX_REGS_H | ||
| 6 | #define __ASM_ARCH_EP93XX_REGS_H | ||
| 7 | |||
| 8 | /* | ||
| 9 | * EP93xx linux memory map: | ||
| 10 | * | ||
| 11 | * virt phys size | ||
| 12 | * fe800000 5M per-platform mappings | ||
| 13 | * fed00000 80800000 2M APB | ||
| 14 | * fef00000 80000000 1M AHB | ||
| 15 | */ | ||
| 16 | |||
| 17 | #define EP93XX_AHB_PHYS_BASE 0x80000000 | ||
| 18 | #define EP93XX_AHB_VIRT_BASE 0xfef00000 | ||
| 19 | #define EP93XX_AHB_SIZE 0x00100000 | ||
| 20 | |||
| 21 | #define EP93XX_APB_PHYS_BASE 0x80800000 | ||
| 22 | #define EP93XX_APB_VIRT_BASE 0xfed00000 | ||
| 23 | #define EP93XX_APB_SIZE 0x00200000 | ||
| 24 | |||
| 25 | |||
| 26 | /* AHB peripherals */ | ||
| 27 | #define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000) | ||
| 28 | |||
| 29 | #define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) | ||
| 30 | #define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) | ||
| 31 | |||
| 32 | #define EP93XX_USB_BASE (EP93XX_AHB_VIRT_BASE + 0x00020000) | ||
| 33 | #define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) | ||
| 34 | |||
| 35 | #define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000) | ||
| 36 | |||
| 37 | #define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000) | ||
| 38 | |||
| 39 | #define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000) | ||
| 40 | |||
| 41 | #define EP93XX_PCMCIA_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00080000) | ||
| 42 | |||
| 43 | #define EP93XX_BOOT_ROM_BASE (EP93XX_AHB_VIRT_BASE + 0x00090000) | ||
| 44 | |||
| 45 | #define EP93XX_IDE_BASE (EP93XX_AHB_VIRT_BASE + 0x000a0000) | ||
| 46 | |||
| 47 | #define EP93XX_VIC1_BASE (EP93XX_AHB_VIRT_BASE + 0x000b0000) | ||
| 48 | |||
| 49 | #define EP93XX_VIC2_BASE (EP93XX_AHB_VIRT_BASE + 0x000c0000) | ||
| 50 | |||
| 51 | |||
| 52 | /* APB peripherals */ | ||
| 53 | #define EP93XX_TIMER_BASE (EP93XX_APB_VIRT_BASE + 0x00010000) | ||
| 54 | #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) | ||
| 55 | #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) | ||
| 56 | #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) | ||
| 57 | #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) | ||
| 58 | #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) | ||
| 59 | #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) | ||
| 60 | #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) | ||
| 61 | #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) | ||
| 62 | #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) | ||
| 63 | #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) | ||
| 64 | #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) | ||
| 65 | #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) | ||
| 66 | #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) | ||
| 67 | #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) | ||
| 68 | #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) | ||
| 69 | |||
| 70 | #define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000) | ||
| 71 | |||
| 72 | #define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000) | ||
| 73 | |||
| 74 | #define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) | ||
| 75 | #define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) | ||
| 76 | #define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c) | ||
| 77 | #define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50) | ||
| 78 | #define EP93XX_GPIO_F_INT_ACK EP93XX_GPIO_REG(0x54) | ||
| 79 | #define EP93XX_GPIO_F_INT_ENABLE EP93XX_GPIO_REG(0x58) | ||
| 80 | #define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) | ||
| 81 | #define EP93XX_GPIO_A_INT_TYPE1 EP93XX_GPIO_REG(0x90) | ||
| 82 | #define EP93XX_GPIO_A_INT_TYPE2 EP93XX_GPIO_REG(0x94) | ||
| 83 | #define EP93XX_GPIO_A_INT_ACK EP93XX_GPIO_REG(0x98) | ||
| 84 | #define EP93XX_GPIO_A_INT_ENABLE EP93XX_GPIO_REG(0x9c) | ||
| 85 | #define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) | ||
| 86 | #define EP93XX_GPIO_B_INT_TYPE1 EP93XX_GPIO_REG(0xac) | ||
| 87 | #define EP93XX_GPIO_B_INT_TYPE2 EP93XX_GPIO_REG(0xb0) | ||
| 88 | #define EP93XX_GPIO_B_INT_ACK EP93XX_GPIO_REG(0xb4) | ||
| 89 | #define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8) | ||
| 90 | #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) | ||
| 91 | |||
| 92 | #define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) | ||
| 93 | |||
| 94 | #define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000) | ||
| 95 | |||
| 96 | #define EP93XX_IRDA_BASE (EP93XX_APB_VIRT_BASE + 0x000b0000) | ||
| 97 | |||
| 98 | #define EP93XX_UART1_BASE (EP93XX_APB_VIRT_BASE + 0x000c0000) | ||
| 99 | #define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000) | ||
| 100 | |||
| 101 | #define EP93XX_UART2_BASE (EP93XX_APB_VIRT_BASE + 0x000d0000) | ||
| 102 | #define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000) | ||
| 103 | |||
| 104 | #define EP93XX_UART3_BASE (EP93XX_APB_VIRT_BASE + 0x000e0000) | ||
| 105 | #define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000) | ||
| 106 | |||
| 107 | #define EP93XX_KEY_MATRIX_BASE (EP93XX_APB_VIRT_BASE + 0x000f0000) | ||
| 108 | |||
| 109 | #define EP93XX_ADC_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) | ||
| 110 | #define EP93XX_TOUCHSCREEN_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) | ||
| 111 | |||
| 112 | #define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) | ||
| 113 | |||
| 114 | #define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000) | ||
| 115 | |||
| 116 | #define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) | ||
| 117 | #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) | ||
| 118 | #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) | ||
| 119 | #define EP93XX_SYSCON_CLOCK_CONTROL EP93XX_SYSCON_REG(0x04) | ||
| 120 | #define EP93XX_SYSCON_CLOCK_UARTBAUD 0x20000000 | ||
| 121 | #define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 | ||
| 122 | #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) | ||
| 123 | #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) | ||
| 124 | #define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) | ||
| 125 | #define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24) | ||
| 126 | #define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) | ||
| 127 | #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000 | ||
| 128 | #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) | ||
| 129 | |||
| 130 | #define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) | ||
| 131 | |||
| 132 | |||
| 133 | #endif | ||
diff --git a/include/asm-arm/arch-ep93xx/gesbc9312.h b/include/asm-arm/arch-ep93xx/gesbc9312.h deleted file mode 100644 index 4d0b3023bff7..000000000000 --- a/include/asm-arm/arch-ep93xx/gesbc9312.h +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/gesbc9312.h | ||
| 3 | */ | ||
diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h deleted file mode 100644 index 186e7c715f8a..000000000000 --- a/include/asm-arm/arch-ep93xx/gpio.h +++ /dev/null | |||
| @@ -1,128 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/gpio.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_ARCH_GPIO_H | ||
| 6 | #define __ASM_ARCH_GPIO_H | ||
| 7 | |||
| 8 | /* GPIO port A. */ | ||
| 9 | #define EP93XX_GPIO_LINE_A(x) ((x) + 0) | ||
| 10 | #define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0) | ||
| 11 | #define EP93XX_GPIO_LINE_EGPIO1 EP93XX_GPIO_LINE_A(1) | ||
| 12 | #define EP93XX_GPIO_LINE_EGPIO2 EP93XX_GPIO_LINE_A(2) | ||
| 13 | #define EP93XX_GPIO_LINE_EGPIO3 EP93XX_GPIO_LINE_A(3) | ||
| 14 | #define EP93XX_GPIO_LINE_EGPIO4 EP93XX_GPIO_LINE_A(4) | ||
| 15 | #define EP93XX_GPIO_LINE_EGPIO5 EP93XX_GPIO_LINE_A(5) | ||
| 16 | #define EP93XX_GPIO_LINE_EGPIO6 EP93XX_GPIO_LINE_A(6) | ||
| 17 | #define EP93XX_GPIO_LINE_EGPIO7 EP93XX_GPIO_LINE_A(7) | ||
| 18 | |||
| 19 | /* GPIO port B. */ | ||
| 20 | #define EP93XX_GPIO_LINE_B(x) ((x) + 8) | ||
| 21 | #define EP93XX_GPIO_LINE_EGPIO8 EP93XX_GPIO_LINE_B(0) | ||
| 22 | #define EP93XX_GPIO_LINE_EGPIO9 EP93XX_GPIO_LINE_B(1) | ||
| 23 | #define EP93XX_GPIO_LINE_EGPIO10 EP93XX_GPIO_LINE_B(2) | ||
| 24 | #define EP93XX_GPIO_LINE_EGPIO11 EP93XX_GPIO_LINE_B(3) | ||
| 25 | #define EP93XX_GPIO_LINE_EGPIO12 EP93XX_GPIO_LINE_B(4) | ||
| 26 | #define EP93XX_GPIO_LINE_EGPIO13 EP93XX_GPIO_LINE_B(5) | ||
| 27 | #define EP93XX_GPIO_LINE_EGPIO14 EP93XX_GPIO_LINE_B(6) | ||
| 28 | #define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7) | ||
| 29 | |||
| 30 | /* GPIO port C. */ | ||
| 31 | #define EP93XX_GPIO_LINE_C(x) ((x) + 40) | ||
| 32 | #define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0) | ||
| 33 | #define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1) | ||
| 34 | #define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2) | ||
| 35 | #define EP93XX_GPIO_LINE_ROW3 EP93XX_GPIO_LINE_C(3) | ||
| 36 | #define EP93XX_GPIO_LINE_ROW4 EP93XX_GPIO_LINE_C(4) | ||
| 37 | #define EP93XX_GPIO_LINE_ROW5 EP93XX_GPIO_LINE_C(5) | ||
| 38 | #define EP93XX_GPIO_LINE_ROW6 EP93XX_GPIO_LINE_C(6) | ||
| 39 | #define EP93XX_GPIO_LINE_ROW7 EP93XX_GPIO_LINE_C(7) | ||
| 40 | |||
| 41 | /* GPIO port D. */ | ||
| 42 | #define EP93XX_GPIO_LINE_D(x) ((x) + 24) | ||
| 43 | #define EP93XX_GPIO_LINE_COL0 EP93XX_GPIO_LINE_D(0) | ||
| 44 | #define EP93XX_GPIO_LINE_COL1 EP93XX_GPIO_LINE_D(1) | ||
| 45 | #define EP93XX_GPIO_LINE_COL2 EP93XX_GPIO_LINE_D(2) | ||
| 46 | #define EP93XX_GPIO_LINE_COL3 EP93XX_GPIO_LINE_D(3) | ||
| 47 | #define EP93XX_GPIO_LINE_COL4 EP93XX_GPIO_LINE_D(4) | ||
| 48 | #define EP93XX_GPIO_LINE_COL5 EP93XX_GPIO_LINE_D(5) | ||
| 49 | #define EP93XX_GPIO_LINE_COL6 EP93XX_GPIO_LINE_D(6) | ||
| 50 | #define EP93XX_GPIO_LINE_COL7 EP93XX_GPIO_LINE_D(7) | ||
| 51 | |||
| 52 | /* GPIO port E. */ | ||
| 53 | #define EP93XX_GPIO_LINE_E(x) ((x) + 32) | ||
| 54 | #define EP93XX_GPIO_LINE_GRLED EP93XX_GPIO_LINE_E(0) | ||
| 55 | #define EP93XX_GPIO_LINE_RDLED EP93XX_GPIO_LINE_E(1) | ||
| 56 | #define EP93XX_GPIO_LINE_DIORn EP93XX_GPIO_LINE_E(2) | ||
| 57 | #define EP93XX_GPIO_LINE_IDECS1n EP93XX_GPIO_LINE_E(3) | ||
| 58 | #define EP93XX_GPIO_LINE_IDECS2n EP93XX_GPIO_LINE_E(4) | ||
| 59 | #define EP93XX_GPIO_LINE_IDEDA0 EP93XX_GPIO_LINE_E(5) | ||
| 60 | #define EP93XX_GPIO_LINE_IDEDA1 EP93XX_GPIO_LINE_E(6) | ||
| 61 | #define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7) | ||
| 62 | |||
| 63 | /* GPIO port F. */ | ||
| 64 | #define EP93XX_GPIO_LINE_F(x) ((x) + 16) | ||
| 65 | #define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0) | ||
| 66 | #define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1) | ||
| 67 | #define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2) | ||
| 68 | #define EP93XX_GPIO_LINE_MCBVD1 EP93XX_GPIO_LINE_F(3) | ||
| 69 | #define EP93XX_GPIO_LINE_MCBVD2 EP93XX_GPIO_LINE_F(4) | ||
| 70 | #define EP93XX_GPIO_LINE_VS1 EP93XX_GPIO_LINE_F(5) | ||
| 71 | #define EP93XX_GPIO_LINE_READY EP93XX_GPIO_LINE_F(6) | ||
| 72 | #define EP93XX_GPIO_LINE_VS2 EP93XX_GPIO_LINE_F(7) | ||
| 73 | |||
| 74 | /* GPIO port G. */ | ||
| 75 | #define EP93XX_GPIO_LINE_G(x) ((x) + 48) | ||
| 76 | #define EP93XX_GPIO_LINE_EECLK EP93XX_GPIO_LINE_G(0) | ||
| 77 | #define EP93XX_GPIO_LINE_EEDAT EP93XX_GPIO_LINE_G(1) | ||
| 78 | #define EP93XX_GPIO_LINE_SLA0 EP93XX_GPIO_LINE_G(2) | ||
| 79 | #define EP93XX_GPIO_LINE_SLA1 EP93XX_GPIO_LINE_G(3) | ||
| 80 | #define EP93XX_GPIO_LINE_DD12 EP93XX_GPIO_LINE_G(4) | ||
| 81 | #define EP93XX_GPIO_LINE_DD13 EP93XX_GPIO_LINE_G(5) | ||
| 82 | #define EP93XX_GPIO_LINE_DD14 EP93XX_GPIO_LINE_G(6) | ||
| 83 | #define EP93XX_GPIO_LINE_DD15 EP93XX_GPIO_LINE_G(7) | ||
| 84 | |||
| 85 | /* GPIO port H. */ | ||
| 86 | #define EP93XX_GPIO_LINE_H(x) ((x) + 56) | ||
| 87 | #define EP93XX_GPIO_LINE_DD0 EP93XX_GPIO_LINE_H(0) | ||
| 88 | #define EP93XX_GPIO_LINE_DD1 EP93XX_GPIO_LINE_H(1) | ||
| 89 | #define EP93XX_GPIO_LINE_DD2 EP93XX_GPIO_LINE_H(2) | ||
| 90 | #define EP93XX_GPIO_LINE_DD3 EP93XX_GPIO_LINE_H(3) | ||
| 91 | #define EP93XX_GPIO_LINE_DD4 EP93XX_GPIO_LINE_H(4) | ||
| 92 | #define EP93XX_GPIO_LINE_DD5 EP93XX_GPIO_LINE_H(5) | ||
| 93 | #define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6) | ||
| 94 | #define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7) | ||
| 95 | |||
| 96 | /* maximum value for gpio line identifiers */ | ||
| 97 | #define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7) | ||
| 98 | |||
| 99 | /* maximum value for irq capable line identifiers */ | ||
| 100 | #define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7) | ||
| 101 | |||
| 102 | /* new generic GPIO API - see Documentation/gpio.txt */ | ||
| 103 | |||
| 104 | #include <asm-generic/gpio.h> | ||
| 105 | |||
| 106 | #define gpio_get_value __gpio_get_value | ||
| 107 | #define gpio_set_value __gpio_set_value | ||
| 108 | #define gpio_cansleep __gpio_cansleep | ||
| 109 | |||
| 110 | /* | ||
| 111 | * Map GPIO A0..A7 (0..7) to irq 64..71, | ||
| 112 | * B0..B7 (7..15) to irq 72..79, and | ||
| 113 | * F0..F7 (16..24) to irq 80..87. | ||
| 114 | */ | ||
| 115 | static inline int gpio_to_irq(unsigned gpio) | ||
| 116 | { | ||
| 117 | if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ) | ||
| 118 | return 64 + gpio; | ||
| 119 | |||
| 120 | return -EINVAL; | ||
| 121 | } | ||
| 122 | |||
| 123 | static inline int irq_to_gpio(unsigned irq) | ||
| 124 | { | ||
| 125 | return irq - gpio_to_irq(0); | ||
| 126 | } | ||
| 127 | |||
| 128 | #endif | ||
diff --git a/include/asm-arm/arch-ep93xx/hardware.h b/include/asm-arm/arch-ep93xx/hardware.h deleted file mode 100644 index 4233f6e85150..000000000000 --- a/include/asm-arm/arch-ep93xx/hardware.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/hardware.h | ||
| 3 | */ | ||
| 4 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 5 | #define __ASM_ARCH_HARDWARE_H | ||
| 6 | |||
| 7 | #include "ep93xx-regs.h" | ||
| 8 | |||
| 9 | #define pcibios_assign_all_busses() 0 | ||
| 10 | |||
| 11 | #include "platform.h" | ||
| 12 | |||
| 13 | #include "gesbc9312.h" | ||
| 14 | #include "ts72xx.h" | ||
| 15 | |||
| 16 | #endif | ||
diff --git a/include/asm-arm/arch-ep93xx/io.h b/include/asm-arm/arch-ep93xx/io.h deleted file mode 100644 index 7b4d25e29060..000000000000 --- a/include/asm-arm/arch-ep93xx/io.h +++ /dev/null | |||
| @@ -1,8 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/io.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 6 | |||
| 7 | #define __io(p) ((void __iomem *)(p)) | ||
| 8 | #define __mem_pci(p) (p) | ||
diff --git a/include/asm-arm/arch-ep93xx/irqs.h b/include/asm-arm/arch-ep93xx/irqs.h deleted file mode 100644 index 53d4a68bfc88..000000000000 --- a/include/asm-arm/arch-ep93xx/irqs.h +++ /dev/null | |||
| @@ -1,78 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/irqs.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_ARCH_IRQS_H | ||
| 6 | #define __ASM_ARCH_IRQS_H | ||
| 7 | |||
| 8 | #define IRQ_EP93XX_COMMRX 2 | ||
| 9 | #define IRQ_EP93XX_COMMTX 3 | ||
| 10 | #define IRQ_EP93XX_TIMER1 4 | ||
| 11 | #define IRQ_EP93XX_TIMER2 5 | ||
| 12 | #define IRQ_EP93XX_AACINTR 6 | ||
| 13 | #define IRQ_EP93XX_DMAM2P0 7 | ||
| 14 | #define IRQ_EP93XX_DMAM2P1 8 | ||
| 15 | #define IRQ_EP93XX_DMAM2P2 9 | ||
| 16 | #define IRQ_EP93XX_DMAM2P3 10 | ||
| 17 | #define IRQ_EP93XX_DMAM2P4 11 | ||
| 18 | #define IRQ_EP93XX_DMAM2P5 12 | ||
| 19 | #define IRQ_EP93XX_DMAM2P6 13 | ||
| 20 | #define IRQ_EP93XX_DMAM2P7 14 | ||
| 21 | #define IRQ_EP93XX_DMAM2P8 15 | ||
| 22 | #define IRQ_EP93XX_DMAM2P9 16 | ||
| 23 | #define IRQ_EP93XX_DMAM2M0 17 | ||
| 24 | #define IRQ_EP93XX_DMAM2M1 18 | ||
| 25 | #define IRQ_EP93XX_GPIO0MUX 19 | ||
| 26 | #define IRQ_EP93XX_GPIO1MUX 20 | ||
| 27 | #define IRQ_EP93XX_GPIO2MUX 21 | ||
| 28 | #define IRQ_EP93XX_GPIO3MUX 22 | ||
| 29 | #define IRQ_EP93XX_UART1RX 23 | ||
| 30 | #define IRQ_EP93XX_UART1TX 24 | ||
| 31 | #define IRQ_EP93XX_UART2RX 25 | ||
| 32 | #define IRQ_EP93XX_UART2TX 26 | ||
| 33 | #define IRQ_EP93XX_UART3RX 27 | ||
| 34 | #define IRQ_EP93XX_UART3TX 28 | ||
| 35 | #define IRQ_EP93XX_KEY 29 | ||
| 36 | #define IRQ_EP93XX_TOUCH 30 | ||
| 37 | #define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc | ||
| 38 | |||
| 39 | #define IRQ_EP93XX_EXT0 32 | ||
| 40 | #define IRQ_EP93XX_EXT1 33 | ||
| 41 | #define IRQ_EP93XX_EXT2 34 | ||
| 42 | #define IRQ_EP93XX_64HZ 35 | ||
| 43 | #define IRQ_EP93XX_WATCHDOG 36 | ||
| 44 | #define IRQ_EP93XX_RTC 37 | ||
| 45 | #define IRQ_EP93XX_IRDA 38 | ||
| 46 | #define IRQ_EP93XX_ETHERNET 39 | ||
| 47 | #define IRQ_EP93XX_EXT3 40 | ||
| 48 | #define IRQ_EP93XX_PROG 41 | ||
| 49 | #define IRQ_EP93XX_1HZ 42 | ||
| 50 | #define IRQ_EP93XX_VSYNC 43 | ||
| 51 | #define IRQ_EP93XX_VIDEO_FIFO 44 | ||
| 52 | #define IRQ_EP93XX_SSP1RX 45 | ||
| 53 | #define IRQ_EP93XX_SSP1TX 46 | ||
| 54 | #define IRQ_EP93XX_GPIO4MUX 47 | ||
| 55 | #define IRQ_EP93XX_GPIO5MUX 48 | ||
| 56 | #define IRQ_EP93XX_GPIO6MUX 49 | ||
| 57 | #define IRQ_EP93XX_GPIO7MUX 50 | ||
| 58 | #define IRQ_EP93XX_TIMER3 51 | ||
| 59 | #define IRQ_EP93XX_UART1 52 | ||
| 60 | #define IRQ_EP93XX_SSP 53 | ||
| 61 | #define IRQ_EP93XX_UART2 54 | ||
| 62 | #define IRQ_EP93XX_UART3 55 | ||
| 63 | #define IRQ_EP93XX_USB 56 | ||
| 64 | #define IRQ_EP93XX_ETHERNET_PME 57 | ||
| 65 | #define IRQ_EP93XX_DSP 58 | ||
| 66 | #define IRQ_EP93XX_GPIO_AB 59 | ||
| 67 | #define IRQ_EP93XX_SAI 60 | ||
| 68 | #define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff | ||
| 69 | |||
| 70 | #define NR_EP93XX_IRQS (64 + 24) | ||
| 71 | |||
| 72 | #define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) | ||
| 73 | #define EP93XX_BOARD_IRQS 32 | ||
| 74 | |||
| 75 | #define NR_IRQS (NR_EP93XX_IRQS + EP93XX_BOARD_IRQS) | ||
| 76 | |||
| 77 | |||
| 78 | #endif | ||
diff --git a/include/asm-arm/arch-ep93xx/memory.h b/include/asm-arm/arch-ep93xx/memory.h deleted file mode 100644 index 4b1a5c7c8363..000000000000 --- a/include/asm-arm/arch-ep93xx/memory.h +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/memory.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 6 | #define __ASM_ARCH_MEMORY_H | ||
| 7 | |||
| 8 | #define PHYS_OFFSET UL(0x00000000) | ||
| 9 | |||
| 10 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 11 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 12 | |||
| 13 | |||
| 14 | #endif | ||
diff --git a/include/asm-arm/arch-ep93xx/platform.h b/include/asm-arm/arch-ep93xx/platform.h deleted file mode 100644 index 44eccec2cba4..000000000000 --- a/include/asm-arm/arch-ep93xx/platform.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/platform.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASSEMBLY__ | ||
| 6 | |||
| 7 | void ep93xx_map_io(void); | ||
| 8 | void ep93xx_init_irq(void); | ||
| 9 | void ep93xx_init_time(unsigned long); | ||
| 10 | void ep93xx_init_devices(void); | ||
| 11 | extern struct sys_timer ep93xx_timer; | ||
| 12 | |||
| 13 | struct ep93xx_eth_data | ||
| 14 | { | ||
| 15 | unsigned char dev_addr[6]; | ||
| 16 | unsigned char phy_id; | ||
| 17 | }; | ||
| 18 | |||
| 19 | |||
| 20 | #endif | ||
diff --git a/include/asm-arm/arch-ep93xx/system.h b/include/asm-arm/arch-ep93xx/system.h deleted file mode 100644 index f1a5acf51919..000000000000 --- a/include/asm-arm/arch-ep93xx/system.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/system.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #include <asm/arch/hardware.h> | ||
| 6 | |||
| 7 | static inline void arch_idle(void) | ||
| 8 | { | ||
| 9 | cpu_do_idle(); | ||
| 10 | } | ||
| 11 | |||
| 12 | static inline void arch_reset(char mode) | ||
| 13 | { | ||
| 14 | u32 devicecfg; | ||
| 15 | |||
| 16 | local_irq_disable(); | ||
| 17 | |||
| 18 | devicecfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG); | ||
| 19 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | ||
| 20 | __raw_writel(devicecfg | 0x80000000, EP93XX_SYSCON_DEVICE_CONFIG); | ||
| 21 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | ||
| 22 | __raw_writel(devicecfg & ~0x80000000, EP93XX_SYSCON_DEVICE_CONFIG); | ||
| 23 | |||
| 24 | while (1) | ||
| 25 | ; | ||
| 26 | } | ||
diff --git a/include/asm-arm/arch-ep93xx/timex.h b/include/asm-arm/arch-ep93xx/timex.h deleted file mode 100644 index 4140bddc97e2..000000000000 --- a/include/asm-arm/arch-ep93xx/timex.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/timex.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define CLOCK_TICK_RATE 983040 | ||
diff --git a/include/asm-arm/arch-ep93xx/ts72xx.h b/include/asm-arm/arch-ep93xx/ts72xx.h deleted file mode 100644 index a94f63ff0535..000000000000 --- a/include/asm-arm/arch-ep93xx/ts72xx.h +++ /dev/null | |||
| @@ -1,101 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/ts72xx.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * TS72xx memory map: | ||
| 7 | * | ||
| 8 | * virt phys size | ||
| 9 | * febff000 22000000 4K model number register | ||
| 10 | * febfe000 22400000 4K options register | ||
| 11 | * febfd000 22800000 4K options register #2 | ||
| 12 | * febfc000 [67]0000000 4K NAND data register | ||
| 13 | * febfb000 [67]0400000 4K NAND control register | ||
| 14 | * febfa000 [67]0800000 4K NAND busy register | ||
| 15 | * febf9000 10800000 4K TS-5620 RTC index register | ||
| 16 | * febf8000 11700000 4K TS-5620 RTC data register | ||
| 17 | */ | ||
| 18 | |||
| 19 | #define TS72XX_MODEL_PHYS_BASE 0x22000000 | ||
| 20 | #define TS72XX_MODEL_VIRT_BASE 0xfebff000 | ||
| 21 | #define TS72XX_MODEL_SIZE 0x00001000 | ||
| 22 | |||
| 23 | #define TS72XX_MODEL_TS7200 0x00 | ||
| 24 | #define TS72XX_MODEL_TS7250 0x01 | ||
| 25 | #define TS72XX_MODEL_TS7260 0x02 | ||
| 26 | |||
| 27 | |||
| 28 | #define TS72XX_OPTIONS_PHYS_BASE 0x22400000 | ||
| 29 | #define TS72XX_OPTIONS_VIRT_BASE 0xfebfe000 | ||
| 30 | #define TS72XX_OPTIONS_SIZE 0x00001000 | ||
| 31 | |||
| 32 | #define TS72XX_OPTIONS_COM2_RS485 0x02 | ||
| 33 | #define TS72XX_OPTIONS_MAX197 0x01 | ||
| 34 | |||
| 35 | |||
| 36 | #define TS72XX_OPTIONS2_PHYS_BASE 0x22800000 | ||
| 37 | #define TS72XX_OPTIONS2_VIRT_BASE 0xfebfd000 | ||
| 38 | #define TS72XX_OPTIONS2_SIZE 0x00001000 | ||
| 39 | |||
| 40 | #define TS72XX_OPTIONS2_TS9420 0x04 | ||
| 41 | #define TS72XX_OPTIONS2_TS9420_BOOT 0x02 | ||
| 42 | |||
| 43 | |||
| 44 | #define TS72XX_NOR_PHYS_BASE 0x60000000 | ||
| 45 | #define TS72XX_NOR2_PHYS_BASE 0x62000000 | ||
| 46 | |||
| 47 | #define TS72XX_NAND1_DATA_PHYS_BASE 0x60000000 | ||
| 48 | #define TS72XX_NAND2_DATA_PHYS_BASE 0x70000000 | ||
| 49 | #define TS72XX_NAND_DATA_VIRT_BASE 0xfebfc000 | ||
| 50 | #define TS72XX_NAND_DATA_SIZE 0x00001000 | ||
| 51 | |||
| 52 | #define TS72XX_NAND1_CONTROL_PHYS_BASE 0x60400000 | ||
| 53 | #define TS72XX_NAND2_CONTROL_PHYS_BASE 0x70400000 | ||
| 54 | #define TS72XX_NAND_CONTROL_VIRT_BASE 0xfebfb000 | ||
| 55 | #define TS72XX_NAND_CONTROL_SIZE 0x00001000 | ||
| 56 | |||
| 57 | #define TS72XX_NAND1_BUSY_PHYS_BASE 0x60800000 | ||
| 58 | #define TS72XX_NAND2_BUSY_PHYS_BASE 0x70800000 | ||
| 59 | #define TS72XX_NAND_BUSY_VIRT_BASE 0xfebfa000 | ||
| 60 | #define TS72XX_NAND_BUSY_SIZE 0x00001000 | ||
| 61 | |||
| 62 | |||
| 63 | #define TS72XX_RTC_INDEX_VIRT_BASE 0xfebf9000 | ||
| 64 | #define TS72XX_RTC_INDEX_PHYS_BASE 0x10800000 | ||
| 65 | #define TS72XX_RTC_INDEX_SIZE 0x00001000 | ||
| 66 | |||
| 67 | #define TS72XX_RTC_DATA_VIRT_BASE 0xfebf8000 | ||
| 68 | #define TS72XX_RTC_DATA_PHYS_BASE 0x11700000 | ||
| 69 | #define TS72XX_RTC_DATA_SIZE 0x00001000 | ||
| 70 | |||
| 71 | |||
| 72 | #ifndef __ASSEMBLY__ | ||
| 73 | #include <asm/io.h> | ||
| 74 | |||
| 75 | static inline int board_is_ts7200(void) | ||
| 76 | { | ||
| 77 | return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200; | ||
| 78 | } | ||
| 79 | |||
| 80 | static inline int board_is_ts7250(void) | ||
| 81 | { | ||
| 82 | return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250; | ||
| 83 | } | ||
| 84 | |||
| 85 | static inline int board_is_ts7260(void) | ||
| 86 | { | ||
| 87 | return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260; | ||
| 88 | } | ||
| 89 | |||
| 90 | static inline int is_max197_installed(void) | ||
| 91 | { | ||
| 92 | return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) & | ||
| 93 | TS72XX_OPTIONS_MAX197); | ||
| 94 | } | ||
| 95 | |||
| 96 | static inline int is_ts9420_installed(void) | ||
| 97 | { | ||
| 98 | return !!(__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) & | ||
| 99 | TS72XX_OPTIONS2_TS9420); | ||
| 100 | } | ||
| 101 | #endif | ||
diff --git a/include/asm-arm/arch-ep93xx/uncompress.h b/include/asm-arm/arch-ep93xx/uncompress.h deleted file mode 100644 index c15274c85d5d..000000000000 --- a/include/asm-arm/arch-ep93xx/uncompress.h +++ /dev/null | |||
| @@ -1,85 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or (at | ||
| 9 | * your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <asm/arch/ep93xx-regs.h> | ||
| 13 | |||
| 14 | static unsigned char __raw_readb(unsigned int ptr) | ||
| 15 | { | ||
| 16 | return *((volatile unsigned char *)ptr); | ||
| 17 | } | ||
| 18 | |||
| 19 | static unsigned int __raw_readl(unsigned int ptr) | ||
| 20 | { | ||
| 21 | return *((volatile unsigned int *)ptr); | ||
| 22 | } | ||
| 23 | |||
| 24 | static void __raw_writeb(unsigned char value, unsigned int ptr) | ||
| 25 | { | ||
| 26 | *((volatile unsigned char *)ptr) = value; | ||
| 27 | } | ||
| 28 | |||
| 29 | static void __raw_writel(unsigned int value, unsigned int ptr) | ||
| 30 | { | ||
| 31 | *((volatile unsigned int *)ptr) = value; | ||
| 32 | } | ||
| 33 | |||
| 34 | |||
| 35 | #define PHYS_UART1_DATA 0x808c0000 | ||
| 36 | #define PHYS_UART1_FLAG 0x808c0018 | ||
| 37 | #define UART1_FLAG_TXFF 0x20 | ||
| 38 | |||
| 39 | static inline void putc(int c) | ||
| 40 | { | ||
| 41 | int i; | ||
| 42 | |||
| 43 | for (i = 0; i < 1000; i++) { | ||
| 44 | /* Transmit fifo not full? */ | ||
| 45 | if (!(__raw_readb(PHYS_UART1_FLAG) & UART1_FLAG_TXFF)) | ||
| 46 | break; | ||
| 47 | } | ||
| 48 | |||
| 49 | __raw_writeb(c, PHYS_UART1_DATA); | ||
| 50 | } | ||
| 51 | |||
| 52 | static inline void flush(void) | ||
| 53 | { | ||
| 54 | } | ||
| 55 | |||
| 56 | |||
| 57 | /* | ||
| 58 | * Some bootloaders don't turn off DMA from the ethernet MAC before | ||
| 59 | * jumping to linux, which means that we might end up with bits of RX | ||
| 60 | * status and packet data scribbled over the uncompressed kernel image. | ||
| 61 | * Work around this by resetting the ethernet MAC before we uncompress. | ||
| 62 | */ | ||
| 63 | #define PHYS_ETH_SELF_CTL 0x80010020 | ||
| 64 | #define ETH_SELF_CTL_RESET 0x00000001 | ||
| 65 | |||
| 66 | static void ethernet_reset(void) | ||
| 67 | { | ||
| 68 | unsigned int v; | ||
| 69 | |||
| 70 | /* Reset the ethernet MAC. */ | ||
| 71 | v = __raw_readl(PHYS_ETH_SELF_CTL); | ||
| 72 | __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL); | ||
| 73 | |||
| 74 | /* Wait for reset to finish. */ | ||
| 75 | while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET) | ||
| 76 | ; | ||
| 77 | } | ||
| 78 | |||
| 79 | |||
| 80 | static void arch_decomp_setup(void) | ||
| 81 | { | ||
| 82 | ethernet_reset(); | ||
| 83 | } | ||
| 84 | |||
| 85 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-ep93xx/vmalloc.h b/include/asm-arm/arch-ep93xx/vmalloc.h deleted file mode 100644 index 205ea6b1cf5e..000000000000 --- a/include/asm-arm/arch-ep93xx/vmalloc.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ep93xx/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define VMALLOC_END 0xfe800000 | ||
diff --git a/include/asm-arm/arch-h720x/boards.h b/include/asm-arm/arch-h720x/boards.h deleted file mode 100644 index 8021f81f0742..000000000000 --- a/include/asm-arm/arch-h720x/boards.h +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/boards.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
| 5 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
| 6 | * | ||
| 7 | * This file contains the board specific defines for various devices | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_HARDWARE_INCMACH_H | ||
| 15 | #error Do not include this file directly. Include asm/hardware.h instead ! | ||
| 16 | #endif | ||
| 17 | |||
| 18 | /* Hynix H7202 developer board specific device defines */ | ||
| 19 | #ifdef CONFIG_ARCH_H7202 | ||
| 20 | |||
| 21 | /* FLASH */ | ||
| 22 | #define FLASH_VIRT 0xd0000000 | ||
| 23 | #define FLASH_PHYS 0x00000000 | ||
| 24 | #define FLASH_SIZE 0x02000000 | ||
| 25 | |||
| 26 | /* onboard LAN controller */ | ||
| 27 | # define ETH0_PHYS 0x08000000 | ||
| 28 | |||
| 29 | /* Touch screen defines */ | ||
| 30 | /* GPIO Port */ | ||
| 31 | #define PEN_GPIO GPIO_B_VIRT | ||
| 32 | /* Bitmask for pen down interrupt */ | ||
| 33 | #define PEN_INT_BIT (1<<7) | ||
| 34 | /* Bitmask for pen up interrupt */ | ||
| 35 | #define PEN_ENA_BIT (1<<6) | ||
| 36 | /* pen up interrupt */ | ||
| 37 | #define IRQ_PEN IRQ_MUX_GPIOB(7) | ||
| 38 | |||
| 39 | #endif | ||
| 40 | |||
| 41 | /* Hynix H7201 developer board specific device defines */ | ||
| 42 | #if defined (CONFIG_ARCH_H7201) | ||
| 43 | /* ROM DISK SPACE */ | ||
| 44 | #define ROM_DISK_BASE 0xc1800000 | ||
| 45 | #define ROM_DISK_START 0x41800000 | ||
| 46 | #define ROM_DISK_SIZE 0x00700000 | ||
| 47 | |||
| 48 | /* SRAM DISK SPACE */ | ||
| 49 | #define SRAM_DISK_BASE 0xf1000000 | ||
| 50 | #define SRAM_DISK_START 0x04000000 | ||
| 51 | #define SRAM_DISK_SIZE 0x00400000 | ||
| 52 | #endif | ||
| 53 | |||
diff --git a/include/asm-arm/arch-h720x/debug-macro.S b/include/asm-arm/arch-h720x/debug-macro.S deleted file mode 100644 index 82822d362733..000000000000 --- a/include/asm-arm/arch-h720x/debug-macro.S +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-h720x/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .equ io_virt, IO_BASE | ||
| 15 | .equ io_phys, IO_START | ||
| 16 | |||
| 17 | .macro addruart,rx | ||
| 18 | mrc p15, 0, \rx, c1, c0 | ||
| 19 | tst \rx, #1 @ MMU enabled? | ||
| 20 | moveq \rx, #io_phys @ physical base address | ||
| 21 | movne \rx, #io_virt @ virtual address | ||
| 22 | add \rx, \rx, #0x00020000 @ UART1 | ||
| 23 | .endm | ||
| 24 | |||
| 25 | .macro senduart,rd,rx | ||
| 26 | str \rd, [\rx, #0x0] @ UARTDR | ||
| 27 | |||
| 28 | .endm | ||
| 29 | |||
| 30 | .macro waituart,rd,rx | ||
| 31 | 1001: ldr \rd, [\rx, #0x18] @ UARTFLG | ||
| 32 | tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full | ||
| 33 | bne 1001b | ||
| 34 | .endm | ||
| 35 | |||
| 36 | .macro busyuart,rd,rx | ||
| 37 | 1001: ldr \rd, [\rx, #0x18] @ UARTFLG | ||
| 38 | tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy | ||
| 39 | bne 1001b | ||
| 40 | .endm | ||
diff --git a/include/asm-arm/arch-h720x/dma.h b/include/asm-arm/arch-h720x/dma.h deleted file mode 100644 index bfc6636679f7..000000000000 --- a/include/asm-arm/arch-h720x/dma.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/dma.h | ||
| 3 | * | ||
| 4 | * Architecture DMA routes | ||
| 5 | * | ||
| 6 | * Copyright (C) 1997.1998 Russell King | ||
| 7 | */ | ||
| 8 | #ifndef __ASM_ARCH_DMA_H | ||
| 9 | #define __ASM_ARCH_DMA_H | ||
| 10 | |||
| 11 | /* | ||
| 12 | * This is the maximum DMA address that can be DMAd to. | ||
| 13 | * There should not be more than (0xd0000000 - 0xc0000000) | ||
| 14 | * bytes of RAM. | ||
| 15 | */ | ||
| 16 | #define MAX_DMA_ADDRESS 0xd0000000 | ||
| 17 | |||
| 18 | #if defined (CONFIG_CPU_H7201) | ||
| 19 | #define MAX_DMA_CHANNELS 3 | ||
| 20 | #elif defined (CONFIG_CPU_H7202) | ||
| 21 | #define MAX_DMA_CHANNELS 4 | ||
| 22 | #else | ||
| 23 | #error processor definition missmatch | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #endif /* __ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-h720x/entry-macro.S b/include/asm-arm/arch-h720x/entry-macro.S deleted file mode 100644 index 38dd63ae104e..000000000000 --- a/include/asm-arm/arch-h720x/entry-macro.S +++ /dev/null | |||
| @@ -1,66 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-h720x/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for Hynix HMS720x based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | .macro disable_fiq | ||
| 12 | .endm | ||
| 13 | |||
| 14 | .macro get_irqnr_preamble, base, tmp | ||
| 15 | .endm | ||
| 16 | |||
| 17 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 18 | .endm | ||
| 19 | |||
| 20 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 21 | #if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202) | ||
| 22 | @ we could use the id register on H7202, but this is not | ||
| 23 | @ properly updated when we come back from asm_do_irq | ||
| 24 | @ without a previous return from interrupt | ||
| 25 | @ (see loops below in irq_svc, irq_usr) | ||
| 26 | @ We see unmasked pending ints only, as the masked pending ints | ||
| 27 | @ are not visible here | ||
| 28 | |||
| 29 | mov \base, #0xf0000000 @ base register | ||
| 30 | orr \base, \base, #0x24000 @ irqbase | ||
| 31 | ldr \irqstat, [\base, #0x04] @ get interrupt status | ||
| 32 | #if defined (CONFIG_CPU_H7201) | ||
| 33 | ldr \tmp, =0x001fffff | ||
| 34 | #else | ||
| 35 | mvn \tmp, #0xc0000000 | ||
| 36 | #endif | ||
| 37 | and \irqstat, \irqstat, \tmp @ mask out unused ints | ||
| 38 | mov \irqnr, #0 | ||
| 39 | |||
| 40 | mov \tmp, #0xff00 | ||
| 41 | orr \tmp, \tmp, #0xff | ||
| 42 | tst \irqstat, \tmp | ||
| 43 | addeq \irqnr, \irqnr, #16 | ||
| 44 | moveq \irqstat, \irqstat, lsr #16 | ||
| 45 | tst \irqstat, #255 | ||
| 46 | addeq \irqnr, \irqnr, #8 | ||
| 47 | moveq \irqstat, \irqstat, lsr #8 | ||
| 48 | tst \irqstat, #15 | ||
| 49 | addeq \irqnr, \irqnr, #4 | ||
| 50 | moveq \irqstat, \irqstat, lsr #4 | ||
| 51 | tst \irqstat, #3 | ||
| 52 | addeq \irqnr, \irqnr, #2 | ||
| 53 | moveq \irqstat, \irqstat, lsr #2 | ||
| 54 | tst \irqstat, #1 | ||
| 55 | addeq \irqnr, \irqnr, #1 | ||
| 56 | moveq \irqstat, \irqstat, lsr #1 | ||
| 57 | tst \irqstat, #1 @ bit 0 should be set | ||
| 58 | .endm | ||
| 59 | |||
| 60 | .macro irq_prio_table | ||
| 61 | .endm | ||
| 62 | |||
| 63 | #else | ||
| 64 | #error hynix processor selection missmatch | ||
| 65 | #endif | ||
| 66 | |||
diff --git a/include/asm-arm/arch-h720x/h7201-regs.h b/include/asm-arm/arch-h720x/h7201-regs.h deleted file mode 100644 index 49d4f6bd3080..000000000000 --- a/include/asm-arm/arch-h720x/h7201-regs.h +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/h7201-regs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. | ||
| 5 | * (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
| 6 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
| 7 | * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de> | ||
| 8 | * | ||
| 9 | * This file contains the hardware definitions of the h720x processors | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | * | ||
| 15 | * Do not add implementations specific defines here. This files contains | ||
| 16 | * only defines of the onchip peripherals. Add those defines to boards.h, | ||
| 17 | * which is included by this file. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define SERIAL2_VIRT (IO_VIRT + 0x50100) | ||
| 21 | #define SERIAL3_VIRT (IO_VIRT + 0x50200) | ||
| 22 | |||
| 23 | /* | ||
| 24 | * PCMCIA | ||
| 25 | */ | ||
| 26 | #define PCMCIA0_ATT_BASE 0xe5000000 | ||
| 27 | #define PCMCIA0_ATT_SIZE 0x00200000 | ||
| 28 | #define PCMCIA0_ATT_START 0x20000000 | ||
| 29 | #define PCMCIA0_MEM_BASE 0xe5200000 | ||
| 30 | #define PCMCIA0_MEM_SIZE 0x00200000 | ||
| 31 | #define PCMCIA0_MEM_START 0x24000000 | ||
| 32 | #define PCMCIA0_IO_BASE 0xe5400000 | ||
| 33 | #define PCMCIA0_IO_SIZE 0x00200000 | ||
| 34 | #define PCMCIA0_IO_START 0x28000000 | ||
| 35 | |||
| 36 | #define PCMCIA1_ATT_BASE 0xe5600000 | ||
| 37 | #define PCMCIA1_ATT_SIZE 0x00200000 | ||
| 38 | #define PCMCIA1_ATT_START 0x30000000 | ||
| 39 | #define PCMCIA1_MEM_BASE 0xe5800000 | ||
| 40 | #define PCMCIA1_MEM_SIZE 0x00200000 | ||
| 41 | #define PCMCIA1_MEM_START 0x34000000 | ||
| 42 | #define PCMCIA1_IO_BASE 0xe5a00000 | ||
| 43 | #define PCMCIA1_IO_SIZE 0x00200000 | ||
| 44 | #define PCMCIA1_IO_START 0x38000000 | ||
| 45 | |||
| 46 | #define PRIME3C_BASE 0xf0050000 | ||
| 47 | #define PRIME3C_SIZE 0x00001000 | ||
| 48 | #define PRIME3C_START 0x10000000 | ||
| 49 | |||
| 50 | /* VGA Controller */ | ||
| 51 | #define VGA_RAMBASE 0x50 | ||
| 52 | #define VGA_TIMING0 0x60 | ||
| 53 | #define VGA_TIMING1 0x64 | ||
| 54 | #define VGA_TIMING2 0x68 | ||
| 55 | #define VGA_TIMING3 0x6c | ||
| 56 | |||
| 57 | #define LCD_CTRL_VGA_ENABLE 0x00000100 | ||
| 58 | #define LCD_CTRL_VGA_BPP_MASK 0x00000600 | ||
| 59 | #define LCD_CTRL_VGA_4BPP 0x00000000 | ||
| 60 | #define LCD_CTRL_VGA_8BPP 0x00000200 | ||
| 61 | #define LCD_CTRL_VGA_16BPP 0x00000300 | ||
| 62 | #define LCD_CTRL_SHARE_DMA 0x00000800 | ||
| 63 | #define LCD_CTRL_VDE 0x00100000 | ||
| 64 | #define LCD_CTRL_LPE 0x00400000 /* LCD Power enable */ | ||
| 65 | #define LCD_CTRL_BLE 0x00800000 /* LCD backlight enable */ | ||
| 66 | |||
| 67 | #define VGA_PALETTE_BASE (IO_VIRT + 0x10800) | ||
diff --git a/include/asm-arm/arch-h720x/h7202-regs.h b/include/asm-arm/arch-h720x/h7202-regs.h deleted file mode 100644 index 43d8ba8a6013..000000000000 --- a/include/asm-arm/arch-h720x/h7202-regs.h +++ /dev/null | |||
| @@ -1,155 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/h7202-regs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. | ||
| 5 | * (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
| 6 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
| 7 | * (C) 2004 Sascha Hauer <s.hauer@pengutronix.de> | ||
| 8 | * | ||
| 9 | * This file contains the hardware definitions of the h720x processors | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | * | ||
| 15 | * Do not add implementations specific defines here. This files contains | ||
| 16 | * only defines of the onchip peripherals. Add those defines to boards.h, | ||
| 17 | * which is included by this file. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define SERIAL2_OFS 0x2d000 | ||
| 21 | #define SERIAL2_BASE (IO_PHYS + SERIAL2_OFS) | ||
| 22 | #define SERIAL2_VIRT (IO_VIRT + SERIAL2_OFS) | ||
| 23 | #define SERIAL3_OFS 0x2e000 | ||
| 24 | #define SERIAL3_BASE (IO_PHYS + SERIAL3_OFS) | ||
| 25 | #define SERIAL3_VIRT (IO_VIRT + SERIAL3_OFS) | ||
| 26 | |||
| 27 | /* Matrix Keyboard Controller */ | ||
| 28 | #define KBD_VIRT (IO_VIRT + 0x22000) | ||
| 29 | #define KBD_KBCR 0x00 | ||
| 30 | #define KBD_KBSC 0x04 | ||
| 31 | #define KBD_KBTR 0x08 | ||
| 32 | #define KBD_KBVR0 0x0C | ||
| 33 | #define KBD_KBVR1 0x10 | ||
| 34 | #define KBD_KBSR 0x18 | ||
| 35 | |||
| 36 | #define KBD_KBCR_SCANENABLE (1 << 7) | ||
| 37 | #define KBD_KBCR_NPOWERDOWN (1 << 2) | ||
| 38 | #define KBD_KBCR_CLKSEL_MASK (3) | ||
| 39 | #define KBD_KBCR_CLKSEL_PCLK2 0x0 | ||
| 40 | #define KBD_KBCR_CLKSEL_PCLK128 0x1 | ||
| 41 | #define KBD_KBCR_CLKSEL_PCLK256 0x2 | ||
| 42 | #define KBD_KBCR_CLKSEL_PCLK512 0x3 | ||
| 43 | |||
| 44 | #define KBD_KBSR_INTR (1 << 0) | ||
| 45 | #define KBD_KBSR_WAKEUP (1 << 1) | ||
| 46 | |||
| 47 | /* USB device controller */ | ||
| 48 | |||
| 49 | #define USBD_BASE (IO_VIRT + 0x12000) | ||
| 50 | #define USBD_LENGTH 0x3C | ||
| 51 | |||
| 52 | #define USBD_GCTRL 0x00 | ||
| 53 | #define USBD_EPCTRL 0x04 | ||
| 54 | #define USBD_INTMASK 0x08 | ||
| 55 | #define USBD_INTSTAT 0x0C | ||
| 56 | #define USBD_PWR 0x10 | ||
| 57 | #define USBD_DMARXTX 0x14 | ||
| 58 | #define USBD_DEVID 0x18 | ||
| 59 | #define USBD_DEVCLASS 0x1C | ||
| 60 | #define USBD_INTCLASS 0x20 | ||
| 61 | #define USBD_SETUP0 0x24 | ||
| 62 | #define USBD_SETUP1 0x28 | ||
| 63 | #define USBD_ENDP0RD 0x2C | ||
| 64 | #define USBD_ENDP0WT 0x30 | ||
| 65 | #define USBD_ENDP1RD 0x34 | ||
| 66 | #define USBD_ENDP2WT 0x38 | ||
| 67 | |||
| 68 | /* PS/2 port */ | ||
| 69 | #define PSDATA 0x00 | ||
| 70 | #define PSSTAT 0x04 | ||
| 71 | #define PSSTAT_TXEMPTY (1<<0) | ||
| 72 | #define PSSTAT_TXBUSY (1<<1) | ||
| 73 | #define PSSTAT_RXFULL (1<<2) | ||
| 74 | #define PSSTAT_RXBUSY (1<<3) | ||
| 75 | #define PSSTAT_CLKIN (1<<4) | ||
| 76 | #define PSSTAT_DATAIN (1<<5) | ||
| 77 | #define PSSTAT_PARITY (1<<6) | ||
| 78 | |||
| 79 | #define PSCONF 0x08 | ||
| 80 | #define PSCONF_ENABLE (1<<0) | ||
| 81 | #define PSCONF_TXINTEN (1<<2) | ||
| 82 | #define PSCONF_RXINTEN (1<<3) | ||
| 83 | #define PSCONF_FORCECLKLOW (1<<4) | ||
| 84 | #define PSCONF_FORCEDATLOW (1<<5) | ||
| 85 | #define PSCONF_LCE (1<<6) | ||
| 86 | |||
| 87 | #define PSINTR 0x0C | ||
| 88 | #define PSINTR_TXINT (1<<0) | ||
| 89 | #define PSINTR_RXINT (1<<1) | ||
| 90 | #define PSINTR_PAR (1<<2) | ||
| 91 | #define PSINTR_RXTO (1<<3) | ||
| 92 | #define PSINTR_TXTO (1<<4) | ||
| 93 | |||
| 94 | #define PSTDLO 0x10 /* clk low before start transmission */ | ||
| 95 | #define PSTPRI 0x14 /* PRI clock */ | ||
| 96 | #define PSTXMT 0x18 /* maximum transmission time */ | ||
| 97 | #define PSTREC 0x20 /* maximum receive time */ | ||
| 98 | #define PSPWDN 0x3c | ||
| 99 | |||
| 100 | /* ADC converter */ | ||
| 101 | #define ADC_BASE (IO_VIRT + 0x29000) | ||
| 102 | #define ADC_CR 0x00 | ||
| 103 | #define ADC_TSCTRL 0x04 | ||
| 104 | #define ADC_BT_CTRL 0x08 | ||
| 105 | #define ADC_MC_CTRL 0x0C | ||
| 106 | #define ADC_STATUS 0x10 | ||
| 107 | |||
| 108 | /* ADC control register bits */ | ||
| 109 | #define ADC_CR_PW_CTRL 0x80 | ||
| 110 | #define ADC_CR_DIRECTC 0x04 | ||
| 111 | #define ADC_CR_CONTIME_NO 0x00 | ||
| 112 | #define ADC_CR_CONTIME_2 0x04 | ||
| 113 | #define ADC_CR_CONTIME_4 0x08 | ||
| 114 | #define ADC_CR_CONTIME_ADE 0x0c | ||
| 115 | #define ADC_CR_LONGCALTIME 0x01 | ||
| 116 | |||
| 117 | /* ADC touch panel register bits */ | ||
| 118 | #define ADC_TSCTRL_ENABLE 0x80 | ||
| 119 | #define ADC_TSCTRL_INTR 0x40 | ||
| 120 | #define ADC_TSCTRL_SWBYPSS 0x20 | ||
| 121 | #define ADC_TSCTRL_SWINVT 0x10 | ||
| 122 | #define ADC_TSCTRL_S400 0x03 | ||
| 123 | #define ADC_TSCTRL_S200 0x02 | ||
| 124 | #define ADC_TSCTRL_S100 0x01 | ||
| 125 | #define ADC_TSCTRL_S50 0x00 | ||
| 126 | |||
| 127 | /* ADC Interrupt Status Register bits */ | ||
| 128 | #define ADC_STATUS_TS_BIT 0x80 | ||
| 129 | #define ADC_STATUS_MBT_BIT 0x40 | ||
| 130 | #define ADC_STATUS_BBT_BIT 0x20 | ||
| 131 | #define ADC_STATUS_MIC_BIT 0x10 | ||
| 132 | |||
| 133 | /* Touch data registers */ | ||
| 134 | #define ADC_TS_X0X1 0x30 | ||
| 135 | #define ADC_TS_X2X3 0x34 | ||
| 136 | #define ADC_TS_Y0Y1 0x38 | ||
| 137 | #define ADC_TS_Y2Y3 0x3c | ||
| 138 | #define ADC_TS_X4X5 0x40 | ||
| 139 | #define ADC_TS_X6X7 0x44 | ||
| 140 | #define ADC_TS_Y4Y5 0x48 | ||
| 141 | #define ADC_TS_Y6Y7 0x50 | ||
| 142 | |||
| 143 | /* battery data */ | ||
| 144 | #define ADC_MB_DATA 0x54 | ||
| 145 | #define ADC_BB_DATA 0x58 | ||
| 146 | |||
| 147 | /* Sound data register */ | ||
| 148 | #define ADC_SD_DAT0 0x60 | ||
| 149 | #define ADC_SD_DAT1 0x64 | ||
| 150 | #define ADC_SD_DAT2 0x68 | ||
| 151 | #define ADC_SD_DAT3 0x6c | ||
| 152 | #define ADC_SD_DAT4 0x70 | ||
| 153 | #define ADC_SD_DAT5 0x74 | ||
| 154 | #define ADC_SD_DAT6 0x78 | ||
| 155 | #define ADC_SD_DAT7 0x7c | ||
diff --git a/include/asm-arm/arch-h720x/hardware.h b/include/asm-arm/arch-h720x/hardware.h deleted file mode 100644 index dfb778906a9f..000000000000 --- a/include/asm-arm/arch-h720x/hardware.h +++ /dev/null | |||
| @@ -1,192 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. | ||
| 5 | * (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
| 6 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
| 7 | * | ||
| 8 | * This file contains the hardware definitions of the h720x processors | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * Do not add implementations specific defines here. This files contains | ||
| 15 | * only defines of the onchip peripherals. Add those defines to boards.h, | ||
| 16 | * which is included by this file. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 20 | #define __ASM_ARCH_HARDWARE_H | ||
| 21 | |||
| 22 | #define IOCLK (3686400L) | ||
| 23 | |||
| 24 | /* Onchip peripherals */ | ||
| 25 | |||
| 26 | #define IO_VIRT 0xf0000000 /* IO peripherals */ | ||
| 27 | #define IO_PHYS 0x80000000 | ||
| 28 | #define IO_SIZE 0x00050000 | ||
| 29 | |||
| 30 | #ifdef CONFIG_CPU_H7202 | ||
| 31 | #include "h7202-regs.h" | ||
| 32 | #elif defined CONFIG_CPU_H7201 | ||
| 33 | #include "h7201-regs.h" | ||
| 34 | #else | ||
| 35 | #error machine definition mismatch | ||
| 36 | #endif | ||
| 37 | |||
| 38 | /* Macro to access the CPU IO */ | ||
| 39 | #define CPU_IO(x) (*(volatile u32*)(x)) | ||
| 40 | |||
| 41 | /* Macro to access general purpose regs (base, offset) */ | ||
| 42 | #define CPU_REG(x,y) CPU_IO(x+y) | ||
| 43 | |||
| 44 | /* Macro to access irq related regs */ | ||
| 45 | #define IRQ_REG(x) CPU_REG(IRQC_VIRT,x) | ||
| 46 | |||
| 47 | /* CPU registers */ | ||
| 48 | /* general purpose I/O */ | ||
| 49 | #define GPIO_VIRT(x) (IO_VIRT + 0x23000 + ((x)<<5)) | ||
| 50 | #define GPIO_A_VIRT (GPIO_VIRT(0)) | ||
| 51 | #define GPIO_B_VIRT (GPIO_VIRT(1)) | ||
| 52 | #define GPIO_C_VIRT (GPIO_VIRT(2)) | ||
| 53 | #define GPIO_D_VIRT (GPIO_VIRT(3)) | ||
| 54 | #define GPIO_E_VIRT (GPIO_VIRT(4)) | ||
| 55 | #define GPIO_AMULSEL (GPIO_VIRT(0) + 0xA4) | ||
| 56 | |||
| 57 | #define AMULSEL_USIN2 (1<<5) | ||
| 58 | #define AMULSEL_USOUT2 (1<<6) | ||
| 59 | #define AMULSEL_USIN3 (1<<13) | ||
| 60 | #define AMULSEL_USOUT3 (1<<14) | ||
| 61 | #define AMULSEL_IRDIN (1<<15) | ||
| 62 | #define AMULSEL_IRDOUT (1<<7) | ||
| 63 | |||
| 64 | /* Register offsets general purpose I/O */ | ||
| 65 | #define GPIO_DATA 0x00 | ||
| 66 | #define GPIO_DIR 0x04 | ||
| 67 | #define GPIO_MASK 0x08 | ||
| 68 | #define GPIO_STAT 0x0C | ||
| 69 | #define GPIO_EDGE 0x10 | ||
| 70 | #define GPIO_CLR 0x14 | ||
| 71 | #define GPIO_POL 0x18 | ||
| 72 | #define GPIO_EN 0x1C | ||
| 73 | |||
| 74 | /*interrupt controller */ | ||
| 75 | #define IRQC_VIRT (IO_VIRT + 0x24000) | ||
| 76 | /* register offset interrupt controller */ | ||
| 77 | #define IRQC_IER 0x00 | ||
| 78 | #define IRQC_ISR 0x04 | ||
| 79 | |||
| 80 | /* timer unit */ | ||
| 81 | #define TIMER_VIRT (IO_VIRT + 0x25000) | ||
| 82 | /* Register offsets timer unit */ | ||
| 83 | #define TM0_PERIOD 0x00 | ||
| 84 | #define TM0_COUNT 0x08 | ||
| 85 | #define TM0_CTRL 0x10 | ||
| 86 | #define TM1_PERIOD 0x20 | ||
| 87 | #define TM1_COUNT 0x28 | ||
| 88 | #define TM1_CTRL 0x30 | ||
| 89 | #define TM2_PERIOD 0x40 | ||
| 90 | #define TM2_COUNT 0x48 | ||
| 91 | #define TM2_CTRL 0x50 | ||
| 92 | #define TIMER_TOPCTRL 0x60 | ||
| 93 | #define TIMER_TOPSTAT 0x64 | ||
| 94 | #define T64_COUNTL 0x80 | ||
| 95 | #define T64_COUNTH 0x84 | ||
| 96 | #define T64_CTRL 0x88 | ||
| 97 | #define T64_BASEL 0x94 | ||
| 98 | #define T64_BASEH 0x98 | ||
| 99 | /* Bitmaks timer unit TOPSTAT reg */ | ||
| 100 | #define TSTAT_T0INT 0x1 | ||
| 101 | #define TSTAT_T1INT 0x2 | ||
| 102 | #define TSTAT_T2INT 0x4 | ||
| 103 | #define TSTAT_T3INT 0x8 | ||
| 104 | /* Bit description of TMx_CTRL register */ | ||
| 105 | #define TM_START 0x1 | ||
| 106 | #define TM_REPEAT 0x2 | ||
| 107 | #define TM_RESET 0x4 | ||
| 108 | /* Bit description of TIMER_CTRL register */ | ||
| 109 | #define ENABLE_TM0_INTR 0x1 | ||
| 110 | #define ENABLE_TM1_INTR 0x2 | ||
| 111 | #define ENABLE_TM2_INTR 0x4 | ||
| 112 | #define TIMER_ENABLE_BIT 0x8 | ||
| 113 | #define ENABLE_TIMER64 0x10 | ||
| 114 | #define ENABLE_TIMER64_INT 0x20 | ||
| 115 | |||
| 116 | /* PMU & PLL */ | ||
| 117 | #define PMU_BASE (IO_VIRT + 0x1000) | ||
| 118 | #define PMU_MODE 0x00 | ||
| 119 | #define PMU_STAT 0x20 | ||
| 120 | #define PMU_PLL_CTRL 0x28 | ||
| 121 | |||
| 122 | /* PMU Mode bits */ | ||
| 123 | #define PMU_MODE_SLOW 0x00 | ||
| 124 | #define PMU_MODE_RUN 0x01 | ||
| 125 | #define PMU_MODE_IDLE 0x02 | ||
| 126 | #define PMU_MODE_SLEEP 0x03 | ||
| 127 | #define PMU_MODE_INIT 0x04 | ||
| 128 | #define PMU_MODE_DEEPSLEEP 0x07 | ||
| 129 | #define PMU_MODE_WAKEUP 0x08 | ||
| 130 | |||
| 131 | /* PMU ... */ | ||
| 132 | #define PLL_2_EN 0x8000 | ||
| 133 | #define PLL_1_EN 0x4000 | ||
| 134 | #define PLL_3_MUTE 0x0080 | ||
| 135 | |||
| 136 | /* Control bits for PMU/ PLL */ | ||
| 137 | #define PMU_WARMRESET 0x00010000 | ||
| 138 | #define PLL_CTRL_MASK23 0x000080ff | ||
| 139 | |||
| 140 | /* LCD Controller */ | ||
| 141 | #define LCD_BASE (IO_VIRT + 0x10000) | ||
| 142 | #define LCD_CTRL 0x00 | ||
| 143 | #define LCD_STATUS 0x04 | ||
| 144 | #define LCD_STATUS_M 0x08 | ||
| 145 | #define LCD_INTERRUPT 0x0C | ||
| 146 | #define LCD_DBAR 0x10 | ||
| 147 | #define LCD_DCAR 0x14 | ||
| 148 | #define LCD_TIMING0 0x20 | ||
| 149 | #define LCD_TIMING1 0x24 | ||
| 150 | #define LCD_TIMING2 0x28 | ||
| 151 | #define LCD_TEST 0x40 | ||
| 152 | |||
| 153 | /* LCD Control Bits */ | ||
| 154 | #define LCD_CTRL_LCD_ENABLE 0x00000001 | ||
| 155 | /* Bits per pixel */ | ||
| 156 | #define LCD_CTRL_LCD_BPP_MASK 0x00000006 | ||
| 157 | #define LCD_CTRL_LCD_4BPP 0x00000000 | ||
| 158 | #define LCD_CTRL_LCD_8BPP 0x00000002 | ||
| 159 | #define LCD_CTRL_LCD_16BPP 0x00000004 | ||
| 160 | #define LCD_CTRL_LCD_BW 0x00000008 | ||
| 161 | #define LCD_CTRL_LCD_TFT 0x00000010 | ||
| 162 | #define LCD_CTRL_BGR 0x00001000 | ||
| 163 | #define LCD_CTRL_LCD_VCOMP 0x00080000 | ||
| 164 | #define LCD_CTRL_LCD_MONO8 0x00200000 | ||
| 165 | #define LCD_CTRL_LCD_PWR 0x00400000 | ||
| 166 | #define LCD_CTRL_LCD_BLE 0x00800000 | ||
| 167 | #define LCD_CTRL_LDBUSEN 0x01000000 | ||
| 168 | |||
| 169 | /* Palette */ | ||
| 170 | #define LCD_PALETTE_BASE (IO_VIRT + 0x10400) | ||
| 171 | |||
| 172 | /* Serial ports */ | ||
| 173 | #define SERIAL0_OFS 0x20000 | ||
| 174 | #define SERIAL0_VIRT (IO_VIRT + SERIAL0_OFS) | ||
| 175 | #define SERIAL0_BASE (IO_PHYS + SERIAL0_OFS) | ||
| 176 | |||
| 177 | #define SERIAL1_OFS 0x21000 | ||
| 178 | #define SERIAL1_VIRT (IO_VIRT + SERIAL1_OFS) | ||
| 179 | #define SERIAL1_BASE (IO_PHYS + SERIAL1_OFS) | ||
| 180 | |||
| 181 | #define SERIAL_ENABLE 0x30 | ||
| 182 | #define SERIAL_ENABLE_EN (1<<0) | ||
| 183 | |||
| 184 | /* General defines to pacify gcc */ | ||
| 185 | #define PCIO_BASE (0) /* for inb, outb and friends */ | ||
| 186 | #define PCIO_VIRT PCIO_BASE | ||
| 187 | |||
| 188 | #define __ASM_ARCH_HARDWARE_INCMACH_H | ||
| 189 | #include "boards.h" | ||
| 190 | #undef __ASM_ARCH_HARDWARE_INCMACH_H | ||
| 191 | |||
| 192 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-h720x/io.h b/include/asm-arm/arch-h720x/io.h deleted file mode 100644 index 68814828c9a7..000000000000 --- a/include/asm-arm/arch-h720x/io.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) | ||
| 5 | * | ||
| 6 | * Changelog: | ||
| 7 | * | ||
| 8 | * 09-19-2001 JJKIM | ||
| 9 | * Created from linux/include/asm-arm/arch-l7200/io.h | ||
| 10 | * | ||
| 11 | * 03-27-2003 Robert Schwebel <r.schwebel@pengutronix.de>: | ||
| 12 | * re-unified header files for h720x | ||
| 13 | */ | ||
| 14 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 15 | #define __ASM_ARM_ARCH_IO_H | ||
| 16 | |||
| 17 | #include <asm/arch/hardware.h> | ||
| 18 | |||
| 19 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 20 | |||
| 21 | #define __io(a) ((void __iomem *)(a)) | ||
| 22 | #define __mem_pci(a) (a) | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/include/asm-arm/arch-h720x/irqs.h b/include/asm-arm/arch-h720x/irqs.h deleted file mode 100644 index 8244413988be..000000000000 --- a/include/asm-arm/arch-h720x/irqs.h +++ /dev/null | |||
| @@ -1,116 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Jungjun Kim | ||
| 5 | * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> | ||
| 6 | * (C) 2003 Thomas Gleixner <tglx@linutronix.de> | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ASM_ARCH_IRQS_H | ||
| 11 | #define __ASM_ARCH_IRQS_H | ||
| 12 | |||
| 13 | #if defined (CONFIG_CPU_H7201) | ||
| 14 | |||
| 15 | #define IRQ_PMU 0 /* 0x000001 */ | ||
| 16 | #define IRQ_DMA 1 /* 0x000002 */ | ||
| 17 | #define IRQ_LCD 2 /* 0x000004 */ | ||
| 18 | #define IRQ_VGA 3 /* 0x000008 */ | ||
| 19 | #define IRQ_PCMCIA1 4 /* 0x000010 */ | ||
| 20 | #define IRQ_PCMCIA2 5 /* 0x000020 */ | ||
| 21 | #define IRQ_AFE 6 /* 0x000040 */ | ||
| 22 | #define IRQ_AIC 7 /* 0x000080 */ | ||
| 23 | #define IRQ_KEYBOARD 8 /* 0x000100 */ | ||
| 24 | #define IRQ_TIMER0 9 /* 0x000200 */ | ||
| 25 | #define IRQ_RTC 10 /* 0x000400 */ | ||
| 26 | #define IRQ_SOUND 11 /* 0x000800 */ | ||
| 27 | #define IRQ_USB 12 /* 0x001000 */ | ||
| 28 | #define IRQ_IrDA 13 /* 0x002000 */ | ||
| 29 | #define IRQ_UART0 14 /* 0x004000 */ | ||
| 30 | #define IRQ_UART1 15 /* 0x008000 */ | ||
| 31 | #define IRQ_SPI 16 /* 0x010000 */ | ||
| 32 | #define IRQ_GPIOA 17 /* 0x020000 */ | ||
| 33 | #define IRQ_GPIOB 18 /* 0x040000 */ | ||
| 34 | #define IRQ_GPIOC 19 /* 0x080000 */ | ||
| 35 | #define IRQ_GPIOD 20 /* 0x100000 */ | ||
| 36 | #define IRQ_CommRX 21 /* 0x200000 */ | ||
| 37 | #define IRQ_CommTX 22 /* 0x400000 */ | ||
| 38 | #define IRQ_Soft 23 /* 0x800000 */ | ||
| 39 | |||
| 40 | #define NR_GLBL_IRQS 24 | ||
| 41 | |||
| 42 | #define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x) | ||
| 43 | #define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x) | ||
| 44 | #define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x) | ||
| 45 | #define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x) | ||
| 46 | #define NR_IRQS IRQ_CHAINED_GPIOD(32) | ||
| 47 | |||
| 48 | /* Enable mask for multiplexed interrupts */ | ||
| 49 | #define IRQ_ENA_MUX (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \ | ||
| 50 | | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD) | ||
| 51 | |||
| 52 | |||
| 53 | #elif defined (CONFIG_CPU_H7202) | ||
| 54 | |||
| 55 | #define IRQ_PMU 0 /* 0x00000001 */ | ||
| 56 | #define IRQ_DMA 1 /* 0x00000002 */ | ||
| 57 | #define IRQ_LCD 2 /* 0x00000004 */ | ||
| 58 | #define IRQ_SOUND 3 /* 0x00000008 */ | ||
| 59 | #define IRQ_I2S 4 /* 0x00000010 */ | ||
| 60 | #define IRQ_USB 5 /* 0x00000020 */ | ||
| 61 | #define IRQ_MMC 6 /* 0x00000040 */ | ||
| 62 | #define IRQ_RTC 7 /* 0x00000080 */ | ||
| 63 | #define IRQ_UART0 8 /* 0x00000100 */ | ||
| 64 | #define IRQ_UART1 9 /* 0x00000200 */ | ||
| 65 | #define IRQ_UART2 10 /* 0x00000400 */ | ||
| 66 | #define IRQ_UART3 11 /* 0x00000800 */ | ||
| 67 | #define IRQ_KBD 12 /* 0x00001000 */ | ||
| 68 | #define IRQ_PS2 13 /* 0x00002000 */ | ||
| 69 | #define IRQ_AIC 14 /* 0x00004000 */ | ||
| 70 | #define IRQ_TIMER0 15 /* 0x00008000 */ | ||
| 71 | #define IRQ_TIMERX 16 /* 0x00010000 */ | ||
| 72 | #define IRQ_WDT 17 /* 0x00020000 */ | ||
| 73 | #define IRQ_CAN0 18 /* 0x00040000 */ | ||
| 74 | #define IRQ_CAN1 19 /* 0x00080000 */ | ||
| 75 | #define IRQ_EXT0 20 /* 0x00100000 */ | ||
| 76 | #define IRQ_EXT1 21 /* 0x00200000 */ | ||
| 77 | #define IRQ_GPIOA 22 /* 0x00400000 */ | ||
| 78 | #define IRQ_GPIOB 23 /* 0x00800000 */ | ||
| 79 | #define IRQ_GPIOC 24 /* 0x01000000 */ | ||
| 80 | #define IRQ_GPIOD 25 /* 0x02000000 */ | ||
| 81 | #define IRQ_GPIOE 26 /* 0x04000000 */ | ||
| 82 | #define IRQ_COMMRX 27 /* 0x08000000 */ | ||
| 83 | #define IRQ_COMMTX 28 /* 0x10000000 */ | ||
| 84 | #define IRQ_SMC 29 /* 0x20000000 */ | ||
| 85 | #define IRQ_Soft 30 /* 0x40000000 */ | ||
| 86 | #define IRQ_RESERVED1 31 /* 0x80000000 */ | ||
| 87 | #define NR_GLBL_IRQS 32 | ||
| 88 | |||
| 89 | #define NR_TIMERX_IRQS 3 | ||
| 90 | |||
| 91 | #define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x) | ||
| 92 | #define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x) | ||
| 93 | #define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x) | ||
| 94 | #define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x) | ||
| 95 | #define IRQ_CHAINED_GPIOE(x) (IRQ_CHAINED_GPIOD(32) + x) | ||
| 96 | #define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x) | ||
| 97 | #define IRQ_TIMER1 (IRQ_CHAINED_TIMERX(0)) | ||
| 98 | #define IRQ_TIMER2 (IRQ_CHAINED_TIMERX(1)) | ||
| 99 | #define IRQ_TIMER64B (IRQ_CHAINED_TIMERX(2)) | ||
| 100 | |||
| 101 | #define NR_IRQS (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS)) | ||
| 102 | |||
| 103 | /* Enable mask for multiplexed interrupts */ | ||
| 104 | #define IRQ_ENA_MUX (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \ | ||
| 105 | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \ | ||
| 106 | (1<<IRQ_TIMERX) | ||
| 107 | |||
| 108 | #else | ||
| 109 | #error cpu definition mismatch | ||
| 110 | #endif | ||
| 111 | |||
| 112 | /* decode irq number to register number */ | ||
| 113 | #define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5) | ||
| 114 | #define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32)) | ||
| 115 | |||
| 116 | #endif | ||
diff --git a/include/asm-arm/arch-h720x/memory.h b/include/asm-arm/arch-h720x/memory.h deleted file mode 100644 index 53e923dba76e..000000000000 --- a/include/asm-arm/arch-h720x/memory.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2000 Jungjun Kim | ||
| 5 | * | ||
| 6 | */ | ||
| 7 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 8 | #define __ASM_ARCH_MEMORY_H | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Page offset: | ||
| 12 | * ( 0xc0000000UL ) | ||
| 13 | */ | ||
| 14 | #define PHYS_OFFSET UL(0x40000000) | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Virtual view <-> DMA view memory address translations | ||
| 18 | * virt_to_bus: Used to translate the virtual address to an | ||
| 19 | * address suitable to be passed to set_dma_addr | ||
| 20 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 21 | * to an address that the kernel can use. | ||
| 22 | * | ||
| 23 | * There is something to do here later !, Mar 2000, Jungjun Kim | ||
| 24 | */ | ||
| 25 | |||
| 26 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 27 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/include/asm-arm/arch-h720x/system.h b/include/asm-arm/arch-h720x/system.h deleted file mode 100644 index ddba93760b42..000000000000 --- a/include/asm-arm/arch-h720x/system.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * linux/include/asm-arm/arch-h720x/system.h | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 14 | #define __ASM_ARCH_SYSTEM_H | ||
| 15 | #include <asm/arch/hardware.h> | ||
| 16 | |||
| 17 | static void arch_idle(void) | ||
| 18 | { | ||
| 19 | CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE; | ||
| 20 | nop(); | ||
| 21 | nop(); | ||
| 22 | CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN; | ||
| 23 | nop(); | ||
| 24 | nop(); | ||
| 25 | } | ||
| 26 | |||
| 27 | |||
| 28 | static __inline__ void arch_reset(char mode) | ||
| 29 | { | ||
| 30 | CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET; | ||
| 31 | } | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/include/asm-arm/arch-h720x/timex.h b/include/asm-arm/arch-h720x/timex.h deleted file mode 100644 index 48a391c4080f..000000000000 --- a/include/asm-arm/arch-h720x/timex.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/timex.h | ||
| 3 | * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ASM_ARCH_TIMEX | ||
| 11 | #define __ASM_ARCH_TIMEX | ||
| 12 | |||
| 13 | #define CLOCK_TICK_RATE 3686400 | ||
| 14 | |||
| 15 | #endif | ||
diff --git a/include/asm-arm/arch-h720x/uncompress.h b/include/asm-arm/arch-h720x/uncompress.h deleted file mode 100644 index 61584cd5f425..000000000000 --- a/include/asm-arm/arch-h720x/uncompress.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001-2002 Jungjun Kim | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
| 8 | #define __ASM_ARCH_UNCOMPRESS_H | ||
| 9 | |||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | |||
| 12 | #define LSR 0x14 | ||
| 13 | #define TEMPTY 0x40 | ||
| 14 | |||
| 15 | static inline void putc(int c) | ||
| 16 | { | ||
| 17 | volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000); | ||
| 18 | |||
| 19 | /* wait until transmit buffer is empty */ | ||
| 20 | while((p[LSR] & TEMPTY) == 0x0) | ||
| 21 | barrier(); | ||
| 22 | |||
| 23 | /* write next character */ | ||
| 24 | *p = c; | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline void flush(void) | ||
| 28 | { | ||
| 29 | } | ||
| 30 | |||
| 31 | /* | ||
| 32 | * nothing to do | ||
| 33 | */ | ||
| 34 | #define arch_decomp_setup() | ||
| 35 | #define arch_decomp_wdog() | ||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-h720x/vmalloc.h b/include/asm-arm/arch-h720x/vmalloc.h deleted file mode 100644 index b4693cb821ef..000000000000 --- a/include/asm-arm/arch-h720x/vmalloc.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-h720x/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ARCH_ARM_VMALLOC_H | ||
| 6 | #define __ARCH_ARM_VMALLOC_H | ||
| 7 | |||
| 8 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
| 9 | |||
| 10 | #endif | ||
diff --git a/include/asm-arm/arch-imx/debug-macro.S b/include/asm-arm/arch-imx/debug-macro.S deleted file mode 100644 index c611871643a2..000000000000 --- a/include/asm-arm/arch-imx/debug-macro.S +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-imx/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | moveq \rx, #0x00000000 @ physical | ||
| 18 | movne \rx, #0xe0000000 @ virtual | ||
| 19 | orreq \rx, \rx, #0x00200000 @ physical | ||
| 20 | orr \rx, \rx, #0x00006000 @ UART1 offset | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro senduart,rd,rx | ||
| 24 | str \rd, [\rx, #0x40] @ TXDATA | ||
| 25 | .endm | ||
| 26 | |||
| 27 | .macro waituart,rd,rx | ||
| 28 | .endm | ||
| 29 | |||
| 30 | .macro busyuart,rd,rx | ||
| 31 | 1002: ldr \rd, [\rx, #0x98] @ SR2 | ||
| 32 | tst \rd, #1 << 3 @ TXDC | ||
| 33 | beq 1002b @ wait until transmit done | ||
| 34 | .endm | ||
diff --git a/include/asm-arm/arch-imx/dma.h b/include/asm-arm/arch-imx/dma.h deleted file mode 100644 index 621ff2c730f2..000000000000 --- a/include/asm-arm/arch-imx/dma.h +++ /dev/null | |||
| @@ -1,56 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/imxads/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997,1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_DMA_H | ||
| 22 | #define __ASM_ARCH_DMA_H | ||
| 23 | |||
| 24 | typedef enum { | ||
| 25 | DMA_PRIO_HIGH = 0, | ||
| 26 | DMA_PRIO_MEDIUM = 1, | ||
| 27 | DMA_PRIO_LOW = 2 | ||
| 28 | } imx_dma_prio; | ||
| 29 | |||
| 30 | #define DMA_REQ_UART3_T 2 | ||
| 31 | #define DMA_REQ_UART3_R 3 | ||
| 32 | #define DMA_REQ_SSI2_T 4 | ||
| 33 | #define DMA_REQ_SSI2_R 5 | ||
| 34 | #define DMA_REQ_CSI_STAT 6 | ||
| 35 | #define DMA_REQ_CSI_R 7 | ||
| 36 | #define DMA_REQ_MSHC 8 | ||
| 37 | #define DMA_REQ_DSPA_DCT_DOUT 9 | ||
| 38 | #define DMA_REQ_DSPA_DCT_DIN 10 | ||
| 39 | #define DMA_REQ_DSPA_MAC 11 | ||
| 40 | #define DMA_REQ_EXT 12 | ||
| 41 | #define DMA_REQ_SDHC 13 | ||
| 42 | #define DMA_REQ_SPI1_R 14 | ||
| 43 | #define DMA_REQ_SPI1_T 15 | ||
| 44 | #define DMA_REQ_SSI_T 16 | ||
| 45 | #define DMA_REQ_SSI_R 17 | ||
| 46 | #define DMA_REQ_ASP_DAC 18 | ||
| 47 | #define DMA_REQ_ASP_ADC 19 | ||
| 48 | #define DMA_REQ_USP_EP(x) (20+(x)) | ||
| 49 | #define DMA_REQ_SPI2_R 26 | ||
| 50 | #define DMA_REQ_SPI2_T 27 | ||
| 51 | #define DMA_REQ_UART2_T 28 | ||
| 52 | #define DMA_REQ_UART2_R 29 | ||
| 53 | #define DMA_REQ_UART1_T 30 | ||
| 54 | #define DMA_REQ_UART1_R 31 | ||
| 55 | |||
| 56 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-imx/entry-macro.S b/include/asm-arm/arch-imx/entry-macro.S deleted file mode 100644 index 5dc0f307c1bb..000000000000 --- a/include/asm-arm/arch-imx/entry-macro.S +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-imx/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for iMX-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | |||
| 12 | .macro disable_fiq | ||
| 13 | .endm | ||
| 14 | |||
| 15 | .macro get_irqnr_preamble, base, tmp | ||
| 16 | .endm | ||
| 17 | |||
| 18 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 19 | .endm | ||
| 20 | |||
| 21 | #define AITC_NIVECSR 0x40 | ||
| 22 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 23 | ldr \base, =IO_ADDRESS(IMX_AITC_BASE) | ||
| 24 | @ Load offset & priority of the highest priority | ||
| 25 | @ interrupt pending. | ||
| 26 | ldr \irqstat, [\base, #AITC_NIVECSR] | ||
| 27 | @ Shift off the priority leaving the offset or | ||
| 28 | @ "interrupt number", use arithmetic shift to | ||
| 29 | @ transform illegal source (0xffff) as -1 | ||
| 30 | mov \irqnr, \irqstat, asr #16 | ||
| 31 | adds \tmp, \irqnr, #1 | ||
| 32 | .endm | ||
diff --git a/include/asm-arm/arch-imx/gpio.h b/include/asm-arm/arch-imx/gpio.h deleted file mode 100644 index 486023263f32..000000000000 --- a/include/asm-arm/arch-imx/gpio.h +++ /dev/null | |||
| @@ -1,102 +0,0 @@ | |||
| 1 | #ifndef _IMX_GPIO_H | ||
| 2 | |||
| 3 | #include <asm/arch/imx-regs.h> | ||
| 4 | |||
| 5 | #define IMX_GPIO_ALLOC_MODE_NORMAL 0 | ||
| 6 | #define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1 | ||
| 7 | #define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2 | ||
| 8 | #define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4 | ||
| 9 | #define IMX_GPIO_ALLOC_MODE_RELEASE 8 | ||
| 10 | |||
| 11 | extern int imx_gpio_request(unsigned gpio, const char *label); | ||
| 12 | |||
| 13 | extern void imx_gpio_free(unsigned gpio); | ||
| 14 | |||
| 15 | extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, | ||
| 16 | int alloc_mode, const char *label); | ||
| 17 | |||
| 18 | extern int imx_gpio_direction_input(unsigned gpio); | ||
| 19 | |||
| 20 | extern int imx_gpio_direction_output(unsigned gpio, int value); | ||
| 21 | |||
| 22 | extern void __imx_gpio_set_value(unsigned gpio, int value); | ||
| 23 | |||
| 24 | static inline int imx_gpio_get_value(unsigned gpio) | ||
| 25 | { | ||
| 26 | return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK)); | ||
| 27 | } | ||
| 28 | |||
| 29 | static inline void imx_gpio_set_value_inline(unsigned gpio, int value) | ||
| 30 | { | ||
| 31 | unsigned long flags; | ||
| 32 | |||
| 33 | raw_local_irq_save(flags); | ||
| 34 | if(value) | ||
| 35 | DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK)); | ||
| 36 | else | ||
| 37 | DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK)); | ||
| 38 | raw_local_irq_restore(flags); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline void imx_gpio_set_value(unsigned gpio, int value) | ||
| 42 | { | ||
| 43 | if(__builtin_constant_p(gpio)) | ||
| 44 | imx_gpio_set_value_inline(gpio, value); | ||
| 45 | else | ||
| 46 | __imx_gpio_set_value(gpio, value); | ||
| 47 | } | ||
| 48 | |||
| 49 | extern int imx_gpio_to_irq(unsigned gpio); | ||
| 50 | |||
| 51 | extern int imx_irq_to_gpio(unsigned irq); | ||
| 52 | |||
| 53 | /*-------------------------------------------------------------------------*/ | ||
| 54 | |||
| 55 | /* Wrappers for "new style" GPIO calls. These calls i.MX specific versions | ||
| 56 | * to allow future extension of GPIO logic. | ||
| 57 | */ | ||
| 58 | |||
| 59 | static inline int gpio_request(unsigned gpio, const char *label) | ||
| 60 | { | ||
| 61 | return imx_gpio_request(gpio, label); | ||
| 62 | } | ||
| 63 | |||
| 64 | static inline void gpio_free(unsigned gpio) | ||
| 65 | { | ||
| 66 | imx_gpio_free(gpio); | ||
| 67 | } | ||
| 68 | |||
| 69 | static inline int gpio_direction_input(unsigned gpio) | ||
| 70 | { | ||
| 71 | return imx_gpio_direction_input(gpio); | ||
| 72 | } | ||
| 73 | |||
| 74 | static inline int gpio_direction_output(unsigned gpio, int value) | ||
| 75 | { | ||
| 76 | return imx_gpio_direction_output(gpio, value); | ||
| 77 | } | ||
| 78 | |||
| 79 | static inline int gpio_get_value(unsigned gpio) | ||
| 80 | { | ||
| 81 | return imx_gpio_get_value(gpio); | ||
| 82 | } | ||
| 83 | |||
| 84 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 85 | { | ||
| 86 | imx_gpio_set_value(gpio, value); | ||
| 87 | } | ||
| 88 | |||
| 89 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
| 90 | |||
| 91 | static inline int gpio_to_irq(unsigned gpio) | ||
| 92 | { | ||
| 93 | return imx_gpio_to_irq(gpio); | ||
| 94 | } | ||
| 95 | |||
| 96 | static inline int irq_to_gpio(unsigned irq) | ||
| 97 | { | ||
| 98 | return imx_irq_to_gpio(irq); | ||
| 99 | } | ||
| 100 | |||
| 101 | |||
| 102 | #endif | ||
diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h deleted file mode 100644 index 6542ca5e8c33..000000000000 --- a/include/asm-arm/arch-imx/hardware.h +++ /dev/null | |||
| @@ -1,91 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-imx/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 21 | #define __ASM_ARCH_HARDWARE_H | ||
| 22 | |||
| 23 | #include <asm/sizes.h> | ||
| 24 | #include "imx-regs.h" | ||
| 25 | |||
| 26 | #ifndef __ASSEMBLY__ | ||
| 27 | # define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) | ||
| 28 | |||
| 29 | # define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Memory map | ||
| 34 | */ | ||
| 35 | |||
| 36 | #define IMX_IO_PHYS 0x00200000 | ||
| 37 | #define IMX_IO_SIZE 0x00100000 | ||
| 38 | #define IMX_IO_BASE 0xe0000000 | ||
| 39 | |||
| 40 | #define IMX_CS0_PHYS 0x10000000 | ||
| 41 | #define IMX_CS0_SIZE 0x02000000 | ||
| 42 | #define IMX_CS0_VIRT 0xe8000000 | ||
| 43 | |||
| 44 | #define IMX_CS1_PHYS 0x12000000 | ||
| 45 | #define IMX_CS1_SIZE 0x01000000 | ||
| 46 | #define IMX_CS1_VIRT 0xea000000 | ||
| 47 | |||
| 48 | #define IMX_CS2_PHYS 0x13000000 | ||
| 49 | #define IMX_CS2_SIZE 0x01000000 | ||
| 50 | #define IMX_CS2_VIRT 0xeb000000 | ||
| 51 | |||
| 52 | #define IMX_CS3_PHYS 0x14000000 | ||
| 53 | #define IMX_CS3_SIZE 0x01000000 | ||
| 54 | #define IMX_CS3_VIRT 0xec000000 | ||
| 55 | |||
| 56 | #define IMX_CS4_PHYS 0x15000000 | ||
| 57 | #define IMX_CS4_SIZE 0x01000000 | ||
| 58 | #define IMX_CS4_VIRT 0xed000000 | ||
| 59 | |||
| 60 | #define IMX_CS5_PHYS 0x16000000 | ||
| 61 | #define IMX_CS5_SIZE 0x01000000 | ||
| 62 | #define IMX_CS5_VIRT 0xee000000 | ||
| 63 | |||
| 64 | #define IMX_FB_VIRT 0xF1000000 | ||
| 65 | #define IMX_FB_SIZE (256*1024) | ||
| 66 | |||
| 67 | /* macro to get at IO space when running virtually */ | ||
| 68 | #define IO_ADDRESS(x) ((x) | IMX_IO_BASE) | ||
| 69 | |||
| 70 | #ifndef __ASSEMBLY__ | ||
| 71 | /* | ||
| 72 | * Handy routine to set GPIO functions | ||
| 73 | */ | ||
| 74 | extern void imx_gpio_mode( int gpio_mode ); | ||
| 75 | |||
| 76 | #endif | ||
| 77 | |||
| 78 | #define MAXIRQNUM 62 | ||
| 79 | #define MAXFIQNUM 62 | ||
| 80 | #define MAXSWINUM 62 | ||
| 81 | |||
| 82 | /* | ||
| 83 | * Use SDRAM for memory | ||
| 84 | */ | ||
| 85 | #define MEM_SIZE 0x01000000 | ||
| 86 | |||
| 87 | #ifdef CONFIG_ARCH_MX1ADS | ||
| 88 | #include "mx1ads.h" | ||
| 89 | #endif | ||
| 90 | |||
| 91 | #endif | ||
diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h deleted file mode 100644 index 44d89c35539a..000000000000 --- a/include/asm-arm/arch-imx/imx-dma.h +++ /dev/null | |||
| @@ -1,94 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/imxads/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997,1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <asm/dma.h> | ||
| 22 | |||
| 23 | #ifndef __ASM_ARCH_IMX_DMA_H | ||
| 24 | #define __ASM_ARCH_IMX_DMA_H | ||
| 25 | |||
| 26 | #define IMX_DMA_CHANNELS 11 | ||
| 27 | |||
| 28 | /* | ||
| 29 | * struct imx_dma_channel - i.MX specific DMA extension | ||
| 30 | * @name: name specified by DMA client | ||
| 31 | * @irq_handler: client callback for end of transfer | ||
| 32 | * @err_handler: client callback for error condition | ||
| 33 | * @data: clients context data for callbacks | ||
| 34 | * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE | ||
| 35 | * @sg: pointer to the actual read/written chunk for scatter-gather emulation | ||
| 36 | * @sgbc: counter of processed bytes in the actual read/written chunk | ||
| 37 | * @resbytes: total residual number of bytes to transfer | ||
| 38 | * (it can be lower or same as sum of SG mapped chunk sizes) | ||
| 39 | * @sgcount: number of chunks to be read/written | ||
| 40 | * | ||
| 41 | * Structure is used for IMX DMA processing. It would be probably good | ||
| 42 | * @struct dma_struct in the future for external interfacing and use | ||
| 43 | * @struct imx_dma_channel only as extension to it. | ||
| 44 | */ | ||
| 45 | |||
| 46 | struct imx_dma_channel { | ||
| 47 | const char *name; | ||
| 48 | void (*irq_handler) (int, void *); | ||
| 49 | void (*err_handler) (int, void *, int errcode); | ||
| 50 | void *data; | ||
| 51 | dmamode_t dma_mode; | ||
| 52 | struct scatterlist *sg; | ||
| 53 | unsigned int sgbc; | ||
| 54 | unsigned int sgcount; | ||
| 55 | unsigned int resbytes; | ||
| 56 | int dma_num; | ||
| 57 | }; | ||
| 58 | |||
| 59 | extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; | ||
| 60 | |||
| 61 | #define IMX_DMA_ERR_BURST 1 | ||
| 62 | #define IMX_DMA_ERR_REQUEST 2 | ||
| 63 | #define IMX_DMA_ERR_TRANSFER 4 | ||
| 64 | #define IMX_DMA_ERR_BUFFER 8 | ||
| 65 | |||
| 66 | /* The type to distinguish channel numbers parameter from ordinal int type */ | ||
| 67 | typedef int imx_dmach_t; | ||
| 68 | |||
| 69 | int | ||
| 70 | imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, | ||
| 71 | unsigned int dma_length, unsigned int dev_addr, dmamode_t dmamode); | ||
| 72 | |||
| 73 | int | ||
| 74 | imx_dma_setup_sg(imx_dmach_t dma_ch, | ||
| 75 | struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, | ||
| 76 | unsigned int dev_addr, dmamode_t dmamode); | ||
| 77 | |||
| 78 | int | ||
| 79 | imx_dma_setup_handlers(imx_dmach_t dma_ch, | ||
| 80 | void (*irq_handler) (int, void *), | ||
| 81 | void (*err_handler) (int, void *, int), void *data); | ||
| 82 | |||
| 83 | void imx_dma_enable(imx_dmach_t dma_ch); | ||
| 84 | |||
| 85 | void imx_dma_disable(imx_dmach_t dma_ch); | ||
| 86 | |||
| 87 | int imx_dma_request(imx_dmach_t dma_ch, const char *name); | ||
| 88 | |||
| 89 | void imx_dma_free(imx_dmach_t dma_ch); | ||
| 90 | |||
| 91 | imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio); | ||
| 92 | |||
| 93 | |||
| 94 | #endif /* _ASM_ARCH_IMX_DMA_H */ | ||
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h deleted file mode 100644 index fb9de2733879..000000000000 --- a/include/asm-arm/arch-imx/imx-regs.h +++ /dev/null | |||
| @@ -1,482 +0,0 @@ | |||
| 1 | #ifndef _IMX_REGS_H | ||
| 2 | #define _IMX_REGS_H | ||
| 3 | /* ------------------------------------------------------------------------ | ||
| 4 | * Motorola IMX system registers | ||
| 5 | * ------------------------------------------------------------------------ | ||
| 6 | * | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Register BASEs, based on OFFSETs | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) | ||
| 14 | #define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) | ||
| 15 | #define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) | ||
| 16 | #define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) | ||
| 17 | #define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) | ||
| 18 | #define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) | ||
| 19 | #define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) | ||
| 20 | #define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) | ||
| 21 | #define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) | ||
| 22 | #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) | ||
| 23 | #define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) | ||
| 24 | #define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) | ||
| 25 | #define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) | ||
| 26 | #define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) | ||
| 27 | #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) | ||
| 28 | #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) | ||
| 29 | #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) | ||
| 30 | #define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) | ||
| 31 | #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) | ||
| 32 | #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) | ||
| 33 | #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) | ||
| 34 | #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) | ||
| 35 | #define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) | ||
| 36 | #define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) | ||
| 37 | #define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) | ||
| 38 | #define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) | ||
| 39 | #define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) | ||
| 40 | #define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) | ||
| 41 | |||
| 42 | /* PLL registers */ | ||
| 43 | #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ | ||
| 44 | #define CSCR_SPLL_RESTART (1<<22) | ||
| 45 | #define CSCR_MPLL_RESTART (1<<21) | ||
| 46 | #define CSCR_SYSTEM_SEL (1<<16) | ||
| 47 | #define CSCR_BCLK_DIV (0xf<<10) | ||
| 48 | #define CSCR_MPU_PRESC (1<<15) | ||
| 49 | #define CSCR_SPEN (1<<1) | ||
| 50 | #define CSCR_MPEN (1<<0) | ||
| 51 | |||
| 52 | #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ | ||
| 53 | #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ | ||
| 54 | #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ | ||
| 55 | #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ | ||
| 56 | #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ | ||
| 57 | |||
| 58 | /* | ||
| 59 | * GPIO Module and I/O Multiplexer | ||
| 60 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D | ||
| 61 | */ | ||
| 62 | #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) | ||
| 63 | #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) | ||
| 64 | #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) | ||
| 65 | #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) | ||
| 66 | #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) | ||
| 67 | #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) | ||
| 68 | #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) | ||
| 69 | #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) | ||
| 70 | #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) | ||
| 71 | #define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) | ||
| 72 | #define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) | ||
| 73 | #define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) | ||
| 74 | #define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) | ||
| 75 | #define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) | ||
| 76 | #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) | ||
| 77 | #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) | ||
| 78 | #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) | ||
| 79 | |||
| 80 | #define GPIO_PORT_MAX 3 | ||
| 81 | |||
| 82 | #define GPIO_PIN_MASK 0x1f | ||
| 83 | #define GPIO_PORT_MASK (0x3 << 5) | ||
| 84 | |||
| 85 | #define GPIO_PORT_SHIFT 5 | ||
| 86 | #define GPIO_PORTA (0<<5) | ||
| 87 | #define GPIO_PORTB (1<<5) | ||
| 88 | #define GPIO_PORTC (2<<5) | ||
| 89 | #define GPIO_PORTD (3<<5) | ||
| 90 | |||
| 91 | #define GPIO_OUT (1<<7) | ||
| 92 | #define GPIO_IN (0<<7) | ||
| 93 | #define GPIO_PUEN (1<<8) | ||
| 94 | |||
| 95 | #define GPIO_PF (0<<9) | ||
| 96 | #define GPIO_AF (1<<9) | ||
| 97 | |||
| 98 | #define GPIO_OCR_SHIFT 10 | ||
| 99 | #define GPIO_OCR_MASK (3<<10) | ||
| 100 | #define GPIO_AIN (0<<10) | ||
| 101 | #define GPIO_BIN (1<<10) | ||
| 102 | #define GPIO_CIN (2<<10) | ||
| 103 | #define GPIO_DR (3<<10) | ||
| 104 | |||
| 105 | #define GPIO_AOUT_SHIFT 12 | ||
| 106 | #define GPIO_AOUT_MASK (3<<12) | ||
| 107 | #define GPIO_AOUT (0<<12) | ||
| 108 | #define GPIO_AOUT_ISR (1<<12) | ||
| 109 | #define GPIO_AOUT_0 (2<<12) | ||
| 110 | #define GPIO_AOUT_1 (3<<12) | ||
| 111 | |||
| 112 | #define GPIO_BOUT_SHIFT 14 | ||
| 113 | #define GPIO_BOUT_MASK (3<<14) | ||
| 114 | #define GPIO_BOUT (0<<14) | ||
| 115 | #define GPIO_BOUT_ISR (1<<14) | ||
| 116 | #define GPIO_BOUT_0 (2<<14) | ||
| 117 | #define GPIO_BOUT_1 (3<<14) | ||
| 118 | |||
| 119 | #define GPIO_GIUS (1<<16) | ||
| 120 | |||
| 121 | /* assignements for GPIO alternate/primary functions */ | ||
| 122 | |||
| 123 | /* FIXME: This list is not completed. The correct directions are | ||
| 124 | * missing on some (many) pins | ||
| 125 | */ | ||
| 126 | #define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) | ||
| 127 | #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) | ||
| 128 | #define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) | ||
| 129 | #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) | ||
| 130 | #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) | ||
| 131 | #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) | ||
| 132 | #define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) | ||
| 133 | #define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) | ||
| 134 | #define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) | ||
| 135 | #define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) | ||
| 136 | #define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) | ||
| 137 | #define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) | ||
| 138 | #define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) | ||
| 139 | #define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) | ||
| 140 | #define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) | ||
| 141 | #define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) | ||
| 142 | #define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) | ||
| 143 | #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) | ||
| 144 | #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) | ||
| 145 | #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) | ||
| 146 | #define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) | ||
| 147 | #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) | ||
| 148 | #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) | ||
| 149 | #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) | ||
| 150 | #define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) | ||
| 151 | #define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) | ||
| 152 | #define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) | ||
| 153 | #define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) | ||
| 154 | #define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) | ||
| 155 | #define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) | ||
| 156 | #define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) | ||
| 157 | #define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) | ||
| 158 | #define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) | ||
| 159 | #define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) | ||
| 160 | #define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) | ||
| 161 | #define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) | ||
| 162 | #define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) | ||
| 163 | #define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) | ||
| 164 | #define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) | ||
| 165 | #define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) | ||
| 166 | #define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) | ||
| 167 | #define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) | ||
| 168 | #define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) | ||
| 169 | #define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) | ||
| 170 | #define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) | ||
| 171 | #define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) | ||
| 172 | #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) | ||
| 173 | #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) | ||
| 174 | #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) | ||
| 175 | #define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) | ||
| 176 | #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) | ||
| 177 | #define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) | ||
| 178 | #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) | ||
| 179 | #define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) | ||
| 180 | #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) | ||
| 181 | #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) | ||
| 182 | #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) | ||
| 183 | #define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) | ||
| 184 | #define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) | ||
| 185 | #define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) | ||
| 186 | #define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) | ||
| 187 | #define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) | ||
| 188 | #define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) | ||
| 189 | #define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) | ||
| 190 | #define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) | ||
| 191 | #define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) | ||
| 192 | #define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) | ||
| 193 | #define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) | ||
| 194 | #define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) | ||
| 195 | #define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) | ||
| 196 | #define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) | ||
| 197 | #define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) | ||
| 198 | #define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) | ||
| 199 | #define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) | ||
| 200 | #define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) | ||
| 201 | #define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) | ||
| 202 | #define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) | ||
| 203 | #define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) | ||
| 204 | #define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) | ||
| 205 | #define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) | ||
| 206 | #define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) | ||
| 207 | #define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) | ||
| 208 | #define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) | ||
| 209 | #define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) | ||
| 210 | #define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) | ||
| 211 | #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) | ||
| 212 | #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) | ||
| 213 | #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) | ||
| 214 | #define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) | ||
| 215 | #define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) | ||
| 216 | #define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) | ||
| 217 | #define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) | ||
| 218 | #define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) | ||
| 219 | #define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) | ||
| 220 | #define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) | ||
| 221 | #define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) | ||
| 222 | #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) | ||
| 223 | #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) | ||
| 224 | #define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) | ||
| 225 | #define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) | ||
| 226 | #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) | ||
| 227 | #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) | ||
| 228 | #define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) | ||
| 229 | #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) | ||
| 230 | #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) | ||
| 231 | #define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) | ||
| 232 | #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) | ||
| 233 | #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) | ||
| 234 | #define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) | ||
| 235 | #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) | ||
| 236 | #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) | ||
| 237 | #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) | ||
| 238 | #define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) | ||
| 239 | #define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) | ||
| 240 | #define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) | ||
| 241 | #define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) | ||
| 242 | #define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) | ||
| 243 | #define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) | ||
| 244 | #define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) | ||
| 245 | #define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) | ||
| 246 | #define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) | ||
| 247 | #define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) | ||
| 248 | #define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) | ||
| 249 | #define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) | ||
| 250 | #define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) | ||
| 251 | #define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) | ||
| 252 | #define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) | ||
| 253 | #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) | ||
| 254 | #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) | ||
| 255 | #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) | ||
| 256 | #define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) | ||
| 257 | |||
| 258 | /* | ||
| 259 | * PWM controller | ||
| 260 | */ | ||
| 261 | #define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ | ||
| 262 | #define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ | ||
| 263 | #define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ | ||
| 264 | #define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ | ||
| 265 | |||
| 266 | #define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ | ||
| 267 | #define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ | ||
| 268 | #define PWMC_SWR (0x01<<16) /* Software Reset */ | ||
| 269 | #define PWMC_CLKSRC (0x01<<15) /* Clock Source */ | ||
| 270 | #define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ | ||
| 271 | #define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ | ||
| 272 | #define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ | ||
| 273 | #define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ | ||
| 274 | #define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ | ||
| 275 | #define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ | ||
| 276 | #define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ | ||
| 277 | |||
| 278 | #define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ | ||
| 279 | #define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ | ||
| 280 | #define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ | ||
| 281 | |||
| 282 | /* | ||
| 283 | * DMA Controller | ||
| 284 | */ | ||
| 285 | #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ | ||
| 286 | #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ | ||
| 287 | #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ | ||
| 288 | #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ | ||
| 289 | #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ | ||
| 290 | #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ | ||
| 291 | #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ | ||
| 292 | #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ | ||
| 293 | #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ | ||
| 294 | #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ | ||
| 295 | #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ | ||
| 296 | #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ | ||
| 297 | #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ | ||
| 298 | #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ | ||
| 299 | #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ | ||
| 300 | #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ | ||
| 301 | #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ | ||
| 302 | #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ | ||
| 303 | #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ | ||
| 304 | #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ | ||
| 305 | #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ | ||
| 306 | #define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ | ||
| 307 | |||
| 308 | #define DCR_DRST (1<<1) | ||
| 309 | #define DCR_DEN (1<<0) | ||
| 310 | #define DBTOCR_EN (1<<15) | ||
| 311 | #define DBTOCR_CNT(x) ((x) & 0x7fff ) | ||
| 312 | #define CNTR_CNT(x) ((x) & 0xffffff ) | ||
| 313 | #define CCR_DMOD_LINEAR ( 0x0 << 12 ) | ||
| 314 | #define CCR_DMOD_2D ( 0x1 << 12 ) | ||
| 315 | #define CCR_DMOD_FIFO ( 0x2 << 12 ) | ||
| 316 | #define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) | ||
| 317 | #define CCR_SMOD_LINEAR ( 0x0 << 10 ) | ||
| 318 | #define CCR_SMOD_2D ( 0x1 << 10 ) | ||
| 319 | #define CCR_SMOD_FIFO ( 0x2 << 10 ) | ||
| 320 | #define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) | ||
| 321 | #define CCR_MDIR_DEC (1<<9) | ||
| 322 | #define CCR_MSEL_B (1<<8) | ||
| 323 | #define CCR_DSIZ_32 ( 0x0 << 6 ) | ||
| 324 | #define CCR_DSIZ_8 ( 0x1 << 6 ) | ||
| 325 | #define CCR_DSIZ_16 ( 0x2 << 6 ) | ||
| 326 | #define CCR_SSIZ_32 ( 0x0 << 4 ) | ||
| 327 | #define CCR_SSIZ_8 ( 0x1 << 4 ) | ||
| 328 | #define CCR_SSIZ_16 ( 0x2 << 4 ) | ||
| 329 | #define CCR_REN (1<<3) | ||
| 330 | #define CCR_RPT (1<<2) | ||
| 331 | #define CCR_FRC (1<<1) | ||
| 332 | #define CCR_CEN (1<<0) | ||
| 333 | #define RTOR_EN (1<<15) | ||
| 334 | #define RTOR_CLK (1<<14) | ||
| 335 | #define RTOR_PSC (1<<13) | ||
| 336 | |||
| 337 | /* | ||
| 338 | * Interrupt controller | ||
| 339 | */ | ||
| 340 | |||
| 341 | #define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00) | ||
| 342 | #define INTCNTL_FIAD (1<<19) | ||
| 343 | #define INTCNTL_NIAD (1<<20) | ||
| 344 | |||
| 345 | #define IMX_NIMASK __REG(IMX_AITC_BASE+0x04) | ||
| 346 | #define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08) | ||
| 347 | #define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c) | ||
| 348 | #define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10) | ||
| 349 | #define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14) | ||
| 350 | |||
| 351 | /* | ||
| 352 | * General purpose timers | ||
| 353 | */ | ||
| 354 | #define IMX_TCTL(x) __REG( 0x00 + (x)) | ||
| 355 | #define TCTL_SWR (1<<15) | ||
| 356 | #define TCTL_FRR (1<<8) | ||
| 357 | #define TCTL_CAP_RIS (1<<6) | ||
| 358 | #define TCTL_CAP_FAL (2<<6) | ||
| 359 | #define TCTL_CAP_RIS_FAL (3<<6) | ||
| 360 | #define TCTL_OM (1<<5) | ||
| 361 | #define TCTL_IRQEN (1<<4) | ||
| 362 | #define TCTL_CLK_PCLK1 (1<<1) | ||
| 363 | #define TCTL_CLK_PCLK1_16 (2<<1) | ||
| 364 | #define TCTL_CLK_TIN (3<<1) | ||
| 365 | #define TCTL_CLK_32 (4<<1) | ||
| 366 | #define TCTL_TEN (1<<0) | ||
| 367 | |||
| 368 | #define IMX_TPRER(x) __REG( 0x04 + (x)) | ||
| 369 | #define IMX_TCMP(x) __REG( 0x08 + (x)) | ||
| 370 | #define IMX_TCR(x) __REG( 0x0C + (x)) | ||
| 371 | #define IMX_TCN(x) __REG( 0x10 + (x)) | ||
| 372 | #define IMX_TSTAT(x) __REG( 0x14 + (x)) | ||
| 373 | #define TSTAT_CAPT (1<<1) | ||
| 374 | #define TSTAT_COMP (1<<0) | ||
| 375 | |||
| 376 | /* | ||
| 377 | * LCD Controller | ||
| 378 | */ | ||
| 379 | |||
| 380 | #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) | ||
| 381 | |||
| 382 | #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) | ||
| 383 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) | ||
| 384 | #define SIZE_YMAX(y) ( (y) & 0x1ff ) | ||
| 385 | |||
| 386 | #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) | ||
| 387 | #define VPW_VPW(x) ( (x) & 0x3ff ) | ||
| 388 | |||
| 389 | #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) | ||
| 390 | #define CPOS_CC1 (1<<31) | ||
| 391 | #define CPOS_CC0 (1<<30) | ||
| 392 | #define CPOS_OP (1<<28) | ||
| 393 | #define CPOS_CXP(x) (((x) & 3ff) << 16) | ||
| 394 | #define CPOS_CYP(y) ((y) & 0x1ff) | ||
| 395 | |||
| 396 | #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) | ||
| 397 | #define LCWHB_BK_EN (1<<31) | ||
| 398 | #define LCWHB_CW(w) (((w) & 0x1f) << 24) | ||
| 399 | #define LCWHB_CH(h) (((h) & 0x1f) << 16) | ||
| 400 | #define LCWHB_BD(x) ((x) & 0xff) | ||
| 401 | |||
| 402 | #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) | ||
| 403 | #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) | ||
| 404 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) | ||
| 405 | #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) | ||
| 406 | |||
| 407 | #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) | ||
| 408 | #define PCR_TFT (1<<31) | ||
| 409 | #define PCR_COLOR (1<<30) | ||
| 410 | #define PCR_PBSIZ_1 (0<<28) | ||
| 411 | #define PCR_PBSIZ_2 (1<<28) | ||
| 412 | #define PCR_PBSIZ_4 (2<<28) | ||
| 413 | #define PCR_PBSIZ_8 (3<<28) | ||
| 414 | #define PCR_BPIX_1 (0<<25) | ||
| 415 | #define PCR_BPIX_2 (1<<25) | ||
| 416 | #define PCR_BPIX_4 (2<<25) | ||
| 417 | #define PCR_BPIX_8 (3<<25) | ||
| 418 | #define PCR_BPIX_12 (4<<25) | ||
| 419 | #define PCR_BPIX_16 (4<<25) | ||
| 420 | #define PCR_PIXPOL (1<<24) | ||
| 421 | #define PCR_FLMPOL (1<<23) | ||
| 422 | #define PCR_LPPOL (1<<22) | ||
| 423 | #define PCR_CLKPOL (1<<21) | ||
| 424 | #define PCR_OEPOL (1<<20) | ||
| 425 | #define PCR_SCLKIDLE (1<<19) | ||
| 426 | #define PCR_END_SEL (1<<18) | ||
| 427 | #define PCR_END_BYTE_SWAP (1<<17) | ||
| 428 | #define PCR_REV_VS (1<<16) | ||
| 429 | #define PCR_ACD_SEL (1<<15) | ||
| 430 | #define PCR_ACD(x) (((x) & 0x7f) << 8) | ||
| 431 | #define PCR_SCLK_SEL (1<<7) | ||
| 432 | #define PCR_SHARP (1<<6) | ||
| 433 | #define PCR_PCD(x) ((x) & 0x3f) | ||
| 434 | |||
| 435 | #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) | ||
| 436 | #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) | ||
| 437 | #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) | ||
| 438 | #define HCR_H_WAIT_2(x) ((x) & 0xff) | ||
| 439 | |||
| 440 | #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) | ||
| 441 | #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) | ||
| 442 | #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) | ||
| 443 | #define VCR_V_WAIT_2(x) ((x) & 0xff) | ||
| 444 | |||
| 445 | #define LCDC_POS __REG(IMX_LCDC_BASE+0x24) | ||
| 446 | #define POS_POS(x) ((x) & 1f) | ||
| 447 | |||
| 448 | #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) | ||
| 449 | #define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) | ||
| 450 | #define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) | ||
| 451 | #define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) | ||
| 452 | #define LSCR1_GRAY2(x) (((x) & 0xf) << 4) | ||
| 453 | #define LSCR1_GRAY1(x) (((x) & 0xf)) | ||
| 454 | |||
| 455 | #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) | ||
| 456 | #define PWMR_CLS(x) (((x) & 0x1ff) << 16) | ||
| 457 | #define PWMR_LDMSK (1<<15) | ||
| 458 | #define PWMR_SCR1 (1<<10) | ||
| 459 | #define PWMR_SCR0 (1<<9) | ||
| 460 | #define PWMR_CC_EN (1<<8) | ||
| 461 | #define PWMR_PW(x) ((x) & 0xff) | ||
| 462 | |||
| 463 | #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) | ||
| 464 | #define DMACR_BURST (1<<31) | ||
| 465 | #define DMACR_HM(x) (((x) & 0xf) << 16) | ||
| 466 | #define DMACR_TM(x) ((x) &0xf) | ||
| 467 | |||
| 468 | #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) | ||
| 469 | #define RMCR_LCDC_EN (1<<1) | ||
| 470 | #define RMCR_SELF_REF (1<<0) | ||
| 471 | |||
| 472 | #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) | ||
| 473 | #define LCDICR_INT_SYN (1<<2) | ||
| 474 | #define LCDICR_INT_CON (1) | ||
| 475 | |||
| 476 | #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) | ||
| 477 | #define LCDISR_UDR_ERR (1<<3) | ||
| 478 | #define LCDISR_ERR_RES (1<<2) | ||
| 479 | #define LCDISR_EOF (1<<1) | ||
| 480 | #define LCDISR_BOF (1<<0) | ||
| 481 | |||
| 482 | #endif // _IMX_REGS_H | ||
diff --git a/include/asm-arm/arch-imx/imx-uart.h b/include/asm-arm/arch-imx/imx-uart.h deleted file mode 100644 index d54eb1d48026..000000000000 --- a/include/asm-arm/arch-imx/imx-uart.h +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | #ifndef ASMARM_ARCH_UART_H | ||
| 2 | #define ASMARM_ARCH_UART_H | ||
| 3 | |||
| 4 | #define IMXUART_HAVE_RTSCTS (1<<0) | ||
| 5 | |||
| 6 | struct imxuart_platform_data { | ||
| 7 | int (*init)(struct platform_device *pdev); | ||
| 8 | void (*exit)(struct platform_device *pdev); | ||
| 9 | unsigned int flags; | ||
| 10 | }; | ||
| 11 | |||
| 12 | #endif | ||
diff --git a/include/asm-arm/arch-imx/imxfb.h b/include/asm-arm/arch-imx/imxfb.h deleted file mode 100644 index 3ed9ec8b9f00..000000000000 --- a/include/asm-arm/arch-imx/imxfb.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This structure describes the machine which we are running on. | ||
| 3 | */ | ||
| 4 | struct imxfb_mach_info { | ||
| 5 | u_long pixclock; | ||
| 6 | |||
| 7 | u_short xres; | ||
| 8 | u_short yres; | ||
| 9 | |||
| 10 | u_int nonstd; | ||
| 11 | u_char bpp; | ||
| 12 | u_char hsync_len; | ||
| 13 | u_char left_margin; | ||
| 14 | u_char right_margin; | ||
| 15 | |||
| 16 | u_char vsync_len; | ||
| 17 | u_char upper_margin; | ||
| 18 | u_char lower_margin; | ||
| 19 | u_char sync; | ||
| 20 | |||
| 21 | u_int cmap_greyscale:1, | ||
| 22 | cmap_inverse:1, | ||
| 23 | cmap_static:1, | ||
| 24 | unused:29; | ||
| 25 | |||
| 26 | u_int pcr; | ||
| 27 | u_int pwmr; | ||
| 28 | u_int lscr1; | ||
| 29 | u_int dmacr; | ||
| 30 | |||
| 31 | u_char * fixed_screen_cpu; | ||
| 32 | dma_addr_t fixed_screen_dma; | ||
| 33 | |||
| 34 | void (*lcd_power)(int); | ||
| 35 | void (*backlight_power)(int); | ||
| 36 | }; | ||
| 37 | void set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info); | ||
diff --git a/include/asm-arm/arch-imx/io.h b/include/asm-arm/arch-imx/io.h deleted file mode 100644 index 1a1d9bb88631..000000000000 --- a/include/asm-arm/arch-imx/io.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-imxads/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 21 | #define __ASM_ARM_ARCH_IO_H | ||
| 22 | |||
| 23 | #include <asm/arch/hardware.h> | ||
| 24 | |||
| 25 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 26 | |||
| 27 | #define __io(a) ((void __iomem *)(a)) | ||
| 28 | #define __mem_pci(a) (a) | ||
| 29 | |||
| 30 | #endif | ||
diff --git a/include/asm-arm/arch-imx/irqs.h b/include/asm-arm/arch-imx/irqs.h deleted file mode 100644 index 238197cfb9d9..000000000000 --- a/include/asm-arm/arch-imx/irqs.h +++ /dev/null | |||
| @@ -1,116 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-imxads/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __ARM_IRQS_H__ | ||
| 23 | #define __ARM_IRQS_H__ | ||
| 24 | |||
| 25 | /* Use the imx definitions */ | ||
| 26 | #include <asm/arch/hardware.h> | ||
| 27 | |||
| 28 | /* | ||
| 29 | * IMX Interrupt numbers | ||
| 30 | * | ||
| 31 | */ | ||
| 32 | #define INT_SOFTINT 0 | ||
| 33 | #define CSI_INT 6 | ||
| 34 | #define DSPA_MAC_INT 7 | ||
| 35 | #define DSPA_INT 8 | ||
| 36 | #define COMP_INT 9 | ||
| 37 | #define MSHC_XINT 10 | ||
| 38 | #define GPIO_INT_PORTA 11 | ||
| 39 | #define GPIO_INT_PORTB 12 | ||
| 40 | #define GPIO_INT_PORTC 13 | ||
| 41 | #define LCDC_INT 14 | ||
| 42 | #define SIM_INT 15 | ||
| 43 | #define SIM_DATA_INT 16 | ||
| 44 | #define RTC_INT 17 | ||
| 45 | #define RTC_SAMINT 18 | ||
| 46 | #define UART2_MINT_PFERR 19 | ||
| 47 | #define UART2_MINT_RTS 20 | ||
| 48 | #define UART2_MINT_DTR 21 | ||
| 49 | #define UART2_MINT_UARTC 22 | ||
| 50 | #define UART2_MINT_TX 23 | ||
| 51 | #define UART2_MINT_RX 24 | ||
| 52 | #define UART1_MINT_PFERR 25 | ||
| 53 | #define UART1_MINT_RTS 26 | ||
| 54 | #define UART1_MINT_DTR 27 | ||
| 55 | #define UART1_MINT_UARTC 28 | ||
| 56 | #define UART1_MINT_TX 29 | ||
| 57 | #define UART1_MINT_RX 30 | ||
| 58 | #define VOICE_DAC_INT 31 | ||
| 59 | #define VOICE_ADC_INT 32 | ||
| 60 | #define PEN_DATA_INT 33 | ||
| 61 | #define PWM_INT 34 | ||
| 62 | #define SDHC_INT 35 | ||
| 63 | #define I2C_INT 39 | ||
| 64 | #define CSPI_INT 41 | ||
| 65 | #define SSI_TX_INT 42 | ||
| 66 | #define SSI_TX_ERR_INT 43 | ||
| 67 | #define SSI_RX_INT 44 | ||
| 68 | #define SSI_RX_ERR_INT 45 | ||
| 69 | #define TOUCH_INT 46 | ||
| 70 | #define USBD_INT0 47 | ||
| 71 | #define USBD_INT1 48 | ||
| 72 | #define USBD_INT2 49 | ||
| 73 | #define USBD_INT3 50 | ||
| 74 | #define USBD_INT4 51 | ||
| 75 | #define USBD_INT5 52 | ||
| 76 | #define USBD_INT6 53 | ||
| 77 | #define BTSYS_INT 55 | ||
| 78 | #define BTTIM_INT 56 | ||
| 79 | #define BTWUI_INT 57 | ||
| 80 | #define TIM2_INT 58 | ||
| 81 | #define TIM1_INT 59 | ||
| 82 | #define DMA_ERR 60 | ||
| 83 | #define DMA_INT 61 | ||
| 84 | #define GPIO_INT_PORTD 62 | ||
| 85 | |||
| 86 | #define IMX_IRQS (64) | ||
| 87 | |||
| 88 | /* note: the IMX has four gpio ports (A-D), but only | ||
| 89 | * the following pins are connected to the outside | ||
| 90 | * world: | ||
| 91 | * | ||
| 92 | * PORT A: bits 0-31 | ||
| 93 | * PORT B: bits 8-31 | ||
| 94 | * PORT C: bits 3-17 | ||
| 95 | * PORT D: bits 6-31 | ||
| 96 | * | ||
| 97 | * We map these interrupts straight on. As a result we have | ||
| 98 | * several holes in the interrupt mapping. We do this for two | ||
| 99 | * reasons: | ||
| 100 | * - mapping the interrupts without holes would get | ||
| 101 | * far more complicated | ||
| 102 | * - Motorola could well decide to bring some processor | ||
| 103 | * with more pins connected | ||
| 104 | */ | ||
| 105 | |||
| 106 | #define IRQ_GPIOA(x) (IMX_IRQS + x) | ||
| 107 | #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) | ||
| 108 | #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) | ||
| 109 | #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) | ||
| 110 | |||
| 111 | /* decode irq number to use with IMR(x), ISR(x) and friends */ | ||
| 112 | #define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5) | ||
| 113 | |||
| 114 | #define NR_IRQS (IRQ_GPIOD(32) + 1) | ||
| 115 | #define IRQ_GPIO(x) | ||
| 116 | #endif | ||
diff --git a/include/asm-arm/arch-imx/memory.h b/include/asm-arm/arch-imx/memory.h deleted file mode 100644 index 5ad90127915f..000000000000 --- a/include/asm-arm/arch-imx/memory.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-imx/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #ifndef __ASM_ARCH_MMU_H | ||
| 22 | #define __ASM_ARCH_MMU_H | ||
| 23 | |||
| 24 | #define PHYS_OFFSET UL(0x08000000) | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Virtual view <-> DMA view memory address translations | ||
| 28 | * virt_to_bus: Used to translate the virtual address to an | ||
| 29 | * address suitable to be passed to set_dma_addr | ||
| 30 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 31 | * to an address that the kernel can use. | ||
| 32 | */ | ||
| 33 | #define __virt_to_bus(x) (x - PAGE_OFFSET + PHYS_OFFSET) | ||
| 34 | #define __bus_to_virt(x) (x - PHYS_OFFSET + PAGE_OFFSET) | ||
| 35 | |||
| 36 | #endif | ||
diff --git a/include/asm-arm/arch-imx/mmc.h b/include/asm-arm/arch-imx/mmc.h deleted file mode 100644 index 4712f354dcca..000000000000 --- a/include/asm-arm/arch-imx/mmc.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | #ifndef ASMARM_ARCH_MMC_H | ||
| 2 | #define ASMARM_ARCH_MMC_H | ||
| 3 | |||
| 4 | #include <linux/mmc/host.h> | ||
| 5 | |||
| 6 | struct device; | ||
| 7 | |||
| 8 | struct imxmmc_platform_data { | ||
| 9 | int (*card_present)(struct device *); | ||
| 10 | int (*get_ro)(struct device *); | ||
| 11 | }; | ||
| 12 | |||
| 13 | extern void imx_set_mmc_info(struct imxmmc_platform_data *info); | ||
| 14 | |||
| 15 | #endif | ||
diff --git a/include/asm-arm/arch-imx/mx1ads.h b/include/asm-arm/arch-imx/mx1ads.h deleted file mode 100644 index d90fa4b49ce1..000000000000 --- a/include/asm-arm/arch-imx/mx1ads.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-imx/mx1ads.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 Robert Schwebel, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | * | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __ASM_ARCH_MX1ADS_H | ||
| 23 | #define __ASM_ARCH_MX1ADS_H | ||
| 24 | |||
| 25 | /* ------------------------------------------------------------------------ */ | ||
| 26 | /* Memory Map for the M9328MX1ADS (MX1ADS) Board */ | ||
| 27 | /* ------------------------------------------------------------------------ */ | ||
| 28 | |||
| 29 | #define MX1ADS_FLASH_PHYS 0x10000000 | ||
| 30 | #define MX1ADS_FLASH_SIZE (16*1024*1024) | ||
| 31 | |||
| 32 | #define IMX_FB_PHYS (0x0C000000 - 0x40000) | ||
| 33 | |||
| 34 | #define CLK32 32000 | ||
| 35 | |||
| 36 | #endif /* __ASM_ARCH_MX1ADS_H */ | ||
diff --git a/include/asm-arm/arch-imx/spi_imx.h b/include/asm-arm/arch-imx/spi_imx.h deleted file mode 100644 index 2165449e976e..000000000000 --- a/include/asm-arm/arch-imx/spi_imx.h +++ /dev/null | |||
| @@ -1,72 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-imx/spi_imx.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 SWAPP | ||
| 5 | * Andrea Paterniani <a.paterniani@swapp-eng.it> | ||
| 6 | * | ||
| 7 | * Initial version inspired by: | ||
| 8 | * linux-2.6.17-rc3-mm1/include/asm-arm/arch-pxa/pxa2xx_spi.h | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 23 | */ | ||
| 24 | |||
| 25 | #ifndef SPI_IMX_H_ | ||
| 26 | #define SPI_IMX_H_ | ||
| 27 | |||
| 28 | |||
| 29 | /*-------------------------------------------------------------------------*/ | ||
| 30 | /** | ||
| 31 | * struct spi_imx_master - device.platform_data for SPI controller devices. | ||
| 32 | * @num_chipselect: chipselects are used to distinguish individual | ||
| 33 | * SPI slaves, and are numbered from zero to num_chipselects - 1. | ||
| 34 | * each slave has a chipselect signal, but it's common that not | ||
| 35 | * every chipselect is connected to a slave. | ||
| 36 | * @enable_dma: if true enables DMA driven transfers. | ||
| 37 | */ | ||
| 38 | struct spi_imx_master { | ||
| 39 | u8 num_chipselect; | ||
| 40 | u8 enable_dma:1; | ||
| 41 | }; | ||
| 42 | /*-------------------------------------------------------------------------*/ | ||
| 43 | |||
| 44 | |||
| 45 | /*-------------------------------------------------------------------------*/ | ||
| 46 | /** | ||
| 47 | * struct spi_imx_chip - spi_board_info.controller_data for SPI | ||
| 48 | * slave devices, copied to spi_device.controller_data. | ||
| 49 | * @enable_loopback : used for test purpouse to internally connect RX and TX | ||
| 50 | * sections. | ||
| 51 | * @enable_dma : enables dma transfer (provided that controller driver has | ||
| 52 | * dma enabled too). | ||
| 53 | * @ins_ss_pulse : enable /SS pulse insertion between SPI burst. | ||
| 54 | * @bclk_wait : number of bclk waits between each bits_per_word SPI burst. | ||
| 55 | * @cs_control : function pointer to board-specific function to assert/deassert | ||
| 56 | * I/O port to control HW generation of devices chip-select. | ||
| 57 | */ | ||
| 58 | struct spi_imx_chip { | ||
| 59 | u8 enable_loopback:1; | ||
| 60 | u8 enable_dma:1; | ||
| 61 | u8 ins_ss_pulse:1; | ||
| 62 | u16 bclk_wait:15; | ||
| 63 | void (*cs_control)(u32 control); | ||
| 64 | }; | ||
| 65 | |||
| 66 | /* Chip-select state */ | ||
| 67 | #define SPI_CS_ASSERT (1 << 0) | ||
| 68 | #define SPI_CS_DEASSERT (1 << 1) | ||
| 69 | /*-------------------------------------------------------------------------*/ | ||
| 70 | |||
| 71 | |||
| 72 | #endif /* SPI_IMX_H_*/ | ||
diff --git a/include/asm-arm/arch-imx/system.h b/include/asm-arm/arch-imx/system.h deleted file mode 100644 index c645fe9afb9d..000000000000 --- a/include/asm-arm/arch-imx/system.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-imxads/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 22 | #define __ASM_ARCH_SYSTEM_H | ||
| 23 | |||
| 24 | static void | ||
| 25 | arch_idle(void) | ||
| 26 | { | ||
| 27 | /* | ||
| 28 | * This should do all the clock switching | ||
| 29 | * and wait for interrupt tricks | ||
| 30 | */ | ||
| 31 | cpu_do_idle(); | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline void | ||
| 35 | arch_reset(char mode) | ||
| 36 | { | ||
| 37 | cpu_reset(0); | ||
| 38 | } | ||
| 39 | |||
| 40 | #endif | ||
diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h deleted file mode 100644 index e22ba789546c..000000000000 --- a/include/asm-arm/arch-imx/timex.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/imx/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 22 | #define __ASM_ARCH_TIMEX_H | ||
| 23 | |||
| 24 | #define CLOCK_TICK_RATE (16000000) | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-arm/arch-imx/uncompress.h b/include/asm-arm/arch-imx/uncompress.h deleted file mode 100644 index da333f69136f..000000000000 --- a/include/asm-arm/arch-imx/uncompress.h +++ /dev/null | |||
| @@ -1,71 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-imxads/uncompress.h | ||
| 3 | * | ||
| 4 | * | ||
| 5 | * | ||
| 6 | * Copyright (C) 1999 ARM Limited | ||
| 7 | * Copyright (C) Shane Nay (shane@minirl.com) | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 22 | */ | ||
| 23 | |||
| 24 | #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) | ||
| 25 | |||
| 26 | #define UART1_BASE 0x206000 | ||
| 27 | #define UART2_BASE 0x207000 | ||
| 28 | #define USR2 0x98 | ||
| 29 | #define USR2_TXFE (1<<14) | ||
| 30 | #define TXR 0x40 | ||
| 31 | #define UCR1 0x80 | ||
| 32 | #define UCR1_UARTEN 1 | ||
| 33 | |||
| 34 | /* | ||
| 35 | * The following code assumes the serial port has already been | ||
| 36 | * initialized by the bootloader. We search for the first enabled | ||
| 37 | * port in the most probable order. If you didn't setup a port in | ||
| 38 | * your bootloader then nothing will appear (which might be desired). | ||
| 39 | * | ||
| 40 | * This does not append a newline | ||
| 41 | */ | ||
| 42 | static void putc(int c) | ||
| 43 | { | ||
| 44 | unsigned long serial_port; | ||
| 45 | |||
| 46 | do { | ||
| 47 | serial_port = UART1_BASE; | ||
| 48 | if ( UART(UCR1) & UCR1_UARTEN ) | ||
| 49 | break; | ||
| 50 | serial_port = UART2_BASE; | ||
| 51 | if ( UART(UCR1) & UCR1_UARTEN ) | ||
| 52 | break; | ||
| 53 | return; | ||
| 54 | } while(0); | ||
| 55 | |||
| 56 | while (!(UART(USR2) & USR2_TXFE)) | ||
| 57 | barrier(); | ||
| 58 | |||
| 59 | UART(TXR) = c; | ||
| 60 | } | ||
| 61 | |||
| 62 | static inline void flush(void) | ||
| 63 | { | ||
| 64 | } | ||
| 65 | |||
| 66 | /* | ||
| 67 | * nothing to do | ||
| 68 | */ | ||
| 69 | #define arch_decomp_setup() | ||
| 70 | |||
| 71 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-imx/vmalloc.h b/include/asm-arm/arch-imx/vmalloc.h deleted file mode 100644 index cb6169127068..000000000000 --- a/include/asm-arm/arch-imx/vmalloc.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-imx/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
diff --git a/include/asm-arm/arch-integrator/bits.h b/include/asm-arm/arch-integrator/bits.h deleted file mode 100644 index 09b024e0496a..000000000000 --- a/include/asm-arm/arch-integrator/bits.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This program is free software; you can redistribute it and/or modify | ||
| 3 | * it under the terms of the GNU General Public License as published by | ||
| 4 | * the Free Software Foundation; either version 2 of the License, or | ||
| 5 | * (at your option) any later version. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | * | ||
| 12 | * You should have received a copy of the GNU General Public License | ||
| 13 | * along with this program; if not, write to the Free Software | ||
| 14 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 15 | */ | ||
| 16 | /* DO NOT EDIT!! - this file automatically generated | ||
| 17 | * from .s file by awk -f s2h.awk | ||
| 18 | */ | ||
| 19 | /* Bit field definitions | ||
| 20 | * Copyright (C) ARM Limited 1998. All rights reserved. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __bits_h | ||
| 24 | #define __bits_h 1 | ||
| 25 | |||
| 26 | #define BIT0 0x00000001 | ||
| 27 | #define BIT1 0x00000002 | ||
| 28 | #define BIT2 0x00000004 | ||
| 29 | #define BIT3 0x00000008 | ||
| 30 | #define BIT4 0x00000010 | ||
| 31 | #define BIT5 0x00000020 | ||
| 32 | #define BIT6 0x00000040 | ||
| 33 | #define BIT7 0x00000080 | ||
| 34 | #define BIT8 0x00000100 | ||
| 35 | #define BIT9 0x00000200 | ||
| 36 | #define BIT10 0x00000400 | ||
| 37 | #define BIT11 0x00000800 | ||
| 38 | #define BIT12 0x00001000 | ||
| 39 | #define BIT13 0x00002000 | ||
| 40 | #define BIT14 0x00004000 | ||
| 41 | #define BIT15 0x00008000 | ||
| 42 | #define BIT16 0x00010000 | ||
| 43 | #define BIT17 0x00020000 | ||
| 44 | #define BIT18 0x00040000 | ||
| 45 | #define BIT19 0x00080000 | ||
| 46 | #define BIT20 0x00100000 | ||
| 47 | #define BIT21 0x00200000 | ||
| 48 | #define BIT22 0x00400000 | ||
| 49 | #define BIT23 0x00800000 | ||
| 50 | #define BIT24 0x01000000 | ||
| 51 | #define BIT25 0x02000000 | ||
| 52 | #define BIT26 0x04000000 | ||
| 53 | #define BIT27 0x08000000 | ||
| 54 | #define BIT28 0x10000000 | ||
| 55 | #define BIT29 0x20000000 | ||
| 56 | #define BIT30 0x40000000 | ||
| 57 | #define BIT31 0x80000000 | ||
| 58 | |||
| 59 | #endif | ||
| 60 | |||
| 61 | /* END */ | ||
diff --git a/include/asm-arm/arch-integrator/cm.h b/include/asm-arm/arch-integrator/cm.h deleted file mode 100644 index 1ab353e23595..000000000000 --- a/include/asm-arm/arch-integrator/cm.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * update the core module control register. | ||
| 3 | */ | ||
| 4 | void cm_control(u32, u32); | ||
| 5 | |||
| 6 | #define CM_CTRL_LED (1 << 0) | ||
| 7 | #define CM_CTRL_nMBDET (1 << 1) | ||
| 8 | #define CM_CTRL_REMAP (1 << 2) | ||
| 9 | #define CM_CTRL_RESET (1 << 3) | ||
| 10 | |||
| 11 | /* | ||
| 12 | * Integrator/AP,PP2 specific | ||
| 13 | */ | ||
| 14 | #define CM_CTRL_HIGHVECTORS (1 << 4) | ||
| 15 | #define CM_CTRL_BIGENDIAN (1 << 5) | ||
| 16 | #define CM_CTRL_FASTBUS (1 << 6) | ||
| 17 | #define CM_CTRL_SYNC (1 << 7) | ||
| 18 | |||
| 19 | /* | ||
| 20 | * ARM926/946/966 Integrator/CP specific | ||
| 21 | */ | ||
| 22 | #define CM_CTRL_LCDBIASEN (1 << 8) | ||
| 23 | #define CM_CTRL_LCDBIASUP (1 << 9) | ||
| 24 | #define CM_CTRL_LCDBIASDN (1 << 10) | ||
| 25 | #define CM_CTRL_LCDMUXSEL_MASK (7 << 11) | ||
| 26 | #define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11) | ||
| 27 | #define CM_CTRL_LCDMUXSEL_VGA_16BPP (2 << 11) | ||
| 28 | #define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11) | ||
| 29 | #define CM_CTRL_LCDMUXSEL_VGA_8421BPP (4 << 11) | ||
| 30 | #define CM_CTRL_LCDEN0 (1 << 14) | ||
| 31 | #define CM_CTRL_LCDEN1 (1 << 15) | ||
| 32 | #define CM_CTRL_STATIC1 (1 << 16) | ||
| 33 | #define CM_CTRL_STATIC2 (1 << 17) | ||
| 34 | #define CM_CTRL_STATIC (1 << 18) | ||
| 35 | #define CM_CTRL_n24BITEN (1 << 19) | ||
| 36 | #define CM_CTRL_EBIWP (1 << 20) | ||
diff --git a/include/asm-arm/arch-integrator/debug-macro.S b/include/asm-arm/arch-integrator/debug-macro.S deleted file mode 100644 index 85b327c352df..000000000000 --- a/include/asm-arm/arch-integrator/debug-macro.S +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-integrator/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | moveq \rx, #0x16000000 @ physical base address | ||
| 18 | movne \rx, #0xf0000000 @ virtual base | ||
| 19 | addne \rx, \rx, #0x16000000 >> 4 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | #include <asm/hardware/debug-pl01x.S> | ||
diff --git a/include/asm-arm/arch-integrator/dma.h b/include/asm-arm/arch-integrator/dma.h deleted file mode 100644 index 83fd6bbaf9d3..000000000000 --- a/include/asm-arm/arch-integrator/dma.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-integrator/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997,1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
diff --git a/include/asm-arm/arch-integrator/entry-macro.S b/include/asm-arm/arch-integrator/entry-macro.S deleted file mode 100644 index ef535a68bdd3..000000000000 --- a/include/asm-arm/arch-integrator/entry-macro.S +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-integrator/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for Integrator platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | #include <asm/arch/irqs.h> | ||
| 12 | |||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro get_irqnr_preamble, base, tmp | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 23 | /* FIXME: should not be using soo many LDRs here */ | ||
| 24 | ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE) | ||
| 25 | mov \irqnr, #IRQ_PIC_START | ||
| 26 | ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status | ||
| 27 | ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE) | ||
| 28 | teq \irqstat, #0 | ||
| 29 | ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)] | ||
| 30 | moveq \irqnr, #IRQ_CIC_START | ||
| 31 | |||
| 32 | 1001: tst \irqstat, #15 | ||
| 33 | bne 1002f | ||
| 34 | add \irqnr, \irqnr, #4 | ||
| 35 | movs \irqstat, \irqstat, lsr #4 | ||
| 36 | bne 1001b | ||
| 37 | 1002: tst \irqstat, #1 | ||
| 38 | bne 1003f | ||
| 39 | add \irqnr, \irqnr, #1 | ||
| 40 | movs \irqstat, \irqstat, lsr #1 | ||
| 41 | bne 1002b | ||
| 42 | 1003: /* EQ will be set if no irqs pending */ | ||
| 43 | .endm | ||
| 44 | |||
diff --git a/include/asm-arm/arch-integrator/hardware.h b/include/asm-arm/arch-integrator/hardware.h deleted file mode 100644 index 6f0947bc500d..000000000000 --- a/include/asm-arm/arch-integrator/hardware.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-integrator/hardware.h | ||
| 3 | * | ||
| 4 | * This file contains the hardware definitions of the Integrator. | ||
| 5 | * | ||
| 6 | * Copyright (C) 1999 ARM Limited. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 23 | #define __ASM_ARCH_HARDWARE_H | ||
| 24 | |||
| 25 | #include <asm/sizes.h> | ||
| 26 | #include <asm/arch/platform.h> | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Where in virtual memory the IO devices (timers, system controllers | ||
| 30 | * and so on) | ||
| 31 | */ | ||
| 32 | #define IO_BASE 0xF0000000 // VA of IO | ||
| 33 | #define IO_SIZE 0x0B000000 // How much? | ||
| 34 | #define IO_START INTEGRATOR_HDR_BASE // PA of IO | ||
| 35 | |||
| 36 | #define PCIO_BASE PCI_IO_VADDR | ||
| 37 | #define PCIMEM_BASE PCI_MEMORY_VADDR | ||
| 38 | |||
| 39 | /* macro to get at IO space when running virtually */ | ||
| 40 | #define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) | ||
| 41 | |||
| 42 | #define pcibios_assign_all_busses() 1 | ||
| 43 | |||
| 44 | #define PCIBIOS_MIN_IO 0x6000 | ||
| 45 | #define PCIBIOS_MIN_MEM 0x00100000 | ||
| 46 | |||
| 47 | #endif | ||
| 48 | |||
diff --git a/include/asm-arm/arch-integrator/impd1.h b/include/asm-arm/arch-integrator/impd1.h deleted file mode 100644 index d75de4b14237..000000000000 --- a/include/asm-arm/arch-integrator/impd1.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | #define IMPD1_OSC1 0x00 | ||
| 2 | #define IMPD1_OSC2 0x04 | ||
| 3 | #define IMPD1_LOCK 0x08 | ||
| 4 | #define IMPD1_LEDS 0x0c | ||
| 5 | #define IMPD1_INT 0x10 | ||
| 6 | #define IMPD1_SW 0x14 | ||
| 7 | #define IMPD1_CTRL 0x18 | ||
| 8 | |||
| 9 | #define IMPD1_CTRL_DISP_LCD (0 << 0) | ||
| 10 | #define IMPD1_CTRL_DISP_VGA (1 << 0) | ||
| 11 | #define IMPD1_CTRL_DISP_LCD1 (2 << 0) | ||
| 12 | #define IMPD1_CTRL_DISP_ENABLE (1 << 2) | ||
| 13 | #define IMPD1_CTRL_DISP_MASK (7 << 0) | ||
| 14 | |||
| 15 | struct device; | ||
| 16 | |||
| 17 | void impd1_tweak_control(struct device *dev, u32 mask, u32 val); | ||
| 18 | |||
diff --git a/include/asm-arm/arch-integrator/io.h b/include/asm-arm/arch-integrator/io.h deleted file mode 100644 index c8f2175948bd..000000000000 --- a/include/asm-arm/arch-integrator/io.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-integrator/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 21 | #define __ASM_ARM_ARCH_IO_H | ||
| 22 | |||
| 23 | #define IO_SPACE_LIMIT 0xffff | ||
| 24 | |||
| 25 | /* | ||
| 26 | * WARNING: this has to mirror definitions in platform.h | ||
| 27 | */ | ||
| 28 | #define PCI_MEMORY_VADDR 0xe8000000 | ||
| 29 | #define PCI_CONFIG_VADDR 0xec000000 | ||
| 30 | #define PCI_V3_VADDR 0xed000000 | ||
| 31 | #define PCI_IO_VADDR 0xee000000 | ||
| 32 | |||
| 33 | #define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) | ||
| 34 | #define __mem_pci(a) (a) | ||
| 35 | |||
| 36 | #endif | ||
diff --git a/include/asm-arm/arch-integrator/irqs.h b/include/asm-arm/arch-integrator/irqs.h deleted file mode 100644 index ba7b3afee445..000000000000 --- a/include/asm-arm/arch-integrator/irqs.h +++ /dev/null | |||
| @@ -1,82 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-integrator/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Interrupt numbers | ||
| 24 | */ | ||
| 25 | #define IRQ_PIC_START 0 | ||
| 26 | #define IRQ_SOFTINT 0 | ||
| 27 | #define IRQ_UARTINT0 1 | ||
| 28 | #define IRQ_UARTINT1 2 | ||
| 29 | #define IRQ_KMIINT0 3 | ||
| 30 | #define IRQ_KMIINT1 4 | ||
| 31 | #define IRQ_TIMERINT0 5 | ||
| 32 | #define IRQ_TIMERINT1 6 | ||
| 33 | #define IRQ_TIMERINT2 7 | ||
| 34 | #define IRQ_RTCINT 8 | ||
| 35 | #define IRQ_AP_EXPINT0 9 | ||
| 36 | #define IRQ_AP_EXPINT1 10 | ||
| 37 | #define IRQ_AP_EXPINT2 11 | ||
| 38 | #define IRQ_AP_EXPINT3 12 | ||
| 39 | #define IRQ_AP_PCIINT0 13 | ||
| 40 | #define IRQ_AP_PCIINT1 14 | ||
| 41 | #define IRQ_AP_PCIINT2 15 | ||
| 42 | #define IRQ_AP_PCIINT3 16 | ||
| 43 | #define IRQ_AP_V3INT 17 | ||
| 44 | #define IRQ_AP_CPINT0 18 | ||
| 45 | #define IRQ_AP_CPINT1 19 | ||
| 46 | #define IRQ_AP_LBUSTIMEOUT 20 | ||
| 47 | #define IRQ_AP_APCINT 21 | ||
| 48 | #define IRQ_CP_CLCDCINT 22 | ||
| 49 | #define IRQ_CP_MMCIINT0 23 | ||
| 50 | #define IRQ_CP_MMCIINT1 24 | ||
| 51 | #define IRQ_CP_AACIINT 25 | ||
| 52 | #define IRQ_CP_CPPLDINT 26 | ||
| 53 | #define IRQ_CP_ETHINT 27 | ||
| 54 | #define IRQ_CP_TSPENINT 28 | ||
| 55 | #define IRQ_PIC_END 31 | ||
| 56 | |||
| 57 | #define IRQ_CIC_START 32 | ||
| 58 | #define IRQ_CM_SOFTINT 32 | ||
| 59 | #define IRQ_CM_COMMRX 33 | ||
| 60 | #define IRQ_CM_COMMTX 34 | ||
| 61 | #define IRQ_CIC_END 34 | ||
| 62 | |||
| 63 | /* | ||
| 64 | * IntegratorCP only | ||
| 65 | */ | ||
| 66 | #define IRQ_SIC_START 35 | ||
| 67 | #define IRQ_SIC_CP_SOFTINT 35 | ||
| 68 | #define IRQ_SIC_CP_RI0 36 | ||
| 69 | #define IRQ_SIC_CP_RI1 37 | ||
| 70 | #define IRQ_SIC_CP_CARDIN 38 | ||
| 71 | #define IRQ_SIC_CP_LMINT0 39 | ||
| 72 | #define IRQ_SIC_CP_LMINT1 40 | ||
| 73 | #define IRQ_SIC_CP_LMINT2 41 | ||
| 74 | #define IRQ_SIC_CP_LMINT3 42 | ||
| 75 | #define IRQ_SIC_CP_LMINT4 43 | ||
| 76 | #define IRQ_SIC_CP_LMINT5 44 | ||
| 77 | #define IRQ_SIC_CP_LMINT6 45 | ||
| 78 | #define IRQ_SIC_CP_LMINT7 46 | ||
| 79 | #define IRQ_SIC_END 46 | ||
| 80 | |||
| 81 | #define NR_IRQS 47 | ||
| 82 | |||
diff --git a/include/asm-arm/arch-integrator/lm.h b/include/asm-arm/arch-integrator/lm.h deleted file mode 100644 index 28186b6f2c09..000000000000 --- a/include/asm-arm/arch-integrator/lm.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | |||
| 2 | struct lm_device { | ||
| 3 | struct device dev; | ||
| 4 | struct resource resource; | ||
| 5 | unsigned int irq; | ||
| 6 | unsigned int id; | ||
| 7 | }; | ||
| 8 | |||
| 9 | struct lm_driver { | ||
| 10 | struct device_driver drv; | ||
| 11 | int (*probe)(struct lm_device *); | ||
| 12 | void (*remove)(struct lm_device *); | ||
| 13 | int (*suspend)(struct lm_device *, pm_message_t); | ||
| 14 | int (*resume)(struct lm_device *); | ||
| 15 | }; | ||
| 16 | |||
| 17 | int lm_driver_register(struct lm_driver *drv); | ||
| 18 | void lm_driver_unregister(struct lm_driver *drv); | ||
| 19 | |||
| 20 | int lm_device_register(struct lm_device *dev); | ||
| 21 | |||
| 22 | #define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev) | ||
| 23 | #define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d) | ||
diff --git a/include/asm-arm/arch-integrator/memory.h b/include/asm-arm/arch-integrator/memory.h deleted file mode 100644 index 1ab56d783e7c..000000000000 --- a/include/asm-arm/arch-integrator/memory.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-integrator/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 21 | #define __ASM_ARCH_MEMORY_H | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Physical DRAM offset. | ||
| 25 | */ | ||
| 26 | #define PHYS_OFFSET UL(0x00000000) | ||
| 27 | #define BUS_OFFSET UL(0x80000000) | ||
| 28 | |||
| 29 | /* | ||
| 30 | * Virtual view <-> DMA view memory address translations | ||
| 31 | * virt_to_bus: Used to translate the virtual address to an | ||
| 32 | * address suitable to be passed to set_dma_addr | ||
| 33 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 34 | * to an address that the kernel can use. | ||
| 35 | */ | ||
| 36 | #define __virt_to_bus(x) (x - PAGE_OFFSET + BUS_OFFSET) | ||
| 37 | #define __bus_to_virt(x) (x - BUS_OFFSET + PAGE_OFFSET) | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-integrator/platform.h b/include/asm-arm/arch-integrator/platform.h deleted file mode 100644 index 83c4c1ceb411..000000000000 --- a/include/asm-arm/arch-integrator/platform.h +++ /dev/null | |||
| @@ -1,469 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This program is free software; you can redistribute it and/or modify | ||
| 3 | * it under the terms of the GNU General Public License as published by | ||
| 4 | * the Free Software Foundation; either version 2 of the License, or | ||
| 5 | * (at your option) any later version. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | * | ||
| 12 | * You should have received a copy of the GNU General Public License | ||
| 13 | * along with this program; if not, write to the Free Software | ||
| 14 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 15 | */ | ||
| 16 | /* DO NOT EDIT!! - this file automatically generated | ||
| 17 | * from .s file by awk -f s2h.awk | ||
| 18 | */ | ||
| 19 | /************************************************************************** | ||
| 20 | * * Copyright © ARM Limited 1998. All rights reserved. | ||
| 21 | * ***********************************************************************/ | ||
| 22 | /* ************************************************************************ | ||
| 23 | * | ||
| 24 | * Integrator address map | ||
| 25 | * | ||
| 26 | * NOTE: This is a multi-hosted header file for use with uHAL and | ||
| 27 | * supported debuggers. | ||
| 28 | * | ||
| 29 | * $Id: platform.s,v 1.32 2000/02/18 10:51:39 asims Exp $ | ||
| 30 | * | ||
| 31 | * ***********************************************************************/ | ||
| 32 | |||
| 33 | #ifndef __address_h | ||
| 34 | #define __address_h 1 | ||
| 35 | |||
| 36 | /* ======================================================================== | ||
| 37 | * Integrator definitions | ||
| 38 | * ======================================================================== | ||
| 39 | * ------------------------------------------------------------------------ | ||
| 40 | * Memory definitions | ||
| 41 | * ------------------------------------------------------------------------ | ||
| 42 | * Integrator memory map | ||
| 43 | * | ||
| 44 | */ | ||
| 45 | #define INTEGRATOR_BOOT_ROM_LO 0x00000000 | ||
| 46 | #define INTEGRATOR_BOOT_ROM_HI 0x20000000 | ||
| 47 | #define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ | ||
| 48 | #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K | ||
| 49 | |||
| 50 | /* | ||
| 51 | * New Core Modules have different amounts of SSRAM, the amount of SSRAM | ||
| 52 | * fitted can be found in HDR_STAT. | ||
| 53 | * | ||
| 54 | * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to | ||
| 55 | * the minimum amount of SSRAM fitted on any core module. | ||
| 56 | * | ||
| 57 | * New Core Modules also alias the SSRAM. | ||
| 58 | * | ||
| 59 | */ | ||
| 60 | #define INTEGRATOR_SSRAM_BASE 0x00000000 | ||
| 61 | #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 | ||
| 62 | #define INTEGRATOR_SSRAM_SIZE SZ_256K | ||
| 63 | |||
| 64 | #define INTEGRATOR_FLASH_BASE 0x24000000 | ||
| 65 | #define INTEGRATOR_FLASH_SIZE SZ_32M | ||
| 66 | |||
| 67 | #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 | ||
| 68 | #define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K | ||
| 69 | |||
| 70 | /* | ||
| 71 | * SDRAM is a SIMM therefore the size is not known. | ||
| 72 | * | ||
| 73 | */ | ||
| 74 | #define INTEGRATOR_SDRAM_BASE 0x00040000 | ||
| 75 | |||
| 76 | #define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 | ||
| 77 | #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 | ||
| 78 | #define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 | ||
| 79 | #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 | ||
| 80 | #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 | ||
| 81 | |||
| 82 | /* | ||
| 83 | * Logic expansion modules | ||
| 84 | * | ||
| 85 | */ | ||
| 86 | #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 | ||
| 87 | #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 | ||
| 88 | #define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 | ||
| 89 | #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 | ||
| 90 | #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 | ||
| 91 | |||
| 92 | /* ------------------------------------------------------------------------ | ||
| 93 | * Integrator header card registers | ||
| 94 | * ------------------------------------------------------------------------ | ||
| 95 | * | ||
| 96 | */ | ||
| 97 | #define INTEGRATOR_HDR_ID_OFFSET 0x00 | ||
| 98 | #define INTEGRATOR_HDR_PROC_OFFSET 0x04 | ||
| 99 | #define INTEGRATOR_HDR_OSC_OFFSET 0x08 | ||
| 100 | #define INTEGRATOR_HDR_CTRL_OFFSET 0x0C | ||
| 101 | #define INTEGRATOR_HDR_STAT_OFFSET 0x10 | ||
| 102 | #define INTEGRATOR_HDR_LOCK_OFFSET 0x14 | ||
| 103 | #define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 | ||
| 104 | #define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ | ||
| 105 | #define INTEGRATOR_HDR_IC_OFFSET 0x40 | ||
| 106 | #define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 | ||
| 107 | #define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 | ||
| 108 | |||
| 109 | #define INTEGRATOR_HDR_BASE 0x10000000 | ||
| 110 | #define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) | ||
| 111 | #define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) | ||
| 112 | #define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) | ||
| 113 | #define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) | ||
| 114 | #define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) | ||
| 115 | #define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) | ||
| 116 | #define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) | ||
| 117 | #define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) | ||
| 118 | #define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) | ||
| 119 | #define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) | ||
| 120 | #define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) | ||
| 121 | |||
| 122 | #define INTEGRATOR_HDR_CTRL_LED 0x01 | ||
| 123 | #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 | ||
| 124 | #define INTEGRATOR_HDR_CTRL_REMAP 0x04 | ||
| 125 | #define INTEGRATOR_HDR_CTRL_RESET 0x08 | ||
| 126 | #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 | ||
| 127 | #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 | ||
| 128 | #define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 | ||
| 129 | #define INTEGRATOR_HDR_CTRL_SYNC 0x80 | ||
| 130 | |||
| 131 | #define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 | ||
| 132 | #define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 | ||
| 133 | #define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C | ||
| 134 | #define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 | ||
| 135 | #define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 | ||
| 136 | #define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B | ||
| 137 | #define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 | ||
| 138 | #define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 | ||
| 139 | #define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A | ||
| 140 | #define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F | ||
| 141 | #define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 | ||
| 142 | #define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 | ||
| 143 | #define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E | ||
| 144 | #define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 | ||
| 145 | #define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 | ||
| 146 | #define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D | ||
| 147 | #define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 | ||
| 148 | #define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 | ||
| 149 | #define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C | ||
| 150 | #define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 | ||
| 151 | #define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 | ||
| 152 | #define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B | ||
| 153 | #define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 | ||
| 154 | #define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 | ||
| 155 | #define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A | ||
| 156 | #define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F | ||
| 157 | #define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 | ||
| 158 | #define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 | ||
| 159 | #define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E | ||
| 160 | #define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 | ||
| 161 | #define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 | ||
| 162 | #define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF | ||
| 163 | |||
| 164 | #define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 | ||
| 165 | #define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 | ||
| 166 | #define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 | ||
| 167 | #define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 | ||
| 168 | #define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 | ||
| 169 | #define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 | ||
| 170 | #define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 | ||
| 171 | #define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 | ||
| 172 | #define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 | ||
| 173 | #define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 | ||
| 174 | #define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 | ||
| 175 | |||
| 176 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 | ||
| 177 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 | ||
| 178 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 | ||
| 179 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 | ||
| 180 | #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 | ||
| 181 | |||
| 182 | #define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) | ||
| 183 | |||
| 184 | |||
| 185 | /* ------------------------------------------------------------------------ | ||
| 186 | * Integrator system registers | ||
| 187 | * ------------------------------------------------------------------------ | ||
| 188 | * | ||
| 189 | */ | ||
| 190 | |||
| 191 | /* | ||
| 192 | * System Controller | ||
| 193 | * | ||
| 194 | */ | ||
| 195 | #define INTEGRATOR_SC_ID_OFFSET 0x00 | ||
| 196 | #define INTEGRATOR_SC_OSC_OFFSET 0x04 | ||
| 197 | #define INTEGRATOR_SC_CTRLS_OFFSET 0x08 | ||
| 198 | #define INTEGRATOR_SC_CTRLC_OFFSET 0x0C | ||
| 199 | #define INTEGRATOR_SC_DEC_OFFSET 0x10 | ||
| 200 | #define INTEGRATOR_SC_ARB_OFFSET 0x14 | ||
| 201 | #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 | ||
| 202 | #define INTEGRATOR_SC_LOCK_OFFSET 0x1C | ||
| 203 | |||
| 204 | #define INTEGRATOR_SC_BASE 0x11000000 | ||
| 205 | #define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET) | ||
| 206 | #define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET) | ||
| 207 | #define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) | ||
| 208 | #define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) | ||
| 209 | #define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET) | ||
| 210 | #define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET) | ||
| 211 | #define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) | ||
| 212 | #define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET) | ||
| 213 | |||
| 214 | #define INTEGRATOR_SC_OSC_SYS_10MHz 0x20 | ||
| 215 | #define INTEGRATOR_SC_OSC_SYS_15MHz 0x34 | ||
| 216 | #define INTEGRATOR_SC_OSC_SYS_20MHz 0x48 | ||
| 217 | #define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C | ||
| 218 | #define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C | ||
| 219 | #define INTEGRATOR_SC_OSC_SYS_MASK 0xFF | ||
| 220 | |||
| 221 | #define INTEGRATOR_SC_OSC_PCI_25MHz 0x100 | ||
| 222 | #define INTEGRATOR_SC_OSC_PCI_33MHz 0x0 | ||
| 223 | #define INTEGRATOR_SC_OSC_PCI_MASK 0x100 | ||
| 224 | |||
| 225 | #define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0) | ||
| 226 | #define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1) | ||
| 227 | #define INTEGRATOR_SC_CTRL_nFLWP (1 << 2) | ||
| 228 | #define INTEGRATOR_SC_CTRL_URTS0 (1 << 4) | ||
| 229 | #define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5) | ||
| 230 | #define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) | ||
| 231 | #define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) | ||
| 232 | |||
| 233 | /* | ||
| 234 | * External Bus Interface | ||
| 235 | * | ||
| 236 | */ | ||
| 237 | #define INTEGRATOR_EBI_BASE 0x12000000 | ||
| 238 | |||
| 239 | #define INTEGRATOR_EBI_CSR0_OFFSET 0x00 | ||
| 240 | #define INTEGRATOR_EBI_CSR1_OFFSET 0x04 | ||
| 241 | #define INTEGRATOR_EBI_CSR2_OFFSET 0x08 | ||
| 242 | #define INTEGRATOR_EBI_CSR3_OFFSET 0x0C | ||
| 243 | #define INTEGRATOR_EBI_LOCK_OFFSET 0x20 | ||
| 244 | |||
| 245 | #define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET) | ||
| 246 | #define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) | ||
| 247 | #define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET) | ||
| 248 | #define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET) | ||
| 249 | #define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) | ||
| 250 | |||
| 251 | #define INTEGRATOR_EBI_8_BIT 0x00 | ||
| 252 | #define INTEGRATOR_EBI_16_BIT 0x01 | ||
| 253 | #define INTEGRATOR_EBI_32_BIT 0x02 | ||
| 254 | #define INTEGRATOR_EBI_WRITE_ENABLE 0x04 | ||
| 255 | #define INTEGRATOR_EBI_SYNC 0x08 | ||
| 256 | #define INTEGRATOR_EBI_WS_2 0x00 | ||
| 257 | #define INTEGRATOR_EBI_WS_3 0x10 | ||
| 258 | #define INTEGRATOR_EBI_WS_4 0x20 | ||
| 259 | #define INTEGRATOR_EBI_WS_5 0x30 | ||
| 260 | #define INTEGRATOR_EBI_WS_6 0x40 | ||
| 261 | #define INTEGRATOR_EBI_WS_7 0x50 | ||
| 262 | #define INTEGRATOR_EBI_WS_8 0x60 | ||
| 263 | #define INTEGRATOR_EBI_WS_9 0x70 | ||
| 264 | #define INTEGRATOR_EBI_WS_10 0x80 | ||
| 265 | #define INTEGRATOR_EBI_WS_11 0x90 | ||
| 266 | #define INTEGRATOR_EBI_WS_12 0xA0 | ||
| 267 | #define INTEGRATOR_EBI_WS_13 0xB0 | ||
| 268 | #define INTEGRATOR_EBI_WS_14 0xC0 | ||
| 269 | #define INTEGRATOR_EBI_WS_15 0xD0 | ||
| 270 | #define INTEGRATOR_EBI_WS_16 0xE0 | ||
| 271 | #define INTEGRATOR_EBI_WS_17 0xF0 | ||
| 272 | |||
| 273 | |||
| 274 | #define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */ | ||
| 275 | #define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */ | ||
| 276 | #define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */ | ||
| 277 | #define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ | ||
| 278 | #define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ | ||
| 279 | #define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ | ||
| 280 | #define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ | ||
| 281 | |||
| 282 | /* | ||
| 283 | * LED's & Switches | ||
| 284 | * | ||
| 285 | */ | ||
| 286 | #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 | ||
| 287 | #define INTEGRATOR_DBG_LEDS_OFFSET 0x04 | ||
| 288 | #define INTEGRATOR_DBG_SWITCH_OFFSET 0x08 | ||
| 289 | |||
| 290 | #define INTEGRATOR_DBG_BASE 0x1A000000 | ||
| 291 | #define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET) | ||
| 292 | #define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) | ||
| 293 | #define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) | ||
| 294 | |||
| 295 | |||
| 296 | #if defined(CONFIG_ARCH_INTEGRATOR_AP) | ||
| 297 | #define INTEGRATOR_GPIO_BASE 0x1B000000 /* GPIO */ | ||
| 298 | #elif defined(CONFIG_ARCH_INTEGRATOR_CP) | ||
| 299 | #define INTEGRATOR_GPIO_BASE 0xC9000000 /* GPIO */ | ||
| 300 | #endif | ||
| 301 | |||
| 302 | /* ------------------------------------------------------------------------ | ||
| 303 | * KMI keyboard/mouse definitions | ||
| 304 | * ------------------------------------------------------------------------ | ||
| 305 | */ | ||
| 306 | /* PS2 Keyboard interface */ | ||
| 307 | #define KMI0_BASE INTEGRATOR_KBD_BASE | ||
| 308 | |||
| 309 | /* PS2 Mouse interface */ | ||
| 310 | #define KMI1_BASE INTEGRATOR_MOUSE_BASE | ||
| 311 | |||
| 312 | /* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */ | ||
| 313 | |||
| 314 | /* ------------------------------------------------------------------------ | ||
| 315 | * Where in the memory map does PCI live? | ||
| 316 | * ------------------------------------------------------------------------ | ||
| 317 | * This represents a fairly liberal usage of address space. Even though | ||
| 318 | * the V3 only has two windows (therefore we need to map stuff on the fly), | ||
| 319 | * we maintain the same addresses, even if they're not mapped. | ||
| 320 | * | ||
| 321 | */ | ||
| 322 | #define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */ | ||
| 323 | /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? | ||
| 324 | */ | ||
| 325 | #define PHYS_PCI_IO_BASE 0x60000000 /* 16M to xxx */ | ||
| 326 | /* unused (128-16)M from B1000000-B7FFFFFF | ||
| 327 | */ | ||
| 328 | #define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ | ||
| 329 | /* unused ((128-16)M - 64K) from XXX | ||
| 330 | */ | ||
| 331 | #define PHYS_PCI_V3_BASE 0x62000000 | ||
| 332 | |||
| 333 | #define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE | ||
| 334 | |||
| 335 | /* 'export' these to UHAL */ | ||
| 336 | #define UHAL_PCI_IO PCI_IO_BASE | ||
| 337 | #define UHAL_PCI_MEM PCI_MEM_BASE | ||
| 338 | #define UHAL_PCI_ALLOC_IO_BASE 0x00004000 | ||
| 339 | #define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE | ||
| 340 | #define UHAL_PCI_MAX_SLOT 20 | ||
| 341 | |||
| 342 | /* ======================================================================== | ||
| 343 | * Start of uHAL definitions | ||
| 344 | * ======================================================================== | ||
| 345 | */ | ||
| 346 | |||
| 347 | /* ------------------------------------------------------------------------ | ||
| 348 | * Integrator Interrupt Controllers | ||
| 349 | * ------------------------------------------------------------------------ | ||
| 350 | * | ||
| 351 | * Offsets from interrupt controller base | ||
| 352 | * | ||
| 353 | * System Controller interrupt controller base is | ||
| 354 | * | ||
| 355 | * INTEGRATOR_IC_BASE + (header_number << 6) | ||
| 356 | * | ||
| 357 | * Core Module interrupt controller base is | ||
| 358 | * | ||
| 359 | * INTEGRATOR_HDR_IC | ||
| 360 | * | ||
| 361 | */ | ||
| 362 | #define IRQ_STATUS 0 | ||
| 363 | #define IRQ_RAW_STATUS 0x04 | ||
| 364 | #define IRQ_ENABLE 0x08 | ||
| 365 | #define IRQ_ENABLE_SET 0x08 | ||
| 366 | #define IRQ_ENABLE_CLEAR 0x0C | ||
| 367 | |||
| 368 | #define INT_SOFT_SET 0x10 | ||
| 369 | #define INT_SOFT_CLEAR 0x14 | ||
| 370 | |||
| 371 | #define FIQ_STATUS 0x20 | ||
| 372 | #define FIQ_RAW_STATUS 0x24 | ||
| 373 | #define FIQ_ENABLE 0x28 | ||
| 374 | #define FIQ_ENABLE_SET 0x28 | ||
| 375 | #define FIQ_ENABLE_CLEAR 0x2C | ||
| 376 | |||
| 377 | |||
| 378 | /* ------------------------------------------------------------------------ | ||
| 379 | * Interrupts | ||
| 380 | * ------------------------------------------------------------------------ | ||
| 381 | * | ||
| 382 | * | ||
| 383 | * Each Core Module has two interrupts controllers, one on the core module | ||
| 384 | * itself and one in the system controller on the motherboard. The | ||
| 385 | * READ_INT macro in target.s reads both interrupt controllers and returns | ||
| 386 | * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller | ||
| 387 | * and bits 24 to 31 are from the core module. | ||
| 388 | * | ||
| 389 | * The following definitions relate to the bitmask returned by READ_INT. | ||
| 390 | * | ||
| 391 | */ | ||
| 392 | |||
| 393 | /* ------------------------------------------------------------------------ | ||
| 394 | * LED's - The header LED is not accessible via the uHAL API | ||
| 395 | * ------------------------------------------------------------------------ | ||
| 396 | * | ||
| 397 | */ | ||
| 398 | #define GREEN_LED 0x01 | ||
| 399 | #define YELLOW_LED 0x02 | ||
| 400 | #define RED_LED 0x04 | ||
| 401 | #define GREEN_LED_2 0x08 | ||
| 402 | #define ALL_LEDS 0x0F | ||
| 403 | |||
| 404 | #define LED_BANK INTEGRATOR_DBG_LEDS | ||
| 405 | |||
| 406 | /* | ||
| 407 | * Memory definitions - run uHAL out of SSRAM. | ||
| 408 | * | ||
| 409 | */ | ||
| 410 | #define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE | ||
| 411 | |||
| 412 | /* | ||
| 413 | * Application Flash | ||
| 414 | * | ||
| 415 | */ | ||
| 416 | #define FLASH_BASE INTEGRATOR_FLASH_BASE | ||
| 417 | #define FLASH_SIZE INTEGRATOR_FLASH_SIZE | ||
| 418 | #define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) | ||
| 419 | #define FLASH_BLOCK_SIZE SZ_128K | ||
| 420 | |||
| 421 | /* | ||
| 422 | * Boot Flash | ||
| 423 | * | ||
| 424 | */ | ||
| 425 | #define EPROM_BASE INTEGRATOR_BOOT_ROM_HI | ||
| 426 | #define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE | ||
| 427 | #define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) | ||
| 428 | |||
| 429 | /* | ||
| 430 | * Clean base - dummy | ||
| 431 | * | ||
| 432 | */ | ||
| 433 | #define CLEAN_BASE EPROM_BASE | ||
| 434 | |||
| 435 | /* | ||
| 436 | * Timer definitions | ||
| 437 | * | ||
| 438 | * Only use timer 1 & 2 | ||
| 439 | * (both run at 24MHz and will need the clock divider set to 16). | ||
| 440 | * | ||
| 441 | * Timer 0 runs at bus frequency and therefore could vary and currently | ||
| 442 | * uHAL can't handle that. | ||
| 443 | * | ||
| 444 | */ | ||
| 445 | |||
| 446 | #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE | ||
| 447 | #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) | ||
| 448 | #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) | ||
| 449 | |||
| 450 | #define MAX_TIMER 2 | ||
| 451 | #define MAX_PERIOD 699050 | ||
| 452 | #define TICKS_PER_uSEC 24 | ||
| 453 | |||
| 454 | /* | ||
| 455 | * These are useconds NOT ticks. | ||
| 456 | * | ||
| 457 | */ | ||
| 458 | #define mSEC_1 1000 | ||
| 459 | #define mSEC_5 (mSEC_1 * 5) | ||
| 460 | #define mSEC_10 (mSEC_1 * 10) | ||
| 461 | #define mSEC_25 (mSEC_1 * 25) | ||
| 462 | #define SEC_1 (mSEC_1 * 1000) | ||
| 463 | |||
| 464 | #define INTEGRATOR_CSR_BASE 0x10000000 | ||
| 465 | #define INTEGRATOR_CSR_SIZE 0x10000000 | ||
| 466 | |||
| 467 | #endif | ||
| 468 | |||
| 469 | /* END */ | ||
diff --git a/include/asm-arm/arch-integrator/system.h b/include/asm-arm/arch-integrator/system.h deleted file mode 100644 index 8ea442237d20..000000000000 --- a/include/asm-arm/arch-integrator/system.h +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-integrator/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 22 | #define __ASM_ARCH_SYSTEM_H | ||
| 23 | |||
| 24 | #include <asm/arch/cm.h> | ||
| 25 | |||
| 26 | static inline void arch_idle(void) | ||
| 27 | { | ||
| 28 | /* | ||
| 29 | * This should do all the clock switching | ||
| 30 | * and wait for interrupt tricks | ||
| 31 | */ | ||
| 32 | cpu_do_idle(); | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline void arch_reset(char mode) | ||
| 36 | { | ||
| 37 | /* | ||
| 38 | * To reset, we hit the on-board reset register | ||
| 39 | * in the system FPGA | ||
| 40 | */ | ||
| 41 | cm_control(CM_CTRL_RESET, CM_CTRL_RESET); | ||
| 42 | } | ||
| 43 | |||
| 44 | #endif | ||
diff --git a/include/asm-arm/arch-integrator/timex.h b/include/asm-arm/arch-integrator/timex.h deleted file mode 100644 index 87a762818ba2..000000000000 --- a/include/asm-arm/arch-integrator/timex.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-integrator/timex.h | ||
| 3 | * | ||
| 4 | * Integrator architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 1999 ARM Limited | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | /* | ||
| 24 | * ?? | ||
| 25 | */ | ||
| 26 | #define CLOCK_TICK_RATE (50000000 / 16) | ||
diff --git a/include/asm-arm/arch-integrator/uncompress.h b/include/asm-arm/arch-integrator/uncompress.h deleted file mode 100644 index f61825c4d901..000000000000 --- a/include/asm-arm/arch-integrator/uncompress.h +++ /dev/null | |||
| @@ -1,50 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-integrator/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #define AMBA_UART_DR (*(volatile unsigned char *)0x16000000) | ||
| 22 | #define AMBA_UART_LCRH (*(volatile unsigned char *)0x16000008) | ||
| 23 | #define AMBA_UART_LCRM (*(volatile unsigned char *)0x1600000c) | ||
| 24 | #define AMBA_UART_LCRL (*(volatile unsigned char *)0x16000010) | ||
| 25 | #define AMBA_UART_CR (*(volatile unsigned char *)0x16000014) | ||
| 26 | #define AMBA_UART_FR (*(volatile unsigned char *)0x16000018) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * This does not append a newline | ||
| 30 | */ | ||
| 31 | static void putc(int c) | ||
| 32 | { | ||
| 33 | while (AMBA_UART_FR & (1 << 5)) | ||
| 34 | barrier(); | ||
| 35 | |||
| 36 | AMBA_UART_DR = c; | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void flush(void) | ||
| 40 | { | ||
| 41 | while (AMBA_UART_FR & (1 << 3)) | ||
| 42 | barrier(); | ||
| 43 | } | ||
| 44 | |||
| 45 | /* | ||
| 46 | * nothing to do | ||
| 47 | */ | ||
| 48 | #define arch_decomp_setup() | ||
| 49 | |||
| 50 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-integrator/vmalloc.h b/include/asm-arm/arch-integrator/vmalloc.h deleted file mode 100644 index 170cccece523..000000000000 --- a/include/asm-arm/arch-integrator/vmalloc.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-integrator/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h deleted file mode 100644 index 26f60af67168..000000000000 --- a/include/asm-arm/arch-iop13xx/adma.h +++ /dev/null | |||
| @@ -1,537 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright(c) 2006, Intel Corporation. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms and conditions of the GNU General Public License, | ||
| 6 | * version 2, as published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 11 | * more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License along with | ||
| 14 | * this program; if not, write to the Free Software Foundation, Inc., | ||
| 15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | #ifndef _ADMA_H | ||
| 19 | #define _ADMA_H | ||
| 20 | #include <linux/types.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | #include <asm/arch/hardware.h> | ||
| 23 | #include <asm/hardware/iop_adma.h> | ||
| 24 | |||
| 25 | #define ADMA_ACCR(chan) (chan->mmr_base + 0x0) | ||
| 26 | #define ADMA_ACSR(chan) (chan->mmr_base + 0x4) | ||
| 27 | #define ADMA_ADAR(chan) (chan->mmr_base + 0x8) | ||
| 28 | #define ADMA_IIPCR(chan) (chan->mmr_base + 0x18) | ||
| 29 | #define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c) | ||
| 30 | #define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20) | ||
| 31 | #define ADMA_ANDAR(chan) (chan->mmr_base + 0x24) | ||
| 32 | #define ADMA_ADCR(chan) (chan->mmr_base + 0x28) | ||
| 33 | #define ADMA_CARMD(chan) (chan->mmr_base + 0x2c) | ||
| 34 | #define ADMA_ABCR(chan) (chan->mmr_base + 0x30) | ||
| 35 | #define ADMA_DLADR(chan) (chan->mmr_base + 0x34) | ||
| 36 | #define ADMA_DUADR(chan) (chan->mmr_base + 0x38) | ||
| 37 | #define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3))) | ||
| 38 | #define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3))) | ||
| 39 | |||
| 40 | struct iop13xx_adma_src { | ||
| 41 | u32 src_addr; | ||
| 42 | union { | ||
| 43 | u32 upper_src_addr; | ||
| 44 | struct { | ||
| 45 | unsigned int pq_upper_src_addr:24; | ||
| 46 | unsigned int pq_dmlt:8; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | struct iop13xx_adma_desc_ctrl { | ||
| 52 | unsigned int int_en:1; | ||
| 53 | unsigned int xfer_dir:2; | ||
| 54 | unsigned int src_select:4; | ||
| 55 | unsigned int zero_result:1; | ||
| 56 | unsigned int block_fill_en:1; | ||
| 57 | unsigned int crc_gen_en:1; | ||
| 58 | unsigned int crc_xfer_dis:1; | ||
| 59 | unsigned int crc_seed_fetch_dis:1; | ||
| 60 | unsigned int status_write_back_en:1; | ||
| 61 | unsigned int endian_swap_en:1; | ||
| 62 | unsigned int reserved0:2; | ||
| 63 | unsigned int pq_update_xfer_en:1; | ||
| 64 | unsigned int dual_xor_en:1; | ||
| 65 | unsigned int pq_xfer_en:1; | ||
| 66 | unsigned int p_xfer_dis:1; | ||
| 67 | unsigned int reserved1:10; | ||
| 68 | unsigned int relax_order_en:1; | ||
| 69 | unsigned int no_snoop_en:1; | ||
| 70 | }; | ||
| 71 | |||
| 72 | struct iop13xx_adma_byte_count { | ||
| 73 | unsigned int byte_count:24; | ||
| 74 | unsigned int host_if:3; | ||
| 75 | unsigned int reserved:2; | ||
| 76 | unsigned int zero_result_err_q:1; | ||
| 77 | unsigned int zero_result_err:1; | ||
| 78 | unsigned int tx_complete:1; | ||
| 79 | }; | ||
| 80 | |||
| 81 | struct iop13xx_adma_desc_hw { | ||
| 82 | u32 next_desc; | ||
| 83 | union { | ||
| 84 | u32 desc_ctrl; | ||
| 85 | struct iop13xx_adma_desc_ctrl desc_ctrl_field; | ||
| 86 | }; | ||
| 87 | union { | ||
| 88 | u32 crc_addr; | ||
| 89 | u32 block_fill_data; | ||
| 90 | u32 q_dest_addr; | ||
| 91 | }; | ||
| 92 | union { | ||
| 93 | u32 byte_count; | ||
| 94 | struct iop13xx_adma_byte_count byte_count_field; | ||
| 95 | }; | ||
| 96 | union { | ||
| 97 | u32 dest_addr; | ||
| 98 | u32 p_dest_addr; | ||
| 99 | }; | ||
| 100 | union { | ||
| 101 | u32 upper_dest_addr; | ||
| 102 | u32 pq_upper_dest_addr; | ||
| 103 | }; | ||
| 104 | struct iop13xx_adma_src src[1]; | ||
| 105 | }; | ||
| 106 | |||
| 107 | struct iop13xx_adma_desc_dual_xor { | ||
| 108 | u32 next_desc; | ||
| 109 | u32 desc_ctrl; | ||
| 110 | u32 reserved; | ||
| 111 | u32 byte_count; | ||
| 112 | u32 h_dest_addr; | ||
| 113 | u32 h_upper_dest_addr; | ||
| 114 | u32 src0_addr; | ||
| 115 | u32 upper_src0_addr; | ||
| 116 | u32 src1_addr; | ||
| 117 | u32 upper_src1_addr; | ||
| 118 | u32 h_src_addr; | ||
| 119 | u32 h_upper_src_addr; | ||
| 120 | u32 d_src_addr; | ||
| 121 | u32 d_upper_src_addr; | ||
| 122 | u32 d_dest_addr; | ||
| 123 | u32 d_upper_dest_addr; | ||
| 124 | }; | ||
| 125 | |||
| 126 | struct iop13xx_adma_desc_pq_update { | ||
| 127 | u32 next_desc; | ||
| 128 | u32 desc_ctrl; | ||
| 129 | u32 reserved; | ||
| 130 | u32 byte_count; | ||
| 131 | u32 p_dest_addr; | ||
| 132 | u32 p_upper_dest_addr; | ||
| 133 | u32 src0_addr; | ||
| 134 | u32 upper_src0_addr; | ||
| 135 | u32 src1_addr; | ||
| 136 | u32 upper_src1_addr; | ||
| 137 | u32 p_src_addr; | ||
| 138 | u32 p_upper_src_addr; | ||
| 139 | u32 q_src_addr; | ||
| 140 | struct { | ||
| 141 | unsigned int q_upper_src_addr:24; | ||
| 142 | unsigned int q_dmlt:8; | ||
| 143 | }; | ||
| 144 | u32 q_dest_addr; | ||
| 145 | u32 q_upper_dest_addr; | ||
| 146 | }; | ||
| 147 | |||
| 148 | static inline int iop_adma_get_max_xor(void) | ||
| 149 | { | ||
| 150 | return 16; | ||
| 151 | } | ||
| 152 | |||
| 153 | static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) | ||
| 154 | { | ||
| 155 | return __raw_readl(ADMA_ADAR(chan)); | ||
| 156 | } | ||
| 157 | |||
| 158 | static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, | ||
| 159 | u32 next_desc_addr) | ||
| 160 | { | ||
| 161 | __raw_writel(next_desc_addr, ADMA_ANDAR(chan)); | ||
| 162 | } | ||
| 163 | |||
| 164 | #define ADMA_STATUS_BUSY (1 << 13) | ||
| 165 | |||
| 166 | static inline char iop_chan_is_busy(struct iop_adma_chan *chan) | ||
| 167 | { | ||
| 168 | if (__raw_readl(ADMA_ACSR(chan)) & | ||
| 169 | ADMA_STATUS_BUSY) | ||
| 170 | return 1; | ||
| 171 | else | ||
| 172 | return 0; | ||
| 173 | } | ||
| 174 | |||
| 175 | static inline int | ||
| 176 | iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots) | ||
| 177 | { | ||
| 178 | return 1; | ||
| 179 | } | ||
| 180 | #define iop_desc_is_aligned(x, y) 1 | ||
| 181 | |||
| 182 | static inline int | ||
| 183 | iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) | ||
| 184 | { | ||
| 185 | *slots_per_op = 1; | ||
| 186 | return 1; | ||
| 187 | } | ||
| 188 | |||
| 189 | #define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s) | ||
| 190 | |||
| 191 | static inline int | ||
| 192 | iop_chan_memset_slot_count(size_t len, int *slots_per_op) | ||
| 193 | { | ||
| 194 | *slots_per_op = 1; | ||
| 195 | return 1; | ||
| 196 | } | ||
| 197 | |||
| 198 | static inline int | ||
| 199 | iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op) | ||
| 200 | { | ||
| 201 | static const char slot_count_table[] = { 1, 2, 2, 2, | ||
| 202 | 2, 3, 3, 3, | ||
| 203 | 3, 4, 4, 4, | ||
| 204 | 4, 5, 5, 5, | ||
| 205 | }; | ||
| 206 | *slots_per_op = slot_count_table[src_cnt - 1]; | ||
| 207 | return *slots_per_op; | ||
| 208 | } | ||
| 209 | |||
| 210 | #define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) | ||
| 211 | #define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT | ||
| 212 | #define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT | ||
| 213 | #define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT | ||
| 214 | #define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o) | ||
| 215 | |||
| 216 | static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc, | ||
| 217 | struct iop_adma_chan *chan) | ||
| 218 | { | ||
| 219 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 220 | return hw_desc->dest_addr; | ||
| 221 | } | ||
| 222 | |||
| 223 | static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, | ||
| 224 | struct iop_adma_chan *chan) | ||
| 225 | { | ||
| 226 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 227 | return hw_desc->byte_count_field.byte_count; | ||
| 228 | } | ||
| 229 | |||
| 230 | static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, | ||
| 231 | struct iop_adma_chan *chan, | ||
| 232 | int src_idx) | ||
| 233 | { | ||
| 234 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 235 | return hw_desc->src[src_idx].src_addr; | ||
| 236 | } | ||
| 237 | |||
| 238 | static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc, | ||
| 239 | struct iop_adma_chan *chan) | ||
| 240 | { | ||
| 241 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 242 | return hw_desc->desc_ctrl_field.src_select + 1; | ||
| 243 | } | ||
| 244 | |||
| 245 | static inline void | ||
| 246 | iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) | ||
| 247 | { | ||
| 248 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 249 | union { | ||
| 250 | u32 value; | ||
| 251 | struct iop13xx_adma_desc_ctrl field; | ||
| 252 | } u_desc_ctrl; | ||
| 253 | |||
| 254 | u_desc_ctrl.value = 0; | ||
| 255 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ | ||
| 256 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; | ||
| 257 | hw_desc->desc_ctrl = u_desc_ctrl.value; | ||
| 258 | hw_desc->crc_addr = 0; | ||
| 259 | } | ||
| 260 | |||
| 261 | static inline void | ||
| 262 | iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) | ||
| 263 | { | ||
| 264 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 265 | union { | ||
| 266 | u32 value; | ||
| 267 | struct iop13xx_adma_desc_ctrl field; | ||
| 268 | } u_desc_ctrl; | ||
| 269 | |||
| 270 | u_desc_ctrl.value = 0; | ||
| 271 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ | ||
| 272 | u_desc_ctrl.field.block_fill_en = 1; | ||
| 273 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; | ||
| 274 | hw_desc->desc_ctrl = u_desc_ctrl.value; | ||
| 275 | hw_desc->crc_addr = 0; | ||
| 276 | } | ||
| 277 | |||
| 278 | /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ | ||
| 279 | static inline void | ||
| 280 | iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, | ||
| 281 | unsigned long flags) | ||
| 282 | { | ||
| 283 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 284 | union { | ||
| 285 | u32 value; | ||
| 286 | struct iop13xx_adma_desc_ctrl field; | ||
| 287 | } u_desc_ctrl; | ||
| 288 | |||
| 289 | u_desc_ctrl.value = 0; | ||
| 290 | u_desc_ctrl.field.src_select = src_cnt - 1; | ||
| 291 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ | ||
| 292 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; | ||
| 293 | hw_desc->desc_ctrl = u_desc_ctrl.value; | ||
| 294 | hw_desc->crc_addr = 0; | ||
| 295 | |||
| 296 | } | ||
| 297 | #define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i) | ||
| 298 | |||
| 299 | /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ | ||
| 300 | static inline int | ||
| 301 | iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, | ||
| 302 | unsigned long flags) | ||
| 303 | { | ||
| 304 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 305 | union { | ||
| 306 | u32 value; | ||
| 307 | struct iop13xx_adma_desc_ctrl field; | ||
| 308 | } u_desc_ctrl; | ||
| 309 | |||
| 310 | u_desc_ctrl.value = 0; | ||
| 311 | u_desc_ctrl.field.src_select = src_cnt - 1; | ||
| 312 | u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ | ||
| 313 | u_desc_ctrl.field.zero_result = 1; | ||
| 314 | u_desc_ctrl.field.status_write_back_en = 1; | ||
| 315 | u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; | ||
| 316 | hw_desc->desc_ctrl = u_desc_ctrl.value; | ||
| 317 | hw_desc->crc_addr = 0; | ||
| 318 | |||
| 319 | return 1; | ||
| 320 | } | ||
| 321 | |||
| 322 | static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, | ||
| 323 | struct iop_adma_chan *chan, | ||
| 324 | u32 byte_count) | ||
| 325 | { | ||
| 326 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 327 | hw_desc->byte_count = byte_count; | ||
| 328 | } | ||
| 329 | |||
| 330 | static inline void | ||
| 331 | iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) | ||
| 332 | { | ||
| 333 | int slots_per_op = desc->slots_per_op; | ||
| 334 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; | ||
| 335 | int i = 0; | ||
| 336 | |||
| 337 | if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { | ||
| 338 | hw_desc->byte_count = len; | ||
| 339 | } else { | ||
| 340 | do { | ||
| 341 | iter = iop_hw_desc_slot_idx(hw_desc, i); | ||
| 342 | iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; | ||
| 343 | len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; | ||
| 344 | i += slots_per_op; | ||
| 345 | } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); | ||
| 346 | |||
| 347 | if (len) { | ||
| 348 | iter = iop_hw_desc_slot_idx(hw_desc, i); | ||
| 349 | iter->byte_count = len; | ||
| 350 | } | ||
| 351 | } | ||
| 352 | } | ||
| 353 | |||
| 354 | |||
| 355 | static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, | ||
| 356 | struct iop_adma_chan *chan, | ||
| 357 | dma_addr_t addr) | ||
| 358 | { | ||
| 359 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 360 | hw_desc->dest_addr = addr; | ||
| 361 | hw_desc->upper_dest_addr = 0; | ||
| 362 | } | ||
| 363 | |||
| 364 | static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, | ||
| 365 | dma_addr_t addr) | ||
| 366 | { | ||
| 367 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 368 | hw_desc->src[0].src_addr = addr; | ||
| 369 | hw_desc->src[0].upper_src_addr = 0; | ||
| 370 | } | ||
| 371 | |||
| 372 | static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, | ||
| 373 | int src_idx, dma_addr_t addr) | ||
| 374 | { | ||
| 375 | int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; | ||
| 376 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter; | ||
| 377 | int i = 0; | ||
| 378 | |||
| 379 | do { | ||
| 380 | iter = iop_hw_desc_slot_idx(hw_desc, i); | ||
| 381 | iter->src[src_idx].src_addr = addr; | ||
| 382 | iter->src[src_idx].upper_src_addr = 0; | ||
| 383 | slot_cnt -= slots_per_op; | ||
| 384 | if (slot_cnt) { | ||
| 385 | i += slots_per_op; | ||
| 386 | addr += IOP_ADMA_XOR_MAX_BYTE_COUNT; | ||
| 387 | } | ||
| 388 | } while (slot_cnt); | ||
| 389 | } | ||
| 390 | |||
| 391 | static inline void | ||
| 392 | iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, | ||
| 393 | struct iop_adma_chan *chan) | ||
| 394 | { | ||
| 395 | iop_desc_init_memcpy(desc, 1); | ||
| 396 | iop_desc_set_byte_count(desc, chan, 0); | ||
| 397 | iop_desc_set_dest_addr(desc, chan, 0); | ||
| 398 | iop_desc_set_memcpy_src_addr(desc, 0); | ||
| 399 | } | ||
| 400 | |||
| 401 | #define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr | ||
| 402 | |||
| 403 | static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, | ||
| 404 | u32 next_desc_addr) | ||
| 405 | { | ||
| 406 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 407 | BUG_ON(hw_desc->next_desc); | ||
| 408 | hw_desc->next_desc = next_desc_addr; | ||
| 409 | } | ||
| 410 | |||
| 411 | static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) | ||
| 412 | { | ||
| 413 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 414 | return hw_desc->next_desc; | ||
| 415 | } | ||
| 416 | |||
| 417 | static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) | ||
| 418 | { | ||
| 419 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 420 | hw_desc->next_desc = 0; | ||
| 421 | } | ||
| 422 | |||
| 423 | static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, | ||
| 424 | u32 val) | ||
| 425 | { | ||
| 426 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 427 | hw_desc->block_fill_data = val; | ||
| 428 | } | ||
| 429 | |||
| 430 | static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) | ||
| 431 | { | ||
| 432 | struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; | ||
| 433 | struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; | ||
| 434 | struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field; | ||
| 435 | |||
| 436 | BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result)); | ||
| 437 | |||
| 438 | if (desc_ctrl.pq_xfer_en) | ||
| 439 | return byte_count.zero_result_err_q; | ||
| 440 | else | ||
| 441 | return byte_count.zero_result_err; | ||
| 442 | } | ||
| 443 | |||
| 444 | static inline void iop_chan_append(struct iop_adma_chan *chan) | ||
| 445 | { | ||
| 446 | u32 adma_accr; | ||
| 447 | |||
| 448 | adma_accr = __raw_readl(ADMA_ACCR(chan)); | ||
| 449 | adma_accr |= 0x2; | ||
| 450 | __raw_writel(adma_accr, ADMA_ACCR(chan)); | ||
| 451 | } | ||
| 452 | |||
| 453 | static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) | ||
| 454 | { | ||
| 455 | return __raw_readl(ADMA_ACSR(chan)); | ||
| 456 | } | ||
| 457 | |||
| 458 | static inline void iop_chan_disable(struct iop_adma_chan *chan) | ||
| 459 | { | ||
| 460 | u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); | ||
| 461 | adma_chan_ctrl &= ~0x1; | ||
| 462 | __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); | ||
| 463 | } | ||
| 464 | |||
| 465 | static inline void iop_chan_enable(struct iop_adma_chan *chan) | ||
| 466 | { | ||
| 467 | u32 adma_chan_ctrl; | ||
| 468 | |||
| 469 | adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan)); | ||
| 470 | adma_chan_ctrl |= 0x1; | ||
| 471 | __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan)); | ||
| 472 | } | ||
| 473 | |||
| 474 | static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) | ||
| 475 | { | ||
| 476 | u32 status = __raw_readl(ADMA_ACSR(chan)); | ||
| 477 | status &= (1 << 12); | ||
| 478 | __raw_writel(status, ADMA_ACSR(chan)); | ||
| 479 | } | ||
| 480 | |||
| 481 | static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) | ||
| 482 | { | ||
| 483 | u32 status = __raw_readl(ADMA_ACSR(chan)); | ||
| 484 | status &= (1 << 11); | ||
| 485 | __raw_writel(status, ADMA_ACSR(chan)); | ||
| 486 | } | ||
| 487 | |||
| 488 | static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) | ||
| 489 | { | ||
| 490 | u32 status = __raw_readl(ADMA_ACSR(chan)); | ||
| 491 | status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3); | ||
| 492 | __raw_writel(status, ADMA_ACSR(chan)); | ||
| 493 | } | ||
| 494 | |||
| 495 | static inline int | ||
| 496 | iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) | ||
| 497 | { | ||
| 498 | return test_bit(9, &status); | ||
| 499 | } | ||
| 500 | |||
| 501 | static inline int | ||
| 502 | iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) | ||
| 503 | { | ||
| 504 | return test_bit(5, &status); | ||
| 505 | } | ||
| 506 | |||
| 507 | static inline int | ||
| 508 | iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) | ||
| 509 | { | ||
| 510 | return test_bit(4, &status); | ||
| 511 | } | ||
| 512 | |||
| 513 | static inline int | ||
| 514 | iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) | ||
| 515 | { | ||
| 516 | return test_bit(3, &status); | ||
| 517 | } | ||
| 518 | |||
| 519 | static inline int | ||
| 520 | iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) | ||
| 521 | { | ||
| 522 | return 0; | ||
| 523 | } | ||
| 524 | |||
| 525 | static inline int | ||
| 526 | iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) | ||
| 527 | { | ||
| 528 | return 0; | ||
| 529 | } | ||
| 530 | |||
| 531 | static inline int | ||
| 532 | iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) | ||
| 533 | { | ||
| 534 | return 0; | ||
| 535 | } | ||
| 536 | |||
| 537 | #endif /* _ADMA_H */ | ||
diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S deleted file mode 100644 index 788b4e386c16..000000000000 --- a/include/asm-arm/arch-iop13xx/debug-macro.S +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop13xx/debug-macro.S | ||
| 3 | * | ||
| 4 | * Debugging macro include header | ||
| 5 | * | ||
| 6 | * Copyright (C) 1994-1999 Russell King | ||
| 7 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart, rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ mmu enabled? | ||
| 17 | moveq \rx, #0xff000000 @ physical | ||
| 18 | orreq \rx, \rx, #0x00d80000 | ||
| 19 | movne \rx, #0xfe000000 @ virtual | ||
| 20 | orrne \rx, \rx, #0x00e80000 | ||
| 21 | orr \rx, \rx, #0x00002300 | ||
| 22 | orr \rx, \rx, #0x00000040 | ||
| 23 | .endm | ||
| 24 | |||
| 25 | #define UART_SHIFT 2 | ||
| 26 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h deleted file mode 100644 index d79846fbb394..000000000000 --- a/include/asm-arm/arch-iop13xx/dma.h +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | #ifndef _IOP13XX_DMA_H | ||
| 2 | #define _IOP13XX_DMA_H | ||
| 3 | #endif | ||
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S deleted file mode 100644 index a624a7870c64..000000000000 --- a/include/asm-arm/arch-iop13xx/entry-macro.S +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * iop13xx low level irq macros | ||
| 3 | * Copyright (c) 2005-2006, Intel Corporation. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms and conditions of the GNU General Public License, | ||
| 7 | * version 2, as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along with | ||
| 15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | ||
| 16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | ||
| 17 | * | ||
| 18 | */ | ||
| 19 | .macro disable_fiq | ||
| 20 | .endm | ||
| 21 | |||
| 22 | .macro get_irqnr_preamble, base, tmp | ||
| 23 | mrc p15, 0, \tmp, c15, c1, 0 | ||
| 24 | orr \tmp, \tmp, #(1 << 6) | ||
| 25 | mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access | ||
| 26 | .endm | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Note: a 1-cycle window exists where iintvec will return the value | ||
| 30 | * of iintbase, so we explicitly check for "bad zeros" | ||
| 31 | */ | ||
| 32 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 33 | mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC | ||
| 34 | cmp \irqnr, #0 | ||
| 35 | mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero | ||
| 36 | adds \irqstat, \irqnr, #1 @ Check for 0xffffffff | ||
| 37 | movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr | ||
| 38 | .endm | ||
| 39 | |||
| 40 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 41 | mrc p15, 0, \tmp1, c15, c1, 0 | ||
| 42 | ands \tmp2, \tmp1, #(1 << 6) | ||
| 43 | bicne \tmp1, \tmp1, #(1 << 6) | ||
| 44 | mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access | ||
| 45 | .endm | ||
diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h deleted file mode 100644 index 8e1d56289846..000000000000 --- a/include/asm-arm/arch-iop13xx/hardware.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 2 | #define __ASM_ARCH_HARDWARE_H | ||
| 3 | #include <asm/types.h> | ||
| 4 | |||
| 5 | #define pcibios_assign_all_busses() 1 | ||
| 6 | |||
| 7 | #ifndef __ASSEMBLY__ | ||
| 8 | extern unsigned long iop13xx_pcibios_min_io; | ||
| 9 | extern unsigned long iop13xx_pcibios_min_mem; | ||
| 10 | extern u16 iop13xx_dev_id(void); | ||
| 11 | extern void iop13xx_set_atu_mmr_bases(void); | ||
| 12 | #endif | ||
| 13 | |||
| 14 | #define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io) | ||
| 15 | #define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem) | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Generic chipset bits | ||
| 19 | * | ||
| 20 | */ | ||
| 21 | #include "iop13xx.h" | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Board specific bits | ||
| 25 | */ | ||
| 26 | #include "iq81340.h" | ||
| 27 | |||
| 28 | #endif /* _ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h deleted file mode 100644 index a6e0f9e6ddcf..000000000000 --- a/include/asm-arm/arch-iop13xx/io.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * iop13xx custom ioremap implementation | ||
| 3 | * Copyright (c) 2005-2006, Intel Corporation. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms and conditions of the GNU General Public License, | ||
| 7 | * version 2, as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along with | ||
| 15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | ||
| 16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | ||
| 17 | * | ||
| 18 | */ | ||
| 19 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 20 | #define __ASM_ARM_ARCH_IO_H | ||
| 21 | |||
| 22 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 23 | |||
| 24 | #define __io(a) __iop13xx_io(a) | ||
| 25 | #define __mem_pci(a) (a) | ||
| 26 | #define __mem_isa(a) (a) | ||
| 27 | |||
| 28 | extern void __iomem * __iop13xx_io(unsigned long io_addr); | ||
| 29 | extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, | ||
| 30 | unsigned int mtype); | ||
| 31 | extern void __iop13xx_iounmap(void __iomem *addr); | ||
| 32 | |||
| 33 | extern u32 iop13xx_atue_mem_base; | ||
| 34 | extern u32 iop13xx_atux_mem_base; | ||
| 35 | extern size_t iop13xx_atue_mem_size; | ||
| 36 | extern size_t iop13xx_atux_mem_size; | ||
| 37 | |||
| 38 | #define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f) | ||
| 39 | #define __arch_iounmap(a) __iop13xx_iounmap(a) | ||
| 40 | |||
| 41 | #endif | ||
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h deleted file mode 100644 index 52b7fab7ef60..000000000000 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ /dev/null | |||
| @@ -1,526 +0,0 @@ | |||
| 1 | #ifndef _IOP13XX_HW_H_ | ||
| 2 | #define _IOP13XX_HW_H_ | ||
| 3 | |||
| 4 | #ifndef __ASSEMBLY__ | ||
| 5 | /* The ATU offsets can change based on the strapping */ | ||
| 6 | extern u32 iop13xx_atux_pmmr_offset; | ||
| 7 | extern u32 iop13xx_atue_pmmr_offset; | ||
| 8 | void iop13xx_init_irq(void); | ||
| 9 | void iop13xx_map_io(void); | ||
| 10 | void iop13xx_platform_init(void); | ||
| 11 | void iop13xx_add_tpmi_devices(void); | ||
| 12 | void iop13xx_init_irq(void); | ||
| 13 | |||
| 14 | /* CPUID CP6 R0 Page 0 */ | ||
| 15 | static inline int iop13xx_cpu_id(void) | ||
| 16 | { | ||
| 17 | int id; | ||
| 18 | asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id)); | ||
| 19 | return id; | ||
| 20 | } | ||
| 21 | |||
| 22 | /* WDTCR CP6 R7 Page 9 */ | ||
| 23 | static inline u32 read_wdtcr(void) | ||
| 24 | { | ||
| 25 | u32 val; | ||
| 26 | asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); | ||
| 27 | return val; | ||
| 28 | } | ||
| 29 | static inline void write_wdtcr(u32 val) | ||
| 30 | { | ||
| 31 | asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); | ||
| 32 | } | ||
| 33 | |||
| 34 | /* WDTSR CP6 R8 Page 9 */ | ||
| 35 | static inline u32 read_wdtsr(void) | ||
| 36 | { | ||
| 37 | u32 val; | ||
| 38 | asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); | ||
| 39 | return val; | ||
| 40 | } | ||
| 41 | static inline void write_wdtsr(u32 val) | ||
| 42 | { | ||
| 43 | asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); | ||
| 44 | } | ||
| 45 | |||
| 46 | /* RCSR - Reset Cause Status Register */ | ||
| 47 | static inline u32 read_rcsr(void) | ||
| 48 | { | ||
| 49 | u32 val; | ||
| 50 | asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val)); | ||
| 51 | return val; | ||
| 52 | } | ||
| 53 | |||
| 54 | extern unsigned long get_iop_tick_rate(void); | ||
| 55 | #endif | ||
| 56 | |||
| 57 | /* | ||
| 58 | * IOP13XX I/O and Mem space regions for PCI autoconfiguration | ||
| 59 | */ | ||
| 60 | #define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */ | ||
| 61 | #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE | ||
| 62 | |||
| 63 | /* PCI MAP | ||
| 64 | * bus range cpu phys cpu virt note | ||
| 65 | * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM | ||
| 66 | * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window | ||
| 67 | * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window | ||
| 68 | * | ||
| 69 | * IO MAP | ||
| 70 | * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window | ||
| 71 | * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window | ||
| 72 | */ | ||
| 73 | #define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL | ||
| 74 | #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL | ||
| 75 | #define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL | ||
| 76 | #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ | ||
| 77 | #define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL | ||
| 78 | #define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ | ||
| 79 | IOP13XX_PCIX_IO_WINDOW_SIZE - 1) | ||
| 80 | #define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ | ||
| 81 | IOP13XX_PCIX_IO_WINDOW_SIZE - 1) | ||
| 82 | #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ | ||
| 83 | (IOP13XX_PCIX_LOWER_IO_PA\ | ||
| 84 | - IOP13XX_PCIX_LOWER_IO_VA)) | ||
| 85 | |||
| 86 | #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL | ||
| 87 | #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL | ||
| 88 | #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) | ||
| 89 | #define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\ | ||
| 90 | IOP13XX_PCIX_LOWER_MEM_BA) | ||
| 91 | #define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\ | ||
| 92 | IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) | ||
| 93 | #define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\ | ||
| 94 | IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) | ||
| 95 | |||
| 96 | #define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL | ||
| 97 | #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE | ||
| 98 | #define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\ | ||
| 99 | IOP13XX_PCIX_MEM_WINDOW_SIZE - 1) | ||
| 100 | #define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\ | ||
| 101 | IOP13XX_PCIX_LOWER_MEM_BA) | ||
| 102 | |||
| 103 | /* PCI-E ranges */ | ||
| 104 | #define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL | ||
| 105 | #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL | ||
| 106 | #define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL | ||
| 107 | #define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */ | ||
| 108 | #define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL | ||
| 109 | #define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ | ||
| 110 | IOP13XX_PCIE_IO_WINDOW_SIZE - 1) | ||
| 111 | #define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ | ||
| 112 | IOP13XX_PCIE_IO_WINDOW_SIZE - 1) | ||
| 113 | #define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ | ||
| 114 | IOP13XX_PCIE_IO_WINDOW_SIZE - 1) | ||
| 115 | #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ | ||
| 116 | (IOP13XX_PCIE_LOWER_IO_PA\ | ||
| 117 | - IOP13XX_PCIE_LOWER_IO_VA)) | ||
| 118 | |||
| 119 | #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL | ||
| 120 | #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL | ||
| 121 | #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET) | ||
| 122 | #define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\ | ||
| 123 | IOP13XX_PCIE_LOWER_MEM_BA) | ||
| 124 | #define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\ | ||
| 125 | IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) | ||
| 126 | #define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\ | ||
| 127 | IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) | ||
| 128 | |||
| 129 | /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */ | ||
| 130 | #define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL | ||
| 131 | #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE | ||
| 132 | #define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\ | ||
| 133 | IOP13XX_PCIE_MEM_WINDOW_SIZE - 1) | ||
| 134 | #define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\ | ||
| 135 | IOP13XX_PCIE_LOWER_MEM_BA) | ||
| 136 | |||
| 137 | /* PBI Ranges */ | ||
| 138 | #define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL | ||
| 139 | #define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL | ||
| 140 | #define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL | ||
| 141 | #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE | ||
| 142 | #define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\ | ||
| 143 | IOP13XX_PBI_MEM_WINDOW_SIZE - 1) | ||
| 144 | |||
| 145 | /* | ||
| 146 | * IOP13XX chipset registers | ||
| 147 | */ | ||
| 148 | #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ | ||
| 149 | #define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */ | ||
| 150 | #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 | ||
| 151 | #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ | ||
| 152 | IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) | ||
| 153 | #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ | ||
| 154 | IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) | ||
| 155 | #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\ | ||
| 156 | (IOP13XX_PMMR_PHYS_MEM_BASE\ | ||
| 157 | - IOP13XX_PMMR_VIRT_MEM_BASE)) | ||
| 158 | #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ | ||
| 159 | (IOP13XX_PMMR_PHYS_MEM_BASE\ | ||
| 160 | - IOP13XX_PMMR_VIRT_MEM_BASE)) | ||
| 161 | #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) | ||
| 162 | #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) | ||
| 163 | #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) | ||
| 164 | #define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) | ||
| 165 | #define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) | ||
| 166 | #define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg)) | ||
| 167 | #define IOP13XX_PMMR_SIZE 0x00080000 | ||
| 168 | |||
| 169 | /*=================== Defines for Platform Devices =====================*/ | ||
| 170 | #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300) | ||
| 171 | #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340) | ||
| 172 | #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300) | ||
| 173 | #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340) | ||
| 174 | |||
| 175 | #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) | ||
| 176 | #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) | ||
| 177 | #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540) | ||
| 178 | #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500) | ||
| 179 | #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520) | ||
| 180 | #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540) | ||
| 181 | |||
| 182 | /* ATU selection flags */ | ||
| 183 | /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */ | ||
| 184 | #define IOP13XX_INIT_ATU_DEFAULT (0) | ||
| 185 | #define IOP13XX_INIT_ATU_ATUX (1 << 0) | ||
| 186 | #define IOP13XX_INIT_ATU_ATUE (1 << 1) | ||
| 187 | #define IOP13XX_INIT_ATU_NONE (1 << 2) | ||
| 188 | |||
| 189 | /* UART selection flags */ | ||
| 190 | /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */ | ||
| 191 | #define IOP13XX_INIT_UART_DEFAULT (0) | ||
| 192 | #define IOP13XX_INIT_UART_0 (1 << 0) | ||
| 193 | #define IOP13XX_INIT_UART_1 (1 << 1) | ||
| 194 | |||
| 195 | /* I2C selection flags */ | ||
| 196 | /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */ | ||
| 197 | #define IOP13XX_INIT_I2C_DEFAULT (0) | ||
| 198 | #define IOP13XX_INIT_I2C_0 (1 << 0) | ||
| 199 | #define IOP13XX_INIT_I2C_1 (1 << 1) | ||
| 200 | #define IOP13XX_INIT_I2C_2 (1 << 2) | ||
| 201 | |||
| 202 | /* ADMA selection flags */ | ||
| 203 | /* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */ | ||
| 204 | #define IOP13XX_INIT_ADMA_DEFAULT (0) | ||
| 205 | #define IOP13XX_INIT_ADMA_0 (1 << 0) | ||
| 206 | #define IOP13XX_INIT_ADMA_1 (1 << 1) | ||
| 207 | #define IOP13XX_INIT_ADMA_2 (1 << 2) | ||
| 208 | |||
| 209 | /* Platform devices */ | ||
| 210 | #define IQ81340_NUM_UART 2 | ||
| 211 | #define IQ81340_NUM_I2C 3 | ||
| 212 | #define IQ81340_NUM_PHYS_MAP_FLASH 1 | ||
| 213 | #define IQ81340_NUM_ADMA 3 | ||
| 214 | #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \ | ||
| 215 | IQ81340_NUM_I2C + \ | ||
| 216 | IQ81340_NUM_PHYS_MAP_FLASH + \ | ||
| 217 | IQ81340_NUM_ADMA) | ||
| 218 | |||
| 219 | /*========================== PMMR offsets for key registers ============*/ | ||
| 220 | #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000 | ||
| 221 | #define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000 | ||
| 222 | #define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000 | ||
| 223 | #define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000 | ||
| 224 | #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 | ||
| 225 | #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 | ||
| 226 | #define IOP13XX_PBI_PMMR_OFFSET 0x00001580 | ||
| 227 | #define IOP13XX_MU_PMMR_OFFSET 0x00004000 | ||
| 228 | #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 | ||
| 229 | #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) | ||
| 230 | |||
| 231 | #define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */ | ||
| 232 | #define IOP13XX_CONTROLLER_ONLY (1 << 14) | ||
| 233 | #define IOP13XX_INTERFACE_SEL_PCIX (1 << 15) | ||
| 234 | |||
| 235 | #define IOP13XX_PMON_PMMR_OFFSET 0x0001A000 | ||
| 236 | #define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\ | ||
| 237 | IOP13XX_PMON_PMMR_OFFSET) | ||
| 238 | #define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\ | ||
| 239 | IOP13XX_PMON_PMMR_OFFSET) | ||
| 240 | |||
| 241 | #define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0) | ||
| 242 | #define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4) | ||
| 243 | #define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8) | ||
| 244 | #define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC) | ||
| 245 | |||
| 246 | #define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30) | ||
| 247 | #define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34) | ||
| 248 | #define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38) | ||
| 249 | #define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C) | ||
| 250 | |||
| 251 | #define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70) | ||
| 252 | #define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74) | ||
| 253 | #define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78) | ||
| 254 | #define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C) | ||
| 255 | |||
| 256 | #define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040) | ||
| 257 | #define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044) | ||
| 258 | |||
| 259 | /*================================ATU===================================*/ | ||
| 260 | #define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\ | ||
| 261 | iop13xx_atux_pmmr_offset + (ofs)) | ||
| 262 | |||
| 263 | #define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\ | ||
| 264 | iop13xx_atux_pmmr_offset + 0x2) | ||
| 265 | |||
| 266 | #define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\ | ||
| 267 | iop13xx_atux_pmmr_offset + 0x4) | ||
| 268 | #define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\ | ||
| 269 | iop13xx_atux_pmmr_offset + 0x6) | ||
| 270 | |||
| 271 | #define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10) | ||
| 272 | #define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14) | ||
| 273 | #define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18) | ||
| 274 | #define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c) | ||
| 275 | #define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20) | ||
| 276 | #define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24) | ||
| 277 | #define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40) | ||
| 278 | #define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44) | ||
| 279 | #define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48) | ||
| 280 | #define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c) | ||
| 281 | #define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50) | ||
| 282 | #define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54) | ||
| 283 | #define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58) | ||
| 284 | #define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c) | ||
| 285 | #define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60) | ||
| 286 | #define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70) | ||
| 287 | #define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74) | ||
| 288 | #define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78) | ||
| 289 | #define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4) | ||
| 290 | #define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200) | ||
| 291 | #define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204) | ||
| 292 | #define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208) | ||
| 293 | #define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c) | ||
| 294 | #define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210) | ||
| 295 | |||
| 296 | #define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300) | ||
| 297 | #define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304) | ||
| 298 | #define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308) | ||
| 299 | #define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c) | ||
| 300 | #define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310) | ||
| 301 | #define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314) | ||
| 302 | #define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318) | ||
| 303 | #define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c) | ||
| 304 | #define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320) | ||
| 305 | #define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324) | ||
| 306 | #define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328) | ||
| 307 | #define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c) | ||
| 308 | #define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330) | ||
| 309 | #define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334) | ||
| 310 | |||
| 311 | #define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1) | ||
| 312 | #define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25) | ||
| 313 | #define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21) | ||
| 314 | #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15) | ||
| 315 | #define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14) | ||
| 316 | #define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16) | ||
| 317 | |||
| 318 | #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18) | ||
| 319 | #define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17) | ||
| 320 | #define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16) | ||
| 321 | #define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15) | ||
| 322 | #define IOP13XX_ATUX_STAT_ERR_COR (1 << 14) | ||
| 323 | #define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13) | ||
| 324 | #define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12) | ||
| 325 | #define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11) | ||
| 326 | #define IOP13XX_ATUX_STAT_TX_SERR (1 << 10) | ||
| 327 | #define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 ) | ||
| 328 | #define IOP13XX_ATUX_STAT_BIST (1 << 8 ) | ||
| 329 | #define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 ) | ||
| 330 | #define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 ) | ||
| 331 | #define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 ) | ||
| 332 | #define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 ) | ||
| 333 | #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 ) | ||
| 334 | #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 ) | ||
| 335 | |||
| 336 | #define IOP13XX_ATUX_PCIXSR_BUS_NUM (8) | ||
| 337 | #define IOP13XX_ATUX_PCIXSR_DEV_NUM (3) | ||
| 338 | #define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0) | ||
| 339 | |||
| 340 | #define IOP13XX_ATUX_IALR_DISABLE 0x00000001 | ||
| 341 | #define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000 | ||
| 342 | |||
| 343 | #define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\ | ||
| 344 | iop13xx_atue_pmmr_offset + (ofs)) | ||
| 345 | |||
| 346 | #define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\ | ||
| 347 | iop13xx_atue_pmmr_offset + 0x2) | ||
| 348 | #define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\ | ||
| 349 | iop13xx_atue_pmmr_offset + 0x4) | ||
| 350 | #define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\ | ||
| 351 | iop13xx_atue_pmmr_offset + 0x6) | ||
| 352 | |||
| 353 | #define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10) | ||
| 354 | #define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14) | ||
| 355 | #define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18) | ||
| 356 | #define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c) | ||
| 357 | #define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20) | ||
| 358 | #define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24) | ||
| 359 | #define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40) | ||
| 360 | #define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44) | ||
| 361 | #define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48) | ||
| 362 | #define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c) | ||
| 363 | #define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50) | ||
| 364 | #define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54) | ||
| 365 | #define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58) | ||
| 366 | #define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c) | ||
| 367 | #define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60) | ||
| 368 | #define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\ | ||
| 369 | iop13xx_atue_pmmr_offset + 0xe2) | ||
| 370 | #define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304) | ||
| 371 | #define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308) | ||
| 372 | #define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c) | ||
| 373 | #define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310) | ||
| 374 | #define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314) | ||
| 375 | #define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318) | ||
| 376 | #define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c) | ||
| 377 | #define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320) | ||
| 378 | #define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324) | ||
| 379 | |||
| 380 | #define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70) | ||
| 381 | #define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74) | ||
| 382 | #define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78) | ||
| 383 | #define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300) | ||
| 384 | #define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c) | ||
| 385 | #define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330) | ||
| 386 | |||
| 387 | #define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384) | ||
| 388 | #define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388) | ||
| 389 | |||
| 390 | #define IOP13XX_ATUE_ATUCR_IVM (1 << 6) | ||
| 391 | #define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1) | ||
| 392 | #define IOP13XX_ATUE_OCCAR_BUS_NUM (24) | ||
| 393 | #define IOP13XX_ATUE_OCCAR_DEV_NUM (19) | ||
| 394 | #define IOP13XX_ATUE_OCCAR_FUNC_NUM (16) | ||
| 395 | #define IOP13XX_ATUE_OCCAR_EXT_REG (8) | ||
| 396 | #define IOP13XX_ATUE_OCCAR_REG (2) | ||
| 397 | |||
| 398 | #define IOP13XX_ATUE_PCSR_BUS_NUM (24) | ||
| 399 | #define IOP13XX_ATUE_PCSR_DEV_NUM (19) | ||
| 400 | #define IOP13XX_ATUE_PCSR_FUNC_NUM (16) | ||
| 401 | #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15) | ||
| 402 | #define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14) | ||
| 403 | #define IOP13XX_ATUE_PCSR_END_POINT (1 << 13) | ||
| 404 | #define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12) | ||
| 405 | |||
| 406 | #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff) | ||
| 407 | #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f) | ||
| 408 | #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7) | ||
| 409 | |||
| 410 | #define IOP13XX_ATUE_PCSR_CORE_RESET (8) | ||
| 411 | #define IOP13XX_ATUE_PCSR_FUNC_NUM (16) | ||
| 412 | |||
| 413 | #define IOP13XX_ATUE_LSTS_TRAINING (1 << 11) | ||
| 414 | #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28) | ||
| 415 | #define IOP13XX_ATUE_STAT_PME (1 << 27) | ||
| 416 | #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26) | ||
| 417 | #define IOP13XX_ATUE_STAT_IVM (1 << 25) | ||
| 418 | #define IOP13XX_ATUE_STAT_BIST (1 << 24) | ||
| 419 | #define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18) | ||
| 420 | #define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17) | ||
| 421 | #define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16) | ||
| 422 | #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13) | ||
| 423 | #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12) | ||
| 424 | #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11) | ||
| 425 | #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10) | ||
| 426 | #define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 ) | ||
| 427 | #define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 ) | ||
| 428 | #define IOP13XX_ATUE_STAT_CRS (1 << 7 ) | ||
| 429 | #define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 ) | ||
| 430 | #define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 ) | ||
| 431 | #define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 ) | ||
| 432 | #define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 ) | ||
| 433 | #define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 ) | ||
| 434 | #define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 ) | ||
| 435 | #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 ) | ||
| 436 | |||
| 437 | #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31) | ||
| 438 | #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30) | ||
| 439 | #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29) | ||
| 440 | #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28) | ||
| 441 | #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20) | ||
| 442 | #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19) | ||
| 443 | #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18) | ||
| 444 | #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17) | ||
| 445 | #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16) | ||
| 446 | #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15) | ||
| 447 | #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14) | ||
| 448 | #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13) | ||
| 449 | #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12) | ||
| 450 | #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 ) | ||
| 451 | #define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 ) | ||
| 452 | |||
| 453 | #define IOP13XX_ATUE_IALR_DISABLE (0x00000001) | ||
| 454 | #define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000) | ||
| 455 | #define IOP13XX_ATU_OUMBAR_FUNC_NUM (28) | ||
| 456 | #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) | ||
| 457 | /*=======================================================================*/ | ||
| 458 | |||
| 459 | /*============================MESSAGING UNIT=============================*/ | ||
| 460 | #define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\ | ||
| 461 | (ofs)) | ||
| 462 | |||
| 463 | #define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) | ||
| 464 | #define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) | ||
| 465 | #define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) | ||
| 466 | #define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) | ||
| 467 | #define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) | ||
| 468 | #define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) | ||
| 469 | #define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) | ||
| 470 | #define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) | ||
| 471 | #define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) | ||
| 472 | #define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) | ||
| 473 | #define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) | ||
| 474 | #define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) | ||
| 475 | #define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) | ||
| 476 | #define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) | ||
| 477 | #define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) | ||
| 478 | #define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) | ||
| 479 | |||
| 480 | #define IOP13XX_MU_WINDOW_SIZE (8 * 1024) | ||
| 481 | #define IOP13XX_MU_BASE_PHYS (0xff000000) | ||
| 482 | #define IOP13XX_MU_BASE_PCI (0xff000000) | ||
| 483 | #define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) | ||
| 484 | #define IOP13XX_MU_MIMR_CORE_SELECT (15) | ||
| 485 | /*=======================================================================*/ | ||
| 486 | |||
| 487 | /*==============================ADMA UNITS===============================*/ | ||
| 488 | #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) | ||
| 489 | #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) | ||
| 490 | |||
| 491 | /*==============================XSI BRIDGE===============================*/ | ||
| 492 | #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c) | ||
| 493 | #define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790) | ||
| 494 | #define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794) | ||
| 495 | #define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ | ||
| 496 | IOP13XX_PMMR_VIRT_TO_PHYS(\ | ||
| 497 | IOP13XX_ATUE_OCCDR))\ | ||
| 498 | && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) | ||
| 499 | #define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \ | ||
| 500 | IOP13XX_PMMR_VIRT_TO_PHYS(\ | ||
| 501 | IOP13XX_ATUX_OCCDR))\ | ||
| 502 | && (__raw_readl(IOP13XX_XBG_BECSR) & 1)) | ||
| 503 | /*=======================================================================*/ | ||
| 504 | |||
| 505 | #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\ | ||
| 506 | (ofs)) | ||
| 507 | |||
| 508 | #define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0) | ||
| 509 | #define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4) | ||
| 510 | #define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8) | ||
| 511 | #define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc) | ||
| 512 | #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) | ||
| 513 | #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) | ||
| 514 | |||
| 515 | #define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) | ||
| 516 | |||
| 517 | /* Watchdog timer definitions */ | ||
| 518 | #define IOP_WDTCR_EN_ARM 0x1e1e1e1e | ||
| 519 | #define IOP_WDTCR_EN 0xe1e1e1e1 | ||
| 520 | #define IOP_WDTCR_DIS_ARM 0x1f1f1f1f | ||
| 521 | #define IOP_WDTCR_DIS 0xf1f1f1f1 | ||
| 522 | #define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */ | ||
| 523 | #define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */ | ||
| 524 | #define IOP13XX_WDTCR_IB_RESET (1 << 0) | ||
| 525 | |||
| 526 | #endif /* _IOP13XX_HW_H_ */ | ||
diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h deleted file mode 100644 index ba2cf931e9ce..000000000000 --- a/include/asm-arm/arch-iop13xx/iq81340.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | #ifndef _IQ81340_H_ | ||
| 2 | #define _IQ81340_H_ | ||
| 3 | |||
| 4 | #define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA | ||
| 5 | #define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000) | ||
| 6 | |||
| 7 | #define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */ | ||
| 8 | |||
| 9 | #define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a)) | ||
| 10 | |||
| 11 | #define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0) | ||
| 12 | #define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000) | ||
| 13 | #define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000) | ||
| 14 | #define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000) | ||
| 15 | #define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000) | ||
| 16 | #define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000) | ||
| 17 | #define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000) | ||
| 18 | #define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000) | ||
| 19 | #define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000) | ||
| 20 | #define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000) | ||
| 21 | #define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000) | ||
| 22 | #define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */ | ||
| 23 | |||
| 24 | #define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH) | ||
| 25 | #define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1) | ||
| 26 | |||
| 27 | |||
| 28 | #endif /* _IQ81340_H_ */ | ||
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h deleted file mode 100644 index 054e7acb5bfa..000000000000 --- a/include/asm-arm/arch-iop13xx/irqs.h +++ /dev/null | |||
| @@ -1,196 +0,0 @@ | |||
| 1 | #ifndef _IOP13XX_IRQS_H_ | ||
| 2 | #define _IOP13XX_IRQS_H_ | ||
| 3 | |||
| 4 | #ifndef __ASSEMBLER__ | ||
| 5 | #include <linux/types.h> | ||
| 6 | |||
| 7 | /* INTPND0 CP6 R0 Page 3 | ||
| 8 | */ | ||
| 9 | static inline u32 read_intpnd_0(void) | ||
| 10 | { | ||
| 11 | u32 val; | ||
| 12 | asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val)); | ||
| 13 | return val; | ||
| 14 | } | ||
| 15 | |||
| 16 | /* INTPND1 CP6 R1 Page 3 | ||
| 17 | */ | ||
| 18 | static inline u32 read_intpnd_1(void) | ||
| 19 | { | ||
| 20 | u32 val; | ||
| 21 | asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val)); | ||
| 22 | return val; | ||
| 23 | } | ||
| 24 | |||
| 25 | /* INTPND2 CP6 R2 Page 3 | ||
| 26 | */ | ||
| 27 | static inline u32 read_intpnd_2(void) | ||
| 28 | { | ||
| 29 | u32 val; | ||
| 30 | asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val)); | ||
| 31 | return val; | ||
| 32 | } | ||
| 33 | |||
| 34 | /* INTPND3 CP6 R3 Page 3 | ||
| 35 | */ | ||
| 36 | static inline u32 read_intpnd_3(void) | ||
| 37 | { | ||
| 38 | u32 val; | ||
| 39 | asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); | ||
| 40 | return val; | ||
| 41 | } | ||
| 42 | #endif | ||
| 43 | |||
| 44 | #define INTBASE 0 | ||
| 45 | #define INTSIZE_4 1 | ||
| 46 | |||
| 47 | /* | ||
| 48 | * iop34x chipset interrupts | ||
| 49 | */ | ||
| 50 | #define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x)) | ||
| 51 | |||
| 52 | /* | ||
| 53 | * On IRQ or FIQ register | ||
| 54 | */ | ||
| 55 | #define IRQ_IOP13XX_ADMA0_EOT (0) | ||
| 56 | #define IRQ_IOP13XX_ADMA0_EOC (1) | ||
| 57 | #define IRQ_IOP13XX_ADMA1_EOT (2) | ||
| 58 | #define IRQ_IOP13XX_ADMA1_EOC (3) | ||
| 59 | #define IRQ_IOP13XX_ADMA2_EOT (4) | ||
| 60 | #define IRQ_IOP13XX_ADMA2_EOC (5) | ||
| 61 | #define IRQ_IOP134_WATCHDOG (6) | ||
| 62 | #define IRQ_IOP13XX_RSVD_7 (7) | ||
| 63 | #define IRQ_IOP13XX_TIMER0 (8) | ||
| 64 | #define IRQ_IOP13XX_TIMER1 (9) | ||
| 65 | #define IRQ_IOP13XX_I2C_0 (10) | ||
| 66 | #define IRQ_IOP13XX_I2C_1 (11) | ||
| 67 | #define IRQ_IOP13XX_MSG (12) | ||
| 68 | #define IRQ_IOP13XX_MSGIBQ (13) | ||
| 69 | #define IRQ_IOP13XX_ATU_IM (14) | ||
| 70 | #define IRQ_IOP13XX_ATU_BIST (15) | ||
| 71 | #define IRQ_IOP13XX_PPMU (16) | ||
| 72 | #define IRQ_IOP13XX_COREPMU (17) | ||
| 73 | #define IRQ_IOP13XX_CORECACHE (18) | ||
| 74 | #define IRQ_IOP13XX_RSVD_19 (19) | ||
| 75 | #define IRQ_IOP13XX_RSVD_20 (20) | ||
| 76 | #define IRQ_IOP13XX_RSVD_21 (21) | ||
| 77 | #define IRQ_IOP13XX_RSVD_22 (22) | ||
| 78 | #define IRQ_IOP13XX_RSVD_23 (23) | ||
| 79 | #define IRQ_IOP13XX_XINT0 (24) | ||
| 80 | #define IRQ_IOP13XX_XINT1 (25) | ||
| 81 | #define IRQ_IOP13XX_XINT2 (26) | ||
| 82 | #define IRQ_IOP13XX_XINT3 (27) | ||
| 83 | #define IRQ_IOP13XX_XINT4 (28) | ||
| 84 | #define IRQ_IOP13XX_XINT5 (29) | ||
| 85 | #define IRQ_IOP13XX_XINT6 (30) | ||
| 86 | #define IRQ_IOP13XX_XINT7 (31) | ||
| 87 | /* IINTSRC1 bit */ | ||
| 88 | #define IRQ_IOP13XX_XINT8 (32) /* 0 */ | ||
| 89 | #define IRQ_IOP13XX_XINT9 (33) /* 1 */ | ||
| 90 | #define IRQ_IOP13XX_XINT10 (34) /* 2 */ | ||
| 91 | #define IRQ_IOP13XX_XINT11 (35) /* 3 */ | ||
| 92 | #define IRQ_IOP13XX_XINT12 (36) /* 4 */ | ||
| 93 | #define IRQ_IOP13XX_XINT13 (37) /* 5 */ | ||
| 94 | #define IRQ_IOP13XX_XINT14 (38) /* 6 */ | ||
| 95 | #define IRQ_IOP13XX_XINT15 (39) /* 7 */ | ||
| 96 | #define IRQ_IOP13XX_RSVD_40 (40) /* 8 */ | ||
| 97 | #define IRQ_IOP13XX_RSVD_41 (41) /* 9 */ | ||
| 98 | #define IRQ_IOP13XX_RSVD_42 (42) /* 10 */ | ||
| 99 | #define IRQ_IOP13XX_RSVD_43 (43) /* 11 */ | ||
| 100 | #define IRQ_IOP13XX_RSVD_44 (44) /* 12 */ | ||
| 101 | #define IRQ_IOP13XX_RSVD_45 (45) /* 13 */ | ||
| 102 | #define IRQ_IOP13XX_RSVD_46 (46) /* 14 */ | ||
| 103 | #define IRQ_IOP13XX_RSVD_47 (47) /* 15 */ | ||
| 104 | #define IRQ_IOP13XX_RSVD_48 (48) /* 16 */ | ||
| 105 | #define IRQ_IOP13XX_RSVD_49 (49) /* 17 */ | ||
| 106 | #define IRQ_IOP13XX_RSVD_50 (50) /* 18 */ | ||
| 107 | #define IRQ_IOP13XX_UART0 (51) /* 19 */ | ||
| 108 | #define IRQ_IOP13XX_UART1 (52) /* 20 */ | ||
| 109 | #define IRQ_IOP13XX_PBIE (53) /* 21 */ | ||
| 110 | #define IRQ_IOP13XX_ATU_CRW (54) /* 22 */ | ||
| 111 | #define IRQ_IOP13XX_ATU_ERR (55) /* 23 */ | ||
| 112 | #define IRQ_IOP13XX_MCU_ERR (56) /* 24 */ | ||
| 113 | #define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */ | ||
| 114 | #define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */ | ||
| 115 | #define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */ | ||
| 116 | #define IRQ_IOP13XX_RSVD_60 (60) /* 28 */ | ||
| 117 | #define IRQ_IOP13XX_RSVD_61 (61) /* 29 */ | ||
| 118 | #define IRQ_IOP13XX_MSG_ERR (62) /* 30 */ | ||
| 119 | #define IRQ_IOP13XX_RSVD_63 (63) /* 31 */ | ||
| 120 | /* IINTSRC2 bit */ | ||
| 121 | #define IRQ_IOP13XX_INTERPROC (64) /* 0 */ | ||
| 122 | #define IRQ_IOP13XX_RSVD_65 (65) /* 1 */ | ||
| 123 | #define IRQ_IOP13XX_RSVD_66 (66) /* 2 */ | ||
| 124 | #define IRQ_IOP13XX_RSVD_67 (67) /* 3 */ | ||
| 125 | #define IRQ_IOP13XX_RSVD_68 (68) /* 4 */ | ||
| 126 | #define IRQ_IOP13XX_RSVD_69 (69) /* 5 */ | ||
| 127 | #define IRQ_IOP13XX_RSVD_70 (70) /* 6 */ | ||
| 128 | #define IRQ_IOP13XX_RSVD_71 (71) /* 7 */ | ||
| 129 | #define IRQ_IOP13XX_RSVD_72 (72) /* 8 */ | ||
| 130 | #define IRQ_IOP13XX_RSVD_73 (73) /* 9 */ | ||
| 131 | #define IRQ_IOP13XX_RSVD_74 (74) /* 10 */ | ||
| 132 | #define IRQ_IOP13XX_RSVD_75 (75) /* 11 */ | ||
| 133 | #define IRQ_IOP13XX_RSVD_76 (76) /* 12 */ | ||
| 134 | #define IRQ_IOP13XX_RSVD_77 (77) /* 13 */ | ||
| 135 | #define IRQ_IOP13XX_RSVD_78 (78) /* 14 */ | ||
| 136 | #define IRQ_IOP13XX_RSVD_79 (79) /* 15 */ | ||
| 137 | #define IRQ_IOP13XX_RSVD_80 (80) /* 16 */ | ||
| 138 | #define IRQ_IOP13XX_RSVD_81 (81) /* 17 */ | ||
| 139 | #define IRQ_IOP13XX_RSVD_82 (82) /* 18 */ | ||
| 140 | #define IRQ_IOP13XX_RSVD_83 (83) /* 19 */ | ||
| 141 | #define IRQ_IOP13XX_RSVD_84 (84) /* 20 */ | ||
| 142 | #define IRQ_IOP13XX_RSVD_85 (85) /* 21 */ | ||
| 143 | #define IRQ_IOP13XX_RSVD_86 (86) /* 22 */ | ||
| 144 | #define IRQ_IOP13XX_RSVD_87 (87) /* 23 */ | ||
| 145 | #define IRQ_IOP13XX_RSVD_88 (88) /* 24 */ | ||
| 146 | #define IRQ_IOP13XX_RSVD_89 (89) /* 25 */ | ||
| 147 | #define IRQ_IOP13XX_RSVD_90 (90) /* 26 */ | ||
| 148 | #define IRQ_IOP13XX_RSVD_91 (91) /* 27 */ | ||
| 149 | #define IRQ_IOP13XX_RSVD_92 (92) /* 28 */ | ||
| 150 | #define IRQ_IOP13XX_RSVD_93 (93) /* 29 */ | ||
| 151 | #define IRQ_IOP13XX_SIB_ERR (94) /* 30 */ | ||
| 152 | #define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */ | ||
| 153 | /* IINTSRC3 bit */ | ||
| 154 | #define IRQ_IOP13XX_I2C_2 (96) /* 0 */ | ||
| 155 | #define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */ | ||
| 156 | #define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */ | ||
| 157 | #define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */ | ||
| 158 | #define IRQ_IOP13XX_IMU (100) /* 4 */ | ||
| 159 | #define IRQ_IOP13XX_RSVD_101 (101) /* 5 */ | ||
| 160 | #define IRQ_IOP13XX_RSVD_102 (102) /* 6 */ | ||
| 161 | #define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */ | ||
| 162 | #define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */ | ||
| 163 | #define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */ | ||
| 164 | #define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */ | ||
| 165 | #define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */ | ||
| 166 | #define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */ | ||
| 167 | #define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */ | ||
| 168 | #define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ | ||
| 169 | #define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ | ||
| 170 | #define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ | ||
| 171 | #define IRQ_IOP13XX_INBD_MSI (113) /* 17 */ | ||
| 172 | #define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ | ||
| 173 | #define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ | ||
| 174 | #define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ | ||
| 175 | #define IRQ_IOP13XX_RSVD_117 (117) /* 21 */ | ||
| 176 | #define IRQ_IOP13XX_RSVD_118 (118) /* 22 */ | ||
| 177 | #define IRQ_IOP13XX_RSVD_119 (119) /* 23 */ | ||
| 178 | #define IRQ_IOP13XX_RSVD_120 (120) /* 24 */ | ||
| 179 | #define IRQ_IOP13XX_RSVD_121 (121) /* 25 */ | ||
| 180 | #define IRQ_IOP13XX_RSVD_122 (122) /* 26 */ | ||
| 181 | #define IRQ_IOP13XX_RSVD_123 (123) /* 27 */ | ||
| 182 | #define IRQ_IOP13XX_RSVD_124 (124) /* 28 */ | ||
| 183 | #define IRQ_IOP13XX_RSVD_125 (125) /* 29 */ | ||
| 184 | #define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ | ||
| 185 | #define IRQ_IOP13XX_HPI (127) /* 31 */ | ||
| 186 | |||
| 187 | #ifdef CONFIG_PCI_MSI | ||
| 188 | #define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1) | ||
| 189 | #define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128) | ||
| 190 | #else | ||
| 191 | #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) | ||
| 192 | #endif | ||
| 193 | |||
| 194 | #define NR_IRQS NR_IOP13XX_IRQS | ||
| 195 | |||
| 196 | #endif /* _IOP13XX_IRQ_H_ */ | ||
diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h deleted file mode 100644 index 031a0fa78eff..000000000000 --- a/include/asm-arm/arch-iop13xx/memory.h +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 2 | #define __ASM_ARCH_MEMORY_H | ||
| 3 | |||
| 4 | #include <asm/arch/hardware.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * Physical DRAM offset. | ||
| 8 | */ | ||
| 9 | #define PHYS_OFFSET UL(0x00000000) | ||
| 10 | #define TASK_SIZE UL(0x3f000000) | ||
| 11 | #define PAGE_OFFSET UL(0x40000000) | ||
| 12 | #define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3) | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | |||
| 16 | #if defined(CONFIG_ARCH_IOP13XX) | ||
| 17 | #define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE) | ||
| 18 | #define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE) | ||
| 19 | #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) | ||
| 20 | #define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Virtual view <-> PCI DMA view memory address translations | ||
| 24 | * virt_to_bus: Used to translate the virtual address to an | ||
| 25 | * address suitable to be passed to set_dma_addr | ||
| 26 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 27 | * to an address that the kernel can use. | ||
| 28 | */ | ||
| 29 | |||
| 30 | /* RAM has 1:1 mapping on the PCIe/x Busses */ | ||
| 31 | #define __virt_to_bus(x) (__virt_to_phys(x)) | ||
| 32 | #define __bus_to_virt(x) (__phys_to_virt(x)) | ||
| 33 | |||
| 34 | #define virt_to_lbus(x) \ | ||
| 35 | (( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \ | ||
| 36 | ((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \ | ||
| 37 | ((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \ | ||
| 38 | ((x) - PAGE_OFFSET + PHYS_OFFSET)) | ||
| 39 | |||
| 40 | #define lbus_to_virt(x) \ | ||
| 41 | (( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \ | ||
| 42 | ((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \ | ||
| 43 | ((x) - PHYS_OFFSET + PAGE_OFFSET)) | ||
| 44 | |||
| 45 | /* Device is an lbus device if it is on the platform bus of the IOP13XX */ | ||
| 46 | #define is_lbus_device(dev) (dev &&\ | ||
| 47 | (strncmp(dev->bus->name, "platform", 8) == 0)) | ||
| 48 | |||
| 49 | #define __arch_page_to_dma(dev, page) \ | ||
| 50 | ({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \ | ||
| 51 | (dma_addr_t)__virt_to_bus(page_address(page));}) | ||
| 52 | |||
| 53 | #define __arch_dma_to_virt(dev, addr) \ | ||
| 54 | ({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);}) | ||
| 55 | |||
| 56 | #define __arch_virt_to_dma(dev, addr) \ | ||
| 57 | ({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);}) | ||
| 58 | |||
| 59 | #endif /* CONFIG_ARCH_IOP13XX */ | ||
| 60 | #endif /* !ASSEMBLY */ | ||
| 61 | |||
| 62 | #define PFN_TO_NID(addr) (0) | ||
| 63 | |||
| 64 | #endif | ||
diff --git a/include/asm-arm/arch-iop13xx/msi.h b/include/asm-arm/arch-iop13xx/msi.h deleted file mode 100644 index b80c5ae17e99..000000000000 --- a/include/asm-arm/arch-iop13xx/msi.h +++ /dev/null | |||
| @@ -1,11 +0,0 @@ | |||
| 1 | #ifndef _IOP13XX_MSI_H_ | ||
| 2 | #define _IOP13XX_MSI_H_ | ||
| 3 | #ifdef CONFIG_PCI_MSI | ||
| 4 | void iop13xx_msi_init(void); | ||
| 5 | #else | ||
| 6 | static inline void iop13xx_msi_init(void) | ||
| 7 | { | ||
| 8 | return; | ||
| 9 | } | ||
| 10 | #endif | ||
| 11 | #endif | ||
diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h deleted file mode 100644 index 4041f30d4cd3..000000000000 --- a/include/asm-arm/arch-iop13xx/pci.h +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | #ifndef _IOP13XX_PCI_H_ | ||
| 2 | #define _IOP13XX_PCI_H_ | ||
| 3 | #include <asm/arch/irqs.h> | ||
| 4 | #include <asm/io.h> | ||
| 5 | |||
| 6 | struct pci_sys_data; | ||
| 7 | struct hw_pci; | ||
| 8 | int iop13xx_pci_setup(int nr, struct pci_sys_data *sys); | ||
| 9 | struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *); | ||
| 10 | void iop13xx_atu_select(struct hw_pci *plat_pci); | ||
| 11 | void iop13xx_pci_init(void); | ||
| 12 | void iop13xx_map_pci_memory(void); | ||
| 13 | |||
| 14 | #define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \ | ||
| 15 | PCI_STATUS_SIG_TARGET_ABORT | \ | ||
| 16 | PCI_STATUS_REC_TARGET_ABORT | \ | ||
| 17 | PCI_STATUS_REC_TARGET_ABORT | \ | ||
| 18 | PCI_STATUS_REC_MASTER_ABORT | \ | ||
| 19 | PCI_STATUS_SIG_SYSTEM_ERROR | \ | ||
| 20 | PCI_STATUS_DETECTED_PARITY) | ||
| 21 | |||
| 22 | #define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \ | ||
| 23 | IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \ | ||
| 24 | IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \ | ||
| 25 | IOP13XX_ATUE_STAT_ERR_COR | \ | ||
| 26 | IOP13XX_ATUE_STAT_ERR_UNCOR | \ | ||
| 27 | IOP13XX_ATUE_STAT_CRS | \ | ||
| 28 | IOP13XX_ATUE_STAT_DET_PAR_ERR | \ | ||
| 29 | IOP13XX_ATUE_STAT_EXT_REC_MABORT | \ | ||
| 30 | IOP13XX_ATUE_STAT_SIG_TABORT | \ | ||
| 31 | IOP13XX_ATUE_STAT_EXT_REC_TABORT | \ | ||
| 32 | IOP13XX_ATUE_STAT_MASTER_DATA_PAR) | ||
| 33 | |||
| 34 | #define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \ | ||
| 35 | IOP13XX_ATUX_STAT_REC_SCEM | \ | ||
| 36 | IOP13XX_ATUX_STAT_TX_SERR | \ | ||
| 37 | IOP13XX_ATUX_STAT_DET_PAR_ERR | \ | ||
| 38 | IOP13XX_ATUX_STAT_INT_REC_MABORT | \ | ||
| 39 | IOP13XX_ATUX_STAT_REC_SERR | \ | ||
| 40 | IOP13XX_ATUX_STAT_EXT_REC_MABORT | \ | ||
| 41 | IOP13XX_ATUX_STAT_EXT_REC_TABORT | \ | ||
| 42 | IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \ | ||
| 43 | IOP13XX_ATUX_STAT_MASTER_DATA_PAR) | ||
| 44 | |||
| 45 | /* PCI interrupts | ||
| 46 | */ | ||
| 47 | #define ATUX_INTA IRQ_IOP13XX_XINT0 | ||
| 48 | #define ATUX_INTB IRQ_IOP13XX_XINT1 | ||
| 49 | #define ATUX_INTC IRQ_IOP13XX_XINT2 | ||
| 50 | #define ATUX_INTD IRQ_IOP13XX_XINT3 | ||
| 51 | |||
| 52 | #define ATUE_INTA IRQ_IOP13XX_ATUE_IMA | ||
| 53 | #define ATUE_INTB IRQ_IOP13XX_ATUE_IMB | ||
| 54 | #define ATUE_INTC IRQ_IOP13XX_ATUE_IMC | ||
| 55 | #define ATUE_INTD IRQ_IOP13XX_ATUE_IMD | ||
| 56 | |||
| 57 | #endif /* _IOP13XX_PCI_H_ */ | ||
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h deleted file mode 100644 index 8575af8db78c..000000000000 --- a/include/asm-arm/arch-iop13xx/system.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-iop13xx/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 Intel Corp. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/iop13xx.h> | ||
| 11 | static inline void arch_idle(void) | ||
| 12 | { | ||
| 13 | cpu_do_idle(); | ||
| 14 | } | ||
| 15 | |||
| 16 | static inline void arch_reset(char mode) | ||
| 17 | { | ||
| 18 | /* | ||
| 19 | * Reset the internal bus (warning both cores are reset) | ||
| 20 | */ | ||
| 21 | write_wdtcr(IOP_WDTCR_EN_ARM); | ||
| 22 | write_wdtcr(IOP_WDTCR_EN); | ||
| 23 | write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); | ||
| 24 | write_wdtcr(0x1000); | ||
| 25 | |||
| 26 | for(;;); | ||
| 27 | } | ||
diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h deleted file mode 100644 index 49213d9d7cad..000000000000 --- a/include/asm-arm/arch-iop13xx/time.h +++ /dev/null | |||
| @@ -1,107 +0,0 @@ | |||
| 1 | #ifndef _IOP13XX_TIME_H_ | ||
| 2 | #define _IOP13XX_TIME_H_ | ||
| 3 | #define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0 | ||
| 4 | |||
| 5 | #define IOP_TMR_EN 0x02 | ||
| 6 | #define IOP_TMR_RELOAD 0x04 | ||
| 7 | #define IOP_TMR_PRIVILEGED 0x08 | ||
| 8 | #define IOP_TMR_RATIO_1_1 0x00 | ||
| 9 | |||
| 10 | #define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19) | ||
| 11 | #define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19) | ||
| 12 | #define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19) | ||
| 13 | #define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19) | ||
| 14 | #define IOP13XX_CORE_FREQ_MASK (7 << 16) | ||
| 15 | #define IOP13XX_CORE_FREQ_600 (0 << 16) | ||
| 16 | #define IOP13XX_CORE_FREQ_667 (1 << 16) | ||
| 17 | #define IOP13XX_CORE_FREQ_800 (2 << 16) | ||
| 18 | #define IOP13XX_CORE_FREQ_933 (3 << 16) | ||
| 19 | #define IOP13XX_CORE_FREQ_1000 (4 << 16) | ||
| 20 | #define IOP13XX_CORE_FREQ_1200 (5 << 16) | ||
| 21 | |||
| 22 | void iop_init_time(unsigned long tickrate); | ||
| 23 | unsigned long iop_gettimeoffset(void); | ||
| 24 | |||
| 25 | static inline unsigned long iop13xx_core_freq(void) | ||
| 26 | { | ||
| 27 | unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ); | ||
| 28 | freq &= IOP13XX_CORE_FREQ_MASK; | ||
| 29 | switch (freq) { | ||
| 30 | case IOP13XX_CORE_FREQ_600: | ||
| 31 | return 600000000; | ||
| 32 | case IOP13XX_CORE_FREQ_667: | ||
| 33 | return 667000000; | ||
| 34 | case IOP13XX_CORE_FREQ_800: | ||
| 35 | return 800000000; | ||
| 36 | case IOP13XX_CORE_FREQ_933: | ||
| 37 | return 933000000; | ||
| 38 | case IOP13XX_CORE_FREQ_1000: | ||
| 39 | return 1000000000; | ||
| 40 | case IOP13XX_CORE_FREQ_1200: | ||
| 41 | return 1200000000; | ||
| 42 | default: | ||
| 43 | printk("%s: warning unknown frequency, defaulting to 800Mhz\n", | ||
| 44 | __FUNCTION__); | ||
| 45 | } | ||
| 46 | |||
| 47 | return 800000000; | ||
| 48 | } | ||
| 49 | |||
| 50 | static inline unsigned long iop13xx_xsi_bus_ratio(void) | ||
| 51 | { | ||
| 52 | unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ); | ||
| 53 | ratio &= IOP13XX_XSI_FREQ_RATIO_MASK; | ||
| 54 | switch (ratio) { | ||
| 55 | case IOP13XX_XSI_FREQ_RATIO_2: | ||
| 56 | return 2; | ||
| 57 | case IOP13XX_XSI_FREQ_RATIO_3: | ||
| 58 | return 3; | ||
| 59 | case IOP13XX_XSI_FREQ_RATIO_4: | ||
| 60 | return 4; | ||
| 61 | default: | ||
| 62 | printk("%s: warning unknown ratio, defaulting to 2\n", | ||
| 63 | __FUNCTION__); | ||
| 64 | } | ||
| 65 | |||
| 66 | return 2; | ||
| 67 | } | ||
| 68 | |||
| 69 | static inline void write_tmr0(u32 val) | ||
| 70 | { | ||
| 71 | asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); | ||
| 72 | } | ||
| 73 | |||
| 74 | static inline void write_tmr1(u32 val) | ||
| 75 | { | ||
| 76 | asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val)); | ||
| 77 | } | ||
| 78 | |||
| 79 | static inline u32 read_tcr0(void) | ||
| 80 | { | ||
| 81 | u32 val; | ||
| 82 | asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val)); | ||
| 83 | return val; | ||
| 84 | } | ||
| 85 | |||
| 86 | static inline u32 read_tcr1(void) | ||
| 87 | { | ||
| 88 | u32 val; | ||
| 89 | asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val)); | ||
| 90 | return val; | ||
| 91 | } | ||
| 92 | |||
| 93 | static inline void write_trr0(u32 val) | ||
| 94 | { | ||
| 95 | asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); | ||
| 96 | } | ||
| 97 | |||
| 98 | static inline void write_trr1(u32 val) | ||
| 99 | { | ||
| 100 | asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val)); | ||
| 101 | } | ||
| 102 | |||
| 103 | static inline void write_tisr(u32 val) | ||
| 104 | { | ||
| 105 | asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val)); | ||
| 106 | } | ||
| 107 | #endif | ||
diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h deleted file mode 100644 index 47564ecb3872..000000000000 --- a/include/asm-arm/arch-iop13xx/timex.h +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | #include <asm/arch/hardware.h> | ||
| 2 | |||
| 3 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h deleted file mode 100644 index 5d4418decb86..000000000000 --- a/include/asm-arm/arch-iop13xx/uncompress.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | #include <asm/types.h> | ||
| 2 | #include <linux/serial_reg.h> | ||
| 3 | #include <asm/arch/hardware.h> | ||
| 4 | |||
| 5 | #define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS) | ||
| 6 | #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) | ||
| 7 | |||
| 8 | static inline void putc(char c) | ||
| 9 | { | ||
| 10 | while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE) | ||
| 11 | barrier(); | ||
| 12 | UART_BASE[UART_TX] = c; | ||
| 13 | } | ||
| 14 | |||
| 15 | static inline void flush(void) | ||
| 16 | { | ||
| 17 | } | ||
| 18 | |||
| 19 | /* | ||
| 20 | * nothing to do | ||
| 21 | */ | ||
| 22 | #define arch_decomp_setup() | ||
| 23 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h deleted file mode 100644 index c53456740345..000000000000 --- a/include/asm-arm/arch-iop13xx/vmalloc.h +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | #ifndef _VMALLOC_H_ | ||
| 2 | #define _VMALLOC_H_ | ||
| 3 | #define VMALLOC_END 0xfa000000UL | ||
| 4 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/adma.h b/include/asm-arm/arch-iop32x/adma.h deleted file mode 100644 index 5ed92037dd10..000000000000 --- a/include/asm-arm/arch-iop32x/adma.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | #ifndef IOP32X_ADMA_H | ||
| 2 | #define IOP32X_ADMA_H | ||
| 3 | #include <asm/hardware/iop3xx-adma.h> | ||
| 4 | #endif | ||
| 5 | |||
diff --git a/include/asm-arm/arch-iop32x/debug-macro.S b/include/asm-arm/arch-iop32x/debug-macro.S deleted file mode 100644 index 9022b6849e23..000000000000 --- a/include/asm-arm/arch-iop32x/debug-macro.S +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/debug-macro.S | ||
| 3 | * | ||
| 4 | * Debugging macro include header | ||
| 5 | * | ||
| 6 | * Copyright (C) 1994-1999 Russell King | ||
| 7 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart, rx | ||
| 15 | mov \rx, #0xfe000000 @ physical as well as virtual | ||
| 16 | orr \rx, \rx, #0x00800000 @ location of the UART | ||
| 17 | .endm | ||
| 18 | |||
| 19 | #define UART_SHIFT 0 | ||
| 20 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-iop32x/dma.h b/include/asm-arm/arch-iop32x/dma.h deleted file mode 100644 index e977a9ef3160..000000000000 --- a/include/asm-arm/arch-iop32x/dma.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 Intel Corp. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S deleted file mode 100644 index 207db99dfbd2..000000000000 --- a/include/asm-arm/arch-iop32x/entry-macro.S +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for IOP32x-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/iop32x.h> | ||
| 11 | |||
| 12 | .macro disable_fiq | ||
| 13 | .endm | ||
| 14 | |||
| 15 | .macro get_irqnr_preamble, base, tmp | ||
| 16 | mrc p15, 0, \tmp, c15, c1, 0 | ||
| 17 | orr \tmp, \tmp, #(1 << 6) | ||
| 18 | mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access | ||
| 19 | mrc p15, 0, \tmp, c15, c1, 0 | ||
| 20 | mov \tmp, \tmp | ||
| 21 | sub pc, pc, #4 @ cp_wait | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 25 | mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC | ||
| 26 | cmp \irqstat, #0 | ||
| 27 | clzne \irqnr, \irqstat | ||
| 28 | rsbne \irqnr, \irqnr, #31 | ||
| 29 | .endm | ||
| 30 | |||
| 31 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 32 | mrc p15, 0, \tmp1, c15, c1, 0 | ||
| 33 | ands \tmp2, \tmp1, #(1 << 6) | ||
| 34 | bicne \tmp1, \tmp1, #(1 << 6) | ||
| 35 | mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access | ||
| 36 | .endm | ||
diff --git a/include/asm-arm/arch-iop32x/glantank.h b/include/asm-arm/arch-iop32x/glantank.h deleted file mode 100644 index bf0665acc1c1..000000000000 --- a/include/asm-arm/arch-iop32x/glantank.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/glantank.h | ||
| 3 | * | ||
| 4 | * IO-Data GLAN Tank board registers | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __GLANTANK_H | ||
| 8 | #define __GLANTANK_H | ||
| 9 | |||
| 10 | #define GLANTANK_UART 0xfe800000 /* UART */ | ||
| 11 | |||
| 12 | |||
| 13 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/gpio.h b/include/asm-arm/arch-iop32x/gpio.h deleted file mode 100644 index 708f4ec9db1d..000000000000 --- a/include/asm-arm/arch-iop32x/gpio.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_IOP32X_GPIO_H | ||
| 2 | #define __ASM_ARCH_IOP32X_GPIO_H | ||
| 3 | |||
| 4 | #include <asm/hardware/iop3xx-gpio.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/hardware.h b/include/asm-arm/arch-iop32x/hardware.h deleted file mode 100644 index 6556ed5eee31..000000000000 --- a/include/asm-arm/arch-iop32x/hardware.h +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/hardware.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __HARDWARE_H | ||
| 6 | #define __HARDWARE_H | ||
| 7 | |||
| 8 | #include <asm/types.h> | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Note about PCI IO space mappings | ||
| 12 | * | ||
| 13 | * To make IO space accesses efficient, we store virtual addresses in | ||
| 14 | * the IO resources. | ||
| 15 | * | ||
| 16 | * The PCI IO space is located at virtual 0xfe000000 from physical | ||
| 17 | * 0x90000000. The PCI BARs must be programmed with physical addresses, | ||
| 18 | * but when we read them, we convert them to virtual addresses. See | ||
| 19 | * arch/arm/plat-iop/pci.c. | ||
| 20 | */ | ||
| 21 | #define pcibios_assign_all_busses() 1 | ||
| 22 | #define PCIBIOS_MIN_IO 0x00000000 | ||
| 23 | #define PCIBIOS_MIN_MEM 0x00000000 | ||
| 24 | |||
| 25 | #ifndef __ASSEMBLY__ | ||
| 26 | void iop32x_init_irq(void); | ||
| 27 | #endif | ||
| 28 | |||
| 29 | |||
| 30 | /* | ||
| 31 | * Generic chipset bits | ||
| 32 | */ | ||
| 33 | #include "iop32x.h" | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Board specific bits | ||
| 37 | */ | ||
| 38 | #include "glantank.h" | ||
| 39 | #include "iq80321.h" | ||
| 40 | #include "iq31244.h" | ||
| 41 | #include "n2100.h" | ||
| 42 | |||
| 43 | |||
| 44 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h deleted file mode 100644 index 47b2736236e4..000000000000 --- a/include/asm-arm/arch-iop32x/io.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 MontaVista Software, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __IO_H | ||
| 12 | #define __IO_H | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, | ||
| 17 | unsigned int mtype); | ||
| 18 | extern void __iop3xx_iounmap(void __iomem *addr); | ||
| 19 | |||
| 20 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 21 | #define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) | ||
| 22 | #define __mem_pci(a) (a) | ||
| 23 | |||
| 24 | #define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f) | ||
| 25 | #define __arch_iounmap(a) __iop3xx_iounmap(a) | ||
| 26 | |||
| 27 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/iop32x.h b/include/asm-arm/arch-iop32x/iop32x.h deleted file mode 100644 index 0d8af57221a1..000000000000 --- a/include/asm-arm/arch-iop32x/iop32x.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/iop32x.h | ||
| 3 | * | ||
| 4 | * Intel IOP32X Chip definitions | ||
| 5 | * | ||
| 6 | * Author: Rory Bolt <rorybolt@pacbell.net> | ||
| 7 | * Copyright (C) 2002 Rory Bolt | ||
| 8 | * Copyright (C) 2004 Intel Corp. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __IOP32X_H | ||
| 16 | #define __IOP32X_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripherals that are shared between the iop32x and iop33x but | ||
| 20 | * located at different addresses. | ||
| 21 | */ | ||
| 22 | #define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c4 + (reg)) | ||
| 23 | #define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) | ||
| 24 | |||
| 25 | #include <asm/hardware/iop3xx.h> | ||
| 26 | |||
| 27 | /* ATU Parameters | ||
| 28 | * set up a 1:1 bus to physical ram relationship | ||
| 29 | * w/ physical ram on top of pci in the memory map | ||
| 30 | */ | ||
| 31 | #define IOP32X_MAX_RAM_SIZE 0x40000000UL | ||
| 32 | #define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE | ||
| 33 | #define IOP3XX_PCI_LOWER_MEM_BA 0x80000000 | ||
| 34 | #define IOP32X_PCI_MEM_WINDOW_SIZE 0x04000000 | ||
| 35 | #define IOP3XX_PCI_MEM_WINDOW_SIZE IOP32X_PCI_MEM_WINDOW_SIZE | ||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/iq31244.h b/include/asm-arm/arch-iop32x/iq31244.h deleted file mode 100644 index fff4eafa1f6b..000000000000 --- a/include/asm-arm/arch-iop32x/iq31244.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/iq31244.h | ||
| 3 | * | ||
| 4 | * Intel IQ31244 evaluation board registers | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __IQ31244_H | ||
| 8 | #define __IQ31244_H | ||
| 9 | |||
| 10 | #define IQ31244_UART 0xfe800000 /* UART #1 */ | ||
| 11 | #define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ | ||
| 12 | #define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ | ||
| 13 | #define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ | ||
| 14 | #define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ | ||
| 15 | |||
| 16 | |||
| 17 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/iq80321.h b/include/asm-arm/arch-iop32x/iq80321.h deleted file mode 100644 index eb69db9b9a06..000000000000 --- a/include/asm-arm/arch-iop32x/iq80321.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/iq80321.h | ||
| 3 | * | ||
| 4 | * Intel IQ80321 evaluation board registers | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __IQ80321_H | ||
| 8 | #define __IQ80321_H | ||
| 9 | |||
| 10 | #define IQ80321_UART 0xfe800000 /* UART #1 */ | ||
| 11 | #define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ | ||
| 12 | #define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ | ||
| 13 | #define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ | ||
| 14 | #define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ | ||
| 15 | |||
| 16 | |||
| 17 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h deleted file mode 100644 index bbaef873afce..000000000000 --- a/include/asm-arm/arch-iop32x/irqs.h +++ /dev/null | |||
| @@ -1,50 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/irqs.h | ||
| 3 | * | ||
| 4 | * Author: Rory Bolt <rorybolt@pacbell.net> | ||
| 5 | * Copyright: (C) 2002 Rory Bolt | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __IRQS_H | ||
| 13 | #define __IRQS_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * IOP80321 chipset interrupts | ||
| 17 | */ | ||
| 18 | #define IRQ_IOP32X_DMA0_EOT 0 | ||
| 19 | #define IRQ_IOP32X_DMA0_EOC 1 | ||
| 20 | #define IRQ_IOP32X_DMA1_EOT 2 | ||
| 21 | #define IRQ_IOP32X_DMA1_EOC 3 | ||
| 22 | #define IRQ_IOP32X_AA_EOT 6 | ||
| 23 | #define IRQ_IOP32X_AA_EOC 7 | ||
| 24 | #define IRQ_IOP32X_CORE_PMON 8 | ||
| 25 | #define IRQ_IOP32X_TIMER0 9 | ||
| 26 | #define IRQ_IOP32X_TIMER1 10 | ||
| 27 | #define IRQ_IOP32X_I2C_0 11 | ||
| 28 | #define IRQ_IOP32X_I2C_1 12 | ||
| 29 | #define IRQ_IOP32X_MESSAGING 13 | ||
| 30 | #define IRQ_IOP32X_ATU_BIST 14 | ||
| 31 | #define IRQ_IOP32X_PERFMON 15 | ||
| 32 | #define IRQ_IOP32X_CORE_PMU 16 | ||
| 33 | #define IRQ_IOP32X_BIU_ERR 17 | ||
| 34 | #define IRQ_IOP32X_ATU_ERR 18 | ||
| 35 | #define IRQ_IOP32X_MCU_ERR 19 | ||
| 36 | #define IRQ_IOP32X_DMA0_ERR 20 | ||
| 37 | #define IRQ_IOP32X_DMA1_ERR 21 | ||
| 38 | #define IRQ_IOP32X_AA_ERR 23 | ||
| 39 | #define IRQ_IOP32X_MSG_ERR 24 | ||
| 40 | #define IRQ_IOP32X_SSP 25 | ||
| 41 | #define IRQ_IOP32X_XINT0 27 | ||
| 42 | #define IRQ_IOP32X_XINT1 28 | ||
| 43 | #define IRQ_IOP32X_XINT2 29 | ||
| 44 | #define IRQ_IOP32X_XINT3 30 | ||
| 45 | #define IRQ_IOP32X_HPI 31 | ||
| 46 | |||
| 47 | #define NR_IRQS 32 | ||
| 48 | |||
| 49 | |||
| 50 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h deleted file mode 100644 index bdcf03895ee0..000000000000 --- a/include/asm-arm/arch-iop32x/memory.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/memory.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __MEMORY_H | ||
| 6 | #define __MEMORY_H | ||
| 7 | |||
| 8 | #include <asm/arch/hardware.h> | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Physical DRAM offset. | ||
| 12 | */ | ||
| 13 | #define PHYS_OFFSET UL(0xa0000000) | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Virtual view <-> PCI DMA view memory address translations | ||
| 17 | * virt_to_bus: Used to translate the virtual address to an | ||
| 18 | * address suitable to be passed to set_dma_addr | ||
| 19 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 20 | * to an address that the kernel can use. | ||
| 21 | */ | ||
| 22 | #define __virt_to_bus(x) (__virt_to_phys(x)) | ||
| 23 | #define __bus_to_virt(x) (__phys_to_virt(x)) | ||
| 24 | |||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/n2100.h b/include/asm-arm/arch-iop32x/n2100.h deleted file mode 100644 index 77a8af476629..000000000000 --- a/include/asm-arm/arch-iop32x/n2100.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/n2100.h | ||
| 3 | * | ||
| 4 | * Thecus N2100 board registers | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __N2100_H | ||
| 8 | #define __N2100_H | ||
| 9 | |||
| 10 | #define N2100_UART 0xfe800000 /* UART */ | ||
| 11 | |||
| 12 | #define N2100_COPY_BUTTON IOP3XX_GPIO_LINE(0) | ||
| 13 | #define N2100_PCA9532_RESET IOP3XX_GPIO_LINE(2) | ||
| 14 | #define N2100_RESET_BUTTON IOP3XX_GPIO_LINE(3) | ||
| 15 | #define N2100_HARDWARE_RESET IOP3XX_GPIO_LINE(4) | ||
| 16 | #define N2100_POWER_BUTTON IOP3XX_GPIO_LINE(5) | ||
| 17 | |||
| 18 | |||
| 19 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/system.h b/include/asm-arm/arch-iop32x/system.h deleted file mode 100644 index 17b7eb7e9c0d..000000000000 --- a/include/asm-arm/arch-iop32x/system.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 MontaVista Software, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/mach-types.h> | ||
| 12 | |||
| 13 | static inline void arch_idle(void) | ||
| 14 | { | ||
| 15 | cpu_do_idle(); | ||
| 16 | } | ||
| 17 | |||
| 18 | static inline void arch_reset(char mode) | ||
| 19 | { | ||
| 20 | local_irq_disable(); | ||
| 21 | |||
| 22 | if (machine_is_n2100()) { | ||
| 23 | gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW); | ||
| 24 | gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT); | ||
| 25 | while (1) | ||
| 26 | ; | ||
| 27 | } | ||
| 28 | |||
| 29 | *IOP3XX_PCSR = 0x30; | ||
| 30 | |||
| 31 | /* Jump into ROM at address 0 */ | ||
| 32 | cpu_reset(0); | ||
| 33 | } | ||
diff --git a/include/asm-arm/arch-iop32x/time.h b/include/asm-arm/arch-iop32x/time.h deleted file mode 100644 index 0f28c9949623..000000000000 --- a/include/asm-arm/arch-iop32x/time.h +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | #ifndef _IOP32X_TIME_H_ | ||
| 2 | #define _IOP32X_TIME_H_ | ||
| 3 | #define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0 | ||
| 4 | #endif | ||
diff --git a/include/asm-arm/arch-iop32x/timex.h b/include/asm-arm/arch-iop32x/timex.h deleted file mode 100644 index 445704619825..000000000000 --- a/include/asm-arm/arch-iop32x/timex.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/timex.h | ||
| 3 | * | ||
| 4 | * IOP32x architecture timex specifications | ||
| 5 | */ | ||
| 6 | |||
| 7 | #include <asm/arch/hardware.h> | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h deleted file mode 100644 index 07028786394e..000000000000 --- a/include/asm-arm/arch-iop32x/uncompress.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/uncompress.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #include <asm/types.h> | ||
| 6 | #include <asm/mach-types.h> | ||
| 7 | #include <linux/serial_reg.h> | ||
| 8 | #include <asm/arch/hardware.h> | ||
| 9 | |||
| 10 | static volatile u8 *uart_base; | ||
| 11 | |||
| 12 | #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) | ||
| 13 | |||
| 14 | static inline void putc(char c) | ||
| 15 | { | ||
| 16 | while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) | ||
| 17 | barrier(); | ||
| 18 | uart_base[UART_TX] = c; | ||
| 19 | } | ||
| 20 | |||
| 21 | static inline void flush(void) | ||
| 22 | { | ||
| 23 | } | ||
| 24 | |||
| 25 | static __inline__ void __arch_decomp_setup(unsigned long arch_id) | ||
| 26 | { | ||
| 27 | if (machine_is_iq80321()) | ||
| 28 | uart_base = (volatile u8 *)IQ80321_UART; | ||
| 29 | else if (machine_is_iq31244() || machine_is_em7210()) | ||
| 30 | uart_base = (volatile u8 *)IQ31244_UART; | ||
| 31 | else | ||
| 32 | uart_base = (volatile u8 *)0xfe800000; | ||
| 33 | } | ||
| 34 | |||
| 35 | /* | ||
| 36 | * nothing to do | ||
| 37 | */ | ||
| 38 | #define arch_decomp_setup() __arch_decomp_setup(arch_id) | ||
| 39 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-iop32x/vmalloc.h b/include/asm-arm/arch-iop32x/vmalloc.h deleted file mode 100644 index 0a70baa19517..000000000000 --- a/include/asm-arm/arch-iop32x/vmalloc.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop32x/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define VMALLOC_END 0xfe000000 | ||
diff --git a/include/asm-arm/arch-iop33x/adma.h b/include/asm-arm/arch-iop33x/adma.h deleted file mode 100644 index 4b92f795f90e..000000000000 --- a/include/asm-arm/arch-iop33x/adma.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | #ifndef IOP33X_ADMA_H | ||
| 2 | #define IOP33X_ADMA_H | ||
| 3 | #include <asm/hardware/iop3xx-adma.h> | ||
| 4 | #endif | ||
| 5 | |||
diff --git a/include/asm-arm/arch-iop33x/debug-macro.S b/include/asm-arm/arch-iop33x/debug-macro.S deleted file mode 100644 index 9e7132ebe6a7..000000000000 --- a/include/asm-arm/arch-iop33x/debug-macro.S +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/debug-macro.S | ||
| 3 | * | ||
| 4 | * Debugging macro include header | ||
| 5 | * | ||
| 6 | * Copyright (C) 1994-1999 Russell King | ||
| 7 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart, rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ mmu enabled? | ||
| 17 | moveq \rx, #0xff000000 @ physical | ||
| 18 | movne \rx, #0xfe000000 @ virtual | ||
| 19 | orr \rx, \rx, #0x00ff0000 | ||
| 20 | orr \rx, \rx, #0x0000f700 | ||
| 21 | .endm | ||
| 22 | |||
| 23 | #define UART_SHIFT 2 | ||
| 24 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-iop33x/dma.h b/include/asm-arm/arch-iop33x/dma.h deleted file mode 100644 index b7775fdc5ad3..000000000000 --- a/include/asm-arm/arch-iop33x/dma.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 Intel Corp. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S deleted file mode 100644 index b8e3d449e882..000000000000 --- a/include/asm-arm/arch-iop33x/entry-macro.S +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for IOP33x-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/iop33x.h> | ||
| 11 | |||
| 12 | .macro disable_fiq | ||
| 13 | .endm | ||
| 14 | |||
| 15 | .macro get_irqnr_preamble, base, tmp | ||
| 16 | mrc p15, 0, \tmp, c15, c1, 0 | ||
| 17 | orr \tmp, \tmp, #(1 << 6) | ||
| 18 | mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access | ||
| 19 | mrc p15, 0, \tmp, c15, c1, 0 | ||
| 20 | mov \tmp, \tmp | ||
| 21 | sub pc, pc, #4 @ cp_wait | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 25 | mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC | ||
| 26 | cmp \irqstat, #0 | ||
| 27 | mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround | ||
| 28 | adds \irqnr, \irqstat, #1 | ||
| 29 | movne \irqnr, \irqstat, lsr #2 | ||
| 30 | .endm | ||
| 31 | |||
| 32 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 33 | mrc p15, 0, \tmp1, c15, c1, 0 | ||
| 34 | ands \tmp2, \tmp1, #(1 << 6) | ||
| 35 | bicne \tmp1, \tmp1, #(1 << 6) | ||
| 36 | mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access | ||
| 37 | .endm | ||
diff --git a/include/asm-arm/arch-iop33x/gpio.h b/include/asm-arm/arch-iop33x/gpio.h deleted file mode 100644 index ddd55bba9bb9..000000000000 --- a/include/asm-arm/arch-iop33x/gpio.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_IOP33X_GPIO_H | ||
| 2 | #define __ASM_ARCH_IOP33X_GPIO_H | ||
| 3 | |||
| 4 | #include <asm/hardware/iop3xx-gpio.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/include/asm-arm/arch-iop33x/hardware.h b/include/asm-arm/arch-iop33x/hardware.h deleted file mode 100644 index 0659cf94d040..000000000000 --- a/include/asm-arm/arch-iop33x/hardware.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/hardware.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __HARDWARE_H | ||
| 6 | #define __HARDWARE_H | ||
| 7 | |||
| 8 | #include <asm/types.h> | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Note about PCI IO space mappings | ||
| 12 | * | ||
| 13 | * To make IO space accesses efficient, we store virtual addresses in | ||
| 14 | * the IO resources. | ||
| 15 | * | ||
| 16 | * The PCI IO space is located at virtual 0xfe000000 from physical | ||
| 17 | * 0x90000000. The PCI BARs must be programmed with physical addresses, | ||
| 18 | * but when we read them, we convert them to virtual addresses. See | ||
| 19 | * arch/arm/mach-iop3xx/iop3xx-pci.c | ||
| 20 | */ | ||
| 21 | #define pcibios_assign_all_busses() 1 | ||
| 22 | #define PCIBIOS_MIN_IO 0x00000000 | ||
| 23 | #define PCIBIOS_MIN_MEM 0x00000000 | ||
| 24 | |||
| 25 | #ifndef __ASSEMBLY__ | ||
| 26 | void iop33x_init_irq(void); | ||
| 27 | |||
| 28 | extern struct platform_device iop33x_uart0_device; | ||
| 29 | extern struct platform_device iop33x_uart1_device; | ||
| 30 | #endif | ||
| 31 | |||
| 32 | |||
| 33 | /* | ||
| 34 | * Generic chipset bits | ||
| 35 | * | ||
| 36 | */ | ||
| 37 | #include "iop33x.h" | ||
| 38 | |||
| 39 | /* | ||
| 40 | * Board specific bits | ||
| 41 | */ | ||
| 42 | #include "iq80331.h" | ||
| 43 | #include "iq80332.h" | ||
| 44 | |||
| 45 | |||
| 46 | #endif | ||
diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h deleted file mode 100644 index 3fc607c46f03..000000000000 --- a/include/asm-arm/arch-iop33x/io.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 MontaVista Software, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __IO_H | ||
| 12 | #define __IO_H | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, | ||
| 17 | unsigned int mtype); | ||
| 18 | extern void __iop3xx_iounmap(void __iomem *addr); | ||
| 19 | |||
| 20 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 21 | #define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) | ||
| 22 | #define __mem_pci(a) (a) | ||
| 23 | |||
| 24 | #define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f) | ||
| 25 | #define __arch_iounmap(a) __iop3xx_iounmap(a) | ||
| 26 | |||
| 27 | #endif | ||
diff --git a/include/asm-arm/arch-iop33x/iop33x.h b/include/asm-arm/arch-iop33x/iop33x.h deleted file mode 100644 index 766985b9a723..000000000000 --- a/include/asm-arm/arch-iop33x/iop33x.h +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/iop33x.h | ||
| 3 | * | ||
| 4 | * Intel IOP33X Chip definitions | ||
| 5 | * | ||
| 6 | * Author: Dave Jiang (dave.jiang@intel.com) | ||
| 7 | * Copyright (C) 2003, 2004 Intel Corp. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __IOP33X_H | ||
| 15 | #define __IOP33X_H | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Peripherals that are shared between the iop32x and iop33x but | ||
| 19 | * located at different addresses. | ||
| 20 | */ | ||
| 21 | #define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg)) | ||
| 22 | #define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg)) | ||
| 23 | |||
| 24 | #include <asm/hardware/iop3xx.h> | ||
| 25 | |||
| 26 | /* UARTs */ | ||
| 27 | #define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700) | ||
| 28 | #define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700) | ||
| 29 | #define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740) | ||
| 30 | #define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740) | ||
| 31 | |||
| 32 | /* ATU Parameters | ||
| 33 | * set up a 1:1 bus to physical ram relationship | ||
| 34 | * w/ pci on top of physical ram in memory map | ||
| 35 | */ | ||
| 36 | #define IOP33X_MAX_RAM_SIZE 0x80000000UL | ||
| 37 | #define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE | ||
| 38 | #define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE) | ||
| 39 | #define IOP33X_PCI_MEM_WINDOW_SIZE 0x08000000 | ||
| 40 | #define IOP3XX_PCI_MEM_WINDOW_SIZE IOP33X_PCI_MEM_WINDOW_SIZE | ||
| 41 | |||
| 42 | |||
| 43 | #endif | ||
diff --git a/include/asm-arm/arch-iop33x/iq80331.h b/include/asm-arm/arch-iop33x/iq80331.h deleted file mode 100644 index 79b9302017ea..000000000000 --- a/include/asm-arm/arch-iop33x/iq80331.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/iq80331.h | ||
| 3 | * | ||
| 4 | * Intel IQ80331 evaluation board registers | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __IQ80331_H | ||
| 8 | #define __IQ80331_H | ||
| 9 | |||
| 10 | #define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */ | ||
| 11 | #define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ | ||
| 12 | #define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */ | ||
| 13 | #define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */ | ||
| 14 | |||
| 15 | |||
| 16 | #endif | ||
diff --git a/include/asm-arm/arch-iop33x/iq80332.h b/include/asm-arm/arch-iop33x/iq80332.h deleted file mode 100644 index 053165629492..000000000000 --- a/include/asm-arm/arch-iop33x/iq80332.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/iq80332.h | ||
| 3 | * | ||
| 4 | * Intel IQ80332 evaluation board registers | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __IQ80332_H | ||
| 8 | #define __IQ80332_H | ||
| 9 | |||
| 10 | #define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */ | ||
| 11 | #define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */ | ||
| 12 | #define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */ | ||
| 13 | #define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */ | ||
| 14 | |||
| 15 | |||
| 16 | #endif | ||
diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h deleted file mode 100644 index d045f8403396..000000000000 --- a/include/asm-arm/arch-iop33x/irqs.h +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/irqs.h | ||
| 3 | * | ||
| 4 | * Author: Dave Jiang (dave.jiang@intel.com) | ||
| 5 | * Copyright: (C) 2003 Intel Corp. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __IRQS_H | ||
| 13 | #define __IRQS_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * IOP80331 chipset interrupts | ||
| 17 | */ | ||
| 18 | #define IRQ_IOP33X_DMA0_EOT 0 | ||
| 19 | #define IRQ_IOP33X_DMA0_EOC 1 | ||
| 20 | #define IRQ_IOP33X_DMA1_EOT 2 | ||
| 21 | #define IRQ_IOP33X_DMA1_EOC 3 | ||
| 22 | #define IRQ_IOP33X_AA_EOT 6 | ||
| 23 | #define IRQ_IOP33X_AA_EOC 7 | ||
| 24 | #define IRQ_IOP33X_TIMER0 8 | ||
| 25 | #define IRQ_IOP33X_TIMER1 9 | ||
| 26 | #define IRQ_IOP33X_I2C_0 10 | ||
| 27 | #define IRQ_IOP33X_I2C_1 11 | ||
| 28 | #define IRQ_IOP33X_MSG 12 | ||
| 29 | #define IRQ_IOP33X_MSGIBQ 13 | ||
| 30 | #define IRQ_IOP33X_ATU_BIST 14 | ||
| 31 | #define IRQ_IOP33X_PERFMON 15 | ||
| 32 | #define IRQ_IOP33X_CORE_PMU 16 | ||
| 33 | #define IRQ_IOP33X_XINT0 24 | ||
| 34 | #define IRQ_IOP33X_XINT1 25 | ||
| 35 | #define IRQ_IOP33X_XINT2 26 | ||
| 36 | #define IRQ_IOP33X_XINT3 27 | ||
| 37 | #define IRQ_IOP33X_XINT8 32 | ||
| 38 | #define IRQ_IOP33X_XINT9 33 | ||
| 39 | #define IRQ_IOP33X_XINT10 34 | ||
| 40 | #define IRQ_IOP33X_XINT11 35 | ||
| 41 | #define IRQ_IOP33X_XINT12 36 | ||
| 42 | #define IRQ_IOP33X_XINT13 37 | ||
| 43 | #define IRQ_IOP33X_XINT14 38 | ||
| 44 | #define IRQ_IOP33X_XINT15 39 | ||
| 45 | #define IRQ_IOP33X_UART0 51 | ||
| 46 | #define IRQ_IOP33X_UART1 52 | ||
| 47 | #define IRQ_IOP33X_PBIE 53 | ||
| 48 | #define IRQ_IOP33X_ATU_CRW 54 | ||
| 49 | #define IRQ_IOP33X_ATU_ERR 55 | ||
| 50 | #define IRQ_IOP33X_MCU_ERR 56 | ||
| 51 | #define IRQ_IOP33X_DMA0_ERR 57 | ||
| 52 | #define IRQ_IOP33X_DMA1_ERR 58 | ||
| 53 | #define IRQ_IOP33X_AA_ERR 60 | ||
| 54 | #define IRQ_IOP33X_MSG_ERR 62 | ||
| 55 | #define IRQ_IOP33X_HPI 63 | ||
| 56 | |||
| 57 | #define NR_IRQS 64 | ||
| 58 | |||
| 59 | |||
| 60 | #endif | ||
diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h deleted file mode 100644 index d798d83c83a5..000000000000 --- a/include/asm-arm/arch-iop33x/memory.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/memory.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __MEMORY_H | ||
| 6 | #define __MEMORY_H | ||
| 7 | |||
| 8 | #include <asm/arch/hardware.h> | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Physical DRAM offset. | ||
| 12 | */ | ||
| 13 | #define PHYS_OFFSET UL(0x00000000) | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Virtual view <-> PCI DMA view memory address translations | ||
| 17 | * virt_to_bus: Used to translate the virtual address to an | ||
| 18 | * address suitable to be passed to set_dma_addr | ||
| 19 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 20 | * to an address that the kernel can use. | ||
| 21 | */ | ||
| 22 | #define __virt_to_bus(x) (__virt_to_phys(x)) | ||
| 23 | #define __bus_to_virt(x) (__phys_to_virt(x)) | ||
| 24 | |||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-arm/arch-iop33x/system.h b/include/asm-arm/arch-iop33x/system.h deleted file mode 100644 index 00dd07ece262..000000000000 --- a/include/asm-arm/arch-iop33x/system.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 MontaVista Software, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | static inline void arch_idle(void) | ||
| 12 | { | ||
| 13 | cpu_do_idle(); | ||
| 14 | } | ||
| 15 | |||
| 16 | static inline void arch_reset(char mode) | ||
| 17 | { | ||
| 18 | *IOP3XX_PCSR = 0x30; | ||
| 19 | |||
| 20 | /* Jump into ROM at address 0 */ | ||
| 21 | cpu_reset(0); | ||
| 22 | } | ||
diff --git a/include/asm-arm/arch-iop33x/time.h b/include/asm-arm/arch-iop33x/time.h deleted file mode 100644 index 4ac4d7664f85..000000000000 --- a/include/asm-arm/arch-iop33x/time.h +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | #ifndef _IOP33X_TIME_H_ | ||
| 2 | #define _IOP33X_TIME_H_ | ||
| 3 | #define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0 | ||
| 4 | #endif | ||
diff --git a/include/asm-arm/arch-iop33x/timex.h b/include/asm-arm/arch-iop33x/timex.h deleted file mode 100644 index 75a001e93daf..000000000000 --- a/include/asm-arm/arch-iop33x/timex.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/timex.h | ||
| 3 | * | ||
| 4 | * IOP3xx architecture timex specifications | ||
| 5 | */ | ||
| 6 | |||
| 7 | #include <asm/arch/hardware.h> | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/include/asm-arm/arch-iop33x/uncompress.h b/include/asm-arm/arch-iop33x/uncompress.h deleted file mode 100644 index 34d9e8e8287a..000000000000 --- a/include/asm-arm/arch-iop33x/uncompress.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/uncompress.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #include <asm/types.h> | ||
| 6 | #include <asm/mach-types.h> | ||
| 7 | #include <linux/serial_reg.h> | ||
| 8 | #include <asm/arch/hardware.h> | ||
| 9 | |||
| 10 | static volatile u32 *uart_base; | ||
| 11 | |||
| 12 | #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) | ||
| 13 | |||
| 14 | static inline void putc(char c) | ||
| 15 | { | ||
| 16 | while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) | ||
| 17 | barrier(); | ||
| 18 | uart_base[UART_TX] = c; | ||
| 19 | } | ||
| 20 | |||
| 21 | static inline void flush(void) | ||
| 22 | { | ||
| 23 | } | ||
| 24 | |||
| 25 | static __inline__ void __arch_decomp_setup(unsigned long arch_id) | ||
| 26 | { | ||
| 27 | if (machine_is_iq80331() || machine_is_iq80332()) | ||
| 28 | uart_base = (volatile u32 *)IOP33X_UART0_PHYS; | ||
| 29 | else | ||
| 30 | uart_base = (volatile u32 *)0xfe800000; | ||
| 31 | } | ||
| 32 | |||
| 33 | /* | ||
| 34 | * nothing to do | ||
| 35 | */ | ||
| 36 | #define arch_decomp_setup() __arch_decomp_setup(arch_id) | ||
| 37 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-iop33x/vmalloc.h b/include/asm-arm/arch-iop33x/vmalloc.h deleted file mode 100644 index 66f545a7f4fc..000000000000 --- a/include/asm-arm/arch-iop33x/vmalloc.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-iop33x/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define VMALLOC_END 0xfe000000 | ||
diff --git a/include/asm-arm/arch-ixp2000/debug-macro.S b/include/asm-arm/arch-ixp2000/debug-macro.S deleted file mode 100644 index bc8b39654793..000000000000 --- a/include/asm-arm/arch-ixp2000/debug-macro.S +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-ixp2000/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | moveq \rx, #0xc0000000 @ Physical base | ||
| 18 | movne \rx, #0xfe000000 @ virtual base | ||
| 19 | orrne \rx, \rx, #0x00f00000 | ||
| 20 | orr \rx, \rx, #0x00030000 | ||
| 21 | #ifdef __ARMEB__ | ||
| 22 | orr \rx, \rx, #0x00000003 | ||
| 23 | #endif | ||
| 24 | .endm | ||
| 25 | |||
| 26 | #define UART_SHIFT 2 | ||
| 27 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-ixp2000/dma.h b/include/asm-arm/arch-ixp2000/dma.h deleted file mode 100644 index 548d8dc507eb..000000000000 --- a/include/asm-arm/arch-ixp2000/dma.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp2000/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002 Intel Corp. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h deleted file mode 100644 index 42f3c28dc5c4..000000000000 --- a/include/asm-arm/arch-ixp2000/enp2611.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp2000/enp2611.h | ||
| 3 | * | ||
| 4 | * Register and other defines for Radisys ENP-2611 | ||
| 5 | * | ||
| 6 | * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The | ||
| 7 | * original version carries the following notices: | ||
| 8 | * | ||
| 9 | * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> | ||
| 10 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | ||
| 11 | * | ||
| 12 | * Copyright (C) 2002 Intel Corp. | ||
| 13 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify it | ||
| 16 | * under the terms of the GNU General Public License as published by the | ||
| 17 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 18 | * option) any later version. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ENP2611_H | ||
| 22 | #define __ENP2611_H | ||
| 23 | |||
| 24 | #define ENP2611_CALEB_PHYS_BASE 0xc5000000 | ||
| 25 | #define ENP2611_CALEB_VIRT_BASE 0xfe000000 | ||
| 26 | #define ENP2611_CALEB_SIZE 0x00100000 | ||
| 27 | |||
| 28 | #define ENP2611_PM3386_0_PHYS_BASE 0xc6000000 | ||
| 29 | #define ENP2611_PM3386_0_VIRT_BASE 0xfe100000 | ||
| 30 | #define ENP2611_PM3386_0_SIZE 0x00100000 | ||
| 31 | |||
| 32 | #define ENP2611_PM3386_1_PHYS_BASE 0xc6400000 | ||
| 33 | #define ENP2611_PM3386_1_VIRT_BASE 0xfe200000 | ||
| 34 | #define ENP2611_PM3386_1_SIZE 0x00100000 | ||
| 35 | |||
| 36 | #define ENP2611_GPIO_SCL 7 | ||
| 37 | #define ENP2611_GPIO_SDA 6 | ||
| 38 | |||
| 39 | #define IRQ_ENP2611_THERMAL IRQ_IXP2000_GPIO4 | ||
| 40 | #define IRQ_ENP2611_OPTION_BOARD IRQ_IXP2000_GPIO3 | ||
| 41 | #define IRQ_ENP2611_CALEB IRQ_IXP2000_GPIO2 | ||
| 42 | #define IRQ_ENP2611_PM3386_1 IRQ_IXP2000_GPIO1 | ||
| 43 | #define IRQ_ENP2611_PM3386_0 IRQ_IXP2000_GPIO0 | ||
| 44 | |||
| 45 | |||
| 46 | #endif | ||
diff --git a/include/asm-arm/arch-ixp2000/entry-macro.S b/include/asm-arm/arch-ixp2000/entry-macro.S deleted file mode 100644 index 11d512ad5945..000000000000 --- a/include/asm-arm/arch-ixp2000/entry-macro.S +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp2000/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for IXP2000-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/irqs.h> | ||
| 11 | |||
| 12 | .macro disable_fiq | ||
| 13 | .endm | ||
| 14 | |||
| 15 | .macro get_irqnr_preamble, base, tmp | ||
| 16 | .endm | ||
| 17 | |||
| 18 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 22 | |||
| 23 | mov \irqnr, #0x0 @clear out irqnr as default | ||
| 24 | mov \base, #0xfe000000 | ||
| 25 | orr \base, \base, #0x00e00000 | ||
| 26 | orr \base, \base, #0x08 | ||
| 27 | ldr \irqstat, [\base] @ get interrupts | ||
| 28 | |||
| 29 | cmp \irqstat, #0 | ||
| 30 | beq 1001f | ||
| 31 | |||
| 32 | clz \irqnr, \irqstat | ||
| 33 | mov \base, #31 | ||
| 34 | subs \irqnr, \base, \irqnr | ||
| 35 | |||
| 36 | /* | ||
| 37 | * We handle PCIA and PCIB here so we don't have an | ||
| 38 | * extra layer of code just to check these two bits. | ||
| 39 | */ | ||
| 40 | cmp \irqnr, #IRQ_IXP2000_PCI | ||
| 41 | bne 1001f | ||
| 42 | |||
| 43 | mov \base, #0xfe000000 | ||
| 44 | orr \base, \base, #0x00c00000 | ||
| 45 | orr \base, \base, #0x00000100 | ||
| 46 | orr \base, \base, #0x00000058 | ||
| 47 | ldr \irqstat, [\base] | ||
| 48 | |||
| 49 | mov \tmp, #(1<<26) | ||
| 50 | tst \irqstat, \tmp | ||
| 51 | movne \irqnr, #IRQ_IXP2000_PCIA | ||
| 52 | bne 1001f | ||
| 53 | |||
| 54 | mov \tmp, #(1<<27) | ||
| 55 | tst \irqstat, \tmp | ||
| 56 | movne \irqnr, #IRQ_IXP2000_PCIB | ||
| 57 | |||
| 58 | 1001: | ||
| 59 | .endm | ||
| 60 | |||
diff --git a/include/asm-arm/arch-ixp2000/gpio.h b/include/asm-arm/arch-ixp2000/gpio.h deleted file mode 100644 index 03cbbe1fd9d8..000000000000 --- a/include/asm-arm/arch-ixp2000/gpio.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp2000/gpio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002 Intel Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software, you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /* | ||
| 12 | * IXP2000 GPIO in/out, edge/level detection for IRQs: | ||
| 13 | * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High | ||
| 14 | * or both Falling-edge and Rising-edge. | ||
| 15 | * This must be called *before* the corresponding IRQ is registerd. | ||
| 16 | * Use this instead of directly setting the GPIO registers. | ||
| 17 | * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb) | ||
| 18 | */ | ||
| 19 | #ifndef __ASM_ARCH_GPIO_H | ||
| 20 | #define __ASM_ARCH_GPIO_H | ||
| 21 | |||
| 22 | #ifndef __ASSEMBLY__ | ||
| 23 | |||
| 24 | #define GPIO_IN 0 | ||
| 25 | #define GPIO_OUT 1 | ||
| 26 | |||
| 27 | #define IXP2000_GPIO_LOW 0 | ||
| 28 | #define IXP2000_GPIO_HIGH 1 | ||
| 29 | |||
| 30 | extern void gpio_line_config(int line, int direction); | ||
| 31 | |||
| 32 | static inline int gpio_line_get(int line) | ||
| 33 | { | ||
| 34 | return (((*IXP2000_GPIO_PLR) >> line) & 1); | ||
| 35 | } | ||
| 36 | |||
| 37 | static inline void gpio_line_set(int line, int value) | ||
| 38 | { | ||
| 39 | if (value == IXP2000_GPIO_HIGH) { | ||
| 40 | ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line); | ||
| 41 | } else if (value == IXP2000_GPIO_LOW) { | ||
| 42 | ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line); | ||
| 43 | } | ||
| 44 | } | ||
| 45 | |||
| 46 | #endif /* !__ASSEMBLY__ */ | ||
| 47 | |||
| 48 | #endif /* ASM_ARCH_IXP2000_GPIO_H_ */ | ||
diff --git a/include/asm-arm/arch-ixp2000/hardware.h b/include/asm-arm/arch-ixp2000/hardware.h deleted file mode 100644 index e7ea781c48aa..000000000000 --- a/include/asm-arm/arch-ixp2000/hardware.h +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp2000/hardware.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for IXP2400/2800 based systems | ||
| 5 | * | ||
| 6 | * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> | ||
| 7 | * | ||
| 8 | * Maintainer: Deepak Saxena <dsaxena@mvista.com> | ||
| 9 | * | ||
| 10 | * Copyright (C) 2001-2002 Intel Corp. | ||
| 11 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify it | ||
| 14 | * under the terms of the GNU General Public License as published by the | ||
| 15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 16 | * option) any later version. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 20 | #define __ASM_ARCH_HARDWARE_H__ | ||
| 21 | |||
| 22 | /* | ||
| 23 | * This needs to be platform-specific? | ||
| 24 | */ | ||
| 25 | #define PCIBIOS_MIN_IO 0x00000000 | ||
| 26 | #define PCIBIOS_MIN_MEM 0x00000000 | ||
| 27 | |||
| 28 | #include "ixp2000-regs.h" /* Chipset Registers */ | ||
| 29 | |||
| 30 | #define pcibios_assign_all_busses() 0 | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Platform helper functions | ||
| 34 | */ | ||
| 35 | #include "platform.h" | ||
| 36 | |||
| 37 | /* | ||
| 38 | * Platform-specific bits | ||
| 39 | */ | ||
| 40 | #include "enp2611.h" /* ENP-2611 */ | ||
| 41 | #include "ixdp2x00.h" /* IXDP2400/2800 */ | ||
| 42 | #include "ixdp2x01.h" /* IXDP2401/2801 */ | ||
| 43 | |||
| 44 | #endif /* _ASM_ARCH_HARDWARE_H__ */ | ||
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h deleted file mode 100644 index 5dc1d25dcb4f..000000000000 --- a/include/asm-arm/arch-ixp2000/io.h +++ /dev/null | |||
| @@ -1,134 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp2000/io.h | ||
| 3 | * | ||
| 4 | * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> | ||
| 5 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | ||
| 6 | * | ||
| 7 | * Copyright (C) 2002 Intel Corp. | ||
| 8 | * Copyrgiht (C) 2003-2004 MontaVista Software, Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 16 | #define __ASM_ARM_ARCH_IO_H | ||
| 17 | |||
| 18 | #include <asm/arch/hardware.h> | ||
| 19 | |||
| 20 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 21 | #define __mem_pci(a) (a) | ||
| 22 | |||
| 23 | /* | ||
| 24 | * The A? revisions of the IXP2000s assert byte lanes for PCI I/O | ||
| 25 | * transactions the other way round (MEM transactions don't have this | ||
| 26 | * issue), so if we want to support those models, we need to override | ||
| 27 | * the standard I/O functions. | ||
| 28 | * | ||
| 29 | * B0 and later have a bit that can be set to 1 to get the proper | ||
| 30 | * behavior for I/O transactions, which then allows us to use the | ||
| 31 | * standard I/O functions. This is what we do if the user does not | ||
| 32 | * explicitly ask for support for pre-B0. | ||
| 33 | */ | ||
| 34 | #ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO | ||
| 35 | #define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) | ||
| 36 | |||
| 37 | #define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3) | ||
| 38 | #define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2) | ||
| 39 | |||
| 40 | #define outb(v,p) __raw_writeb((v),alignb(___io(p))) | ||
| 41 | #define outw(v,p) __raw_writew((v),alignw(___io(p))) | ||
| 42 | #define outl(v,p) __raw_writel((v),___io(p)) | ||
| 43 | |||
| 44 | #define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; }) | ||
| 45 | #define inw(p) \ | ||
| 46 | ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; }) | ||
| 47 | #define inl(p) \ | ||
| 48 | ({ unsigned int __v = (__raw_readl(___io(p))); __v; }) | ||
| 49 | |||
| 50 | #define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l) | ||
| 51 | #define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l) | ||
| 52 | #define outsl(p,d,l) __raw_writesl(___io(p),d,l) | ||
| 53 | |||
| 54 | #define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l) | ||
| 55 | #define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l) | ||
| 56 | #define insl(p,d,l) __raw_readsl(___io(p),d,l) | ||
| 57 | |||
| 58 | #define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE) | ||
| 59 | |||
| 60 | #define ioread8(p) \ | ||
| 61 | ({ \ | ||
| 62 | unsigned int __v; \ | ||
| 63 | \ | ||
| 64 | if (__is_io_address(p)) { \ | ||
| 65 | __v = __raw_readb(alignb(p)); \ | ||
| 66 | } else { \ | ||
| 67 | __v = __raw_readb(p); \ | ||
| 68 | } \ | ||
| 69 | \ | ||
| 70 | __v; \ | ||
| 71 | }) \ | ||
| 72 | |||
| 73 | #define ioread16(p) \ | ||
| 74 | ({ \ | ||
| 75 | unsigned int __v; \ | ||
| 76 | \ | ||
| 77 | if (__is_io_address(p)) { \ | ||
| 78 | __v = __raw_readw(alignw(p)); \ | ||
| 79 | } else { \ | ||
| 80 | __v = le16_to_cpu(__raw_readw(p)); \ | ||
| 81 | } \ | ||
| 82 | \ | ||
| 83 | __v; \ | ||
| 84 | }) | ||
| 85 | |||
| 86 | #define ioread32(p) \ | ||
| 87 | ({ \ | ||
| 88 | unsigned int __v; \ | ||
| 89 | \ | ||
| 90 | if (__is_io_address(p)) { \ | ||
| 91 | __v = __raw_readl(p); \ | ||
| 92 | } else { \ | ||
| 93 | __v = le32_to_cpu(__raw_readl(p)); \ | ||
| 94 | } \ | ||
| 95 | \ | ||
| 96 | __v; \ | ||
| 97 | }) | ||
| 98 | |||
| 99 | #define iowrite8(v,p) \ | ||
| 100 | ({ \ | ||
| 101 | if (__is_io_address(p)) { \ | ||
| 102 | __raw_writeb((v), alignb(p)); \ | ||
| 103 | } else { \ | ||
| 104 | __raw_writeb((v), p); \ | ||
| 105 | } \ | ||
| 106 | }) | ||
| 107 | |||
| 108 | #define iowrite16(v,p) \ | ||
| 109 | ({ \ | ||
| 110 | if (__is_io_address(p)) { \ | ||
| 111 | __raw_writew((v), alignw(p)); \ | ||
| 112 | } else { \ | ||
| 113 | __raw_writew(cpu_to_le16(v), p); \ | ||
| 114 | } \ | ||
| 115 | }) | ||
| 116 | |||
| 117 | #define iowrite32(v,p) \ | ||
| 118 | ({ \ | ||
| 119 | if (__is_io_address(p)) { \ | ||
| 120 | __raw_writel((v), p); \ | ||
| 121 | } else { \ | ||
| 122 | __raw_writel(cpu_to_le32(v), p); \ | ||
| 123 | } \ | ||
| 124 | }) | ||
| 125 | |||
| 126 | #define ioport_map(port, nr) ___io(port) | ||
| 127 | |||
| 128 | #define ioport_unmap(addr) | ||
| 129 | #else | ||
| 130 | #define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) | ||
| 131 | #endif | ||
| 132 | |||
| 133 | |||
| 134 | #endif | ||
diff --git a/include/asm-arm/arch-ixp2000/irqs.h b/include/asm-arm/arch-ixp2000/irqs.h deleted file mode 100644 index 62f09c7ff420..000000000000 --- a/include/asm-arm/arch-ixp2000/irqs.h +++ /dev/null | |||
| @@ -1,207 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp2000/irqs.h | ||
| 3 | * | ||
| 4 | * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> | ||
| 5 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | ||
| 6 | * | ||
| 7 | * Copyright (C) 2002 Intel Corp. | ||
| 8 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef _IRQS_H | ||
| 16 | #define _IRQS_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Do NOT add #ifdef MACHINE_FOO in here. | ||
| 20 | * Simpy add your machine IRQs here and increase NR_IRQS if needed to | ||
| 21 | * hold your machine's IRQ table. | ||
| 22 | */ | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Some interrupt numbers go unused b/c the IRQ mask/ummask/status | ||
| 26 | * register has those bit reserved. We just mark those interrupts | ||
| 27 | * as invalid and this allows us to do mask/unmask with a single | ||
| 28 | * shift operation instead of having to map the IRQ number to | ||
| 29 | * a HW IRQ number. | ||
| 30 | */ | ||
| 31 | #define IRQ_IXP2000_SOFT_INT 0 /* soft interrupt */ | ||
| 32 | #define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/ | ||
| 33 | #define IRQ_IXP2000_UART 2 | ||
| 34 | #define IRQ_IXP2000_GPIO 3 | ||
| 35 | #define IRQ_IXP2000_TIMER1 4 | ||
| 36 | #define IRQ_IXP2000_TIMER2 5 | ||
| 37 | #define IRQ_IXP2000_TIMER3 6 | ||
| 38 | #define IRQ_IXP2000_TIMER4 7 | ||
| 39 | #define IRQ_IXP2000_PMU 8 | ||
| 40 | #define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */ | ||
| 41 | #define IRQ_IXP2000_DMA1 10 | ||
| 42 | #define IRQ_IXP2000_DMA2 11 | ||
| 43 | #define IRQ_IXP2000_DMA3 12 | ||
| 44 | #define IRQ_IXP2000_PCI_DOORBELL 13 | ||
| 45 | #define IRQ_IXP2000_ME_ATTN 14 | ||
| 46 | #define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */ | ||
| 47 | #define IRQ_IXP2000_THDA0 16 /* thread 0-31A */ | ||
| 48 | #define IRQ_IXP2000_THDA1 17 /* thread 32-63A, IXP2800 only */ | ||
| 49 | #define IRQ_IXP2000_THDA2 18 /* thread 64-95A */ | ||
| 50 | #define IRQ_IXP2000_THDA3 19 /* thread 96-127A, IXP2800 only */ | ||
| 51 | #define IRQ_IXP2000_THDB0 24 /* thread 0-31B */ | ||
| 52 | #define IRQ_IXP2000_THDB1 25 /* thread 32-63B, IXP2800 only */ | ||
| 53 | #define IRQ_IXP2000_THDB2 26 /* thread 64-95B */ | ||
| 54 | #define IRQ_IXP2000_THDB3 27 /* thread 96-127B, IXP2800 only */ | ||
| 55 | |||
| 56 | /* define generic GPIOs */ | ||
| 57 | #define IRQ_IXP2000_GPIO0 32 | ||
| 58 | #define IRQ_IXP2000_GPIO1 33 | ||
| 59 | #define IRQ_IXP2000_GPIO2 34 | ||
| 60 | #define IRQ_IXP2000_GPIO3 35 | ||
| 61 | #define IRQ_IXP2000_GPIO4 36 | ||
| 62 | #define IRQ_IXP2000_GPIO5 37 | ||
| 63 | #define IRQ_IXP2000_GPIO6 38 | ||
| 64 | #define IRQ_IXP2000_GPIO7 39 | ||
| 65 | |||
| 66 | /* split off the 2 PCI sources */ | ||
| 67 | #define IRQ_IXP2000_PCIA 40 | ||
| 68 | #define IRQ_IXP2000_PCIB 41 | ||
| 69 | |||
| 70 | /* Int sources from IRQ_ERROR_STATUS */ | ||
| 71 | #define IRQ_IXP2000_DRAM0_MIN_ERR 42 | ||
| 72 | #define IRQ_IXP2000_DRAM0_MAJ_ERR 43 | ||
| 73 | #define IRQ_IXP2000_DRAM1_MIN_ERR 44 | ||
| 74 | #define IRQ_IXP2000_DRAM1_MAJ_ERR 45 | ||
| 75 | #define IRQ_IXP2000_DRAM2_MIN_ERR 46 | ||
| 76 | #define IRQ_IXP2000_DRAM2_MAJ_ERR 47 | ||
| 77 | /* 48-57 reserved */ | ||
| 78 | #define IRQ_IXP2000_SRAM0_ERR 58 | ||
| 79 | #define IRQ_IXP2000_SRAM1_ERR 59 | ||
| 80 | #define IRQ_IXP2000_SRAM2_ERR 60 | ||
| 81 | #define IRQ_IXP2000_SRAM3_ERR 61 | ||
| 82 | /* 62-65 reserved */ | ||
| 83 | #define IRQ_IXP2000_MEDIA_ERR 66 | ||
| 84 | #define IRQ_IXP2000_PCI_ERR 67 | ||
| 85 | #define IRQ_IXP2000_SP_INT 68 | ||
| 86 | |||
| 87 | #define NR_IXP2000_IRQS 69 | ||
| 88 | |||
| 89 | #define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x)) | ||
| 90 | |||
| 91 | #define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS)) | ||
| 92 | |||
| 93 | #define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) | ||
| 94 | #define IXP2000_VALID_ERR_IRQ_MASK (\ | ||
| 95 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \ | ||
| 96 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \ | ||
| 97 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \ | ||
| 98 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \ | ||
| 99 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \ | ||
| 100 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \ | ||
| 101 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \ | ||
| 102 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \ | ||
| 103 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \ | ||
| 104 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \ | ||
| 105 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \ | ||
| 106 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \ | ||
| 107 | IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) ) | ||
| 108 | |||
| 109 | /* | ||
| 110 | * This allows for all the on-chip sources plus up to 32 CPLD based | ||
| 111 | * IRQs. Should be more than enough. | ||
| 112 | */ | ||
| 113 | #define IXP2000_BOARD_IRQS 32 | ||
| 114 | #define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS) | ||
| 115 | |||
| 116 | |||
| 117 | /* | ||
| 118 | * IXDP2400 specific IRQs | ||
| 119 | */ | ||
| 120 | #define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0) | ||
| 121 | #define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1) | ||
| 122 | #define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2) | ||
| 123 | #define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3) | ||
| 124 | #define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4) | ||
| 125 | #define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5) | ||
| 126 | #define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6) | ||
| 127 | #define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7) | ||
| 128 | |||
| 129 | #define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1) | ||
| 130 | #define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS | ||
| 131 | |||
| 132 | /* IXDP2800 specific IRQs */ | ||
| 133 | #define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0) | ||
| 134 | #define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1) | ||
| 135 | #define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2) | ||
| 136 | #define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3) | ||
| 137 | #define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4) | ||
| 138 | #define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5) | ||
| 139 | |||
| 140 | #define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1) | ||
| 141 | #define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS | ||
| 142 | |||
| 143 | /* | ||
| 144 | * IRQs on both IXDP2x01 boards | ||
| 145 | */ | ||
| 146 | #define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2) | ||
| 147 | #define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3) | ||
| 148 | #define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4) | ||
| 149 | #define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5) | ||
| 150 | #define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6) | ||
| 151 | #define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7) | ||
| 152 | #define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8) | ||
| 153 | #define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16) | ||
| 154 | #define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17) | ||
| 155 | #define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18) | ||
| 156 | #define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19) | ||
| 157 | #define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21) | ||
| 158 | #define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22) | ||
| 159 | #define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24) | ||
| 160 | #define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25) | ||
| 161 | #define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26) | ||
| 162 | |||
| 163 | #define IXDP2X01_VALID_IRQ_MASK ( \ | ||
| 164 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \ | ||
| 165 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \ | ||
| 166 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \ | ||
| 167 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \ | ||
| 168 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \ | ||
| 169 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \ | ||
| 170 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \ | ||
| 171 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \ | ||
| 172 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \ | ||
| 173 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \ | ||
| 174 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \ | ||
| 175 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \ | ||
| 176 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \ | ||
| 177 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \ | ||
| 178 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \ | ||
| 179 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) ) | ||
| 180 | |||
| 181 | /* | ||
| 182 | * IXDP2401 specific IRQs | ||
| 183 | */ | ||
| 184 | #define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0) | ||
| 185 | #define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1) | ||
| 186 | |||
| 187 | #define IXDP2401_VALID_IRQ_MASK ( \ | ||
| 188 | IXDP2X01_VALID_IRQ_MASK | \ | ||
| 189 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\ | ||
| 190 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546)) | ||
| 191 | |||
| 192 | /* | ||
| 193 | * IXDP2801-specific IRQs | ||
| 194 | */ | ||
| 195 | #define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0) | ||
| 196 | #define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27) | ||
| 197 | #define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28) | ||
| 198 | |||
| 199 | #define IXDP2801_VALID_IRQ_MASK ( \ | ||
| 200 | IXDP2X01_VALID_IRQ_MASK | \ | ||
| 201 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\ | ||
| 202 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\ | ||
| 203 | IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF)) | ||
| 204 | |||
| 205 | #define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1) | ||
| 206 | |||
| 207 | #endif /*_IRQS_H*/ | ||
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x00.h b/include/asm-arm/arch-ixp2000/ixdp2x00.h deleted file mode 100644 index 546e2e8e27b8..000000000000 --- a/include/asm-arm/arch-ixp2000/ixdp2x00.h +++ /dev/null | |||
| @@ -1,92 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp2000/ixdp2x00.h | ||
| 3 | * | ||
| 4 | * Register and other defines for IXDP2[48]00 platforms | ||
| 5 | * | ||
| 6 | * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> | ||
| 7 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | ||
| 8 | * | ||
| 9 | * Copyright (C) 2002 Intel Corp. | ||
| 10 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify it | ||
| 13 | * under the terms of the GNU General Public License as published by the | ||
| 14 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 15 | * option) any later version. | ||
| 16 | */ | ||
| 17 | #ifndef _IXDP2X00_H_ | ||
| 18 | #define _IXDP2X00_H_ | ||
| 19 | |||
| 20 | /* | ||
| 21 | * On board CPLD memory map | ||
| 22 | */ | ||
| 23 | #define IXDP2X00_PHYS_CPLD_BASE 0xc7000000 | ||
| 24 | #define IXDP2X00_VIRT_CPLD_BASE 0xfe000000 | ||
| 25 | #define IXDP2X00_CPLD_SIZE 0x00100000 | ||
| 26 | |||
| 27 | |||
| 28 | #define IXDP2X00_CPLD_REG(x) \ | ||
| 29 | (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x) | ||
| 30 | |||
| 31 | /* | ||
| 32 | * IXDP2400 CPLD registers | ||
| 33 | */ | ||
| 34 | #define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0) | ||
| 35 | #define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4) | ||
| 36 | #define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8) | ||
| 37 | #define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc) | ||
| 38 | #define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10) | ||
| 39 | #define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14) | ||
| 40 | #define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18) | ||
| 41 | #define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * IXDP2800 CPLD registers | ||
| 45 | */ | ||
| 46 | #define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0) | ||
| 47 | #define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140) | ||
| 48 | |||
| 49 | |||
| 50 | #define IXDP2X00_GPIO_I2C_ENABLE 0x02 | ||
| 51 | #define IXDP2X00_GPIO_SCL 0x07 | ||
| 52 | #define IXDP2X00_GPIO_SDA 0x06 | ||
| 53 | |||
| 54 | /* | ||
| 55 | * PCI devfns for on-board devices. We need these to be able to | ||
| 56 | * properly translate IRQs and for device removal. | ||
| 57 | */ | ||
| 58 | #define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */ | ||
| 59 | #define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */ | ||
| 60 | #define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */ | ||
| 61 | #define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */ | ||
| 62 | |||
| 63 | #define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */ | ||
| 64 | #define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */ | ||
| 65 | #define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */ | ||
| 66 | |||
| 67 | #define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */ | ||
| 68 | #define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */ | ||
| 69 | #define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */ | ||
| 70 | #define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */ | ||
| 71 | #define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */ | ||
| 72 | |||
| 73 | #ifndef __ASSEMBLY__ | ||
| 74 | /* | ||
| 75 | * The master NPU is always PCI master. | ||
| 76 | */ | ||
| 77 | static inline unsigned int ixdp2x00_master_npu(void) | ||
| 78 | { | ||
| 79 | return !!ixp2000_is_pcimaster(); | ||
| 80 | } | ||
| 81 | |||
| 82 | /* | ||
| 83 | * Helper functions used by ixdp2400 and ixdp2800 specific code | ||
| 84 | */ | ||
| 85 | void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long); | ||
| 86 | void ixdp2x00_slave_pci_postinit(void); | ||
| 87 | void ixdp2x00_init_machine(void); | ||
| 88 | void ixdp2x00_map_io(void); | ||
| 89 | |||
| 90 | #endif | ||
| 91 | |||
| 92 | #endif /*_IXDP2X00_H_ */ | ||
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h deleted file mode 100644 index c6d51426e98f..000000000000 --- a/include/asm-arm/arch-ixp2000/ixdp2x01.h +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp2000/ixdp2x01.h | ||
| 3 | * | ||
| 4 | * Platform definitions for IXDP2X01 && IXDP2801 systems | ||
| 5 | * | ||
| 6 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
| 7 | * | ||
| 8 | * Copyright 2004 (c) MontaVista Software, Inc. | ||
| 9 | * | ||
| 10 | * Based on original code Copyright (c) 2002-2003 Intel Corporation | ||
| 11 | * | ||
| 12 | * This file is licensed under the terms of the GNU General Public | ||
| 13 | * License version 2. This program is licensed "as is" without any | ||
| 14 | * warranty of any kind, whether express or implied. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __IXDP2X01_H__ | ||
| 18 | #define __IXDP2X01_H__ | ||
| 19 | |||
| 20 | #define IXDP2X01_PHYS_CPLD_BASE 0xc6024000 | ||
| 21 | #define IXDP2X01_VIRT_CPLD_BASE 0xfe000000 | ||
| 22 | #define IXDP2X01_CPLD_REGION_SIZE 0x00100000 | ||
| 23 | |||
| 24 | #define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg) | ||
| 25 | #define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg) | ||
| 26 | |||
| 27 | #define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40) | ||
| 28 | #define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40) | ||
| 29 | |||
| 30 | #define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60) | ||
| 31 | #define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60) | ||
| 32 | |||
| 33 | #define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80) | ||
| 34 | #define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16) | ||
| 35 | |||
| 36 | #define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00) | ||
| 37 | #define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08) | ||
| 38 | #define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C) | ||
| 39 | #define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10) | ||
| 40 | #define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG | ||
| 41 | #define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14) | ||
| 42 | |||
| 43 | #define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20) | ||
| 44 | |||
| 45 | #define IXDP2X01_CPLD_FLASH_INTERN 0x8000 | ||
| 46 | #define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF | ||
| 47 | #define IXDP2X01_FLASH_WINDOW_BITS 25 | ||
| 48 | #define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS) | ||
| 49 | #define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1) | ||
| 50 | |||
| 51 | #define IXDP2X01_UART_CLK 1843200 | ||
| 52 | |||
| 53 | #define IXDP2X01_GPIO_I2C_ENABLE 0x02 | ||
| 54 | #define IXDP2X01_GPIO_SCL 0x07 | ||
| 55 | #define IXDP2X01_GPIO_SDA 0x06 | ||
| 56 | |||
| 57 | #endif /* __IXDP2x01_H__ */ | ||
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h deleted file mode 100644 index ccae4bec92c5..000000000000 --- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h +++ /dev/null | |||
| @@ -1,457 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp2000/ixp2000-regs.h | ||
| 3 | * | ||
| 4 | * Chipset register definitions for IXP2400/2800 based systems. | ||
| 5 | * | ||
| 6 | * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> | ||
| 7 | * | ||
| 8 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | ||
| 9 | * | ||
| 10 | * Copyright (C) 2002 Intel Corp. | ||
| 11 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify it | ||
| 14 | * under the terms of the GNU General Public License as published by the | ||
| 15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 16 | * option) any later version. | ||
| 17 | */ | ||
| 18 | #ifndef _IXP2000_REGS_H_ | ||
| 19 | #define _IXP2000_REGS_H_ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * IXP2000 linux memory map: | ||
| 23 | * | ||
| 24 | * virt phys size | ||
| 25 | * fb000000 db000000 16M PCI CFG1 | ||
| 26 | * fc000000 da000000 16M PCI CFG0 | ||
| 27 | * fd000000 d8000000 16M PCI I/O | ||
| 28 | * fe[0-7]00000 8M per-platform mappings | ||
| 29 | * fe900000 80000000 1M SRAM #0 (first MB) | ||
| 30 | * fea00000 cb400000 1M SCRATCH ring get/put | ||
| 31 | * feb00000 c8000000 1M MSF | ||
| 32 | * fec00000 df000000 1M PCI CSRs | ||
| 33 | * fed00000 de000000 1M PCI CREG | ||
| 34 | * fee00000 d6000000 1M INTCTL | ||
| 35 | * fef00000 c0000000 1M CAP | ||
| 36 | */ | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Static I/O regions. | ||
| 40 | * | ||
| 41 | * Most of the registers are clumped in 4K regions spread throughout | ||
| 42 | * the 0xc0000000 -> 0xc0100000 address range, but we just map in | ||
| 43 | * the whole range using a single 1 MB section instead of small | ||
| 44 | * 4K pages. This has two advantages for us: | ||
| 45 | * | ||
| 46 | * 1) We use only one TLB entry for large number of on-chip I/O devices. | ||
| 47 | * | ||
| 48 | * 2) We can easily set the Section attributes to XCB=101 on the IXP2400 | ||
| 49 | * as required per erratum #66. We accomplish this by using a | ||
| 50 | * new MT_IXP2000_DEVICE memory type with the bits set as required. | ||
| 51 | * | ||
| 52 | * CAP stands for CSR Access Proxy. | ||
| 53 | * | ||
| 54 | * If you change the virtual address of this mapping, please propagate | ||
| 55 | * the change to arch/arm/kernel/debug.S, which hardcodes the virtual | ||
| 56 | * address of the UART located in this region. | ||
| 57 | */ | ||
| 58 | |||
| 59 | #define IXP2000_CAP_PHYS_BASE 0xc0000000 | ||
| 60 | #define IXP2000_CAP_VIRT_BASE 0xfef00000 | ||
| 61 | #define IXP2000_CAP_SIZE 0x00100000 | ||
| 62 | |||
| 63 | /* | ||
| 64 | * Addresses for specific on-chip peripherals. | ||
| 65 | */ | ||
| 66 | #define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000 | ||
| 67 | #define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000 | ||
| 68 | #define IXP2000_UART_PHYS_BASE 0xc0030000 | ||
| 69 | #define IXP2000_UART_VIRT_BASE 0xfef30000 | ||
| 70 | #define IXP2000_TIMER_VIRT_BASE 0xfef20000 | ||
| 71 | #define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000 | ||
| 72 | #define IXP2000_GPIO_VIRT_BASE 0xfef10000 | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual | ||
| 76 | * addresses of the INTCTL and PCI_CSR mappings are hardcoded in | ||
| 77 | * entry-macro.S, so if you ever change these please propagate | ||
| 78 | * the change. | ||
| 79 | */ | ||
| 80 | #define IXP2000_INTCTL_PHYS_BASE 0xd6000000 | ||
| 81 | #define IXP2000_INTCTL_VIRT_BASE 0xfee00000 | ||
| 82 | #define IXP2000_INTCTL_SIZE 0x00100000 | ||
| 83 | |||
| 84 | #define IXP2000_PCI_CREG_PHYS_BASE 0xde000000 | ||
| 85 | #define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000 | ||
| 86 | #define IXP2000_PCI_CREG_SIZE 0x00100000 | ||
| 87 | |||
| 88 | #define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000 | ||
| 89 | #define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 | ||
| 90 | #define IXP2000_PCI_CSR_SIZE 0x00100000 | ||
| 91 | |||
| 92 | #define IXP2000_MSF_PHYS_BASE 0xc8000000 | ||
| 93 | #define IXP2000_MSF_VIRT_BASE 0xfeb00000 | ||
| 94 | #define IXP2000_MSF_SIZE 0x00100000 | ||
| 95 | |||
| 96 | #define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000 | ||
| 97 | #define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000 | ||
| 98 | #define IXP2000_SCRATCH_RING_SIZE 0x00100000 | ||
| 99 | |||
| 100 | #define IXP2000_SRAM0_PHYS_BASE 0x80000000 | ||
| 101 | #define IXP2000_SRAM0_VIRT_BASE 0xfe900000 | ||
| 102 | #define IXP2000_SRAM0_SIZE 0x00100000 | ||
| 103 | |||
| 104 | #define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 | ||
| 105 | #define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 | ||
| 106 | #define IXP2000_PCI_IO_SIZE 0x01000000 | ||
| 107 | |||
| 108 | #define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000 | ||
| 109 | #define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000 | ||
| 110 | #define IXP2000_PCI_CFG0_SIZE 0x01000000 | ||
| 111 | |||
| 112 | #define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000 | ||
| 113 | #define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000 | ||
| 114 | #define IXP2000_PCI_CFG1_SIZE 0x01000000 | ||
| 115 | |||
| 116 | /* | ||
| 117 | * Timers | ||
| 118 | */ | ||
| 119 | #define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x))) | ||
| 120 | /* Timer control */ | ||
| 121 | #define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00) | ||
| 122 | #define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04) | ||
| 123 | #define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08) | ||
| 124 | #define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c) | ||
| 125 | /* Store initial value */ | ||
| 126 | #define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10) | ||
| 127 | #define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14) | ||
| 128 | #define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18) | ||
| 129 | #define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c) | ||
| 130 | /* Read current value */ | ||
| 131 | #define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20) | ||
| 132 | #define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24) | ||
| 133 | #define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28) | ||
| 134 | #define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c) | ||
| 135 | /* Clear associated timer interrupt */ | ||
| 136 | #define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30) | ||
| 137 | #define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34) | ||
| 138 | #define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38) | ||
| 139 | #define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c) | ||
| 140 | /* Timer watchdog enable for T4 */ | ||
| 141 | #define IXP2000_TWDE IXP2000_TIMER_REG(0x40) | ||
| 142 | |||
| 143 | #define WDT_ENABLE 0x00000001 | ||
| 144 | #define TIMER_DIVIDER_256 0x00000008 | ||
| 145 | #define TIMER_ENABLE 0x00000080 | ||
| 146 | #define IRQ_MASK_TIMER1 (1 << 4) | ||
| 147 | |||
| 148 | /* | ||
| 149 | * Interrupt controller registers | ||
| 150 | */ | ||
| 151 | #define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x)) | ||
| 152 | #define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08) | ||
| 153 | #define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10) | ||
| 154 | #define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10) | ||
| 155 | #define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18) | ||
| 156 | #define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14) | ||
| 157 | #define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24) | ||
| 158 | #define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c) | ||
| 159 | #define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30) | ||
| 160 | #define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34) | ||
| 161 | #define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60) | ||
| 162 | #define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64) | ||
| 163 | #define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68) | ||
| 164 | #define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c) | ||
| 165 | #define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80) | ||
| 166 | #define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84) | ||
| 167 | #define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88) | ||
| 168 | #define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c) | ||
| 169 | #define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0) | ||
| 170 | #define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4) | ||
| 171 | #define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8) | ||
| 172 | #define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec) | ||
| 173 | #define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100) | ||
| 174 | #define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104) | ||
| 175 | #define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108) | ||
| 176 | #define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c) | ||
| 177 | #define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160) | ||
| 178 | #define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164) | ||
| 179 | #define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168) | ||
| 180 | #define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c) | ||
| 181 | #define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180) | ||
| 182 | #define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184) | ||
| 183 | #define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188) | ||
| 184 | #define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c) | ||
| 185 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0) | ||
| 186 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4) | ||
| 187 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8) | ||
| 188 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec) | ||
| 189 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200) | ||
| 190 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204) | ||
| 191 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208) | ||
| 192 | #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c) | ||
| 193 | |||
| 194 | /* | ||
| 195 | * Mask of valid IRQs in the 32-bit IRQ register. We use | ||
| 196 | * this to mark certain IRQs as being invalid. | ||
| 197 | */ | ||
| 198 | #define IXP2000_VALID_IRQ_MASK 0x0f0fffff | ||
| 199 | |||
| 200 | /* | ||
| 201 | * PCI config register access from core | ||
| 202 | */ | ||
| 203 | #define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x)) | ||
| 204 | #define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04) | ||
| 205 | #define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10) | ||
| 206 | #define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14) | ||
| 207 | #define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18) | ||
| 208 | |||
| 209 | /* | ||
| 210 | * PCI CSRs | ||
| 211 | */ | ||
| 212 | #define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x)) | ||
| 213 | |||
| 214 | /* | ||
| 215 | * PCI outbound interrupts | ||
| 216 | */ | ||
| 217 | #define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30) | ||
| 218 | #define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34) | ||
| 219 | /* | ||
| 220 | * PCI communications | ||
| 221 | */ | ||
| 222 | #define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50) | ||
| 223 | #define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54) | ||
| 224 | #define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58) | ||
| 225 | #define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C) | ||
| 226 | #define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60) | ||
| 227 | #define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64) | ||
| 228 | #define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70) | ||
| 229 | #define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74) | ||
| 230 | |||
| 231 | /* | ||
| 232 | * DMA engines | ||
| 233 | */ | ||
| 234 | #define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80) | ||
| 235 | #define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84) | ||
| 236 | #define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88) | ||
| 237 | #define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C) | ||
| 238 | #define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90) | ||
| 239 | #define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94) | ||
| 240 | #define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0) | ||
| 241 | #define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4) | ||
| 242 | #define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8) | ||
| 243 | #define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC) | ||
| 244 | #define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0) | ||
| 245 | #define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4) | ||
| 246 | #define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0) | ||
| 247 | #define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4) | ||
| 248 | #define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8) | ||
| 249 | #define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC) | ||
| 250 | #define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0) | ||
| 251 | #define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4) | ||
| 252 | #define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0) | ||
| 253 | /* | ||
| 254 | * Size masks for BARs | ||
| 255 | */ | ||
| 256 | #define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC) | ||
| 257 | #define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100) | ||
| 258 | /* | ||
| 259 | * Control and uEngine related | ||
| 260 | */ | ||
| 261 | #define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C) | ||
| 262 | #define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140) | ||
| 263 | #define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148) | ||
| 264 | #define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C) | ||
| 265 | #define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150) | ||
| 266 | #define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154) | ||
| 267 | /* | ||
| 268 | * Inbound PCI interrupt control | ||
| 269 | */ | ||
| 270 | #define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158) | ||
| 271 | #define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C) | ||
| 272 | |||
| 273 | #define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */ | ||
| 274 | #define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */ | ||
| 275 | #define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ | ||
| 276 | |||
| 277 | /* These are from the IRQ register in the PCI ISR register */ | ||
| 278 | #define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */ | ||
| 279 | #define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */ | ||
| 280 | #define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */ | ||
| 281 | #define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */ | ||
| 282 | #define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */ | ||
| 283 | |||
| 284 | #define IXP2000_PCI_RST_REL (1 << 2) | ||
| 285 | #define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF) | ||
| 286 | #define CFG_PCI_BOOT_HOST (1 << 2) | ||
| 287 | #define CFG_BOOT_PROM (1 << 1) | ||
| 288 | |||
| 289 | /* | ||
| 290 | * SlowPort CSRs | ||
| 291 | * | ||
| 292 | * The slowport is used to access things like flash, SONET framer control | ||
| 293 | * ports, slave microprocessors, CPLDs, and others of chip memory mapped | ||
| 294 | * peripherals. | ||
| 295 | */ | ||
| 296 | #define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x)) | ||
| 297 | |||
| 298 | #define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00) | ||
| 299 | #define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04) | ||
| 300 | #define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08) | ||
| 301 | #define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c) | ||
| 302 | #define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10) | ||
| 303 | #define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14) | ||
| 304 | #define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18) | ||
| 305 | #define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C) | ||
| 306 | #define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20) | ||
| 307 | #define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24) | ||
| 308 | #define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28) | ||
| 309 | |||
| 310 | /* | ||
| 311 | * CCR values. | ||
| 312 | * The CCR configures the clock division for the slowport interface. | ||
| 313 | */ | ||
| 314 | #define SLOWPORT_CCR_DIV_1 0x00 | ||
| 315 | #define SLOWPORT_CCR_DIV_2 0x01 | ||
| 316 | #define SLOWPORT_CCR_DIV_4 0x02 | ||
| 317 | #define SLOWPORT_CCR_DIV_6 0x03 | ||
| 318 | #define SLOWPORT_CCR_DIV_8 0x04 | ||
| 319 | #define SLOWPORT_CCR_DIV_10 0x05 | ||
| 320 | #define SLOWPORT_CCR_DIV_12 0x06 | ||
| 321 | #define SLOWPORT_CCR_DIV_14 0x07 | ||
| 322 | #define SLOWPORT_CCR_DIV_16 0x08 | ||
| 323 | #define SLOWPORT_CCR_DIV_18 0x09 | ||
| 324 | #define SLOWPORT_CCR_DIV_20 0x0a | ||
| 325 | #define SLOWPORT_CCR_DIV_22 0x0b | ||
| 326 | #define SLOWPORT_CCR_DIV_24 0x0c | ||
| 327 | #define SLOWPORT_CCR_DIV_26 0x0d | ||
| 328 | #define SLOWPORT_CCR_DIV_28 0x0e | ||
| 329 | #define SLOWPORT_CCR_DIV_30 0x0f | ||
| 330 | |||
| 331 | /* | ||
| 332 | * PCR values. PCR configure the mode of the interface. | ||
| 333 | */ | ||
| 334 | #define SLOWPORT_MODE_FLASH 0x00 | ||
| 335 | #define SLOWPORT_MODE_LUCENT 0x01 | ||
| 336 | #define SLOWPORT_MODE_PMC_SIERRA 0x02 | ||
| 337 | #define SLOWPORT_MODE_INTEL_UP 0x03 | ||
| 338 | #define SLOWPORT_MODE_MOTOROLA_UP 0x04 | ||
| 339 | |||
| 340 | /* | ||
| 341 | * ADC values. Defines data and address bus widths. | ||
| 342 | */ | ||
| 343 | #define SLOWPORT_ADDR_WIDTH_8 0x00 | ||
| 344 | #define SLOWPORT_ADDR_WIDTH_16 0x01 | ||
| 345 | #define SLOWPORT_ADDR_WIDTH_24 0x02 | ||
| 346 | #define SLOWPORT_ADDR_WIDTH_32 0x03 | ||
| 347 | #define SLOWPORT_DATA_WIDTH_8 0x00 | ||
| 348 | #define SLOWPORT_DATA_WIDTH_16 0x10 | ||
| 349 | #define SLOWPORT_DATA_WIDTH_24 0x20 | ||
| 350 | #define SLOWPORT_DATA_WIDTH_32 0x30 | ||
| 351 | |||
| 352 | /* | ||
| 353 | * Masks and shifts for various fields in the WTC and RTC registers. | ||
| 354 | */ | ||
| 355 | #define SLOWPORT_WRTC_MASK_HD 0x0003 | ||
| 356 | #define SLOWPORT_WRTC_MASK_PW 0x003c | ||
| 357 | #define SLOWPORT_WRTC_MASK_SU 0x03c0 | ||
| 358 | |||
| 359 | #define SLOWPORT_WRTC_SHIFT_HD 0x00 | ||
| 360 | #define SLOWPORT_WRTC_SHIFT_SU 0x02 | ||
| 361 | #define SLOWPORT_WRTC_SHFIT_PW 0x06 | ||
| 362 | |||
| 363 | |||
| 364 | /* | ||
| 365 | * GPIO registers & GPIO interface. | ||
| 366 | */ | ||
| 367 | #define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x))) | ||
| 368 | #define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00) | ||
| 369 | #define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04) | ||
| 370 | #define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08) | ||
| 371 | #define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c) | ||
| 372 | #define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10) | ||
| 373 | #define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14) | ||
| 374 | #define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18) | ||
| 375 | #define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c) | ||
| 376 | #define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20) | ||
| 377 | #define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24) | ||
| 378 | #define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28) | ||
| 379 | #define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c) | ||
| 380 | #define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30) | ||
| 381 | #define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34) | ||
| 382 | #define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38) | ||
| 383 | #define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c) | ||
| 384 | #define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40) | ||
| 385 | |||
| 386 | /* | ||
| 387 | * "Global" registers...whatever that's supposed to mean. | ||
| 388 | */ | ||
| 389 | #define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00) | ||
| 390 | #define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x)) | ||
| 391 | |||
| 392 | #define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000 | ||
| 393 | #define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000 | ||
| 394 | #define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00 | ||
| 395 | #define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200 | ||
| 396 | #define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100 | ||
| 397 | #define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000 | ||
| 398 | #define IXP2000_MAJ_REV_MASK 0x000000F0 | ||
| 399 | #define IXP2000_MIN_REV_MASK 0x0000000F | ||
| 400 | #define IXP2000_PROD_ID_MASK 0xFFFFFFFF | ||
| 401 | |||
| 402 | #define IXP2000_PRODUCT_ID GLOBAL_REG(0x00) | ||
| 403 | #define IXP2000_MISC_CONTROL GLOBAL_REG(0x04) | ||
| 404 | #define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08) | ||
| 405 | #define IXP2000_RESET0 GLOBAL_REG(0x0c) | ||
| 406 | #define IXP2000_RESET1 GLOBAL_REG(0x10) | ||
| 407 | #define IXP2000_CCR GLOBAL_REG(0x14) | ||
| 408 | #define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18) | ||
| 409 | |||
| 410 | #define RSTALL (1 << 16) | ||
| 411 | #define WDT_RESET_ENABLE 0x01000000 | ||
| 412 | |||
| 413 | |||
| 414 | /* | ||
| 415 | * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF | ||
| 416 | * units, but the registers that differ between the two don't overlap, | ||
| 417 | * so we can have one register list for both. | ||
| 418 | */ | ||
| 419 | #define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x))) | ||
| 420 | #define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000) | ||
| 421 | #define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004) | ||
| 422 | #define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008) | ||
| 423 | #define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c) | ||
| 424 | #define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010) | ||
| 425 | #define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014) | ||
| 426 | #define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018) | ||
| 427 | #define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024) | ||
| 428 | #define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028) | ||
| 429 | #define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c) | ||
| 430 | #define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040) | ||
| 431 | #define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044) | ||
| 432 | #define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048) | ||
| 433 | #define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048) | ||
| 434 | #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050) | ||
| 435 | #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054) | ||
| 436 | #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058) | ||
| 437 | #define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060) | ||
| 438 | #define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064) | ||
| 439 | #define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068) | ||
| 440 | #define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070) | ||
| 441 | #define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070) | ||
| 442 | #define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080) | ||
| 443 | #define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084) | ||
| 444 | #define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088) | ||
| 445 | #define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c) | ||
| 446 | #define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090) | ||
| 447 | #define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094) | ||
| 448 | #define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098) | ||
| 449 | #define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c) | ||
| 450 | #define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0) | ||
| 451 | #define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4) | ||
| 452 | #define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8) | ||
| 453 | #define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000) | ||
| 454 | #define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400) | ||
| 455 | |||
| 456 | |||
| 457 | #endif /* _IXP2000_H_ */ | ||
diff --git a/include/asm-arm/arch-ixp2000/memory.h b/include/asm-arm/arch-ixp2000/memory.h deleted file mode 100644 index 21e1de51e3f6..000000000000 --- a/include/asm-arm/arch-ixp2000/memory.h +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp2000/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2002 Intel Corp. | ||
| 5 | * Copyright (c) 2003-2004 MontaVista Software, Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 14 | #define __ASM_ARCH_MEMORY_H | ||
| 15 | |||
| 16 | #define PHYS_OFFSET UL(0x00000000) | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Virtual view <-> DMA view memory address translations | ||
| 20 | * virt_to_bus: Used to translate the virtual address to an | ||
| 21 | * address suitable to be passed to set_dma_addr | ||
| 22 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 23 | * to an address that the kernel can use. | ||
| 24 | */ | ||
| 25 | #include <asm/arch/ixp2000-regs.h> | ||
| 26 | |||
| 27 | #define __virt_to_bus(v) \ | ||
| 28 | (((__virt_to_phys(v) - 0x0) + (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0))) | ||
| 29 | |||
| 30 | #define __bus_to_virt(b) \ | ||
| 31 | __phys_to_virt((((b - (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)) + 0x0))) | ||
| 32 | |||
| 33 | #endif | ||
| 34 | |||
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h deleted file mode 100644 index a66317ab2071..000000000000 --- a/include/asm-arm/arch-ixp2000/platform.h +++ /dev/null | |||
| @@ -1,152 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp2000/platform.h | ||
| 3 | * | ||
| 4 | * Various bits of code used by platform-level code. | ||
| 5 | * | ||
| 6 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
| 7 | * | ||
| 8 | * Copyright 2004 (c) MontaVista Software, Inc. | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | |||
| 16 | #ifndef __ASSEMBLY__ | ||
| 17 | |||
| 18 | static inline unsigned long ixp2000_reg_read(volatile void *reg) | ||
| 19 | { | ||
| 20 | return *((volatile unsigned long *)reg); | ||
| 21 | } | ||
| 22 | |||
| 23 | static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) | ||
| 24 | { | ||
| 25 | *((volatile unsigned long *)reg) = val; | ||
| 26 | } | ||
| 27 | |||
| 28 | /* | ||
| 29 | * On the IXP2400, we can't use XCB=000 due to chip bugs. We use | ||
| 30 | * XCB=101 instead, but that makes all I/O accesses bufferable. This | ||
| 31 | * is not a problem in general, but we do have to be slightly more | ||
| 32 | * careful because I/O writes are no longer automatically flushed out | ||
| 33 | * of the write buffer. | ||
| 34 | * | ||
| 35 | * In cases where we want to make sure that a write has been flushed | ||
| 36 | * out of the write buffer before we proceed, for example when masking | ||
| 37 | * a device interrupt before re-enabling IRQs in CPSR, we can use this | ||
| 38 | * function, ixp2000_reg_wrb, which performs a write, a readback, and | ||
| 39 | * issues a dummy instruction dependent on the value of the readback | ||
| 40 | * (mov rX, rX) to make sure that the readback has completed before we | ||
| 41 | * continue. | ||
| 42 | */ | ||
| 43 | static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) | ||
| 44 | { | ||
| 45 | unsigned long dummy; | ||
| 46 | |||
| 47 | *((volatile unsigned long *)reg) = val; | ||
| 48 | |||
| 49 | dummy = *((volatile unsigned long *)reg); | ||
| 50 | __asm__ __volatile__("mov %0, %0" : "+r" (dummy)); | ||
| 51 | } | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Boards may multiplex different devices on the 2nd channel of | ||
| 55 | * the slowport interface that each need different configuration | ||
| 56 | * settings. For example, the IXDP2400 uses channel 2 on the interface | ||
| 57 | * to access the CPLD, the switch fabric card, and the media card. Each | ||
| 58 | * one needs a different mode so drivers must save/restore the mode | ||
| 59 | * before and after each operation. | ||
| 60 | * | ||
| 61 | * acquire_slowport(&your_config); | ||
| 62 | * ... | ||
| 63 | * do slowport operations | ||
| 64 | * ... | ||
| 65 | * release_slowport(); | ||
| 66 | * | ||
| 67 | * Note that while you have the slowport, you are holding a spinlock, | ||
| 68 | * so your code should be written as if you explicitly acquired a lock. | ||
| 69 | * | ||
| 70 | * The configuration only affects device 2 on the slowport, so the | ||
| 71 | * MTD map driver does not acquire/release the slowport. | ||
| 72 | */ | ||
| 73 | struct slowport_cfg { | ||
| 74 | unsigned long CCR; /* Clock divide */ | ||
| 75 | unsigned long WTC; /* Write Timing Control */ | ||
| 76 | unsigned long RTC; /* Read Timing Control */ | ||
| 77 | unsigned long PCR; /* Protocol Control Register */ | ||
| 78 | unsigned long ADC; /* Address/Data Width Control */ | ||
| 79 | }; | ||
| 80 | |||
| 81 | |||
| 82 | void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *); | ||
| 83 | void ixp2000_release_slowport(struct slowport_cfg *); | ||
| 84 | |||
| 85 | /* | ||
| 86 | * IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires | ||
| 87 | * tweaking of addresses in the MTD driver. | ||
| 88 | */ | ||
| 89 | static inline unsigned ixp2000_has_broken_slowport(void) | ||
| 90 | { | ||
| 91 | unsigned long id = *IXP2000_PRODUCT_ID; | ||
| 92 | unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK | | ||
| 93 | IXP2000_MIN_PROD_TYPE_MASK); | ||
| 94 | return (((id_prod == | ||
| 95 | /* fixed in IXP2400-B0 */ | ||
| 96 | (IXP2000_MAJ_PROD_TYPE_IXP2000 | | ||
| 97 | IXP2000_MIN_PROD_TYPE_IXP2400)) && | ||
| 98 | ((id & IXP2000_MAJ_REV_MASK) == 0)) || | ||
| 99 | ((id_prod == | ||
| 100 | /* fixed in IXP2800-B0 */ | ||
| 101 | (IXP2000_MAJ_PROD_TYPE_IXP2000 | | ||
| 102 | IXP2000_MIN_PROD_TYPE_IXP2800)) && | ||
| 103 | ((id & IXP2000_MAJ_REV_MASK) == 0)) || | ||
| 104 | ((id_prod == | ||
| 105 | /* fixed in IXP2850-B0 */ | ||
| 106 | (IXP2000_MAJ_PROD_TYPE_IXP2000 | | ||
| 107 | IXP2000_MIN_PROD_TYPE_IXP2850)) && | ||
| 108 | ((id & IXP2000_MAJ_REV_MASK) == 0))); | ||
| 109 | } | ||
| 110 | |||
| 111 | static inline unsigned int ixp2000_has_flash(void) | ||
| 112 | { | ||
| 113 | return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM)); | ||
| 114 | } | ||
| 115 | |||
| 116 | static inline unsigned int ixp2000_is_pcimaster(void) | ||
| 117 | { | ||
| 118 | return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST)); | ||
| 119 | } | ||
| 120 | |||
| 121 | void ixp2000_map_io(void); | ||
| 122 | void ixp2000_uart_init(void); | ||
| 123 | void ixp2000_init_irq(void); | ||
| 124 | void ixp2000_init_time(unsigned long); | ||
| 125 | unsigned long ixp2000_gettimeoffset(void); | ||
| 126 | |||
| 127 | struct pci_sys_data; | ||
| 128 | |||
| 129 | u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where); | ||
| 130 | void ixp2000_pci_preinit(void); | ||
| 131 | int ixp2000_pci_setup(int, struct pci_sys_data*); | ||
| 132 | struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*); | ||
| 133 | int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *); | ||
| 134 | int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32); | ||
| 135 | |||
| 136 | /* | ||
| 137 | * Several of the IXP2000 systems have banked flash so we need to extend the | ||
| 138 | * flash_platform_data structure with some private pointers | ||
| 139 | */ | ||
| 140 | struct ixp2000_flash_data { | ||
| 141 | struct flash_platform_data *platform_data; | ||
| 142 | int nr_banks; | ||
| 143 | unsigned long (*bank_setup)(unsigned long); | ||
| 144 | }; | ||
| 145 | |||
| 146 | struct ixp2000_i2c_pins { | ||
| 147 | unsigned long sda_pin; | ||
| 148 | unsigned long scl_pin; | ||
| 149 | }; | ||
| 150 | |||
| 151 | |||
| 152 | #endif /* !__ASSEMBLY__ */ | ||
diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h deleted file mode 100644 index 8731dd36e452..000000000000 --- a/include/asm-arm/arch-ixp2000/system.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp2000/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002 Intel Corp. | ||
| 5 | * Copyricht (C) 2003-2005 MontaVista Software, Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <asm/arch/hardware.h> | ||
| 13 | #include <asm/mach-types.h> | ||
| 14 | |||
| 15 | static inline void arch_idle(void) | ||
| 16 | { | ||
| 17 | cpu_do_idle(); | ||
| 18 | } | ||
| 19 | |||
| 20 | static inline void arch_reset(char mode) | ||
| 21 | { | ||
| 22 | local_irq_disable(); | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Reset flash banking register so that we are pointing at | ||
| 26 | * RedBoot bank. | ||
| 27 | */ | ||
| 28 | if (machine_is_ixdp2401()) { | ||
| 29 | ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, | ||
| 30 | ((0 >> IXDP2X01_FLASH_WINDOW_BITS) | ||
| 31 | | IXDP2X01_CPLD_FLASH_INTERN)); | ||
| 32 | ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff); | ||
| 33 | } | ||
| 34 | |||
| 35 | /* | ||
| 36 | * On IXDP2801 we need to write this magic sequence to the CPLD | ||
| 37 | * to cause a complete reset of the CPU and all external devices | ||
| 38 | * and move the flash bank register back to 0. | ||
| 39 | */ | ||
| 40 | if (machine_is_ixdp2801() || machine_is_ixdp28x5()) { | ||
| 41 | unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG; | ||
| 42 | |||
| 43 | reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF); | ||
| 44 | ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg); | ||
| 45 | ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000); | ||
| 46 | } | ||
| 47 | |||
| 48 | ixp2000_reg_wrb(IXP2000_RESET0, RSTALL); | ||
| 49 | } | ||
diff --git a/include/asm-arm/arch-ixp2000/timex.h b/include/asm-arm/arch-ixp2000/timex.h deleted file mode 100644 index b78a183d4698..000000000000 --- a/include/asm-arm/arch-ixp2000/timex.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp2000/timex.h | ||
| 3 | * | ||
| 4 | * IXP2000 architecture timex specifications | ||
| 5 | */ | ||
| 6 | |||
| 7 | |||
| 8 | /* | ||
| 9 | * Default clock is 50MHz APB, but platform code can override this | ||
| 10 | */ | ||
| 11 | #define CLOCK_TICK_RATE 50000000 | ||
| 12 | |||
| 13 | |||
diff --git a/include/asm-arm/arch-ixp2000/uncompress.h b/include/asm-arm/arch-ixp2000/uncompress.h deleted file mode 100644 index f66b408f363e..000000000000 --- a/include/asm-arm/arch-ixp2000/uncompress.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp2000/uncompress.h | ||
| 3 | * | ||
| 4 | * | ||
| 5 | * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> | ||
| 6 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | ||
| 7 | * | ||
| 8 | * Copyright 2002 Intel Corp. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/serial_reg.h> | ||
| 18 | |||
| 19 | #define UART_BASE 0xc0030000 | ||
| 20 | |||
| 21 | #define PHYS(x) ((volatile unsigned long *)(UART_BASE + x)) | ||
| 22 | |||
| 23 | #define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */ | ||
| 24 | #define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/ | ||
| 25 | #define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/ | ||
| 26 | #define UARTIER PHYS(0x04) /* Interrupt enable reg */ | ||
| 27 | #define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/ | ||
| 28 | #define UARTLCR PHYS(0x0c) /* Control reg */ | ||
| 29 | #define UARTSR PHYS(0x14) /* Status reg */ | ||
| 30 | |||
| 31 | |||
| 32 | static inline void putc(int c) | ||
| 33 | { | ||
| 34 | int j = 0x1000; | ||
| 35 | |||
| 36 | while (--j && !(*UARTSR & UART_LSR_THRE)) | ||
| 37 | barrier(); | ||
| 38 | |||
| 39 | *UARTDR = c; | ||
| 40 | } | ||
| 41 | |||
| 42 | static inline void flush(void) | ||
| 43 | { | ||
| 44 | } | ||
| 45 | |||
| 46 | #define arch_decomp_setup() | ||
| 47 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-ixp2000/vmalloc.h b/include/asm-arm/arch-ixp2000/vmalloc.h deleted file mode 100644 index 275136963a0c..000000000000 --- a/include/asm-arm/arch-ixp2000/vmalloc.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp2000/vmalloc.h | ||
| 3 | * | ||
| 4 | * Author: Naeem Afzal <naeem.m.afzal@intel.com> | ||
| 5 | * | ||
| 6 | * Copyright 2002 Intel Corp. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * Just any arbitrary offset to the start of the vmalloc VM area: the | ||
| 14 | * current 8MB value just means that there will be a 8MB "hole" after the | ||
| 15 | * physical memory until the kernel virtual memory starts. That means that | ||
| 16 | * any out-of-bounds memory accesses will hopefully be caught. | ||
| 17 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced | ||
| 18 | * area for the same reason. ;) | ||
| 19 | */ | ||
| 20 | #define VMALLOC_END 0xfb000000 | ||
diff --git a/include/asm-arm/arch-ixp23xx/debug-macro.S b/include/asm-arm/arch-ixp23xx/debug-macro.S deleted file mode 100644 index 2b25e640247d..000000000000 --- a/include/asm-arm/arch-ixp23xx/debug-macro.S +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/debug-macro.S | ||
| 3 | * | ||
| 4 | * Debugging macro include header | ||
| 5 | * | ||
| 6 | * Copyright (C) 1994-1999 Russell King | ||
| 7 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | #include <asm/arch/ixp23xx.h> | ||
| 14 | |||
| 15 | .macro addruart,rx | ||
| 16 | mrc p15, 0, \rx, c1, c0 | ||
| 17 | tst \rx, #1 @ mmu enabled? | ||
| 18 | ldreq \rx, =IXP23XX_PERIPHERAL_PHYS @ physical | ||
| 19 | ldrne \rx, =IXP23XX_PERIPHERAL_VIRT @ virtual | ||
| 20 | #ifdef __ARMEB__ | ||
| 21 | orr \rx, \rx, #0x00000003 | ||
| 22 | #endif | ||
| 23 | .endm | ||
| 24 | |||
| 25 | #define UART_SHIFT 2 | ||
| 26 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-ixp23xx/dma.h b/include/asm-arm/arch-ixp23xx/dma.h deleted file mode 100644 index 2f4335e3b836..000000000000 --- a/include/asm-arm/arch-ixp23xx/dma.h +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/dma.h | ||
| 3 | */ | ||
diff --git a/include/asm-arm/arch-ixp23xx/entry-macro.S b/include/asm-arm/arch-ixp23xx/entry-macro.S deleted file mode 100644 index ec9dd6fc2d0f..000000000000 --- a/include/asm-arm/arch-ixp23xx/entry-macro.S +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/entry-macro.S | ||
| 3 | */ | ||
| 4 | |||
| 5 | .macro disable_fiq | ||
| 6 | .endm | ||
| 7 | |||
| 8 | .macro get_irqnr_preamble, base, tmp | ||
| 9 | .endm | ||
| 10 | |||
| 11 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 12 | .endm | ||
| 13 | |||
| 14 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 15 | ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET) | ||
| 16 | ldr \irqnr, [\irqnr] @ get interrupt number | ||
| 17 | cmp \irqnr, #0x0 @ spurious interrupt ? | ||
| 18 | movne \irqnr, \irqnr, lsr #2 @ skip unwanted low order bits | ||
| 19 | subne \irqnr, \irqnr, #1 @ convert to 0 based | ||
| 20 | |||
| 21 | #if 0 | ||
| 22 | cmp \irqnr, #IRQ_IXP23XX_PCI_INT_RPH | ||
| 23 | bne 1001f | ||
| 24 | mov \irqnr, #IRQ_IXP23XX_INTA | ||
| 25 | |||
| 26 | ldr \irqnr, =0xf5000030 | ||
| 27 | |||
| 28 | mov \tmp, #(1<<26) | ||
| 29 | tst \irqnr, \tmp | ||
| 30 | movne \irqnr, #IRQ_IXP23XX_INTB | ||
| 31 | |||
| 32 | mov \tmp, #(1<<27) | ||
| 33 | tst \irqnr, \tmp | ||
| 34 | movne \irqnr, #IRQ_IXP23XX_INTA | ||
| 35 | 1001: | ||
| 36 | #endif | ||
| 37 | .endm | ||
diff --git a/include/asm-arm/arch-ixp23xx/hardware.h b/include/asm-arm/arch-ixp23xx/hardware.h deleted file mode 100644 index c0010d21a684..000000000000 --- a/include/asm-arm/arch-ixp23xx/hardware.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002-2004 Intel Corporation. | ||
| 5 | * Copyricht (C) 2005 MontaVista Software, Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * Hardware definitions for IXP23XX based systems | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 15 | #define __ASM_ARCH_HARDWARE_H | ||
| 16 | |||
| 17 | /* PCI IO info */ | ||
| 18 | #define PCIO_BASE IXP23XX_PCI_IO_VIRT | ||
| 19 | #define PCIBIOS_MIN_IO 0x00000000 | ||
| 20 | #define PCIBIOS_MIN_MEM 0xe0000000 | ||
| 21 | |||
| 22 | #include "ixp23xx.h" | ||
| 23 | |||
| 24 | #define pcibios_assign_all_busses() 0 | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Platform helper functions | ||
| 28 | */ | ||
| 29 | #include "platform.h" | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Platform-specific headers | ||
| 33 | */ | ||
| 34 | #include "ixdp2351.h" | ||
| 35 | |||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-ixp23xx/io.h b/include/asm-arm/arch-ixp23xx/io.h deleted file mode 100644 index 66f5bafc315c..000000000000 --- a/include/asm-arm/arch-ixp23xx/io.h +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/io.h | ||
| 3 | * | ||
| 4 | * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> | ||
| 5 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | ||
| 6 | * | ||
| 7 | * Copyright (C) 2003-2005 Intel Corp. | ||
| 8 | * Copyright (C) 2005 MontaVista Software, Inc | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_IO_H | ||
| 16 | #define __ASM_ARCH_IO_H | ||
| 17 | |||
| 18 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 19 | |||
| 20 | #define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT)) | ||
| 21 | #define __mem_pci(a) (a) | ||
| 22 | |||
| 23 | #include <linux/kernel.h> /* For BUG */ | ||
| 24 | |||
| 25 | static inline void __iomem * | ||
| 26 | ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype) | ||
| 27 | { | ||
| 28 | if (addr >= IXP23XX_PCI_MEM_START && | ||
| 29 | addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) { | ||
| 30 | if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) | ||
| 31 | return NULL; | ||
| 32 | |||
| 33 | return (void __iomem *) | ||
| 34 | ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT); | ||
| 35 | } | ||
| 36 | |||
| 37 | return __arm_ioremap(addr, size, mtype); | ||
| 38 | } | ||
| 39 | |||
| 40 | static inline void | ||
| 41 | ixp23xx_iounmap(void __iomem *addr) | ||
| 42 | { | ||
| 43 | if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) && | ||
| 44 | (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE)) | ||
| 45 | return; | ||
| 46 | |||
| 47 | __iounmap(addr); | ||
| 48 | } | ||
| 49 | |||
| 50 | #define __arch_ioremap(a,s,f) ixp23xx_ioremap(a,s,f) | ||
| 51 | #define __arch_iounmap(a) ixp23xx_iounmap(a) | ||
| 52 | |||
| 53 | |||
| 54 | #endif | ||
diff --git a/include/asm-arm/arch-ixp23xx/irqs.h b/include/asm-arm/arch-ixp23xx/irqs.h deleted file mode 100644 index 27c580898958..000000000000 --- a/include/asm-arm/arch-ixp23xx/irqs.h +++ /dev/null | |||
| @@ -1,223 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ definitions for IXP23XX based systems | ||
| 5 | * | ||
| 6 | * Author: Naeem Afzal <naeem.m.afzal@intel.com> | ||
| 7 | * | ||
| 8 | * Copyright (C) 2003-2004 Intel Corporation. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_IRQS_H | ||
| 16 | #define __ASM_ARCH_IRQS_H | ||
| 17 | |||
| 18 | #define NR_IXP23XX_IRQS IRQ_IXP23XX_INTB+1 | ||
| 19 | #define IRQ_IXP23XX_EXTIRQS NR_IXP23XX_IRQS | ||
| 20 | |||
| 21 | |||
| 22 | #define IRQ_IXP23XX_DBG0 0 /* Debug/Execution/MBox */ | ||
| 23 | #define IRQ_IXP23XX_DBG1 1 /* Debug/Execution/MBox */ | ||
| 24 | #define IRQ_IXP23XX_NPE_TRG 2 /* npe_trigger */ | ||
| 25 | #define IRQ_IXP23XX_TIMER1 3 /* Timer[0] */ | ||
| 26 | #define IRQ_IXP23XX_TIMER2 4 /* Timer[1] */ | ||
| 27 | #define IRQ_IXP23XX_TIMESTAMP 5 /* Timer[2], Time-stamp */ | ||
| 28 | #define IRQ_IXP23XX_WDOG 6 /* Time[3], Watchdog Timer */ | ||
| 29 | #define IRQ_IXP23XX_PCI_DBELL 7 /* PCI Doorbell */ | ||
| 30 | #define IRQ_IXP23XX_PCI_DMA1 8 /* PCI DMA Channel 1 */ | ||
| 31 | #define IRQ_IXP23XX_PCI_DMA2 9 /* PCI DMA Channel 2 */ | ||
| 32 | #define IRQ_IXP23XX_PCI_DMA3 10 /* PCI DMA Channel 3 */ | ||
| 33 | #define IRQ_IXP23XX_PCI_INT_RPH 11 /* pcxg_pci_int_rph */ | ||
| 34 | #define IRQ_IXP23XX_CPP_PMU 12 /* xpxg_pm_int_rpl */ | ||
| 35 | #define IRQ_IXP23XX_SWINT0 13 /* S/W Interrupt0 */ | ||
| 36 | #define IRQ_IXP23XX_SWINT1 14 /* S/W Interrupt1 */ | ||
| 37 | #define IRQ_IXP23XX_UART2 15 /* UART1 Interrupt */ | ||
| 38 | #define IRQ_IXP23XX_UART1 16 /* UART0 Interrupt */ | ||
| 39 | #define IRQ_IXP23XX_XSI_PMU_ROLLOVER 17 /* AHB Performance M. Unit counter rollover */ | ||
| 40 | #define IRQ_IXP23XX_XSI_AHB_PM0 18 /* intr_pm_o */ | ||
| 41 | #define IRQ_IXP23XX_XSI_AHB_ECE0 19 /* intr_ece_o */ | ||
| 42 | #define IRQ_IXP23XX_XSI_AHB_GASKET 20 /* gas_intr_o */ | ||
| 43 | #define IRQ_IXP23XX_XSI_CPP 21 /* xsi2cpp_int */ | ||
| 44 | #define IRQ_IXP23XX_CPP_XSI 22 /* cpp2xsi_int */ | ||
| 45 | #define IRQ_IXP23XX_ME_ATTN0 23 /* ME_ATTN */ | ||
| 46 | #define IRQ_IXP23XX_ME_ATTN1 24 /* ME_ATTN */ | ||
| 47 | #define IRQ_IXP23XX_ME_ATTN2 25 /* ME_ATTN */ | ||
| 48 | #define IRQ_IXP23XX_ME_ATTN3 26 /* ME_ATTN */ | ||
| 49 | #define IRQ_IXP23XX_PCI_ERR_RPH 27 /* PCXG_PCI_ERR_RPH */ | ||
| 50 | #define IRQ_IXP23XX_D0XG_ECC_CORR 28 /* D0XG_DRAM_ECC_CORR */ | ||
| 51 | #define IRQ_IXP23XX_D0XG_ECC_UNCORR 29 /* D0XG_DRAM_ECC_UNCORR */ | ||
| 52 | #define IRQ_IXP23XX_SRAM_ERR1 30 /* SRAM1_ERR */ | ||
| 53 | #define IRQ_IXP23XX_SRAM_ERR0 31 /* SRAM0_ERR */ | ||
| 54 | #define IRQ_IXP23XX_MEDIA_ERR 32 /* MEDIA_ERR */ | ||
| 55 | #define IRQ_IXP23XX_STH_DRAM_ECC_MAJ 33 /* STH_DRAM0_ECC_MAJ */ | ||
| 56 | #define IRQ_IXP23XX_GPIO6 34 /* GPIO0 interrupts */ | ||
| 57 | #define IRQ_IXP23XX_GPIO7 35 /* GPIO1 interrupts */ | ||
| 58 | #define IRQ_IXP23XX_GPIO8 36 /* GPIO2 interrupts */ | ||
| 59 | #define IRQ_IXP23XX_GPIO9 37 /* GPIO3 interrupts */ | ||
| 60 | #define IRQ_IXP23XX_GPIO10 38 /* GPIO4 interrupts */ | ||
| 61 | #define IRQ_IXP23XX_GPIO11 39 /* GPIO5 interrupts */ | ||
| 62 | #define IRQ_IXP23XX_GPIO12 40 /* GPIO6 interrupts */ | ||
| 63 | #define IRQ_IXP23XX_GPIO13 41 /* GPIO7 interrupts */ | ||
| 64 | #define IRQ_IXP23XX_GPIO14 42 /* GPIO8 interrupts */ | ||
| 65 | #define IRQ_IXP23XX_GPIO15 43 /* GPIO9 interrupts */ | ||
| 66 | #define IRQ_IXP23XX_SHAC_RING0 44 /* SHAC Ring Full */ | ||
| 67 | #define IRQ_IXP23XX_SHAC_RING1 45 /* SHAC Ring Full */ | ||
| 68 | #define IRQ_IXP23XX_SHAC_RING2 46 /* SHAC Ring Full */ | ||
| 69 | #define IRQ_IXP23XX_SHAC_RING3 47 /* SHAC Ring Full */ | ||
| 70 | #define IRQ_IXP23XX_SHAC_RING4 48 /* SHAC Ring Full */ | ||
| 71 | #define IRQ_IXP23XX_SHAC_RING5 49 /* SHAC Ring Full */ | ||
| 72 | #define IRQ_IXP23XX_SHAC_RING6 50 /* SHAC RING Full */ | ||
| 73 | #define IRQ_IXP23XX_SHAC_RING7 51 /* SHAC Ring Full */ | ||
| 74 | #define IRQ_IXP23XX_SHAC_RING8 52 /* SHAC Ring Full */ | ||
| 75 | #define IRQ_IXP23XX_SHAC_RING9 53 /* SHAC Ring Full */ | ||
| 76 | #define IRQ_IXP23XX_SHAC_RING10 54 /* SHAC Ring Full */ | ||
| 77 | #define IRQ_IXP23XX_SHAC_RING11 55 /* SHAC Ring Full */ | ||
| 78 | #define IRQ_IXP23XX_ME_THREAD_A0_ME0 56 /* ME_THREAD_A */ | ||
| 79 | #define IRQ_IXP23XX_ME_THREAD_A1_ME0 57 /* ME_THREAD_A */ | ||
| 80 | #define IRQ_IXP23XX_ME_THREAD_A2_ME0 58 /* ME_THREAD_A */ | ||
| 81 | #define IRQ_IXP23XX_ME_THREAD_A3_ME0 59 /* ME_THREAD_A */ | ||
| 82 | #define IRQ_IXP23XX_ME_THREAD_A4_ME0 60 /* ME_THREAD_A */ | ||
| 83 | #define IRQ_IXP23XX_ME_THREAD_A5_ME0 61 /* ME_THREAD_A */ | ||
| 84 | #define IRQ_IXP23XX_ME_THREAD_A6_ME0 62 /* ME_THREAD_A */ | ||
| 85 | #define IRQ_IXP23XX_ME_THREAD_A7_ME0 63 /* ME_THREAD_A */ | ||
| 86 | #define IRQ_IXP23XX_ME_THREAD_A8_ME1 64 /* ME_THREAD_A */ | ||
| 87 | #define IRQ_IXP23XX_ME_THREAD_A9_ME1 65 /* ME_THREAD_A */ | ||
| 88 | #define IRQ_IXP23XX_ME_THREAD_A10_ME1 66 /* ME_THREAD_A */ | ||
| 89 | #define IRQ_IXP23XX_ME_THREAD_A11_ME1 67 /* ME_THREAD_A */ | ||
| 90 | #define IRQ_IXP23XX_ME_THREAD_A12_ME1 68 /* ME_THREAD_A */ | ||
| 91 | #define IRQ_IXP23XX_ME_THREAD_A13_ME1 69 /* ME_THREAD_A */ | ||
| 92 | #define IRQ_IXP23XX_ME_THREAD_A14_ME1 70 /* ME_THREAD_A */ | ||
| 93 | #define IRQ_IXP23XX_ME_THREAD_A15_ME1 71 /* ME_THREAD_A */ | ||
| 94 | #define IRQ_IXP23XX_ME_THREAD_A16_ME2 72 /* ME_THREAD_A */ | ||
| 95 | #define IRQ_IXP23XX_ME_THREAD_A17_ME2 73 /* ME_THREAD_A */ | ||
| 96 | #define IRQ_IXP23XX_ME_THREAD_A18_ME2 74 /* ME_THREAD_A */ | ||
| 97 | #define IRQ_IXP23XX_ME_THREAD_A19_ME2 75 /* ME_THREAD_A */ | ||
| 98 | #define IRQ_IXP23XX_ME_THREAD_A20_ME2 76 /* ME_THREAD_A */ | ||
| 99 | #define IRQ_IXP23XX_ME_THREAD_A21_ME2 77 /* ME_THREAD_A */ | ||
| 100 | #define IRQ_IXP23XX_ME_THREAD_A22_ME2 78 /* ME_THREAD_A */ | ||
| 101 | #define IRQ_IXP23XX_ME_THREAD_A23_ME2 79 /* ME_THREAD_A */ | ||
| 102 | #define IRQ_IXP23XX_ME_THREAD_A24_ME3 80 /* ME_THREAD_A */ | ||
| 103 | #define IRQ_IXP23XX_ME_THREAD_A25_ME3 81 /* ME_THREAD_A */ | ||
| 104 | #define IRQ_IXP23XX_ME_THREAD_A26_ME3 82 /* ME_THREAD_A */ | ||
| 105 | #define IRQ_IXP23XX_ME_THREAD_A27_ME3 83 /* ME_THREAD_A */ | ||
| 106 | #define IRQ_IXP23XX_ME_THREAD_A28_ME3 84 /* ME_THREAD_A */ | ||
| 107 | #define IRQ_IXP23XX_ME_THREAD_A29_ME3 85 /* ME_THREAD_A */ | ||
| 108 | #define IRQ_IXP23XX_ME_THREAD_A30_ME3 86 /* ME_THREAD_A */ | ||
| 109 | #define IRQ_IXP23XX_ME_THREAD_A31_ME3 87 /* ME_THREAD_A */ | ||
| 110 | #define IRQ_IXP23XX_ME_THREAD_B0_ME0 88 /* ME_THREAD_B */ | ||
| 111 | #define IRQ_IXP23XX_ME_THREAD_B1_ME0 89 /* ME_THREAD_B */ | ||
| 112 | #define IRQ_IXP23XX_ME_THREAD_B2_ME0 90 /* ME_THREAD_B */ | ||
| 113 | #define IRQ_IXP23XX_ME_THREAD_B3_ME0 91 /* ME_THREAD_B */ | ||
| 114 | #define IRQ_IXP23XX_ME_THREAD_B4_ME0 92 /* ME_THREAD_B */ | ||
| 115 | #define IRQ_IXP23XX_ME_THREAD_B5_ME0 93 /* ME_THREAD_B */ | ||
| 116 | #define IRQ_IXP23XX_ME_THREAD_B6_ME0 94 /* ME_THREAD_B */ | ||
| 117 | #define IRQ_IXP23XX_ME_THREAD_B7_ME0 95 /* ME_THREAD_B */ | ||
| 118 | #define IRQ_IXP23XX_ME_THREAD_B8_ME1 96 /* ME_THREAD_B */ | ||
| 119 | #define IRQ_IXP23XX_ME_THREAD_B9_ME1 97 /* ME_THREAD_B */ | ||
| 120 | #define IRQ_IXP23XX_ME_THREAD_B10_ME1 98 /* ME_THREAD_B */ | ||
| 121 | #define IRQ_IXP23XX_ME_THREAD_B11_ME1 99 /* ME_THREAD_B */ | ||
| 122 | #define IRQ_IXP23XX_ME_THREAD_B12_ME1 100 /* ME_THREAD_B */ | ||
| 123 | #define IRQ_IXP23XX_ME_THREAD_B13_ME1 101 /* ME_THREAD_B */ | ||
| 124 | #define IRQ_IXP23XX_ME_THREAD_B14_ME1 102 /* ME_THREAD_B */ | ||
| 125 | #define IRQ_IXP23XX_ME_THREAD_B15_ME1 103 /* ME_THREAD_B */ | ||
| 126 | #define IRQ_IXP23XX_ME_THREAD_B16_ME2 104 /* ME_THREAD_B */ | ||
| 127 | #define IRQ_IXP23XX_ME_THREAD_B17_ME2 105 /* ME_THREAD_B */ | ||
| 128 | #define IRQ_IXP23XX_ME_THREAD_B18_ME2 106 /* ME_THREAD_B */ | ||
| 129 | #define IRQ_IXP23XX_ME_THREAD_B19_ME2 107 /* ME_THREAD_B */ | ||
| 130 | #define IRQ_IXP23XX_ME_THREAD_B20_ME2 108 /* ME_THREAD_B */ | ||
| 131 | #define IRQ_IXP23XX_ME_THREAD_B21_ME2 109 /* ME_THREAD_B */ | ||
| 132 | #define IRQ_IXP23XX_ME_THREAD_B22_ME2 110 /* ME_THREAD_B */ | ||
| 133 | #define IRQ_IXP23XX_ME_THREAD_B23_ME2 111 /* ME_THREAD_B */ | ||
| 134 | #define IRQ_IXP23XX_ME_THREAD_B24_ME3 112 /* ME_THREAD_B */ | ||
| 135 | #define IRQ_IXP23XX_ME_THREAD_B25_ME3 113 /* ME_THREAD_B */ | ||
| 136 | #define IRQ_IXP23XX_ME_THREAD_B26_ME3 114 /* ME_THREAD_B */ | ||
| 137 | #define IRQ_IXP23XX_ME_THREAD_B27_ME3 115 /* ME_THREAD_B */ | ||
| 138 | #define IRQ_IXP23XX_ME_THREAD_B28_ME3 116 /* ME_THREAD_B */ | ||
| 139 | #define IRQ_IXP23XX_ME_THREAD_B29_ME3 117 /* ME_THREAD_B */ | ||
| 140 | #define IRQ_IXP23XX_ME_THREAD_B30_ME3 118 /* ME_THREAD_B */ | ||
| 141 | #define IRQ_IXP23XX_ME_THREAD_B31_ME3 119 /* ME_THREAD_B */ | ||
| 142 | |||
| 143 | #define NUM_IXP23XX_RAW_IRQS 120 | ||
| 144 | |||
| 145 | #define IRQ_IXP23XX_INTA 120 /* Indirect pcxg_pci_int_rph */ | ||
| 146 | #define IRQ_IXP23XX_INTB 121 /* Indirect pcxg_pci_int_rph */ | ||
| 147 | |||
| 148 | #define NR_IXP23XX_IRQ (IRQ_IXP23XX_INTB + 1) | ||
| 149 | |||
| 150 | /* | ||
| 151 | * We default to 32 per-board IRQs. Increase this number if you need | ||
| 152 | * more, but keep it realistic. | ||
| 153 | */ | ||
| 154 | #define NR_IXP23XX_MACH_IRQS 32 | ||
| 155 | |||
| 156 | #define NR_IRQS (NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS) | ||
| 157 | |||
| 158 | #define IXP23XX_MACH_IRQ(irq) (NR_IXP23XX_IRQ + (irq)) | ||
| 159 | |||
| 160 | |||
| 161 | /* | ||
| 162 | * IXDP2351-specific interrupts | ||
| 163 | */ | ||
| 164 | |||
| 165 | /* | ||
| 166 | * External PCI interrupts signaled through INTB | ||
| 167 | * | ||
| 168 | */ | ||
| 169 | #define IXDP2351_INTB_IRQ_BASE 0 | ||
| 170 | #define IRQ_IXDP2351_INTA_82546 IXP23XX_MACH_IRQ(0) | ||
| 171 | #define IRQ_IXDP2351_INTB_82546 IXP23XX_MACH_IRQ(1) | ||
| 172 | #define IRQ_IXDP2351_SPCI_DB_0 IXP23XX_MACH_IRQ(2) | ||
| 173 | #define IRQ_IXDP2351_SPCI_DB_1 IXP23XX_MACH_IRQ(3) | ||
| 174 | #define IRQ_IXDP2351_SPCI_PMC_INTA IXP23XX_MACH_IRQ(4) | ||
| 175 | #define IRQ_IXDP2351_SPCI_PMC_INTB IXP23XX_MACH_IRQ(5) | ||
| 176 | #define IRQ_IXDP2351_SPCI_PMC_INTC IXP23XX_MACH_IRQ(6) | ||
| 177 | #define IRQ_IXDP2351_SPCI_PMC_INTD IXP23XX_MACH_IRQ(7) | ||
| 178 | #define IRQ_IXDP2351_SPCI_FIC IXP23XX_MACH_IRQ(8) | ||
| 179 | |||
| 180 | #define IXDP2351_INTB_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(0)) | ||
| 181 | #define IXDP2351_INTB_IRQ_MASK(irq) (1 << IXDP2351_INTB_IRQ_BIT(irq)) | ||
| 182 | #define IXDP2351_INTB_IRQ_VALID 0x01FF | ||
| 183 | #define IXDP2351_INTB_IRQ_NUM 16 | ||
| 184 | |||
| 185 | /* | ||
| 186 | * Other external interrupts signaled through INTA | ||
| 187 | */ | ||
| 188 | #define IXDP2351_INTA_IRQ_BASE 16 | ||
| 189 | #define IRQ_IXDP2351_IPMI_FROM IXP23XX_MACH_IRQ(16) | ||
| 190 | #define IRQ_IXDP2351_125US IXP23XX_MACH_IRQ(17) | ||
| 191 | #define IRQ_IXDP2351_DB_0_ADD IXP23XX_MACH_IRQ(18) | ||
| 192 | #define IRQ_IXDP2351_DB_1_ADD IXP23XX_MACH_IRQ(19) | ||
| 193 | #define IRQ_IXDP2351_DEBUG1 IXP23XX_MACH_IRQ(20) | ||
| 194 | #define IRQ_IXDP2351_ADD_UART IXP23XX_MACH_IRQ(21) | ||
| 195 | #define IRQ_IXDP2351_FIC_ADD IXP23XX_MACH_IRQ(24) | ||
| 196 | #define IRQ_IXDP2351_CS8900 IXP23XX_MACH_IRQ(25) | ||
| 197 | #define IRQ_IXDP2351_BBSRAM IXP23XX_MACH_IRQ(26) | ||
| 198 | #define IRQ_IXDP2351_CONFIG_MEDIA IXP23XX_MACH_IRQ(27) | ||
| 199 | #define IRQ_IXDP2351_CLOCK_REF IXP23XX_MACH_IRQ(28) | ||
| 200 | #define IRQ_IXDP2351_A10_NP IXP23XX_MACH_IRQ(29) | ||
| 201 | #define IRQ_IXDP2351_A11_NP IXP23XX_MACH_IRQ(30) | ||
| 202 | #define IRQ_IXDP2351_DEBUG_NP IXP23XX_MACH_IRQ(31) | ||
| 203 | |||
| 204 | #define IXDP2351_INTA_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(16)) | ||
| 205 | #define IXDP2351_INTA_IRQ_MASK(irq) (1 << IXDP2351_INTA_IRQ_BIT(irq)) | ||
| 206 | #define IXDP2351_INTA_IRQ_VALID 0xFF3F | ||
| 207 | #define IXDP2351_INTA_IRQ_NUM 16 | ||
| 208 | |||
| 209 | |||
| 210 | /* | ||
| 211 | * ADI RoadRunner IRQs | ||
| 212 | */ | ||
| 213 | #define IRQ_ROADRUNNER_PCI_INTA IRQ_IXP23XX_INTA | ||
| 214 | #define IRQ_ROADRUNNER_PCI_INTB IRQ_IXP23XX_INTB | ||
| 215 | #define IRQ_ROADRUNNER_PCI_INTC IRQ_IXP23XX_GPIO11 | ||
| 216 | #define IRQ_ROADRUNNER_PCI_INTD IRQ_IXP23XX_GPIO12 | ||
| 217 | |||
| 218 | /* | ||
| 219 | * Put new board definitions here | ||
| 220 | */ | ||
| 221 | |||
| 222 | |||
| 223 | #endif | ||
diff --git a/include/asm-arm/arch-ixp23xx/ixdp2351.h b/include/asm-arm/arch-ixp23xx/ixdp2351.h deleted file mode 100644 index d5e8a43d7bbd..000000000000 --- a/include/asm-arm/arch-ixp23xx/ixdp2351.h +++ /dev/null | |||
| @@ -1,89 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/ixdp2351.h | ||
| 3 | * | ||
| 4 | * Register and other defines for IXDP2351 | ||
| 5 | * | ||
| 6 | * Copyright (c) 2002-2004 Intel Corp. | ||
| 7 | * Copytight (c) 2005 MontaVista Software, Inc. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_IXDP2351_H | ||
| 16 | #define __ASM_ARCH_IXDP2351_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * NP module memory map | ||
| 20 | */ | ||
| 21 | #define IXDP2351_NP_PHYS_BASE (IXP23XX_EXP_BUS_CS4_BASE) | ||
| 22 | #define IXDP2351_NP_PHYS_SIZE 0x00100000 | ||
| 23 | #define IXDP2351_NP_VIRT_BASE 0xeff00000 | ||
| 24 | |||
| 25 | #define IXDP2351_VIRT_CS8900_BASE (IXDP2351_NP_VIRT_BASE) | ||
| 26 | #define IXDP2351_VIRT_CS8900_END (IXDP2351_VIRT_CS8900_BASE + 16) | ||
| 27 | |||
| 28 | #define IXDP2351_VIRT_NP_CPLD_BASE (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000) | ||
| 29 | |||
| 30 | #define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg)) | ||
| 31 | |||
| 32 | #define IXDP2351_NP_CPLD_RESET1_REG IXDP2351_NP_CPLD_REG(0x00) | ||
| 33 | #define IXDP2351_NP_CPLD_LED_REG IXDP2351_NP_CPLD_REG(0x02) | ||
| 34 | #define IXDP2351_NP_CPLD_VERSION_REG IXDP2351_NP_CPLD_REG(0x04) | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Base board module memory map | ||
| 38 | */ | ||
| 39 | |||
| 40 | #define IXDP2351_BB_BASE_PHYS (IXP23XX_EXP_BUS_CS5_BASE) | ||
| 41 | #define IXDP2351_BB_SIZE 0x01000000 | ||
| 42 | #define IXDP2351_BB_BASE_VIRT (0xee000000) | ||
| 43 | |||
| 44 | #define IXDP2351_BB_AREA_BASE(offset) (IXDP2351_BB_BASE_VIRT + offset) | ||
| 45 | |||
| 46 | #define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0) | ||
| 47 | #define IXDP2351_NVRAM_SIZE (0x20000) | ||
| 48 | |||
| 49 | #define IXDP2351_VIRT_MB_IXF1104_BASE IXDP2351_BB_AREA_BASE(0x00020000) | ||
| 50 | #define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0) | ||
| 51 | #define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000) | ||
| 52 | #define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000) | ||
| 53 | #define IXDP2351_VIRT_DB1_BASE IXDP2351_BB_AREA_BASE(0x00600000) | ||
| 54 | #define IXDP2351_VIRT_CPLD_BASE IXDP2351_BB_AREA_BASE(0x00024000) | ||
| 55 | |||
| 56 | /* | ||
| 57 | * On board CPLD registers | ||
| 58 | */ | ||
| 59 | #define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg)) | ||
| 60 | |||
| 61 | #define IXDP2351_CPLD_RESET0_REG IXDP2351_CPLD_BB_REG(0x00) | ||
| 62 | #define IXDP2351_CPLD_RESET1_REG IXDP2351_CPLD_BB_REG(0x04) | ||
| 63 | |||
| 64 | #define IXDP2351_CPLD_RESET1_MAGIC 0x55AA | ||
| 65 | #define IXDP2351_CPLD_RESET1_ENABLE 0x8000 | ||
| 66 | |||
| 67 | #define IXDP2351_CPLD_FPGA_CONFIG_REG IXDP2351_CPLD_BB_REG(0x08) | ||
| 68 | #define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10) | ||
| 69 | #define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14) | ||
| 70 | #define IXDP2351_CPLD_INTB_STAT_REG IXDP2351_CPLD_BB_REG(0x18) | ||
| 71 | #define IXDP2351_CPLD_INTA_STAT_REG IXDP2351_CPLD_BB_REG(0x1C) | ||
| 72 | #define IXDP2351_CPLD_INTB_RAW_REG IXDP2351_CPLD_BB_REG(0x20) /* read */ | ||
| 73 | #define IXDP2351_CPLD_INTA_RAW_REG IXDP2351_CPLD_BB_REG(0x24) /* read */ | ||
| 74 | #define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG /* write */ | ||
| 75 | #define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG /* write */ | ||
| 76 | #define IXDP2351_CPLD_INTB_SIM_REG IXDP2351_CPLD_BB_REG(0x28) | ||
| 77 | #define IXDP2351_CPLD_INTA_SIM_REG IXDP2351_CPLD_BB_REG(0x2C) | ||
| 78 | /* Interrupt bits are defined in irqs.h */ | ||
| 79 | #define IXDP2351_CPLD_BB_GBE0_REG IXDP2351_CPLD_BB_REG(0x30) | ||
| 80 | #define IXDP2351_CPLD_BB_GBE1_REG IXDP2351_CPLD_BB_REG(0x34) | ||
| 81 | |||
| 82 | /* #define IXDP2351_CPLD_BB_MISC_REG IXDP2351_CPLD_REG(0x1C) */ | ||
| 83 | /* #define IXDP2351_CPLD_BB_MISC_REV_MASK 0xFF */ | ||
| 84 | /* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */ | ||
| 85 | /* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */ | ||
| 86 | /* #define IXDP2351_CPLD_BB_CLOCK_REG IXDP2351_CPLD_REG(0x04) */ | ||
| 87 | |||
| 88 | |||
| 89 | #endif | ||
diff --git a/include/asm-arm/arch-ixp23xx/ixp23xx.h b/include/asm-arm/arch-ixp23xx/ixp23xx.h deleted file mode 100644 index 3927b1d61b17..000000000000 --- a/include/asm-arm/arch-ixp23xx/ixp23xx.h +++ /dev/null | |||
| @@ -1,298 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/ixp23xx.h | ||
| 3 | * | ||
| 4 | * Register definitions for IXP23XX | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003-2005 Intel Corporation. | ||
| 7 | * Copyright (C) 2005 MontaVista Software, Inc. | ||
| 8 | * | ||
| 9 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_IXP23XX_H | ||
| 17 | #define __ASM_ARCH_IXP23XX_H | ||
| 18 | |||
| 19 | /* | ||
| 20 | * IXP2300 linux memory map: | ||
| 21 | * | ||
| 22 | * virt phys size | ||
| 23 | * fffd0000 a0000000 64K XSI2CPP_CSR | ||
| 24 | * fffc0000 c4000000 4K EXP_CFG | ||
| 25 | * fff00000 c8000000 64K PERIPHERAL | ||
| 26 | * fe000000 1c0000000 16M CAP_CSR | ||
| 27 | * fd000000 1c8000000 16M MSF_CSR | ||
| 28 | * fb000000 16M --- | ||
| 29 | * fa000000 1d8000000 32M PCI_IO | ||
| 30 | * f8000000 1da000000 32M PCI_CFG | ||
| 31 | * f6000000 1de000000 32M PCI_CREG | ||
| 32 | * f4000000 32M --- | ||
| 33 | * f0000000 1e0000000 64M PCI_MEM | ||
| 34 | * e[c-f]000000 per-platform mappings | ||
| 35 | */ | ||
| 36 | |||
| 37 | |||
| 38 | /**************************************************************************** | ||
| 39 | * Static mappings. | ||
| 40 | ****************************************************************************/ | ||
| 41 | #define IXP23XX_XSI2CPP_CSR_PHYS 0xa0000000 | ||
| 42 | #define IXP23XX_XSI2CPP_CSR_VIRT 0xfffd0000 | ||
| 43 | #define IXP23XX_XSI2CPP_CSR_SIZE 0x00010000 | ||
| 44 | |||
| 45 | #define IXP23XX_EXP_CFG_PHYS 0xc4000000 | ||
| 46 | #define IXP23XX_EXP_CFG_VIRT 0xfffc0000 | ||
| 47 | #define IXP23XX_EXP_CFG_SIZE 0x00001000 | ||
| 48 | |||
| 49 | #define IXP23XX_PERIPHERAL_PHYS 0xc8000000 | ||
| 50 | #define IXP23XX_PERIPHERAL_VIRT 0xfff00000 | ||
| 51 | #define IXP23XX_PERIPHERAL_SIZE 0x00010000 | ||
| 52 | |||
| 53 | #define IXP23XX_CAP_CSR_PHYS 0x1c0000000ULL | ||
| 54 | #define IXP23XX_CAP_CSR_VIRT 0xfe000000 | ||
| 55 | #define IXP23XX_CAP_CSR_SIZE 0x01000000 | ||
| 56 | |||
| 57 | #define IXP23XX_MSF_CSR_PHYS 0x1c8000000ULL | ||
| 58 | #define IXP23XX_MSF_CSR_VIRT 0xfd000000 | ||
| 59 | #define IXP23XX_MSF_CSR_SIZE 0x01000000 | ||
| 60 | |||
| 61 | #define IXP23XX_PCI_IO_PHYS 0x1d8000000ULL | ||
| 62 | #define IXP23XX_PCI_IO_VIRT 0xfa000000 | ||
| 63 | #define IXP23XX_PCI_IO_SIZE 0x02000000 | ||
| 64 | |||
| 65 | #define IXP23XX_PCI_CFG_PHYS 0x1da000000ULL | ||
| 66 | #define IXP23XX_PCI_CFG_VIRT 0xf8000000 | ||
| 67 | #define IXP23XX_PCI_CFG_SIZE 0x02000000 | ||
| 68 | #define IXP23XX_PCI_CFG0_VIRT IXP23XX_PCI_CFG_VIRT | ||
| 69 | #define IXP23XX_PCI_CFG1_VIRT (IXP23XX_PCI_CFG_VIRT + 0x01000000) | ||
| 70 | |||
| 71 | #define IXP23XX_PCI_CREG_PHYS 0x1de000000ULL | ||
| 72 | #define IXP23XX_PCI_CREG_VIRT 0xf6000000 | ||
| 73 | #define IXP23XX_PCI_CREG_SIZE 0x02000000 | ||
| 74 | #define IXP23XX_PCI_CSR_VIRT (IXP23XX_PCI_CREG_VIRT + 0x01000000) | ||
| 75 | |||
| 76 | #define IXP23XX_PCI_MEM_START 0xe0000000 | ||
| 77 | #define IXP23XX_PCI_MEM_PHYS 0x1e0000000ULL | ||
| 78 | #define IXP23XX_PCI_MEM_VIRT 0xf0000000 | ||
| 79 | #define IXP23XX_PCI_MEM_SIZE 0x04000000 | ||
| 80 | |||
| 81 | |||
| 82 | /**************************************************************************** | ||
| 83 | * XSI2CPP CSRs. | ||
| 84 | ****************************************************************************/ | ||
| 85 | #define IXP23XX_XSI2CPP_REG(x) ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x))) | ||
| 86 | #define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8) | ||
| 87 | #define IXP23XX_CPP2XSI_ADDR_31 (1 << 19) | ||
| 88 | #define IXP23XX_CPP2XSI_PSH_OFF (1 << 20) | ||
| 89 | #define IXP23XX_CPP2XSI_COH_OFF (1 << 21) | ||
| 90 | |||
| 91 | |||
| 92 | /**************************************************************************** | ||
| 93 | * Expansion Bus Config. | ||
| 94 | ****************************************************************************/ | ||
| 95 | #define IXP23XX_EXP_CFG_REG(x) ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x))) | ||
| 96 | #define IXP23XX_EXP_CS0 IXP23XX_EXP_CFG_REG(0x00) | ||
| 97 | #define IXP23XX_EXP_CS1 IXP23XX_EXP_CFG_REG(0x04) | ||
| 98 | #define IXP23XX_EXP_CS2 IXP23XX_EXP_CFG_REG(0x08) | ||
| 99 | #define IXP23XX_EXP_CS3 IXP23XX_EXP_CFG_REG(0x0c) | ||
| 100 | #define IXP23XX_EXP_CS4 IXP23XX_EXP_CFG_REG(0x10) | ||
| 101 | #define IXP23XX_EXP_CS5 IXP23XX_EXP_CFG_REG(0x14) | ||
| 102 | #define IXP23XX_EXP_CS6 IXP23XX_EXP_CFG_REG(0x18) | ||
| 103 | #define IXP23XX_EXP_CS7 IXP23XX_EXP_CFG_REG(0x1c) | ||
| 104 | #define IXP23XX_FLASH_WRITABLE (0x2) | ||
| 105 | #define IXP23XX_FLASH_BUS8 (0x1) | ||
| 106 | |||
| 107 | #define IXP23XX_EXP_CFG0 IXP23XX_EXP_CFG_REG(0x20) | ||
| 108 | #define IXP23XX_EXP_CFG1 IXP23XX_EXP_CFG_REG(0x24) | ||
| 109 | #define IXP23XX_EXP_CFG0_MEM_MAP (1 << 31) | ||
| 110 | #define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL (3 << 22) | ||
| 111 | #define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN (1 << 21) | ||
| 112 | #define IXP23XX_EXP_CFG0_CPP_SPEED_SEL (3 << 19) | ||
| 113 | #define IXP23XX_EXP_CFG0_CPP_SPEED_EN (1 << 18) | ||
| 114 | #define IXP23XX_EXP_CFG0_PCI_SWIN (3 << 16) | ||
| 115 | #define IXP23XX_EXP_CFG0_PCI_DWIN (3 << 14) | ||
| 116 | #define IXP23XX_EXP_CFG0_PCI33_MODE (1 << 13) | ||
| 117 | #define IXP23XX_EXP_CFG0_QDR_SPEED_SEL (1 << 12) | ||
| 118 | #define IXP23XX_EXP_CFG0_CPP_DIV_SEL (1 << 5) | ||
| 119 | #define IXP23XX_EXP_CFG0_XSI_NOT_PRES (1 << 4) | ||
| 120 | #define IXP23XX_EXP_CFG0_PROM_BOOT (1 << 3) | ||
| 121 | #define IXP23XX_EXP_CFG0_PCI_ARB (1 << 2) | ||
| 122 | #define IXP23XX_EXP_CFG0_PCI_HOST (1 << 1) | ||
| 123 | #define IXP23XX_EXP_CFG0_FLASH_WIDTH (1 << 0) | ||
| 124 | |||
| 125 | #define IXP23XX_EXP_UNIT_FUSE IXP23XX_EXP_CFG_REG(0x28) | ||
| 126 | #define IXP23XX_EXP_MSF_MUX IXP23XX_EXP_CFG_REG(0x30) | ||
| 127 | #define IXP23XX_EXP_CFG_FUSE IXP23XX_EXP_CFG_REG(0x34) | ||
| 128 | |||
| 129 | #define IXP23XX_EXP_BUS_PHYS 0x90000000 | ||
| 130 | #define IXP23XX_EXP_BUS_WINDOW_SIZE 0x01000000 | ||
| 131 | |||
| 132 | #define IXP23XX_EXP_BUS_CS0_BASE (IXP23XX_EXP_BUS_PHYS + 0x00000000) | ||
| 133 | #define IXP23XX_EXP_BUS_CS1_BASE (IXP23XX_EXP_BUS_PHYS + 0x01000000) | ||
| 134 | #define IXP23XX_EXP_BUS_CS2_BASE (IXP23XX_EXP_BUS_PHYS + 0x02000000) | ||
| 135 | #define IXP23XX_EXP_BUS_CS3_BASE (IXP23XX_EXP_BUS_PHYS + 0x03000000) | ||
| 136 | #define IXP23XX_EXP_BUS_CS4_BASE (IXP23XX_EXP_BUS_PHYS + 0x04000000) | ||
| 137 | #define IXP23XX_EXP_BUS_CS5_BASE (IXP23XX_EXP_BUS_PHYS + 0x05000000) | ||
| 138 | #define IXP23XX_EXP_BUS_CS6_BASE (IXP23XX_EXP_BUS_PHYS + 0x06000000) | ||
| 139 | #define IXP23XX_EXP_BUS_CS7_BASE (IXP23XX_EXP_BUS_PHYS + 0x07000000) | ||
| 140 | |||
| 141 | |||
| 142 | /**************************************************************************** | ||
| 143 | * Peripherals. | ||
| 144 | ****************************************************************************/ | ||
| 145 | #define IXP23XX_UART1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x0000) | ||
| 146 | #define IXP23XX_UART2_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x1000) | ||
| 147 | #define IXP23XX_PMU_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x2000) | ||
| 148 | #define IXP23XX_INTC_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x3000) | ||
| 149 | #define IXP23XX_GPIO_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x4000) | ||
| 150 | #define IXP23XX_TIMER_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x5000) | ||
| 151 | #define IXP23XX_NPE0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x6000) | ||
| 152 | #define IXP23XX_DSR_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x7000) | ||
| 153 | #define IXP23XX_NPE1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x8000) | ||
| 154 | #define IXP23XX_ETH0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x9000) | ||
| 155 | #define IXP23XX_ETH1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xA000) | ||
| 156 | #define IXP23XX_GIG0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xB000) | ||
| 157 | #define IXP23XX_GIG1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xC000) | ||
| 158 | #define IXP23XX_DDRS_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xD000) | ||
| 159 | |||
| 160 | #define IXP23XX_UART1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x0000) | ||
| 161 | #define IXP23XX_UART2_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x1000) | ||
| 162 | #define IXP23XX_PMU_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x2000) | ||
| 163 | #define IXP23XX_INTC_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x3000) | ||
| 164 | #define IXP23XX_GPIO_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x4000) | ||
| 165 | #define IXP23XX_TIMER_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x5000) | ||
| 166 | #define IXP23XX_NPE0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x6000) | ||
| 167 | #define IXP23XX_DSR_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x7000) | ||
| 168 | #define IXP23XX_NPE1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x8000) | ||
| 169 | #define IXP23XX_ETH0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x9000) | ||
| 170 | #define IXP23XX_ETH1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xA000) | ||
| 171 | #define IXP23XX_GIG0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xB000) | ||
| 172 | #define IXP23XX_GIG1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xC000) | ||
| 173 | #define IXP23XX_DDRS_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xD000) | ||
| 174 | |||
| 175 | |||
| 176 | /**************************************************************************** | ||
| 177 | * Interrupt controller. | ||
| 178 | ****************************************************************************/ | ||
| 179 | #define IXP23XX_INTC_REG(x) ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x))) | ||
| 180 | #define IXP23XX_INTR_ST1 IXP23XX_INTC_REG(0x00) | ||
| 181 | #define IXP23XX_INTR_ST2 IXP23XX_INTC_REG(0x04) | ||
| 182 | #define IXP23XX_INTR_ST3 IXP23XX_INTC_REG(0x08) | ||
| 183 | #define IXP23XX_INTR_ST4 IXP23XX_INTC_REG(0x0c) | ||
| 184 | #define IXP23XX_INTR_EN1 IXP23XX_INTC_REG(0x10) | ||
| 185 | #define IXP23XX_INTR_EN2 IXP23XX_INTC_REG(0x14) | ||
| 186 | #define IXP23XX_INTR_EN3 IXP23XX_INTC_REG(0x18) | ||
| 187 | #define IXP23XX_INTR_EN4 IXP23XX_INTC_REG(0x1c) | ||
| 188 | #define IXP23XX_INTR_SEL1 IXP23XX_INTC_REG(0x20) | ||
| 189 | #define IXP23XX_INTR_SEL2 IXP23XX_INTC_REG(0x24) | ||
| 190 | #define IXP23XX_INTR_SEL3 IXP23XX_INTC_REG(0x28) | ||
| 191 | #define IXP23XX_INTR_SEL4 IXP23XX_INTC_REG(0x2c) | ||
| 192 | #define IXP23XX_INTR_IRQ_ST1 IXP23XX_INTC_REG(0x30) | ||
| 193 | #define IXP23XX_INTR_IRQ_ST2 IXP23XX_INTC_REG(0x34) | ||
| 194 | #define IXP23XX_INTR_IRQ_ST3 IXP23XX_INTC_REG(0x38) | ||
| 195 | #define IXP23XX_INTR_IRQ_ST4 IXP23XX_INTC_REG(0x3c) | ||
| 196 | #define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54 | ||
| 197 | |||
| 198 | |||
| 199 | /**************************************************************************** | ||
| 200 | * GPIO. | ||
| 201 | ****************************************************************************/ | ||
| 202 | #define IXP23XX_GPIO_REG(x) ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x))) | ||
| 203 | #define IXP23XX_GPIO_GPOUTR IXP23XX_GPIO_REG(0x00) | ||
| 204 | #define IXP23XX_GPIO_GPOER IXP23XX_GPIO_REG(0x04) | ||
| 205 | #define IXP23XX_GPIO_GPINR IXP23XX_GPIO_REG(0x08) | ||
| 206 | #define IXP23XX_GPIO_GPISR IXP23XX_GPIO_REG(0x0c) | ||
| 207 | #define IXP23XX_GPIO_GPIT1R IXP23XX_GPIO_REG(0x10) | ||
| 208 | #define IXP23XX_GPIO_GPIT2R IXP23XX_GPIO_REG(0x14) | ||
| 209 | #define IXP23XX_GPIO_GPCLKR IXP23XX_GPIO_REG(0x18) | ||
| 210 | #define IXP23XX_GPIO_GPDBSELR IXP23XX_GPIO_REG(0x1c) | ||
| 211 | |||
| 212 | #define IXP23XX_GPIO_STYLE_MASK 0x7 | ||
| 213 | #define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0 | ||
| 214 | #define IXP23XX_GPIO_STYLE_ACTIVE_LOW 0x1 | ||
| 215 | #define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2 | ||
| 216 | #define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3 | ||
| 217 | #define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4 | ||
| 218 | |||
| 219 | #define IXP23XX_GPIO_STYLE_SIZE 3 | ||
| 220 | |||
| 221 | |||
| 222 | /**************************************************************************** | ||
| 223 | * Timer. | ||
| 224 | ****************************************************************************/ | ||
| 225 | #define IXP23XX_TIMER_REG(x) ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x))) | ||
| 226 | #define IXP23XX_TIMER_CONT IXP23XX_TIMER_REG(0x00) | ||
| 227 | #define IXP23XX_TIMER1_TIMESTAMP IXP23XX_TIMER_REG(0x04) | ||
| 228 | #define IXP23XX_TIMER1_RELOAD IXP23XX_TIMER_REG(0x08) | ||
| 229 | #define IXP23XX_TIMER2_TIMESTAMP IXP23XX_TIMER_REG(0x0c) | ||
| 230 | #define IXP23XX_TIMER2_RELOAD IXP23XX_TIMER_REG(0x10) | ||
| 231 | #define IXP23XX_TIMER_WDOG IXP23XX_TIMER_REG(0x14) | ||
| 232 | #define IXP23XX_TIMER_WDOG_EN IXP23XX_TIMER_REG(0x18) | ||
| 233 | #define IXP23XX_TIMER_WDOG_KEY IXP23XX_TIMER_REG(0x1c) | ||
| 234 | #define IXP23XX_TIMER_WDOG_KEY_MAGIC 0x482e | ||
| 235 | #define IXP23XX_TIMER_STATUS IXP23XX_TIMER_REG(0x20) | ||
| 236 | #define IXP23XX_TIMER_SOFT_RESET IXP23XX_TIMER_REG(0x24) | ||
| 237 | #define IXP23XX_TIMER_SOFT_RESET_EN IXP23XX_TIMER_REG(0x28) | ||
| 238 | |||
| 239 | #define IXP23XX_TIMER_ENABLE (1 << 0) | ||
| 240 | #define IXP23XX_TIMER_ONE_SHOT (1 << 1) | ||
| 241 | /* Low order bits of reload value ignored */ | ||
| 242 | #define IXP23XX_TIMER_RELOAD_MASK (0x3) | ||
| 243 | #define IXP23XX_TIMER_DISABLED (0x0) | ||
| 244 | #define IXP23XX_TIMER1_INT_PEND (1 << 0) | ||
| 245 | #define IXP23XX_TIMER2_INT_PEND (1 << 1) | ||
| 246 | #define IXP23XX_TIMER_STATUS_TS_PEND (1 << 2) | ||
| 247 | #define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3) | ||
| 248 | #define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4) | ||
| 249 | |||
| 250 | |||
| 251 | /**************************************************************************** | ||
| 252 | * CAP CSRs. | ||
| 253 | ****************************************************************************/ | ||
| 254 | #define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x))) | ||
| 255 | #define IXP23XX_PRODUCT_ID IXP23XX_GLOBAL_REG(0x00) | ||
| 256 | #define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04) | ||
| 257 | #define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08) | ||
| 258 | #define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c) | ||
| 259 | #define IXP23XX_RESET1 IXP23XX_GLOBAL_REG(0x10) | ||
| 260 | #define IXP23XX_STRAP_OPTIONS IXP23XX_GLOBAL_REG(0x18) | ||
| 261 | |||
| 262 | #define IXP23XX_ENABLE_WATCHDOG (1 << 24) | ||
| 263 | #define IXP23XX_SHPC_INIT_COMP (1 << 21) | ||
| 264 | #define IXP23XX_RST_ALL (1 << 16) | ||
| 265 | #define IXP23XX_RESET_PCI (1 << 2) | ||
| 266 | #define IXP23XX_PCI_UNIT_RESET (1 << 1) | ||
| 267 | #define IXP23XX_XSCALE_RESET (1 << 0) | ||
| 268 | |||
| 269 | #define IXP23XX_UENGINE_CSR_VIRT_BASE (IXP23XX_CAP_CSR_VIRT + 0x18000) | ||
| 270 | |||
| 271 | |||
| 272 | /**************************************************************************** | ||
| 273 | * PCI CSRs. | ||
| 274 | ****************************************************************************/ | ||
| 275 | #define IXP23XX_PCI_CREG(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x))) | ||
| 276 | #define IXP23XX_PCI_CMDSTAT IXP23XX_PCI_CREG(0x04) | ||
| 277 | #define IXP23XX_PCI_SRAM_BAR IXP23XX_PCI_CREG(0x14) | ||
| 278 | #define IXP23XX_PCI_SDRAM_BAR IXP23XX_PCI_CREG(0x18) | ||
| 279 | |||
| 280 | |||
| 281 | #define IXP23XX_PCI_CSR(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x))) | ||
| 282 | #define IXP23XX_PCI_OUT_INT_STATUS IXP23XX_PCI_CSR(0x0030) | ||
| 283 | #define IXP23XX_PCI_OUT_INT_MASK IXP23XX_PCI_CSR(0x0034) | ||
| 284 | #define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc) | ||
| 285 | #define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100) | ||
| 286 | #define IXP23XX_PCI_CONTROL IXP23XX_PCI_CSR(0x013c) | ||
| 287 | #define IXP23XX_PCI_ADDR_EXT IXP23XX_PCI_CSR(0x0140) | ||
| 288 | #define IXP23XX_PCI_ME_PUSH_STATUS IXP23XX_PCI_CSR(0x0148) | ||
| 289 | #define IXP23XX_PCI_ME_PUSH_EN IXP23XX_PCI_CSR(0x014c) | ||
| 290 | #define IXP23XX_PCI_ERR_STATUS IXP23XX_PCI_CSR(0x0150) | ||
| 291 | #define IXP23XX_PCI_ERROR_STATUS IXP23XX_PCI_CSR(0x0150) | ||
| 292 | #define IXP23XX_PCI_ERR_ENABLE IXP23XX_PCI_CSR(0x0154) | ||
| 293 | #define IXP23XX_PCI_XSCALE_INT_STATUS IXP23XX_PCI_CSR(0x0158) | ||
| 294 | #define IXP23XX_PCI_XSCALE_INT_ENABLE IXP23XX_PCI_CSR(0x015c) | ||
| 295 | #define IXP23XX_PCI_CPP_ADDR_BITS IXP23XX_PCI_CSR(0x0160) | ||
| 296 | |||
| 297 | |||
| 298 | #endif | ||
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h deleted file mode 100644 index c3d906af9fea..000000000000 --- a/include/asm-arm/arch-ixp23xx/memory.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2003-2004 Intel Corp. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 13 | #define __ASM_ARCH_MEMORY_H | ||
| 14 | |||
| 15 | #include <asm/arch/hardware.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Physical DRAM offset. | ||
| 19 | */ | ||
| 20 | #define PHYS_OFFSET (0x00000000) | ||
| 21 | |||
| 22 | |||
| 23 | /* | ||
| 24 | * Virtual view <-> DMA view memory address translations | ||
| 25 | * virt_to_bus: Used to translate the virtual address to an | ||
| 26 | * address suitable to be passed to set_dma_addr | ||
| 27 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 28 | * to an address that the kernel can use. | ||
| 29 | */ | ||
| 30 | #ifndef __ASSEMBLY__ | ||
| 31 | |||
| 32 | #define __virt_to_bus(v) \ | ||
| 33 | ({ unsigned int ret; \ | ||
| 34 | ret = ((__virt_to_phys(v) - 0x00000000) + \ | ||
| 35 | (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)); \ | ||
| 36 | ret; }) | ||
| 37 | |||
| 38 | #define __bus_to_virt(b) \ | ||
| 39 | ({ unsigned int data; \ | ||
| 40 | data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \ | ||
| 41 | __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); }) | ||
| 42 | |||
| 43 | #define arch_is_coherent() 1 | ||
| 44 | |||
| 45 | #endif | ||
| 46 | |||
| 47 | |||
| 48 | #endif | ||
diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h deleted file mode 100644 index db8aa304c93d..000000000000 --- a/include/asm-arm/arch-ixp23xx/platform.h +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/platform.h | ||
| 3 | * | ||
| 4 | * Various bits of code used by platform-level code. | ||
| 5 | * | ||
| 6 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
| 7 | * | ||
| 8 | * Copyright 2005 (c) MontaVista Software, Inc. | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASSEMBLY__ | ||
| 16 | |||
| 17 | static inline unsigned long ixp2000_reg_read(volatile void *reg) | ||
| 18 | { | ||
| 19 | return *((volatile unsigned long *)reg); | ||
| 20 | } | ||
| 21 | |||
| 22 | static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) | ||
| 23 | { | ||
| 24 | *((volatile unsigned long *)reg) = val; | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) | ||
| 28 | { | ||
| 29 | *((volatile unsigned long *)reg) = val; | ||
| 30 | } | ||
| 31 | |||
| 32 | struct pci_sys_data; | ||
| 33 | |||
| 34 | void ixp23xx_map_io(void); | ||
| 35 | void ixp23xx_init_irq(void); | ||
| 36 | void ixp23xx_sys_init(void); | ||
| 37 | int ixp23xx_pci_setup(int, struct pci_sys_data *); | ||
| 38 | void ixp23xx_pci_preinit(void); | ||
| 39 | struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*); | ||
| 40 | void ixp23xx_pci_slave_init(void); | ||
| 41 | |||
| 42 | extern struct sys_timer ixp23xx_timer; | ||
| 43 | |||
| 44 | #define IXP23XX_UART_XTAL 14745600 | ||
| 45 | |||
| 46 | #ifndef __ASSEMBLY__ | ||
| 47 | /* | ||
| 48 | * Is system memory on the XSI or CPP bus? | ||
| 49 | */ | ||
| 50 | static inline unsigned ixp23xx_cpp_boot(void) | ||
| 51 | { | ||
| 52 | return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES); | ||
| 53 | } | ||
| 54 | #endif | ||
| 55 | |||
| 56 | |||
| 57 | #endif | ||
diff --git a/include/asm-arm/arch-ixp23xx/system.h b/include/asm-arm/arch-ixp23xx/system.h deleted file mode 100644 index 54e8a51475e6..000000000000 --- a/include/asm-arm/arch-ixp23xx/system.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 Intel Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/arch/hardware.h> | ||
| 12 | #include <asm/mach-types.h> | ||
| 13 | |||
| 14 | static inline void arch_idle(void) | ||
| 15 | { | ||
| 16 | #if 0 | ||
| 17 | if (!hlt_counter) | ||
| 18 | cpu_do_idle(); | ||
| 19 | #endif | ||
| 20 | } | ||
| 21 | |||
| 22 | static inline void arch_reset(char mode) | ||
| 23 | { | ||
| 24 | /* First try machine specific support */ | ||
| 25 | if (machine_is_ixdp2351()) { | ||
| 26 | *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC; | ||
| 27 | (void) *IXDP2351_CPLD_RESET1_REG; | ||
| 28 | *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE; | ||
| 29 | } | ||
| 30 | |||
| 31 | /* Use on-chip reset capability */ | ||
| 32 | *IXP23XX_RESET0 |= IXP23XX_RST_ALL; | ||
| 33 | } | ||
diff --git a/include/asm-arm/arch-ixp23xx/time.h b/include/asm-arm/arch-ixp23xx/time.h deleted file mode 100644 index f6828fdd2883..000000000000 --- a/include/asm-arm/arch-ixp23xx/time.h +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/time.h | ||
| 3 | */ | ||
diff --git a/include/asm-arm/arch-ixp23xx/timex.h b/include/asm-arm/arch-ixp23xx/timex.h deleted file mode 100644 index 516f72fe6082..000000000000 --- a/include/asm-arm/arch-ixp23xx/timex.h +++ /dev/null | |||
| @@ -1,7 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/timex.h | ||
| 3 | * | ||
| 4 | * XScale architecture timex specifications | ||
| 5 | */ | ||
| 6 | |||
| 7 | #define CLOCK_TICK_RATE 75000000 | ||
diff --git a/include/asm-arm/arch-ixp23xx/uncompress.h b/include/asm-arm/arch-ixp23xx/uncompress.h deleted file mode 100644 index 16c1110f2304..000000000000 --- a/include/asm-arm/arch-ixp23xx/uncompress.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002-2004 Intel Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
| 12 | #define __ASM_ARCH_UNCOMPRESS_H | ||
| 13 | |||
| 14 | #include <asm/arch/ixp23xx.h> | ||
| 15 | #include <linux/serial_reg.h> | ||
| 16 | |||
| 17 | #define UART_BASE ((volatile u32 *)IXP23XX_UART1_PHYS) | ||
| 18 | |||
| 19 | static inline void putc(char c) | ||
| 20 | { | ||
| 21 | int j; | ||
| 22 | |||
| 23 | for (j = 0; j < 0x1000; j++) { | ||
| 24 | if (UART_BASE[UART_LSR] & UART_LSR_THRE) | ||
| 25 | break; | ||
| 26 | barrier(); | ||
| 27 | } | ||
| 28 | |||
| 29 | UART_BASE[UART_TX] = c; | ||
| 30 | } | ||
| 31 | |||
| 32 | static inline void flush(void) | ||
| 33 | { | ||
| 34 | } | ||
| 35 | |||
| 36 | #define arch_decomp_setup() | ||
| 37 | #define arch_decomp_wdog() | ||
| 38 | |||
| 39 | |||
| 40 | #endif | ||
diff --git a/include/asm-arm/arch-ixp23xx/vmalloc.h b/include/asm-arm/arch-ixp23xx/vmalloc.h deleted file mode 100644 index 9f2566658541..000000000000 --- a/include/asm-arm/arch-ixp23xx/vmalloc.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp23xx/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 MontaVista Software, Inc. | ||
| 5 | * | ||
| 6 | * NPU mappings end at 0xf0000000 and we allocate 64MB for board | ||
| 7 | * specific static I/O. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define VMALLOC_END (0xec000000) | ||
diff --git a/include/asm-arm/arch-ixp4xx/avila.h b/include/asm-arm/arch-ixp4xx/avila.h deleted file mode 100644 index 88f053d64430..000000000000 --- a/include/asm-arm/arch-ixp4xx/avila.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/avila.h | ||
| 3 | * | ||
| 4 | * Gateworks Avila platform specific definitions | ||
| 5 | * | ||
| 6 | * Author: Michael-Luke Jones <mlj28@cam.ac.uk> | ||
| 7 | * | ||
| 8 | * Based on ixdp425.h | ||
| 9 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
| 10 | * | ||
| 11 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
| 12 | * | ||
| 13 | * This file is licensed under the terms of the GNU General Public | ||
| 14 | * License version 2. This program is licensed "as is" without any | ||
| 15 | * warranty of any kind, whether express or implied. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 19 | #error "Do not include this directly, instead #include <asm/arch/hardware.h>" | ||
| 20 | #endif | ||
| 21 | |||
| 22 | #define AVILA_SDA_PIN 7 | ||
| 23 | #define AVILA_SCL_PIN 6 | ||
| 24 | |||
| 25 | /* | ||
| 26 | * AVILA PCI IRQs | ||
| 27 | */ | ||
| 28 | #define AVILA_PCI_MAX_DEV 4 | ||
| 29 | #define LOFT_PCI_MAX_DEV 6 | ||
| 30 | #define AVILA_PCI_IRQ_LINES 4 | ||
| 31 | |||
| 32 | |||
| 33 | /* PCI controller GPIO to IRQ pin mappings */ | ||
| 34 | #define AVILA_PCI_INTA_PIN 11 | ||
| 35 | #define AVILA_PCI_INTB_PIN 10 | ||
| 36 | #define AVILA_PCI_INTC_PIN 9 | ||
| 37 | #define AVILA_PCI_INTD_PIN 8 | ||
| 38 | |||
| 39 | |||
diff --git a/include/asm-arm/arch-ixp4xx/coyote.h b/include/asm-arm/arch-ixp4xx/coyote.h deleted file mode 100644 index 428b298afc1f..000000000000 --- a/include/asm-arm/arch-ixp4xx/coyote.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/coyote.h | ||
| 3 | * | ||
| 4 | * ADI Engineering platform specific definitions | ||
| 5 | * | ||
| 6 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
| 7 | * | ||
| 8 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 16 | #error "Do not include this directly, instead #include <asm/arch/hardware.h>" | ||
| 17 | #endif | ||
| 18 | |||
| 19 | /* PCI controller GPIO to IRQ pin mappings */ | ||
| 20 | #define COYOTE_PCI_SLOT0_PIN 6 | ||
| 21 | #define COYOTE_PCI_SLOT1_PIN 11 | ||
| 22 | |||
| 23 | #define COYOTE_PCI_SLOT0_DEVID 14 | ||
| 24 | #define COYOTE_PCI_SLOT1_DEVID 15 | ||
| 25 | |||
| 26 | #define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3) | ||
| 27 | #define COYOTE_IDE_BASE_VIRT 0xFFFE1000 | ||
| 28 | #define COYOTE_IDE_REGION_SIZE 0x1000 | ||
| 29 | |||
| 30 | #define COYOTE_IDE_DATA_PORT 0xFFFE10E0 | ||
| 31 | #define COYOTE_IDE_CTRL_PORT 0xFFFE10FC | ||
| 32 | #define COYOTE_IDE_ERROR_PORT 0xFFFE10E2 | ||
| 33 | |||
diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h deleted file mode 100644 index 2fa3d6b8dbb8..000000000000 --- a/include/asm-arm/arch-ixp4xx/cpu.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/cpu.h | ||
| 3 | * | ||
| 4 | * IXP4XX cpu type detection | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 MontaVista Software, Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_CPU_H__ | ||
| 15 | #define __ASM_ARCH_CPU_H__ | ||
| 16 | |||
| 17 | extern unsigned int processor_id; | ||
| 18 | /* Processor id value in CP15 Register 0 */ | ||
| 19 | #define IXP425_PROCESSOR_ID_VALUE 0x690541c0 | ||
| 20 | #define IXP435_PROCESSOR_ID_VALUE 0x69054040 | ||
| 21 | #define IXP465_PROCESSOR_ID_VALUE 0x69054200 | ||
| 22 | #define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0 | ||
| 23 | |||
| 24 | #define cpu_is_ixp42x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ | ||
| 25 | IXP425_PROCESSOR_ID_VALUE) | ||
| 26 | #define cpu_is_ixp43x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ | ||
| 27 | IXP435_PROCESSOR_ID_VALUE) | ||
| 28 | #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ | ||
| 29 | IXP465_PROCESSOR_ID_VALUE) | ||
| 30 | |||
| 31 | static inline u32 ixp4xx_read_feature_bits(void) | ||
| 32 | { | ||
| 33 | unsigned int val = ~*IXP4XX_EXP_CFG2; | ||
| 34 | val &= ~IXP4XX_FEATURE_RESERVED; | ||
| 35 | if (!cpu_is_ixp46x()) | ||
| 36 | val &= ~IXP4XX_FEATURE_IXP46X_ONLY; | ||
| 37 | |||
| 38 | return val; | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline void ixp4xx_write_feature_bits(u32 value) | ||
| 42 | { | ||
| 43 | *IXP4XX_EXP_CFG2 = ~value; | ||
| 44 | } | ||
| 45 | |||
| 46 | #endif /* _ASM_ARCH_CPU_H */ | ||
diff --git a/include/asm-arm/arch-ixp4xx/debug-macro.S b/include/asm-arm/arch-ixp4xx/debug-macro.S deleted file mode 100644 index 37bc8ef23e67..000000000000 --- a/include/asm-arm/arch-ixp4xx/debug-macro.S +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-ixp4xx/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | .macro addruart,rx | ||
| 14 | mrc p15, 0, \rx, c1, c0 | ||
| 15 | tst \rx, #1 @ MMU enabled? | ||
| 16 | moveq \rx, #0xc8000000 | ||
| 17 | movne \rx, #0xff000000 | ||
| 18 | orrne \rx, \rx, #0x00b00000 | ||
| 19 | add \rx,\rx,#3 @ Uart regs are at off set of 3 if | ||
| 20 | @ byte writes used - Big Endian. | ||
| 21 | .endm | ||
| 22 | |||
| 23 | #define UART_SHIFT 2 | ||
| 24 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-ixp4xx/dma.h b/include/asm-arm/arch-ixp4xx/dma.h deleted file mode 100644 index 0b755d6e9198..000000000000 --- a/include/asm-arm/arch-ixp4xx/dma.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001-2004 MontaVista Software, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_DMA_H | ||
| 12 | #define __ASM_ARCH_DMA_H | ||
| 13 | |||
| 14 | #include <linux/device.h> | ||
| 15 | #include <asm/page.h> | ||
| 16 | #include <asm/sizes.h> | ||
| 17 | #include <asm/arch/hardware.h> | ||
| 18 | |||
| 19 | #define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) | ||
| 20 | |||
| 21 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-ixp4xx/dsmg600.h b/include/asm-arm/arch-ixp4xx/dsmg600.h deleted file mode 100644 index 5afae8c2e296..000000000000 --- a/include/asm-arm/arch-ixp4xx/dsmg600.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * DSM-G600 platform specific definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Tower Technologies | ||
| 5 | * Author: Alessandro Zummo <a.zummo@towertech.it> | ||
| 6 | * | ||
| 7 | * based on ixdp425.h: | ||
| 8 | * Copyright 2004 (C) MontaVista, Software, Inc. | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 16 | #error "Do not include this directly, instead #include <asm/arch/hardware.h>" | ||
| 17 | #endif | ||
| 18 | |||
| 19 | #define DSMG600_SDA_PIN 5 | ||
| 20 | #define DSMG600_SCL_PIN 4 | ||
| 21 | |||
| 22 | /* | ||
| 23 | * DSMG600 PCI IRQs | ||
| 24 | */ | ||
| 25 | #define DSMG600_PCI_MAX_DEV 4 | ||
| 26 | #define DSMG600_PCI_IRQ_LINES 3 | ||
| 27 | |||
| 28 | |||
| 29 | /* PCI controller GPIO to IRQ pin mappings */ | ||
| 30 | #define DSMG600_PCI_INTA_PIN 11 | ||
| 31 | #define DSMG600_PCI_INTB_PIN 10 | ||
| 32 | #define DSMG600_PCI_INTC_PIN 9 | ||
| 33 | #define DSMG600_PCI_INTD_PIN 8 | ||
| 34 | #define DSMG600_PCI_INTE_PIN 7 | ||
| 35 | #define DSMG600_PCI_INTF_PIN 6 | ||
| 36 | |||
| 37 | /* DSM-G600 Timer Setting */ | ||
| 38 | #define DSMG600_FREQ 66000000 | ||
| 39 | |||
| 40 | /* Buttons */ | ||
| 41 | |||
| 42 | #define DSMG600_PB_GPIO 15 /* power button */ | ||
| 43 | #define DSMG600_RB_GPIO 3 /* reset button */ | ||
| 44 | |||
| 45 | /* Power control */ | ||
| 46 | |||
| 47 | #define DSMG600_PO_GPIO 2 /* power off */ | ||
| 48 | |||
| 49 | /* LEDs */ | ||
| 50 | |||
| 51 | #define DSMG600_LED_PWR_GPIO 0 | ||
| 52 | #define DSMG600_LED_WLAN_GPIO 14 | ||
diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S deleted file mode 100644 index ed313c52a8a4..000000000000 --- a/include/asm-arm/arch-ixp4xx/entry-macro.S +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for IXP4xx-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | |||
| 12 | .macro disable_fiq | ||
| 13 | .endm | ||
| 14 | |||
| 15 | .macro get_irqnr_preamble, base, tmp | ||
| 16 | .endm | ||
| 17 | |||
| 18 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 22 | ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET) | ||
| 23 | ldr \irqstat, [\irqstat] @ get interrupts | ||
| 24 | cmp \irqstat, #0 | ||
| 25 | beq 1001f @ upper IRQ? | ||
| 26 | clz \irqnr, \irqstat | ||
| 27 | mov \base, #31 | ||
| 28 | sub \irqnr, \base, \irqnr | ||
| 29 | b 1002f @ lower IRQ being | ||
| 30 | @ handled | ||
| 31 | |||
| 32 | 1001: | ||
| 33 | /* | ||
| 34 | * IXP465/IXP435 has an upper IRQ status register | ||
| 35 | */ | ||
| 36 | #if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X) | ||
| 37 | ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET) | ||
| 38 | ldr \irqstat, [\irqstat] @ get upper interrupts | ||
| 39 | mov \irqnr, #63 | ||
| 40 | clz \irqstat, \irqstat | ||
| 41 | cmp \irqstat, #32 | ||
| 42 | subne \irqnr, \irqnr, \irqstat | ||
| 43 | #endif | ||
| 44 | 1002: | ||
| 45 | .endm | ||
| 46 | |||
| 47 | |||
diff --git a/include/asm-arm/arch-ixp4xx/fsg.h b/include/asm-arm/arch-ixp4xx/fsg.h deleted file mode 100644 index 168b9848eb4a..000000000000 --- a/include/asm-arm/arch-ixp4xx/fsg.h +++ /dev/null | |||
| @@ -1,50 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/fsg.h | ||
| 3 | * | ||
| 4 | * Freecom FSG-3 platform specific definitions | ||
| 5 | * | ||
| 6 | * Author: Rod Whitby <rod@whitby.id.au> | ||
| 7 | * Author: Tomasz Chmielewski <mangoo@wpkg.org> | ||
| 8 | * Maintainers: http://www.nslu2-linux.org | ||
| 9 | * | ||
| 10 | * Based on coyote.h by | ||
| 11 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
| 12 | * | ||
| 13 | * This file is licensed under the terms of the GNU General Public | ||
| 14 | * License version 2. This program is licensed "as is" without any | ||
| 15 | * warranty of any kind, whether express or implied. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 19 | #error "Do not include this directly, instead #include <asm/arch/hardware.h>" | ||
| 20 | #endif | ||
| 21 | |||
| 22 | #define FSG_SDA_PIN 12 | ||
| 23 | #define FSG_SCL_PIN 13 | ||
| 24 | |||
| 25 | /* | ||
| 26 | * FSG PCI IRQs | ||
| 27 | */ | ||
| 28 | #define FSG_PCI_MAX_DEV 3 | ||
| 29 | #define FSG_PCI_IRQ_LINES 3 | ||
| 30 | |||
| 31 | |||
| 32 | /* PCI controller GPIO to IRQ pin mappings */ | ||
| 33 | #define FSG_PCI_INTA_PIN 6 | ||
| 34 | #define FSG_PCI_INTB_PIN 7 | ||
| 35 | #define FSG_PCI_INTC_PIN 5 | ||
| 36 | |||
| 37 | /* Buttons */ | ||
| 38 | |||
| 39 | #define FSG_SB_GPIO 4 /* sync button */ | ||
| 40 | #define FSG_RB_GPIO 9 /* reset button */ | ||
| 41 | #define FSG_UB_GPIO 10 /* usb button */ | ||
| 42 | |||
| 43 | /* LEDs */ | ||
| 44 | |||
| 45 | #define FSG_LED_WLAN_BIT 0 | ||
| 46 | #define FSG_LED_WAN_BIT 1 | ||
| 47 | #define FSG_LED_SATA_BIT 2 | ||
| 48 | #define FSG_LED_USB_BIT 4 | ||
| 49 | #define FSG_LED_RING_BIT 5 | ||
| 50 | #define FSG_LED_SYNC_BIT 7 | ||
diff --git a/include/asm-arm/arch-ixp4xx/gpio.h b/include/asm-arm/arch-ixp4xx/gpio.h deleted file mode 100644 index 28e7d27b1b8f..000000000000 --- a/include/asm-arm/arch-ixp4xx/gpio.h +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp4xx/gpio.h | ||
| 3 | * | ||
| 4 | * IXP4XX GPIO wrappers for arch-neutral GPIO calls | ||
| 5 | * | ||
| 6 | * Written by Milan Svoboda <msvoboda@ra.rockwell.com> | ||
| 7 | * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 22 | * | ||
| 23 | */ | ||
| 24 | |||
| 25 | #ifndef __ASM_ARCH_IXP4XX_GPIO_H | ||
| 26 | #define __ASM_ARCH_IXP4XX_GPIO_H | ||
| 27 | |||
| 28 | #include <asm/arch/hardware.h> | ||
| 29 | |||
| 30 | static inline int gpio_request(unsigned gpio, const char *label) | ||
| 31 | { | ||
| 32 | return 0; | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline void gpio_free(unsigned gpio) | ||
| 36 | { | ||
| 37 | return; | ||
| 38 | } | ||
| 39 | |||
| 40 | static inline int gpio_direction_input(unsigned gpio) | ||
| 41 | { | ||
| 42 | gpio_line_config(gpio, IXP4XX_GPIO_IN); | ||
| 43 | return 0; | ||
| 44 | } | ||
| 45 | |||
| 46 | static inline int gpio_direction_output(unsigned gpio, int level) | ||
| 47 | { | ||
| 48 | gpio_line_set(gpio, level); | ||
| 49 | gpio_line_config(gpio, IXP4XX_GPIO_OUT); | ||
| 50 | return 0; | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline int gpio_get_value(unsigned gpio) | ||
| 54 | { | ||
| 55 | int value; | ||
| 56 | |||
| 57 | gpio_line_get(gpio, &value); | ||
| 58 | |||
| 59 | return value; | ||
| 60 | } | ||
| 61 | |||
| 62 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 63 | { | ||
| 64 | gpio_line_set(gpio, value); | ||
| 65 | } | ||
| 66 | |||
| 67 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
| 68 | |||
| 69 | extern int gpio_to_irq(int gpio); | ||
| 70 | extern int irq_to_gpio(int gpio); | ||
| 71 | |||
| 72 | #endif | ||
| 73 | |||
diff --git a/include/asm-arm/arch-ixp4xx/gtwx5715.h b/include/asm-arm/arch-ixp4xx/gtwx5715.h deleted file mode 100644 index 2192dedc2f59..000000000000 --- a/include/asm-arm/arch-ixp4xx/gtwx5715.h +++ /dev/null | |||
| @@ -1,116 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/gtwx5715.h | ||
| 3 | * | ||
| 4 | * Gemtek GTWX5715 Gateway (Linksys WRV54G) | ||
| 5 | * | ||
| 6 | * Copyright 2004 (c) George T. Joseph | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * as published by the Free Software Foundation; either version 2 | ||
| 11 | * of the License, or (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 24 | #error "Do not include this directly, instead #include <asm/arch/hardware.h>" | ||
| 25 | #endif | ||
| 26 | #include "irqs.h" | ||
| 27 | |||
| 28 | #define GTWX5715_GPIO0 0 | ||
| 29 | #define GTWX5715_GPIO1 1 | ||
| 30 | #define GTWX5715_GPIO2 2 | ||
| 31 | #define GTWX5715_GPIO3 3 | ||
| 32 | #define GTWX5715_GPIO4 4 | ||
| 33 | #define GTWX5715_GPIO5 5 | ||
| 34 | #define GTWX5715_GPIO6 6 | ||
| 35 | #define GTWX5715_GPIO7 7 | ||
| 36 | #define GTWX5715_GPIO8 8 | ||
| 37 | #define GTWX5715_GPIO9 9 | ||
| 38 | #define GTWX5715_GPIO10 10 | ||
| 39 | #define GTWX5715_GPIO11 11 | ||
| 40 | #define GTWX5715_GPIO12 12 | ||
| 41 | #define GTWX5715_GPIO13 13 | ||
| 42 | #define GTWX5715_GPIO14 14 | ||
| 43 | |||
| 44 | #define GTWX5715_GPIO0_IRQ IRQ_IXP4XX_GPIO0 | ||
| 45 | #define GTWX5715_GPIO1_IRQ IRQ_IXP4XX_GPIO1 | ||
| 46 | #define GTWX5715_GPIO2_IRQ IRQ_IXP4XX_GPIO2 | ||
| 47 | #define GTWX5715_GPIO3_IRQ IRQ_IXP4XX_GPIO3 | ||
| 48 | #define GTWX5715_GPIO4_IRQ IRQ_IXP4XX_GPIO4 | ||
| 49 | #define GTWX5715_GPIO5_IRQ IRQ_IXP4XX_GPIO5 | ||
| 50 | #define GTWX5715_GPIO6_IRQ IRQ_IXP4XX_GPIO6 | ||
| 51 | #define GTWX5715_GPIO7_IRQ IRQ_IXP4XX_GPIO7 | ||
| 52 | #define GTWX5715_GPIO8_IRQ IRQ_IXP4XX_GPIO8 | ||
| 53 | #define GTWX5715_GPIO9_IRQ IRQ_IXP4XX_GPIO9 | ||
| 54 | #define GTWX5715_GPIO10_IRQ IRQ_IXP4XX_GPIO10 | ||
| 55 | #define GTWX5715_GPIO11_IRQ IRQ_IXP4XX_GPIO11 | ||
| 56 | #define GTWX5715_GPIO12_IRQ IRQ_IXP4XX_GPIO12 | ||
| 57 | #define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1 | ||
| 58 | #define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2 | ||
| 59 | |||
| 60 | /* PCI controller GPIO to IRQ pin mappings | ||
| 61 | |||
| 62 | INTA INTB | ||
| 63 | SLOT 0 10 11 | ||
| 64 | SLOT 1 11 10 | ||
| 65 | |||
| 66 | */ | ||
| 67 | |||
| 68 | #define GTWX5715_PCI_SLOT0_DEVID 0 | ||
| 69 | #define GTWX5715_PCI_SLOT0_INTA_GPIO GTWX5715_GPIO10 | ||
| 70 | #define GTWX5715_PCI_SLOT0_INTB_GPIO GTWX5715_GPIO11 | ||
| 71 | #define GTWX5715_PCI_SLOT0_INTA_IRQ GTWX5715_GPIO10_IRQ | ||
| 72 | #define GTWX5715_PCI_SLOT0_INTB_IRQ GTWX5715_GPIO11_IRQ | ||
| 73 | |||
| 74 | #define GTWX5715_PCI_SLOT1_DEVID 1 | ||
| 75 | #define GTWX5715_PCI_SLOT1_INTA_GPIO GTWX5715_GPIO11 | ||
| 76 | #define GTWX5715_PCI_SLOT1_INTB_GPIO GTWX5715_GPIO10 | ||
| 77 | #define GTWX5715_PCI_SLOT1_INTA_IRQ GTWX5715_GPIO11_IRQ | ||
| 78 | #define GTWX5715_PCI_SLOT1_INTB_IRQ GTWX5715_GPIO10_IRQ | ||
| 79 | |||
| 80 | #define GTWX5715_PCI_SLOT_COUNT 2 | ||
| 81 | #define GTWX5715_PCI_INT_PIN_COUNT 2 | ||
| 82 | |||
| 83 | /* | ||
| 84 | * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch | ||
| 85 | * and operate as an SPI type interface. The details of the interface | ||
| 86 | * are available on Kendin/Micrel's web site. | ||
| 87 | */ | ||
| 88 | |||
| 89 | #define GTWX5715_KSSPI_SELECT GTWX5715_GPIO5 | ||
| 90 | #define GTWX5715_KSSPI_TXD GTWX5715_GPIO6 | ||
| 91 | #define GTWX5715_KSSPI_CLOCK GTWX5715_GPIO7 | ||
| 92 | #define GTWX5715_KSSPI_RXD GTWX5715_GPIO12 | ||
| 93 | |||
| 94 | /* | ||
| 95 | * The "reset" button is wired to GPIO 3. | ||
| 96 | * The GPIO is brought "low" when the button is pushed. | ||
| 97 | */ | ||
| 98 | |||
| 99 | #define GTWX5715_BUTTON_GPIO GTWX5715_GPIO3 | ||
| 100 | #define GTWX5715_BUTTON_IRQ GTWX5715_GPIO3_IRQ | ||
| 101 | |||
| 102 | /* | ||
| 103 | * Board Label Front Label | ||
| 104 | * LED1 Power | ||
| 105 | * LED2 Wireless-G | ||
| 106 | * LED3 not populated but could be | ||
| 107 | * LED4 Internet | ||
| 108 | * LED5 - LED8 Controlled by KS8995M Switch | ||
| 109 | * LED9 DMZ | ||
| 110 | */ | ||
| 111 | |||
| 112 | #define GTWX5715_LED1_GPIO GTWX5715_GPIO2 | ||
| 113 | #define GTWX5715_LED2_GPIO GTWX5715_GPIO9 | ||
| 114 | #define GTWX5715_LED3_GPIO GTWX5715_GPIO8 | ||
| 115 | #define GTWX5715_LED4_GPIO GTWX5715_GPIO1 | ||
| 116 | #define GTWX5715_LED9_GPIO GTWX5715_GPIO4 | ||
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h deleted file mode 100644 index fa723a627854..000000000000 --- a/include/asm-arm/arch-ixp4xx/hardware.h +++ /dev/null | |||
| @@ -1,50 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002 Intel Corporation. | ||
| 5 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * Hardware definitions for IXP4xx based systems | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 18 | #define __ASM_ARCH_HARDWARE_H__ | ||
| 19 | |||
| 20 | #define PCIBIOS_MIN_IO 0x00001000 | ||
| 21 | #define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000) | ||
| 22 | |||
| 23 | /* | ||
| 24 | * We override the standard dma-mask routines for bouncing. | ||
| 25 | */ | ||
| 26 | #define HAVE_ARCH_PCI_SET_DMA_MASK | ||
| 27 | |||
| 28 | #define pcibios_assign_all_busses() 1 | ||
| 29 | |||
| 30 | /* Register locations and bits */ | ||
| 31 | #include "ixp4xx-regs.h" | ||
| 32 | |||
| 33 | #ifndef __ASSEMBLER__ | ||
| 34 | #include <asm/arch/cpu.h> | ||
| 35 | #endif | ||
| 36 | |||
| 37 | /* Platform helper functions and definitions */ | ||
| 38 | #include "platform.h" | ||
| 39 | |||
| 40 | /* Platform specific details */ | ||
| 41 | #include "ixdp425.h" | ||
| 42 | #include "avila.h" | ||
| 43 | #include "coyote.h" | ||
| 44 | #include "prpmc1100.h" | ||
| 45 | #include "nslu2.h" | ||
| 46 | #include "nas100d.h" | ||
| 47 | #include "dsmg600.h" | ||
| 48 | #include "fsg.h" | ||
| 49 | |||
| 50 | #endif /* _ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h deleted file mode 100644 index 8e7426081f0e..000000000000 --- a/include/asm-arm/arch-ixp4xx/io.h +++ /dev/null | |||
| @@ -1,569 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp4xx/io.h | ||
| 3 | * | ||
| 4 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
| 5 | * | ||
| 6 | * Copyright (C) 2002-2005 MontaVista Software, Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 14 | #define __ASM_ARM_ARCH_IO_H | ||
| 15 | |||
| 16 | #include <linux/bitops.h> | ||
| 17 | |||
| 18 | #include <asm/arch/hardware.h> | ||
| 19 | |||
| 20 | #define IO_SPACE_LIMIT 0xffff0000 | ||
| 21 | |||
| 22 | extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); | ||
| 23 | extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | ||
| 24 | |||
| 25 | |||
| 26 | /* | ||
| 27 | * IXP4xx provides two methods of accessing PCI memory space: | ||
| 28 | * | ||
| 29 | * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). | ||
| 30 | * To access PCI via this space, we simply ioremap() the BAR | ||
| 31 | * into the kernel and we can use the standard read[bwl]/write[bwl] | ||
| 32 | * macros. This is the preffered method due to speed but it | ||
| 33 | * limits the system to just 64MB of PCI memory. This can be | ||
| 34 | * problamatic if using video cards and other memory-heavy | ||
| 35 | * targets. | ||
| 36 | * | ||
| 37 | * 2) If > 64MB of memory space is required, the IXP4xx can be configured | ||
| 38 | * to use indirect registers to access PCI (as we do below for I/O | ||
| 39 | * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) | ||
| 40 | * of memory on the bus. The disadvantage of this is that every | ||
| 41 | * PCI access requires three local register accesses plus a spinlock, | ||
| 42 | * but in some cases the performance hit is acceptable. In addition, | ||
| 43 | * you cannot mmap() PCI devices in this case. | ||
| 44 | * | ||
| 45 | */ | ||
| 46 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 47 | |||
| 48 | #define __mem_pci(a) (a) | ||
| 49 | |||
| 50 | #else | ||
| 51 | |||
| 52 | #include <linux/mm.h> | ||
| 53 | |||
| 54 | /* | ||
| 55 | * In the case of using indirect PCI, we simply return the actual PCI | ||
| 56 | * address and our read/write implementation use that to drive the | ||
| 57 | * access registers. If something outside of PCI is ioremap'd, we | ||
| 58 | * fallback to the default. | ||
| 59 | */ | ||
| 60 | static inline void __iomem * | ||
| 61 | __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype) | ||
| 62 | { | ||
| 63 | if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) | ||
| 64 | return __arm_ioremap(addr, size, mtype); | ||
| 65 | |||
| 66 | return (void __iomem *)addr; | ||
| 67 | } | ||
| 68 | |||
| 69 | static inline void | ||
| 70 | __ixp4xx_iounmap(void __iomem *addr) | ||
| 71 | { | ||
| 72 | if ((__force u32)addr >= VMALLOC_START) | ||
| 73 | __iounmap(addr); | ||
| 74 | } | ||
| 75 | |||
| 76 | #define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f) | ||
| 77 | #define __arch_iounmap(a) __ixp4xx_iounmap(a) | ||
| 78 | |||
| 79 | #define writeb(v, p) __ixp4xx_writeb(v, p) | ||
| 80 | #define writew(v, p) __ixp4xx_writew(v, p) | ||
| 81 | #define writel(v, p) __ixp4xx_writel(v, p) | ||
| 82 | |||
| 83 | #define writesb(p, v, l) __ixp4xx_writesb(p, v, l) | ||
| 84 | #define writesw(p, v, l) __ixp4xx_writesw(p, v, l) | ||
| 85 | #define writesl(p, v, l) __ixp4xx_writesl(p, v, l) | ||
| 86 | |||
| 87 | #define readb(p) __ixp4xx_readb(p) | ||
| 88 | #define readw(p) __ixp4xx_readw(p) | ||
| 89 | #define readl(p) __ixp4xx_readl(p) | ||
| 90 | |||
| 91 | #define readsb(p, v, l) __ixp4xx_readsb(p, v, l) | ||
| 92 | #define readsw(p, v, l) __ixp4xx_readsw(p, v, l) | ||
| 93 | #define readsl(p, v, l) __ixp4xx_readsl(p, v, l) | ||
| 94 | |||
| 95 | static inline void | ||
| 96 | __ixp4xx_writeb(u8 value, volatile void __iomem *p) | ||
| 97 | { | ||
| 98 | u32 addr = (u32)p; | ||
| 99 | u32 n, byte_enables, data; | ||
| 100 | |||
| 101 | if (addr >= VMALLOC_START) { | ||
| 102 | __raw_writeb(value, addr); | ||
| 103 | return; | ||
| 104 | } | ||
| 105 | |||
| 106 | n = addr % 4; | ||
| 107 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | ||
| 108 | data = value << (8*n); | ||
| 109 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | ||
| 110 | } | ||
| 111 | |||
| 112 | static inline void | ||
| 113 | __ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) | ||
| 114 | { | ||
| 115 | while (count--) | ||
| 116 | writeb(*vaddr++, bus_addr); | ||
| 117 | } | ||
| 118 | |||
| 119 | static inline void | ||
| 120 | __ixp4xx_writew(u16 value, volatile void __iomem *p) | ||
| 121 | { | ||
| 122 | u32 addr = (u32)p; | ||
| 123 | u32 n, byte_enables, data; | ||
| 124 | |||
| 125 | if (addr >= VMALLOC_START) { | ||
| 126 | __raw_writew(value, addr); | ||
| 127 | return; | ||
| 128 | } | ||
| 129 | |||
| 130 | n = addr % 4; | ||
| 131 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | ||
| 132 | data = value << (8*n); | ||
| 133 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | ||
| 134 | } | ||
| 135 | |||
| 136 | static inline void | ||
| 137 | __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) | ||
| 138 | { | ||
| 139 | while (count--) | ||
| 140 | writew(*vaddr++, bus_addr); | ||
| 141 | } | ||
| 142 | |||
| 143 | static inline void | ||
| 144 | __ixp4xx_writel(u32 value, volatile void __iomem *p) | ||
| 145 | { | ||
| 146 | u32 addr = (__force u32)p; | ||
| 147 | if (addr >= VMALLOC_START) { | ||
| 148 | __raw_writel(value, p); | ||
| 149 | return; | ||
| 150 | } | ||
| 151 | |||
| 152 | ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); | ||
| 153 | } | ||
| 154 | |||
| 155 | static inline void | ||
| 156 | __ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) | ||
| 157 | { | ||
| 158 | while (count--) | ||
| 159 | writel(*vaddr++, bus_addr); | ||
| 160 | } | ||
| 161 | |||
| 162 | static inline unsigned char | ||
| 163 | __ixp4xx_readb(const volatile void __iomem *p) | ||
| 164 | { | ||
| 165 | u32 addr = (u32)p; | ||
| 166 | u32 n, byte_enables, data; | ||
| 167 | |||
| 168 | if (addr >= VMALLOC_START) | ||
| 169 | return __raw_readb(addr); | ||
| 170 | |||
| 171 | n = addr % 4; | ||
| 172 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | ||
| 173 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) | ||
| 174 | return 0xff; | ||
| 175 | |||
| 176 | return data >> (8*n); | ||
| 177 | } | ||
| 178 | |||
| 179 | static inline void | ||
| 180 | __ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) | ||
| 181 | { | ||
| 182 | while (count--) | ||
| 183 | *vaddr++ = readb(bus_addr); | ||
| 184 | } | ||
| 185 | |||
| 186 | static inline unsigned short | ||
| 187 | __ixp4xx_readw(const volatile void __iomem *p) | ||
| 188 | { | ||
| 189 | u32 addr = (u32)p; | ||
| 190 | u32 n, byte_enables, data; | ||
| 191 | |||
| 192 | if (addr >= VMALLOC_START) | ||
| 193 | return __raw_readw(addr); | ||
| 194 | |||
| 195 | n = addr % 4; | ||
| 196 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | ||
| 197 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) | ||
| 198 | return 0xffff; | ||
| 199 | |||
| 200 | return data>>(8*n); | ||
| 201 | } | ||
| 202 | |||
| 203 | static inline void | ||
| 204 | __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) | ||
| 205 | { | ||
| 206 | while (count--) | ||
| 207 | *vaddr++ = readw(bus_addr); | ||
| 208 | } | ||
| 209 | |||
| 210 | static inline unsigned long | ||
| 211 | __ixp4xx_readl(const volatile void __iomem *p) | ||
| 212 | { | ||
| 213 | u32 addr = (__force u32)p; | ||
| 214 | u32 data; | ||
| 215 | |||
| 216 | if (addr >= VMALLOC_START) | ||
| 217 | return __raw_readl(p); | ||
| 218 | |||
| 219 | if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) | ||
| 220 | return 0xffffffff; | ||
| 221 | |||
| 222 | return data; | ||
| 223 | } | ||
| 224 | |||
| 225 | static inline void | ||
| 226 | __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) | ||
| 227 | { | ||
| 228 | while (count--) | ||
| 229 | *vaddr++ = readl(bus_addr); | ||
| 230 | } | ||
| 231 | |||
| 232 | |||
| 233 | /* | ||
| 234 | * We can use the built-in functions b/c they end up calling writeb/readb | ||
| 235 | */ | ||
| 236 | #define memset_io(c,v,l) _memset_io((c),(v),(l)) | ||
| 237 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) | ||
| 238 | #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) | ||
| 239 | |||
| 240 | #endif | ||
| 241 | |||
| 242 | #ifndef CONFIG_PCI | ||
| 243 | |||
| 244 | #define __io(v) v | ||
| 245 | |||
| 246 | #else | ||
| 247 | |||
| 248 | /* | ||
| 249 | * IXP4xx does not have a transparent cpu -> PCI I/O translation | ||
| 250 | * window. Instead, it has a set of registers that must be tweaked | ||
| 251 | * with the proper byte lanes, command types, and address for the | ||
| 252 | * transaction. This means that we need to override the default | ||
| 253 | * I/O functions. | ||
| 254 | */ | ||
| 255 | #define outb(p, v) __ixp4xx_outb(p, v) | ||
| 256 | #define outw(p, v) __ixp4xx_outw(p, v) | ||
| 257 | #define outl(p, v) __ixp4xx_outl(p, v) | ||
| 258 | |||
| 259 | #define outsb(p, v, l) __ixp4xx_outsb(p, v, l) | ||
| 260 | #define outsw(p, v, l) __ixp4xx_outsw(p, v, l) | ||
| 261 | #define outsl(p, v, l) __ixp4xx_outsl(p, v, l) | ||
| 262 | |||
| 263 | #define inb(p) __ixp4xx_inb(p) | ||
| 264 | #define inw(p) __ixp4xx_inw(p) | ||
| 265 | #define inl(p) __ixp4xx_inl(p) | ||
| 266 | |||
| 267 | #define insb(p, v, l) __ixp4xx_insb(p, v, l) | ||
| 268 | #define insw(p, v, l) __ixp4xx_insw(p, v, l) | ||
| 269 | #define insl(p, v, l) __ixp4xx_insl(p, v, l) | ||
| 270 | |||
| 271 | |||
| 272 | static inline void | ||
| 273 | __ixp4xx_outb(u8 value, u32 addr) | ||
| 274 | { | ||
| 275 | u32 n, byte_enables, data; | ||
| 276 | n = addr % 4; | ||
| 277 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | ||
| 278 | data = value << (8*n); | ||
| 279 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | ||
| 280 | } | ||
| 281 | |||
| 282 | static inline void | ||
| 283 | __ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count) | ||
| 284 | { | ||
| 285 | while (count--) | ||
| 286 | outb(*vaddr++, io_addr); | ||
| 287 | } | ||
| 288 | |||
| 289 | static inline void | ||
| 290 | __ixp4xx_outw(u16 value, u32 addr) | ||
| 291 | { | ||
| 292 | u32 n, byte_enables, data; | ||
| 293 | n = addr % 4; | ||
| 294 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | ||
| 295 | data = value << (8*n); | ||
| 296 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); | ||
| 297 | } | ||
| 298 | |||
| 299 | static inline void | ||
| 300 | __ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count) | ||
| 301 | { | ||
| 302 | while (count--) | ||
| 303 | outw(cpu_to_le16(*vaddr++), io_addr); | ||
| 304 | } | ||
| 305 | |||
| 306 | static inline void | ||
| 307 | __ixp4xx_outl(u32 value, u32 addr) | ||
| 308 | { | ||
| 309 | ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); | ||
| 310 | } | ||
| 311 | |||
| 312 | static inline void | ||
| 313 | __ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count) | ||
| 314 | { | ||
| 315 | while (count--) | ||
| 316 | outl(*vaddr++, io_addr); | ||
| 317 | } | ||
| 318 | |||
| 319 | static inline u8 | ||
| 320 | __ixp4xx_inb(u32 addr) | ||
| 321 | { | ||
| 322 | u32 n, byte_enables, data; | ||
| 323 | n = addr % 4; | ||
| 324 | byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; | ||
| 325 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) | ||
| 326 | return 0xff; | ||
| 327 | |||
| 328 | return data >> (8*n); | ||
| 329 | } | ||
| 330 | |||
| 331 | static inline void | ||
| 332 | __ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count) | ||
| 333 | { | ||
| 334 | while (count--) | ||
| 335 | *vaddr++ = inb(io_addr); | ||
| 336 | } | ||
| 337 | |||
| 338 | static inline u16 | ||
| 339 | __ixp4xx_inw(u32 addr) | ||
| 340 | { | ||
| 341 | u32 n, byte_enables, data; | ||
| 342 | n = addr % 4; | ||
| 343 | byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; | ||
| 344 | if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) | ||
| 345 | return 0xffff; | ||
| 346 | |||
| 347 | return data>>(8*n); | ||
| 348 | } | ||
| 349 | |||
| 350 | static inline void | ||
| 351 | __ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count) | ||
| 352 | { | ||
| 353 | while (count--) | ||
| 354 | *vaddr++ = le16_to_cpu(inw(io_addr)); | ||
| 355 | } | ||
| 356 | |||
| 357 | static inline u32 | ||
| 358 | __ixp4xx_inl(u32 addr) | ||
| 359 | { | ||
| 360 | u32 data; | ||
| 361 | if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) | ||
| 362 | return 0xffffffff; | ||
| 363 | |||
| 364 | return data; | ||
| 365 | } | ||
| 366 | |||
| 367 | static inline void | ||
| 368 | __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) | ||
| 369 | { | ||
| 370 | while (count--) | ||
| 371 | *vaddr++ = inl(io_addr); | ||
| 372 | } | ||
| 373 | |||
| 374 | #define PIO_OFFSET 0x10000UL | ||
| 375 | #define PIO_MASK 0x0ffffUL | ||
| 376 | |||
| 377 | #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ | ||
| 378 | ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) | ||
| 379 | static inline unsigned int | ||
| 380 | __ixp4xx_ioread8(const void __iomem *addr) | ||
| 381 | { | ||
| 382 | unsigned long port = (unsigned long __force)addr; | ||
| 383 | if (__is_io_address(port)) | ||
| 384 | return (unsigned int)__ixp4xx_inb(port & PIO_MASK); | ||
| 385 | else | ||
| 386 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 387 | return (unsigned int)__raw_readb(port); | ||
| 388 | #else | ||
| 389 | return (unsigned int)__ixp4xx_readb(addr); | ||
| 390 | #endif | ||
| 391 | } | ||
| 392 | |||
| 393 | static inline void | ||
| 394 | __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) | ||
| 395 | { | ||
| 396 | unsigned long port = (unsigned long __force)addr; | ||
| 397 | if (__is_io_address(port)) | ||
| 398 | __ixp4xx_insb(port & PIO_MASK, vaddr, count); | ||
| 399 | else | ||
| 400 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 401 | __raw_readsb(addr, vaddr, count); | ||
| 402 | #else | ||
| 403 | __ixp4xx_readsb(addr, vaddr, count); | ||
| 404 | #endif | ||
| 405 | } | ||
| 406 | |||
| 407 | static inline unsigned int | ||
| 408 | __ixp4xx_ioread16(const void __iomem *addr) | ||
| 409 | { | ||
| 410 | unsigned long port = (unsigned long __force)addr; | ||
| 411 | if (__is_io_address(port)) | ||
| 412 | return (unsigned int)__ixp4xx_inw(port & PIO_MASK); | ||
| 413 | else | ||
| 414 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 415 | return le16_to_cpu(__raw_readw((u32)port)); | ||
| 416 | #else | ||
| 417 | return (unsigned int)__ixp4xx_readw(addr); | ||
| 418 | #endif | ||
| 419 | } | ||
| 420 | |||
| 421 | static inline void | ||
| 422 | __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) | ||
| 423 | { | ||
| 424 | unsigned long port = (unsigned long __force)addr; | ||
| 425 | if (__is_io_address(port)) | ||
| 426 | __ixp4xx_insw(port & PIO_MASK, vaddr, count); | ||
| 427 | else | ||
| 428 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 429 | __raw_readsw(addr, vaddr, count); | ||
| 430 | #else | ||
| 431 | __ixp4xx_readsw(addr, vaddr, count); | ||
| 432 | #endif | ||
| 433 | } | ||
| 434 | |||
| 435 | static inline unsigned int | ||
| 436 | __ixp4xx_ioread32(const void __iomem *addr) | ||
| 437 | { | ||
| 438 | unsigned long port = (unsigned long __force)addr; | ||
| 439 | if (__is_io_address(port)) | ||
| 440 | return (unsigned int)__ixp4xx_inl(port & PIO_MASK); | ||
| 441 | else { | ||
| 442 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 443 | return le32_to_cpu((__force __le32)__raw_readl(addr)); | ||
| 444 | #else | ||
| 445 | return (unsigned int)__ixp4xx_readl(addr); | ||
| 446 | #endif | ||
| 447 | } | ||
| 448 | } | ||
| 449 | |||
| 450 | static inline void | ||
| 451 | __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) | ||
| 452 | { | ||
| 453 | unsigned long port = (unsigned long __force)addr; | ||
| 454 | if (__is_io_address(port)) | ||
| 455 | __ixp4xx_insl(port & PIO_MASK, vaddr, count); | ||
| 456 | else | ||
| 457 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 458 | __raw_readsl(addr, vaddr, count); | ||
| 459 | #else | ||
| 460 | __ixp4xx_readsl(addr, vaddr, count); | ||
| 461 | #endif | ||
| 462 | } | ||
| 463 | |||
| 464 | static inline void | ||
| 465 | __ixp4xx_iowrite8(u8 value, void __iomem *addr) | ||
| 466 | { | ||
| 467 | unsigned long port = (unsigned long __force)addr; | ||
| 468 | if (__is_io_address(port)) | ||
| 469 | __ixp4xx_outb(value, port & PIO_MASK); | ||
| 470 | else | ||
| 471 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 472 | __raw_writeb(value, port); | ||
| 473 | #else | ||
| 474 | __ixp4xx_writeb(value, addr); | ||
| 475 | #endif | ||
| 476 | } | ||
| 477 | |||
| 478 | static inline void | ||
| 479 | __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) | ||
| 480 | { | ||
| 481 | unsigned long port = (unsigned long __force)addr; | ||
| 482 | if (__is_io_address(port)) | ||
| 483 | __ixp4xx_outsb(port & PIO_MASK, vaddr, count); | ||
| 484 | else | ||
| 485 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 486 | __raw_writesb(addr, vaddr, count); | ||
| 487 | #else | ||
| 488 | __ixp4xx_writesb(addr, vaddr, count); | ||
| 489 | #endif | ||
| 490 | } | ||
| 491 | |||
| 492 | static inline void | ||
| 493 | __ixp4xx_iowrite16(u16 value, void __iomem *addr) | ||
| 494 | { | ||
| 495 | unsigned long port = (unsigned long __force)addr; | ||
| 496 | if (__is_io_address(port)) | ||
| 497 | __ixp4xx_outw(value, port & PIO_MASK); | ||
| 498 | else | ||
| 499 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 500 | __raw_writew(cpu_to_le16(value), addr); | ||
| 501 | #else | ||
| 502 | __ixp4xx_writew(value, addr); | ||
| 503 | #endif | ||
| 504 | } | ||
| 505 | |||
| 506 | static inline void | ||
| 507 | __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) | ||
| 508 | { | ||
| 509 | unsigned long port = (unsigned long __force)addr; | ||
| 510 | if (__is_io_address(port)) | ||
| 511 | __ixp4xx_outsw(port & PIO_MASK, vaddr, count); | ||
| 512 | else | ||
| 513 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 514 | __raw_writesw(addr, vaddr, count); | ||
| 515 | #else | ||
| 516 | __ixp4xx_writesw(addr, vaddr, count); | ||
| 517 | #endif | ||
| 518 | } | ||
| 519 | |||
| 520 | static inline void | ||
| 521 | __ixp4xx_iowrite32(u32 value, void __iomem *addr) | ||
| 522 | { | ||
| 523 | unsigned long port = (unsigned long __force)addr; | ||
| 524 | if (__is_io_address(port)) | ||
| 525 | __ixp4xx_outl(value, port & PIO_MASK); | ||
| 526 | else | ||
| 527 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 528 | __raw_writel((u32 __force)cpu_to_le32(value), addr); | ||
| 529 | #else | ||
| 530 | __ixp4xx_writel(value, addr); | ||
| 531 | #endif | ||
| 532 | } | ||
| 533 | |||
| 534 | static inline void | ||
| 535 | __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) | ||
| 536 | { | ||
| 537 | unsigned long port = (unsigned long __force)addr; | ||
| 538 | if (__is_io_address(port)) | ||
| 539 | __ixp4xx_outsl(port & PIO_MASK, vaddr, count); | ||
| 540 | else | ||
| 541 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | ||
| 542 | __raw_writesl(addr, vaddr, count); | ||
| 543 | #else | ||
| 544 | __ixp4xx_writesl(addr, vaddr, count); | ||
| 545 | #endif | ||
| 546 | } | ||
| 547 | |||
| 548 | #define ioread8(p) __ixp4xx_ioread8(p) | ||
| 549 | #define ioread16(p) __ixp4xx_ioread16(p) | ||
| 550 | #define ioread32(p) __ixp4xx_ioread32(p) | ||
| 551 | |||
| 552 | #define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c) | ||
| 553 | #define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c) | ||
| 554 | #define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c) | ||
| 555 | |||
| 556 | #define iowrite8(v,p) __ixp4xx_iowrite8(v,p) | ||
| 557 | #define iowrite16(v,p) __ixp4xx_iowrite16(v,p) | ||
| 558 | #define iowrite32(v,p) __ixp4xx_iowrite32(v,p) | ||
| 559 | |||
| 560 | #define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c) | ||
| 561 | #define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c) | ||
| 562 | #define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c) | ||
| 563 | |||
| 564 | #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET)) | ||
| 565 | #define ioport_unmap(addr) | ||
| 566 | #endif // !CONFIG_PCI | ||
| 567 | |||
| 568 | #endif // __ASM_ARM_ARCH_IO_H | ||
| 569 | |||
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h deleted file mode 100644 index 674af4a84147..000000000000 --- a/include/asm-arm/arch-ixp4xx/irqs.h +++ /dev/null | |||
| @@ -1,138 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ definitions for IXP4XX based systems | ||
| 5 | * | ||
| 6 | * Copyright (C) 2002 Intel Corporation. | ||
| 7 | * Copyright (C) 2003 MontaVista Software, Inc. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef _ARCH_IXP4XX_IRQS_H_ | ||
| 16 | #define _ARCH_IXP4XX_IRQS_H_ | ||
| 17 | |||
| 18 | |||
| 19 | #define IRQ_IXP4XX_NPEA 0 | ||
| 20 | #define IRQ_IXP4XX_NPEB 1 | ||
| 21 | #define IRQ_IXP4XX_NPEC 2 | ||
| 22 | #define IRQ_IXP4XX_QM1 3 | ||
| 23 | #define IRQ_IXP4XX_QM2 4 | ||
| 24 | #define IRQ_IXP4XX_TIMER1 5 | ||
| 25 | #define IRQ_IXP4XX_GPIO0 6 | ||
| 26 | #define IRQ_IXP4XX_GPIO1 7 | ||
| 27 | #define IRQ_IXP4XX_PCI_INT 8 | ||
| 28 | #define IRQ_IXP4XX_PCI_DMA1 9 | ||
| 29 | #define IRQ_IXP4XX_PCI_DMA2 10 | ||
| 30 | #define IRQ_IXP4XX_TIMER2 11 | ||
| 31 | #define IRQ_IXP4XX_USB 12 | ||
| 32 | #define IRQ_IXP4XX_UART2 13 | ||
| 33 | #define IRQ_IXP4XX_TIMESTAMP 14 | ||
| 34 | #define IRQ_IXP4XX_UART1 15 | ||
| 35 | #define IRQ_IXP4XX_WDOG 16 | ||
| 36 | #define IRQ_IXP4XX_AHB_PMU 17 | ||
| 37 | #define IRQ_IXP4XX_XSCALE_PMU 18 | ||
| 38 | #define IRQ_IXP4XX_GPIO2 19 | ||
| 39 | #define IRQ_IXP4XX_GPIO3 20 | ||
| 40 | #define IRQ_IXP4XX_GPIO4 21 | ||
| 41 | #define IRQ_IXP4XX_GPIO5 22 | ||
| 42 | #define IRQ_IXP4XX_GPIO6 23 | ||
| 43 | #define IRQ_IXP4XX_GPIO7 24 | ||
| 44 | #define IRQ_IXP4XX_GPIO8 25 | ||
| 45 | #define IRQ_IXP4XX_GPIO9 26 | ||
| 46 | #define IRQ_IXP4XX_GPIO10 27 | ||
| 47 | #define IRQ_IXP4XX_GPIO11 28 | ||
| 48 | #define IRQ_IXP4XX_GPIO12 29 | ||
| 49 | #define IRQ_IXP4XX_SW_INT1 30 | ||
| 50 | #define IRQ_IXP4XX_SW_INT2 31 | ||
| 51 | #define IRQ_IXP4XX_USB_HOST 32 | ||
| 52 | #define IRQ_IXP4XX_I2C 33 | ||
| 53 | #define IRQ_IXP4XX_SSP 34 | ||
| 54 | #define IRQ_IXP4XX_TSYNC 35 | ||
| 55 | #define IRQ_IXP4XX_EAU_DONE 36 | ||
| 56 | #define IRQ_IXP4XX_SHA_DONE 37 | ||
| 57 | #define IRQ_IXP4XX_SWCP_PE 58 | ||
| 58 | #define IRQ_IXP4XX_QM_PE 60 | ||
| 59 | #define IRQ_IXP4XX_MCU_ECC 61 | ||
| 60 | #define IRQ_IXP4XX_EXP_PE 62 | ||
| 61 | |||
| 62 | /* | ||
| 63 | * Only first 32 sources are valid if running on IXP42x systems | ||
| 64 | */ | ||
| 65 | #if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X) | ||
| 66 | #define NR_IRQS 64 | ||
| 67 | #else | ||
| 68 | #define NR_IRQS 32 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) | ||
| 72 | |||
| 73 | /* | ||
| 74 | * IXDP425 board IRQs | ||
| 75 | */ | ||
| 76 | #define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
| 77 | #define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
| 78 | #define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
| 79 | #define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
| 80 | |||
| 81 | /* | ||
| 82 | * Gateworks Avila board IRQs | ||
| 83 | */ | ||
| 84 | #define IRQ_AVILA_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
| 85 | #define IRQ_AVILA_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
| 86 | #define IRQ_AVILA_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
| 87 | #define IRQ_AVILA_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
| 88 | |||
| 89 | |||
| 90 | /* | ||
| 91 | * PrPMC1100 Board IRQs | ||
| 92 | */ | ||
| 93 | #define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
| 94 | #define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
| 95 | #define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
| 96 | #define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
| 97 | |||
| 98 | /* | ||
| 99 | * ADI Coyote Board IRQs | ||
| 100 | */ | ||
| 101 | #define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6 | ||
| 102 | #define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11 | ||
| 103 | #define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5 | ||
| 104 | |||
| 105 | /* | ||
| 106 | * NSLU2 board IRQs | ||
| 107 | */ | ||
| 108 | #define IRQ_NSLU2_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
| 109 | #define IRQ_NSLU2_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
| 110 | #define IRQ_NSLU2_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
| 111 | |||
| 112 | /* | ||
| 113 | * NAS100D board IRQs | ||
| 114 | */ | ||
| 115 | #define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
| 116 | #define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
| 117 | #define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
| 118 | #define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
| 119 | #define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7 | ||
| 120 | |||
| 121 | /* | ||
| 122 | * D-Link DSM-G600 RevA board IRQs | ||
| 123 | */ | ||
| 124 | #define IRQ_DSMG600_PCI_INTA IRQ_IXP4XX_GPIO11 | ||
| 125 | #define IRQ_DSMG600_PCI_INTB IRQ_IXP4XX_GPIO10 | ||
| 126 | #define IRQ_DSMG600_PCI_INTC IRQ_IXP4XX_GPIO9 | ||
| 127 | #define IRQ_DSMG600_PCI_INTD IRQ_IXP4XX_GPIO8 | ||
| 128 | #define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 | ||
| 129 | #define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 | ||
| 130 | |||
| 131 | /* | ||
| 132 | * Freecom FSG-3 Board IRQs | ||
| 133 | */ | ||
| 134 | #define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 | ||
| 135 | #define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 | ||
| 136 | #define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 | ||
| 137 | |||
| 138 | #endif | ||
diff --git a/include/asm-arm/arch-ixp4xx/ixdp425.h b/include/asm-arm/arch-ixp4xx/ixdp425.h deleted file mode 100644 index d0a1dcb48d53..000000000000 --- a/include/asm-arm/arch-ixp4xx/ixdp425.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/ixdp425.h | ||
| 3 | * | ||
| 4 | * IXDP425 platform specific definitions | ||
| 5 | * | ||
| 6 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
| 7 | * | ||
| 8 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 16 | #error "Do not include this directly, instead #include <asm/arch/hardware.h>" | ||
| 17 | #endif | ||
| 18 | |||
| 19 | #define IXDP425_SDA_PIN 7 | ||
| 20 | #define IXDP425_SCL_PIN 6 | ||
| 21 | |||
| 22 | /* | ||
| 23 | * IXDP425 PCI IRQs | ||
| 24 | */ | ||
| 25 | #define IXDP425_PCI_MAX_DEV 4 | ||
| 26 | #define IXDP425_PCI_IRQ_LINES 4 | ||
| 27 | |||
| 28 | |||
| 29 | /* PCI controller GPIO to IRQ pin mappings */ | ||
| 30 | #define IXDP425_PCI_INTA_PIN 11 | ||
| 31 | #define IXDP425_PCI_INTB_PIN 10 | ||
| 32 | #define IXDP425_PCI_INTC_PIN 9 | ||
| 33 | #define IXDP425_PCI_INTD_PIN 8 | ||
| 34 | |||
| 35 | /* NAND Flash pins */ | ||
| 36 | #define IXDP425_NAND_NCE_PIN 12 | ||
| 37 | |||
| 38 | #define IXDP425_NAND_CMD_BYTE 0x01 | ||
| 39 | #define IXDP425_NAND_ADDR_BYTE 0x02 | ||
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h deleted file mode 100644 index 68aca8554f5a..000000000000 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h +++ /dev/null | |||
| @@ -1,638 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | ||
| 3 | * | ||
| 4 | * Register definitions for IXP4xx chipset. This file contains | ||
| 5 | * register location and bit definitions only. Platform specific | ||
| 6 | * definitions and helper function declarations are in platform.h | ||
| 7 | * and machine-name.h. | ||
| 8 | * | ||
| 9 | * Copyright (C) 2002 Intel Corporation. | ||
| 10 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | * | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef _ASM_ARM_IXP4XX_H_ | ||
| 19 | #define _ASM_ARM_IXP4XX_H_ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * IXP4xx Linux Memory Map: | ||
| 23 | * | ||
| 24 | * Phy Size Virt Description | ||
| 25 | * ========================================================================= | ||
| 26 | * | ||
| 27 | * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM | ||
| 28 | * | ||
| 29 | * 0x48000000 0x04000000 ioremap'd PCI Memory Space | ||
| 30 | * | ||
| 31 | * 0x50000000 0x10000000 ioremap'd EXP BUS | ||
| 32 | * | ||
| 33 | * 0x6000000 0x00004000 ioremap'd QMgr | ||
| 34 | * | ||
| 35 | * 0xC0000000 0x00001000 0xffbff000 PCI CFG | ||
| 36 | * | ||
| 37 | * 0xC4000000 0x00001000 0xffbfe000 EXP CFG | ||
| 38 | * | ||
| 39 | * 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals | ||
| 40 | */ | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Queue Manager | ||
| 44 | */ | ||
| 45 | #define IXP4XX_QMGR_BASE_PHYS (0x60000000) | ||
| 46 | #define IXP4XX_QMGR_REGION_SIZE (0x00004000) | ||
| 47 | |||
| 48 | /* | ||
| 49 | * Expansion BUS Configuration registers | ||
| 50 | */ | ||
| 51 | #define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000) | ||
| 52 | #define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000) | ||
| 53 | #define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000) | ||
| 54 | |||
| 55 | /* | ||
| 56 | * PCI Config registers | ||
| 57 | */ | ||
| 58 | #define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000) | ||
| 59 | #define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000) | ||
| 60 | #define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000) | ||
| 61 | |||
| 62 | /* | ||
| 63 | * Peripheral space | ||
| 64 | */ | ||
| 65 | #define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000) | ||
| 66 | #define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000) | ||
| 67 | #define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000) | ||
| 68 | |||
| 69 | /* | ||
| 70 | * Debug UART | ||
| 71 | * | ||
| 72 | * This is basically a remap of UART1 into a region that is section | ||
| 73 | * aligned so that it * can be used with the low-level debug code. | ||
| 74 | */ | ||
| 75 | #define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000) | ||
| 76 | #define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000) | ||
| 77 | #define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000) | ||
| 78 | |||
| 79 | #define IXP4XX_EXP_CS0_OFFSET 0x00 | ||
| 80 | #define IXP4XX_EXP_CS1_OFFSET 0x04 | ||
| 81 | #define IXP4XX_EXP_CS2_OFFSET 0x08 | ||
| 82 | #define IXP4XX_EXP_CS3_OFFSET 0x0C | ||
| 83 | #define IXP4XX_EXP_CS4_OFFSET 0x10 | ||
| 84 | #define IXP4XX_EXP_CS5_OFFSET 0x14 | ||
| 85 | #define IXP4XX_EXP_CS6_OFFSET 0x18 | ||
| 86 | #define IXP4XX_EXP_CS7_OFFSET 0x1C | ||
| 87 | #define IXP4XX_EXP_CFG0_OFFSET 0x20 | ||
| 88 | #define IXP4XX_EXP_CFG1_OFFSET 0x24 | ||
| 89 | #define IXP4XX_EXP_CFG2_OFFSET 0x28 | ||
| 90 | #define IXP4XX_EXP_CFG3_OFFSET 0x2C | ||
| 91 | |||
| 92 | /* | ||
| 93 | * Expansion Bus Controller registers. | ||
| 94 | */ | ||
| 95 | #define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) | ||
| 96 | |||
| 97 | #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) | ||
| 98 | #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) | ||
| 99 | #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) | ||
| 100 | #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET) | ||
| 101 | #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET) | ||
| 102 | #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET) | ||
| 103 | #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET) | ||
| 104 | #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET) | ||
| 105 | |||
| 106 | #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) | ||
| 107 | #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) | ||
| 108 | #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) | ||
| 109 | #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET) | ||
| 110 | |||
| 111 | |||
| 112 | /* | ||
| 113 | * Peripheral Space Register Region Base Addresses | ||
| 114 | */ | ||
| 115 | #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) | ||
| 116 | #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) | ||
| 117 | #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) | ||
| 118 | #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) | ||
| 119 | #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) | ||
| 120 | #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) | ||
| 121 | #define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000) | ||
| 122 | #define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000) | ||
| 123 | #define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000) | ||
| 124 | #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) | ||
| 125 | #define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) | ||
| 126 | #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) | ||
| 127 | /* ixp46X only */ | ||
| 128 | #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000) | ||
| 129 | #define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000) | ||
| 130 | #define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000) | ||
| 131 | #define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000) | ||
| 132 | #define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000) | ||
| 133 | #define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000) | ||
| 134 | #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) | ||
| 135 | |||
| 136 | |||
| 137 | #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) | ||
| 138 | #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) | ||
| 139 | #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) | ||
| 140 | #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) | ||
| 141 | #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) | ||
| 142 | #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) | ||
| 143 | #define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000) | ||
| 144 | #define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000) | ||
| 145 | #define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000) | ||
| 146 | #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) | ||
| 147 | #define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) | ||
| 148 | #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) | ||
| 149 | /* ixp46X only */ | ||
| 150 | #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000) | ||
| 151 | #define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000) | ||
| 152 | #define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000) | ||
| 153 | #define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000) | ||
| 154 | #define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000) | ||
| 155 | #define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000) | ||
| 156 | #define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000) | ||
| 157 | |||
| 158 | /* | ||
| 159 | * Constants to make it easy to access Interrupt Controller registers | ||
| 160 | */ | ||
| 161 | #define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */ | ||
| 162 | #define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */ | ||
| 163 | #define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ | ||
| 164 | #define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */ | ||
| 165 | #define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */ | ||
| 166 | #define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */ | ||
| 167 | #define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ | ||
| 168 | #define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ | ||
| 169 | |||
| 170 | /* | ||
| 171 | * IXP465-only | ||
| 172 | */ | ||
| 173 | #define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */ | ||
| 174 | #define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */ | ||
| 175 | #define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */ | ||
| 176 | #define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */ | ||
| 177 | #define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */ | ||
| 178 | #define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */ | ||
| 179 | |||
| 180 | |||
| 181 | /* | ||
| 182 | * Interrupt Controller Register Definitions. | ||
| 183 | */ | ||
| 184 | |||
| 185 | #define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x))) | ||
| 186 | |||
| 187 | #define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET) | ||
| 188 | #define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET) | ||
| 189 | #define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET) | ||
| 190 | #define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET) | ||
| 191 | #define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET) | ||
| 192 | #define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET) | ||
| 193 | #define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET) | ||
| 194 | #define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET) | ||
| 195 | #define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET) | ||
| 196 | #define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET) | ||
| 197 | #define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET) | ||
| 198 | #define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET) | ||
| 199 | #define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET) | ||
| 200 | #define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET) | ||
| 201 | |||
| 202 | /* | ||
| 203 | * Constants to make it easy to access GPIO registers | ||
| 204 | */ | ||
| 205 | #define IXP4XX_GPIO_GPOUTR_OFFSET 0x00 | ||
| 206 | #define IXP4XX_GPIO_GPOER_OFFSET 0x04 | ||
| 207 | #define IXP4XX_GPIO_GPINR_OFFSET 0x08 | ||
| 208 | #define IXP4XX_GPIO_GPISR_OFFSET 0x0C | ||
| 209 | #define IXP4XX_GPIO_GPIT1R_OFFSET 0x10 | ||
| 210 | #define IXP4XX_GPIO_GPIT2R_OFFSET 0x14 | ||
| 211 | #define IXP4XX_GPIO_GPCLKR_OFFSET 0x18 | ||
| 212 | #define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C | ||
| 213 | |||
| 214 | /* | ||
| 215 | * GPIO Register Definitions. | ||
| 216 | * [Only perform 32bit reads/writes] | ||
| 217 | */ | ||
| 218 | #define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x))) | ||
| 219 | |||
| 220 | #define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET) | ||
| 221 | #define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET) | ||
| 222 | #define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET) | ||
| 223 | #define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET) | ||
| 224 | #define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET) | ||
| 225 | #define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET) | ||
| 226 | #define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET) | ||
| 227 | #define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET) | ||
| 228 | |||
| 229 | /* | ||
| 230 | * GPIO register bit definitions | ||
| 231 | */ | ||
| 232 | |||
| 233 | /* Interrupt styles | ||
| 234 | */ | ||
| 235 | #define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0 | ||
| 236 | #define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1 | ||
| 237 | #define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2 | ||
| 238 | #define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3 | ||
| 239 | #define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4 | ||
| 240 | |||
| 241 | /* | ||
| 242 | * Mask used to clear interrupt styles | ||
| 243 | */ | ||
| 244 | #define IXP4XX_GPIO_STYLE_CLEAR 0x7 | ||
| 245 | #define IXP4XX_GPIO_STYLE_SIZE 3 | ||
| 246 | |||
| 247 | /* | ||
| 248 | * Constants to make it easy to access Timer Control/Status registers | ||
| 249 | */ | ||
| 250 | #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */ | ||
| 251 | #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ | ||
| 252 | #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ | ||
| 253 | #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ | ||
| 254 | #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ | ||
| 255 | #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */ | ||
| 256 | #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */ | ||
| 257 | #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */ | ||
| 258 | #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */ | ||
| 259 | |||
| 260 | /* | ||
| 261 | * Operating System Timer Register Definitions. | ||
| 262 | */ | ||
| 263 | |||
| 264 | #define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x))) | ||
| 265 | |||
| 266 | #define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET) | ||
| 267 | #define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET) | ||
| 268 | #define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET) | ||
| 269 | #define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET) | ||
| 270 | #define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET) | ||
| 271 | #define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET) | ||
| 272 | #define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET) | ||
| 273 | #define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET) | ||
| 274 | #define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET) | ||
| 275 | |||
| 276 | /* | ||
| 277 | * Timer register values and bit definitions | ||
| 278 | */ | ||
| 279 | #define IXP4XX_OST_ENABLE 0x00000001 | ||
| 280 | #define IXP4XX_OST_ONE_SHOT 0x00000002 | ||
| 281 | /* Low order bits of reload value ignored */ | ||
| 282 | #define IXP4XX_OST_RELOAD_MASK 0x00000003 | ||
| 283 | #define IXP4XX_OST_DISABLED 0x00000000 | ||
| 284 | #define IXP4XX_OSST_TIMER_1_PEND 0x00000001 | ||
| 285 | #define IXP4XX_OSST_TIMER_2_PEND 0x00000002 | ||
| 286 | #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004 | ||
| 287 | #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008 | ||
| 288 | #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010 | ||
| 289 | |||
| 290 | #define IXP4XX_WDT_KEY 0x0000482E | ||
| 291 | |||
| 292 | #define IXP4XX_WDT_RESET_ENABLE 0x00000001 | ||
| 293 | #define IXP4XX_WDT_IRQ_ENABLE 0x00000002 | ||
| 294 | #define IXP4XX_WDT_COUNT_ENABLE 0x00000004 | ||
| 295 | |||
| 296 | |||
| 297 | /* | ||
| 298 | * Constants to make it easy to access PCI Control/Status registers | ||
| 299 | */ | ||
| 300 | #define PCI_NP_AD_OFFSET 0x00 | ||
| 301 | #define PCI_NP_CBE_OFFSET 0x04 | ||
| 302 | #define PCI_NP_WDATA_OFFSET 0x08 | ||
| 303 | #define PCI_NP_RDATA_OFFSET 0x0c | ||
| 304 | #define PCI_CRP_AD_CBE_OFFSET 0x10 | ||
| 305 | #define PCI_CRP_WDATA_OFFSET 0x14 | ||
| 306 | #define PCI_CRP_RDATA_OFFSET 0x18 | ||
| 307 | #define PCI_CSR_OFFSET 0x1c | ||
| 308 | #define PCI_ISR_OFFSET 0x20 | ||
| 309 | #define PCI_INTEN_OFFSET 0x24 | ||
| 310 | #define PCI_DMACTRL_OFFSET 0x28 | ||
| 311 | #define PCI_AHBMEMBASE_OFFSET 0x2c | ||
| 312 | #define PCI_AHBIOBASE_OFFSET 0x30 | ||
| 313 | #define PCI_PCIMEMBASE_OFFSET 0x34 | ||
| 314 | #define PCI_AHBDOORBELL_OFFSET 0x38 | ||
| 315 | #define PCI_PCIDOORBELL_OFFSET 0x3C | ||
| 316 | #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 | ||
| 317 | #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 | ||
| 318 | #define PCI_ATPDMA0_LENADDR_OFFSET 0x48 | ||
| 319 | #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C | ||
| 320 | #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 | ||
| 321 | #define PCI_ATPDMA1_LENADDR_OFFSET 0x54 | ||
| 322 | |||
| 323 | /* | ||
| 324 | * PCI Control/Status Registers | ||
| 325 | */ | ||
| 326 | #define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) | ||
| 327 | |||
| 328 | #define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) | ||
| 329 | #define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) | ||
| 330 | #define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) | ||
| 331 | #define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) | ||
| 332 | #define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) | ||
| 333 | #define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) | ||
| 334 | #define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) | ||
| 335 | #define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET) | ||
| 336 | #define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET) | ||
| 337 | #define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) | ||
| 338 | #define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) | ||
| 339 | #define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) | ||
| 340 | #define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) | ||
| 341 | #define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) | ||
| 342 | #define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) | ||
| 343 | #define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) | ||
| 344 | #define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) | ||
| 345 | #define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) | ||
| 346 | #define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) | ||
| 347 | #define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) | ||
| 348 | #define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) | ||
| 349 | #define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) | ||
| 350 | |||
| 351 | /* | ||
| 352 | * PCI register values and bit definitions | ||
| 353 | */ | ||
| 354 | |||
| 355 | /* CSR bit definitions */ | ||
| 356 | #define PCI_CSR_HOST 0x00000001 | ||
| 357 | #define PCI_CSR_ARBEN 0x00000002 | ||
| 358 | #define PCI_CSR_ADS 0x00000004 | ||
| 359 | #define PCI_CSR_PDS 0x00000008 | ||
| 360 | #define PCI_CSR_ABE 0x00000010 | ||
| 361 | #define PCI_CSR_DBT 0x00000020 | ||
| 362 | #define PCI_CSR_ASE 0x00000100 | ||
| 363 | #define PCI_CSR_IC 0x00008000 | ||
| 364 | |||
| 365 | /* ISR (Interrupt status) Register bit definitions */ | ||
| 366 | #define PCI_ISR_PSE 0x00000001 | ||
| 367 | #define PCI_ISR_PFE 0x00000002 | ||
| 368 | #define PCI_ISR_PPE 0x00000004 | ||
| 369 | #define PCI_ISR_AHBE 0x00000008 | ||
| 370 | #define PCI_ISR_APDC 0x00000010 | ||
| 371 | #define PCI_ISR_PADC 0x00000020 | ||
| 372 | #define PCI_ISR_ADB 0x00000040 | ||
| 373 | #define PCI_ISR_PDB 0x00000080 | ||
| 374 | |||
| 375 | /* INTEN (Interrupt Enable) Register bit definitions */ | ||
| 376 | #define PCI_INTEN_PSE 0x00000001 | ||
| 377 | #define PCI_INTEN_PFE 0x00000002 | ||
| 378 | #define PCI_INTEN_PPE 0x00000004 | ||
| 379 | #define PCI_INTEN_AHBE 0x00000008 | ||
| 380 | #define PCI_INTEN_APDC 0x00000010 | ||
| 381 | #define PCI_INTEN_PADC 0x00000020 | ||
| 382 | #define PCI_INTEN_ADB 0x00000040 | ||
| 383 | #define PCI_INTEN_PDB 0x00000080 | ||
| 384 | |||
| 385 | /* | ||
| 386 | * Shift value for byte enable on NP cmd/byte enable register | ||
| 387 | */ | ||
| 388 | #define IXP4XX_PCI_NP_CBE_BESL 4 | ||
| 389 | |||
| 390 | /* | ||
| 391 | * PCI commands supported by NP access unit | ||
| 392 | */ | ||
| 393 | #define NP_CMD_IOREAD 0x2 | ||
| 394 | #define NP_CMD_IOWRITE 0x3 | ||
| 395 | #define NP_CMD_CONFIGREAD 0xa | ||
| 396 | #define NP_CMD_CONFIGWRITE 0xb | ||
| 397 | #define NP_CMD_MEMREAD 0x6 | ||
| 398 | #define NP_CMD_MEMWRITE 0x7 | ||
| 399 | |||
| 400 | /* | ||
| 401 | * Constants for CRP access into local config space | ||
| 402 | */ | ||
| 403 | #define CRP_AD_CBE_BESL 20 | ||
| 404 | #define CRP_AD_CBE_WRITE 0x00010000 | ||
| 405 | |||
| 406 | |||
| 407 | /* | ||
| 408 | * USB Device Controller | ||
| 409 | * | ||
| 410 | * These are used by the USB gadget driver, so they don't follow the | ||
| 411 | * IXP4XX_ naming convetions. | ||
| 412 | * | ||
| 413 | */ | ||
| 414 | # define IXP4XX_USB_REG(x) (*((volatile u32 *)(x))) | ||
| 415 | |||
| 416 | /* UDC Undocumented - Reserved1 */ | ||
| 417 | #define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004) | ||
| 418 | /* UDC Undocumented - Reserved2 */ | ||
| 419 | #define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008) | ||
| 420 | /* UDC Undocumented - Reserved3 */ | ||
| 421 | #define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C) | ||
| 422 | /* UDC Control Register */ | ||
| 423 | #define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000) | ||
| 424 | /* UDC Endpoint 0 Control/Status Register */ | ||
| 425 | #define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010) | ||
| 426 | /* UDC Endpoint 1 (IN) Control/Status Register */ | ||
| 427 | #define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014) | ||
| 428 | /* UDC Endpoint 2 (OUT) Control/Status Register */ | ||
| 429 | #define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018) | ||
| 430 | /* UDC Endpoint 3 (IN) Control/Status Register */ | ||
| 431 | #define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C) | ||
| 432 | /* UDC Endpoint 4 (OUT) Control/Status Register */ | ||
| 433 | #define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020) | ||
| 434 | /* UDC Endpoint 5 (Interrupt) Control/Status Register */ | ||
| 435 | #define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024) | ||
| 436 | /* UDC Endpoint 6 (IN) Control/Status Register */ | ||
| 437 | #define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028) | ||
| 438 | /* UDC Endpoint 7 (OUT) Control/Status Register */ | ||
| 439 | #define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C) | ||
| 440 | /* UDC Endpoint 8 (IN) Control/Status Register */ | ||
| 441 | #define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030) | ||
| 442 | /* UDC Endpoint 9 (OUT) Control/Status Register */ | ||
| 443 | #define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034) | ||
| 444 | /* UDC Endpoint 10 (Interrupt) Control/Status Register */ | ||
| 445 | #define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038) | ||
| 446 | /* UDC Endpoint 11 (IN) Control/Status Register */ | ||
| 447 | #define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C) | ||
| 448 | /* UDC Endpoint 12 (OUT) Control/Status Register */ | ||
| 449 | #define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040) | ||
| 450 | /* UDC Endpoint 13 (IN) Control/Status Register */ | ||
| 451 | #define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044) | ||
| 452 | /* UDC Endpoint 14 (OUT) Control/Status Register */ | ||
| 453 | #define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048) | ||
| 454 | /* UDC Endpoint 15 (Interrupt) Control/Status Register */ | ||
| 455 | #define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C) | ||
| 456 | /* UDC Frame Number Register High */ | ||
| 457 | #define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060) | ||
| 458 | /* UDC Frame Number Register Low */ | ||
| 459 | #define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064) | ||
| 460 | /* UDC Byte Count Reg 2 */ | ||
| 461 | #define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068) | ||
| 462 | /* UDC Byte Count Reg 4 */ | ||
| 463 | #define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c) | ||
| 464 | /* UDC Byte Count Reg 7 */ | ||
| 465 | #define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070) | ||
| 466 | /* UDC Byte Count Reg 9 */ | ||
| 467 | #define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074) | ||
| 468 | /* UDC Byte Count Reg 12 */ | ||
| 469 | #define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078) | ||
| 470 | /* UDC Byte Count Reg 14 */ | ||
| 471 | #define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c) | ||
| 472 | /* UDC Endpoint 0 Data Register */ | ||
| 473 | #define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080) | ||
| 474 | /* UDC Endpoint 1 Data Register */ | ||
| 475 | #define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100) | ||
| 476 | /* UDC Endpoint 2 Data Register */ | ||
| 477 | #define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180) | ||
| 478 | /* UDC Endpoint 3 Data Register */ | ||
| 479 | #define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200) | ||
| 480 | /* UDC Endpoint 4 Data Register */ | ||
| 481 | #define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400) | ||
| 482 | /* UDC Endpoint 5 Data Register */ | ||
| 483 | #define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0) | ||
| 484 | /* UDC Endpoint 6 Data Register */ | ||
| 485 | #define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600) | ||
| 486 | /* UDC Endpoint 7 Data Register */ | ||
| 487 | #define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680) | ||
| 488 | /* UDC Endpoint 8 Data Register */ | ||
| 489 | #define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700) | ||
| 490 | /* UDC Endpoint 9 Data Register */ | ||
| 491 | #define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900) | ||
| 492 | /* UDC Endpoint 10 Data Register */ | ||
| 493 | #define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0) | ||
| 494 | /* UDC Endpoint 11 Data Register */ | ||
| 495 | #define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00) | ||
| 496 | /* UDC Endpoint 12 Data Register */ | ||
| 497 | #define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80) | ||
| 498 | /* UDC Endpoint 13 Data Register */ | ||
| 499 | #define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00) | ||
| 500 | /* UDC Endpoint 14 Data Register */ | ||
| 501 | #define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00) | ||
| 502 | /* UDC Endpoint 15 Data Register */ | ||
| 503 | #define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0) | ||
| 504 | /* UDC Interrupt Control Register 0 */ | ||
| 505 | #define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050) | ||
| 506 | /* UDC Interrupt Control Register 1 */ | ||
| 507 | #define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054) | ||
| 508 | /* UDC Status Interrupt Register 0 */ | ||
| 509 | #define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058) | ||
| 510 | /* UDC Status Interrupt Register 1 */ | ||
| 511 | #define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C) | ||
| 512 | |||
| 513 | #define UDCCR_UDE (1 << 0) /* UDC enable */ | ||
| 514 | #define UDCCR_UDA (1 << 1) /* UDC active */ | ||
| 515 | #define UDCCR_RSM (1 << 2) /* Device resume */ | ||
| 516 | #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ | ||
| 517 | #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ | ||
| 518 | #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ | ||
| 519 | #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ | ||
| 520 | #define UDCCR_REM (1 << 7) /* Reset interrupt mask */ | ||
| 521 | |||
| 522 | #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ | ||
| 523 | #define UDCCS0_IPR (1 << 1) /* IN packet ready */ | ||
| 524 | #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ | ||
| 525 | #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ | ||
| 526 | #define UDCCS0_SST (1 << 4) /* Sent stall */ | ||
| 527 | #define UDCCS0_FST (1 << 5) /* Force stall */ | ||
| 528 | #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ | ||
| 529 | #define UDCCS0_SA (1 << 7) /* Setup active */ | ||
| 530 | |||
| 531 | #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ | ||
| 532 | #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ | ||
| 533 | #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ | ||
| 534 | #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
| 535 | #define UDCCS_BI_SST (1 << 4) /* Sent stall */ | ||
| 536 | #define UDCCS_BI_FST (1 << 5) /* Force stall */ | ||
| 537 | #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ | ||
| 538 | |||
| 539 | #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ | ||
| 540 | #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ | ||
| 541 | #define UDCCS_BO_DME (1 << 3) /* DMA enable */ | ||
| 542 | #define UDCCS_BO_SST (1 << 4) /* Sent stall */ | ||
| 543 | #define UDCCS_BO_FST (1 << 5) /* Force stall */ | ||
| 544 | #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ | ||
| 545 | #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ | ||
| 546 | |||
| 547 | #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ | ||
| 548 | #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ | ||
| 549 | #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ | ||
| 550 | #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
| 551 | #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ | ||
| 552 | |||
| 553 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ | ||
| 554 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ | ||
| 555 | #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ | ||
| 556 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ | ||
| 557 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ | ||
| 558 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ | ||
| 559 | |||
| 560 | #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ | ||
| 561 | #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ | ||
| 562 | #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ | ||
| 563 | #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
| 564 | #define UDCCS_INT_SST (1 << 4) /* Sent stall */ | ||
| 565 | #define UDCCS_INT_FST (1 << 5) /* Force stall */ | ||
| 566 | #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ | ||
| 567 | |||
| 568 | #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ | ||
| 569 | #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ | ||
| 570 | #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ | ||
| 571 | #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ | ||
| 572 | #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ | ||
| 573 | #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ | ||
| 574 | #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ | ||
| 575 | #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ | ||
| 576 | |||
| 577 | #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ | ||
| 578 | #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ | ||
| 579 | #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ | ||
| 580 | #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ | ||
| 581 | #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ | ||
| 582 | #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ | ||
| 583 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ | ||
| 584 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ | ||
| 585 | |||
| 586 | #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ | ||
| 587 | #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ | ||
| 588 | #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ | ||
| 589 | #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ | ||
| 590 | #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ | ||
| 591 | #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ | ||
| 592 | #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ | ||
| 593 | #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ | ||
| 594 | |||
| 595 | #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ | ||
| 596 | #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ | ||
| 597 | #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ | ||
| 598 | #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ | ||
| 599 | #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ | ||
| 600 | #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ | ||
| 601 | #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ | ||
| 602 | #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ | ||
| 603 | |||
| 604 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | ||
| 605 | |||
| 606 | /* "fuse" bits of IXP_EXP_CFG2 */ | ||
| 607 | #define IXP4XX_FEATURE_RCOMP (1 << 0) | ||
| 608 | #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) | ||
| 609 | #define IXP4XX_FEATURE_HASH (1 << 2) | ||
| 610 | #define IXP4XX_FEATURE_AES (1 << 3) | ||
| 611 | #define IXP4XX_FEATURE_DES (1 << 4) | ||
| 612 | #define IXP4XX_FEATURE_HDLC (1 << 5) | ||
| 613 | #define IXP4XX_FEATURE_AAL (1 << 6) | ||
| 614 | #define IXP4XX_FEATURE_HSS (1 << 7) | ||
| 615 | #define IXP4XX_FEATURE_UTOPIA (1 << 8) | ||
| 616 | #define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9) | ||
| 617 | #define IXP4XX_FEATURE_NPEC_ETH (1 << 10) | ||
| 618 | #define IXP4XX_FEATURE_RESET_NPEA (1 << 11) | ||
| 619 | #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) | ||
| 620 | #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) | ||
| 621 | #define IXP4XX_FEATURE_PCI (1 << 14) | ||
| 622 | #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) | ||
| 623 | #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) | ||
| 624 | #define IXP4XX_FEATURE_USB_HOST (1 << 18) | ||
| 625 | #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) | ||
| 626 | #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) | ||
| 627 | #define IXP4XX_FEATURE_RSA (1 << 21) | ||
| 628 | #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) | ||
| 629 | #define IXP4XX_FEATURE_RESERVED (0xFF << 24) | ||
| 630 | |||
| 631 | #define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \ | ||
| 632 | IXP4XX_FEATURE_USB_HOST | \ | ||
| 633 | IXP4XX_FEATURE_NPEA_ETH | \ | ||
| 634 | IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ | ||
| 635 | IXP4XX_FEATURE_RSA | \ | ||
| 636 | IXP4XX_FEATURE_XSCALE_MAX_FREQ) | ||
| 637 | |||
| 638 | #endif | ||
diff --git a/include/asm-arm/arch-ixp4xx/memory.h b/include/asm-arm/arch-ixp4xx/memory.h deleted file mode 100644 index af9667b57ab3..000000000000 --- a/include/asm-arm/arch-ixp4xx/memory.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp4xx/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2001-2004 MontaVista Software, Inc. | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 8 | #define __ASM_ARCH_MEMORY_H | ||
| 9 | |||
| 10 | #include <asm/sizes.h> | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Physical DRAM offset. | ||
| 14 | */ | ||
| 15 | #define PHYS_OFFSET UL(0x00000000) | ||
| 16 | |||
| 17 | #if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) | ||
| 18 | |||
| 19 | void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes); | ||
| 20 | |||
| 21 | #define arch_adjust_zones(node, size, holes) \ | ||
| 22 | ixp4xx_adjust_zones(node, size, holes) | ||
| 23 | |||
| 24 | #define ISA_DMA_THRESHOLD (SZ_64M - 1) | ||
| 25 | |||
| 26 | #endif | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Virtual view <-> DMA view memory address translations | ||
| 30 | * virt_to_bus: Used to translate the virtual address to an | ||
| 31 | * address suitable to be passed to set_dma_addr | ||
| 32 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 33 | * to an address that the kernel can use. | ||
| 34 | * | ||
| 35 | * These are dummies for now. | ||
| 36 | */ | ||
| 37 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 38 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 39 | |||
| 40 | #endif | ||
diff --git a/include/asm-arm/arch-ixp4xx/nas100d.h b/include/asm-arm/arch-ixp4xx/nas100d.h deleted file mode 100644 index ecb12d66399c..000000000000 --- a/include/asm-arm/arch-ixp4xx/nas100d.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/nas100d.h | ||
| 3 | * | ||
| 4 | * NAS100D platform specific definitions | ||
| 5 | * | ||
| 6 | * Copyright (c) 2005 Tower Technologies | ||
| 7 | * | ||
| 8 | * Author: Alessandro Zummo <a.zummo@towertech.it> | ||
| 9 | * | ||
| 10 | * based on ixdp425.h: | ||
| 11 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
| 12 | * | ||
| 13 | * This file is licensed under the terms of the GNU General Public | ||
| 14 | * License version 2. This program is licensed "as is" without any | ||
| 15 | * warranty of any kind, whether express or implied. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 19 | #error "Do not include this directly, instead #include <asm/arch/hardware.h>" | ||
| 20 | #endif | ||
| 21 | |||
| 22 | #define NAS100D_SDA_PIN 5 | ||
| 23 | #define NAS100D_SCL_PIN 6 | ||
| 24 | |||
| 25 | /* | ||
| 26 | * NAS100D PCI IRQs | ||
| 27 | */ | ||
| 28 | #define NAS100D_PCI_MAX_DEV 3 | ||
| 29 | #define NAS100D_PCI_IRQ_LINES 3 | ||
| 30 | |||
| 31 | |||
| 32 | /* PCI controller GPIO to IRQ pin mappings */ | ||
| 33 | #define NAS100D_PCI_INTA_PIN 11 | ||
| 34 | #define NAS100D_PCI_INTB_PIN 10 | ||
| 35 | #define NAS100D_PCI_INTC_PIN 9 | ||
| 36 | #define NAS100D_PCI_INTD_PIN 8 | ||
| 37 | #define NAS100D_PCI_INTE_PIN 7 | ||
| 38 | |||
| 39 | /* Buttons */ | ||
| 40 | |||
| 41 | #define NAS100D_PB_GPIO 14 /* power button */ | ||
| 42 | #define NAS100D_RB_GPIO 4 /* reset button */ | ||
| 43 | |||
| 44 | /* Power control */ | ||
| 45 | |||
| 46 | #define NAS100D_PO_GPIO 12 /* power off */ | ||
| 47 | |||
| 48 | /* LEDs */ | ||
| 49 | |||
| 50 | #define NAS100D_LED_WLAN_GPIO 0 | ||
| 51 | #define NAS100D_LED_DISK_GPIO 3 | ||
| 52 | #define NAS100D_LED_PWR_GPIO 15 | ||
diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h deleted file mode 100644 index 37d0511689dc..000000000000 --- a/include/asm-arm/arch-ixp4xx/npe.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | #ifndef __IXP4XX_NPE_H | ||
| 2 | #define __IXP4XX_NPE_H | ||
| 3 | |||
| 4 | #include <linux/kernel.h> | ||
| 5 | |||
| 6 | extern const char *npe_names[]; | ||
| 7 | |||
| 8 | struct npe_regs { | ||
| 9 | u32 exec_addr, exec_data, exec_status_cmd, exec_count; | ||
| 10 | u32 action_points[4]; | ||
| 11 | u32 watchpoint_fifo, watch_count; | ||
| 12 | u32 profile_count; | ||
| 13 | u32 messaging_status, messaging_control; | ||
| 14 | u32 mailbox_status, /*messaging_*/ in_out_fifo; | ||
| 15 | }; | ||
| 16 | |||
| 17 | struct npe { | ||
| 18 | struct resource *mem_res; | ||
| 19 | struct npe_regs __iomem *regs; | ||
| 20 | u32 regs_phys; | ||
| 21 | int id; | ||
| 22 | int valid; | ||
| 23 | }; | ||
| 24 | |||
| 25 | |||
| 26 | static inline const char *npe_name(struct npe *npe) | ||
| 27 | { | ||
| 28 | return npe_names[npe->id]; | ||
| 29 | } | ||
| 30 | |||
| 31 | int npe_running(struct npe *npe); | ||
| 32 | int npe_send_message(struct npe *npe, const void *msg, const char *what); | ||
| 33 | int npe_recv_message(struct npe *npe, void *msg, const char *what); | ||
| 34 | int npe_send_recv_message(struct npe *npe, void *msg, const char *what); | ||
| 35 | int npe_load_firmware(struct npe *npe, const char *name, struct device *dev); | ||
| 36 | struct npe *npe_request(int id); | ||
| 37 | void npe_release(struct npe *npe); | ||
| 38 | |||
| 39 | #endif /* __IXP4XX_NPE_H */ | ||
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h deleted file mode 100644 index fa895f44e431..000000000000 --- a/include/asm-arm/arch-ixp4xx/nslu2.h +++ /dev/null | |||
| @@ -1,55 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/nslu2.h | ||
| 3 | * | ||
| 4 | * NSLU2 platform specific definitions | ||
| 5 | * | ||
| 6 | * Author: Mark Rakes <mrakes AT mac.com> | ||
| 7 | * Maintainers: http://www.nslu2-linux.org | ||
| 8 | * | ||
| 9 | * based on ixdp425.h: | ||
| 10 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
| 11 | * | ||
| 12 | * This file is licensed under the terms of the GNU General Public | ||
| 13 | * License version 2. This program is licensed "as is" without any | ||
| 14 | * warranty of any kind, whether express or implied. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 18 | #error "Do not include this directly, instead #include <asm/arch/hardware.h>" | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #define NSLU2_SDA_PIN 7 | ||
| 22 | #define NSLU2_SCL_PIN 6 | ||
| 23 | |||
| 24 | /* | ||
| 25 | * NSLU2 PCI IRQs | ||
| 26 | */ | ||
| 27 | #define NSLU2_PCI_MAX_DEV 3 | ||
| 28 | #define NSLU2_PCI_IRQ_LINES 3 | ||
| 29 | |||
| 30 | |||
| 31 | /* PCI controller GPIO to IRQ pin mappings */ | ||
| 32 | #define NSLU2_PCI_INTA_PIN 11 | ||
| 33 | #define NSLU2_PCI_INTB_PIN 10 | ||
| 34 | #define NSLU2_PCI_INTC_PIN 9 | ||
| 35 | #define NSLU2_PCI_INTD_PIN 8 | ||
| 36 | |||
| 37 | /* NSLU2 Timer */ | ||
| 38 | #define NSLU2_FREQ 66000000 | ||
| 39 | |||
| 40 | /* Buttons */ | ||
| 41 | |||
| 42 | #define NSLU2_PB_GPIO 5 /* power button */ | ||
| 43 | #define NSLU2_PO_GPIO 8 /* power off */ | ||
| 44 | #define NSLU2_RB_GPIO 12 /* reset button */ | ||
| 45 | |||
| 46 | /* Buzzer */ | ||
| 47 | |||
| 48 | #define NSLU2_GPIO_BUZZ 4 | ||
| 49 | |||
| 50 | /* LEDs */ | ||
| 51 | |||
| 52 | #define NSLU2_LED_RED_GPIO 0 | ||
| 53 | #define NSLU2_LED_GRN_GPIO 1 | ||
| 54 | #define NSLU2_LED_DISK1_GPIO 3 | ||
| 55 | #define NSLU2_LED_DISK2_GPIO 2 | ||
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h deleted file mode 100644 index b2af5154cef3..000000000000 --- a/include/asm-arm/arch-ixp4xx/platform.h +++ /dev/null | |||
| @@ -1,173 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/platform.h | ||
| 3 | * | ||
| 4 | * Constants and functions that are useful to IXP4xx platform-specific code | ||
| 5 | * and device drivers. | ||
| 6 | * | ||
| 7 | * Copyright (C) 2004 MontaVista Software, Inc. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 11 | #error "Do not include this directly, instead #include <asm/arch/hardware.h>" | ||
| 12 | #endif | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | |||
| 16 | #include <asm/types.h> | ||
| 17 | |||
| 18 | #ifndef __ARMEB__ | ||
| 19 | #define REG_OFFSET 0 | ||
| 20 | #else | ||
| 21 | #define REG_OFFSET 3 | ||
| 22 | #endif | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Expansion bus memory regions | ||
| 26 | */ | ||
| 27 | #define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000) | ||
| 28 | |||
| 29 | /* | ||
| 30 | * The expansion bus on the IXP4xx can be configured for either 16 or | ||
| 31 | * 32MB windows and the CS offset for each region changes based on the | ||
| 32 | * current configuration. This means that we cannot simply hardcode | ||
| 33 | * each offset. ixp4xx_sys_init() looks at the expansion bus configuration | ||
| 34 | * as setup by the bootloader to determine our window size. | ||
| 35 | */ | ||
| 36 | extern unsigned long ixp4xx_exp_bus_size; | ||
| 37 | |||
| 38 | #define IXP4XX_EXP_BUS_BASE(region)\ | ||
| 39 | (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size)) | ||
| 40 | |||
| 41 | #define IXP4XX_EXP_BUS_END(region)\ | ||
| 42 | (IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1) | ||
| 43 | |||
| 44 | /* Those macros can be used to adjust timing and configure | ||
| 45 | * other features for each region. | ||
| 46 | */ | ||
| 47 | |||
| 48 | #define IXP4XX_EXP_BUS_RECOVERY_T(x) (((x) & 0x0f) << 16) | ||
| 49 | #define IXP4XX_EXP_BUS_HOLD_T(x) (((x) & 0x03) << 20) | ||
| 50 | #define IXP4XX_EXP_BUS_STROBE_T(x) (((x) & 0x0f) << 22) | ||
| 51 | #define IXP4XX_EXP_BUS_SETUP_T(x) (((x) & 0x03) << 26) | ||
| 52 | #define IXP4XX_EXP_BUS_ADDR_T(x) (((x) & 0x03) << 28) | ||
| 53 | #define IXP4XX_EXP_BUS_SIZE(x) (((x) & 0x0f) << 10) | ||
| 54 | #define IXP4XX_EXP_BUS_CYCLES(x) (((x) & 0x03) << 14) | ||
| 55 | |||
| 56 | #define IXP4XX_EXP_BUS_CS_EN (1L << 31) | ||
| 57 | #define IXP4XX_EXP_BUS_BYTE_RD16 (1L << 6) | ||
| 58 | #define IXP4XX_EXP_BUS_HRDY_POL (1L << 5) | ||
| 59 | #define IXP4XX_EXP_BUS_MUX_EN (1L << 4) | ||
| 60 | #define IXP4XX_EXP_BUS_SPLT_EN (1L << 3) | ||
| 61 | #define IXP4XX_EXP_BUS_WR_EN (1L << 1) | ||
| 62 | #define IXP4XX_EXP_BUS_BYTE_EN (1L << 0) | ||
| 63 | |||
| 64 | #define IXP4XX_EXP_BUS_CYCLES_INTEL 0x00 | ||
| 65 | #define IXP4XX_EXP_BUS_CYCLES_MOTOROLA 0x01 | ||
| 66 | #define IXP4XX_EXP_BUS_CYCLES_HPI 0x02 | ||
| 67 | |||
| 68 | #define IXP4XX_FLASH_WRITABLE (0x2) | ||
| 69 | #define IXP4XX_FLASH_DEFAULT (0xbcd23c40) | ||
| 70 | #define IXP4XX_FLASH_WRITE (0xbcd23c42) | ||
| 71 | |||
| 72 | /* | ||
| 73 | * Clock Speed Definitions. | ||
| 74 | */ | ||
| 75 | #define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ | ||
| 76 | #define IXP4XX_UART_XTAL 14745600 | ||
| 77 | |||
| 78 | /* | ||
| 79 | * This structure provide a means for the board setup code | ||
| 80 | * to give information to th pata_ixp4xx driver. It is | ||
| 81 | * passed as platform_data. | ||
| 82 | */ | ||
| 83 | struct ixp4xx_pata_data { | ||
| 84 | volatile u32 *cs0_cfg; | ||
| 85 | volatile u32 *cs1_cfg; | ||
| 86 | unsigned long cs0_bits; | ||
| 87 | unsigned long cs1_bits; | ||
| 88 | void __iomem *cs0; | ||
| 89 | void __iomem *cs1; | ||
| 90 | }; | ||
| 91 | |||
| 92 | struct sys_timer; | ||
| 93 | |||
| 94 | #define IXP4XX_ETH_NPEA 0x00 | ||
| 95 | #define IXP4XX_ETH_NPEB 0x10 | ||
| 96 | #define IXP4XX_ETH_NPEC 0x20 | ||
| 97 | |||
| 98 | /* Information about built-in Ethernet MAC interfaces */ | ||
| 99 | struct eth_plat_info { | ||
| 100 | u8 phy; /* MII PHY ID, 0 - 31 */ | ||
| 101 | u8 rxq; /* configurable, currently 0 - 31 only */ | ||
| 102 | u8 txreadyq; | ||
| 103 | u8 hwaddr[6]; | ||
| 104 | }; | ||
| 105 | |||
| 106 | /* Information about built-in HSS (synchronous serial) interfaces */ | ||
| 107 | struct hss_plat_info { | ||
| 108 | int (*set_clock)(int port, unsigned int clock_type); | ||
| 109 | int (*open)(int port, void *pdev, | ||
| 110 | void (*set_carrier_cb)(void *pdev, int carrier)); | ||
| 111 | void (*close)(int port, void *pdev); | ||
| 112 | u8 txreadyq; | ||
| 113 | }; | ||
| 114 | |||
| 115 | /* | ||
| 116 | * Frequency of clock used for primary clocksource | ||
| 117 | */ | ||
| 118 | extern unsigned long ixp4xx_timer_freq; | ||
| 119 | |||
| 120 | /* | ||
| 121 | * Functions used by platform-level setup code | ||
| 122 | */ | ||
| 123 | extern void ixp4xx_map_io(void); | ||
| 124 | extern void ixp4xx_init_irq(void); | ||
| 125 | extern void ixp4xx_sys_init(void); | ||
| 126 | extern void ixp4xx_timer_init(void); | ||
| 127 | extern struct sys_timer ixp4xx_timer; | ||
| 128 | extern void ixp4xx_pci_preinit(void); | ||
| 129 | struct pci_sys_data; | ||
| 130 | extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); | ||
| 131 | extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); | ||
| 132 | |||
| 133 | /* | ||
| 134 | * GPIO-functions | ||
| 135 | */ | ||
| 136 | /* | ||
| 137 | * The following converted to the real HW bits the gpio_line_config | ||
| 138 | */ | ||
| 139 | /* GPIO pin types */ | ||
| 140 | #define IXP4XX_GPIO_OUT 0x1 | ||
| 141 | #define IXP4XX_GPIO_IN 0x2 | ||
| 142 | |||
| 143 | /* GPIO signal types */ | ||
| 144 | #define IXP4XX_GPIO_LOW 0 | ||
| 145 | #define IXP4XX_GPIO_HIGH 1 | ||
| 146 | |||
| 147 | /* GPIO Clocks */ | ||
| 148 | #define IXP4XX_GPIO_CLK_0 14 | ||
| 149 | #define IXP4XX_GPIO_CLK_1 15 | ||
| 150 | |||
| 151 | static inline void gpio_line_config(u8 line, u32 direction) | ||
| 152 | { | ||
| 153 | if (direction == IXP4XX_GPIO_IN) | ||
| 154 | *IXP4XX_GPIO_GPOER |= (1 << line); | ||
| 155 | else | ||
| 156 | *IXP4XX_GPIO_GPOER &= ~(1 << line); | ||
| 157 | } | ||
| 158 | |||
| 159 | static inline void gpio_line_get(u8 line, int *value) | ||
| 160 | { | ||
| 161 | *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1; | ||
| 162 | } | ||
| 163 | |||
| 164 | static inline void gpio_line_set(u8 line, int value) | ||
| 165 | { | ||
| 166 | if (value == IXP4XX_GPIO_HIGH) | ||
| 167 | *IXP4XX_GPIO_GPOUTR |= (1 << line); | ||
| 168 | else if (value == IXP4XX_GPIO_LOW) | ||
| 169 | *IXP4XX_GPIO_GPOUTR &= ~(1 << line); | ||
| 170 | } | ||
| 171 | |||
| 172 | #endif // __ASSEMBLY__ | ||
| 173 | |||
diff --git a/include/asm-arm/arch-ixp4xx/prpmc1100.h b/include/asm-arm/arch-ixp4xx/prpmc1100.h deleted file mode 100644 index 100855feafdd..000000000000 --- a/include/asm-arm/arch-ixp4xx/prpmc1100.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/prpmc1100.h | ||
| 3 | * | ||
| 4 | * Motorolla PrPMC1100 platform specific definitions | ||
| 5 | * | ||
| 6 | * Author: Deepak Saxena <dsaxena@plexity.net> | ||
| 7 | * | ||
| 8 | * Copyright 2004 (c) MontaVista, Software, Inc. | ||
| 9 | * | ||
| 10 | * This file is licensed under the terms of the GNU General Public | ||
| 11 | * License version 2. This program is licensed "as is" without any | ||
| 12 | * warranty of any kind, whether express or implied. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_HARDWARE_H__ | ||
| 16 | #error "Do not include this directly, instead #include <asm/arch/hardware.h>" | ||
| 17 | #endif | ||
| 18 | |||
| 19 | #define PRPMC1100_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS | ||
| 20 | #define PRPMC1100_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE | ||
| 21 | |||
| 22 | #define PRPMC1100_PCI_MIN_DEVID 10 | ||
| 23 | #define PRPMC1100_PCI_MAX_DEVID 16 | ||
| 24 | #define PRPMC1100_PCI_IRQ_LINES 4 | ||
| 25 | |||
| 26 | |||
| 27 | /* PCI controller GPIO to IRQ pin mappings */ | ||
| 28 | #define PRPMC1100_PCI_INTA_PIN 11 | ||
| 29 | #define PRPMC1100_PCI_INTB_PIN 10 | ||
| 30 | #define PRPMC1100_PCI_INTC_PIN 9 | ||
| 31 | #define PRPMC1100_PCI_INTD_PIN 8 | ||
| 32 | |||
| 33 | |||
diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h deleted file mode 100644 index 1e52b95cede5..000000000000 --- a/include/asm-arm/arch-ixp4xx/qmgr.h +++ /dev/null | |||
| @@ -1,126 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms of version 2 of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef IXP4XX_QMGR_H | ||
| 10 | #define IXP4XX_QMGR_H | ||
| 11 | |||
| 12 | #include <linux/io.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | |||
| 15 | #define HALF_QUEUES 32 | ||
| 16 | #define QUEUES 64 /* only 32 lower queues currently supported */ | ||
| 17 | #define MAX_QUEUE_LENGTH 4 /* in dwords */ | ||
| 18 | |||
| 19 | #define QUEUE_STAT1_EMPTY 1 /* queue status bits */ | ||
| 20 | #define QUEUE_STAT1_NEARLY_EMPTY 2 | ||
| 21 | #define QUEUE_STAT1_NEARLY_FULL 4 | ||
| 22 | #define QUEUE_STAT1_FULL 8 | ||
| 23 | #define QUEUE_STAT2_UNDERFLOW 1 | ||
| 24 | #define QUEUE_STAT2_OVERFLOW 2 | ||
| 25 | |||
| 26 | #define QUEUE_WATERMARK_0_ENTRIES 0 | ||
| 27 | #define QUEUE_WATERMARK_1_ENTRY 1 | ||
| 28 | #define QUEUE_WATERMARK_2_ENTRIES 2 | ||
| 29 | #define QUEUE_WATERMARK_4_ENTRIES 3 | ||
| 30 | #define QUEUE_WATERMARK_8_ENTRIES 4 | ||
| 31 | #define QUEUE_WATERMARK_16_ENTRIES 5 | ||
| 32 | #define QUEUE_WATERMARK_32_ENTRIES 6 | ||
| 33 | #define QUEUE_WATERMARK_64_ENTRIES 7 | ||
| 34 | |||
| 35 | /* queue interrupt request conditions */ | ||
| 36 | #define QUEUE_IRQ_SRC_EMPTY 0 | ||
| 37 | #define QUEUE_IRQ_SRC_NEARLY_EMPTY 1 | ||
| 38 | #define QUEUE_IRQ_SRC_NEARLY_FULL 2 | ||
| 39 | #define QUEUE_IRQ_SRC_FULL 3 | ||
| 40 | #define QUEUE_IRQ_SRC_NOT_EMPTY 4 | ||
| 41 | #define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5 | ||
| 42 | #define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6 | ||
| 43 | #define QUEUE_IRQ_SRC_NOT_FULL 7 | ||
| 44 | |||
| 45 | struct qmgr_regs { | ||
| 46 | u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */ | ||
| 47 | u32 stat1[4]; /* 0x400 - 0x40F */ | ||
| 48 | u32 stat2[2]; /* 0x410 - 0x417 */ | ||
| 49 | u32 statne_h; /* 0x418 - queue nearly empty */ | ||
| 50 | u32 statf_h; /* 0x41C - queue full */ | ||
| 51 | u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */ | ||
| 52 | u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */ | ||
| 53 | u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */ | ||
| 54 | u32 reserved[1776]; | ||
| 55 | u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */ | ||
| 56 | }; | ||
| 57 | |||
| 58 | void qmgr_set_irq(unsigned int queue, int src, | ||
| 59 | void (*handler)(void *pdev), void *pdev); | ||
| 60 | void qmgr_enable_irq(unsigned int queue); | ||
| 61 | void qmgr_disable_irq(unsigned int queue); | ||
| 62 | |||
| 63 | /* request_ and release_queue() must be called from non-IRQ context */ | ||
| 64 | int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, | ||
| 65 | unsigned int nearly_empty_watermark, | ||
| 66 | unsigned int nearly_full_watermark); | ||
| 67 | void qmgr_release_queue(unsigned int queue); | ||
| 68 | |||
| 69 | |||
| 70 | static inline void qmgr_put_entry(unsigned int queue, u32 val) | ||
| 71 | { | ||
| 72 | extern struct qmgr_regs __iomem *qmgr_regs; | ||
| 73 | __raw_writel(val, &qmgr_regs->acc[queue][0]); | ||
| 74 | } | ||
| 75 | |||
| 76 | static inline u32 qmgr_get_entry(unsigned int queue) | ||
| 77 | { | ||
| 78 | extern struct qmgr_regs __iomem *qmgr_regs; | ||
| 79 | return __raw_readl(&qmgr_regs->acc[queue][0]); | ||
| 80 | } | ||
| 81 | |||
| 82 | static inline int qmgr_get_stat1(unsigned int queue) | ||
| 83 | { | ||
| 84 | extern struct qmgr_regs __iomem *qmgr_regs; | ||
| 85 | return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) | ||
| 86 | >> ((queue & 7) << 2)) & 0xF; | ||
| 87 | } | ||
| 88 | |||
| 89 | static inline int qmgr_get_stat2(unsigned int queue) | ||
| 90 | { | ||
| 91 | extern struct qmgr_regs __iomem *qmgr_regs; | ||
| 92 | return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) | ||
| 93 | >> ((queue & 0xF) << 1)) & 0x3; | ||
| 94 | } | ||
| 95 | |||
| 96 | static inline int qmgr_stat_empty(unsigned int queue) | ||
| 97 | { | ||
| 98 | return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY); | ||
| 99 | } | ||
| 100 | |||
| 101 | static inline int qmgr_stat_nearly_empty(unsigned int queue) | ||
| 102 | { | ||
| 103 | return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY); | ||
| 104 | } | ||
| 105 | |||
| 106 | static inline int qmgr_stat_nearly_full(unsigned int queue) | ||
| 107 | { | ||
| 108 | return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL); | ||
| 109 | } | ||
| 110 | |||
| 111 | static inline int qmgr_stat_full(unsigned int queue) | ||
| 112 | { | ||
| 113 | return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL); | ||
| 114 | } | ||
| 115 | |||
| 116 | static inline int qmgr_stat_underflow(unsigned int queue) | ||
| 117 | { | ||
| 118 | return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW); | ||
| 119 | } | ||
| 120 | |||
| 121 | static inline int qmgr_stat_overflow(unsigned int queue) | ||
| 122 | { | ||
| 123 | return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW); | ||
| 124 | } | ||
| 125 | |||
| 126 | #endif | ||
diff --git a/include/asm-arm/arch-ixp4xx/system.h b/include/asm-arm/arch-ixp4xx/system.h deleted file mode 100644 index f11b92262a07..000000000000 --- a/include/asm-arm/arch-ixp4xx/system.h +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002 Intel Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <asm/arch/hardware.h> | ||
| 13 | |||
| 14 | static inline void arch_idle(void) | ||
| 15 | { | ||
| 16 | #if 0 | ||
| 17 | if (!hlt_counter) | ||
| 18 | cpu_do_idle(0); | ||
| 19 | #endif | ||
| 20 | } | ||
| 21 | |||
| 22 | |||
| 23 | static inline void arch_reset(char mode) | ||
| 24 | { | ||
| 25 | if ( 1 && mode == 's') { | ||
| 26 | /* Jump into ROM at address 0 */ | ||
| 27 | cpu_reset(0); | ||
| 28 | } else { | ||
| 29 | /* Use on-chip reset capability */ | ||
| 30 | |||
| 31 | /* set the "key" register to enable access to | ||
| 32 | * "timer" and "enable" registers | ||
| 33 | */ | ||
| 34 | *IXP4XX_OSWK = IXP4XX_WDT_KEY; | ||
| 35 | |||
| 36 | /* write 0 to the timer register for an immediate reset */ | ||
| 37 | *IXP4XX_OSWT = 0; | ||
| 38 | |||
| 39 | *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE; | ||
| 40 | } | ||
| 41 | } | ||
| 42 | |||
diff --git a/include/asm-arm/arch-ixp4xx/timex.h b/include/asm-arm/arch-ixp4xx/timex.h deleted file mode 100644 index c2559e28cbcb..000000000000 --- a/include/asm-arm/arch-ixp4xx/timex.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp4xx/timex.h | ||
| 3 | * | ||
| 4 | */ | ||
| 5 | |||
| 6 | #include <asm/arch/hardware.h> | ||
| 7 | |||
| 8 | /* | ||
| 9 | * We use IXP425 General purpose timer for our timer needs, it runs at | ||
| 10 | * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the | ||
| 11 | * timer register ignores the bottom 2 bits of the LATCH value. | ||
| 12 | */ | ||
| 13 | #define FREQ 66666666 | ||
| 14 | #define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) | ||
| 15 | |||
diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h deleted file mode 100644 index dbdec36ff0d1..000000000000 --- a/include/asm-arm/arch-ixp4xx/udc.h +++ /dev/null | |||
| @@ -1,8 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp4xx/udc.h | ||
| 3 | * | ||
| 4 | */ | ||
| 5 | #include <asm/mach/udc_pxa2xx.h> | ||
| 6 | |||
| 7 | extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info); | ||
| 8 | |||
diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h deleted file mode 100644 index 34ef48fe327e..000000000000 --- a/include/asm-arm/arch-ixp4xx/uncompress.h +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ixp4xx/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002 Intel Corporation. | ||
| 5 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef _ARCH_UNCOMPRESS_H_ | ||
| 14 | #define _ARCH_UNCOMPRESS_H_ | ||
| 15 | |||
| 16 | #include "ixp4xx-regs.h" | ||
| 17 | #include <asm/mach-types.h> | ||
| 18 | #include <linux/serial_reg.h> | ||
| 19 | |||
| 20 | #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) | ||
| 21 | |||
| 22 | static volatile u32* uart_base; | ||
| 23 | |||
| 24 | static inline void putc(int c) | ||
| 25 | { | ||
| 26 | /* Check THRE and TEMT bits before we transmit the character. | ||
| 27 | */ | ||
| 28 | while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) | ||
| 29 | barrier(); | ||
| 30 | |||
| 31 | *uart_base = c; | ||
| 32 | } | ||
| 33 | |||
| 34 | static void flush(void) | ||
| 35 | { | ||
| 36 | } | ||
| 37 | |||
| 38 | static __inline__ void __arch_decomp_setup(unsigned long arch_id) | ||
| 39 | { | ||
| 40 | /* | ||
| 41 | * Some boards are using UART2 as console | ||
| 42 | */ | ||
| 43 | if (machine_is_adi_coyote() || machine_is_gtwx5715() || | ||
| 44 | machine_is_gateway7001() || machine_is_wg302v2()) | ||
| 45 | uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; | ||
| 46 | else | ||
| 47 | uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; | ||
| 48 | } | ||
| 49 | |||
| 50 | /* | ||
| 51 | * arch_id is a variable in decompress_kernel() | ||
| 52 | */ | ||
| 53 | #define arch_decomp_setup() __arch_decomp_setup(arch_id) | ||
| 54 | |||
| 55 | #define arch_decomp_wdog() | ||
| 56 | |||
| 57 | #endif | ||
diff --git a/include/asm-arm/arch-ixp4xx/vmalloc.h b/include/asm-arm/arch-ixp4xx/vmalloc.h deleted file mode 100644 index 050d46e6b126..000000000000 --- a/include/asm-arm/arch-ixp4xx/vmalloc.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ixp4xx/vmalloc.h | ||
| 3 | */ | ||
| 4 | #define VMALLOC_END (0xFF000000) | ||
| 5 | |||
diff --git a/include/asm-arm/arch-kirkwood/debug-macro.S b/include/asm-arm/arch-kirkwood/debug-macro.S deleted file mode 100644 index f55fb8ad9ee4..000000000000 --- a/include/asm-arm/arch-kirkwood/debug-macro.S +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/debug-macro.S | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <asm/arch/kirkwood.h> | ||
| 10 | |||
| 11 | .macro addruart,rx | ||
| 12 | mrc p15, 0, \rx, c1, c0 | ||
| 13 | tst \rx, #1 @ MMU enabled? | ||
| 14 | ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE | ||
| 15 | ldrne \rx, =KIRKWOOD_REGS_VIRT_BASE | ||
| 16 | orr \rx, \rx, #0x00012000 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | #define UART_SHIFT 2 | ||
| 20 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-kirkwood/dma.h b/include/asm-arm/arch-kirkwood/dma.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/include/asm-arm/arch-kirkwood/dma.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | /* empty */ | ||
diff --git a/include/asm-arm/arch-kirkwood/entry-macro.S b/include/asm-arm/arch-kirkwood/entry-macro.S deleted file mode 100644 index fc6a43d9355c..000000000000 --- a/include/asm-arm/arch-kirkwood/entry-macro.S +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for Marvell Kirkwood platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/arch/kirkwood.h> | ||
| 12 | |||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro get_irqnr_preamble, base, tmp | ||
| 20 | ldr \base, =IRQ_VIRT_BASE | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 24 | @ check low interrupts | ||
| 25 | ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] | ||
| 26 | ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] | ||
| 27 | mov \irqnr, #31 | ||
| 28 | ands \irqstat, \irqstat, \tmp | ||
| 29 | bne 1001f | ||
| 30 | |||
| 31 | @ if no low interrupts set, check high interrupts | ||
| 32 | ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] | ||
| 33 | ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF] | ||
| 34 | mov \irqnr, #63 | ||
| 35 | ands \irqstat, \irqstat, \tmp | ||
| 36 | |||
| 37 | @ find first active interrupt source | ||
| 38 | 1001: clzne \irqstat, \irqstat | ||
| 39 | subne \irqnr, \irqnr, \irqstat | ||
| 40 | .endm | ||
diff --git a/include/asm-arm/arch-kirkwood/hardware.h b/include/asm-arm/arch-kirkwood/hardware.h deleted file mode 100644 index e695719771a5..000000000000 --- a/include/asm-arm/arch-kirkwood/hardware.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/hardware.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 10 | #define __ASM_ARCH_HARDWARE_H | ||
| 11 | |||
| 12 | #include "kirkwood.h" | ||
| 13 | |||
| 14 | #define pcibios_assign_all_busses() 1 | ||
| 15 | |||
| 16 | #define PCIBIOS_MIN_IO 0x00001000 | ||
| 17 | #define PCIBIOS_MIN_MEM 0x01000000 | ||
| 18 | #define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */ | ||
| 19 | |||
| 20 | |||
| 21 | #endif | ||
diff --git a/include/asm-arm/arch-kirkwood/io.h b/include/asm-arm/arch-kirkwood/io.h deleted file mode 100644 index 0ef6e95f5d5b..000000000000 --- a/include/asm-arm/arch-kirkwood/io.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/io.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_IO_H | ||
| 10 | #define __ASM_ARCH_IO_H | ||
| 11 | |||
| 12 | #include "kirkwood.h" | ||
| 13 | |||
| 14 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 15 | |||
| 16 | static inline void __iomem *__io(unsigned long addr) | ||
| 17 | { | ||
| 18 | return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE) | ||
| 19 | + KIRKWOOD_PCIE_IO_VIRT_BASE); | ||
| 20 | } | ||
| 21 | |||
| 22 | #define __io(a) __io(a) | ||
| 23 | #define __mem_pci(a) (a) | ||
| 24 | |||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-arm/arch-kirkwood/irqs.h b/include/asm-arm/arch-kirkwood/irqs.h deleted file mode 100644 index 2e7b5da6335c..000000000000 --- a/include/asm-arm/arch-kirkwood/irqs.h +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ definitions for Marvell Kirkwood SoCs | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_IRQS_H | ||
| 12 | #define __ASM_ARCH_IRQS_H | ||
| 13 | |||
| 14 | #include "kirkwood.h" /* need GPIO_MAX */ | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Low Interrupt Controller | ||
| 18 | */ | ||
| 19 | #define IRQ_KIRKWOOD_HIGH_SUM 0 | ||
| 20 | #define IRQ_KIRKWOOD_BRIDGE 1 | ||
| 21 | #define IRQ_KIRKWOOD_HOST2CPU 2 | ||
| 22 | #define IRQ_KIRKWOOD_CPU2HOST 3 | ||
| 23 | #define IRQ_KIRKWOOD_XOR_00 5 | ||
| 24 | #define IRQ_KIRKWOOD_XOR_01 6 | ||
| 25 | #define IRQ_KIRKWOOD_XOR_10 7 | ||
| 26 | #define IRQ_KIRKWOOD_XOR_11 8 | ||
| 27 | #define IRQ_KIRKWOOD_PCIE 9 | ||
| 28 | #define IRQ_KIRKWOOD_GE00_SUM 11 | ||
| 29 | #define IRQ_KIRKWOOD_GE01_SUM 15 | ||
| 30 | #define IRQ_KIRKWOOD_USB 19 | ||
| 31 | #define IRQ_KIRKWOOD_SATA 21 | ||
| 32 | #define IRQ_KIRKWOOD_CRYPTO 22 | ||
| 33 | #define IRQ_KIRKWOOD_SPI 23 | ||
| 34 | #define IRQ_KIRKWOOD_I2S 24 | ||
| 35 | #define IRQ_KIRKWOOD_TS_0 26 | ||
| 36 | #define IRQ_KIRKWOOD_SDIO 28 | ||
| 37 | #define IRQ_KIRKWOOD_TWSI 29 | ||
| 38 | #define IRQ_KIRKWOOD_AVB 30 | ||
| 39 | #define IRQ_KIRKWOOD_TDMI 31 | ||
| 40 | |||
| 41 | /* | ||
| 42 | * High Interrupt Controller | ||
| 43 | */ | ||
| 44 | #define IRQ_KIRKWOOD_UART_0 33 | ||
| 45 | #define IRQ_KIRKWOOD_UART_1 34 | ||
| 46 | #define IRQ_KIRKWOOD_GPIO_LOW_0_7 35 | ||
| 47 | #define IRQ_KIRKWOOD_GPIO_LOW_8_15 36 | ||
| 48 | #define IRQ_KIRKWOOD_GPIO_LOW_16_23 37 | ||
| 49 | #define IRQ_KIRKWOOD_GPIO_LOW_24_31 38 | ||
| 50 | #define IRQ_KIRKWOOD_GPIO_HIGH_0_7 39 | ||
| 51 | #define IRQ_KIRKWOOD_GPIO_HIGH_8_15 40 | ||
| 52 | #define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41 | ||
| 53 | |||
| 54 | /* | ||
| 55 | * KIRKWOOD General Purpose Pins | ||
| 56 | */ | ||
| 57 | #define IRQ_KIRKWOOD_GPIO_START 64 | ||
| 58 | #define NR_GPIO_IRQS GPIO_MAX | ||
| 59 | |||
| 60 | #define NR_IRQS (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS) | ||
| 61 | |||
| 62 | |||
| 63 | #endif | ||
diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h deleted file mode 100644 index bb31b315c350..000000000000 --- a/include/asm-arm/arch-kirkwood/kirkwood.h +++ /dev/null | |||
| @@ -1,100 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/kirkwood.h | ||
| 3 | * | ||
| 4 | * Generic definitions for Marvell Kirkwood SoC flavors: | ||
| 5 | * 88F6180, 88F6192 and 88F6281. | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_KIRKWOOD_H | ||
| 13 | #define __ASM_ARCH_KIRKWOOD_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Marvell Kirkwood address maps. | ||
| 17 | * | ||
| 18 | * phys | ||
| 19 | * e0000000 PCIe Memory space | ||
| 20 | * f1000000 on-chip peripheral registers | ||
| 21 | * f2000000 PCIe I/O space | ||
| 22 | * f3000000 NAND controller address window | ||
| 23 | * | ||
| 24 | * virt phys size | ||
| 25 | * fee00000 f1000000 1M on-chip peripheral registers | ||
| 26 | * fef00000 f2000000 1M PCIe I/O space | ||
| 27 | */ | ||
| 28 | |||
| 29 | #define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 | ||
| 30 | #define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K | ||
| 31 | * is the minimal window size | ||
| 32 | */ | ||
| 33 | |||
| 34 | #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 | ||
| 35 | #define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 | ||
| 36 | #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 | ||
| 37 | #define KIRKWOOD_PCIE_IO_SIZE SZ_1M | ||
| 38 | |||
| 39 | #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 | ||
| 40 | #define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 | ||
| 41 | #define KIRKWOOD_REGS_SIZE SZ_1M | ||
| 42 | |||
| 43 | #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 | ||
| 44 | #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M | ||
| 45 | |||
| 46 | /* | ||
| 47 | * MBUS bridge registers. | ||
| 48 | */ | ||
| 49 | #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) | ||
| 50 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | ||
| 51 | #define CPU_RESET 0x00000002 | ||
| 52 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
| 53 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
| 54 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
| 55 | #define SOFT_RESET 0x00000001 | ||
| 56 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
| 57 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
| 58 | #define BRIDGE_INT_TIMER0 0x0002 | ||
| 59 | #define BRIDGE_INT_TIMER1 0x0004 | ||
| 60 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | ||
| 61 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
| 62 | #define IRQ_CAUSE_LOW_OFF 0x0000 | ||
| 63 | #define IRQ_MASK_LOW_OFF 0x0004 | ||
| 64 | #define IRQ_CAUSE_HIGH_OFF 0x0010 | ||
| 65 | #define IRQ_MASK_HIGH_OFF 0x0014 | ||
| 66 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
| 67 | #define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) | ||
| 68 | #define L2_WRITETHROUGH 0x00000010 | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Register Map | ||
| 72 | */ | ||
| 73 | #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) | ||
| 74 | #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) | ||
| 75 | |||
| 76 | #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) | ||
| 77 | #define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) | ||
| 78 | #define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) | ||
| 79 | #define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) | ||
| 80 | #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) | ||
| 81 | #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) | ||
| 82 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) | ||
| 83 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | ||
| 84 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | ||
| 85 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) | ||
| 86 | |||
| 87 | #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) | ||
| 88 | |||
| 89 | #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) | ||
| 90 | |||
| 91 | #define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) | ||
| 92 | #define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) | ||
| 93 | |||
| 94 | #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) | ||
| 95 | |||
| 96 | |||
| 97 | #define GPIO_MAX 50 | ||
| 98 | |||
| 99 | |||
| 100 | #endif | ||
diff --git a/include/asm-arm/arch-kirkwood/memory.h b/include/asm-arm/arch-kirkwood/memory.h deleted file mode 100644 index e5108f408ce6..000000000000 --- a/include/asm-arm/arch-kirkwood/memory.h +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/memory.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 6 | #define __ASM_ARCH_MEMORY_H | ||
| 7 | |||
| 8 | #define PHYS_OFFSET UL(0x00000000) | ||
| 9 | |||
| 10 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 11 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 12 | |||
| 13 | |||
| 14 | #endif | ||
diff --git a/include/asm-arm/arch-kirkwood/system.h b/include/asm-arm/arch-kirkwood/system.h deleted file mode 100644 index 8dde7e379855..000000000000 --- a/include/asm-arm/arch-kirkwood/system.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/system.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 10 | #define __ASM_ARCH_SYSTEM_H | ||
| 11 | |||
| 12 | #include <asm/arch/hardware.h> | ||
| 13 | #include <asm/arch/kirkwood.h> | ||
| 14 | |||
| 15 | static inline void arch_idle(void) | ||
| 16 | { | ||
| 17 | cpu_do_idle(); | ||
| 18 | } | ||
| 19 | |||
| 20 | static inline void arch_reset(char mode) | ||
| 21 | { | ||
| 22 | /* | ||
| 23 | * Enable soft reset to assert RSTOUTn. | ||
| 24 | */ | ||
| 25 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Assert soft reset. | ||
| 29 | */ | ||
| 30 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | ||
| 31 | |||
| 32 | while (1) | ||
| 33 | ; | ||
| 34 | } | ||
| 35 | |||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-kirkwood/timex.h b/include/asm-arm/arch-kirkwood/timex.h deleted file mode 100644 index 82122e134e3c..000000000000 --- a/include/asm-arm/arch-kirkwood/timex.h +++ /dev/null | |||
| @@ -1,11 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/timex.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE (100 * HZ) | ||
| 10 | |||
| 11 | #define KIRKWOOD_TCLK 166666667 | ||
diff --git a/include/asm-arm/arch-kirkwood/uncompress.h b/include/asm-arm/arch-kirkwood/uncompress.h deleted file mode 100644 index a9062b6d7680..000000000000 --- a/include/asm-arm/arch-kirkwood/uncompress.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/uncompress.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/serial_reg.h> | ||
| 10 | #include <asm/arch/kirkwood.h> | ||
| 11 | |||
| 12 | #define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) | ||
| 13 | |||
| 14 | static void putc(const char c) | ||
| 15 | { | ||
| 16 | unsigned char *base = SERIAL_BASE; | ||
| 17 | int i; | ||
| 18 | |||
| 19 | for (i = 0; i < 0x1000; i++) { | ||
| 20 | if (base[UART_LSR << 2] & UART_LSR_THRE) | ||
| 21 | break; | ||
| 22 | barrier(); | ||
| 23 | } | ||
| 24 | |||
| 25 | base[UART_TX << 2] = c; | ||
| 26 | } | ||
| 27 | |||
| 28 | static void flush(void) | ||
| 29 | { | ||
| 30 | unsigned char *base = SERIAL_BASE; | ||
| 31 | unsigned char mask; | ||
| 32 | int i; | ||
| 33 | |||
| 34 | mask = UART_LSR_TEMT | UART_LSR_THRE; | ||
| 35 | |||
| 36 | for (i = 0; i < 0x1000; i++) { | ||
| 37 | if ((base[UART_LSR << 2] & mask) == mask) | ||
| 38 | break; | ||
| 39 | barrier(); | ||
| 40 | } | ||
| 41 | } | ||
| 42 | |||
| 43 | /* | ||
| 44 | * nothing to do | ||
| 45 | */ | ||
| 46 | #define arch_decomp_setup() | ||
| 47 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-kirkwood/vmalloc.h b/include/asm-arm/arch-kirkwood/vmalloc.h deleted file mode 100644 index 41852c6e77f3..000000000000 --- a/include/asm-arm/arch-kirkwood/vmalloc.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-kirkwood/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define VMALLOC_END 0xfe800000 | ||
diff --git a/include/asm-arm/arch-ks8695/debug-macro.S b/include/asm-arm/arch-ks8695/debug-macro.S deleted file mode 100644 index d2583ffffa95..000000000000 --- a/include/asm-arm/arch-ks8695/debug-macro.S +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/debug-macro.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Copyright (C) 2006 Simtec Electronics | ||
| 6 | * | ||
| 7 | * KS8695 - Debug macros | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | #include <asm/arch/regs-uart.h> | ||
| 16 | |||
| 17 | .macro addruart, rx | ||
| 18 | mrc p15, 0, \rx, c1, c0 | ||
| 19 | tst \rx, #1 @ MMU enabled? | ||
| 20 | ldreq \rx, =KS8695_UART_PA @ physical base address | ||
| 21 | ldrne \rx, =KS8695_UART_VA @ virtual base address | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro senduart, rd, rx | ||
| 25 | str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register | ||
| 26 | .endm | ||
| 27 | |||
| 28 | .macro busyuart, rd, rx | ||
| 29 | 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register | ||
| 30 | tst \rd, #URLS_URTE @ Holding & Shift registers empty? | ||
| 31 | beq 1001b | ||
| 32 | .endm | ||
| 33 | |||
| 34 | .macro waituart, rd, rx | ||
| 35 | 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register | ||
| 36 | tst \rd, #URLS_URTHRE @ Holding Register empty? | ||
| 37 | beq 1001b | ||
| 38 | .endm | ||
diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h deleted file mode 100644 index 7ad2c656e162..000000000000 --- a/include/asm-arm/arch-ks8695/devices.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/devices.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_DEVICES_H | ||
| 12 | #define __ASM_ARCH_DEVICES_H | ||
| 13 | |||
| 14 | #include <linux/pci.h> | ||
| 15 | |||
| 16 | /* Ethernet */ | ||
| 17 | extern void __init ks8695_add_device_wan(void); | ||
| 18 | extern void __init ks8695_add_device_lan(void); | ||
| 19 | extern void __init ks8695_add_device_hpna(void); | ||
| 20 | |||
| 21 | /* LEDs */ | ||
| 22 | extern short ks8695_leds_cpu; | ||
| 23 | extern short ks8695_leds_timer; | ||
| 24 | extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led); | ||
| 25 | |||
| 26 | /* PCI */ | ||
| 27 | #define KS8695_MODE_PCI 0 | ||
| 28 | #define KS8695_MODE_MINIPCI 1 | ||
| 29 | #define KS8695_MODE_CARDBUS 2 | ||
| 30 | |||
| 31 | struct ks8695_pci_cfg { | ||
| 32 | short mode; | ||
| 33 | int (*map_irq)(struct pci_dev *, u8, u8); | ||
| 34 | }; | ||
| 35 | extern __init void ks8695_init_pci(struct ks8695_pci_cfg *); | ||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/dma.h b/include/asm-arm/arch-ks8695/dma.h deleted file mode 100644 index e5159ed42a4b..000000000000 --- a/include/asm-arm/arch-ks8695/dma.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/dma.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 17 | */ | ||
diff --git a/include/asm-arm/arch-ks8695/entry-macro.S b/include/asm-arm/arch-ks8695/entry-macro.S deleted file mode 100644 index 3993cfe67cfa..000000000000 --- a/include/asm-arm/arch-ks8695/entry-macro.S +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/entry-macro.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Copyright (C) 2006 Simtec Electronics | ||
| 6 | * | ||
| 7 | * Low-level IRQ helper macros for KS8695 | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | #include <asm/arch/regs-irq.h> | ||
| 16 | |||
| 17 | .macro disable_fiq | ||
| 18 | .endm | ||
| 19 | |||
| 20 | .macro get_irqnr_preamble, base, tmp | ||
| 21 | ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 25 | .endm | ||
| 26 | |||
| 27 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 28 | ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register | ||
| 29 | |||
| 30 | teq \irqstat, #0 | ||
| 31 | beq 1001f | ||
| 32 | |||
| 33 | mov \irqnr, #0 | ||
| 34 | |||
| 35 | tst \irqstat, #0xff | ||
| 36 | moveq \irqstat, \irqstat, lsr #8 | ||
| 37 | addeq \irqnr, \irqnr, #8 | ||
| 38 | tsteq \irqstat, #0xff | ||
| 39 | moveq \irqstat, \irqstat, lsr #8 | ||
| 40 | addeq \irqnr, \irqnr, #8 | ||
| 41 | tsteq \irqstat, #0xff | ||
| 42 | moveq \irqstat, \irqstat, lsr #8 | ||
| 43 | addeq \irqnr, \irqnr, #8 | ||
| 44 | tst \irqstat, #0x0f | ||
| 45 | moveq \irqstat, \irqstat, lsr #4 | ||
| 46 | addeq \irqnr, \irqnr, #4 | ||
| 47 | tst \irqstat, #0x03 | ||
| 48 | moveq \irqstat, \irqstat, lsr #2 | ||
| 49 | addeq \irqnr, \irqnr, #2 | ||
| 50 | tst \irqstat, #0x01 | ||
| 51 | addeqs \irqnr, \irqnr, #1 | ||
| 52 | 1001: | ||
| 53 | .endm | ||
diff --git a/include/asm-arm/arch-ks8695/gpio.h b/include/asm-arm/arch-ks8695/gpio.h deleted file mode 100644 index 65ceea28607b..000000000000 --- a/include/asm-arm/arch-ks8695/gpio.h +++ /dev/null | |||
| @@ -1,79 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/gpio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_GPIO_H_ | ||
| 12 | #define __ASM_ARCH_GPIO_H_ | ||
| 13 | |||
| 14 | #define KS8695_GPIO_0 0 | ||
| 15 | #define KS8695_GPIO_1 1 | ||
| 16 | #define KS8695_GPIO_2 2 | ||
| 17 | #define KS8695_GPIO_3 3 | ||
| 18 | #define KS8695_GPIO_4 4 | ||
| 19 | #define KS8695_GPIO_5 5 | ||
| 20 | #define KS8695_GPIO_6 6 | ||
| 21 | #define KS8695_GPIO_7 7 | ||
| 22 | #define KS8695_GPIO_8 8 | ||
| 23 | #define KS8695_GPIO_9 9 | ||
| 24 | #define KS8695_GPIO_10 10 | ||
| 25 | #define KS8695_GPIO_11 11 | ||
| 26 | #define KS8695_GPIO_12 12 | ||
| 27 | #define KS8695_GPIO_13 13 | ||
| 28 | #define KS8695_GPIO_14 14 | ||
| 29 | #define KS8695_GPIO_15 15 | ||
| 30 | |||
| 31 | |||
| 32 | /* | ||
| 33 | * Configure GPIO pin as external interrupt source. | ||
| 34 | */ | ||
| 35 | int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type); | ||
| 36 | |||
| 37 | /* | ||
| 38 | * Configure the GPIO line as an input. | ||
| 39 | */ | ||
| 40 | int __init_or_module gpio_direction_input(unsigned int pin); | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Configure the GPIO line as an output, with default state. | ||
| 44 | */ | ||
| 45 | int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state); | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Set the state of an output GPIO line. | ||
| 49 | */ | ||
| 50 | void gpio_set_value(unsigned int pin, unsigned int state); | ||
| 51 | |||
| 52 | /* | ||
| 53 | * Read the state of a GPIO line. | ||
| 54 | */ | ||
| 55 | int gpio_get_value(unsigned int pin); | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Map GPIO line to IRQ number. | ||
| 59 | */ | ||
| 60 | int gpio_to_irq(unsigned int pin); | ||
| 61 | |||
| 62 | /* | ||
| 63 | * Map IRQ number to GPIO line. | ||
| 64 | */ | ||
| 65 | int irq_to_gpio(unsigned int irq); | ||
| 66 | |||
| 67 | |||
| 68 | #include <asm-generic/gpio.h> | ||
| 69 | |||
| 70 | static inline int gpio_request(unsigned int pin, const char *label) | ||
| 71 | { | ||
| 72 | return 0; | ||
| 73 | } | ||
| 74 | |||
| 75 | static inline void gpio_free(unsigned int pin) | ||
| 76 | { | ||
| 77 | } | ||
| 78 | |||
| 79 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/hardware.h b/include/asm-arm/arch-ks8695/hardware.h deleted file mode 100644 index cb732bff3288..000000000000 --- a/include/asm-arm/arch-ks8695/hardware.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Copyright (C) 2006 Simtec Electronics | ||
| 6 | * | ||
| 7 | * KS8695 - Memory Map definitions | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 15 | #define __ASM_ARCH_HARDWARE_H | ||
| 16 | |||
| 17 | #include <asm/sizes.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Physical RAM address. | ||
| 21 | */ | ||
| 22 | #define KS8695_SDRAM_PA 0x00000000 | ||
| 23 | |||
| 24 | |||
| 25 | /* | ||
| 26 | * We map an entire MiB with the System Configuration Registers in even | ||
| 27 | * though only 64KiB is needed. This makes it easier for use with the | ||
| 28 | * head debug code as the initial MMU setup only deals in L1 sections. | ||
| 29 | */ | ||
| 30 | #define KS8695_IO_PA 0x03F00000 | ||
| 31 | #define KS8695_IO_VA 0xF0000000 | ||
| 32 | #define KS8695_IO_SIZE SZ_1M | ||
| 33 | |||
| 34 | #define KS8695_PCIMEM_PA 0x60000000 | ||
| 35 | #define KS8695_PCIMEM_SIZE SZ_512M | ||
| 36 | |||
| 37 | #define KS8695_PCIIO_PA 0x80000000 | ||
| 38 | #define KS8695_PCIIO_SIZE SZ_64K | ||
| 39 | |||
| 40 | |||
| 41 | /* | ||
| 42 | * PCI support | ||
| 43 | */ | ||
| 44 | #define pcibios_assign_all_busses() 1 | ||
| 45 | |||
| 46 | #define PCIBIOS_MIN_IO 0 | ||
| 47 | #define PCIBIOS_MIN_MEM 0 | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/io.h b/include/asm-arm/arch-ks8695/io.h deleted file mode 100644 index 8edc4bd6aadf..000000000000 --- a/include/asm-arm/arch-ks8695/io.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_IO_H | ||
| 12 | #define __ASM_ARCH_IO_H | ||
| 13 | |||
| 14 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 15 | |||
| 16 | #define __io(a) ((void __iomem *)(a)) | ||
| 17 | #define __mem_pci(a) (a) | ||
| 18 | |||
| 19 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/irqs.h b/include/asm-arm/arch-ks8695/irqs.h deleted file mode 100644 index 8b1c4fe96a81..000000000000 --- a/include/asm-arm/arch-ks8695/irqs.h +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ks8695/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_IRQS_H | ||
| 13 | #define __ASM_ARCH_IRQS_H | ||
| 14 | |||
| 15 | |||
| 16 | #define NR_IRQS 32 | ||
| 17 | |||
| 18 | /* | ||
| 19 | * IRQ definitions | ||
| 20 | */ | ||
| 21 | #define KS8695_IRQ_COMM_RX 0 | ||
| 22 | #define KS8695_IRQ_COMM_TX 1 | ||
| 23 | #define KS8695_IRQ_EXTERN0 2 | ||
| 24 | #define KS8695_IRQ_EXTERN1 3 | ||
| 25 | #define KS8695_IRQ_EXTERN2 4 | ||
| 26 | #define KS8695_IRQ_EXTERN3 5 | ||
| 27 | #define KS8695_IRQ_TIMER0 6 | ||
| 28 | #define KS8695_IRQ_TIMER1 7 | ||
| 29 | #define KS8695_IRQ_UART_TX 8 | ||
| 30 | #define KS8695_IRQ_UART_RX 9 | ||
| 31 | #define KS8695_IRQ_UART_LINE_STATUS 10 | ||
| 32 | #define KS8695_IRQ_UART_MODEM_STATUS 11 | ||
| 33 | #define KS8695_IRQ_LAN_RX_STOP 12 | ||
| 34 | #define KS8695_IRQ_LAN_TX_STOP 13 | ||
| 35 | #define KS8695_IRQ_LAN_RX_BUF 14 | ||
| 36 | #define KS8695_IRQ_LAN_TX_BUF 15 | ||
| 37 | #define KS8695_IRQ_LAN_RX_STATUS 16 | ||
| 38 | #define KS8695_IRQ_LAN_TX_STATUS 17 | ||
| 39 | #define KS8695_IRQ_HPNA_RX_STOP 18 | ||
| 40 | #define KS8695_IRQ_HPNA_TX_STOP 19 | ||
| 41 | #define KS8695_IRQ_HPNA_RX_BUF 20 | ||
| 42 | #define KS8695_IRQ_HPNA_TX_BUF 21 | ||
| 43 | #define KS8695_IRQ_HPNA_RX_STATUS 22 | ||
| 44 | #define KS8695_IRQ_HPNA_TX_STATUS 23 | ||
| 45 | #define KS8695_IRQ_BUS_ERROR 24 | ||
| 46 | #define KS8695_IRQ_WAN_RX_STOP 25 | ||
| 47 | #define KS8695_IRQ_WAN_TX_STOP 26 | ||
| 48 | #define KS8695_IRQ_WAN_RX_BUF 27 | ||
| 49 | #define KS8695_IRQ_WAN_TX_BUF 28 | ||
| 50 | #define KS8695_IRQ_WAN_RX_STATUS 29 | ||
| 51 | #define KS8695_IRQ_WAN_TX_STATUS 30 | ||
| 52 | #define KS8695_IRQ_WAN_LINK 31 | ||
| 53 | |||
| 54 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/memory.h b/include/asm-arm/arch-ks8695/memory.h deleted file mode 100644 index 1b542f77977a..000000000000 --- a/include/asm-arm/arch-ks8695/memory.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * KS8695 Memory definitions | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 14 | #define __ASM_ARCH_MEMORY_H | ||
| 15 | |||
| 16 | #include <asm/arch/hardware.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Physical SRAM offset. | ||
| 20 | */ | ||
| 21 | #define PHYS_OFFSET KS8695_SDRAM_PA | ||
| 22 | |||
| 23 | #ifndef __ASSEMBLY__ | ||
| 24 | |||
| 25 | #ifdef CONFIG_PCI | ||
| 26 | |||
| 27 | /* PCI mappings */ | ||
| 28 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET + KS8695_PCIMEM_PA) | ||
| 29 | #define __bus_to_virt(x) ((x) - KS8695_PCIMEM_PA + PAGE_OFFSET) | ||
| 30 | |||
| 31 | /* Platform-bus mapping */ | ||
| 32 | extern struct bus_type platform_bus_type; | ||
| 33 | #define is_lbus_device(dev) (dev && dev->bus == &platform_bus_type) | ||
| 34 | #define __arch_dma_to_virt(dev, x) ({ is_lbus_device(dev) ? \ | ||
| 35 | __phys_to_virt(x) : __bus_to_virt(x); }) | ||
| 36 | #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ | ||
| 37 | (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) | ||
| 38 | #define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x)) | ||
| 39 | |||
| 40 | #else | ||
| 41 | |||
| 42 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 43 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 44 | |||
| 45 | #endif | ||
| 46 | |||
| 47 | #endif | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h deleted file mode 100644 index 6b95d77aea19..000000000000 --- a/include/asm-arm/arch-ks8695/regs-gpio.h +++ /dev/null | |||
| @@ -1,55 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-gpio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Andrew Victor | ||
| 5 | * | ||
| 6 | * KS8695 - GPIO control registers and bit definitions. | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef KS8695_GPIO_H | ||
| 14 | #define KS8695_GPIO_H | ||
| 15 | |||
| 16 | #define KS8695_GPIO_OFFSET (0xF0000 + 0xE600) | ||
| 17 | #define KS8695_GPIO_VA (KS8695_IO_VA + KS8695_GPIO_OFFSET) | ||
| 18 | #define KS8695_GPIO_PA (KS8695_IO_PA + KS8695_GPIO_OFFSET) | ||
| 19 | |||
| 20 | |||
| 21 | #define KS8695_IOPM (0x00) /* I/O Port Mode Register */ | ||
| 22 | #define KS8695_IOPC (0x04) /* I/O Port Control Register */ | ||
| 23 | #define KS8695_IOPD (0x08) /* I/O Port Data Register */ | ||
| 24 | |||
| 25 | |||
| 26 | /* Port Mode Register */ | ||
| 27 | #define IOPM_(x) (1 << (x)) /* Mode for GPIO Pin x */ | ||
| 28 | |||
| 29 | /* Port Control Register */ | ||
| 30 | #define IOPC_IOTIM1EN (1 << 17) /* GPIO Pin for Timer1 Enable */ | ||
| 31 | #define IOPC_IOTIM0EN (1 << 16) /* GPIO Pin for Timer0 Enable */ | ||
| 32 | #define IOPC_IOEINT3EN (1 << 15) /* GPIO Pin for External/Soft Interrupt 3 Enable */ | ||
| 33 | #define IOPC_IOEINT3TM (7 << 12) /* GPIO Pin for External/Soft Interrupt 3 Trigger Mode */ | ||
| 34 | #define IOPC_IOEINT3_MODE(x) ((x) << 12) | ||
| 35 | #define IOPC_IOEINT2EN (1 << 11) /* GPIO Pin for External/Soft Interrupt 2 Enable */ | ||
| 36 | #define IOPC_IOEINT2TM (7 << 8) /* GPIO Pin for External/Soft Interrupt 2 Trigger Mode */ | ||
| 37 | #define IOPC_IOEINT2_MODE(x) ((x) << 8) | ||
| 38 | #define IOPC_IOEINT1EN (1 << 7) /* GPIO Pin for External/Soft Interrupt 1 Enable */ | ||
| 39 | #define IOPC_IOEINT1TM (7 << 4) /* GPIO Pin for External/Soft Interrupt 1 Trigger Mode */ | ||
| 40 | #define IOPC_IOEINT1_MODE(x) ((x) << 4) | ||
| 41 | #define IOPC_IOEINT0EN (1 << 3) /* GPIO Pin for External/Soft Interrupt 0 Enable */ | ||
| 42 | #define IOPC_IOEINT0TM (7 << 0) /* GPIO Pin for External/Soft Interrupt 0 Trigger Mode */ | ||
| 43 | #define IOPC_IOEINT0_MODE(x) ((x) << 0) | ||
| 44 | |||
| 45 | /* Trigger Modes */ | ||
| 46 | #define IOPC_TM_LOW (0) /* Level Detection (Active Low) */ | ||
| 47 | #define IOPC_TM_HIGH (1) /* Level Detection (Active High) */ | ||
| 48 | #define IOPC_TM_RISING (2) /* Rising Edge Detection */ | ||
| 49 | #define IOPC_TM_FALLING (4) /* Falling Edge Detection */ | ||
| 50 | #define IOPC_TM_EDGE (6) /* Both Edge Detection */ | ||
| 51 | |||
| 52 | /* Port Data Register */ | ||
| 53 | #define IOPD_(x) (1 << (x)) /* Signal Level of GPIO Pin x */ | ||
| 54 | |||
| 55 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-hpna.h b/include/asm-arm/arch-ks8695/regs-hpna.h deleted file mode 100644 index 14091cdec103..000000000000 --- a/include/asm-arm/arch-ks8695/regs-hpna.h +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-wan.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * KS8695 - HPNA Registers and bit definitions. | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef KS8695_HPNA_H | ||
| 14 | #define KS8695_HPNA_H | ||
| 15 | |||
| 16 | #define KS8695_HPNA_OFFSET (0xF0000 + 0xA000) | ||
| 17 | #define KS8695_HPNA_VA (KS8695_IO_VA + KS8695_HPNA_OFFSET) | ||
| 18 | #define KS8695_HPNA_PA (KS8695_IO_PA + KS8695_HPNA_OFFSET) | ||
| 19 | |||
| 20 | |||
| 21 | /* | ||
| 22 | * HPNA registers | ||
| 23 | */ | ||
| 24 | |||
| 25 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-irq.h b/include/asm-arm/arch-ks8695/regs-irq.h deleted file mode 100644 index 70b193f6b756..000000000000 --- a/include/asm-arm/arch-ks8695/regs-irq.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-irq.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Copyright (C) 2006 Simtec Electronics | ||
| 6 | * | ||
| 7 | * KS8695 - IRQ registers and bit definitions | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef KS8695_IRQ_H | ||
| 15 | #define KS8695_IRQ_H | ||
| 16 | |||
| 17 | #define KS8695_IRQ_OFFSET (0xF0000 + 0xE200) | ||
| 18 | #define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET) | ||
| 19 | #define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET) | ||
| 20 | |||
| 21 | |||
| 22 | /* | ||
| 23 | * Interrupt Controller registers | ||
| 24 | */ | ||
| 25 | #define KS8695_INTMC (0x00) /* Mode Control Register */ | ||
| 26 | #define KS8695_INTEN (0x04) /* Interrupt Enable Register */ | ||
| 27 | #define KS8695_INTST (0x08) /* Interrupt Status Register */ | ||
| 28 | #define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */ | ||
| 29 | #define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */ | ||
| 30 | #define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */ | ||
| 31 | #define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */ | ||
| 32 | #define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */ | ||
| 33 | #define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */ | ||
| 34 | #define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */ | ||
| 35 | #define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */ | ||
| 36 | #define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */ | ||
| 37 | #define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */ | ||
| 38 | #define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */ | ||
| 39 | |||
| 40 | |||
| 41 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-lan.h b/include/asm-arm/arch-ks8695/regs-lan.h deleted file mode 100644 index a63bd61c64ed..000000000000 --- a/include/asm-arm/arch-ks8695/regs-lan.h +++ /dev/null | |||
| @@ -1,65 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-lan.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * KS8695 - LAN Registers and bit definitions. | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef KS8695_LAN_H | ||
| 14 | #define KS8695_LAN_H | ||
| 15 | |||
| 16 | #define KS8695_LAN_OFFSET (0xF0000 + 0x8000) | ||
| 17 | #define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET) | ||
| 18 | #define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET) | ||
| 19 | |||
| 20 | |||
| 21 | /* | ||
| 22 | * LAN registers | ||
| 23 | */ | ||
| 24 | #define KS8695_LMDTXC (0x00) /* DMA Transmit Control */ | ||
| 25 | #define KS8695_LMDRXC (0x04) /* DMA Receive Control */ | ||
| 26 | #define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */ | ||
| 27 | #define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */ | ||
| 28 | #define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */ | ||
| 29 | #define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */ | ||
| 30 | #define KS8695_LMAL (0x18) /* MAC Station Address Low */ | ||
| 31 | #define KS8695_LMAH (0x1c) /* MAC Station Address High */ | ||
| 32 | #define KS8695_LMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ | ||
| 33 | #define KS8695_LMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ | ||
| 34 | |||
| 35 | |||
| 36 | /* DMA Transmit Control Register */ | ||
| 37 | #define LMDTXC_LMTRST (1 << 31) /* Soft Reset */ | ||
| 38 | #define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */ | ||
| 39 | #define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ | ||
| 40 | #define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ | ||
| 41 | #define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */ | ||
| 42 | #define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */ | ||
| 43 | #define LMDTXC_LMTLB (1 << 8) /* Loopback mode */ | ||
| 44 | #define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */ | ||
| 45 | #define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */ | ||
| 46 | #define LMDTXC_LMTE (1 << 0) /* TX Enable */ | ||
| 47 | |||
| 48 | /* DMA Receive Control Register */ | ||
| 49 | #define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */ | ||
| 50 | #define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */ | ||
| 51 | #define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */ | ||
| 52 | #define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */ | ||
| 53 | #define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */ | ||
| 54 | #define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */ | ||
| 55 | #define LMDRXC_LMRM (1 << 5) /* Receive Multicast */ | ||
| 56 | #define LMDRXC_LMRU (1 << 4) /* Receive Unicast */ | ||
| 57 | #define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */ | ||
| 58 | #define LMDRXC_LMRA (1 << 2) /* Receive All */ | ||
| 59 | #define LMDRXC_LMRE (1 << 1) /* RX Enable */ | ||
| 60 | |||
| 61 | /* Additional Station Address High */ | ||
| 62 | #define LMAAH_E (1 << 31) /* Address Enabled */ | ||
| 63 | |||
| 64 | |||
| 65 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-mem.h b/include/asm-arm/arch-ks8695/regs-mem.h deleted file mode 100644 index 76b38e0862e6..000000000000 --- a/include/asm-arm/arch-ks8695/regs-mem.h +++ /dev/null | |||
| @@ -1,89 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-mem.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * KS8695 - Memory Controller registers and bit definitions | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef KS8695_MEM_H | ||
| 14 | #define KS8695_MEM_H | ||
| 15 | |||
| 16 | #define KS8695_MEM_OFFSET (0xF0000 + 0x4000) | ||
| 17 | #define KS8695_MEM_VA (KS8695_IO_VA + KS8695_MEM_OFFSET) | ||
| 18 | #define KS8695_MEM_PA (KS8695_IO_PA + KS8695_MEM_OFFSET) | ||
| 19 | |||
| 20 | |||
| 21 | /* | ||
| 22 | * Memory Controller Registers | ||
| 23 | */ | ||
| 24 | #define KS8695_EXTACON0 (0x00) /* External I/O 0 Access Control */ | ||
| 25 | #define KS8695_EXTACON1 (0x04) /* External I/O 1 Access Control */ | ||
| 26 | #define KS8695_EXTACON2 (0x08) /* External I/O 2 Access Control */ | ||
| 27 | #define KS8695_ROMCON0 (0x10) /* ROM/SRAM/Flash 1 Control Register */ | ||
| 28 | #define KS8695_ROMCON1 (0x14) /* ROM/SRAM/Flash 2 Control Register */ | ||
| 29 | #define KS8695_ERGCON (0x20) /* External I/O and ROM/SRAM/Flash General Register */ | ||
| 30 | #define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */ | ||
| 31 | #define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */ | ||
| 32 | #define KS8695_SDGCON (0x38) /* SDRAM General Control */ | ||
| 33 | #define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */ | ||
| 34 | #define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */ | ||
| 35 | |||
| 36 | |||
| 37 | /* External I/O Access Control Registers */ | ||
| 38 | #define EXTACON_EBNPTR (0x3ff << 22) /* Last Address Pointer */ | ||
| 39 | #define EXTACON_EBBPTR (0x3ff << 12) /* Base Pointer */ | ||
| 40 | #define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */ | ||
| 41 | #define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */ | ||
| 42 | #define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */ | ||
| 43 | #define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */ | ||
| 44 | |||
| 45 | /* ROM/SRAM/Flash Control Register */ | ||
| 46 | #define ROMCON_RBNPTR (0x3ff << 22) /* Next Pointer */ | ||
| 47 | #define ROMCON_RBBPTR (0x3ff << 12) /* Base Pointer */ | ||
| 48 | #define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */ | ||
| 49 | #define ROMCON_RBTPA (3 << 2) /* Page Address Access Time */ | ||
| 50 | #define ROMCON_PMC (3 << 0) /* Page Mode Configuration */ | ||
| 51 | #define PMC_NORMAL (0 << 0) | ||
| 52 | #define PMC_4WORD (1 << 0) | ||
| 53 | #define PMC_8WORD (2 << 0) | ||
| 54 | #define PMC_16WORD (3 << 0) | ||
| 55 | |||
| 56 | /* External I/O and ROM/SRAM/Flash General Register */ | ||
| 57 | #define ERGCON_TMULT (3 << 28) /* Time Multiplier */ | ||
| 58 | #define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */ | ||
| 59 | #define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */ | ||
| 60 | #define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */ | ||
| 61 | #define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */ | ||
| 62 | #define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */ | ||
| 63 | |||
| 64 | /* SDRAM Control Register */ | ||
| 65 | #define SDCON_DBNPTR (0x3ff << 22) /* Last Address Pointer */ | ||
| 66 | #define SDCON_DBBPTR (0x3ff << 12) /* Base Pointer */ | ||
| 67 | #define SDCON_DBCAB (3 << 8) /* Column Address Bits */ | ||
| 68 | #define SDCON_DBBNUM (1 << 3) /* Number of Banks */ | ||
| 69 | #define SDCON_DBDBW (3 << 1) /* Data Bus Width */ | ||
| 70 | |||
| 71 | /* SDRAM General Control Register */ | ||
| 72 | #define SDGCON_SDTRC (3 << 2) /* RAS to CAS latency */ | ||
| 73 | #define SDGCON_SDCAS (3 << 0) /* CAS latency */ | ||
| 74 | |||
| 75 | /* SDRAM Buffer Control Register */ | ||
| 76 | #define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */ | ||
| 77 | #define SDBCON_RBUFBDIS (1 << 24) /* Read Buffer Burst Enable */ | ||
| 78 | #define SDBCON_WFIFOEN (1 << 23) /* Write FIFO Enable */ | ||
| 79 | #define SDBCON_RBUFEN (1 << 22) /* Read Buffer Enable */ | ||
| 80 | #define SDBCON_FLUSHWFIFO (1 << 21) /* Flush Write FIFO */ | ||
| 81 | #define SDBCON_RBUFINV (1 << 20) /* Read Buffer Invalidate */ | ||
| 82 | #define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */ | ||
| 83 | #define SDBCON_SDMODE (0x3fff << 0) /* SDRAM Mode Register Value Program */ | ||
| 84 | |||
| 85 | /* SDRAM Refresh Timer Register */ | ||
| 86 | #define REFTIM_REFTIM (0xffff << 0) /* Refresh Timer Value */ | ||
| 87 | |||
| 88 | |||
| 89 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-misc.h b/include/asm-arm/arch-ks8695/regs-misc.h deleted file mode 100644 index 632ca6601a94..000000000000 --- a/include/asm-arm/arch-ks8695/regs-misc.h +++ /dev/null | |||
| @@ -1,97 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-misc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * KS8695 - Miscellaneous Registers | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef KS8695_MISC_H | ||
| 14 | #define KS8695_MISC_H | ||
| 15 | |||
| 16 | #define KS8695_MISC_OFFSET (0xF0000 + 0xEA00) | ||
| 17 | #define KS8695_MISC_VA (KS8695_IO_VA + KS8695_MISC_OFFSET) | ||
| 18 | #define KS8695_MISC_PA (KS8695_IO_PA + KS8695_MISC_OFFSET) | ||
| 19 | |||
| 20 | |||
| 21 | /* | ||
| 22 | * Miscellaneous registers | ||
| 23 | */ | ||
| 24 | #define KS8695_DID (0x00) /* Device ID */ | ||
| 25 | #define KS8695_RID (0x04) /* Revision ID */ | ||
| 26 | #define KS8695_HMC (0x08) /* HPNA Miscellaneous Control [KS8695 only] */ | ||
| 27 | #define KS8695_WMC (0x0c) /* WAN Miscellaneous Control */ | ||
| 28 | #define KS8695_WPPM (0x10) /* WAN PHY Power Management */ | ||
| 29 | #define KS8695_PPS (0x1c) /* PHY PowerSave */ | ||
| 30 | |||
| 31 | /* Device ID Register */ | ||
| 32 | #define DID_ID (0xffff << 0) /* Device ID */ | ||
| 33 | |||
| 34 | /* Revision ID Register */ | ||
| 35 | #define RID_SUBID (0xf << 4) /* Sub-Device ID */ | ||
| 36 | #define RID_REVISION (0xf << 0) /* Revision ID */ | ||
| 37 | |||
| 38 | /* HPNA Miscellaneous Control Register */ | ||
| 39 | #define HMC_HSS (1 << 1) /* Speed */ | ||
| 40 | #define HMC_HDS (1 << 0) /* Duplex */ | ||
| 41 | |||
| 42 | /* WAN Miscellaneous Control Register */ | ||
| 43 | #define WMC_WANC (1 << 30) /* Auto-negotiation complete */ | ||
| 44 | #define WMC_WANR (1 << 29) /* Auto-negotiation restart */ | ||
| 45 | #define WMC_WANAP (1 << 28) /* Advertise Pause */ | ||
| 46 | #define WMC_WANA100F (1 << 27) /* Advertise 100 FDX */ | ||
| 47 | #define WMC_WANA100H (1 << 26) /* Advertise 100 HDX */ | ||
| 48 | #define WMC_WANA10F (1 << 25) /* Advertise 10 FDX */ | ||
| 49 | #define WMC_WANA10H (1 << 24) /* Advertise 10 HDX */ | ||
| 50 | #define WMC_WLS (1 << 23) /* Link status */ | ||
| 51 | #define WMC_WDS (1 << 22) /* Duplex status */ | ||
| 52 | #define WMC_WSS (1 << 21) /* Speed status */ | ||
| 53 | #define WMC_WLPP (1 << 20) /* Link Partner Pause */ | ||
| 54 | #define WMC_WLP100F (1 << 19) /* Link Partner 100 FDX */ | ||
| 55 | #define WMC_WLP100H (1 << 18) /* Link Partner 100 HDX */ | ||
| 56 | #define WMC_WLP10F (1 << 17) /* Link Partner 10 FDX */ | ||
| 57 | #define WMC_WLP10H (1 << 16) /* Link Partner 10 HDX */ | ||
| 58 | #define WMC_WAND (1 << 15) /* Auto-negotiation disable */ | ||
| 59 | #define WMC_WANF100 (1 << 14) /* Force 100 */ | ||
| 60 | #define WMC_WANFF (1 << 13) /* Force FDX */ | ||
| 61 | #define WMC_WLED1S (7 << 4) /* LED1 Select */ | ||
| 62 | #define WLED1S_SPEED (0 << 4) | ||
| 63 | #define WLED1S_LINK (1 << 4) | ||
| 64 | #define WLED1S_DUPLEX (2 << 4) | ||
| 65 | #define WLED1S_COLLISION (3 << 4) | ||
| 66 | #define WLED1S_ACTIVITY (4 << 4) | ||
| 67 | #define WLED1S_FDX_COLLISION (5 << 4) | ||
| 68 | #define WLED1S_LINK_ACTIVITY (6 << 4) | ||
| 69 | #define WMC_WLED0S (7 << 0) /* LED0 Select */ | ||
| 70 | #define WLED0S_SPEED (0 << 0) | ||
| 71 | #define WLED0S_LINK (1 << 0) | ||
| 72 | #define WLED0S_DUPLEX (2 << 0) | ||
| 73 | #define WLED0S_COLLISION (3 << 0) | ||
| 74 | #define WLED0S_ACTIVITY (4 << 0) | ||
| 75 | #define WLED0S_FDX_COLLISION (5 << 0) | ||
| 76 | #define WLED0S_LINK_ACTIVITY (6 << 0) | ||
| 77 | |||
| 78 | /* WAN PHY Power Management Register */ | ||
| 79 | #define WPPM_WLPBK (1 << 14) /* Local Loopback */ | ||
| 80 | #define WPPM_WRLPKB (1 << 13) /* Remove Loopback */ | ||
| 81 | #define WPPM_WPI (1 << 12) /* PHY isolate */ | ||
| 82 | #define WPPM_WFL (1 << 10) /* Force link */ | ||
| 83 | #define WPPM_MDIXS (1 << 9) /* MDIX Status */ | ||
| 84 | #define WPPM_FEF (1 << 8) /* Far End Fault */ | ||
| 85 | #define WPPM_AMDIXP (1 << 7) /* Auto MDIX Parameter */ | ||
| 86 | #define WPPM_TXDIS (1 << 6) /* Disable transmitter */ | ||
| 87 | #define WPPM_DFEF (1 << 5) /* Disable Far End Fault */ | ||
| 88 | #define WPPM_PD (1 << 4) /* Power Down */ | ||
| 89 | #define WPPM_DMDX (1 << 3) /* Disable Auto MDI/MDIX */ | ||
| 90 | #define WPPM_FMDX (1 << 2) /* Force MDIX */ | ||
| 91 | #define WPPM_LPBK (1 << 1) /* MAX Loopback */ | ||
| 92 | |||
| 93 | /* PHY Power Save Register */ | ||
| 94 | #define PPS_PPSM (1 << 0) /* PHY Power Save Mode */ | ||
| 95 | |||
| 96 | |||
| 97 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-pci.h b/include/asm-arm/arch-ks8695/regs-pci.h deleted file mode 100644 index 286d6d488df8..000000000000 --- a/include/asm-arm/arch-ks8695/regs-pci.h +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-pci.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Copyright (C) 2006 Simtec Electronics | ||
| 6 | * | ||
| 7 | * KS8695 - PCI bridge registers and bit definitions. | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #define KS8695_PCI_OFFSET (0xF0000 + 0x2000) | ||
| 15 | #define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET) | ||
| 16 | #define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET) | ||
| 17 | |||
| 18 | |||
| 19 | #define KS8695_CRCFID (0x000) /* Configuration: Identification */ | ||
| 20 | #define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */ | ||
| 21 | #define KS8695_CRCFRV (0x008) /* Configuration: Revision */ | ||
| 22 | #define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */ | ||
| 23 | #define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */ | ||
| 24 | #define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */ | ||
| 25 | #define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */ | ||
| 26 | #define KS8695_PBCA (0x100) /* Bridge Configuration Address */ | ||
| 27 | #define KS8695_PBCD (0x104) /* Bridge Configuration Data */ | ||
| 28 | #define KS8695_PBM (0x200) /* Bridge Mode */ | ||
| 29 | #define KS8695_PBCS (0x204) /* Bridge Control and Status */ | ||
| 30 | #define KS8695_PMBA (0x208) /* Bridge Memory Base Address */ | ||
| 31 | #define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */ | ||
| 32 | #define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */ | ||
| 33 | #define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */ | ||
| 34 | #define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */ | ||
| 35 | #define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */ | ||
| 36 | #define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */ | ||
| 37 | #define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */ | ||
| 38 | |||
| 39 | |||
| 40 | /* Configuration: Identification */ | ||
| 41 | |||
| 42 | /* Configuration: Command and Status */ | ||
| 43 | |||
| 44 | /* Configuration: Revision */ | ||
| 45 | |||
| 46 | |||
| 47 | |||
| 48 | #define CFRV_GUEST (1 << 23) | ||
| 49 | |||
| 50 | #define PBCA_TYPE1 (1) | ||
| 51 | #define PBCA_ENABLE (1 << 31) | ||
| 52 | |||
| 53 | |||
diff --git a/include/asm-arm/arch-ks8695/regs-switch.h b/include/asm-arm/arch-ks8695/regs-switch.h deleted file mode 100644 index 5f37be3f2f60..000000000000 --- a/include/asm-arm/arch-ks8695/regs-switch.h +++ /dev/null | |||
| @@ -1,66 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-switch.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * KS8695 - Switch Registers and bit definitions. | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef KS8695_SWITCH_H | ||
| 14 | #define KS8695_SWITCH_H | ||
| 15 | |||
| 16 | #define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800) | ||
| 17 | #define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET) | ||
| 18 | #define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET) | ||
| 19 | |||
| 20 | |||
| 21 | /* | ||
| 22 | * Switch registers | ||
| 23 | */ | ||
| 24 | #define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */ | ||
| 25 | #define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */ | ||
| 26 | #define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */ | ||
| 27 | |||
| 28 | #define KS8695_P(x)_C(z) (0xc0 + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */ | ||
| 29 | |||
| 30 | #define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */ | ||
| 31 | #define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */ | ||
| 32 | #define KS8695_SEIAC (0x50) /* Indirect Access Control */ | ||
| 33 | #define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */ | ||
| 34 | #define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */ | ||
| 35 | #define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */ | ||
| 36 | #define KS8695_SEAFC (0x60) /* Advance Feature Control */ | ||
| 37 | #define KS8695_SEDSCPH (0x64) /* TOS Priority High */ | ||
| 38 | #define KS8695_SEDSCPL (0x68) /* TOS Priority Low */ | ||
| 39 | #define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */ | ||
| 40 | #define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */ | ||
| 41 | #define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */ | ||
| 42 | #define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */ | ||
| 43 | |||
| 44 | |||
| 45 | /* Switch Engine Control 0 */ | ||
| 46 | #define SEC0_LLED1S (7 << 25) /* LED1 Select */ | ||
| 47 | #define LLED1S_SPEED (0 << 25) | ||
| 48 | #define LLED1S_LINK (1 << 25) | ||
| 49 | #define LLED1S_DUPLEX (2 << 25) | ||
| 50 | #define LLED1S_COLLISION (3 << 25) | ||
| 51 | #define LLED1S_ACTIVITY (4 << 25) | ||
| 52 | #define LLED1S_FDX_COLLISION (5 << 25) | ||
| 53 | #define LLED1S_LINK_ACTIVITY (6 << 25) | ||
| 54 | #define SEC0_LLED0S (7 << 22) /* LED0 Select */ | ||
| 55 | #define LLED0S_SPEED (0 << 22) | ||
| 56 | #define LLED0S_LINK (1 << 22) | ||
| 57 | #define LLED0S_DUPLEX (2 << 22) | ||
| 58 | #define LLED0S_COLLISION (3 << 22) | ||
| 59 | #define LLED0S_ACTIVITY (4 << 22) | ||
| 60 | #define LLED0S_FDX_COLLISION (5 << 22) | ||
| 61 | #define LLED0S_LINK_ACTIVITY (6 << 22) | ||
| 62 | #define SEC0_ENABLE (1 << 0) /* Enable Switch */ | ||
| 63 | |||
| 64 | |||
| 65 | |||
| 66 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-sys.h b/include/asm-arm/arch-ks8695/regs-sys.h deleted file mode 100644 index f3179815b8ee..000000000000 --- a/include/asm-arm/arch-ks8695/regs-sys.h +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-sys.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Copyright (C) 2006 Simtec Electronics | ||
| 6 | * | ||
| 7 | * KS8695 - System control registers and bit definitions | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef KS8695_SYS_H | ||
| 15 | #define KS8695_SYS_H | ||
| 16 | |||
| 17 | #define KS8695_SYS_OFFSET (0xF0000 + 0x0000) | ||
| 18 | #define KS8695_SYS_VA (KS8695_IO_VA + KS8695_SYS_OFFSET) | ||
| 19 | #define KS8695_SYS_PA (KS8695_IO_PA + KS8695_SYS_OFFSET) | ||
| 20 | |||
| 21 | |||
| 22 | #define KS8695_SYSCFG (0x00) /* System Configuration Register */ | ||
| 23 | #define KS8695_CLKCON (0x04) /* System Clock and Bus Control Register */ | ||
| 24 | |||
| 25 | |||
| 26 | /* System Configuration Register */ | ||
| 27 | #define SYSCFG_SPRBP (0x3ff << 16) /* Register Bank Base Pointer */ | ||
| 28 | |||
| 29 | /* System Clock and Bus Control Register */ | ||
| 30 | #define CLKCON_SFMODE (1 << 8) /* System Fast Mode for Simulation */ | ||
| 31 | #define CLKCON_SCDC (7 << 0) /* System Clock Divider Select */ | ||
| 32 | |||
| 33 | |||
| 34 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-timer.h b/include/asm-arm/arch-ks8695/regs-timer.h deleted file mode 100644 index 0a9f7f99ec52..000000000000 --- a/include/asm-arm/arch-ks8695/regs-timer.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-timer.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Copyright (C) 2006 Simtec Electronics | ||
| 6 | * | ||
| 7 | * KS8695 - Timer registers and bit definitions. | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef KS8695_TIMER_H | ||
| 15 | #define KS8695_TIMER_H | ||
| 16 | |||
| 17 | #define KS8695_TMR_OFFSET (0xF0000 + 0xE400) | ||
| 18 | #define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) | ||
| 19 | #define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) | ||
| 20 | |||
| 21 | |||
| 22 | /* | ||
| 23 | * Timer registers | ||
| 24 | */ | ||
| 25 | #define KS8695_TMCON (0x00) /* Timer Control Register */ | ||
| 26 | #define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ | ||
| 27 | #define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ | ||
| 28 | #define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ | ||
| 29 | #define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ | ||
| 30 | |||
| 31 | |||
| 32 | /* Timer Control Register */ | ||
| 33 | #define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ | ||
| 34 | #define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ | ||
| 35 | |||
| 36 | /* Timer0 Timeout Counter Register */ | ||
| 37 | #define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ | ||
| 38 | |||
| 39 | |||
| 40 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-uart.h b/include/asm-arm/arch-ks8695/regs-uart.h deleted file mode 100644 index a27cb20502a3..000000000000 --- a/include/asm-arm/arch-ks8695/regs-uart.h +++ /dev/null | |||
| @@ -1,92 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-ks8695/regs-uart.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Copyright (C) 2006 Simtec Electronics | ||
| 6 | * | ||
| 7 | * KS8695 - UART register and bit definitions. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef KS8695_UART_H | ||
| 15 | #define KS8695_UART_H | ||
| 16 | |||
| 17 | #define KS8695_UART_OFFSET (0xF0000 + 0xE000) | ||
| 18 | #define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET) | ||
| 19 | #define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET) | ||
| 20 | |||
| 21 | |||
| 22 | /* | ||
| 23 | * UART registers | ||
| 24 | */ | ||
| 25 | #define KS8695_URRB (0x00) /* Receive Buffer Register */ | ||
| 26 | #define KS8695_URTH (0x04) /* Transmit Holding Register */ | ||
| 27 | #define KS8695_URFC (0x08) /* FIFO Control Register */ | ||
| 28 | #define KS8695_URLC (0x0C) /* Line Control Register */ | ||
| 29 | #define KS8695_URMC (0x10) /* Modem Control Register */ | ||
| 30 | #define KS8695_URLS (0x14) /* Line Status Register */ | ||
| 31 | #define KS8695_URMS (0x18) /* Modem Status Register */ | ||
| 32 | #define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */ | ||
| 33 | #define KS8695_USR (0x20) /* Status Register */ | ||
| 34 | |||
| 35 | |||
| 36 | /* FIFO Control Register */ | ||
| 37 | #define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */ | ||
| 38 | #define URFC_URFRT_1 (0 << 6) | ||
| 39 | #define URFC_URFRT_4 (1 << 6) | ||
| 40 | #define URFC_URFRT_8 (2 << 6) | ||
| 41 | #define URFC_URFRT_14 (3 << 6) | ||
| 42 | #define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */ | ||
| 43 | #define URFC_URRFR (1 << 1) /* Receive FIFO Reset */ | ||
| 44 | #define URFC_URFE (1 << 0) /* FIFO Enable */ | ||
| 45 | |||
| 46 | /* Line Control Register */ | ||
| 47 | #define URLC_URSBC (1 << 6) /* Set Break Condition */ | ||
| 48 | #define URLC_PARITY (7 << 3) /* Parity */ | ||
| 49 | #define URPE_NONE (0 << 3) | ||
| 50 | #define URPE_ODD (1 << 3) | ||
| 51 | #define URPE_EVEN (3 << 3) | ||
| 52 | #define URPE_MARK (5 << 3) | ||
| 53 | #define URPE_SPACE (7 << 3) | ||
| 54 | #define URLC_URSB (1 << 2) /* Stop Bits */ | ||
| 55 | #define URLC_URCL (3 << 0) /* Character Length */ | ||
| 56 | #define URCL_5 (0 << 0) | ||
| 57 | #define URCL_6 (1 << 0) | ||
| 58 | #define URCL_7 (2 << 0) | ||
| 59 | #define URCL_8 (3 << 0) | ||
| 60 | |||
| 61 | /* Modem Control Register */ | ||
| 62 | #define URMC_URLB (1 << 4) /* Loop-back mode */ | ||
| 63 | #define URMC_UROUT2 (1 << 3) /* OUT2 signal */ | ||
| 64 | #define URMC_UROUT1 (1 << 2) /* OUT1 signal */ | ||
| 65 | #define URMC_URRTS (1 << 1) /* Request to Send */ | ||
| 66 | #define URMC_URDTR (1 << 0) /* Data Terminal Ready */ | ||
| 67 | |||
| 68 | /* Line Status Register */ | ||
| 69 | #define URLS_URRFE (1 << 7) /* Receive FIFO Error */ | ||
| 70 | #define URLS_URTE (1 << 6) /* Transmit Empty */ | ||
| 71 | #define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */ | ||
| 72 | #define URLS_URBI (1 << 4) /* Break Interrupt */ | ||
| 73 | #define URLS_URFE (1 << 3) /* Framing Error */ | ||
| 74 | #define URLS_URPE (1 << 2) /* Parity Error */ | ||
| 75 | #define URLS_URROE (1 << 1) /* Receive Overrun Error */ | ||
| 76 | #define URLS_URDR (1 << 0) /* Receive Data Ready */ | ||
| 77 | |||
| 78 | /* Modem Status Register */ | ||
| 79 | #define URMS_URDCD (1 << 7) /* Data Carrier Detect */ | ||
| 80 | #define URMS_URRI (1 << 6) /* Ring Indicator */ | ||
| 81 | #define URMS_URDSR (1 << 5) /* Data Set Ready */ | ||
| 82 | #define URMS_URCTS (1 << 4) /* Clear to Send */ | ||
| 83 | #define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */ | ||
| 84 | #define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */ | ||
| 85 | #define URMS_URDDST (1 << 1) /* Delta Data Set Ready */ | ||
| 86 | #define URMS_URDCTS (1 << 0) /* Delta Clear to Send */ | ||
| 87 | |||
| 88 | /* Status Register */ | ||
| 89 | #define USR_UTI (1 << 0) /* Timeout Indication */ | ||
| 90 | |||
| 91 | |||
| 92 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/regs-wan.h b/include/asm-arm/arch-ks8695/regs-wan.h deleted file mode 100644 index 52e35b0d65e4..000000000000 --- a/include/asm-arm/arch-ks8695/regs-wan.h +++ /dev/null | |||
| @@ -1,65 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-wan.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * KS8695 - WAN Registers and bit definitions. | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef KS8695_WAN_H | ||
| 14 | #define KS8695_WAN_H | ||
| 15 | |||
| 16 | #define KS8695_WAN_OFFSET (0xF0000 + 0x6000) | ||
| 17 | #define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) | ||
| 18 | #define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) | ||
| 19 | |||
| 20 | |||
| 21 | /* | ||
| 22 | * WAN registers | ||
| 23 | */ | ||
| 24 | #define KS8695_WMDTXC (0x00) /* DMA Transmit Control */ | ||
| 25 | #define KS8695_WMDRXC (0x04) /* DMA Receive Control */ | ||
| 26 | #define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ | ||
| 27 | #define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ | ||
| 28 | #define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ | ||
| 29 | #define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ | ||
| 30 | #define KS8695_WMAL (0x18) /* MAC Station Address Low */ | ||
| 31 | #define KS8695_WMAH (0x1c) /* MAC Station Address High */ | ||
| 32 | #define KS8695_WMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ | ||
| 33 | #define KS8695_WMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ | ||
| 34 | |||
| 35 | |||
| 36 | /* DMA Transmit Control Register */ | ||
| 37 | #define WMDTXC_WMTRST (1 << 31) /* Soft Reset */ | ||
| 38 | #define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ | ||
| 39 | #define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ | ||
| 40 | #define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ | ||
| 41 | #define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */ | ||
| 42 | #define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */ | ||
| 43 | #define WMDTXC_WMTLB (1 << 8) /* Loopback mode */ | ||
| 44 | #define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ | ||
| 45 | #define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */ | ||
| 46 | #define WMDTXC_WMTE (1 << 0) /* TX Enable */ | ||
| 47 | |||
| 48 | /* DMA Receive Control Register */ | ||
| 49 | #define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ | ||
| 50 | #define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */ | ||
| 51 | #define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */ | ||
| 52 | #define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */ | ||
| 53 | #define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ | ||
| 54 | #define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ | ||
| 55 | #define WMDRXC_WMRM (1 << 5) /* Receive Multicast */ | ||
| 56 | #define WMDRXC_WMRU (1 << 4) /* Receive Unicast */ | ||
| 57 | #define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ | ||
| 58 | #define WMDRXC_WMRA (1 << 2) /* Receive All */ | ||
| 59 | #define WMDRXC_WMRE (1 << 0) /* RX Enable */ | ||
| 60 | |||
| 61 | /* Additional Station Address High */ | ||
| 62 | #define WMAAH_E (1 << 31) /* Address Enabled */ | ||
| 63 | |||
| 64 | |||
| 65 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/system.h b/include/asm-arm/arch-ks8695/system.h deleted file mode 100644 index 3bc28106d937..000000000000 --- a/include/asm-arm/arch-ks8695/system.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-s3c2410/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * KS8695 - System function defines and includes | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 15 | #define __ASM_ARCH_SYSTEM_H | ||
| 16 | |||
| 17 | #include <asm/io.h> | ||
| 18 | #include <asm/arch/regs-timer.h> | ||
| 19 | |||
| 20 | static void arch_idle(void) | ||
| 21 | { | ||
| 22 | /* | ||
| 23 | * This should do all the clock switching | ||
| 24 | * and wait for interrupt tricks, | ||
| 25 | */ | ||
| 26 | cpu_do_idle(); | ||
| 27 | |||
| 28 | } | ||
| 29 | |||
| 30 | static void arch_reset(char mode) | ||
| 31 | { | ||
| 32 | unsigned int reg; | ||
| 33 | |||
| 34 | if (mode == 's') | ||
| 35 | cpu_reset(0); | ||
| 36 | |||
| 37 | /* disable timer0 */ | ||
| 38 | reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); | ||
| 39 | __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | ||
| 40 | |||
| 41 | /* enable watchdog mode */ | ||
| 42 | __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); | ||
| 43 | |||
| 44 | /* re-enable timer0 */ | ||
| 45 | __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); | ||
| 46 | } | ||
| 47 | |||
| 48 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/timex.h b/include/asm-arm/arch-ks8695/timex.h deleted file mode 100644 index 8320d528b903..000000000000 --- a/include/asm-arm/arch-ks8695/timex.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * KS8695 - Time Parameters | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 15 | #define __ASM_ARCH_TIMEX_H | ||
| 16 | |||
| 17 | /* timers are derived from MCLK, which is 25MHz */ | ||
| 18 | #define CLOCK_TICK_RATE 25000000 | ||
| 19 | |||
| 20 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/uncompress.h b/include/asm-arm/arch-ks8695/uncompress.h deleted file mode 100644 index 733a50855b5d..000000000000 --- a/include/asm-arm/arch-ks8695/uncompress.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Copyright (C) 2006 Simtec Electronics | ||
| 6 | * | ||
| 7 | * KS8695 - Kernel uncompressor | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
| 15 | #define __ASM_ARCH_UNCOMPRESS_H | ||
| 16 | |||
| 17 | #include <asm/io.h> | ||
| 18 | #include <asm/arch/regs-uart.h> | ||
| 19 | |||
| 20 | static void putc(char c) | ||
| 21 | { | ||
| 22 | while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) | ||
| 23 | barrier(); | ||
| 24 | |||
| 25 | __raw_writel(c, KS8695_UART_PA + KS8695_URTH); | ||
| 26 | } | ||
| 27 | |||
| 28 | static inline void flush(void) | ||
| 29 | { | ||
| 30 | while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) | ||
| 31 | barrier(); | ||
| 32 | } | ||
| 33 | |||
| 34 | #define arch_decomp_setup() | ||
| 35 | #define arch_decomp_wdog() | ||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-ks8695/vmalloc.h b/include/asm-arm/arch-ks8695/vmalloc.h deleted file mode 100644 index d1d88e58117d..000000000000 --- a/include/asm-arm/arch-ks8695/vmalloc.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Ben Dooks | ||
| 5 | * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * KS8695 vmalloc definition | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_VMALLOC_H | ||
| 15 | #define __ASM_ARCH_VMALLOC_H | ||
| 16 | |||
| 17 | #define VMALLOC_END (KS8695_IO_VA & PGDIR_MASK) | ||
| 18 | |||
| 19 | #endif | ||
diff --git a/include/asm-arm/arch-l7200/aux_reg.h b/include/asm-arm/arch-l7200/aux_reg.h deleted file mode 100644 index 762cbc76c501..000000000000 --- a/include/asm-arm/arch-l7200/aux_reg.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/aux_reg.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) | ||
| 5 | * | ||
| 6 | * Changelog: | ||
| 7 | * 08-02-2000 SJH Created file | ||
| 8 | */ | ||
| 9 | #ifndef _ASM_ARCH_AUXREG_H | ||
| 10 | #define _ASM_ARCH_AUXREG_H | ||
| 11 | |||
| 12 | #include <asm/arch/hardware.h> | ||
| 13 | |||
| 14 | #define l7200aux_reg *((volatile unsigned int *) (AUX_BASE)) | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Auxillary register values | ||
| 18 | */ | ||
| 19 | #define AUX_CLEAR 0x00000000 | ||
| 20 | #define AUX_DIAG_LED_ON 0x00000002 | ||
| 21 | #define AUX_RTS_UART1 0x00000004 | ||
| 22 | #define AUX_DTR_UART1 0x00000008 | ||
| 23 | #define AUX_KBD_COLUMN_12_HIGH 0x00000010 | ||
| 24 | #define AUX_KBD_COLUMN_12_OFF 0x00000020 | ||
| 25 | #define AUX_KBD_COLUMN_13_HIGH 0x00000040 | ||
| 26 | #define AUX_KBD_COLUMN_13_OFF 0x00000080 | ||
| 27 | |||
| 28 | #endif | ||
diff --git a/include/asm-arm/arch-l7200/debug-macro.S b/include/asm-arm/arch-l7200/debug-macro.S deleted file mode 100644 index 846473318e8b..000000000000 --- a/include/asm-arm/arch-l7200/debug-macro.S +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-l7200/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .equ io_virt, IO_BASE | ||
| 15 | .equ io_phys, IO_START | ||
| 16 | |||
| 17 | .macro addruart,rx | ||
| 18 | mrc p15, 0, \rx, c1, c0 | ||
| 19 | tst \rx, #1 @ MMU enabled? | ||
| 20 | moveq \rx, #io_phys @ physical base address | ||
| 21 | movne \rx, #io_virt @ virtual address | ||
| 22 | add \rx, \rx, #0x00044000 @ UART1 | ||
| 23 | @ add \rx, \rx, #0x00045000 @ UART2 | ||
| 24 | .endm | ||
| 25 | |||
| 26 | .macro senduart,rd,rx | ||
| 27 | str \rd, [\rx, #0x0] @ UARTDR | ||
| 28 | .endm | ||
| 29 | |||
| 30 | .macro waituart,rd,rx | ||
| 31 | 1001: ldr \rd, [\rx, #0x18] @ UARTFLG | ||
| 32 | tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full | ||
| 33 | bne 1001b | ||
| 34 | .endm | ||
| 35 | |||
| 36 | .macro busyuart,rd,rx | ||
| 37 | 1001: ldr \rd, [\rx, #0x18] @ UARTFLG | ||
| 38 | tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy | ||
| 39 | bne 1001b | ||
| 40 | .endm | ||
diff --git a/include/asm-arm/arch-l7200/dma.h b/include/asm-arm/arch-l7200/dma.h deleted file mode 100644 index 4c7eca63f035..000000000000 --- a/include/asm-arm/arch-l7200/dma.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) | ||
| 5 | * | ||
| 6 | * Changelog: | ||
| 7 | * 08-29-2000 SJH Created | ||
| 8 | */ | ||
| 9 | #ifndef __ASM_ARCH_DMA_H | ||
| 10 | #define __ASM_ARCH_DMA_H | ||
| 11 | |||
| 12 | /* DMA is not yet implemented! It should be the same as acorn, copy over.. */ | ||
| 13 | |||
| 14 | /* | ||
| 15 | * This is the maximum DMA address that can be DMAd to. | ||
| 16 | * There should not be more than (0xd0000000 - 0xc0000000) | ||
| 17 | * bytes of RAM. | ||
| 18 | */ | ||
| 19 | #define MAX_DMA_ADDRESS 0xd0000000 | ||
| 20 | |||
| 21 | #define DMA_S0 0 | ||
| 22 | |||
| 23 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-l7200/entry-macro.S b/include/asm-arm/arch-l7200/entry-macro.S deleted file mode 100644 index d5e7294df1d5..000000000000 --- a/include/asm-arm/arch-l7200/entry-macro.S +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-l7200/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for L7200-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | |||
| 12 | .equ irq_base_addr, IO_BASE_2 | ||
| 13 | |||
| 14 | .macro disable_fiq | ||
| 15 | .endm | ||
| 16 | |||
| 17 | .macro get_irqnr_preamble, base, tmp | ||
| 18 | .endm | ||
| 19 | |||
| 20 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 24 | mov \irqstat, #irq_base_addr @ Virt addr IRQ regs | ||
| 25 | add \irqstat, \irqstat, #0x00001000 @ Status reg | ||
| 26 | ldr \irqstat, [\irqstat, #0] @ get interrupts | ||
| 27 | mov \irqnr, #0 | ||
| 28 | 1001: tst \irqstat, #1 | ||
| 29 | addeq \irqnr, \irqnr, #1 | ||
| 30 | moveq \irqstat, \irqstat, lsr #1 | ||
| 31 | tsteq \irqnr, #32 | ||
| 32 | beq 1001b | ||
| 33 | teq \irqnr, #32 | ||
| 34 | .endm | ||
| 35 | |||
diff --git a/include/asm-arm/arch-l7200/gp_timers.h b/include/asm-arm/arch-l7200/gp_timers.h deleted file mode 100644 index 6f20962df248..000000000000 --- a/include/asm-arm/arch-l7200/gp_timers.h +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/gp_timers.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) | ||
| 5 | * | ||
| 6 | * Changelog: | ||
| 7 | * 07-28-2000 SJH Created file | ||
| 8 | * 08-02-2000 SJH Used structure for registers | ||
| 9 | */ | ||
| 10 | #ifndef _ASM_ARCH_GPTIMERS_H | ||
| 11 | #define _ASM_ARCH_GPTIMERS_H | ||
| 12 | |||
| 13 | #include <asm/arch/hardware.h> | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Layout of L7200 general purpose timer registers | ||
| 17 | */ | ||
| 18 | struct GPT_Regs { | ||
| 19 | unsigned int TIMERLOAD; | ||
| 20 | unsigned int TIMERVALUE; | ||
| 21 | unsigned int TIMERCONTROL; | ||
| 22 | unsigned int TIMERCLEAR; | ||
| 23 | }; | ||
| 24 | |||
| 25 | #define GPT_BASE (IO_BASE_2 + 0x3000) | ||
| 26 | #define l7200_timer1_regs ((volatile struct GPT_Regs *) (GPT_BASE)) | ||
| 27 | #define l7200_timer2_regs ((volatile struct GPT_Regs *) (GPT_BASE + 0x20)) | ||
| 28 | |||
| 29 | /* | ||
| 30 | * General register values | ||
| 31 | */ | ||
| 32 | #define GPT_PRESCALE_1 0x00000000 | ||
| 33 | #define GPT_PRESCALE_16 0x00000004 | ||
| 34 | #define GPT_PRESCALE_256 0x00000008 | ||
| 35 | #define GPT_MODE_FREERUN 0x00000000 | ||
| 36 | #define GPT_MODE_PERIODIC 0x00000040 | ||
| 37 | #define GPT_ENABLE 0x00000080 | ||
| 38 | #define GPT_BZTOG 0x00000100 | ||
| 39 | #define GPT_BZMOD 0x00000200 | ||
| 40 | #define GPT_LOAD_MASK 0x0000ffff | ||
| 41 | |||
| 42 | #endif | ||
diff --git a/include/asm-arm/arch-l7200/gpio.h b/include/asm-arm/arch-l7200/gpio.h deleted file mode 100644 index 0b63e4239bdd..000000000000 --- a/include/asm-arm/arch-l7200/gpio.h +++ /dev/null | |||
| @@ -1,105 +0,0 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | /* | ||
| 3 | * linux/include/asm-arm/arch-l7200/gpio.h | ||
| 4 | * | ||
| 5 | * Registers and helper functions for the L7200 Link-Up Systems | ||
| 6 | * GPIO. | ||
| 7 | * | ||
| 8 | * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) | ||
| 9 | * | ||
| 10 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 11 | * License. See the file COPYING in the main directory of this archive for | ||
| 12 | * more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | |||
| 17 | #define GPIO_OFF 0x00005000 /* Offset from IO_START to the GPIO reg's. */ | ||
| 18 | |||
| 19 | /* IO_START and IO_BASE are defined in hardware.h */ | ||
| 20 | |||
| 21 | #define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */ | ||
| 22 | #define GPIO_BASE (IO_BASE_2 + GPIO_OFF) /* Virtual addr of the GPIO reg. */ | ||
| 23 | |||
| 24 | /* Offsets from the start of the GPIO for all the registers. */ | ||
| 25 | #define PADR_OFF 0x000 | ||
| 26 | #define PADDR_OFF 0x004 | ||
| 27 | #define PASBSR_OFF 0x008 | ||
| 28 | #define PAEENR_OFF 0x00c | ||
| 29 | #define PAESNR_OFF 0x010 | ||
| 30 | #define PAESTR_OFF 0x014 | ||
| 31 | #define PAIMR_OFF 0x018 | ||
| 32 | #define PAINT_OFF 0x01c | ||
| 33 | |||
| 34 | #define PBDR_OFF 0x020 | ||
| 35 | #define PBDDR_OFF 0x024 | ||
| 36 | #define PBSBSR_OFF 0x028 | ||
| 37 | #define PBIMR_OFF 0x038 | ||
| 38 | #define PBINT_OFF 0x03c | ||
| 39 | |||
| 40 | #define PCDR_OFF 0x040 | ||
| 41 | #define PCDDR_OFF 0x044 | ||
| 42 | #define PCSBSR_OFF 0x048 | ||
| 43 | #define PCIMR_OFF 0x058 | ||
| 44 | #define PCINT_OFF 0x05c | ||
| 45 | |||
| 46 | #define PDDR_OFF 0x060 | ||
| 47 | #define PDDDR_OFF 0x064 | ||
| 48 | #define PDSBSR_OFF 0x068 | ||
| 49 | #define PDEENR_OFF 0x06c | ||
| 50 | #define PDESNR_OFF 0x070 | ||
| 51 | #define PDESTR_OFF 0x074 | ||
| 52 | #define PDIMR_OFF 0x078 | ||
| 53 | #define PDINT_OFF 0x07c | ||
| 54 | |||
| 55 | #define PEDR_OFF 0x080 | ||
| 56 | #define PEDDR_OFF 0x084 | ||
| 57 | #define PESBSR_OFF 0x088 | ||
| 58 | #define PEEENR_OFF 0x08c | ||
| 59 | #define PEESNR_OFF 0x090 | ||
| 60 | #define PEESTR_OFF 0x094 | ||
| 61 | #define PEIMR_OFF 0x098 | ||
| 62 | #define PEINT_OFF 0x09c | ||
| 63 | |||
| 64 | /* Define the GPIO registers for use by device drivers and the kernel. */ | ||
| 65 | #define PADR (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF)) | ||
| 66 | #define PADDR (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF)) | ||
| 67 | #define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF)) | ||
| 68 | #define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF)) | ||
| 69 | #define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF)) | ||
| 70 | #define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF)) | ||
| 71 | #define PAIMR (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF)) | ||
| 72 | #define PAINT (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF)) | ||
| 73 | |||
| 74 | #define PBDR (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF)) | ||
| 75 | #define PBDDR (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF)) | ||
| 76 | #define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF)) | ||
| 77 | #define PBIMR (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF)) | ||
| 78 | #define PBINT (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF)) | ||
| 79 | |||
| 80 | #define PCDR (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF)) | ||
| 81 | #define PCDDR (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF)) | ||
| 82 | #define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF)) | ||
| 83 | #define PCIMR (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF)) | ||
| 84 | #define PCINT (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF)) | ||
| 85 | |||
| 86 | #define PDDR (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF)) | ||
| 87 | #define PDDDR (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF)) | ||
| 88 | #define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF)) | ||
| 89 | #define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF)) | ||
| 90 | #define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF)) | ||
| 91 | #define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF)) | ||
| 92 | #define PDIMR (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF)) | ||
| 93 | #define PDINT (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF)) | ||
| 94 | |||
| 95 | #define PEDR (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF)) | ||
| 96 | #define PEDDR (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF)) | ||
| 97 | #define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF)) | ||
| 98 | #define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF)) | ||
| 99 | #define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF)) | ||
| 100 | #define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF)) | ||
| 101 | #define PEIMR (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF)) | ||
| 102 | #define PEINT (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF)) | ||
| 103 | |||
| 104 | #define VEE_EN 0x02 | ||
| 105 | #define BACKLIGHT_EN 0x04 | ||
diff --git a/include/asm-arm/arch-l7200/hardware.h b/include/asm-arm/arch-l7200/hardware.h deleted file mode 100644 index 2ab43f3a4a8d..000000000000 --- a/include/asm-arm/arch-l7200/hardware.h +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) | ||
| 5 | * Steve Hill (sjhill@cotw.com) | ||
| 6 | * | ||
| 7 | * This file contains the hardware definitions for the | ||
| 8 | * LinkUp Systems L7200 SOC development board. | ||
| 9 | * | ||
| 10 | * Changelog: | ||
| 11 | * 02-01-2000 RS Created L7200 version, derived from rpc code | ||
| 12 | * 03-21-2000 SJH Cleaned up file | ||
| 13 | * 04-21-2000 RS Changed mapping of I/O in virtual space | ||
| 14 | * 04-25-2000 SJH Removed unused symbols and such | ||
| 15 | * 05-05-2000 SJH Complete rewrite | ||
| 16 | * 07-31-2000 SJH Added undocumented debug auxillary port to | ||
| 17 | * get at last two columns for keyboard driver | ||
| 18 | */ | ||
| 19 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 20 | #define __ASM_ARCH_HARDWARE_H | ||
| 21 | |||
| 22 | /* Hardware addresses of major areas. | ||
| 23 | * *_START is the physical address | ||
| 24 | * *_SIZE is the size of the region | ||
| 25 | * *_BASE is the virtual address | ||
| 26 | */ | ||
| 27 | #define RAM_START 0xf0000000 | ||
| 28 | #define RAM_SIZE 0x02000000 | ||
| 29 | #define RAM_BASE 0xc0000000 | ||
| 30 | |||
| 31 | #define IO_START 0x80000000 /* I/O */ | ||
| 32 | #define IO_SIZE 0x01000000 | ||
| 33 | #define IO_BASE 0xd0000000 | ||
| 34 | |||
| 35 | #define IO_START_2 0x90000000 /* I/O */ | ||
| 36 | #define IO_SIZE_2 0x01000000 | ||
| 37 | #define IO_BASE_2 0xd1000000 | ||
| 38 | |||
| 39 | #define AUX_START 0x1a000000 /* AUX PORT */ | ||
| 40 | #define AUX_SIZE 0x01000000 | ||
| 41 | #define AUX_BASE 0xd2000000 | ||
| 42 | |||
| 43 | #define FLASH1_START 0x00000000 /* FLASH BANK 1 */ | ||
| 44 | #define FLASH1_SIZE 0x01000000 | ||
| 45 | #define FLASH1_BASE 0xd3000000 | ||
| 46 | |||
| 47 | #define FLASH2_START 0x10000000 /* FLASH BANK 2 */ | ||
| 48 | #define FLASH2_SIZE 0x01000000 | ||
| 49 | #define FLASH2_BASE 0xd4000000 | ||
| 50 | |||
| 51 | #define ISA_START 0x20000000 /* ISA */ | ||
| 52 | #define ISA_SIZE 0x20000000 | ||
| 53 | #define ISA_BASE 0xe0000000 | ||
| 54 | |||
| 55 | #define PCIO_BASE IO_BASE | ||
| 56 | |||
| 57 | #endif | ||
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h deleted file mode 100644 index e24a10a7ed8c..000000000000 --- a/include/asm-arm/arch-l7200/io.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) | ||
| 5 | * | ||
| 6 | * Changelog: | ||
| 7 | * 03-21-2000 SJH Created from linux/include/asm-arm/arch-nexuspci/io.h | ||
| 8 | * 08-31-2000 SJH Added in IO functions necessary for new drivers | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 11 | #define __ASM_ARM_ARCH_IO_H | ||
| 12 | |||
| 13 | #include <asm/arch/hardware.h> | ||
| 14 | |||
| 15 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 16 | |||
| 17 | /* | ||
| 18 | * There are not real ISA nor PCI buses, so we fake it. | ||
| 19 | */ | ||
| 20 | static inline void __iomem *__io(unsigned long addr) | ||
| 21 | { | ||
| 22 | return (void __iomem *)addr; | ||
| 23 | } | ||
| 24 | #define __io(a) __io(a) | ||
| 25 | #define __mem_pci(a) (a) | ||
| 26 | |||
| 27 | #endif | ||
diff --git a/include/asm-arm/arch-l7200/irqs.h b/include/asm-arm/arch-l7200/irqs.h deleted file mode 100644 index 7120c016e29e..000000000000 --- a/include/asm-arm/arch-l7200/irqs.h +++ /dev/null | |||
| @@ -1,56 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-l7200/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) | ||
| 5 | * Steve Hill (sjhill@cotw.com) | ||
| 6 | * | ||
| 7 | * Changelog: | ||
| 8 | * 01-02-2000 RS Create l7200 version | ||
| 9 | * 03-28-2000 SJH Removed unused interrupt | ||
| 10 | * 07-28-2000 SJH Added pseudo-keyboard interrupt | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * NOTE: The second timer (Timer 2) is used as the keyboard | ||
| 15 | * interrupt when the keyboard driver is enabled. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #define NR_IRQS 32 | ||
| 19 | |||
| 20 | #define IRQ_STWDOG 0 /* Watchdog timer */ | ||
| 21 | #define IRQ_PROG 1 /* Programmable interrupt */ | ||
| 22 | #define IRQ_DEBUG_RX 2 /* Comm Rx debug */ | ||
| 23 | #define IRQ_DEBUG_TX 3 /* Comm Tx debug */ | ||
| 24 | #define IRQ_GCTC1 4 /* Timer 1 */ | ||
| 25 | #define IRQ_GCTC2 5 /* Timer 2 / Keyboard */ | ||
| 26 | #define IRQ_DMA 6 /* DMA controller */ | ||
| 27 | #define IRQ_CLCD 7 /* Color LCD controller */ | ||
| 28 | #define IRQ_SM_RX 8 /* Smart card */ | ||
| 29 | #define IRQ_SM_TX 9 /* Smart cart */ | ||
| 30 | #define IRQ_SM_RST 10 /* Smart card */ | ||
| 31 | #define IRQ_SIB 11 /* Serial Interface Bus */ | ||
| 32 | #define IRQ_MMC 12 /* MultiMediaCard */ | ||
| 33 | #define IRQ_SSP1 13 /* Synchronous Serial Port 1 */ | ||
| 34 | #define IRQ_SSP2 14 /* Synchronous Serial Port 1 */ | ||
| 35 | #define IRQ_SPI 15 /* SPI slave */ | ||
| 36 | #define IRQ_UART_1 16 /* UART 1 */ | ||
| 37 | #define IRQ_UART_2 17 /* UART 2 */ | ||
| 38 | #define IRQ_IRDA 18 /* IRDA */ | ||
| 39 | #define IRQ_RTC_TICK 19 /* Real Time Clock tick */ | ||
| 40 | #define IRQ_RTC_ALARM 20 /* Real Time Clock alarm */ | ||
| 41 | #define IRQ_GPIO 21 /* General Purpose IO */ | ||
| 42 | #define IRQ_GPIO_DMA 22 /* General Purpose IO, DMA */ | ||
| 43 | #define IRQ_M2M 23 /* Memory to memory DMA */ | ||
| 44 | #define IRQ_RESERVED 24 /* RESERVED, don't use */ | ||
| 45 | #define IRQ_INTF 25 /* External active low interrupt */ | ||
| 46 | #define IRQ_INT0 26 /* External active low interrupt */ | ||
| 47 | #define IRQ_INT1 27 /* External active low interrupt */ | ||
| 48 | #define IRQ_INT2 28 /* External active low interrupt */ | ||
| 49 | #define IRQ_UCB1200 29 /* Interrupt generated by UCB1200*/ | ||
| 50 | #define IRQ_BAT_LO 30 /* Low batery or external power */ | ||
| 51 | #define IRQ_MEDIA_CHG 31 /* Media change interrupt */ | ||
| 52 | |||
| 53 | /* | ||
| 54 | * This is the offset of the FIQ "IRQ" numbers | ||
| 55 | */ | ||
| 56 | #define FIQ_START 64 | ||
diff --git a/include/asm-arm/arch-l7200/memory.h b/include/asm-arm/arch-l7200/memory.h deleted file mode 100644 index 402df637e740..000000000000 --- a/include/asm-arm/arch-l7200/memory.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2000 Steve Hill (sjhill@cotw.com) | ||
| 5 | * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net) | ||
| 6 | * | ||
| 7 | * Changelog: | ||
| 8 | * 03-13-2000 SJH Created | ||
| 9 | * 04-13-2000 RS Changed bus macros for new addr | ||
| 10 | * 05-03-2000 SJH Removed bus macros and fixed virt_to_phys macro | ||
| 11 | */ | ||
| 12 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 13 | #define __ASM_ARCH_MEMORY_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Physical DRAM offset on the L7200 SDB. | ||
| 17 | */ | ||
| 18 | #define PHYS_OFFSET UL(0xf0000000) | ||
| 19 | |||
| 20 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 21 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Cache flushing area - ROM | ||
| 25 | */ | ||
| 26 | #define FLUSH_BASE_PHYS 0x40000000 | ||
| 27 | #define FLUSH_BASE 0xdf000000 | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/include/asm-arm/arch-l7200/pmpcon.h b/include/asm-arm/arch-l7200/pmpcon.h deleted file mode 100644 index 730056c194be..000000000000 --- a/include/asm-arm/arch-l7200/pmpcon.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | /* | ||
| 3 | * linux/include/asm-arm/arch-l7200/pmpcon.h | ||
| 4 | * | ||
| 5 | * Registers and helper functions for the L7200 Link-Up Systems | ||
| 6 | * DC/DC converter register. | ||
| 7 | * | ||
| 8 | * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) | ||
| 9 | * | ||
| 10 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 11 | * License. See the file COPYING in the main directory of this archive for | ||
| 12 | * more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | |||
| 17 | #define PMPCON_OFF 0x00006000 /* Offset from IO_START_2. */ | ||
| 18 | |||
| 19 | /* IO_START_2 and IO_BASE_2 are defined in hardware.h */ | ||
| 20 | |||
| 21 | #define PMPCON_START (IO_START_2 + PMPCON_OFF) /* Physical address of reg. */ | ||
| 22 | #define PMPCON_BASE (IO_BASE_2 + PMPCON_OFF) /* Virtual address of reg. */ | ||
| 23 | |||
| 24 | |||
| 25 | #define PMPCON (*(volatile unsigned int *)(PMPCON_BASE)) | ||
| 26 | |||
| 27 | #define PWM2_50CYCLE 0x800 | ||
| 28 | #define CONTRAST 0x9 | ||
| 29 | |||
| 30 | #define PWM1H (CONTRAST) | ||
| 31 | #define PWM1L (CONTRAST << 4) | ||
| 32 | |||
| 33 | #define PMPCON_VALUE (PWM2_50CYCLE | PWM1L | PWM1H) | ||
| 34 | |||
| 35 | /* PMPCON = 0x811; // too light and fuzzy | ||
| 36 | * PMPCON = 0x844; | ||
| 37 | * PMPCON = 0x866; // better color poor depth | ||
| 38 | * PMPCON = 0x888; // Darker but better depth | ||
| 39 | * PMPCON = 0x899; // Darker even better depth | ||
| 40 | * PMPCON = 0x8aa; // too dark even better depth | ||
| 41 | * PMPCON = 0X8cc; // Way too dark | ||
| 42 | */ | ||
| 43 | |||
| 44 | /* As CONTRAST value increases the greater the depth perception and | ||
| 45 | * the darker the colors. | ||
| 46 | */ | ||
diff --git a/include/asm-arm/arch-l7200/pmu.h b/include/asm-arm/arch-l7200/pmu.h deleted file mode 100644 index 57faea76d1b3..000000000000 --- a/include/asm-arm/arch-l7200/pmu.h +++ /dev/null | |||
| @@ -1,125 +0,0 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | /* | ||
| 3 | * linux/include/asm-arm/arch-l7200/pmu.h | ||
| 4 | * | ||
| 5 | * Registers and helper functions for the L7200 Link-Up Systems | ||
| 6 | * Power Management Unit (PMU). | ||
| 7 | * | ||
| 8 | * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) | ||
| 9 | * | ||
| 10 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 11 | * License. See the file COPYING in the main directory of this archive for | ||
| 12 | * more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | |||
| 17 | #define PMU_OFF 0x00050000 /* Offset from IO_START to the PMU registers. */ | ||
| 18 | |||
| 19 | /* IO_START and IO_BASE are defined in hardware.h */ | ||
| 20 | |||
| 21 | #define PMU_START (IO_START + PMU_OFF) /* Physical addr. of the PMU reg. */ | ||
| 22 | #define PMU_BASE (IO_BASE + PMU_OFF) /* Virtual addr. of the PMU reg. */ | ||
| 23 | |||
| 24 | |||
| 25 | /* Define the PMU registers for use by device drivers and the kernel. */ | ||
| 26 | |||
| 27 | typedef struct { | ||
| 28 | unsigned int CURRENT; /* Current configuration register */ | ||
| 29 | unsigned int NEXT; /* Next configuration register */ | ||
| 30 | unsigned int reserved; | ||
| 31 | unsigned int RUN; /* Run configuration register */ | ||
| 32 | unsigned int COMM; /* Configuration command register */ | ||
| 33 | unsigned int SDRAM; /* SDRAM configuration bypass register */ | ||
| 34 | } pmu_interface; | ||
| 35 | |||
| 36 | #define PMU ((volatile pmu_interface *)(PMU_BASE)) | ||
| 37 | |||
| 38 | |||
| 39 | /* Macro's for reading the common register fields. */ | ||
| 40 | |||
| 41 | #define GET_TRANSOP(reg) ((reg >> 25) & 0x03) /* Bits 26-25 */ | ||
| 42 | #define GET_OSCEN(reg) ((reg >> 16) & 0x01) | ||
| 43 | #define GET_OSCMUX(reg) ((reg >> 15) & 0x01) | ||
| 44 | #define GET_PLLMUL(reg) ((reg >> 9) & 0x3f) /* Bits 14-9 */ | ||
| 45 | #define GET_PLLEN(reg) ((reg >> 8) & 0x01) | ||
| 46 | #define GET_PLLMUX(reg) ((reg >> 7) & 0x01) | ||
| 47 | #define GET_BCLK_DIV(reg) ((reg >> 3) & 0x03) /* Bits 4-3 */ | ||
| 48 | #define GET_SDRB_SEL(reg) ((reg >> 2) & 0x01) | ||
| 49 | #define GET_SDRF_SEL(reg) ((reg >> 1) & 0x01) | ||
| 50 | #define GET_FASTBUS(reg) (reg & 0x1) | ||
| 51 | |||
| 52 | /* CFG_NEXT register */ | ||
| 53 | |||
| 54 | #define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f) /* Bits 24-18 */ | ||
| 55 | #define CFG_NEXT_INTRET ((PMU->NEXT >> 17) & 0x01) | ||
| 56 | #define CFG_NEXT_SDR_STOP ((PMU->NEXT >> 6) & 0x01) | ||
| 57 | #define CFG_NEXT_SYSCLKEN ((PMU->NEXT >> 5) & 0x01) | ||
| 58 | |||
| 59 | /* Useful field values that can be used to construct the | ||
| 60 | * CFG_NEXT and CFG_RUN registers. | ||
| 61 | */ | ||
| 62 | |||
| 63 | #define TRANSOP_NOP 0<<25 /* NOCHANGE_NOSTALL */ | ||
| 64 | #define NOCHANGE_STALL 1<<25 | ||
| 65 | #define CHANGE_NOSTALL 2<<25 | ||
| 66 | #define CHANGE_STALL 3<<25 | ||
| 67 | |||
| 68 | #define INTRET 1<<17 | ||
| 69 | #define OSCEN 1<<16 | ||
| 70 | #define OSCMUX 1<<15 | ||
| 71 | |||
| 72 | /* PLL frequencies */ | ||
| 73 | |||
| 74 | #define PLLMUL_0 0<<9 /* 3.6864 MHz */ | ||
| 75 | #define PLLMUL_1 1<<9 /* ?????? MHz */ | ||
| 76 | #define PLLMUL_5 5<<9 /* 18.432 MHz */ | ||
| 77 | #define PLLMUL_10 10<<9 /* 36.864 MHz */ | ||
| 78 | #define PLLMUL_18 18<<9 /* ?????? MHz */ | ||
| 79 | #define PLLMUL_20 20<<9 /* 73.728 MHz */ | ||
| 80 | #define PLLMUL_32 32<<9 /* ?????? MHz */ | ||
| 81 | #define PLLMUL_35 35<<9 /* 129.024 MHz */ | ||
| 82 | #define PLLMUL_36 36<<9 /* ?????? MHz */ | ||
| 83 | #define PLLMUL_39 39<<9 /* ?????? MHz */ | ||
| 84 | #define PLLMUL_40 40<<9 /* 147.456 MHz */ | ||
| 85 | |||
| 86 | /* Clock recovery times */ | ||
| 87 | |||
| 88 | #define CRCLOCK_1 1<<18 | ||
| 89 | #define CRCLOCK_2 2<<18 | ||
| 90 | #define CRCLOCK_4 4<<18 | ||
| 91 | #define CRCLOCK_8 8<<18 | ||
| 92 | #define CRCLOCK_16 16<<18 | ||
| 93 | #define CRCLOCK_32 32<<18 | ||
| 94 | #define CRCLOCK_63 63<<18 | ||
| 95 | #define CRCLOCK_127 127<<18 | ||
| 96 | |||
| 97 | #define PLLEN 1<<8 | ||
| 98 | #define PLLMUX 1<<7 | ||
| 99 | #define SDR_STOP 1<<6 | ||
| 100 | #define SYSCLKEN 1<<5 | ||
| 101 | |||
| 102 | #define BCLK_DIV_4 2<<3 | ||
| 103 | #define BCLK_DIV_2 1<<3 | ||
| 104 | #define BCLK_DIV_1 0<<3 | ||
| 105 | |||
| 106 | #define SDRB_SEL 1<<2 | ||
| 107 | #define SDRF_SEL 1<<1 | ||
| 108 | #define FASTBUS 1<<0 | ||
| 109 | |||
| 110 | |||
| 111 | /* CFG_SDRAM */ | ||
| 112 | |||
| 113 | #define SDRREFFQ 1<<0 /* Only if SDRSTOPRQ is not set. */ | ||
| 114 | #define SDRREFACK 1<<1 /* Read-only */ | ||
| 115 | #define SDRSTOPRQ 1<<2 /* Only if SDRREFFQ is not set. */ | ||
| 116 | #define SDRSTOPACK 1<<3 /* Read-only */ | ||
| 117 | #define PICEN 1<<4 /* Enable Co-procesor */ | ||
| 118 | #define PICTEST 1<<5 | ||
| 119 | |||
| 120 | #define GET_SDRREFFQ ((PMU->SDRAM >> 0) & 0x01) | ||
| 121 | #define GET_SDRREFACK ((PMU->SDRAM >> 1) & 0x01) /* Read-only */ | ||
| 122 | #define GET_SDRSTOPRQ ((PMU->SDRAM >> 2) & 0x01) | ||
| 123 | #define GET_SDRSTOPACK ((PMU->SDRAM >> 3) & 0x01) /* Read-only */ | ||
| 124 | #define GET_PICEN ((PMU->SDRAM >> 4) & 0x01) | ||
| 125 | #define GET_PICTEST ((PMU->SDRAM >> 5) & 0x01) | ||
diff --git a/include/asm-arm/arch-l7200/serial.h b/include/asm-arm/arch-l7200/serial.h deleted file mode 100644 index defb8b7fca73..000000000000 --- a/include/asm-arm/arch-l7200/serial.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/serial.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net) | ||
| 5 | * Steve Hill (sjhill@cotw.com) | ||
| 6 | * | ||
| 7 | * Changelog: | ||
| 8 | * 03-20-2000 SJH Created | ||
| 9 | * 03-26-2000 SJH Added flags for serial ports | ||
| 10 | * 03-27-2000 SJH Corrected BASE_BAUD value | ||
| 11 | * 04-14-2000 RS Made register addr dependent on IO_BASE | ||
| 12 | * 05-03-2000 SJH Complete rewrite | ||
| 13 | * 05-09-2000 SJH Stripped out architecture specific serial stuff | ||
| 14 | * and placed it in a separate file | ||
| 15 | * 07-28-2000 SJH Moved base baud rate variable | ||
| 16 | */ | ||
| 17 | #ifndef __ASM_ARCH_SERIAL_H | ||
| 18 | #define __ASM_ARCH_SERIAL_H | ||
| 19 | |||
| 20 | /* | ||
| 21 | * This assumes you have a 3.6864 MHz clock for your UART. | ||
| 22 | */ | ||
| 23 | #define BASE_BAUD 3686400 | ||
| 24 | |||
| 25 | /* | ||
| 26 | * Standard COM flags | ||
| 27 | */ | ||
| 28 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) | ||
| 29 | |||
| 30 | #define STD_SERIAL_PORT_DEFNS \ | ||
| 31 | /* MAGIC UART CLK PORT IRQ FLAGS */ \ | ||
| 32 | { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS }, /* ttyLU0 */ \ | ||
| 33 | { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS }, /* ttyLU1 */ \ | ||
| 34 | |||
| 35 | #define EXTRA_SERIAL_PORT_DEFNS | ||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-l7200/serial_l7200.h b/include/asm-arm/arch-l7200/serial_l7200.h deleted file mode 100644 index b1008a9d23e5..000000000000 --- a/include/asm-arm/arch-l7200/serial_l7200.h +++ /dev/null | |||
| @@ -1,101 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/serial_l7200.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2000 Steven Hill (sjhill@cotw.com) | ||
| 5 | * | ||
| 6 | * Changelog: | ||
| 7 | * 05-09-2000 SJH Created | ||
| 8 | */ | ||
| 9 | #ifndef __ASM_ARCH_SERIAL_L7200_H | ||
| 10 | #define __ASM_ARCH_SERIAL_L7200_H | ||
| 11 | |||
| 12 | #include <asm/arch/memory.h> | ||
| 13 | |||
| 14 | /* | ||
| 15 | * This assumes you have a 3.6864 MHz clock for your UART. | ||
| 16 | */ | ||
| 17 | #define BASE_BAUD 3686400 | ||
| 18 | |||
| 19 | /* | ||
| 20 | * UART base register addresses | ||
| 21 | */ | ||
| 22 | #define UART1_BASE (IO_BASE + 0x00044000) | ||
| 23 | #define UART2_BASE (IO_BASE + 0x00045000) | ||
| 24 | |||
| 25 | /* | ||
| 26 | * UART register offsets | ||
| 27 | */ | ||
| 28 | #define UARTDR 0x00 /* Tx/Rx data */ | ||
| 29 | #define RXSTAT 0x04 /* Rx status */ | ||
| 30 | #define H_UBRLCR 0x08 /* mode register high */ | ||
| 31 | #define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/ | ||
| 32 | #define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/ | ||
| 33 | #define UARTCON 0x14 /* control register */ | ||
| 34 | #define UARTFLG 0x18 /* flag register */ | ||
| 35 | #define UARTINTSTAT 0x1C /* FIFO IRQ status register */ | ||
| 36 | #define UARTINTMASK 0x20 /* FIFO IRQ mask register */ | ||
| 37 | |||
| 38 | /* | ||
| 39 | * UART baud rate register values | ||
| 40 | */ | ||
| 41 | #define BR_110 0x827 | ||
| 42 | #define BR_1200 0x06e | ||
| 43 | #define BR_2400 0x05f | ||
| 44 | #define BR_4800 0x02f | ||
| 45 | #define BR_9600 0x017 | ||
| 46 | #define BR_14400 0x00f | ||
| 47 | #define BR_19200 0x00b | ||
| 48 | #define BR_38400 0x005 | ||
| 49 | #define BR_57600 0x003 | ||
| 50 | #define BR_76800 0x002 | ||
| 51 | #define BR_115200 0x001 | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Receiver status register (RXSTAT) mask values | ||
| 55 | */ | ||
| 56 | #define RXSTAT_NO_ERR 0x00 /* No error */ | ||
| 57 | #define RXSTAT_FRM_ERR 0x01 /* Framing error */ | ||
| 58 | #define RXSTAT_PAR_ERR 0x02 /* Parity error */ | ||
| 59 | #define RXSTAT_OVR_ERR 0x04 /* Overrun error */ | ||
| 60 | |||
| 61 | /* | ||
| 62 | * High byte of UART bit rate and line control register (H_UBRLCR) values | ||
| 63 | */ | ||
| 64 | #define UBRLCR_BRK 0x01 /* generate break on tx */ | ||
| 65 | #define UBRLCR_PEN 0x02 /* enable parity */ | ||
| 66 | #define UBRLCR_PDIS 0x00 /* disable parity */ | ||
| 67 | #define UBRLCR_EVEN 0x04 /* 1= even parity,0 = odd parity */ | ||
| 68 | #define UBRLCR_STP2 0x08 /* transmit 2 stop bits */ | ||
| 69 | #define UBRLCR_FIFO 0x10 /* enable FIFO */ | ||
| 70 | #define UBRLCR_LEN5 0x60 /* word length5 */ | ||
| 71 | #define UBRLCR_LEN6 0x40 /* word length6 */ | ||
| 72 | #define UBRLCR_LEN7 0x20 /* word length7 */ | ||
| 73 | #define UBRLCR_LEN8 0x00 /* word length8 */ | ||
| 74 | |||
| 75 | /* | ||
| 76 | * UART control register (UARTCON) values | ||
| 77 | */ | ||
| 78 | #define UARTCON_UARTEN 0x01 /* Enable UART */ | ||
| 79 | #define UARTCON_DMAONERR 0x08 /* Mask RxDmaRq when errors occur */ | ||
| 80 | |||
| 81 | /* | ||
| 82 | * UART flag register (UARTFLG) mask values | ||
| 83 | */ | ||
| 84 | #define UARTFLG_UTXFF 0x20 /* Transmit FIFO full */ | ||
| 85 | #define UARTFLG_URXFE 0x10 /* Receiver FIFO empty */ | ||
| 86 | #define UARTFLG_UBUSY 0x08 /* Transmitter busy */ | ||
| 87 | #define UARTFLG_DCD 0x04 /* Data carrier detect */ | ||
| 88 | #define UARTFLG_DSR 0x02 /* Data set ready */ | ||
| 89 | #define UARTFLG_CTS 0x01 /* Clear to send */ | ||
| 90 | |||
| 91 | /* | ||
| 92 | * UART interrupt status/clear registers (UARTINTSTAT/CLR) values | ||
| 93 | */ | ||
| 94 | #define UART_TXINT 0x01 /* TX interrupt */ | ||
| 95 | #define UART_RXINT 0x02 /* RX interrupt */ | ||
| 96 | #define UART_RXERRINT 0x04 /* RX error interrupt */ | ||
| 97 | #define UART_MSINT 0x08 /* Modem Status interrupt */ | ||
| 98 | #define UART_UDINT 0x10 /* UART Disabled interrupt */ | ||
| 99 | #define UART_ALLIRQS 0x1f /* All interrupts */ | ||
| 100 | |||
| 101 | #endif | ||
diff --git a/include/asm-arm/arch-l7200/sib.h b/include/asm-arm/arch-l7200/sib.h deleted file mode 100644 index bf4364ee2535..000000000000 --- a/include/asm-arm/arch-l7200/sib.h +++ /dev/null | |||
| @@ -1,119 +0,0 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | /* | ||
| 3 | * linux/include/asm-arm/arch-l7200/sib.h | ||
| 4 | * | ||
| 5 | * Registers and helper functions for the Serial Interface Bus. | ||
| 6 | * | ||
| 7 | * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) | ||
| 8 | * | ||
| 9 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 10 | * License. See the file COPYING in the main directory of this archive for | ||
| 11 | * more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /****************************************************************************/ | ||
| 15 | |||
| 16 | #define SIB_OFF 0x00040000 /* Offset from IO_START to the SIB reg's. */ | ||
| 17 | |||
| 18 | /* IO_START and IO_BASE are defined in hardware.h */ | ||
| 19 | |||
| 20 | #define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */ | ||
| 21 | #define SIB_BASE (IO_BASE + SIB_OFF) /* Virtual addr of the SIB reg. */ | ||
| 22 | |||
| 23 | /* Offsets from the start of the SIB for all the registers. */ | ||
| 24 | |||
| 25 | /* Define the SIB registers for use by device drivers and the kernel. */ | ||
| 26 | |||
| 27 | typedef struct | ||
| 28 | { | ||
| 29 | unsigned int MCCR; /* SIB Control Register Offset: 0x00 */ | ||
| 30 | unsigned int RES1; /* Reserved Offset: 0x04 */ | ||
| 31 | unsigned int MCDR0; /* SIB Data Register 0 Offset: 0x08 */ | ||
| 32 | unsigned int MCDR1; /* SIB Data Register 1 Offset: 0x0c */ | ||
| 33 | unsigned int MCDR2; /* SIB Data Register 2 (UCB1x00) Offset: 0x10 */ | ||
| 34 | unsigned int RES2; /* Reserved Offset: 0x14 */ | ||
| 35 | unsigned int MCSR; /* SIB Status Register Offset: 0x18 */ | ||
| 36 | } SIB_Interface; | ||
| 37 | |||
| 38 | #define SIB ((volatile SIB_Interface *) (SIB_BASE)) | ||
| 39 | |||
| 40 | /* MCCR */ | ||
| 41 | |||
| 42 | #define INTERNAL_FREQ 9216000 /* Hertz */ | ||
| 43 | #define AUDIO_FREQ 5000 /* Hertz */ | ||
| 44 | #define TELECOM_FREQ 5000 /* Hertz */ | ||
| 45 | |||
| 46 | #define AUDIO_DIVIDE (INTERNAL_FREQ / (32 * AUDIO_FREQ)) | ||
| 47 | #define TELECOM_DIVIDE (INTERNAL_FREQ / (32 * TELECOM_FREQ)) | ||
| 48 | |||
| 49 | #define MCCR_ASD57 AUDIO_DIVIDE | ||
| 50 | #define MCCR_TSD57 (TELECOM_DIVIDE << 8) | ||
| 51 | #define MCCR_MCE (1 << 16) /* SIB enable */ | ||
| 52 | #define MCCR_ECS (1 << 17) /* External Clock Select */ | ||
| 53 | #define MCCR_ADM (1 << 18) /* A/D Data Sampling */ | ||
| 54 | #define MCCR_PMC (1 << 26) /* PIN Multiplexer Control */ | ||
| 55 | |||
| 56 | |||
| 57 | #define GET_ASD ((SIB->MCCR >> 0) & 0x3f) /* Audio Sample Rate Div. */ | ||
| 58 | #define GET_TSD ((SIB->MCCR >> 8) & 0x3f) /* Telcom Sample Rate Div. */ | ||
| 59 | #define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */ | ||
| 60 | #define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */ | ||
| 61 | #define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */ | ||
| 62 | #define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */ | ||
| 63 | #define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */ | ||
| 64 | #define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */ | ||
| 65 | #define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */ | ||
| 66 | #define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */ | ||
| 67 | #define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */ | ||
| 68 | #define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */ | ||
| 69 | #define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */ | ||
| 70 | #define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */ | ||
| 71 | |||
| 72 | /* MCDR0 */ | ||
| 73 | |||
| 74 | #define AUDIO_RECV ((SIB->MCDR0 >> 4) & 0xfff) | ||
| 75 | #define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4)) | ||
| 76 | |||
| 77 | /* MCDR1 */ | ||
| 78 | |||
| 79 | #define TELECOM_RECV ((SIB->MCDR1 >> 2) & 032fff) | ||
| 80 | #define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2)) | ||
| 81 | |||
| 82 | |||
| 83 | /* MCSR */ | ||
| 84 | |||
| 85 | #define MCSR_ATU (1 << 4) /* Audio Transmit FIFO Underrun */ | ||
| 86 | #define MCSR_ARO (1 << 5) /* Audio Receive FIFO Underrun */ | ||
| 87 | #define MCSR_TTU (1 << 6) /* TELECOM Transmit FIFO Underrun */ | ||
| 88 | #define MCSR_TRO (1 << 7) /* TELECOM Receive FIFO Underrun */ | ||
| 89 | |||
| 90 | #define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO) | ||
| 91 | |||
| 92 | |||
| 93 | #define GET_ATS ((SIB->MCSR >> 0) & 0x01) /* Audio Transmit FIFO Service Req*/ | ||
| 94 | #define GET_ARS ((SIB->MCSR >> 1) & 0x01) /* Audio Recv FIFO Service Request*/ | ||
| 95 | #define GET_TTS ((SIB->MCSR >> 2) & 0x01) /* TELECOM Transmit FIFO Flag */ | ||
| 96 | #define GET_TRS ((SIB->MCSR >> 3) & 0x01) /* TELECOM Recv FIFO Service Req. */ | ||
| 97 | #define GET_ATU ((SIB->MCSR >> 4) & 0x01) /* Audio Transmit FIFO Underrun */ | ||
| 98 | #define GET_ARO ((SIB->MCSR >> 5) & 0x01) /* Audio Receive FIFO Underrun */ | ||
| 99 | #define GET_TTU ((SIB->MCSR >> 6) & 0x01) /* TELECOM Transmit FIFO Underrun */ | ||
| 100 | #define GET_TRO ((SIB->MCSR >> 7) & 0x01) /* TELECOM Receive FIFO Underrun */ | ||
| 101 | #define GET_ANF ((SIB->MCSR >> 8) & 0x01) /* Audio Transmit FIFO not full */ | ||
| 102 | #define GET_ANE ((SIB->MCSR >> 9) & 0x01) /* Audio Receive FIFO not empty */ | ||
| 103 | #define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */ | ||
| 104 | #define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */ | ||
| 105 | #define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */ | ||
| 106 | #define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */ | ||
| 107 | #define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */ | ||
| 108 | #define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */ | ||
| 109 | |||
| 110 | /* MCDR2 */ | ||
| 111 | |||
| 112 | #define MCDR2_rW (1 << 16) | ||
| 113 | |||
| 114 | #define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff))) | ||
| 115 | #define MCDR2_WRITE_COMPLETE GET_CWC | ||
| 116 | |||
| 117 | #define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17)) | ||
| 118 | #define MCDR2_READ_COMPLETE GET_CRC | ||
| 119 | #define MCDR2_READ (SIB->MCDR2 & 0xffff) | ||
diff --git a/include/asm-arm/arch-l7200/sys-clock.h b/include/asm-arm/arch-l7200/sys-clock.h deleted file mode 100644 index 771c774f4815..000000000000 --- a/include/asm-arm/arch-l7200/sys-clock.h +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | /* | ||
| 3 | * linux/include/asm-arm/arch-l7200/sys-clock.h | ||
| 4 | * | ||
| 5 | * Registers and helper functions for the L7200 Link-Up Systems | ||
| 6 | * System clocks. | ||
| 7 | * | ||
| 8 | * (C) Copyright 2000, S A McConnell (samcconn@cotw.com) | ||
| 9 | * | ||
| 10 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 11 | * License. See the file COPYING in the main directory of this archive for | ||
| 12 | * more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | |||
| 17 | #define SYS_CLOCK_OFF 0x00050030 /* Offset from IO_START. */ | ||
| 18 | |||
| 19 | /* IO_START and IO_BASE are defined in hardware.h */ | ||
| 20 | |||
| 21 | #define SYS_CLOCK_START (IO_START + SYS_CLCOK_OFF) /* Physical address */ | ||
| 22 | #define SYS_CLOCK_BASE (IO_BASE + SYS_CLOCK_OFF) /* Virtual address */ | ||
| 23 | |||
| 24 | /* Define the interface to the SYS_CLOCK */ | ||
| 25 | |||
| 26 | typedef struct | ||
| 27 | { | ||
| 28 | unsigned int ENABLE; | ||
| 29 | unsigned int ESYNC; | ||
| 30 | unsigned int SELECT; | ||
| 31 | } sys_clock_interface; | ||
| 32 | |||
| 33 | #define SYS_CLOCK ((volatile sys_clock_interface *)(SYS_CLOCK_BASE)) | ||
| 34 | |||
| 35 | //#define CLOCK_EN (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF)) | ||
| 36 | //#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF)) | ||
| 37 | //#define CLOCK_SEL (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF)) | ||
| 38 | |||
| 39 | /* SYS_CLOCK -> ENABLE */ | ||
| 40 | |||
| 41 | #define SYN_EN 1<<0 | ||
| 42 | #define B18M_EN 1<<1 | ||
| 43 | #define CLK3M6_EN 1<<2 | ||
| 44 | #define BUART_EN 1<<3 | ||
| 45 | #define CLK18MU_EN 1<<4 | ||
| 46 | #define FIR_EN 1<<5 | ||
| 47 | #define MIRN_EN 1<<6 | ||
| 48 | #define UARTM_EN 1<<7 | ||
| 49 | #define SIBADC_EN 1<<8 | ||
| 50 | #define ALTD_EN 1<<9 | ||
| 51 | #define CLCLK_EN 1<<10 | ||
| 52 | |||
| 53 | /* SYS_CLOCK -> SELECT */ | ||
| 54 | |||
| 55 | #define CLK18M_DIV 1<<0 | ||
| 56 | #define MIR_SEL 1<<1 | ||
| 57 | #define SSP_SEL 1<<4 | ||
| 58 | #define MM_DIV 1<<5 | ||
| 59 | #define MM_SEL 1<<6 | ||
| 60 | #define ADC_SEL_2 0<<7 | ||
| 61 | #define ADC_SEL_4 1<<7 | ||
| 62 | #define ADC_SEL_8 3<<7 | ||
| 63 | #define ADC_SEL_16 7<<7 | ||
| 64 | #define ADC_SEL_32 0x0f<<7 | ||
| 65 | #define ADC_SEL_64 0x1f<<7 | ||
| 66 | #define ADC_SEL_128 0x3f<<7 | ||
| 67 | #define ALTD_SEL 1<<13 | ||
diff --git a/include/asm-arm/arch-l7200/system.h b/include/asm-arm/arch-l7200/system.h deleted file mode 100644 index efef950a5b5d..000000000000 --- a/include/asm-arm/arch-l7200/system.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/system.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2000 Steve Hill (sjhill@cotw.com) | ||
| 5 | * | ||
| 6 | * Changelog | ||
| 7 | * 03-21-2000 SJH Created | ||
| 8 | * 04-26-2000 SJH Fixed functions | ||
| 9 | * 05-03-2000 SJH Removed usage of obsolete 'iomd.h' | ||
| 10 | * 05-31-2000 SJH Properly implemented 'arch_idle' | ||
| 11 | */ | ||
| 12 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 13 | #define __ASM_ARCH_SYSTEM_H | ||
| 14 | |||
| 15 | #include <asm/arch/hardware.h> | ||
| 16 | |||
| 17 | static inline void arch_idle(void) | ||
| 18 | { | ||
| 19 | *(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */ | ||
| 20 | } | ||
| 21 | |||
| 22 | static inline void arch_reset(char mode) | ||
| 23 | { | ||
| 24 | if (mode == 's') { | ||
| 25 | cpu_reset(0); | ||
| 26 | } | ||
| 27 | } | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/include/asm-arm/arch-l7200/time.h b/include/asm-arm/arch-l7200/time.h deleted file mode 100644 index ea22f7fff9cd..000000000000 --- a/include/asm-arm/arch-l7200/time.h +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/time.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) | ||
| 5 | * Steve Hill (sjhill@cotw.com) | ||
| 6 | * | ||
| 7 | * Changelog: | ||
| 8 | * 01-02-2000 RS Created l7200 version, derived from rpc code | ||
| 9 | * 05-03-2000 SJH Complete rewrite | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_ARCH_TIME_H | ||
| 12 | #define _ASM_ARCH_TIME_H | ||
| 13 | |||
| 14 | #include <asm/arch/irqs.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * RTC base register address | ||
| 18 | */ | ||
| 19 | #define RTC_BASE (IO_BASE_2 + 0x2000) | ||
| 20 | |||
| 21 | /* | ||
| 22 | * RTC registers | ||
| 23 | */ | ||
| 24 | #define RTC_RTCDR (*(volatile unsigned char *) (RTC_BASE + 0x000)) | ||
| 25 | #define RTC_RTCMR (*(volatile unsigned char *) (RTC_BASE + 0x004)) | ||
| 26 | #define RTC_RTCS (*(volatile unsigned char *) (RTC_BASE + 0x008)) | ||
| 27 | #define RTC_RTCC (*(volatile unsigned char *) (RTC_BASE + 0x008)) | ||
| 28 | #define RTC_RTCDV (*(volatile unsigned char *) (RTC_BASE + 0x00c)) | ||
| 29 | #define RTC_RTCCR (*(volatile unsigned char *) (RTC_BASE + 0x010)) | ||
| 30 | |||
| 31 | /* | ||
| 32 | * RTCCR register values | ||
| 33 | */ | ||
| 34 | #define RTC_RATE_32 0x00 /* 32 Hz tick */ | ||
| 35 | #define RTC_RATE_64 0x10 /* 64 Hz tick */ | ||
| 36 | #define RTC_RATE_128 0x20 /* 128 Hz tick */ | ||
| 37 | #define RTC_RATE_256 0x30 /* 256 Hz tick */ | ||
| 38 | #define RTC_EN_ALARM 0x01 /* Enable alarm */ | ||
| 39 | #define RTC_EN_TIC 0x04 /* Enable counter */ | ||
| 40 | #define RTC_EN_STWDOG 0x08 /* Enable watchdog */ | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Handler for RTC timer interrupt | ||
| 44 | */ | ||
| 45 | static irqreturn_t | ||
| 46 | timer_interrupt(int irq, void *dev_id) | ||
| 47 | { | ||
| 48 | struct pt_regs *regs = get_irq_regs(); | ||
| 49 | do_timer(1); | ||
| 50 | #ifndef CONFIG_SMP | ||
| 51 | update_process_times(user_mode(regs)); | ||
| 52 | #endif | ||
| 53 | do_profile(regs); | ||
| 54 | RTC_RTCC = 0; /* Clear interrupt */ | ||
| 55 | |||
| 56 | return IRQ_HANDLED; | ||
| 57 | } | ||
| 58 | |||
| 59 | /* | ||
| 60 | * Set up RTC timer interrupt, and return the current time in seconds. | ||
| 61 | */ | ||
| 62 | void __init time_init(void) | ||
| 63 | { | ||
| 64 | RTC_RTCC = 0; /* Clear interrupt */ | ||
| 65 | |||
| 66 | timer_irq.handler = timer_interrupt; | ||
| 67 | |||
| 68 | setup_irq(IRQ_RTC_TICK, &timer_irq); | ||
| 69 | |||
| 70 | RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC; /* Set rate and enable timer */ | ||
| 71 | } | ||
| 72 | |||
| 73 | #endif | ||
diff --git a/include/asm-arm/arch-l7200/timex.h b/include/asm-arm/arch-l7200/timex.h deleted file mode 100644 index 3c3202620f00..000000000000 --- a/include/asm-arm/arch-l7200/timex.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net) | ||
| 5 | * Steve Hill (sjhill@cotw.com) | ||
| 6 | * | ||
| 7 | * 04-21-2000 RS Created file | ||
| 8 | * 05-03-2000 SJH Tick rate was wrong | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * On the ARM720T, clock ticks are set to 128 Hz. | ||
| 14 | * | ||
| 15 | * NOTE: The actual RTC value is set in 'time.h' which | ||
| 16 | * must be changed when choosing a different tick | ||
| 17 | * rate. The value of HZ in 'param.h' must also | ||
| 18 | * be changed to match below. | ||
| 19 | */ | ||
| 20 | #define CLOCK_TICK_RATE 128 | ||
diff --git a/include/asm-arm/arch-l7200/uncompress.h b/include/asm-arm/arch-l7200/uncompress.h deleted file mode 100644 index c5ba0adf4a5d..000000000000 --- a/include/asm-arm/arch-l7200/uncompress.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) | ||
| 5 | * | ||
| 6 | * Changelog: | ||
| 7 | * 05-01-2000 SJH Created | ||
| 8 | * 05-13-2000 SJH Filled in function bodies | ||
| 9 | * 07-26-2000 SJH Removed hard coded baud rate | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <asm/arch/hardware.h> | ||
| 13 | |||
| 14 | #define IO_UART IO_START + 0x00044000 | ||
| 15 | |||
| 16 | #define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v)) | ||
| 17 | #define __raw_readb(p) (*(volatile unsigned char *)(p)) | ||
| 18 | |||
| 19 | static inline void putc(int c) | ||
| 20 | { | ||
| 21 | while(__raw_readb(IO_UART + 0x18) & 0x20 || | ||
| 22 | __raw_readb(IO_UART + 0x18) & 0x08) | ||
| 23 | barrier(); | ||
| 24 | |||
| 25 | __raw_writeb(c, IO_UART + 0x00); | ||
| 26 | } | ||
| 27 | |||
| 28 | static inline void flush(void) | ||
| 29 | { | ||
| 30 | } | ||
| 31 | |||
| 32 | static __inline__ void arch_decomp_setup(void) | ||
| 33 | { | ||
| 34 | __raw_writeb(0x00, IO_UART + 0x08); /* Set HSB */ | ||
| 35 | __raw_writeb(0x00, IO_UART + 0x20); /* Disable IRQs */ | ||
| 36 | __raw_writeb(0x01, IO_UART + 0x14); /* Enable UART */ | ||
| 37 | } | ||
| 38 | |||
| 39 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-l7200/vmalloc.h b/include/asm-arm/arch-l7200/vmalloc.h deleted file mode 100644 index 816231eedaac..000000000000 --- a/include/asm-arm/arch-l7200/vmalloc.h +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-l7200/vmalloc.h | ||
| 3 | */ | ||
| 4 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
diff --git a/include/asm-arm/arch-lh7a40x/clocks.h b/include/asm-arm/arch-lh7a40x/clocks.h deleted file mode 100644 index 7d0ba18ad578..000000000000 --- a/include/asm-arm/arch-lh7a40x/clocks.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Marc Singer | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * version 2 as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_CLOCKS_H | ||
| 12 | #define __ASM_ARCH_CLOCKS_H | ||
| 13 | |||
| 14 | unsigned int fclkfreq_get (void); | ||
| 15 | unsigned int hclkfreq_get (void); | ||
| 16 | unsigned int pclkfreq_get (void); | ||
| 17 | |||
| 18 | #endif /* _ASM_ARCH_CLOCKS_H */ | ||
diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h deleted file mode 100644 index 51de96e87faf..000000000000 --- a/include/asm-arm/arch-lh7a40x/constants.h +++ /dev/null | |||
| @@ -1,91 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/constants.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
| 4 | * Copyright (C) 2004 Logic Product Development | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * version 2 as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_CONSTANTS_H | ||
| 13 | #define __ASM_ARCH_CONSTANTS_H | ||
| 14 | |||
| 15 | |||
| 16 | /* Addressing constants */ | ||
| 17 | |||
| 18 | /* SoC CPU IO addressing */ | ||
| 19 | #define IO_PHYS (0x80000000) | ||
| 20 | #define IO_VIRT (0xf8000000) | ||
| 21 | #define IO_SIZE (0x0000B000) | ||
| 22 | |||
| 23 | #ifdef CONFIG_MACH_KEV7A400 | ||
| 24 | # define CPLD_PHYS (0x20000000) | ||
| 25 | # define CPLD_VIRT (0xf2000000) | ||
| 26 | # define CPLD_SIZE PAGE_SIZE | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) | ||
| 30 | |||
| 31 | # define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */ | ||
| 32 | # define IOBARRIER_VIRT 0xf0000000 | ||
| 33 | # define IOBARRIER_SIZE PAGE_SIZE | ||
| 34 | |||
| 35 | # define CF_PHYS 0x60200000 | ||
| 36 | # define CF_VIRT 0xf6020000 | ||
| 37 | # define CF_SIZE (8*1024) | ||
| 38 | |||
| 39 | /* The IO mappings for the LPD CPLD are, unfortunately, sparse. */ | ||
| 40 | # define CPLDX_PHYS(x) (0x70000000 | ((x) << 20)) | ||
| 41 | # define CPLDX_VIRT(x) (0xf7000000 | ((x) << 16)) | ||
| 42 | # define CPLD00_PHYS CPLDX_PHYS (0x00) /* Wired LAN */ | ||
| 43 | # define CPLD00_VIRT CPLDX_VIRT (0x00) | ||
| 44 | # define CPLD00_SIZE PAGE_SIZE | ||
| 45 | # define CPLD02_PHYS CPLDX_PHYS (0x02) | ||
| 46 | # define CPLD02_VIRT CPLDX_VIRT (0x02) | ||
| 47 | # define CPLD02_SIZE PAGE_SIZE | ||
| 48 | # define CPLD06_PHYS CPLDX_PHYS (0x06) | ||
| 49 | # define CPLD06_VIRT CPLDX_VIRT (0x06) | ||
| 50 | # define CPLD06_SIZE PAGE_SIZE | ||
| 51 | # define CPLD08_PHYS CPLDX_PHYS (0x08) | ||
| 52 | # define CPLD08_VIRT CPLDX_VIRT (0x08) | ||
| 53 | # define CPLD08_SIZE PAGE_SIZE | ||
| 54 | # define CPLD0A_PHYS CPLDX_PHYS (0x0a) | ||
| 55 | # define CPLD0A_VIRT CPLDX_VIRT (0x0a) | ||
| 56 | # define CPLD0A_SIZE PAGE_SIZE | ||
| 57 | # define CPLD0C_PHYS CPLDX_PHYS (0x0c) | ||
| 58 | # define CPLD0C_VIRT CPLDX_VIRT (0x0c) | ||
| 59 | # define CPLD0C_SIZE PAGE_SIZE | ||
| 60 | # define CPLD0E_PHYS CPLDX_PHYS (0x0e) | ||
| 61 | # define CPLD0E_VIRT CPLDX_VIRT (0x0e) | ||
| 62 | # define CPLD0E_SIZE PAGE_SIZE | ||
| 63 | # define CPLD10_PHYS CPLDX_PHYS (0x10) | ||
| 64 | # define CPLD10_VIRT CPLDX_VIRT (0x10) | ||
| 65 | # define CPLD10_SIZE PAGE_SIZE | ||
| 66 | # define CPLD12_PHYS CPLDX_PHYS (0x12) | ||
| 67 | # define CPLD12_VIRT CPLDX_VIRT (0x12) | ||
| 68 | # define CPLD12_SIZE PAGE_SIZE | ||
| 69 | # define CPLD14_PHYS CPLDX_PHYS (0x14) | ||
| 70 | # define CPLD14_VIRT CPLDX_VIRT (0x14) | ||
| 71 | # define CPLD14_SIZE PAGE_SIZE | ||
| 72 | # define CPLD16_PHYS CPLDX_PHYS (0x16) | ||
| 73 | # define CPLD16_VIRT CPLDX_VIRT (0x16) | ||
| 74 | # define CPLD16_SIZE PAGE_SIZE | ||
| 75 | # define CPLD18_PHYS CPLDX_PHYS (0x18) | ||
| 76 | # define CPLD18_VIRT CPLDX_VIRT (0x18) | ||
| 77 | # define CPLD18_SIZE PAGE_SIZE | ||
| 78 | # define CPLD1A_PHYS CPLDX_PHYS (0x1a) | ||
| 79 | # define CPLD1A_VIRT CPLDX_VIRT (0x1a) | ||
| 80 | # define CPLD1A_SIZE PAGE_SIZE | ||
| 81 | #endif | ||
| 82 | |||
| 83 | /* Timing constants */ | ||
| 84 | |||
| 85 | #define XTAL_IN 14745600 /* 14.7456 MHz crystal */ | ||
| 86 | #define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ | ||
| 87 | #define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */ | ||
| 88 | #define HCLK (99993600) | ||
| 89 | //#define HCLK (119808000) | ||
| 90 | |||
| 91 | #endif /* __ASM_ARCH_CONSTANTS_H */ | ||
diff --git a/include/asm-arm/arch-lh7a40x/debug-macro.S b/include/asm-arm/arch-lh7a40x/debug-macro.S deleted file mode 100644 index 421dcd6a8506..000000000000 --- a/include/asm-arm/arch-lh7a40x/debug-macro.S +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-lh7a40x/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | @ It is not known if this will be appropriate for every 40x | ||
| 15 | @ board. | ||
| 16 | |||
| 17 | .macro addruart,rx | ||
| 18 | mrc p15, 0, \rx, c1, c0 | ||
| 19 | tst \rx, #1 @ MMU enabled? | ||
| 20 | mov \rx, #0x00000700 @ offset from base | ||
| 21 | orreq \rx, \rx, #0x80000000 @ physical base | ||
| 22 | orrne \rx, \rx, #0xf8000000 @ virtual base | ||
| 23 | .endm | ||
| 24 | |||
| 25 | .macro senduart,rd,rx | ||
| 26 | strb \rd, [\rx] @ DATA | ||
| 27 | .endm | ||
| 28 | |||
| 29 | .macro busyuart,rd,rx @ spin while busy | ||
| 30 | 1001: ldr \rd, [\rx, #0x10] @ STATUS | ||
| 31 | tst \rd, #1 << 3 @ BUSY (TX FIFO not empty) | ||
| 32 | bne 1001b @ yes, spin | ||
| 33 | .endm | ||
| 34 | |||
| 35 | .macro waituart,rd,rx @ wait for Tx FIFO room | ||
| 36 | 1001: ldrb \rd, [\rx, #0x10] @ STATUS | ||
| 37 | tst \rd, #1 << 5 @ TXFF (TX FIFO full) | ||
| 38 | bne 1001b @ yes, spin | ||
| 39 | .endm | ||
diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h deleted file mode 100644 index a8cbd14bbf9d..000000000000 --- a/include/asm-arm/arch-lh7a40x/dma.h +++ /dev/null | |||
| @@ -1,86 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/dma.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2005 Marc Singer | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * version 2 as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | typedef enum { | ||
| 12 | DMA_M2M0 = 0, | ||
| 13 | DMA_M2M1 = 1, | ||
| 14 | DMA_M2P0 = 2, /* Tx */ | ||
| 15 | DMA_M2P1 = 3, /* Rx */ | ||
| 16 | DMA_M2P2 = 4, /* Tx */ | ||
| 17 | DMA_M2P3 = 5, /* Rx */ | ||
| 18 | DMA_M2P4 = 6, /* Tx - AC97 */ | ||
| 19 | DMA_M2P5 = 7, /* Rx - AC97 */ | ||
| 20 | DMA_M2P6 = 8, /* Tx */ | ||
| 21 | DMA_M2P7 = 9, /* Rx */ | ||
| 22 | } dma_device_t; | ||
| 23 | |||
| 24 | #define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */ | ||
| 25 | |||
| 26 | #define DMAC_GCA __REG(DMAC_PHYS + 0x2b80) | ||
| 27 | #define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0) | ||
| 28 | |||
| 29 | #define DMAC_GIR_MMI1 (1<<11) | ||
| 30 | #define DMAC_GIR_MMI0 (1<<10) | ||
| 31 | #define DMAC_GIR_MPI8 (1<<9) | ||
| 32 | #define DMAC_GIR_MPI9 (1<<8) | ||
| 33 | #define DMAC_GIR_MPI6 (1<<7) | ||
| 34 | #define DMAC_GIR_MPI7 (1<<6) | ||
| 35 | #define DMAC_GIR_MPI4 (1<<5) | ||
| 36 | #define DMAC_GIR_MPI5 (1<<4) | ||
| 37 | #define DMAC_GIR_MPI2 (1<<3) | ||
| 38 | #define DMAC_GIR_MPI3 (1<<2) | ||
| 39 | #define DMAC_GIR_MPI0 (1<<1) | ||
| 40 | #define DMAC_GIR_MPI1 (1<<0) | ||
| 41 | |||
| 42 | #define DMAC_M2P0 0x0000 | ||
| 43 | #define DMAC_M2P1 0x0040 | ||
| 44 | #define DMAC_M2P2 0x0080 | ||
| 45 | #define DMAC_M2P3 0x00c0 | ||
| 46 | #define DMAC_M2P4 0x0240 | ||
| 47 | #define DMAC_M2P5 0x0200 | ||
| 48 | #define DMAC_M2P6 0x02c0 | ||
| 49 | #define DMAC_M2P7 0x0280 | ||
| 50 | #define DMAC_M2P8 0x0340 | ||
| 51 | #define DMAC_M2P9 0x0300 | ||
| 52 | #define DMAC_M2M0 0x0100 | ||
| 53 | #define DMAC_M2M1 0x0140 | ||
| 54 | |||
| 55 | #define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00) | ||
| 56 | #define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04) | ||
| 57 | #define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08) | ||
| 58 | #define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c) | ||
| 59 | #define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14) | ||
| 60 | #define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20) | ||
| 61 | #define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24) | ||
| 62 | #define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28) | ||
| 63 | #define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30) | ||
| 64 | #define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34) | ||
| 65 | #define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38) | ||
| 66 | |||
| 67 | #define DMAC_PCONTROL_ENABLE (1<<4) | ||
| 68 | |||
| 69 | #define DMAC_PORT_USB 0 | ||
| 70 | #define DMAC_PORT_SDMMC 1 | ||
| 71 | #define DMAC_PORT_AC97_1 2 | ||
| 72 | #define DMAC_PORT_AC97_2 3 | ||
| 73 | #define DMAC_PORT_AC97_3 4 | ||
| 74 | #define DMAC_PORT_UART1 6 | ||
| 75 | #define DMAC_PORT_UART2 7 | ||
| 76 | #define DMAC_PORT_UART3 8 | ||
| 77 | |||
| 78 | #define DMAC_PSTATUS_CURRSTATE_SHIFT 4 | ||
| 79 | #define DMAC_PSTATUS_CURRSTATE_MASK 0x3 | ||
| 80 | |||
| 81 | #define DMAC_PSTATUS_NEXTBUF (1<<6) | ||
| 82 | #define DMAC_PSTATUS_STALLRINT (1<<0) | ||
| 83 | |||
| 84 | #define DMAC_INT_CHE (1<<3) | ||
| 85 | #define DMAC_INT_NFB (1<<1) | ||
| 86 | #define DMAC_INT_STALL (1<<0) | ||
diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S deleted file mode 100644 index 34468e064629..000000000000 --- a/include/asm-arm/arch-lh7a40x/entry-macro.S +++ /dev/null | |||
| @@ -1,149 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-lh7a40x/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for LH7A40x platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | #include <asm/arch/irqs.h> | ||
| 12 | |||
| 13 | /* In order to allow there to be support for both of the processor | ||
| 14 | classes at the same time, we make a hack here that isn't very | ||
| 15 | pretty. At startup, the link pointed to with the | ||
| 16 | branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is | ||
| 17 | detected as a lh7a404. | ||
| 18 | |||
| 19 | *** FIXME: we should clean this up so that there is only one | ||
| 20 | implementation for each CPU's design. | ||
| 21 | |||
| 22 | */ | ||
| 23 | |||
| 24 | #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404) | ||
| 25 | |||
| 26 | .macro disable_fiq | ||
| 27 | .endm | ||
| 28 | |||
| 29 | .macro get_irqnr_preamble, base, tmp | ||
| 30 | .endm | ||
| 31 | |||
| 32 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 33 | .endm | ||
| 34 | |||
| 35 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 36 | |||
| 37 | branch_irq_lh7a400: b 1000f | ||
| 38 | |||
| 39 | @ Implementation of the LH7A404 get_irqnr_and_base. | ||
| 40 | |||
| 41 | mov \irqnr, #0 @ VIC1 irq base | ||
| 42 | mov \base, #io_p2v(0x80000000) @ APB registers | ||
| 43 | add \base, \base, #0x8000 | ||
| 44 | ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR | ||
| 45 | tst \tmp, #VA_VECTORED @ Direct vectored | ||
| 46 | bne 1002f | ||
| 47 | tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1 | ||
| 48 | ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS | ||
| 49 | bne 1001f | ||
| 50 | add \base, \base, #(0xa000 - 0x8000) | ||
| 51 | ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR | ||
| 52 | tst \tmp, #VA_VECTORED @ Direct vectored | ||
| 53 | bne 1002f | ||
| 54 | ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS | ||
| 55 | mov \irqnr, #32 @ VIC2 irq base | ||
| 56 | |||
| 57 | 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry | ||
| 58 | bcs 1008f @ Bit set; irq found | ||
| 59 | add \irqnr, \irqnr, #1 | ||
| 60 | bne 1001b @ Until no bits | ||
| 61 | b 1009f @ Nothing? Hmm. | ||
| 62 | 1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits | ||
| 63 | 1008: movs \irqstat, #1 @ Force !Z | ||
| 64 | str \tmp, [\base, #0x0030] @ Clear vector | ||
| 65 | b 1009f | ||
| 66 | |||
| 67 | @ Implementation of the LH7A400 get_irqnr_and_base. | ||
| 68 | |||
| 69 | 1000: mov \irqnr, #0 | ||
| 70 | mov \base, #io_p2v(0x80000000) @ APB registers | ||
| 71 | ldr \irqstat, [\base, #0x500] @ PIC INTSR | ||
| 72 | |||
| 73 | 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry | ||
| 74 | bcs 1008f @ Bit set; irq found | ||
| 75 | add \irqnr, \irqnr, #1 | ||
| 76 | bne 1001b @ Until no bits | ||
| 77 | b 1009f @ Nothing? Hmm. | ||
| 78 | 1008: movs \irqstat, #1 @ Force !Z | ||
| 79 | |||
| 80 | 1009: | ||
| 81 | .endm | ||
| 82 | |||
| 83 | |||
| 84 | |||
| 85 | #elif defined (CONFIG_ARCH_LH7A400) | ||
| 86 | .macro disable_fiq | ||
| 87 | .endm | ||
| 88 | |||
| 89 | .macro get_irqnr_preamble, base, tmp | ||
| 90 | .endm | ||
| 91 | |||
| 92 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 93 | .endm | ||
| 94 | |||
| 95 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 96 | mov \irqnr, #0 | ||
| 97 | mov \base, #io_p2v(0x80000000) @ APB registers | ||
| 98 | ldr \irqstat, [\base, #0x500] @ PIC INTSR | ||
| 99 | |||
| 100 | 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry | ||
| 101 | bcs 1008f @ Bit set; irq found | ||
| 102 | add \irqnr, \irqnr, #1 | ||
| 103 | bne 1001b @ Until no bits | ||
| 104 | b 1009f @ Nothing? Hmm. | ||
| 105 | 1008: movs \irqstat, #1 @ Force !Z | ||
| 106 | 1009: | ||
| 107 | .endm | ||
| 108 | |||
| 109 | #elif defined(CONFIG_ARCH_LH7A404) | ||
| 110 | |||
| 111 | .macro disable_fiq | ||
| 112 | .endm | ||
| 113 | |||
| 114 | .macro get_irqnr_preamble, base, tmp | ||
| 115 | .endm | ||
| 116 | |||
| 117 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 118 | .endm | ||
| 119 | |||
| 120 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 121 | mov \irqnr, #0 @ VIC1 irq base | ||
| 122 | mov \base, #io_p2v(0x80000000) @ APB registers | ||
| 123 | add \base, \base, #0x8000 | ||
| 124 | ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR | ||
| 125 | tst \tmp, #VA_VECTORED @ Direct vectored | ||
| 126 | bne 1002f | ||
| 127 | tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1 | ||
| 128 | ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS | ||
| 129 | bne 1001f | ||
| 130 | add \base, \base, #(0xa000 - 0x8000) | ||
| 131 | ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR | ||
| 132 | tst \tmp, #VA_VECTORED @ Direct vectored | ||
| 133 | bne 1002f | ||
| 134 | ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS | ||
| 135 | mov \irqnr, #32 @ VIC2 irq base | ||
| 136 | |||
| 137 | 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry | ||
| 138 | bcs 1008f @ Bit set; irq found | ||
| 139 | add \irqnr, \irqnr, #1 | ||
| 140 | bne 1001b @ Until no bits | ||
| 141 | b 1009f @ Nothing? Hmm. | ||
| 142 | 1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits | ||
| 143 | 1008: movs \irqstat, #1 @ Force !Z | ||
| 144 | str \tmp, [\base, #0x0030] @ Clear vector | ||
| 145 | 1009: | ||
| 146 | .endm | ||
| 147 | #endif | ||
| 148 | |||
| 149 | |||
diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h deleted file mode 100644 index e9ff74fd7939..000000000000 --- a/include/asm-arm/arch-lh7a40x/hardware.h +++ /dev/null | |||
| @@ -1,62 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/hardware.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
| 4 | * | ||
| 5 | * [ Substantially cribbed from include/asm-arm/arch-pxa/hardware.h ] | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public License | ||
| 9 | * version 2 as published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 14 | #define __ASM_ARCH_HARDWARE_H | ||
| 15 | |||
| 16 | #include <asm/sizes.h> /* Added for the sake of amba-clcd driver */ | ||
| 17 | |||
| 18 | #define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff)) | ||
| 19 | #define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff)) | ||
| 20 | |||
| 21 | #ifdef __ASSEMBLY__ | ||
| 22 | |||
| 23 | # define __REG(x) io_p2v(x) | ||
| 24 | # define __PREG(x) io_v2p(x) | ||
| 25 | |||
| 26 | #else | ||
| 27 | |||
| 28 | # if 0 | ||
| 29 | # define __REG(x) (*((volatile u32 *)io_p2v(x))) | ||
| 30 | # else | ||
| 31 | /* | ||
| 32 | * This __REG() version gives the same results as the one above, except | ||
| 33 | * that we are fooling gcc somehow so it generates far better and smaller | ||
| 34 | * assembly code for access to contigous registers. It's a shame that gcc | ||
| 35 | * doesn't guess this by itself. | ||
| 36 | */ | ||
| 37 | #include <asm/types.h> | ||
| 38 | typedef struct { volatile u32 offset[4096]; } __regbase; | ||
| 39 | # define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] | ||
| 40 | # define __REG(x) __REGP(io_p2v(x)) | ||
| 41 | typedef struct { volatile u16 offset[4096]; } __regbase16; | ||
| 42 | # define __REGP16(x) ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>1] | ||
| 43 | # define __REG16(x) __REGP16(io_p2v(x)) | ||
| 44 | typedef struct { volatile u8 offset[4096]; } __regbase8; | ||
| 45 | # define __REGP8(x) ((__regbase8 *)((x)&~4095))->offset[(x)&4095] | ||
| 46 | # define __REG8(x) __REGP8(io_p2v(x)) | ||
| 47 | #endif | ||
| 48 | |||
| 49 | /* Let's kick gcc's ass again... */ | ||
| 50 | # define __REG2(x,y) \ | ||
| 51 | ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ | ||
| 52 | : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) | ||
| 53 | |||
| 54 | # define __PREG(x) (io_v2p((u32)&(x))) | ||
| 55 | |||
| 56 | #endif | ||
| 57 | |||
| 58 | #define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s) | ||
| 59 | |||
| 60 | #include "registers.h" | ||
| 61 | |||
| 62 | #endif /* _ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-lh7a40x/io.h b/include/asm-arm/arch-lh7a40x/io.h deleted file mode 100644 index 8d591d0927c1..000000000000 --- a/include/asm-arm/arch-lh7a40x/io.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/io.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * version 2 as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_IO_H | ||
| 12 | #define __ASM_ARCH_IO_H | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 17 | |||
| 18 | /* No ISA or PCI bus on this machine. */ | ||
| 19 | #define __io(a) ((void __iomem *)(a)) | ||
| 20 | #define __mem_pci(a) (a) | ||
| 21 | |||
| 22 | #endif /* __ASM_ARCH_IO_H */ | ||
diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h deleted file mode 100644 index afe8c7cbad6a..000000000000 --- a/include/asm-arm/arch-lh7a40x/irqs.h +++ /dev/null | |||
| @@ -1,200 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/irqs.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
| 4 | * Copyright (C) 2004 Logic Product Development | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * version 2 as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* It is to be seen whether or not we can build a kernel for more than | ||
| 13 | * one board. For the time being, these macros assume that we cannot. | ||
| 14 | * Thus, it is OK to ifdef machine/board specific IRQ assignments. | ||
| 15 | */ | ||
| 16 | |||
| 17 | |||
| 18 | #ifndef __ASM_ARCH_IRQS_H | ||
| 19 | #define __ASM_ARCH_IRQS_H | ||
| 20 | |||
| 21 | |||
| 22 | #define FIQ_START 80 | ||
| 23 | |||
| 24 | #if defined (CONFIG_ARCH_LH7A400) | ||
| 25 | |||
| 26 | /* FIQs */ | ||
| 27 | |||
| 28 | # define IRQ_GPIO0FIQ 0 /* GPIO External FIQ Interrupt on F0 */ | ||
| 29 | # define IRQ_BLINT 1 /* Battery Low */ | ||
| 30 | # define IRQ_WEINT 2 /* Watchdog Timer, WDT overflow */ | ||
| 31 | # define IRQ_MCINT 3 /* Media Change, MEDCHG pin rising */ | ||
| 32 | |||
| 33 | /* IRQs */ | ||
| 34 | |||
| 35 | # define IRQ_CSINT 4 /* Audio Codec (ACI) */ | ||
| 36 | # define IRQ_GPIO1INTR 5 /* GPIO External IRQ Interrupt on F1 */ | ||
| 37 | # define IRQ_GPIO2INTR 6 /* GPIO External IRQ Interrupt on F2 */ | ||
| 38 | # define IRQ_GPIO3INTR 7 /* GPIO External IRQ Interrupt on F3 */ | ||
| 39 | # define IRQ_T1UI 8 /* Timer 1 underflow */ | ||
| 40 | # define IRQ_T2UI 9 /* Timer 2 underflow */ | ||
| 41 | # define IRQ_RTCMI 10 | ||
| 42 | # define IRQ_TINTR 11 /* Clock State Controller 64 Hz tick (CSC) */ | ||
| 43 | # define IRQ_UART1INTR 12 | ||
| 44 | # define IRQ_UART2INTR 13 | ||
| 45 | # define IRQ_LCDINTR 14 | ||
| 46 | # define IRQ_SSIEOT 15 /* Synchronous Serial Interface (SSI) */ | ||
| 47 | # define IRQ_UART3INTR 16 | ||
| 48 | # define IRQ_SCIINTR 17 /* Smart Card Interface (SCI) */ | ||
| 49 | # define IRQ_AACINTR 18 /* Advanced Audio Codec (AAC) */ | ||
| 50 | # define IRQ_MMCINTR 19 /* Multimedia Card (MMC) */ | ||
| 51 | # define IRQ_USBINTR 20 | ||
| 52 | # define IRQ_DMAINTR 21 | ||
| 53 | # define IRQ_T3UI 22 /* Timer 3 underflow */ | ||
| 54 | # define IRQ_GPIO4INTR 23 /* GPIO External IRQ Interrupt on F4 */ | ||
| 55 | # define IRQ_GPIO5INTR 24 /* GPIO External IRQ Interrupt on F5 */ | ||
| 56 | # define IRQ_GPIO6INTR 25 /* GPIO External IRQ Interrupt on F6 */ | ||
| 57 | # define IRQ_GPIO7INTR 26 /* GPIO External IRQ Interrupt on F7 */ | ||
| 58 | # define IRQ_BMIINTR 27 /* Battery Monitor Interface (BMI) */ | ||
| 59 | |||
| 60 | # define NR_IRQ_CPU 28 /* IRQs directly recognized by CPU */ | ||
| 61 | |||
| 62 | /* Given IRQ, return GPIO interrupt number 0-7 */ | ||
| 63 | # define IRQ_TO_GPIO(i) ((i) \ | ||
| 64 | - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\ | ||
| 65 | - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0)) | ||
| 66 | |||
| 67 | #endif | ||
| 68 | |||
| 69 | #if defined (CONFIG_ARCH_LH7A404) | ||
| 70 | |||
| 71 | # define IRQ_BROWN 0 /* Brownout */ | ||
| 72 | # define IRQ_WDTINTR 1 /* Watchdog Timer */ | ||
| 73 | # define IRQ_COMMRX 2 /* ARM Comm Rx for Debug */ | ||
| 74 | # define IRQ_COMMTX 3 /* ARM Comm Tx for Debug */ | ||
| 75 | # define IRQ_T1UI 4 /* Timer 1 underflow */ | ||
| 76 | # define IRQ_T2UI 5 /* Timer 2 underflow */ | ||
| 77 | # define IRQ_CSINT 6 /* Codec Interrupt (shared by AAC on 404) */ | ||
| 78 | # define IRQ_DMAM2P0 7 /* -- DMA Memory to Peripheral */ | ||
| 79 | # define IRQ_DMAM2P1 8 | ||
| 80 | # define IRQ_DMAM2P2 9 | ||
| 81 | # define IRQ_DMAM2P3 10 | ||
| 82 | # define IRQ_DMAM2P4 11 | ||
| 83 | # define IRQ_DMAM2P5 12 | ||
| 84 | # define IRQ_DMAM2P6 13 | ||
| 85 | # define IRQ_DMAM2P7 14 | ||
| 86 | # define IRQ_DMAM2P8 15 | ||
| 87 | # define IRQ_DMAM2P9 16 | ||
| 88 | # define IRQ_DMAM2M0 17 /* -- DMA Memory to Memory */ | ||
| 89 | # define IRQ_DMAM2M1 18 | ||
| 90 | # define IRQ_GPIO0INTR 19 /* -- GPIOF Interrupt */ | ||
| 91 | # define IRQ_GPIO1INTR 20 | ||
| 92 | # define IRQ_GPIO2INTR 21 | ||
| 93 | # define IRQ_GPIO3INTR 22 | ||
| 94 | # define IRQ_SOFT_V1_23 23 /* -- Unassigned */ | ||
| 95 | # define IRQ_SOFT_V1_24 24 | ||
| 96 | # define IRQ_SOFT_V1_25 25 | ||
| 97 | # define IRQ_SOFT_V1_26 26 | ||
| 98 | # define IRQ_SOFT_V1_27 27 | ||
| 99 | # define IRQ_SOFT_V1_28 28 | ||
| 100 | # define IRQ_SOFT_V1_29 29 | ||
| 101 | # define IRQ_SOFT_V1_30 30 | ||
| 102 | # define IRQ_SOFT_V1_31 31 | ||
| 103 | |||
| 104 | # define IRQ_BLINT 32 /* Battery Low */ | ||
| 105 | # define IRQ_BMIINTR 33 /* Battery Monitor */ | ||
| 106 | # define IRQ_MCINTR 34 /* Media Change */ | ||
| 107 | # define IRQ_TINTR 35 /* 64Hz Tick */ | ||
| 108 | # define IRQ_WEINT 36 /* Watchdog Expired */ | ||
| 109 | # define IRQ_RTCMI 37 /* Real-time Clock Match */ | ||
| 110 | # define IRQ_UART1INTR 38 /* UART1 Interrupt (including error) */ | ||
| 111 | # define IRQ_UART1ERR 39 /* UART1 Error */ | ||
| 112 | # define IRQ_UART2INTR 40 /* UART2 Interrupt (including error) */ | ||
| 113 | # define IRQ_UART2ERR 41 /* UART2 Error */ | ||
| 114 | # define IRQ_UART3INTR 42 /* UART3 Interrupt (including error) */ | ||
| 115 | # define IRQ_UART3ERR 43 /* UART3 Error */ | ||
| 116 | # define IRQ_SCIINTR 44 /* Smart Card */ | ||
| 117 | # define IRQ_TSCINTR 45 /* Touchscreen */ | ||
| 118 | # define IRQ_KMIINTR 46 /* Keyboard/Mouse (PS/2) */ | ||
| 119 | # define IRQ_GPIO4INTR 47 /* -- GPIOF Interrupt */ | ||
| 120 | # define IRQ_GPIO5INTR 48 | ||
| 121 | # define IRQ_GPIO6INTR 49 | ||
| 122 | # define IRQ_GPIO7INTR 50 | ||
| 123 | # define IRQ_T3UI 51 /* Timer 3 underflow */ | ||
| 124 | # define IRQ_LCDINTR 52 /* LCD Controller */ | ||
| 125 | # define IRQ_SSPINTR 53 /* Synchronous Serial Port */ | ||
| 126 | # define IRQ_SDINTR 54 /* Secure Digital Port (MMC) */ | ||
| 127 | # define IRQ_USBINTR 55 /* USB Device Port */ | ||
| 128 | # define IRQ_USHINTR 56 /* USB Host Port */ | ||
| 129 | # define IRQ_SOFT_V2_25 57 /* -- Unassigned */ | ||
| 130 | # define IRQ_SOFT_V2_26 58 | ||
| 131 | # define IRQ_SOFT_V2_27 59 | ||
| 132 | # define IRQ_SOFT_V2_28 60 | ||
| 133 | # define IRQ_SOFT_V2_29 61 | ||
| 134 | # define IRQ_SOFT_V2_30 62 | ||
| 135 | # define IRQ_SOFT_V2_31 63 | ||
| 136 | |||
| 137 | # define NR_IRQ_CPU 64 /* IRQs directly recognized by CPU */ | ||
| 138 | |||
| 139 | /* Given IRQ, return GPIO interrupt number 0-7 */ | ||
| 140 | # define IRQ_TO_GPIO(i) ((i) \ | ||
| 141 | - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\ | ||
| 142 | - IRQ_GPIO0INTR) | ||
| 143 | |||
| 144 | /* Vector Address constants */ | ||
| 145 | # define VA_VECTORED 0x100 /* Set for vectored interrupt */ | ||
| 146 | # define VA_VIC1DEFAULT 0x200 /* Set as default VECTADDR for VIC1 */ | ||
| 147 | # define VA_VIC2DEFAULT 0x400 /* Set as default VECTADDR for VIC2 */ | ||
| 148 | |||
| 149 | #endif | ||
| 150 | |||
| 151 | /* IRQ aliases */ | ||
| 152 | |||
| 153 | #if !defined (IRQ_GPIO0INTR) | ||
| 154 | # define IRQ_GPIO0INTR IRQ_GPIO0FIQ | ||
| 155 | #endif | ||
| 156 | #define IRQ_TICK IRQ_TINTR | ||
| 157 | #define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */ | ||
| 158 | #define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */ | ||
| 159 | #define IRQ_USB IRQ_USBINTR /* USB device */ | ||
| 160 | |||
| 161 | #ifdef CONFIG_MACH_KEV7A400 | ||
| 162 | # define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */ | ||
| 163 | # define IRQ_CPLD IRQ_GPIO1INTR /* CPLD cascade */ | ||
| 164 | # define IRQ_PCC1_CD IRQ_GPIO_F2 /* PCCard 1 card detect */ | ||
| 165 | # define IRQ_PCC2_CD IRQ_GPIO_F3 /* PCCard 2 card detect */ | ||
| 166 | #endif | ||
| 167 | |||
| 168 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) | ||
| 169 | # define IRQ_CPLD_V28 IRQ_GPIO7INTR /* CPLD cascade through GPIO_PF7 */ | ||
| 170 | # define IRQ_CPLD_V34 IRQ_GPIO3INTR /* CPLD cascade through GPIO_PF3 */ | ||
| 171 | #endif | ||
| 172 | |||
| 173 | /* System specific IRQs */ | ||
| 174 | |||
| 175 | #define IRQ_BOARD_START NR_IRQ_CPU | ||
| 176 | |||
| 177 | #ifdef CONFIG_MACH_KEV7A400 | ||
| 178 | # define IRQ_KEV7A400_CPLD IRQ_BOARD_START | ||
| 179 | # define NR_IRQ_BOARD 5 | ||
| 180 | # define IRQ_KEV7A400_MMC_CD IRQ_KEV7A400_CPLD + 0 /* MMC Card Detect */ | ||
| 181 | # define IRQ_KEV7A400_RI2 IRQ_KEV7A400_CPLD + 1 /* Ring Indicator 2 */ | ||
| 182 | # define IRQ_KEV7A400_IDE_CF IRQ_KEV7A400_CPLD + 2 /* Compact Flash (?) */ | ||
| 183 | # define IRQ_KEV7A400_ETH_INT IRQ_KEV7A400_CPLD + 3 /* Ethernet chip */ | ||
| 184 | # define IRQ_KEV7A400_INT IRQ_KEV7A400_CPLD + 4 | ||
| 185 | #endif | ||
| 186 | |||
| 187 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) | ||
| 188 | # define IRQ_LPD7A40X_CPLD IRQ_BOARD_START | ||
| 189 | # define NR_IRQ_BOARD 2 | ||
| 190 | # define IRQ_LPD7A40X_ETH_INT IRQ_LPD7A40X_CPLD + 0 /* Ethernet chip */ | ||
| 191 | # define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */ | ||
| 192 | #endif | ||
| 193 | |||
| 194 | #if defined (CONFIG_MACH_LPD7A400) | ||
| 195 | # define IRQ_TOUCH IRQ_LPD7A400_TS | ||
| 196 | #endif | ||
| 197 | |||
| 198 | #define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD) | ||
| 199 | |||
| 200 | #endif | ||
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h deleted file mode 100644 index 9b0c8012e713..000000000000 --- a/include/asm-arm/arch-lh7a40x/memory.h +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/memory.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * version 2 as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * | ||
| 10 | * Refer to <file:Documentation/arm/Sharp-LH/SDRAM> for more information. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 15 | #define __ASM_ARCH_MEMORY_H | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Physical DRAM offset. | ||
| 19 | */ | ||
| 20 | #define PHYS_OFFSET UL(0xc0000000) | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Virtual view <-> DMA view memory address translations | ||
| 24 | * virt_to_bus: Used to translate the virtual address to an | ||
| 25 | * address suitable to be passed to set_dma_addr | ||
| 26 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 27 | * to an address that the kernel can use. | ||
| 28 | */ | ||
| 29 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 30 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 31 | |||
| 32 | #ifdef CONFIG_DISCONTIGMEM | ||
| 33 | |||
| 34 | /* | ||
| 35 | * Given a kernel address, find the home node of the underlying memory. | ||
| 36 | */ | ||
| 37 | |||
| 38 | # ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE | ||
| 39 | # define KVADDR_TO_NID(addr) \ | ||
| 40 | ( ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) & 1)\ | ||
| 41 | | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1)) | ||
| 42 | # else /* 2 banks per node */ | ||
| 43 | # define KVADDR_TO_NID(addr) \ | ||
| 44 | (((unsigned long) (addr) - PAGE_OFFSET) >> 26) | ||
| 45 | # endif | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Given a page frame number, convert it to a node id. | ||
| 49 | */ | ||
| 50 | |||
| 51 | # ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE | ||
| 52 | # define PFN_TO_NID(pfn) \ | ||
| 53 | (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) & 1)\ | ||
| 54 | | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1)) | ||
| 55 | # else /* 2 banks per node */ | ||
| 56 | # define PFN_TO_NID(pfn) \ | ||
| 57 | (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT)) | ||
| 58 | #endif | ||
| 59 | |||
| 60 | /* | ||
| 61 | * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory | ||
| 62 | * and returns the index corresponding to the appropriate page in the | ||
| 63 | * node's mem_map. | ||
| 64 | */ | ||
| 65 | |||
| 66 | # ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE | ||
| 67 | # define LOCAL_MAP_NR(addr) \ | ||
| 68 | (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT) | ||
| 69 | # else /* 2 banks per node */ | ||
| 70 | # define LOCAL_MAP_NR(addr) \ | ||
| 71 | (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT) | ||
| 72 | # endif | ||
| 73 | |||
| 74 | #endif | ||
| 75 | |||
| 76 | #endif | ||
diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h deleted file mode 100644 index b4f09b3e2d03..000000000000 --- a/include/asm-arm/arch-lh7a40x/registers.h +++ /dev/null | |||
| @@ -1,224 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/registers.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
| 4 | * Copyright (C) 2004 Logic Product Development | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * version 2 as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <asm/arch/constants.h> | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_REGISTERS_H | ||
| 15 | #define __ASM_ARCH_REGISTERS_H | ||
| 16 | |||
| 17 | |||
| 18 | /* Physical register base addresses */ | ||
| 19 | |||
| 20 | #define AC97C_PHYS (0x80000000) /* AC97 Controller */ | ||
| 21 | #define MMC_PHYS (0x80000100) /* Multimedia Card Controller */ | ||
| 22 | #define USB_PHYS (0x80000200) /* USB Client */ | ||
| 23 | #define SCI_PHYS (0x80000300) /* Secure Card Interface */ | ||
| 24 | #define CSC_PHYS (0x80000400) /* Clock/State Controller */ | ||
| 25 | #define INTC_PHYS (0x80000500) /* Interrupt Controller */ | ||
| 26 | #define UART1_PHYS (0x80000600) /* UART1 Controller */ | ||
| 27 | #define SIR_PHYS (0x80000600) /* IR Controller, same are UART1 */ | ||
| 28 | #define UART2_PHYS (0x80000700) /* UART2 Controller */ | ||
| 29 | #define UART3_PHYS (0x80000800) /* UART3 Controller */ | ||
| 30 | #define DCDC_PHYS (0x80000900) /* DC to DC Controller */ | ||
| 31 | #define ACI_PHYS (0x80000a00) /* Audio Codec Interface */ | ||
| 32 | #define SSP_PHYS (0x80000b00) /* Synchronous ... */ | ||
| 33 | #define TIMER_PHYS (0x80000c00) /* Timer Controller */ | ||
| 34 | #define RTC_PHYS (0x80000d00) /* Real-time Clock */ | ||
| 35 | #define GPIO_PHYS (0x80000e00) /* General Purpose IO */ | ||
| 36 | #define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */ | ||
| 37 | #define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */ | ||
| 38 | #define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */ | ||
| 39 | #define WDT_PHYS (0x80001400) /* Watchdog Timer */ | ||
| 40 | #define SMC_PHYS (0x80002000) /* Static Memory Controller */ | ||
| 41 | #define SDRC_PHYS (0x80002400) /* SDRAM Controller */ | ||
| 42 | #define DMAC_PHYS (0x80002800) /* DMA Controller */ | ||
| 43 | #define CLCDC_PHYS (0x80003000) /* Color LCD Controller */ | ||
| 44 | |||
| 45 | /* Physical registers of the LH7A404 */ | ||
| 46 | |||
| 47 | #define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */ | ||
| 48 | #define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */ | ||
| 49 | #define USBH_PHYS (0x80009000) /* USB OHCI host controller */ | ||
| 50 | #define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */ | ||
| 51 | |||
| 52 | /*#define KBD_PHYS (0x80000e00) */ | ||
| 53 | /*#define LCDICP_PHYS (0x80001000) */ | ||
| 54 | |||
| 55 | |||
| 56 | /* Clock/State Controller register */ | ||
| 57 | |||
| 58 | #define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */ | ||
| 59 | #define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */ | ||
| 60 | #define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */ | ||
| 61 | #define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */ | ||
| 62 | |||
| 63 | #define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */ | ||
| 64 | #define CSC_PWRCNT_DMAC_M2M1_EN (1<<27) | ||
| 65 | #define CSC_PWRCNT_DMAC_M2M0_EN (1<<26) | ||
| 66 | #define CSC_PWRCNT_DMAC_M2P8_EN (1<<25) | ||
| 67 | #define CSC_PWRCNT_DMAC_M2P9_EN (1<<24) | ||
| 68 | #define CSC_PWRCNT_DMAC_M2P6_EN (1<<23) | ||
| 69 | #define CSC_PWRCNT_DMAC_M2P7_EN (1<<22) | ||
| 70 | #define CSC_PWRCNT_DMAC_M2P4_EN (1<<21) | ||
| 71 | #define CSC_PWRCNT_DMAC_M2P5_EN (1<<20) | ||
| 72 | #define CSC_PWRCNT_DMAC_M2P2_EN (1<<19) | ||
| 73 | #define CSC_PWRCNT_DMAC_M2P3_EN (1<<18) | ||
| 74 | #define CSC_PWRCNT_DMAC_M2P0_EN (1<<17) | ||
| 75 | #define CSC_PWRCNT_DMAC_M2P1_EN (1<<16) | ||
| 76 | |||
| 77 | #define CSC_PWRSR_CHIPMAN_SHIFT (24) | ||
| 78 | #define CSC_PWRSR_CHIPMAN_MASK (0xff) | ||
| 79 | #define CSC_PWRSR_CHIPID_SHIFT (16) | ||
| 80 | #define CSC_PWRSR_CHIPID_MASK (0xff) | ||
| 81 | |||
| 82 | #define CSC_USBDRESET_APBRESETREG (1<<1) | ||
| 83 | #define CSC_USBDRESET_IORESETREG (1<<0) | ||
| 84 | |||
| 85 | /* Interrupt Controller registers */ | ||
| 86 | |||
| 87 | #define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */ | ||
| 88 | #define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */ | ||
| 89 | #define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */ | ||
| 90 | #define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */ | ||
| 91 | |||
| 92 | |||
| 93 | /* Vectored Interrupted Controller registers */ | ||
| 94 | |||
| 95 | #define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00) | ||
| 96 | #define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04) | ||
| 97 | #define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08) | ||
| 98 | #define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c) | ||
| 99 | #define VIC1_INTEN __REG(VIC1_PHYS + 0x10) | ||
| 100 | #define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14) | ||
| 101 | #define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18) | ||
| 102 | #define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c) | ||
| 103 | #define VIC1_PROTECT __REG(VIC1_PHYS + 0x20) | ||
| 104 | #define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30) | ||
| 105 | #define VIC1_NVADDR __REG(VIC1_PHYS + 0x34) | ||
| 106 | #define VIC1_VAD0 __REG(VIC1_PHYS + 0x100) | ||
| 107 | #define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200) | ||
| 108 | #define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00) | ||
| 109 | #define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04) | ||
| 110 | #define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08) | ||
| 111 | #define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c) | ||
| 112 | #define VIC2_INTEN __REG(VIC2_PHYS + 0x10) | ||
| 113 | #define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14) | ||
| 114 | #define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18) | ||
| 115 | #define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c) | ||
| 116 | #define VIC2_PROTECT __REG(VIC2_PHYS + 0x20) | ||
| 117 | #define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30) | ||
| 118 | #define VIC2_NVADDR __REG(VIC2_PHYS + 0x34) | ||
| 119 | #define VIC2_VAD0 __REG(VIC2_PHYS + 0x100) | ||
| 120 | #define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200) | ||
| 121 | |||
| 122 | #define VIC_CNTL_ENABLE (0x20) | ||
| 123 | |||
| 124 | /* USB Host registers (Open HCI compatible) */ | ||
| 125 | |||
| 126 | #define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08) | ||
| 127 | |||
| 128 | |||
| 129 | /* GPIO registers */ | ||
| 130 | |||
| 131 | #define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */ | ||
| 132 | #define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */ | ||
| 133 | #define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */ | ||
| 134 | #define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */ | ||
| 135 | #define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */ | ||
| 136 | #define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c) | ||
| 137 | #define GPIO_PADD __REG(GPIO_PHYS + 0x10) | ||
| 138 | #define GPIO_PAD __REG(GPIO_PHYS + 0x00) | ||
| 139 | #define GPIO_PCD __REG(GPIO_PHYS + 0x08) | ||
| 140 | #define GPIO_PCDD __REG(GPIO_PHYS + 0x18) | ||
| 141 | #define GPIO_PEDD __REG(GPIO_PHYS + 0x24) | ||
| 142 | #define GPIO_PED __REG(GPIO_PHYS + 0x20) | ||
| 143 | |||
| 144 | |||
| 145 | /* Static Memory Controller registers */ | ||
| 146 | |||
| 147 | #define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */ | ||
| 148 | #define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */ | ||
| 149 | #define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */ | ||
| 150 | #define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */ | ||
| 151 | #define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */ | ||
| 152 | #define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */ | ||
| 153 | |||
| 154 | |||
| 155 | #ifdef CONFIG_MACH_KEV7A400 | ||
| 156 | # define CPLD_RD_OPT_DIP_SW __REG16(CPLD_PHYS + 0x00) /* Read Option SW */ | ||
| 157 | # define CPLD_WR_IO_BRD_CTL __REG16(CPLD_PHYS + 0x00) /* Write Control */ | ||
| 158 | # define CPLD_RD_PB_KEYS __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */ | ||
| 159 | # define CPLD_LATCHED_INTS __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */ | ||
| 160 | # define CPLD_CL_INT __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */ | ||
| 161 | # define CPLD_BOOT_MMC_STATUS __REG16(CPLD_PHYS + 0x06) /* R/O */ | ||
| 162 | # define CPLD_RD_KPD_ROW_SENSE __REG16(CPLD_PHYS + 0x08) | ||
| 163 | # define CPLD_WR_PB_INT_MASK __REG16(CPLD_PHYS + 0x08) | ||
| 164 | # define CPLD_RD_BRD_DISP_SW __REG16(CPLD_PHYS + 0x0a) | ||
| 165 | # define CPLD_WR_EXT_INT_MASK __REG16(CPLD_PHYS + 0x0a) | ||
| 166 | # define CPLD_LCD_PWR_CNTL __REG16(CPLD_PHYS + 0x0c) | ||
| 167 | # define CPLD_SEVEN_SEG __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */ | ||
| 168 | |||
| 169 | #endif | ||
| 170 | |||
| 171 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) | ||
| 172 | |||
| 173 | # define CPLD_CONTROL __REG16(CPLD02_PHYS) | ||
| 174 | # define CPLD_SPI_DATA __REG16(CPLD06_PHYS) | ||
| 175 | # define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS) | ||
| 176 | # define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS) | ||
| 177 | # define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */ | ||
| 178 | # define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS) | ||
| 179 | # define CPLD_FLASH __REG16(CPLD10_PHYS) | ||
| 180 | # define CPLD_POWER_MGMT __REG16(CPLD12_PHYS) | ||
| 181 | # define CPLD_REVISION __REG16(CPLD14_PHYS) | ||
| 182 | # define CPLD_GPIO_EXT __REG16(CPLD16_PHYS) | ||
| 183 | # define CPLD_GPIO_DATA __REG16(CPLD18_PHYS) | ||
| 184 | # define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS) | ||
| 185 | |||
| 186 | #endif | ||
| 187 | |||
| 188 | /* Timer registers */ | ||
| 189 | |||
| 190 | #define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */ | ||
| 191 | #define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */ | ||
| 192 | #define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */ | ||
| 193 | #define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */ | ||
| 194 | |||
| 195 | #define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */ | ||
| 196 | #define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */ | ||
| 197 | #define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */ | ||
| 198 | #define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */ | ||
| 199 | |||
| 200 | #define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */ | ||
| 201 | |||
| 202 | #define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */ | ||
| 203 | #define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */ | ||
| 204 | #define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */ | ||
| 205 | #define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */ | ||
| 206 | |||
| 207 | #define TIMER_C_ENABLE (1<<7) | ||
| 208 | #define TIMER_C_PERIODIC (1<<6) | ||
| 209 | #define TIMER_C_FREERUNNING (0) | ||
| 210 | #define TIMER_C_2KHZ (0x00) /* 1.986 kHz */ | ||
| 211 | #define TIMER_C_508KHZ (0x08) | ||
| 212 | |||
| 213 | /* GPIO registers */ | ||
| 214 | |||
| 215 | #define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */ | ||
| 216 | #define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */ | ||
| 217 | #define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */ | ||
| 218 | #define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */ | ||
| 219 | #define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */ | ||
| 220 | #define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */ | ||
| 221 | #define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */ | ||
| 222 | |||
| 223 | |||
| 224 | #endif /* _ASM_ARCH_REGISTERS_H */ | ||
diff --git a/include/asm-arm/arch-lh7a40x/ssp.h b/include/asm-arm/arch-lh7a40x/ssp.h deleted file mode 100644 index 132b1c4d5ce6..000000000000 --- a/include/asm-arm/arch-lh7a40x/ssp.h +++ /dev/null | |||
| @@ -1,71 +0,0 @@ | |||
| 1 | /* ssp.h | ||
| 2 | $Id$ | ||
| 3 | |||
| 4 | written by Marc Singer | ||
| 5 | 6 Dec 2004 | ||
| 6 | |||
| 7 | Copyright (C) 2004 Marc Singer | ||
| 8 | |||
| 9 | ----------- | ||
| 10 | DESCRIPTION | ||
| 11 | ----------- | ||
| 12 | |||
| 13 | This SSP header is available throughout the kernel, for this | ||
| 14 | machine/architecture, because drivers that use it may be dispersed. | ||
| 15 | |||
| 16 | This file was cloned from the 7952x implementation. It would be | ||
| 17 | better to share them, but we're taking an easier approach for the | ||
| 18 | time being. | ||
| 19 | |||
| 20 | */ | ||
| 21 | |||
| 22 | #if !defined (__SSP_H__) | ||
| 23 | # define __SSP_H__ | ||
| 24 | |||
| 25 | /* ----- Includes */ | ||
| 26 | |||
| 27 | /* ----- Types */ | ||
| 28 | |||
| 29 | struct ssp_driver { | ||
| 30 | int (*init) (void); | ||
| 31 | void (*exit) (void); | ||
| 32 | void (*acquire) (void); | ||
| 33 | void (*release) (void); | ||
| 34 | int (*configure) (int device, int mode, int speed, | ||
| 35 | int frame_size_write, int frame_size_read); | ||
| 36 | void (*chip_select) (int enable); | ||
| 37 | void (*set_callbacks) (void* handle, | ||
| 38 | irqreturn_t (*callback_tx)(void*), | ||
| 39 | irqreturn_t (*callback_rx)(void*)); | ||
| 40 | void (*enable) (void); | ||
| 41 | void (*disable) (void); | ||
| 42 | // int (*save_state) (void*); | ||
| 43 | // void (*restore_state) (void*); | ||
| 44 | int (*read) (void); | ||
| 45 | int (*write) (u16 data); | ||
| 46 | int (*write_read) (u16 data); | ||
| 47 | void (*flush) (void); | ||
| 48 | void (*write_async) (void* pv, size_t cb); | ||
| 49 | size_t (*write_pos) (void); | ||
| 50 | }; | ||
| 51 | |||
| 52 | /* These modes are only available on the LH79524 */ | ||
| 53 | #define SSP_MODE_SPI (1) | ||
| 54 | #define SSP_MODE_SSI (2) | ||
| 55 | #define SSP_MODE_MICROWIRE (3) | ||
| 56 | #define SSP_MODE_I2S (4) | ||
| 57 | |||
| 58 | /* CPLD SPI devices */ | ||
| 59 | #define DEVICE_EEPROM 0 /* Configuration eeprom */ | ||
| 60 | #define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */ | ||
| 61 | #define DEVICE_CODEC 2 /* Audio codec */ | ||
| 62 | #define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */ | ||
| 63 | |||
| 64 | /* ----- Globals */ | ||
| 65 | |||
| 66 | /* ----- Prototypes */ | ||
| 67 | |||
| 68 | //extern struct ssp_driver lh79520_i2s_driver; | ||
| 69 | extern struct ssp_driver lh7a400_cpld_ssp_driver; | ||
| 70 | |||
| 71 | #endif /* __SSP_H__ */ | ||
diff --git a/include/asm-arm/arch-lh7a40x/system.h b/include/asm-arm/arch-lh7a40x/system.h deleted file mode 100644 index e1df8aa460f2..000000000000 --- a/include/asm-arm/arch-lh7a40x/system.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/system.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * version 2 as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | static inline void arch_idle(void) | ||
| 12 | { | ||
| 13 | cpu_do_idle (); | ||
| 14 | } | ||
| 15 | |||
| 16 | static inline void arch_reset(char mode) | ||
| 17 | { | ||
| 18 | cpu_reset (0); | ||
| 19 | } | ||
diff --git a/include/asm-arm/arch-lh7a40x/timex.h b/include/asm-arm/arch-lh7a40x/timex.h deleted file mode 100644 index fa726b670829..000000000000 --- a/include/asm-arm/arch-lh7a40x/timex.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/timex.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * version 2 as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/arch/constants.h> | ||
| 12 | |||
| 13 | #define CLOCK_TICK_RATE (PLL_CLOCK/6/16) | ||
| 14 | |||
| 15 | /* | ||
| 16 | #define CLOCK_TICK_RATE 3686400 | ||
| 17 | */ | ||
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h deleted file mode 100644 index 3d1ce0426a33..000000000000 --- a/include/asm-arm/arch-lh7a40x/uncompress.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/uncompress.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * version 2 as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/arch/registers.h> | ||
| 12 | |||
| 13 | #ifndef UART_R_DATA | ||
| 14 | # define UART_R_DATA (0x00) | ||
| 15 | #endif | ||
| 16 | #ifndef UART_R_STATUS | ||
| 17 | # define UART_R_STATUS (0x10) | ||
| 18 | #endif | ||
| 19 | #define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ | ||
| 20 | |||
| 21 | /* Access UART with physical addresses before MMU is setup */ | ||
| 22 | #define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) | ||
| 23 | #define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA)) | ||
| 24 | |||
| 25 | static inline void putc(int ch) | ||
| 26 | { | ||
| 27 | while (UART_STATUS & nTxRdy) | ||
| 28 | barrier(); | ||
| 29 | UART_DATA = ch; | ||
| 30 | } | ||
| 31 | |||
| 32 | static inline void flush(void) | ||
| 33 | { | ||
| 34 | } | ||
| 35 | |||
| 36 | /* NULL functions; we don't presently need them */ | ||
| 37 | #define arch_decomp_setup() | ||
| 38 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-lh7a40x/vmalloc.h b/include/asm-arm/arch-lh7a40x/vmalloc.h deleted file mode 100644 index 8163e45109b9..000000000000 --- a/include/asm-arm/arch-lh7a40x/vmalloc.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-lh7a40x/vmalloc.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * version 2 as published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | #define VMALLOC_END (0xe8000000) | ||
diff --git a/include/asm-arm/arch-loki/debug-macro.S b/include/asm-arm/arch-loki/debug-macro.S deleted file mode 100644 index 585502e96513..000000000000 --- a/include/asm-arm/arch-loki/debug-macro.S +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/debug-macro.S | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <asm/arch/loki.h> | ||
| 10 | |||
| 11 | .macro addruart,rx | ||
| 12 | mrc p15, 0, \rx, c1, c0 | ||
| 13 | tst \rx, #1 @ MMU enabled? | ||
| 14 | ldreq \rx, =LOKI_REGS_PHYS_BASE | ||
| 15 | ldrne \rx, =LOKI_REGS_VIRT_BASE | ||
| 16 | orr \rx, \rx, #0x00012000 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | #define UART_SHIFT 2 | ||
| 20 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-loki/dma.h b/include/asm-arm/arch-loki/dma.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/include/asm-arm/arch-loki/dma.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | /* empty */ | ||
diff --git a/include/asm-arm/arch-loki/entry-macro.S b/include/asm-arm/arch-loki/entry-macro.S deleted file mode 100644 index 693257cdbeb8..000000000000 --- a/include/asm-arm/arch-loki/entry-macro.S +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/arch/loki.h> | ||
| 12 | |||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro get_irqnr_preamble, base, tmp | ||
| 20 | ldr \base, =IRQ_VIRT_BASE | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 24 | ldr \irqstat, [\base, #IRQ_CAUSE_OFF] | ||
| 25 | ldr \tmp, [\base, #IRQ_MASK_OFF] | ||
| 26 | mov \irqnr, #0 | ||
| 27 | ands \irqstat, \irqstat, \tmp | ||
| 28 | clzne \irqnr, \irqstat | ||
| 29 | rsbne \irqnr, \irqnr, #31 | ||
| 30 | .endm | ||
diff --git a/include/asm-arm/arch-loki/hardware.h b/include/asm-arm/arch-loki/hardware.h deleted file mode 100644 index f65b01c733b6..000000000000 --- a/include/asm-arm/arch-loki/hardware.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/hardware.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 10 | #define __ASM_ARCH_HARDWARE_H | ||
| 11 | |||
| 12 | #include "loki.h" | ||
| 13 | |||
| 14 | |||
| 15 | #endif | ||
diff --git a/include/asm-arm/arch-loki/io.h b/include/asm-arm/arch-loki/io.h deleted file mode 100644 index e7418a915e75..000000000000 --- a/include/asm-arm/arch-loki/io.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/io.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_IO_H | ||
| 10 | #define __ASM_ARCH_IO_H | ||
| 11 | |||
| 12 | #include "loki.h" | ||
| 13 | |||
| 14 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 15 | |||
| 16 | static inline void __iomem *__io(unsigned long addr) | ||
| 17 | { | ||
| 18 | return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE) | ||
| 19 | + LOKI_PCIE0_IO_VIRT_BASE); | ||
| 20 | } | ||
| 21 | |||
| 22 | #define __io(a) __io(a) | ||
| 23 | #define __mem_pci(a) (a) | ||
| 24 | |||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-arm/arch-loki/irqs.h b/include/asm-arm/arch-loki/irqs.h deleted file mode 100644 index 7e4971438072..000000000000 --- a/include/asm-arm/arch-loki/irqs.h +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ definitions for Marvell Loki (88RC8480) SoCs | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_IRQS_H | ||
| 12 | #define __ASM_ARCH_IRQS_H | ||
| 13 | |||
| 14 | #include "loki.h" /* need GPIO_MAX */ | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Interrupt Controller | ||
| 18 | */ | ||
| 19 | #define IRQ_LOKI_PCIE_A_CPU_DRBL 0 | ||
| 20 | #define IRQ_LOKI_CPU_PCIE_A_DRBL 1 | ||
| 21 | #define IRQ_LOKI_PCIE_B_CPU_DRBL 2 | ||
| 22 | #define IRQ_LOKI_CPU_PCIE_B_DRBL 3 | ||
| 23 | #define IRQ_LOKI_COM_A_ERR 6 | ||
| 24 | #define IRQ_LOKI_COM_A_IN 7 | ||
| 25 | #define IRQ_LOKI_COM_A_OUT 8 | ||
| 26 | #define IRQ_LOKI_COM_B_ERR 9 | ||
| 27 | #define IRQ_LOKI_COM_B_IN 10 | ||
| 28 | #define IRQ_LOKI_COM_B_OUT 11 | ||
| 29 | #define IRQ_LOKI_DMA_A 12 | ||
| 30 | #define IRQ_LOKI_DMA_B 13 | ||
| 31 | #define IRQ_LOKI_SAS_A 14 | ||
| 32 | #define IRQ_LOKI_SAS_B 15 | ||
| 33 | #define IRQ_LOKI_DDR 16 | ||
| 34 | #define IRQ_LOKI_XOR 17 | ||
| 35 | #define IRQ_LOKI_BRIDGE 18 | ||
| 36 | #define IRQ_LOKI_PCIE_A_ERR 20 | ||
| 37 | #define IRQ_LOKI_PCIE_A_INT 21 | ||
| 38 | #define IRQ_LOKI_PCIE_B_ERR 22 | ||
| 39 | #define IRQ_LOKI_PCIE_B_INT 23 | ||
| 40 | #define IRQ_LOKI_GBE_A_INT 24 | ||
| 41 | #define IRQ_LOKI_GBE_B_INT 25 | ||
| 42 | #define IRQ_LOKI_DEV_ERR 26 | ||
| 43 | #define IRQ_LOKI_UART0 27 | ||
| 44 | #define IRQ_LOKI_UART1 28 | ||
| 45 | #define IRQ_LOKI_TWSI 29 | ||
| 46 | #define IRQ_LOKI_GPIO_23_0 30 | ||
| 47 | #define IRQ_LOKI_GPIO_25_24 31 | ||
| 48 | |||
| 49 | /* | ||
| 50 | * Loki General Purpose Pins | ||
| 51 | */ | ||
| 52 | #define IRQ_LOKI_GPIO_START 32 | ||
| 53 | #define NR_GPIO_IRQS GPIO_MAX | ||
| 54 | |||
| 55 | #define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS) | ||
| 56 | |||
| 57 | |||
| 58 | #endif | ||
diff --git a/include/asm-arm/arch-loki/loki.h b/include/asm-arm/arch-loki/loki.h deleted file mode 100644 index 5dd05ee0a4e6..000000000000 --- a/include/asm-arm/arch-loki/loki.h +++ /dev/null | |||
| @@ -1,97 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/loki.h | ||
| 3 | * | ||
| 4 | * Generic definitions for Marvell Loki (88RC8480) SoC flavors | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_LOKI_H | ||
| 12 | #define __ASM_ARCH_LOKI_H | ||
| 13 | |||
| 14 | /* | ||
| 15 | * Marvell Loki (88RC8480) address maps. | ||
| 16 | * | ||
| 17 | * phys | ||
| 18 | * d0000000 on-chip peripheral registers | ||
| 19 | * e0000000 PCIe 0 Memory space | ||
| 20 | * e8000000 PCIe 1 Memory space | ||
| 21 | * f0000000 PCIe 0 I/O space | ||
| 22 | * f0100000 PCIe 1 I/O space | ||
| 23 | * | ||
| 24 | * virt phys size | ||
| 25 | * fed00000 d0000000 1M on-chip peripheral registers | ||
| 26 | * fee00000 f0000000 64K PCIe 0 I/O space | ||
| 27 | * fef00000 f0100000 64K PCIe 1 I/O space | ||
| 28 | */ | ||
| 29 | |||
| 30 | #define LOKI_REGS_PHYS_BASE 0xd0000000 | ||
| 31 | #define LOKI_REGS_VIRT_BASE 0xfed00000 | ||
| 32 | #define LOKI_REGS_SIZE SZ_1M | ||
| 33 | |||
| 34 | #define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000 | ||
| 35 | #define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000 | ||
| 36 | #define LOKI_PCIE0_IO_BUS_BASE 0x00000000 | ||
| 37 | #define LOKI_PCIE0_IO_SIZE SZ_64K | ||
| 38 | |||
| 39 | #define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000 | ||
| 40 | #define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000 | ||
| 41 | #define LOKI_PCIE1_IO_BUS_BASE 0x00000000 | ||
| 42 | #define LOKI_PCIE1_IO_SIZE SZ_64K | ||
| 43 | |||
| 44 | #define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000 | ||
| 45 | #define LOKI_PCIE0_MEM_SIZE SZ_128M | ||
| 46 | |||
| 47 | #define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000 | ||
| 48 | #define LOKI_PCIE1_MEM_SIZE SZ_128M | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Register Map | ||
| 52 | */ | ||
| 53 | #define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000) | ||
| 54 | #define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000) | ||
| 55 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) | ||
| 56 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | ||
| 57 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | ||
| 58 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) | ||
| 59 | |||
| 60 | #define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000) | ||
| 61 | #define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x)) | ||
| 62 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
| 63 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
| 64 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
| 65 | #define SOFT_RESET 0x00000001 | ||
| 66 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
| 67 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
| 68 | #define BRIDGE_INT_TIMER0 0x0002 | ||
| 69 | #define BRIDGE_INT_TIMER1 0x0004 | ||
| 70 | #define BRIDGE_INT_TIMER1_CLR 0x0004 | ||
| 71 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
| 72 | #define IRQ_CAUSE_OFF 0x0000 | ||
| 73 | #define IRQ_MASK_OFF 0x0004 | ||
| 74 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
| 75 | |||
| 76 | #define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000) | ||
| 77 | |||
| 78 | #define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000) | ||
| 79 | |||
| 80 | #define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000) | ||
| 81 | |||
| 82 | #define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000) | ||
| 83 | |||
| 84 | #define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000) | ||
| 85 | #define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000) | ||
| 86 | |||
| 87 | #define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000) | ||
| 88 | #define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000) | ||
| 89 | |||
| 90 | #define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000) | ||
| 91 | #define DDR_REG(x) (DDR_VIRT_BASE | (x)) | ||
| 92 | |||
| 93 | |||
| 94 | #define GPIO_MAX 8 | ||
| 95 | |||
| 96 | |||
| 97 | #endif | ||
diff --git a/include/asm-arm/arch-loki/memory.h b/include/asm-arm/arch-loki/memory.h deleted file mode 100644 index 835101e49875..000000000000 --- a/include/asm-arm/arch-loki/memory.h +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/memory.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 6 | #define __ASM_ARCH_MEMORY_H | ||
| 7 | |||
| 8 | #define PHYS_OFFSET UL(0x00000000) | ||
| 9 | |||
| 10 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 11 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 12 | |||
| 13 | |||
| 14 | #endif | ||
diff --git a/include/asm-arm/arch-loki/system.h b/include/asm-arm/arch-loki/system.h deleted file mode 100644 index a3568ac8ec35..000000000000 --- a/include/asm-arm/arch-loki/system.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/system.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 10 | #define __ASM_ARCH_SYSTEM_H | ||
| 11 | |||
| 12 | #include <asm/arch/hardware.h> | ||
| 13 | #include <asm/arch/loki.h> | ||
| 14 | |||
| 15 | static inline void arch_idle(void) | ||
| 16 | { | ||
| 17 | cpu_do_idle(); | ||
| 18 | } | ||
| 19 | |||
| 20 | static inline void arch_reset(char mode) | ||
| 21 | { | ||
| 22 | /* | ||
| 23 | * Enable soft reset to assert RSTOUTn. | ||
| 24 | */ | ||
| 25 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Assert soft reset. | ||
| 29 | */ | ||
| 30 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | ||
| 31 | |||
| 32 | while (1) | ||
| 33 | ; | ||
| 34 | } | ||
| 35 | |||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-loki/timex.h b/include/asm-arm/arch-loki/timex.h deleted file mode 100644 index 940014f97cae..000000000000 --- a/include/asm-arm/arch-loki/timex.h +++ /dev/null | |||
| @@ -1,11 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/timex.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE (100 * HZ) | ||
| 10 | |||
| 11 | #define LOKI_TCLK 180000000 | ||
diff --git a/include/asm-arm/arch-loki/uncompress.h b/include/asm-arm/arch-loki/uncompress.h deleted file mode 100644 index 89a0cf88d3a5..000000000000 --- a/include/asm-arm/arch-loki/uncompress.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/uncompress.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/serial_reg.h> | ||
| 10 | #include <asm/arch/loki.h> | ||
| 11 | |||
| 12 | #define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) | ||
| 13 | |||
| 14 | static void putc(const char c) | ||
| 15 | { | ||
| 16 | unsigned char *base = SERIAL_BASE; | ||
| 17 | int i; | ||
| 18 | |||
| 19 | for (i = 0; i < 0x1000; i++) { | ||
| 20 | if (base[UART_LSR << 2] & UART_LSR_THRE) | ||
| 21 | break; | ||
| 22 | barrier(); | ||
| 23 | } | ||
| 24 | |||
| 25 | base[UART_TX << 2] = c; | ||
| 26 | } | ||
| 27 | |||
| 28 | static void flush(void) | ||
| 29 | { | ||
| 30 | unsigned char *base = SERIAL_BASE; | ||
| 31 | unsigned char mask; | ||
| 32 | int i; | ||
| 33 | |||
| 34 | mask = UART_LSR_TEMT | UART_LSR_THRE; | ||
| 35 | |||
| 36 | for (i = 0; i < 0x1000; i++) { | ||
| 37 | if ((base[UART_LSR << 2] & mask) == mask) | ||
| 38 | break; | ||
| 39 | barrier(); | ||
| 40 | } | ||
| 41 | } | ||
| 42 | |||
| 43 | /* | ||
| 44 | * nothing to do | ||
| 45 | */ | ||
| 46 | #define arch_decomp_setup() | ||
| 47 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-loki/vmalloc.h b/include/asm-arm/arch-loki/vmalloc.h deleted file mode 100644 index f5be06220491..000000000000 --- a/include/asm-arm/arch-loki/vmalloc.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-loki/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define VMALLOC_END 0xfe800000 | ||
diff --git a/include/asm-arm/arch-msm/board.h b/include/asm-arm/arch-msm/board.h deleted file mode 100644 index 763051f8ba14..000000000000 --- a/include/asm-arm/arch-msm/board.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-msm/board.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * Author: Brian Swetland <swetland@google.com> | ||
| 5 | * | ||
| 6 | * This software is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2, as published by the Free Software Foundation, and | ||
| 8 | * may be copied, distributed, and modified under those terms. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ASM_ARCH_MSM_BOARD_H | ||
| 18 | #define __ASM_ARCH_MSM_BOARD_H | ||
| 19 | |||
| 20 | #include <linux/types.h> | ||
| 21 | |||
| 22 | /* platform device data structures */ | ||
| 23 | |||
| 24 | struct msm_mddi_platform_data | ||
| 25 | { | ||
| 26 | void (*panel_power)(int on); | ||
| 27 | unsigned has_vsync_irq:1; | ||
| 28 | }; | ||
| 29 | |||
| 30 | /* common init routines for use by arch/arm/mach-msm/board-*.c */ | ||
| 31 | |||
| 32 | void __init msm_add_devices(void); | ||
| 33 | void __init msm_map_common_io(void); | ||
| 34 | void __init msm_init_irq(void); | ||
| 35 | void __init msm_init_gpio(void); | ||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-msm/debug-macro.S b/include/asm-arm/arch-msm/debug-macro.S deleted file mode 100644 index e131b44b2107..000000000000 --- a/include/asm-arm/arch-msm/debug-macro.S +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-msm7200/debug-macro.S | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * Author: Brian Swetland <swetland@google.com> | ||
| 5 | * | ||
| 6 | * This software is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2, as published by the Free Software Foundation, and | ||
| 8 | * may be copied, distributed, and modified under those terms. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <asm/arch/hardware.h> | ||
| 18 | #include <asm/arch/msm_iomap.h> | ||
| 19 | |||
| 20 | .macro addruart,rx | ||
| 21 | @ see if the MMU is enabled and select appropriate base address | ||
| 22 | mrc p15, 0, \rx, c1, c0 | ||
| 23 | tst \rx, #1 | ||
| 24 | ldreq \rx, =MSM_UART1_PHYS | ||
| 25 | ldrne \rx, =MSM_UART1_BASE | ||
| 26 | .endm | ||
| 27 | |||
| 28 | .macro senduart,rd,rx | ||
| 29 | str \rd, [\rx, #0x0C] | ||
| 30 | .endm | ||
| 31 | |||
| 32 | .macro waituart,rd,rx | ||
| 33 | @ wait for TX_READY | ||
| 34 | 1: ldr \rd, [\rx, #0x08] | ||
| 35 | tst \rd, #0x04 | ||
| 36 | beq 1b | ||
| 37 | .endm | ||
| 38 | |||
| 39 | .macro busyuart,rd,rx | ||
| 40 | .endm | ||
diff --git a/include/asm-arm/arch-msm/dma.h b/include/asm-arm/arch-msm/dma.h deleted file mode 100644 index e4b565b27b35..000000000000 --- a/include/asm-arm/arch-msm/dma.h +++ /dev/null | |||
| @@ -1,151 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-msm/dma.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_MSM_DMA_H | ||
| 17 | |||
| 18 | #include <linux/list.h> | ||
| 19 | #include <asm/arch/msm_iomap.h> | ||
| 20 | |||
| 21 | struct msm_dmov_cmd { | ||
| 22 | struct list_head list; | ||
| 23 | unsigned int cmdptr; | ||
| 24 | void (*complete_func)(struct msm_dmov_cmd *cmd, unsigned int result); | ||
| 25 | /* void (*user_result_func)(struct msm_dmov_cmd *cmd); */ | ||
| 26 | }; | ||
| 27 | |||
| 28 | void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd); | ||
| 29 | void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd); | ||
| 30 | int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr); | ||
| 31 | /* int msm_dmov_exec_cmd_etc(unsigned id, unsigned int cmdptr, int timeout, int interruptible); */ | ||
| 32 | |||
| 33 | |||
| 34 | |||
| 35 | #define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2)) | ||
| 36 | #define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2)) | ||
| 37 | #define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) | ||
| 38 | #define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) | ||
| 39 | |||
| 40 | /* only security domain 3 is available to the ARM11 | ||
| 41 | * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM | ||
| 42 | */ | ||
| 43 | |||
| 44 | #define DMOV_CMD_PTR(ch) DMOV_SD3(0x000, ch) | ||
| 45 | #define DMOV_CMD_LIST (0 << 29) /* does not work */ | ||
| 46 | #define DMOV_CMD_PTR_LIST (1 << 29) /* works */ | ||
| 47 | #define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */ | ||
| 48 | #define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */ | ||
| 49 | #define DMOV_CMD_ADDR(addr) ((addr) >> 3) | ||
| 50 | |||
| 51 | #define DMOV_RSLT(ch) DMOV_SD3(0x040, ch) | ||
| 52 | #define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */ | ||
| 53 | #define DMOV_RSLT_ERROR (1 << 3) | ||
| 54 | #define DMOV_RSLT_FLUSH (1 << 2) | ||
| 55 | #define DMOV_RSLT_DONE (1 << 1) /* top pointer done */ | ||
| 56 | #define DMOV_RSLT_USER (1 << 0) /* command with FR force result */ | ||
| 57 | |||
| 58 | #define DMOV_FLUSH0(ch) DMOV_SD3(0x080, ch) | ||
| 59 | #define DMOV_FLUSH1(ch) DMOV_SD3(0x0C0, ch) | ||
| 60 | #define DMOV_FLUSH2(ch) DMOV_SD3(0x100, ch) | ||
| 61 | #define DMOV_FLUSH3(ch) DMOV_SD3(0x140, ch) | ||
| 62 | #define DMOV_FLUSH4(ch) DMOV_SD3(0x180, ch) | ||
| 63 | #define DMOV_FLUSH5(ch) DMOV_SD3(0x1C0, ch) | ||
| 64 | |||
| 65 | #define DMOV_STATUS(ch) DMOV_SD3(0x200, ch) | ||
| 66 | #define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29)) | ||
| 67 | #define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3) | ||
| 68 | #define DMOV_STATUS_RSLT_VALID (1 << 1) | ||
| 69 | #define DMOV_STATUS_CMD_PTR_RDY (1 << 0) | ||
| 70 | |||
| 71 | #define DMOV_ISR DMOV_SD3(0x380, 0) | ||
| 72 | |||
| 73 | #define DMOV_CONFIG(ch) DMOV_SD3(0x300, ch) | ||
| 74 | #define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2) | ||
| 75 | #define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1) | ||
| 76 | #define DMOV_CONFIG_IRQ_EN (1 << 0) | ||
| 77 | |||
| 78 | /* channel assignments */ | ||
| 79 | |||
| 80 | #define DMOV_NAND_CHAN 7 | ||
| 81 | #define DMOV_NAND_CRCI_CMD 5 | ||
| 82 | #define DMOV_NAND_CRCI_DATA 4 | ||
| 83 | |||
| 84 | #define DMOV_SDC1_CHAN 8 | ||
| 85 | #define DMOV_SDC1_CRCI 6 | ||
| 86 | |||
| 87 | #define DMOV_SDC2_CHAN 8 | ||
| 88 | #define DMOV_SDC2_CRCI 7 | ||
| 89 | |||
| 90 | #define DMOV_TSIF_CHAN 10 | ||
| 91 | #define DMOV_TSIF_CRCI 10 | ||
| 92 | |||
| 93 | #define DMOV_USB_CHAN 11 | ||
| 94 | |||
| 95 | /* no client rate control ifc (eg, ram) */ | ||
| 96 | #define DMOV_NONE_CRCI 0 | ||
| 97 | |||
| 98 | |||
| 99 | /* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover | ||
| 100 | * is going to walk a list of 32bit pointers as described below. Each | ||
| 101 | * pointer points to a *array* of dmov_s, etc structs. The last pointer | ||
| 102 | * in the list is marked with CMD_PTR_LP. The last struct in each array | ||
| 103 | * is marked with CMD_LC (see below). | ||
| 104 | */ | ||
| 105 | #define CMD_PTR_ADDR(addr) ((addr) >> 3) | ||
| 106 | #define CMD_PTR_LP (1 << 31) /* last pointer */ | ||
| 107 | #define CMD_PTR_PT (3 << 29) /* ? */ | ||
| 108 | |||
| 109 | /* Single Item Mode */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned cmd; | ||
| 112 | unsigned src; | ||
| 113 | unsigned dst; | ||
| 114 | unsigned len; | ||
| 115 | } dmov_s; | ||
| 116 | |||
| 117 | /* Scatter/Gather Mode */ | ||
| 118 | typedef struct { | ||
| 119 | unsigned cmd; | ||
| 120 | unsigned src_dscr; | ||
| 121 | unsigned dst_dscr; | ||
| 122 | unsigned _reserved; | ||
| 123 | } dmov_sg; | ||
| 124 | |||
| 125 | /* bits for the cmd field of the above structures */ | ||
| 126 | |||
| 127 | #define CMD_LC (1 << 31) /* last command */ | ||
| 128 | #define CMD_FR (1 << 22) /* force result -- does not work? */ | ||
| 129 | #define CMD_OCU (1 << 21) /* other channel unblock */ | ||
| 130 | #define CMD_OCB (1 << 20) /* other channel block */ | ||
| 131 | #define CMD_TCB (1 << 19) /* ? */ | ||
| 132 | #define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/ | ||
| 133 | #define CMD_SAH (1 << 17) /* source address hold -- does not work? */ | ||
| 134 | |||
| 135 | #define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */ | ||
| 136 | #define CMD_MODE_SG (1 << 0) /* untested */ | ||
| 137 | #define CMD_MODE_IND_SG (2 << 0) /* untested */ | ||
| 138 | #define CMD_MODE_BOX (3 << 0) /* untested */ | ||
| 139 | |||
| 140 | #define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */ | ||
| 141 | #define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */ | ||
| 142 | #define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */ | ||
| 143 | |||
| 144 | #define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */ | ||
| 145 | #define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */ | ||
| 146 | #define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */ | ||
| 147 | |||
| 148 | #define CMD_DST_CRCI(n) (((n) & 15) << 7) | ||
| 149 | #define CMD_SRC_CRCI(n) (((n) & 15) << 3) | ||
| 150 | |||
| 151 | #endif | ||
diff --git a/include/asm-arm/arch-msm/entry-macro.S b/include/asm-arm/arch-msm/entry-macro.S deleted file mode 100644 index ee24aece4cb0..000000000000 --- a/include/asm-arm/arch-msm/entry-macro.S +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-msm7200/entry-macro.S | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * Author: Brian Swetland <swetland@google.com> | ||
| 5 | * | ||
| 6 | * This software is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2, as published by the Free Software Foundation, and | ||
| 8 | * may be copied, distributed, and modified under those terms. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <asm/arch/msm_iomap.h> | ||
| 18 | |||
| 19 | .macro disable_fiq | ||
| 20 | .endm | ||
| 21 | |||
| 22 | .macro get_irqnr_preamble, base, tmp | ||
| 23 | @ enable imprecise aborts | ||
| 24 | cpsie a | ||
| 25 | mov \base, #MSM_VIC_BASE | ||
| 26 | .endm | ||
| 27 | |||
| 28 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 29 | .endm | ||
| 30 | |||
| 31 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 32 | @ 0xD0 has irq# or old irq# if the irq has been handled | ||
| 33 | @ 0xD4 has irq# or -1 if none pending *but* if you just | ||
| 34 | @ read 0xD4 you never get the first irq for some reason | ||
| 35 | ldr \irqnr, [\base, #0xD0] | ||
| 36 | ldr \irqnr, [\base, #0xD4] | ||
| 37 | cmp \irqnr, #0xffffffff | ||
| 38 | .endm | ||
diff --git a/include/asm-arm/arch-msm/hardware.h b/include/asm-arm/arch-msm/hardware.h deleted file mode 100644 index 89af2b70182f..000000000000 --- a/include/asm-arm/arch-msm/hardware.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-msm/hardware.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_MSM_HARDWARE_H | ||
| 17 | |||
| 18 | #endif | ||
diff --git a/include/asm-arm/arch-msm/io.h b/include/asm-arm/arch-msm/io.h deleted file mode 100644 index 4645ae26b62a..000000000000 --- a/include/asm-arm/arch-msm/io.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* include/asm-arm/arch-msm/io.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 17 | #define __ASM_ARM_ARCH_IO_H | ||
| 18 | |||
| 19 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 20 | |||
| 21 | #define __arch_ioremap __msm_ioremap | ||
| 22 | #define __arch_iounmap __iounmap | ||
| 23 | |||
| 24 | void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype); | ||
| 25 | |||
| 26 | static inline void __iomem *__io(unsigned long addr) | ||
| 27 | { | ||
| 28 | return (void __iomem *)addr; | ||
| 29 | } | ||
| 30 | #define __io(a) __io(a) | ||
| 31 | #define __mem_pci(a) (a) | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h deleted file mode 100644 index e62a108b1857..000000000000 --- a/include/asm-arm/arch-msm/irqs.h +++ /dev/null | |||
| @@ -1,90 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-msm/irqs.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * Author: Brian Swetland <swetland@google.com> | ||
| 5 | * | ||
| 6 | * This software is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2, as published by the Free Software Foundation, and | ||
| 8 | * may be copied, distributed, and modified under those terms. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ASM_ARCH_MSM_IRQS_H | ||
| 18 | #define __ASM_ARCH_MSM_IRQS_H | ||
| 19 | |||
| 20 | /* MSM ARM11 Interrupt Numbers */ | ||
| 21 | /* See 80-VE113-1 A, pp219-221 */ | ||
| 22 | |||
| 23 | #define INT_A9_M2A_0 0 | ||
| 24 | #define INT_A9_M2A_1 1 | ||
| 25 | #define INT_A9_M2A_2 2 | ||
| 26 | #define INT_A9_M2A_3 3 | ||
| 27 | #define INT_A9_M2A_4 4 | ||
| 28 | #define INT_A9_M2A_5 5 | ||
| 29 | #define INT_A9_M2A_6 6 | ||
| 30 | #define INT_GP_TIMER_EXP 7 | ||
| 31 | #define INT_DEBUG_TIMER_EXP 8 | ||
| 32 | #define INT_UART1 9 | ||
| 33 | #define INT_UART2 10 | ||
| 34 | #define INT_UART3 11 | ||
| 35 | #define INT_UART1_RX 12 | ||
| 36 | #define INT_UART2_RX 13 | ||
| 37 | #define INT_UART3_RX 14 | ||
| 38 | #define INT_USB_OTG 15 | ||
| 39 | #define INT_MDDI_PRI 16 | ||
| 40 | #define INT_MDDI_EXT 17 | ||
| 41 | #define INT_MDDI_CLIENT 18 | ||
| 42 | #define INT_MDP 19 | ||
| 43 | #define INT_GRAPHICS 20 | ||
| 44 | #define INT_ADM_AARM 21 | ||
| 45 | #define INT_ADSP_A11 22 | ||
| 46 | #define INT_ADSP_A9_A11 23 | ||
| 47 | #define INT_SDC1_0 24 | ||
| 48 | #define INT_SDC1_1 25 | ||
| 49 | #define INT_SDC2_0 26 | ||
| 50 | #define INT_SDC2_1 27 | ||
| 51 | #define INT_KEYSENSE 28 | ||
| 52 | #define INT_TCHSCRN_SSBI 29 | ||
| 53 | #define INT_TCHSCRN1 30 | ||
| 54 | #define INT_TCHSCRN2 31 | ||
| 55 | |||
| 56 | #define INT_GPIO_GROUP1 (32 + 0) | ||
| 57 | #define INT_GPIO_GROUP2 (32 + 1) | ||
| 58 | #define INT_PWB_I2C (32 + 2) | ||
| 59 | #define INT_SOFTRESET (32 + 3) | ||
| 60 | #define INT_NAND_WR_ER_DONE (32 + 4) | ||
| 61 | #define INT_NAND_OP_DONE (32 + 5) | ||
| 62 | #define INT_PBUS_ARM11 (32 + 6) | ||
| 63 | #define INT_AXI_MPU_SMI (32 + 7) | ||
| 64 | #define INT_AXI_MPU_EBI1 (32 + 8) | ||
| 65 | #define INT_AD_HSSD (32 + 9) | ||
| 66 | #define INT_ARM11_PMU (32 + 10) | ||
| 67 | #define INT_ARM11_DMA (32 + 11) | ||
| 68 | #define INT_TSIF_IRQ (32 + 12) | ||
| 69 | #define INT_UART1DM_IRQ (32 + 13) | ||
| 70 | #define INT_UART1DM_RX (32 + 14) | ||
| 71 | #define INT_USB_HS (32 + 15) | ||
| 72 | #define INT_SDC3_0 (32 + 16) | ||
| 73 | #define INT_SDC3_1 (32 + 17) | ||
| 74 | #define INT_SDC4_0 (32 + 18) | ||
| 75 | #define INT_SDC4_1 (32 + 19) | ||
| 76 | #define INT_UART2DM_RX (32 + 20) | ||
| 77 | #define INT_UART2DM_IRQ (32 + 21) | ||
| 78 | |||
| 79 | /* 22-31 are reserved */ | ||
| 80 | |||
| 81 | #define MSM_IRQ_BIT(irq) (1 << ((irq) & 31)) | ||
| 82 | |||
| 83 | #define NR_MSM_IRQS 64 | ||
| 84 | #define NR_GPIO_IRQS 122 | ||
| 85 | #define NR_BOARD_IRQS 64 | ||
| 86 | #define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS) | ||
| 87 | |||
| 88 | #define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n)) | ||
| 89 | |||
| 90 | #endif | ||
diff --git a/include/asm-arm/arch-msm/memory.h b/include/asm-arm/arch-msm/memory.h deleted file mode 100644 index b5ce0e9ac86d..000000000000 --- a/include/asm-arm/arch-msm/memory.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-msm/memory.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 17 | #define __ASM_ARCH_MEMORY_H | ||
| 18 | |||
| 19 | /* physical offset of RAM */ | ||
| 20 | #define PHYS_OFFSET UL(0x10000000) | ||
| 21 | |||
| 22 | /* bus address and physical addresses are identical */ | ||
| 23 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 24 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 25 | |||
| 26 | #endif | ||
| 27 | |||
diff --git a/include/asm-arm/arch-msm/msm_iomap.h b/include/asm-arm/arch-msm/msm_iomap.h deleted file mode 100644 index b8955cc26fec..000000000000 --- a/include/asm-arm/arch-msm/msm_iomap.h +++ /dev/null | |||
| @@ -1,104 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-msm/msm_iomap.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * Author: Brian Swetland <swetland@google.com> | ||
| 5 | * | ||
| 6 | * This software is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2, as published by the Free Software Foundation, and | ||
| 8 | * may be copied, distributed, and modified under those terms. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * | ||
| 16 | * The MSM peripherals are spread all over across 768MB of physical | ||
| 17 | * space, which makes just having a simple IO_ADDRESS macro to slide | ||
| 18 | * them into the right virtual location rough. Instead, we will | ||
| 19 | * provide a master phys->virt mapping for peripherals here. | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __ASM_ARCH_MSM_IOMAP_H | ||
| 24 | #define __ASM_ARCH_MSM_IOMAP_H | ||
| 25 | |||
| 26 | #include <asm/sizes.h> | ||
| 27 | |||
| 28 | /* Physical base address and size of peripherals. | ||
| 29 | * Ordered by the virtual base addresses they will be mapped at. | ||
| 30 | * | ||
| 31 | * MSM_VIC_BASE must be an value that can be loaded via a "mov" | ||
| 32 | * instruction, otherwise entry-macro.S will not compile. | ||
| 33 | * | ||
| 34 | * If you add or remove entries here, you'll want to edit the | ||
| 35 | * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your | ||
| 36 | * changes. | ||
| 37 | * | ||
| 38 | */ | ||
| 39 | |||
| 40 | #define MSM_VIC_BASE 0xE0000000 | ||
| 41 | #define MSM_VIC_PHYS 0xC0000000 | ||
| 42 | #define MSM_VIC_SIZE SZ_4K | ||
| 43 | |||
| 44 | #define MSM_CSR_BASE 0xE0001000 | ||
| 45 | #define MSM_CSR_PHYS 0xC0100000 | ||
| 46 | #define MSM_CSR_SIZE SZ_4K | ||
| 47 | |||
| 48 | #define MSM_GPT_PHYS MSM_CSR_PHYS | ||
| 49 | #define MSM_GPT_BASE MSM_CSR_BASE | ||
| 50 | #define MSM_GPT_SIZE SZ_4K | ||
| 51 | |||
| 52 | #define MSM_DMOV_BASE 0xE0002000 | ||
| 53 | #define MSM_DMOV_PHYS 0xA9700000 | ||
| 54 | #define MSM_DMOV_SIZE SZ_4K | ||
| 55 | |||
| 56 | #define MSM_UART1_BASE 0xE0003000 | ||
| 57 | #define MSM_UART1_PHYS 0xA9A00000 | ||
| 58 | #define MSM_UART1_SIZE SZ_4K | ||
| 59 | |||
| 60 | #define MSM_UART2_BASE 0xE0004000 | ||
| 61 | #define MSM_UART2_PHYS 0xA9B00000 | ||
| 62 | #define MSM_UART2_SIZE SZ_4K | ||
| 63 | |||
| 64 | #define MSM_UART3_BASE 0xE0005000 | ||
| 65 | #define MSM_UART3_PHYS 0xA9C00000 | ||
| 66 | #define MSM_UART3_SIZE SZ_4K | ||
| 67 | |||
| 68 | #define MSM_I2C_BASE 0xE0006000 | ||
| 69 | #define MSM_I2C_PHYS 0xA9900000 | ||
| 70 | #define MSM_I2C_SIZE SZ_4K | ||
| 71 | |||
| 72 | #define MSM_GPIO1_BASE 0xE0007000 | ||
| 73 | #define MSM_GPIO1_PHYS 0xA9200000 | ||
| 74 | #define MSM_GPIO1_SIZE SZ_4K | ||
| 75 | |||
| 76 | #define MSM_GPIO2_BASE 0xE0008000 | ||
| 77 | #define MSM_GPIO2_PHYS 0xA9300000 | ||
| 78 | #define MSM_GPIO2_SIZE SZ_4K | ||
| 79 | |||
| 80 | #define MSM_HSUSB_BASE 0xE0009000 | ||
| 81 | #define MSM_HSUSB_PHYS 0xA0800000 | ||
| 82 | #define MSM_HSUSB_SIZE SZ_4K | ||
| 83 | |||
| 84 | #define MSM_CLK_CTL_BASE 0xE000A000 | ||
| 85 | #define MSM_CLK_CTL_PHYS 0xA8600000 | ||
| 86 | #define MSM_CLK_CTL_SIZE SZ_4K | ||
| 87 | |||
| 88 | #define MSM_PMDH_BASE 0xE000B000 | ||
| 89 | #define MSM_PMDH_PHYS 0xAA600000 | ||
| 90 | #define MSM_PMDH_SIZE SZ_4K | ||
| 91 | |||
| 92 | #define MSM_EMDH_BASE 0xE000C000 | ||
| 93 | #define MSM_EMDH_PHYS 0xAA700000 | ||
| 94 | #define MSM_EMDH_SIZE SZ_4K | ||
| 95 | |||
| 96 | #define MSM_MDP_BASE 0xE0010000 | ||
| 97 | #define MSM_MDP_PHYS 0xAA200000 | ||
| 98 | #define MSM_MDP_SIZE 0x000F0000 | ||
| 99 | |||
| 100 | #define MSM_SHARED_RAM_BASE 0xE0100000 | ||
| 101 | #define MSM_SHARED_RAM_PHYS 0x01F00000 | ||
| 102 | #define MSM_SHARED_RAM_SIZE SZ_1M | ||
| 103 | |||
| 104 | #endif | ||
diff --git a/include/asm-arm/arch-msm/system.h b/include/asm-arm/arch-msm/system.h deleted file mode 100644 index fb31b3aa6750..000000000000 --- a/include/asm-arm/arch-msm/system.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-msm/system.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <asm/arch/hardware.h> | ||
| 17 | |||
| 18 | void arch_idle(void); | ||
| 19 | |||
| 20 | static inline void arch_reset(char mode) | ||
| 21 | { | ||
| 22 | for (;;) ; /* depends on IPC w/ other core */ | ||
| 23 | } | ||
diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h deleted file mode 100644 index 8724487ab4c9..000000000000 --- a/include/asm-arm/arch-msm/timex.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-msm/timex.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_MSM_TIMEX_H | ||
| 17 | #define __ASM_ARCH_MSM_TIMEX_H | ||
| 18 | |||
| 19 | #define CLOCK_TICK_RATE 1000000 | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/include/asm-arm/arch-msm/uncompress.h b/include/asm-arm/arch-msm/uncompress.h deleted file mode 100644 index e91ed786ffec..000000000000 --- a/include/asm-arm/arch-msm/uncompress.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-msm/uncompress.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_MSM_UNCOMPRESS_H | ||
| 17 | |||
| 18 | #include "hardware.h" | ||
| 19 | |||
| 20 | static void putc(int c) | ||
| 21 | { | ||
| 22 | } | ||
| 23 | |||
| 24 | static inline void flush(void) | ||
| 25 | { | ||
| 26 | } | ||
| 27 | |||
| 28 | static inline void arch_decomp_setup(void) | ||
| 29 | { | ||
| 30 | } | ||
| 31 | |||
| 32 | static inline void arch_decomp_wdog(void) | ||
| 33 | { | ||
| 34 | } | ||
| 35 | |||
| 36 | #endif | ||
diff --git a/include/asm-arm/arch-msm/vmalloc.h b/include/asm-arm/arch-msm/vmalloc.h deleted file mode 100644 index 60f8d910e825..000000000000 --- a/include/asm-arm/arch-msm/vmalloc.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-msm/vmalloc.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Google, Inc. | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_MSM_VMALLOC_H | ||
| 17 | #define __ASM_ARCH_MSM_VMALLOC_H | ||
| 18 | |||
| 19 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
| 20 | |||
| 21 | #endif | ||
| 22 | |||
diff --git a/include/asm-arm/arch-mv78xx0/debug-macro.S b/include/asm-arm/arch-mv78xx0/debug-macro.S deleted file mode 100644 index d0595bd645e5..000000000000 --- a/include/asm-arm/arch-mv78xx0/debug-macro.S +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/debug-macro.S | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <asm/arch/mv78xx0.h> | ||
| 10 | |||
| 11 | .macro addruart,rx | ||
| 12 | mrc p15, 0, \rx, c1, c0 | ||
| 13 | tst \rx, #1 @ MMU enabled? | ||
| 14 | ldreq \rx, =MV78XX0_REGS_PHYS_BASE | ||
| 15 | ldrne \rx, =MV78XX0_REGS_VIRT_BASE | ||
| 16 | orr \rx, \rx, #0x00012000 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | #define UART_SHIFT 2 | ||
| 20 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-mv78xx0/dma.h b/include/asm-arm/arch-mv78xx0/dma.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/include/asm-arm/arch-mv78xx0/dma.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | /* empty */ | ||
diff --git a/include/asm-arm/arch-mv78xx0/entry-macro.S b/include/asm-arm/arch-mv78xx0/entry-macro.S deleted file mode 100644 index e9a606b12669..000000000000 --- a/include/asm-arm/arch-mv78xx0/entry-macro.S +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for Marvell MV78xx0 platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/arch/mv78xx0.h> | ||
| 12 | |||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro get_irqnr_preamble, base, tmp | ||
| 20 | ldr \base, =IRQ_VIRT_BASE | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 24 | @ check low interrupts | ||
| 25 | ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] | ||
| 26 | ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] | ||
| 27 | mov \irqnr, #31 | ||
| 28 | ands \irqstat, \irqstat, \tmp | ||
| 29 | |||
| 30 | @ if no low interrupts set, check high interrupts | ||
| 31 | ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] | ||
| 32 | ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF] | ||
| 33 | moveq \irqnr, #63 | ||
| 34 | andeqs \irqstat, \irqstat, \tmp | ||
| 35 | |||
| 36 | @ find first active interrupt source | ||
| 37 | clzne \irqstat, \irqstat | ||
| 38 | subne \irqnr, \irqnr, \irqstat | ||
| 39 | .endm | ||
diff --git a/include/asm-arm/arch-mv78xx0/hardware.h b/include/asm-arm/arch-mv78xx0/hardware.h deleted file mode 100644 index 8e17926086c6..000000000000 --- a/include/asm-arm/arch-mv78xx0/hardware.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/hardware.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 10 | #define __ASM_ARCH_HARDWARE_H | ||
| 11 | |||
| 12 | #include "mv78xx0.h" | ||
| 13 | |||
| 14 | #define pcibios_assign_all_busses() 1 | ||
| 15 | |||
| 16 | #define PCIBIOS_MIN_IO 0x00001000 | ||
| 17 | #define PCIBIOS_MIN_MEM 0x01000000 | ||
| 18 | #define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */ | ||
| 19 | |||
| 20 | |||
| 21 | #endif | ||
diff --git a/include/asm-arm/arch-mv78xx0/io.h b/include/asm-arm/arch-mv78xx0/io.h deleted file mode 100644 index 415d4c98e3d1..000000000000 --- a/include/asm-arm/arch-mv78xx0/io.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/io.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_IO_H | ||
| 10 | #define __ASM_ARCH_IO_H | ||
| 11 | |||
| 12 | #include "mv78xx0.h" | ||
| 13 | |||
| 14 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 15 | |||
| 16 | static inline void __iomem *__io(unsigned long addr) | ||
| 17 | { | ||
| 18 | return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) | ||
| 19 | + MV78XX0_PCIE_IO_VIRT_BASE(0)); | ||
| 20 | } | ||
| 21 | |||
| 22 | #define __io(a) __io(a) | ||
| 23 | #define __mem_pci(a) (a) | ||
| 24 | |||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-arm/arch-mv78xx0/irqs.h b/include/asm-arm/arch-mv78xx0/irqs.h deleted file mode 100644 index 75930450cd65..000000000000 --- a/include/asm-arm/arch-mv78xx0/irqs.h +++ /dev/null | |||
| @@ -1,91 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ definitions for Marvell MV78xx0 SoCs | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_IRQS_H | ||
| 12 | #define __ASM_ARCH_IRQS_H | ||
| 13 | |||
| 14 | #include "mv78xx0.h" /* need GPIO_MAX */ | ||
| 15 | |||
| 16 | /* | ||
| 17 | * MV78xx0 Low Interrupt Controller | ||
| 18 | */ | ||
| 19 | #define IRQ_MV78XX0_ERR 0 | ||
| 20 | #define IRQ_MV78XX0_SPI 1 | ||
| 21 | #define IRQ_MV78XX0_I2C_0 2 | ||
| 22 | #define IRQ_MV78XX0_I2C_1 3 | ||
| 23 | #define IRQ_MV78XX0_IDMA_0 4 | ||
| 24 | #define IRQ_MV78XX0_IDMA_1 5 | ||
| 25 | #define IRQ_MV78XX0_IDMA_2 6 | ||
| 26 | #define IRQ_MV78XX0_IDMA_3 7 | ||
| 27 | #define IRQ_MV78XX0_TIMER_0 8 | ||
| 28 | #define IRQ_MV78XX0_TIMER_1 9 | ||
| 29 | #define IRQ_MV78XX0_TIMER_2 10 | ||
| 30 | #define IRQ_MV78XX0_TIMER_3 11 | ||
| 31 | #define IRQ_MV78XX0_UART_0 12 | ||
| 32 | #define IRQ_MV78XX0_UART_1 13 | ||
| 33 | #define IRQ_MV78XX0_UART_2 14 | ||
| 34 | #define IRQ_MV78XX0_UART_3 15 | ||
| 35 | #define IRQ_MV78XX0_USB_0 16 | ||
| 36 | #define IRQ_MV78XX0_USB_1 17 | ||
| 37 | #define IRQ_MV78XX0_USB_2 18 | ||
| 38 | #define IRQ_MV78XX0_CRYPTO 19 | ||
| 39 | #define IRQ_MV78XX0_SDIO_0 20 | ||
| 40 | #define IRQ_MV78XX0_SDIO_1 21 | ||
| 41 | #define IRQ_MV78XX0_XOR_0 22 | ||
| 42 | #define IRQ_MV78XX0_XOR_1 23 | ||
| 43 | #define IRQ_MV78XX0_I2S_0 24 | ||
| 44 | #define IRQ_MV78XX0_I2S_1 25 | ||
| 45 | #define IRQ_MV78XX0_SATA 26 | ||
| 46 | #define IRQ_MV78XX0_TDMI 27 | ||
| 47 | |||
| 48 | /* | ||
| 49 | * MV78xx0 High Interrupt Controller | ||
| 50 | */ | ||
| 51 | #define IRQ_MV78XX0_PCIE_00 32 | ||
| 52 | #define IRQ_MV78XX0_PCIE_01 33 | ||
| 53 | #define IRQ_MV78XX0_PCIE_02 34 | ||
| 54 | #define IRQ_MV78XX0_PCIE_03 35 | ||
| 55 | #define IRQ_MV78XX0_PCIE_10 36 | ||
| 56 | #define IRQ_MV78XX0_PCIE_11 37 | ||
| 57 | #define IRQ_MV78XX0_PCIE_12 38 | ||
| 58 | #define IRQ_MV78XX0_PCIE_13 39 | ||
| 59 | #define IRQ_MV78XX0_GE00_SUM 40 | ||
| 60 | #define IRQ_MV78XX0_GE00_RX 41 | ||
| 61 | #define IRQ_MV78XX0_GE00_TX 42 | ||
| 62 | #define IRQ_MV78XX0_GE00_MISC 43 | ||
| 63 | #define IRQ_MV78XX0_GE01_SUM 44 | ||
| 64 | #define IRQ_MV78XX0_GE01_RX 45 | ||
| 65 | #define IRQ_MV78XX0_GE01_TX 46 | ||
| 66 | #define IRQ_MV78XX0_GE01_MISC 47 | ||
| 67 | #define IRQ_MV78XX0_GE10_SUM 48 | ||
| 68 | #define IRQ_MV78XX0_GE10_RX 49 | ||
| 69 | #define IRQ_MV78XX0_GE10_TX 50 | ||
| 70 | #define IRQ_MV78XX0_GE10_MISC 51 | ||
| 71 | #define IRQ_MV78XX0_GE11_SUM 52 | ||
| 72 | #define IRQ_MV78XX0_GE11_RX 53 | ||
| 73 | #define IRQ_MV78XX0_GE11_TX 54 | ||
| 74 | #define IRQ_MV78XX0_GE11_MISC 55 | ||
| 75 | #define IRQ_MV78XX0_GPIO_0_7 56 | ||
| 76 | #define IRQ_MV78XX0_GPIO_8_15 57 | ||
| 77 | #define IRQ_MV78XX0_GPIO_16_23 58 | ||
| 78 | #define IRQ_MV78XX0_GPIO_24_31 59 | ||
| 79 | #define IRQ_MV78XX0_DB_IN 60 | ||
| 80 | #define IRQ_MV78XX0_DB_OUT 61 | ||
| 81 | |||
| 82 | /* | ||
| 83 | * MV78XX0 General Purpose Pins | ||
| 84 | */ | ||
| 85 | #define IRQ_MV78XX0_GPIO_START 64 | ||
| 86 | #define NR_GPIO_IRQS GPIO_MAX | ||
| 87 | |||
| 88 | #define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) | ||
| 89 | |||
| 90 | |||
| 91 | #endif | ||
diff --git a/include/asm-arm/arch-mv78xx0/memory.h b/include/asm-arm/arch-mv78xx0/memory.h deleted file mode 100644 index 721a6b185b91..000000000000 --- a/include/asm-arm/arch-mv78xx0/memory.h +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/memory.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 6 | #define __ASM_ARCH_MEMORY_H | ||
| 7 | |||
| 8 | #define PHYS_OFFSET UL(0x00000000) | ||
| 9 | |||
| 10 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 11 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 12 | |||
| 13 | |||
| 14 | #endif | ||
diff --git a/include/asm-arm/arch-mv78xx0/mv78xx0.h b/include/asm-arm/arch-mv78xx0/mv78xx0.h deleted file mode 100644 index 9f5d83c73faa..000000000000 --- a/include/asm-arm/arch-mv78xx0/mv78xx0.h +++ /dev/null | |||
| @@ -1,126 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/mv78xx0.h | ||
| 3 | * | ||
| 4 | * Generic definitions for Marvell MV78xx0 SoC flavors: | ||
| 5 | * MV781x0 and MV782x0. | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_MV78XX0_H | ||
| 13 | #define __ASM_ARCH_MV78XX0_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Marvell MV78xx0 address maps. | ||
| 17 | * | ||
| 18 | * phys | ||
| 19 | * c0000000 PCIe Memory space | ||
| 20 | * f0800000 PCIe #0 I/O space | ||
| 21 | * f0900000 PCIe #1 I/O space | ||
| 22 | * f0a00000 PCIe #2 I/O space | ||
| 23 | * f0b00000 PCIe #3 I/O space | ||
| 24 | * f0c00000 PCIe #4 I/O space | ||
| 25 | * f0d00000 PCIe #5 I/O space | ||
| 26 | * f0e00000 PCIe #6 I/O space | ||
| 27 | * f0f00000 PCIe #7 I/O space | ||
| 28 | * f1000000 on-chip peripheral registers | ||
| 29 | * | ||
| 30 | * virt phys size | ||
| 31 | * fe400000 f102x000 16K core-specific peripheral registers | ||
| 32 | * fe700000 f0800000 1M PCIe #0 I/O space | ||
| 33 | * fe800000 f0900000 1M PCIe #1 I/O space | ||
| 34 | * fe900000 f0a00000 1M PCIe #2 I/O space | ||
| 35 | * fea00000 f0b00000 1M PCIe #3 I/O space | ||
| 36 | * feb00000 f0c00000 1M PCIe #4 I/O space | ||
| 37 | * fec00000 f0d00000 1M PCIe #5 I/O space | ||
| 38 | * fed00000 f0e00000 1M PCIe #6 I/O space | ||
| 39 | * fee00000 f0f00000 1M PCIe #7 I/O space | ||
| 40 | * fef00000 f1000000 1M on-chip peripheral registers | ||
| 41 | */ | ||
| 42 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 | ||
| 43 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 | ||
| 44 | #define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 | ||
| 45 | #define MV78XX0_CORE_REGS_SIZE SZ_16K | ||
| 46 | |||
| 47 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) | ||
| 48 | #define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) | ||
| 49 | #define MV78XX0_PCIE_IO_SIZE SZ_1M | ||
| 50 | |||
| 51 | #define MV78XX0_REGS_PHYS_BASE 0xf1000000 | ||
| 52 | #define MV78XX0_REGS_VIRT_BASE 0xfef00000 | ||
| 53 | #define MV78XX0_REGS_SIZE SZ_1M | ||
| 54 | |||
| 55 | #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 | ||
| 56 | #define MV78XX0_PCIE_MEM_SIZE 0x30000000 | ||
| 57 | |||
| 58 | /* | ||
| 59 | * Core-specific peripheral registers. | ||
| 60 | */ | ||
| 61 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) | ||
| 62 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | ||
| 63 | #define L2_WRITETHROUGH 0x00020000 | ||
| 64 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
| 65 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
| 66 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
| 67 | #define SOFT_RESET 0x00000001 | ||
| 68 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
| 69 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
| 70 | #define BRIDGE_INT_TIMER0 0x0002 | ||
| 71 | #define BRIDGE_INT_TIMER1 0x0004 | ||
| 72 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | ||
| 73 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
| 74 | #define IRQ_CAUSE_LOW_OFF 0x0004 | ||
| 75 | #define IRQ_CAUSE_HIGH_OFF 0x0008 | ||
| 76 | #define IRQ_MASK_LOW_OFF 0x0010 | ||
| 77 | #define IRQ_MASK_HIGH_OFF 0x0014 | ||
| 78 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
| 79 | |||
| 80 | /* | ||
| 81 | * Register Map | ||
| 82 | */ | ||
| 83 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) | ||
| 84 | #define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) | ||
| 85 | #define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700) | ||
| 86 | |||
| 87 | #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) | ||
| 88 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) | ||
| 89 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) | ||
| 90 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) | ||
| 91 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) | ||
| 92 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | ||
| 93 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | ||
| 94 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) | ||
| 95 | #define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) | ||
| 96 | #define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) | ||
| 97 | #define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) | ||
| 98 | #define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) | ||
| 99 | |||
| 100 | #define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) | ||
| 101 | #define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) | ||
| 102 | |||
| 103 | #define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) | ||
| 104 | #define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) | ||
| 105 | #define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) | ||
| 106 | #define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) | ||
| 107 | |||
| 108 | #define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) | ||
| 109 | #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) | ||
| 110 | #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) | ||
| 111 | |||
| 112 | #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) | ||
| 113 | #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) | ||
| 114 | |||
| 115 | #define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) | ||
| 116 | #define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) | ||
| 117 | #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) | ||
| 118 | #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) | ||
| 119 | |||
| 120 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) | ||
| 121 | |||
| 122 | |||
| 123 | #define GPIO_MAX 32 | ||
| 124 | |||
| 125 | |||
| 126 | #endif | ||
diff --git a/include/asm-arm/arch-mv78xx0/system.h b/include/asm-arm/arch-mv78xx0/system.h deleted file mode 100644 index 7eb47d376db9..000000000000 --- a/include/asm-arm/arch-mv78xx0/system.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/system.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 10 | #define __ASM_ARCH_SYSTEM_H | ||
| 11 | |||
| 12 | #include <asm/arch/hardware.h> | ||
| 13 | #include <asm/arch/mv78xx0.h> | ||
| 14 | |||
| 15 | static inline void arch_idle(void) | ||
| 16 | { | ||
| 17 | cpu_do_idle(); | ||
| 18 | } | ||
| 19 | |||
| 20 | static inline void arch_reset(char mode) | ||
| 21 | { | ||
| 22 | /* | ||
| 23 | * Enable soft reset to assert RSTOUTn. | ||
| 24 | */ | ||
| 25 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Assert soft reset. | ||
| 29 | */ | ||
| 30 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | ||
| 31 | |||
| 32 | while (1) | ||
| 33 | ; | ||
| 34 | } | ||
| 35 | |||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-mv78xx0/timex.h b/include/asm-arm/arch-mv78xx0/timex.h deleted file mode 100644 index a854b1ccbd01..000000000000 --- a/include/asm-arm/arch-mv78xx0/timex.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/timex.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/include/asm-arm/arch-mv78xx0/uncompress.h b/include/asm-arm/arch-mv78xx0/uncompress.h deleted file mode 100644 index 3bfe0a293ef7..000000000000 --- a/include/asm-arm/arch-mv78xx0/uncompress.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/uncompress.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/serial_reg.h> | ||
| 10 | #include <asm/arch/mv78xx0.h> | ||
| 11 | |||
| 12 | #define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) | ||
| 13 | |||
| 14 | static void putc(const char c) | ||
| 15 | { | ||
| 16 | unsigned char *base = SERIAL_BASE; | ||
| 17 | int i; | ||
| 18 | |||
| 19 | for (i = 0; i < 0x1000; i++) { | ||
| 20 | if (base[UART_LSR << 2] & UART_LSR_THRE) | ||
| 21 | break; | ||
| 22 | barrier(); | ||
| 23 | } | ||
| 24 | |||
| 25 | base[UART_TX << 2] = c; | ||
| 26 | } | ||
| 27 | |||
| 28 | static void flush(void) | ||
| 29 | { | ||
| 30 | unsigned char *base = SERIAL_BASE; | ||
| 31 | unsigned char mask; | ||
| 32 | int i; | ||
| 33 | |||
| 34 | mask = UART_LSR_TEMT | UART_LSR_THRE; | ||
| 35 | |||
| 36 | for (i = 0; i < 0x1000; i++) { | ||
| 37 | if ((base[UART_LSR << 2] & mask) == mask) | ||
| 38 | break; | ||
| 39 | barrier(); | ||
| 40 | } | ||
| 41 | } | ||
| 42 | |||
| 43 | /* | ||
| 44 | * nothing to do | ||
| 45 | */ | ||
| 46 | #define arch_decomp_setup() | ||
| 47 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-mv78xx0/vmalloc.h b/include/asm-arm/arch-mv78xx0/vmalloc.h deleted file mode 100644 index f2c512197579..000000000000 --- a/include/asm-arm/arch-mv78xx0/vmalloc.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mv78xx0/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define VMALLOC_END 0xfe000000 | ||
diff --git a/include/asm-arm/arch-mxc/board-mx27ads.h b/include/asm-arm/arch-mxc/board-mx27ads.h deleted file mode 100644 index 61e66dac90ef..000000000000 --- a/include/asm-arm/arch-mxc/board-mx27ads.h +++ /dev/null | |||
| @@ -1,354 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__ | ||
| 15 | #define __ASM_ARCH_MXC_BOARD_MX27ADS_H__ | ||
| 16 | |||
| 17 | /* external interrupt multiplexer */ | ||
| 18 | #define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES) | ||
| 19 | |||
| 20 | #define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES) | ||
| 21 | #define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE | ||
| 22 | #define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1) | ||
| 23 | #define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2) | ||
| 24 | |||
| 25 | #define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \ | ||
| 26 | MXC_MAX_VIRTUAL_INTS) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * MXC UART EVB board level configurations | ||
| 30 | */ | ||
| 31 | |||
| 32 | #define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000) | ||
| 33 | #define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000) | ||
| 34 | #define MXC_LL_EXTUART_16BIT_BUS | ||
| 35 | |||
| 36 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR | ||
| 37 | #define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) | ||
| 38 | |||
| 39 | /* | ||
| 40 | * @name Memory Size parameters | ||
| 41 | */ | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Size of SDRAM memory | ||
| 45 | */ | ||
| 46 | #define SDRAM_MEM_SIZE SZ_128M | ||
| 47 | |||
| 48 | /* | ||
| 49 | * PBC Controller parameters | ||
| 50 | */ | ||
| 51 | |||
| 52 | /* | ||
| 53 | * Base address of PBC controller, CS4 | ||
| 54 | */ | ||
| 55 | #define PBC_BASE_ADDRESS 0xEB000000 | ||
| 56 | #define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset)) | ||
| 57 | |||
| 58 | /* | ||
| 59 | * PBC Interupt name definitions | ||
| 60 | */ | ||
| 61 | #define PBC_GPIO1_0 0 | ||
| 62 | #define PBC_GPIO1_1 1 | ||
| 63 | #define PBC_GPIO1_2 2 | ||
| 64 | #define PBC_GPIO1_3 3 | ||
| 65 | #define PBC_GPIO1_4 4 | ||
| 66 | #define PBC_GPIO1_5 5 | ||
| 67 | |||
| 68 | #define PBC_INTR_MAX_NUM 6 | ||
| 69 | #define PBC_INTR_SHARED_MAX_NUM 8 | ||
| 70 | |||
| 71 | /* When the PBC address connection is fixed in h/w, defined as 1 */ | ||
| 72 | #define PBC_ADDR_SH 0 | ||
| 73 | |||
| 74 | /* Offsets for the PBC Controller register */ | ||
| 75 | /* | ||
| 76 | * PBC Board version register offset | ||
| 77 | */ | ||
| 78 | #define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) | ||
| 79 | /* | ||
| 80 | * PBC Board control register 1 set address. | ||
| 81 | */ | ||
| 82 | #define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) | ||
| 83 | /* | ||
| 84 | * PBC Board control register 1 clear address. | ||
| 85 | */ | ||
| 86 | #define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) | ||
| 87 | /* | ||
| 88 | * PBC Board control register 2 set address. | ||
| 89 | */ | ||
| 90 | #define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH) | ||
| 91 | /* | ||
| 92 | * PBC Board control register 2 clear address. | ||
| 93 | */ | ||
| 94 | #define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH) | ||
| 95 | /* | ||
| 96 | * PBC Board control register 3 set address. | ||
| 97 | */ | ||
| 98 | #define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH) | ||
| 99 | /* | ||
| 100 | * PBC Board control register 3 clear address. | ||
| 101 | */ | ||
| 102 | #define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH) | ||
| 103 | /* | ||
| 104 | * PBC Board control register 3 set address. | ||
| 105 | */ | ||
| 106 | #define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH) | ||
| 107 | /* | ||
| 108 | * PBC Board control register 4 clear address. | ||
| 109 | */ | ||
| 110 | #define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH) | ||
| 111 | /*PBC_ADDR_SH | ||
| 112 | * PBC Board status register 1. | ||
| 113 | */ | ||
| 114 | #define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH) | ||
| 115 | /* | ||
| 116 | * PBC Board interrupt status register. | ||
| 117 | */ | ||
| 118 | #define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH) | ||
| 119 | /* | ||
| 120 | * PBC Board interrupt current status register. | ||
| 121 | */ | ||
| 122 | #define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH) | ||
| 123 | /* | ||
| 124 | * PBC Interrupt mask register set address. | ||
| 125 | */ | ||
| 126 | #define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH) | ||
| 127 | /* | ||
| 128 | * PBC Interrupt mask register clear address. | ||
| 129 | */ | ||
| 130 | #define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH) | ||
| 131 | /* | ||
| 132 | * External UART A. | ||
| 133 | */ | ||
| 134 | #define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH) | ||
| 135 | /* | ||
| 136 | * UART 4 Expanding Signal Status. | ||
| 137 | */ | ||
| 138 | #define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH) | ||
| 139 | /* | ||
| 140 | * UART 4 Expanding Signal Control Set. | ||
| 141 | */ | ||
| 142 | #define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH) | ||
| 143 | /* | ||
| 144 | * UART 4 Expanding Signal Control Clear. | ||
| 145 | */ | ||
| 146 | #define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH) | ||
| 147 | /* | ||
| 148 | * Ethernet Controller IO base address. | ||
| 149 | */ | ||
| 150 | #define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH) | ||
| 151 | /* | ||
| 152 | * Ethernet Controller Memory base address. | ||
| 153 | */ | ||
| 154 | #define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH) | ||
| 155 | /* | ||
| 156 | * Ethernet Controller DMA base address. | ||
| 157 | */ | ||
| 158 | #define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH) | ||
| 159 | |||
| 160 | /* PBC Board Version Register bit definition */ | ||
| 161 | #define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */ | ||
| 162 | #define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */ | ||
| 163 | |||
| 164 | /* PBC Board Control Register 1 bit definitions */ | ||
| 165 | #define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */ | ||
| 166 | #define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */ | ||
| 167 | #define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */ | ||
| 168 | #define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */ | ||
| 169 | #define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ | ||
| 170 | |||
| 171 | /* PBC Board Control Register 2 bit definitions */ | ||
| 172 | #define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */ | ||
| 173 | #define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */ | ||
| 174 | #define PBC_BCTRL2_ATAFEC_EN 0X0010 | ||
| 175 | #define PBC_BCTRL2_ATAFEC_SEL 0X0020 | ||
| 176 | #define PBC_BCTRL2_ATA_EN 0X0040 | ||
| 177 | #define PBC_BCTRL2_IRDA_SD 0X0080 | ||
| 178 | #define PBC_BCTRL2_IRDA_EN 0X0100 | ||
| 179 | #define PBC_BCTRL2_CCTL10 0X0200 | ||
| 180 | #define PBC_BCTRL2_CCTL11 0X0400 | ||
| 181 | |||
| 182 | /* PBC Board Control Register 3 bit definitions */ | ||
| 183 | #define PBC_BCTRL3_HSH_EN 0X0020 | ||
| 184 | #define PBC_BCTRL3_FSH_MOD 0X0040 | ||
| 185 | #define PBC_BCTRL3_OTG_HS_EN 0X0080 | ||
| 186 | #define PBC_BCTRL3_OTG_VBUS_EN 0X0100 | ||
| 187 | #define PBC_BCTRL3_FSH_VBUS_EN 0X0200 | ||
| 188 | #define PBC_BCTRL3_USB_OTG_ON 0X0800 | ||
| 189 | #define PBC_BCTRL3_USB_FSH_ON 0X1000 | ||
| 190 | |||
| 191 | /* PBC Board Control Register 4 bit definitions */ | ||
| 192 | #define PBC_BCTRL4_REGEN_SEL 0X0001 | ||
| 193 | #define PBC_BCTRL4_USER_OFF 0X0002 | ||
| 194 | #define PBC_BCTRL4_VIB_EN 0X0004 | ||
| 195 | #define PBC_BCTRL4_PWRGT1_EN 0X0008 | ||
| 196 | #define PBC_BCTRL4_PWRGT2_EN 0X0010 | ||
| 197 | #define PBC_BCTRL4_STDBY_PRI 0X0020 | ||
| 198 | |||
| 199 | #ifndef __ASSEMBLY__ | ||
| 200 | /* | ||
| 201 | * Enumerations for SD cards and memory stick card. This corresponds to | ||
| 202 | * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN. | ||
| 203 | */ | ||
| 204 | enum mxc_card_no { | ||
| 205 | MXC_CARD_SD2 = 0, | ||
| 206 | MXC_CARD_SD3, | ||
| 207 | MXC_CARD_MS, | ||
| 208 | MXC_CARD_SD1, | ||
| 209 | MXC_CARD_MIN = MXC_CARD_SD2, | ||
| 210 | MXC_CARD_MAX = MXC_CARD_SD1, | ||
| 211 | }; | ||
| 212 | #endif | ||
| 213 | |||
| 214 | #define MXC_CPLD_VER_1_50 0x01 | ||
| 215 | |||
| 216 | /* | ||
| 217 | * PBC BSTAT Register bit definitions | ||
| 218 | */ | ||
| 219 | #define PBC_BSTAT_PRI_INT 0X0001 | ||
| 220 | #define PBC_BSTAT_USB_BYP 0X0002 | ||
| 221 | #define PBC_BSTAT_ATA_IOCS16 0X0004 | ||
| 222 | #define PBC_BSTAT_ATA_CBLID 0X0008 | ||
| 223 | #define PBC_BSTAT_ATA_DASP 0X0010 | ||
| 224 | #define PBC_BSTAT_PWR_RDY 0X0020 | ||
| 225 | #define PBC_BSTAT_SD3_WP 0X0100 | ||
| 226 | #define PBC_BSTAT_SD2_WP 0X0200 | ||
| 227 | #define PBC_BSTAT_SD1_WP 0X0400 | ||
| 228 | #define PBC_BSTAT_SD3_DET 0X0800 | ||
| 229 | #define PBC_BSTAT_SD2_DET 0X1000 | ||
| 230 | #define PBC_BSTAT_SD1_DET 0X2000 | ||
| 231 | #define PBC_BSTAT_MS_DET 0X4000 | ||
| 232 | #define PBC_BSTAT_SD3_DET_BIT 11 | ||
| 233 | #define PBC_BSTAT_SD2_DET_BIT 12 | ||
| 234 | #define PBC_BSTAT_SD1_DET_BIT 13 | ||
| 235 | #define PBC_BSTAT_MS_DET_BIT 14 | ||
| 236 | #define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \ | ||
| 237 | ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \ | ||
| 238 | ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \ | ||
| 239 | ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \ | ||
| 240 | 0x0)))) | ||
| 241 | |||
| 242 | /* | ||
| 243 | * PBC UART Control Register bit definitions | ||
| 244 | */ | ||
| 245 | #define PBC_UCTRL_DCE_DCD 0X0001 | ||
| 246 | #define PBC_UCTRL_DCE_DSR 0X0002 | ||
| 247 | #define PBC_UCTRL_DCE_RI 0X0004 | ||
| 248 | #define PBC_UCTRL_DTE_DTR 0X0100 | ||
| 249 | |||
| 250 | /* | ||
| 251 | * PBC UART Status Register bit definitions | ||
| 252 | */ | ||
| 253 | #define PBC_USTAT_DTE_DCD 0X0001 | ||
| 254 | #define PBC_USTAT_DTE_DSR 0X0002 | ||
| 255 | #define PBC_USTAT_DTE_RI 0X0004 | ||
| 256 | #define PBC_USTAT_DCE_DTR 0X0100 | ||
| 257 | |||
| 258 | /* | ||
| 259 | * PBC Interupt mask register bit definitions | ||
| 260 | */ | ||
| 261 | #define PBC_INTR_SD3_R_EN_BIT 4 | ||
| 262 | #define PBC_INTR_SD2_R_EN_BIT 0 | ||
| 263 | #define PBC_INTR_SD1_R_EN_BIT 6 | ||
| 264 | #define PBC_INTR_MS_R_EN_BIT 5 | ||
| 265 | #define PBC_INTR_SD3_EN_BIT 13 | ||
| 266 | #define PBC_INTR_SD2_EN_BIT 12 | ||
| 267 | #define PBC_INTR_MS_EN_BIT 14 | ||
| 268 | #define PBC_INTR_SD1_EN_BIT 15 | ||
| 269 | |||
| 270 | #define PBC_INTR_SD2_R_EN 0x0001 | ||
| 271 | #define PBC_INTR_LOW_BAT 0X0002 | ||
| 272 | #define PBC_INTR_OTG_FSOVER 0X0004 | ||
| 273 | #define PBC_INTR_FSH_OVER 0X0008 | ||
| 274 | #define PBC_INTR_SD3_R_EN 0x0010 | ||
| 275 | #define PBC_INTR_MS_R_EN 0x0020 | ||
| 276 | #define PBC_INTR_SD1_R_EN 0x0040 | ||
| 277 | #define PBC_INTR_FEC_INT 0X0080 | ||
| 278 | #define PBC_INTR_ENET_INT 0X0100 | ||
| 279 | #define PBC_INTR_OTGFS_INT 0X0200 | ||
| 280 | #define PBC_INTR_XUART_INT 0X0400 | ||
| 281 | #define PBC_INTR_CCTL12 0X0800 | ||
| 282 | #define PBC_INTR_SD2_EN 0x1000 | ||
| 283 | #define PBC_INTR_SD3_EN 0x2000 | ||
| 284 | #define PBC_INTR_MS_EN 0x4000 | ||
| 285 | #define PBC_INTR_SD1_EN 0x8000 | ||
| 286 | |||
| 287 | |||
| 288 | |||
| 289 | /* For interrupts like xuart, enet etc */ | ||
| 290 | #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN) | ||
| 291 | #define MXC_MAX_EXP_IO_LINES 16 | ||
| 292 | |||
| 293 | /* | ||
| 294 | * This corresponds to PBC_INTMASK_SET_REG at offset 0x38. | ||
| 295 | * | ||
| 296 | */ | ||
| 297 | #define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1) | ||
| 298 | #define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) | ||
| 299 | #define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) | ||
| 300 | #define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) | ||
| 301 | #define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) | ||
| 302 | #define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) | ||
| 303 | #define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7) | ||
| 304 | #define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) | ||
| 305 | #define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) | ||
| 306 | #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) | ||
| 307 | #define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11) | ||
| 308 | #define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12) | ||
| 309 | #define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13) | ||
| 310 | #define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14) | ||
| 311 | #define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15) | ||
| 312 | |||
| 313 | /* | ||
| 314 | * This is System IRQ used by CS8900A for interrupt generation | ||
| 315 | * taken from platform.h | ||
| 316 | */ | ||
| 317 | #define CS8900AIRQ EXPIO_INT_ENET_INT | ||
| 318 | /* This is I/O Base address used to access registers of CS8900A on MXC ADS */ | ||
| 319 | #define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300) | ||
| 320 | |||
| 321 | #define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT) | ||
| 322 | |||
| 323 | /* | ||
| 324 | * This is used to detect if the CPLD version is for mx27 evb board rev-a | ||
| 325 | */ | ||
| 326 | #define PBC_CPLD_VERSION_IS_REVA() \ | ||
| 327 | ((__raw_readw(PBC_VERSION_REG) & \ | ||
| 328 | (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\ | ||
| 329 | == 0) | ||
| 330 | |||
| 331 | /* This is used to active or inactive ata signal in CPLD . | ||
| 332 | * It is dependent with hardware | ||
| 333 | */ | ||
| 334 | #define PBC_ATA_SIGNAL_ACTIVE() \ | ||
| 335 | __raw_writew( \ | ||
| 336 | PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \ | ||
| 337 | PBC_BCTRL2_CLEAR_REG) | ||
| 338 | |||
| 339 | #define PBC_ATA_SIGNAL_INACTIVE() \ | ||
| 340 | __raw_writew( \ | ||
| 341 | PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \ | ||
| 342 | PBC_BCTRL2_SET_REG) | ||
| 343 | |||
| 344 | #define MXC_BD_LED1 (1 << 5) | ||
| 345 | #define MXC_BD_LED2 (1 << 6) | ||
| 346 | #define MXC_BD_LED_ON(led) \ | ||
| 347 | __raw_writew(led, PBC_BCTRL1_SET_REG) | ||
| 348 | #define MXC_BD_LED_OFF(led) \ | ||
| 349 | __raw_writew(led, PBC_BCTRL1_CLEAR_REG) | ||
| 350 | |||
| 351 | /* to determine the correct external crystal reference */ | ||
| 352 | #define CKIH_27MHZ_BIT_SET (1 << 3) | ||
| 353 | |||
| 354 | #endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h deleted file mode 100644 index 1bc6fb0f9a83..000000000000 --- a/include/asm-arm/arch-mxc/board-mx31ads.h +++ /dev/null | |||
| @@ -1,117 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ | ||
| 12 | #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ | ||
| 13 | |||
| 14 | /* Base address of PBC controller */ | ||
| 15 | #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) | ||
| 16 | /* Offsets for the PBC Controller register */ | ||
| 17 | |||
| 18 | /* PBC Board status register offset */ | ||
| 19 | #define PBC_BSTAT 0x000002 | ||
| 20 | |||
| 21 | /* PBC Board control register 1 set address */ | ||
| 22 | #define PBC_BCTRL1_SET 0x000004 | ||
| 23 | |||
| 24 | /* PBC Board control register 1 clear address */ | ||
| 25 | #define PBC_BCTRL1_CLEAR 0x000006 | ||
| 26 | |||
| 27 | /* PBC Board control register 2 set address */ | ||
| 28 | #define PBC_BCTRL2_SET 0x000008 | ||
| 29 | |||
| 30 | /* PBC Board control register 2 clear address */ | ||
| 31 | #define PBC_BCTRL2_CLEAR 0x00000A | ||
| 32 | |||
| 33 | /* PBC Board control register 3 set address */ | ||
| 34 | #define PBC_BCTRL3_SET 0x00000C | ||
| 35 | |||
| 36 | /* PBC Board control register 3 clear address */ | ||
| 37 | #define PBC_BCTRL3_CLEAR 0x00000E | ||
| 38 | |||
| 39 | /* PBC Board control register 4 set address */ | ||
| 40 | #define PBC_BCTRL4_SET 0x000010 | ||
| 41 | |||
| 42 | /* PBC Board control register 4 clear address */ | ||
| 43 | #define PBC_BCTRL4_CLEAR 0x000012 | ||
| 44 | |||
| 45 | /* PBC Board status register 1 */ | ||
| 46 | #define PBC_BSTAT1 0x000014 | ||
| 47 | |||
| 48 | /* PBC Board interrupt status register */ | ||
| 49 | #define PBC_INTSTATUS 0x000016 | ||
| 50 | |||
| 51 | /* PBC Board interrupt current status register */ | ||
| 52 | #define PBC_INTCURR_STATUS 0x000018 | ||
| 53 | |||
| 54 | /* PBC Interrupt mask register set address */ | ||
| 55 | #define PBC_INTMASK_SET 0x00001A | ||
| 56 | |||
| 57 | /* PBC Interrupt mask register clear address */ | ||
| 58 | #define PBC_INTMASK_CLEAR 0x00001C | ||
| 59 | |||
| 60 | /* External UART A */ | ||
| 61 | #define PBC_SC16C652_UARTA 0x010000 | ||
| 62 | |||
| 63 | /* External UART B */ | ||
| 64 | #define PBC_SC16C652_UARTB 0x010010 | ||
| 65 | |||
| 66 | /* Ethernet Controller IO base address */ | ||
| 67 | #define PBC_CS8900A_IOBASE 0x020000 | ||
| 68 | |||
| 69 | /* Ethernet Controller Memory base address */ | ||
| 70 | #define PBC_CS8900A_MEMBASE 0x021000 | ||
| 71 | |||
| 72 | /* Ethernet Controller DMA base address */ | ||
| 73 | #define PBC_CS8900A_DMABASE 0x022000 | ||
| 74 | |||
| 75 | /* External chip select 0 */ | ||
| 76 | #define PBC_XCS0 0x040000 | ||
| 77 | |||
| 78 | /* LCD Display enable */ | ||
| 79 | #define PBC_LCD_EN_B 0x060000 | ||
| 80 | |||
| 81 | /* Code test debug enable */ | ||
| 82 | #define PBC_CODE_B 0x070000 | ||
| 83 | |||
| 84 | /* PSRAM memory select */ | ||
| 85 | #define PBC_PSRAM_B 0x5000000 | ||
| 86 | |||
| 87 | #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) | ||
| 88 | #define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS) | ||
| 89 | #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) | ||
| 90 | #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) | ||
| 91 | #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) | ||
| 92 | |||
| 93 | #define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0) | ||
| 94 | #define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1) | ||
| 95 | #define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2) | ||
| 96 | #define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3) | ||
| 97 | #define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4) | ||
| 98 | #define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5) | ||
| 99 | #define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6) | ||
| 100 | #define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7) | ||
| 101 | #define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8) | ||
| 102 | #define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9) | ||
| 103 | #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) | ||
| 104 | #define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) | ||
| 105 | #define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12) | ||
| 106 | #define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13) | ||
| 107 | #define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14) | ||
| 108 | #define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15) | ||
| 109 | |||
| 110 | #define MXC_MAX_EXP_IO_LINES 16 | ||
| 111 | |||
| 112 | /* mandatory for CONFIG_LL_DEBUG */ | ||
| 113 | |||
| 114 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR | ||
| 115 | #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) | ||
| 116 | |||
| 117 | #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/board-mx31lite.h b/include/asm-arm/arch-mxc/board-mx31lite.h deleted file mode 100644 index e4e5cf5ad7db..000000000000 --- a/include/asm-arm/arch-mxc/board-mx31lite.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ | ||
| 12 | #define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ | ||
| 13 | |||
| 14 | #define MXC_MAX_EXP_IO_LINES 16 | ||
| 15 | |||
| 16 | |||
| 17 | /* | ||
| 18 | * Memory Size parameters | ||
| 19 | */ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Size of SDRAM memory | ||
| 23 | */ | ||
| 24 | #define SDRAM_MEM_SIZE SZ_128M | ||
| 25 | /* | ||
| 26 | * Size of MBX buffer memory | ||
| 27 | */ | ||
| 28 | #define MXC_MBX_MEM_SIZE SZ_16M | ||
| 29 | /* | ||
| 30 | * Size of memory available to kernel | ||
| 31 | */ | ||
| 32 | #define MEM_SIZE (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE) | ||
| 33 | |||
| 34 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR | ||
| 35 | #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) | ||
| 36 | |||
| 37 | #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ | ||
| 38 | |||
diff --git a/include/asm-arm/arch-mxc/board-pcm037.h b/include/asm-arm/arch-mxc/board-pcm037.h deleted file mode 100644 index 82232ba3c8fc..000000000000 --- a/include/asm-arm/arch-mxc/board-pcm037.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 Sascha Hauer, Pengutronix | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__ | ||
| 20 | #define __ASM_ARCH_MXC_BOARD_PCM037_H__ | ||
| 21 | |||
| 22 | /* mandatory for CONFIG_LL_DEBUG */ | ||
| 23 | |||
| 24 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR | ||
| 25 | #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) | ||
| 26 | |||
| 27 | #endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/board-pcm038.h b/include/asm-arm/arch-mxc/board-pcm038.h deleted file mode 100644 index 750c62afd90f..000000000000 --- a/include/asm-arm/arch-mxc/board-pcm038.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__ | ||
| 20 | #define __ASM_ARCH_MXC_BOARD_PCM038_H__ | ||
| 21 | |||
| 22 | /* mandatory for CONFIG_LL_DEBUG */ | ||
| 23 | |||
| 24 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR | ||
| 25 | #define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000) | ||
| 26 | |||
| 27 | #ifndef __ASSEMBLY__ | ||
| 28 | /* | ||
| 29 | * This CPU module needs a baseboard to work. After basic initializing | ||
| 30 | * its own devices, it calls baseboard's init function. | ||
| 31 | * TODO: Add your own baseboard init function and call it from | ||
| 32 | * inside pcm038_init(). | ||
| 33 | * | ||
| 34 | * This example here is for the development board. Refer pcm970-baseboard.c | ||
| 35 | */ | ||
| 36 | |||
| 37 | extern void pcm970_baseboard_init(void); | ||
| 38 | |||
| 39 | #endif | ||
| 40 | |||
| 41 | #endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/clock.h b/include/asm-arm/arch-mxc/clock.h deleted file mode 100644 index 24caa2b7c91d..000000000000 --- a/include/asm-arm/arch-mxc/clock.h +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_MXC_CLOCK_H__ | ||
| 21 | #define __ASM_ARCH_MXC_CLOCK_H__ | ||
| 22 | |||
| 23 | #ifndef __ASSEMBLY__ | ||
| 24 | #include <linux/list.h> | ||
| 25 | |||
| 26 | struct module; | ||
| 27 | |||
| 28 | struct clk { | ||
| 29 | struct list_head node; | ||
| 30 | struct module *owner; | ||
| 31 | const char *name; | ||
| 32 | int id; | ||
| 33 | /* Source clock this clk depends on */ | ||
| 34 | struct clk *parent; | ||
| 35 | /* Secondary clock to enable/disable with this clock */ | ||
| 36 | struct clk *secondary; | ||
| 37 | /* Reference count of clock enable/disable */ | ||
| 38 | __s8 usecount; | ||
| 39 | /* Register bit position for clock's enable/disable control. */ | ||
| 40 | u8 enable_shift; | ||
| 41 | /* Register address for clock's enable/disable control. */ | ||
| 42 | u32 enable_reg; | ||
| 43 | u32 flags; | ||
| 44 | /* get the current clock rate (always a fresh value) */ | ||
| 45 | unsigned long (*get_rate) (struct clk *); | ||
| 46 | /* Function ptr to set the clock to a new rate. The rate must match a | ||
| 47 | supported rate returned from round_rate. Leave blank if clock is not | ||
| 48 | programmable */ | ||
| 49 | int (*set_rate) (struct clk *, unsigned long); | ||
| 50 | /* Function ptr to round the requested clock rate to the nearest | ||
| 51 | supported rate that is less than or equal to the requested rate. */ | ||
| 52 | unsigned long (*round_rate) (struct clk *, unsigned long); | ||
| 53 | /* Function ptr to enable the clock. Leave blank if clock can not | ||
| 54 | be gated. */ | ||
| 55 | int (*enable) (struct clk *); | ||
| 56 | /* Function ptr to disable the clock. Leave blank if clock can not | ||
| 57 | be gated. */ | ||
| 58 | void (*disable) (struct clk *); | ||
| 59 | /* Function ptr to set the parent clock of the clock. */ | ||
| 60 | int (*set_parent) (struct clk *, struct clk *); | ||
| 61 | }; | ||
| 62 | |||
| 63 | int clk_register(struct clk *clk); | ||
| 64 | void clk_unregister(struct clk *clk); | ||
| 65 | |||
| 66 | #endif /* __ASSEMBLY__ */ | ||
| 67 | #endif /* __ASM_ARCH_MXC_CLOCK_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h deleted file mode 100644 index a6d2e24aab15..000000000000 --- a/include/asm-arm/arch-mxc/common.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_COMMON_H__ | ||
| 12 | #define __ASM_ARCH_MXC_COMMON_H__ | ||
| 13 | |||
| 14 | extern void mxc_map_io(void); | ||
| 15 | extern void mxc_init_irq(void); | ||
| 16 | extern void mxc_timer_init(const char *clk_timer); | ||
| 17 | extern int mxc_clocks_init(unsigned long fref); | ||
| 18 | extern int mxc_register_gpios(void); | ||
| 19 | |||
| 20 | #endif | ||
diff --git a/include/asm-arm/arch-mxc/debug-macro.S b/include/asm-arm/arch-mxc/debug-macro.S deleted file mode 100644 index 575087f8561a..000000000000 --- a/include/asm-arm/arch-mxc/debug-macro.S +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-imx/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | #ifdef CONFIG_MACH_MX31ADS | ||
| 17 | #include <asm/arch/board-mx31ads.h> | ||
| 18 | #endif | ||
| 19 | #ifdef CONFIG_MACH_PCM037 | ||
| 20 | #include <asm/arch/board-pcm037.h> | ||
| 21 | #endif | ||
| 22 | #ifdef CONFIG_MACH_MX31LITE | ||
| 23 | #include <asm/arch/board-mx31lite.h> | ||
| 24 | #endif | ||
| 25 | #ifdef CONFIG_MACH_MX27ADS | ||
| 26 | #include <asm/arch/board-mx27ads.h> | ||
| 27 | #endif | ||
| 28 | #ifdef CONFIG_MACH_PCM038 | ||
| 29 | #include <asm/arch/board-pcm038.h> | ||
| 30 | #endif | ||
| 31 | .macro addruart,rx | ||
| 32 | mrc p15, 0, \rx, c1, c0 | ||
| 33 | tst \rx, #1 @ MMU enabled? | ||
| 34 | ldreq \rx, =MXC_LL_UART_PADDR @ physical | ||
| 35 | ldrne \rx, =MXC_LL_UART_VADDR @ virtual | ||
| 36 | .endm | ||
| 37 | |||
| 38 | .macro senduart,rd,rx | ||
| 39 | str \rd, [\rx, #0x40] @ TXDATA | ||
| 40 | .endm | ||
| 41 | |||
| 42 | .macro waituart,rd,rx | ||
| 43 | .endm | ||
| 44 | |||
| 45 | .macro busyuart,rd,rx | ||
| 46 | 1002: ldr \rd, [\rx, #0x98] @ SR2 | ||
| 47 | tst \rd, #1 << 3 @ TXDC | ||
| 48 | beq 1002b @ wait until transmit done | ||
| 49 | .endm | ||
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h deleted file mode 100644 index c822d569a05e..000000000000 --- a/include/asm-arm/arch-mxc/dma.h +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_DMA_H__ | ||
| 12 | #define __ASM_ARCH_MXC_DMA_H__ | ||
| 13 | |||
| 14 | #endif | ||
diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/include/asm-arm/arch-mxc/entry-macro.S deleted file mode 100644 index b542433afb1b..000000000000 --- a/include/asm-arm/arch-mxc/entry-macro.S +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> | ||
| 3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 4 | */ | ||
| 5 | |||
| 6 | /* | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | @ this macro disables fast irq (not implemented) | ||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro get_irqnr_preamble, base, tmp | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | @ this macro checks which interrupt occured | ||
| 23 | @ and returns its number in irqnr | ||
| 24 | @ and returns if an interrupt occured in irqstat | ||
| 25 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 26 | ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR) | ||
| 27 | @ Load offset & priority of the highest priority | ||
| 28 | @ interrupt pending from AVIC_NIVECSR | ||
| 29 | ldr \irqstat, [\base, #0x40] | ||
| 30 | @ Shift to get the decoded IRQ number, using ASR so | ||
| 31 | @ 'no interrupt pending' becomes 0xffffffff | ||
| 32 | mov \irqnr, \irqstat, asr #16 | ||
| 33 | @ set zero flag if IRQ + 1 == 0 | ||
| 34 | adds \tmp, \irqnr, #1 | ||
| 35 | .endm | ||
| 36 | |||
| 37 | @ irq priority table (not used) | ||
| 38 | .macro irq_prio_table | ||
| 39 | .endm | ||
diff --git a/include/asm-arm/arch-mxc/gpio.h b/include/asm-arm/arch-mxc/gpio.h deleted file mode 100644 index 5f13a65e4044..000000000000 --- a/include/asm-arm/arch-mxc/gpio.h +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_MXC_GPIO_H__ | ||
| 20 | #define __ASM_ARCH_MXC_GPIO_H__ | ||
| 21 | |||
| 22 | #include <asm/arch/hardware.h> | ||
| 23 | #include <asm-generic/gpio.h> | ||
| 24 | |||
| 25 | /* use gpiolib dispatchers */ | ||
| 26 | #define gpio_get_value __gpio_get_value | ||
| 27 | #define gpio_set_value __gpio_set_value | ||
| 28 | #define gpio_cansleep __gpio_cansleep | ||
| 29 | |||
| 30 | #define gpio_to_irq(gpio) (MXC_MAX_INT_LINES + (gpio)) | ||
| 31 | #define irq_to_gpio(irq) ((irq) - MXC_MAX_INT_LINES) | ||
| 32 | |||
| 33 | struct mxc_gpio_port { | ||
| 34 | void __iomem *base; | ||
| 35 | int irq; | ||
| 36 | int virtual_irq_start; | ||
| 37 | struct gpio_chip chip; | ||
| 38 | }; | ||
| 39 | |||
| 40 | int mxc_gpio_init(struct mxc_gpio_port*, int); | ||
| 41 | |||
| 42 | #endif | ||
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h deleted file mode 100644 index 37cddbaaade7..000000000000 --- a/include/asm-arm/arch-mxc/hardware.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 21 | #define __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 22 | |||
| 23 | #include <asm/sizes.h> | ||
| 24 | |||
| 25 | #ifdef CONFIG_ARCH_MX3 | ||
| 26 | # include <asm/arch/mx31.h> | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifdef CONFIG_ARCH_MX2 | ||
| 30 | # ifdef CONFIG_MACH_MX27 | ||
| 31 | # include <asm/arch/mx27.h> | ||
| 32 | # endif | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #include <asm/arch/mxc.h> | ||
| 36 | |||
| 37 | #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/iim.h b/include/asm-arm/arch-mxc/iim.h deleted file mode 100644 index 315bffadafda..000000000000 --- a/include/asm-arm/arch-mxc/iim.h +++ /dev/null | |||
| @@ -1,77 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_MXC_IIM_H__ | ||
| 21 | #define __ASM_ARCH_MXC_IIM_H__ | ||
| 22 | |||
| 23 | /* Register offsets */ | ||
| 24 | #define MXC_IIMSTAT 0x0000 | ||
| 25 | #define MXC_IIMSTATM 0x0004 | ||
| 26 | #define MXC_IIMERR 0x0008 | ||
| 27 | #define MXC_IIMEMASK 0x000C | ||
| 28 | #define MXC_IIMFCTL 0x0010 | ||
| 29 | #define MXC_IIMUA 0x0014 | ||
| 30 | #define MXC_IIMLA 0x0018 | ||
| 31 | #define MXC_IIMSDAT 0x001C | ||
| 32 | #define MXC_IIMPREV 0x0020 | ||
| 33 | #define MXC_IIMSREV 0x0024 | ||
| 34 | #define MXC_IIMPRG_P 0x0028 | ||
| 35 | #define MXC_IIMSCS0 0x002C | ||
| 36 | #define MXC_IIMSCS1 0x0030 | ||
| 37 | #define MXC_IIMSCS2 0x0034 | ||
| 38 | #define MXC_IIMSCS3 0x0038 | ||
| 39 | #define MXC_IIMFBAC0 0x0800 | ||
| 40 | #define MXC_IIMJAC 0x0804 | ||
| 41 | #define MXC_IIMHWV1 0x0808 | ||
| 42 | #define MXC_IIMHWV2 0x080C | ||
| 43 | #define MXC_IIMHAB0 0x0810 | ||
| 44 | #define MXC_IIMHAB1 0x0814 | ||
| 45 | /* Definitions for i.MX27 TO2 */ | ||
| 46 | #define MXC_IIMMAC 0x0814 | ||
| 47 | #define MXC_IIMPREV_FUSE 0x0818 | ||
| 48 | #define MXC_IIMSREV_FUSE 0x081C | ||
| 49 | #define MXC_IIMSJC_CHALL_0 0x0820 | ||
| 50 | #define MXC_IIMSJC_CHALL_7 0x083C | ||
| 51 | #define MXC_IIMFB0UC17 0x0840 | ||
| 52 | #define MXC_IIMFB0UC255 0x0BFC | ||
| 53 | #define MXC_IIMFBAC1 0x0C00 | ||
| 54 | /* Definitions for i.MX27 TO2 */ | ||
| 55 | #define MXC_IIMSUID 0x0C04 | ||
| 56 | #define MXC_IIMKEY0 0x0C04 | ||
| 57 | #define MXC_IIMKEY20 0x0C54 | ||
| 58 | #define MXC_IIMSJC_RESP_0 0x0C58 | ||
| 59 | #define MXC_IIMSJC_RESP_7 0x0C74 | ||
| 60 | #define MXC_IIMFB1UC30 0x0C78 | ||
| 61 | #define MXC_IIMFB1UC255 0x0FFC | ||
| 62 | |||
| 63 | /* Bit definitions */ | ||
| 64 | |||
| 65 | #define MXC_IIMHWV1_WLOCK (0x1 << 7) | ||
| 66 | #define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6) | ||
| 67 | #define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5) | ||
| 68 | #define MXC_IIMHWV1_BOOT_INT (0x1 << 4) | ||
| 69 | #define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3) | ||
| 70 | #define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2) | ||
| 71 | #define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1) | ||
| 72 | |||
| 73 | #define MXC_IIMHWV2_WLOCK (0x1 << 7) | ||
| 74 | #define MXC_IIMHWV2_BP_SDMA (0x1 << 6) | ||
| 75 | #define MXC_IIMHWV2_SCM_DCM (0x1 << 5) | ||
| 76 | |||
| 77 | #endif /* __ASM_ARCH_MXC_IIM_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/imx-uart.h b/include/asm-arm/arch-mxc/imx-uart.h deleted file mode 100644 index 83fb72c4048a..000000000000 --- a/include/asm-arm/arch-mxc/imx-uart.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef ASMARM_ARCH_UART_H | ||
| 20 | #define ASMARM_ARCH_UART_H | ||
| 21 | |||
| 22 | #define IMXUART_HAVE_RTSCTS (1<<0) | ||
| 23 | |||
| 24 | struct imxuart_platform_data { | ||
| 25 | int (*init)(struct platform_device *pdev); | ||
| 26 | int (*exit)(struct platform_device *pdev); | ||
| 27 | unsigned int flags; | ||
| 28 | }; | ||
| 29 | |||
| 30 | int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata); | ||
| 31 | |||
| 32 | #endif | ||
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h deleted file mode 100644 index 65b6810124c1..000000000000 --- a/include/asm-arm/arch-mxc/io.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_IO_H__ | ||
| 12 | #define __ASM_ARCH_MXC_IO_H__ | ||
| 13 | |||
| 14 | /* Allow IO space to be anywhere in the memory */ | ||
| 15 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 16 | |||
| 17 | /* io address mapping macro */ | ||
| 18 | #define __io(a) ((void __iomem *)(a)) | ||
| 19 | |||
| 20 | #define __mem_pci(a) (a) | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/include/asm-arm/arch-mxc/iomux-mx1-mx2.h b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h deleted file mode 100644 index 076d37b38eb2..000000000000 --- a/include/asm-arm/arch-mxc/iomux-mx1-mx2.h +++ /dev/null | |||
| @@ -1,372 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef _MXC_GPIO_MX1_MX2_H | ||
| 20 | #define _MXC_GPIO_MX1_MX2_H | ||
| 21 | |||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | #define MXC_GPIO_ALLOC_MODE_NORMAL 0 | ||
| 25 | #define MXC_GPIO_ALLOC_MODE_NO_ALLOC 1 | ||
| 26 | #define MXC_GPIO_ALLOC_MODE_TRY_ALLOC 2 | ||
| 27 | #define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY 4 | ||
| 28 | #define MXC_GPIO_ALLOC_MODE_RELEASE 8 | ||
| 29 | |||
| 30 | /* | ||
| 31 | * GPIO Module and I/O Multiplexer | ||
| 32 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D | ||
| 33 | */ | ||
| 34 | #define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR) | ||
| 35 | #define MXC_DDIR(x) (0x00 + ((x) << 8)) | ||
| 36 | #define MXC_OCR1(x) (0x04 + ((x) << 8)) | ||
| 37 | #define MXC_OCR2(x) (0x08 + ((x) << 8)) | ||
| 38 | #define MXC_ICONFA1(x) (0x0c + ((x) << 8)) | ||
| 39 | #define MXC_ICONFA2(x) (0x10 + ((x) << 8)) | ||
| 40 | #define MXC_ICONFB1(x) (0x14 + ((x) << 8)) | ||
| 41 | #define MXC_ICONFB2(x) (0x18 + ((x) << 8)) | ||
| 42 | #define MXC_DR(x) (0x1c + ((x) << 8)) | ||
| 43 | #define MXC_GIUS(x) (0x20 + ((x) << 8)) | ||
| 44 | #define MXC_SSR(x) (0x24 + ((x) << 8)) | ||
| 45 | #define MXC_ICR1(x) (0x28 + ((x) << 8)) | ||
| 46 | #define MXC_ICR2(x) (0x2c + ((x) << 8)) | ||
| 47 | #define MXC_IMR(x) (0x30 + ((x) << 8)) | ||
| 48 | #define MXC_ISR(x) (0x34 + ((x) << 8)) | ||
| 49 | #define MXC_GPR(x) (0x38 + ((x) << 8)) | ||
| 50 | #define MXC_SWR(x) (0x3c + ((x) << 8)) | ||
| 51 | #define MXC_PUEN(x) (0x40 + ((x) << 8)) | ||
| 52 | |||
| 53 | #ifdef CONFIG_ARCH_MX1 | ||
| 54 | # define GPIO_PORT_MAX 3 | ||
| 55 | #endif | ||
| 56 | #ifdef CONFIG_ARCH_MX2 | ||
| 57 | # define GPIO_PORT_MAX 5 | ||
| 58 | #endif | ||
| 59 | |||
| 60 | #ifndef GPIO_PORT_MAX | ||
| 61 | # error "GPIO config port count unknown!" | ||
| 62 | #endif | ||
| 63 | |||
| 64 | #define GPIO_PIN_MASK 0x1f | ||
| 65 | |||
| 66 | #define GPIO_PORT_SHIFT 5 | ||
| 67 | #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) | ||
| 68 | |||
| 69 | #define GPIO_PORTA (0 << GPIO_PORT_SHIFT) | ||
| 70 | #define GPIO_PORTB (1 << GPIO_PORT_SHIFT) | ||
| 71 | #define GPIO_PORTC (2 << GPIO_PORT_SHIFT) | ||
| 72 | #define GPIO_PORTD (3 << GPIO_PORT_SHIFT) | ||
| 73 | #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) | ||
| 74 | #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) | ||
| 75 | |||
| 76 | #define GPIO_OUT (1 << 8) | ||
| 77 | #define GPIO_IN (0 << 8) | ||
| 78 | #define GPIO_PUEN (1 << 9) | ||
| 79 | |||
| 80 | #define GPIO_PF (1 << 10) | ||
| 81 | #define GPIO_AF (1 << 11) | ||
| 82 | |||
| 83 | #define GPIO_OCR_SHIFT 12 | ||
| 84 | #define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) | ||
| 85 | #define GPIO_AIN (0 << GPIO_OCR_SHIFT) | ||
| 86 | #define GPIO_BIN (1 << GPIO_OCR_SHIFT) | ||
| 87 | #define GPIO_CIN (2 << GPIO_OCR_SHIFT) | ||
| 88 | #define GPIO_GPIO (3 << GPIO_OCR_SHIFT) | ||
| 89 | |||
| 90 | #define GPIO_AOUT_SHIFT 14 | ||
| 91 | #define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) | ||
| 92 | #define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) | ||
| 93 | #define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) | ||
| 94 | #define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) | ||
| 95 | #define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) | ||
| 96 | |||
| 97 | #define GPIO_BOUT_SHIFT 16 | ||
| 98 | #define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) | ||
| 99 | #define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) | ||
| 100 | #define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) | ||
| 101 | #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) | ||
| 102 | #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) | ||
| 103 | |||
| 104 | extern void mxc_gpio_mode(int gpio_mode); | ||
| 105 | extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, | ||
| 106 | int alloc_mode, const char *label); | ||
| 107 | |||
| 108 | /*-------------------------------------------------------------------------*/ | ||
| 109 | |||
| 110 | /* assignements for GPIO alternate/primary functions */ | ||
| 111 | |||
| 112 | /* FIXME: This list is not completed. The correct directions are | ||
| 113 | * missing on some (many) pins | ||
| 114 | */ | ||
| 115 | #ifdef CONFIG_ARCH_MX1 | ||
| 116 | #define PA0_AIN_SPI2_CLK (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0) | ||
| 117 | #define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) | ||
| 118 | #define PA1_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1) | ||
| 119 | #define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) | ||
| 120 | #define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2) | ||
| 121 | #define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) | ||
| 122 | #define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) | ||
| 123 | #define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) | ||
| 124 | #define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) | ||
| 125 | #define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) | ||
| 126 | #define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) | ||
| 127 | #define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) | ||
| 128 | #define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) | ||
| 129 | #define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) | ||
| 130 | #define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) | ||
| 131 | #define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) | ||
| 132 | #define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) | ||
| 133 | #define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15) | ||
| 134 | #define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16) | ||
| 135 | #define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) | ||
| 136 | #define PA17_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17) | ||
| 137 | #define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) | ||
| 138 | #define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) | ||
| 139 | #define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) | ||
| 140 | #define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) | ||
| 141 | #define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) | ||
| 142 | #define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) | ||
| 143 | #define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) | ||
| 144 | #define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) | ||
| 145 | #define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) | ||
| 146 | #define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) | ||
| 147 | #define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) | ||
| 148 | #define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) | ||
| 149 | #define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) | ||
| 150 | #define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) | ||
| 151 | #define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) | ||
| 152 | #define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) | ||
| 153 | #define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) | ||
| 154 | #define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) | ||
| 155 | #define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) | ||
| 156 | #define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) | ||
| 157 | #define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) | ||
| 158 | #define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) | ||
| 159 | #define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) | ||
| 160 | #define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) | ||
| 161 | #define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) | ||
| 162 | #define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) | ||
| 163 | #define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) | ||
| 164 | #define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) | ||
| 165 | #define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) | ||
| 166 | #define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) | ||
| 167 | #define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) | ||
| 168 | #define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) | ||
| 169 | #define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) | ||
| 170 | #define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) | ||
| 171 | #define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) | ||
| 172 | #define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) | ||
| 173 | #define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_IN | GPIO_AF | 16) | ||
| 174 | #define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17) | ||
| 175 | #define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) | ||
| 176 | #define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) | ||
| 177 | #define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) | ||
| 178 | #define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) | ||
| 179 | #define PB22_PFUSBD_RCV (GPIO_PORTB | GPIO_PF | 22) | ||
| 180 | #define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) | ||
| 181 | #define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) | ||
| 182 | #define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) | ||
| 183 | #define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) | ||
| 184 | #define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) | ||
| 185 | #define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28) | ||
| 186 | #define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 29) | ||
| 187 | #define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30) | ||
| 188 | #define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_IN | GPIO_PF | 31) | ||
| 189 | #define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) | ||
| 190 | #define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) | ||
| 191 | #define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_IN | GPIO_PF | 5) | ||
| 192 | #define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) | ||
| 193 | #define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) | ||
| 194 | #define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) | ||
| 195 | #define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) | ||
| 196 | #define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_IN | GPIO_PF | 10) | ||
| 197 | #define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) | ||
| 198 | #define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 12) | ||
| 199 | #define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) | ||
| 200 | #define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) | ||
| 201 | #define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) | ||
| 202 | #define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) | ||
| 203 | #define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) | ||
| 204 | #define PC24_BIN_UART3_RI (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24) | ||
| 205 | #define PC25_BIN_UART3_DSR (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25) | ||
| 206 | #define PC26_AOUT_UART3_DTR (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26) | ||
| 207 | #define PC27_BIN_UART3_DCD (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27) | ||
| 208 | #define PC28_BIN_UART3_CTS (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28) | ||
| 209 | #define PC29_AOUT_UART3_RTS (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29) | ||
| 210 | #define PC30_BIN_UART3_TX (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30) | ||
| 211 | #define PC31_AOUT_UART3_RX (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) | ||
| 212 | #define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6) | ||
| 213 | #define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) | ||
| 214 | #define PD7_AF_UART2_DTR (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7) | ||
| 215 | #define PD7_AIN_SPI2_SCLK (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7) | ||
| 216 | #define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) | ||
| 217 | #define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8) | ||
| 218 | #define PD8_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8) | ||
| 219 | #define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) | ||
| 220 | #define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9) | ||
| 221 | #define PD9_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9) | ||
| 222 | #define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10) | ||
| 223 | #define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10) | ||
| 224 | #define PD10_AIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10) | ||
| 225 | #define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11) | ||
| 226 | #define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12) | ||
| 227 | #define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13) | ||
| 228 | #define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14) | ||
| 229 | #define PD15_PF_LD0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15) | ||
| 230 | #define PD16_PF_LD1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16) | ||
| 231 | #define PD17_PF_LD2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) | ||
| 232 | #define PD18_PF_LD3 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) | ||
| 233 | #define PD19_PF_LD4 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19) | ||
| 234 | #define PD20_PF_LD5 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20) | ||
| 235 | #define PD21_PF_LD6 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21) | ||
| 236 | #define PD22_PF_LD7 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22) | ||
| 237 | #define PD23_PF_LD8 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23) | ||
| 238 | #define PD24_PF_LD9 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24) | ||
| 239 | #define PD25_PF_LD10 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25) | ||
| 240 | #define PD26_PF_LD11 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26) | ||
| 241 | #define PD27_PF_LD12 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27) | ||
| 242 | #define PD28_PF_LD13 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28) | ||
| 243 | #define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) | ||
| 244 | #define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30) | ||
| 245 | #define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) | ||
| 246 | #define PD31_BIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31) | ||
| 247 | #endif | ||
| 248 | |||
| 249 | #ifdef CONFIG_ARCH_MX2 | ||
| 250 | #define PA5_PF_LSCLK (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5) | ||
| 251 | #define PA6_PF_LD0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6) | ||
| 252 | #define PA7_PF_LD1 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7) | ||
| 253 | #define PA8_PF_LD2 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8) | ||
| 254 | #define PA9_PF_LD3 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9) | ||
| 255 | #define PA10_PF_LD4 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10) | ||
| 256 | #define PA11_PF_LD5 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11) | ||
| 257 | #define PA12_PF_LD6 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12) | ||
| 258 | #define PA13_PF_LD7 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13) | ||
| 259 | #define PA14_PF_LD8 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14) | ||
| 260 | #define PA15_PF_LD9 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15) | ||
| 261 | #define PA16_PF_LD10 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16) | ||
| 262 | #define PA17_PF_LD11 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17) | ||
| 263 | #define PA18_PF_LD12 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18) | ||
| 264 | #define PA19_PF_LD13 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19) | ||
| 265 | #define PA20_PF_LD14 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20) | ||
| 266 | #define PA21_PF_LD15 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21) | ||
| 267 | #define PA22_PF_LD16 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22) | ||
| 268 | #define PA23_PF_LD17 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23) | ||
| 269 | #define PA24_PF_REV (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24) | ||
| 270 | #define PA25_PF_CLS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25) | ||
| 271 | #define PA26_PF_PS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26) | ||
| 272 | #define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27) | ||
| 273 | #define PA28_PF_HSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28) | ||
| 274 | #define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29) | ||
| 275 | #define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30) | ||
| 276 | #define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31) | ||
| 277 | #define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10) | ||
| 278 | #define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10) | ||
| 279 | #define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11) | ||
| 280 | #define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 11) | ||
| 281 | #define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12) | ||
| 282 | #define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12) | ||
| 283 | #define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13) | ||
| 284 | #define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 13) | ||
| 285 | #define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14) | ||
| 286 | #define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15) | ||
| 287 | #define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16) | ||
| 288 | #define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17) | ||
| 289 | #define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18) | ||
| 290 | #define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18) | ||
| 291 | #define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19) | ||
| 292 | #define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 19) | ||
| 293 | #define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20) | ||
| 294 | #define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20) | ||
| 295 | #define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21) | ||
| 296 | #define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 21) | ||
| 297 | #define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 26) | ||
| 298 | #define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28) | ||
| 299 | #define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29) | ||
| 300 | #define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31) | ||
| 301 | #define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5) | ||
| 302 | #define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6) | ||
| 303 | #define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16) | ||
| 304 | #define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17) | ||
| 305 | #define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18) | ||
| 306 | #define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 19) | ||
| 307 | #define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 20) | ||
| 308 | #define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 21) | ||
| 309 | #define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 22) | ||
| 310 | #define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 23) | ||
| 311 | #define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 24) | ||
| 312 | #define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 25) | ||
| 313 | #define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 26) | ||
| 314 | #define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 27) | ||
| 315 | #define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 28) | ||
| 316 | #define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 29) | ||
| 317 | #define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 30) | ||
| 318 | #define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 31) | ||
| 319 | #define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) | ||
| 320 | #define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) | ||
| 321 | #define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) | ||
| 322 | #define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) | ||
| 323 | #define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) | ||
| 324 | #define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) | ||
| 325 | #define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) | ||
| 326 | #define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) | ||
| 327 | #define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) | ||
| 328 | #define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) | ||
| 329 | #define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) | ||
| 330 | #define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) | ||
| 331 | #define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) | ||
| 332 | #define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) | ||
| 333 | #define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) | ||
| 334 | #define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) | ||
| 335 | #define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) | ||
| 336 | #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) | ||
| 337 | #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) | ||
| 338 | #define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25) | ||
| 339 | #define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26) | ||
| 340 | #define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27) | ||
| 341 | #define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28) | ||
| 342 | #define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) | ||
| 343 | #define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30) | ||
| 344 | #define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31) | ||
| 345 | #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) | ||
| 346 | #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) | ||
| 347 | #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) | ||
| 348 | #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) | ||
| 349 | #define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) | ||
| 350 | #define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) | ||
| 351 | #define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) | ||
| 352 | #define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) | ||
| 353 | #define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) | ||
| 354 | #define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) | ||
| 355 | #define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) | ||
| 356 | #define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) | ||
| 357 | #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) | ||
| 358 | #define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18) | ||
| 359 | #define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21) | ||
| 360 | #define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22) | ||
| 361 | #define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23) | ||
| 362 | #endif | ||
| 363 | |||
| 364 | /* decode irq number to use with IMR(x), ISR(x) and friends */ | ||
| 365 | #define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5) | ||
| 366 | |||
| 367 | #define IRQ_GPIOA(x) (MXC_MAX_INT_LINES + x) | ||
| 368 | #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) | ||
| 369 | #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) | ||
| 370 | #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) | ||
| 371 | |||
| 372 | #endif /* _MXC_GPIO_MX1_MX2_H */ | ||
diff --git a/include/asm-arm/arch-mxc/iomux-mx3.h b/include/asm-arm/arch-mxc/iomux-mx3.h deleted file mode 100644 index 7509e7692f08..000000000000 --- a/include/asm-arm/arch-mxc/iomux-mx3.h +++ /dev/null | |||
| @@ -1,501 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __MACH_MX31_IOMUX_H__ | ||
| 21 | #define __MACH_MX31_IOMUX_H__ | ||
| 22 | |||
| 23 | #include <linux/types.h> | ||
| 24 | |||
| 25 | /* | ||
| 26 | * various IOMUX output functions | ||
| 27 | */ | ||
| 28 | |||
| 29 | #define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ | ||
| 30 | #define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ | ||
| 31 | #define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ | ||
| 32 | #define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ | ||
| 33 | #define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ | ||
| 34 | #define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ | ||
| 35 | #define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ | ||
| 36 | #define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ | ||
| 37 | #define IOMUX_ICONFIG_NONE 0 /* not configured for input */ | ||
| 38 | #define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ | ||
| 39 | #define IOMUX_ICONFIG_FUNC 2 /* used as function */ | ||
| 40 | #define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ | ||
| 41 | #define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ | ||
| 42 | |||
| 43 | #define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) | ||
| 44 | #define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) | ||
| 45 | #define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) | ||
| 46 | #define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) | ||
| 47 | |||
| 48 | /* | ||
| 49 | * various IOMUX pad functions | ||
| 50 | */ | ||
| 51 | enum iomux_pad_config { | ||
| 52 | PAD_CTL_NOLOOPBACK = 0x0 << 9, | ||
| 53 | PAD_CTL_LOOPBACK = 0x1 << 9, | ||
| 54 | PAD_CTL_PKE_NONE = 0x0 << 8, | ||
| 55 | PAD_CTL_PKE_ENABLE = 0x1 << 8, | ||
| 56 | PAD_CTL_PUE_KEEPER = 0x0 << 7, | ||
| 57 | PAD_CTL_PUE_PUD = 0x1 << 7, | ||
| 58 | PAD_CTL_100K_PD = 0x0 << 5, | ||
| 59 | PAD_CTL_100K_PU = 0x1 << 5, | ||
| 60 | PAD_CTL_47K_PU = 0x2 << 5, | ||
| 61 | PAD_CTL_22K_PU = 0x3 << 5, | ||
| 62 | PAD_CTL_HYS_CMOS = 0x0 << 4, | ||
| 63 | PAD_CTL_HYS_SCHMITZ = 0x1 << 4, | ||
| 64 | PAD_CTL_ODE_CMOS = 0x0 << 3, | ||
| 65 | PAD_CTL_ODE_OpenDrain = 0x1 << 3, | ||
| 66 | PAD_CTL_DRV_NORMAL = 0x0 << 1, | ||
| 67 | PAD_CTL_DRV_HIGH = 0x1 << 1, | ||
| 68 | PAD_CTL_DRV_MAX = 0x2 << 1, | ||
| 69 | PAD_CTL_SRE_SLOW = 0x0 << 0, | ||
| 70 | PAD_CTL_SRE_FAST = 0x1 << 0 | ||
| 71 | }; | ||
| 72 | |||
| 73 | /* | ||
| 74 | * various IOMUX general purpose functions | ||
| 75 | */ | ||
| 76 | enum iomux_gp_func { | ||
| 77 | MUX_PGP_FIRI = 1 << 0, | ||
| 78 | MUX_DDR_MODE = 1 << 1, | ||
| 79 | MUX_PGP_CSPI_BB = 1 << 2, | ||
| 80 | MUX_PGP_ATA_1 = 1 << 3, | ||
| 81 | MUX_PGP_ATA_2 = 1 << 4, | ||
| 82 | MUX_PGP_ATA_3 = 1 << 5, | ||
| 83 | MUX_PGP_ATA_4 = 1 << 6, | ||
| 84 | MUX_PGP_ATA_5 = 1 << 7, | ||
| 85 | MUX_PGP_ATA_6 = 1 << 8, | ||
| 86 | MUX_PGP_ATA_7 = 1 << 9, | ||
| 87 | MUX_PGP_ATA_8 = 1 << 10, | ||
| 88 | MUX_PGP_UH2 = 1 << 11, | ||
| 89 | MUX_SDCTL_CSD0_SEL = 1 << 12, | ||
| 90 | MUX_SDCTL_CSD1_SEL = 1 << 13, | ||
| 91 | MUX_CSPI1_UART3 = 1 << 14, | ||
| 92 | MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, | ||
| 93 | MUX_TAMPER_DETECT_EN = 1 << 16, | ||
| 94 | MUX_PGP_USB_4WIRE = 1 << 17, | ||
| 95 | MUX_PGB_USB_COMMON = 1 << 18, | ||
| 96 | MUX_SDHC_MEMSTICK1 = 1 << 19, | ||
| 97 | MUX_SDHC_MEMSTICK2 = 1 << 20, | ||
| 98 | MUX_PGP_SPLL_BYP = 1 << 21, | ||
| 99 | MUX_PGP_UPLL_BYP = 1 << 22, | ||
| 100 | MUX_PGP_MSHC1_CLK_SEL = 1 << 23, | ||
| 101 | MUX_PGP_MSHC2_CLK_SEL = 1 << 24, | ||
| 102 | MUX_CSPI3_UART5_SEL = 1 << 25, | ||
| 103 | MUX_PGP_ATA_9 = 1 << 26, | ||
| 104 | MUX_PGP_USB_SUSPEND = 1 << 27, | ||
| 105 | MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, | ||
| 106 | MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, | ||
| 107 | MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, | ||
| 108 | MUX_CLKO_DDR_MODE = 1 << 31, | ||
| 109 | }; | ||
| 110 | |||
| 111 | /* | ||
| 112 | * This function enables/disables the general purpose function for a particular | ||
| 113 | * signal. | ||
| 114 | */ | ||
| 115 | void iomux_config_gpr(enum iomux_gp_func , bool); | ||
| 116 | |||
| 117 | /* | ||
| 118 | * set the mode for a IOMUX pin. | ||
| 119 | */ | ||
| 120 | int mxc_iomux_mode(unsigned int); | ||
| 121 | |||
| 122 | /* | ||
| 123 | * This function enables/disables the general purpose function for a particular | ||
| 124 | * signal. | ||
| 125 | */ | ||
| 126 | void mxc_iomux_set_gpr(enum iomux_gp_func, bool); | ||
| 127 | |||
| 128 | #define IOMUX_PADNUM_MASK 0x1ff | ||
| 129 | #define IOMUX_GPIONUM_SHIFT 9 | ||
| 130 | #define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) | ||
| 131 | #define IOMUX_MODE_SHIFT 17 | ||
| 132 | #define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT) | ||
| 133 | |||
| 134 | #define IOMUX_PIN(gpionum, padnum) \ | ||
| 135 | (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \ | ||
| 136 | (padnum & IOMUX_PADNUM_MASK)) | ||
| 137 | |||
| 138 | #define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT) | ||
| 139 | |||
| 140 | #define IOMUX_TO_GPIO(iomux_pin) \ | ||
| 141 | ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) | ||
| 142 | #define IOMUX_TO_IRQ(iomux_pin) \ | ||
| 143 | (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ | ||
| 144 | MXC_GPIO_INT_BASE) | ||
| 145 | |||
| 146 | /* | ||
| 147 | * This enumeration is constructed based on the Section | ||
| 148 | * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated | ||
| 149 | * value is constructed based on the rules described above. | ||
| 150 | */ | ||
| 151 | |||
| 152 | enum iomux_pins { | ||
| 153 | MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), | ||
| 154 | MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), | ||
| 155 | MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), | ||
| 156 | MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), | ||
| 157 | MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), | ||
| 158 | MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), | ||
| 159 | MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), | ||
| 160 | MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), | ||
| 161 | MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), | ||
| 162 | MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), | ||
| 163 | MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), | ||
| 164 | MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), | ||
| 165 | MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), | ||
| 166 | MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), | ||
| 167 | MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), | ||
| 168 | MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), | ||
| 169 | MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), | ||
| 170 | MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), | ||
| 171 | MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), | ||
| 172 | MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), | ||
| 173 | MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), | ||
| 174 | MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), | ||
| 175 | MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), | ||
| 176 | MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), | ||
| 177 | MX31_PIN_READ = IOMUX_PIN(0xff, 24), | ||
| 178 | MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), | ||
| 179 | MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), | ||
| 180 | MX31_PIN_SER_RS = IOMUX_PIN(89, 27), | ||
| 181 | MX31_PIN_LCS1 = IOMUX_PIN(88, 28), | ||
| 182 | MX31_PIN_LCS0 = IOMUX_PIN(87, 29), | ||
| 183 | MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), | ||
| 184 | MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), | ||
| 185 | MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), | ||
| 186 | MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), | ||
| 187 | MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), | ||
| 188 | MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), | ||
| 189 | MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), | ||
| 190 | MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), | ||
| 191 | MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), | ||
| 192 | MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), | ||
| 193 | MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), | ||
| 194 | MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), | ||
| 195 | MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), | ||
| 196 | MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), | ||
| 197 | MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), | ||
| 198 | MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), | ||
| 199 | MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), | ||
| 200 | MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), | ||
| 201 | MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), | ||
| 202 | MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), | ||
| 203 | MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), | ||
| 204 | MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), | ||
| 205 | MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), | ||
| 206 | MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), | ||
| 207 | MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), | ||
| 208 | MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), | ||
| 209 | MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), | ||
| 210 | MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), | ||
| 211 | MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), | ||
| 212 | MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), | ||
| 213 | MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), | ||
| 214 | MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), | ||
| 215 | MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), | ||
| 216 | MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), | ||
| 217 | MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), | ||
| 218 | MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), | ||
| 219 | MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), | ||
| 220 | MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), | ||
| 221 | MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), | ||
| 222 | MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), | ||
| 223 | MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), | ||
| 224 | MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), | ||
| 225 | MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), | ||
| 226 | MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), | ||
| 227 | MX31_PIN_USB_OC = IOMUX_PIN(30, 74), | ||
| 228 | MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), | ||
| 229 | MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), | ||
| 230 | MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), | ||
| 231 | MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), | ||
| 232 | MX31_PIN_TDO = IOMUX_PIN(0xff, 79), | ||
| 233 | MX31_PIN_TDI = IOMUX_PIN(0xff, 80), | ||
| 234 | MX31_PIN_TMS = IOMUX_PIN(0xff, 81), | ||
| 235 | MX31_PIN_TCK = IOMUX_PIN(0xff, 82), | ||
| 236 | MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), | ||
| 237 | MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), | ||
| 238 | MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), | ||
| 239 | MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), | ||
| 240 | MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), | ||
| 241 | MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), | ||
| 242 | MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), | ||
| 243 | MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), | ||
| 244 | MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), | ||
| 245 | MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), | ||
| 246 | MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), | ||
| 247 | MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), | ||
| 248 | MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), | ||
| 249 | MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), | ||
| 250 | MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), | ||
| 251 | MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), | ||
| 252 | MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), | ||
| 253 | MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), | ||
| 254 | MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), | ||
| 255 | MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), | ||
| 256 | MX31_PIN_TXD2 = IOMUX_PIN(28, 103), | ||
| 257 | MX31_PIN_RXD2 = IOMUX_PIN(27, 104), | ||
| 258 | MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), | ||
| 259 | MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), | ||
| 260 | MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), | ||
| 261 | MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), | ||
| 262 | MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), | ||
| 263 | MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), | ||
| 264 | MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), | ||
| 265 | MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), | ||
| 266 | MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), | ||
| 267 | MX31_PIN_CTS1 = IOMUX_PIN(39, 114), | ||
| 268 | MX31_PIN_RTS1 = IOMUX_PIN(38, 115), | ||
| 269 | MX31_PIN_TXD1 = IOMUX_PIN(37, 116), | ||
| 270 | MX31_PIN_RXD1 = IOMUX_PIN(36, 117), | ||
| 271 | MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), | ||
| 272 | MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), | ||
| 273 | MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), | ||
| 274 | MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), | ||
| 275 | MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), | ||
| 276 | MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), | ||
| 277 | MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), | ||
| 278 | MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), | ||
| 279 | MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), | ||
| 280 | MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), | ||
| 281 | MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), | ||
| 282 | MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), | ||
| 283 | MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), | ||
| 284 | MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), | ||
| 285 | MX31_PIN_SFS6 = IOMUX_PIN(26, 132), | ||
| 286 | MX31_PIN_SCK6 = IOMUX_PIN(25, 133), | ||
| 287 | MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), | ||
| 288 | MX31_PIN_STXD6 = IOMUX_PIN(23, 135), | ||
| 289 | MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), | ||
| 290 | MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), | ||
| 291 | MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), | ||
| 292 | MX31_PIN_STXD5 = IOMUX_PIN(21, 139), | ||
| 293 | MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), | ||
| 294 | MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), | ||
| 295 | MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), | ||
| 296 | MX31_PIN_STXD4 = IOMUX_PIN(19, 143), | ||
| 297 | MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), | ||
| 298 | MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), | ||
| 299 | MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), | ||
| 300 | MX31_PIN_STXD3 = IOMUX_PIN(17, 147), | ||
| 301 | MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), | ||
| 302 | MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), | ||
| 303 | MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), | ||
| 304 | MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), | ||
| 305 | MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), | ||
| 306 | MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), | ||
| 307 | MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), | ||
| 308 | MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), | ||
| 309 | MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), | ||
| 310 | MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), | ||
| 311 | MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), | ||
| 312 | MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), | ||
| 313 | MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), | ||
| 314 | MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), | ||
| 315 | MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), | ||
| 316 | MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), | ||
| 317 | MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), | ||
| 318 | MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), | ||
| 319 | MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), | ||
| 320 | MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), | ||
| 321 | MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), | ||
| 322 | MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), | ||
| 323 | MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), | ||
| 324 | MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), | ||
| 325 | MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), | ||
| 326 | MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), | ||
| 327 | MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), | ||
| 328 | MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), | ||
| 329 | MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), | ||
| 330 | MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), | ||
| 331 | MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), | ||
| 332 | MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), | ||
| 333 | MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), | ||
| 334 | MX31_PIN_D0 = IOMUX_PIN(0xff, 181), | ||
| 335 | MX31_PIN_D1 = IOMUX_PIN(0xff, 182), | ||
| 336 | MX31_PIN_D2 = IOMUX_PIN(0xff, 183), | ||
| 337 | MX31_PIN_D3 = IOMUX_PIN(0xff, 184), | ||
| 338 | MX31_PIN_D4 = IOMUX_PIN(0xff, 185), | ||
| 339 | MX31_PIN_D5 = IOMUX_PIN(0xff, 186), | ||
| 340 | MX31_PIN_D6 = IOMUX_PIN(0xff, 187), | ||
| 341 | MX31_PIN_D7 = IOMUX_PIN(0xff, 188), | ||
| 342 | MX31_PIN_D8 = IOMUX_PIN(0xff, 189), | ||
| 343 | MX31_PIN_D9 = IOMUX_PIN(0xff, 190), | ||
| 344 | MX31_PIN_D10 = IOMUX_PIN(0xff, 191), | ||
| 345 | MX31_PIN_D11 = IOMUX_PIN(0xff, 192), | ||
| 346 | MX31_PIN_D12 = IOMUX_PIN(0xff, 193), | ||
| 347 | MX31_PIN_D13 = IOMUX_PIN(0xff, 194), | ||
| 348 | MX31_PIN_D14 = IOMUX_PIN(0xff, 195), | ||
| 349 | MX31_PIN_D15 = IOMUX_PIN(0xff, 196), | ||
| 350 | MX31_PIN_NFRB = IOMUX_PIN(16, 197), | ||
| 351 | MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), | ||
| 352 | MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), | ||
| 353 | MX31_PIN_NFCLE = IOMUX_PIN(13, 200), | ||
| 354 | MX31_PIN_NFALE = IOMUX_PIN(12, 201), | ||
| 355 | MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), | ||
| 356 | MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), | ||
| 357 | MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), | ||
| 358 | MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), | ||
| 359 | MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), | ||
| 360 | MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), | ||
| 361 | MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), | ||
| 362 | MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), | ||
| 363 | MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), | ||
| 364 | MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), | ||
| 365 | MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), | ||
| 366 | MX31_PIN_CAS = IOMUX_PIN(0xff, 213), | ||
| 367 | MX31_PIN_RAS = IOMUX_PIN(0xff, 214), | ||
| 368 | MX31_PIN_RW = IOMUX_PIN(0xff, 215), | ||
| 369 | MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), | ||
| 370 | MX31_PIN_LBA = IOMUX_PIN(0xff, 217), | ||
| 371 | MX31_PIN_ECB = IOMUX_PIN(0xff, 218), | ||
| 372 | MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), | ||
| 373 | MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), | ||
| 374 | MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), | ||
| 375 | MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), | ||
| 376 | MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), | ||
| 377 | MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), | ||
| 378 | MX31_PIN_OE = IOMUX_PIN(0xff, 225), | ||
| 379 | MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), | ||
| 380 | MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), | ||
| 381 | MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), | ||
| 382 | MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), | ||
| 383 | MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), | ||
| 384 | MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), | ||
| 385 | MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), | ||
| 386 | MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), | ||
| 387 | MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), | ||
| 388 | MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), | ||
| 389 | MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), | ||
| 390 | MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), | ||
| 391 | MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), | ||
| 392 | MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), | ||
| 393 | MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), | ||
| 394 | MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), | ||
| 395 | MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), | ||
| 396 | MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), | ||
| 397 | MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), | ||
| 398 | MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), | ||
| 399 | MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), | ||
| 400 | MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), | ||
| 401 | MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), | ||
| 402 | MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), | ||
| 403 | MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), | ||
| 404 | MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), | ||
| 405 | MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), | ||
| 406 | MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), | ||
| 407 | MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), | ||
| 408 | MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), | ||
| 409 | MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), | ||
| 410 | MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), | ||
| 411 | MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), | ||
| 412 | MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), | ||
| 413 | MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), | ||
| 414 | MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), | ||
| 415 | MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), | ||
| 416 | MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), | ||
| 417 | MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), | ||
| 418 | MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), | ||
| 419 | MX31_PIN_A25 = IOMUX_PIN(0xff, 266), | ||
| 420 | MX31_PIN_A24 = IOMUX_PIN(0xff, 267), | ||
| 421 | MX31_PIN_A23 = IOMUX_PIN(0xff, 268), | ||
| 422 | MX31_PIN_A22 = IOMUX_PIN(0xff, 269), | ||
| 423 | MX31_PIN_A21 = IOMUX_PIN(0xff, 270), | ||
| 424 | MX31_PIN_A20 = IOMUX_PIN(0xff, 271), | ||
| 425 | MX31_PIN_A19 = IOMUX_PIN(0xff, 272), | ||
| 426 | MX31_PIN_A18 = IOMUX_PIN(0xff, 273), | ||
| 427 | MX31_PIN_A17 = IOMUX_PIN(0xff, 274), | ||
| 428 | MX31_PIN_A16 = IOMUX_PIN(0xff, 275), | ||
| 429 | MX31_PIN_A14 = IOMUX_PIN(0xff, 276), | ||
| 430 | MX31_PIN_A15 = IOMUX_PIN(0xff, 277), | ||
| 431 | MX31_PIN_A13 = IOMUX_PIN(0xff, 278), | ||
| 432 | MX31_PIN_A12 = IOMUX_PIN(0xff, 279), | ||
| 433 | MX31_PIN_A11 = IOMUX_PIN(0xff, 280), | ||
| 434 | MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), | ||
| 435 | MX31_PIN_A10 = IOMUX_PIN(0xff, 282), | ||
| 436 | MX31_PIN_A9 = IOMUX_PIN(0xff, 283), | ||
| 437 | MX31_PIN_A8 = IOMUX_PIN(0xff, 284), | ||
| 438 | MX31_PIN_A7 = IOMUX_PIN(0xff, 285), | ||
| 439 | MX31_PIN_A6 = IOMUX_PIN(0xff, 286), | ||
| 440 | MX31_PIN_A5 = IOMUX_PIN(0xff, 287), | ||
| 441 | MX31_PIN_A4 = IOMUX_PIN(0xff, 288), | ||
| 442 | MX31_PIN_A3 = IOMUX_PIN(0xff, 289), | ||
| 443 | MX31_PIN_A2 = IOMUX_PIN(0xff, 290), | ||
| 444 | MX31_PIN_A1 = IOMUX_PIN(0xff, 291), | ||
| 445 | MX31_PIN_A0 = IOMUX_PIN(0xff, 292), | ||
| 446 | MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), | ||
| 447 | MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), | ||
| 448 | MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), | ||
| 449 | MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), | ||
| 450 | MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), | ||
| 451 | MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), | ||
| 452 | MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), | ||
| 453 | MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), | ||
| 454 | MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), | ||
| 455 | MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), | ||
| 456 | MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), | ||
| 457 | MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), | ||
| 458 | MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), | ||
| 459 | MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), | ||
| 460 | MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), | ||
| 461 | MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), | ||
| 462 | MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), | ||
| 463 | MX31_PIN_SRX0 = IOMUX_PIN(34, 310), | ||
| 464 | MX31_PIN_STX0 = IOMUX_PIN(33, 311), | ||
| 465 | MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), | ||
| 466 | MX31_PIN_SRST0 = IOMUX_PIN(67, 313), | ||
| 467 | MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), | ||
| 468 | MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), | ||
| 469 | MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), | ||
| 470 | MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317), | ||
| 471 | MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318), | ||
| 472 | MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319), | ||
| 473 | MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320), | ||
| 474 | MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321), | ||
| 475 | MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322), | ||
| 476 | MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323), | ||
| 477 | MX31_PIN_PWMO = IOMUX_PIN( 9, 324), | ||
| 478 | MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), | ||
| 479 | MX31_PIN_COMPARE = IOMUX_PIN( 8, 326), | ||
| 480 | MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), | ||
| 481 | }; | ||
| 482 | |||
| 483 | /* | ||
| 484 | * Convenience values for use with mxc_iomux_mode() | ||
| 485 | * | ||
| 486 | * Format here is MX31_PIN_(pin name)__(function) | ||
| 487 | */ | ||
| 488 | #define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1) | ||
| 489 | #define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1) | ||
| 490 | #define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) | ||
| 491 | #define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) | ||
| 492 | #define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) | ||
| 493 | #define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) | ||
| 494 | |||
| 495 | /* | ||
| 496 | * This function configures the pad value for a IOMUX pin. | ||
| 497 | */ | ||
| 498 | void mxc_iomux_set_pad(enum iomux_pins, u32); | ||
| 499 | |||
| 500 | #endif | ||
| 501 | |||
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h deleted file mode 100644 index 21411efc10fb..000000000000 --- a/include/asm-arm/arch-mxc/irqs.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_IRQS_H__ | ||
| 12 | #define __ASM_ARCH_MXC_IRQS_H__ | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | #endif /* __ASM_ARCH_MXC_IRQS_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h deleted file mode 100644 index 7e669ee0d634..000000000000 --- a/include/asm-arm/arch-mxc/memory.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_MEMORY_H__ | ||
| 12 | #define __ASM_ARCH_MXC_MEMORY_H__ | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Virtual view <-> DMA view memory address translations | ||
| 18 | * This macro is used to translate the virtual address to an address | ||
| 19 | * suitable to be passed to set_dma_addr() | ||
| 20 | */ | ||
| 21 | #define __virt_to_bus(a) __virt_to_phys(a) | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Used to convert an address for DMA operations to an address that the | ||
| 25 | * kernel can use. | ||
| 26 | */ | ||
| 27 | #define __bus_to_virt(a) __phys_to_virt(a) | ||
| 28 | |||
| 29 | #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/mx27.h b/include/asm-arm/arch-mxc/mx27.h deleted file mode 100644 index 212ecc246626..000000000000 --- a/include/asm-arm/arch-mxc/mx27.h +++ /dev/null | |||
| @@ -1,302 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_MXC_MX27_H__ | ||
| 21 | #define __ASM_ARCH_MXC_MX27_H__ | ||
| 22 | |||
| 23 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 24 | #error "Do not include directly." | ||
| 25 | #endif | ||
| 26 | |||
| 27 | /* IRAM */ | ||
| 28 | #define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ | ||
| 29 | |||
| 30 | /* Register offests */ | ||
| 31 | #define AIPI_BASE_ADDR 0x10000000 | ||
| 32 | #define AIPI_BASE_ADDR_VIRT 0xF4000000 | ||
| 33 | #define AIPI_SIZE SZ_1M | ||
| 34 | |||
| 35 | #define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) | ||
| 36 | #define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) | ||
| 37 | #define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) | ||
| 38 | #define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) | ||
| 39 | #define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) | ||
| 40 | #define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) | ||
| 41 | #define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) | ||
| 42 | #define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) | ||
| 43 | #define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) | ||
| 44 | #define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) | ||
| 45 | #define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) | ||
| 46 | #define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) | ||
| 47 | #define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) | ||
| 48 | #define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) | ||
| 49 | #define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) | ||
| 50 | #define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) | ||
| 51 | #define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) | ||
| 52 | #define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) | ||
| 53 | #define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) | ||
| 54 | #define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) | ||
| 55 | #define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) | ||
| 56 | #define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) | ||
| 57 | |||
| 58 | #define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) | ||
| 59 | #define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) | ||
| 60 | #define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) | ||
| 61 | #define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) | ||
| 62 | #define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000) | ||
| 63 | #define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000) | ||
| 64 | #define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) | ||
| 65 | #define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) | ||
| 66 | #define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) | ||
| 67 | |||
| 68 | #define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) | ||
| 69 | #define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) | ||
| 70 | #define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) | ||
| 71 | #define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) | ||
| 72 | /* for mx27*/ | ||
| 73 | #define OTG_BASE_ADDR USBOTG_BASE_ADDR | ||
| 74 | #define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) | ||
| 75 | #define EMMA_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) | ||
| 76 | #define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) | ||
| 77 | #define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) | ||
| 78 | #define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) | ||
| 79 | |||
| 80 | #define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) | ||
| 81 | #define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) | ||
| 82 | #define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) | ||
| 83 | #define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) | ||
| 84 | #define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) | ||
| 85 | |||
| 86 | #define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) | ||
| 87 | #define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) | ||
| 88 | |||
| 89 | /* ROMP and AVIC */ | ||
| 90 | #define ROMP_BASE_ADDR 0x10041000 | ||
| 91 | |||
| 92 | #define AVIC_BASE_ADDR 0x10040000 | ||
| 93 | |||
| 94 | #define SAHB1_BASE_ADDR 0x80000000 | ||
| 95 | #define SAHB1_BASE_ADDR_VIRT 0xF4100000 | ||
| 96 | #define SAHB1_SIZE SZ_1M | ||
| 97 | |||
| 98 | #define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000) | ||
| 99 | #define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) | ||
| 100 | |||
| 101 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ | ||
| 102 | #define X_MEMC_BASE_ADDR 0xD8000000 | ||
| 103 | #define X_MEMC_BASE_ADDR_VIRT 0xF4200000 | ||
| 104 | #define X_MEMC_SIZE SZ_1M | ||
| 105 | |||
| 106 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR) | ||
| 107 | #define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | ||
| 108 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 109 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 110 | #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 111 | |||
| 112 | /* Memory regions and CS */ | ||
| 113 | #define SDRAM_BASE_ADDR 0xA0000000 | ||
| 114 | #define CSD1_BASE_ADDR 0xB0000000 | ||
| 115 | |||
| 116 | #define CS0_BASE_ADDR 0xC0000000 | ||
| 117 | #define CS1_BASE_ADDR 0xC8000000 | ||
| 118 | #define CS2_BASE_ADDR 0xD0000000 | ||
| 119 | #define CS3_BASE_ADDR 0xD2000000 | ||
| 120 | #define CS4_BASE_ADDR 0xD4000000 | ||
| 121 | #define CS5_BASE_ADDR 0xD6000000 | ||
| 122 | #define PCMCIA_MEM_BASE_ADDR 0xDC000000 | ||
| 123 | |||
| 124 | /* | ||
| 125 | * This macro defines the physical to virtual address mapping for all the | ||
| 126 | * peripheral modules. It is used by passing in the physical address as x | ||
| 127 | * and returning the virtual address. If the physical address is not mapped, | ||
| 128 | * it returns 0xDEADBEEF | ||
| 129 | */ | ||
| 130 | #define IO_ADDRESS(x) \ | ||
| 131 | (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ | ||
| 132 | AIPI_IO_ADDRESS(x) : \ | ||
| 133 | ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ | ||
| 134 | SAHB1_IO_ADDRESS(x) : \ | ||
| 135 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ | ||
| 136 | X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) | ||
| 137 | |||
| 138 | /* define the address mapping macros: in physical address order */ | ||
| 139 | #define AIPI_IO_ADDRESS(x) \ | ||
| 140 | (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) | ||
| 141 | |||
| 142 | #define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) | ||
| 143 | |||
| 144 | #define SAHB1_IO_ADDRESS(x) \ | ||
| 145 | (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) | ||
| 146 | |||
| 147 | #define CS4_IO_ADDRESS(x) \ | ||
| 148 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 149 | |||
| 150 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 151 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 152 | |||
| 153 | #define PCMCIA_IO_ADDRESS(x) \ | ||
| 154 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 155 | |||
| 156 | /* fixed interrput numbers */ | ||
| 157 | #define MXC_INT_CCM 63 | ||
| 158 | #define MXC_INT_IIM 62 | ||
| 159 | #define MXC_INT_LCDC 61 | ||
| 160 | #define MXC_INT_SLCDC 60 | ||
| 161 | #define MXC_INT_SAHARA 59 | ||
| 162 | #define MXC_INT_SCC_SCM 58 | ||
| 163 | #define MXC_INT_SCC_SMN 57 | ||
| 164 | #define MXC_INT_USB3 56 | ||
| 165 | #define MXC_INT_USB2 55 | ||
| 166 | #define MXC_INT_USB1 54 | ||
| 167 | #define MXC_INT_VPU 53 | ||
| 168 | #define MXC_INT_EMMAPP 52 | ||
| 169 | #define MXC_INT_EMMAPRP 51 | ||
| 170 | #define MXC_INT_FEC 50 | ||
| 171 | #define MXC_INT_UART5 49 | ||
| 172 | #define MXC_INT_UART6 48 | ||
| 173 | #define MXC_INT_DMACH15 47 | ||
| 174 | #define MXC_INT_DMACH14 46 | ||
| 175 | #define MXC_INT_DMACH13 45 | ||
| 176 | #define MXC_INT_DMACH12 44 | ||
| 177 | #define MXC_INT_DMACH11 43 | ||
| 178 | #define MXC_INT_DMACH10 42 | ||
| 179 | #define MXC_INT_DMACH9 41 | ||
| 180 | #define MXC_INT_DMACH8 40 | ||
| 181 | #define MXC_INT_DMACH7 39 | ||
| 182 | #define MXC_INT_DMACH6 38 | ||
| 183 | #define MXC_INT_DMACH5 37 | ||
| 184 | #define MXC_INT_DMACH4 36 | ||
| 185 | #define MXC_INT_DMACH3 35 | ||
| 186 | #define MXC_INT_DMACH2 34 | ||
| 187 | #define MXC_INT_DMACH1 33 | ||
| 188 | #define MXC_INT_DMACH0 32 | ||
| 189 | #define MXC_INT_CSI 31 | ||
| 190 | #define MXC_INT_ATA 30 | ||
| 191 | #define MXC_INT_NANDFC 29 | ||
| 192 | #define MXC_INT_PCMCIA 28 | ||
| 193 | #define MXC_INT_WDOG 27 | ||
| 194 | #define MXC_INT_GPT1 26 | ||
| 195 | #define MXC_INT_GPT2 25 | ||
| 196 | #define MXC_INT_GPT3 24 | ||
| 197 | #define MXC_INT_GPT INT_GPT1 | ||
| 198 | #define MXC_INT_PWM 23 | ||
| 199 | #define MXC_INT_RTC 22 | ||
| 200 | #define MXC_INT_KPP 21 | ||
| 201 | #define MXC_INT_UART1 20 | ||
| 202 | #define MXC_INT_UART2 19 | ||
| 203 | #define MXC_INT_UART3 18 | ||
| 204 | #define MXC_INT_UART4 17 | ||
| 205 | #define MXC_INT_CSPI1 16 | ||
| 206 | #define MXC_INT_CSPI2 15 | ||
| 207 | #define MXC_INT_SSI1 14 | ||
| 208 | #define MXC_INT_SSI2 13 | ||
| 209 | #define MXC_INT_I2C 12 | ||
| 210 | #define MXC_INT_SDHC1 11 | ||
| 211 | #define MXC_INT_SDHC2 10 | ||
| 212 | #define MXC_INT_SDHC3 9 | ||
| 213 | #define MXC_INT_GPIO 8 | ||
| 214 | #define MXC_INT_SDHC 7 | ||
| 215 | #define MXC_INT_CSPI3 6 | ||
| 216 | #define MXC_INT_RTIC 5 | ||
| 217 | #define MXC_INT_GPT4 4 | ||
| 218 | #define MXC_INT_GPT5 3 | ||
| 219 | #define MXC_INT_GPT6 2 | ||
| 220 | #define MXC_INT_I2C2 1 | ||
| 221 | |||
| 222 | /* fixed DMA request numbers */ | ||
| 223 | #define DMA_REQ_NFC 37 | ||
| 224 | #define DMA_REQ_SDHC3 36 | ||
| 225 | #define DMA_REQ_UART6_RX 35 | ||
| 226 | #define DMA_REQ_UART6_TX 34 | ||
| 227 | #define DMA_REQ_UART5_RX 33 | ||
| 228 | #define DMA_REQ_UART5_TX 32 | ||
| 229 | #define DMA_REQ_CSI_RX 31 | ||
| 230 | #define DMA_REQ_CSI_STAT 30 | ||
| 231 | #define DMA_REQ_ATA_RCV 29 | ||
| 232 | #define DMA_REQ_ATA_TX 28 | ||
| 233 | #define DMA_REQ_UART1_TX 27 | ||
| 234 | #define DMA_REQ_UART1_RX 26 | ||
| 235 | #define DMA_REQ_UART2_TX 25 | ||
| 236 | #define DMA_REQ_UART2_RX 24 | ||
| 237 | #define DMA_REQ_UART3_TX 23 | ||
| 238 | #define DMA_REQ_UART3_RX 22 | ||
| 239 | #define DMA_REQ_UART4_TX 21 | ||
| 240 | #define DMA_REQ_UART4_RX 20 | ||
| 241 | #define DMA_REQ_CSPI1_TX 19 | ||
| 242 | #define DMA_REQ_CSPI1_RX 18 | ||
| 243 | #define DMA_REQ_CSPI2_TX 17 | ||
| 244 | #define DMA_REQ_CSPI2_RX 16 | ||
| 245 | #define DMA_REQ_SSI1_TX1 15 | ||
| 246 | #define DMA_REQ_SSI1_RX1 14 | ||
| 247 | #define DMA_REQ_SSI1_TX0 13 | ||
| 248 | #define DMA_REQ_SSI1_RX0 12 | ||
| 249 | #define DMA_REQ_SSI2_TX1 11 | ||
| 250 | #define DMA_REQ_SSI2_RX1 10 | ||
| 251 | #define DMA_REQ_SSI2_TX0 9 | ||
| 252 | #define DMA_REQ_SSI2_RX0 8 | ||
| 253 | #define DMA_REQ_SDHC1 7 | ||
| 254 | #define DMA_REQ_SDHC2 6 | ||
| 255 | #define DMA_REQ_MSHC 4 | ||
| 256 | #define DMA_REQ_EXT 3 | ||
| 257 | #define DMA_REQ_CSPI3_TX 2 | ||
| 258 | #define DMA_REQ_CSPI3_RX 1 | ||
| 259 | |||
| 260 | /* silicon revisions specific to i.MX27 */ | ||
| 261 | #define CHIP_REV_1_0 0x00 | ||
| 262 | #define CHIP_REV_2_0 0x01 | ||
| 263 | |||
| 264 | #ifndef __ASSEMBLY__ | ||
| 265 | extern int mx27_revision(void); | ||
| 266 | #endif | ||
| 267 | |||
| 268 | /* gpio and gpio based interrupt handling */ | ||
| 269 | #define GPIO_DR 0x1C | ||
| 270 | #define GPIO_GDIR 0x00 | ||
| 271 | #define GPIO_PSR 0x24 | ||
| 272 | #define GPIO_ICR1 0x28 | ||
| 273 | #define GPIO_ICR2 0x2C | ||
| 274 | #define GPIO_IMR 0x30 | ||
| 275 | #define GPIO_ISR 0x34 | ||
| 276 | #define GPIO_INT_LOW_LEV 0x3 | ||
| 277 | #define GPIO_INT_HIGH_LEV 0x2 | ||
| 278 | #define GPIO_INT_RISE_EDGE 0x0 | ||
| 279 | #define GPIO_INT_FALL_EDGE 0x1 | ||
| 280 | #define GPIO_INT_NONE 0x4 | ||
| 281 | |||
| 282 | /* Mandatory defines used globally */ | ||
| 283 | |||
| 284 | /* this is an i.MX27 CPU */ | ||
| 285 | #define cpu_is_mx27() (1) | ||
| 286 | |||
| 287 | /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ | ||
| 288 | #define ARCH_NR_GPIOS (192 + 16) | ||
| 289 | |||
| 290 | /* OS clock tick rate */ | ||
| 291 | #define CLOCK_TICK_RATE 13300000 | ||
| 292 | |||
| 293 | /* Start of RAM */ | ||
| 294 | #define PHYS_OFFSET SDRAM_BASE_ADDR | ||
| 295 | |||
| 296 | /* max interrupt lines count */ | ||
| 297 | #define NR_IRQS 256 | ||
| 298 | |||
| 299 | /* count of internal interrupt sources */ | ||
| 300 | #define MXC_MAX_INT_LINES 64 | ||
| 301 | |||
| 302 | #endif /* __ASM_ARCH_MXC_MX27_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h deleted file mode 100644 index a7373e4a56cb..000000000000 --- a/include/asm-arm/arch-mxc/mx31.h +++ /dev/null | |||
| @@ -1,384 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_MX31_H__ | ||
| 12 | #define __ASM_ARCH_MXC_MX31_H__ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 15 | #error "Do not include directly." | ||
| 16 | #endif | ||
| 17 | |||
| 18 | /*! | ||
| 19 | * defines the hardware clock tick rate | ||
| 20 | */ | ||
| 21 | #define CLOCK_TICK_RATE 16625000 | ||
| 22 | |||
| 23 | /* | ||
| 24 | * MX31 memory map: | ||
| 25 | * | ||
| 26 | * Virt Phys Size What | ||
| 27 | * --------------------------------------------------------------------------- | ||
| 28 | * F8000000 1FFC0000 16K IRAM | ||
| 29 | * F9000000 30000000 256M L2CC | ||
| 30 | * FC000000 43F00000 1M AIPS 1 | ||
| 31 | * FC100000 50000000 1M SPBA | ||
| 32 | * FC200000 53F00000 1M AIPS 2 | ||
| 33 | * FC500000 60000000 128M ROMPATCH | ||
| 34 | * FC400000 68000000 128M AVIC | ||
| 35 | * 70000000 256M IPU (MAX M2) | ||
| 36 | * 80000000 256M CSD0 SDRAM/DDR | ||
| 37 | * 90000000 256M CSD1 SDRAM/DDR | ||
| 38 | * A0000000 128M CS0 Flash | ||
| 39 | * A8000000 128M CS1 Flash | ||
| 40 | * B0000000 32M CS2 | ||
| 41 | * B2000000 32M CS3 | ||
| 42 | * F4000000 B4000000 32M CS4 | ||
| 43 | * B6000000 32M CS5 | ||
| 44 | * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 45 | * C0000000 64M PCMCIA/CF | ||
| 46 | */ | ||
| 47 | |||
| 48 | #define CS0_BASE_ADDR 0xA0000000 | ||
| 49 | #define CS1_BASE_ADDR 0xA8000000 | ||
| 50 | #define CS2_BASE_ADDR 0xB0000000 | ||
| 51 | #define CS3_BASE_ADDR 0xB2000000 | ||
| 52 | |||
| 53 | #define CS4_BASE_ADDR 0xB4000000 | ||
| 54 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
| 55 | #define CS4_SIZE SZ_32M | ||
| 56 | |||
| 57 | #define CS5_BASE_ADDR 0xB6000000 | ||
| 58 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 | ||
| 59 | |||
| 60 | /* | ||
| 61 | * IRAM | ||
| 62 | */ | ||
| 63 | #define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ | ||
| 64 | #define IRAM_BASE_ADDR_VIRT 0xF8000000 | ||
| 65 | #define IRAM_SIZE SZ_16K | ||
| 66 | |||
| 67 | /* | ||
| 68 | * L2CC | ||
| 69 | */ | ||
| 70 | #define L2CC_BASE_ADDR 0x30000000 | ||
| 71 | #define L2CC_BASE_ADDR_VIRT 0xF9000000 | ||
| 72 | #define L2CC_SIZE SZ_1M | ||
| 73 | |||
| 74 | /* | ||
| 75 | * AIPS 1 | ||
| 76 | */ | ||
| 77 | #define AIPS1_BASE_ADDR 0x43F00000 | ||
| 78 | #define AIPS1_BASE_ADDR_VIRT 0xFC000000 | ||
| 79 | #define AIPS1_SIZE SZ_1M | ||
| 80 | |||
| 81 | #define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000) | ||
| 82 | #define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000) | ||
| 83 | #define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000) | ||
| 84 | #define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000) | ||
| 85 | #define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000) | ||
| 86 | #define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000) | ||
| 87 | #define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) | ||
| 88 | #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) | ||
| 89 | #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) | ||
| 90 | #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) | ||
| 91 | #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) | ||
| 92 | #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) | ||
| 93 | #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) | ||
| 94 | #define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) | ||
| 95 | #define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) | ||
| 96 | #define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) | ||
| 97 | #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) | ||
| 98 | #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) | ||
| 99 | #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) | ||
| 100 | #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) | ||
| 101 | #define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) | ||
| 102 | #define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) | ||
| 103 | |||
| 104 | /* | ||
| 105 | * SPBA global module enabled #0 | ||
| 106 | */ | ||
| 107 | #define SPBA0_BASE_ADDR 0x50000000 | ||
| 108 | #define SPBA0_BASE_ADDR_VIRT 0xFC100000 | ||
| 109 | #define SPBA0_SIZE SZ_1M | ||
| 110 | |||
| 111 | #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) | ||
| 112 | #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) | ||
| 113 | #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) | ||
| 114 | #define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) | ||
| 115 | #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) | ||
| 116 | #define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) | ||
| 117 | #define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) | ||
| 118 | #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) | ||
| 119 | #define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) | ||
| 120 | #define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) | ||
| 121 | #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) | ||
| 122 | |||
| 123 | /* | ||
| 124 | * AIPS 2 | ||
| 125 | */ | ||
| 126 | #define AIPS2_BASE_ADDR 0x53F00000 | ||
| 127 | #define AIPS2_BASE_ADDR_VIRT 0xFC200000 | ||
| 128 | #define AIPS2_SIZE SZ_1M | ||
| 129 | #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) | ||
| 130 | #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) | ||
| 131 | #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) | ||
| 132 | #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) | ||
| 133 | #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) | ||
| 134 | #define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) | ||
| 135 | #define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) | ||
| 136 | #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) | ||
| 137 | #define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) | ||
| 138 | #define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) | ||
| 139 | #define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) | ||
| 140 | #define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) | ||
| 141 | #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) | ||
| 142 | #define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) | ||
| 143 | #define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) | ||
| 144 | #define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) | ||
| 145 | #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) | ||
| 146 | #define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) | ||
| 147 | #define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) | ||
| 148 | #define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) | ||
| 149 | #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) | ||
| 150 | |||
| 151 | /* | ||
| 152 | * ROMP and AVIC | ||
| 153 | */ | ||
| 154 | #define ROMP_BASE_ADDR 0x60000000 | ||
| 155 | #define ROMP_BASE_ADDR_VIRT 0xFC500000 | ||
| 156 | #define ROMP_SIZE SZ_1M | ||
| 157 | |||
| 158 | #define AVIC_BASE_ADDR 0x68000000 | ||
| 159 | #define AVIC_BASE_ADDR_VIRT 0xFC400000 | ||
| 160 | #define AVIC_SIZE SZ_1M | ||
| 161 | |||
| 162 | /* | ||
| 163 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 164 | */ | ||
| 165 | #define X_MEMC_BASE_ADDR 0xB8000000 | ||
| 166 | #define X_MEMC_BASE_ADDR_VIRT 0xFC320000 | ||
| 167 | #define X_MEMC_SIZE SZ_64K | ||
| 168 | |||
| 169 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) | ||
| 170 | #define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | ||
| 171 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 172 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 173 | #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 174 | #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR | ||
| 175 | |||
| 176 | /* | ||
| 177 | * Memory regions and CS | ||
| 178 | */ | ||
| 179 | #define IPU_MEM_BASE_ADDR 0x70000000 | ||
| 180 | #define CSD0_BASE_ADDR 0x80000000 | ||
| 181 | #define CSD1_BASE_ADDR 0x90000000 | ||
| 182 | #define CS0_BASE_ADDR 0xA0000000 | ||
| 183 | #define CS1_BASE_ADDR 0xA8000000 | ||
| 184 | #define CS2_BASE_ADDR 0xB0000000 | ||
| 185 | #define CS3_BASE_ADDR 0xB2000000 | ||
| 186 | |||
| 187 | #define CS4_BASE_ADDR 0xB4000000 | ||
| 188 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
| 189 | #define CS4_SIZE SZ_32M | ||
| 190 | |||
| 191 | #define CS5_BASE_ADDR 0xB6000000 | ||
| 192 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 | ||
| 193 | |||
| 194 | /*! | ||
| 195 | * This macro defines the physical to virtual address mapping for all the | ||
| 196 | * peripheral modules. It is used by passing in the physical address as x | ||
| 197 | * and returning the virtual address. If the physical address is not mapped, | ||
| 198 | * it returns 0xDEADBEEF | ||
| 199 | */ | ||
| 200 | #define IO_ADDRESS(x) \ | ||
| 201 | (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\ | ||
| 202 | ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\ | ||
| 203 | ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ | ||
| 204 | ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ | ||
| 205 | ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ | ||
| 206 | ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ | ||
| 207 | ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ | ||
| 208 | ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ | ||
| 209 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ | ||
| 210 | 0xDEADBEEF) | ||
| 211 | |||
| 212 | /* | ||
| 213 | * define the address mapping macros: in physical address order | ||
| 214 | */ | ||
| 215 | |||
| 216 | #define IRAM_IO_ADDRESS(x) \ | ||
| 217 | (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT) | ||
| 218 | |||
| 219 | #define L2CC_IO_ADDRESS(x) \ | ||
| 220 | (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) | ||
| 221 | |||
| 222 | #define AIPS1_IO_ADDRESS(x) \ | ||
| 223 | (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) | ||
| 224 | |||
| 225 | #define SPBA0_IO_ADDRESS(x) \ | ||
| 226 | (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) | ||
| 227 | |||
| 228 | #define AIPS2_IO_ADDRESS(x) \ | ||
| 229 | (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) | ||
| 230 | |||
| 231 | #define ROMP_IO_ADDRESS(x) \ | ||
| 232 | (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) | ||
| 233 | |||
| 234 | #define AVIC_IO_ADDRESS(x) \ | ||
| 235 | (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) | ||
| 236 | |||
| 237 | #define CS4_IO_ADDRESS(x) \ | ||
| 238 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 239 | |||
| 240 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 241 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 242 | |||
| 243 | #define PCMCIA_IO_ADDRESS(x) \ | ||
| 244 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 245 | |||
| 246 | /* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */ | ||
| 247 | #define PHYS_OFFSET CSD0_BASE_ADDR | ||
| 248 | |||
| 249 | /* | ||
| 250 | * Interrupt numbers | ||
| 251 | */ | ||
| 252 | #define MXC_INT_PEN_ADS7843 0 | ||
| 253 | #define MXC_INT_RESV1 1 | ||
| 254 | #define MXC_INT_CS8900A 2 | ||
| 255 | #define MXC_INT_I2C3 3 | ||
| 256 | #define MXC_INT_I2C2 4 | ||
| 257 | #define MXC_INT_MPEG4_ENCODER 5 | ||
| 258 | #define MXC_INT_RTIC 6 | ||
| 259 | #define MXC_INT_FIRI 7 | ||
| 260 | #define MXC_INT_MMC_SDHC2 8 | ||
| 261 | #define MXC_INT_MMC_SDHC1 9 | ||
| 262 | #define MXC_INT_I2C 10 | ||
| 263 | #define MXC_INT_SSI2 11 | ||
| 264 | #define MXC_INT_SSI1 12 | ||
| 265 | #define MXC_INT_CSPI2 13 | ||
| 266 | #define MXC_INT_CSPI1 14 | ||
| 267 | #define MXC_INT_ATA 15 | ||
| 268 | #define MXC_INT_MBX 16 | ||
| 269 | #define MXC_INT_CSPI3 17 | ||
| 270 | #define MXC_INT_UART3 18 | ||
| 271 | #define MXC_INT_IIM 19 | ||
| 272 | #define MXC_INT_SIM2 20 | ||
| 273 | #define MXC_INT_SIM1 21 | ||
| 274 | #define MXC_INT_RNGA 22 | ||
| 275 | #define MXC_INT_EVTMON 23 | ||
| 276 | #define MXC_INT_KPP 24 | ||
| 277 | #define MXC_INT_RTC 25 | ||
| 278 | #define MXC_INT_PWM 26 | ||
| 279 | #define MXC_INT_EPIT2 27 | ||
| 280 | #define MXC_INT_EPIT1 28 | ||
| 281 | #define MXC_INT_GPT 29 | ||
| 282 | #define MXC_INT_RESV30 30 | ||
| 283 | #define MXC_INT_RESV31 31 | ||
| 284 | #define MXC_INT_UART2 32 | ||
| 285 | #define MXC_INT_NANDFC 33 | ||
| 286 | #define MXC_INT_SDMA 34 | ||
| 287 | #define MXC_INT_USB1 35 | ||
| 288 | #define MXC_INT_USB2 36 | ||
| 289 | #define MXC_INT_USB3 37 | ||
| 290 | #define MXC_INT_USB4 38 | ||
| 291 | #define MXC_INT_MSHC1 39 | ||
| 292 | #define MXC_INT_MSHC2 40 | ||
| 293 | #define MXC_INT_IPU_ERR 41 | ||
| 294 | #define MXC_INT_IPU_SYN 42 | ||
| 295 | #define MXC_INT_RESV43 43 | ||
| 296 | #define MXC_INT_RESV44 44 | ||
| 297 | #define MXC_INT_UART1 45 | ||
| 298 | #define MXC_INT_UART4 46 | ||
| 299 | #define MXC_INT_UART5 47 | ||
| 300 | #define MXC_INT_ECT 48 | ||
| 301 | #define MXC_INT_SCC_SCM 49 | ||
| 302 | #define MXC_INT_SCC_SMN 50 | ||
| 303 | #define MXC_INT_GPIO2 51 | ||
| 304 | #define MXC_INT_GPIO1 52 | ||
| 305 | #define MXC_INT_CCM 53 | ||
| 306 | #define MXC_INT_PCMCIA 54 | ||
| 307 | #define MXC_INT_WDOG 55 | ||
| 308 | #define MXC_INT_GPIO3 56 | ||
| 309 | #define MXC_INT_RESV57 57 | ||
| 310 | #define MXC_INT_EXT_POWER 58 | ||
| 311 | #define MXC_INT_EXT_TEMPER 59 | ||
| 312 | #define MXC_INT_EXT_SENSOR60 60 | ||
| 313 | #define MXC_INT_EXT_SENSOR61 61 | ||
| 314 | #define MXC_INT_EXT_WDOG 62 | ||
| 315 | #define MXC_INT_EXT_TV 63 | ||
| 316 | |||
| 317 | #define MXC_MAX_INT_LINES 64 | ||
| 318 | |||
| 319 | #define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES | ||
| 320 | #define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) | ||
| 321 | #define MXC_MAX_VIRTUAL_INTS 16 | ||
| 322 | |||
| 323 | #define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS) | ||
| 324 | |||
| 325 | /*! | ||
| 326 | * Number of GPIO port as defined in the IC Spec | ||
| 327 | */ | ||
| 328 | #define GPIO_PORT_NUM 3 | ||
| 329 | /*! | ||
| 330 | * Number of GPIO pins per port | ||
| 331 | */ | ||
| 332 | #define GPIO_NUM_PIN 32 | ||
| 333 | |||
| 334 | #define PROD_SIGNATURE 0x1 /* For MX31 */ | ||
| 335 | |||
| 336 | /* silicon revisions specific to i.MX31 */ | ||
| 337 | #define CHIP_REV_1_0 0x10 | ||
| 338 | #define CHIP_REV_1_1 0x11 | ||
| 339 | #define CHIP_REV_1_2 0x12 | ||
| 340 | #define CHIP_REV_1_3 0x13 | ||
| 341 | #define CHIP_REV_2_0 0x20 | ||
| 342 | #define CHIP_REV_2_1 0x21 | ||
| 343 | #define CHIP_REV_2_2 0x22 | ||
| 344 | #define CHIP_REV_2_3 0x23 | ||
| 345 | #define CHIP_REV_3_0 0x30 | ||
| 346 | #define CHIP_REV_3_1 0x31 | ||
| 347 | #define CHIP_REV_3_2 0x32 | ||
| 348 | |||
| 349 | #define SYSTEM_REV_MIN CHIP_REV_1_0 | ||
| 350 | #define SYSTEM_REV_NUM 3 | ||
| 351 | |||
| 352 | /* gpio and gpio based interrupt handling */ | ||
| 353 | #define GPIO_DR 0x00 | ||
| 354 | #define GPIO_GDIR 0x04 | ||
| 355 | #define GPIO_PSR 0x08 | ||
| 356 | #define GPIO_ICR1 0x0C | ||
| 357 | #define GPIO_ICR2 0x10 | ||
| 358 | #define GPIO_IMR 0x14 | ||
| 359 | #define GPIO_ISR 0x18 | ||
| 360 | #define GPIO_INT_LOW_LEV 0x0 | ||
| 361 | #define GPIO_INT_HIGH_LEV 0x1 | ||
| 362 | #define GPIO_INT_RISE_EDGE 0x2 | ||
| 363 | #define GPIO_INT_FALL_EDGE 0x3 | ||
| 364 | #define GPIO_INT_NONE 0x4 | ||
| 365 | |||
| 366 | /* Mandatory defines used globally */ | ||
| 367 | |||
| 368 | /* this CPU supports up to 96 GPIOs */ | ||
| 369 | #define ARCH_NR_GPIOS 96 | ||
| 370 | |||
| 371 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | ||
| 372 | |||
| 373 | /* this is a i.MX31 CPU */ | ||
| 374 | #define cpu_is_mx31() (1) | ||
| 375 | |||
| 376 | extern unsigned int system_rev; | ||
| 377 | |||
| 378 | static inline int mx31_revision(void) | ||
| 379 | { | ||
| 380 | return system_rev; | ||
| 381 | } | ||
| 382 | #endif | ||
| 383 | |||
| 384 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h deleted file mode 100644 index 332eda4dbd3b..000000000000 --- a/include/asm-arm/arch-mxc/mxc.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_MXC_H__ | ||
| 21 | #define __ASM_ARCH_MXC_H__ | ||
| 22 | |||
| 23 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 24 | #error "Do not include directly." | ||
| 25 | #endif | ||
| 26 | |||
| 27 | /* clean up all things that are not used */ | ||
| 28 | #ifndef CONFIG_ARCH_MX3 | ||
| 29 | # define cpu_is_mx31() (0) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef CONFIG_MACH_MX27 | ||
| 33 | # define cpu_is_mx27() (0) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #endif /* __ASM_ARCH_MXC_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/mxc_timer.h b/include/asm-arm/arch-mxc/mxc_timer.h deleted file mode 100644 index 5439fa6cf615..000000000000 --- a/include/asm-arm/arch-mxc/mxc_timer.h +++ /dev/null | |||
| @@ -1,158 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * mxc_timer.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) | ||
| 5 | * | ||
| 6 | * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * as published by the Free Software Foundation; either version 2 | ||
| 11 | * of the License, or (at your option) any later version. | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, | ||
| 20 | * Boston, MA 02110-1301, USA. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __PLAT_MXC_TIMER_H | ||
| 24 | #define __PLAT_MXC_TIMER_H | ||
| 25 | |||
| 26 | #include <linux/clk.h> | ||
| 27 | #include <asm/arch/hardware.h> | ||
| 28 | |||
| 29 | #ifdef CONFIG_ARCH_IMX | ||
| 30 | #define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR) | ||
| 31 | #define TIMER_INTERRUPT TIM1_INT | ||
| 32 | |||
| 33 | #define TCTL_VAL TCTL_CLK_PCLK1 | ||
| 34 | #define TCTL_IRQEN (1<<4) | ||
| 35 | #define TCTL_FRR (1<<8) | ||
| 36 | #define TCTL_CLK_PCLK1 (1<<1) | ||
| 37 | #define TCTL_CLK_PCLK1_4 (2<<1) | ||
| 38 | #define TCTL_CLK_TIN (3<<1) | ||
| 39 | #define TCTL_CLK_32 (4<<1) | ||
| 40 | |||
| 41 | #define MXC_TCTL 0x00 | ||
| 42 | #define MXC_TPRER 0x04 | ||
| 43 | #define MXC_TCMP 0x08 | ||
| 44 | #define MXC_TCR 0x0c | ||
| 45 | #define MXC_TCN 0x10 | ||
| 46 | #define MXC_TSTAT 0x14 | ||
| 47 | #define TSTAT_CAPT (1<<1) | ||
| 48 | #define TSTAT_COMP (1<<0) | ||
| 49 | |||
| 50 | static inline void gpt_irq_disable(void) | ||
| 51 | { | ||
| 52 | unsigned int tmp; | ||
| 53 | |||
| 54 | tmp = __raw_readl(TIMER_BASE + MXC_TCTL); | ||
| 55 | __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL); | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline void gpt_irq_enable(void) | ||
| 59 | { | ||
| 60 | __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN, | ||
| 61 | TIMER_BASE + MXC_TCTL); | ||
| 62 | } | ||
| 63 | |||
| 64 | static void gpt_irq_acknowledge(void) | ||
| 65 | { | ||
| 66 | __raw_writel(0, TIMER_BASE + MXC_TSTAT); | ||
| 67 | } | ||
| 68 | #endif /* CONFIG_ARCH_IMX */ | ||
| 69 | |||
| 70 | #ifdef CONFIG_ARCH_MX2 | ||
| 71 | #define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) | ||
| 72 | #define TIMER_INTERRUPT MXC_INT_GPT1 | ||
| 73 | |||
| 74 | #define MXC_TCTL 0x00 | ||
| 75 | #define TCTL_VAL TCTL_CLK_PCLK1 | ||
| 76 | #define TCTL_CLK_PCLK1 (1<<1) | ||
| 77 | #define TCTL_CLK_PCLK1_4 (2<<1) | ||
| 78 | #define TCTL_IRQEN (1<<4) | ||
| 79 | #define TCTL_FRR (1<<8) | ||
| 80 | #define MXC_TPRER 0x04 | ||
| 81 | #define MXC_TCMP 0x08 | ||
| 82 | #define MXC_TCR 0x0c | ||
| 83 | #define MXC_TCN 0x10 | ||
| 84 | #define MXC_TSTAT 0x14 | ||
| 85 | #define TSTAT_CAPT (1<<1) | ||
| 86 | #define TSTAT_COMP (1<<0) | ||
| 87 | |||
| 88 | static inline void gpt_irq_disable(void) | ||
| 89 | { | ||
| 90 | unsigned int tmp; | ||
| 91 | |||
| 92 | tmp = __raw_readl(TIMER_BASE + MXC_TCTL); | ||
| 93 | __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL); | ||
| 94 | } | ||
| 95 | |||
| 96 | static inline void gpt_irq_enable(void) | ||
| 97 | { | ||
| 98 | __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN, | ||
| 99 | TIMER_BASE + MXC_TCTL); | ||
| 100 | } | ||
| 101 | |||
| 102 | static void gpt_irq_acknowledge(void) | ||
| 103 | { | ||
| 104 | __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT); | ||
| 105 | } | ||
| 106 | #endif /* CONFIG_ARCH_MX2 */ | ||
| 107 | |||
| 108 | #ifdef CONFIG_ARCH_MX3 | ||
| 109 | #define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) | ||
| 110 | #define TIMER_INTERRUPT MXC_INT_GPT | ||
| 111 | |||
| 112 | #define MXC_TCTL 0x00 | ||
| 113 | #define TCTL_VAL (TCTL_CLK_IPG | TCTL_WAITEN) | ||
| 114 | #define TCTL_CLK_IPG (1<<6) | ||
| 115 | #define TCTL_FRR (1<<9) | ||
| 116 | #define TCTL_WAITEN (1<<3) | ||
| 117 | |||
| 118 | #define MXC_TPRER 0x04 | ||
| 119 | #define MXC_TSTAT 0x08 | ||
| 120 | #define TSTAT_OF1 (1<<0) | ||
| 121 | #define TSTAT_OF2 (1<<1) | ||
| 122 | #define TSTAT_OF3 (1<<2) | ||
| 123 | #define TSTAT_IF1 (1<<3) | ||
| 124 | #define TSTAT_IF2 (1<<4) | ||
| 125 | #define TSTAT_ROV (1<<5) | ||
| 126 | #define MXC_IR 0x0c | ||
| 127 | #define MXC_TCMP 0x10 | ||
| 128 | #define MXC_TCMP2 0x14 | ||
| 129 | #define MXC_TCMP3 0x18 | ||
| 130 | #define MXC_TCR 0x1c | ||
| 131 | #define MXC_TCN 0x24 | ||
| 132 | |||
| 133 | static inline void gpt_irq_disable(void) | ||
| 134 | { | ||
| 135 | __raw_writel(0, TIMER_BASE + MXC_IR); | ||
| 136 | } | ||
| 137 | |||
| 138 | static inline void gpt_irq_enable(void) | ||
| 139 | { | ||
| 140 | __raw_writel(1<<0, TIMER_BASE + MXC_IR); | ||
| 141 | } | ||
| 142 | |||
| 143 | static inline void gpt_irq_acknowledge(void) | ||
| 144 | { | ||
| 145 | __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT); | ||
| 146 | } | ||
| 147 | #endif /* CONFIG_ARCH_MX3 */ | ||
| 148 | |||
| 149 | #define TCTL_SWR (1<<15) | ||
| 150 | #define TCTL_CC (1<<10) | ||
| 151 | #define TCTL_OM (1<<9) | ||
| 152 | #define TCTL_CAP_RIS (1<<6) | ||
| 153 | #define TCTL_CAP_FAL (2<<6) | ||
| 154 | #define TCTL_CAP_RIS_FAL (3<<6) | ||
| 155 | #define TCTL_CAP_ENA (1<<5) | ||
| 156 | #define TCTL_TEN (1<<0) | ||
| 157 | |||
| 158 | #endif | ||
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h deleted file mode 100644 index bbfc37465fc5..000000000000 --- a/include/asm-arm/arch-mxc/system.h +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 1999 ARM Limited | ||
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 4 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_MXC_SYSTEM_H__ | ||
| 22 | #define __ASM_ARCH_MXC_SYSTEM_H__ | ||
| 23 | |||
| 24 | static inline void arch_idle(void) | ||
| 25 | { | ||
| 26 | cpu_do_idle(); | ||
| 27 | } | ||
| 28 | |||
| 29 | static inline void arch_reset(char mode) | ||
| 30 | { | ||
| 31 | cpu_reset(0); | ||
| 32 | } | ||
| 33 | |||
| 34 | #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/timex.h b/include/asm-arm/arch-mxc/timex.h deleted file mode 100644 index 432e0c84c509..000000000000 --- a/include/asm-arm/arch-mxc/timex.h +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 1999 ARM Limited | ||
| 3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_MXC_TIMEX_H__ | ||
| 21 | #define __ASM_ARCH_MXC_TIMEX_H__ | ||
| 22 | |||
| 23 | #include <asm/arch/hardware.h> /* for CLOCK_TICK_RATE */ | ||
| 24 | |||
| 25 | #endif /* __ASM_ARCH_MXC_TIMEX_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/uncompress.h b/include/asm-arm/arch-mxc/uncompress.h deleted file mode 100644 index 18f33b0cdeb2..000000000000 --- a/include/asm-arm/arch-mxc/uncompress.h +++ /dev/null | |||
| @@ -1,78 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-mxc/uncompress.h | ||
| 3 | * | ||
| 4 | * | ||
| 5 | * | ||
| 6 | * Copyright (C) 1999 ARM Limited | ||
| 7 | * Copyright (C) Shane Nay (shane@minirl.com) | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 22 | */ | ||
| 23 | #ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ | ||
| 24 | #define __ASM_ARCH_MXC_UNCOMPRESS_H__ | ||
| 25 | |||
| 26 | #define __MXC_BOOT_UNCOMPRESS | ||
| 27 | |||
| 28 | #include <asm/arch/hardware.h> | ||
| 29 | |||
| 30 | #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) | ||
| 31 | |||
| 32 | #define USR2 0x98 | ||
| 33 | #define USR2_TXFE (1<<14) | ||
| 34 | #define TXR 0x40 | ||
| 35 | #define UCR1 0x80 | ||
| 36 | #define UCR1_UARTEN 1 | ||
| 37 | |||
| 38 | /* | ||
| 39 | * The following code assumes the serial port has already been | ||
| 40 | * initialized by the bootloader. We search for the first enabled | ||
| 41 | * port in the most probable order. If you didn't setup a port in | ||
| 42 | * your bootloader then nothing will appear (which might be desired). | ||
| 43 | * | ||
| 44 | * This does not append a newline | ||
| 45 | */ | ||
| 46 | |||
| 47 | static void putc(int ch) | ||
| 48 | { | ||
| 49 | static unsigned long serial_port = 0; | ||
| 50 | |||
| 51 | if (unlikely(serial_port == 0)) { | ||
| 52 | do { | ||
| 53 | serial_port = UART1_BASE_ADDR; | ||
| 54 | if (UART(UCR1) & UCR1_UARTEN) | ||
| 55 | break; | ||
| 56 | serial_port = UART2_BASE_ADDR; | ||
| 57 | if (UART(UCR1) & UCR1_UARTEN) | ||
| 58 | break; | ||
| 59 | return; | ||
| 60 | } while (0); | ||
| 61 | } | ||
| 62 | |||
| 63 | while (!(UART(USR2) & USR2_TXFE)) | ||
| 64 | barrier(); | ||
| 65 | |||
| 66 | UART(TXR) = ch; | ||
| 67 | } | ||
| 68 | |||
| 69 | #define flush() do { } while (0) | ||
| 70 | |||
| 71 | /* | ||
| 72 | * nothing to do | ||
| 73 | */ | ||
| 74 | #define arch_decomp_setup() | ||
| 75 | |||
| 76 | #define arch_decomp_wdog() | ||
| 77 | |||
| 78 | #endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */ | ||
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h deleted file mode 100644 index 62d97623412f..000000000000 --- a/include/asm-arm/arch-mxc/vmalloc.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2000 Russell King. | ||
| 3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_MXC_VMALLOC_H__ | ||
| 21 | #define __ASM_ARCH_MXC_VMALLOC_H__ | ||
| 22 | |||
| 23 | /* vmalloc ending address */ | ||
| 24 | #define VMALLOC_END 0xF4000000 | ||
| 25 | |||
| 26 | #endif /* __ASM_ARCH_MXC_VMALLOC_H__ */ | ||
diff --git a/include/asm-arm/arch-netx/debug-macro.S b/include/asm-arm/arch-netx/debug-macro.S deleted file mode 100644 index a940d0e80cb2..000000000000 --- a/include/asm-arm/arch-netx/debug-macro.S +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-netx/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include "hardware.h" | ||
| 15 | |||
| 16 | .macro addruart,rx | ||
| 17 | mrc p15, 0, \rx, c1, c0 | ||
| 18 | tst \rx, #1 @ MMU enabled? | ||
| 19 | moveq \rx, #0x00100000 @ physical | ||
| 20 | movne \rx, #io_p2v(0x00100000) @ virtual | ||
| 21 | orr \rx, \rx, #0x00000a00 | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro senduart,rd,rx | ||
| 25 | str \rd, [\rx, #0] | ||
| 26 | .endm | ||
| 27 | |||
| 28 | .macro busyuart,rd,rx | ||
| 29 | 1002: ldr \rd, [\rx, #0x18] | ||
| 30 | tst \rd, #(1 << 3) | ||
| 31 | bne 1002b | ||
| 32 | .endm | ||
| 33 | |||
| 34 | .macro waituart,rd,rx | ||
| 35 | 1001: ldr \rd, [\rx, #0x18] | ||
| 36 | tst \rd, #(1 << 3) | ||
| 37 | bne 1001b | ||
| 38 | .endm | ||
diff --git a/include/asm-arm/arch-netx/dma.h b/include/asm-arm/arch-netx/dma.h deleted file mode 100644 index 4eda5feed81c..000000000000 --- a/include/asm-arm/arch-netx/dma.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-netx/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define MAX_DMA_CHANNELS 0 | ||
| 21 | #define MAX_DMA_ADDRESS ~0 | ||
diff --git a/include/asm-arm/arch-netx/entry-macro.S b/include/asm-arm/arch-netx/entry-macro.S deleted file mode 100644 index 4115bbdf97ae..000000000000 --- a/include/asm-arm/arch-netx/entry-macro.S +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-netx/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for Hilscher netX based platforms | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 | ||
| 10 | * as published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #include <asm/arch/hardware.h> | ||
| 22 | |||
| 23 | .macro disable_fiq | ||
| 24 | .endm | ||
| 25 | |||
| 26 | .macro get_irqnr_preamble, base, tmp | ||
| 27 | .endm | ||
| 28 | |||
| 29 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 30 | .endm | ||
| 31 | |||
| 32 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 33 | mov \base, #io_p2v(0x00100000) | ||
| 34 | add \base, \base, #0x000ff000 | ||
| 35 | |||
| 36 | ldr \irqstat, [\base, #0] | ||
| 37 | clz \irqnr, \irqstat | ||
| 38 | rsb \irqnr, \irqnr, #31 | ||
| 39 | cmp \irqstat, #0 | ||
| 40 | .endm | ||
| 41 | |||
diff --git a/include/asm-arm/arch-netx/eth.h b/include/asm-arm/arch-netx/eth.h deleted file mode 100644 index 643c90ef8b72..000000000000 --- a/include/asm-arm/arch-netx/eth.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-netx/eth.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef ASMARM_ARCH_ETH_H | ||
| 21 | #define ASMARM_ARCH_ETH_H | ||
| 22 | |||
| 23 | struct netxeth_platform_data { | ||
| 24 | unsigned int xcno; /* number of xmac/xpec engine this eth uses */ | ||
| 25 | }; | ||
| 26 | |||
| 27 | #endif | ||
diff --git a/include/asm-arm/arch-netx/hardware.h b/include/asm-arm/arch-netx/hardware.h deleted file mode 100644 index 7786c45455cd..000000000000 --- a/include/asm-arm/arch-netx/hardware.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-netx/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 20 | #define __ASM_ARCH_HARDWARE_H | ||
| 21 | |||
| 22 | #define NETX_IO_PHYS 0x00100000 | ||
| 23 | #define NETX_IO_VIRT 0xe0000000 | ||
| 24 | #define NETX_IO_SIZE 0x00100000 | ||
| 25 | |||
| 26 | #define SRAM_INTERNAL_PHYS_0 0x00000 | ||
| 27 | #define SRAM_INTERNAL_PHYS_1 0x08000 | ||
| 28 | #define SRAM_INTERNAL_PHYS_2 0x10000 | ||
| 29 | #define SRAM_INTERNAL_PHYS_3 0x18000 | ||
| 30 | #define SRAM_INTERNAL_PHYS(no) ((no) * 0x8000) | ||
| 31 | |||
| 32 | #define XPEC_MEM_SIZE 0x4000 | ||
| 33 | #define XMAC_MEM_SIZE 0x1000 | ||
| 34 | #define SRAM_MEM_SIZE 0x8000 | ||
| 35 | |||
| 36 | #define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT) | ||
| 37 | #define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS) | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-netx/io.h b/include/asm-arm/arch-netx/io.h deleted file mode 100644 index a7a53f80165d..000000000000 --- a/include/asm-arm/arch-netx/io.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-netx/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 21 | #define __ASM_ARM_ARCH_IO_H | ||
| 22 | |||
| 23 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 24 | |||
| 25 | #define __io(a) ((void __iomem *)(a)) | ||
| 26 | #define __mem_pci(a) (a) | ||
| 27 | |||
| 28 | #endif | ||
diff --git a/include/asm-arm/arch-netx/irqs.h b/include/asm-arm/arch-netx/irqs.h deleted file mode 100644 index a487dc6e2661..000000000000 --- a/include/asm-arm/arch-netx/irqs.h +++ /dev/null | |||
| @@ -1,70 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-netx/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define NETX_IRQ_VIC_START 0 | ||
| 21 | #define NETX_IRQ_SOFTINT 0 | ||
| 22 | #define NETX_IRQ_TIMER0 1 | ||
| 23 | #define NETX_IRQ_TIMER1 2 | ||
| 24 | #define NETX_IRQ_TIMER2 3 | ||
| 25 | #define NETX_IRQ_SYSTIME_NS 4 | ||
| 26 | #define NETX_IRQ_SYSTIME_S 5 | ||
| 27 | #define NETX_IRQ_GPIO_15 6 | ||
| 28 | #define NETX_IRQ_WATCHDOG 7 | ||
| 29 | #define NETX_IRQ_UART0 8 | ||
| 30 | #define NETX_IRQ_UART1 9 | ||
| 31 | #define NETX_IRQ_UART2 10 | ||
| 32 | #define NETX_IRQ_USB 11 | ||
| 33 | #define NETX_IRQ_SPI 12 | ||
| 34 | #define NETX_IRQ_I2C 13 | ||
| 35 | #define NETX_IRQ_LCD 14 | ||
| 36 | #define NETX_IRQ_HIF 15 | ||
| 37 | #define NETX_IRQ_GPIO_0_14 16 | ||
| 38 | #define NETX_IRQ_XPEC0 17 | ||
| 39 | #define NETX_IRQ_XPEC1 18 | ||
| 40 | #define NETX_IRQ_XPEC2 19 | ||
| 41 | #define NETX_IRQ_XPEC3 20 | ||
| 42 | #define NETX_IRQ_XPEC(no) (17 + (no)) | ||
| 43 | #define NETX_IRQ_MSYNC0 21 | ||
| 44 | #define NETX_IRQ_MSYNC1 22 | ||
| 45 | #define NETX_IRQ_MSYNC2 23 | ||
| 46 | #define NETX_IRQ_MSYNC3 24 | ||
| 47 | #define NETX_IRQ_IRQ_PHY 25 | ||
| 48 | #define NETX_IRQ_ISO_AREA 26 | ||
| 49 | /* int 27 is reserved */ | ||
| 50 | /* int 28 is reserved */ | ||
| 51 | #define NETX_IRQ_TIMER3 29 | ||
| 52 | #define NETX_IRQ_TIMER4 30 | ||
| 53 | /* int 31 is reserved */ | ||
| 54 | |||
| 55 | #define NETX_IRQS 32 | ||
| 56 | |||
| 57 | /* for multiplexed irqs on gpio 0..14 */ | ||
| 58 | #define NETX_IRQ_GPIO(x) (NETX_IRQS + (x)) | ||
| 59 | #define NETX_IRQ_GPIO_LAST NETX_IRQ_GPIO(14) | ||
| 60 | |||
| 61 | /* Host interface interrupts */ | ||
| 62 | #define NETX_IRQ_HIF_CHAINED(x) (NETX_IRQ_GPIO_LAST + 1 + (x)) | ||
| 63 | #define NETX_IRQ_HIF_PIO35 NETX_IRQ_HIF_CHAINED(0) | ||
| 64 | #define NETX_IRQ_HIF_PIO36 NETX_IRQ_HIF_CHAINED(1) | ||
| 65 | #define NETX_IRQ_HIF_PIO40 NETX_IRQ_HIF_CHAINED(2) | ||
| 66 | #define NETX_IRQ_HIF_PIO47 NETX_IRQ_HIF_CHAINED(3) | ||
| 67 | #define NETX_IRQ_HIF_PIO72 NETX_IRQ_HIF_CHAINED(4) | ||
| 68 | #define NETX_IRQ_HIF_LAST NETX_IRQ_HIF_CHAINED(4) | ||
| 69 | |||
| 70 | #define NR_IRQS (NETX_IRQ_HIF_LAST + 1) | ||
diff --git a/include/asm-arm/arch-netx/memory.h b/include/asm-arm/arch-netx/memory.h deleted file mode 100644 index 6d8d2df3e99d..000000000000 --- a/include/asm-arm/arch-netx/memory.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-netx/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 21 | #define __ASM_ARCH_MEMORY_H | ||
| 22 | |||
| 23 | #define PHYS_OFFSET UL(0x80000000) | ||
| 24 | |||
| 25 | /* | ||
| 26 | * Virtual view <-> DMA view memory address translations | ||
| 27 | * virt_to_bus: Used to translate the virtual address to an | ||
| 28 | * address suitable to be passed to set_dma_addr | ||
| 29 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 30 | * to an address that the kernel can use. | ||
| 31 | */ | ||
| 32 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 33 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 34 | |||
| 35 | #endif | ||
| 36 | |||
diff --git a/include/asm-arm/arch-netx/netx-regs.h b/include/asm-arm/arch-netx/netx-regs.h deleted file mode 100644 index fc9aa21f360c..000000000000 --- a/include/asm-arm/arch-netx/netx-regs.h +++ /dev/null | |||
| @@ -1,410 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-netx/netx-regs.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_NETX_REGS_H | ||
| 21 | #define __ASM_ARCH_NETX_REGS_H | ||
| 22 | |||
| 23 | /* offsets relative to the beginning of the io space */ | ||
| 24 | #define NETX_OFS_SYSTEM 0x00000 | ||
| 25 | #define NETX_OFS_MEMCR 0x00100 | ||
| 26 | #define NETX_OFS_DPMAS 0x03000 | ||
| 27 | #define NETX_OFS_GPIO 0x00800 | ||
| 28 | #define NETX_OFS_PIO 0x00900 | ||
| 29 | #define NETX_OFS_UART0 0x00a00 | ||
| 30 | #define NETX_OFS_UART1 0x00a40 | ||
| 31 | #define NETX_OFS_UART2 0x00a80 | ||
| 32 | #define NETX_OF_MIIMU 0x00b00 | ||
| 33 | #define NETX_OFS_SPI 0x00c00 | ||
| 34 | #define NETX_OFS_I2C 0x00d00 | ||
| 35 | #define NETX_OFS_SYSTIME 0x01100 | ||
| 36 | #define NETX_OFS_RTC 0x01200 | ||
| 37 | #define NETX_OFS_EXTBUS 0x03600 | ||
| 38 | #define NETX_OFS_LCD 0x04000 | ||
| 39 | #define NETX_OFS_USB 0x20000 | ||
| 40 | #define NETX_OFS_XMAC0 0x60000 | ||
| 41 | #define NETX_OFS_XMAC1 0x61000 | ||
| 42 | #define NETX_OFS_XMAC2 0x62000 | ||
| 43 | #define NETX_OFS_XMAC3 0x63000 | ||
| 44 | #define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000) | ||
| 45 | #define NETX_OFS_PFIFO 0x64000 | ||
| 46 | #define NETX_OFS_XPEC0 0x70000 | ||
| 47 | #define NETX_OFS_XPEC1 0x74000 | ||
| 48 | #define NETX_OFS_XPEC2 0x78000 | ||
| 49 | #define NETX_OFS_XPEC3 0x7c000 | ||
| 50 | #define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000) | ||
| 51 | #define NETX_OFS_VIC 0xff000 | ||
| 52 | |||
| 53 | /* physical addresses */ | ||
| 54 | #define NETX_PA_SYSTEM (NETX_IO_PHYS + NETX_OFS_SYSTEM) | ||
| 55 | #define NETX_PA_MEMCR (NETX_IO_PHYS + NETX_OFS_MEMCR) | ||
| 56 | #define NETX_PA_DPMAS (NETX_IO_PHYS + NETX_OFS_DPMAS) | ||
| 57 | #define NETX_PA_GPIO (NETX_IO_PHYS + NETX_OFS_GPIO) | ||
| 58 | #define NETX_PA_PIO (NETX_IO_PHYS + NETX_OFS_PIO) | ||
| 59 | #define NETX_PA_UART0 (NETX_IO_PHYS + NETX_OFS_UART0) | ||
| 60 | #define NETX_PA_UART1 (NETX_IO_PHYS + NETX_OFS_UART1) | ||
| 61 | #define NETX_PA_UART2 (NETX_IO_PHYS + NETX_OFS_UART2) | ||
| 62 | #define NETX_PA_MIIMU (NETX_IO_PHYS + NETX_OF_MIIMU) | ||
| 63 | #define NETX_PA_SPI (NETX_IO_PHYS + NETX_OFS_SPI) | ||
| 64 | #define NETX_PA_I2C (NETX_IO_PHYS + NETX_OFS_I2C) | ||
| 65 | #define NETX_PA_SYSTIME (NETX_IO_PHYS + NETX_OFS_SYSTIME) | ||
| 66 | #define NETX_PA_RTC (NETX_IO_PHYS + NETX_OFS_RTC) | ||
| 67 | #define NETX_PA_EXTBUS (NETX_IO_PHYS + NETX_OFS_EXTBUS) | ||
| 68 | #define NETX_PA_LCD (NETX_IO_PHYS + NETX_OFS_LCD) | ||
| 69 | #define NETX_PA_USB (NETX_IO_PHYS + NETX_OFS_USB) | ||
| 70 | #define NETX_PA_XMAC0 (NETX_IO_PHYS + NETX_OFS_XMAC0) | ||
| 71 | #define NETX_PA_XMAC1 (NETX_IO_PHYS + NETX_OFS_XMAC1) | ||
| 72 | #define NETX_PA_XMAC2 (NETX_IO_PHYS + NETX_OFS_XMAC2) | ||
| 73 | #define NETX_PA_XMAC3 (NETX_IO_PHYS + NETX_OFS_XMAC3) | ||
| 74 | #define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no)) | ||
| 75 | #define NETX_PA_PFIFO (NETX_IO_PHYS + NETX_OFS_PFIFO) | ||
| 76 | #define NETX_PA_XPEC0 (NETX_IO_PHYS + NETX_OFS_XPEC0) | ||
| 77 | #define NETX_PA_XPEC1 (NETX_IO_PHYS + NETX_OFS_XPEC1) | ||
| 78 | #define NETX_PA_XPEC2 (NETX_IO_PHYS + NETX_OFS_XPEC2) | ||
| 79 | #define NETX_PA_XPEC3 (NETX_IO_PHYS + NETX_OFS_XPEC3) | ||
| 80 | #define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no)) | ||
| 81 | #define NETX_PA_VIC (NETX_IO_PHYS + NETX_OFS_VIC) | ||
| 82 | |||
| 83 | /* virual addresses */ | ||
| 84 | #define NETX_VA_SYSTEM (NETX_IO_VIRT + NETX_OFS_SYSTEM) | ||
| 85 | #define NETX_VA_MEMCR (NETX_IO_VIRT + NETX_OFS_MEMCR) | ||
| 86 | #define NETX_VA_DPMAS (NETX_IO_VIRT + NETX_OFS_DPMAS) | ||
| 87 | #define NETX_VA_GPIO (NETX_IO_VIRT + NETX_OFS_GPIO) | ||
| 88 | #define NETX_VA_PIO (NETX_IO_VIRT + NETX_OFS_PIO) | ||
| 89 | #define NETX_VA_UART0 (NETX_IO_VIRT + NETX_OFS_UART0) | ||
| 90 | #define NETX_VA_UART1 (NETX_IO_VIRT + NETX_OFS_UART1) | ||
| 91 | #define NETX_VA_UART2 (NETX_IO_VIRT + NETX_OFS_UART2) | ||
| 92 | #define NETX_VA_MIIMU (NETX_IO_VIRT + NETX_OF_MIIMU) | ||
| 93 | #define NETX_VA_SPI (NETX_IO_VIRT + NETX_OFS_SPI) | ||
| 94 | #define NETX_VA_I2C (NETX_IO_VIRT + NETX_OFS_I2C) | ||
| 95 | #define NETX_VA_SYSTIME (NETX_IO_VIRT + NETX_OFS_SYSTIME) | ||
| 96 | #define NETX_VA_RTC (NETX_IO_VIRT + NETX_OFS_RTC) | ||
| 97 | #define NETX_VA_EXTBUS (NETX_IO_VIRT + NETX_OFS_EXTBUS) | ||
| 98 | #define NETX_VA_LCD (NETX_IO_VIRT + NETX_OFS_LCD) | ||
| 99 | #define NETX_VA_USB (NETX_IO_VIRT + NETX_OFS_USB) | ||
| 100 | #define NETX_VA_XMAC0 (NETX_IO_VIRT + NETX_OFS_XMAC0) | ||
| 101 | #define NETX_VA_XMAC1 (NETX_IO_VIRT + NETX_OFS_XMAC1) | ||
| 102 | #define NETX_VA_XMAC2 (NETX_IO_VIRT + NETX_OFS_XMAC2) | ||
| 103 | #define NETX_VA_XMAC3 (NETX_IO_VIRT + NETX_OFS_XMAC3) | ||
| 104 | #define NETX_VA_XMAC(no) (NETX_IO_VIRT + NETX_OFS_XMAC(no)) | ||
| 105 | #define NETX_VA_PFIFO (NETX_IO_VIRT + NETX_OFS_PFIFO) | ||
| 106 | #define NETX_VA_XPEC0 (NETX_IO_VIRT + NETX_OFS_XPEC0) | ||
| 107 | #define NETX_VA_XPEC1 (NETX_IO_VIRT + NETX_OFS_XPEC1) | ||
| 108 | #define NETX_VA_XPEC2 (NETX_IO_VIRT + NETX_OFS_XPEC2) | ||
| 109 | #define NETX_VA_XPEC3 (NETX_IO_VIRT + NETX_OFS_XPEC3) | ||
| 110 | #define NETX_VA_XPEC(no) (NETX_IO_VIRT + NETX_OFS_XPEC(no)) | ||
| 111 | #define NETX_VA_VIC (NETX_IO_VIRT + NETX_OFS_VIC) | ||
| 112 | |||
| 113 | /********************************* | ||
| 114 | * System functions * | ||
| 115 | *********************************/ | ||
| 116 | |||
| 117 | /* Registers */ | ||
| 118 | #define NETX_SYSTEM_REG(ofs) __io(NETX_VA_SYSTEM + (ofs)) | ||
| 119 | #define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00) | ||
| 120 | #define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04) | ||
| 121 | #define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08) | ||
| 122 | |||
| 123 | /* FIXME: Docs are not consistent */ | ||
| 124 | /* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08) */ | ||
| 125 | #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c) | ||
| 126 | |||
| 127 | #define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10) | ||
| 128 | #define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34) | ||
| 129 | #define NETX_SYSTEM_IOC_ACCESS_KEY NETX_SYSTEM_REG(0x70) | ||
| 130 | #define NETX_SYSTEM_WDG_TR NETX_SYSTEM_REG(0x200) | ||
| 131 | #define NETX_SYSTEM_WDG_CTR NETX_SYSTEM_REG(0x204) | ||
| 132 | #define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208) | ||
| 133 | #define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c) | ||
| 134 | |||
| 135 | /* Bits */ | ||
| 136 | #define NETX_SYSTEM_RES_CR_RSTIN (1<<0) | ||
| 137 | #define NETX_SYSTEM_RES_CR_WDG_RES (1<<1) | ||
| 138 | #define NETX_SYSTEM_RES_CR_HOST_RES (1<<2) | ||
| 139 | #define NETX_SYSTEM_RES_CR_FIRMW_RES (1<<3) | ||
| 140 | #define NETX_SYSTEM_RES_CR_XPEC0_RES (1<<4) | ||
| 141 | #define NETX_SYSTEM_RES_CR_XPEC1_RES (1<<5) | ||
| 142 | #define NETX_SYSTEM_RES_CR_XPEC2_RES (1<<6) | ||
| 143 | #define NETX_SYSTEM_RES_CR_XPEC3_RES (1<<7) | ||
| 144 | #define NETX_SYSTEM_RES_CR_DIS_XPEC0_RES (1<<16) | ||
| 145 | #define NETX_SYSTEM_RES_CR_DIS_XPEC1_RES (1<<17) | ||
| 146 | #define NETX_SYSTEM_RES_CR_DIS_XPEC2_RES (1<<18) | ||
| 147 | #define NETX_SYSTEM_RES_CR_DIS_XPEC3_RES (1<<19) | ||
| 148 | #define NETX_SYSTEM_RES_CR_FIRMW_FLG0 (1<<20) | ||
| 149 | #define NETX_SYSTEM_RES_CR_FIRMW_FLG1 (1<<21) | ||
| 150 | #define NETX_SYSTEM_RES_CR_FIRMW_FLG2 (1<<22) | ||
| 151 | #define NETX_SYSTEM_RES_CR_FIRMW_FLG3 (1<<23) | ||
| 152 | #define NETX_SYSTEM_RES_CR_FIRMW_RES_EN (1<<24) | ||
| 153 | #define NETX_SYSTEM_RES_CR_RSTOUT (1<<25) | ||
| 154 | #define NETX_SYSTEM_RES_CR_EN_RSTOUT (1<<26) | ||
| 155 | |||
| 156 | #define PHY_CONTROL_RESET (1<<31) | ||
| 157 | #define PHY_CONTROL_SIM_BYP (1<<30) | ||
| 158 | #define PHY_CONTROL_CLK_XLATIN (1<<29) | ||
| 159 | #define PHY_CONTROL_PHY1_EN (1<<21) | ||
| 160 | #define PHY_CONTROL_PHY1_NP_MSG_CODE | ||
| 161 | #define PHY_CONTROL_PHY1_AUTOMDIX (1<<17) | ||
| 162 | #define PHY_CONTROL_PHY1_FIXMODE (1<<16) | ||
| 163 | #define PHY_CONTROL_PHY1_MODE(mode) (((mode) & 0x7) << 13) | ||
| 164 | #define PHY_CONTROL_PHY0_EN (1<<12) | ||
| 165 | #define PHY_CONTROL_PHY0_NP_MSG_CODE | ||
| 166 | #define PHY_CONTROL_PHY0_AUTOMDIX (1<<8) | ||
| 167 | #define PHY_CONTROL_PHY0_FIXMODE (1<<7) | ||
| 168 | #define PHY_CONTROL_PHY0_MODE(mode) (((mode) & 0x7) << 4) | ||
| 169 | #define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf) | ||
| 170 | |||
| 171 | #define PHY_MODE_10BASE_T_HALF 0 | ||
| 172 | #define PHY_MODE_10BASE_T_FULL 1 | ||
| 173 | #define PHY_MODE_100BASE_TX_FX_FULL 2 | ||
| 174 | #define PHY_MODE_100BASE_TX_FX_HALF 3 | ||
| 175 | #define PHY_MODE_100BASE_TX_HALF 4 | ||
| 176 | #define PHY_MODE_REPEATER 5 | ||
| 177 | #define PHY_MODE_POWER_DOWN 6 | ||
| 178 | #define PHY_MODE_ALL 7 | ||
| 179 | |||
| 180 | /* Bits */ | ||
| 181 | #define VECT_CNTL_ENABLE (1 << 5) | ||
| 182 | |||
| 183 | /******************************* | ||
| 184 | * GPIO and timer module * | ||
| 185 | *******************************/ | ||
| 186 | |||
| 187 | /* Registers */ | ||
| 188 | #define NETX_GPIO_REG(ofs) __io(NETX_VA_GPIO + (ofs)) | ||
| 189 | #define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2)) | ||
| 190 | #define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2)) | ||
| 191 | #define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2)) | ||
| 192 | #define NETX_GPIO_COUNTER_MAX(counter) NETX_GPIO_REG(0x94 + ((counter)<<2)) | ||
| 193 | #define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2)) | ||
| 194 | #define NETX_GPIO_IRQ_ENABLE NETX_GPIO_REG(0xbc) | ||
| 195 | #define NETX_GPIO_IRQ_DISABLE NETX_GPIO_REG(0xc0) | ||
| 196 | #define NETX_GPIO_SYSTIME_NS_CMP NETX_GPIO_REG(0xc4) | ||
| 197 | #define NETX_GPIO_LINE NETX_GPIO_REG(0xc8) | ||
| 198 | #define NETX_GPIO_IRQ NETX_GPIO_REG(0xd0) | ||
| 199 | |||
| 200 | /* Bits */ | ||
| 201 | #define NETX_GPIO_CFG_IOCFG_GP_INPUT (0x0) | ||
| 202 | #define NETX_GPIO_CFG_IOCFG_GP_OUTPUT (0x1) | ||
| 203 | #define NETX_GPIO_CFG_IOCFG_GP_UART (0x2) | ||
| 204 | #define NETX_GPIO_CFG_INV (1<<2) | ||
| 205 | #define NETX_GPIO_CFG_MODE_INPUT_READ (0<<3) | ||
| 206 | #define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3) | ||
| 207 | #define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3) | ||
| 208 | #define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL (3<<3) | ||
| 209 | #define NETX_GPIO_CFG_COUNT_REF_COUNTER0 (0<<5) | ||
| 210 | #define NETX_GPIO_CFG_COUNT_REF_COUNTER1 (1<<5) | ||
| 211 | #define NETX_GPIO_CFG_COUNT_REF_COUNTER2 (2<<5) | ||
| 212 | #define NETX_GPIO_CFG_COUNT_REF_COUNTER3 (3<<5) | ||
| 213 | #define NETX_GPIO_CFG_COUNT_REF_COUNTER4 (4<<5) | ||
| 214 | #define NETX_GPIO_CFG_COUNT_REF_SYSTIME (7<<5) | ||
| 215 | |||
| 216 | #define NETX_GPIO_COUNTER_CTRL_RUN (1<<0) | ||
| 217 | #define NETX_GPIO_COUNTER_CTRL_SYM (1<<1) | ||
| 218 | #define NETX_GPIO_COUNTER_CTRL_ONCE (1<<2) | ||
| 219 | #define NETX_GPIO_COUNTER_CTRL_IRQ_EN (1<<3) | ||
| 220 | #define NETX_GPIO_COUNTER_CTRL_CNT_EVENT (1<<4) | ||
| 221 | #define NETX_GPIO_COUNTER_CTRL_RST_EN (1<<5) | ||
| 222 | #define NETX_GPIO_COUNTER_CTRL_SEL_EVENT (1<<6) | ||
| 223 | #define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */ | ||
| 224 | |||
| 225 | #define GPIO_BIT(gpio) (1<<(gpio)) | ||
| 226 | #define COUNTER_BIT(counter) ((1<<16)<<(counter)) | ||
| 227 | |||
| 228 | /******************************* | ||
| 229 | * PIO * | ||
| 230 | *******************************/ | ||
| 231 | |||
| 232 | /* Registers */ | ||
| 233 | #define NETX_PIO_REG(ofs) __io(NETX_VA_PIO + (ofs)) | ||
| 234 | #define NETX_PIO_INPIO NETX_PIO_REG(0x0) | ||
| 235 | #define NETX_PIO_OUTPIO NETX_PIO_REG(0x4) | ||
| 236 | #define NETX_PIO_OEPIO NETX_PIO_REG(0x8) | ||
| 237 | |||
| 238 | /******************************* | ||
| 239 | * MII Unit * | ||
| 240 | *******************************/ | ||
| 241 | |||
| 242 | /* Registers */ | ||
| 243 | #define NETX_MIIMU __io(NETX_VA_MIIMU) | ||
| 244 | |||
| 245 | /* Bits */ | ||
| 246 | #define MIIMU_SNRDY (1<<0) | ||
| 247 | #define MIIMU_PREAMBLE (1<<1) | ||
| 248 | #define MIIMU_OPMODE_WRITE (1<<2) | ||
| 249 | #define MIIMU_MDC_PERIOD (1<<3) | ||
| 250 | #define MIIMU_PHY_NRES (1<<4) | ||
| 251 | #define MIIMU_RTA (1<<5) | ||
| 252 | #define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6) | ||
| 253 | #define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11) | ||
| 254 | #define MIIMU_DATA(data) (((data) & 0xffff) << 16) | ||
| 255 | |||
| 256 | /******************************* | ||
| 257 | * xmac / xpec * | ||
| 258 | *******************************/ | ||
| 259 | |||
| 260 | /* XPEC register offsets relative to NETX_VA_XPEC(no) */ | ||
| 261 | #define NETX_XPEC_R0_OFS 0x00 | ||
| 262 | #define NETX_XPEC_R1_OFS 0x04 | ||
| 263 | #define NETX_XPEC_R2_OFS 0x08 | ||
| 264 | #define NETX_XPEC_R3_OFS 0x0c | ||
| 265 | #define NETX_XPEC_R4_OFS 0x10 | ||
| 266 | #define NETX_XPEC_R5_OFS 0x14 | ||
| 267 | #define NETX_XPEC_R6_OFS 0x18 | ||
| 268 | #define NETX_XPEC_R7_OFS 0x1c | ||
| 269 | #define NETX_XPEC_RANGE01_OFS 0x20 | ||
| 270 | #define NETX_XPEC_RANGE23_OFS 0x24 | ||
| 271 | #define NETX_XPEC_RANGE45_OFS 0x28 | ||
| 272 | #define NETX_XPEC_RANGE67_OFS 0x2c | ||
| 273 | #define NETX_XPEC_PC_OFS 0x48 | ||
| 274 | #define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2)) | ||
| 275 | #define NETX_XPEC_IRQ_OFS 0x8c | ||
| 276 | #define NETX_XPEC_SYSTIME_NS_OFS 0x90 | ||
| 277 | #define NETX_XPEC_FIFO_DATA_OFS 0x94 | ||
| 278 | #define NETX_XPEC_SYSTIME_S_OFS 0x98 | ||
| 279 | #define NETX_XPEC_ADC_OFS 0x9c | ||
| 280 | #define NETX_XPEC_URX_COUNT_OFS 0x40 | ||
| 281 | #define NETX_XPEC_UTX_COUNT_OFS 0x44 | ||
| 282 | #define NETX_XPEC_PC_OFS 0x48 | ||
| 283 | #define NETX_XPEC_ZERO_OFS 0x4c | ||
| 284 | #define NETX_XPEC_STATCFG_OFS 0x50 | ||
| 285 | #define NETX_XPEC_EC_MASKA_OFS 0x54 | ||
| 286 | #define NETX_XPEC_EC_MASKB_OFS 0x58 | ||
| 287 | #define NETX_XPEC_EC_MASK0_OFS 0x5c | ||
| 288 | #define NETX_XPEC_EC_MASK8_OFS 0x7c | ||
| 289 | #define NETX_XPEC_EC_MASK9_OFS 0x80 | ||
| 290 | #define NETX_XPEC_XPU_HOLD_PC_OFS 0x100 | ||
| 291 | #define NETX_XPEC_RAM_START_OFS 0x2000 | ||
| 292 | |||
| 293 | /* Bits */ | ||
| 294 | #define XPU_HOLD_PC (1<<0) | ||
| 295 | |||
| 296 | /* XMAC register offsets relative to NETX_VA_XMAC(no) */ | ||
| 297 | #define NETX_XMAC_RPU_PROGRAM_START_OFS 0x000 | ||
| 298 | #define NETX_XMAC_RPU_PROGRAM_END_OFS 0x3ff | ||
| 299 | #define NETX_XMAC_TPU_PROGRAM_START_OFS 0x400 | ||
| 300 | #define NETX_XMAC_TPU_PROGRAM_END_OFS 0x7ff | ||
| 301 | #define NETX_XMAC_RPU_HOLD_PC_OFS 0xa00 | ||
| 302 | #define NETX_XMAC_TPU_HOLD_PC_OFS 0xa04 | ||
| 303 | #define NETX_XMAC_STATUS_SHARED0_OFS 0x840 | ||
| 304 | #define NETX_XMAC_CONFIG_SHARED0_OFS 0x844 | ||
| 305 | #define NETX_XMAC_STATUS_SHARED1_OFS 0x848 | ||
| 306 | #define NETX_XMAC_CONFIG_SHARED1_OFS 0x84c | ||
| 307 | #define NETX_XMAC_STATUS_SHARED2_OFS 0x850 | ||
| 308 | #define NETX_XMAC_CONFIG_SHARED2_OFS 0x854 | ||
| 309 | #define NETX_XMAC_STATUS_SHARED3_OFS 0x858 | ||
| 310 | #define NETX_XMAC_CONFIG_SHARED3_OFS 0x85c | ||
| 311 | |||
| 312 | #define RPU_HOLD_PC (1<<15) | ||
| 313 | #define TPU_HOLD_PC (1<<15) | ||
| 314 | |||
| 315 | /******************************* | ||
| 316 | * Pointer FIFO * | ||
| 317 | *******************************/ | ||
| 318 | |||
| 319 | /* Registers */ | ||
| 320 | #define NETX_PFIFO_REG(ofs) __io(NETX_VA_PFIFO + (ofs)) | ||
| 321 | #define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2)) | ||
| 322 | #define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2)) | ||
| 323 | #define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100) | ||
| 324 | #define NETX_PFIFO_FULL NETX_PFIFO_REG(0x104) | ||
| 325 | #define NETX_PFIFO_EMPTY NETX_PFIFO_REG(0x108) | ||
| 326 | #define NETX_PFIFO_OVEFLOW NETX_PFIFO_REG(0x10c) | ||
| 327 | #define NETX_PFIFO_UNDERRUN NETX_PFIFO_REG(0x110) | ||
| 328 | #define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2)) | ||
| 329 | #define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2)) | ||
| 330 | |||
| 331 | /******************************* | ||
| 332 | * Dual Port Memory * | ||
| 333 | *******************************/ | ||
| 334 | |||
| 335 | /* Registers */ | ||
| 336 | #define NETX_DPMAS_REG(ofs) __io(NETX_VA_DPMAS + (ofs)) | ||
| 337 | #define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8) | ||
| 338 | #define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0) | ||
| 339 | #define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0) | ||
| 340 | #define NETX_DPMAS_IF_CONF0 NETX_DPMAS_REG(0x608) | ||
| 341 | #define NETX_DPMAS_IF_CONF1 NETX_DPMAS_REG(0x60c) | ||
| 342 | #define NETX_DPMAS_EXT_CONFIG(cs) NETX_DPMAS_REG(0x610 + 4 * (cs)) | ||
| 343 | #define NETX_DPMAS_IO_MODE0 NETX_DPMAS_REG(0x620) /* I/O 32..63 */ | ||
| 344 | #define NETX_DPMAS_DRV_EN0 NETX_DPMAS_REG(0x624) | ||
| 345 | #define NETX_DPMAS_DATA0 NETX_DPMAS_REG(0x628) | ||
| 346 | #define NETX_DPMAS_IO_MODE1 NETX_DPMAS_REG(0x630) /* I/O 64..84 */ | ||
| 347 | #define NETX_DPMAS_DRV_EN1 NETX_DPMAS_REG(0x634) | ||
| 348 | #define NETX_DPMAS_DATA1 NETX_DPMAS_REG(0x638) | ||
| 349 | |||
| 350 | /* Bits */ | ||
| 351 | #define NETX_DPMAS_INT_EN_GLB_EN (1<<31) | ||
| 352 | #define NETX_DPMAS_INT_EN_MEM_LCK (1<<30) | ||
| 353 | #define NETX_DPMAS_INT_EN_WDG (1<<29) | ||
| 354 | #define NETX_DPMAS_INT_EN_PIO72 (1<<28) | ||
| 355 | #define NETX_DPMAS_INT_EN_PIO47 (1<<27) | ||
| 356 | #define NETX_DPMAS_INT_EN_PIO40 (1<<26) | ||
| 357 | #define NETX_DPMAS_INT_EN_PIO36 (1<<25) | ||
| 358 | #define NETX_DPMAS_INT_EN_PIO35 (1<<24) | ||
| 359 | |||
| 360 | #define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28) | ||
| 361 | #define NETX_DPMAS_IF_CONF0_HIF_EXT_BUS (1<<28) | ||
| 362 | #define NETX_DPMAS_IF_CONF0_HIF_UP_8BIT (2<<28) | ||
| 363 | #define NETX_DPMAS_IF_CONF0_HIF_UP_16BIT (3<<28) | ||
| 364 | #define NETX_DPMAS_IF_CONF0_HIF_IO (4<<28) | ||
| 365 | #define NETX_DPMAS_IF_CONF0_WAIT_DRV_PP (1<<14) | ||
| 366 | #define NETX_DPMAS_IF_CONF0_WAIT_DRV_OD (2<<14) | ||
| 367 | #define NETX_DPMAS_IF_CONF0_WAIT_DRV_TRI (3<<14) | ||
| 368 | |||
| 369 | #define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO35 (1<<26) | ||
| 370 | #define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO36 (1<<27) | ||
| 371 | #define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO40 (1<<28) | ||
| 372 | #define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO47 (1<<29) | ||
| 373 | #define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO72 (1<<30) | ||
| 374 | |||
| 375 | #define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29) | ||
| 376 | #define NETX_EXT_CONFIG_TADRHOLD(x) (((x) & 0x7) << 26) | ||
| 377 | #define NETX_EXT_CONFIG_TCSON(x) (((x) & 0x7) << 23) | ||
| 378 | #define NETX_EXT_CONFIG_TRDON(x) (((x) & 0x7) << 20) | ||
| 379 | #define NETX_EXT_CONFIG_TWRON(x) (((x) & 0x7) << 17) | ||
| 380 | #define NETX_EXT_CONFIG_TWROFF(x) (((x) & 0x1f) << 12) | ||
| 381 | #define NETX_EXT_CONFIG_TRDWRCYC(x) (((x) & 0x1f) << 7) | ||
| 382 | #define NETX_EXT_CONFIG_WAIT_POL (1<<6) | ||
| 383 | #define NETX_EXT_CONFIG_WAIT_EN (1<<5) | ||
| 384 | #define NETX_EXT_CONFIG_NRD_MODE (1<<4) | ||
| 385 | #define NETX_EXT_CONFIG_DS_MODE (1<<3) | ||
| 386 | #define NETX_EXT_CONFIG_NWR_MODE (1<<2) | ||
| 387 | #define NETX_EXT_CONFIG_16BIT (1<<1) | ||
| 388 | #define NETX_EXT_CONFIG_CS_ENABLE (1<<0) | ||
| 389 | |||
| 390 | #define NETX_DPMAS_IO_MODE0_WRL (1<<13) | ||
| 391 | #define NETX_DPMAS_IO_MODE0_WAIT (1<<14) | ||
| 392 | #define NETX_DPMAS_IO_MODE0_READY (1<<15) | ||
| 393 | #define NETX_DPMAS_IO_MODE0_CS0 (1<<19) | ||
| 394 | #define NETX_DPMAS_IO_MODE0_EXTRD (1<<20) | ||
| 395 | |||
| 396 | #define NETX_DPMAS_IO_MODE1_CS2 (1<<15) | ||
| 397 | #define NETX_DPMAS_IO_MODE1_CS1 (1<<16) | ||
| 398 | #define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR (0<<30) | ||
| 399 | #define NETX_DPMAS_IO_MODE1_SAMPLE_100MHZ (1<<30) | ||
| 400 | #define NETX_DPMAS_IO_MODE1_SAMPLE_NPIO36 (2<<30) | ||
| 401 | #define NETX_DPMAS_IO_MODE1_SAMPLE_PIO36 (3<<30) | ||
| 402 | |||
| 403 | /******************************* | ||
| 404 | * I2C * | ||
| 405 | *******************************/ | ||
| 406 | #define NETX_I2C_REG(ofs) __io(NETX_VA_I2C, (ofs)) | ||
| 407 | #define NETX_I2C_CTRL NETX_I2C_REG(0x0) | ||
| 408 | #define NETX_I2C_DATA NETX_I2C_REG(0x4) | ||
| 409 | |||
| 410 | #endif /* __ASM_ARCH_NETX_REGS_H */ | ||
diff --git a/include/asm-arm/arch-netx/param.h b/include/asm-arm/arch-netx/param.h deleted file mode 100644 index 7a80c26178a8..000000000000 --- a/include/asm-arm/arch-netx/param.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-netx/param.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
diff --git a/include/asm-arm/arch-netx/pfifo.h b/include/asm-arm/arch-netx/pfifo.h deleted file mode 100644 index 4af2ee4a32c1..000000000000 --- a/include/asm-arm/arch-netx/pfifo.h +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-netx/pfifo.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | |||
| 21 | #ifndef ASM_ARCH_PFIFO_H | ||
| 22 | #define ASM_ARCH_PFIFO_H | ||
| 23 | |||
| 24 | static inline int pfifo_push(int no, unsigned int pointer) | ||
| 25 | { | ||
| 26 | writel(pointer, NETX_PFIFO_BASE(no)); | ||
| 27 | return 0; | ||
| 28 | } | ||
| 29 | |||
| 30 | static inline unsigned int pfifo_pop(int no) | ||
| 31 | { | ||
| 32 | return readl(NETX_PFIFO_BASE(no)); | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline int pfifo_fill_level(int no) | ||
| 36 | { | ||
| 37 | |||
| 38 | return readl(NETX_PFIFO_FILL_LEVEL(no)); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline int pfifo_full(int no) | ||
| 42 | { | ||
| 43 | return readl(NETX_PFIFO_FULL) & (1<<no) ? 1 : 0; | ||
| 44 | } | ||
| 45 | |||
| 46 | static inline int pfifo_empty(int no) | ||
| 47 | { | ||
| 48 | return readl(NETX_PFIFO_EMPTY) & (1<<no) ? 1 : 0; | ||
| 49 | } | ||
| 50 | |||
| 51 | int pfifo_request(unsigned int pfifo_mask); | ||
| 52 | void pfifo_free(unsigned int pfifo_mask); | ||
| 53 | |||
| 54 | #endif /* ASM_ARCH_PFIFO_H */ | ||
diff --git a/include/asm-arm/arch-netx/system.h b/include/asm-arm/arch-netx/system.h deleted file mode 100644 index 0624d87e1db8..000000000000 --- a/include/asm-arm/arch-netx/system.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-netx/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 20 | #define __ASM_ARCH_SYSTEM_H | ||
| 21 | |||
| 22 | #include <asm/io.h> | ||
| 23 | #include <asm/arch/hardware.h> | ||
| 24 | #include "netx-regs.h" | ||
| 25 | |||
| 26 | static inline void arch_idle(void) | ||
| 27 | { | ||
| 28 | cpu_do_idle(); | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline void arch_reset(char mode) | ||
| 32 | { | ||
| 33 | writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES, | ||
| 34 | NETX_SYSTEM_RES_CR); | ||
| 35 | } | ||
| 36 | |||
| 37 | #endif | ||
| 38 | |||
diff --git a/include/asm-arm/arch-netx/timex.h b/include/asm-arm/arch-netx/timex.h deleted file mode 100644 index 7fdb42da0b40..000000000000 --- a/include/asm-arm/arch-netx/timex.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-netx/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define CLOCK_TICK_RATE 100000000 | ||
diff --git a/include/asm-arm/arch-netx/uncompress.h b/include/asm-arm/arch-netx/uncompress.h deleted file mode 100644 index f89434547102..000000000000 --- a/include/asm-arm/arch-netx/uncompress.h +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-netx/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | /* | ||
| 21 | * The following code assumes the serial port has already been | ||
| 22 | * initialized by the bootloader. We search for the first enabled | ||
| 23 | * port in the most probable order. If you didn't setup a port in | ||
| 24 | * your bootloader then nothing will appear (which might be desired). | ||
| 25 | * | ||
| 26 | * This does not append a newline | ||
| 27 | */ | ||
| 28 | |||
| 29 | #define REG(x) (*(volatile unsigned long *)(x)) | ||
| 30 | |||
| 31 | #define UART1_BASE 0x100a00 | ||
| 32 | #define UART2_BASE 0x100a80 | ||
| 33 | |||
| 34 | #define UART_DR 0x0 | ||
| 35 | |||
| 36 | #define UART_CR 0x14 | ||
| 37 | #define CR_UART_EN (1<<0) | ||
| 38 | |||
| 39 | #define UART_FR 0x18 | ||
| 40 | #define FR_BUSY (1<<3) | ||
| 41 | #define FR_TXFF (1<<5) | ||
| 42 | |||
| 43 | static void putc(char c) | ||
| 44 | { | ||
| 45 | unsigned long base; | ||
| 46 | |||
| 47 | if (REG(UART1_BASE + UART_CR) & CR_UART_EN) | ||
| 48 | base = UART1_BASE; | ||
| 49 | else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) | ||
| 50 | base = UART2_BASE; | ||
| 51 | else | ||
| 52 | return; | ||
| 53 | |||
| 54 | while (REG(base + UART_FR) & FR_TXFF); | ||
| 55 | REG(base + UART_DR) = c; | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline void flush(void) | ||
| 59 | { | ||
| 60 | unsigned long base; | ||
| 61 | |||
| 62 | if (REG(UART1_BASE + UART_CR) & CR_UART_EN) | ||
| 63 | base = UART1_BASE; | ||
| 64 | else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) | ||
| 65 | base = UART2_BASE; | ||
| 66 | else | ||
| 67 | return; | ||
| 68 | |||
| 69 | while (REG(base + UART_FR) & FR_BUSY); | ||
| 70 | } | ||
| 71 | |||
| 72 | /* | ||
| 73 | * nothing to do | ||
| 74 | */ | ||
| 75 | #define arch_decomp_setup() | ||
| 76 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-netx/vmalloc.h b/include/asm-arm/arch-netx/vmalloc.h deleted file mode 100644 index da2da5a595da..000000000000 --- a/include/asm-arm/arch-netx/vmalloc.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-netx/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
diff --git a/include/asm-arm/arch-netx/xc.h b/include/asm-arm/arch-netx/xc.h deleted file mode 100644 index 659af19512a9..000000000000 --- a/include/asm-arm/arch-netx/xc.h +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-netx/xc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 | ||
| 8 | * as published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_XC_H | ||
| 21 | #define __ASM_ARCH_XC_H | ||
| 22 | |||
| 23 | struct xc { | ||
| 24 | int no; | ||
| 25 | unsigned int type; | ||
| 26 | unsigned int version; | ||
| 27 | void __iomem *xpec_base; | ||
| 28 | void __iomem *xmac_base; | ||
| 29 | void __iomem *sram_base; | ||
| 30 | int irq; | ||
| 31 | struct device *dev; | ||
| 32 | }; | ||
| 33 | |||
| 34 | int xc_reset(struct xc *x); | ||
| 35 | int xc_stop(struct xc* x); | ||
| 36 | int xc_start(struct xc *x); | ||
| 37 | int xc_running(struct xc *x); | ||
| 38 | int xc_request_firmware(struct xc* x); | ||
| 39 | struct xc* request_xc(int xcno, struct device *dev); | ||
| 40 | void free_xc(struct xc *x); | ||
| 41 | |||
| 42 | #endif /* __ASM_ARCH_XC_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/board.h b/include/asm-arm/arch-ns9xxx/board.h deleted file mode 100644 index e57443bdbbd9..000000000000 --- a/include/asm-arm/arch-ns9xxx/board.h +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/board.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_BOARD_H | ||
| 12 | #define __ASM_ARCH_BOARD_H | ||
| 13 | |||
| 14 | #include <asm/mach-types.h> | ||
| 15 | |||
| 16 | #define board_is_a9m9750dev() (0 \ | ||
| 17 | || machine_is_cc9p9360dev() \ | ||
| 18 | || machine_is_cc9p9750dev() \ | ||
| 19 | ) | ||
| 20 | |||
| 21 | #define board_is_a9mvali() (0 \ | ||
| 22 | || machine_is_cc9p9360val() \ | ||
| 23 | || machine_is_cc9p9750val() \ | ||
| 24 | ) | ||
| 25 | |||
| 26 | #define board_is_jscc9p9210() (0 \ | ||
| 27 | || machine_is_cc9p9210js() \ | ||
| 28 | ) | ||
| 29 | |||
| 30 | #define board_is_jscc9p9215() (0 \ | ||
| 31 | || machine_is_cc9p9215js() \ | ||
| 32 | ) | ||
| 33 | |||
| 34 | #define board_is_jscc9p9360() (0 \ | ||
| 35 | || machine_is_cc9p9360js() \ | ||
| 36 | ) | ||
| 37 | |||
| 38 | #define board_is_uncbas() (0 \ | ||
| 39 | || machine_is_cc7ucamry() \ | ||
| 40 | ) | ||
| 41 | |||
| 42 | #endif /* ifndef __ASM_ARCH_BOARD_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/debug-macro.S b/include/asm-arm/arch-ns9xxx/debug-macro.S deleted file mode 100644 index c78908d7203d..000000000000 --- a/include/asm-arm/arch-ns9xxx/debug-macro.S +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/debug-macro.S | ||
| 3 | * Copyright (C) 2006 by Digi International Inc. | ||
| 4 | * All rights reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License version 2 as published by | ||
| 8 | * the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | |||
| 12 | #include <asm/arch/regs-board-a9m9750dev.h> | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 | ||
| 17 | ldreq \rx, =NS9XXX_CSxSTAT_PHYS(0) | ||
| 18 | ldrne \rx, =io_p2v(NS9XXX_CSxSTAT_PHYS(0)) | ||
| 19 | .endm | ||
| 20 | |||
| 21 | #define UART_SHIFT 2 | ||
| 22 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-ns9xxx/dma.h b/include/asm-arm/arch-ns9xxx/dma.h deleted file mode 100644 index a67cbbe009c4..000000000000 --- a/include/asm-arm/arch-ns9xxx/dma.h +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_DMA_H | ||
| 12 | #define __ASM_ARCH_DMA_H | ||
| 13 | |||
| 14 | #endif /* ifndef __ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/entry-macro.S b/include/asm-arm/arch-ns9xxx/entry-macro.S deleted file mode 100644 index e9d9449d300a..000000000000 --- a/include/asm-arm/arch-ns9xxx/entry-macro.S +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/entry-macro.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <asm/arch/hardware.h> | ||
| 12 | #include <asm/arch/regs-sys-common.h> | ||
| 13 | |||
| 14 | .macro get_irqnr_preamble, base, tmp | ||
| 15 | ldr \base, =SYS_ISRADDR | ||
| 16 | .endm | ||
| 17 | |||
| 18 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 22 | ldr \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)] | ||
| 23 | cmp \irqstat, #0 | ||
| 24 | ldrne \irqnr, [\base] | ||
| 25 | .endm | ||
| 26 | |||
| 27 | .macro disable_fiq | ||
| 28 | .endm | ||
diff --git a/include/asm-arm/arch-ns9xxx/gpio.h b/include/asm-arm/arch-ns9xxx/gpio.h deleted file mode 100644 index adbca08583c0..000000000000 --- a/include/asm-arm/arch-ns9xxx/gpio.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/gpio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_GPIO_H | ||
| 12 | #define __ASM_ARCH_GPIO_H | ||
| 13 | |||
| 14 | #include <asm/errno.h> | ||
| 15 | |||
| 16 | int gpio_request(unsigned gpio, const char *label); | ||
| 17 | |||
| 18 | void gpio_free(unsigned gpio); | ||
| 19 | |||
| 20 | int ns9xxx_gpio_configure(unsigned gpio, int inv, int func); | ||
| 21 | |||
| 22 | int gpio_direction_input(unsigned gpio); | ||
| 23 | |||
| 24 | int gpio_direction_output(unsigned gpio, int value); | ||
| 25 | |||
| 26 | int gpio_get_value(unsigned gpio); | ||
| 27 | |||
| 28 | void gpio_set_value(unsigned gpio, int value); | ||
| 29 | |||
| 30 | /* | ||
| 31 | * ns9xxx can use gpio pins to trigger an irq, but it's not generic | ||
| 32 | * enough to be supported by the gpio_to_irq/irq_to_gpio interface | ||
| 33 | */ | ||
| 34 | static inline int gpio_to_irq(unsigned gpio) | ||
| 35 | { | ||
| 36 | return -EINVAL; | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline int irq_to_gpio(unsigned irq) | ||
| 40 | { | ||
| 41 | return -EINVAL; | ||
| 42 | } | ||
| 43 | |||
| 44 | /* get the cansleep() stubs */ | ||
| 45 | #include <asm-generic/gpio.h> | ||
| 46 | |||
| 47 | #endif /* ifndef __ASM_ARCH_GPIO_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h deleted file mode 100644 index 0dca11ce21fc..000000000000 --- a/include/asm-arm/arch-ns9xxx/hardware.h +++ /dev/null | |||
| @@ -1,79 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 12 | #define __ASM_ARCH_HARDWARE_H | ||
| 13 | |||
| 14 | #include <asm/memory.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * NetSilicon NS9xxx internal mapping: | ||
| 18 | * | ||
| 19 | * physical <--> virtual | ||
| 20 | * 0x90000000 - 0x906fffff <--> 0xf9000000 - 0xf96fffff | ||
| 21 | * 0xa0100000 - 0xa0afffff <--> 0xfa100000 - 0xfaafffff | ||
| 22 | */ | ||
| 23 | #define io_p2v(x) (0xf0000000 \ | ||
| 24 | + (((x) & 0xf0000000) >> 4) \ | ||
| 25 | + ((x) & 0x00ffffff)) | ||
| 26 | |||
| 27 | #define io_v2p(x) ((((x) & 0x0f000000) << 4) \ | ||
| 28 | + ((x) & 0x00ffffff)) | ||
| 29 | |||
| 30 | #define __REGSHIFT(mask) ((mask) & (-(mask))) | ||
| 31 | |||
| 32 | #define __REGBIT(bit) ((u32)1 << (bit)) | ||
| 33 | #define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit)) | ||
| 34 | #define __REGVAL(mask, value) (((value) * __REGSHIFT(mask)) & (mask)) | ||
| 35 | |||
| 36 | #ifndef __ASSEMBLY__ | ||
| 37 | |||
| 38 | # define __REG(x) ((void __iomem __force *)io_p2v((x))) | ||
| 39 | # define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y))) | ||
| 40 | |||
| 41 | # define __REGSET(var, field, value) \ | ||
| 42 | ((var) = (((var) & ~((field) & ~(value))) | (value))) | ||
| 43 | |||
| 44 | # define REGSET(var, reg, field, value) \ | ||
| 45 | __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value) | ||
| 46 | |||
| 47 | # define REGSET_IDX(var, reg, field, idx, value) \ | ||
| 48 | __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx))) | ||
| 49 | |||
| 50 | # define REGSETIM(var, reg, field, value) \ | ||
| 51 | __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value))) | ||
| 52 | |||
| 53 | # define REGSETIM_IDX(var, reg, field, idx, value) \ | ||
| 54 | __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value))) | ||
| 55 | |||
| 56 | # define __REGGET(var, field) \ | ||
| 57 | (((var) & (field))) | ||
| 58 | |||
| 59 | # define REGGET(var, reg, field) \ | ||
| 60 | __REGGET(var, reg ## _ ## field) | ||
| 61 | |||
| 62 | # define REGGET_IDX(var, reg, field, idx) \ | ||
| 63 | __REGGET(var, reg ## _ ## field((idx))) | ||
| 64 | |||
| 65 | # define REGGETIM(var, reg, field) \ | ||
| 66 | __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field) | ||
| 67 | |||
| 68 | # define REGGETIM_IDX(var, reg, field, idx) \ | ||
| 69 | __REGGET(var, reg ## _ ## field((idx))) / \ | ||
| 70 | __REGSHIFT(reg ## _ ## field((idx))) | ||
| 71 | |||
| 72 | #else | ||
| 73 | |||
| 74 | # define __REG(x) io_p2v(x) | ||
| 75 | # define __REG2(x, y) io_p2v((x) + 4 * (y)) | ||
| 76 | |||
| 77 | #endif | ||
| 78 | |||
| 79 | #endif /* ifndef __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/io.h b/include/asm-arm/arch-ns9xxx/io.h deleted file mode 100644 index 6f82d28af120..000000000000 --- a/include/asm-arm/arch-ns9xxx/io.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_IO_H | ||
| 12 | #define __ASM_ARCH_IO_H | ||
| 13 | |||
| 14 | #define IO_SPACE_LIMIT 0xffffffff /* XXX */ | ||
| 15 | |||
| 16 | #define __io(a) ((void __iomem *)(a)) | ||
| 17 | #define __mem_pci(a) (a) | ||
| 18 | #define __mem_isa(a) (IO_BASE + (a)) | ||
| 19 | |||
| 20 | #endif /* ifndef __ASM_ARCH_IO_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/irqs.h b/include/asm-arm/arch-ns9xxx/irqs.h deleted file mode 100644 index e83d48ec42c9..000000000000 --- a/include/asm-arm/arch-ns9xxx/irqs.h +++ /dev/null | |||
| @@ -1,86 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_IRQS_H | ||
| 12 | #define __ASM_ARCH_IRQS_H | ||
| 13 | |||
| 14 | /* NetSilicon 9360 */ | ||
| 15 | #define IRQ_NS9XXX_WATCHDOG 0 | ||
| 16 | #define IRQ_NS9XXX_AHBBUSERR 1 | ||
| 17 | #define IRQ_NS9360_BBUSAGG 2 | ||
| 18 | /* irq 3 is reserved for NS9360 */ | ||
| 19 | #define IRQ_NS9XXX_ETHRX 4 | ||
| 20 | #define IRQ_NS9XXX_ETHTX 5 | ||
| 21 | #define IRQ_NS9XXX_ETHPHY 6 | ||
| 22 | #define IRQ_NS9360_LCD 7 | ||
| 23 | #define IRQ_NS9360_SERBRX 8 | ||
| 24 | #define IRQ_NS9360_SERBTX 9 | ||
| 25 | #define IRQ_NS9360_SERARX 10 | ||
| 26 | #define IRQ_NS9360_SERATX 11 | ||
| 27 | #define IRQ_NS9360_SERCRX 12 | ||
| 28 | #define IRQ_NS9360_SERCTX 13 | ||
| 29 | #define IRQ_NS9360_I2C 14 | ||
| 30 | #define IRQ_NS9360_BBUSDMA 15 | ||
| 31 | #define IRQ_NS9360_TIMER0 16 | ||
| 32 | #define IRQ_NS9360_TIMER1 17 | ||
| 33 | #define IRQ_NS9360_TIMER2 18 | ||
| 34 | #define IRQ_NS9360_TIMER3 19 | ||
| 35 | #define IRQ_NS9360_TIMER4 20 | ||
| 36 | #define IRQ_NS9360_TIMER5 21 | ||
| 37 | #define IRQ_NS9360_TIMER6 22 | ||
| 38 | #define IRQ_NS9360_TIMER7 23 | ||
| 39 | #define IRQ_NS9360_RTC 24 | ||
| 40 | #define IRQ_NS9360_USBHOST 25 | ||
| 41 | #define IRQ_NS9360_USBDEVICE 26 | ||
| 42 | #define IRQ_NS9360_IEEE1284 27 | ||
| 43 | #define IRQ_NS9XXX_EXT0 28 | ||
| 44 | #define IRQ_NS9XXX_EXT1 29 | ||
| 45 | #define IRQ_NS9XXX_EXT2 30 | ||
| 46 | #define IRQ_NS9XXX_EXT3 31 | ||
| 47 | |||
| 48 | #define BBUS_IRQ(irq) (32 + irq) | ||
| 49 | |||
| 50 | #define IRQ_BBUS_DMA BBUS_IRQ(0) | ||
| 51 | #define IRQ_BBUS_SERBRX BBUS_IRQ(2) | ||
| 52 | #define IRQ_BBUS_SERBTX BBUS_IRQ(3) | ||
| 53 | #define IRQ_BBUS_SERARX BBUS_IRQ(4) | ||
| 54 | #define IRQ_BBUS_SERATX BBUS_IRQ(5) | ||
| 55 | #define IRQ_BBUS_SERCRX BBUS_IRQ(6) | ||
| 56 | #define IRQ_BBUS_SERCTX BBUS_IRQ(7) | ||
| 57 | #define IRQ_BBUS_SERDRX BBUS_IRQ(8) | ||
| 58 | #define IRQ_BBUS_SERDTX BBUS_IRQ(9) | ||
| 59 | #define IRQ_BBUS_I2C BBUS_IRQ(10) | ||
| 60 | #define IRQ_BBUS_1284 BBUS_IRQ(11) | ||
| 61 | #define IRQ_BBUS_UTIL BBUS_IRQ(12) | ||
| 62 | #define IRQ_BBUS_RTC BBUS_IRQ(13) | ||
| 63 | #define IRQ_BBUS_USBHST BBUS_IRQ(14) | ||
| 64 | #define IRQ_BBUS_USBDEV BBUS_IRQ(15) | ||
| 65 | #define IRQ_BBUS_AHBDMA1 BBUS_IRQ(24) | ||
| 66 | #define IRQ_BBUS_AHBDMA2 BBUS_IRQ(25) | ||
| 67 | |||
| 68 | /* | ||
| 69 | * these Interrupts are specific for the a9m9750dev board. | ||
| 70 | * They are generated by an FPGA that interrupts the CPU on | ||
| 71 | * IRQ_NS9360_EXT2 | ||
| 72 | */ | ||
| 73 | #define FPGA_IRQ(irq) (64 + irq) | ||
| 74 | |||
| 75 | #define IRQ_FPGA_UARTA FPGA_IRQ(0) | ||
| 76 | #define IRQ_FPGA_UARTB FPGA_IRQ(1) | ||
| 77 | #define IRQ_FPGA_UARTC FPGA_IRQ(2) | ||
| 78 | #define IRQ_FPGA_UARTD FPGA_IRQ(3) | ||
| 79 | #define IRQ_FPGA_TOUCH FPGA_IRQ(4) | ||
| 80 | #define IRQ_FPGA_CF FPGA_IRQ(5) | ||
| 81 | #define IRQ_FPGA_CAN0 FPGA_IRQ(6) | ||
| 82 | #define IRQ_FPGA_CAN1 FPGA_IRQ(7) | ||
| 83 | |||
| 84 | #define NR_IRQS 72 | ||
| 85 | |||
| 86 | #endif /* __ASM_ARCH_IRQS_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/memory.h b/include/asm-arm/arch-ns9xxx/memory.h deleted file mode 100644 index ce1343e593e1..000000000000 --- a/include/asm-arm/arch-ns9xxx/memory.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 12 | #define __ASM_ARCH_MEMORY_H | ||
| 13 | |||
| 14 | /* x in [0..3] */ | ||
| 15 | #define NS9XXX_CSxSTAT_PHYS(x) UL(((x) + 4) << 28) | ||
| 16 | |||
| 17 | #define NS9XXX_CS0STAT_LENGTH UL(0x1000) | ||
| 18 | #define NS9XXX_CS1STAT_LENGTH UL(0x1000) | ||
| 19 | #define NS9XXX_CS2STAT_LENGTH UL(0x1000) | ||
| 20 | #define NS9XXX_CS3STAT_LENGTH UL(0x1000) | ||
| 21 | |||
| 22 | #define PHYS_OFFSET UL(0x00000000) | ||
| 23 | |||
| 24 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 25 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 26 | |||
| 27 | #endif | ||
diff --git a/include/asm-arm/arch-ns9xxx/module.h b/include/asm-arm/arch-ns9xxx/module.h deleted file mode 100644 index ac08a31111e4..000000000000 --- a/include/asm-arm/arch-ns9xxx/module.h +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/module.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_MODULE_H | ||
| 12 | #define __ASM_ARCH_MODULE_H | ||
| 13 | |||
| 14 | #include <asm/mach-types.h> | ||
| 15 | |||
| 16 | #define module_is_cc7ucamry() (0 \ | ||
| 17 | || machine_is_cc7ucamry() \ | ||
| 18 | ) | ||
| 19 | |||
| 20 | #define module_is_cc9c() (0 \ | ||
| 21 | || machine_is_cc9c() \ | ||
| 22 | ) | ||
| 23 | |||
| 24 | #define module_is_cc9p9210() (0 \ | ||
| 25 | || machine_is_cc9p9210() \ | ||
| 26 | || machine_is_cc9p9210js() \ | ||
| 27 | ) | ||
| 28 | |||
| 29 | #define module_is_cc9p9215() (0 \ | ||
| 30 | || machine_is_cc9p9215() \ | ||
| 31 | || machine_is_cc9p9215js() \ | ||
| 32 | ) | ||
| 33 | |||
| 34 | #define module_is_cc9p9360() (0 \ | ||
| 35 | || machine_is_a9m9360() \ | ||
| 36 | || machine_is_cc9p9360dev() \ | ||
| 37 | || machine_is_cc9p9360js() \ | ||
| 38 | || machine_is_cc9p9360val() \ | ||
| 39 | ) | ||
| 40 | |||
| 41 | #define module_is_cc9p9750() (0 \ | ||
| 42 | || machine_is_a9m9750() \ | ||
| 43 | || machine_is_cc9p9750dev() \ | ||
| 44 | || machine_is_cc9p9750js() \ | ||
| 45 | || machine_is_cc9p9750val() \ | ||
| 46 | ) | ||
| 47 | |||
| 48 | #define module_is_ccw9c() (0 \ | ||
| 49 | || machine_is_ccw9c() \ | ||
| 50 | ) | ||
| 51 | |||
| 52 | #define module_is_inc20otter() (0 \ | ||
| 53 | || machine_is_inc20otter() \ | ||
| 54 | ) | ||
| 55 | |||
| 56 | #define module_is_otter() (0 \ | ||
| 57 | || machine_is_otter() \ | ||
| 58 | ) | ||
| 59 | |||
| 60 | #endif /* ifndef __ASM_ARCH_MODULE_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/processor-ns9360.h b/include/asm-arm/arch-ns9xxx/processor-ns9360.h deleted file mode 100644 index f3aa6c50dbe5..000000000000 --- a/include/asm-arm/arch-ns9xxx/processor-ns9360.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/processor-ns9360.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_PROCESSORNS9360_H | ||
| 12 | #define __ASM_ARCH_PROCESSORNS9360_H | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | |||
| 16 | void ns9360_reset(char mode); | ||
| 17 | |||
| 18 | unsigned long ns9360_systemclock(void) __attribute__((const)); | ||
| 19 | |||
| 20 | static inline unsigned long ns9360_cpuclock(void) __attribute__((const)); | ||
| 21 | static inline unsigned long ns9360_cpuclock(void) | ||
| 22 | { | ||
| 23 | return ns9360_systemclock() / 2; | ||
| 24 | } | ||
| 25 | |||
| 26 | void __init ns9360_map_io(void); | ||
| 27 | |||
| 28 | extern struct sys_timer ns9360_timer; | ||
| 29 | |||
| 30 | int ns9360_gpio_configure(unsigned gpio, int inv, int func); | ||
| 31 | |||
| 32 | #endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/processor.h b/include/asm-arm/arch-ns9xxx/processor.h deleted file mode 100644 index 3137e5ba01a9..000000000000 --- a/include/asm-arm/arch-ns9xxx/processor.h +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/processor.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_PROCESSOR_H | ||
| 12 | #define __ASM_ARCH_PROCESSOR_H | ||
| 13 | |||
| 14 | #include <asm/arch/module.h> | ||
| 15 | |||
| 16 | #define processor_is_ns9210() (0 \ | ||
| 17 | || module_is_cc7ucamry() \ | ||
| 18 | || module_is_cc9p9210() \ | ||
| 19 | || module_is_inc20otter() \ | ||
| 20 | || module_is_otter() \ | ||
| 21 | ) | ||
| 22 | |||
| 23 | #define processor_is_ns9215() (0 \ | ||
| 24 | || module_is_cc9p9215() \ | ||
| 25 | ) | ||
| 26 | |||
| 27 | #define processor_is_ns9360() (0 \ | ||
| 28 | || module_is_cc9p9360() \ | ||
| 29 | || module_is_cc9c() \ | ||
| 30 | || module_is_ccw9c() \ | ||
| 31 | ) | ||
| 32 | |||
| 33 | #define processor_is_ns9750() (0 \ | ||
| 34 | || module_is_cc9p9750() \ | ||
| 35 | ) | ||
| 36 | |||
| 37 | #define processor_is_ns921x() (0 \ | ||
| 38 | || processor_is_ns9210() \ | ||
| 39 | || processor_is_ns9215() \ | ||
| 40 | ) | ||
| 41 | |||
| 42 | #endif /* ifndef __ASM_ARCH_PROCESSOR_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/regs-bbu.h b/include/asm-arm/arch-ns9xxx/regs-bbu.h deleted file mode 100644 index b41b31d04f03..000000000000 --- a/include/asm-arm/arch-ns9xxx/regs-bbu.h +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/regs-bbu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_REGSBBU_H | ||
| 12 | #define __ASM_ARCH_REGSBBU_H | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | /* BBus Utility */ | ||
| 17 | |||
| 18 | /* GPIO Configuration Registers block 1 */ | ||
| 19 | /* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is | ||
| 20 | * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register | ||
| 21 | * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */ | ||
| 22 | #define BBU_GCONFb1(x) __REG2(0x90600010, (x)) | ||
| 23 | #define BBU_GCONFb2(x) __REG2(0x90600100, (x)) | ||
| 24 | |||
| 25 | #define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2)) | ||
| 26 | #define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0) | ||
| 27 | #define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1) | ||
| 28 | #define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2)) | ||
| 29 | #define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0) | ||
| 30 | #define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1) | ||
| 31 | #define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2) | ||
| 32 | #define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0) | ||
| 33 | #define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1) | ||
| 34 | #define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2) | ||
| 35 | #define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3) | ||
| 36 | |||
| 37 | #define BBU_GCTRL1 __REG(0x90600030) | ||
| 38 | #define BBU_GCTRL2 __REG(0x90600034) | ||
| 39 | #define BBU_GCTRL3 __REG(0x90600120) | ||
| 40 | |||
| 41 | #define BBU_GSTAT1 __REG(0x90600040) | ||
| 42 | #define BBU_GSTAT2 __REG(0x90600044) | ||
| 43 | #define BBU_GSTAT3 __REG(0x90600130) | ||
| 44 | |||
| 45 | #endif /* ifndef __ASM_ARCH_REGSBBU_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h b/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h deleted file mode 100644 index 6bf1ed2ac3d2..000000000000 --- a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_REGSBOARDA9M9750_H | ||
| 12 | #define __ASM_ARCH_REGSBOARDA9M9750_H | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | #define FPGA_UARTA_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0)) | ||
| 17 | #define FPGA_UARTB_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08) | ||
| 18 | #define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10) | ||
| 19 | #define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18) | ||
| 20 | |||
| 21 | #define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50) | ||
| 22 | #define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60) | ||
| 23 | |||
| 24 | #endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/regs-mem.h b/include/asm-arm/arch-ns9xxx/regs-mem.h deleted file mode 100644 index 023f7be6f4c6..000000000000 --- a/include/asm-arm/arch-ns9xxx/regs-mem.h +++ /dev/null | |||
| @@ -1,135 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/regs-mem.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_REGSMEM_H | ||
| 12 | #define __ASM_ARCH_REGSMEM_H | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | /* Memory Module */ | ||
| 17 | |||
| 18 | /* Control register */ | ||
| 19 | #define MEM_CTRL __REG(0xa0700000) | ||
| 20 | |||
| 21 | /* Status register */ | ||
| 22 | #define MEM_STAT __REG(0xa0700004) | ||
| 23 | |||
| 24 | /* Configuration register */ | ||
| 25 | #define MEM_CONF __REG(0xa0700008) | ||
| 26 | |||
| 27 | /* Dynamic Memory Control register */ | ||
| 28 | #define MEM_DMCTRL __REG(0xa0700020) | ||
| 29 | |||
| 30 | /* Dynamic Memory Refresh Timer */ | ||
| 31 | #define MEM_DMRT __REG(0xa0700024) | ||
| 32 | |||
| 33 | /* Dynamic Memory Read Configuration register */ | ||
| 34 | #define MEM_DMRC __REG(0xa0700028) | ||
| 35 | |||
| 36 | /* Dynamic Memory Precharge Command Period (tRP) */ | ||
| 37 | #define MEM_DMPCP __REG(0xa0700030) | ||
| 38 | |||
| 39 | /* Dynamic Memory Active to Precharge Command Period (tRAS) */ | ||
| 40 | #define MEM_DMAPCP __REG(0xa0700034) | ||
| 41 | |||
| 42 | /* Dynamic Memory Self-Refresh Exit Time (tSREX) */ | ||
| 43 | #define MEM_DMSRET __REG(0xa0700038) | ||
| 44 | |||
| 45 | /* Dynamic Memory Last Data Out to Active Time (tAPR) */ | ||
| 46 | #define MEM_DMLDOAT __REG(0xa070003c) | ||
| 47 | |||
| 48 | /* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */ | ||
| 49 | #define MEM_DMDIACT __REG(0xa0700040) | ||
| 50 | |||
| 51 | /* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */ | ||
| 52 | #define MEM_DMWRT __REG(0xa0700044) | ||
| 53 | |||
| 54 | /* Dynamic Memory Active to Active Command Period (tRC) */ | ||
| 55 | #define MEM_DMAACP __REG(0xa0700048) | ||
| 56 | |||
| 57 | /* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */ | ||
| 58 | #define MEM_DMARP __REG(0xa070004c) | ||
| 59 | |||
| 60 | /* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */ | ||
| 61 | #define MEM_DMESRAC __REG(0xa0700050) | ||
| 62 | |||
| 63 | /* Dynamic Memory Active Bank A to Active B Time (tRRD) */ | ||
| 64 | #define MEM_DMABAABT __REG(0xa0700054) | ||
| 65 | |||
| 66 | /* Dynamic Memory Load Mode register to Active Command Time (tMRD) */ | ||
| 67 | #define MEM_DMLMACT __REG(0xa0700058) | ||
| 68 | |||
| 69 | /* Static Memory Extended Wait */ | ||
| 70 | #define MEM_SMEW __REG(0xa0700080) | ||
| 71 | |||
| 72 | /* Dynamic Memory Configuration Register x */ | ||
| 73 | #define MEM_DMCONF(x) __REG2(0xa0700100, (x) << 3) | ||
| 74 | |||
| 75 | /* Dynamic Memory RAS and CAS Delay x */ | ||
| 76 | #define MEM_DMRCD(x) __REG2(0xa0700104, (x) << 3) | ||
| 77 | |||
| 78 | /* Static Memory Configuration Register x */ | ||
| 79 | #define MEM_SMC(x) __REG2(0xa0700200, (x) << 3) | ||
| 80 | |||
| 81 | /* Static Memory Configuration Register x: Write protect */ | ||
| 82 | #define MEM_SMC_PSMC __REGBIT(20) | ||
| 83 | #define MEM_SMC_PSMC_OFF __REGVAL(MEM_SMC_PSMC, 0) | ||
| 84 | #define MEM_SMC_PSMC_ON __REGVAL(MEM_SMC_PSMC, 1) | ||
| 85 | |||
| 86 | /* Static Memory Configuration Register x: Buffer enable */ | ||
| 87 | #define MEM_SMC_BSMC __REGBIT(19) | ||
| 88 | #define MEM_SMC_BSMC_OFF __REGVAL(MEM_SMC_BSMC, 0) | ||
| 89 | #define MEM_SMC_BSMC_ON __REGVAL(MEM_SMC_BSMC, 1) | ||
| 90 | |||
| 91 | /* Static Memory Configuration Register x: Extended Wait */ | ||
| 92 | #define MEM_SMC_EW __REGBIT(8) | ||
| 93 | #define MEM_SMC_EW_OFF __REGVAL(MEM_SMC_EW, 0) | ||
| 94 | #define MEM_SMC_EW_ON __REGVAL(MEM_SMC_EW, 1) | ||
| 95 | |||
| 96 | /* Static Memory Configuration Register x: Byte lane state */ | ||
| 97 | #define MEM_SMC_PB __REGBIT(7) | ||
| 98 | #define MEM_SMC_PB_0 __REGVAL(MEM_SMC_PB, 0) | ||
| 99 | #define MEM_SMC_PB_1 __REGVAL(MEM_SMC_PB, 1) | ||
| 100 | |||
| 101 | /* Static Memory Configuration Register x: Chip select polarity */ | ||
| 102 | #define MEM_SMC_PC __REGBIT(6) | ||
| 103 | #define MEM_SMC_PC_AL __REGVAL(MEM_SMC_PC, 0) | ||
| 104 | #define MEM_SMC_PC_AH __REGVAL(MEM_SMC_PC, 1) | ||
| 105 | |||
| 106 | /* static memory configuration register x: page mode*/ | ||
| 107 | #define MEM_SMC_PM __REGBIT(3) | ||
| 108 | #define MEM_SMC_PM_DIS __REGVAL(MEM_SMC_PM, 0) | ||
| 109 | #define MEM_SMC_PM_ASYNC __REGVAL(MEM_SMC_PM, 1) | ||
| 110 | |||
| 111 | /* static memory configuration register x: Memory width */ | ||
| 112 | #define MEM_SMC_MW __REGBITS(1, 0) | ||
| 113 | #define MEM_SMC_MW_8 __REGVAL(MEM_SMC_MW, 0) | ||
| 114 | #define MEM_SMC_MW_16 __REGVAL(MEM_SMC_MW, 1) | ||
| 115 | #define MEM_SMC_MW_32 __REGVAL(MEM_SMC_MW, 2) | ||
| 116 | |||
| 117 | /* Static Memory Write Enable Delay x */ | ||
| 118 | #define MEM_SMWED(x) __REG2(0xa0700204, (x) << 3) | ||
| 119 | |||
| 120 | /* Static Memory Output Enable Delay x */ | ||
| 121 | #define MEM_SMOED(x) __REG2(0xa0700208, (x) << 3) | ||
| 122 | |||
| 123 | /* Static Memory Read Delay x */ | ||
| 124 | #define MEM_SMRD(x) __REG2(0xa070020c, (x) << 3) | ||
| 125 | |||
| 126 | /* Static Memory Page Mode Read Delay 0 */ | ||
| 127 | #define MEM_SMPMRD(x) __REG2(0xa0700210, (x) << 3) | ||
| 128 | |||
| 129 | /* Static Memory Write Delay */ | ||
| 130 | #define MEM_SMWD(x) __REG2(0xa0700214, (x) << 3) | ||
| 131 | |||
| 132 | /* Static Memory Turn Round Delay x */ | ||
| 133 | #define MEM_SWT(x) __REG2(0xa0700218, (x) << 3) | ||
| 134 | |||
| 135 | #endif /* ifndef __ASM_ARCH_REGSMEM_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys-common.h b/include/asm-arm/arch-ns9xxx/regs-sys-common.h deleted file mode 100644 index bc82d5ec2a88..000000000000 --- a/include/asm-arm/arch-ns9xxx/regs-sys-common.h +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/regs-sys-common.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_REGSSYSCOMMON_H | ||
| 13 | #define __ASM_ARCH_REGSSYSCOMMON_H | ||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | /* Interrupt Vector Address Register Level x */ | ||
| 17 | #define SYS_IVA(x) __REG2(0xa09000c4, (x)) | ||
| 18 | |||
| 19 | /* Interrupt Configuration registers */ | ||
| 20 | #define SYS_IC(x) __REG2(0xa0900144, (x)) | ||
| 21 | |||
| 22 | /* ISRADDR */ | ||
| 23 | #define SYS_ISRADDR __REG(0xa0900164) | ||
| 24 | |||
| 25 | /* Interrupt Status Active */ | ||
| 26 | #define SYS_ISA __REG(0xa0900168) | ||
| 27 | |||
| 28 | /* Interrupt Status Raw */ | ||
| 29 | #define SYS_ISR __REG(0xa090016c) | ||
| 30 | |||
| 31 | #endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h b/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h deleted file mode 100644 index 821275a88cb1..000000000000 --- a/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h +++ /dev/null | |||
| @@ -1,148 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_REGSSYSNS9360_H | ||
| 12 | #define __ASM_ARCH_REGSSYSNS9360_H | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | /* System Control Module */ | ||
| 17 | |||
| 18 | /* AHB Arbiter Gen Configuration */ | ||
| 19 | #define SYS_AHBAGENCONF __REG(0xa0900000) | ||
| 20 | |||
| 21 | /* BRC */ | ||
| 22 | #define SYS_BRC(x) __REG2(0xa0900004, (x)) | ||
| 23 | |||
| 24 | /* Timer x Reload Count register */ | ||
| 25 | #define SYS_TRC(x) __REG2(0xa0900044, (x)) | ||
| 26 | |||
| 27 | /* Timer x Read register */ | ||
| 28 | #define SYS_TR(x) __REG2(0xa0900084, (x)) | ||
| 29 | |||
| 30 | /* Timer Interrupt Status register */ | ||
| 31 | #define SYS_TIS __REG(0xa0900170) | ||
| 32 | |||
| 33 | /* PLL Configuration register */ | ||
| 34 | #define SYS_PLL __REG(0xa0900188) | ||
| 35 | |||
| 36 | /* PLL FS status */ | ||
| 37 | #define SYS_PLL_FS __REGBITS(24, 23) | ||
| 38 | |||
| 39 | /* PLL ND status */ | ||
| 40 | #define SYS_PLL_ND __REGBITS(20, 16) | ||
| 41 | |||
| 42 | /* PLL Configuration register: PLL SW change */ | ||
| 43 | #define SYS_PLL_SWC __REGBIT(15) | ||
| 44 | #define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0) | ||
| 45 | #define SYS_PLL_SWC_YES __REGVAL(SYS_PLL_SWC, 1) | ||
| 46 | |||
| 47 | /* Timer x Control register */ | ||
| 48 | #define SYS_TC(x) __REG2(0xa0900190, (x)) | ||
| 49 | |||
| 50 | /* Timer x Control register: Timer enable */ | ||
| 51 | #define SYS_TCx_TEN __REGBIT(15) | ||
| 52 | #define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0) | ||
| 53 | #define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1) | ||
| 54 | |||
| 55 | /* Timer x Control register: CPU debug mode */ | ||
| 56 | #define SYS_TCx_TDBG __REGBIT(10) | ||
| 57 | #define SYS_TCx_TDBG_CONT __REGVAL(SYS_TCx_TDBG, 0) | ||
| 58 | #define SYS_TCx_TDBG_STOP __REGVAL(SYS_TCx_TDBG, 1) | ||
| 59 | |||
| 60 | /* Timer x Control register: Interrupt clear */ | ||
| 61 | #define SYS_TCx_INTC __REGBIT(9) | ||
| 62 | #define SYS_TCx_INTC_UNSET __REGVAL(SYS_TCx_INTC, 0) | ||
| 63 | #define SYS_TCx_INTC_SET __REGVAL(SYS_TCx_INTC, 1) | ||
| 64 | |||
| 65 | /* Timer x Control register: Timer clock select */ | ||
| 66 | #define SYS_TCx_TLCS __REGBITS(8, 6) | ||
| 67 | #define SYS_TCx_TLCS_CPU __REGVAL(SYS_TCx_TLCS, 0) /* CPU clock */ | ||
| 68 | #define SYS_TCx_TLCS_DIV2 __REGVAL(SYS_TCx_TLCS, 1) /* CPU clock / 2 */ | ||
| 69 | #define SYS_TCx_TLCS_DIV4 __REGVAL(SYS_TCx_TLCS, 2) /* CPU clock / 4 */ | ||
| 70 | #define SYS_TCx_TLCS_DIV8 __REGVAL(SYS_TCx_TLCS, 3) /* CPU clock / 8 */ | ||
| 71 | #define SYS_TCx_TLCS_DIV16 __REGVAL(SYS_TCx_TLCS, 4) /* CPU clock / 16 */ | ||
| 72 | #define SYS_TCx_TLCS_DIV32 __REGVAL(SYS_TCx_TLCS, 5) /* CPU clock / 32 */ | ||
| 73 | #define SYS_TCx_TLCS_DIV64 __REGVAL(SYS_TCx_TLCS, 6) /* CPU clock / 64 */ | ||
| 74 | #define SYS_TCx_TLCS_EXT __REGVAL(SYS_TCx_TLCS, 7) | ||
| 75 | |||
| 76 | /* Timer x Control register: Timer mode */ | ||
| 77 | #define SYS_TCx_TM __REGBITS(5, 4) | ||
| 78 | #define SYS_TCx_TM_IEE __REGVAL(SYS_TCx_TM, 0) /* Internal timer or external event */ | ||
| 79 | #define SYS_TCx_TM_ELL __REGVAL(SYS_TCx_TM, 1) /* External low-level, gated timer */ | ||
| 80 | #define SYS_TCx_TM_EHL __REGVAL(SYS_TCx_TM, 2) /* External high-level, gated timer */ | ||
| 81 | #define SYS_TCx_TM_CONCAT __REGVAL(SYS_TCx_TM, 3) /* Concatenate the lower timer. */ | ||
| 82 | |||
| 83 | /* Timer x Control register: Interrupt select */ | ||
| 84 | #define SYS_TCx_INTS __REGBIT(3) | ||
| 85 | #define SYS_TCx_INTS_DIS __REGVAL(SYS_TCx_INTS, 0) | ||
| 86 | #define SYS_TCx_INTS_EN __REGVAL(SYS_TCx_INTS, 1) | ||
| 87 | |||
| 88 | /* Timer x Control register: Up/down select */ | ||
| 89 | #define SYS_TCx_UDS __REGBIT(2) | ||
| 90 | #define SYS_TCx_UDS_UP __REGVAL(SYS_TCx_UDS, 0) | ||
| 91 | #define SYS_TCx_UDS_DOWN __REGVAL(SYS_TCx_UDS, 1) | ||
| 92 | |||
| 93 | /* Timer x Control register: 32- or 16-bit timer */ | ||
| 94 | #define SYS_TCx_TSZ __REGBIT(1) | ||
| 95 | #define SYS_TCx_TSZ_16 __REGVAL(SYS_TCx_TSZ, 0) | ||
| 96 | #define SYS_TCx_TSZ_32 __REGVAL(SYS_TCx_TSZ, 1) | ||
| 97 | |||
| 98 | /* Timer x Control register: Reload enable */ | ||
| 99 | #define SYS_TCx_REN __REGBIT(0) | ||
| 100 | #define SYS_TCx_REN_DIS __REGVAL(SYS_TCx_REN, 0) | ||
| 101 | #define SYS_TCx_REN_EN __REGVAL(SYS_TCx_REN, 1) | ||
| 102 | |||
| 103 | /* System Memory Chip Select x Dynamic Memory Base */ | ||
| 104 | #define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1) | ||
| 105 | |||
| 106 | /* System Memory Chip Select x Dynamic Memory Mask */ | ||
| 107 | #define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1) | ||
| 108 | |||
| 109 | /* System Memory Chip Select x Static Memory Base */ | ||
| 110 | #define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1) | ||
| 111 | |||
| 112 | /* System Memory Chip Select x Static Memory Base: Chip select x base */ | ||
| 113 | #define SYS_SMCSSMB_CSxB __REGBITS(31, 12) | ||
| 114 | |||
| 115 | /* System Memory Chip Select x Static Memory Mask */ | ||
| 116 | #define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1) | ||
| 117 | |||
| 118 | /* System Memory Chip Select x Static Memory Mask: Chip select x mask */ | ||
| 119 | #define SYS_SMCSSMM_CSxM __REGBITS(31, 12) | ||
| 120 | |||
| 121 | /* System Memory Chip Select x Static Memory Mask: Chip select x enable */ | ||
| 122 | #define SYS_SMCSSMM_CSEx __REGBIT(0) | ||
| 123 | #define SYS_SMCSSMM_CSEx_DIS __REGVAL(SYS_SMCSSMM_CSEx, 0) | ||
| 124 | #define SYS_SMCSSMM_CSEx_EN __REGVAL(SYS_SMCSSMM_CSEx, 1) | ||
| 125 | |||
| 126 | /* General purpose, user-defined ID register */ | ||
| 127 | #define SYS_GENID __REG(0xa0900210) | ||
| 128 | |||
| 129 | /* External Interrupt x Control register */ | ||
| 130 | #define SYS_EIC(x) __REG2(0xa0900214, (x)) | ||
| 131 | |||
| 132 | /* External Interrupt x Control register: Status */ | ||
| 133 | #define SYS_EIC_STS __REGBIT(3) | ||
| 134 | |||
| 135 | /* External Interrupt x Control register: Clear */ | ||
| 136 | #define SYS_EIC_CLR __REGBIT(2) | ||
| 137 | |||
| 138 | /* External Interrupt x Control register: Polarity */ | ||
| 139 | #define SYS_EIC_PLTY __REGBIT(1) | ||
| 140 | #define SYS_EIC_PLTY_AH __REGVAL(SYS_EIC_PLTY, 0) | ||
| 141 | #define SYS_EIC_PLTY_AL __REGVAL(SYS_EIC_PLTY, 1) | ||
| 142 | |||
| 143 | /* External Interrupt x Control register: Level edge */ | ||
| 144 | #define SYS_EIC_LVEDG __REGBIT(0) | ||
| 145 | #define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0) | ||
| 146 | #define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1) | ||
| 147 | |||
| 148 | #endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/system.h b/include/asm-arm/arch-ns9xxx/system.h deleted file mode 100644 index c2941684d667..000000000000 --- a/include/asm-arm/arch-ns9xxx/system.h +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006,2007 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 12 | #define __ASM_ARCH_SYSTEM_H | ||
| 13 | |||
| 14 | #include <asm/proc-fns.h> | ||
| 15 | #include <asm/arch/processor.h> | ||
| 16 | #include <asm/arch/processor-ns9360.h> | ||
| 17 | |||
| 18 | static inline void arch_idle(void) | ||
| 19 | { | ||
| 20 | cpu_do_idle(); | ||
| 21 | } | ||
| 22 | |||
| 23 | static inline void arch_reset(char mode) | ||
| 24 | { | ||
| 25 | #ifdef CONFIG_PROCESSOR_NS9360 | ||
| 26 | if (processor_is_ns9360()) | ||
| 27 | ns9360_reset(mode); | ||
| 28 | else | ||
| 29 | #endif | ||
| 30 | BUG(); | ||
| 31 | |||
| 32 | BUG(); | ||
| 33 | } | ||
| 34 | |||
| 35 | #endif /* ifndef __ASM_ARCH_SYSTEM_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/timex.h b/include/asm-arm/arch-ns9xxx/timex.h deleted file mode 100644 index f776cbd2622d..000000000000 --- a/include/asm-arm/arch-ns9xxx/timex.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2006 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 12 | #define __ASM_ARCH_TIMEX_H | ||
| 13 | |||
| 14 | /* | ||
| 15 | * value for CLOCK_TICK_RATE stolen from include/asm-arm/arch-s3c2410/timex.h. | ||
| 16 | * See there for an explanation. | ||
| 17 | */ | ||
| 18 | #define CLOCK_TICK_RATE 12000000 | ||
| 19 | |||
| 20 | #endif /* ifndef __ASM_ARCH_TIMEX_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/uncompress.h b/include/asm-arm/arch-ns9xxx/uncompress.h deleted file mode 100644 index 71066baceab7..000000000000 --- a/include/asm-arm/arch-ns9xxx/uncompress.h +++ /dev/null | |||
| @@ -1,164 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
| 12 | #define __ASM_ARCH_UNCOMPRESS_H | ||
| 13 | |||
| 14 | #include <asm/io.h> | ||
| 15 | |||
| 16 | #define __REG(x) ((void __iomem __force *)(x)) | ||
| 17 | |||
| 18 | static void putc_dummy(char c, void __iomem *base) | ||
| 19 | { | ||
| 20 | /* nothing */ | ||
| 21 | } | ||
| 22 | |||
| 23 | static void putc_ns9360(char c, void __iomem *base) | ||
| 24 | { | ||
| 25 | static int t = 0x10000; | ||
| 26 | do { | ||
| 27 | if (t) | ||
| 28 | --t; | ||
| 29 | |||
| 30 | if (__raw_readl(base + 8) & (1 << 3)) { | ||
| 31 | __raw_writeb(c, base + 16); | ||
| 32 | t = 0x10000; | ||
| 33 | break; | ||
| 34 | } | ||
| 35 | } while (t); | ||
| 36 | } | ||
| 37 | |||
| 38 | static void putc_a9m9750dev(char c, void __iomem *base) | ||
| 39 | { | ||
| 40 | static int t = 0x10000; | ||
| 41 | do { | ||
| 42 | if (t) | ||
| 43 | --t; | ||
| 44 | |||
| 45 | if (__raw_readb(base + 5) & (1 << 5)) { | ||
| 46 | __raw_writeb(c, base); | ||
| 47 | t = 0x10000; | ||
| 48 | break; | ||
| 49 | } | ||
| 50 | } while (t); | ||
| 51 | |||
| 52 | } | ||
| 53 | |||
| 54 | static void putc_ns921x(char c, void __iomem *base) | ||
| 55 | { | ||
| 56 | static int t = 0x10000; | ||
| 57 | do { | ||
| 58 | if (t) | ||
| 59 | --t; | ||
| 60 | |||
| 61 | if (!(__raw_readl(base) & (1 << 11))) { | ||
| 62 | __raw_writeb(c, base + 0x0028); | ||
| 63 | t = 0x10000; | ||
| 64 | break; | ||
| 65 | } | ||
| 66 | } while (t); | ||
| 67 | } | ||
| 68 | |||
| 69 | #define MSCS __REG(0xA0900184) | ||
| 70 | |||
| 71 | #define NS9360_UARTA __REG(0x90200040) | ||
| 72 | #define NS9360_UARTB __REG(0x90200000) | ||
| 73 | #define NS9360_UARTC __REG(0x90300000) | ||
| 74 | #define NS9360_UARTD __REG(0x90300040) | ||
| 75 | |||
| 76 | #define NS9360_UART_ENABLED(base) \ | ||
| 77 | (__raw_readl(NS9360_UARTA) & (1 << 31)) | ||
| 78 | |||
| 79 | #define A9M9750DEV_UARTA __REG(0x40000000) | ||
| 80 | |||
| 81 | #define NS921XSYS_CLOCK __REG(0xa090017c) | ||
| 82 | #define NS921X_UARTA __REG(0x90010000) | ||
| 83 | #define NS921X_UARTB __REG(0x90018000) | ||
| 84 | #define NS921X_UARTC __REG(0x90020000) | ||
| 85 | #define NS921X_UARTD __REG(0x90028000) | ||
| 86 | |||
| 87 | #define NS921X_UART_ENABLED(base) \ | ||
| 88 | (__raw_readl((base) + 0x1000) & (1 << 29)) | ||
| 89 | |||
| 90 | static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base) | ||
| 91 | { | ||
| 92 | if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) { | ||
| 93 | /* ns9360 or ns9750 */ | ||
| 94 | if (NS9360_UART_ENABLED(NS9360_UARTA)) { | ||
| 95 | *putc = putc_ns9360; | ||
| 96 | *base = NS9360_UARTA; | ||
| 97 | return; | ||
| 98 | } else if (NS9360_UART_ENABLED(NS9360_UARTB)) { | ||
| 99 | *putc = putc_ns9360; | ||
| 100 | *base = NS9360_UARTB; | ||
| 101 | return; | ||
| 102 | } else if (NS9360_UART_ENABLED(NS9360_UARTC)) { | ||
| 103 | *putc = putc_ns9360; | ||
| 104 | *base = NS9360_UARTC; | ||
| 105 | return; | ||
| 106 | } else if (NS9360_UART_ENABLED(NS9360_UARTD)) { | ||
| 107 | *putc = putc_ns9360; | ||
| 108 | *base = NS9360_UARTD; | ||
| 109 | return; | ||
| 110 | } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) { | ||
| 111 | *putc = putc_a9m9750dev; | ||
| 112 | *base = A9M9750DEV_UARTA; | ||
| 113 | return; | ||
| 114 | } | ||
| 115 | } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) { | ||
| 116 | /* ns921x */ | ||
| 117 | u32 clock = __raw_readl(NS921XSYS_CLOCK); | ||
| 118 | |||
| 119 | if ((clock & (1 << 1)) && | ||
| 120 | NS921X_UART_ENABLED(NS921X_UARTA)) { | ||
| 121 | *putc = putc_ns921x; | ||
| 122 | *base = NS921X_UARTA; | ||
| 123 | return; | ||
| 124 | } else if ((clock & (1 << 2)) && | ||
| 125 | NS921X_UART_ENABLED(NS921X_UARTB)) { | ||
| 126 | *putc = putc_ns921x; | ||
| 127 | *base = NS921X_UARTB; | ||
| 128 | return; | ||
| 129 | } else if ((clock & (1 << 3)) && | ||
| 130 | NS921X_UART_ENABLED(NS921X_UARTC)) { | ||
| 131 | *putc = putc_ns921x; | ||
| 132 | *base = NS921X_UARTC; | ||
| 133 | return; | ||
| 134 | } else if ((clock & (1 << 4)) && | ||
| 135 | NS921X_UART_ENABLED(NS921X_UARTD)) { | ||
| 136 | *putc = putc_ns921x; | ||
| 137 | *base = NS921X_UARTD; | ||
| 138 | return; | ||
| 139 | } | ||
| 140 | } | ||
| 141 | |||
| 142 | *putc = putc_dummy; | ||
| 143 | } | ||
| 144 | |||
| 145 | void (*myputc)(char, void __iomem *); | ||
| 146 | void __iomem *base; | ||
| 147 | |||
| 148 | static void putc(char c) | ||
| 149 | { | ||
| 150 | myputc(c, base); | ||
| 151 | } | ||
| 152 | |||
| 153 | static void arch_decomp_setup(void) | ||
| 154 | { | ||
| 155 | autodetect(&myputc, &base); | ||
| 156 | } | ||
| 157 | #define arch_decomp_wdog() | ||
| 158 | |||
| 159 | static void flush(void) | ||
| 160 | { | ||
| 161 | /* nothing */ | ||
| 162 | } | ||
| 163 | |||
| 164 | #endif /* ifndef __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/include/asm-arm/arch-ns9xxx/vmalloc.h b/include/asm-arm/arch-ns9xxx/vmalloc.h deleted file mode 100644 index 2f3cb6f6be24..000000000000 --- a/include/asm-arm/arch-ns9xxx/vmalloc.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ns9xxx/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 by Digi International Inc. | ||
| 5 | * All rights reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ASM_ARCH_VMALLOC_H | ||
| 12 | #define __ASM_ARCH_VMALLOC_H | ||
| 13 | |||
| 14 | #define VMALLOC_END (0xf0000000) | ||
| 15 | |||
| 16 | #endif /* ifndef __ASM_ARCH_VMALLOC_H */ | ||
diff --git a/include/asm-arm/arch-omap/aic23.h b/include/asm-arm/arch-omap/aic23.h deleted file mode 100644 index aec2d6563622..000000000000 --- a/include/asm-arm/arch-omap/aic23.h +++ /dev/null | |||
| @@ -1,116 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/aic23.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI TLV320AIC23 audio codec | ||
| 5 | * | ||
| 6 | * Copyright (C) 2002 RidgeRun, Inc. | ||
| 7 | * Author: Steve Johnson | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | * | ||
| 14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License along | ||
| 26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 28 | */ | ||
| 29 | |||
| 30 | #ifndef __ASM_ARCH_AIC23_H | ||
| 31 | #define __ASM_ARCH_AIC23_H | ||
| 32 | |||
| 33 | // Codec TLV320AIC23 | ||
| 34 | #define LEFT_LINE_VOLUME_ADDR 0x00 | ||
| 35 | #define RIGHT_LINE_VOLUME_ADDR 0x01 | ||
| 36 | #define LEFT_CHANNEL_VOLUME_ADDR 0x02 | ||
| 37 | #define RIGHT_CHANNEL_VOLUME_ADDR 0x03 | ||
| 38 | #define ANALOG_AUDIO_CONTROL_ADDR 0x04 | ||
| 39 | #define DIGITAL_AUDIO_CONTROL_ADDR 0x05 | ||
| 40 | #define POWER_DOWN_CONTROL_ADDR 0x06 | ||
| 41 | #define DIGITAL_AUDIO_FORMAT_ADDR 0x07 | ||
| 42 | #define SAMPLE_RATE_CONTROL_ADDR 0x08 | ||
| 43 | #define DIGITAL_INTERFACE_ACT_ADDR 0x09 | ||
| 44 | #define RESET_CONTROL_ADDR 0x0F | ||
| 45 | |||
| 46 | // Left (right) line input volume control register | ||
| 47 | #define LRS_ENABLED 0x0100 | ||
| 48 | #define LIM_MUTED 0x0080 | ||
| 49 | #define LIV_DEFAULT 0x0017 | ||
| 50 | #define LIV_MAX 0x001f | ||
| 51 | #define LIV_MIN 0x0000 | ||
| 52 | |||
| 53 | // Left (right) channel headphone volume control register | ||
| 54 | #define LZC_ON 0x0080 | ||
| 55 | #define LHV_DEFAULT 0x0079 | ||
| 56 | #define LHV_MAX 0x007f | ||
| 57 | #define LHV_MIN 0x0000 | ||
| 58 | |||
| 59 | // Analog audio path control register | ||
| 60 | #define STA_REG(x) ((x)<<6) | ||
| 61 | #define STE_ENABLED 0x0020 | ||
| 62 | #define DAC_SELECTED 0x0010 | ||
| 63 | #define BYPASS_ON 0x0008 | ||
| 64 | #define INSEL_MIC 0x0004 | ||
| 65 | #define MICM_MUTED 0x0002 | ||
| 66 | #define MICB_20DB 0x0001 | ||
| 67 | |||
| 68 | // Digital audio path control register | ||
| 69 | #define DACM_MUTE 0x0008 | ||
| 70 | #define DEEMP_32K 0x0002 | ||
| 71 | #define DEEMP_44K 0x0004 | ||
| 72 | #define DEEMP_48K 0x0006 | ||
| 73 | #define ADCHP_ON 0x0001 | ||
| 74 | |||
| 75 | // Power control down register | ||
| 76 | #define DEVICE_POWER_OFF 0x0080 | ||
| 77 | #define CLK_OFF 0x0040 | ||
| 78 | #define OSC_OFF 0x0020 | ||
| 79 | #define OUT_OFF 0x0010 | ||
| 80 | #define DAC_OFF 0x0008 | ||
| 81 | #define ADC_OFF 0x0004 | ||
| 82 | #define MIC_OFF 0x0002 | ||
| 83 | #define LINE_OFF 0x0001 | ||
| 84 | |||
| 85 | // Digital audio interface register | ||
| 86 | #define MS_MASTER 0x0040 | ||
| 87 | #define LRSWAP_ON 0x0020 | ||
| 88 | #define LRP_ON 0x0010 | ||
| 89 | #define IWL_16 0x0000 | ||
| 90 | #define IWL_20 0x0004 | ||
| 91 | #define IWL_24 0x0008 | ||
| 92 | #define IWL_32 0x000C | ||
| 93 | #define FOR_I2S 0x0002 | ||
| 94 | #define FOR_DSP 0x0003 | ||
| 95 | |||
| 96 | // Sample rate control register | ||
| 97 | #define CLKOUT_HALF 0x0080 | ||
| 98 | #define CLKIN_HALF 0x0040 | ||
| 99 | #define BOSR_384fs 0x0002 // BOSR_272fs when in USB mode | ||
| 100 | #define USB_CLK_ON 0x0001 | ||
| 101 | #define SR_MASK 0xf | ||
| 102 | #define CLKOUT_SHIFT 7 | ||
| 103 | #define CLKIN_SHIFT 6 | ||
| 104 | #define SR_SHIFT 2 | ||
| 105 | #define BOSR_SHIFT 1 | ||
| 106 | |||
| 107 | // Digital interface register | ||
| 108 | #define ACT_ON 0x0001 | ||
| 109 | |||
| 110 | #define TLV320AIC23ID1 (0x1a) // cs low | ||
| 111 | #define TLV320AIC23ID2 (0x1b) // cs high | ||
| 112 | |||
| 113 | void aic23_power_up(void); | ||
| 114 | void aic23_power_down(void); | ||
| 115 | |||
| 116 | #endif /* __ASM_ARCH_AIC23_H */ | ||
diff --git a/include/asm-arm/arch-omap/blizzard.h b/include/asm-arm/arch-omap/blizzard.h deleted file mode 100644 index 8d160f171372..000000000000 --- a/include/asm-arm/arch-omap/blizzard.h +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | #ifndef _BLIZZARD_H | ||
| 2 | #define _BLIZZARD_H | ||
| 3 | |||
| 4 | struct blizzard_platform_data { | ||
| 5 | void (*power_up)(struct device *dev); | ||
| 6 | void (*power_down)(struct device *dev); | ||
| 7 | unsigned long (*get_clock_rate)(struct device *dev); | ||
| 8 | |||
| 9 | unsigned te_connected : 1; | ||
| 10 | }; | ||
| 11 | |||
| 12 | #endif | ||
diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h deleted file mode 100644 index c7db9004ec31..000000000000 --- a/include/asm-arm/arch-omap/board-2430sdp.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-2430sdp.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP2430 SDP board. | ||
| 5 | * | ||
| 6 | * Based on board-h4.h by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_2430SDP_H | ||
| 30 | #define __ASM_ARCH_OMAP_2430SDP_H | ||
| 31 | |||
| 32 | /* Placeholder for 2430SDP specific defines */ | ||
| 33 | #define OMAP24XX_ETHR_START 0x08000300 | ||
| 34 | #define OMAP24XX_ETHR_GPIO_IRQ 149 | ||
| 35 | #define SDP2430_CS0_BASE 0x04000000 | ||
| 36 | |||
| 37 | #define TWL4030_IRQNUM INT_24XX_SYS_NIRQ | ||
| 38 | |||
| 39 | #endif /* __ASM_ARCH_OMAP_2430SDP_H */ | ||
diff --git a/include/asm-arm/arch-omap/board-ams-delta.h b/include/asm-arm/arch-omap/board-ams-delta.h deleted file mode 100644 index 9aee15d97145..000000000000 --- a/include/asm-arm/arch-omap/board-ams-delta.h +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-ams-delta.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | * | ||
| 11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License along | ||
| 23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 25 | */ | ||
| 26 | #ifndef __ASM_ARCH_OMAP_AMS_DELTA_H | ||
| 27 | #define __ASM_ARCH_OMAP_AMS_DELTA_H | ||
| 28 | |||
| 29 | #if defined (CONFIG_MACH_AMS_DELTA) | ||
| 30 | |||
| 31 | #define AMS_DELTA_LATCH1_PHYS 0x01000000 | ||
| 32 | #define AMS_DELTA_LATCH1_VIRT 0xEA000000 | ||
| 33 | #define AMS_DELTA_MODEM_PHYS 0x04000000 | ||
| 34 | #define AMS_DELTA_MODEM_VIRT 0xEB000000 | ||
| 35 | #define AMS_DELTA_LATCH2_PHYS 0x08000000 | ||
| 36 | #define AMS_DELTA_LATCH2_VIRT 0xEC000000 | ||
| 37 | |||
| 38 | #define AMS_DELTA_LATCH1_LED_CAMERA 0x01 | ||
| 39 | #define AMS_DELTA_LATCH1_LED_ADVERT 0x02 | ||
| 40 | #define AMS_DELTA_LATCH1_LED_EMAIL 0x04 | ||
| 41 | #define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08 | ||
| 42 | #define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10 | ||
| 43 | #define AMS_DELTA_LATCH1_LED_VOICE 0x20 | ||
| 44 | |||
| 45 | #define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001 | ||
| 46 | #define AMS_DELTA_LATCH2_LCD_NDISP 0x0002 | ||
| 47 | #define AMS_DELTA_LATCH2_NAND_NCE 0x0004 | ||
| 48 | #define AMS_DELTA_LATCH2_NAND_NRE 0x0008 | ||
| 49 | #define AMS_DELTA_LATCH2_NAND_NWP 0x0010 | ||
| 50 | #define AMS_DELTA_LATCH2_NAND_NWE 0x0020 | ||
| 51 | #define AMS_DELTA_LATCH2_NAND_ALE 0x0040 | ||
| 52 | #define AMS_DELTA_LATCH2_NAND_CLE 0x0080 | ||
| 53 | #define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100 | ||
| 54 | #define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200 | ||
| 55 | #define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400 | ||
| 56 | #define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800 | ||
| 57 | #define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000 | ||
| 58 | #define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000 | ||
| 59 | |||
| 60 | #define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0 | ||
| 61 | #define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1 | ||
| 62 | #define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2 | ||
| 63 | #define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4 | ||
| 64 | #define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6 | ||
| 65 | #define AMS_DELTA_GPIO_PIN_SCARD_IO 7 | ||
| 66 | #define AMS_DELTA_GPIO_PIN_CONFIG 11 | ||
| 67 | #define AMS_DELTA_GPIO_PIN_NAND_RB 12 | ||
| 68 | |||
| 69 | #ifndef __ASSEMBLY__ | ||
| 70 | void ams_delta_latch1_write(u8 mask, u8 value); | ||
| 71 | void ams_delta_latch2_write(u16 mask, u16 value); | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #endif /* CONFIG_MACH_AMS_DELTA */ | ||
| 75 | |||
| 76 | #endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */ | ||
diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h deleted file mode 100644 index 547125a4695e..000000000000 --- a/include/asm-arm/arch-omap/board-apollon.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-apollon.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for Samsung OMAP24XX Apollon board. | ||
| 5 | * | ||
| 6 | * Initial creation by Kyungmin Park <kyungmin.park@samsung.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_APOLLON_H | ||
| 30 | #define __ASM_ARCH_OMAP_APOLLON_H | ||
| 31 | |||
| 32 | extern void apollon_mmc_init(void); | ||
| 33 | |||
| 34 | /* Placeholder for APOLLON specific defines */ | ||
| 35 | #define APOLLON_ETHR_GPIO_IRQ 74 | ||
| 36 | |||
| 37 | #endif /* __ASM_ARCH_OMAP_APOLLON_H */ | ||
| 38 | |||
diff --git a/include/asm-arm/arch-omap/board-fsample.h b/include/asm-arm/arch-omap/board-fsample.h deleted file mode 100644 index 89a1e529fb6f..000000000000 --- a/include/asm-arm/arch-omap/board-fsample.h +++ /dev/null | |||
| @@ -1,51 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-fsample.h | ||
| 3 | * | ||
| 4 | * Board-specific goodies for TI F-Sample. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2006 Google, Inc. | ||
| 7 | * Author: Brian Swetland <swetland@google.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_OMAP_FSAMPLE_H | ||
| 15 | #define __ASM_ARCH_OMAP_FSAMPLE_H | ||
| 16 | |||
| 17 | /* fsample is pretty close to p2-sample */ | ||
| 18 | #include <asm/arch/board-perseus2.h> | ||
| 19 | |||
| 20 | #define fsample_cpld_read(reg) __raw_readb(reg) | ||
| 21 | #define fsample_cpld_write(val, reg) __raw_writeb(val, reg) | ||
| 22 | |||
| 23 | #define FSAMPLE_CPLD_BASE 0xE8100000 | ||
| 24 | #define FSAMPLE_CPLD_SIZE SZ_4K | ||
| 25 | #define FSAMPLE_CPLD_START 0x05080000 | ||
| 26 | |||
| 27 | #define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00) | ||
| 28 | #define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02) | ||
| 29 | #define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02) | ||
| 30 | #define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04) | ||
| 31 | #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06) | ||
| 32 | #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06) | ||
| 33 | |||
| 34 | #define FSAMPLE_CPLD_BIT_BT_RESET 0 | ||
| 35 | #define FSAMPLE_CPLD_BIT_LCD_RESET 1 | ||
| 36 | #define FSAMPLE_CPLD_BIT_CAM_PWDN 2 | ||
| 37 | #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3 | ||
| 38 | #define FSAMPLE_CPLD_BIT_SD_MMC_EN 4 | ||
| 39 | #define FSAMPLE_CPLD_BIT_aGPS_PWREN 5 | ||
| 40 | #define FSAMPLE_CPLD_BIT_BACKLIGHT 6 | ||
| 41 | #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7 | ||
| 42 | #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8 | ||
| 43 | #define FSAMPLE_CPLD_BIT_OTG_RESET 9 | ||
| 44 | |||
| 45 | #define fsample_cpld_set(bit) \ | ||
| 46 | fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR) | ||
| 47 | |||
| 48 | #define fsample_cpld_clear(bit) \ | ||
| 49 | fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR) | ||
| 50 | |||
| 51 | #endif | ||
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h deleted file mode 100644 index c322796d0d26..000000000000 --- a/include/asm-arm/arch-omap/board-h2.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-h2.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP1610 H2 board. | ||
| 5 | * | ||
| 6 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_H2_H | ||
| 30 | #define __ASM_ARCH_OMAP_H2_H | ||
| 31 | |||
| 32 | /* Placeholder for H2 specific defines */ | ||
| 33 | |||
| 34 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | ||
| 35 | #define OMAP1610_ETHR_START 0x04000300 | ||
| 36 | |||
| 37 | extern void h2_mmc_init(void); | ||
| 38 | extern void h2_mmc_slot_cover_handler(void *arg, int state); | ||
| 39 | |||
| 40 | #endif /* __ASM_ARCH_OMAP_H2_H */ | ||
| 41 | |||
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h deleted file mode 100644 index c5d0f32a40ac..000000000000 --- a/include/asm-arm/arch-omap/board-h3.h +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-h3.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 RidgeRun, Inc. | ||
| 5 | * Copyright (C) 2004 Texas Instruments, Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License along | ||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 26 | */ | ||
| 27 | #ifndef __ASM_ARCH_OMAP_H3_H | ||
| 28 | #define __ASM_ARCH_OMAP_H3_H | ||
| 29 | |||
| 30 | /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ | ||
| 31 | #define OMAP1710_ETHR_START 0x04000300 | ||
| 32 | |||
| 33 | extern void h3_mmc_init(void); | ||
| 34 | extern void h3_mmc_slot_cover_handler(void *arg, int state); | ||
| 35 | |||
| 36 | #endif /* __ASM_ARCH_OMAP_H3_H */ | ||
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h deleted file mode 100644 index 7e0efef4bb65..000000000000 --- a/include/asm-arm/arch-omap/board-h4.h +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-h4.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP1610 H4 board. | ||
| 5 | * | ||
| 6 | * Initial creation by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_H4_H | ||
| 30 | #define __ASM_ARCH_OMAP_H4_H | ||
| 31 | |||
| 32 | /* Placeholder for H4 specific defines */ | ||
| 33 | #define OMAP24XX_ETHR_GPIO_IRQ 92 | ||
| 34 | #endif /* __ASM_ARCH_OMAP_H4_H */ | ||
| 35 | |||
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h deleted file mode 100644 index 9ca03dec9d36..000000000000 --- a/include/asm-arm/arch-omap/board-innovator.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-innovator.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 RidgeRun, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | * | ||
| 11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License along | ||
| 23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 25 | */ | ||
| 26 | #ifndef __ASM_ARCH_OMAP_INNOVATOR_H | ||
| 27 | #define __ASM_ARCH_OMAP_INNOVATOR_H | ||
| 28 | |||
| 29 | #if defined (CONFIG_ARCH_OMAP15XX) | ||
| 30 | |||
| 31 | #ifndef OMAP_SDRAM_DEVICE | ||
| 32 | #define OMAP_SDRAM_DEVICE D256M_1X16_4B | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #define OMAP1510P1_IMIF_PRI_VALUE 0x00 | ||
| 36 | #define OMAP1510P1_EMIFS_PRI_VALUE 0x00 | ||
| 37 | #define OMAP1510P1_EMIFF_PRI_VALUE 0x00 | ||
| 38 | |||
| 39 | #ifndef __ASSEMBLY__ | ||
| 40 | void fpga_write(unsigned char val, int reg); | ||
| 41 | unsigned char fpga_read(int reg); | ||
| 42 | #endif | ||
| 43 | |||
| 44 | #endif /* CONFIG_ARCH_OMAP15XX */ | ||
| 45 | |||
| 46 | #if defined (CONFIG_ARCH_OMAP16XX) | ||
| 47 | |||
| 48 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | ||
| 49 | #define INNOVATOR1610_ETHR_START 0x04000300 | ||
| 50 | |||
| 51 | #endif /* CONFIG_ARCH_OMAP1610 */ | ||
| 52 | #endif /* __ASM_ARCH_OMAP_INNOVATOR_H */ | ||
diff --git a/include/asm-arm/arch-omap/board-nokia.h b/include/asm-arm/arch-omap/board-nokia.h deleted file mode 100644 index 72deea203493..000000000000 --- a/include/asm-arm/arch-omap/board-nokia.h +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-nokia.h | ||
| 3 | * | ||
| 4 | * Information structures for Nokia-specific board config data | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005 Nokia Corporation | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _OMAP_BOARD_NOKIA_H | ||
| 10 | #define _OMAP_BOARD_NOKIA_H | ||
| 11 | |||
| 12 | #include <linux/types.h> | ||
| 13 | |||
| 14 | #define OMAP_TAG_NOKIA_BT 0x4e01 | ||
| 15 | #define OMAP_TAG_WLAN_CX3110X 0x4e02 | ||
| 16 | #define OMAP_TAG_CBUS 0x4e03 | ||
| 17 | #define OMAP_TAG_EM_ASIC_BB5 0x4e04 | ||
| 18 | |||
| 19 | |||
| 20 | #define BT_CHIP_CSR 1 | ||
| 21 | #define BT_CHIP_TI 2 | ||
| 22 | |||
| 23 | #define BT_SYSCLK_12 1 | ||
| 24 | #define BT_SYSCLK_38_4 2 | ||
| 25 | |||
| 26 | struct omap_bluetooth_config { | ||
| 27 | u8 chip_type; | ||
| 28 | u8 bt_wakeup_gpio; | ||
| 29 | u8 host_wakeup_gpio; | ||
| 30 | u8 reset_gpio; | ||
| 31 | u8 bt_uart; | ||
| 32 | u8 bd_addr[6]; | ||
| 33 | u8 bt_sysclk; | ||
| 34 | }; | ||
| 35 | |||
| 36 | struct omap_wlan_cx3110x_config { | ||
| 37 | u8 chip_type; | ||
| 38 | s16 power_gpio; | ||
| 39 | s16 irq_gpio; | ||
| 40 | s16 spi_cs_gpio; | ||
| 41 | }; | ||
| 42 | |||
| 43 | struct omap_cbus_config { | ||
| 44 | s16 clk_gpio; | ||
| 45 | s16 dat_gpio; | ||
| 46 | s16 sel_gpio; | ||
| 47 | }; | ||
| 48 | |||
| 49 | struct omap_em_asic_bb5_config { | ||
| 50 | s16 retu_irq_gpio; | ||
| 51 | s16 tahvo_irq_gpio; | ||
| 52 | }; | ||
| 53 | |||
| 54 | #endif | ||
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h deleted file mode 100644 index 94926090e475..000000000000 --- a/include/asm-arm/arch-omap/board-osk.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-osk.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP5912 OSK board. | ||
| 5 | * | ||
| 6 | * Written by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_OSK_H | ||
| 30 | #define __ASM_ARCH_OMAP_OSK_H | ||
| 31 | |||
| 32 | /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ | ||
| 33 | #define OMAP_OSK_ETHR_START 0x04800300 | ||
| 34 | |||
| 35 | /* TPS65010 has four GPIOs. nPG and LED2 can be treated like GPIOs with | ||
| 36 | * alternate pin configurations for hardware-controlled blinking. | ||
| 37 | */ | ||
| 38 | #define OSK_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) | ||
| 39 | # define OSK_TPS_GPIO_USB_PWR_EN (OSK_TPS_GPIO_BASE + 0) | ||
| 40 | # define OSK_TPS_GPIO_LED_D3 (OSK_TPS_GPIO_BASE + 1) | ||
| 41 | # define OSK_TPS_GPIO_LAN_RESET (OSK_TPS_GPIO_BASE + 2) | ||
| 42 | # define OSK_TPS_GPIO_DSP_PWR_EN (OSK_TPS_GPIO_BASE + 3) | ||
| 43 | # define OSK_TPS_GPIO_LED_D9 (OSK_TPS_GPIO_BASE + 4) | ||
| 44 | # define OSK_TPS_GPIO_LED_D2 (OSK_TPS_GPIO_BASE + 5) | ||
| 45 | |||
| 46 | #endif /* __ASM_ARCH_OMAP_OSK_H */ | ||
| 47 | |||
diff --git a/include/asm-arm/arch-omap/board-palmte.h b/include/asm-arm/arch-omap/board-palmte.h deleted file mode 100644 index 6fac2c8935be..000000000000 --- a/include/asm-arm/arch-omap/board-palmte.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-palmte.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for the Palm Tungsten E device. | ||
| 5 | * | ||
| 6 | * Maintainters : http://palmtelinux.sf.net | ||
| 7 | * palmtelinux-developpers@lists.sf.net | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __OMAP_BOARD_PALMTE_H | ||
| 15 | #define __OMAP_BOARD_PALMTE_H | ||
| 16 | |||
| 17 | #define PALMTE_USBDETECT_GPIO 0 | ||
| 18 | #define PALMTE_USB_OR_DC_GPIO 1 | ||
| 19 | #define PALMTE_TSC_GPIO 4 | ||
| 20 | #define PALMTE_PINTDAV_GPIO 6 | ||
| 21 | #define PALMTE_MMC_WP_GPIO 8 | ||
| 22 | #define PALMTE_MMC_POWER_GPIO 9 | ||
| 23 | #define PALMTE_HDQ_GPIO 11 | ||
| 24 | #define PALMTE_HEADPHONES_GPIO 14 | ||
| 25 | #define PALMTE_SPEAKER_GPIO 15 | ||
| 26 | #define PALMTE_DC_GPIO OMAP_MPUIO(2) | ||
| 27 | #define PALMTE_MMC_SWITCH_GPIO OMAP_MPUIO(4) | ||
| 28 | #define PALMTE_MMC1_GPIO OMAP_MPUIO(6) | ||
| 29 | #define PALMTE_MMC2_GPIO OMAP_MPUIO(7) | ||
| 30 | #define PALMTE_MMC3_GPIO OMAP_MPUIO(11) | ||
| 31 | |||
| 32 | #endif /* __OMAP_BOARD_PALMTE_H */ | ||
diff --git a/include/asm-arm/arch-omap/board-palmtt.h b/include/asm-arm/arch-omap/board-palmtt.h deleted file mode 100644 index d9590b0ec90e..000000000000 --- a/include/asm-arm/arch-omap/board-palmtt.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-palmte.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for the Palm Tungsten|T device. | ||
| 5 | * | ||
| 6 | * Maintainters : Marek Vasut <marek.vasut@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __OMAP_BOARD_PALMTT_H | ||
| 14 | #define __OMAP_BOARD_PALMTT_H | ||
| 15 | |||
| 16 | #define PALMTT_USBDETECT_GPIO 0 | ||
| 17 | #define PALMTT_CABLE_GPIO 1 | ||
| 18 | #define PALMTT_LED_GPIO 3 | ||
| 19 | #define PALMTT_PENIRQ_GPIO 6 | ||
| 20 | #define PALMTT_MMC_WP_GPIO 8 | ||
| 21 | #define PALMTT_HDQ_GPIO 11 | ||
| 22 | |||
| 23 | #endif /* __OMAP_BOARD_PALMTT_H */ | ||
diff --git a/include/asm-arm/arch-omap/board-palmz71.h b/include/asm-arm/arch-omap/board-palmz71.h deleted file mode 100644 index 1252a859787d..000000000000 --- a/include/asm-arm/arch-omap/board-palmz71.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-palmz71.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for the Palm Zire71 device. | ||
| 5 | * | ||
| 6 | * Maintainters : Marek Vasut <marek.vasut@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __OMAP_BOARD_PALMZ71_H | ||
| 14 | #define __OMAP_BOARD_PALMZ71_H | ||
| 15 | |||
| 16 | #define PALMZ71_USBDETECT_GPIO 0 | ||
| 17 | #define PALMZ71_PENIRQ_GPIO 6 | ||
| 18 | #define PALMZ71_MMC_WP_GPIO 8 | ||
| 19 | #define PALMZ71_HDQ_GPIO 11 | ||
| 20 | |||
| 21 | #define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1) | ||
| 22 | #define PALMZ71_CABLE_GPIO OMAP_MPUIO(2) | ||
| 23 | #define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3) | ||
| 24 | #define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4) | ||
| 25 | |||
| 26 | #endif /* __OMAP_BOARD_PALMZ71_H */ | ||
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h deleted file mode 100644 index d7429cb0f726..000000000000 --- a/include/asm-arm/arch-omap/board-perseus2.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board-perseus2.h | ||
| 3 | * | ||
| 4 | * Copyright 2003 by Texas Instruments Incorporated | ||
| 5 | * OMAP730 / Perseus2 support by Jean Pihet | ||
| 6 | * | ||
| 7 | * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) | ||
| 8 | * Author: RidgeRun, Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License along | ||
| 27 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 29 | */ | ||
| 30 | #ifndef __ASM_ARCH_OMAP_PERSEUS2_H | ||
| 31 | #define __ASM_ARCH_OMAP_PERSEUS2_H | ||
| 32 | |||
| 33 | #include <asm/arch/fpga.h> | ||
| 34 | |||
| 35 | #ifndef OMAP_SDRAM_DEVICE | ||
| 36 | #define OMAP_SDRAM_DEVICE D256M_1X16_4B | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-omap/board-sx1.h b/include/asm-arm/arch-omap/board-sx1.h deleted file mode 100644 index 355adbdaae33..000000000000 --- a/include/asm-arm/arch-omap/board-sx1.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Siemens SX1 board definitions | ||
| 3 | * | ||
| 4 | * Copyright: Vovan888 at gmail com | ||
| 5 | * | ||
| 6 | * This package is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR | ||
| 11 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED | ||
| 12 | * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_SX1_I2C_CHIPS_H | ||
| 16 | #define __ASM_ARCH_SX1_I2C_CHIPS_H | ||
| 17 | |||
| 18 | #define SOFIA_MAX_LIGHT_VAL 0x2B | ||
| 19 | |||
| 20 | #define SOFIA_I2C_ADDR 0x32 | ||
| 21 | /* Sofia reg 3 bits masks */ | ||
| 22 | #define SOFIA_POWER1_REG 0x03 | ||
| 23 | |||
| 24 | #define SOFIA_USB_POWER 0x01 | ||
| 25 | #define SOFIA_MMC_POWER 0x04 | ||
| 26 | #define SOFIA_BLUETOOTH_POWER 0x08 | ||
| 27 | #define SOFIA_MMILIGHT_POWER 0x20 | ||
| 28 | |||
| 29 | #define SOFIA_POWER2_REG 0x04 | ||
| 30 | #define SOFIA_BACKLIGHT_REG 0x06 | ||
| 31 | #define SOFIA_KEYLIGHT_REG 0x07 | ||
| 32 | #define SOFIA_DIMMING_REG 0x09 | ||
| 33 | |||
| 34 | |||
| 35 | /* Function Prototypes for SX1 devices control on I2C bus */ | ||
| 36 | |||
| 37 | int sx1_setbacklight(u8 backlight); | ||
| 38 | int sx1_getbacklight(u8 *backlight); | ||
| 39 | int sx1_setkeylight(u8 keylight); | ||
| 40 | int sx1_getkeylight(u8 *keylight); | ||
| 41 | |||
| 42 | int sx1_setmmipower(u8 onoff); | ||
| 43 | int sx1_setusbpower(u8 onoff); | ||
| 44 | int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value); | ||
| 45 | int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value); | ||
| 46 | |||
| 47 | /* MMC prototypes */ | ||
| 48 | |||
| 49 | extern void sx1_mmc_init(void); | ||
| 50 | extern void sx1_mmc_slot_cover_handler(void *arg, int state); | ||
| 51 | |||
| 52 | #endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */ | ||
diff --git a/include/asm-arm/arch-omap/board-voiceblue.h b/include/asm-arm/arch-omap/board-voiceblue.h deleted file mode 100644 index ed6d346ee123..000000000000 --- a/include/asm-arm/arch-omap/board-voiceblue.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz> | ||
| 3 | * | ||
| 4 | * Hardware definitions for OMAP5910 based VoiceBlue board. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_VOICEBLUE_H | ||
| 12 | #define __ASM_ARCH_VOICEBLUE_H | ||
| 13 | |||
| 14 | extern void voiceblue_wdt_enable(void); | ||
| 15 | extern void voiceblue_wdt_disable(void); | ||
| 16 | extern void voiceblue_wdt_ping(void); | ||
| 17 | extern void voiceblue_reset(void); | ||
| 18 | |||
| 19 | #endif /* __ASM_ARCH_VOICEBLUE_H */ | ||
| 20 | |||
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h deleted file mode 100644 index 99564c70f128..000000000000 --- a/include/asm-arm/arch-omap/board.h +++ /dev/null | |||
| @@ -1,186 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/board.h | ||
| 3 | * | ||
| 4 | * Information structures for board-specific data | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004 Nokia Corporation | ||
| 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _OMAP_BOARD_H | ||
| 11 | #define _OMAP_BOARD_H | ||
| 12 | |||
| 13 | #include <linux/types.h> | ||
| 14 | |||
| 15 | #include <asm/arch/gpio-switch.h> | ||
| 16 | |||
| 17 | /* Different peripheral ids */ | ||
| 18 | #define OMAP_TAG_CLOCK 0x4f01 | ||
| 19 | #define OMAP_TAG_MMC 0x4f02 | ||
| 20 | #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 | ||
| 21 | #define OMAP_TAG_USB 0x4f04 | ||
| 22 | #define OMAP_TAG_LCD 0x4f05 | ||
| 23 | #define OMAP_TAG_GPIO_SWITCH 0x4f06 | ||
| 24 | #define OMAP_TAG_UART 0x4f07 | ||
| 25 | #define OMAP_TAG_FBMEM 0x4f08 | ||
| 26 | #define OMAP_TAG_STI_CONSOLE 0x4f09 | ||
| 27 | #define OMAP_TAG_CAMERA_SENSOR 0x4f0a | ||
| 28 | |||
| 29 | #define OMAP_TAG_BOOT_REASON 0x4f80 | ||
| 30 | #define OMAP_TAG_FLASH_PART 0x4f81 | ||
| 31 | #define OMAP_TAG_VERSION_STR 0x4f82 | ||
| 32 | |||
| 33 | struct omap_clock_config { | ||
| 34 | /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */ | ||
| 35 | u8 system_clock_type; | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct omap_mmc_conf { | ||
| 39 | unsigned enabled:1; | ||
| 40 | /* nomux means "standard" muxing is wrong on this board, and that | ||
| 41 | * board-specific code handled it before common init logic. | ||
| 42 | */ | ||
| 43 | unsigned nomux:1; | ||
| 44 | /* switch pin can be for card detect (default) or card cover */ | ||
| 45 | unsigned cover:1; | ||
| 46 | /* 4 wire signaling is optional, and is only used for SD/SDIO */ | ||
| 47 | unsigned wire4:1; | ||
| 48 | s16 power_pin; | ||
| 49 | s16 switch_pin; | ||
| 50 | s16 wp_pin; | ||
| 51 | }; | ||
| 52 | |||
| 53 | struct omap_mmc_config { | ||
| 54 | struct omap_mmc_conf mmc[2]; | ||
| 55 | }; | ||
| 56 | |||
| 57 | struct omap_serial_console_config { | ||
| 58 | u8 console_uart; | ||
| 59 | u32 console_speed; | ||
| 60 | }; | ||
| 61 | |||
| 62 | struct omap_sti_console_config { | ||
| 63 | unsigned enable:1; | ||
| 64 | u8 channel; | ||
| 65 | }; | ||
| 66 | |||
| 67 | struct omap_camera_sensor_config { | ||
| 68 | u16 reset_gpio; | ||
| 69 | int (*power_on)(void * data); | ||
| 70 | int (*power_off)(void * data); | ||
| 71 | }; | ||
| 72 | |||
| 73 | struct omap_usb_config { | ||
| 74 | /* Configure drivers according to the connectors on your board: | ||
| 75 | * - "A" connector (rectagular) | ||
| 76 | * ... for host/OHCI use, set "register_host". | ||
| 77 | * - "B" connector (squarish) or "Mini-B" | ||
| 78 | * ... for device/gadget use, set "register_dev". | ||
| 79 | * - "Mini-AB" connector (very similar to Mini-B) | ||
| 80 | * ... for OTG use as device OR host, initialize "otg" | ||
| 81 | */ | ||
| 82 | unsigned register_host:1; | ||
| 83 | unsigned register_dev:1; | ||
| 84 | u8 otg; /* port number, 1-based: usb1 == 2 */ | ||
| 85 | |||
| 86 | u8 hmc_mode; | ||
| 87 | |||
| 88 | /* implicitly true if otg: host supports remote wakeup? */ | ||
| 89 | u8 rwc; | ||
| 90 | |||
| 91 | /* signaling pins used to talk to transceiver on usbN: | ||
| 92 | * 0 == usbN unused | ||
| 93 | * 2 == usb0-only, using internal transceiver | ||
| 94 | * 3 == 3 wire bidirectional | ||
| 95 | * 4 == 4 wire bidirectional | ||
| 96 | * 6 == 6 wire unidirectional (or TLL) | ||
| 97 | */ | ||
| 98 | u8 pins[3]; | ||
| 99 | }; | ||
| 100 | |||
| 101 | struct omap_lcd_config { | ||
| 102 | char panel_name[16]; | ||
| 103 | char ctrl_name[16]; | ||
| 104 | s16 nreset_gpio; | ||
| 105 | u8 data_lines; | ||
| 106 | }; | ||
| 107 | |||
| 108 | struct device; | ||
| 109 | struct fb_info; | ||
| 110 | struct omap_backlight_config { | ||
| 111 | int default_intensity; | ||
| 112 | int (*set_power)(struct device *dev, int state); | ||
| 113 | int (*check_fb)(struct fb_info *fb); | ||
| 114 | }; | ||
| 115 | |||
| 116 | struct omap_fbmem_config { | ||
| 117 | u32 start; | ||
| 118 | u32 size; | ||
| 119 | }; | ||
| 120 | |||
| 121 | struct omap_pwm_led_platform_data { | ||
| 122 | const char *name; | ||
| 123 | int intensity_timer; | ||
| 124 | int blink_timer; | ||
| 125 | void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off); | ||
| 126 | }; | ||
| 127 | |||
| 128 | /* See include/asm-arm/arch-omap/gpio-switch.h for definitions */ | ||
| 129 | struct omap_gpio_switch_config { | ||
| 130 | char name[12]; | ||
| 131 | u16 gpio; | ||
| 132 | int flags:4; | ||
| 133 | int type:4; | ||
| 134 | int key_code:24; /* Linux key code */ | ||
| 135 | }; | ||
| 136 | |||
| 137 | struct omap_uart_config { | ||
| 138 | /* Bit field of UARTs present; bit 0 --> UART1 */ | ||
| 139 | unsigned int enabled_uarts; | ||
| 140 | }; | ||
| 141 | |||
| 142 | |||
| 143 | struct omap_flash_part_config { | ||
| 144 | char part_table[0]; | ||
| 145 | }; | ||
| 146 | |||
| 147 | struct omap_boot_reason_config { | ||
| 148 | char reason_str[12]; | ||
| 149 | }; | ||
| 150 | |||
| 151 | struct omap_version_config { | ||
| 152 | char component[12]; | ||
| 153 | char version[12]; | ||
| 154 | }; | ||
| 155 | |||
| 156 | |||
| 157 | #include <asm/arch/board-nokia.h> | ||
| 158 | |||
| 159 | struct omap_board_config_entry { | ||
| 160 | u16 tag; | ||
| 161 | u16 len; | ||
| 162 | u8 data[0]; | ||
| 163 | }; | ||
| 164 | |||
| 165 | struct omap_board_config_kernel { | ||
| 166 | u16 tag; | ||
| 167 | const void *data; | ||
| 168 | }; | ||
| 169 | |||
| 170 | extern const void *__omap_get_config(u16 tag, size_t len, int nr); | ||
| 171 | |||
| 172 | #define omap_get_config(tag, type) \ | ||
| 173 | ((const type *) __omap_get_config((tag), sizeof(type), 0)) | ||
| 174 | #define omap_get_nr_config(tag, type, nr) \ | ||
| 175 | ((const type *) __omap_get_config((tag), sizeof(type), (nr))) | ||
| 176 | |||
| 177 | extern const void *omap_get_var_config(u16 tag, size_t *len); | ||
| 178 | |||
| 179 | extern struct omap_board_config_kernel *omap_board_config; | ||
| 180 | extern int omap_board_config_size; | ||
| 181 | |||
| 182 | |||
| 183 | /* for TI reference platforms sharing the same debug card */ | ||
| 184 | extern int debug_card_init(u32 addr, unsigned gpio); | ||
| 185 | |||
| 186 | #endif | ||
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h deleted file mode 100644 index 4c7b3514f71a..000000000000 --- a/include/asm-arm/arch-omap/clock.h +++ /dev/null | |||
| @@ -1,162 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/clock.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 - 2005 Nokia corporation | ||
| 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | ||
| 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ARCH_ARM_OMAP_CLOCK_H | ||
| 14 | #define __ARCH_ARM_OMAP_CLOCK_H | ||
| 15 | |||
| 16 | struct module; | ||
| 17 | struct clk; | ||
| 18 | |||
| 19 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 20 | |||
| 21 | struct clksel_rate { | ||
| 22 | u8 div; | ||
| 23 | u32 val; | ||
| 24 | u8 flags; | ||
| 25 | }; | ||
| 26 | |||
| 27 | struct clksel { | ||
| 28 | struct clk *parent; | ||
| 29 | const struct clksel_rate *rates; | ||
| 30 | }; | ||
| 31 | |||
| 32 | struct dpll_data { | ||
| 33 | void __iomem *mult_div1_reg; | ||
| 34 | u32 mult_mask; | ||
| 35 | u32 div1_mask; | ||
| 36 | u16 last_rounded_m; | ||
| 37 | u8 last_rounded_n; | ||
| 38 | unsigned long last_rounded_rate; | ||
| 39 | unsigned int rate_tolerance; | ||
| 40 | u16 max_multiplier; | ||
| 41 | u8 max_divider; | ||
| 42 | u32 max_tolerance; | ||
| 43 | # if defined(CONFIG_ARCH_OMAP3) | ||
| 44 | u8 modes; | ||
| 45 | void __iomem *control_reg; | ||
| 46 | u32 enable_mask; | ||
| 47 | u8 auto_recal_bit; | ||
| 48 | u8 recal_en_bit; | ||
| 49 | u8 recal_st_bit; | ||
| 50 | void __iomem *autoidle_reg; | ||
| 51 | u32 autoidle_mask; | ||
| 52 | void __iomem *idlest_reg; | ||
| 53 | u8 idlest_bit; | ||
| 54 | # endif | ||
| 55 | }; | ||
| 56 | |||
| 57 | #endif | ||
| 58 | |||
| 59 | struct clk { | ||
| 60 | struct list_head node; | ||
| 61 | struct module *owner; | ||
| 62 | const char *name; | ||
| 63 | int id; | ||
| 64 | struct clk *parent; | ||
| 65 | unsigned long rate; | ||
| 66 | __u32 flags; | ||
| 67 | void __iomem *enable_reg; | ||
| 68 | __u8 enable_bit; | ||
| 69 | __s8 usecount; | ||
| 70 | void (*recalc)(struct clk *); | ||
| 71 | int (*set_rate)(struct clk *, unsigned long); | ||
| 72 | long (*round_rate)(struct clk *, unsigned long); | ||
| 73 | void (*init)(struct clk *); | ||
| 74 | int (*enable)(struct clk *); | ||
| 75 | void (*disable)(struct clk *); | ||
| 76 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 77 | u8 fixed_div; | ||
| 78 | void __iomem *clksel_reg; | ||
| 79 | u32 clksel_mask; | ||
| 80 | const struct clksel *clksel; | ||
| 81 | struct dpll_data *dpll_data; | ||
| 82 | #else | ||
| 83 | __u8 rate_offset; | ||
| 84 | __u8 src_offset; | ||
| 85 | #endif | ||
| 86 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) | ||
| 87 | struct dentry *dent; /* For visible tree hierarchy */ | ||
| 88 | #endif | ||
| 89 | }; | ||
| 90 | |||
| 91 | struct cpufreq_frequency_table; | ||
| 92 | |||
| 93 | struct clk_functions { | ||
| 94 | int (*clk_enable)(struct clk *clk); | ||
| 95 | void (*clk_disable)(struct clk *clk); | ||
| 96 | long (*clk_round_rate)(struct clk *clk, unsigned long rate); | ||
| 97 | int (*clk_set_rate)(struct clk *clk, unsigned long rate); | ||
| 98 | int (*clk_set_parent)(struct clk *clk, struct clk *parent); | ||
| 99 | struct clk * (*clk_get_parent)(struct clk *clk); | ||
| 100 | void (*clk_allow_idle)(struct clk *clk); | ||
| 101 | void (*clk_deny_idle)(struct clk *clk); | ||
| 102 | void (*clk_disable_unused)(struct clk *clk); | ||
| 103 | #ifdef CONFIG_CPU_FREQ | ||
| 104 | void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **); | ||
| 105 | #endif | ||
| 106 | }; | ||
| 107 | |||
| 108 | extern unsigned int mpurate; | ||
| 109 | |||
| 110 | extern int clk_init(struct clk_functions * custom_clocks); | ||
| 111 | extern int clk_register(struct clk *clk); | ||
| 112 | extern void clk_unregister(struct clk *clk); | ||
| 113 | extern void propagate_rate(struct clk *clk); | ||
| 114 | extern void recalculate_root_clocks(void); | ||
| 115 | extern void followparent_recalc(struct clk * clk); | ||
| 116 | extern void clk_allow_idle(struct clk *clk); | ||
| 117 | extern void clk_deny_idle(struct clk *clk); | ||
| 118 | extern int clk_get_usecount(struct clk *clk); | ||
| 119 | extern void clk_enable_init_clocks(void); | ||
| 120 | |||
| 121 | /* Clock flags */ | ||
| 122 | #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ | ||
| 123 | #define RATE_FIXED (1 << 1) /* Fixed clock rate */ | ||
| 124 | #define RATE_PROPAGATES (1 << 2) /* Program children too */ | ||
| 125 | #define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */ | ||
| 126 | #define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */ | ||
| 127 | #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ | ||
| 128 | #define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */ | ||
| 129 | #define CLOCK_IDLE_CONTROL (1 << 7) | ||
| 130 | #define CLOCK_NO_IDLE_PARENT (1 << 8) | ||
| 131 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ | ||
| 132 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ | ||
| 133 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ | ||
| 134 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ | ||
| 135 | /* bits 13-20 are currently free */ | ||
| 136 | #define CLOCK_IN_OMAP310 (1 << 21) | ||
| 137 | #define CLOCK_IN_OMAP730 (1 << 22) | ||
| 138 | #define CLOCK_IN_OMAP1510 (1 << 23) | ||
| 139 | #define CLOCK_IN_OMAP16XX (1 << 24) | ||
| 140 | #define CLOCK_IN_OMAP242X (1 << 25) | ||
| 141 | #define CLOCK_IN_OMAP243X (1 << 26) | ||
| 142 | #define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ | ||
| 143 | #define PARENT_CONTROLS_CLOCK (1 << 28) | ||
| 144 | #define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */ | ||
| 145 | #define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */ | ||
| 146 | |||
| 147 | /* Clksel_rate flags */ | ||
| 148 | #define DEFAULT_RATE (1 << 0) | ||
| 149 | #define RATE_IN_242X (1 << 1) | ||
| 150 | #define RATE_IN_243X (1 << 2) | ||
| 151 | #define RATE_IN_343X (1 << 3) /* rates common to all 343X */ | ||
| 152 | #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ | ||
| 153 | |||
| 154 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | ||
| 155 | |||
| 156 | |||
| 157 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ | ||
| 158 | #define CORE_CLK_SRC_32K 0 | ||
| 159 | #define CORE_CLK_SRC_DPLL 1 | ||
| 160 | #define CORE_CLK_SRC_DPLL_X2 2 | ||
| 161 | |||
| 162 | #endif | ||
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h deleted file mode 100644 index 8ac03071f60c..000000000000 --- a/include/asm-arm/arch-omap/common.h +++ /dev/null | |||
| @@ -1,69 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/common.h | ||
| 3 | * | ||
| 4 | * Header for code common to all OMAP machines. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | * | ||
| 11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License along | ||
| 23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 25 | */ | ||
| 26 | |||
| 27 | #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H | ||
| 28 | #define __ARCH_ARM_MACH_OMAP_COMMON_H | ||
| 29 | |||
| 30 | #include <linux/i2c.h> | ||
| 31 | |||
| 32 | struct sys_timer; | ||
| 33 | |||
| 34 | extern void omap_map_common_io(void); | ||
| 35 | extern struct sys_timer omap_timer; | ||
| 36 | extern void omap_serial_init(void); | ||
| 37 | #ifdef CONFIG_I2C_OMAP | ||
| 38 | extern int omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
| 39 | struct i2c_board_info const *info, | ||
| 40 | unsigned len); | ||
| 41 | #else | ||
| 42 | static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
| 43 | struct i2c_board_info const *info, | ||
| 44 | unsigned len) | ||
| 45 | { | ||
| 46 | return 0; | ||
| 47 | } | ||
| 48 | #endif | ||
| 49 | |||
| 50 | /* IO bases for various OMAP processors */ | ||
| 51 | struct omap_globals { | ||
| 52 | void __iomem *tap; /* Control module ID code */ | ||
| 53 | void __iomem *sdrc; /* SDRAM Controller */ | ||
| 54 | void __iomem *sms; /* SDRAM Memory Scheduler */ | ||
| 55 | void __iomem *ctrl; /* System Control Module */ | ||
| 56 | void __iomem *prm; /* Power and Reset Management */ | ||
| 57 | void __iomem *cm; /* Clock Management */ | ||
| 58 | }; | ||
| 59 | |||
| 60 | void omap2_set_globals_242x(void); | ||
| 61 | void omap2_set_globals_243x(void); | ||
| 62 | void omap2_set_globals_343x(void); | ||
| 63 | |||
| 64 | /* These get called from omap2_set_globals_xxxx(), do not call these */ | ||
| 65 | void omap2_set_globals_memory(struct omap_globals *); | ||
| 66 | void omap2_set_globals_control(struct omap_globals *); | ||
| 67 | void omap2_set_globals_prcm(struct omap_globals *); | ||
| 68 | |||
| 69 | #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ | ||
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h deleted file mode 100644 index 987553e3eeb9..000000000000 --- a/include/asm-arm/arch-omap/control.h +++ /dev/null | |||
| @@ -1,189 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_CONTROL_H | ||
| 2 | #define __ASM_ARCH_CONTROL_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * include/asm-arm/arch-omap/control.h | ||
| 6 | * | ||
| 7 | * OMAP2/3 System Control Module definitions | ||
| 8 | * | ||
| 9 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 10 | * Copyright (C) 2007 Nokia Corporation | ||
| 11 | * | ||
| 12 | * Written by Paul Walmsley | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <asm/arch/io.h> | ||
| 20 | |||
| 21 | #define OMAP242X_CTRL_REGADDR(reg) \ | ||
| 22 | (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | ||
| 23 | #define OMAP243X_CTRL_REGADDR(reg) \ | ||
| 24 | (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | ||
| 25 | #define OMAP343X_CTRL_REGADDR(reg) \ | ||
| 26 | (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for | ||
| 30 | * OMAP24XX and OMAP34XX. | ||
| 31 | */ | ||
| 32 | |||
| 33 | /* Control submodule offsets */ | ||
| 34 | |||
| 35 | #define OMAP2_CONTROL_INTERFACE 0x000 | ||
| 36 | #define OMAP2_CONTROL_PADCONFS 0x030 | ||
| 37 | #define OMAP2_CONTROL_GENERAL 0x270 | ||
| 38 | #define OMAP343X_CONTROL_MEM_WKUP 0x600 | ||
| 39 | #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 | ||
| 40 | #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 | ||
| 41 | |||
| 42 | /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ | ||
| 43 | |||
| 44 | #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) | ||
| 45 | |||
| 46 | /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ | ||
| 47 | #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) | ||
| 48 | #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) | ||
| 49 | #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) | ||
| 50 | #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) | ||
| 51 | #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) | ||
| 52 | #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) | ||
| 53 | #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) | ||
| 54 | #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) | ||
| 55 | #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) | ||
| 56 | #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) | ||
| 57 | #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) | ||
| 58 | #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) | ||
| 59 | |||
| 60 | /* 242x-only CONTROL_GENERAL register offsets */ | ||
| 61 | #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ | ||
| 62 | #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) | ||
| 63 | |||
| 64 | /* 243x-only CONTROL_GENERAL register offsets */ | ||
| 65 | /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ | ||
| 66 | #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) | ||
| 67 | #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) | ||
| 68 | #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) | ||
| 69 | #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | ||
| 70 | #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) | ||
| 71 | |||
| 72 | /* 24xx-only CONTROL_GENERAL register offsets */ | ||
| 73 | #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) | ||
| 74 | #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) | ||
| 75 | #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) | ||
| 76 | #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) | ||
| 77 | #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) | ||
| 78 | #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) | ||
| 79 | #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) | ||
| 80 | #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) | ||
| 81 | #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) | ||
| 82 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) | ||
| 83 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) | ||
| 84 | #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) | ||
| 85 | #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) | ||
| 86 | #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) | ||
| 87 | #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) | ||
| 88 | #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) | ||
| 89 | #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) | ||
| 90 | #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) | ||
| 91 | #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) | ||
| 92 | #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) | ||
| 93 | #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) | ||
| 94 | #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) | ||
| 95 | #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) | ||
| 96 | #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) | ||
| 97 | #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) | ||
| 98 | #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) | ||
| 99 | #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) | ||
| 100 | #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) | ||
| 101 | #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) | ||
| 102 | #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) | ||
| 103 | #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) | ||
| 104 | |||
| 105 | /* 34xx-only CONTROL_GENERAL register offsets */ | ||
| 106 | #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) | ||
| 107 | #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) | ||
| 108 | #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) | ||
| 109 | #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) | ||
| 110 | #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) | ||
| 111 | #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) | ||
| 112 | #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) | ||
| 113 | #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) | ||
| 114 | #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) | ||
| 115 | #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) | ||
| 116 | #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) | ||
| 117 | #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) | ||
| 118 | #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) | ||
| 119 | #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) | ||
| 120 | #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) | ||
| 121 | #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) | ||
| 122 | #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) | ||
| 123 | #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) | ||
| 124 | #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) | ||
| 125 | #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) | ||
| 126 | #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) | ||
| 127 | #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) | ||
| 128 | #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) | ||
| 129 | #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) | ||
| 130 | #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) | ||
| 131 | #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) | ||
| 132 | #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) | ||
| 133 | #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) | ||
| 134 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) | ||
| 135 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) | ||
| 136 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | ||
| 137 | |||
| 138 | /* | ||
| 139 | * REVISIT: This list of registers is not comprehensive - there are more | ||
| 140 | * that should be added. | ||
| 141 | */ | ||
| 142 | |||
| 143 | /* | ||
| 144 | * Control module register bit defines - these should eventually go into | ||
| 145 | * their own regbits file. Some of these will be complicated, depending | ||
| 146 | * on the device type (general-purpose, emulator, test, secure, bad, other) | ||
| 147 | * and the security mode (secure, non-secure, don't care) | ||
| 148 | */ | ||
| 149 | /* CONTROL_DEVCONF0 bits */ | ||
| 150 | #define OMAP24XX_USBSTANDBYCTRL (1 << 15) | ||
| 151 | #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) | ||
| 152 | #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) | ||
| 153 | |||
| 154 | /* CONTROL_DEVCONF1 bits */ | ||
| 155 | #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ | ||
| 156 | #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ | ||
| 157 | #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ | ||
| 158 | |||
| 159 | /* CONTROL_STATUS bits */ | ||
| 160 | #define OMAP2_DEVICETYPE_MASK (0x7 << 8) | ||
| 161 | #define OMAP2_SYSBOOT_5_MASK (1 << 5) | ||
| 162 | #define OMAP2_SYSBOOT_4_MASK (1 << 4) | ||
| 163 | #define OMAP2_SYSBOOT_3_MASK (1 << 3) | ||
| 164 | #define OMAP2_SYSBOOT_2_MASK (1 << 2) | ||
| 165 | #define OMAP2_SYSBOOT_1_MASK (1 << 1) | ||
| 166 | #define OMAP2_SYSBOOT_0_MASK (1 << 0) | ||
| 167 | |||
| 168 | #ifndef __ASSEMBLY__ | ||
| 169 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 170 | extern void __iomem *omap_ctrl_base_get(void); | ||
| 171 | extern u8 omap_ctrl_readb(u16 offset); | ||
| 172 | extern u16 omap_ctrl_readw(u16 offset); | ||
| 173 | extern u32 omap_ctrl_readl(u16 offset); | ||
| 174 | extern void omap_ctrl_writeb(u8 val, u16 offset); | ||
| 175 | extern void omap_ctrl_writew(u16 val, u16 offset); | ||
| 176 | extern void omap_ctrl_writel(u32 val, u16 offset); | ||
| 177 | #else | ||
| 178 | #define omap_ctrl_base_get() 0 | ||
| 179 | #define omap_ctrl_readb(x) 0 | ||
| 180 | #define omap_ctrl_readw(x) 0 | ||
| 181 | #define omap_ctrl_readl(x) 0 | ||
| 182 | #define omap_ctrl_writeb(x, y) WARN_ON(1) | ||
| 183 | #define omap_ctrl_writew(x, y) WARN_ON(1) | ||
| 184 | #define omap_ctrl_writel(x, y) WARN_ON(1) | ||
| 185 | #endif | ||
| 186 | #endif /* __ASSEMBLY__ */ | ||
| 187 | |||
| 188 | #endif /* __ASM_ARCH_CONTROL_H */ | ||
| 189 | |||
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h deleted file mode 100644 index 52db09f83281..000000000000 --- a/include/asm-arm/arch-omap/cpu.h +++ /dev/null | |||
| @@ -1,402 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/cpu.h | ||
| 3 | * | ||
| 4 | * OMAP cpu type detection | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004, 2008 Nokia Corporation | ||
| 7 | * | ||
| 8 | * Written by Tony Lindgren <tony.lindgren@nokia.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 23 | * | ||
| 24 | */ | ||
| 25 | |||
| 26 | #ifndef __ASM_ARCH_OMAP_CPU_H | ||
| 27 | #define __ASM_ARCH_OMAP_CPU_H | ||
| 28 | |||
| 29 | struct omap_chip_id { | ||
| 30 | u8 oc; | ||
| 31 | }; | ||
| 32 | |||
| 33 | #define OMAP_CHIP_INIT(x) { .oc = x } | ||
| 34 | |||
| 35 | extern unsigned int system_rev; | ||
| 36 | |||
| 37 | #define omap2_cpu_rev() ((system_rev >> 12) & 0x0f) | ||
| 38 | |||
| 39 | /* | ||
| 40 | * Test if multicore OMAP support is needed | ||
| 41 | */ | ||
| 42 | #undef MULTI_OMAP1 | ||
| 43 | #undef MULTI_OMAP2 | ||
| 44 | #undef OMAP_NAME | ||
| 45 | |||
| 46 | #ifdef CONFIG_ARCH_OMAP730 | ||
| 47 | # ifdef OMAP_NAME | ||
| 48 | # undef MULTI_OMAP1 | ||
| 49 | # define MULTI_OMAP1 | ||
| 50 | # else | ||
| 51 | # define OMAP_NAME omap730 | ||
| 52 | # endif | ||
| 53 | #endif | ||
| 54 | #ifdef CONFIG_ARCH_OMAP15XX | ||
| 55 | # ifdef OMAP_NAME | ||
| 56 | # undef MULTI_OMAP1 | ||
| 57 | # define MULTI_OMAP1 | ||
| 58 | # else | ||
| 59 | # define OMAP_NAME omap1510 | ||
| 60 | # endif | ||
| 61 | #endif | ||
| 62 | #ifdef CONFIG_ARCH_OMAP16XX | ||
| 63 | # ifdef OMAP_NAME | ||
| 64 | # undef MULTI_OMAP1 | ||
| 65 | # define MULTI_OMAP1 | ||
| 66 | # else | ||
| 67 | # define OMAP_NAME omap16xx | ||
| 68 | # endif | ||
| 69 | #endif | ||
| 70 | #if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)) | ||
| 71 | # if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) | ||
| 72 | # error "OMAP1 and OMAP2 can't be selected at the same time" | ||
| 73 | # endif | ||
| 74 | #endif | ||
| 75 | #ifdef CONFIG_ARCH_OMAP2420 | ||
| 76 | # ifdef OMAP_NAME | ||
| 77 | # undef MULTI_OMAP2 | ||
| 78 | # define MULTI_OMAP2 | ||
| 79 | # else | ||
| 80 | # define OMAP_NAME omap2420 | ||
| 81 | # endif | ||
| 82 | #endif | ||
| 83 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 84 | # ifdef OMAP_NAME | ||
| 85 | # undef MULTI_OMAP2 | ||
| 86 | # define MULTI_OMAP2 | ||
| 87 | # else | ||
| 88 | # define OMAP_NAME omap2430 | ||
| 89 | # endif | ||
| 90 | #endif | ||
| 91 | #ifdef CONFIG_ARCH_OMAP3430 | ||
| 92 | # ifdef OMAP_NAME | ||
| 93 | # undef MULTI_OMAP2 | ||
| 94 | # define MULTI_OMAP2 | ||
| 95 | # else | ||
| 96 | # define OMAP_NAME omap3430 | ||
| 97 | # endif | ||
| 98 | #endif | ||
| 99 | |||
| 100 | /* | ||
| 101 | * Macros to group OMAP into cpu classes. | ||
| 102 | * These can be used in most places. | ||
| 103 | * cpu_is_omap7xx(): True for OMAP730 | ||
| 104 | * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 | ||
| 105 | * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 | ||
| 106 | * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 | ||
| 107 | * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 | ||
| 108 | * cpu_is_omap243x(): True for OMAP2430 | ||
| 109 | * cpu_is_omap343x(): True for OMAP3430 | ||
| 110 | */ | ||
| 111 | #define GET_OMAP_CLASS ((system_rev >> 24) & 0xff) | ||
| 112 | |||
| 113 | #define IS_OMAP_CLASS(class, id) \ | ||
| 114 | static inline int is_omap ##class (void) \ | ||
| 115 | { \ | ||
| 116 | return (GET_OMAP_CLASS == (id)) ? 1 : 0; \ | ||
| 117 | } | ||
| 118 | |||
| 119 | #define GET_OMAP_SUBCLASS ((system_rev >> 20) & 0x0fff) | ||
| 120 | |||
| 121 | #define IS_OMAP_SUBCLASS(subclass, id) \ | ||
| 122 | static inline int is_omap ##subclass (void) \ | ||
| 123 | { \ | ||
| 124 | return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ | ||
| 125 | } | ||
| 126 | |||
| 127 | IS_OMAP_CLASS(7xx, 0x07) | ||
| 128 | IS_OMAP_CLASS(15xx, 0x15) | ||
| 129 | IS_OMAP_CLASS(16xx, 0x16) | ||
| 130 | IS_OMAP_CLASS(24xx, 0x24) | ||
| 131 | IS_OMAP_CLASS(34xx, 0x34) | ||
| 132 | |||
| 133 | IS_OMAP_SUBCLASS(242x, 0x242) | ||
| 134 | IS_OMAP_SUBCLASS(243x, 0x243) | ||
| 135 | IS_OMAP_SUBCLASS(343x, 0x343) | ||
| 136 | |||
| 137 | #define cpu_is_omap7xx() 0 | ||
| 138 | #define cpu_is_omap15xx() 0 | ||
| 139 | #define cpu_is_omap16xx() 0 | ||
| 140 | #define cpu_is_omap24xx() 0 | ||
| 141 | #define cpu_is_omap242x() 0 | ||
| 142 | #define cpu_is_omap243x() 0 | ||
| 143 | #define cpu_is_omap34xx() 0 | ||
| 144 | #define cpu_is_omap343x() 0 | ||
| 145 | |||
| 146 | #if defined(MULTI_OMAP1) | ||
| 147 | # if defined(CONFIG_ARCH_OMAP730) | ||
| 148 | # undef cpu_is_omap7xx | ||
| 149 | # define cpu_is_omap7xx() is_omap7xx() | ||
| 150 | # endif | ||
| 151 | # if defined(CONFIG_ARCH_OMAP15XX) | ||
| 152 | # undef cpu_is_omap15xx | ||
| 153 | # define cpu_is_omap15xx() is_omap15xx() | ||
| 154 | # endif | ||
| 155 | # if defined(CONFIG_ARCH_OMAP16XX) | ||
| 156 | # undef cpu_is_omap16xx | ||
| 157 | # define cpu_is_omap16xx() is_omap16xx() | ||
| 158 | # endif | ||
| 159 | #else | ||
| 160 | # if defined(CONFIG_ARCH_OMAP730) | ||
| 161 | # undef cpu_is_omap7xx | ||
| 162 | # define cpu_is_omap7xx() 1 | ||
| 163 | # endif | ||
| 164 | # if defined(CONFIG_ARCH_OMAP15XX) | ||
| 165 | # undef cpu_is_omap15xx | ||
| 166 | # define cpu_is_omap15xx() 1 | ||
| 167 | # endif | ||
| 168 | # if defined(CONFIG_ARCH_OMAP16XX) | ||
| 169 | # undef cpu_is_omap16xx | ||
| 170 | # define cpu_is_omap16xx() 1 | ||
| 171 | # endif | ||
| 172 | #endif | ||
| 173 | |||
| 174 | #if defined(MULTI_OMAP2) | ||
| 175 | # if defined(CONFIG_ARCH_OMAP24XX) | ||
| 176 | # undef cpu_is_omap24xx | ||
| 177 | # undef cpu_is_omap242x | ||
| 178 | # undef cpu_is_omap243x | ||
| 179 | # define cpu_is_omap24xx() is_omap24xx() | ||
| 180 | # define cpu_is_omap242x() is_omap242x() | ||
| 181 | # define cpu_is_omap243x() is_omap243x() | ||
| 182 | # endif | ||
| 183 | # if defined(CONFIG_ARCH_OMAP34XX) | ||
| 184 | # undef cpu_is_omap34xx | ||
| 185 | # undef cpu_is_omap343x | ||
| 186 | # define cpu_is_omap34xx() is_omap34xx() | ||
| 187 | # define cpu_is_omap343x() is_omap343x() | ||
| 188 | # endif | ||
| 189 | #else | ||
| 190 | # if defined(CONFIG_ARCH_OMAP24XX) | ||
| 191 | # undef cpu_is_omap24xx | ||
| 192 | # define cpu_is_omap24xx() 1 | ||
| 193 | # endif | ||
| 194 | # if defined(CONFIG_ARCH_OMAP2420) | ||
| 195 | # undef cpu_is_omap242x | ||
| 196 | # define cpu_is_omap242x() 1 | ||
| 197 | # endif | ||
| 198 | # if defined(CONFIG_ARCH_OMAP2430) | ||
| 199 | # undef cpu_is_omap243x | ||
| 200 | # define cpu_is_omap243x() 1 | ||
| 201 | # endif | ||
| 202 | # if defined(CONFIG_ARCH_OMAP34XX) | ||
| 203 | # undef cpu_is_omap34xx | ||
| 204 | # define cpu_is_omap34xx() 1 | ||
| 205 | # endif | ||
| 206 | # if defined(CONFIG_ARCH_OMAP3430) | ||
| 207 | # undef cpu_is_omap343x | ||
| 208 | # define cpu_is_omap343x() 1 | ||
| 209 | # endif | ||
| 210 | #endif | ||
| 211 | |||
| 212 | /* | ||
| 213 | * Macros to detect individual cpu types. | ||
| 214 | * These are only rarely needed. | ||
| 215 | * cpu_is_omap330(): True for OMAP330 | ||
| 216 | * cpu_is_omap730(): True for OMAP730 | ||
| 217 | * cpu_is_omap1510(): True for OMAP1510 | ||
| 218 | * cpu_is_omap1610(): True for OMAP1610 | ||
| 219 | * cpu_is_omap1611(): True for OMAP1611 | ||
| 220 | * cpu_is_omap5912(): True for OMAP5912 | ||
| 221 | * cpu_is_omap1621(): True for OMAP1621 | ||
| 222 | * cpu_is_omap1710(): True for OMAP1710 | ||
| 223 | * cpu_is_omap2420(): True for OMAP2420 | ||
| 224 | * cpu_is_omap2422(): True for OMAP2422 | ||
| 225 | * cpu_is_omap2423(): True for OMAP2423 | ||
| 226 | * cpu_is_omap2430(): True for OMAP2430 | ||
| 227 | * cpu_is_omap3430(): True for OMAP3430 | ||
| 228 | */ | ||
| 229 | #define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff) | ||
| 230 | |||
| 231 | #define IS_OMAP_TYPE(type, id) \ | ||
| 232 | static inline int is_omap ##type (void) \ | ||
| 233 | { \ | ||
| 234 | return (GET_OMAP_TYPE == (id)) ? 1 : 0; \ | ||
| 235 | } | ||
| 236 | |||
| 237 | IS_OMAP_TYPE(310, 0x0310) | ||
| 238 | IS_OMAP_TYPE(730, 0x0730) | ||
| 239 | IS_OMAP_TYPE(1510, 0x1510) | ||
| 240 | IS_OMAP_TYPE(1610, 0x1610) | ||
| 241 | IS_OMAP_TYPE(1611, 0x1611) | ||
| 242 | IS_OMAP_TYPE(5912, 0x1611) | ||
| 243 | IS_OMAP_TYPE(1621, 0x1621) | ||
| 244 | IS_OMAP_TYPE(1710, 0x1710) | ||
| 245 | IS_OMAP_TYPE(2420, 0x2420) | ||
| 246 | IS_OMAP_TYPE(2422, 0x2422) | ||
| 247 | IS_OMAP_TYPE(2423, 0x2423) | ||
| 248 | IS_OMAP_TYPE(2430, 0x2430) | ||
| 249 | IS_OMAP_TYPE(3430, 0x3430) | ||
| 250 | |||
| 251 | #define cpu_is_omap310() 0 | ||
| 252 | #define cpu_is_omap730() 0 | ||
| 253 | #define cpu_is_omap1510() 0 | ||
| 254 | #define cpu_is_omap1610() 0 | ||
| 255 | #define cpu_is_omap5912() 0 | ||
| 256 | #define cpu_is_omap1611() 0 | ||
| 257 | #define cpu_is_omap1621() 0 | ||
| 258 | #define cpu_is_omap1710() 0 | ||
| 259 | #define cpu_is_omap2420() 0 | ||
| 260 | #define cpu_is_omap2422() 0 | ||
| 261 | #define cpu_is_omap2423() 0 | ||
| 262 | #define cpu_is_omap2430() 0 | ||
| 263 | #define cpu_is_omap3430() 0 | ||
| 264 | |||
| 265 | #if defined(MULTI_OMAP1) | ||
| 266 | # if defined(CONFIG_ARCH_OMAP730) | ||
| 267 | # undef cpu_is_omap730 | ||
| 268 | # define cpu_is_omap730() is_omap730() | ||
| 269 | # endif | ||
| 270 | #else | ||
| 271 | # if defined(CONFIG_ARCH_OMAP730) | ||
| 272 | # undef cpu_is_omap730 | ||
| 273 | # define cpu_is_omap730() 1 | ||
| 274 | # endif | ||
| 275 | #endif | ||
| 276 | |||
| 277 | /* | ||
| 278 | * Whether we have MULTI_OMAP1 or not, we still need to distinguish | ||
| 279 | * between 330 vs. 1510 and 1611B/5912 vs. 1710. | ||
| 280 | */ | ||
| 281 | #if defined(CONFIG_ARCH_OMAP15XX) | ||
| 282 | # undef cpu_is_omap310 | ||
| 283 | # undef cpu_is_omap1510 | ||
| 284 | # define cpu_is_omap310() is_omap310() | ||
| 285 | # define cpu_is_omap1510() is_omap1510() | ||
| 286 | #endif | ||
| 287 | |||
| 288 | #if defined(CONFIG_ARCH_OMAP16XX) | ||
| 289 | # undef cpu_is_omap1610 | ||
| 290 | # undef cpu_is_omap1611 | ||
| 291 | # undef cpu_is_omap5912 | ||
| 292 | # undef cpu_is_omap1621 | ||
| 293 | # undef cpu_is_omap1710 | ||
| 294 | # define cpu_is_omap1610() is_omap1610() | ||
| 295 | # define cpu_is_omap1611() is_omap1611() | ||
| 296 | # define cpu_is_omap5912() is_omap5912() | ||
| 297 | # define cpu_is_omap1621() is_omap1621() | ||
| 298 | # define cpu_is_omap1710() is_omap1710() | ||
| 299 | #endif | ||
| 300 | |||
| 301 | #if defined(CONFIG_ARCH_OMAP24XX) | ||
| 302 | # undef cpu_is_omap2420 | ||
| 303 | # undef cpu_is_omap2422 | ||
| 304 | # undef cpu_is_omap2423 | ||
| 305 | # undef cpu_is_omap2430 | ||
| 306 | # define cpu_is_omap2420() is_omap2420() | ||
| 307 | # define cpu_is_omap2422() is_omap2422() | ||
| 308 | # define cpu_is_omap2423() is_omap2423() | ||
| 309 | # define cpu_is_omap2430() is_omap2430() | ||
| 310 | #endif | ||
| 311 | |||
| 312 | #if defined(CONFIG_ARCH_OMAP34XX) | ||
| 313 | # undef cpu_is_omap3430 | ||
| 314 | # define cpu_is_omap3430() is_omap3430() | ||
| 315 | #endif | ||
| 316 | |||
| 317 | /* Macros to detect if we have OMAP1 or OMAP2 */ | ||
| 318 | #define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \ | ||
| 319 | cpu_is_omap16xx()) | ||
| 320 | #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) | ||
| 321 | |||
| 322 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 323 | /* | ||
| 324 | * Macros to detect silicon revision of OMAP2/3 processors. | ||
| 325 | * is_sil_rev_greater_than: true if passed cpu type & its rev is greater. | ||
| 326 | * is_sil_rev_lesser_than: true if passed cpu type & its rev is lesser. | ||
| 327 | * is_sil_rev_equal_to: true if passed cpu type & its rev is equal. | ||
| 328 | * get_sil_rev: return the silicon rev value. | ||
| 329 | */ | ||
| 330 | #define get_sil_omap_type(rev) ((rev & 0xffff0000) >> 16) | ||
| 331 | #define get_sil_revision(rev) ((rev & 0x0000f000) >> 12) | ||
| 332 | |||
| 333 | #define is_sil_rev_greater_than(rev) \ | ||
| 334 | ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ | ||
| 335 | (get_sil_revision(system_rev) > get_sil_revision(rev))) | ||
| 336 | |||
| 337 | #define is_sil_rev_less_than(rev) \ | ||
| 338 | ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ | ||
| 339 | (get_sil_revision(system_rev) < get_sil_revision(rev))) | ||
| 340 | |||
| 341 | #define is_sil_rev_equal_to(rev) \ | ||
| 342 | ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ | ||
| 343 | (get_sil_revision(system_rev) == get_sil_revision(rev))) | ||
| 344 | |||
| 345 | #define get_sil_rev() \ | ||
| 346 | get_sil_revision(system_rev) | ||
| 347 | |||
| 348 | /* Various silicon macros defined here */ | ||
| 349 | #define OMAP2420_REV_ES1_0 0x24200000 | ||
| 350 | #define OMAP2420_REV_ES2_0 0x24201000 | ||
| 351 | #define OMAP2430_REV_ES1_0 0x24300000 | ||
| 352 | #define OMAP3430_REV_ES1_0 0x34300000 | ||
| 353 | #define OMAP3430_REV_ES2_0 0x34301000 | ||
| 354 | #define OMAP3430_REV_ES2_1 0x34302000 | ||
| 355 | #define OMAP3430_REV_ES2_2 0x34303000 | ||
| 356 | |||
| 357 | /* | ||
| 358 | * omap_chip bits | ||
| 359 | * | ||
| 360 | * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is | ||
| 361 | * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates | ||
| 362 | * something that is only valid on that particular ES revision. | ||
| 363 | * | ||
| 364 | * These bits may be ORed together to indicate structures that are | ||
| 365 | * available on multiple chip types. | ||
| 366 | * | ||
| 367 | * To test whether a particular structure matches the current OMAP chip type, | ||
| 368 | * use omap_chip_is(). | ||
| 369 | * | ||
| 370 | */ | ||
| 371 | #define CHIP_IS_OMAP2420 (1 << 0) | ||
| 372 | #define CHIP_IS_OMAP2430 (1 << 1) | ||
| 373 | #define CHIP_IS_OMAP3430 (1 << 2) | ||
| 374 | #define CHIP_IS_OMAP3430ES1 (1 << 3) | ||
| 375 | #define CHIP_IS_OMAP3430ES2 (1 << 4) | ||
| 376 | |||
| 377 | #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) | ||
| 378 | |||
| 379 | int omap_chip_is(struct omap_chip_id oci); | ||
| 380 | |||
| 381 | |||
| 382 | /* | ||
| 383 | * Macro to detect device type i.e. EMU/HS/TST/GP/BAD | ||
| 384 | */ | ||
| 385 | #define DEVICE_TYPE_TEST 0 | ||
| 386 | #define DEVICE_TYPE_EMU 1 | ||
| 387 | #define DEVICE_TYPE_SEC 2 | ||
| 388 | #define DEVICE_TYPE_GP 3 | ||
| 389 | #define DEVICE_TYPE_BAD 4 | ||
| 390 | |||
| 391 | #define get_device_type() ((system_rev & 0x700) >> 8) | ||
| 392 | #define is_device_type_test() (get_device_type() == DEVICE_TYPE_TEST) | ||
| 393 | #define is_device_type_emu() (get_device_type() == DEVICE_TYPE_EMU) | ||
| 394 | #define is_device_type_sec() (get_device_type() == DEVICE_TYPE_SEC) | ||
| 395 | #define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP) | ||
| 396 | #define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD) | ||
| 397 | |||
| 398 | void omap2_check_revision(void); | ||
| 399 | |||
| 400 | #endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ | ||
| 401 | |||
| 402 | #endif | ||
diff --git a/include/asm-arm/arch-omap/debug-macro.S b/include/asm-arm/arch-omap/debug-macro.S deleted file mode 100644 index ca4f577f9675..000000000000 --- a/include/asm-arm/arch-omap/debug-macro.S +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-omap/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 18 | moveq \rx, #0xff000000 @ physical base address | ||
| 19 | movne \rx, #0xfe000000 @ virtual base | ||
| 20 | orr \rx, \rx, #0x00fb0000 | ||
| 21 | #ifdef CONFIG_OMAP_LL_DEBUG_UART3 | ||
| 22 | orr \rx, \rx, #0x00009000 @ UART 3 | ||
| 23 | #endif | ||
| 24 | #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3) | ||
| 25 | orr \rx, \rx, #0x00000800 @ UART 2 & 3 | ||
| 26 | #endif | ||
| 27 | |||
| 28 | #elif CONFIG_ARCH_OMAP2 | ||
| 29 | moveq \rx, #0x48000000 @ physical base address | ||
| 30 | movne \rx, #0xd8000000 @ virtual base | ||
| 31 | orr \rx, \rx, #0x0006a000 | ||
| 32 | #ifdef CONFIG_OMAP_LL_DEBUG_UART2 | ||
| 33 | add \rx, \rx, #0x00002000 @ UART 2 | ||
| 34 | #endif | ||
| 35 | #ifdef CONFIG_OMAP_LL_DEBUG_UART3 | ||
| 36 | add \rx, \rx, #0x00004000 @ UART 3 | ||
| 37 | #endif | ||
| 38 | #endif | ||
| 39 | .endm | ||
| 40 | |||
| 41 | .macro senduart,rd,rx | ||
| 42 | strb \rd, [\rx] | ||
| 43 | .endm | ||
| 44 | |||
| 45 | .macro busyuart,rd,rx | ||
| 46 | 1001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends | ||
| 47 | and \rd, \rd, #0x60 | ||
| 48 | teq \rd, #0x60 | ||
| 49 | beq 1002f | ||
| 50 | ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only | ||
| 51 | and \rd, \rd, #0x60 | ||
| 52 | teq \rd, #0x60 | ||
| 53 | bne 1001b | ||
| 54 | 1002: | ||
| 55 | .endm | ||
| 56 | |||
| 57 | .macro waituart,rd,rx | ||
| 58 | .endm | ||
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h deleted file mode 100644 index f4dcb9587869..000000000000 --- a/include/asm-arm/arch-omap/dma.h +++ /dev/null | |||
| @@ -1,570 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 Nokia Corporation | ||
| 5 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #ifndef __ASM_ARCH_DMA_H | ||
| 22 | #define __ASM_ARCH_DMA_H | ||
| 23 | |||
| 24 | /* Hardware registers for omap1 */ | ||
| 25 | #define OMAP1_DMA_BASE (0xfffed800) | ||
| 26 | |||
| 27 | #define OMAP1_DMA_GCR 0x400 | ||
| 28 | #define OMAP1_DMA_GSCR 0x404 | ||
| 29 | #define OMAP1_DMA_GRST 0x408 | ||
| 30 | #define OMAP1_DMA_HW_ID 0x442 | ||
| 31 | #define OMAP1_DMA_PCH2_ID 0x444 | ||
| 32 | #define OMAP1_DMA_PCH0_ID 0x446 | ||
| 33 | #define OMAP1_DMA_PCH1_ID 0x448 | ||
| 34 | #define OMAP1_DMA_PCHG_ID 0x44a | ||
| 35 | #define OMAP1_DMA_PCHD_ID 0x44c | ||
| 36 | #define OMAP1_DMA_CAPS_0_U 0x44e | ||
| 37 | #define OMAP1_DMA_CAPS_0_L 0x450 | ||
| 38 | #define OMAP1_DMA_CAPS_1_U 0x452 | ||
| 39 | #define OMAP1_DMA_CAPS_1_L 0x454 | ||
| 40 | #define OMAP1_DMA_CAPS_2 0x456 | ||
| 41 | #define OMAP1_DMA_CAPS_3 0x458 | ||
| 42 | #define OMAP1_DMA_CAPS_4 0x45a | ||
| 43 | #define OMAP1_DMA_PCH2_SR 0x460 | ||
| 44 | #define OMAP1_DMA_PCH0_SR 0x480 | ||
| 45 | #define OMAP1_DMA_PCH1_SR 0x482 | ||
| 46 | #define OMAP1_DMA_PCHD_SR 0x4c0 | ||
| 47 | |||
| 48 | /* Hardware registers for omap2 and omap3 */ | ||
| 49 | #define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) | ||
| 50 | #define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) | ||
| 51 | |||
| 52 | #define OMAP_DMA4_REVISION 0x00 | ||
| 53 | #define OMAP_DMA4_GCR 0x78 | ||
| 54 | #define OMAP_DMA4_IRQSTATUS_L0 0x08 | ||
| 55 | #define OMAP_DMA4_IRQSTATUS_L1 0x0c | ||
| 56 | #define OMAP_DMA4_IRQSTATUS_L2 0x10 | ||
| 57 | #define OMAP_DMA4_IRQSTATUS_L3 0x14 | ||
| 58 | #define OMAP_DMA4_IRQENABLE_L0 0x18 | ||
| 59 | #define OMAP_DMA4_IRQENABLE_L1 0x1c | ||
| 60 | #define OMAP_DMA4_IRQENABLE_L2 0x20 | ||
| 61 | #define OMAP_DMA4_IRQENABLE_L3 0x24 | ||
| 62 | #define OMAP_DMA4_SYSSTATUS 0x28 | ||
| 63 | #define OMAP_DMA4_OCP_SYSCONFIG 0x2c | ||
| 64 | #define OMAP_DMA4_CAPS_0 0x64 | ||
| 65 | #define OMAP_DMA4_CAPS_2 0x6c | ||
| 66 | #define OMAP_DMA4_CAPS_3 0x70 | ||
| 67 | #define OMAP_DMA4_CAPS_4 0x74 | ||
| 68 | |||
| 69 | #define OMAP1_LOGICAL_DMA_CH_COUNT 17 | ||
| 70 | #define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ | ||
| 71 | |||
| 72 | /* Common channel specific registers for omap1 */ | ||
| 73 | #define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00) | ||
| 74 | #define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00) | ||
| 75 | #define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02) | ||
| 76 | #define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04) | ||
| 77 | #define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06) | ||
| 78 | #define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10) | ||
| 79 | #define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12) | ||
| 80 | #define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14) | ||
| 81 | #define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16) | ||
| 82 | #define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */ | ||
| 83 | #define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18) | ||
| 84 | #define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a) | ||
| 85 | #define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c) | ||
| 86 | #define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e) | ||
| 87 | #define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28) | ||
| 88 | |||
| 89 | /* Common channel specific registers for omap2 */ | ||
| 90 | #define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80) | ||
| 91 | #define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80) | ||
| 92 | #define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84) | ||
| 93 | #define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88) | ||
| 94 | #define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c) | ||
| 95 | #define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90) | ||
| 96 | #define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94) | ||
| 97 | #define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98) | ||
| 98 | #define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4) | ||
| 99 | #define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8) | ||
| 100 | #define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac) | ||
| 101 | #define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0) | ||
| 102 | #define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4) | ||
| 103 | #define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8) | ||
| 104 | |||
| 105 | /* Channel specific registers only on omap1 */ | ||
| 106 | #define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08) | ||
| 107 | #define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a) | ||
| 108 | #define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c) | ||
| 109 | #define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e) | ||
| 110 | #define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20) | ||
| 111 | #define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22) | ||
| 112 | #define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) | ||
| 113 | #define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */ | ||
| 114 | #define OMAP1_DMA_CCEN(n) 0 | ||
| 115 | #define OMAP1_DMA_CCFN(n) 0 | ||
| 116 | |||
| 117 | /* Channel specific registers only on omap2 */ | ||
| 118 | #define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c) | ||
| 119 | #define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0) | ||
| 120 | #define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc) | ||
| 121 | #define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) | ||
| 122 | #define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) | ||
| 123 | |||
| 124 | /* Dummy defines to keep multi-omap compiles happy */ | ||
| 125 | #define OMAP1_DMA_REVISION 0 | ||
| 126 | #define OMAP1_DMA_IRQSTATUS_L0 0 | ||
| 127 | #define OMAP1_DMA_IRQENABLE_L0 0 | ||
| 128 | #define OMAP1_DMA_OCP_SYSCONFIG 0 | ||
| 129 | #define OMAP_DMA4_HW_ID 0 | ||
| 130 | #define OMAP_DMA4_CAPS_0_L 0 | ||
| 131 | #define OMAP_DMA4_CAPS_0_U 0 | ||
| 132 | #define OMAP_DMA4_CAPS_1_L 0 | ||
| 133 | #define OMAP_DMA4_CAPS_1_U 0 | ||
| 134 | #define OMAP_DMA4_GSCR 0 | ||
| 135 | #define OMAP_DMA4_CPC(n) 0 | ||
| 136 | |||
| 137 | #define OMAP_DMA4_LCH_CTRL(n) 0 | ||
| 138 | #define OMAP_DMA4_COLOR_L(n) 0 | ||
| 139 | #define OMAP_DMA4_COLOR_U(n) 0 | ||
| 140 | #define OMAP_DMA4_CCR2(n) 0 | ||
| 141 | #define OMAP1_DMA_CSSA(n) 0 | ||
| 142 | #define OMAP1_DMA_CDSA(n) 0 | ||
| 143 | #define OMAP_DMA4_CSSA_L(n) 0 | ||
| 144 | #define OMAP_DMA4_CSSA_U(n) 0 | ||
| 145 | #define OMAP_DMA4_CDSA_L(n) 0 | ||
| 146 | #define OMAP_DMA4_CDSA_U(n) 0 | ||
| 147 | |||
| 148 | /*----------------------------------------------------------------------------*/ | ||
| 149 | |||
| 150 | /* DMA channels for omap1 */ | ||
| 151 | #define OMAP_DMA_NO_DEVICE 0 | ||
| 152 | #define OMAP_DMA_MCSI1_TX 1 | ||
| 153 | #define OMAP_DMA_MCSI1_RX 2 | ||
| 154 | #define OMAP_DMA_I2C_RX 3 | ||
| 155 | #define OMAP_DMA_I2C_TX 4 | ||
| 156 | #define OMAP_DMA_EXT_NDMA_REQ 5 | ||
| 157 | #define OMAP_DMA_EXT_NDMA_REQ2 6 | ||
| 158 | #define OMAP_DMA_UWIRE_TX 7 | ||
| 159 | #define OMAP_DMA_MCBSP1_TX 8 | ||
| 160 | #define OMAP_DMA_MCBSP1_RX 9 | ||
| 161 | #define OMAP_DMA_MCBSP3_TX 10 | ||
| 162 | #define OMAP_DMA_MCBSP3_RX 11 | ||
| 163 | #define OMAP_DMA_UART1_TX 12 | ||
| 164 | #define OMAP_DMA_UART1_RX 13 | ||
| 165 | #define OMAP_DMA_UART2_TX 14 | ||
| 166 | #define OMAP_DMA_UART2_RX 15 | ||
| 167 | #define OMAP_DMA_MCBSP2_TX 16 | ||
| 168 | #define OMAP_DMA_MCBSP2_RX 17 | ||
| 169 | #define OMAP_DMA_UART3_TX 18 | ||
| 170 | #define OMAP_DMA_UART3_RX 19 | ||
| 171 | #define OMAP_DMA_CAMERA_IF_RX 20 | ||
| 172 | #define OMAP_DMA_MMC_TX 21 | ||
| 173 | #define OMAP_DMA_MMC_RX 22 | ||
| 174 | #define OMAP_DMA_NAND 23 | ||
| 175 | #define OMAP_DMA_IRQ_LCD_LINE 24 | ||
| 176 | #define OMAP_DMA_MEMORY_STICK 25 | ||
| 177 | #define OMAP_DMA_USB_W2FC_RX0 26 | ||
| 178 | #define OMAP_DMA_USB_W2FC_RX1 27 | ||
| 179 | #define OMAP_DMA_USB_W2FC_RX2 28 | ||
| 180 | #define OMAP_DMA_USB_W2FC_TX0 29 | ||
| 181 | #define OMAP_DMA_USB_W2FC_TX1 30 | ||
| 182 | #define OMAP_DMA_USB_W2FC_TX2 31 | ||
| 183 | |||
| 184 | /* These are only for 1610 */ | ||
| 185 | #define OMAP_DMA_CRYPTO_DES_IN 32 | ||
| 186 | #define OMAP_DMA_SPI_TX 33 | ||
| 187 | #define OMAP_DMA_SPI_RX 34 | ||
| 188 | #define OMAP_DMA_CRYPTO_HASH 35 | ||
| 189 | #define OMAP_DMA_CCP_ATTN 36 | ||
| 190 | #define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 | ||
| 191 | #define OMAP_DMA_CMT_APE_TX_CHAN_0 38 | ||
| 192 | #define OMAP_DMA_CMT_APE_RV_CHAN_0 39 | ||
| 193 | #define OMAP_DMA_CMT_APE_TX_CHAN_1 40 | ||
| 194 | #define OMAP_DMA_CMT_APE_RV_CHAN_1 41 | ||
| 195 | #define OMAP_DMA_CMT_APE_TX_CHAN_2 42 | ||
| 196 | #define OMAP_DMA_CMT_APE_RV_CHAN_2 43 | ||
| 197 | #define OMAP_DMA_CMT_APE_TX_CHAN_3 44 | ||
| 198 | #define OMAP_DMA_CMT_APE_RV_CHAN_3 45 | ||
| 199 | #define OMAP_DMA_CMT_APE_TX_CHAN_4 46 | ||
| 200 | #define OMAP_DMA_CMT_APE_RV_CHAN_4 47 | ||
| 201 | #define OMAP_DMA_CMT_APE_TX_CHAN_5 48 | ||
| 202 | #define OMAP_DMA_CMT_APE_RV_CHAN_5 49 | ||
| 203 | #define OMAP_DMA_CMT_APE_TX_CHAN_6 50 | ||
| 204 | #define OMAP_DMA_CMT_APE_RV_CHAN_6 51 | ||
| 205 | #define OMAP_DMA_CMT_APE_TX_CHAN_7 52 | ||
| 206 | #define OMAP_DMA_CMT_APE_RV_CHAN_7 53 | ||
| 207 | #define OMAP_DMA_MMC2_TX 54 | ||
| 208 | #define OMAP_DMA_MMC2_RX 55 | ||
| 209 | #define OMAP_DMA_CRYPTO_DES_OUT 56 | ||
| 210 | |||
| 211 | /* DMA channels for 24xx */ | ||
| 212 | #define OMAP24XX_DMA_NO_DEVICE 0 | ||
| 213 | #define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ | ||
| 214 | #define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ | ||
| 215 | #define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ | ||
| 216 | #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ | ||
| 217 | #define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ | ||
| 218 | #define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ | ||
| 219 | #define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */ | ||
| 220 | #define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */ | ||
| 221 | #define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ | ||
| 222 | #define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ | ||
| 223 | #define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ | ||
| 224 | #define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ | ||
| 225 | #define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ | ||
| 226 | #define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ | ||
| 227 | #define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */ | ||
| 228 | #define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ | ||
| 229 | #define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ | ||
| 230 | #define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ | ||
| 231 | #define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */ | ||
| 232 | #define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */ | ||
| 233 | #define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ | ||
| 234 | #define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ | ||
| 235 | #define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ | ||
| 236 | #define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ | ||
| 237 | #define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ | ||
| 238 | #define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ | ||
| 239 | #define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ | ||
| 240 | #define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ | ||
| 241 | #define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */ | ||
| 242 | #define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ | ||
| 243 | #define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ | ||
| 244 | #define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */ | ||
| 245 | #define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */ | ||
| 246 | #define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */ | ||
| 247 | #define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */ | ||
| 248 | #define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */ | ||
| 249 | #define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */ | ||
| 250 | #define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ | ||
| 251 | #define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ | ||
| 252 | #define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */ | ||
| 253 | #define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */ | ||
| 254 | #define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ | ||
| 255 | #define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ | ||
| 256 | #define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ | ||
| 257 | #define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ | ||
| 258 | #define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ | ||
| 259 | #define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ | ||
| 260 | #define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */ | ||
| 261 | #define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */ | ||
| 262 | #define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */ | ||
| 263 | #define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */ | ||
| 264 | #define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ | ||
| 265 | #define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ | ||
| 266 | #define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ | ||
| 267 | #define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ | ||
| 268 | #define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ | ||
| 269 | #define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ | ||
| 270 | #define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ | ||
| 271 | #define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ | ||
| 272 | #define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ | ||
| 273 | #define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ | ||
| 274 | #define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ | ||
| 275 | #define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ | ||
| 276 | #define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ | ||
| 277 | #define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ | ||
| 278 | #define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ | ||
| 279 | #define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */ | ||
| 280 | #define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */ | ||
| 281 | #define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ | ||
| 282 | #define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ | ||
| 283 | #define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ | ||
| 284 | #define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */ | ||
| 285 | #define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */ | ||
| 286 | #define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */ | ||
| 287 | #define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */ | ||
| 288 | #define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */ | ||
| 289 | #define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */ | ||
| 290 | #define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ | ||
| 291 | #define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ | ||
| 292 | #define OMAP24XX_DMA_MS 63 /* S_DMA_62 */ | ||
| 293 | #define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ | ||
| 294 | #define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */ | ||
| 295 | #define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */ | ||
| 296 | #define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ | ||
| 297 | #define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ | ||
| 298 | #define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */ | ||
| 299 | #define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */ | ||
| 300 | #define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ | ||
| 301 | #define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ | ||
| 302 | #define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ | ||
| 303 | #define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */ | ||
| 304 | #define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */ | ||
| 305 | #define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */ | ||
| 306 | #define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */ | ||
| 307 | #define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */ | ||
| 308 | #define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */ | ||
| 309 | #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ | ||
| 310 | #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ | ||
| 311 | |||
| 312 | /*----------------------------------------------------------------------------*/ | ||
| 313 | |||
| 314 | /* Hardware registers for LCD DMA */ | ||
| 315 | #define OMAP1510_DMA_LCD_BASE (0xfffedb00) | ||
| 316 | #define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) | ||
| 317 | #define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) | ||
| 318 | #define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04) | ||
| 319 | #define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06) | ||
| 320 | #define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) | ||
| 321 | |||
| 322 | #define OMAP1610_DMA_LCD_BASE (0xfffee300) | ||
| 323 | #define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) | ||
| 324 | #define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) | ||
| 325 | #define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) | ||
| 326 | #define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) | ||
| 327 | #define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca) | ||
| 328 | #define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc) | ||
| 329 | #define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce) | ||
| 330 | #define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0) | ||
| 331 | #define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2) | ||
| 332 | #define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4) | ||
| 333 | #define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6) | ||
| 334 | #define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8) | ||
| 335 | #define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda) | ||
| 336 | #define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0) | ||
| 337 | #define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4) | ||
| 338 | #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) | ||
| 339 | #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) | ||
| 340 | |||
| 341 | #define OMAP1_DMA_TOUT_IRQ (1 << 0) | ||
| 342 | #define OMAP_DMA_DROP_IRQ (1 << 1) | ||
| 343 | #define OMAP_DMA_HALF_IRQ (1 << 2) | ||
| 344 | #define OMAP_DMA_FRAME_IRQ (1 << 3) | ||
| 345 | #define OMAP_DMA_LAST_IRQ (1 << 4) | ||
| 346 | #define OMAP_DMA_BLOCK_IRQ (1 << 5) | ||
| 347 | #define OMAP1_DMA_SYNC_IRQ (1 << 6) | ||
| 348 | #define OMAP2_DMA_PKT_IRQ (1 << 7) | ||
| 349 | #define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8) | ||
| 350 | #define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9) | ||
| 351 | #define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) | ||
| 352 | #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) | ||
| 353 | |||
| 354 | #define OMAP_DMA_DATA_TYPE_S8 0x00 | ||
| 355 | #define OMAP_DMA_DATA_TYPE_S16 0x01 | ||
| 356 | #define OMAP_DMA_DATA_TYPE_S32 0x02 | ||
| 357 | |||
| 358 | #define OMAP_DMA_SYNC_ELEMENT 0x00 | ||
| 359 | #define OMAP_DMA_SYNC_FRAME 0x01 | ||
| 360 | #define OMAP_DMA_SYNC_BLOCK 0x02 | ||
| 361 | #define OMAP_DMA_SYNC_PACKET 0x03 | ||
| 362 | |||
| 363 | #define OMAP_DMA_SRC_SYNC 0x01 | ||
| 364 | #define OMAP_DMA_DST_SYNC 0x00 | ||
| 365 | |||
| 366 | #define OMAP_DMA_PORT_EMIFF 0x00 | ||
| 367 | #define OMAP_DMA_PORT_EMIFS 0x01 | ||
| 368 | #define OMAP_DMA_PORT_OCP_T1 0x02 | ||
| 369 | #define OMAP_DMA_PORT_TIPB 0x03 | ||
| 370 | #define OMAP_DMA_PORT_OCP_T2 0x04 | ||
| 371 | #define OMAP_DMA_PORT_MPUI 0x05 | ||
| 372 | |||
| 373 | #define OMAP_DMA_AMODE_CONSTANT 0x00 | ||
| 374 | #define OMAP_DMA_AMODE_POST_INC 0x01 | ||
| 375 | #define OMAP_DMA_AMODE_SINGLE_IDX 0x02 | ||
| 376 | #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 | ||
| 377 | |||
| 378 | #define DMA_DEFAULT_FIFO_DEPTH 0x10 | ||
| 379 | #define DMA_DEFAULT_ARB_RATE 0x01 | ||
| 380 | /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */ | ||
| 381 | #define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */ | ||
| 382 | #define DMA_THREAD_RESERVE_ONET (0x01 << 12) | ||
| 383 | #define DMA_THREAD_RESERVE_TWOT (0x02 << 12) | ||
| 384 | #define DMA_THREAD_RESERVE_THREET (0x03 << 12) | ||
| 385 | #define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */ | ||
| 386 | #define DMA_THREAD_FIFO_75 (0x01 << 14) | ||
| 387 | #define DMA_THREAD_FIFO_25 (0x02 << 14) | ||
| 388 | #define DMA_THREAD_FIFO_50 (0x03 << 14) | ||
| 389 | |||
| 390 | /* Chaining modes*/ | ||
| 391 | #ifndef CONFIG_ARCH_OMAP1 | ||
| 392 | #define OMAP_DMA_STATIC_CHAIN 0x1 | ||
| 393 | #define OMAP_DMA_DYNAMIC_CHAIN 0x2 | ||
| 394 | #define OMAP_DMA_CHAIN_ACTIVE 0x1 | ||
| 395 | #define OMAP_DMA_CHAIN_INACTIVE 0x0 | ||
| 396 | #endif | ||
| 397 | |||
| 398 | #define DMA_CH_PRIO_HIGH 0x1 | ||
| 399 | #define DMA_CH_PRIO_LOW 0x0 /* Def */ | ||
| 400 | |||
| 401 | /* LCD DMA block numbers */ | ||
| 402 | enum { | ||
| 403 | OMAP_LCD_DMA_B1_TOP, | ||
| 404 | OMAP_LCD_DMA_B1_BOTTOM, | ||
| 405 | OMAP_LCD_DMA_B2_TOP, | ||
| 406 | OMAP_LCD_DMA_B2_BOTTOM | ||
| 407 | }; | ||
| 408 | |||
| 409 | enum omap_dma_burst_mode { | ||
| 410 | OMAP_DMA_DATA_BURST_DIS = 0, | ||
| 411 | OMAP_DMA_DATA_BURST_4, | ||
| 412 | OMAP_DMA_DATA_BURST_8, | ||
| 413 | OMAP_DMA_DATA_BURST_16, | ||
| 414 | }; | ||
| 415 | |||
| 416 | enum end_type { | ||
| 417 | OMAP_DMA_LITTLE_ENDIAN = 0, | ||
| 418 | OMAP_DMA_BIG_ENDIAN | ||
| 419 | }; | ||
| 420 | |||
| 421 | enum omap_dma_color_mode { | ||
| 422 | OMAP_DMA_COLOR_DIS = 0, | ||
| 423 | OMAP_DMA_CONSTANT_FILL, | ||
| 424 | OMAP_DMA_TRANSPARENT_COPY | ||
| 425 | }; | ||
| 426 | |||
| 427 | enum omap_dma_write_mode { | ||
| 428 | OMAP_DMA_WRITE_NON_POSTED = 0, | ||
| 429 | OMAP_DMA_WRITE_POSTED, | ||
| 430 | OMAP_DMA_WRITE_LAST_NON_POSTED | ||
| 431 | }; | ||
| 432 | |||
| 433 | enum omap_dma_channel_mode { | ||
| 434 | OMAP_DMA_LCH_2D = 0, | ||
| 435 | OMAP_DMA_LCH_G, | ||
| 436 | OMAP_DMA_LCH_P, | ||
| 437 | OMAP_DMA_LCH_PD | ||
| 438 | }; | ||
| 439 | |||
| 440 | struct omap_dma_channel_params { | ||
| 441 | int data_type; /* data type 8,16,32 */ | ||
| 442 | int elem_count; /* number of elements in a frame */ | ||
| 443 | int frame_count; /* number of frames in a element */ | ||
| 444 | |||
| 445 | int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ | ||
| 446 | int src_amode; /* constant, post increment, indexed, | ||
| 447 | double indexed */ | ||
| 448 | unsigned long src_start; /* source address : physical */ | ||
| 449 | int src_ei; /* source element index */ | ||
| 450 | int src_fi; /* source frame index */ | ||
| 451 | |||
| 452 | int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ | ||
| 453 | int dst_amode; /* constant, post increment, indexed, | ||
| 454 | double indexed */ | ||
| 455 | unsigned long dst_start; /* source address : physical */ | ||
| 456 | int dst_ei; /* source element index */ | ||
| 457 | int dst_fi; /* source frame index */ | ||
| 458 | |||
| 459 | int trigger; /* trigger attached if the channel is | ||
| 460 | synchronized */ | ||
| 461 | int sync_mode; /* sycn on element, frame , block or packet */ | ||
| 462 | int src_or_dst_synch; /* source synch(1) or destination synch(0) */ | ||
| 463 | |||
| 464 | int ie; /* interrupt enabled */ | ||
| 465 | |||
| 466 | unsigned char read_prio;/* read priority */ | ||
| 467 | unsigned char write_prio;/* write priority */ | ||
| 468 | |||
| 469 | #ifndef CONFIG_ARCH_OMAP1 | ||
| 470 | enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */ | ||
| 471 | #endif | ||
| 472 | }; | ||
| 473 | |||
| 474 | |||
| 475 | extern void omap_set_dma_priority(int lch, int dst_port, int priority); | ||
| 476 | extern int omap_request_dma(int dev_id, const char *dev_name, | ||
| 477 | void (*callback)(int lch, u16 ch_status, void *data), | ||
| 478 | void *data, int *dma_ch); | ||
| 479 | extern void omap_enable_dma_irq(int ch, u16 irq_bits); | ||
| 480 | extern void omap_disable_dma_irq(int ch, u16 irq_bits); | ||
| 481 | extern void omap_free_dma(int ch); | ||
| 482 | extern void omap_start_dma(int lch); | ||
| 483 | extern void omap_stop_dma(int lch); | ||
| 484 | extern void omap_set_dma_transfer_params(int lch, int data_type, | ||
| 485 | int elem_count, int frame_count, | ||
| 486 | int sync_mode, | ||
| 487 | int dma_trigger, int src_or_dst_synch); | ||
| 488 | extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, | ||
| 489 | u32 color); | ||
| 490 | extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); | ||
| 491 | extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode); | ||
| 492 | |||
| 493 | extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, | ||
| 494 | unsigned long src_start, | ||
| 495 | int src_ei, int src_fi); | ||
| 496 | extern void omap_set_dma_src_index(int lch, int eidx, int fidx); | ||
| 497 | extern void omap_set_dma_src_data_pack(int lch, int enable); | ||
| 498 | extern void omap_set_dma_src_burst_mode(int lch, | ||
| 499 | enum omap_dma_burst_mode burst_mode); | ||
| 500 | |||
| 501 | extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, | ||
| 502 | unsigned long dest_start, | ||
| 503 | int dst_ei, int dst_fi); | ||
| 504 | extern void omap_set_dma_dest_index(int lch, int eidx, int fidx); | ||
| 505 | extern void omap_set_dma_dest_data_pack(int lch, int enable); | ||
| 506 | extern void omap_set_dma_dest_burst_mode(int lch, | ||
| 507 | enum omap_dma_burst_mode burst_mode); | ||
| 508 | |||
| 509 | extern void omap_set_dma_params(int lch, | ||
| 510 | struct omap_dma_channel_params *params); | ||
| 511 | |||
| 512 | extern void omap_dma_link_lch(int lch_head, int lch_queue); | ||
| 513 | extern void omap_dma_unlink_lch(int lch_head, int lch_queue); | ||
| 514 | |||
| 515 | extern int omap_set_dma_callback(int lch, | ||
| 516 | void (*callback)(int lch, u16 ch_status, void *data), | ||
| 517 | void *data); | ||
| 518 | extern dma_addr_t omap_get_dma_src_pos(int lch); | ||
| 519 | extern dma_addr_t omap_get_dma_dst_pos(int lch); | ||
| 520 | extern void omap_clear_dma(int lch); | ||
| 521 | extern int omap_get_dma_active_status(int lch); | ||
| 522 | extern int omap_dma_running(void); | ||
| 523 | extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, | ||
| 524 | int tparams); | ||
| 525 | extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, | ||
| 526 | unsigned char write_prio); | ||
| 527 | extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype); | ||
| 528 | extern void omap_set_dma_src_endian_type(int lch, enum end_type etype); | ||
| 529 | extern int omap_get_dma_index(int lch, int *ei, int *fi); | ||
| 530 | |||
| 531 | /* Chaining APIs */ | ||
| 532 | #ifndef CONFIG_ARCH_OMAP1 | ||
| 533 | extern int omap_request_dma_chain(int dev_id, const char *dev_name, | ||
| 534 | void (*callback) (int chain_id, u16 ch_status, | ||
| 535 | void *data), | ||
| 536 | int *chain_id, int no_of_chans, | ||
| 537 | int chain_mode, | ||
| 538 | struct omap_dma_channel_params params); | ||
| 539 | extern int omap_free_dma_chain(int chain_id); | ||
| 540 | extern int omap_dma_chain_a_transfer(int chain_id, int src_start, | ||
| 541 | int dest_start, int elem_count, | ||
| 542 | int frame_count, void *callbk_data); | ||
| 543 | extern int omap_start_dma_chain_transfers(int chain_id); | ||
| 544 | extern int omap_stop_dma_chain_transfers(int chain_id); | ||
| 545 | extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi); | ||
| 546 | extern int omap_get_dma_chain_dst_pos(int chain_id); | ||
| 547 | extern int omap_get_dma_chain_src_pos(int chain_id); | ||
| 548 | |||
| 549 | extern int omap_modify_dma_chain_params(int chain_id, | ||
| 550 | struct omap_dma_channel_params params); | ||
| 551 | extern int omap_dma_chain_status(int chain_id); | ||
| 552 | #endif | ||
| 553 | |||
| 554 | /* LCD DMA functions */ | ||
| 555 | extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), | ||
| 556 | void *data); | ||
| 557 | extern void omap_free_lcd_dma(void); | ||
| 558 | extern void omap_setup_lcd_dma(void); | ||
| 559 | extern void omap_enable_lcd_dma(void); | ||
| 560 | extern void omap_stop_lcd_dma(void); | ||
| 561 | extern void omap_set_lcd_dma_ext_controller(int external); | ||
| 562 | extern void omap_set_lcd_dma_single_transfer(int single); | ||
| 563 | extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, | ||
| 564 | int data_type); | ||
| 565 | extern void omap_set_lcd_dma_b1_rotation(int rotate); | ||
| 566 | extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres); | ||
| 567 | extern void omap_set_lcd_dma_b1_mirror(int mirror); | ||
| 568 | extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale); | ||
| 569 | |||
| 570 | #endif /* __ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h deleted file mode 100644 index 02b29e8437ae..000000000000 --- a/include/asm-arm/arch-omap/dmtimer.h +++ /dev/null | |||
| @@ -1,84 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/dmtimer.h | ||
| 3 | * | ||
| 4 | * OMAP Dual-Mode Timers | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005 Nokia Corporation | ||
| 7 | * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> | ||
| 8 | * PWM and clock framwork support by Timo Teras. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_DMTIMER_H | ||
| 30 | #define __ASM_ARCH_DMTIMER_H | ||
| 31 | |||
| 32 | /* clock sources */ | ||
| 33 | #define OMAP_TIMER_SRC_SYS_CLK 0x00 | ||
| 34 | #define OMAP_TIMER_SRC_32_KHZ 0x01 | ||
| 35 | #define OMAP_TIMER_SRC_EXT_CLK 0x02 | ||
| 36 | |||
| 37 | /* timer interrupt enable bits */ | ||
| 38 | #define OMAP_TIMER_INT_CAPTURE (1 << 2) | ||
| 39 | #define OMAP_TIMER_INT_OVERFLOW (1 << 1) | ||
| 40 | #define OMAP_TIMER_INT_MATCH (1 << 0) | ||
| 41 | |||
| 42 | /* trigger types */ | ||
| 43 | #define OMAP_TIMER_TRIGGER_NONE 0x00 | ||
| 44 | #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 | ||
| 45 | #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 | ||
| 46 | |||
| 47 | struct omap_dm_timer; | ||
| 48 | struct clk; | ||
| 49 | |||
| 50 | int omap_dm_timer_init(void); | ||
| 51 | |||
| 52 | struct omap_dm_timer *omap_dm_timer_request(void); | ||
| 53 | struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); | ||
| 54 | void omap_dm_timer_free(struct omap_dm_timer *timer); | ||
| 55 | void omap_dm_timer_enable(struct omap_dm_timer *timer); | ||
| 56 | void omap_dm_timer_disable(struct omap_dm_timer *timer); | ||
| 57 | |||
| 58 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer); | ||
| 59 | |||
| 60 | u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); | ||
| 61 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer); | ||
| 62 | |||
| 63 | void omap_dm_timer_trigger(struct omap_dm_timer *timer); | ||
| 64 | void omap_dm_timer_start(struct omap_dm_timer *timer); | ||
| 65 | void omap_dm_timer_stop(struct omap_dm_timer *timer); | ||
| 66 | |||
| 67 | void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); | ||
| 68 | void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); | ||
| 69 | void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); | ||
| 70 | void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); | ||
| 71 | void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); | ||
| 72 | void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); | ||
| 73 | |||
| 74 | void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); | ||
| 75 | |||
| 76 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); | ||
| 77 | void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); | ||
| 78 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); | ||
| 79 | void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value); | ||
| 80 | |||
| 81 | int omap_dm_timers_active(void); | ||
| 82 | |||
| 83 | |||
| 84 | #endif /* __ASM_ARCH_DMTIMER_H */ | ||
diff --git a/include/asm-arm/arch-omap/dsp_common.h b/include/asm-arm/arch-omap/dsp_common.h deleted file mode 100644 index da97736f3efa..000000000000 --- a/include/asm-arm/arch-omap/dsp_common.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1) | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved. | ||
| 5 | * | ||
| 6 | * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * version 2 as published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, but | ||
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 15 | * General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | ||
| 20 | * 02110-1301 USA | ||
| 21 | * | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef ASM_ARCH_DSP_COMMON_H | ||
| 25 | #define ASM_ARCH_DSP_COMMON_H | ||
| 26 | |||
| 27 | #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK) | ||
| 28 | extern void omap_dsp_request_mpui(void); | ||
| 29 | extern void omap_dsp_release_mpui(void); | ||
| 30 | extern int omap_dsp_request_mem(void); | ||
| 31 | extern int omap_dsp_release_mem(void); | ||
| 32 | #else | ||
| 33 | static inline int omap_dsp_request_mem(void) | ||
| 34 | { | ||
| 35 | return 0; | ||
| 36 | } | ||
| 37 | #define omap_dsp_release_mem() do {} while (0) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #endif /* ASM_ARCH_DSP_COMMON_H */ | ||
diff --git a/include/asm-arm/arch-omap/eac.h b/include/asm-arm/arch-omap/eac.h deleted file mode 100644 index ccee3b0700b3..000000000000 --- a/include/asm-arm/arch-omap/eac.h +++ /dev/null | |||
| @@ -1,100 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap2/eac.h | ||
| 3 | * | ||
| 4 | * Defines for Enhanced Audio Controller | ||
| 5 | * | ||
| 6 | * Contact: Jarkko Nikula <jarkko.nikula@nokia.com> | ||
| 7 | * | ||
| 8 | * Copyright (C) 2006 Nokia Corporation | ||
| 9 | * Copyright (C) 2004 Texas Instruments, Inc. | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or | ||
| 12 | * modify it under the terms of the GNU General Public License | ||
| 13 | * version 2 as published by the Free Software Foundation. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, but | ||
| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 18 | * General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | ||
| 23 | * 02110-1301 USA | ||
| 24 | * | ||
| 25 | */ | ||
| 26 | |||
| 27 | #ifndef __ASM_ARM_ARCH_OMAP2_EAC_H | ||
| 28 | #define __ASM_ARM_ARCH_OMAP2_EAC_H | ||
| 29 | |||
| 30 | #include <asm/arch/io.h> | ||
| 31 | #include <asm/arch/hardware.h> | ||
| 32 | #include <asm/irq.h> | ||
| 33 | |||
| 34 | #include <sound/core.h> | ||
| 35 | |||
| 36 | /* master codec clock source */ | ||
| 37 | #define EAC_MCLK_EXT_MASK 0x100 | ||
| 38 | enum eac_mclk_src { | ||
| 39 | EAC_MCLK_INT_11290000, /* internal 96 MHz / 8.5 = 11.29 Mhz */ | ||
| 40 | EAC_MCLK_EXT_11289600 = EAC_MCLK_EXT_MASK, | ||
| 41 | EAC_MCLK_EXT_12288000, | ||
| 42 | EAC_MCLK_EXT_2x11289600, | ||
| 43 | EAC_MCLK_EXT_2x12288000, | ||
| 44 | }; | ||
| 45 | |||
| 46 | /* codec port interface mode */ | ||
| 47 | enum eac_codec_mode { | ||
| 48 | EAC_CODEC_PCM, | ||
| 49 | EAC_CODEC_AC97, | ||
| 50 | EAC_CODEC_I2S_MASTER, /* codec port, I.e. EAC is the master */ | ||
| 51 | EAC_CODEC_I2S_SLAVE, | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* configuration structure for I2S mode */ | ||
| 55 | struct eac_i2s_conf { | ||
| 56 | /* if enabled, then first data slot (left channel) is signaled as | ||
| 57 | * positive level of frame sync EAC.AC_FS */ | ||
| 58 | unsigned polarity_changed_mode:1; | ||
| 59 | /* if enabled, then serial data starts one clock cycle after the | ||
| 60 | * of EAC.AC_FS for first audio slot */ | ||
| 61 | unsigned sync_delay_enable:1; | ||
| 62 | }; | ||
| 63 | |||
| 64 | /* configuration structure for EAC codec port */ | ||
| 65 | struct eac_codec { | ||
| 66 | enum eac_mclk_src mclk_src; | ||
| 67 | |||
| 68 | enum eac_codec_mode codec_mode; | ||
| 69 | union { | ||
| 70 | struct eac_i2s_conf i2s; | ||
| 71 | } codec_conf; | ||
| 72 | |||
| 73 | int default_rate; /* audio sampling rate */ | ||
| 74 | |||
| 75 | int (* set_power)(void *private_data, int dac, int adc); | ||
| 76 | int (* register_controls)(void *private_data, | ||
| 77 | struct snd_card *card); | ||
| 78 | const char *short_name; | ||
| 79 | |||
| 80 | void *private_data; | ||
| 81 | }; | ||
| 82 | |||
| 83 | /* structure for passing platform dependent data to the EAC driver */ | ||
| 84 | struct eac_platform_data { | ||
| 85 | int (* init)(struct device *eac_dev); | ||
| 86 | void (* cleanup)(struct device *eac_dev); | ||
| 87 | /* these callbacks are used to configure & control external MCLK | ||
| 88 | * source. NULL if not used */ | ||
| 89 | int (* enable_ext_clocks)(struct device *eac_dev); | ||
| 90 | void (* disable_ext_clocks)(struct device *eac_dev); | ||
| 91 | }; | ||
| 92 | |||
| 93 | extern void omap_init_eac(struct eac_platform_data *pdata); | ||
| 94 | |||
| 95 | extern int eac_register_codec(struct device *eac_dev, struct eac_codec *codec); | ||
| 96 | extern void eac_unregister_codec(struct device *eac_dev); | ||
| 97 | |||
| 98 | extern int eac_set_mode(struct device *eac_dev, int play, int rec); | ||
| 99 | |||
| 100 | #endif /* __ASM_ARM_ARCH_OMAP2_EAC_H */ | ||
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S deleted file mode 100644 index 67ed7839e782..000000000000 --- a/include/asm-arm/arch-omap/entry-macro.S +++ /dev/null | |||
| @@ -1,89 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-omap/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for OMAP-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | #include <asm/arch/io.h> | ||
| 12 | #include <asm/arch/irqs.h> | ||
| 13 | |||
| 14 | #if defined(CONFIG_ARCH_OMAP1) | ||
| 15 | |||
| 16 | #if defined(CONFIG_ARCH_OMAP730) && \ | ||
| 17 | (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) | ||
| 18 | #error "FIXME: OMAP730 doesn't support multiple-OMAP" | ||
| 19 | #elif defined(CONFIG_ARCH_OMAP730) | ||
| 20 | #define INT_IH2_IRQ INT_730_IH2_IRQ | ||
| 21 | #elif defined(CONFIG_ARCH_OMAP15XX) | ||
| 22 | #define INT_IH2_IRQ INT_1510_IH2_IRQ | ||
| 23 | #elif defined(CONFIG_ARCH_OMAP16XX) | ||
| 24 | #define INT_IH2_IRQ INT_1610_IH2_IRQ | ||
| 25 | #else | ||
| 26 | #warning "IH2 IRQ defaulted" | ||
| 27 | #define INT_IH2_IRQ INT_1510_IH2_IRQ | ||
| 28 | #endif | ||
| 29 | |||
| 30 | .macro disable_fiq | ||
| 31 | .endm | ||
| 32 | |||
| 33 | .macro get_irqnr_preamble, base, tmp | ||
| 34 | .endm | ||
| 35 | |||
| 36 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 37 | .endm | ||
| 38 | |||
| 39 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 40 | ldr \base, =IO_ADDRESS(OMAP_IH1_BASE) | ||
| 41 | ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] | ||
| 42 | ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET] | ||
| 43 | mov \irqstat, #0xffffffff | ||
| 44 | bic \tmp, \irqstat, \tmp | ||
| 45 | tst \irqnr, \tmp | ||
| 46 | beq 1510f | ||
| 47 | |||
| 48 | ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET] | ||
| 49 | cmp \irqnr, #0 | ||
| 50 | ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] | ||
| 51 | cmpeq \irqnr, #INT_IH2_IRQ | ||
| 52 | ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE) | ||
| 53 | ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] | ||
| 54 | addeqs \irqnr, \irqnr, #32 | ||
| 55 | 1510: | ||
| 56 | .endm | ||
| 57 | |||
| 58 | #elif defined(CONFIG_ARCH_OMAP24XX) | ||
| 59 | |||
| 60 | #include <asm/arch/omap24xx.h> | ||
| 61 | |||
| 62 | .macro disable_fiq | ||
| 63 | .endm | ||
| 64 | |||
| 65 | .macro get_irqnr_preamble, base, tmp | ||
| 66 | .endm | ||
| 67 | |||
| 68 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 69 | .endm | ||
| 70 | |||
| 71 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 72 | ldr \base, =OMAP2_VA_IC_BASE | ||
| 73 | ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ | ||
| 74 | cmp \irqnr, #0x0 | ||
| 75 | bne 2222f | ||
| 76 | ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ | ||
| 77 | cmp \irqnr, #0x0 | ||
| 78 | bne 2222f | ||
| 79 | ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ | ||
| 80 | cmp \irqnr, #0x0 | ||
| 81 | 2222: | ||
| 82 | ldrne \irqnr, [\base, #IRQ_SIR_IRQ] | ||
| 83 | |||
| 84 | .endm | ||
| 85 | |||
| 86 | .macro irq_prio_table | ||
| 87 | .endm | ||
| 88 | |||
| 89 | #endif | ||
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h deleted file mode 100644 index f420881d2a3b..000000000000 --- a/include/asm-arm/arch-omap/fpga.h +++ /dev/null | |||
| @@ -1,197 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/fpga.h | ||
| 3 | * | ||
| 4 | * Interrupt handler for OMAP-1510 FPGA | ||
| 5 | * | ||
| 6 | * Copyright (C) 2001 RidgeRun, Inc. | ||
| 7 | * Author: Greg Lonnon <glonnon@ridgerun.com> | ||
| 8 | * | ||
| 9 | * Copyright (C) 2002 MontaVista Software, Inc. | ||
| 10 | * | ||
| 11 | * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 | ||
| 12 | * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com> | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_OMAP_FPGA_H | ||
| 20 | #define __ASM_ARCH_OMAP_FPGA_H | ||
| 21 | |||
| 22 | #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX) | ||
| 23 | extern void omap1510_fpga_init_irq(void); | ||
| 24 | #else | ||
| 25 | #define omap1510_fpga_init_irq() (0) | ||
| 26 | #endif | ||
| 27 | |||
| 28 | #define fpga_read(reg) __raw_readb(reg) | ||
| 29 | #define fpga_write(val, reg) __raw_writeb(val, reg) | ||
| 30 | |||
| 31 | /* | ||
| 32 | * --------------------------------------------------------------------------- | ||
| 33 | * H2/P2 Debug board FPGA | ||
| 34 | * --------------------------------------------------------------------------- | ||
| 35 | */ | ||
| 36 | /* maps in the FPGA registers and the ETHR registers */ | ||
| 37 | #define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ | ||
| 38 | #define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ | ||
| 39 | #define H2P2_DBG_FPGA_START 0x04000000 /* PA */ | ||
| 40 | |||
| 41 | #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) | ||
| 42 | #define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ | ||
| 43 | #define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ | ||
| 44 | #define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ | ||
| 45 | #define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ | ||
| 46 | #define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ | ||
| 47 | #define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ | ||
| 48 | #define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ | ||
| 49 | |||
| 50 | /* NOTE: most boards don't have a static mapping for the FPGA ... */ | ||
| 51 | struct h2p2_dbg_fpga { | ||
| 52 | /* offset 0x00 */ | ||
| 53 | u16 smc91x[8]; | ||
| 54 | /* offset 0x10 */ | ||
| 55 | u16 fpga_rev; | ||
| 56 | u16 board_rev; | ||
| 57 | u16 gpio_outputs; | ||
| 58 | u16 leds; | ||
| 59 | /* offset 0x18 */ | ||
| 60 | u16 misc_inputs; | ||
| 61 | u16 lan_status; | ||
| 62 | u16 lan_reset; | ||
| 63 | u16 reserved0; | ||
| 64 | /* offset 0x20 */ | ||
| 65 | u16 ps2_data; | ||
| 66 | u16 ps2_ctrl; | ||
| 67 | /* plus also 4 rs232 ports ... */ | ||
| 68 | }; | ||
| 69 | |||
| 70 | /* LEDs definition on debug board (16 LEDs, all physically green) */ | ||
| 71 | #define H2P2_DBG_FPGA_LED_GREEN (1 << 15) | ||
| 72 | #define H2P2_DBG_FPGA_LED_AMBER (1 << 14) | ||
| 73 | #define H2P2_DBG_FPGA_LED_RED (1 << 13) | ||
| 74 | #define H2P2_DBG_FPGA_LED_BLUE (1 << 12) | ||
| 75 | /* cpu0 load-meter LEDs */ | ||
| 76 | #define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... | ||
| 77 | #define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 | ||
| 78 | #define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) | ||
| 79 | |||
| 80 | #define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) | ||
| 81 | #define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) | ||
| 82 | |||
| 83 | /* | ||
| 84 | * --------------------------------------------------------------------------- | ||
| 85 | * OMAP-1510 FPGA | ||
| 86 | * --------------------------------------------------------------------------- | ||
| 87 | */ | ||
| 88 | #define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */ | ||
| 89 | #define OMAP1510_FPGA_SIZE SZ_4K | ||
| 90 | #define OMAP1510_FPGA_START 0x08000000 /* Physical */ | ||
| 91 | |||
| 92 | /* Revision */ | ||
| 93 | #define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) | ||
| 94 | #define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1) | ||
| 95 | |||
| 96 | #define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2) | ||
| 97 | #define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3) | ||
| 98 | #define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4) | ||
| 99 | #define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5) | ||
| 100 | |||
| 101 | /* Interrupt status */ | ||
| 102 | #define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6) | ||
| 103 | #define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7) | ||
| 104 | |||
| 105 | /* Interrupt mask */ | ||
| 106 | #define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8) | ||
| 107 | #define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9) | ||
| 108 | |||
| 109 | /* Reset registers */ | ||
| 110 | #define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa) | ||
| 111 | #define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb) | ||
| 112 | |||
| 113 | #define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc) | ||
| 114 | #define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe) | ||
| 115 | #define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf) | ||
| 116 | #define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14) | ||
| 117 | #define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15) | ||
| 118 | #define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16) | ||
| 119 | #define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18) | ||
| 120 | #define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100) | ||
| 121 | #define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101) | ||
| 122 | #define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102) | ||
| 123 | |||
| 124 | #define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204) | ||
| 125 | |||
| 126 | #define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205) | ||
| 127 | #define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206) | ||
| 128 | #define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207) | ||
| 129 | #define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208) | ||
| 130 | #define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209) | ||
| 131 | #define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a) | ||
| 132 | #define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b) | ||
| 133 | #define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c) | ||
| 134 | #define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d) | ||
| 135 | #define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e) | ||
| 136 | #define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210) | ||
| 137 | |||
| 138 | #define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) | ||
| 139 | |||
| 140 | /* | ||
| 141 | * Power up Giga UART driver, turn on HID clock. | ||
| 142 | * Turn off BT power, since we're not using it and it | ||
| 143 | * draws power. | ||
| 144 | */ | ||
| 145 | #define OMAP1510_FPGA_RESET_VALUE 0x42 | ||
| 146 | |||
| 147 | #define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) | ||
| 148 | #define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) | ||
| 149 | #define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) | ||
| 150 | #define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) | ||
| 151 | #define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) | ||
| 152 | #define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) | ||
| 153 | #define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) | ||
| 154 | #define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) | ||
| 155 | |||
| 156 | /* | ||
| 157 | * Innovator/OMAP1510 FPGA HID register bit definitions | ||
| 158 | */ | ||
| 159 | #define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */ | ||
| 160 | #define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */ | ||
| 161 | #define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ | ||
| 162 | #define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ | ||
| 163 | #define OMAP1510_FPGA_HID_MISO (1<<4) /* input */ | ||
| 164 | #define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ | ||
| 165 | #define OMAP1510_FPGA_HID_rsrvd (1<<6) | ||
| 166 | #define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ | ||
| 167 | |||
| 168 | /* The FPGA IRQ is cascaded through GPIO_13 */ | ||
| 169 | #define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) | ||
| 170 | |||
| 171 | /* IRQ Numbers for interrupts muxed through the FPGA */ | ||
| 172 | #define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0) | ||
| 173 | #define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1) | ||
| 174 | #define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2) | ||
| 175 | #define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3) | ||
| 176 | #define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4) | ||
| 177 | #define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5) | ||
| 178 | #define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6) | ||
| 179 | #define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7) | ||
| 180 | #define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8) | ||
| 181 | #define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9) | ||
| 182 | #define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10) | ||
| 183 | #define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11) | ||
| 184 | #define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12) | ||
| 185 | #define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13) | ||
| 186 | #define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14) | ||
| 187 | #define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15) | ||
| 188 | #define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16) | ||
| 189 | #define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17) | ||
| 190 | #define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18) | ||
| 191 | #define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19) | ||
| 192 | #define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20) | ||
| 193 | #define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21) | ||
| 194 | #define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22) | ||
| 195 | #define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23) | ||
| 196 | |||
| 197 | #endif | ||
diff --git a/include/asm-arm/arch-omap/gpio-switch.h b/include/asm-arm/arch-omap/gpio-switch.h deleted file mode 100644 index 10da0e07c0cf..000000000000 --- a/include/asm-arm/arch-omap/gpio-switch.h +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * GPIO switch definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Nokia Corporation | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H | ||
| 12 | #define __ASM_ARCH_OMAP_GPIO_SWITCH_H | ||
| 13 | |||
| 14 | #include <linux/types.h> | ||
| 15 | |||
| 16 | /* Cover: | ||
| 17 | * high -> closed | ||
| 18 | * low -> open | ||
| 19 | * Connection: | ||
| 20 | * high -> connected | ||
| 21 | * low -> disconnected | ||
| 22 | * Activity: | ||
| 23 | * high -> active | ||
| 24 | * low -> inactive | ||
| 25 | * | ||
| 26 | */ | ||
| 27 | #define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000 | ||
| 28 | #define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001 | ||
| 29 | #define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002 | ||
| 30 | #define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001 | ||
| 31 | #define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002 | ||
| 32 | |||
| 33 | struct omap_gpio_switch { | ||
| 34 | const char *name; | ||
| 35 | s16 gpio; | ||
| 36 | unsigned flags:4; | ||
| 37 | unsigned type:4; | ||
| 38 | |||
| 39 | /* Time in ms to debounce when transitioning from | ||
| 40 | * inactive state to active state. */ | ||
| 41 | u16 debounce_rising; | ||
| 42 | /* Same for transition from active to inactive state. */ | ||
| 43 | u16 debounce_falling; | ||
| 44 | |||
| 45 | /* notify board-specific code about state changes */ | ||
| 46 | void (* notify)(void *data, int state); | ||
| 47 | void *notify_data; | ||
| 48 | }; | ||
| 49 | |||
| 50 | /* Call at init time only */ | ||
| 51 | extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl, | ||
| 52 | int count); | ||
| 53 | |||
| 54 | #endif | ||
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h deleted file mode 100644 index 5ee6a49864c3..000000000000 --- a/include/asm-arm/arch-omap/gpio.h +++ /dev/null | |||
| @@ -1,122 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/gpio.h | ||
| 3 | * | ||
| 4 | * OMAP GPIO handling defines and functions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003-2005 Nokia Corporation | ||
| 7 | * | ||
| 8 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 23 | * | ||
| 24 | */ | ||
| 25 | |||
| 26 | #ifndef __ASM_ARCH_OMAP_GPIO_H | ||
| 27 | #define __ASM_ARCH_OMAP_GPIO_H | ||
| 28 | |||
| 29 | #include <asm/arch/irqs.h> | ||
| 30 | #include <asm/io.h> | ||
| 31 | |||
| 32 | #define OMAP_MPUIO_BASE (void __iomem *)0xfffb5000 | ||
| 33 | |||
| 34 | #ifdef CONFIG_ARCH_OMAP730 | ||
| 35 | #define OMAP_MPUIO_INPUT_LATCH 0x00 | ||
| 36 | #define OMAP_MPUIO_OUTPUT 0x02 | ||
| 37 | #define OMAP_MPUIO_IO_CNTL 0x04 | ||
| 38 | #define OMAP_MPUIO_KBR_LATCH 0x08 | ||
| 39 | #define OMAP_MPUIO_KBC 0x0a | ||
| 40 | #define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c | ||
| 41 | #define OMAP_MPUIO_GPIO_INT_EDGE 0x0e | ||
| 42 | #define OMAP_MPUIO_KBD_INT 0x10 | ||
| 43 | #define OMAP_MPUIO_GPIO_INT 0x12 | ||
| 44 | #define OMAP_MPUIO_KBD_MASKIT 0x14 | ||
| 45 | #define OMAP_MPUIO_GPIO_MASKIT 0x16 | ||
| 46 | #define OMAP_MPUIO_GPIO_DEBOUNCING 0x18 | ||
| 47 | #define OMAP_MPUIO_LATCH 0x1a | ||
| 48 | #else | ||
| 49 | #define OMAP_MPUIO_INPUT_LATCH 0x00 | ||
| 50 | #define OMAP_MPUIO_OUTPUT 0x04 | ||
| 51 | #define OMAP_MPUIO_IO_CNTL 0x08 | ||
| 52 | #define OMAP_MPUIO_KBR_LATCH 0x10 | ||
| 53 | #define OMAP_MPUIO_KBC 0x14 | ||
| 54 | #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18 | ||
| 55 | #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c | ||
| 56 | #define OMAP_MPUIO_KBD_INT 0x20 | ||
| 57 | #define OMAP_MPUIO_GPIO_INT 0x24 | ||
| 58 | #define OMAP_MPUIO_KBD_MASKIT 0x28 | ||
| 59 | #define OMAP_MPUIO_GPIO_MASKIT 0x2c | ||
| 60 | #define OMAP_MPUIO_GPIO_DEBOUNCING 0x30 | ||
| 61 | #define OMAP_MPUIO_LATCH 0x34 | ||
| 62 | #endif | ||
| 63 | |||
| 64 | #define OMAP34XX_NR_GPIOS 6 | ||
| 65 | |||
| 66 | #define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) | ||
| 67 | #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) | ||
| 68 | |||
| 69 | #define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \ | ||
| 70 | IH_MPUIO_BASE + ((nr) & 0x0f) : \ | ||
| 71 | IH_GPIO_BASE + (nr)) | ||
| 72 | |||
| 73 | extern int omap_gpio_init(void); /* Call from board init only */ | ||
| 74 | extern int omap_request_gpio(int gpio); | ||
| 75 | extern void omap_free_gpio(int gpio); | ||
| 76 | extern void omap_set_gpio_direction(int gpio, int is_input); | ||
| 77 | extern void omap_set_gpio_dataout(int gpio, int enable); | ||
| 78 | extern int omap_get_gpio_datain(int gpio); | ||
| 79 | extern void omap_set_gpio_debounce(int gpio, int enable); | ||
| 80 | extern void omap_set_gpio_debounce_time(int gpio, int enable); | ||
| 81 | |||
| 82 | /*-------------------------------------------------------------------------*/ | ||
| 83 | |||
| 84 | /* Wrappers for "new style" GPIO calls, using the new infrastructure | ||
| 85 | * which lets us plug in FPGA, I2C, and other implementations. | ||
| 86 | * * | ||
| 87 | * The original OMAP-specfic calls should eventually be removed. | ||
| 88 | */ | ||
| 89 | |||
| 90 | #include <linux/errno.h> | ||
| 91 | #include <asm-generic/gpio.h> | ||
| 92 | |||
| 93 | static inline int gpio_get_value(unsigned gpio) | ||
| 94 | { | ||
| 95 | return __gpio_get_value(gpio); | ||
| 96 | } | ||
| 97 | |||
| 98 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 99 | { | ||
| 100 | __gpio_set_value(gpio, value); | ||
| 101 | } | ||
| 102 | |||
| 103 | static inline int gpio_cansleep(unsigned gpio) | ||
| 104 | { | ||
| 105 | return __gpio_cansleep(gpio); | ||
| 106 | } | ||
| 107 | |||
| 108 | static inline int gpio_to_irq(unsigned gpio) | ||
| 109 | { | ||
| 110 | if (gpio < (OMAP_MAX_GPIO_LINES + 16)) | ||
| 111 | return OMAP_GPIO_IRQ(gpio); | ||
| 112 | return -EINVAL; | ||
| 113 | } | ||
| 114 | |||
| 115 | static inline int irq_to_gpio(unsigned irq) | ||
| 116 | { | ||
| 117 | if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16))) | ||
| 118 | return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES; | ||
| 119 | return irq - IH_GPIO_BASE; | ||
| 120 | } | ||
| 121 | |||
| 122 | #endif | ||
diff --git a/include/asm-arm/arch-omap/gpioexpander.h b/include/asm-arm/arch-omap/gpioexpander.h deleted file mode 100644 index 4eed1f80e2fb..000000000000 --- a/include/asm-arm/arch-omap/gpioexpander.h +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/gpioexpander.h | ||
| 3 | * | ||
| 4 | * | ||
| 5 | * Copyright (C) 2004 Texas Instruments, Inc. | ||
| 6 | * | ||
| 7 | * This package is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR | ||
| 12 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED | ||
| 13 | * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_OMAP_GPIOEXPANDER_H | ||
| 17 | #define __ASM_ARCH_OMAP_GPIOEXPANDER_H | ||
| 18 | |||
| 19 | /* Function Prototypes for GPIO Expander functions */ | ||
| 20 | |||
| 21 | #ifdef CONFIG_GPIOEXPANDER_OMAP | ||
| 22 | int read_gpio_expa(u8 *, int); | ||
| 23 | int write_gpio_expa(u8 , int); | ||
| 24 | #else | ||
| 25 | static inline int read_gpio_expa(u8 *val, int addr) | ||
| 26 | { | ||
| 27 | return 0; | ||
| 28 | } | ||
| 29 | static inline int write_gpio_expa(u8 val, int addr) | ||
| 30 | { | ||
| 31 | return 0; | ||
| 32 | } | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #endif /* __ASM_ARCH_OMAP_GPIOEXPANDER_H */ | ||
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h deleted file mode 100644 index 6a8e07ffc2d0..000000000000 --- a/include/asm-arm/arch-omap/gpmc.h +++ /dev/null | |||
| @@ -1,96 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * General-Purpose Memory Controller for OMAP2 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2006 Nokia Corporation | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __OMAP2_GPMC_H | ||
| 12 | #define __OMAP2_GPMC_H | ||
| 13 | |||
| 14 | #define GPMC_CS_CONFIG1 0x00 | ||
| 15 | #define GPMC_CS_CONFIG2 0x04 | ||
| 16 | #define GPMC_CS_CONFIG3 0x08 | ||
| 17 | #define GPMC_CS_CONFIG4 0x0c | ||
| 18 | #define GPMC_CS_CONFIG5 0x10 | ||
| 19 | #define GPMC_CS_CONFIG6 0x14 | ||
| 20 | #define GPMC_CS_CONFIG7 0x18 | ||
| 21 | #define GPMC_CS_NAND_COMMAND 0x1c | ||
| 22 | #define GPMC_CS_NAND_ADDRESS 0x20 | ||
| 23 | #define GPMC_CS_NAND_DATA 0x24 | ||
| 24 | |||
| 25 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) | ||
| 26 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) | ||
| 27 | #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) | ||
| 28 | #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) | ||
| 29 | #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) | ||
| 30 | #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) | ||
| 31 | #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) | ||
| 32 | #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) | ||
| 33 | #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) | ||
| 34 | #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) | ||
| 35 | #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) | ||
| 36 | #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) | ||
| 37 | #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) | ||
| 38 | #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) | ||
| 39 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | ||
| 40 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) | ||
| 41 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | ||
| 42 | #define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1) | ||
| 43 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) | ||
| 44 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | ||
| 45 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | ||
| 46 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | ||
| 47 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) | ||
| 48 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Note that all values in this struct are in nanoseconds, while | ||
| 52 | * the register values are in gpmc_fck cycles. | ||
| 53 | */ | ||
| 54 | struct gpmc_timings { | ||
| 55 | /* Minimum clock period for synchronous mode */ | ||
| 56 | u16 sync_clk; | ||
| 57 | |||
| 58 | /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ | ||
| 59 | u16 cs_on; /* Assertion time */ | ||
| 60 | u16 cs_rd_off; /* Read deassertion time */ | ||
| 61 | u16 cs_wr_off; /* Write deassertion time */ | ||
| 62 | |||
| 63 | /* ADV signal timings corresponding to GPMC_CONFIG3 */ | ||
| 64 | u16 adv_on; /* Assertion time */ | ||
| 65 | u16 adv_rd_off; /* Read deassertion time */ | ||
| 66 | u16 adv_wr_off; /* Write deassertion time */ | ||
| 67 | |||
| 68 | /* WE signals timings corresponding to GPMC_CONFIG4 */ | ||
| 69 | u16 we_on; /* WE assertion time */ | ||
| 70 | u16 we_off; /* WE deassertion time */ | ||
| 71 | |||
| 72 | /* OE signals timings corresponding to GPMC_CONFIG4 */ | ||
| 73 | u16 oe_on; /* OE assertion time */ | ||
| 74 | u16 oe_off; /* OE deassertion time */ | ||
| 75 | |||
| 76 | /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ | ||
| 77 | u16 page_burst_access; /* Multiple access word delay */ | ||
| 78 | u16 access; /* Start-cycle to first data valid delay */ | ||
| 79 | u16 rd_cycle; /* Total read cycle time */ | ||
| 80 | u16 wr_cycle; /* Total write cycle time */ | ||
| 81 | }; | ||
| 82 | |||
| 83 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); | ||
| 84 | extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); | ||
| 85 | extern unsigned long gpmc_get_fclk_period(void); | ||
| 86 | |||
| 87 | extern void gpmc_cs_write_reg(int cs, int idx, u32 val); | ||
| 88 | extern u32 gpmc_cs_read_reg(int cs, int idx); | ||
| 89 | extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); | ||
| 90 | extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); | ||
| 91 | extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); | ||
| 92 | extern void gpmc_cs_free(int cs); | ||
| 93 | extern int gpmc_cs_set_reserved(int cs, int reserved); | ||
| 94 | extern int gpmc_cs_reserved(int cs); | ||
| 95 | |||
| 96 | #endif | ||
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h deleted file mode 100644 index 45fdfccbd5d4..000000000000 --- a/include/asm-arm/arch-omap/hardware.h +++ /dev/null | |||
| @@ -1,355 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/hardware.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP processors and boards | ||
| 5 | * | ||
| 6 | * NOTE: Please put device driver specific defines into a separate header | ||
| 7 | * file for each driver. | ||
| 8 | * | ||
| 9 | * Copyright (C) 2001 RidgeRun, Inc. | ||
| 10 | * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> | ||
| 11 | * | ||
| 12 | * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com> | ||
| 13 | * and Dirk Behme <dirk.behme@de.bosch.com> | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify it | ||
| 16 | * under the terms of the GNU General Public License as published by the | ||
| 17 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 18 | * option) any later version. | ||
| 19 | * | ||
| 20 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 21 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 23 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 26 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 30 | * | ||
| 31 | * You should have received a copy of the GNU General Public License along | ||
| 32 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 33 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 34 | */ | ||
| 35 | |||
| 36 | #ifndef __ASM_ARCH_OMAP_HARDWARE_H | ||
| 37 | #define __ASM_ARCH_OMAP_HARDWARE_H | ||
| 38 | |||
| 39 | #include <asm/sizes.h> | ||
| 40 | #ifndef __ASSEMBLER__ | ||
| 41 | #include <asm/types.h> | ||
| 42 | #include <asm/arch/cpu.h> | ||
| 43 | #endif | ||
| 44 | #include <asm/arch/serial.h> | ||
| 45 | |||
| 46 | /* | ||
| 47 | * --------------------------------------------------------------------------- | ||
| 48 | * Common definitions for all OMAP processors | ||
| 49 | * NOTE: Put all processor or board specific parts to the special header | ||
| 50 | * files. | ||
| 51 | * --------------------------------------------------------------------------- | ||
| 52 | */ | ||
| 53 | |||
| 54 | /* | ||
| 55 | * ---------------------------------------------------------------------------- | ||
| 56 | * Timers | ||
| 57 | * ---------------------------------------------------------------------------- | ||
| 58 | */ | ||
| 59 | #define OMAP_MPU_TIMER1_BASE (0xfffec500) | ||
| 60 | #define OMAP_MPU_TIMER2_BASE (0xfffec600) | ||
| 61 | #define OMAP_MPU_TIMER3_BASE (0xfffec700) | ||
| 62 | #define MPU_TIMER_FREE (1 << 6) | ||
| 63 | #define MPU_TIMER_CLOCK_ENABLE (1 << 5) | ||
| 64 | #define MPU_TIMER_AR (1 << 1) | ||
| 65 | #define MPU_TIMER_ST (1 << 0) | ||
| 66 | |||
| 67 | /* | ||
| 68 | * ---------------------------------------------------------------------------- | ||
| 69 | * Clocks | ||
| 70 | * ---------------------------------------------------------------------------- | ||
| 71 | */ | ||
| 72 | #define CLKGEN_REG_BASE (0xfffece00) | ||
| 73 | #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) | ||
| 74 | #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) | ||
| 75 | #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) | ||
| 76 | #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) | ||
| 77 | #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) | ||
| 78 | #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) | ||
| 79 | #define ARM_SYSST (CLKGEN_REG_BASE + 0x18) | ||
| 80 | #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) | ||
| 81 | |||
| 82 | #define CK_RATEF 1 | ||
| 83 | #define CK_IDLEF 2 | ||
| 84 | #define CK_ENABLEF 4 | ||
| 85 | #define CK_SELECTF 8 | ||
| 86 | #define SETARM_IDLE_SHIFT | ||
| 87 | |||
| 88 | /* DPLL control registers */ | ||
| 89 | #define DPLL_CTL (0xfffecf00) | ||
| 90 | |||
| 91 | /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ | ||
| 92 | #define DSP_CONFIG_REG_BASE (0xe1008000) | ||
| 93 | #define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) | ||
| 94 | #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) | ||
| 95 | #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) | ||
| 96 | #define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) | ||
| 97 | |||
| 98 | /* | ||
| 99 | * --------------------------------------------------------------------------- | ||
| 100 | * UPLD | ||
| 101 | * --------------------------------------------------------------------------- | ||
| 102 | */ | ||
| 103 | #define ULPD_REG_BASE (0xfffe0800) | ||
| 104 | #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) | ||
| 105 | #define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) | ||
| 106 | #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) | ||
| 107 | # define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ | ||
| 108 | # define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ | ||
| 109 | #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) | ||
| 110 | # define SOFT_UDC_REQ (1 << 4) | ||
| 111 | # define SOFT_USB_CLK_REQ (1 << 3) | ||
| 112 | # define SOFT_DPLL_REQ (1 << 0) | ||
| 113 | #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) | ||
| 114 | #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) | ||
| 115 | #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) | ||
| 116 | #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) | ||
| 117 | #define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) | ||
| 118 | # define DIS_MMC2_DPLL_REQ (1 << 11) | ||
| 119 | # define DIS_MMC1_DPLL_REQ (1 << 10) | ||
| 120 | # define DIS_UART3_DPLL_REQ (1 << 9) | ||
| 121 | # define DIS_UART2_DPLL_REQ (1 << 8) | ||
| 122 | # define DIS_UART1_DPLL_REQ (1 << 7) | ||
| 123 | # define DIS_USB_HOST_DPLL_REQ (1 << 6) | ||
| 124 | #define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) | ||
| 125 | #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) | ||
| 126 | |||
| 127 | /* | ||
| 128 | * --------------------------------------------------------------------------- | ||
| 129 | * Watchdog timer | ||
| 130 | * --------------------------------------------------------------------------- | ||
| 131 | */ | ||
| 132 | |||
| 133 | /* Watchdog timer within the OMAP3.2 gigacell */ | ||
| 134 | #define OMAP_MPU_WATCHDOG_BASE (0xfffec800) | ||
| 135 | #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) | ||
| 136 | #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) | ||
| 137 | #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) | ||
| 138 | #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) | ||
| 139 | |||
| 140 | /* | ||
| 141 | * --------------------------------------------------------------------------- | ||
| 142 | * Interrupts | ||
| 143 | * --------------------------------------------------------------------------- | ||
| 144 | */ | ||
| 145 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 146 | |||
| 147 | /* | ||
| 148 | * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c | ||
| 149 | * or something similar.. -- PFM. | ||
| 150 | */ | ||
| 151 | |||
| 152 | #define OMAP_IH1_BASE 0xfffecb00 | ||
| 153 | #define OMAP_IH2_BASE 0xfffe0000 | ||
| 154 | |||
| 155 | #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) | ||
| 156 | #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) | ||
| 157 | #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) | ||
| 158 | #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) | ||
| 159 | #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) | ||
| 160 | #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) | ||
| 161 | #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) | ||
| 162 | |||
| 163 | #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) | ||
| 164 | #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) | ||
| 165 | #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) | ||
| 166 | #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) | ||
| 167 | #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) | ||
| 168 | #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) | ||
| 169 | #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) | ||
| 170 | |||
| 171 | #define IRQ_ITR_REG_OFFSET 0x00 | ||
| 172 | #define IRQ_MIR_REG_OFFSET 0x04 | ||
| 173 | #define IRQ_SIR_IRQ_REG_OFFSET 0x10 | ||
| 174 | #define IRQ_SIR_FIQ_REG_OFFSET 0x14 | ||
| 175 | #define IRQ_CONTROL_REG_OFFSET 0x18 | ||
| 176 | #define IRQ_ISR_REG_OFFSET 0x9c | ||
| 177 | #define IRQ_ILR0_REG_OFFSET 0x1c | ||
| 178 | #define IRQ_GMR_REG_OFFSET 0xa0 | ||
| 179 | |||
| 180 | #endif | ||
| 181 | |||
| 182 | /* | ||
| 183 | * ---------------------------------------------------------------------------- | ||
| 184 | * System control registers | ||
| 185 | * ---------------------------------------------------------------------------- | ||
| 186 | */ | ||
| 187 | #define MOD_CONF_CTRL_0 0xfffe1080 | ||
| 188 | #define MOD_CONF_CTRL_1 0xfffe1110 | ||
| 189 | |||
| 190 | /* | ||
| 191 | * ---------------------------------------------------------------------------- | ||
| 192 | * Pin multiplexing registers | ||
| 193 | * ---------------------------------------------------------------------------- | ||
| 194 | */ | ||
| 195 | #define FUNC_MUX_CTRL_0 0xfffe1000 | ||
| 196 | #define FUNC_MUX_CTRL_1 0xfffe1004 | ||
| 197 | #define FUNC_MUX_CTRL_2 0xfffe1008 | ||
| 198 | #define COMP_MODE_CTRL_0 0xfffe100c | ||
| 199 | #define FUNC_MUX_CTRL_3 0xfffe1010 | ||
| 200 | #define FUNC_MUX_CTRL_4 0xfffe1014 | ||
| 201 | #define FUNC_MUX_CTRL_5 0xfffe1018 | ||
| 202 | #define FUNC_MUX_CTRL_6 0xfffe101C | ||
| 203 | #define FUNC_MUX_CTRL_7 0xfffe1020 | ||
| 204 | #define FUNC_MUX_CTRL_8 0xfffe1024 | ||
| 205 | #define FUNC_MUX_CTRL_9 0xfffe1028 | ||
| 206 | #define FUNC_MUX_CTRL_A 0xfffe102C | ||
| 207 | #define FUNC_MUX_CTRL_B 0xfffe1030 | ||
| 208 | #define FUNC_MUX_CTRL_C 0xfffe1034 | ||
| 209 | #define FUNC_MUX_CTRL_D 0xfffe1038 | ||
| 210 | #define PULL_DWN_CTRL_0 0xfffe1040 | ||
| 211 | #define PULL_DWN_CTRL_1 0xfffe1044 | ||
| 212 | #define PULL_DWN_CTRL_2 0xfffe1048 | ||
| 213 | #define PULL_DWN_CTRL_3 0xfffe104c | ||
| 214 | #define PULL_DWN_CTRL_4 0xfffe10ac | ||
| 215 | |||
| 216 | /* OMAP-1610 specific multiplexing registers */ | ||
| 217 | #define FUNC_MUX_CTRL_E 0xfffe1090 | ||
| 218 | #define FUNC_MUX_CTRL_F 0xfffe1094 | ||
| 219 | #define FUNC_MUX_CTRL_10 0xfffe1098 | ||
| 220 | #define FUNC_MUX_CTRL_11 0xfffe109c | ||
| 221 | #define FUNC_MUX_CTRL_12 0xfffe10a0 | ||
| 222 | #define PU_PD_SEL_0 0xfffe10b4 | ||
| 223 | #define PU_PD_SEL_1 0xfffe10b8 | ||
| 224 | #define PU_PD_SEL_2 0xfffe10bc | ||
| 225 | #define PU_PD_SEL_3 0xfffe10c0 | ||
| 226 | #define PU_PD_SEL_4 0xfffe10c4 | ||
| 227 | |||
| 228 | /* Timer32K for 1610 and 1710*/ | ||
| 229 | #define OMAP_TIMER32K_BASE 0xFFFBC400 | ||
| 230 | |||
| 231 | /* | ||
| 232 | * --------------------------------------------------------------------------- | ||
| 233 | * TIPB bus interface | ||
| 234 | * --------------------------------------------------------------------------- | ||
| 235 | */ | ||
| 236 | #define TIPB_PUBLIC_CNTL_BASE 0xfffed300 | ||
| 237 | #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) | ||
| 238 | #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 | ||
| 239 | #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) | ||
| 240 | |||
| 241 | /* | ||
| 242 | * ---------------------------------------------------------------------------- | ||
| 243 | * MPUI interface | ||
| 244 | * ---------------------------------------------------------------------------- | ||
| 245 | */ | ||
| 246 | #define MPUI_BASE (0xfffec900) | ||
| 247 | #define MPUI_CTRL (MPUI_BASE + 0x0) | ||
| 248 | #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) | ||
| 249 | #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) | ||
| 250 | #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) | ||
| 251 | #define MPUI_STATUS_REG (MPUI_BASE + 0x10) | ||
| 252 | #define MPUI_DSP_STATUS (MPUI_BASE + 0x14) | ||
| 253 | #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) | ||
| 254 | #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) | ||
| 255 | |||
| 256 | /* | ||
| 257 | * ---------------------------------------------------------------------------- | ||
| 258 | * LED Pulse Generator | ||
| 259 | * ---------------------------------------------------------------------------- | ||
| 260 | */ | ||
| 261 | #define OMAP_LPG1_BASE 0xfffbd000 | ||
| 262 | #define OMAP_LPG2_BASE 0xfffbd800 | ||
| 263 | #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) | ||
| 264 | #define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) | ||
| 265 | #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) | ||
| 266 | #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) | ||
| 267 | |||
| 268 | /* | ||
| 269 | * ---------------------------------------------------------------------------- | ||
| 270 | * Pulse-Width Light | ||
| 271 | * ---------------------------------------------------------------------------- | ||
| 272 | */ | ||
| 273 | #define OMAP_PWL_BASE 0xfffb5800 | ||
| 274 | #define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) | ||
| 275 | #define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) | ||
| 276 | |||
| 277 | /* | ||
| 278 | * --------------------------------------------------------------------------- | ||
| 279 | * Processor specific defines | ||
| 280 | * --------------------------------------------------------------------------- | ||
| 281 | */ | ||
| 282 | |||
| 283 | #include "omap730.h" | ||
| 284 | #include "omap1510.h" | ||
| 285 | #include "omap24xx.h" | ||
| 286 | #include "omap16xx.h" | ||
| 287 | #include "omap34xx.h" | ||
| 288 | |||
| 289 | #ifndef __ASSEMBLER__ | ||
| 290 | |||
| 291 | /* | ||
| 292 | * --------------------------------------------------------------------------- | ||
| 293 | * Board specific defines | ||
| 294 | * --------------------------------------------------------------------------- | ||
| 295 | */ | ||
| 296 | |||
| 297 | #ifdef CONFIG_MACH_OMAP_INNOVATOR | ||
| 298 | #include "board-innovator.h" | ||
| 299 | #endif | ||
| 300 | |||
| 301 | #ifdef CONFIG_MACH_OMAP_H2 | ||
| 302 | #include "board-h2.h" | ||
| 303 | #endif | ||
| 304 | |||
| 305 | #ifdef CONFIG_MACH_OMAP_PERSEUS2 | ||
| 306 | #include "board-perseus2.h" | ||
| 307 | #endif | ||
| 308 | |||
| 309 | #ifdef CONFIG_MACH_OMAP_FSAMPLE | ||
| 310 | #include "board-fsample.h" | ||
| 311 | #endif | ||
| 312 | |||
| 313 | #ifdef CONFIG_MACH_OMAP_H3 | ||
| 314 | #include "board-h3.h" | ||
| 315 | #endif | ||
| 316 | |||
| 317 | #ifdef CONFIG_MACH_OMAP_H4 | ||
| 318 | #include "board-h4.h" | ||
| 319 | #endif | ||
| 320 | |||
| 321 | #ifdef CONFIG_MACH_OMAP_2430SDP | ||
| 322 | #include "board-2430sdp.h" | ||
| 323 | #endif | ||
| 324 | |||
| 325 | #ifdef CONFIG_MACH_OMAP_APOLLON | ||
| 326 | #include "board-apollon.h" | ||
| 327 | #endif | ||
| 328 | |||
| 329 | #ifdef CONFIG_MACH_OMAP_OSK | ||
| 330 | #include "board-osk.h" | ||
| 331 | #endif | ||
| 332 | |||
| 333 | #ifdef CONFIG_MACH_VOICEBLUE | ||
| 334 | #include "board-voiceblue.h" | ||
| 335 | #endif | ||
| 336 | |||
| 337 | #ifdef CONFIG_MACH_OMAP_PALMTE | ||
| 338 | #include "board-palmte.h" | ||
| 339 | #endif | ||
| 340 | |||
| 341 | #ifdef CONFIG_MACH_OMAP_PALMZ71 | ||
| 342 | #include "board-palmz71.h" | ||
| 343 | #endif | ||
| 344 | |||
| 345 | #ifdef CONFIG_MACH_OMAP_PALMTT | ||
| 346 | #include "board-palmtt.h" | ||
| 347 | #endif | ||
| 348 | |||
| 349 | #ifdef CONFIG_MACH_SX1 | ||
| 350 | #include "board-sx1.h" | ||
| 351 | #endif | ||
| 352 | |||
| 353 | #endif /* !__ASSEMBLER__ */ | ||
| 354 | |||
| 355 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-omap/hwa742.h b/include/asm-arm/arch-omap/hwa742.h deleted file mode 100644 index 577f492f2d3c..000000000000 --- a/include/asm-arm/arch-omap/hwa742.h +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | #ifndef _HWA742_H | ||
| 2 | #define _HWA742_H | ||
| 3 | |||
| 4 | struct hwa742_platform_data { | ||
| 5 | void (*power_up)(struct device *dev); | ||
| 6 | void (*power_down)(struct device *dev); | ||
| 7 | unsigned long (*get_clock_rate)(struct device *dev); | ||
| 8 | |||
| 9 | unsigned te_connected:1; | ||
| 10 | }; | ||
| 11 | |||
| 12 | #endif | ||
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h deleted file mode 100644 index 449e3568baa6..000000000000 --- a/include/asm-arm/arch-omap/io.h +++ /dev/null | |||
| @@ -1,197 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/io.h | ||
| 3 | * | ||
| 4 | * IO definitions for TI OMAP processors and boards | ||
| 5 | * | ||
| 6 | * Copied from linux/include/asm-arm/arch-sa1100/io.h | ||
| 7 | * Copyright (C) 1997-1999 Russell King | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | * | ||
| 14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License along | ||
| 26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 28 | * | ||
| 29 | * Modifications: | ||
| 30 | * 06-12-1997 RMK Created. | ||
| 31 | * 07-04-1999 RMK Major cleanup | ||
| 32 | */ | ||
| 33 | |||
| 34 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 35 | #define __ASM_ARM_ARCH_IO_H | ||
| 36 | |||
| 37 | #include <asm/arch/hardware.h> | ||
| 38 | |||
| 39 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 40 | |||
| 41 | /* | ||
| 42 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
| 43 | * drivers out there that might just work if we fake them... | ||
| 44 | */ | ||
| 45 | #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) | ||
| 46 | #define __mem_pci(a) (a) | ||
| 47 | |||
| 48 | /* | ||
| 49 | * ---------------------------------------------------------------------------- | ||
| 50 | * I/O mapping | ||
| 51 | * ---------------------------------------------------------------------------- | ||
| 52 | */ | ||
| 53 | |||
| 54 | #define PCIO_BASE 0 | ||
| 55 | |||
| 56 | #if defined(CONFIG_ARCH_OMAP1) | ||
| 57 | |||
| 58 | #define IO_PHYS 0xFFFB0000 | ||
| 59 | #define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ | ||
| 60 | #define IO_SIZE 0x40000 | ||
| 61 | #define IO_VIRT (IO_PHYS - IO_OFFSET) | ||
| 62 | #define IO_ADDRESS(pa) ((pa) - IO_OFFSET) | ||
| 63 | #define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET) | ||
| 64 | #define io_p2v(pa) ((pa) - IO_OFFSET) | ||
| 65 | #define io_v2p(va) ((va) + IO_OFFSET) | ||
| 66 | |||
| 67 | #elif defined(CONFIG_ARCH_OMAP2) | ||
| 68 | |||
| 69 | /* We map both L3 and L4 on OMAP2 */ | ||
| 70 | #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */ | ||
| 71 | #define L3_24XX_VIRT 0xf8000000 | ||
| 72 | #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ | ||
| 73 | #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */ | ||
| 74 | #define L4_24XX_VIRT 0xd8000000 | ||
| 75 | #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ | ||
| 76 | |||
| 77 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 78 | #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ | ||
| 79 | #define L4_WK_243X_VIRT 0xd9000000 | ||
| 80 | #define L4_WK_243X_SIZE SZ_1M | ||
| 81 | #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ | ||
| 82 | #define OMAP243X_GPMC_VIRT 0xFE000000 | ||
| 83 | #define OMAP243X_GPMC_SIZE SZ_1M | ||
| 84 | #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE | ||
| 85 | #define OMAP243X_SDRC_VIRT 0xFD000000 | ||
| 86 | #define OMAP243X_SDRC_SIZE SZ_1M | ||
| 87 | #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE | ||
| 88 | #define OMAP243X_SMS_VIRT 0xFC000000 | ||
| 89 | #define OMAP243X_SMS_SIZE SZ_1M | ||
| 90 | |||
| 91 | #endif | ||
| 92 | |||
| 93 | #define IO_OFFSET 0x90000000 | ||
| 94 | #define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ | ||
| 95 | #define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ | ||
| 96 | #define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ | ||
| 97 | #define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ | ||
| 98 | |||
| 99 | /* DSP */ | ||
| 100 | #define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */ | ||
| 101 | #define DSP_MEM_24XX_VIRT 0xe0000000 | ||
| 102 | #define DSP_MEM_24XX_SIZE 0x28000 | ||
| 103 | #define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */ | ||
| 104 | #define DSP_IPI_24XX_VIRT 0xe1000000 | ||
| 105 | #define DSP_IPI_24XX_SIZE SZ_4K | ||
| 106 | #define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */ | ||
| 107 | #define DSP_MMU_24XX_VIRT 0xe2000000 | ||
| 108 | #define DSP_MMU_24XX_SIZE SZ_4K | ||
| 109 | |||
| 110 | #elif defined(CONFIG_ARCH_OMAP3) | ||
| 111 | |||
| 112 | /* We map both L3 and L4 on OMAP3 */ | ||
| 113 | #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */ | ||
| 114 | #define L3_34XX_VIRT 0xf8000000 | ||
| 115 | #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ | ||
| 116 | |||
| 117 | #define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */ | ||
| 118 | #define L4_34XX_VIRT 0xd8000000 | ||
| 119 | #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ | ||
| 120 | |||
| 121 | /* | ||
| 122 | * Need to look at the Size 4M for L4. | ||
| 123 | * VPOM3430 was not working for Int controller | ||
| 124 | */ | ||
| 125 | |||
| 126 | #define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */ | ||
| 127 | #define L4_WK_34XX_VIRT 0xd8300000 | ||
| 128 | #define L4_WK_34XX_SIZE SZ_1M | ||
| 129 | |||
| 130 | #define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */ | ||
| 131 | #define L4_PER_34XX_VIRT 0xd9000000 | ||
| 132 | #define L4_PER_34XX_SIZE SZ_1M | ||
| 133 | |||
| 134 | #define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */ | ||
| 135 | #define L4_EMU_34XX_VIRT 0xe4000000 | ||
| 136 | #define L4_EMU_34XX_SIZE SZ_64M | ||
| 137 | |||
| 138 | #define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */ | ||
| 139 | #define OMAP34XX_GPMC_VIRT 0xFE000000 | ||
| 140 | #define OMAP34XX_GPMC_SIZE SZ_1M | ||
| 141 | |||
| 142 | #define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */ | ||
| 143 | #define OMAP343X_SMS_VIRT 0xFC000000 | ||
| 144 | #define OMAP343X_SMS_SIZE SZ_1M | ||
| 145 | |||
| 146 | #define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */ | ||
| 147 | #define OMAP343X_SDRC_VIRT 0xFD000000 | ||
| 148 | #define OMAP343X_SDRC_SIZE SZ_1M | ||
| 149 | |||
| 150 | |||
| 151 | #define IO_OFFSET 0x90000000 | ||
| 152 | #define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ | ||
| 153 | #define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ | ||
| 154 | #define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ | ||
| 155 | #define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ | ||
| 156 | |||
| 157 | /* DSP */ | ||
| 158 | #define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */ | ||
| 159 | #define DSP_MEM_34XX_VIRT 0xe0000000 | ||
| 160 | #define DSP_MEM_34XX_SIZE 0x28000 | ||
| 161 | #define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */ | ||
| 162 | #define DSP_IPI_34XX_VIRT 0xe1000000 | ||
| 163 | #define DSP_IPI_34XX_SIZE SZ_4K | ||
| 164 | #define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */ | ||
| 165 | #define DSP_MMU_34XX_VIRT 0xe2000000 | ||
| 166 | #define DSP_MMU_34XX_SIZE SZ_4K | ||
| 167 | |||
| 168 | #endif | ||
| 169 | |||
| 170 | #ifndef __ASSEMBLER__ | ||
| 171 | |||
| 172 | /* | ||
| 173 | * Functions to access the OMAP IO region | ||
| 174 | * | ||
| 175 | * NOTE: - Use omap_read/write[bwl] for physical register addresses | ||
| 176 | * - Use __raw_read/write[bwl]() for virtual register addresses | ||
| 177 | * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses | ||
| 178 | * - DO NOT use hardcoded virtual addresses to allow changing the | ||
| 179 | * IO address space again if needed | ||
| 180 | */ | ||
| 181 | #define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) | ||
| 182 | #define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) | ||
| 183 | #define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) | ||
| 184 | |||
| 185 | #define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) | ||
| 186 | #define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) | ||
| 187 | #define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) | ||
| 188 | |||
| 189 | extern void omap1_map_common_io(void); | ||
| 190 | extern void omap1_init_common_hw(void); | ||
| 191 | |||
| 192 | extern void omap2_map_common_io(void); | ||
| 193 | extern void omap2_init_common_hw(void); | ||
| 194 | |||
| 195 | #endif | ||
| 196 | |||
| 197 | #endif | ||
diff --git a/include/asm-arm/arch-omap/irda.h b/include/asm-arm/arch-omap/irda.h deleted file mode 100644 index 96bb12fab438..000000000000 --- a/include/asm-arm/arch-omap/irda.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/irda.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #ifndef ASMARM_ARCH_IRDA_H | ||
| 11 | #define ASMARM_ARCH_IRDA_H | ||
| 12 | |||
| 13 | /* board specific transceiver capabilities */ | ||
| 14 | |||
| 15 | #define IR_SEL 1 /* Selects IrDA */ | ||
| 16 | #define IR_SIRMODE 2 | ||
| 17 | #define IR_FIRMODE 4 | ||
| 18 | #define IR_MIRMODE 8 | ||
| 19 | |||
| 20 | struct omap_irda_config { | ||
| 21 | int transceiver_cap; | ||
| 22 | int (*transceiver_mode)(struct device *dev, int mode); | ||
| 23 | int (*select_irda)(struct device *dev, int state); | ||
| 24 | /* Very specific to the needs of some platforms (h3,h4) | ||
| 25 | * having calls which can sleep in irda_set_speed. | ||
| 26 | */ | ||
| 27 | struct delayed_work gpio_expa; | ||
| 28 | int rx_channel; | ||
| 29 | int tx_channel; | ||
| 30 | unsigned long dest_start; | ||
| 31 | unsigned long src_start; | ||
| 32 | int tx_trigger; | ||
| 33 | int rx_trigger; | ||
| 34 | int mode; | ||
| 35 | }; | ||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h deleted file mode 100644 index afbf1e846468..000000000000 --- a/include/asm-arm/arch-omap/irqs.h +++ /dev/null | |||
| @@ -1,332 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) Greg Lonnon 2001 | ||
| 5 | * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | * | ||
| 21 | * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 | ||
| 22 | * are different. | ||
| 23 | */ | ||
| 24 | |||
| 25 | #ifndef __ASM_ARCH_OMAP15XX_IRQS_H | ||
| 26 | #define __ASM_ARCH_OMAP15XX_IRQS_H | ||
| 27 | |||
| 28 | /* | ||
| 29 | * IRQ numbers for interrupt handler 1 | ||
| 30 | * | ||
| 31 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below | ||
| 32 | * | ||
| 33 | */ | ||
| 34 | #define INT_CAMERA 1 | ||
| 35 | #define INT_FIQ 3 | ||
| 36 | #define INT_RTDX 6 | ||
| 37 | #define INT_DSP_MMU_ABORT 7 | ||
| 38 | #define INT_HOST 8 | ||
| 39 | #define INT_ABORT 9 | ||
| 40 | #define INT_BRIDGE_PRIV 13 | ||
| 41 | #define INT_GPIO_BANK1 14 | ||
| 42 | #define INT_UART3 15 | ||
| 43 | #define INT_TIMER3 16 | ||
| 44 | #define INT_DMA_CH0_6 19 | ||
| 45 | #define INT_DMA_CH1_7 20 | ||
| 46 | #define INT_DMA_CH2_8 21 | ||
| 47 | #define INT_DMA_CH3 22 | ||
| 48 | #define INT_DMA_CH4 23 | ||
| 49 | #define INT_DMA_CH5 24 | ||
| 50 | #define INT_DMA_LCD 25 | ||
| 51 | #define INT_TIMER1 26 | ||
| 52 | #define INT_WD_TIMER 27 | ||
| 53 | #define INT_BRIDGE_PUB 28 | ||
| 54 | #define INT_TIMER2 30 | ||
| 55 | #define INT_LCD_CTRL 31 | ||
| 56 | |||
| 57 | /* | ||
| 58 | * OMAP-1510 specific IRQ numbers for interrupt handler 1 | ||
| 59 | */ | ||
| 60 | #define INT_1510_IH2_IRQ 0 | ||
| 61 | #define INT_1510_RES2 2 | ||
| 62 | #define INT_1510_SPI_TX 4 | ||
| 63 | #define INT_1510_SPI_RX 5 | ||
| 64 | #define INT_1510_DSP_MAILBOX1 10 | ||
| 65 | #define INT_1510_DSP_MAILBOX2 11 | ||
| 66 | #define INT_1510_RES12 12 | ||
| 67 | #define INT_1510_LB_MMU 17 | ||
| 68 | #define INT_1510_RES18 18 | ||
| 69 | #define INT_1510_LOCAL_BUS 29 | ||
| 70 | |||
| 71 | /* | ||
| 72 | * OMAP-1610 specific IRQ numbers for interrupt handler 1 | ||
| 73 | */ | ||
| 74 | #define INT_1610_IH2_IRQ 0 | ||
| 75 | #define INT_1610_IH2_FIQ 2 | ||
| 76 | #define INT_1610_McBSP2_TX 4 | ||
| 77 | #define INT_1610_McBSP2_RX 5 | ||
| 78 | #define INT_1610_DSP_MAILBOX1 10 | ||
| 79 | #define INT_1610_DSP_MAILBOX2 11 | ||
| 80 | #define INT_1610_LCD_LINE 12 | ||
| 81 | #define INT_1610_GPTIMER1 17 | ||
| 82 | #define INT_1610_GPTIMER2 18 | ||
| 83 | #define INT_1610_SSR_FIFO_0 29 | ||
| 84 | |||
| 85 | /* | ||
| 86 | * OMAP-730 specific IRQ numbers for interrupt handler 1 | ||
| 87 | */ | ||
| 88 | #define INT_730_IH2_FIQ 0 | ||
| 89 | #define INT_730_IH2_IRQ 1 | ||
| 90 | #define INT_730_USB_NON_ISO 2 | ||
| 91 | #define INT_730_USB_ISO 3 | ||
| 92 | #define INT_730_ICR 4 | ||
| 93 | #define INT_730_EAC 5 | ||
| 94 | #define INT_730_GPIO_BANK1 6 | ||
| 95 | #define INT_730_GPIO_BANK2 7 | ||
| 96 | #define INT_730_GPIO_BANK3 8 | ||
| 97 | #define INT_730_McBSP2TX 10 | ||
| 98 | #define INT_730_McBSP2RX 11 | ||
| 99 | #define INT_730_McBSP2RX_OVF 12 | ||
| 100 | #define INT_730_LCD_LINE 14 | ||
| 101 | #define INT_730_GSM_PROTECT 15 | ||
| 102 | #define INT_730_TIMER3 16 | ||
| 103 | #define INT_730_GPIO_BANK5 17 | ||
| 104 | #define INT_730_GPIO_BANK6 18 | ||
| 105 | #define INT_730_SPGIO_WR 29 | ||
| 106 | |||
| 107 | /* | ||
| 108 | * IRQ numbers for interrupt handler 2 | ||
| 109 | * | ||
| 110 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below | ||
| 111 | */ | ||
| 112 | #define IH2_BASE 32 | ||
| 113 | |||
| 114 | #define INT_KEYBOARD (1 + IH2_BASE) | ||
| 115 | #define INT_uWireTX (2 + IH2_BASE) | ||
| 116 | #define INT_uWireRX (3 + IH2_BASE) | ||
| 117 | #define INT_I2C (4 + IH2_BASE) | ||
| 118 | #define INT_MPUIO (5 + IH2_BASE) | ||
| 119 | #define INT_USB_HHC_1 (6 + IH2_BASE) | ||
| 120 | #define INT_McBSP3TX (10 + IH2_BASE) | ||
| 121 | #define INT_McBSP3RX (11 + IH2_BASE) | ||
| 122 | #define INT_McBSP1TX (12 + IH2_BASE) | ||
| 123 | #define INT_McBSP1RX (13 + IH2_BASE) | ||
| 124 | #define INT_UART1 (14 + IH2_BASE) | ||
| 125 | #define INT_UART2 (15 + IH2_BASE) | ||
| 126 | #define INT_BT_MCSI1TX (16 + IH2_BASE) | ||
| 127 | #define INT_BT_MCSI1RX (17 + IH2_BASE) | ||
| 128 | #define INT_USB_W2FC (20 + IH2_BASE) | ||
| 129 | #define INT_1WIRE (21 + IH2_BASE) | ||
| 130 | #define INT_OS_TIMER (22 + IH2_BASE) | ||
| 131 | #define INT_MMC (23 + IH2_BASE) | ||
| 132 | #define INT_GAUGE_32K (24 + IH2_BASE) | ||
| 133 | #define INT_RTC_TIMER (25 + IH2_BASE) | ||
| 134 | #define INT_RTC_ALARM (26 + IH2_BASE) | ||
| 135 | #define INT_MEM_STICK (27 + IH2_BASE) | ||
| 136 | |||
| 137 | /* | ||
| 138 | * OMAP-1510 specific IRQ numbers for interrupt handler 2 | ||
| 139 | */ | ||
| 140 | #define INT_1510_DSP_MMU (28 + IH2_BASE) | ||
| 141 | #define INT_1510_COM_SPI_RO (31 + IH2_BASE) | ||
| 142 | |||
| 143 | /* | ||
| 144 | * OMAP-1610 specific IRQ numbers for interrupt handler 2 | ||
| 145 | */ | ||
| 146 | #define INT_1610_FAC (0 + IH2_BASE) | ||
| 147 | #define INT_1610_USB_HHC_2 (7 + IH2_BASE) | ||
| 148 | #define INT_1610_USB_OTG (8 + IH2_BASE) | ||
| 149 | #define INT_1610_SoSSI (9 + IH2_BASE) | ||
| 150 | #define INT_1610_SoSSI_MATCH (19 + IH2_BASE) | ||
| 151 | #define INT_1610_DSP_MMU (28 + IH2_BASE) | ||
| 152 | #define INT_1610_McBSP2RX_OF (31 + IH2_BASE) | ||
| 153 | #define INT_1610_STI (32 + IH2_BASE) | ||
| 154 | #define INT_1610_STI_WAKEUP (33 + IH2_BASE) | ||
| 155 | #define INT_1610_GPTIMER3 (34 + IH2_BASE) | ||
| 156 | #define INT_1610_GPTIMER4 (35 + IH2_BASE) | ||
| 157 | #define INT_1610_GPTIMER5 (36 + IH2_BASE) | ||
| 158 | #define INT_1610_GPTIMER6 (37 + IH2_BASE) | ||
| 159 | #define INT_1610_GPTIMER7 (38 + IH2_BASE) | ||
| 160 | #define INT_1610_GPTIMER8 (39 + IH2_BASE) | ||
| 161 | #define INT_1610_GPIO_BANK2 (40 + IH2_BASE) | ||
| 162 | #define INT_1610_GPIO_BANK3 (41 + IH2_BASE) | ||
| 163 | #define INT_1610_MMC2 (42 + IH2_BASE) | ||
| 164 | #define INT_1610_CF (43 + IH2_BASE) | ||
| 165 | #define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) | ||
| 166 | #define INT_1610_GPIO_BANK4 (48 + IH2_BASE) | ||
| 167 | #define INT_1610_SPI (49 + IH2_BASE) | ||
| 168 | #define INT_1610_DMA_CH6 (53 + IH2_BASE) | ||
| 169 | #define INT_1610_DMA_CH7 (54 + IH2_BASE) | ||
| 170 | #define INT_1610_DMA_CH8 (55 + IH2_BASE) | ||
| 171 | #define INT_1610_DMA_CH9 (56 + IH2_BASE) | ||
| 172 | #define INT_1610_DMA_CH10 (57 + IH2_BASE) | ||
| 173 | #define INT_1610_DMA_CH11 (58 + IH2_BASE) | ||
| 174 | #define INT_1610_DMA_CH12 (59 + IH2_BASE) | ||
| 175 | #define INT_1610_DMA_CH13 (60 + IH2_BASE) | ||
| 176 | #define INT_1610_DMA_CH14 (61 + IH2_BASE) | ||
| 177 | #define INT_1610_DMA_CH15 (62 + IH2_BASE) | ||
| 178 | #define INT_1610_NAND (63 + IH2_BASE) | ||
| 179 | |||
| 180 | /* | ||
| 181 | * OMAP-730 specific IRQ numbers for interrupt handler 2 | ||
| 182 | */ | ||
| 183 | #define INT_730_HW_ERRORS (0 + IH2_BASE) | ||
| 184 | #define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE) | ||
| 185 | #define INT_730_CFCD (2 + IH2_BASE) | ||
| 186 | #define INT_730_CFIREQ (3 + IH2_BASE) | ||
| 187 | #define INT_730_I2C (4 + IH2_BASE) | ||
| 188 | #define INT_730_PCC (5 + IH2_BASE) | ||
| 189 | #define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE) | ||
| 190 | #define INT_730_SPI_100K_1 (7 + IH2_BASE) | ||
| 191 | #define INT_730_SYREN_SPI (8 + IH2_BASE) | ||
| 192 | #define INT_730_VLYNQ (9 + IH2_BASE) | ||
| 193 | #define INT_730_GPIO_BANK4 (10 + IH2_BASE) | ||
| 194 | #define INT_730_McBSP1TX (11 + IH2_BASE) | ||
| 195 | #define INT_730_McBSP1RX (12 + IH2_BASE) | ||
| 196 | #define INT_730_McBSP1RX_OF (13 + IH2_BASE) | ||
| 197 | #define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE) | ||
| 198 | #define INT_730_UART_MODEM_1 (15 + IH2_BASE) | ||
| 199 | #define INT_730_MCSI (16 + IH2_BASE) | ||
| 200 | #define INT_730_uWireTX (17 + IH2_BASE) | ||
| 201 | #define INT_730_uWireRX (18 + IH2_BASE) | ||
| 202 | #define INT_730_SMC_CD (19 + IH2_BASE) | ||
| 203 | #define INT_730_SMC_IREQ (20 + IH2_BASE) | ||
| 204 | #define INT_730_HDQ_1WIRE (21 + IH2_BASE) | ||
| 205 | #define INT_730_TIMER32K (22 + IH2_BASE) | ||
| 206 | #define INT_730_MMC_SDIO (23 + IH2_BASE) | ||
| 207 | #define INT_730_UPLD (24 + IH2_BASE) | ||
| 208 | #define INT_730_USB_HHC_1 (27 + IH2_BASE) | ||
| 209 | #define INT_730_USB_HHC_2 (28 + IH2_BASE) | ||
| 210 | #define INT_730_USB_GENI (29 + IH2_BASE) | ||
| 211 | #define INT_730_USB_OTG (30 + IH2_BASE) | ||
| 212 | #define INT_730_CAMERA_IF (31 + IH2_BASE) | ||
| 213 | #define INT_730_RNG (32 + IH2_BASE) | ||
| 214 | #define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE) | ||
| 215 | #define INT_730_DBB_RF_EN (34 + IH2_BASE) | ||
| 216 | #define INT_730_MPUIO_KEYPAD (35 + IH2_BASE) | ||
| 217 | #define INT_730_SHA1_MD5 (36 + IH2_BASE) | ||
| 218 | #define INT_730_SPI_100K_2 (37 + IH2_BASE) | ||
| 219 | #define INT_730_RNG_IDLE (38 + IH2_BASE) | ||
| 220 | #define INT_730_MPUIO (39 + IH2_BASE) | ||
| 221 | #define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) | ||
| 222 | #define INT_730_LLPC_OE_FALLING (41 + IH2_BASE) | ||
| 223 | #define INT_730_LLPC_OE_RISING (42 + IH2_BASE) | ||
| 224 | #define INT_730_LLPC_VSYNC (43 + IH2_BASE) | ||
| 225 | #define INT_730_WAKE_UP_REQ (46 + IH2_BASE) | ||
| 226 | #define INT_730_DMA_CH6 (53 + IH2_BASE) | ||
| 227 | #define INT_730_DMA_CH7 (54 + IH2_BASE) | ||
| 228 | #define INT_730_DMA_CH8 (55 + IH2_BASE) | ||
| 229 | #define INT_730_DMA_CH9 (56 + IH2_BASE) | ||
| 230 | #define INT_730_DMA_CH10 (57 + IH2_BASE) | ||
| 231 | #define INT_730_DMA_CH11 (58 + IH2_BASE) | ||
| 232 | #define INT_730_DMA_CH12 (59 + IH2_BASE) | ||
| 233 | #define INT_730_DMA_CH13 (60 + IH2_BASE) | ||
| 234 | #define INT_730_DMA_CH14 (61 + IH2_BASE) | ||
| 235 | #define INT_730_DMA_CH15 (62 + IH2_BASE) | ||
| 236 | #define INT_730_NAND (63 + IH2_BASE) | ||
| 237 | |||
| 238 | #define INT_24XX_SYS_NIRQ 7 | ||
| 239 | #define INT_24XX_SDMA_IRQ0 12 | ||
| 240 | #define INT_24XX_SDMA_IRQ1 13 | ||
| 241 | #define INT_24XX_SDMA_IRQ2 14 | ||
| 242 | #define INT_24XX_SDMA_IRQ3 15 | ||
| 243 | #define INT_24XX_CAM_IRQ 24 | ||
| 244 | #define INT_24XX_DSS_IRQ 25 | ||
| 245 | #define INT_24XX_MAIL_U0_MPU 26 | ||
| 246 | #define INT_24XX_DSP_UMA 27 | ||
| 247 | #define INT_24XX_DSP_MMU 28 | ||
| 248 | #define INT_24XX_GPIO_BANK1 29 | ||
| 249 | #define INT_24XX_GPIO_BANK2 30 | ||
| 250 | #define INT_24XX_GPIO_BANK3 31 | ||
| 251 | #define INT_24XX_GPIO_BANK4 32 | ||
| 252 | #define INT_24XX_GPIO_BANK5 33 | ||
| 253 | #define INT_24XX_MAIL_U3_MPU 34 | ||
| 254 | #define INT_24XX_GPTIMER1 37 | ||
| 255 | #define INT_24XX_GPTIMER2 38 | ||
| 256 | #define INT_24XX_GPTIMER3 39 | ||
| 257 | #define INT_24XX_GPTIMER4 40 | ||
| 258 | #define INT_24XX_GPTIMER5 41 | ||
| 259 | #define INT_24XX_GPTIMER6 42 | ||
| 260 | #define INT_24XX_GPTIMER7 43 | ||
| 261 | #define INT_24XX_GPTIMER8 44 | ||
| 262 | #define INT_24XX_GPTIMER9 45 | ||
| 263 | #define INT_24XX_GPTIMER10 46 | ||
| 264 | #define INT_24XX_GPTIMER11 47 | ||
| 265 | #define INT_24XX_GPTIMER12 48 | ||
| 266 | #define INT_24XX_I2C1_IRQ 56 | ||
| 267 | #define INT_24XX_I2C2_IRQ 57 | ||
| 268 | #define INT_24XX_MCBSP1_IRQ_TX 59 | ||
| 269 | #define INT_24XX_MCBSP1_IRQ_RX 60 | ||
| 270 | #define INT_24XX_MCBSP2_IRQ_TX 62 | ||
| 271 | #define INT_24XX_MCBSP2_IRQ_RX 63 | ||
| 272 | #define INT_24XX_UART1_IRQ 72 | ||
| 273 | #define INT_24XX_UART2_IRQ 73 | ||
| 274 | #define INT_24XX_UART3_IRQ 74 | ||
| 275 | #define INT_24XX_USB_IRQ_GEN 75 | ||
| 276 | #define INT_24XX_USB_IRQ_NISO 76 | ||
| 277 | #define INT_24XX_USB_IRQ_ISO 77 | ||
| 278 | #define INT_24XX_USB_IRQ_HGEN 78 | ||
| 279 | #define INT_24XX_USB_IRQ_HSOF 79 | ||
| 280 | #define INT_24XX_USB_IRQ_OTG 80 | ||
| 281 | #define INT_24XX_MMC_IRQ 83 | ||
| 282 | |||
| 283 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and | ||
| 284 | * 16 MPUIO lines */ | ||
| 285 | #define OMAP_MAX_GPIO_LINES 192 | ||
| 286 | #define IH_GPIO_BASE (128 + IH2_BASE) | ||
| 287 | #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) | ||
| 288 | #define OMAP_IRQ_END (IH_MPUIO_BASE + 16) | ||
| 289 | |||
| 290 | /* External FPGA handles interrupts on Innovator boards */ | ||
| 291 | #define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) | ||
| 292 | #ifdef CONFIG_MACH_OMAP_INNOVATOR | ||
| 293 | #define OMAP_FPGA_NR_IRQS 24 | ||
| 294 | #else | ||
| 295 | #define OMAP_FPGA_NR_IRQS 0 | ||
| 296 | #endif | ||
| 297 | #define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) | ||
| 298 | |||
| 299 | /* External TWL4030 can handle interrupts on 2430 and 34xx boards */ | ||
| 300 | #define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END) | ||
| 301 | #ifdef CONFIG_TWL4030_CORE | ||
| 302 | #define TWL4030_BASE_NR_IRQS 8 | ||
| 303 | #define TWL4030_PWR_NR_IRQS 8 | ||
| 304 | #else | ||
| 305 | #define TWL4030_BASE_NR_IRQS 0 | ||
| 306 | #define TWL4030_PWR_NR_IRQS 0 | ||
| 307 | #endif | ||
| 308 | #define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS) | ||
| 309 | #define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END | ||
| 310 | #define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS) | ||
| 311 | |||
| 312 | /* External TWL4030 gpio interrupts are optional */ | ||
| 313 | #define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END | ||
| 314 | #ifdef CONFIG_TWL4030_GPIO | ||
| 315 | #define TWL4030_GPIO_NR_IRQS 18 | ||
| 316 | #else | ||
| 317 | #define TWL4030_GPIO_NR_IRQS 0 | ||
| 318 | #endif | ||
| 319 | #define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS) | ||
| 320 | |||
| 321 | /* Total number of interrupts depends on the enabled blocks above */ | ||
| 322 | #define NR_IRQS TWL4030_GPIO_IRQ_END | ||
| 323 | |||
| 324 | #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) | ||
| 325 | |||
| 326 | #ifndef __ASSEMBLY__ | ||
| 327 | extern void omap_init_irq(void); | ||
| 328 | #endif | ||
| 329 | |||
| 330 | #include <asm/arch/hardware.h> | ||
| 331 | |||
| 332 | #endif | ||
diff --git a/include/asm-arm/arch-omap/keypad.h b/include/asm-arm/arch-omap/keypad.h deleted file mode 100644 index b7f83075436e..000000000000 --- a/include/asm-arm/arch-omap/keypad.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/keypad.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #ifndef ASMARM_ARCH_KEYPAD_H | ||
| 11 | #define ASMARM_ARCH_KEYPAD_H | ||
| 12 | |||
| 13 | struct omap_kp_platform_data { | ||
| 14 | int rows; | ||
| 15 | int cols; | ||
| 16 | int *keymap; | ||
| 17 | unsigned int keymapsize; | ||
| 18 | unsigned int rep:1; | ||
| 19 | unsigned long delay; | ||
| 20 | unsigned int dbounce:1; | ||
| 21 | /* specific to OMAP242x*/ | ||
| 22 | unsigned int *row_gpios; | ||
| 23 | unsigned int *col_gpios; | ||
| 24 | }; | ||
| 25 | |||
| 26 | /* Group (0..3) -- when multiple keys are pressed, only the | ||
| 27 | * keys pressed in the same group are considered as pressed. This is | ||
| 28 | * in order to workaround certain crappy HW designs that produce ghost | ||
| 29 | * keypresses. */ | ||
| 30 | #define GROUP_0 (0 << 16) | ||
| 31 | #define GROUP_1 (1 << 16) | ||
| 32 | #define GROUP_2 (2 << 16) | ||
| 33 | #define GROUP_3 (3 << 16) | ||
| 34 | #define GROUP_MASK GROUP_3 | ||
| 35 | |||
| 36 | #define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val)) | ||
| 37 | |||
| 38 | #endif | ||
| 39 | |||
diff --git a/include/asm-arm/arch-omap/lcd_mipid.h b/include/asm-arm/arch-omap/lcd_mipid.h deleted file mode 100644 index f8fbc4801e52..000000000000 --- a/include/asm-arm/arch-omap/lcd_mipid.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | #ifndef __LCD_MIPID_H | ||
| 2 | #define __LCD_MIPID_H | ||
| 3 | |||
| 4 | enum mipid_test_num { | ||
| 5 | MIPID_TEST_RGB_LINES, | ||
| 6 | }; | ||
| 7 | |||
| 8 | enum mipid_test_result { | ||
| 9 | MIPID_TEST_SUCCESS, | ||
| 10 | MIPID_TEST_INVALID, | ||
| 11 | MIPID_TEST_FAILED, | ||
| 12 | }; | ||
| 13 | |||
| 14 | #ifdef __KERNEL__ | ||
| 15 | |||
| 16 | struct mipid_platform_data { | ||
| 17 | int nreset_gpio; | ||
| 18 | int data_lines; | ||
| 19 | void (*shutdown)(struct mipid_platform_data *pdata); | ||
| 20 | }; | ||
| 21 | |||
| 22 | #endif | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/include/asm-arm/arch-omap/led.h b/include/asm-arm/arch-omap/led.h deleted file mode 100644 index f3acae28e2da..000000000000 --- a/include/asm-arm/arch-omap/led.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/led.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Samsung Electronics | ||
| 5 | * Kyungmin Park <kyungmin.park@samsung.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef ASMARM_ARCH_LED_H | ||
| 12 | #define ASMARM_ARCH_LED_H | ||
| 13 | |||
| 14 | struct omap_led_config { | ||
| 15 | struct led_classdev cdev; | ||
| 16 | s16 gpio; | ||
| 17 | }; | ||
| 18 | |||
| 19 | struct omap_led_platform_data { | ||
| 20 | s16 nr_leds; | ||
| 21 | struct omap_led_config *leds; | ||
| 22 | }; | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/include/asm-arm/arch-omap/mailbox.h b/include/asm-arm/arch-omap/mailbox.h deleted file mode 100644 index 7cbed9332e16..000000000000 --- a/include/asm-arm/arch-omap/mailbox.h +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | /* mailbox.h */ | ||
| 2 | |||
| 3 | #ifndef MAILBOX_H | ||
| 4 | #define MAILBOX_H | ||
| 5 | |||
| 6 | #include <linux/wait.h> | ||
| 7 | #include <linux/workqueue.h> | ||
| 8 | #include <linux/blkdev.h> | ||
| 9 | |||
| 10 | typedef u32 mbox_msg_t; | ||
| 11 | typedef void (mbox_receiver_t)(mbox_msg_t msg); | ||
| 12 | struct omap_mbox; | ||
| 13 | |||
| 14 | typedef int __bitwise omap_mbox_irq_t; | ||
| 15 | #define IRQ_TX ((__force omap_mbox_irq_t) 1) | ||
| 16 | #define IRQ_RX ((__force omap_mbox_irq_t) 2) | ||
| 17 | |||
| 18 | typedef int __bitwise omap_mbox_type_t; | ||
| 19 | #define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1) | ||
| 20 | #define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2) | ||
| 21 | |||
| 22 | struct omap_mbox_ops { | ||
| 23 | omap_mbox_type_t type; | ||
| 24 | int (*startup)(struct omap_mbox *mbox); | ||
| 25 | void (*shutdown)(struct omap_mbox *mbox); | ||
| 26 | /* fifo */ | ||
| 27 | mbox_msg_t (*fifo_read)(struct omap_mbox *mbox); | ||
| 28 | void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg); | ||
| 29 | int (*fifo_empty)(struct omap_mbox *mbox); | ||
| 30 | int (*fifo_full)(struct omap_mbox *mbox); | ||
| 31 | /* irq */ | ||
| 32 | void (*enable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); | ||
| 33 | void (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); | ||
| 34 | void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); | ||
| 35 | int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct omap_mbox_queue { | ||
| 39 | spinlock_t lock; | ||
| 40 | struct request_queue *queue; | ||
| 41 | struct work_struct work; | ||
| 42 | int (*callback)(void *); | ||
| 43 | struct omap_mbox *mbox; | ||
| 44 | }; | ||
| 45 | |||
| 46 | struct omap_mbox { | ||
| 47 | char *name; | ||
| 48 | unsigned int irq; | ||
| 49 | |||
| 50 | struct omap_mbox_queue *txq, *rxq; | ||
| 51 | |||
| 52 | struct omap_mbox_ops *ops; | ||
| 53 | |||
| 54 | mbox_msg_t seq_snd, seq_rcv; | ||
| 55 | |||
| 56 | struct device dev; | ||
| 57 | |||
| 58 | struct omap_mbox *next; | ||
| 59 | void *priv; | ||
| 60 | |||
| 61 | void (*err_notify)(void); | ||
| 62 | }; | ||
| 63 | |||
| 64 | int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *); | ||
| 65 | void omap_mbox_init_seq(struct omap_mbox *); | ||
| 66 | |||
| 67 | struct omap_mbox *omap_mbox_get(const char *); | ||
| 68 | void omap_mbox_put(struct omap_mbox *); | ||
| 69 | |||
| 70 | int omap_mbox_register(struct omap_mbox *); | ||
| 71 | int omap_mbox_unregister(struct omap_mbox *); | ||
| 72 | |||
| 73 | #endif /* MAILBOX_H */ | ||
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h deleted file mode 100644 index 3da459a282b9..000000000000 --- a/include/asm-arm/arch-omap/mcbsp.h +++ /dev/null | |||
| @@ -1,380 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/mcbsp.h | ||
| 3 | * | ||
| 4 | * Defines for Multi-Channel Buffered Serial Port | ||
| 5 | * | ||
| 6 | * Copyright (C) 2002 RidgeRun, Inc. | ||
| 7 | * Author: Steve Johnson | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 22 | * | ||
| 23 | */ | ||
| 24 | #ifndef __ASM_ARCH_OMAP_MCBSP_H | ||
| 25 | #define __ASM_ARCH_OMAP_MCBSP_H | ||
| 26 | |||
| 27 | #include <linux/completion.h> | ||
| 28 | #include <linux/spinlock.h> | ||
| 29 | |||
| 30 | #include <asm/arch/hardware.h> | ||
| 31 | #include <asm/arch/clock.h> | ||
| 32 | |||
| 33 | #define OMAP730_MCBSP1_BASE 0xfffb1000 | ||
| 34 | #define OMAP730_MCBSP2_BASE 0xfffb1800 | ||
| 35 | |||
| 36 | #define OMAP1510_MCBSP1_BASE 0xe1011800 | ||
| 37 | #define OMAP1510_MCBSP2_BASE 0xfffb1000 | ||
| 38 | #define OMAP1510_MCBSP3_BASE 0xe1017000 | ||
| 39 | |||
| 40 | #define OMAP1610_MCBSP1_BASE 0xe1011800 | ||
| 41 | #define OMAP1610_MCBSP2_BASE 0xfffb1000 | ||
| 42 | #define OMAP1610_MCBSP3_BASE 0xe1017000 | ||
| 43 | |||
| 44 | #define OMAP24XX_MCBSP1_BASE 0x48074000 | ||
| 45 | #define OMAP24XX_MCBSP2_BASE 0x48076000 | ||
| 46 | |||
| 47 | #define OMAP34XX_MCBSP1_BASE 0x48074000 | ||
| 48 | #define OMAP34XX_MCBSP2_BASE 0x49022000 | ||
| 49 | |||
| 50 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) | ||
| 51 | |||
| 52 | #define OMAP_MCBSP_REG_DRR2 0x00 | ||
| 53 | #define OMAP_MCBSP_REG_DRR1 0x02 | ||
| 54 | #define OMAP_MCBSP_REG_DXR2 0x04 | ||
| 55 | #define OMAP_MCBSP_REG_DXR1 0x06 | ||
| 56 | #define OMAP_MCBSP_REG_SPCR2 0x08 | ||
| 57 | #define OMAP_MCBSP_REG_SPCR1 0x0a | ||
| 58 | #define OMAP_MCBSP_REG_RCR2 0x0c | ||
| 59 | #define OMAP_MCBSP_REG_RCR1 0x0e | ||
| 60 | #define OMAP_MCBSP_REG_XCR2 0x10 | ||
| 61 | #define OMAP_MCBSP_REG_XCR1 0x12 | ||
| 62 | #define OMAP_MCBSP_REG_SRGR2 0x14 | ||
| 63 | #define OMAP_MCBSP_REG_SRGR1 0x16 | ||
| 64 | #define OMAP_MCBSP_REG_MCR2 0x18 | ||
| 65 | #define OMAP_MCBSP_REG_MCR1 0x1a | ||
| 66 | #define OMAP_MCBSP_REG_RCERA 0x1c | ||
| 67 | #define OMAP_MCBSP_REG_RCERB 0x1e | ||
| 68 | #define OMAP_MCBSP_REG_XCERA 0x20 | ||
| 69 | #define OMAP_MCBSP_REG_XCERB 0x22 | ||
| 70 | #define OMAP_MCBSP_REG_PCR0 0x24 | ||
| 71 | #define OMAP_MCBSP_REG_RCERC 0x26 | ||
| 72 | #define OMAP_MCBSP_REG_RCERD 0x28 | ||
| 73 | #define OMAP_MCBSP_REG_XCERC 0x2A | ||
| 74 | #define OMAP_MCBSP_REG_XCERD 0x2C | ||
| 75 | #define OMAP_MCBSP_REG_RCERE 0x2E | ||
| 76 | #define OMAP_MCBSP_REG_RCERF 0x30 | ||
| 77 | #define OMAP_MCBSP_REG_XCERE 0x32 | ||
| 78 | #define OMAP_MCBSP_REG_XCERF 0x34 | ||
| 79 | #define OMAP_MCBSP_REG_RCERG 0x36 | ||
| 80 | #define OMAP_MCBSP_REG_RCERH 0x38 | ||
| 81 | #define OMAP_MCBSP_REG_XCERG 0x3A | ||
| 82 | #define OMAP_MCBSP_REG_XCERH 0x3C | ||
| 83 | |||
| 84 | #define OMAP_MAX_MCBSP_COUNT 3 | ||
| 85 | #define MAX_MCBSP_CLOCKS 3 | ||
| 86 | |||
| 87 | #define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) | ||
| 88 | #define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) | ||
| 89 | |||
| 90 | #define AUDIO_MCBSP OMAP_MCBSP1 | ||
| 91 | #define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX | ||
| 92 | #define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX | ||
| 93 | |||
| 94 | #elif defined(CONFIG_ARCH_OMAP24XX) | ||
| 95 | |||
| 96 | #define OMAP_MCBSP_REG_DRR2 0x00 | ||
| 97 | #define OMAP_MCBSP_REG_DRR1 0x04 | ||
| 98 | #define OMAP_MCBSP_REG_DXR2 0x08 | ||
| 99 | #define OMAP_MCBSP_REG_DXR1 0x0C | ||
| 100 | #define OMAP_MCBSP_REG_SPCR2 0x10 | ||
| 101 | #define OMAP_MCBSP_REG_SPCR1 0x14 | ||
| 102 | #define OMAP_MCBSP_REG_RCR2 0x18 | ||
| 103 | #define OMAP_MCBSP_REG_RCR1 0x1C | ||
| 104 | #define OMAP_MCBSP_REG_XCR2 0x20 | ||
| 105 | #define OMAP_MCBSP_REG_XCR1 0x24 | ||
| 106 | #define OMAP_MCBSP_REG_SRGR2 0x28 | ||
| 107 | #define OMAP_MCBSP_REG_SRGR1 0x2C | ||
| 108 | #define OMAP_MCBSP_REG_MCR2 0x30 | ||
| 109 | #define OMAP_MCBSP_REG_MCR1 0x34 | ||
| 110 | #define OMAP_MCBSP_REG_RCERA 0x38 | ||
| 111 | #define OMAP_MCBSP_REG_RCERB 0x3C | ||
| 112 | #define OMAP_MCBSP_REG_XCERA 0x40 | ||
| 113 | #define OMAP_MCBSP_REG_XCERB 0x44 | ||
| 114 | #define OMAP_MCBSP_REG_PCR0 0x48 | ||
| 115 | #define OMAP_MCBSP_REG_RCERC 0x4C | ||
| 116 | #define OMAP_MCBSP_REG_RCERD 0x50 | ||
| 117 | #define OMAP_MCBSP_REG_XCERC 0x54 | ||
| 118 | #define OMAP_MCBSP_REG_XCERD 0x58 | ||
| 119 | #define OMAP_MCBSP_REG_RCERE 0x5C | ||
| 120 | #define OMAP_MCBSP_REG_RCERF 0x60 | ||
| 121 | #define OMAP_MCBSP_REG_XCERE 0x64 | ||
| 122 | #define OMAP_MCBSP_REG_XCERF 0x68 | ||
| 123 | #define OMAP_MCBSP_REG_RCERG 0x6C | ||
| 124 | #define OMAP_MCBSP_REG_RCERH 0x70 | ||
| 125 | #define OMAP_MCBSP_REG_XCERG 0x74 | ||
| 126 | #define OMAP_MCBSP_REG_XCERH 0x78 | ||
| 127 | |||
| 128 | #define OMAP_MAX_MCBSP_COUNT 2 | ||
| 129 | #define MAX_MCBSP_CLOCKS 2 | ||
| 130 | |||
| 131 | #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) | ||
| 132 | #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) | ||
| 133 | |||
| 134 | #define AUDIO_MCBSP OMAP_MCBSP2 | ||
| 135 | #define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX | ||
| 136 | #define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX | ||
| 137 | |||
| 138 | #endif | ||
| 139 | |||
| 140 | #define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg) | ||
| 141 | #define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg) | ||
| 142 | |||
| 143 | |||
| 144 | /************************** McBSP SPCR1 bit definitions ***********************/ | ||
| 145 | #define RRST 0x0001 | ||
| 146 | #define RRDY 0x0002 | ||
| 147 | #define RFULL 0x0004 | ||
| 148 | #define RSYNC_ERR 0x0008 | ||
| 149 | #define RINTM(value) ((value)<<4) /* bits 4:5 */ | ||
| 150 | #define ABIS 0x0040 | ||
| 151 | #define DXENA 0x0080 | ||
| 152 | #define CLKSTP(value) ((value)<<11) /* bits 11:12 */ | ||
| 153 | #define RJUST(value) ((value)<<13) /* bits 13:14 */ | ||
| 154 | #define DLB 0x8000 | ||
| 155 | |||
| 156 | /************************** McBSP SPCR2 bit definitions ***********************/ | ||
| 157 | #define XRST 0x0001 | ||
| 158 | #define XRDY 0x0002 | ||
| 159 | #define XEMPTY 0x0004 | ||
| 160 | #define XSYNC_ERR 0x0008 | ||
| 161 | #define XINTM(value) ((value)<<4) /* bits 4:5 */ | ||
| 162 | #define GRST 0x0040 | ||
| 163 | #define FRST 0x0080 | ||
| 164 | #define SOFT 0x0100 | ||
| 165 | #define FREE 0x0200 | ||
| 166 | |||
| 167 | /************************** McBSP PCR bit definitions *************************/ | ||
| 168 | #define CLKRP 0x0001 | ||
| 169 | #define CLKXP 0x0002 | ||
| 170 | #define FSRP 0x0004 | ||
| 171 | #define FSXP 0x0008 | ||
| 172 | #define DR_STAT 0x0010 | ||
| 173 | #define DX_STAT 0x0020 | ||
| 174 | #define CLKS_STAT 0x0040 | ||
| 175 | #define SCLKME 0x0080 | ||
| 176 | #define CLKRM 0x0100 | ||
| 177 | #define CLKXM 0x0200 | ||
| 178 | #define FSRM 0x0400 | ||
| 179 | #define FSXM 0x0800 | ||
| 180 | #define RIOEN 0x1000 | ||
| 181 | #define XIOEN 0x2000 | ||
| 182 | #define IDLE_EN 0x4000 | ||
| 183 | |||
| 184 | /************************** McBSP RCR1 bit definitions ************************/ | ||
| 185 | #define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */ | ||
| 186 | #define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */ | ||
| 187 | |||
| 188 | /************************** McBSP XCR1 bit definitions ************************/ | ||
| 189 | #define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */ | ||
| 190 | #define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */ | ||
| 191 | |||
| 192 | /*************************** McBSP RCR2 bit definitions ***********************/ | ||
| 193 | #define RDATDLY(value) (value) /* Bits 0:1 */ | ||
| 194 | #define RFIG 0x0004 | ||
| 195 | #define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */ | ||
| 196 | #define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */ | ||
| 197 | #define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */ | ||
| 198 | #define RPHASE 0x8000 | ||
| 199 | |||
| 200 | /*************************** McBSP XCR2 bit definitions ***********************/ | ||
| 201 | #define XDATDLY(value) (value) /* Bits 0:1 */ | ||
| 202 | #define XFIG 0x0004 | ||
| 203 | #define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */ | ||
| 204 | #define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */ | ||
| 205 | #define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */ | ||
| 206 | #define XPHASE 0x8000 | ||
| 207 | |||
| 208 | /************************* McBSP SRGR1 bit definitions ************************/ | ||
| 209 | #define CLKGDV(value) (value) /* Bits 0:7 */ | ||
| 210 | #define FWID(value) ((value)<<8) /* Bits 8:15 */ | ||
| 211 | |||
| 212 | /************************* McBSP SRGR2 bit definitions ************************/ | ||
| 213 | #define FPER(value) (value) /* Bits 0:11 */ | ||
| 214 | #define FSGM 0x1000 | ||
| 215 | #define CLKSM 0x2000 | ||
| 216 | #define CLKSP 0x4000 | ||
| 217 | #define GSYNC 0x8000 | ||
| 218 | |||
| 219 | /************************* McBSP MCR1 bit definitions *************************/ | ||
| 220 | #define RMCM 0x0001 | ||
| 221 | #define RCBLK(value) ((value)<<2) /* Bits 2:4 */ | ||
| 222 | #define RPABLK(value) ((value)<<5) /* Bits 5:6 */ | ||
| 223 | #define RPBBLK(value) ((value)<<7) /* Bits 7:8 */ | ||
| 224 | |||
| 225 | /************************* McBSP MCR2 bit definitions *************************/ | ||
| 226 | #define XMCM(value) (value) /* Bits 0:1 */ | ||
| 227 | #define XCBLK(value) ((value)<<2) /* Bits 2:4 */ | ||
| 228 | #define XPABLK(value) ((value)<<5) /* Bits 5:6 */ | ||
| 229 | #define XPBBLK(value) ((value)<<7) /* Bits 7:8 */ | ||
| 230 | |||
| 231 | |||
| 232 | /* we don't do multichannel for now */ | ||
| 233 | struct omap_mcbsp_reg_cfg { | ||
| 234 | u16 spcr2; | ||
| 235 | u16 spcr1; | ||
| 236 | u16 rcr2; | ||
| 237 | u16 rcr1; | ||
| 238 | u16 xcr2; | ||
| 239 | u16 xcr1; | ||
| 240 | u16 srgr2; | ||
| 241 | u16 srgr1; | ||
| 242 | u16 mcr2; | ||
| 243 | u16 mcr1; | ||
| 244 | u16 pcr0; | ||
| 245 | u16 rcerc; | ||
| 246 | u16 rcerd; | ||
| 247 | u16 xcerc; | ||
| 248 | u16 xcerd; | ||
| 249 | u16 rcere; | ||
| 250 | u16 rcerf; | ||
| 251 | u16 xcere; | ||
| 252 | u16 xcerf; | ||
| 253 | u16 rcerg; | ||
| 254 | u16 rcerh; | ||
| 255 | u16 xcerg; | ||
| 256 | u16 xcerh; | ||
| 257 | }; | ||
| 258 | |||
| 259 | typedef enum { | ||
| 260 | OMAP_MCBSP1 = 0, | ||
| 261 | OMAP_MCBSP2, | ||
| 262 | OMAP_MCBSP3, | ||
| 263 | } omap_mcbsp_id; | ||
| 264 | |||
| 265 | typedef int __bitwise omap_mcbsp_io_type_t; | ||
| 266 | #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1) | ||
| 267 | #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2) | ||
| 268 | |||
| 269 | typedef enum { | ||
| 270 | OMAP_MCBSP_WORD_8 = 0, | ||
| 271 | OMAP_MCBSP_WORD_12, | ||
| 272 | OMAP_MCBSP_WORD_16, | ||
| 273 | OMAP_MCBSP_WORD_20, | ||
| 274 | OMAP_MCBSP_WORD_24, | ||
| 275 | OMAP_MCBSP_WORD_32, | ||
| 276 | } omap_mcbsp_word_length; | ||
| 277 | |||
| 278 | typedef enum { | ||
| 279 | OMAP_MCBSP_CLK_RISING = 0, | ||
| 280 | OMAP_MCBSP_CLK_FALLING, | ||
| 281 | } omap_mcbsp_clk_polarity; | ||
| 282 | |||
| 283 | typedef enum { | ||
| 284 | OMAP_MCBSP_FS_ACTIVE_HIGH = 0, | ||
| 285 | OMAP_MCBSP_FS_ACTIVE_LOW, | ||
| 286 | } omap_mcbsp_fs_polarity; | ||
| 287 | |||
| 288 | typedef enum { | ||
| 289 | OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0, | ||
| 290 | OMAP_MCBSP_CLK_STP_MODE_DELAY, | ||
| 291 | } omap_mcbsp_clk_stp_mode; | ||
| 292 | |||
| 293 | |||
| 294 | /******* SPI specific mode **********/ | ||
| 295 | typedef enum { | ||
| 296 | OMAP_MCBSP_SPI_MASTER = 0, | ||
| 297 | OMAP_MCBSP_SPI_SLAVE, | ||
| 298 | } omap_mcbsp_spi_mode; | ||
| 299 | |||
| 300 | struct omap_mcbsp_spi_cfg { | ||
| 301 | omap_mcbsp_spi_mode spi_mode; | ||
| 302 | omap_mcbsp_clk_polarity rx_clock_polarity; | ||
| 303 | omap_mcbsp_clk_polarity tx_clock_polarity; | ||
| 304 | omap_mcbsp_fs_polarity fsx_polarity; | ||
| 305 | u8 clk_div; | ||
| 306 | omap_mcbsp_clk_stp_mode clk_stp_mode; | ||
| 307 | omap_mcbsp_word_length word_length; | ||
| 308 | }; | ||
| 309 | |||
| 310 | /* Platform specific configuration */ | ||
| 311 | struct omap_mcbsp_ops { | ||
| 312 | void (*request)(unsigned int); | ||
| 313 | void (*free)(unsigned int); | ||
| 314 | int (*check)(unsigned int); | ||
| 315 | }; | ||
| 316 | |||
| 317 | struct omap_mcbsp_platform_data { | ||
| 318 | u32 virt_base; | ||
| 319 | u8 dma_rx_sync, dma_tx_sync; | ||
| 320 | u16 rx_irq, tx_irq; | ||
| 321 | struct omap_mcbsp_ops *ops; | ||
| 322 | char const *clk_name; | ||
| 323 | }; | ||
| 324 | |||
| 325 | struct omap_mcbsp { | ||
| 326 | struct device *dev; | ||
| 327 | u32 io_base; | ||
| 328 | u8 id; | ||
| 329 | u8 free; | ||
| 330 | omap_mcbsp_word_length rx_word_length; | ||
| 331 | omap_mcbsp_word_length tx_word_length; | ||
| 332 | |||
| 333 | omap_mcbsp_io_type_t io_type; /* IRQ or poll */ | ||
| 334 | /* IRQ based TX/RX */ | ||
| 335 | int rx_irq; | ||
| 336 | int tx_irq; | ||
| 337 | |||
| 338 | /* DMA stuff */ | ||
| 339 | u8 dma_rx_sync; | ||
| 340 | short dma_rx_lch; | ||
| 341 | u8 dma_tx_sync; | ||
| 342 | short dma_tx_lch; | ||
| 343 | |||
| 344 | /* Completion queues */ | ||
| 345 | struct completion tx_irq_completion; | ||
| 346 | struct completion rx_irq_completion; | ||
| 347 | struct completion tx_dma_completion; | ||
| 348 | struct completion rx_dma_completion; | ||
| 349 | |||
| 350 | /* Protect the field .free, while checking if the mcbsp is in use */ | ||
| 351 | spinlock_t lock; | ||
| 352 | struct omap_mcbsp_platform_data *pdata; | ||
| 353 | struct clk *clk; | ||
| 354 | }; | ||
| 355 | |||
| 356 | int omap_mcbsp_init(void); | ||
| 357 | void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, | ||
| 358 | int size); | ||
| 359 | void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); | ||
| 360 | int omap_mcbsp_request(unsigned int id); | ||
| 361 | void omap_mcbsp_free(unsigned int id); | ||
| 362 | void omap_mcbsp_start(unsigned int id); | ||
| 363 | void omap_mcbsp_stop(unsigned int id); | ||
| 364 | void omap_mcbsp_xmit_word(unsigned int id, u32 word); | ||
| 365 | u32 omap_mcbsp_recv_word(unsigned int id); | ||
| 366 | |||
| 367 | int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); | ||
| 368 | int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); | ||
| 369 | int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word); | ||
| 370 | int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); | ||
| 371 | |||
| 372 | |||
| 373 | /* SPI specific API */ | ||
| 374 | void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); | ||
| 375 | |||
| 376 | /* Polled read/write functions */ | ||
| 377 | int omap_mcbsp_pollread(unsigned int id, u16 * buf); | ||
| 378 | int omap_mcbsp_pollwrite(unsigned int id, u16 buf); | ||
| 379 | |||
| 380 | #endif | ||
diff --git a/include/asm-arm/arch-omap/mcspi.h b/include/asm-arm/arch-omap/mcspi.h deleted file mode 100644 index 1254e4945b6f..000000000000 --- a/include/asm-arm/arch-omap/mcspi.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | #ifndef _OMAP2_MCSPI_H | ||
| 2 | #define _OMAP2_MCSPI_H | ||
| 3 | |||
| 4 | struct omap2_mcspi_platform_config { | ||
| 5 | unsigned short num_cs; | ||
| 6 | }; | ||
| 7 | |||
| 8 | struct omap2_mcspi_device_config { | ||
| 9 | unsigned turbo_mode:1; | ||
| 10 | |||
| 11 | /* Do we want one channel enabled at the same time? */ | ||
| 12 | unsigned single_channel:1; | ||
| 13 | }; | ||
| 14 | |||
| 15 | #endif | ||
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h deleted file mode 100644 index 14cba97c18ad..000000000000 --- a/include/asm-arm/arch-omap/memory.h +++ /dev/null | |||
| @@ -1,103 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/memory.h | ||
| 3 | * | ||
| 4 | * Memory map for OMAP-1510 and 1610 | ||
| 5 | * | ||
| 6 | * Copyright (C) 2000 RidgeRun, Inc. | ||
| 7 | * Author: Greg Lonnon <glonnon@ridgerun.com> | ||
| 8 | * | ||
| 9 | * This file was derived from linux/include/asm-arm/arch-intergrator/memory.h | ||
| 10 | * Copyright (C) 1999 ARM Limited | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify it | ||
| 13 | * under the terms of the GNU General Public License as published by the | ||
| 14 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 15 | * option) any later version. | ||
| 16 | * | ||
| 17 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 20 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 23 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 24 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 27 | * | ||
| 28 | * You should have received a copy of the GNU General Public License along | ||
| 29 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 30 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 31 | */ | ||
| 32 | |||
| 33 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 34 | #define __ASM_ARCH_MEMORY_H | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Physical DRAM offset. | ||
| 38 | */ | ||
| 39 | #if defined(CONFIG_ARCH_OMAP1) | ||
| 40 | #define PHYS_OFFSET UL(0x10000000) | ||
| 41 | #elif defined(CONFIG_ARCH_OMAP2) | ||
| 42 | #define PHYS_OFFSET UL(0x80000000) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Conversion between SDRAM and fake PCI bus, used by USB | ||
| 47 | * NOTE: Physical address must be converted to Local Bus address | ||
| 48 | * on OMAP-1510 only | ||
| 49 | */ | ||
| 50 | |||
| 51 | /* | ||
| 52 | * Bus address is physical address, except for OMAP-1510 Local Bus. | ||
| 53 | */ | ||
| 54 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 55 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 56 | |||
| 57 | /* | ||
| 58 | * OMAP-1510 bus address is translated into a Local Bus address if the | ||
| 59 | * OMAP bus type is lbus. We do the address translation based on the | ||
| 60 | * device overriding the defaults used in the dma-mapping API. | ||
| 61 | * Note that the is_lbus_device() test is not very efficient on 1510 | ||
| 62 | * because of the strncmp(). | ||
| 63 | */ | ||
| 64 | #ifdef CONFIG_ARCH_OMAP15XX | ||
| 65 | |||
| 66 | /* | ||
| 67 | * OMAP-1510 Local Bus address offset | ||
| 68 | */ | ||
| 69 | #define OMAP1510_LB_OFFSET UL(0x30000000) | ||
| 70 | |||
| 71 | #define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET) | ||
| 72 | #define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET) | ||
| 73 | #define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev->bus_id, "ohci", 4) == 0)) | ||
| 74 | |||
| 75 | #define __arch_page_to_dma(dev, page) ({is_lbus_device(dev) ? \ | ||
| 76 | (dma_addr_t)virt_to_lbus(page_address(page)) : \ | ||
| 77 | (dma_addr_t)__virt_to_bus(page_address(page));}) | ||
| 78 | |||
| 79 | #define __arch_dma_to_virt(dev, addr) ({is_lbus_device(dev) ? \ | ||
| 80 | lbus_to_virt(addr) : \ | ||
| 81 | __bus_to_virt(addr);}) | ||
| 82 | |||
| 83 | #define __arch_virt_to_dma(dev, addr) ({is_lbus_device(dev) ? \ | ||
| 84 | virt_to_lbus(addr) : \ | ||
| 85 | __virt_to_bus(addr);}) | ||
| 86 | |||
| 87 | #endif /* CONFIG_ARCH_OMAP15XX */ | ||
| 88 | |||
| 89 | /* Override the ARM default */ | ||
| 90 | #ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE | ||
| 91 | |||
| 92 | #if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0) | ||
| 93 | #undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE | ||
| 94 | #define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2 | ||
| 95 | #endif | ||
| 96 | |||
| 97 | #define CONSISTENT_DMA_SIZE \ | ||
| 98 | (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024) | ||
| 99 | |||
| 100 | #endif | ||
| 101 | |||
| 102 | #endif | ||
| 103 | |||
diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h deleted file mode 100644 index 69ed7ee40179..000000000000 --- a/include/asm-arm/arch-omap/menelaus.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/menelaus.h | ||
| 3 | * | ||
| 4 | * Functions to access Menelaus power management chip | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __ASM_ARCH_MENELAUS_H | ||
| 8 | #define __ASM_ARCH_MENELAUS_H | ||
| 9 | |||
| 10 | struct device; | ||
| 11 | |||
| 12 | struct menelaus_platform_data { | ||
| 13 | int (* late_init)(struct device *dev); | ||
| 14 | }; | ||
| 15 | |||
| 16 | extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask), | ||
| 17 | void *data); | ||
| 18 | extern void menelaus_unregister_mmc_callback(void); | ||
| 19 | extern int menelaus_set_mmc_opendrain(int slot, int enable); | ||
| 20 | extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on); | ||
| 21 | |||
| 22 | extern int menelaus_set_vmem(unsigned int mV); | ||
| 23 | extern int menelaus_set_vio(unsigned int mV); | ||
| 24 | extern int menelaus_set_vmmc(unsigned int mV); | ||
| 25 | extern int menelaus_set_vaux(unsigned int mV); | ||
| 26 | extern int menelaus_set_vdcdc(int dcdc, unsigned int mV); | ||
| 27 | extern int menelaus_set_slot_sel(int enable); | ||
| 28 | extern int menelaus_get_slot_pin_states(void); | ||
| 29 | extern int menelaus_set_vcore_sw(unsigned int mV); | ||
| 30 | extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV); | ||
| 31 | |||
| 32 | #define EN_VPLL_SLEEP (1 << 7) | ||
| 33 | #define EN_VMMC_SLEEP (1 << 6) | ||
| 34 | #define EN_VAUX_SLEEP (1 << 5) | ||
| 35 | #define EN_VIO_SLEEP (1 << 4) | ||
| 36 | #define EN_VMEM_SLEEP (1 << 3) | ||
| 37 | #define EN_DC3_SLEEP (1 << 2) | ||
| 38 | #define EN_DC2_SLEEP (1 << 1) | ||
| 39 | #define EN_VC_SLEEP (1 << 0) | ||
| 40 | |||
| 41 | extern int menelaus_set_regulator_sleep(int enable, u32 val); | ||
| 42 | |||
| 43 | #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS) | ||
| 44 | #define omap_has_menelaus() 1 | ||
| 45 | #else | ||
| 46 | #define omap_has_menelaus() 0 | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-omap/mmc.h b/include/asm-arm/arch-omap/mmc.h deleted file mode 100644 index 7cfc5f258560..000000000000 --- a/include/asm-arm/arch-omap/mmc.h +++ /dev/null | |||
| @@ -1,74 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * MMC definitions for OMAP2 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Nokia Corporation | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __OMAP2_MMC_H | ||
| 12 | #define __OMAP2_MMC_H | ||
| 13 | |||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/device.h> | ||
| 16 | #include <linux/mmc/host.h> | ||
| 17 | |||
| 18 | #include <asm/arch/board.h> | ||
| 19 | |||
| 20 | #define OMAP_MMC_MAX_SLOTS 2 | ||
| 21 | |||
| 22 | struct omap_mmc_platform_data { | ||
| 23 | struct omap_mmc_conf conf; | ||
| 24 | |||
| 25 | /* number of slots on board */ | ||
| 26 | unsigned nr_slots:2; | ||
| 27 | |||
| 28 | /* set if your board has components or wiring that limits the | ||
| 29 | * maximum frequency on the MMC bus */ | ||
| 30 | unsigned int max_freq; | ||
| 31 | |||
| 32 | /* switch the bus to a new slot */ | ||
| 33 | int (* switch_slot)(struct device *dev, int slot); | ||
| 34 | /* initialize board-specific MMC functionality, can be NULL if | ||
| 35 | * not supported */ | ||
| 36 | int (* init)(struct device *dev); | ||
| 37 | void (* cleanup)(struct device *dev); | ||
| 38 | void (* shutdown)(struct device *dev); | ||
| 39 | |||
| 40 | /* To handle board related suspend/resume functionality for MMC */ | ||
| 41 | int (*suspend)(struct device *dev, int slot); | ||
| 42 | int (*resume)(struct device *dev, int slot); | ||
| 43 | |||
| 44 | struct omap_mmc_slot_data { | ||
| 45 | int (* set_bus_mode)(struct device *dev, int slot, int bus_mode); | ||
| 46 | int (* set_power)(struct device *dev, int slot, int power_on, int vdd); | ||
| 47 | int (* get_ro)(struct device *dev, int slot); | ||
| 48 | |||
| 49 | /* return MMC cover switch state, can be NULL if not supported. | ||
| 50 | * | ||
| 51 | * possible return values: | ||
| 52 | * 0 - open | ||
| 53 | * 1 - closed | ||
| 54 | */ | ||
| 55 | int (* get_cover_state)(struct device *dev, int slot); | ||
| 56 | |||
| 57 | const char *name; | ||
| 58 | u32 ocr_mask; | ||
| 59 | |||
| 60 | /* Card detection IRQs */ | ||
| 61 | int card_detect_irq; | ||
| 62 | int (* card_detect)(int irq); | ||
| 63 | |||
| 64 | unsigned int ban_openended:1; | ||
| 65 | |||
| 66 | } slots[OMAP_MMC_MAX_SLOTS]; | ||
| 67 | }; | ||
| 68 | |||
| 69 | extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info); | ||
| 70 | |||
| 71 | /* called from board-specific card detection service routine */ | ||
| 72 | extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed); | ||
| 73 | |||
| 74 | #endif | ||
diff --git a/include/asm-arm/arch-omap/mtd-xip.h b/include/asm-arm/arch-omap/mtd-xip.h deleted file mode 100644 index f4714b5270d0..000000000000 --- a/include/asm-arm/arch-omap/mtd-xip.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * MTD primitives for XIP support. Architecture specific functions. | ||
| 3 | * | ||
| 4 | * Do not include this file directly. It's included from linux/mtd/xip.h | ||
| 5 | * | ||
| 6 | * Author: Vladimir Barinov <vbarinov@ru.mvista.com> | ||
| 7 | * | ||
| 8 | * (c) 2005 MontaVista Software, Inc. This file is licensed under the | ||
| 9 | * terms of the GNU General Public License version 2. This program is | ||
| 10 | * licensed "as is" without any warranty of any kind, whether express or | ||
| 11 | * implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ARCH_OMAP_MTD_XIP_H__ | ||
| 15 | #define __ARCH_OMAP_MTD_XIP_H__ | ||
| 16 | |||
| 17 | #include <asm/arch/hardware.h> | ||
| 18 | #define OMAP_MPU_TIMER_BASE (0xfffec500) | ||
| 19 | #define OMAP_MPU_TIMER_OFFSET 0x100 | ||
| 20 | |||
| 21 | typedef struct { | ||
| 22 | u32 cntl; /* CNTL_TIMER, R/W */ | ||
| 23 | u32 load_tim; /* LOAD_TIM, W */ | ||
| 24 | u32 read_tim; /* READ_TIM, R */ | ||
| 25 | } xip_omap_mpu_timer_regs_t; | ||
| 26 | |||
| 27 | #define xip_omap_mpu_timer_base(n) \ | ||
| 28 | ((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ | ||
| 29 | (n)*OMAP_MPU_TIMER_OFFSET)) | ||
| 30 | |||
| 31 | static inline unsigned long xip_omap_mpu_timer_read(int nr) | ||
| 32 | { | ||
| 33 | volatile xip_omap_mpu_timer_regs_t* timer = xip_omap_mpu_timer_base(nr); | ||
| 34 | return timer->read_tim; | ||
| 35 | } | ||
| 36 | |||
| 37 | #define xip_irqpending() \ | ||
| 38 | (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR)) | ||
| 39 | #define xip_currtime() (~xip_omap_mpu_timer_read(0)) | ||
| 40 | |||
| 41 | /* | ||
| 42 | * It's permitted to do approxmation for xip_elapsed_since macro | ||
| 43 | * (see linux/mtd/xip.h) | ||
| 44 | */ | ||
| 45 | |||
| 46 | #ifdef CONFIG_MACH_OMAP_PERSEUS2 | ||
| 47 | #define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7) | ||
| 48 | #else | ||
| 49 | #define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6) | ||
| 50 | #endif | ||
| 51 | |||
| 52 | /* | ||
| 53 | * xip_cpu_idle() is used when waiting for a delay equal or larger than | ||
| 54 | * the system timer tick period. This should put the CPU into idle mode | ||
| 55 | * to save power and to be woken up only when some interrupts are pending. | ||
| 56 | * As above, this should not rely upon standard kernel code. | ||
| 57 | */ | ||
| 58 | |||
| 59 | #define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1)) | ||
| 60 | |||
| 61 | #endif /* __ARCH_OMAP_MTD_XIP_H__ */ | ||
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h deleted file mode 100644 index ff9a5b5575fd..000000000000 --- a/include/asm-arm/arch-omap/mux.h +++ /dev/null | |||
| @@ -1,615 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/mux.h | ||
| 3 | * | ||
| 4 | * Table of the Omap register configurations for the FUNC_MUX and | ||
| 5 | * PULL_DWN combinations. | ||
| 6 | * | ||
| 7 | * Copyright (C) 2004 - 2008 Texas Instruments Inc. | ||
| 8 | * Copyright (C) 2003 - 2008 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Tony Lindgren | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License as published by | ||
| 14 | * the Free Software Foundation; either version 2 of the License, or | ||
| 15 | * (at your option) any later version. | ||
| 16 | * | ||
| 17 | * This program is distributed in the hope that it will be useful, | ||
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 20 | * GNU General Public License for more details. | ||
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License | ||
| 23 | * along with this program; if not, write to the Free Software | ||
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 25 | * | ||
| 26 | * NOTE: Please use the following naming style for new pin entries. | ||
| 27 | * For example, W8_1610_MMC2_DAT0, where: | ||
| 28 | * - W8 = ball | ||
| 29 | * - 1610 = 1510 or 1610, none if common for both 1510 and 1610 | ||
| 30 | * - MMC2_DAT0 = function | ||
| 31 | */ | ||
| 32 | |||
| 33 | #ifndef __ASM_ARCH_MUX_H | ||
| 34 | #define __ASM_ARCH_MUX_H | ||
| 35 | |||
| 36 | #define PU_PD_SEL_NA 0 /* No pu_pd reg available */ | ||
| 37 | #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */ | ||
| 38 | |||
| 39 | #ifdef CONFIG_OMAP_MUX_DEBUG | ||
| 40 | #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ | ||
| 41 | .mux_reg = FUNC_MUX_CTRL_##reg, \ | ||
| 42 | .mask_offset = mode_offset, \ | ||
| 43 | .mask = mode, | ||
| 44 | |||
| 45 | #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ | ||
| 46 | .pull_reg = PULL_DWN_CTRL_##reg, \ | ||
| 47 | .pull_bit = bit, \ | ||
| 48 | .pull_val = status, | ||
| 49 | |||
| 50 | #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ | ||
| 51 | .pu_pd_reg = PU_PD_SEL_##reg, \ | ||
| 52 | .pu_pd_val = status, | ||
| 53 | |||
| 54 | #define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \ | ||
| 55 | .mux_reg = OMAP730_IO_CONF_##reg, \ | ||
| 56 | .mask_offset = mode_offset, \ | ||
| 57 | .mask = mode, | ||
| 58 | |||
| 59 | #define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \ | ||
| 60 | .pull_reg = OMAP730_IO_CONF_##reg, \ | ||
| 61 | .pull_bit = bit, \ | ||
| 62 | .pull_val = status, | ||
| 63 | |||
| 64 | #else | ||
| 65 | |||
| 66 | #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ | ||
| 67 | .mask_offset = mode_offset, \ | ||
| 68 | .mask = mode, | ||
| 69 | |||
| 70 | #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \ | ||
| 71 | .pull_bit = bit, \ | ||
| 72 | .pull_val = status, | ||
| 73 | |||
| 74 | #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ | ||
| 75 | .pu_pd_val = status, | ||
| 76 | |||
| 77 | #define MUX_REG_730(reg, mode_offset, mode) \ | ||
| 78 | .mux_reg = OMAP730_IO_CONF_##reg, \ | ||
| 79 | .mask_offset = mode_offset, \ | ||
| 80 | .mask = mode, | ||
| 81 | |||
| 82 | #define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \ | ||
| 83 | .pull_bit = bit, \ | ||
| 84 | .pull_val = status, | ||
| 85 | |||
| 86 | #endif /* CONFIG_OMAP_MUX_DEBUG */ | ||
| 87 | |||
| 88 | #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ | ||
| 89 | pull_reg, pull_bit, pull_status, \ | ||
| 90 | pu_pd_reg, pu_pd_status, debug_status) \ | ||
| 91 | { \ | ||
| 92 | .name = desc, \ | ||
| 93 | .debug = debug_status, \ | ||
| 94 | MUX_REG(mux_reg, mode_offset, mode) \ | ||
| 95 | PULL_REG(pull_reg, pull_bit, pull_status) \ | ||
| 96 | PU_PD_REG(pu_pd_reg, pu_pd_status) \ | ||
| 97 | }, | ||
| 98 | |||
| 99 | |||
| 100 | /* | ||
| 101 | * OMAP730 has a slightly different config for the pin mux. | ||
| 102 | * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and | ||
| 103 | * not the FUNC_MUX_CTRL_x regs from hardware.h | ||
| 104 | * - for pull-up/down, only has one enable bit which is is in the same register | ||
| 105 | * as mux config | ||
| 106 | */ | ||
| 107 | #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ | ||
| 108 | pull_bit, pull_status, debug_status)\ | ||
| 109 | { \ | ||
| 110 | .name = desc, \ | ||
| 111 | .debug = debug_status, \ | ||
| 112 | MUX_REG_730(mux_reg, mode_offset, mode) \ | ||
| 113 | PULL_REG_730(mux_reg, pull_bit, pull_status) \ | ||
| 114 | PU_PD_REG(NA, 0) \ | ||
| 115 | }, | ||
| 116 | |||
| 117 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ | ||
| 118 | pull_en, pull_mode, dbg) \ | ||
| 119 | { \ | ||
| 120 | .name = desc, \ | ||
| 121 | .debug = dbg, \ | ||
| 122 | .mux_reg = reg_offset, \ | ||
| 123 | .mask = mode, \ | ||
| 124 | .pull_val = pull_en, \ | ||
| 125 | .pu_pd_val = pull_mode, \ | ||
| 126 | }, | ||
| 127 | |||
| 128 | |||
| 129 | #define PULL_DISABLED 0 | ||
| 130 | #define PULL_ENABLED 1 | ||
| 131 | |||
| 132 | #define PULL_DOWN 0 | ||
| 133 | #define PULL_UP 1 | ||
| 134 | |||
| 135 | struct pin_config { | ||
| 136 | char *name; | ||
| 137 | unsigned char busy; | ||
| 138 | unsigned char debug; | ||
| 139 | |||
| 140 | const char *mux_reg_name; | ||
| 141 | const unsigned int mux_reg; | ||
| 142 | const unsigned char mask_offset; | ||
| 143 | const unsigned char mask; | ||
| 144 | |||
| 145 | const char *pull_name; | ||
| 146 | const unsigned int pull_reg; | ||
| 147 | const unsigned char pull_val; | ||
| 148 | const unsigned char pull_bit; | ||
| 149 | |||
| 150 | const char *pu_pd_name; | ||
| 151 | const unsigned int pu_pd_reg; | ||
| 152 | const unsigned char pu_pd_val; | ||
| 153 | }; | ||
| 154 | |||
| 155 | enum omap730_index { | ||
| 156 | /* OMAP 730 keyboard */ | ||
| 157 | E2_730_KBR0, | ||
| 158 | J7_730_KBR1, | ||
| 159 | E1_730_KBR2, | ||
| 160 | F3_730_KBR3, | ||
| 161 | D2_730_KBR4, | ||
| 162 | C2_730_KBC0, | ||
| 163 | D3_730_KBC1, | ||
| 164 | E4_730_KBC2, | ||
| 165 | F4_730_KBC3, | ||
| 166 | E3_730_KBC4, | ||
| 167 | |||
| 168 | /* USB */ | ||
| 169 | AA17_730_USB_DM, | ||
| 170 | W16_730_USB_PU_EN, | ||
| 171 | W17_730_USB_VBUSI, | ||
| 172 | }; | ||
| 173 | |||
| 174 | enum omap1xxx_index { | ||
| 175 | /* UART1 (BT_UART_GATING)*/ | ||
| 176 | UART1_TX = 0, | ||
| 177 | UART1_RTS, | ||
| 178 | |||
| 179 | /* UART2 (COM_UART_GATING)*/ | ||
| 180 | UART2_TX, | ||
| 181 | UART2_RX, | ||
| 182 | UART2_CTS, | ||
| 183 | UART2_RTS, | ||
| 184 | |||
| 185 | /* UART3 (GIGA_UART_GATING) */ | ||
| 186 | UART3_TX, | ||
| 187 | UART3_RX, | ||
| 188 | UART3_CTS, | ||
| 189 | UART3_RTS, | ||
| 190 | UART3_CLKREQ, | ||
| 191 | UART3_BCLK, /* 12MHz clock out */ | ||
| 192 | Y15_1610_UART3_RTS, | ||
| 193 | |||
| 194 | /* PWT & PWL */ | ||
| 195 | PWT, | ||
| 196 | PWL, | ||
| 197 | |||
| 198 | /* USB master generic */ | ||
| 199 | R18_USB_VBUS, | ||
| 200 | R18_1510_USB_GPIO0, | ||
| 201 | W4_USB_PUEN, | ||
| 202 | W4_USB_CLKO, | ||
| 203 | W4_USB_HIGHZ, | ||
| 204 | W4_GPIO58, | ||
| 205 | |||
| 206 | /* USB1 master */ | ||
| 207 | USB1_SUSP, | ||
| 208 | USB1_SEO, | ||
| 209 | W13_1610_USB1_SE0, | ||
| 210 | USB1_TXEN, | ||
| 211 | USB1_TXD, | ||
| 212 | USB1_VP, | ||
| 213 | USB1_VM, | ||
| 214 | USB1_RCV, | ||
| 215 | USB1_SPEED, | ||
| 216 | R13_1610_USB1_SPEED, | ||
| 217 | R13_1710_USB1_SE0, | ||
| 218 | |||
| 219 | /* USB2 master */ | ||
| 220 | USB2_SUSP, | ||
| 221 | USB2_VP, | ||
| 222 | USB2_TXEN, | ||
| 223 | USB2_VM, | ||
| 224 | USB2_RCV, | ||
| 225 | USB2_SEO, | ||
| 226 | USB2_TXD, | ||
| 227 | |||
| 228 | /* OMAP-1510 GPIO */ | ||
| 229 | R18_1510_GPIO0, | ||
| 230 | R19_1510_GPIO1, | ||
| 231 | M14_1510_GPIO2, | ||
| 232 | |||
| 233 | /* OMAP1610 GPIO */ | ||
| 234 | P18_1610_GPIO3, | ||
| 235 | Y15_1610_GPIO17, | ||
| 236 | |||
| 237 | /* OMAP-1710 GPIO */ | ||
| 238 | R18_1710_GPIO0, | ||
| 239 | V2_1710_GPIO10, | ||
| 240 | N21_1710_GPIO14, | ||
| 241 | W15_1710_GPIO40, | ||
| 242 | |||
| 243 | /* MPUIO */ | ||
| 244 | MPUIO2, | ||
| 245 | N15_1610_MPUIO2, | ||
| 246 | MPUIO4, | ||
| 247 | MPUIO5, | ||
| 248 | T20_1610_MPUIO5, | ||
| 249 | W11_1610_MPUIO6, | ||
| 250 | V10_1610_MPUIO7, | ||
| 251 | W11_1610_MPUIO9, | ||
| 252 | V10_1610_MPUIO10, | ||
| 253 | W10_1610_MPUIO11, | ||
| 254 | E20_1610_MPUIO13, | ||
| 255 | U20_1610_MPUIO14, | ||
| 256 | E19_1610_MPUIO15, | ||
| 257 | |||
| 258 | /* MCBSP2 */ | ||
| 259 | MCBSP2_CLKR, | ||
| 260 | MCBSP2_CLKX, | ||
| 261 | MCBSP2_DR, | ||
| 262 | MCBSP2_DX, | ||
| 263 | MCBSP2_FSR, | ||
| 264 | MCBSP2_FSX, | ||
| 265 | |||
| 266 | /* MCBSP3 */ | ||
| 267 | MCBSP3_CLKX, | ||
| 268 | |||
| 269 | /* Misc ballouts */ | ||
| 270 | BALLOUT_V8_ARMIO3, | ||
| 271 | N20_HDQ, | ||
| 272 | |||
| 273 | /* OMAP-1610 MMC2 */ | ||
| 274 | W8_1610_MMC2_DAT0, | ||
| 275 | V8_1610_MMC2_DAT1, | ||
| 276 | W15_1610_MMC2_DAT2, | ||
| 277 | R10_1610_MMC2_DAT3, | ||
| 278 | Y10_1610_MMC2_CLK, | ||
| 279 | Y8_1610_MMC2_CMD, | ||
| 280 | V9_1610_MMC2_CMDDIR, | ||
| 281 | V5_1610_MMC2_DATDIR0, | ||
| 282 | W19_1610_MMC2_DATDIR1, | ||
| 283 | R18_1610_MMC2_CLKIN, | ||
| 284 | |||
| 285 | /* OMAP-1610 External Trace Interface */ | ||
| 286 | M19_1610_ETM_PSTAT0, | ||
| 287 | L15_1610_ETM_PSTAT1, | ||
| 288 | L18_1610_ETM_PSTAT2, | ||
| 289 | L19_1610_ETM_D0, | ||
| 290 | J19_1610_ETM_D6, | ||
| 291 | J18_1610_ETM_D7, | ||
| 292 | |||
| 293 | /* OMAP16XX GPIO */ | ||
| 294 | P20_1610_GPIO4, | ||
| 295 | V9_1610_GPIO7, | ||
| 296 | W8_1610_GPIO9, | ||
| 297 | N20_1610_GPIO11, | ||
| 298 | N19_1610_GPIO13, | ||
| 299 | P10_1610_GPIO22, | ||
| 300 | V5_1610_GPIO24, | ||
| 301 | AA20_1610_GPIO_41, | ||
| 302 | W19_1610_GPIO48, | ||
| 303 | M7_1610_GPIO62, | ||
| 304 | V14_16XX_GPIO37, | ||
| 305 | R9_16XX_GPIO18, | ||
| 306 | L14_16XX_GPIO49, | ||
| 307 | |||
| 308 | /* OMAP-1610 uWire */ | ||
| 309 | V19_1610_UWIRE_SCLK, | ||
| 310 | U18_1610_UWIRE_SDI, | ||
| 311 | W21_1610_UWIRE_SDO, | ||
| 312 | N14_1610_UWIRE_CS0, | ||
| 313 | P15_1610_UWIRE_CS3, | ||
| 314 | N15_1610_UWIRE_CS1, | ||
| 315 | |||
| 316 | /* OMAP-1610 SPI */ | ||
| 317 | U19_1610_SPIF_SCK, | ||
| 318 | U18_1610_SPIF_DIN, | ||
| 319 | P20_1610_SPIF_DIN, | ||
| 320 | W21_1610_SPIF_DOUT, | ||
| 321 | R18_1610_SPIF_DOUT, | ||
| 322 | N14_1610_SPIF_CS0, | ||
| 323 | N15_1610_SPIF_CS1, | ||
| 324 | T19_1610_SPIF_CS2, | ||
| 325 | P15_1610_SPIF_CS3, | ||
| 326 | |||
| 327 | /* OMAP-1610 Flash */ | ||
| 328 | L3_1610_FLASH_CS2B_OE, | ||
| 329 | M8_1610_FLASH_CS2B_WE, | ||
| 330 | |||
| 331 | /* First MMC */ | ||
| 332 | MMC_CMD, | ||
| 333 | MMC_DAT1, | ||
| 334 | MMC_DAT2, | ||
| 335 | MMC_DAT0, | ||
| 336 | MMC_CLK, | ||
| 337 | MMC_DAT3, | ||
| 338 | |||
| 339 | /* OMAP-1710 MMC CMDDIR and DATDIR0 */ | ||
| 340 | M15_1710_MMC_CLKI, | ||
| 341 | P19_1710_MMC_CMDDIR, | ||
| 342 | P20_1710_MMC_DATDIR0, | ||
| 343 | |||
| 344 | /* OMAP-1610 USB0 alternate pin configuration */ | ||
| 345 | W9_USB0_TXEN, | ||
| 346 | AA9_USB0_VP, | ||
| 347 | Y5_USB0_RCV, | ||
| 348 | R9_USB0_VM, | ||
| 349 | V6_USB0_TXD, | ||
| 350 | W5_USB0_SE0, | ||
| 351 | V9_USB0_SPEED, | ||
| 352 | V9_USB0_SUSP, | ||
| 353 | |||
| 354 | /* USB2 */ | ||
| 355 | W9_USB2_TXEN, | ||
| 356 | AA9_USB2_VP, | ||
| 357 | Y5_USB2_RCV, | ||
| 358 | R9_USB2_VM, | ||
| 359 | V6_USB2_TXD, | ||
| 360 | W5_USB2_SE0, | ||
| 361 | |||
| 362 | /* 16XX UART */ | ||
| 363 | R13_1610_UART1_TX, | ||
| 364 | V14_16XX_UART1_RX, | ||
| 365 | R14_1610_UART1_CTS, | ||
| 366 | AA15_1610_UART1_RTS, | ||
| 367 | R9_16XX_UART2_RX, | ||
| 368 | L14_16XX_UART3_RX, | ||
| 369 | |||
| 370 | /* I2C OMAP-1610 */ | ||
| 371 | I2C_SCL, | ||
| 372 | I2C_SDA, | ||
| 373 | |||
| 374 | /* Keypad */ | ||
| 375 | F18_1610_KBC0, | ||
| 376 | D20_1610_KBC1, | ||
| 377 | D19_1610_KBC2, | ||
| 378 | E18_1610_KBC3, | ||
| 379 | C21_1610_KBC4, | ||
| 380 | G18_1610_KBR0, | ||
| 381 | F19_1610_KBR1, | ||
| 382 | H14_1610_KBR2, | ||
| 383 | E20_1610_KBR3, | ||
| 384 | E19_1610_KBR4, | ||
| 385 | N19_1610_KBR5, | ||
| 386 | |||
| 387 | /* Power management */ | ||
| 388 | T20_1610_LOW_PWR, | ||
| 389 | |||
| 390 | /* MCLK Settings */ | ||
| 391 | V5_1710_MCLK_ON, | ||
| 392 | V5_1710_MCLK_OFF, | ||
| 393 | R10_1610_MCLK_ON, | ||
| 394 | R10_1610_MCLK_OFF, | ||
| 395 | |||
| 396 | /* CompactFlash controller */ | ||
| 397 | P11_1610_CF_CD2, | ||
| 398 | R11_1610_CF_IOIS16, | ||
| 399 | V10_1610_CF_IREQ, | ||
| 400 | W10_1610_CF_RESET, | ||
| 401 | W11_1610_CF_CD1, | ||
| 402 | |||
| 403 | /* parallel camera */ | ||
| 404 | J15_1610_CAM_LCLK, | ||
| 405 | J18_1610_CAM_D7, | ||
| 406 | J19_1610_CAM_D6, | ||
| 407 | J14_1610_CAM_D5, | ||
| 408 | K18_1610_CAM_D4, | ||
| 409 | K19_1610_CAM_D3, | ||
| 410 | K15_1610_CAM_D2, | ||
| 411 | K14_1610_CAM_D1, | ||
| 412 | L19_1610_CAM_D0, | ||
| 413 | L18_1610_CAM_VS, | ||
| 414 | L15_1610_CAM_HS, | ||
| 415 | M19_1610_CAM_RSTZ, | ||
| 416 | Y15_1610_CAM_OUTCLK, | ||
| 417 | |||
| 418 | /* serial camera */ | ||
| 419 | H19_1610_CAM_EXCLK, | ||
| 420 | Y12_1610_CCP_CLKP, | ||
| 421 | W13_1610_CCP_CLKM, | ||
| 422 | W14_1610_CCP_DATAP, | ||
| 423 | Y14_1610_CCP_DATAM, | ||
| 424 | |||
| 425 | }; | ||
| 426 | |||
| 427 | enum omap24xx_index { | ||
| 428 | /* 24xx I2C */ | ||
| 429 | M19_24XX_I2C1_SCL, | ||
| 430 | L15_24XX_I2C1_SDA, | ||
| 431 | J15_24XX_I2C2_SCL, | ||
| 432 | H19_24XX_I2C2_SDA, | ||
| 433 | |||
| 434 | /* 24xx Menelaus interrupt */ | ||
| 435 | W19_24XX_SYS_NIRQ, | ||
| 436 | |||
| 437 | /* 24xx clock */ | ||
| 438 | W14_24XX_SYS_CLKOUT, | ||
| 439 | |||
| 440 | /* 24xx GPMC chipselects, wait pin monitoring */ | ||
| 441 | E2_GPMC_NCS2, | ||
| 442 | L2_GPMC_NCS7, | ||
| 443 | L3_GPMC_WAIT0, | ||
| 444 | N7_GPMC_WAIT1, | ||
| 445 | M1_GPMC_WAIT2, | ||
| 446 | P1_GPMC_WAIT3, | ||
| 447 | |||
| 448 | /* 242X McBSP */ | ||
| 449 | Y15_24XX_MCBSP2_CLKX, | ||
| 450 | R14_24XX_MCBSP2_FSX, | ||
| 451 | W15_24XX_MCBSP2_DR, | ||
| 452 | V15_24XX_MCBSP2_DX, | ||
| 453 | |||
| 454 | /* 24xx GPIO */ | ||
| 455 | M21_242X_GPIO11, | ||
| 456 | P21_242X_GPIO12, | ||
| 457 | AA10_242X_GPIO13, | ||
| 458 | AA6_242X_GPIO14, | ||
| 459 | AA4_242X_GPIO15, | ||
| 460 | Y11_242X_GPIO16, | ||
| 461 | AA12_242X_GPIO17, | ||
| 462 | AA8_242X_GPIO58, | ||
| 463 | Y20_24XX_GPIO60, | ||
| 464 | W4__24XX_GPIO74, | ||
| 465 | N15_24XX_GPIO85, | ||
| 466 | M15_24XX_GPIO92, | ||
| 467 | P20_24XX_GPIO93, | ||
| 468 | P18_24XX_GPIO95, | ||
| 469 | M18_24XX_GPIO96, | ||
| 470 | L14_24XX_GPIO97, | ||
| 471 | J15_24XX_GPIO99, | ||
| 472 | V14_24XX_GPIO117, | ||
| 473 | P14_24XX_GPIO125, | ||
| 474 | |||
| 475 | /* 242x DBG GPIO */ | ||
| 476 | V4_242X_GPIO49, | ||
| 477 | W2_242X_GPIO50, | ||
| 478 | U4_242X_GPIO51, | ||
| 479 | V3_242X_GPIO52, | ||
| 480 | V2_242X_GPIO53, | ||
| 481 | V6_242X_GPIO53, | ||
| 482 | T4_242X_GPIO54, | ||
| 483 | Y4_242X_GPIO54, | ||
| 484 | T3_242X_GPIO55, | ||
| 485 | U2_242X_GPIO56, | ||
| 486 | |||
| 487 | /* 24xx external DMA requests */ | ||
| 488 | AA10_242X_DMAREQ0, | ||
| 489 | AA6_242X_DMAREQ1, | ||
| 490 | E4_242X_DMAREQ2, | ||
| 491 | G4_242X_DMAREQ3, | ||
| 492 | D3_242X_DMAREQ4, | ||
| 493 | E3_242X_DMAREQ5, | ||
| 494 | |||
| 495 | /* UART3 */ | ||
| 496 | K15_24XX_UART3_TX, | ||
| 497 | K14_24XX_UART3_RX, | ||
| 498 | |||
| 499 | /* MMC/SDIO */ | ||
| 500 | G19_24XX_MMC_CLKO, | ||
| 501 | H18_24XX_MMC_CMD, | ||
| 502 | F20_24XX_MMC_DAT0, | ||
| 503 | H14_24XX_MMC_DAT1, | ||
| 504 | E19_24XX_MMC_DAT2, | ||
| 505 | D19_24XX_MMC_DAT3, | ||
| 506 | F19_24XX_MMC_DAT_DIR0, | ||
| 507 | E20_24XX_MMC_DAT_DIR1, | ||
| 508 | F18_24XX_MMC_DAT_DIR2, | ||
| 509 | E18_24XX_MMC_DAT_DIR3, | ||
| 510 | G18_24XX_MMC_CMD_DIR, | ||
| 511 | H15_24XX_MMC_CLKI, | ||
| 512 | |||
| 513 | /* Full speed USB */ | ||
| 514 | J20_24XX_USB0_PUEN, | ||
| 515 | J19_24XX_USB0_VP, | ||
| 516 | K20_24XX_USB0_VM, | ||
| 517 | J18_24XX_USB0_RCV, | ||
| 518 | K19_24XX_USB0_TXEN, | ||
| 519 | J14_24XX_USB0_SE0, | ||
| 520 | K18_24XX_USB0_DAT, | ||
| 521 | |||
| 522 | N14_24XX_USB1_SE0, | ||
| 523 | W12_24XX_USB1_SE0, | ||
| 524 | P15_24XX_USB1_DAT, | ||
| 525 | R13_24XX_USB1_DAT, | ||
| 526 | W20_24XX_USB1_TXEN, | ||
| 527 | P13_24XX_USB1_TXEN, | ||
| 528 | V19_24XX_USB1_RCV, | ||
| 529 | V12_24XX_USB1_RCV, | ||
| 530 | |||
| 531 | AA10_24XX_USB2_SE0, | ||
| 532 | Y11_24XX_USB2_DAT, | ||
| 533 | AA12_24XX_USB2_TXEN, | ||
| 534 | AA6_24XX_USB2_RCV, | ||
| 535 | AA4_24XX_USB2_TLLSE0, | ||
| 536 | |||
| 537 | /* Keypad GPIO*/ | ||
| 538 | T19_24XX_KBR0, | ||
| 539 | R19_24XX_KBR1, | ||
| 540 | V18_24XX_KBR2, | ||
| 541 | M21_24XX_KBR3, | ||
| 542 | E5__24XX_KBR4, | ||
| 543 | M18_24XX_KBR5, | ||
| 544 | R20_24XX_KBC0, | ||
| 545 | M14_24XX_KBC1, | ||
| 546 | H19_24XX_KBC2, | ||
| 547 | V17_24XX_KBC3, | ||
| 548 | P21_24XX_KBC4, | ||
| 549 | L14_24XX_KBC5, | ||
| 550 | N19_24XX_KBC6, | ||
| 551 | |||
| 552 | /* 24xx Menelaus Keypad GPIO */ | ||
| 553 | B3__24XX_KBR5, | ||
| 554 | AA4_24XX_KBC2, | ||
| 555 | B13_24XX_KBC6, | ||
| 556 | |||
| 557 | /* 2430 USB */ | ||
| 558 | AD9_2430_USB0_PUEN, | ||
| 559 | Y11_2430_USB0_VP, | ||
| 560 | AD7_2430_USB0_VM, | ||
| 561 | AE7_2430_USB0_RCV, | ||
| 562 | AD4_2430_USB0_TXEN, | ||
| 563 | AF9_2430_USB0_SE0, | ||
| 564 | AE6_2430_USB0_DAT, | ||
| 565 | AD24_2430_USB1_SE0, | ||
| 566 | AB24_2430_USB1_RCV, | ||
| 567 | Y25_2430_USB1_TXEN, | ||
| 568 | AA26_2430_USB1_DAT, | ||
| 569 | |||
| 570 | /* 2430 HS-USB */ | ||
| 571 | AD9_2430_USB0HS_DATA3, | ||
| 572 | Y11_2430_USB0HS_DATA4, | ||
| 573 | AD7_2430_USB0HS_DATA5, | ||
| 574 | AE7_2430_USB0HS_DATA6, | ||
| 575 | AD4_2430_USB0HS_DATA2, | ||
| 576 | AF9_2430_USB0HS_DATA0, | ||
| 577 | AE6_2430_USB0HS_DATA1, | ||
| 578 | AE8_2430_USB0HS_CLK, | ||
| 579 | AD8_2430_USB0HS_DIR, | ||
| 580 | AE5_2430_USB0HS_STP, | ||
| 581 | AE9_2430_USB0HS_NXT, | ||
| 582 | AC7_2430_USB0HS_DATA7, | ||
| 583 | |||
| 584 | /* 2430 McBSP */ | ||
| 585 | AC10_2430_MCBSP2_FSX, | ||
| 586 | AD16_2430_MCBSP2_CLX, | ||
| 587 | AE13_2430_MCBSP2_DX, | ||
| 588 | AD13_2430_MCBSP2_DR, | ||
| 589 | AC10_2430_MCBSP2_FSX_OFF, | ||
| 590 | AD16_2430_MCBSP2_CLX_OFF, | ||
| 591 | AE13_2430_MCBSP2_DX_OFF, | ||
| 592 | AD13_2430_MCBSP2_DR_OFF, | ||
| 593 | |||
| 594 | }; | ||
| 595 | |||
| 596 | struct omap_mux_cfg { | ||
| 597 | struct pin_config *pins; | ||
| 598 | unsigned long size; | ||
| 599 | int (*cfg_reg)(const struct pin_config *cfg); | ||
| 600 | }; | ||
| 601 | |||
| 602 | #ifdef CONFIG_OMAP_MUX | ||
| 603 | /* setup pin muxing in Linux */ | ||
| 604 | extern int omap1_mux_init(void); | ||
| 605 | extern int omap2_mux_init(void); | ||
| 606 | extern int omap_mux_register(struct omap_mux_cfg *); | ||
| 607 | extern int omap_cfg_reg(unsigned long reg_cfg); | ||
| 608 | #else | ||
| 609 | /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ | ||
| 610 | static inline int omap1_mux_init(void) { return 0; } | ||
| 611 | static inline int omap2_mux_init(void) { return 0; } | ||
| 612 | static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } | ||
| 613 | #endif | ||
| 614 | |||
| 615 | #endif | ||
diff --git a/include/asm-arm/arch-omap/nand.h b/include/asm-arm/arch-omap/nand.h deleted file mode 100644 index 17ae26e35353..000000000000 --- a/include/asm-arm/arch-omap/nand.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-omap/nand.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Micron Technology Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/mtd/partitions.h> | ||
| 12 | |||
| 13 | struct omap_nand_platform_data { | ||
| 14 | unsigned int options; | ||
| 15 | int cs; | ||
| 16 | int gpio_irq; | ||
| 17 | struct mtd_partition *parts; | ||
| 18 | int nr_parts; | ||
| 19 | int (*nand_setup)(void __iomem *); | ||
| 20 | int (*dev_ready)(struct omap_nand_platform_data *); | ||
| 21 | int dma_channel; | ||
| 22 | void __iomem *gpmc_cs_baseaddr; | ||
| 23 | void __iomem *gpmc_baseaddr; | ||
| 24 | }; | ||
diff --git a/include/asm-arm/arch-omap/omap-alsa.h b/include/asm-arm/arch-omap/omap-alsa.h deleted file mode 100644 index faa0ed23d4ba..000000000000 --- a/include/asm-arm/arch-omap/omap-alsa.h +++ /dev/null | |||
| @@ -1,123 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/omap-alsa.h | ||
| 3 | * | ||
| 4 | * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi> | ||
| 7 | * | ||
| 8 | * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil | ||
| 9 | * Written by Daniel Petrini, David Cohen, Anderson Briglia | ||
| 10 | * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify it | ||
| 13 | * under the terms of the GNU General Public License as published by the | ||
| 14 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 15 | * option) any later version. | ||
| 16 | * | ||
| 17 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 20 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 23 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 24 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 27 | * | ||
| 28 | * You should have received a copy of the GNU General Public License along | ||
| 29 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 30 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 31 | * | ||
| 32 | * History | ||
| 33 | * ------- | ||
| 34 | * | ||
| 35 | * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk, | ||
| 36 | * original version based in sa1100 driver | ||
| 37 | * and omap oss driver. | ||
| 38 | */ | ||
| 39 | |||
| 40 | #ifndef __OMAP_ALSA_H | ||
| 41 | #define __OMAP_ALSA_H | ||
| 42 | |||
| 43 | #include <asm/arch/dma.h> | ||
| 44 | #include <sound/core.h> | ||
| 45 | #include <sound/pcm.h> | ||
| 46 | #include <asm/arch/mcbsp.h> | ||
| 47 | #include <linux/platform_device.h> | ||
| 48 | |||
| 49 | #define DMA_BUF_SIZE (1024 * 8) | ||
| 50 | |||
| 51 | /* | ||
| 52 | * Buffer management for alsa and dma | ||
| 53 | */ | ||
| 54 | struct audio_stream { | ||
| 55 | char *id; /* identification string */ | ||
| 56 | int stream_id; /* numeric identification */ | ||
| 57 | int dma_dev; /* dma number of that device */ | ||
| 58 | int *lch; /* Chain of channels this stream is linked to */ | ||
| 59 | char started; /* to store if the chain was started or not */ | ||
| 60 | int dma_q_head; /* DMA Channel Q Head */ | ||
| 61 | int dma_q_tail; /* DMA Channel Q Tail */ | ||
| 62 | char dma_q_count; /* DMA Channel Q Count */ | ||
| 63 | int active:1; /* we are using this stream for transfer now */ | ||
| 64 | int period; /* current transfer period */ | ||
| 65 | int periods; /* current count of periods registerd in the DMA engine */ | ||
| 66 | spinlock_t dma_lock; /* for locking in DMA operations */ | ||
| 67 | struct snd_pcm_substream *stream; /* the pcm stream */ | ||
| 68 | unsigned linked:1; /* dma channels linked */ | ||
| 69 | int offset; /* store start position of the last period in the alsa buffer */ | ||
| 70 | int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */ | ||
| 71 | int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */ | ||
| 72 | }; | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Alsa card structure for aic23 | ||
| 76 | */ | ||
| 77 | struct snd_card_omap_codec { | ||
| 78 | struct snd_card *card; | ||
| 79 | struct snd_pcm *pcm; | ||
| 80 | long samplerate; | ||
| 81 | struct audio_stream s[2]; /* playback & capture */ | ||
| 82 | }; | ||
| 83 | |||
| 84 | /* Codec specific information and function pointers. | ||
| 85 | * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c) | ||
| 86 | * are responsible for defining the function pointers. | ||
| 87 | */ | ||
| 88 | struct omap_alsa_codec_config { | ||
| 89 | char *name; | ||
| 90 | struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa; | ||
| 91 | struct snd_pcm_hw_constraint_list *hw_constraints_rates; | ||
| 92 | struct snd_pcm_hardware *snd_omap_alsa_playback; | ||
| 93 | struct snd_pcm_hardware *snd_omap_alsa_capture; | ||
| 94 | void (*codec_configure_dev)(void); | ||
| 95 | void (*codec_set_samplerate)(long); | ||
| 96 | void (*codec_clock_setup)(void); | ||
| 97 | int (*codec_clock_on)(void); | ||
| 98 | int (*codec_clock_off)(void); | ||
| 99 | int (*get_default_samplerate)(void); | ||
| 100 | }; | ||
| 101 | |||
| 102 | /*********** Mixer function prototypes *************************/ | ||
| 103 | int snd_omap_mixer(struct snd_card_omap_codec *); | ||
| 104 | void snd_omap_init_mixer(void); | ||
| 105 | |||
| 106 | #ifdef CONFIG_PM | ||
| 107 | void snd_omap_suspend_mixer(void); | ||
| 108 | void snd_omap_resume_mixer(void); | ||
| 109 | #endif | ||
| 110 | |||
| 111 | int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config); | ||
| 112 | int snd_omap_alsa_remove(struct platform_device *pdev); | ||
| 113 | #ifdef CONFIG_PM | ||
| 114 | int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state); | ||
| 115 | int snd_omap_alsa_resume(struct platform_device *pdev); | ||
| 116 | #else | ||
| 117 | #define snd_omap_alsa_suspend NULL | ||
| 118 | #define snd_omap_alsa_resume NULL | ||
| 119 | #endif | ||
| 120 | |||
| 121 | void callback_omap_alsa_sound_dma(void *); | ||
| 122 | |||
| 123 | #endif | ||
diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h deleted file mode 100644 index c575d354850f..000000000000 --- a/include/asm-arm/arch-omap/omap1510.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-omap/omap1510.h | ||
| 2 | * | ||
| 3 | * Hardware definitions for TI OMAP1510 processor. | ||
| 4 | * | ||
| 5 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License along | ||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 26 | */ | ||
| 27 | |||
| 28 | #ifndef __ASM_ARCH_OMAP15XX_H | ||
| 29 | #define __ASM_ARCH_OMAP15XX_H | ||
| 30 | |||
| 31 | /* | ||
| 32 | * ---------------------------------------------------------------------------- | ||
| 33 | * Base addresses | ||
| 34 | * ---------------------------------------------------------------------------- | ||
| 35 | */ | ||
| 36 | |||
| 37 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ | ||
| 38 | |||
| 39 | #define OMAP1510_DSP_BASE 0xE0000000 | ||
| 40 | #define OMAP1510_DSP_SIZE 0x28000 | ||
| 41 | #define OMAP1510_DSP_START 0xE0000000 | ||
| 42 | |||
| 43 | #define OMAP1510_DSPREG_BASE 0xE1000000 | ||
| 44 | #define OMAP1510_DSPREG_SIZE SZ_128K | ||
| 45 | #define OMAP1510_DSPREG_START 0xE1000000 | ||
| 46 | |||
| 47 | #endif /* __ASM_ARCH_OMAP15XX_H */ | ||
| 48 | |||
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h deleted file mode 100644 index f7f5cdfdccce..000000000000 --- a/include/asm-arm/arch-omap/omap16xx.h +++ /dev/null | |||
| @@ -1,197 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-omap/omap16xx.h | ||
| 2 | * | ||
| 3 | * Hardware definitions for TI OMAP1610/5912/1710 processors. | ||
| 4 | * | ||
| 5 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License along | ||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 26 | */ | ||
| 27 | |||
| 28 | #ifndef __ASM_ARCH_OMAP16XX_H | ||
| 29 | #define __ASM_ARCH_OMAP16XX_H | ||
| 30 | |||
| 31 | /* | ||
| 32 | * ---------------------------------------------------------------------------- | ||
| 33 | * Base addresses | ||
| 34 | * ---------------------------------------------------------------------------- | ||
| 35 | */ | ||
| 36 | |||
| 37 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ | ||
| 38 | |||
| 39 | #define OMAP16XX_DSP_BASE 0xE0000000 | ||
| 40 | #define OMAP16XX_DSP_SIZE 0x28000 | ||
| 41 | #define OMAP16XX_DSP_START 0xE0000000 | ||
| 42 | |||
| 43 | #define OMAP16XX_DSPREG_BASE 0xE1000000 | ||
| 44 | #define OMAP16XX_DSPREG_SIZE SZ_128K | ||
| 45 | #define OMAP16XX_DSPREG_START 0xE1000000 | ||
| 46 | |||
| 47 | /* | ||
| 48 | * --------------------------------------------------------------------------- | ||
| 49 | * Interrupts | ||
| 50 | * --------------------------------------------------------------------------- | ||
| 51 | */ | ||
| 52 | #define OMAP_IH2_0_BASE (0xfffe0000) | ||
| 53 | #define OMAP_IH2_1_BASE (0xfffe0100) | ||
| 54 | #define OMAP_IH2_2_BASE (0xfffe0200) | ||
| 55 | #define OMAP_IH2_3_BASE (0xfffe0300) | ||
| 56 | |||
| 57 | #define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00) | ||
| 58 | #define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04) | ||
| 59 | #define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10) | ||
| 60 | #define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14) | ||
| 61 | #define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18) | ||
| 62 | #define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c) | ||
| 63 | #define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c) | ||
| 64 | |||
| 65 | #define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00) | ||
| 66 | #define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04) | ||
| 67 | #define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10) | ||
| 68 | #define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14) | ||
| 69 | #define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18) | ||
| 70 | #define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c) | ||
| 71 | #define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c) | ||
| 72 | |||
| 73 | #define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00) | ||
| 74 | #define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04) | ||
| 75 | #define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10) | ||
| 76 | #define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14) | ||
| 77 | #define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18) | ||
| 78 | #define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c) | ||
| 79 | #define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c) | ||
| 80 | |||
| 81 | #define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00) | ||
| 82 | #define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04) | ||
| 83 | #define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10) | ||
| 84 | #define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14) | ||
| 85 | #define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18) | ||
| 86 | #define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c) | ||
| 87 | #define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c) | ||
| 88 | |||
| 89 | /* | ||
| 90 | * ---------------------------------------------------------------------------- | ||
| 91 | * Clocks | ||
| 92 | * ---------------------------------------------------------------------------- | ||
| 93 | */ | ||
| 94 | #define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) | ||
| 95 | |||
| 96 | /* | ||
| 97 | * ---------------------------------------------------------------------------- | ||
| 98 | * Pin configuration registers | ||
| 99 | * ---------------------------------------------------------------------------- | ||
| 100 | */ | ||
| 101 | #define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8) | ||
| 102 | #define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9) | ||
| 103 | #define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10) | ||
| 104 | #define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11) | ||
| 105 | #define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13) | ||
| 106 | |||
| 107 | /* | ||
| 108 | * ---------------------------------------------------------------------------- | ||
| 109 | * System control registers | ||
| 110 | * ---------------------------------------------------------------------------- | ||
| 111 | */ | ||
| 112 | #define OMAP1610_RESET_CONTROL 0xfffe1140 | ||
| 113 | |||
| 114 | /* | ||
| 115 | * --------------------------------------------------------------------------- | ||
| 116 | * TIPB bus interface | ||
| 117 | * --------------------------------------------------------------------------- | ||
| 118 | */ | ||
| 119 | #define TIPB_SWITCH_BASE (0xfffbc800) | ||
| 120 | #define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) | ||
| 121 | |||
| 122 | /* UART3 Registers Maping through MPU bus */ | ||
| 123 | #define UART3_RHR (OMAP_UART3_BASE + 0) | ||
| 124 | #define UART3_THR (OMAP_UART3_BASE + 0) | ||
| 125 | #define UART3_DLL (OMAP_UART3_BASE + 0) | ||
| 126 | #define UART3_IER (OMAP_UART3_BASE + 4) | ||
| 127 | #define UART3_DLH (OMAP_UART3_BASE + 4) | ||
| 128 | #define UART3_IIR (OMAP_UART3_BASE + 8) | ||
| 129 | #define UART3_FCR (OMAP_UART3_BASE + 8) | ||
| 130 | #define UART3_EFR (OMAP_UART3_BASE + 8) | ||
| 131 | #define UART3_LCR (OMAP_UART3_BASE + 0x0C) | ||
| 132 | #define UART3_MCR (OMAP_UART3_BASE + 0x10) | ||
| 133 | #define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10) | ||
| 134 | #define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14) | ||
| 135 | #define UART3_LSR (OMAP_UART3_BASE + 0x14) | ||
| 136 | #define UART3_TCR (OMAP_UART3_BASE + 0x18) | ||
| 137 | #define UART3_MSR (OMAP_UART3_BASE + 0x18) | ||
| 138 | #define UART3_XOFF1 (OMAP_UART3_BASE + 0x18) | ||
| 139 | #define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C) | ||
| 140 | #define UART3_SPR (OMAP_UART3_BASE + 0x1C) | ||
| 141 | #define UART3_TLR (OMAP_UART3_BASE + 0x1C) | ||
| 142 | #define UART3_MDR1 (OMAP_UART3_BASE + 0x20) | ||
| 143 | #define UART3_MDR2 (OMAP_UART3_BASE + 0x24) | ||
| 144 | #define UART3_SFLSR (OMAP_UART3_BASE + 0x28) | ||
| 145 | #define UART3_TXFLL (OMAP_UART3_BASE + 0x28) | ||
| 146 | #define UART3_RESUME (OMAP_UART3_BASE + 0x2C) | ||
| 147 | #define UART3_TXFLH (OMAP_UART3_BASE + 0x2C) | ||
| 148 | #define UART3_SFREGL (OMAP_UART3_BASE + 0x30) | ||
| 149 | #define UART3_RXFLL (OMAP_UART3_BASE + 0x30) | ||
| 150 | #define UART3_SFREGH (OMAP_UART3_BASE + 0x34) | ||
| 151 | #define UART3_RXFLH (OMAP_UART3_BASE + 0x34) | ||
| 152 | #define UART3_BLR (OMAP_UART3_BASE + 0x38) | ||
| 153 | #define UART3_ACREG (OMAP_UART3_BASE + 0x3C) | ||
| 154 | #define UART3_DIV16 (OMAP_UART3_BASE + 0x3C) | ||
| 155 | #define UART3_SCR (OMAP_UART3_BASE + 0x40) | ||
| 156 | #define UART3_SSR (OMAP_UART3_BASE + 0x44) | ||
| 157 | #define UART3_EBLR (OMAP_UART3_BASE + 0x48) | ||
| 158 | #define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C) | ||
| 159 | #define UART3_MVR (OMAP_UART3_BASE + 0x50) | ||
| 160 | |||
| 161 | /* | ||
| 162 | * --------------------------------------------------------------------------- | ||
| 163 | * Watchdog timer | ||
| 164 | * --------------------------------------------------------------------------- | ||
| 165 | */ | ||
| 166 | |||
| 167 | /* 32-bit Watchdog timer in OMAP 16XX */ | ||
| 168 | #define OMAP_16XX_WATCHDOG_BASE (0xfffeb000) | ||
| 169 | #define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00) | ||
| 170 | #define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10) | ||
| 171 | #define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14) | ||
| 172 | #define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24) | ||
| 173 | #define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28) | ||
| 174 | #define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c) | ||
| 175 | #define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30) | ||
| 176 | #define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34) | ||
| 177 | #define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48) | ||
| 178 | |||
| 179 | #define WCLR_PRE_SHIFT 5 | ||
| 180 | #define WCLR_PTV_SHIFT 2 | ||
| 181 | |||
| 182 | #define WWPS_W_PEND_WSPR (1 << 4) | ||
| 183 | #define WWPS_W_PEND_WTGR (1 << 3) | ||
| 184 | #define WWPS_W_PEND_WLDR (1 << 2) | ||
| 185 | #define WWPS_W_PEND_WCRR (1 << 1) | ||
| 186 | #define WWPS_W_PEND_WCLR (1 << 0) | ||
| 187 | |||
| 188 | #define WSPR_ENABLE_0 (0x0000bbbb) | ||
| 189 | #define WSPR_ENABLE_1 (0x00004444) | ||
| 190 | #define WSPR_DISABLE_0 (0x0000aaaa) | ||
| 191 | #define WSPR_DISABLE_1 (0x00005555) | ||
| 192 | |||
| 193 | /* Mailbox */ | ||
| 194 | #define OMAP16XX_MAILBOX_BASE (0xfffcf000) | ||
| 195 | |||
| 196 | #endif /* __ASM_ARCH_OMAP16XX_H */ | ||
| 197 | |||
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h deleted file mode 100644 index b9fcaae287c8..000000000000 --- a/include/asm-arm/arch-omap/omap24xx.h +++ /dev/null | |||
| @@ -1,107 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-omap/omap24xx.h | ||
| 3 | * | ||
| 4 | * This file contains the processor specific definitions | ||
| 5 | * of the TI OMAP24XX. | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007 Texas Instruments. | ||
| 8 | * Copyright (C) 2007 Nokia Corporation. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 23 | * | ||
| 24 | */ | ||
| 25 | |||
| 26 | #ifndef __ASM_ARCH_OMAP24XX_H | ||
| 27 | #define __ASM_ARCH_OMAP24XX_H | ||
| 28 | |||
| 29 | /* | ||
| 30 | * Please place only base defines here and put the rest in device | ||
| 31 | * specific headers. Note also that some of these defines are needed | ||
| 32 | * for omap1 to compile without adding ifdefs. | ||
| 33 | */ | ||
| 34 | |||
| 35 | #define L4_24XX_BASE 0x48000000 | ||
| 36 | #define L4_WK_243X_BASE 0x49000000 | ||
| 37 | #define L3_24XX_BASE 0x68000000 | ||
| 38 | |||
| 39 | /* interrupt controller */ | ||
| 40 | #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) | ||
| 41 | #define OMAP24XX_IVA_INTC_BASE 0x40000000 | ||
| 42 | #define IRQ_SIR_IRQ 0x0040 | ||
| 43 | |||
| 44 | #define OMAP2420_CTRL_BASE L4_24XX_BASE | ||
| 45 | #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) | ||
| 46 | #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) | ||
| 47 | #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) | ||
| 48 | #define OMAP2420_PRM_BASE OMAP2420_CM_BASE | ||
| 49 | #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) | ||
| 50 | #define OMAP2420_SMS_BASE 0x68008000 | ||
| 51 | |||
| 52 | #define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) | ||
| 53 | #define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000) | ||
| 54 | #define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000) | ||
| 55 | #define OMAP2430_PRM_BASE OMAP2430_CM_BASE | ||
| 56 | |||
| 57 | #define OMAP243X_SMS_BASE 0x6C000000 | ||
| 58 | #define OMAP243X_SDRC_BASE 0x6D000000 | ||
| 59 | #define OMAP243X_GPMC_BASE 0x6E000000 | ||
| 60 | #define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000) | ||
| 61 | #define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE | ||
| 62 | #define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000) | ||
| 63 | |||
| 64 | /* DSP SS */ | ||
| 65 | #define OMAP2420_DSP_BASE 0x58000000 | ||
| 66 | #define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0) | ||
| 67 | #define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000) | ||
| 68 | #define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000) | ||
| 69 | |||
| 70 | #define OMAP243X_DSP_BASE 0x5C000000 | ||
| 71 | #define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0) | ||
| 72 | #define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000) | ||
| 73 | |||
| 74 | /* Mailbox */ | ||
| 75 | #define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000) | ||
| 76 | |||
| 77 | /* Camera */ | ||
| 78 | #define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000) | ||
| 79 | |||
| 80 | /* Security */ | ||
| 81 | #define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000) | ||
| 82 | #define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000) | ||
| 83 | #define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000) | ||
| 84 | #define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000) | ||
| 85 | #define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) | ||
| 86 | #define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) | ||
| 87 | |||
| 88 | #if defined(CONFIG_ARCH_OMAP2420) | ||
| 89 | |||
| 90 | #define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE | ||
| 91 | #define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE | ||
| 92 | #define OMAP2_CM_BASE OMAP2420_CM_BASE | ||
| 93 | #define OMAP2_PRM_BASE OMAP2420_PRM_BASE | ||
| 94 | #define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) | ||
| 95 | |||
| 96 | #elif defined(CONFIG_ARCH_OMAP2430) | ||
| 97 | |||
| 98 | #define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE | ||
| 99 | #define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE | ||
| 100 | #define OMAP2_CM_BASE OMAP2430_CM_BASE | ||
| 101 | #define OMAP2_PRM_BASE OMAP2430_PRM_BASE | ||
| 102 | #define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE) | ||
| 103 | |||
| 104 | #endif | ||
| 105 | |||
| 106 | #endif /* __ASM_ARCH_OMAP24XX_H */ | ||
| 107 | |||
diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h deleted file mode 100644 index aa30c6d10abd..000000000000 --- a/include/asm-arm/arch-omap/omap34xx.h +++ /dev/null | |||
| @@ -1,72 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-omap/omap34xx.h | ||
| 3 | * | ||
| 4 | * This file contains the processor specific definitions of the TI OMAP34XX. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Texas Instruments. | ||
| 7 | * Copyright (C) 2007 Nokia Corporation. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef __ASM_ARCH_OMAP34XX_H | ||
| 25 | #define __ASM_ARCH_OMAP34XX_H | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Please place only base defines here and put the rest in device | ||
| 29 | * specific headers. | ||
| 30 | */ | ||
| 31 | |||
| 32 | #define L4_34XX_BASE 0x48000000 | ||
| 33 | #define L4_WK_34XX_BASE 0x48300000 | ||
| 34 | #define L4_WK_OMAP_BASE L4_WK_34XX_BASE | ||
| 35 | #define L4_PER_34XX_BASE 0x49000000 | ||
| 36 | #define L4_PER_OMAP_BASE L4_PER_34XX_BASE | ||
| 37 | #define L4_EMU_34XX_BASE 0x54000000 | ||
| 38 | #define L4_EMU_BASE L4_EMU_34XX_BASE | ||
| 39 | #define L3_34XX_BASE 0x68000000 | ||
| 40 | #define L3_OMAP_BASE L3_34XX_BASE | ||
| 41 | |||
| 42 | #define OMAP3430_32KSYNCT_BASE 0x48320000 | ||
| 43 | #define OMAP3430_CM_BASE 0x48004800 | ||
| 44 | #define OMAP3430_PRM_BASE 0x48306800 | ||
| 45 | #define OMAP343X_SMS_BASE 0x6C000000 | ||
| 46 | #define OMAP343X_SDRC_BASE 0x6D000000 | ||
| 47 | #define OMAP34XX_GPMC_BASE 0x6E000000 | ||
| 48 | #define OMAP343X_SCM_BASE 0x48002000 | ||
| 49 | #define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE | ||
| 50 | |||
| 51 | #define OMAP34XX_IC_BASE 0x48200000 | ||
| 52 | #define OMAP34XX_IVA_INTC_BASE 0x40000000 | ||
| 53 | #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) | ||
| 54 | #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) | ||
| 55 | #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) | ||
| 56 | |||
| 57 | |||
| 58 | #if defined(CONFIG_ARCH_OMAP3430) | ||
| 59 | |||
| 60 | #define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE | ||
| 61 | #define OMAP2_CM_BASE OMAP3430_CM_BASE | ||
| 62 | #define OMAP2_PRM_BASE OMAP3430_PRM_BASE | ||
| 63 | #define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) | ||
| 64 | |||
| 65 | #endif | ||
| 66 | |||
| 67 | #define OMAP34XX_DSP_BASE 0x58000000 | ||
| 68 | #define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0) | ||
| 69 | #define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000) | ||
| 70 | #define OMAP34XX_DSP_MMU_BASE (OMAP34XX_DSP_BASE + 0x2000000) | ||
| 71 | #endif /* __ASM_ARCH_OMAP34XX_H */ | ||
| 72 | |||
diff --git a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h deleted file mode 100644 index 755b64c5e9f0..000000000000 --- a/include/asm-arm/arch-omap/omap730.h +++ /dev/null | |||
| @@ -1,102 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-omap/omap730.h | ||
| 2 | * | ||
| 3 | * Hardware definitions for TI OMAP730 processor. | ||
| 4 | * | ||
| 5 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License along | ||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 26 | */ | ||
| 27 | |||
| 28 | #ifndef __ASM_ARCH_OMAP730_H | ||
| 29 | #define __ASM_ARCH_OMAP730_H | ||
| 30 | |||
| 31 | /* | ||
| 32 | * ---------------------------------------------------------------------------- | ||
| 33 | * Base addresses | ||
| 34 | * ---------------------------------------------------------------------------- | ||
| 35 | */ | ||
| 36 | |||
| 37 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ | ||
| 38 | |||
| 39 | #define OMAP730_DSP_BASE 0xE0000000 | ||
| 40 | #define OMAP730_DSP_SIZE 0x50000 | ||
| 41 | #define OMAP730_DSP_START 0xE0000000 | ||
| 42 | |||
| 43 | #define OMAP730_DSPREG_BASE 0xE1000000 | ||
| 44 | #define OMAP730_DSPREG_SIZE SZ_128K | ||
| 45 | #define OMAP730_DSPREG_START 0xE1000000 | ||
| 46 | |||
| 47 | /* | ||
| 48 | * ---------------------------------------------------------------------------- | ||
| 49 | * OMAP730 specific configuration registers | ||
| 50 | * ---------------------------------------------------------------------------- | ||
| 51 | */ | ||
| 52 | #define OMAP730_CONFIG_BASE 0xfffe1000 | ||
| 53 | #define OMAP730_IO_CONF_0 0xfffe1070 | ||
| 54 | #define OMAP730_IO_CONF_1 0xfffe1074 | ||
| 55 | #define OMAP730_IO_CONF_2 0xfffe1078 | ||
| 56 | #define OMAP730_IO_CONF_3 0xfffe107c | ||
| 57 | #define OMAP730_IO_CONF_4 0xfffe1080 | ||
| 58 | #define OMAP730_IO_CONF_5 0xfffe1084 | ||
| 59 | #define OMAP730_IO_CONF_6 0xfffe1088 | ||
| 60 | #define OMAP730_IO_CONF_7 0xfffe108c | ||
| 61 | #define OMAP730_IO_CONF_8 0xfffe1090 | ||
| 62 | #define OMAP730_IO_CONF_9 0xfffe1094 | ||
| 63 | #define OMAP730_IO_CONF_10 0xfffe1098 | ||
| 64 | #define OMAP730_IO_CONF_11 0xfffe109c | ||
| 65 | #define OMAP730_IO_CONF_12 0xfffe10a0 | ||
| 66 | #define OMAP730_IO_CONF_13 0xfffe10a4 | ||
| 67 | |||
| 68 | #define OMAP730_MODE_1 0xfffe1010 | ||
| 69 | #define OMAP730_MODE_2 0xfffe1014 | ||
| 70 | |||
| 71 | /* CSMI specials: in terms of base + offset */ | ||
| 72 | #define OMAP730_MODE2_OFFSET 0x14 | ||
| 73 | |||
| 74 | /* | ||
| 75 | * ---------------------------------------------------------------------------- | ||
| 76 | * OMAP730 traffic controller configuration registers | ||
| 77 | * ---------------------------------------------------------------------------- | ||
| 78 | */ | ||
| 79 | #define OMAP730_FLASH_CFG_0 0xfffecc10 | ||
| 80 | #define OMAP730_FLASH_ACFG_0 0xfffecc50 | ||
| 81 | #define OMAP730_FLASH_CFG_1 0xfffecc14 | ||
| 82 | #define OMAP730_FLASH_ACFG_1 0xfffecc54 | ||
| 83 | |||
| 84 | /* | ||
| 85 | * ---------------------------------------------------------------------------- | ||
| 86 | * OMAP730 DSP control registers | ||
| 87 | * ---------------------------------------------------------------------------- | ||
| 88 | */ | ||
| 89 | #define OMAP730_ICR_BASE 0xfffbb800 | ||
| 90 | #define OMAP730_DSP_M_CTL 0xfffbb804 | ||
| 91 | #define OMAP730_DSP_MMU_BASE 0xfffed200 | ||
| 92 | |||
| 93 | /* | ||
| 94 | * ---------------------------------------------------------------------------- | ||
| 95 | * OMAP730 PCC_UPLD configuration registers | ||
| 96 | * ---------------------------------------------------------------------------- | ||
| 97 | */ | ||
| 98 | #define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900) | ||
| 99 | #define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00) | ||
| 100 | |||
| 101 | #endif /* __ASM_ARCH_OMAP730_H */ | ||
| 102 | |||
diff --git a/include/asm-arm/arch-omap/omapfb.h b/include/asm-arm/arch-omap/omapfb.h deleted file mode 100644 index 46d7a4f60854..000000000000 --- a/include/asm-arm/arch-omap/omapfb.h +++ /dev/null | |||
| @@ -1,395 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-arm/arch-omap/omapfb.h | ||
| 3 | * | ||
| 4 | * Framebuffer driver for TI OMAP boards | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004 Nokia Corporation | ||
| 7 | * Author: Imre Deak <imre.deak@nokia.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, but | ||
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 17 | * General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License along | ||
| 20 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 21 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef __OMAPFB_H | ||
| 25 | #define __OMAPFB_H | ||
| 26 | |||
| 27 | #include <asm/ioctl.h> | ||
| 28 | #include <asm/types.h> | ||
| 29 | |||
| 30 | /* IOCTL commands. */ | ||
| 31 | |||
| 32 | #define OMAP_IOW(num, dtype) _IOW('O', num, dtype) | ||
| 33 | #define OMAP_IOR(num, dtype) _IOR('O', num, dtype) | ||
| 34 | #define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype) | ||
| 35 | #define OMAP_IO(num) _IO('O', num) | ||
| 36 | |||
| 37 | #define OMAPFB_MIRROR OMAP_IOW(31, int) | ||
| 38 | #define OMAPFB_SYNC_GFX OMAP_IO(37) | ||
| 39 | #define OMAPFB_VSYNC OMAP_IO(38) | ||
| 40 | #define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int) | ||
| 41 | #define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps) | ||
| 42 | #define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int) | ||
| 43 | #define OMAPFB_LCD_TEST OMAP_IOW(45, int) | ||
| 44 | #define OMAPFB_CTRL_TEST OMAP_IOW(46, int) | ||
| 45 | #define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old) | ||
| 46 | #define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key) | ||
| 47 | #define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key) | ||
| 48 | #define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info) | ||
| 49 | #define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info) | ||
| 50 | #define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window) | ||
| 51 | #define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info) | ||
| 52 | #define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info) | ||
| 53 | |||
| 54 | #define OMAPFB_CAPS_GENERIC_MASK 0x00000fff | ||
| 55 | #define OMAPFB_CAPS_LCDC_MASK 0x00fff000 | ||
| 56 | #define OMAPFB_CAPS_PANEL_MASK 0xff000000 | ||
| 57 | |||
| 58 | #define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000 | ||
| 59 | #define OMAPFB_CAPS_TEARSYNC 0x00002000 | ||
| 60 | #define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000 | ||
| 61 | #define OMAPFB_CAPS_PLANE_SCALE 0x00008000 | ||
| 62 | #define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000 | ||
| 63 | #define OMAPFB_CAPS_WINDOW_SCALE 0x00020000 | ||
| 64 | #define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000 | ||
| 65 | #define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000 | ||
| 66 | |||
| 67 | /* Values from DSP must map to lower 16-bits */ | ||
| 68 | #define OMAPFB_FORMAT_MASK 0x00ff | ||
| 69 | #define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100 | ||
| 70 | #define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200 | ||
| 71 | #define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400 | ||
| 72 | #define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800 | ||
| 73 | #define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000 | ||
| 74 | |||
| 75 | #define OMAPFB_EVENT_READY 1 | ||
| 76 | #define OMAPFB_EVENT_DISABLED 2 | ||
| 77 | |||
| 78 | #define OMAPFB_MEMTYPE_SDRAM 0 | ||
| 79 | #define OMAPFB_MEMTYPE_SRAM 1 | ||
| 80 | #define OMAPFB_MEMTYPE_MAX 1 | ||
| 81 | |||
| 82 | enum omapfb_color_format { | ||
| 83 | OMAPFB_COLOR_RGB565 = 0, | ||
| 84 | OMAPFB_COLOR_YUV422, | ||
| 85 | OMAPFB_COLOR_YUV420, | ||
| 86 | OMAPFB_COLOR_CLUT_8BPP, | ||
| 87 | OMAPFB_COLOR_CLUT_4BPP, | ||
| 88 | OMAPFB_COLOR_CLUT_2BPP, | ||
| 89 | OMAPFB_COLOR_CLUT_1BPP, | ||
| 90 | OMAPFB_COLOR_RGB444, | ||
| 91 | OMAPFB_COLOR_YUY422, | ||
| 92 | }; | ||
| 93 | |||
| 94 | struct omapfb_update_window { | ||
| 95 | __u32 x, y; | ||
| 96 | __u32 width, height; | ||
| 97 | __u32 format; | ||
| 98 | __u32 out_x, out_y; | ||
| 99 | __u32 out_width, out_height; | ||
| 100 | __u32 reserved[8]; | ||
| 101 | }; | ||
| 102 | |||
| 103 | struct omapfb_update_window_old { | ||
| 104 | __u32 x, y; | ||
| 105 | __u32 width, height; | ||
| 106 | __u32 format; | ||
| 107 | }; | ||
| 108 | |||
| 109 | enum omapfb_plane { | ||
| 110 | OMAPFB_PLANE_GFX = 0, | ||
| 111 | OMAPFB_PLANE_VID1, | ||
| 112 | OMAPFB_PLANE_VID2, | ||
| 113 | }; | ||
| 114 | |||
| 115 | enum omapfb_channel_out { | ||
| 116 | OMAPFB_CHANNEL_OUT_LCD = 0, | ||
| 117 | OMAPFB_CHANNEL_OUT_DIGIT, | ||
| 118 | }; | ||
| 119 | |||
| 120 | struct omapfb_plane_info { | ||
| 121 | __u32 pos_x; | ||
| 122 | __u32 pos_y; | ||
| 123 | __u8 enabled; | ||
| 124 | __u8 channel_out; | ||
| 125 | __u8 mirror; | ||
| 126 | __u8 reserved1; | ||
| 127 | __u32 out_width; | ||
| 128 | __u32 out_height; | ||
| 129 | __u32 reserved2[12]; | ||
| 130 | }; | ||
| 131 | |||
| 132 | struct omapfb_mem_info { | ||
| 133 | __u32 size; | ||
| 134 | __u8 type; | ||
| 135 | __u8 reserved[3]; | ||
| 136 | }; | ||
| 137 | |||
| 138 | struct omapfb_caps { | ||
| 139 | __u32 ctrl; | ||
| 140 | __u32 plane_color; | ||
| 141 | __u32 wnd_color; | ||
| 142 | }; | ||
| 143 | |||
| 144 | enum omapfb_color_key_type { | ||
| 145 | OMAPFB_COLOR_KEY_DISABLED = 0, | ||
| 146 | OMAPFB_COLOR_KEY_GFX_DST, | ||
| 147 | OMAPFB_COLOR_KEY_VID_SRC, | ||
| 148 | }; | ||
| 149 | |||
| 150 | struct omapfb_color_key { | ||
| 151 | __u8 channel_out; | ||
| 152 | __u32 background; | ||
| 153 | __u32 trans_key; | ||
| 154 | __u8 key_type; | ||
| 155 | }; | ||
| 156 | |||
| 157 | enum omapfb_update_mode { | ||
| 158 | OMAPFB_UPDATE_DISABLED = 0, | ||
| 159 | OMAPFB_AUTO_UPDATE, | ||
| 160 | OMAPFB_MANUAL_UPDATE | ||
| 161 | }; | ||
| 162 | |||
| 163 | #ifdef __KERNEL__ | ||
| 164 | |||
| 165 | #include <linux/completion.h> | ||
| 166 | #include <linux/interrupt.h> | ||
| 167 | #include <linux/fb.h> | ||
| 168 | #include <linux/mutex.h> | ||
| 169 | |||
| 170 | #include <asm/arch/board.h> | ||
| 171 | |||
| 172 | #define OMAP_LCDC_INV_VSYNC 0x0001 | ||
| 173 | #define OMAP_LCDC_INV_HSYNC 0x0002 | ||
| 174 | #define OMAP_LCDC_INV_PIX_CLOCK 0x0004 | ||
| 175 | #define OMAP_LCDC_INV_OUTPUT_EN 0x0008 | ||
| 176 | #define OMAP_LCDC_HSVS_RISING_EDGE 0x0010 | ||
| 177 | #define OMAP_LCDC_HSVS_OPPOSITE 0x0020 | ||
| 178 | |||
| 179 | #define OMAP_LCDC_SIGNAL_MASK 0x003f | ||
| 180 | |||
| 181 | #define OMAP_LCDC_PANEL_TFT 0x0100 | ||
| 182 | |||
| 183 | #define OMAPFB_PLANE_XRES_MIN 8 | ||
| 184 | #define OMAPFB_PLANE_YRES_MIN 8 | ||
| 185 | |||
| 186 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 187 | #define OMAPFB_PLANE_NUM 1 | ||
| 188 | #else | ||
| 189 | #define OMAPFB_PLANE_NUM 3 | ||
| 190 | #endif | ||
| 191 | |||
| 192 | struct omapfb_device; | ||
| 193 | |||
| 194 | struct lcd_panel { | ||
| 195 | const char *name; | ||
| 196 | int config; /* TFT/STN, signal inversion */ | ||
| 197 | int bpp; /* Pixel format in fb mem */ | ||
| 198 | int data_lines; /* Lines on LCD HW interface */ | ||
| 199 | |||
| 200 | int x_res, y_res; | ||
| 201 | int pixel_clock; /* In kHz */ | ||
| 202 | int hsw; /* Horizontal synchronization | ||
| 203 | pulse width */ | ||
| 204 | int hfp; /* Horizontal front porch */ | ||
| 205 | int hbp; /* Horizontal back porch */ | ||
| 206 | int vsw; /* Vertical synchronization | ||
| 207 | pulse width */ | ||
| 208 | int vfp; /* Vertical front porch */ | ||
| 209 | int vbp; /* Vertical back porch */ | ||
| 210 | int acb; /* ac-bias pin frequency */ | ||
| 211 | int pcd; /* pixel clock divider. | ||
| 212 | Obsolete use pixel_clock instead */ | ||
| 213 | |||
| 214 | int (*init) (struct lcd_panel *panel, | ||
| 215 | struct omapfb_device *fbdev); | ||
| 216 | void (*cleanup) (struct lcd_panel *panel); | ||
| 217 | int (*enable) (struct lcd_panel *panel); | ||
| 218 | void (*disable) (struct lcd_panel *panel); | ||
| 219 | unsigned long (*get_caps) (struct lcd_panel *panel); | ||
| 220 | int (*set_bklight_level)(struct lcd_panel *panel, | ||
| 221 | unsigned int level); | ||
| 222 | unsigned int (*get_bklight_level)(struct lcd_panel *panel); | ||
| 223 | unsigned int (*get_bklight_max) (struct lcd_panel *panel); | ||
| 224 | int (*run_test) (struct lcd_panel *panel, int test_num); | ||
| 225 | }; | ||
| 226 | |||
| 227 | struct extif_timings { | ||
| 228 | int cs_on_time; | ||
| 229 | int cs_off_time; | ||
| 230 | int we_on_time; | ||
| 231 | int we_off_time; | ||
| 232 | int re_on_time; | ||
| 233 | int re_off_time; | ||
| 234 | int we_cycle_time; | ||
| 235 | int re_cycle_time; | ||
| 236 | int cs_pulse_width; | ||
| 237 | int access_time; | ||
| 238 | |||
| 239 | int clk_div; | ||
| 240 | |||
| 241 | u32 tim[5]; /* set by extif->convert_timings */ | ||
| 242 | |||
| 243 | int converted; | ||
| 244 | }; | ||
| 245 | |||
| 246 | struct lcd_ctrl_extif { | ||
| 247 | int (*init) (struct omapfb_device *fbdev); | ||
| 248 | void (*cleanup) (void); | ||
| 249 | void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div); | ||
| 250 | unsigned long (*get_max_tx_rate)(void); | ||
| 251 | int (*convert_timings) (struct extif_timings *timings); | ||
| 252 | void (*set_timings) (const struct extif_timings *timings); | ||
| 253 | void (*set_bits_per_cycle)(int bpc); | ||
| 254 | void (*write_command) (const void *buf, unsigned int len); | ||
| 255 | void (*read_data) (void *buf, unsigned int len); | ||
| 256 | void (*write_data) (const void *buf, unsigned int len); | ||
| 257 | void (*transfer_area) (int width, int height, | ||
| 258 | void (callback)(void * data), void *data); | ||
| 259 | int (*setup_tearsync) (unsigned pin_cnt, | ||
| 260 | unsigned hs_pulse_time, unsigned vs_pulse_time, | ||
| 261 | int hs_pol_inv, int vs_pol_inv, int div); | ||
| 262 | int (*enable_tearsync) (int enable, unsigned line); | ||
| 263 | |||
| 264 | unsigned long max_transmit_size; | ||
| 265 | }; | ||
| 266 | |||
| 267 | struct omapfb_notifier_block { | ||
| 268 | struct notifier_block nb; | ||
| 269 | void *data; | ||
| 270 | int plane_idx; | ||
| 271 | }; | ||
| 272 | |||
| 273 | typedef int (*omapfb_notifier_callback_t)(struct notifier_block *, | ||
| 274 | unsigned long event, | ||
| 275 | void *fbi); | ||
| 276 | |||
| 277 | struct omapfb_mem_region { | ||
| 278 | dma_addr_t paddr; | ||
| 279 | void *vaddr; | ||
| 280 | unsigned long size; | ||
| 281 | u8 type; /* OMAPFB_PLANE_MEM_* */ | ||
| 282 | unsigned alloc:1; /* allocated by the driver */ | ||
| 283 | unsigned map:1; /* kernel mapped by the driver */ | ||
| 284 | }; | ||
| 285 | |||
| 286 | struct omapfb_mem_desc { | ||
| 287 | int region_cnt; | ||
| 288 | struct omapfb_mem_region region[OMAPFB_PLANE_NUM]; | ||
| 289 | }; | ||
| 290 | |||
| 291 | struct lcd_ctrl { | ||
| 292 | const char *name; | ||
| 293 | void *data; | ||
| 294 | |||
| 295 | int (*init) (struct omapfb_device *fbdev, | ||
| 296 | int ext_mode, | ||
| 297 | struct omapfb_mem_desc *req_md); | ||
| 298 | void (*cleanup) (void); | ||
| 299 | void (*bind_client) (struct omapfb_notifier_block *nb); | ||
| 300 | void (*get_caps) (int plane, struct omapfb_caps *caps); | ||
| 301 | int (*set_update_mode)(enum omapfb_update_mode mode); | ||
| 302 | enum omapfb_update_mode (*get_update_mode)(void); | ||
| 303 | int (*setup_plane) (int plane, int channel_out, | ||
| 304 | unsigned long offset, | ||
| 305 | int screen_width, | ||
| 306 | int pos_x, int pos_y, int width, | ||
| 307 | int height, int color_mode); | ||
| 308 | int (*setup_mem) (int plane, size_t size, | ||
| 309 | int mem_type, unsigned long *paddr); | ||
| 310 | int (*mmap) (struct fb_info *info, | ||
| 311 | struct vm_area_struct *vma); | ||
| 312 | int (*set_scale) (int plane, | ||
| 313 | int orig_width, int orig_height, | ||
| 314 | int out_width, int out_height); | ||
| 315 | int (*enable_plane) (int plane, int enable); | ||
| 316 | int (*update_window) (struct fb_info *fbi, | ||
| 317 | struct omapfb_update_window *win, | ||
| 318 | void (*callback)(void *), | ||
| 319 | void *callback_data); | ||
| 320 | void (*sync) (void); | ||
| 321 | void (*suspend) (void); | ||
| 322 | void (*resume) (void); | ||
| 323 | int (*run_test) (int test_num); | ||
| 324 | int (*setcolreg) (u_int regno, u16 red, u16 green, | ||
| 325 | u16 blue, u16 transp, | ||
| 326 | int update_hw_mem); | ||
| 327 | int (*set_color_key) (struct omapfb_color_key *ck); | ||
| 328 | int (*get_color_key) (struct omapfb_color_key *ck); | ||
| 329 | }; | ||
| 330 | |||
| 331 | enum omapfb_state { | ||
| 332 | OMAPFB_DISABLED = 0, | ||
| 333 | OMAPFB_SUSPENDED= 99, | ||
| 334 | OMAPFB_ACTIVE = 100 | ||
| 335 | }; | ||
| 336 | |||
| 337 | struct omapfb_plane_struct { | ||
| 338 | int idx; | ||
| 339 | struct omapfb_plane_info info; | ||
| 340 | enum omapfb_color_format color_mode; | ||
| 341 | struct omapfb_device *fbdev; | ||
| 342 | }; | ||
| 343 | |||
| 344 | struct omapfb_device { | ||
| 345 | int state; | ||
| 346 | int ext_lcdc; /* Using external | ||
| 347 | LCD controller */ | ||
| 348 | struct mutex rqueue_mutex; | ||
| 349 | |||
| 350 | int palette_size; | ||
| 351 | u32 pseudo_palette[17]; | ||
| 352 | |||
| 353 | struct lcd_panel *panel; /* LCD panel */ | ||
| 354 | struct lcd_ctrl *ctrl; /* LCD controller */ | ||
| 355 | struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */ | ||
| 356 | struct lcd_ctrl_extif *ext_if; /* LCD ctrl external | ||
| 357 | interface */ | ||
| 358 | struct device *dev; | ||
| 359 | struct fb_var_screeninfo new_var; /* for mode changes */ | ||
| 360 | |||
| 361 | struct omapfb_mem_desc mem_desc; | ||
| 362 | struct fb_info *fb_info[OMAPFB_PLANE_NUM]; | ||
| 363 | }; | ||
| 364 | |||
| 365 | struct omapfb_platform_data { | ||
| 366 | struct omap_lcd_config lcd; | ||
| 367 | struct omapfb_mem_desc mem_desc; | ||
| 368 | void *ctrl_platform_data; | ||
| 369 | }; | ||
| 370 | |||
| 371 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 372 | extern struct lcd_ctrl omap1_lcd_ctrl; | ||
| 373 | #else | ||
| 374 | extern struct lcd_ctrl omap2_disp_ctrl; | ||
| 375 | #endif | ||
| 376 | |||
| 377 | extern void omapfb_register_panel(struct lcd_panel *panel); | ||
| 378 | extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); | ||
| 379 | extern void omapfb_notify_clients(struct omapfb_device *fbdev, | ||
| 380 | unsigned long event); | ||
| 381 | extern int omapfb_register_client(struct omapfb_notifier_block *nb, | ||
| 382 | omapfb_notifier_callback_t callback, | ||
| 383 | void *callback_data); | ||
| 384 | extern int omapfb_unregister_client(struct omapfb_notifier_block *nb); | ||
| 385 | extern int omapfb_update_window_async(struct fb_info *fbi, | ||
| 386 | struct omapfb_update_window *win, | ||
| 387 | void (*callback)(void *), | ||
| 388 | void *callback_data); | ||
| 389 | |||
| 390 | /* in arch/arm/plat-omap/fb.c */ | ||
| 391 | extern void omapfb_set_ctrl_platform_data(void *pdata); | ||
| 392 | |||
| 393 | #endif /* __KERNEL__ */ | ||
| 394 | |||
| 395 | #endif /* __OMAPFB_H */ | ||
diff --git a/include/asm-arm/arch-omap/onenand.h b/include/asm-arm/arch-omap/onenand.h deleted file mode 100644 index 6c959d0ce470..000000000000 --- a/include/asm-arm/arch-omap/onenand.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-omap/onenand.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Nokia Corporation | ||
| 5 | * Author: Juha Yrjola | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/mtd/partitions.h> | ||
| 13 | |||
| 14 | struct omap_onenand_platform_data { | ||
| 15 | int cs; | ||
| 16 | int gpio_irq; | ||
| 17 | struct mtd_partition *parts; | ||
| 18 | int nr_parts; | ||
| 19 | int (*onenand_setup)(void __iomem *); | ||
| 20 | int dma_channel; | ||
| 21 | }; | ||
diff --git a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h deleted file mode 100644 index face9ad41e97..000000000000 --- a/include/asm-arm/arch-omap/param.h +++ /dev/null | |||
| @@ -1,8 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/param.h | ||
| 3 | * | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifdef CONFIG_OMAP_32K_TIMER_HZ | ||
| 7 | #define HZ CONFIG_OMAP_32K_TIMER_HZ | ||
| 8 | #endif | ||
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h deleted file mode 100644 index 14588059981f..000000000000 --- a/include/asm-arm/arch-omap/pm.h +++ /dev/null | |||
| @@ -1,356 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/pm.h | ||
| 3 | * | ||
| 4 | * Header file for OMAP Power Management Routines | ||
| 5 | * | ||
| 6 | * Author: MontaVista Software, Inc. | ||
| 7 | * support@mvista.com | ||
| 8 | * | ||
| 9 | * Copyright 2002 MontaVista Software Inc. | ||
| 10 | * | ||
| 11 | * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify it | ||
| 14 | * under the terms of the GNU General Public License as published by the | ||
| 15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 16 | * option) any later version. | ||
| 17 | * | ||
| 18 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 19 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 21 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 24 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 25 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 28 | * | ||
| 29 | * You should have received a copy of the GNU General Public License along | ||
| 30 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 31 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 32 | */ | ||
| 33 | |||
| 34 | #ifndef __ASM_ARCH_OMAP_PM_H | ||
| 35 | #define __ASM_ARCH_OMAP_PM_H | ||
| 36 | |||
| 37 | /* | ||
| 38 | * ---------------------------------------------------------------------------- | ||
| 39 | * Register and offset definitions to be used in PM assembler code | ||
| 40 | * ---------------------------------------------------------------------------- | ||
| 41 | */ | ||
| 42 | #define CLKGEN_REG_ASM_BASE io_p2v(0xfffece00) | ||
| 43 | #define ARM_IDLECT1_ASM_OFFSET 0x04 | ||
| 44 | #define ARM_IDLECT2_ASM_OFFSET 0x08 | ||
| 45 | |||
| 46 | #define TCMIF_ASM_BASE io_p2v(0xfffecc00) | ||
| 47 | #define EMIFS_CONFIG_ASM_OFFSET 0x0c | ||
| 48 | #define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 | ||
| 49 | |||
| 50 | /* | ||
| 51 | * ---------------------------------------------------------------------------- | ||
| 52 | * Power management bitmasks | ||
| 53 | * ---------------------------------------------------------------------------- | ||
| 54 | */ | ||
| 55 | #define IDLE_WAIT_CYCLES 0x00000fff | ||
| 56 | #define PERIPHERAL_ENABLE 0x2 | ||
| 57 | |||
| 58 | #define SELF_REFRESH_MODE 0x0c000001 | ||
| 59 | #define IDLE_EMIFS_REQUEST 0xc | ||
| 60 | #define MODEM_32K_EN 0x1 | ||
| 61 | #define PER_EN 0x1 | ||
| 62 | |||
| 63 | #define CPU_SUSPEND_SIZE 200 | ||
| 64 | #define ULPD_LOW_PWR_EN 0x0001 | ||
| 65 | #define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010 | ||
| 66 | #define ULPD_SETUP_ANALOG_CELL_3_VAL 0 | ||
| 67 | #define ULPD_POWER_CTRL_REG_VAL 0x0219 | ||
| 68 | |||
| 69 | #define DSP_IDLE_DELAY 10 | ||
| 70 | #define DSP_IDLE 0x0040 | ||
| 71 | #define DSP_RST 0x0004 | ||
| 72 | #define DSP_ENABLE 0x0002 | ||
| 73 | #define SUFFICIENT_DSP_RESET_TIME 1000 | ||
| 74 | #define DEFAULT_MPUI_CONFIG 0x05cf | ||
| 75 | #define ENABLE_XORCLK 0x2 | ||
| 76 | #define DSP_CLOCK_ENABLE 0x2000 | ||
| 77 | #define DSP_IDLE_MODE 0x2 | ||
| 78 | #define TC_IDLE_REQUEST (0x0000000c) | ||
| 79 | |||
| 80 | #define IRQ_LEVEL2 (1<<0) | ||
| 81 | #define IRQ_KEYBOARD (1<<1) | ||
| 82 | #define IRQ_UART2 (1<<15) | ||
| 83 | |||
| 84 | #define PDE_BIT 0x08 | ||
| 85 | #define PWD_EN_BIT 0x04 | ||
| 86 | #define EN_PERCK_BIT 0x04 | ||
| 87 | |||
| 88 | #define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7 | ||
| 89 | #define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5 | ||
| 90 | #define OMAP1510_IDLE_LOOP_REQUEST 0x0c00 | ||
| 91 | #define OMAP1510_IDLE_CLOCK_DOMAINS 0x2 | ||
| 92 | |||
| 93 | /* Both big sleep and deep sleep use same values. Difference is in ULPD. */ | ||
| 94 | #define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7 | ||
| 95 | #define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7 | ||
| 96 | #define OMAP1610_IDLECT3_VAL 0x3f | ||
| 97 | #define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c | ||
| 98 | #define OMAP1610_IDLECT3 0xfffece24 | ||
| 99 | #define OMAP1610_IDLE_LOOP_REQUEST 0x0400 | ||
| 100 | |||
| 101 | #define OMAP730_IDLECT1_SLEEP_VAL 0x16c7 | ||
| 102 | #define OMAP730_IDLECT2_SLEEP_VAL 0x09c7 | ||
| 103 | #define OMAP730_IDLECT3_VAL 0x3f | ||
| 104 | #define OMAP730_IDLECT3 0xfffece24 | ||
| 105 | #define OMAP730_IDLE_LOOP_REQUEST 0x0C00 | ||
| 106 | |||
| 107 | #if !defined(CONFIG_ARCH_OMAP730) && \ | ||
| 108 | !defined(CONFIG_ARCH_OMAP15XX) && \ | ||
| 109 | !defined(CONFIG_ARCH_OMAP16XX) && \ | ||
| 110 | !defined(CONFIG_ARCH_OMAP24XX) | ||
| 111 | #error "Power management for this processor not implemented yet" | ||
| 112 | #endif | ||
| 113 | |||
| 114 | #ifndef __ASSEMBLER__ | ||
| 115 | |||
| 116 | #include <linux/clk.h> | ||
| 117 | |||
| 118 | extern void prevent_idle_sleep(void); | ||
| 119 | extern void allow_idle_sleep(void); | ||
| 120 | |||
| 121 | /** | ||
| 122 | * clk_deny_idle - Prevents the clock from being idled during MPU idle | ||
| 123 | * @clk: clock signal handle | ||
| 124 | */ | ||
| 125 | void clk_deny_idle(struct clk *clk); | ||
| 126 | |||
| 127 | /** | ||
| 128 | * clk_allow_idle - Counters previous clk_deny_idle | ||
| 129 | * @clk: clock signal handle | ||
| 130 | */ | ||
| 131 | void clk_deny_idle(struct clk *clk); | ||
| 132 | |||
| 133 | extern void omap_pm_idle(void); | ||
| 134 | extern void omap_pm_suspend(void); | ||
| 135 | extern void omap730_cpu_suspend(unsigned short, unsigned short); | ||
| 136 | extern void omap1510_cpu_suspend(unsigned short, unsigned short); | ||
| 137 | extern void omap1610_cpu_suspend(unsigned short, unsigned short); | ||
| 138 | extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision); | ||
| 139 | extern void omap730_idle_loop_suspend(void); | ||
| 140 | extern void omap1510_idle_loop_suspend(void); | ||
| 141 | extern void omap1610_idle_loop_suspend(void); | ||
| 142 | extern void omap24xx_idle_loop_suspend(void); | ||
| 143 | |||
| 144 | extern unsigned int omap730_cpu_suspend_sz; | ||
| 145 | extern unsigned int omap1510_cpu_suspend_sz; | ||
| 146 | extern unsigned int omap1610_cpu_suspend_sz; | ||
| 147 | extern unsigned int omap24xx_cpu_suspend_sz; | ||
| 148 | extern unsigned int omap730_idle_loop_suspend_sz; | ||
| 149 | extern unsigned int omap1510_idle_loop_suspend_sz; | ||
| 150 | extern unsigned int omap1610_idle_loop_suspend_sz; | ||
| 151 | extern unsigned int omap24xx_idle_loop_suspend_sz; | ||
| 152 | |||
| 153 | #ifdef CONFIG_OMAP_SERIAL_WAKE | ||
| 154 | extern void omap_serial_wake_trigger(int enable); | ||
| 155 | #else | ||
| 156 | #define omap_serial_wakeup_init() {} | ||
| 157 | #define omap_serial_wake_trigger(x) {} | ||
| 158 | #endif /* CONFIG_OMAP_SERIAL_WAKE */ | ||
| 159 | |||
| 160 | #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x) | ||
| 161 | #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x)) | ||
| 162 | #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] | ||
| 163 | |||
| 164 | #define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x) | ||
| 165 | #define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x)) | ||
| 166 | #define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] | ||
| 167 | |||
| 168 | #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x) | ||
| 169 | #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) | ||
| 170 | #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] | ||
| 171 | |||
| 172 | #define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x) | ||
| 173 | #define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x)) | ||
| 174 | #define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] | ||
| 175 | |||
| 176 | #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) | ||
| 177 | #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) | ||
| 178 | #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] | ||
| 179 | |||
| 180 | #define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x) | ||
| 181 | #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x)) | ||
| 182 | #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] | ||
| 183 | |||
| 184 | #define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x | ||
| 185 | #define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] | ||
| 186 | #define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] | ||
| 187 | |||
| 188 | /* | ||
| 189 | * List of global OMAP registers to preserve. | ||
| 190 | * More ones like CP and general purpose register values are preserved | ||
| 191 | * with the stack pointer in sleep.S. | ||
| 192 | */ | ||
| 193 | |||
| 194 | enum arm_save_state { | ||
| 195 | ARM_SLEEP_SAVE_START = 0, | ||
| 196 | /* | ||
| 197 | * MPU control registers 32 bits | ||
| 198 | */ | ||
| 199 | ARM_SLEEP_SAVE_ARM_CKCTL, | ||
| 200 | ARM_SLEEP_SAVE_ARM_IDLECT1, | ||
| 201 | ARM_SLEEP_SAVE_ARM_IDLECT2, | ||
| 202 | ARM_SLEEP_SAVE_ARM_IDLECT3, | ||
| 203 | ARM_SLEEP_SAVE_ARM_EWUPCT, | ||
| 204 | ARM_SLEEP_SAVE_ARM_RSTCT1, | ||
| 205 | ARM_SLEEP_SAVE_ARM_RSTCT2, | ||
| 206 | ARM_SLEEP_SAVE_ARM_SYSST, | ||
| 207 | ARM_SLEEP_SAVE_SIZE | ||
| 208 | }; | ||
| 209 | |||
| 210 | enum dsp_save_state { | ||
| 211 | DSP_SLEEP_SAVE_START = 0, | ||
| 212 | /* | ||
| 213 | * DSP registers 16 bits | ||
| 214 | */ | ||
| 215 | DSP_SLEEP_SAVE_DSP_IDLECT2, | ||
| 216 | DSP_SLEEP_SAVE_SIZE | ||
| 217 | }; | ||
| 218 | |||
| 219 | enum ulpd_save_state { | ||
| 220 | ULPD_SLEEP_SAVE_START = 0, | ||
| 221 | /* | ||
| 222 | * ULPD registers 16 bits | ||
| 223 | */ | ||
| 224 | ULPD_SLEEP_SAVE_ULPD_IT_STATUS, | ||
| 225 | ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL, | ||
| 226 | ULPD_SLEEP_SAVE_ULPD_SOFT_REQ, | ||
| 227 | ULPD_SLEEP_SAVE_ULPD_STATUS_REQ, | ||
| 228 | ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL, | ||
| 229 | ULPD_SLEEP_SAVE_ULPD_POWER_CTRL, | ||
| 230 | ULPD_SLEEP_SAVE_SIZE | ||
| 231 | }; | ||
| 232 | |||
| 233 | enum mpui1510_save_state { | ||
| 234 | MPUI1510_SLEEP_SAVE_START = 0, | ||
| 235 | /* | ||
| 236 | * MPUI registers 32 bits | ||
| 237 | */ | ||
| 238 | MPUI1510_SLEEP_SAVE_MPUI_CTRL, | ||
| 239 | MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, | ||
| 240 | MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG, | ||
| 241 | MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS, | ||
| 242 | MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, | ||
| 243 | MPUI1510_SLEEP_SAVE_EMIFS_CONFIG, | ||
| 244 | MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR, | ||
| 245 | MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR, | ||
| 246 | #if defined(CONFIG_ARCH_OMAP15XX) | ||
| 247 | MPUI1510_SLEEP_SAVE_SIZE | ||
| 248 | #else | ||
| 249 | MPUI1510_SLEEP_SAVE_SIZE = 0 | ||
| 250 | #endif | ||
| 251 | }; | ||
| 252 | |||
| 253 | enum mpui730_save_state { | ||
| 254 | MPUI730_SLEEP_SAVE_START = 0, | ||
| 255 | /* | ||
| 256 | * MPUI registers 32 bits | ||
| 257 | */ | ||
| 258 | MPUI730_SLEEP_SAVE_MPUI_CTRL, | ||
| 259 | MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, | ||
| 260 | MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG, | ||
| 261 | MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS, | ||
| 262 | MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, | ||
| 263 | MPUI730_SLEEP_SAVE_EMIFS_CONFIG, | ||
| 264 | MPUI730_SLEEP_SAVE_OMAP_IH1_MIR, | ||
| 265 | MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR, | ||
| 266 | MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR, | ||
| 267 | #if defined(CONFIG_ARCH_OMAP730) | ||
| 268 | MPUI730_SLEEP_SAVE_SIZE | ||
| 269 | #else | ||
| 270 | MPUI730_SLEEP_SAVE_SIZE = 0 | ||
| 271 | #endif | ||
| 272 | }; | ||
| 273 | |||
| 274 | enum mpui1610_save_state { | ||
| 275 | MPUI1610_SLEEP_SAVE_START = 0, | ||
| 276 | /* | ||
| 277 | * MPUI registers 32 bits | ||
| 278 | */ | ||
| 279 | MPUI1610_SLEEP_SAVE_MPUI_CTRL, | ||
| 280 | MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, | ||
| 281 | MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG, | ||
| 282 | MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS, | ||
| 283 | MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, | ||
| 284 | MPUI1610_SLEEP_SAVE_EMIFS_CONFIG, | ||
| 285 | MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR, | ||
| 286 | MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR, | ||
| 287 | MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR, | ||
| 288 | MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR, | ||
| 289 | MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR, | ||
| 290 | #if defined(CONFIG_ARCH_OMAP16XX) | ||
| 291 | MPUI1610_SLEEP_SAVE_SIZE | ||
| 292 | #else | ||
| 293 | MPUI1610_SLEEP_SAVE_SIZE = 0 | ||
| 294 | #endif | ||
| 295 | }; | ||
| 296 | |||
| 297 | enum omap24xx_save_state { | ||
| 298 | OMAP24XX_SLEEP_SAVE_START = 0, | ||
| 299 | OMAP24XX_SLEEP_SAVE_INTC_MIR0, | ||
| 300 | OMAP24XX_SLEEP_SAVE_INTC_MIR1, | ||
| 301 | OMAP24XX_SLEEP_SAVE_INTC_MIR2, | ||
| 302 | |||
| 303 | OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU, | ||
| 304 | OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE, | ||
| 305 | OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX, | ||
| 306 | OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP, | ||
| 307 | OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM, | ||
| 308 | |||
| 309 | OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU, | ||
| 310 | OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE, | ||
| 311 | OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX, | ||
| 312 | OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP, | ||
| 313 | OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM, | ||
| 314 | |||
| 315 | OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE, | ||
| 316 | OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE, | ||
| 317 | OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE, | ||
| 318 | OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE, | ||
| 319 | OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX, | ||
| 320 | OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP, | ||
| 321 | OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN, | ||
| 322 | OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP, | ||
| 323 | OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM, | ||
| 324 | |||
| 325 | OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE, | ||
| 326 | OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE, | ||
| 327 | OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE, | ||
| 328 | OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE, | ||
| 329 | OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP, | ||
| 330 | OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL, | ||
| 331 | OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP, | ||
| 332 | OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM, | ||
| 333 | |||
| 334 | OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE, | ||
| 335 | OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE, | ||
| 336 | OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE, | ||
| 337 | OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE, | ||
| 338 | OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE, | ||
| 339 | OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE, | ||
| 340 | OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1, | ||
| 341 | OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1, | ||
| 342 | OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1, | ||
| 343 | OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1, | ||
| 344 | OMAP24XX_SLEEP_SAVE_GPIO3_OE, | ||
| 345 | OMAP24XX_SLEEP_SAVE_GPIO4_OE, | ||
| 346 | OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT, | ||
| 347 | OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT, | ||
| 348 | OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2, | ||
| 349 | OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX, | ||
| 350 | OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX, | ||
| 351 | OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0, | ||
| 352 | OMAP24XX_SLEEP_SAVE_SIZE | ||
| 353 | }; | ||
| 354 | |||
| 355 | #endif /* ASSEMBLER */ | ||
| 356 | #endif /* __ASM_ARCH_OMAP_PM_H */ | ||
diff --git a/include/asm-arm/arch-omap/prcm.h b/include/asm-arm/arch-omap/prcm.h deleted file mode 100644 index 7bcaf94bde9f..000000000000 --- a/include/asm-arm/arch-omap/prcm.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/prcm.h | ||
| 3 | * | ||
| 4 | * Access definations for use in OMAP24XX clock and power management | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005 Texas Instruments, Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __ASM_ARM_ARCH_DPM_PRCM_H | ||
| 24 | #define __ASM_ARM_ARCH_DPM_PRCM_H | ||
| 25 | |||
| 26 | u32 omap_prcm_get_reset_sources(void); | ||
| 27 | |||
| 28 | #endif | ||
| 29 | |||
| 30 | |||
| 31 | |||
| 32 | |||
| 33 | |||
diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h deleted file mode 100644 index 673b3965befc..000000000000 --- a/include/asm-arm/arch-omap/sdrc.h +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | #ifndef ____ASM_ARCH_SDRC_H | ||
| 2 | #define ____ASM_ARCH_SDRC_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP2/3 SDRC/SMS register definitions | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <asm/arch/io.h> | ||
| 18 | |||
| 19 | /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ | ||
| 20 | |||
| 21 | #define SDRC_SYSCONFIG 0x010 | ||
| 22 | #define SDRC_DLLA_CTRL 0x060 | ||
| 23 | #define SDRC_DLLA_STATUS 0x064 | ||
| 24 | #define SDRC_DLLB_CTRL 0x068 | ||
| 25 | #define SDRC_DLLB_STATUS 0x06C | ||
| 26 | #define SDRC_POWER 0x070 | ||
| 27 | #define SDRC_MR_0 0x084 | ||
| 28 | #define SDRC_RFR_CTRL_0 0x0a4 | ||
| 29 | |||
| 30 | /* | ||
| 31 | * These values represent the number of memory clock cycles between | ||
| 32 | * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 | ||
| 33 | * rows per device, and include a subtraction of a 50 cycle window in the | ||
| 34 | * event that the autorefresh command is delayed due to other SDRC activity. | ||
| 35 | * The '| 1' sets the ARE field to send one autorefresh when the autorefresh | ||
| 36 | * counter reaches 0. | ||
| 37 | * | ||
| 38 | * These represent optimal values for common parts, it won't work for all. | ||
| 39 | * As long as you scale down, most parameters are still work, they just | ||
| 40 | * become sub-optimal. The RFR value goes in the opposite direction. If you | ||
| 41 | * don't adjust it down as your clock period increases the refresh interval | ||
| 42 | * will not be met. Setting all parameters for complete worst case may work, | ||
| 43 | * but may cut memory performance by 2x. Due to errata the DLLs need to be | ||
| 44 | * unlocked and their value needs run time calibration. A dynamic call is | ||
| 45 | * need for that as no single right value exists acorss production samples. | ||
| 46 | * | ||
| 47 | * Only the FULL speed values are given. Current code is such that rate | ||
| 48 | * changes must be made at DPLLoutx2. The actual value adjustment for low | ||
| 49 | * frequency operation will be handled by omap_set_performance() | ||
| 50 | * | ||
| 51 | * By having the boot loader boot up in the fastest L4 speed available likely | ||
| 52 | * will result in something which you can switch between. | ||
| 53 | */ | ||
| 54 | #define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1) | ||
| 55 | #define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) | ||
| 56 | #define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) | ||
| 57 | #define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ | ||
| 58 | #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ | ||
| 59 | |||
| 60 | |||
| 61 | /* | ||
| 62 | * SMS register access | ||
| 63 | */ | ||
| 64 | |||
| 65 | |||
| 66 | #define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) | ||
| 67 | #define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) | ||
| 68 | #define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) | ||
| 69 | |||
| 70 | /* SMS register offsets - read/write with sms_{read,write}_reg() */ | ||
| 71 | |||
| 72 | #define SMS_SYSCONFIG 0x010 | ||
| 73 | /* REVISIT: fill in other SMS registers here */ | ||
| 74 | |||
| 75 | #endif | ||
diff --git a/include/asm-arm/arch-omap/serial.h b/include/asm-arm/arch-omap/serial.h deleted file mode 100644 index 79a5297af9fc..000000000000 --- a/include/asm-arm/arch-omap/serial.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/serial.h | ||
| 3 | * | ||
| 4 | * This program is distributed in the hope that it will be useful, | ||
| 5 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 6 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 7 | * GNU General Public License for more details. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ASM_ARCH_SERIAL_H | ||
| 11 | #define __ASM_ARCH_SERIAL_H | ||
| 12 | |||
| 13 | #if defined(CONFIG_ARCH_OMAP1) | ||
| 14 | /* OMAP1 serial ports */ | ||
| 15 | #define OMAP_UART1_BASE 0xfffb0000 | ||
| 16 | #define OMAP_UART2_BASE 0xfffb0800 | ||
| 17 | #define OMAP_UART3_BASE 0xfffb9800 | ||
| 18 | #elif defined(CONFIG_ARCH_OMAP2) | ||
| 19 | /* OMAP2 serial ports */ | ||
| 20 | #define OMAP_UART1_BASE 0x4806a000 | ||
| 21 | #define OMAP_UART2_BASE 0x4806c000 | ||
| 22 | #define OMAP_UART3_BASE 0x4806e000 | ||
| 23 | #endif | ||
| 24 | |||
| 25 | #define OMAP_MAX_NR_PORTS 3 | ||
| 26 | #define OMAP1510_BASE_BAUD (12000000/16) | ||
| 27 | #define OMAP16XX_BASE_BAUD (48000000/16) | ||
| 28 | |||
| 29 | #define is_omap_port(p) ({int __ret = 0; \ | ||
| 30 | if (p == IO_ADDRESS(OMAP_UART1_BASE) || \ | ||
| 31 | p == IO_ADDRESS(OMAP_UART2_BASE) || \ | ||
| 32 | p == IO_ADDRESS(OMAP_UART3_BASE)) \ | ||
| 33 | __ret = 1; \ | ||
| 34 | __ret; \ | ||
| 35 | }) | ||
| 36 | |||
| 37 | #endif | ||
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h deleted file mode 100644 index be59f4a9828b..000000000000 --- a/include/asm-arm/arch-omap/sram.h +++ /dev/null | |||
| @@ -1,56 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/sram.h | ||
| 3 | * | ||
| 4 | * Interface for functions that need to be run in internal SRAM | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ARCH_ARM_OMAP_SRAM_H | ||
| 12 | #define __ARCH_ARM_OMAP_SRAM_H | ||
| 13 | |||
| 14 | extern int __init omap_sram_init(void); | ||
| 15 | extern void * omap_sram_push(void * start, unsigned long size); | ||
| 16 | extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); | ||
| 17 | |||
| 18 | extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | ||
| 19 | u32 base_cs, u32 force_unlock); | ||
| 20 | extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, | ||
| 21 | u32 mem_type); | ||
| 22 | extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); | ||
| 23 | |||
| 24 | /* Do not use these */ | ||
| 25 | extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); | ||
| 26 | extern unsigned long omap1_sram_reprogram_clock_sz; | ||
| 27 | |||
| 28 | extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl); | ||
| 29 | extern unsigned long omap24xx_sram_reprogram_clock_sz; | ||
| 30 | |||
| 31 | extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | ||
| 32 | u32 base_cs, u32 force_unlock); | ||
| 33 | extern unsigned long omap242x_sram_ddr_init_sz; | ||
| 34 | |||
| 35 | extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, | ||
| 36 | int bypass); | ||
| 37 | extern unsigned long omap242x_sram_set_prcm_sz; | ||
| 38 | |||
| 39 | extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, | ||
| 40 | u32 mem_type); | ||
| 41 | extern unsigned long omap242x_sram_reprogram_sdrc_sz; | ||
| 42 | |||
| 43 | |||
| 44 | extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | ||
| 45 | u32 base_cs, u32 force_unlock); | ||
| 46 | extern unsigned long omap243x_sram_ddr_init_sz; | ||
| 47 | |||
| 48 | extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, | ||
| 49 | int bypass); | ||
| 50 | extern unsigned long omap243x_sram_set_prcm_sz; | ||
| 51 | |||
| 52 | extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, | ||
| 53 | u32 mem_type); | ||
| 54 | extern unsigned long omap243x_sram_reprogram_sdrc_sz; | ||
| 55 | |||
| 56 | #endif | ||
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h deleted file mode 100644 index 176d9d6c258e..000000000000 --- a/include/asm-arm/arch-omap/system.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copied from linux/include/asm-arm/arch-sa1100/system.h | ||
| 3 | * Copyright (c) 1999 Nicolas Pitre <nico@cam.org> | ||
| 4 | */ | ||
| 5 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 6 | #define __ASM_ARCH_SYSTEM_H | ||
| 7 | #include <linux/clk.h> | ||
| 8 | |||
| 9 | #include <asm/mach-types.h> | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | |||
| 12 | #ifndef CONFIG_MACH_VOICEBLUE | ||
| 13 | #define voiceblue_reset() do {} while (0) | ||
| 14 | #endif | ||
| 15 | |||
| 16 | extern void omap_prcm_arch_reset(char mode); | ||
| 17 | |||
| 18 | static inline void arch_idle(void) | ||
| 19 | { | ||
| 20 | cpu_do_idle(); | ||
| 21 | } | ||
| 22 | |||
| 23 | static inline void omap1_arch_reset(char mode) | ||
| 24 | { | ||
| 25 | /* | ||
| 26 | * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 | ||
| 27 | * "Global Software Reset Affects Traffic Controller Frequency". | ||
| 28 | */ | ||
| 29 | if (cpu_is_omap5912()) { | ||
| 30 | omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), | ||
| 31 | DPLL_CTL); | ||
| 32 | omap_writew(0x8, ARM_RSTCT1); | ||
| 33 | } | ||
| 34 | |||
| 35 | if (machine_is_voiceblue()) | ||
| 36 | voiceblue_reset(); | ||
| 37 | else | ||
| 38 | omap_writew(1, ARM_RSTCT1); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline void arch_reset(char mode) | ||
| 42 | { | ||
| 43 | if (!cpu_is_omap24xx()) | ||
| 44 | omap1_arch_reset(mode); | ||
| 45 | else | ||
| 46 | omap_prcm_arch_reset(mode); | ||
| 47 | } | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h deleted file mode 100644 index 65a9c82d3bf7..000000000000 --- a/include/asm-arm/arch-omap/tc.h +++ /dev/null | |||
| @@ -1,106 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/tc.h | ||
| 3 | * | ||
| 4 | * OMAP Traffic Controller | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004 Nokia Corporation | ||
| 7 | * Author: Imre Deak <imre.deak@nokia.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, but | ||
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 17 | * General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License along | ||
| 20 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 21 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef __ASM_ARCH_TC_H | ||
| 25 | #define __ASM_ARCH_TC_H | ||
| 26 | |||
| 27 | #define TCMIF_BASE 0xfffecc00 | ||
| 28 | #define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00) | ||
| 29 | #define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04) | ||
| 30 | #define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08) | ||
| 31 | #define EMIFS_CONFIG (TCMIF_BASE + 0x0c) | ||
| 32 | #define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) | ||
| 33 | #define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) | ||
| 34 | #define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) | ||
| 35 | #define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) | ||
| 36 | #define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) | ||
| 37 | #define EMIFF_MRS (TCMIF_BASE + 0x24) | ||
| 38 | #define TC_TIMEOUT1 (TCMIF_BASE + 0x28) | ||
| 39 | #define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) | ||
| 40 | #define TC_TIMEOUT3 (TCMIF_BASE + 0x30) | ||
| 41 | #define TC_ENDIANISM (TCMIF_BASE + 0x34) | ||
| 42 | #define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) | ||
| 43 | #define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) | ||
| 44 | #define EMIFS_ACS0 (TCMIF_BASE + 0x50) | ||
| 45 | #define EMIFS_ACS1 (TCMIF_BASE + 0x54) | ||
| 46 | #define EMIFS_ACS2 (TCMIF_BASE + 0x58) | ||
| 47 | #define EMIFS_ACS3 (TCMIF_BASE + 0x5c) | ||
| 48 | #define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0) | ||
| 49 | |||
| 50 | /* external EMIFS chipselect regions */ | ||
| 51 | #define OMAP_CS0_PHYS 0x00000000 | ||
| 52 | #define OMAP_CS0_SIZE SZ_64M | ||
| 53 | |||
| 54 | #define OMAP_CS1_PHYS 0x04000000 | ||
| 55 | #define OMAP_CS1_SIZE SZ_64M | ||
| 56 | |||
| 57 | #define OMAP_CS1A_PHYS OMAP_CS1_PHYS | ||
| 58 | #define OMAP_CS1A_SIZE SZ_32M | ||
| 59 | |||
| 60 | #define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE) | ||
| 61 | #define OMAP_CS1B_SIZE SZ_32M | ||
| 62 | |||
| 63 | #define OMAP_CS2_PHYS 0x08000000 | ||
| 64 | #define OMAP_CS2_SIZE SZ_64M | ||
| 65 | |||
| 66 | #define OMAP_CS2A_PHYS OMAP_CS2_PHYS | ||
| 67 | #define OMAP_CS2A_SIZE SZ_32M | ||
| 68 | |||
| 69 | #define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE) | ||
| 70 | #define OMAP_CS2B_SIZE SZ_32M | ||
| 71 | |||
| 72 | #define OMAP_CS3_PHYS 0x0c000000 | ||
| 73 | #define OMAP_CS3_SIZE SZ_64M | ||
| 74 | |||
| 75 | #ifndef __ASSEMBLER__ | ||
| 76 | |||
| 77 | /* EMIF Slow Interface Configuration Register */ | ||
| 78 | #define OMAP_EMIFS_CONFIG_FR (1 << 4) | ||
| 79 | #define OMAP_EMIFS_CONFIG_PDE (1 << 3) | ||
| 80 | #define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) | ||
| 81 | #define OMAP_EMIFS_CONFIG_BM (1 << 1) | ||
| 82 | #define OMAP_EMIFS_CONFIG_WP (1 << 0) | ||
| 83 | |||
| 84 | #define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n))) | ||
| 85 | #define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n))) | ||
| 86 | |||
| 87 | /* Almost all documentation for chip and board memory maps assumes | ||
| 88 | * BM is clear. Most devel boards have a switch to control booting | ||
| 89 | * from NOR flash (using external chipselect 3) rather than mask ROM, | ||
| 90 | * which uses BM to interchange the physical CS0 and CS3 addresses. | ||
| 91 | */ | ||
| 92 | static inline u32 omap_cs0_phys(void) | ||
| 93 | { | ||
| 94 | return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) | ||
| 95 | ? OMAP_CS3_PHYS : 0; | ||
| 96 | } | ||
| 97 | |||
| 98 | static inline u32 omap_cs3_phys(void) | ||
| 99 | { | ||
| 100 | return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) | ||
| 101 | ? 0 : OMAP_CS3_PHYS; | ||
| 102 | } | ||
| 103 | |||
| 104 | #endif /* __ASSEMBLER__ */ | ||
| 105 | |||
| 106 | #endif /* __ASM_ARCH_TC_H */ | ||
diff --git a/include/asm-arm/arch-omap/timex.h b/include/asm-arm/arch-omap/timex.h deleted file mode 100644 index 21f2e367185a..000000000000 --- a/include/asm-arm/arch-omap/timex.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 RidgeRun, Inc. | ||
| 5 | * Author: Greg Lonnon <glonnon@ridgerun.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License along | ||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 26 | */ | ||
| 27 | |||
| 28 | #if !defined(__ASM_ARCH_OMAP_TIMEX_H) | ||
| 29 | #define __ASM_ARCH_OMAP_TIMEX_H | ||
| 30 | |||
| 31 | /* | ||
| 32 | * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer, | ||
| 33 | * and that's why the CLOCK_TICK_RATE is not 32768. | ||
| 34 | */ | ||
| 35 | #ifdef CONFIG_OMAP_32K_TIMER | ||
| 36 | #define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ) | ||
| 37 | #else | ||
| 38 | #define CLOCK_TICK_RATE (HZ * 100000UL) | ||
| 39 | #endif | ||
| 40 | |||
| 41 | #endif /* __ASM_ARCH_OMAP_TIMEX_H */ | ||
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h deleted file mode 100644 index aca0adfef1b8..000000000000 --- a/include/asm-arm/arch-omap/uncompress.h +++ /dev/null | |||
| @@ -1,83 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/uncompress.h | ||
| 3 | * | ||
| 4 | * Serial port stubs for kernel decompress status messages | ||
| 5 | * | ||
| 6 | * Initially based on: | ||
| 7 | * linux-2.4.15-rmk1-dsplinux1.6/include/asm-arm/arch-omap1510/uncompress.h | ||
| 8 | * Copyright (C) 2000 RidgeRun, Inc. | ||
| 9 | * Author: Greg Lonnon <glonnon@ridgerun.com> | ||
| 10 | * | ||
| 11 | * Rewritten by: | ||
| 12 | * Author: <source@mvista.com> | ||
| 13 | * 2004 (c) MontaVista Software, Inc. | ||
| 14 | * | ||
| 15 | * This file is licensed under the terms of the GNU General Public License | ||
| 16 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 17 | * kind, whether express or implied. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/types.h> | ||
| 21 | #include <linux/serial_reg.h> | ||
| 22 | #include <asm/arch/serial.h> | ||
| 23 | |||
| 24 | unsigned int system_rev; | ||
| 25 | |||
| 26 | #define UART_OMAP_MDR1 0x08 /* mode definition register */ | ||
| 27 | #define OMAP_ID_730 0x355F | ||
| 28 | #define ID_MASK 0x7fff | ||
| 29 | #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) | ||
| 30 | #define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK | ||
| 31 | |||
| 32 | static void putc(int c) | ||
| 33 | { | ||
| 34 | volatile u8 * uart = 0; | ||
| 35 | int shift = 2; | ||
| 36 | |||
| 37 | #ifdef CONFIG_MACH_OMAP_PALMTE | ||
| 38 | return; | ||
| 39 | #endif | ||
| 40 | |||
| 41 | #ifdef CONFIG_ARCH_OMAP | ||
| 42 | #ifdef CONFIG_OMAP_LL_DEBUG_UART3 | ||
| 43 | uart = (volatile u8 *)(OMAP_UART3_BASE); | ||
| 44 | #elif defined(CONFIG_OMAP_LL_DEBUG_UART2) | ||
| 45 | uart = (volatile u8 *)(OMAP_UART2_BASE); | ||
| 46 | #else | ||
| 47 | uart = (volatile u8 *)(OMAP_UART1_BASE); | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 51 | /* Determine which serial port to use */ | ||
| 52 | do { | ||
| 53 | /* MMU is not on, so cpu_is_omapXXXX() won't work here */ | ||
| 54 | unsigned int omap_id = omap_get_id(); | ||
| 55 | |||
| 56 | if (omap_id == OMAP_ID_730) | ||
| 57 | shift = 0; | ||
| 58 | |||
| 59 | if (check_port(uart, shift)) | ||
| 60 | break; | ||
| 61 | /* Silent boot if no serial ports are enabled. */ | ||
| 62 | return; | ||
| 63 | } while (0); | ||
| 64 | #endif /* CONFIG_ARCH_OMAP1 */ | ||
| 65 | #endif | ||
| 66 | |||
| 67 | /* | ||
| 68 | * Now, xmit each character | ||
| 69 | */ | ||
| 70 | while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) | ||
| 71 | barrier(); | ||
| 72 | uart[UART_TX << shift] = c; | ||
| 73 | } | ||
| 74 | |||
| 75 | static inline void flush(void) | ||
| 76 | { | ||
| 77 | } | ||
| 78 | |||
| 79 | /* | ||
| 80 | * nothing to do | ||
| 81 | */ | ||
| 82 | #define arch_decomp_setup() | ||
| 83 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h deleted file mode 100644 index ddf1861e6df9..000000000000 --- a/include/asm-arm/arch-omap/usb.h +++ /dev/null | |||
| @@ -1,141 +0,0 @@ | |||
| 1 | // include/asm-arm/mach-omap/usb.h | ||
| 2 | |||
| 3 | #ifndef __ASM_ARCH_OMAP_USB_H | ||
| 4 | #define __ASM_ARCH_OMAP_USB_H | ||
| 5 | |||
| 6 | #include <asm/arch/board.h> | ||
| 7 | |||
| 8 | /*-------------------------------------------------------------------------*/ | ||
| 9 | |||
| 10 | #define OMAP1_OTG_BASE 0xfffb0400 | ||
| 11 | #define OMAP1_UDC_BASE 0xfffb4000 | ||
| 12 | #define OMAP1_OHCI_BASE 0xfffba000 | ||
| 13 | |||
| 14 | #define OMAP2_OHCI_BASE 0x4805e000 | ||
| 15 | #define OMAP2_UDC_BASE 0x4805e200 | ||
| 16 | #define OMAP2_OTG_BASE 0x4805e300 | ||
| 17 | |||
| 18 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 19 | |||
| 20 | #define OTG_BASE OMAP1_OTG_BASE | ||
| 21 | #define UDC_BASE OMAP1_UDC_BASE | ||
| 22 | #define OMAP_OHCI_BASE OMAP1_OHCI_BASE | ||
| 23 | |||
| 24 | #else | ||
| 25 | |||
| 26 | #define OTG_BASE OMAP2_OTG_BASE | ||
| 27 | #define UDC_BASE OMAP2_UDC_BASE | ||
| 28 | #define OMAP_OHCI_BASE OMAP2_OHCI_BASE | ||
| 29 | |||
| 30 | #endif | ||
| 31 | |||
| 32 | /*-------------------------------------------------------------------------*/ | ||
| 33 | |||
| 34 | /* | ||
| 35 | * OTG and transceiver registers, for OMAPs starting with ARM926 | ||
| 36 | */ | ||
| 37 | #define OTG_REV (OTG_BASE + 0x00) | ||
| 38 | #define OTG_SYSCON_1 (OTG_BASE + 0x04) | ||
| 39 | # define USB2_TRX_MODE(w) (((w)>>24)&0x07) | ||
| 40 | # define USB1_TRX_MODE(w) (((w)>>20)&0x07) | ||
| 41 | # define USB0_TRX_MODE(w) (((w)>>16)&0x07) | ||
| 42 | # define OTG_IDLE_EN (1 << 15) | ||
| 43 | # define HST_IDLE_EN (1 << 14) | ||
| 44 | # define DEV_IDLE_EN (1 << 13) | ||
| 45 | # define OTG_RESET_DONE (1 << 2) | ||
| 46 | # define OTG_SOFT_RESET (1 << 1) | ||
| 47 | #define OTG_SYSCON_2 (OTG_BASE + 0x08) | ||
| 48 | # define OTG_EN (1 << 31) | ||
| 49 | # define USBX_SYNCHRO (1 << 30) | ||
| 50 | # define OTG_MST16 (1 << 29) | ||
| 51 | # define SRP_GPDATA (1 << 28) | ||
| 52 | # define SRP_GPDVBUS (1 << 27) | ||
| 53 | # define SRP_GPUVBUS(w) (((w)>>24)&0x07) | ||
| 54 | # define A_WAIT_VRISE(w) (((w)>>20)&0x07) | ||
| 55 | # define B_ASE_BRST(w) (((w)>>16)&0x07) | ||
| 56 | # define SRP_DPW (1 << 14) | ||
| 57 | # define SRP_DATA (1 << 13) | ||
| 58 | # define SRP_VBUS (1 << 12) | ||
| 59 | # define OTG_PADEN (1 << 10) | ||
| 60 | # define HMC_PADEN (1 << 9) | ||
| 61 | # define UHOST_EN (1 << 8) | ||
| 62 | # define HMC_TLLSPEED (1 << 7) | ||
| 63 | # define HMC_TLLATTACH (1 << 6) | ||
| 64 | # define OTG_HMC(w) (((w)>>0)&0x3f) | ||
| 65 | #define OTG_CTRL (OTG_BASE + 0x0c) | ||
| 66 | # define OTG_USB2_EN (1 << 29) | ||
| 67 | # define OTG_USB2_DP (1 << 28) | ||
| 68 | # define OTG_USB2_DM (1 << 27) | ||
| 69 | # define OTG_USB1_EN (1 << 26) | ||
| 70 | # define OTG_USB1_DP (1 << 25) | ||
| 71 | # define OTG_USB1_DM (1 << 24) | ||
| 72 | # define OTG_USB0_EN (1 << 23) | ||
| 73 | # define OTG_USB0_DP (1 << 22) | ||
| 74 | # define OTG_USB0_DM (1 << 21) | ||
| 75 | # define OTG_ASESSVLD (1 << 20) | ||
| 76 | # define OTG_BSESSEND (1 << 19) | ||
| 77 | # define OTG_BSESSVLD (1 << 18) | ||
| 78 | # define OTG_VBUSVLD (1 << 17) | ||
| 79 | # define OTG_ID (1 << 16) | ||
| 80 | # define OTG_DRIVER_SEL (1 << 15) | ||
| 81 | # define OTG_A_SETB_HNPEN (1 << 12) | ||
| 82 | # define OTG_A_BUSREQ (1 << 11) | ||
| 83 | # define OTG_B_HNPEN (1 << 9) | ||
| 84 | # define OTG_B_BUSREQ (1 << 8) | ||
| 85 | # define OTG_BUSDROP (1 << 7) | ||
| 86 | # define OTG_PULLDOWN (1 << 5) | ||
| 87 | # define OTG_PULLUP (1 << 4) | ||
| 88 | # define OTG_DRV_VBUS (1 << 3) | ||
| 89 | # define OTG_PD_VBUS (1 << 2) | ||
| 90 | # define OTG_PU_VBUS (1 << 1) | ||
| 91 | # define OTG_PU_ID (1 << 0) | ||
| 92 | #define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ | ||
| 93 | # define DRIVER_SWITCH (1 << 15) | ||
| 94 | # define A_VBUS_ERR (1 << 13) | ||
| 95 | # define A_REQ_TMROUT (1 << 12) | ||
| 96 | # define A_SRP_DETECT (1 << 11) | ||
| 97 | # define B_HNP_FAIL (1 << 10) | ||
| 98 | # define B_SRP_TMROUT (1 << 9) | ||
| 99 | # define B_SRP_DONE (1 << 8) | ||
| 100 | # define B_SRP_STARTED (1 << 7) | ||
| 101 | # define OPRT_CHG (1 << 0) | ||
| 102 | #define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ | ||
| 103 | // same bits as in IRQ_EN | ||
| 104 | #define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ | ||
| 105 | # define OTGVPD (1 << 14) | ||
| 106 | # define OTGVPU (1 << 13) | ||
| 107 | # define OTGPUID (1 << 12) | ||
| 108 | # define USB2VDR (1 << 10) | ||
| 109 | # define USB2PDEN (1 << 9) | ||
| 110 | # define USB2PUEN (1 << 8) | ||
| 111 | # define USB1VDR (1 << 6) | ||
| 112 | # define USB1PDEN (1 << 5) | ||
| 113 | # define USB1PUEN (1 << 4) | ||
| 114 | # define USB0VDR (1 << 2) | ||
| 115 | # define USB0PDEN (1 << 1) | ||
| 116 | # define USB0PUEN (1 << 0) | ||
| 117 | #define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ | ||
| 118 | #define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ | ||
| 119 | |||
| 120 | /*-------------------------------------------------------------------------*/ | ||
| 121 | |||
| 122 | /* OMAP1 */ | ||
| 123 | #define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) | ||
| 124 | # define CONF_USB2_UNI_R (1 << 8) | ||
| 125 | # define CONF_USB1_UNI_R (1 << 7) | ||
| 126 | # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) | ||
| 127 | # define CONF_USB0_ISOLATE_R (1 << 3) | ||
| 128 | # define CONF_USB_PWRDN_DM_R (1 << 2) | ||
| 129 | # define CONF_USB_PWRDN_DP_R (1 << 1) | ||
| 130 | |||
| 131 | /* OMAP2 */ | ||
| 132 | # define USB_UNIDIR 0x0 | ||
| 133 | # define USB_UNIDIR_TLL 0x1 | ||
| 134 | # define USB_BIDIR 0x2 | ||
| 135 | # define USB_BIDIR_TLL 0x3 | ||
| 136 | # define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2))) | ||
| 137 | # define USBT2TLL5PI (1 << 17) | ||
| 138 | # define USB0PUENACTLOI (1 << 16) | ||
| 139 | # define USBSTANDBYCTRL (1 << 15) | ||
| 140 | |||
| 141 | #endif /* __ASM_ARCH_OMAP_USB_H */ | ||
diff --git a/include/asm-arm/arch-omap/vmalloc.h b/include/asm-arm/arch-omap/vmalloc.h deleted file mode 100644 index 5b8bd8dae8be..000000000000 --- a/include/asm-arm/arch-omap/vmalloc.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-omap/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
| 21 | |||
diff --git a/include/asm-arm/arch-orion5x/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S deleted file mode 100644 index 4f98f3ba2929..000000000000 --- a/include/asm-arm/arch-orion5x/debug-macro.S +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/debug-macro.S | ||
| 3 | * | ||
| 4 | * Debugging macro include header | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/arch/orion5x.h> | ||
| 12 | |||
| 13 | .macro addruart,rx | ||
| 14 | mrc p15, 0, \rx, c1, c0 | ||
| 15 | tst \rx, #1 @ MMU enabled? | ||
| 16 | ldreq \rx, =ORION5X_REGS_PHYS_BASE | ||
| 17 | ldrne \rx, =ORION5X_REGS_VIRT_BASE | ||
| 18 | orr \rx, \rx, #0x00012000 | ||
| 19 | .endm | ||
| 20 | |||
| 21 | #define UART_SHIFT 2 | ||
| 22 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-orion5x/dma.h b/include/asm-arm/arch-orion5x/dma.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/include/asm-arm/arch-orion5x/dma.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | /* empty */ | ||
diff --git a/include/asm-arm/arch-orion5x/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S deleted file mode 100644 index d8ef54c0ee9a..000000000000 --- a/include/asm-arm/arch-orion5x/entry-macro.S +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for Orion platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/arch/orion5x.h> | ||
| 12 | |||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro get_irqnr_preamble, base, tmp | ||
| 20 | ldr \base, =MAIN_IRQ_CAUSE | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 24 | ldr \irqstat, [\base, #0] @ main cause | ||
| 25 | ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask | ||
| 26 | mov \irqnr, #0 @ default irqnr | ||
| 27 | @ find cause bits that are unmasked | ||
| 28 | ands \irqstat, \irqstat, \tmp @ clear Z flag if any | ||
| 29 | clzne \irqnr, \irqstat @ calc irqnr | ||
| 30 | rsbne \irqnr, \irqnr, #31 | ||
| 31 | .endm | ||
diff --git a/include/asm-arm/arch-orion5x/gpio.h b/include/asm-arm/arch-orion5x/gpio.h deleted file mode 100644 index c85e498388b6..000000000000 --- a/include/asm-arm/arch-orion5x/gpio.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/gpio.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | extern int gpio_request(unsigned pin, const char *label); | ||
| 10 | extern void gpio_free(unsigned pin); | ||
| 11 | extern int gpio_direction_input(unsigned pin); | ||
| 12 | extern int gpio_direction_output(unsigned pin, int value); | ||
| 13 | extern int gpio_get_value(unsigned pin); | ||
| 14 | extern void gpio_set_value(unsigned pin, int value); | ||
| 15 | extern void orion5x_gpio_set_blink(unsigned pin, int blink); | ||
| 16 | extern void gpio_display(void); /* debug */ | ||
| 17 | |||
| 18 | static inline int gpio_to_irq(int pin) | ||
| 19 | { | ||
| 20 | return pin + IRQ_ORION5X_GPIO_START; | ||
| 21 | } | ||
| 22 | |||
| 23 | static inline int irq_to_gpio(int irq) | ||
| 24 | { | ||
| 25 | return irq - IRQ_ORION5X_GPIO_START; | ||
| 26 | } | ||
| 27 | |||
| 28 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
diff --git a/include/asm-arm/arch-orion5x/hardware.h b/include/asm-arm/arch-orion5x/hardware.h deleted file mode 100644 index 5d2d8e0b5630..000000000000 --- a/include/asm-arm/arch-orion5x/hardware.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/hardware.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 10 | #define __ASM_ARCH_HARDWARE_H | ||
| 11 | |||
| 12 | #include "orion5x.h" | ||
| 13 | |||
| 14 | #define pcibios_assign_all_busses() 1 | ||
| 15 | |||
| 16 | #define PCIBIOS_MIN_IO 0x00001000 | ||
| 17 | #define PCIBIOS_MIN_MEM 0x01000000 | ||
| 18 | #define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE | ||
| 19 | |||
| 20 | |||
| 21 | #endif | ||
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h deleted file mode 100644 index 59f1bc96a23b..000000000000 --- a/include/asm-arm/arch-orion5x/io.h +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/io.h | ||
| 3 | * | ||
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_IO_H | ||
| 12 | #define __ASM_ARCH_IO_H | ||
| 13 | |||
| 14 | #include "orion5x.h" | ||
| 15 | |||
| 16 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 17 | |||
| 18 | static inline void __iomem * | ||
| 19 | __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) | ||
| 20 | { | ||
| 21 | void __iomem *retval; | ||
| 22 | unsigned long offs = paddr - ORION5X_REGS_PHYS_BASE; | ||
| 23 | if (mtype == MT_DEVICE && size && offs < ORION5X_REGS_SIZE && | ||
| 24 | size <= ORION5X_REGS_SIZE && offs + size <= ORION5X_REGS_SIZE) { | ||
| 25 | retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + offs; | ||
| 26 | } else { | ||
| 27 | retval = __arm_ioremap(paddr, size, mtype); | ||
| 28 | } | ||
| 29 | |||
| 30 | return retval; | ||
| 31 | } | ||
| 32 | |||
| 33 | static inline void | ||
| 34 | __arch_iounmap(void __iomem *addr) | ||
| 35 | { | ||
| 36 | if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE || | ||
| 37 | addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE)) | ||
| 38 | __iounmap(addr); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline void __iomem *__io(unsigned long addr) | ||
| 42 | { | ||
| 43 | return (void __iomem *)addr; | ||
| 44 | } | ||
| 45 | |||
| 46 | #define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) | ||
| 47 | #define __arch_iounmap(a) __arch_iounmap(a) | ||
| 48 | #define __io(a) __io(a) | ||
| 49 | #define __mem_pci(a) (a) | ||
| 50 | |||
| 51 | |||
| 52 | /***************************************************************************** | ||
| 53 | * Helpers to access Orion registers | ||
| 54 | ****************************************************************************/ | ||
| 55 | /* | ||
| 56 | * These are not preempt-safe. Locks, if needed, must be taken | ||
| 57 | * care of by the caller. | ||
| 58 | */ | ||
| 59 | #define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r)) | ||
| 60 | #define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r)) | ||
| 61 | |||
| 62 | |||
| 63 | #endif | ||
diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h deleted file mode 100644 index abdd61a4833a..000000000000 --- a/include/asm-arm/arch-orion5x/irqs.h +++ /dev/null | |||
| @@ -1,62 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ definitions for Orion SoC | ||
| 5 | * | ||
| 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_IRQS_H | ||
| 14 | #define __ASM_ARCH_IRQS_H | ||
| 15 | |||
| 16 | #include "orion5x.h" /* need GPIO_MAX */ | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Orion Main Interrupt Controller | ||
| 20 | */ | ||
| 21 | #define IRQ_ORION5X_BRIDGE 0 | ||
| 22 | #define IRQ_ORION5X_DOORBELL_H2C 1 | ||
| 23 | #define IRQ_ORION5X_DOORBELL_C2H 2 | ||
| 24 | #define IRQ_ORION5X_UART0 3 | ||
| 25 | #define IRQ_ORION5X_UART1 4 | ||
| 26 | #define IRQ_ORION5X_I2C 5 | ||
| 27 | #define IRQ_ORION5X_GPIO_0_7 6 | ||
| 28 | #define IRQ_ORION5X_GPIO_8_15 7 | ||
| 29 | #define IRQ_ORION5X_GPIO_16_23 8 | ||
| 30 | #define IRQ_ORION5X_GPIO_24_31 9 | ||
| 31 | #define IRQ_ORION5X_PCIE0_ERR 10 | ||
| 32 | #define IRQ_ORION5X_PCIE0_INT 11 | ||
| 33 | #define IRQ_ORION5X_USB1_CTRL 12 | ||
| 34 | #define IRQ_ORION5X_DEV_BUS_ERR 14 | ||
| 35 | #define IRQ_ORION5X_PCI_ERR 15 | ||
| 36 | #define IRQ_ORION5X_USB_BR_ERR 16 | ||
| 37 | #define IRQ_ORION5X_USB0_CTRL 17 | ||
| 38 | #define IRQ_ORION5X_ETH_RX 18 | ||
| 39 | #define IRQ_ORION5X_ETH_TX 19 | ||
| 40 | #define IRQ_ORION5X_ETH_MISC 20 | ||
| 41 | #define IRQ_ORION5X_ETH_SUM 21 | ||
| 42 | #define IRQ_ORION5X_ETH_ERR 22 | ||
| 43 | #define IRQ_ORION5X_IDMA_ERR 23 | ||
| 44 | #define IRQ_ORION5X_IDMA_0 24 | ||
| 45 | #define IRQ_ORION5X_IDMA_1 25 | ||
| 46 | #define IRQ_ORION5X_IDMA_2 26 | ||
| 47 | #define IRQ_ORION5X_IDMA_3 27 | ||
| 48 | #define IRQ_ORION5X_CESA 28 | ||
| 49 | #define IRQ_ORION5X_SATA 29 | ||
| 50 | #define IRQ_ORION5X_XOR0 30 | ||
| 51 | #define IRQ_ORION5X_XOR1 31 | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Orion General Purpose Pins | ||
| 55 | */ | ||
| 56 | #define IRQ_ORION5X_GPIO_START 32 | ||
| 57 | #define NR_GPIO_IRQS GPIO_MAX | ||
| 58 | |||
| 59 | #define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) | ||
| 60 | |||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/asm-arm/arch-orion5x/memory.h b/include/asm-arm/arch-orion5x/memory.h deleted file mode 100644 index 80053a7afc7a..000000000000 --- a/include/asm-arm/arch-orion5x/memory.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/memory.h | ||
| 3 | * | ||
| 4 | * Marvell Orion memory definitions | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 8 | #define __ASM_ARCH_MEMORY_H | ||
| 9 | |||
| 10 | #define PHYS_OFFSET UL(0x00000000) | ||
| 11 | |||
| 12 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 13 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 14 | |||
| 15 | |||
| 16 | #endif | ||
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h deleted file mode 100644 index 10257f5c5e9e..000000000000 --- a/include/asm-arm/arch-orion5x/orion5x.h +++ /dev/null | |||
| @@ -1,162 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/orion5x.h | ||
| 3 | * | ||
| 4 | * Generic definitions of Orion SoC flavors: | ||
| 5 | * Orion-1, Orion-VoIP, Orion-NAS, and Orion-2. | ||
| 6 | * | ||
| 7 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_ORION5X_H | ||
| 15 | #define __ASM_ARCH_ORION5X_H | ||
| 16 | |||
| 17 | /***************************************************************************** | ||
| 18 | * Orion Address Maps | ||
| 19 | * | ||
| 20 | * phys | ||
| 21 | * e0000000 PCIe MEM space | ||
| 22 | * e8000000 PCI MEM space | ||
| 23 | * f0000000 PCIe WA space (Orion-1/Orion-NAS only) | ||
| 24 | * f1000000 on-chip peripheral registers | ||
| 25 | * f2000000 PCIe I/O space | ||
| 26 | * f2100000 PCI I/O space | ||
| 27 | * f4000000 device bus mappings (boot) | ||
| 28 | * fa000000 device bus mappings (cs0) | ||
| 29 | * fa800000 device bus mappings (cs2) | ||
| 30 | * fc000000 device bus mappings (cs0/cs1) | ||
| 31 | * | ||
| 32 | * virt phys size | ||
| 33 | * fdd00000 f1000000 1M on-chip peripheral registers | ||
| 34 | * fde00000 f2000000 1M PCIe I/O space | ||
| 35 | * fdf00000 f2100000 1M PCI I/O space | ||
| 36 | * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) | ||
| 37 | ****************************************************************************/ | ||
| 38 | #define ORION5X_REGS_PHYS_BASE 0xf1000000 | ||
| 39 | #define ORION5X_REGS_VIRT_BASE 0xfdd00000 | ||
| 40 | #define ORION5X_REGS_SIZE SZ_1M | ||
| 41 | |||
| 42 | #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 | ||
| 43 | #define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 | ||
| 44 | #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 | ||
| 45 | #define ORION5X_PCIE_IO_SIZE SZ_1M | ||
| 46 | |||
| 47 | #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 | ||
| 48 | #define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 | ||
| 49 | #define ORION5X_PCI_IO_BUS_BASE 0x00100000 | ||
| 50 | #define ORION5X_PCI_IO_SIZE SZ_1M | ||
| 51 | |||
| 52 | /* Relevant only for Orion-1/Orion-NAS */ | ||
| 53 | #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 | ||
| 54 | #define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 | ||
| 55 | #define ORION5X_PCIE_WA_SIZE SZ_16M | ||
| 56 | |||
| 57 | #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 | ||
| 58 | #define ORION5X_PCIE_MEM_SIZE SZ_128M | ||
| 59 | |||
| 60 | #define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 | ||
| 61 | #define ORION5X_PCI_MEM_SIZE SZ_128M | ||
| 62 | |||
| 63 | /******************************************************************************* | ||
| 64 | * Supported Devices & Revisions | ||
| 65 | ******************************************************************************/ | ||
| 66 | /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ | ||
| 67 | #define MV88F5181_DEV_ID 0x5181 | ||
| 68 | #define MV88F5181_REV_B1 3 | ||
| 69 | #define MV88F5181L_REV_A0 8 | ||
| 70 | #define MV88F5181L_REV_A1 9 | ||
| 71 | /* Orion-NAS (88F5182) */ | ||
| 72 | #define MV88F5182_DEV_ID 0x5182 | ||
| 73 | #define MV88F5182_REV_A2 2 | ||
| 74 | /* Orion-2 (88F5281) */ | ||
| 75 | #define MV88F5281_DEV_ID 0x5281 | ||
| 76 | #define MV88F5281_REV_D1 5 | ||
| 77 | #define MV88F5281_REV_D2 6 | ||
| 78 | |||
| 79 | /******************************************************************************* | ||
| 80 | * Orion Registers Map | ||
| 81 | ******************************************************************************/ | ||
| 82 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) | ||
| 83 | #define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) | ||
| 84 | |||
| 85 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) | ||
| 86 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) | ||
| 87 | #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) | ||
| 88 | #define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) | ||
| 89 | #define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) | ||
| 90 | #define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) | ||
| 91 | #define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) | ||
| 92 | #define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) | ||
| 93 | |||
| 94 | #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) | ||
| 95 | #define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) | ||
| 96 | #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) | ||
| 97 | |||
| 98 | #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) | ||
| 99 | #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) | ||
| 100 | |||
| 101 | #define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) | ||
| 102 | #define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) | ||
| 103 | |||
| 104 | #define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) | ||
| 105 | #define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) | ||
| 106 | #define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) | ||
| 107 | |||
| 108 | #define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) | ||
| 109 | #define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) | ||
| 110 | #define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) | ||
| 111 | |||
| 112 | #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) | ||
| 113 | #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) | ||
| 114 | #define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) | ||
| 115 | |||
| 116 | #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) | ||
| 117 | #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) | ||
| 118 | #define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) | ||
| 119 | |||
| 120 | /******************************************************************************* | ||
| 121 | * Device Bus Registers | ||
| 122 | ******************************************************************************/ | ||
| 123 | #define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) | ||
| 124 | #define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) | ||
| 125 | #define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) | ||
| 126 | #define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) | ||
| 127 | #define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) | ||
| 128 | #define GPIO_OUT ORION5X_DEV_BUS_REG(0x100) | ||
| 129 | #define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104) | ||
| 130 | #define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108) | ||
| 131 | #define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c) | ||
| 132 | #define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110) | ||
| 133 | #define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114) | ||
| 134 | #define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118) | ||
| 135 | #define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c) | ||
| 136 | #define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) | ||
| 137 | #define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) | ||
| 138 | #define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) | ||
| 139 | #define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) | ||
| 140 | #define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) | ||
| 141 | #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) | ||
| 142 | #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) | ||
| 143 | #define GPIO_MAX 32 | ||
| 144 | |||
| 145 | /*************************************************************************** | ||
| 146 | * Orion CPU Bridge Registers | ||
| 147 | **************************************************************************/ | ||
| 148 | #define CPU_CONF ORION5X_BRIDGE_REG(0x100) | ||
| 149 | #define CPU_CTRL ORION5X_BRIDGE_REG(0x104) | ||
| 150 | #define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) | ||
| 151 | #define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) | ||
| 152 | #define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) | ||
| 153 | #define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) | ||
| 154 | #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) | ||
| 155 | #define BRIDGE_INT_TIMER0 0x0002 | ||
| 156 | #define BRIDGE_INT_TIMER1 0x0004 | ||
| 157 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | ||
| 158 | #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) | ||
| 159 | #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) | ||
| 160 | |||
| 161 | |||
| 162 | #endif | ||
diff --git a/include/asm-arm/arch-orion5x/system.h b/include/asm-arm/arch-orion5x/system.h deleted file mode 100644 index 3f1d1e2d38f8..000000000000 --- a/include/asm-arm/arch-orion5x/system.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/system.h | ||
| 3 | * | ||
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 12 | #define __ASM_ARCH_SYSTEM_H | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | #include <asm/arch/orion5x.h> | ||
| 16 | |||
| 17 | static inline void arch_idle(void) | ||
| 18 | { | ||
| 19 | cpu_do_idle(); | ||
| 20 | } | ||
| 21 | |||
| 22 | static inline void arch_reset(char mode) | ||
| 23 | { | ||
| 24 | /* | ||
| 25 | * Enable and issue soft reset | ||
| 26 | */ | ||
| 27 | orion5x_setbits(CPU_RESET_MASK, (1 << 2)); | ||
| 28 | orion5x_setbits(CPU_SOFT_RESET, 1); | ||
| 29 | } | ||
| 30 | |||
| 31 | |||
| 32 | #endif | ||
diff --git a/include/asm-arm/arch-orion5x/timex.h b/include/asm-arm/arch-orion5x/timex.h deleted file mode 100644 index 31c568e28cc3..000000000000 --- a/include/asm-arm/arch-orion5x/timex.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/timex.h | ||
| 3 | * | ||
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #define CLOCK_TICK_RATE (100 * HZ) | ||
| 12 | |||
| 13 | #define ORION5X_TCLK 166666667 | ||
diff --git a/include/asm-arm/arch-orion5x/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h deleted file mode 100644 index 7548cedf2d76..000000000000 --- a/include/asm-arm/arch-orion5x/uncompress.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/uncompress.h | ||
| 3 | * | ||
| 4 | * Tzachi Perelstein <tzachi@marvell.com> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/serial_reg.h> | ||
| 12 | #include <asm/arch/orion5x.h> | ||
| 13 | |||
| 14 | #define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) | ||
| 15 | |||
| 16 | static void putc(const char c) | ||
| 17 | { | ||
| 18 | unsigned char *base = SERIAL_BASE; | ||
| 19 | int i; | ||
| 20 | |||
| 21 | for (i = 0; i < 0x1000; i++) { | ||
| 22 | if (base[UART_LSR << 2] & UART_LSR_THRE) | ||
| 23 | break; | ||
| 24 | barrier(); | ||
| 25 | } | ||
| 26 | |||
| 27 | base[UART_TX << 2] = c; | ||
| 28 | } | ||
| 29 | |||
| 30 | static void flush(void) | ||
| 31 | { | ||
| 32 | unsigned char *base = SERIAL_BASE; | ||
| 33 | unsigned char mask; | ||
| 34 | int i; | ||
| 35 | |||
| 36 | mask = UART_LSR_TEMT | UART_LSR_THRE; | ||
| 37 | |||
| 38 | for (i = 0; i < 0x1000; i++) { | ||
| 39 | if ((base[UART_LSR << 2] & mask) == mask) | ||
| 40 | break; | ||
| 41 | barrier(); | ||
| 42 | } | ||
| 43 | } | ||
| 44 | |||
| 45 | /* | ||
| 46 | * nothing to do | ||
| 47 | */ | ||
| 48 | #define arch_decomp_setup() | ||
| 49 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-orion5x/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h deleted file mode 100644 index 2b3061e90dc1..000000000000 --- a/include/asm-arm/arch-orion5x/vmalloc.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-orion5x/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define VMALLOC_END 0xfd800000 | ||
diff --git a/include/asm-arm/arch-pnx4008/clock.h b/include/asm-arm/arch-pnx4008/clock.h deleted file mode 100644 index ce155e161269..000000000000 --- a/include/asm-arm/arch-pnx4008/clock.h +++ /dev/null | |||
| @@ -1,62 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pnx4008/clock.h | ||
| 3 | * | ||
| 4 | * Clock control driver for PNX4008 - header file | ||
| 5 | * | ||
| 6 | * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com> | ||
| 7 | * | ||
| 8 | * 2005 (c) MontaVista Software, Inc. This file is licensed under | ||
| 9 | * the terms of the GNU General Public License version 2. This program | ||
| 10 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 11 | * or implied. | ||
| 12 | */ | ||
| 13 | #ifndef __PNX4008_CLOCK_H__ | ||
| 14 | #define __PNX4008_CLOCK_H__ | ||
| 15 | |||
| 16 | struct module; | ||
| 17 | struct clk; | ||
| 18 | |||
| 19 | #define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE) | ||
| 20 | #define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40) | ||
| 21 | #define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44) | ||
| 22 | #define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48) | ||
| 23 | #define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c) | ||
| 24 | #define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50) | ||
| 25 | #define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58) | ||
| 26 | #define USBCTRL_REG (PWRMAN_VA_BASE + 0x64) | ||
| 27 | #define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68) | ||
| 28 | #define MSCTRL_REG (PWRMAN_VA_BASE + 0x80) | ||
| 29 | #define BTCLKCTRL (PWRMAN_VA_BASE + 0x84) | ||
| 30 | #define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90) | ||
| 31 | #define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac) | ||
| 32 | #define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0) | ||
| 33 | #define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4) | ||
| 34 | #define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8) | ||
| 35 | #define TIMCLKCTRL_REG (PWRMAN_VA_BASE + 0xbc) | ||
| 36 | #define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4) | ||
| 37 | #define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8) | ||
| 38 | #define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0) | ||
| 39 | #define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4) | ||
| 40 | #define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8) | ||
| 41 | #define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec) | ||
| 42 | #define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc) | ||
| 43 | |||
| 44 | #define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE) | ||
| 45 | #define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60) | ||
| 46 | #define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64) | ||
| 47 | #define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68) | ||
| 48 | #define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C) | ||
| 49 | |||
| 50 | #define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4) | ||
| 51 | |||
| 52 | #define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE) | ||
| 53 | |||
| 54 | #define CLK_RATE_13MHZ 13000 | ||
| 55 | #define CLK_RATE_1MHZ 1000 | ||
| 56 | #define CLK_RATE_208MHZ 208000 | ||
| 57 | #define CLK_RATE_48MHZ 48000 | ||
| 58 | #define CLK_RATE_32KHZ 32 | ||
| 59 | |||
| 60 | #define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */ | ||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/asm-arm/arch-pnx4008/debug-macro.S b/include/asm-arm/arch-pnx4008/debug-macro.S deleted file mode 100644 index 67d18a203d23..000000000000 --- a/include/asm-arm/arch-pnx4008/debug-macro.S +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-pnx4008/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | mov \rx, #0x00090000 | ||
| 18 | addeq \rx, \rx, #0x40000000 | ||
| 19 | addne \rx, \rx, #0xf4000000 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | #define UART_SHIFT 2 | ||
| 23 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-pnx4008/dma.h b/include/asm-arm/arch-pnx4008/dma.h deleted file mode 100644 index 418f15283ff1..000000000000 --- a/include/asm-arm/arch-pnx4008/dma.h +++ /dev/null | |||
| @@ -1,162 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pnx4008/dma.h | ||
| 3 | * | ||
| 4 | * PNX4008 DMA header file | ||
| 5 | * | ||
| 6 | * Author: Vitaly Wool | ||
| 7 | * Copyright: MontaVista Software Inc. (c) 2005 | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_DMA_H | ||
| 15 | #define __ASM_ARCH_DMA_H | ||
| 16 | |||
| 17 | #include "platform.h" | ||
| 18 | |||
| 19 | #define MAX_DMA_ADDRESS 0xffffffff | ||
| 20 | |||
| 21 | #define MAX_DMA_CHANNELS 8 | ||
| 22 | |||
| 23 | #define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE) | ||
| 24 | #define DMAC_INT_STAT (DMAC_BASE + 0x0000) | ||
| 25 | #define DMAC_INT_TC_STAT (DMAC_BASE + 0x0004) | ||
| 26 | #define DMAC_INT_TC_CLEAR (DMAC_BASE + 0x0008) | ||
| 27 | #define DMAC_INT_ERR_STAT (DMAC_BASE + 0x000c) | ||
| 28 | #define DMAC_INT_ERR_CLEAR (DMAC_BASE + 0x0010) | ||
| 29 | #define DMAC_SOFT_SREQ (DMAC_BASE + 0x0024) | ||
| 30 | #define DMAC_CONFIG (DMAC_BASE + 0x0030) | ||
| 31 | #define DMAC_Cx_SRC_ADDR(c) (DMAC_BASE + 0x0100 + (c) * 0x20) | ||
| 32 | #define DMAC_Cx_DEST_ADDR(c) (DMAC_BASE + 0x0104 + (c) * 0x20) | ||
| 33 | #define DMAC_Cx_LLI(c) (DMAC_BASE + 0x0108 + (c) * 0x20) | ||
| 34 | #define DMAC_Cx_CONTROL(c) (DMAC_BASE + 0x010c + (c) * 0x20) | ||
| 35 | #define DMAC_Cx_CONFIG(c) (DMAC_BASE + 0x0110 + (c) * 0x20) | ||
| 36 | |||
| 37 | enum { | ||
| 38 | WIDTH_BYTE = 0, | ||
| 39 | WIDTH_HWORD, | ||
| 40 | WIDTH_WORD | ||
| 41 | }; | ||
| 42 | |||
| 43 | enum { | ||
| 44 | FC_MEM2MEM_DMA, | ||
| 45 | FC_MEM2PER_DMA, | ||
| 46 | FC_PER2MEM_DMA, | ||
| 47 | FC_PER2PER_DMA, | ||
| 48 | FC_PER2PER_DPER, | ||
| 49 | FC_MEM2PER_PER, | ||
| 50 | FC_PER2MEM_PER, | ||
| 51 | FC_PER2PER_SPER | ||
| 52 | }; | ||
| 53 | |||
| 54 | enum { | ||
| 55 | DMA_INT_UNKNOWN = 0, | ||
| 56 | DMA_ERR_INT = 1, | ||
| 57 | DMA_TC_INT = 2, | ||
| 58 | }; | ||
| 59 | |||
| 60 | enum { | ||
| 61 | DMA_BUFFER_ALLOCATED = 1, | ||
| 62 | DMA_HAS_LL = 2, | ||
| 63 | }; | ||
| 64 | |||
| 65 | enum { | ||
| 66 | PER_CAM_DMA_1 = 0, | ||
| 67 | PER_NDF_FLASH = 1, | ||
| 68 | PER_MBX_SLAVE_FIFO = 2, | ||
| 69 | PER_SPI2_REC_XMIT = 3, | ||
| 70 | PER_MS_SD_RX_XMIT = 4, | ||
| 71 | PER_HS_UART_1_XMIT = 5, | ||
| 72 | PER_HS_UART_1_RX = 6, | ||
| 73 | PER_HS_UART_2_XMIT = 7, | ||
| 74 | PER_HS_UART_2_RX = 8, | ||
| 75 | PER_HS_UART_7_XMIT = 9, | ||
| 76 | PER_HS_UART_7_RX = 10, | ||
| 77 | PER_SPI1_REC_XMIT = 11, | ||
| 78 | PER_MLC_NDF_SREC = 12, | ||
| 79 | PER_CAM_DMA_2 = 13, | ||
| 80 | PER_PRNG_INFIFO = 14, | ||
| 81 | PER_PRNG_OUTFIFO = 15, | ||
| 82 | }; | ||
| 83 | |||
| 84 | struct pnx4008_dma_ch_ctrl { | ||
| 85 | int tc_mask; | ||
| 86 | int cacheable; | ||
| 87 | int bufferable; | ||
| 88 | int priv_mode; | ||
| 89 | int di; | ||
| 90 | int si; | ||
| 91 | int dest_ahb1; | ||
| 92 | int src_ahb1; | ||
| 93 | int dwidth; | ||
| 94 | int swidth; | ||
| 95 | int dbsize; | ||
| 96 | int sbsize; | ||
| 97 | int tr_size; | ||
| 98 | }; | ||
| 99 | |||
| 100 | struct pnx4008_dma_ch_config { | ||
| 101 | int halt; | ||
| 102 | int active; | ||
| 103 | int lock; | ||
| 104 | int itc; | ||
| 105 | int ie; | ||
| 106 | int flow_cntrl; | ||
| 107 | int dest_per; | ||
| 108 | int src_per; | ||
| 109 | }; | ||
| 110 | |||
| 111 | struct pnx4008_dma_ll { | ||
| 112 | unsigned long src_addr; | ||
| 113 | unsigned long dest_addr; | ||
| 114 | u32 next_dma; | ||
| 115 | unsigned long ch_ctrl; | ||
| 116 | struct pnx4008_dma_ll *next; | ||
| 117 | int flags; | ||
| 118 | void *alloc_data; | ||
| 119 | int (*free) (void *); | ||
| 120 | }; | ||
| 121 | |||
| 122 | struct pnx4008_dma_config { | ||
| 123 | int is_ll; | ||
| 124 | unsigned long src_addr; | ||
| 125 | unsigned long dest_addr; | ||
| 126 | unsigned long ch_ctrl; | ||
| 127 | unsigned long ch_cfg; | ||
| 128 | struct pnx4008_dma_ll *ll; | ||
| 129 | u32 ll_dma; | ||
| 130 | int flags; | ||
| 131 | void *alloc_data; | ||
| 132 | int (*free) (void *); | ||
| 133 | }; | ||
| 134 | |||
| 135 | extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *); | ||
| 136 | extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t); | ||
| 137 | extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *); | ||
| 138 | |||
| 139 | extern int pnx4008_request_channel(char *, int, | ||
| 140 | void (*)(int, int, void *), | ||
| 141 | void *); | ||
| 142 | extern void pnx4008_free_channel(int); | ||
| 143 | extern int pnx4008_config_dma(int, int, int); | ||
| 144 | extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *, | ||
| 145 | unsigned long *); | ||
| 146 | extern int pnx4008_dma_parse_control(unsigned long, | ||
| 147 | struct pnx4008_dma_ch_ctrl *); | ||
| 148 | extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *, | ||
| 149 | unsigned long *); | ||
| 150 | extern int pnx4008_dma_parse_config(unsigned long, | ||
| 151 | struct pnx4008_dma_ch_config *); | ||
| 152 | extern int pnx4008_config_channel(int, struct pnx4008_dma_config *); | ||
| 153 | extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *); | ||
| 154 | extern int pnx4008_dma_ch_enable(int); | ||
| 155 | extern int pnx4008_dma_ch_disable(int); | ||
| 156 | extern int pnx4008_dma_ch_enabled(int); | ||
| 157 | extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *, | ||
| 158 | struct pnx4008_dma_ch_ctrl *); | ||
| 159 | extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *, | ||
| 160 | struct pnx4008_dma_ch_ctrl *); | ||
| 161 | |||
| 162 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-pnx4008/entry-macro.S b/include/asm-arm/arch-pnx4008/entry-macro.S deleted file mode 100644 index f11731974e5d..000000000000 --- a/include/asm-arm/arch-pnx4008/entry-macro.S +++ /dev/null | |||
| @@ -1,127 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pnx4008/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for PNX4008-based platforms | ||
| 5 | * | ||
| 6 | * 2005-2006 (c) MontaVista Software, Inc. | ||
| 7 | * Author: Vitaly Wool <vwool@ru.mvista.com> | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include "platform.h" | ||
| 14 | |||
| 15 | #define IO_BASE 0xF0000000 | ||
| 16 | #define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE) | ||
| 17 | |||
| 18 | #define INTRC_MASK 0x00 | ||
| 19 | #define INTRC_RAW_STAT 0x04 | ||
| 20 | #define INTRC_STAT 0x08 | ||
| 21 | #define INTRC_POLAR 0x0C | ||
| 22 | #define INTRC_ACT_TYPE 0x10 | ||
| 23 | #define INTRC_TYPE 0x14 | ||
| 24 | |||
| 25 | #define SIC1_BASE_INT 32 | ||
| 26 | #define SIC2_BASE_INT 64 | ||
| 27 | |||
| 28 | .macro disable_fiq | ||
| 29 | .endm | ||
| 30 | |||
| 31 | .macro get_irqnr_preamble, base, tmp | ||
| 32 | .endm | ||
| 33 | |||
| 34 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 35 | .endm | ||
| 36 | |||
| 37 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 38 | /* decode the MIC interrupt numbers */ | ||
| 39 | ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) | ||
| 40 | ldr \irqstat, [\base, #INTRC_STAT] | ||
| 41 | |||
| 42 | cmp \irqstat,#1<<16 | ||
| 43 | movhs \irqnr,#16 | ||
| 44 | movlo \irqnr,#0 | ||
| 45 | movhs \irqstat,\irqstat,lsr#16 | ||
| 46 | cmp \irqstat,#1<<8 | ||
| 47 | addhs \irqnr,\irqnr,#8 | ||
| 48 | movhs \irqstat,\irqstat,lsr#8 | ||
| 49 | cmp \irqstat,#1<<4 | ||
| 50 | addhs \irqnr,\irqnr,#4 | ||
| 51 | movhs \irqstat,\irqstat,lsr#4 | ||
| 52 | cmp \irqstat,#1<<2 | ||
| 53 | addhs \irqnr,\irqnr,#2 | ||
| 54 | movhs \irqstat,\irqstat,lsr#2 | ||
| 55 | cmp \irqstat,#1<<1 | ||
| 56 | addhs \irqnr,\irqnr,#1 | ||
| 57 | |||
| 58 | /* was there an interrupt ? if not then drop out with EQ status */ | ||
| 59 | teq \irqstat,#0 | ||
| 60 | beq 1003f | ||
| 61 | |||
| 62 | /* and now check for extended IRQ reasons */ | ||
| 63 | cmp \irqnr,#1 | ||
| 64 | bls 1003f | ||
| 65 | cmp \irqnr,#30 | ||
| 66 | blo 1002f | ||
| 67 | |||
| 68 | /* IRQ 31,30 : High priority cascade IRQ handle */ | ||
| 69 | /* read the correct SIC */ | ||
| 70 | /* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */ | ||
| 71 | /* set the base IRQ number */ | ||
| 72 | ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) | ||
| 73 | moveq \irqnr,#SIC1_BASE_INT | ||
| 74 | ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) | ||
| 75 | movne \irqnr,#SIC2_BASE_INT | ||
| 76 | ldr \irqstat, [\base, #INTRC_STAT] | ||
| 77 | ldr \tmp, [\base, #INTRC_TYPE] | ||
| 78 | /* and with inverted mask : low priority interrupts */ | ||
| 79 | and \irqstat,\irqstat,\tmp | ||
| 80 | b 1004f | ||
| 81 | |||
| 82 | 1003: | ||
| 83 | /* IRQ 1,0 : Low priority cascade IRQ handle */ | ||
| 84 | /* read the correct SIC */ | ||
| 85 | /* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/ | ||
| 86 | /* read the correct SIC */ | ||
| 87 | /* set the base IRQ number */ | ||
| 88 | ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) | ||
| 89 | movne \irqnr,#SIC1_BASE_INT | ||
| 90 | ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) | ||
| 91 | moveq \irqnr,#SIC2_BASE_INT | ||
| 92 | ldr \irqstat, [\base, #INTRC_STAT] | ||
| 93 | ldr \tmp, [\base, #INTRC_TYPE] | ||
| 94 | /* and with inverted mask : low priority interrupts */ | ||
| 95 | bic \irqstat,\irqstat,\tmp | ||
| 96 | |||
| 97 | 1004: | ||
| 98 | |||
| 99 | cmp \irqstat,#1<<16 | ||
| 100 | addhs \irqnr,\irqnr,#16 | ||
| 101 | movhs \irqstat,\irqstat,lsr#16 | ||
| 102 | cmp \irqstat,#1<<8 | ||
| 103 | addhs \irqnr,\irqnr,#8 | ||
| 104 | movhs \irqstat,\irqstat,lsr#8 | ||
| 105 | cmp \irqstat,#1<<4 | ||
| 106 | addhs \irqnr,\irqnr,#4 | ||
| 107 | movhs \irqstat,\irqstat,lsr#4 | ||
| 108 | cmp \irqstat,#1<<2 | ||
| 109 | addhs \irqnr,\irqnr,#2 | ||
| 110 | movhs \irqstat,\irqstat,lsr#2 | ||
| 111 | cmp \irqstat,#1<<1 | ||
| 112 | addhs \irqnr,\irqnr,#1 | ||
| 113 | |||
| 114 | |||
| 115 | /* is irqstat not zero */ | ||
| 116 | |||
| 117 | 1002: | ||
| 118 | /* we assert that irqstat is not equal to zero and return ne status if true*/ | ||
| 119 | teq \irqstat,#0 | ||
| 120 | 1003: | ||
| 121 | .endm | ||
| 122 | |||
| 123 | |||
| 124 | .macro irq_prio_table | ||
| 125 | .endm | ||
| 126 | |||
| 127 | |||
diff --git a/include/asm-arm/arch-pnx4008/gpio.h b/include/asm-arm/arch-pnx4008/gpio.h deleted file mode 100644 index d01bf83d55c2..000000000000 --- a/include/asm-arm/arch-pnx4008/gpio.h +++ /dev/null | |||
| @@ -1,241 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pnx4008/gpio.h | ||
| 3 | * | ||
| 4 | * PNX4008 GPIO driver - header file | ||
| 5 | * | ||
| 6 | * Author: Dmitry Chigirev <source@mvista.com> | ||
| 7 | * | ||
| 8 | * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips: | ||
| 9 | * Copyright (c) 2005 Koninklijke Philips Electronics N.V. | ||
| 10 | * | ||
| 11 | * 2005 (c) MontaVista Software, Inc. This file is licensed under | ||
| 12 | * the terms of the GNU General Public License version 2. This program | ||
| 13 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 14 | * or implied. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef _PNX4008_GPIO_H_ | ||
| 18 | #define _PNX4008_GPIO_H_ | ||
| 19 | |||
| 20 | |||
| 21 | /* Block numbers */ | ||
| 22 | #define GPIO_IN (0) | ||
| 23 | #define GPIO_OUT (0x100) | ||
| 24 | #define GPIO_BID (0x200) | ||
| 25 | #define GPIO_RAM (0x300) | ||
| 26 | #define GPIO_MUX (0x400) | ||
| 27 | |||
| 28 | #define GPIO_TYPE_MASK(K) ((K) & 0x700) | ||
| 29 | |||
| 30 | /* INPUT GPIOs */ | ||
| 31 | /* GPI */ | ||
| 32 | #define GPI_00 (GPIO_IN | 0) | ||
| 33 | #define GPI_01 (GPIO_IN | 1) | ||
| 34 | #define GPI_02 (GPIO_IN | 2) | ||
| 35 | #define GPI_03 (GPIO_IN | 3) | ||
| 36 | #define GPI_04 (GPIO_IN | 4) | ||
| 37 | #define GPI_05 (GPIO_IN | 5) | ||
| 38 | #define GPI_06 (GPIO_IN | 6) | ||
| 39 | #define GPI_07 (GPIO_IN | 7) | ||
| 40 | #define GPI_08 (GPIO_IN | 8) | ||
| 41 | #define GPI_09 (GPIO_IN | 9) | ||
| 42 | #define U1_RX (GPIO_IN | 15) | ||
| 43 | #define U2_HTCS (GPIO_IN | 16) | ||
| 44 | #define U2_RX (GPIO_IN | 17) | ||
| 45 | #define U3_RX (GPIO_IN | 18) | ||
| 46 | #define U4_RX (GPIO_IN | 19) | ||
| 47 | #define U5_RX (GPIO_IN | 20) | ||
| 48 | #define U6_IRRX (GPIO_IN | 21) | ||
| 49 | #define U7_HCTS (GPIO_IN | 22) | ||
| 50 | #define U7_RX (GPIO_IN | 23) | ||
| 51 | /* MISC IN */ | ||
| 52 | #define SPI1_DATIN (GPIO_IN | 25) | ||
| 53 | #define DISP_SYNC (GPIO_IN | 26) | ||
| 54 | #define SPI2_DATIN (GPIO_IN | 27) | ||
| 55 | #define GPI_11 (GPIO_IN | 28) | ||
| 56 | |||
| 57 | #define GPIO_IN_MASK 0x1eff83ff | ||
| 58 | |||
| 59 | /* OUTPUT GPIOs */ | ||
| 60 | /* GPO */ | ||
| 61 | #define GPO_00 (GPIO_OUT | 0) | ||
| 62 | #define GPO_01 (GPIO_OUT | 1) | ||
| 63 | #define GPO_02 (GPIO_OUT | 2) | ||
| 64 | #define GPO_03 (GPIO_OUT | 3) | ||
| 65 | #define GPO_04 (GPIO_OUT | 4) | ||
| 66 | #define GPO_05 (GPIO_OUT | 5) | ||
| 67 | #define GPO_06 (GPIO_OUT | 6) | ||
| 68 | #define GPO_07 (GPIO_OUT | 7) | ||
| 69 | #define GPO_08 (GPIO_OUT | 8) | ||
| 70 | #define GPO_09 (GPIO_OUT | 9) | ||
| 71 | #define GPO_10 (GPIO_OUT | 10) | ||
| 72 | #define GPO_11 (GPIO_OUT | 11) | ||
| 73 | #define GPO_12 (GPIO_OUT | 12) | ||
| 74 | #define GPO_13 (GPIO_OUT | 13) | ||
| 75 | #define GPO_14 (GPIO_OUT | 14) | ||
| 76 | #define GPO_15 (GPIO_OUT | 15) | ||
| 77 | #define GPO_16 (GPIO_OUT | 16) | ||
| 78 | #define GPO_17 (GPIO_OUT | 17) | ||
| 79 | #define GPO_18 (GPIO_OUT | 18) | ||
| 80 | #define GPO_19 (GPIO_OUT | 19) | ||
| 81 | #define GPO_20 (GPIO_OUT | 20) | ||
| 82 | #define GPO_21 (GPIO_OUT | 21) | ||
| 83 | #define GPO_22 (GPIO_OUT | 22) | ||
| 84 | #define GPO_23 (GPIO_OUT | 23) | ||
| 85 | |||
| 86 | #define GPIO_OUT_MASK 0xffffff | ||
| 87 | |||
| 88 | /* BIDIRECTIONAL GPIOs */ | ||
| 89 | /* RAM pins */ | ||
| 90 | #define RAM_D19 (GPIO_RAM | 0) | ||
| 91 | #define RAM_D20 (GPIO_RAM | 1) | ||
| 92 | #define RAM_D21 (GPIO_RAM | 2) | ||
| 93 | #define RAM_D22 (GPIO_RAM | 3) | ||
| 94 | #define RAM_D23 (GPIO_RAM | 4) | ||
| 95 | #define RAM_D24 (GPIO_RAM | 5) | ||
| 96 | #define RAM_D25 (GPIO_RAM | 6) | ||
| 97 | #define RAM_D26 (GPIO_RAM | 7) | ||
| 98 | #define RAM_D27 (GPIO_RAM | 8) | ||
| 99 | #define RAM_D28 (GPIO_RAM | 9) | ||
| 100 | #define RAM_D29 (GPIO_RAM | 10) | ||
| 101 | #define RAM_D30 (GPIO_RAM | 11) | ||
| 102 | #define RAM_D31 (GPIO_RAM | 12) | ||
| 103 | |||
| 104 | #define GPIO_RAM_MASK 0x1fff | ||
| 105 | |||
| 106 | /* I/O pins */ | ||
| 107 | #define GPIO_00 (GPIO_BID | 25) | ||
| 108 | #define GPIO_01 (GPIO_BID | 26) | ||
| 109 | #define GPIO_02 (GPIO_BID | 27) | ||
| 110 | #define GPIO_03 (GPIO_BID | 28) | ||
| 111 | #define GPIO_04 (GPIO_BID | 29) | ||
| 112 | #define GPIO_05 (GPIO_BID | 30) | ||
| 113 | |||
| 114 | #define GPIO_BID_MASK 0x7e000000 | ||
| 115 | |||
| 116 | /* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */ | ||
| 117 | #define GPIO_SDRAM_SEL (GPIO_MUX | 3) | ||
| 118 | |||
| 119 | #define GPIO_MUX_MASK 0x8 | ||
| 120 | |||
| 121 | /* Extraction/assembly macros */ | ||
| 122 | #define GPIO_BIT_MASK(K) ((K) & 0x1F) | ||
| 123 | #define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K)) | ||
| 124 | #define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK)) | ||
| 125 | #define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK)) | ||
| 126 | #define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK)) | ||
| 127 | #define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK)) | ||
| 128 | #define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK)) | ||
| 129 | |||
| 130 | /* Start Enable Pin Interrupts - table 58 page 66 */ | ||
| 131 | |||
| 132 | #define SE_PIN_BASE_INT 32 | ||
| 133 | |||
| 134 | #define SE_U7_RX_INT 63 | ||
| 135 | #define SE_U7_HCTS_INT 62 | ||
| 136 | #define SE_BT_CLKREQ_INT 61 | ||
| 137 | #define SE_U6_IRRX_INT 60 | ||
| 138 | /*59 unused*/ | ||
| 139 | #define SE_U5_RX_INT 58 | ||
| 140 | #define SE_GPI_11_INT 57 | ||
| 141 | #define SE_U3_RX_INT 56 | ||
| 142 | #define SE_U2_HCTS_INT 55 | ||
| 143 | #define SE_U2_RX_INT 54 | ||
| 144 | #define SE_U1_RX_INT 53 | ||
| 145 | #define SE_DISP_SYNC_INT 52 | ||
| 146 | /*51 unused*/ | ||
| 147 | #define SE_SDIO_INT_N 50 | ||
| 148 | #define SE_MSDIO_START_INT 49 | ||
| 149 | #define SE_GPI_06_INT 48 | ||
| 150 | #define SE_GPI_05_INT 47 | ||
| 151 | #define SE_GPI_04_INT 46 | ||
| 152 | #define SE_GPI_03_INT 45 | ||
| 153 | #define SE_GPI_02_INT 44 | ||
| 154 | #define SE_GPI_01_INT 43 | ||
| 155 | #define SE_GPI_00_INT 42 | ||
| 156 | #define SE_SYSCLKEN_PIN_INT 41 | ||
| 157 | #define SE_SPI1_DATAIN_INT 40 | ||
| 158 | #define SE_GPI_07_INT 39 | ||
| 159 | #define SE_SPI2_DATAIN_INT 38 | ||
| 160 | #define SE_GPI_10_INT 37 | ||
| 161 | #define SE_GPI_09_INT 36 | ||
| 162 | #define SE_GPI_08_INT 35 | ||
| 163 | /*34-32 unused*/ | ||
| 164 | |||
| 165 | /* Start Enable Internal Interrupts - table 57 page 65 */ | ||
| 166 | |||
| 167 | #define SE_INT_BASE_INT 0 | ||
| 168 | |||
| 169 | #define SE_TS_IRQ 31 | ||
| 170 | #define SE_TS_P_INT 30 | ||
| 171 | #define SE_TS_AUX_INT 29 | ||
| 172 | /*27-28 unused*/ | ||
| 173 | #define SE_USB_AHB_NEED_CLK_INT 26 | ||
| 174 | #define SE_MSTIMER_INT 25 | ||
| 175 | #define SE_RTC_INT 24 | ||
| 176 | #define SE_USB_NEED_CLK_INT 23 | ||
| 177 | #define SE_USB_INT 22 | ||
| 178 | #define SE_USB_I2C_INT 21 | ||
| 179 | #define SE_USB_OTG_TIMER_INT 20 | ||
| 180 | #define SE_USB_OTG_ATX_INT_N 19 | ||
| 181 | /*18 unused*/ | ||
| 182 | #define SE_DSP_GPIO4_INT 17 | ||
| 183 | #define SE_KEY_IRQ 16 | ||
| 184 | #define SE_DSP_SLAVEPORT_INT 15 | ||
| 185 | #define SE_DSP_GPIO1_INT 14 | ||
| 186 | #define SE_DSP_GPIO0_INT 13 | ||
| 187 | #define SE_DSP_AHB_INT 12 | ||
| 188 | /*11-6 unused*/ | ||
| 189 | #define SE_GPIO_05_INT 5 | ||
| 190 | #define SE_GPIO_04_INT 4 | ||
| 191 | #define SE_GPIO_03_INT 3 | ||
| 192 | #define SE_GPIO_02_INT 2 | ||
| 193 | #define SE_GPIO_01_INT 1 | ||
| 194 | #define SE_GPIO_00_INT 0 | ||
| 195 | |||
| 196 | #define START_INT_REG_BIT(irq) (1<<((irq)&0x1F)) | ||
| 197 | |||
| 198 | #define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1))) | ||
| 199 | #define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1))) | ||
| 200 | #define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1))) | ||
| 201 | #define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1))) | ||
| 202 | |||
| 203 | extern int pnx4008_gpio_register_pin(unsigned short pin); | ||
| 204 | extern int pnx4008_gpio_unregister_pin(unsigned short pin); | ||
| 205 | extern unsigned long pnx4008_gpio_read_pin(unsigned short pin); | ||
| 206 | extern int pnx4008_gpio_write_pin(unsigned short pin, int output); | ||
| 207 | extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output); | ||
| 208 | extern int pnx4008_gpio_read_pin_direction(unsigned short pin); | ||
| 209 | extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output); | ||
| 210 | extern int pnx4008_gpio_read_pin_mux(unsigned short pin); | ||
| 211 | |||
| 212 | static inline void start_int_umask(u8 irq) | ||
| 213 | { | ||
| 214 | __raw_writel(__raw_readl(START_INT_ER_REG(irq)) | | ||
| 215 | START_INT_REG_BIT(irq), START_INT_ER_REG(irq)); | ||
| 216 | } | ||
| 217 | |||
| 218 | static inline void start_int_mask(u8 irq) | ||
| 219 | { | ||
| 220 | __raw_writel(__raw_readl(START_INT_ER_REG(irq)) & | ||
| 221 | ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq)); | ||
| 222 | } | ||
| 223 | |||
| 224 | static inline void start_int_ack(u8 irq) | ||
| 225 | { | ||
| 226 | __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq)); | ||
| 227 | } | ||
| 228 | |||
| 229 | static inline void start_int_set_falling_edge(u8 irq) | ||
| 230 | { | ||
| 231 | __raw_writel(__raw_readl(START_INT_APR_REG(irq)) & | ||
| 232 | ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq)); | ||
| 233 | } | ||
| 234 | |||
| 235 | static inline void start_int_set_rising_edge(u8 irq) | ||
| 236 | { | ||
| 237 | __raw_writel(__raw_readl(START_INT_APR_REG(irq)) | | ||
| 238 | START_INT_REG_BIT(irq), START_INT_APR_REG(irq)); | ||
| 239 | } | ||
| 240 | |||
| 241 | #endif /* _PNX4008_GPIO_H_ */ | ||
diff --git a/include/asm-arm/arch-pnx4008/hardware.h b/include/asm-arm/arch-pnx4008/hardware.h deleted file mode 100644 index a4410397a921..000000000000 --- a/include/asm-arm/arch-pnx4008/hardware.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pnx4008/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 21 | #define __ASM_ARCH_HARDWARE_H | ||
| 22 | |||
| 23 | #include <asm/sizes.h> | ||
| 24 | #include <asm/arch/platform.h> | ||
| 25 | |||
| 26 | /* Start of virtual addresses for IO devices */ | ||
| 27 | #define IO_BASE 0xF0000000 | ||
| 28 | |||
| 29 | /* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */ | ||
| 30 | #define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE) | ||
| 31 | |||
| 32 | #endif | ||
diff --git a/include/asm-arm/arch-pnx4008/i2c.h b/include/asm-arm/arch-pnx4008/i2c.h deleted file mode 100644 index 92e8d65006f7..000000000000 --- a/include/asm-arm/arch-pnx4008/i2c.h +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * PNX4008-specific tweaks for I2C IP3204 block | ||
| 3 | * | ||
| 4 | * Author: Vitaly Wool <vwool@ru.mvista.com> | ||
| 5 | * | ||
| 6 | * 2005 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_I2C_H__ | ||
| 13 | #define __ASM_ARCH_I2C_H__ | ||
| 14 | |||
| 15 | #include <linux/pm.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | |||
| 18 | enum { | ||
| 19 | mstatus_tdi = 0x00000001, | ||
| 20 | mstatus_afi = 0x00000002, | ||
| 21 | mstatus_nai = 0x00000004, | ||
| 22 | mstatus_drmi = 0x00000008, | ||
| 23 | mstatus_active = 0x00000020, | ||
| 24 | mstatus_scl = 0x00000040, | ||
| 25 | mstatus_sda = 0x00000080, | ||
| 26 | mstatus_rff = 0x00000100, | ||
| 27 | mstatus_rfe = 0x00000200, | ||
| 28 | mstatus_tff = 0x00000400, | ||
| 29 | mstatus_tfe = 0x00000800, | ||
| 30 | }; | ||
| 31 | |||
| 32 | enum { | ||
| 33 | mcntrl_tdie = 0x00000001, | ||
| 34 | mcntrl_afie = 0x00000002, | ||
| 35 | mcntrl_naie = 0x00000004, | ||
| 36 | mcntrl_drmie = 0x00000008, | ||
| 37 | mcntrl_daie = 0x00000020, | ||
| 38 | mcntrl_rffie = 0x00000040, | ||
| 39 | mcntrl_tffie = 0x00000080, | ||
| 40 | mcntrl_reset = 0x00000100, | ||
| 41 | mcntrl_cdbmode = 0x00000400, | ||
| 42 | }; | ||
| 43 | |||
| 44 | enum { | ||
| 45 | rw_bit = 1 << 0, | ||
| 46 | start_bit = 1 << 8, | ||
| 47 | stop_bit = 1 << 9, | ||
| 48 | }; | ||
| 49 | |||
| 50 | #define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */ | ||
| 51 | #define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */ | ||
| 52 | #define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */ | ||
| 53 | #define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */ | ||
| 54 | #define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */ | ||
| 55 | #define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */ | ||
| 56 | #define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */ | ||
| 57 | #define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */ | ||
| 58 | #define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */ | ||
| 59 | #define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */ | ||
| 60 | #define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */ | ||
| 61 | #define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */ | ||
| 62 | #define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */ | ||
| 63 | |||
| 64 | #define HCLK_MHZ 13 | ||
| 65 | #define I2C_CHIP_NAME "PNX4008-I2C" | ||
| 66 | |||
| 67 | #endif /* __ASM_ARCH_I2C_H___ */ | ||
diff --git a/include/asm-arm/arch-pnx4008/io.h b/include/asm-arm/arch-pnx4008/io.h deleted file mode 100644 index 29ee43955c52..000000000000 --- a/include/asm-arm/arch-pnx4008/io.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | |||
| 2 | /* | ||
| 3 | * include/asm-arm/arch-pnx4008/io.h | ||
| 4 | * | ||
| 5 | * Author: Dmitry Chigirev <chigirev@ru.mvista.com> | ||
| 6 | * | ||
| 7 | * 2005 (c) MontaVista Software, Inc. This file is licensed under | ||
| 8 | * the terms of the GNU General Public License version 2. This program | ||
| 9 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 10 | * or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 14 | #define __ASM_ARM_ARCH_IO_H | ||
| 15 | |||
| 16 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 17 | |||
| 18 | #define __io(a) ((void __iomem *)(a)) | ||
| 19 | #define __mem_pci(a) (a) | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/include/asm-arm/arch-pnx4008/irq.h b/include/asm-arm/arch-pnx4008/irq.h deleted file mode 100644 index fabff5dc337f..000000000000 --- a/include/asm-arm/arch-pnx4008/irq.h +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pnx4008/irq.h | ||
| 3 | * | ||
| 4 | * PNX4008 IRQ controller driver - header file | ||
| 5 | * this one is used in entry-arnv.S as well so it cannot contain C code | ||
| 6 | * | ||
| 7 | * Copyright (c) 2005 Philips Semiconductors | ||
| 8 | * Copyright (c) 2005 MontaVista Software, Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | */ | ||
| 15 | #ifndef __PNX4008_IRQ_H__ | ||
| 16 | #define __PNX4008_IRQ_H__ | ||
| 17 | |||
| 18 | #define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) | ||
| 19 | #define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) | ||
| 20 | #define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) | ||
| 21 | |||
| 22 | /* Manual: Chapter 20, page 195 */ | ||
| 23 | |||
| 24 | #define INTC_BIT(irq) (1<< ((irq) & 0x1F)) | ||
| 25 | |||
| 26 | #define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9))) | ||
| 27 | #define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9))) | ||
| 28 | #define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9))) | ||
| 29 | #define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9))) | ||
| 30 | #define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9))) | ||
| 31 | #define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9))) | ||
| 32 | |||
| 33 | #define START_INT_REG_BIT(irq) (1<<((irq)&0x1F)) | ||
| 34 | |||
| 35 | #define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1))) | ||
| 36 | #define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1))) | ||
| 37 | #define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1))) | ||
| 38 | #define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1))) | ||
| 39 | |||
| 40 | extern void __init pnx4008_init_irq(void); | ||
| 41 | |||
| 42 | #endif /* __PNX4008_IRQ_H__ */ | ||
diff --git a/include/asm-arm/arch-pnx4008/irqs.h b/include/asm-arm/arch-pnx4008/irqs.h deleted file mode 100644 index a25d18f2d87a..000000000000 --- a/include/asm-arm/arch-pnx4008/irqs.h +++ /dev/null | |||
| @@ -1,215 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pnx4008/irqs.h | ||
| 3 | * | ||
| 4 | * PNX4008 IRQ controller driver - header file | ||
| 5 | * | ||
| 6 | * Author: Dmitry Chigirev <source@mvista.com> | ||
| 7 | * | ||
| 8 | * 2005 (c) MontaVista Software, Inc. This file is licensed under | ||
| 9 | * the terms of the GNU General Public License version 2. This program | ||
| 10 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 11 | * or implied. | ||
| 12 | */ | ||
| 13 | #ifndef __PNX4008_IRQS_h__ | ||
| 14 | #define __PNX4008_IRQS_h__ | ||
| 15 | |||
| 16 | #define NR_IRQS 96 | ||
| 17 | |||
| 18 | /*Manual: table 259, page 199*/ | ||
| 19 | |||
| 20 | /*SUB2 Interrupt Routing (SIC2)*/ | ||
| 21 | |||
| 22 | #define SIC2_BASE_INT 64 | ||
| 23 | |||
| 24 | #define CLK_SWITCH_ARM_INT 95 /*manual: Clkswitch ARM */ | ||
| 25 | #define CLK_SWITCH_DSP_INT 94 /*manual: ClkSwitch DSP */ | ||
| 26 | #define CLK_SWITCH_AUD_INT 93 /*manual: Clkswitch AUD */ | ||
| 27 | #define GPI_06_INT 92 | ||
| 28 | #define GPI_05_INT 91 | ||
| 29 | #define GPI_04_INT 90 | ||
| 30 | #define GPI_03_INT 89 | ||
| 31 | #define GPI_02_INT 88 | ||
| 32 | #define GPI_01_INT 87 | ||
| 33 | #define GPI_00_INT 86 | ||
| 34 | #define BT_CLKREQ_INT 85 | ||
| 35 | #define SPI1_DATIN_INT 84 | ||
| 36 | #define U5_RX_INT 83 | ||
| 37 | #define SDIO_INT_N 82 | ||
| 38 | #define CAM_HS_INT 81 | ||
| 39 | #define CAM_VS_INT 80 | ||
| 40 | #define GPI_07_INT 79 | ||
| 41 | #define DISP_SYNC_INT 78 | ||
| 42 | #define DSP_INT8 77 | ||
| 43 | #define U7_HCTS_INT 76 | ||
| 44 | #define GPI_10_INT 75 | ||
| 45 | #define GPI_09_INT 74 | ||
| 46 | #define GPI_08_INT 73 | ||
| 47 | #define DSP_INT7 72 | ||
| 48 | #define U2_HCTS_INT 71 | ||
| 49 | #define SPI2_DATIN_INT 70 | ||
| 50 | #define GPIO_05_INT 69 | ||
| 51 | #define GPIO_04_INT 68 | ||
| 52 | #define GPIO_03_INT 67 | ||
| 53 | #define GPIO_02_INT 66 | ||
| 54 | #define GPIO_01_INT 65 | ||
| 55 | #define GPIO_00_INT 64 | ||
| 56 | |||
| 57 | /*Manual: table 258, page 198*/ | ||
| 58 | |||
| 59 | /*SUB1 Interrupt Routing (SIC1)*/ | ||
| 60 | |||
| 61 | #define SIC1_BASE_INT 32 | ||
| 62 | |||
| 63 | #define USB_I2C_INT 63 | ||
| 64 | #define USB_DEV_HP_INT 62 | ||
| 65 | #define USB_DEV_LP_INT 61 | ||
| 66 | #define USB_DEV_DMA_INT 60 | ||
| 67 | #define USB_HOST_INT 59 | ||
| 68 | #define USB_OTG_ATX_INT_N 58 | ||
| 69 | #define USB_OTG_TIMER_INT 57 | ||
| 70 | #define SW_INT 56 | ||
| 71 | #define SPI1_INT 55 | ||
| 72 | #define KEY_IRQ 54 | ||
| 73 | #define DSP_M_INT 53 | ||
| 74 | #define RTC_INT 52 | ||
| 75 | #define I2C_1_INT 51 | ||
| 76 | #define I2C_2_INT 50 | ||
| 77 | #define PLL1_LOCK_INT 49 | ||
| 78 | #define PLL2_LOCK_INT 48 | ||
| 79 | #define PLL3_LOCK_INT 47 | ||
| 80 | #define PLL4_LOCK_INT 46 | ||
| 81 | #define PLL5_LOCK_INT 45 | ||
| 82 | #define SPI2_INT 44 | ||
| 83 | #define DSP_INT1 43 | ||
| 84 | #define DSP_INT2 42 | ||
| 85 | #define DSP_TDM_INT2 41 | ||
| 86 | #define TS_AUX_INT 40 | ||
| 87 | #define TS_IRQ 39 | ||
| 88 | #define TS_P_INT 38 | ||
| 89 | #define UOUT1_TO_PAD_INT 37 | ||
| 90 | #define GPI_11_INT 36 | ||
| 91 | #define DSP_INT4 35 | ||
| 92 | #define JTAG_COMM_RX_INT 34 | ||
| 93 | #define JTAG_COMM_TX_INT 33 | ||
| 94 | #define DSP_INT3 32 | ||
| 95 | |||
| 96 | /*Manual: table 257, page 197*/ | ||
| 97 | |||
| 98 | /*MAIN Interrupt Routing*/ | ||
| 99 | |||
| 100 | #define MAIN_BASE_INT 0 | ||
| 101 | |||
| 102 | #define SUB2_FIQ_N 31 /*active low */ | ||
| 103 | #define SUB1_FIQ_N 30 /*active low */ | ||
| 104 | #define JPEG_INT 29 | ||
| 105 | #define DMA_INT 28 | ||
| 106 | #define MSTIMER_INT 27 | ||
| 107 | #define IIR1_INT 26 | ||
| 108 | #define IIR2_INT 25 | ||
| 109 | #define IIR7_INT 24 | ||
| 110 | #define DSP_TDM_INT0 23 | ||
| 111 | #define DSP_TDM_INT1 22 | ||
| 112 | #define DSP_P_INT 21 | ||
| 113 | #define DSP_INT0 20 | ||
| 114 | #define DUM_INT 19 | ||
| 115 | #define UOUT0_TO_PAD_INT 18 | ||
| 116 | #define MP4_ENC_INT 17 | ||
| 117 | #define MP4_DEC_INT 16 | ||
| 118 | #define SD0_INT 15 | ||
| 119 | #define MBX_INT 14 | ||
| 120 | #define SD1_INT 13 | ||
| 121 | #define MS_INT_N 12 | ||
| 122 | #define FLASH_INT 11 /*NAND*/ | ||
| 123 | #define IIR6_INT 10 | ||
| 124 | #define IIR5_INT 9 | ||
| 125 | #define IIR4_INT 8 | ||
| 126 | #define IIR3_INT 7 | ||
| 127 | #define WATCH_INT 6 | ||
| 128 | #define HSTIMER_INT 5 | ||
| 129 | #define ARCH_TIMER_IRQ HSTIMER_INT | ||
| 130 | #define CAM_INT 4 | ||
| 131 | #define PRNG_INT 3 | ||
| 132 | #define CRYPTO_INT 2 | ||
| 133 | #define SUB2_IRQ_N 1 /*active low */ | ||
| 134 | #define SUB1_IRQ_N 0 /*active low */ | ||
| 135 | |||
| 136 | #define PNX4008_IRQ_TYPES \ | ||
| 137 | { /*IRQ #'s: */ \ | ||
| 138 | IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \ | ||
| 139 | IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \ | ||
| 140 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \ | ||
| 141 | IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \ | ||
| 142 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \ | ||
| 143 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \ | ||
| 144 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \ | ||
| 145 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \ | ||
| 146 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \ | ||
| 147 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \ | ||
| 148 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \ | ||
| 149 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \ | ||
| 150 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \ | ||
| 151 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \ | ||
| 152 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \ | ||
| 153 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \ | ||
| 154 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \ | ||
| 155 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \ | ||
| 156 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \ | ||
| 157 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \ | ||
| 158 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \ | ||
| 159 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \ | ||
| 160 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \ | ||
| 161 | IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \ | ||
| 162 | } | ||
| 163 | |||
| 164 | /* Start Enable Pin Interrupts - table 58 page 66 */ | ||
| 165 | |||
| 166 | #define SE_PIN_BASE_INT 32 | ||
| 167 | |||
| 168 | #define SE_U7_RX_INT 63 | ||
| 169 | #define SE_U7_HCTS_INT 62 | ||
| 170 | #define SE_BT_CLKREQ_INT 61 | ||
| 171 | #define SE_U6_IRRX_INT 60 | ||
| 172 | /*59 unused*/ | ||
| 173 | #define SE_U5_RX_INT 58 | ||
| 174 | #define SE_GPI_11_INT 57 | ||
| 175 | #define SE_U3_RX_INT 56 | ||
| 176 | #define SE_U2_HCTS_INT 55 | ||
| 177 | #define SE_U2_RX_INT 54 | ||
| 178 | #define SE_U1_RX_INT 53 | ||
| 179 | #define SE_DISP_SYNC_INT 52 | ||
| 180 | /*51 unused*/ | ||
| 181 | #define SE_SDIO_INT_N 50 | ||
| 182 | #define SE_MSDIO_START_INT 49 | ||
| 183 | #define SE_GPI_06_INT 48 | ||
| 184 | #define SE_GPI_05_INT 47 | ||
| 185 | #define SE_GPI_04_INT 46 | ||
| 186 | #define SE_GPI_03_INT 45 | ||
| 187 | #define SE_GPI_02_INT 44 | ||
| 188 | #define SE_GPI_01_INT 43 | ||
| 189 | #define SE_GPI_00_INT 42 | ||
| 190 | #define SE_SYSCLKEN_PIN_INT 41 | ||
| 191 | #define SE_SPI1_DATAIN_INT 40 | ||
| 192 | #define SE_GPI_07_INT 39 | ||
| 193 | #define SE_SPI2_DATAIN_INT 38 | ||
| 194 | #define SE_GPI_10_INT 37 | ||
| 195 | #define SE_GPI_09_INT 36 | ||
| 196 | #define SE_GPI_08_INT 35 | ||
| 197 | /*34-32 unused*/ | ||
| 198 | |||
| 199 | /* Start Enable Internal Interrupts - table 57 page 65 */ | ||
| 200 | |||
| 201 | #define SE_INT_BASE_INT 0 | ||
| 202 | |||
| 203 | #define SE_TS_IRQ 31 | ||
| 204 | #define SE_TS_P_INT 30 | ||
| 205 | #define SE_TS_AUX_INT 29 | ||
| 206 | /*27-28 unused*/ | ||
| 207 | #define SE_USB_AHB_NEED_CLK_INT 26 | ||
| 208 | #define SE_MSTIMER_INT 25 | ||
| 209 | #define SE_RTC_INT 24 | ||
| 210 | #define SE_USB_NEED_CLK_INT 23 | ||
| 211 | #define SE_USB_INT 22 | ||
| 212 | #define SE_USB_I2C_INT 21 | ||
| 213 | #define SE_USB_OTG_TIMER_INT 20 | ||
| 214 | |||
| 215 | #endif /* __PNX4008_IRQS_h__ */ | ||
diff --git a/include/asm-arm/arch-pnx4008/memory.h b/include/asm-arm/arch-pnx4008/memory.h deleted file mode 100644 index 0d8268a95261..000000000000 --- a/include/asm-arm/arch-pnx4008/memory.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pnx4008/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Philips Semiconductors | ||
| 5 | * Copyright (c) 2005 MontaVista Software, Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 14 | #define __ASM_ARCH_MEMORY_H | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Physical DRAM offset. | ||
| 18 | */ | ||
| 19 | #define PHYS_OFFSET (0x80000000) | ||
| 20 | |||
| 21 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) | ||
| 22 | #define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET) | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/include/asm-arm/arch-pnx4008/param.h b/include/asm-arm/arch-pnx4008/param.h deleted file mode 100644 index 95d5f547b416..000000000000 --- a/include/asm-arm/arch-pnx4008/param.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pnx4008/param.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #define HZ 100 | ||
diff --git a/include/asm-arm/arch-pnx4008/platform.h b/include/asm-arm/arch-pnx4008/platform.h deleted file mode 100644 index 2613c7c669b1..000000000000 --- a/include/asm-arm/arch-pnx4008/platform.h +++ /dev/null | |||
| @@ -1,69 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pnx4008/platform.h | ||
| 3 | * | ||
| 4 | * PNX4008 Base addresses - header file | ||
| 5 | * | ||
| 6 | * Author: Dmitry Chigirev <source@mvista.com> | ||
| 7 | * | ||
| 8 | * Based on reference code received from Philips: | ||
| 9 | * Copyright (C) 2003 Philips Semiconductors | ||
| 10 | * | ||
| 11 | * 2005 (c) MontaVista Software, Inc. This file is licensed under | ||
| 12 | * the terms of the GNU General Public License version 2. This program | ||
| 13 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 14 | * or implied. | ||
| 15 | */ | ||
| 16 | |||
| 17 | |||
| 18 | #ifndef __ASM_ARCH_PLATFORM_H__ | ||
| 19 | #define __ASM_ARCH_PLATFORM_H__ | ||
| 20 | |||
| 21 | #define PNX4008_IRAM_BASE 0x08000000 | ||
| 22 | #define PNX4008_IRAM_SIZE 0x00010000 | ||
| 23 | #define PNX4008_YUV_SLAVE_BASE 0x10000000 | ||
| 24 | #define PNX4008_DUM_SLAVE_BASE 0x18000000 | ||
| 25 | #define PNX4008_NDF_FLASH_BASE 0x20020000 | ||
| 26 | #define PNX4008_SPI1_BASE 0x20088000 | ||
| 27 | #define PNX4008_SPI2_BASE 0x20090000 | ||
| 28 | #define PNX4008_SD_CONFIG_BASE 0x20098000 | ||
| 29 | #define PNX4008_FLASH_DATA 0x200B0000 | ||
| 30 | #define PNX4008_MLC_FLASH_BASE 0x200B8000 | ||
| 31 | #define PNX4008_JPEG_CONFIG_BASE 0x300A0000 | ||
| 32 | #define PNX4008_DMA_CONFIG_BASE 0x31000000 | ||
| 33 | #define PNX4008_USB_CONFIG_BASE 0x31020000 | ||
| 34 | #define PNX4008_SDRAM_CFG_BASE 0x31080000 | ||
| 35 | #define PNX4008_AHB2FAB_BASE 0x40000000 | ||
| 36 | #define PNX4008_PWRMAN_BASE 0x40004000 | ||
| 37 | #define PNX4008_INTCTRLMIC_BASE 0x40008000 | ||
| 38 | #define PNX4008_INTCTRLSIC1_BASE 0x4000C000 | ||
| 39 | #define PNX4008_INTCTRLSIC2_BASE 0x40010000 | ||
| 40 | #define PNX4008_HSUART1_BASE 0x40014000 | ||
| 41 | #define PNX4008_HSUART2_BASE 0x40018000 | ||
| 42 | #define PNX4008_HSUART7_BASE 0x4001C000 | ||
| 43 | #define PNX4008_RTC_BASE 0x40024000 | ||
| 44 | #define PNX4008_PIO_BASE 0x40028000 | ||
| 45 | #define PNX4008_MSTIMER_BASE 0x40034000 | ||
| 46 | #define PNX4008_HSTIMER_BASE 0x40038000 | ||
| 47 | #define PNX4008_WDOG_BASE 0x4003C000 | ||
| 48 | #define PNX4008_DEBUG_BASE 0x40040000 | ||
| 49 | #define PNX4008_TOUCH1_BASE 0x40048000 | ||
| 50 | #define PNX4008_KEYSCAN_BASE 0x40050000 | ||
| 51 | #define PNX4008_UARTCTRL_BASE 0x40054000 | ||
| 52 | #define PNX4008_PWM_BASE 0x4005C000 | ||
| 53 | #define PNX4008_UART3_BASE 0x40080000 | ||
| 54 | #define PNX4008_UART4_BASE 0x40088000 | ||
| 55 | #define PNX4008_UART5_BASE 0x40090000 | ||
| 56 | #define PNX4008_UART6_BASE 0x40098000 | ||
| 57 | #define PNX4008_I2C1_BASE 0x400A0000 | ||
| 58 | #define PNX4008_I2C2_BASE 0x400A8000 | ||
| 59 | #define PNX4008_MAGICGATE_BASE 0x400B0000 | ||
| 60 | #define PNX4008_DUMCONF_BASE 0x400B8000 | ||
| 61 | #define PNX4008_DUM_MAINCFG_BASE 0x400BC000 | ||
| 62 | #define PNX4008_DSP_BASE 0x400C0000 | ||
| 63 | #define PNX4008_PROFCOUNTER_BASE 0x400C8000 | ||
| 64 | #define PNX4008_CRYPTO_BASE 0x400D0000 | ||
| 65 | #define PNX4008_CAMIFCONF_BASE 0x400D8000 | ||
| 66 | #define PNX4008_YUV2RGB_BASE 0x400E0000 | ||
| 67 | #define PNX4008_AUDIOCONFIG_BASE 0x400E8000 | ||
| 68 | |||
| 69 | #endif | ||
diff --git a/include/asm-arm/arch-pnx4008/pm.h b/include/asm-arm/arch-pnx4008/pm.h deleted file mode 100644 index bac1634cb3e0..000000000000 --- a/include/asm-arm/arch-pnx4008/pm.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pnx4008/pm.h | ||
| 3 | * | ||
| 4 | * PNX4008 Power Management Routiness - header file | ||
| 5 | * | ||
| 6 | * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com> | ||
| 7 | * | ||
| 8 | * 2005 (c) MontaVista Software, Inc. This file is licensed under | ||
| 9 | * the terms of the GNU General Public License version 2. This program | ||
| 10 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 11 | * or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_PNX4008_PM_H | ||
| 15 | #define __ASM_ARCH_PNX4008_PM_H | ||
| 16 | |||
| 17 | #ifndef __ASSEMBLER__ | ||
| 18 | #include "irq.h" | ||
| 19 | #include "irqs.h" | ||
| 20 | #include "clock.h" | ||
| 21 | |||
| 22 | extern void pnx4008_pm_idle(void); | ||
| 23 | extern void pnx4008_pm_suspend(void); | ||
| 24 | extern unsigned int pnx4008_cpu_suspend_sz; | ||
| 25 | extern void pnx4008_cpu_suspend(void); | ||
| 26 | extern unsigned int pnx4008_cpu_standby_sz; | ||
| 27 | extern void pnx4008_cpu_standby(void); | ||
| 28 | |||
| 29 | extern int pnx4008_startup_pll(struct clk *); | ||
| 30 | extern int pnx4008_shutdown_pll(struct clk *); | ||
| 31 | |||
| 32 | #endif /* ASSEMBLER */ | ||
| 33 | #endif /* __ASM_ARCH_PNX4008_PM_H */ | ||
diff --git a/include/asm-arm/arch-pnx4008/system.h b/include/asm-arm/arch-pnx4008/system.h deleted file mode 100644 index 17f9d7f9e5a1..000000000000 --- a/include/asm-arm/arch-pnx4008/system.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pnx4008/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 Philips Semiconductors | ||
| 5 | * Copyright (C) 2005 MontaVista Software, Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 22 | #define __ASM_ARCH_SYSTEM_H | ||
| 23 | |||
| 24 | #include <asm/arch/hardware.h> | ||
| 25 | #include <asm/io.h> | ||
| 26 | #include <asm/arch/platform.h> | ||
| 27 | |||
| 28 | static void arch_idle(void) | ||
| 29 | { | ||
| 30 | cpu_do_idle(); | ||
| 31 | } | ||
| 32 | |||
| 33 | static inline void arch_reset(char mode) | ||
| 34 | { | ||
| 35 | cpu_reset(0); | ||
| 36 | } | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-pnx4008/timex.h b/include/asm-arm/arch-pnx4008/timex.h deleted file mode 100644 index f22ee24a0219..000000000000 --- a/include/asm-arm/arch-pnx4008/timex.h +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pnx4008/timex.h | ||
| 3 | * | ||
| 4 | * PNX4008 timers header file | ||
| 5 | * | ||
| 6 | * Author: Dmitry Chigirev <source@mvista.com> | ||
| 7 | * | ||
| 8 | * 2005 (c) MontaVista Software, Inc. This file is licensed under | ||
| 9 | * the terms of the GNU General Public License version 2. This program | ||
| 10 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 11 | * or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __PNX4008_TIMEX_H | ||
| 15 | #define __PNX4008_TIMEX_H | ||
| 16 | |||
| 17 | #include <asm/arch/hardware.h> | ||
| 18 | #include <asm/io.h> | ||
| 19 | |||
| 20 | #define CLOCK_TICK_RATE 1000000 | ||
| 21 | |||
| 22 | #define TICKS2USECS(x) (x) | ||
| 23 | |||
| 24 | /* MilliSecond Timer - Chapter 21 Page 202 */ | ||
| 25 | |||
| 26 | #define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0)) | ||
| 27 | #define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4)) | ||
| 28 | #define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8)) | ||
| 29 | #define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14)) | ||
| 30 | #define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18)) | ||
| 31 | #define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c)) | ||
| 32 | |||
| 33 | /* High Speed Timer - Chpater 22, Page 205 */ | ||
| 34 | |||
| 35 | #define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0)) | ||
| 36 | #define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4)) | ||
| 37 | #define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8)) | ||
| 38 | #define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC)) | ||
| 39 | #define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10)) | ||
| 40 | #define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14)) | ||
| 41 | #define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18)) | ||
| 42 | #define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c)) | ||
| 43 | #define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20)) | ||
| 44 | #define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28)) | ||
| 45 | #define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C)) | ||
| 46 | #define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30)) | ||
| 47 | |||
| 48 | /* IMPORTANT: both timers are UPCOUNTING */ | ||
| 49 | |||
| 50 | /* xSTIM_MCTRL bit definitions */ | ||
| 51 | #define MR0_INT 1 | ||
| 52 | #define RESET_COUNT0 (1<<1) | ||
| 53 | #define STOP_COUNT0 (1<<2) | ||
| 54 | #define MR1_INT (1<<3) | ||
| 55 | #define RESET_COUNT1 (1<<4) | ||
| 56 | #define STOP_COUNT1 (1<<5) | ||
| 57 | #define MR2_INT (1<<6) | ||
| 58 | #define RESET_COUNT2 (1<<7) | ||
| 59 | #define STOP_COUNT2 (1<<8) | ||
| 60 | |||
| 61 | /* xSTIM_CTRL bit definitions */ | ||
| 62 | #define COUNT_ENAB 1 | ||
| 63 | #define RESET_COUNT (1<<1) | ||
| 64 | #define DEBUG_EN (1<<2) | ||
| 65 | |||
| 66 | /* xSTIM_INT bit definitions */ | ||
| 67 | #define MATCH0_INT 1 | ||
| 68 | #define MATCH1_INT (1<<1) | ||
| 69 | #define MATCH2_INT (1<<2) | ||
| 70 | #define RTC_TICK0 (1<<4) | ||
| 71 | #define RTC_TICK1 (1<<5) | ||
| 72 | |||
| 73 | #endif | ||
diff --git a/include/asm-arm/arch-pnx4008/uncompress.h b/include/asm-arm/arch-pnx4008/uncompress.h deleted file mode 100644 index 8fa4d24b72b4..000000000000 --- a/include/asm-arm/arch-pnx4008/uncompress.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pnx4008/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * Copyright (C) 2006 MontaVista Software, Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define UART5_BASE 0x40090000 | ||
| 23 | |||
| 24 | #define UART5_DR (*(volatile unsigned char *) (UART5_BASE)) | ||
| 25 | #define UART5_FR (*(volatile unsigned char *) (UART5_BASE + 18)) | ||
| 26 | |||
| 27 | static __inline__ void putc(char c) | ||
| 28 | { | ||
| 29 | while (UART5_FR & (1 << 5)) | ||
| 30 | barrier(); | ||
| 31 | |||
| 32 | UART5_DR = c; | ||
| 33 | } | ||
| 34 | |||
| 35 | /* | ||
| 36 | * This does not append a newline | ||
| 37 | */ | ||
| 38 | static inline void flush(void) | ||
| 39 | { | ||
| 40 | } | ||
| 41 | |||
| 42 | /* | ||
| 43 | * nothing to do | ||
| 44 | */ | ||
| 45 | #define arch_decomp_setup() | ||
| 46 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-pnx4008/vmalloc.h b/include/asm-arm/arch-pnx4008/vmalloc.h deleted file mode 100644 index 140d925f6f37..000000000000 --- a/include/asm-arm/arch-pnx4008/vmalloc.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pnx4008/vmalloc.h | ||
| 3 | * | ||
| 4 | * Author: Vitaly Wool <source@mvista.com> | ||
| 5 | * | ||
| 6 | * 2006 (c) MontaVista Software, Inc. This file is licensed under | ||
| 7 | * the terms of the GNU General Public License version 2. This program | ||
| 8 | * is licensed "as is" without any warranty of any kind, whether express | ||
| 9 | * or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Just any arbitrary offset to the start of the vmalloc VM area: the | ||
| 14 | * current 8MB value just means that there will be a 8MB "hole" after the | ||
| 15 | * physical memory until the kernel virtual memory starts. That means that | ||
| 16 | * any out-of-bounds memory accesses will hopefully be caught. | ||
| 17 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced | ||
| 18 | * area for the same reason. ;) | ||
| 19 | */ | ||
| 20 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
diff --git a/include/asm-arm/arch-pxa/akita.h b/include/asm-arm/arch-pxa/akita.h deleted file mode 100644 index 5d8cc1d9cb10..000000000000 --- a/include/asm-arm/arch-pxa/akita.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Hardware specific definitions for SL-C1000 (Akita) | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Richard Purdie | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* Akita IO Expander GPIOs */ | ||
| 13 | |||
| 14 | #define AKITA_IOEXP_RESERVED_7 (1 << 7) | ||
| 15 | #define AKITA_IOEXP_IR_ON (1 << 6) | ||
| 16 | #define AKITA_IOEXP_AKIN_PULLUP (1 << 5) | ||
| 17 | #define AKITA_IOEXP_BACKLIGHT_CONT (1 << 4) | ||
| 18 | #define AKITA_IOEXP_BACKLIGHT_ON (1 << 3) | ||
| 19 | #define AKITA_IOEXP_MIC_BIAS (1 << 2) | ||
| 20 | #define AKITA_IOEXP_RESERVED_1 (1 << 1) | ||
| 21 | #define AKITA_IOEXP_RESERVED_0 (1 << 0) | ||
| 22 | |||
| 23 | /* Direction Bitfield 0=output 1=input */ | ||
| 24 | #define AKITA_IOEXP_IO_DIR 0 | ||
| 25 | /* Default Values */ | ||
| 26 | #define AKITA_IOEXP_IO_OUT (AKITA_IOEXP_IR_ON | AKITA_IOEXP_AKIN_PULLUP) | ||
| 27 | |||
| 28 | extern struct platform_device akitaioexp_device; | ||
| 29 | |||
| 30 | void akita_set_ioexp(struct device *dev, unsigned char bitmask); | ||
| 31 | void akita_reset_ioexp(struct device *dev, unsigned char bitmask); | ||
| 32 | |||
diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h deleted file mode 100644 index f82f96dd1053..000000000000 --- a/include/asm-arm/arch-pxa/audio.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_AUDIO_H__ | ||
| 2 | #define __ASM_ARCH_AUDIO_H__ | ||
| 3 | |||
| 4 | #include <sound/core.h> | ||
| 5 | #include <sound/pcm.h> | ||
| 6 | |||
| 7 | typedef struct { | ||
| 8 | int (*startup)(struct snd_pcm_substream *, void *); | ||
| 9 | void (*shutdown)(struct snd_pcm_substream *, void *); | ||
| 10 | void (*suspend)(void *); | ||
| 11 | void (*resume)(void *); | ||
| 12 | void *priv; | ||
| 13 | } pxa2xx_audio_ops_t; | ||
| 14 | |||
| 15 | extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops); | ||
| 16 | |||
| 17 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h deleted file mode 100644 index f1f0e3387d9c..000000000000 --- a/include/asm-arm/arch-pxa/bitfield.h +++ /dev/null | |||
| @@ -1,113 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * FILE bitfield.h | ||
| 3 | * | ||
| 4 | * Version 1.1 | ||
| 5 | * Author Copyright (c) Marc A. Viredaz, 1998 | ||
| 6 | * DEC Western Research Laboratory, Palo Alto, CA | ||
| 7 | * Date April 1998 (April 1997) | ||
| 8 | * System Advanced RISC Machine (ARM) | ||
| 9 | * Language C or ARM Assembly | ||
| 10 | * Purpose Definition of macros to operate on bit fields. | ||
| 11 | */ | ||
| 12 | |||
| 13 | |||
| 14 | |||
| 15 | #ifndef __BITFIELD_H | ||
| 16 | #define __BITFIELD_H | ||
| 17 | |||
| 18 | #ifndef __ASSEMBLY__ | ||
| 19 | #define UData(Data) ((unsigned long) (Data)) | ||
| 20 | #else | ||
| 21 | #define UData(Data) (Data) | ||
| 22 | #endif | ||
| 23 | |||
| 24 | |||
| 25 | /* | ||
| 26 | * MACRO: Fld | ||
| 27 | * | ||
| 28 | * Purpose | ||
| 29 | * The macro "Fld" encodes a bit field, given its size and its shift value | ||
| 30 | * with respect to bit 0. | ||
| 31 | * | ||
| 32 | * Note | ||
| 33 | * A more intuitive way to encode bit fields would have been to use their | ||
| 34 | * mask. However, extracting size and shift value information from a bit | ||
| 35 | * field's mask is cumbersome and might break the assembler (255-character | ||
| 36 | * line-size limit). | ||
| 37 | * | ||
| 38 | * Input | ||
| 39 | * Size Size of the bit field, in number of bits. | ||
| 40 | * Shft Shift value of the bit field with respect to bit 0. | ||
| 41 | * | ||
| 42 | * Output | ||
| 43 | * Fld Encoded bit field. | ||
| 44 | */ | ||
| 45 | |||
| 46 | #define Fld(Size, Shft) (((Size) << 16) + (Shft)) | ||
| 47 | |||
| 48 | |||
| 49 | /* | ||
| 50 | * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit | ||
| 51 | * | ||
| 52 | * Purpose | ||
| 53 | * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return | ||
| 54 | * the size, shift value, mask, aligned mask, and first bit of a | ||
| 55 | * bit field. | ||
| 56 | * | ||
| 57 | * Input | ||
| 58 | * Field Encoded bit field (using the macro "Fld"). | ||
| 59 | * | ||
| 60 | * Output | ||
| 61 | * FSize Size of the bit field, in number of bits. | ||
| 62 | * FShft Shift value of the bit field with respect to bit 0. | ||
| 63 | * FMsk Mask for the bit field. | ||
| 64 | * FAlnMsk Mask for the bit field, aligned on bit 0. | ||
| 65 | * F1stBit First bit of the bit field. | ||
| 66 | */ | ||
| 67 | |||
| 68 | #define FSize(Field) ((Field) >> 16) | ||
| 69 | #define FShft(Field) ((Field) & 0x0000FFFF) | ||
| 70 | #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) | ||
| 71 | #define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) | ||
| 72 | #define F1stBit(Field) (UData (1) << FShft (Field)) | ||
| 73 | |||
| 74 | |||
| 75 | /* | ||
| 76 | * MACRO: FInsrt | ||
| 77 | * | ||
| 78 | * Purpose | ||
| 79 | * The macro "FInsrt" inserts a value into a bit field by shifting the | ||
| 80 | * former appropriately. | ||
| 81 | * | ||
| 82 | * Input | ||
| 83 | * Value Bit-field value. | ||
| 84 | * Field Encoded bit field (using the macro "Fld"). | ||
| 85 | * | ||
| 86 | * Output | ||
| 87 | * FInsrt Bit-field value positioned appropriately. | ||
| 88 | */ | ||
| 89 | |||
| 90 | #define FInsrt(Value, Field) \ | ||
| 91 | (UData (Value) << FShft (Field)) | ||
| 92 | |||
| 93 | |||
| 94 | /* | ||
| 95 | * MACRO: FExtr | ||
| 96 | * | ||
| 97 | * Purpose | ||
| 98 | * The macro "FExtr" extracts the value of a bit field by masking and | ||
| 99 | * shifting it appropriately. | ||
| 100 | * | ||
| 101 | * Input | ||
| 102 | * Data Data containing the bit-field to be extracted. | ||
| 103 | * Field Encoded bit field (using the macro "Fld"). | ||
| 104 | * | ||
| 105 | * Output | ||
| 106 | * FExtr Bit-field value. | ||
| 107 | */ | ||
| 108 | |||
| 109 | #define FExtr(Data, Field) \ | ||
| 110 | ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) | ||
| 111 | |||
| 112 | |||
| 113 | #endif /* __BITFIELD_H */ | ||
diff --git a/include/asm-arm/arch-pxa/camera.h b/include/asm-arm/arch-pxa/camera.h deleted file mode 100644 index 39516ced8b1f..000000000000 --- a/include/asm-arm/arch-pxa/camera.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | camera.h - PXA camera driver header file | ||
| 3 | |||
| 4 | Copyright (C) 2003, Intel Corporation | ||
| 5 | Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | ||
| 6 | |||
| 7 | This program is free software; you can redistribute it and/or modify | ||
| 8 | it under the terms of the GNU General Public License as published by | ||
| 9 | the Free Software Foundation; either version 2 of the License, or | ||
| 10 | (at your option) any later version. | ||
| 11 | |||
| 12 | This program is distributed in the hope that it will be useful, | ||
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | GNU General Public License for more details. | ||
| 16 | |||
| 17 | You should have received a copy of the GNU General Public License | ||
| 18 | along with this program; if not, write to the Free Software | ||
| 19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __ASM_ARCH_CAMERA_H_ | ||
| 23 | #define __ASM_ARCH_CAMERA_H_ | ||
| 24 | |||
| 25 | #define PXA_CAMERA_MASTER 1 | ||
| 26 | #define PXA_CAMERA_DATAWIDTH_4 2 | ||
| 27 | #define PXA_CAMERA_DATAWIDTH_5 4 | ||
| 28 | #define PXA_CAMERA_DATAWIDTH_8 8 | ||
| 29 | #define PXA_CAMERA_DATAWIDTH_9 0x10 | ||
| 30 | #define PXA_CAMERA_DATAWIDTH_10 0x20 | ||
| 31 | #define PXA_CAMERA_PCLK_EN 0x40 | ||
| 32 | #define PXA_CAMERA_MCLK_EN 0x80 | ||
| 33 | #define PXA_CAMERA_PCP 0x100 | ||
| 34 | #define PXA_CAMERA_HSP 0x200 | ||
| 35 | #define PXA_CAMERA_VSP 0x400 | ||
| 36 | |||
| 37 | struct pxacamera_platform_data { | ||
| 38 | int (*init)(struct device *); | ||
| 39 | int (*power)(struct device *, int); | ||
| 40 | int (*reset)(struct device *, int); | ||
| 41 | |||
| 42 | unsigned long flags; | ||
| 43 | unsigned long mclk_10khz; | ||
| 44 | }; | ||
| 45 | |||
| 46 | extern void pxa_set_camera_info(struct pxacamera_platform_data *); | ||
| 47 | |||
| 48 | #endif /* __ASM_ARCH_CAMERA_H_ */ | ||
diff --git a/include/asm-arm/arch-pxa/colibri.h b/include/asm-arm/arch-pxa/colibri.h deleted file mode 100644 index 2ae373fb5675..000000000000 --- a/include/asm-arm/arch-pxa/colibri.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | #ifndef _COLIBRI_H_ | ||
| 2 | #define _COLIBRI_H_ | ||
| 3 | |||
| 4 | /* physical memory regions */ | ||
| 5 | #define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ | ||
| 6 | #define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ | ||
| 7 | #define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ | ||
| 8 | |||
| 9 | /* virtual memory regions */ | ||
| 10 | #define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */ | ||
| 11 | |||
| 12 | /* size of flash */ | ||
| 13 | #define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ | ||
| 14 | |||
| 15 | /* Ethernet Controller Davicom DM9000 */ | ||
| 16 | #define GPIO_DM9000 114 | ||
| 17 | #define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000) | ||
| 18 | |||
| 19 | #endif /* _COLIBRI_H_ */ | ||
diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h deleted file mode 100644 index bf856503baf6..000000000000 --- a/include/asm-arm/arch-pxa/corgi.h +++ /dev/null | |||
| @@ -1,109 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Hardware specific definitions for SL-C7xx series of PDAs | ||
| 3 | * | ||
| 4 | * Copyright (c) 2004-2005 Richard Purdie | ||
| 5 | * | ||
| 6 | * Based on Sharp's 2.4 kernel patches | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #ifndef __ASM_ARCH_CORGI_H | ||
| 14 | #define __ASM_ARCH_CORGI_H 1 | ||
| 15 | |||
| 16 | |||
| 17 | /* | ||
| 18 | * Corgi (Non Standard) GPIO Definitions | ||
| 19 | */ | ||
| 20 | #define CORGI_GPIO_KEY_INT (0) /* Keyboard Interrupt */ | ||
| 21 | #define CORGI_GPIO_AC_IN (1) /* Charger Detection */ | ||
| 22 | #define CORGI_GPIO_WAKEUP (3) /* System wakeup notification? */ | ||
| 23 | #define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */ | ||
| 24 | #define CORGI_GPIO_TP_INT (5) /* Touch Panel Interrupt */ | ||
| 25 | #define CORGI_GPIO_nSD_WP (7) /* SD Write Protect? */ | ||
| 26 | #define CORGI_GPIO_nSD_DETECT (9) /* MMC/SD Card Detect */ | ||
| 27 | #define CORGI_GPIO_nSD_INT (10) /* SD Interrupt for SDIO? */ | ||
| 28 | #define CORGI_GPIO_MAIN_BAT_LOW (11) /* Main Battery Low Notification */ | ||
| 29 | #define CORGI_GPIO_BAT_COVER (11) /* Battery Cover Detect */ | ||
| 30 | #define CORGI_GPIO_LED_ORANGE (13) /* Orange LED Control */ | ||
| 31 | #define CORGI_GPIO_CF_CD (14) /* Compact Flash Card Detect */ | ||
| 32 | #define CORGI_GPIO_CHRG_FULL (16) /* Charging Complete Notification */ | ||
| 33 | #define CORGI_GPIO_CF_IRQ (17) /* Compact Flash Interrupt */ | ||
| 34 | #define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */ | ||
| 35 | #define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */ | ||
| 36 | #define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */ | ||
| 37 | #define CORGI_GPIO_IR_ON (22) /* Enable IR Transciever */ | ||
| 38 | #define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */ | ||
| 39 | #define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */ | ||
| 40 | #define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */ | ||
| 41 | #define CORGI_GPIO_DISCHARGE_ON (42) /* Enable battery Discharge */ | ||
| 42 | #define CORGI_GPIO_CHRG_UKN (43) /* Unknown Charging (Bypass Control?) */ | ||
| 43 | #define CORGI_GPIO_HSYNC (44) /* LCD HSync Pulse */ | ||
| 44 | #define CORGI_GPIO_USB_PULLUP (45) /* USB show presence to host */ | ||
| 45 | |||
| 46 | |||
| 47 | /* | ||
| 48 | * Corgi Keyboard Definitions | ||
| 49 | */ | ||
| 50 | #define CORGI_KEY_STROBE_NUM (12) | ||
| 51 | #define CORGI_KEY_SENSE_NUM (8) | ||
| 52 | #define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc) | ||
| 53 | #define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000) | ||
| 54 | #define CORGI_GPIO_HIGH_SENSE_RSHIFT (26) | ||
| 55 | #define CORGI_GPIO_LOW_SENSE_BIT (0x00000003) | ||
| 56 | #define CORGI_GPIO_LOW_SENSE_LSHIFT (6) | ||
| 57 | #define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a)) | ||
| 58 | #define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a)) | ||
| 59 | #define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0) | ||
| 60 | #define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000) | ||
| 61 | #define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f) | ||
| 62 | #define CORGI_GPIO_KEY_SENSE(a) (58+(a)) | ||
| 63 | #define CORGI_GPIO_KEY_STROBE(a) (66+(a)) | ||
| 64 | |||
| 65 | |||
| 66 | /* | ||
| 67 | * Corgi Interrupts | ||
| 68 | */ | ||
| 69 | #define CORGI_IRQ_GPIO_KEY_INT IRQ_GPIO(0) | ||
| 70 | #define CORGI_IRQ_GPIO_AC_IN IRQ_GPIO(1) | ||
| 71 | #define CORGI_IRQ_GPIO_WAKEUP IRQ_GPIO(3) | ||
| 72 | #define CORGI_IRQ_GPIO_AK_INT IRQ_GPIO(4) | ||
| 73 | #define CORGI_IRQ_GPIO_TP_INT IRQ_GPIO(5) | ||
| 74 | #define CORGI_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) | ||
| 75 | #define CORGI_IRQ_GPIO_nSD_INT IRQ_GPIO(10) | ||
| 76 | #define CORGI_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(11) | ||
| 77 | #define CORGI_IRQ_GPIO_CF_CD IRQ_GPIO(14) | ||
| 78 | #define CORGI_IRQ_GPIO_CHRG_FULL IRQ_GPIO(16) /* Battery fully charged */ | ||
| 79 | #define CORGI_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) | ||
| 80 | #define CORGI_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(58+(a)) /* Keyboard Sense lines */ | ||
| 81 | |||
| 82 | |||
| 83 | /* | ||
| 84 | * Corgi SCOOP GPIOs and Config | ||
| 85 | */ | ||
| 86 | #define CORGI_SCP_LED_GREEN SCOOP_GPCR_PA11 | ||
| 87 | #define CORGI_SCP_SWA SCOOP_GPCR_PA12 /* Hinge Switch A */ | ||
| 88 | #define CORGI_SCP_SWB SCOOP_GPCR_PA13 /* Hinge Switch B */ | ||
| 89 | #define CORGI_SCP_MUTE_L SCOOP_GPCR_PA14 | ||
| 90 | #define CORGI_SCP_MUTE_R SCOOP_GPCR_PA15 | ||
| 91 | #define CORGI_SCP_AKIN_PULLUP SCOOP_GPCR_PA16 | ||
| 92 | #define CORGI_SCP_APM_ON SCOOP_GPCR_PA17 | ||
| 93 | #define CORGI_SCP_BACKLIGHT_CONT SCOOP_GPCR_PA18 | ||
| 94 | #define CORGI_SCP_MIC_BIAS SCOOP_GPCR_PA19 | ||
| 95 | |||
| 96 | #define CORGI_SCOOP_IO_DIR ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \ | ||
| 97 | CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \ | ||
| 98 | CORGI_SCP_MIC_BIAS ) | ||
| 99 | #define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) | ||
| 100 | |||
| 101 | |||
| 102 | /* | ||
| 103 | * Shared data structures | ||
| 104 | */ | ||
| 105 | extern struct platform_device corgiscoop_device; | ||
| 106 | extern struct platform_device corgissp_device; | ||
| 107 | |||
| 108 | #endif /* __ASM_ARCH_CORGI_H */ | ||
| 109 | |||
diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S deleted file mode 100644 index 9012cbc0ad8b..000000000000 --- a/include/asm-arm/arch-pxa/debug-macro.S +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-pxa/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include "hardware.h" | ||
| 15 | |||
| 16 | .macro addruart,rx | ||
| 17 | mrc p15, 0, \rx, c1, c0 | ||
| 18 | tst \rx, #1 @ MMU enabled? | ||
| 19 | moveq \rx, #0x40000000 @ physical | ||
| 20 | movne \rx, #io_p2v(0x40000000) @ virtual | ||
| 21 | orr \rx, \rx, #0x00100000 | ||
| 22 | .endm | ||
| 23 | |||
| 24 | #define UART_SHIFT 2 | ||
| 25 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h deleted file mode 100644 index dbe110ee2666..000000000000 --- a/include/asm-arm/arch-pxa/dma.h +++ /dev/null | |||
| @@ -1,50 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/dma.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Jun 15, 2001 | ||
| 6 | * Copyright: MontaVista Software, Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | #ifndef __ASM_ARCH_DMA_H | ||
| 13 | #define __ASM_ARCH_DMA_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Descriptor structure for PXA's DMA engine | ||
| 17 | * Note: this structure must always be aligned to a 16-byte boundary. | ||
| 18 | */ | ||
| 19 | |||
| 20 | typedef struct pxa_dma_desc { | ||
| 21 | volatile u32 ddadr; /* Points to the next descriptor + flags */ | ||
| 22 | volatile u32 dsadr; /* DSADR value for the current transfer */ | ||
| 23 | volatile u32 dtadr; /* DTADR value for the current transfer */ | ||
| 24 | volatile u32 dcmd; /* DCMD value for the current transfer */ | ||
| 25 | } pxa_dma_desc; | ||
| 26 | |||
| 27 | typedef enum { | ||
| 28 | DMA_PRIO_HIGH = 0, | ||
| 29 | DMA_PRIO_MEDIUM = 1, | ||
| 30 | DMA_PRIO_LOW = 2 | ||
| 31 | } pxa_dma_prio; | ||
| 32 | |||
| 33 | #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) | ||
| 34 | #define HAVE_ARCH_PCI_SET_DMA_MASK 1 | ||
| 35 | #endif | ||
| 36 | |||
| 37 | /* | ||
| 38 | * DMA registration | ||
| 39 | */ | ||
| 40 | |||
| 41 | int __init pxa_init_dma(int num_ch); | ||
| 42 | |||
| 43 | int pxa_request_dma (char *name, | ||
| 44 | pxa_dma_prio prio, | ||
| 45 | void (*irq_handler)(int, void *), | ||
| 46 | void *data); | ||
| 47 | |||
| 48 | void pxa_free_dma (int dma_ch); | ||
| 49 | |||
| 50 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S deleted file mode 100644 index 897d164da223..000000000000 --- a/include/asm-arm/arch-pxa/entry-macro.S +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pxa/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for PXA-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | #include <asm/arch/irqs.h> | ||
| 12 | |||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro get_irqnr_preamble, base, tmp | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 23 | mrc p15, 0, \tmp, c0, c0, 0 @ CPUID | ||
| 24 | mov \tmp, \tmp, lsr #13 | ||
| 25 | and \tmp, \tmp, #0x7 @ Core G | ||
| 26 | cmp \tmp, #1 | ||
| 27 | bhi 1004f | ||
| 28 | |||
| 29 | mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 | ||
| 30 | add \base, \base, #0x00d00000 | ||
| 31 | ldr \irqstat, [\base, #0] @ ICIP | ||
| 32 | ldr \irqnr, [\base, #4] @ ICMR | ||
| 33 | b 1002f | ||
| 34 | |||
| 35 | 1004: | ||
| 36 | mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2 | ||
| 37 | mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2 | ||
| 38 | ands \irqnr, \irqstat, \irqnr | ||
| 39 | beq 1003f | ||
| 40 | rsb \irqstat, \irqnr, #0 | ||
| 41 | and \irqstat, \irqstat, \irqnr | ||
| 42 | clz \irqnr, \irqstat | ||
| 43 | rsb \irqnr, \irqnr, #31 | ||
| 44 | add \irqnr, \irqnr, #32 | ||
| 45 | b 1001f | ||
| 46 | 1003: | ||
| 47 | mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP | ||
| 48 | mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR | ||
| 49 | 1002: | ||
| 50 | ands \irqnr, \irqstat, \irqnr | ||
| 51 | beq 1001f | ||
| 52 | rsb \irqstat, \irqnr, #0 | ||
| 53 | and \irqstat, \irqstat, \irqnr | ||
| 54 | clz \irqnr, \irqstat | ||
| 55 | rsb \irqnr, \irqnr, #31 | ||
| 56 | 1001: | ||
| 57 | .endm | ||
diff --git a/include/asm-arm/arch-pxa/eseries-gpio.h b/include/asm-arm/arch-pxa/eseries-gpio.h deleted file mode 100644 index 4c90b1310270..000000000000 --- a/include/asm-arm/arch-pxa/eseries-gpio.h +++ /dev/null | |||
| @@ -1,50 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * eseries-gpio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) Ian Molton <spyro@f2s.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* e-series power button */ | ||
| 13 | #define GPIO_ESERIES_POWERBTN 0 | ||
| 14 | |||
| 15 | /* UDC GPIO definitions */ | ||
| 16 | #define GPIO_E7XX_USB_DISC 13 | ||
| 17 | #define GPIO_E7XX_USB_PULLUP 3 | ||
| 18 | |||
| 19 | #define GPIO_E800_USB_DISC 4 | ||
| 20 | #define GPIO_E800_USB_PULLUP 84 | ||
| 21 | |||
| 22 | /* e740 PCMCIA GPIO definitions */ | ||
| 23 | /* Note: PWR1 seems to be inverted */ | ||
| 24 | #define GPIO_E740_PCMCIA_CD0 8 | ||
| 25 | #define GPIO_E740_PCMCIA_CD1 44 | ||
| 26 | #define GPIO_E740_PCMCIA_RDY0 11 | ||
| 27 | #define GPIO_E740_PCMCIA_RDY1 6 | ||
| 28 | #define GPIO_E740_PCMCIA_RST0 27 | ||
| 29 | #define GPIO_E740_PCMCIA_RST1 24 | ||
| 30 | #define GPIO_E740_PCMCIA_PWR0 20 | ||
| 31 | #define GPIO_E740_PCMCIA_PWR1 23 | ||
| 32 | |||
| 33 | /* e750 PCMCIA GPIO definitions */ | ||
| 34 | #define GPIO_E750_PCMCIA_CD0 8 | ||
| 35 | #define GPIO_E750_PCMCIA_RDY0 12 | ||
| 36 | #define GPIO_E750_PCMCIA_RST0 27 | ||
| 37 | #define GPIO_E750_PCMCIA_PWR0 20 | ||
| 38 | |||
| 39 | /* e800 PCMCIA GPIO definitions */ | ||
| 40 | #define GPIO_E800_PCMCIA_RST0 69 | ||
| 41 | #define GPIO_E800_PCMCIA_RST1 72 | ||
| 42 | #define GPIO_E800_PCMCIA_PWR0 20 | ||
| 43 | #define GPIO_E800_PCMCIA_PWR1 73 | ||
| 44 | |||
| 45 | /* e7xx IrDA power control */ | ||
| 46 | #define GPIO_E7XX_IR_ON 38 | ||
| 47 | |||
| 48 | /* ASIC related GPIOs */ | ||
| 49 | #define GPIO_ESERIES_TMIO_IRQ 5 | ||
| 50 | #define GPIO_E800_ANGELX_IRQ 8 | ||
diff --git a/include/asm-arm/arch-pxa/eseries-irq.h b/include/asm-arm/arch-pxa/eseries-irq.h deleted file mode 100644 index f2a93d5e31d3..000000000000 --- a/include/asm-arm/arch-pxa/eseries-irq.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * eseries-irq.h | ||
| 3 | * | ||
| 4 | * Copyright (C) Ian Molton <spyro@f2s.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #define ANGELX_IRQ_BASE (IRQ_BOARD_START+8) | ||
| 13 | #define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n)) | ||
| 14 | |||
| 15 | #define ANGELX_RDY0_IRQ IRQ_ANGELX(0) | ||
| 16 | #define ANGELX_ST0_IRQ IRQ_ANGELX(1) | ||
| 17 | #define ANGELX_CD0_IRQ IRQ_ANGELX(2) | ||
| 18 | #define ANGELX_RDY1_IRQ IRQ_ANGELX(3) | ||
| 19 | #define ANGELX_ST1_IRQ IRQ_ANGELX(4) | ||
| 20 | #define ANGELX_CD1_IRQ IRQ_ANGELX(5) | ||
| 21 | |||
| 22 | #define TMIO_IRQ_BASE (IRQ_BOARD_START+0) | ||
| 23 | #define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n)) | ||
| 24 | |||
| 25 | #define TMIO_SD_IRQ IRQ_TMIO(1) | ||
| 26 | #define TMIO_USB_IRQ IRQ_TMIO(2) | ||
| 27 | |||
diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h deleted file mode 100644 index 2c1e3d8ad7a2..000000000000 --- a/include/asm-arm/arch-pxa/gpio.h +++ /dev/null | |||
| @@ -1,65 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/gpio.h | ||
| 3 | * | ||
| 4 | * PXA GPIO wrappers for arch-neutral GPIO calls | ||
| 5 | * | ||
| 6 | * Written by Philipp Zabel <philipp.zabel@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | * | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef __ASM_ARCH_PXA_GPIO_H | ||
| 25 | #define __ASM_ARCH_PXA_GPIO_H | ||
| 26 | |||
| 27 | #include <asm/arch/pxa-regs.h> | ||
| 28 | #include <asm/irq.h> | ||
| 29 | #include <asm/arch/hardware.h> | ||
| 30 | |||
| 31 | #include <asm-generic/gpio.h> | ||
| 32 | |||
| 33 | |||
| 34 | /* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). | ||
| 35 | * Those cases currently cause holes in the GPIO number space. | ||
| 36 | */ | ||
| 37 | #define NR_BUILTIN_GPIO 128 | ||
| 38 | |||
| 39 | static inline int gpio_get_value(unsigned gpio) | ||
| 40 | { | ||
| 41 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) | ||
| 42 | return GPLR(gpio) & GPIO_bit(gpio); | ||
| 43 | else | ||
| 44 | return __gpio_get_value(gpio); | ||
| 45 | } | ||
| 46 | |||
| 47 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 48 | { | ||
| 49 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { | ||
| 50 | if (value) | ||
| 51 | GPSR(gpio) = GPIO_bit(gpio); | ||
| 52 | else | ||
| 53 | GPCR(gpio) = GPIO_bit(gpio); | ||
| 54 | } else { | ||
| 55 | __gpio_set_value(gpio, value); | ||
| 56 | } | ||
| 57 | } | ||
| 58 | |||
| 59 | #define gpio_cansleep __gpio_cansleep | ||
| 60 | |||
| 61 | #define gpio_to_irq(gpio) IRQ_GPIO(gpio) | ||
| 62 | #define irq_to_gpio(irq) IRQ_TO_GPIO(irq) | ||
| 63 | |||
| 64 | |||
| 65 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/gumstix.h b/include/asm-arm/arch-pxa/gumstix.h deleted file mode 100644 index 6fa85c4f94f8..000000000000 --- a/include/asm-arm/arch-pxa/gumstix.h +++ /dev/null | |||
| @@ -1,96 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/gumstix.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | /* BTRESET - Reset line to Bluetooth module, active low signal. */ | ||
| 11 | #define GPIO_GUMSTIX_BTRESET 7 | ||
| 12 | #define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT) | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean | ||
| 17 | interrupt signal for determining cable presence. On the original gumstix, | ||
| 18 | this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F, | ||
| 19 | this moves to GPIO17 and GPIO37. */ | ||
| 20 | |||
| 21 | /* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn | ||
| 22 | has detected a cable insertion; driven low otherwise. */ | ||
| 23 | |||
| 24 | #ifdef CONFIG_ARCH_GUMSTIX_ORIG | ||
| 25 | |||
| 26 | #define GPIO_GUMSTIX_USB_GPIOn 81 | ||
| 27 | #define GPIO_GUMSTIX_USB_GPIOx 83 | ||
| 28 | |||
| 29 | #else | ||
| 30 | |||
| 31 | #define GPIO_GUMSTIX_USB_GPIOn 35 | ||
| 32 | #define GPIO_GUMSTIX_USB_GPIOx 41 | ||
| 33 | |||
| 34 | #endif | ||
| 35 | |||
| 36 | /* usb state change */ | ||
| 37 | #define GUMSTIX_USB_INTR_IRQ IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn) | ||
| 38 | |||
| 39 | #define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN) | ||
| 40 | #define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT) | ||
| 41 | #define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * SD/MMC definitions | ||
| 45 | */ | ||
| 46 | #define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */ | ||
| 47 | #define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */ | ||
| 48 | #define GUMSTIX_IRQ_GPIO_nSD_DETECT IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * SMC Ethernet definitions | ||
| 52 | * ETH_RST provides a hardware reset line to the ethernet chip | ||
| 53 | * ETH is the IRQ line in from the ethernet chip to the PXA | ||
| 54 | */ | ||
| 55 | #define GPIO_GUMSTIX_ETH0_RST 80 | ||
| 56 | #define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT) | ||
| 57 | #define GPIO_GUMSTIX_ETH1_RST 52 | ||
| 58 | #define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT) | ||
| 59 | |||
| 60 | #define GPIO_GUMSTIX_ETH0 36 | ||
| 61 | #define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN) | ||
| 62 | #define GUMSTIX_ETH0_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH0) | ||
| 63 | #define GPIO_GUMSTIX_ETH1 27 | ||
| 64 | #define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN) | ||
| 65 | #define GUMSTIX_ETH1_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH1) | ||
| 66 | |||
| 67 | |||
| 68 | /* CF reset line */ | ||
| 69 | #define GPIO8_RESET 8 | ||
| 70 | |||
| 71 | /* CF slot 0 */ | ||
| 72 | #define GPIO4_nBVD1 4 | ||
| 73 | #define GPIO4_nSTSCHG GPIO4_nBVD1 | ||
| 74 | #define GPIO11_nCD 11 | ||
| 75 | #define GPIO26_PRDY_nBSY 26 | ||
| 76 | #define GUMSTIX_S0_nSTSCHG_IRQ IRQ_GPIO(GPIO4_nSTSCHG) | ||
| 77 | #define GUMSTIX_S0_nCD_IRQ IRQ_GPIO(GPIO11_nCD) | ||
| 78 | #define GUMSTIX_S0_PRDY_nBSY_IRQ IRQ_GPIO(GPIO26_PRDY_nBSY) | ||
| 79 | |||
| 80 | /* CF slot 1 */ | ||
| 81 | #define GPIO18_nBVD1 18 | ||
| 82 | #define GPIO18_nSTSCHG GPIO18_nBVD1 | ||
| 83 | #define GPIO36_nCD 36 | ||
| 84 | #define GPIO27_PRDY_nBSY 27 | ||
| 85 | #define GUMSTIX_S1_nSTSCHG_IRQ IRQ_GPIO(GPIO18_nSTSCHG) | ||
| 86 | #define GUMSTIX_S1_nCD_IRQ IRQ_GPIO(GPIO36_nCD) | ||
| 87 | #define GUMSTIX_S1_PRDY_nBSY_IRQ IRQ_GPIO(GPIO27_PRDY_nBSY) | ||
| 88 | |||
| 89 | /* CF GPIO line modes */ | ||
| 90 | #define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN) | ||
| 91 | #define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT) | ||
| 92 | #define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN) | ||
| 93 | #define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN) | ||
| 94 | #define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN) | ||
| 95 | #define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN) | ||
| 96 | #define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN) | ||
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h deleted file mode 100644 index 979a45695d7d..000000000000 --- a/include/asm-arm/arch-pxa/hardware.h +++ /dev/null | |||
| @@ -1,240 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/hardware.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Jun 15, 2001 | ||
| 6 | * Copyright: MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 14 | #define __ASM_ARCH_HARDWARE_H | ||
| 15 | |||
| 16 | /* | ||
| 17 | * We requires absolute addresses. | ||
| 18 | */ | ||
| 19 | #define PCIO_BASE 0 | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Workarounds for at least 2 errata so far require this. | ||
| 23 | * The mapping is set in mach-pxa/generic.c. | ||
| 24 | */ | ||
| 25 | #define UNCACHED_PHYS_0 0xff000000 | ||
| 26 | #define UNCACHED_ADDR UNCACHED_PHYS_0 | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Intel PXA2xx internal register mapping: | ||
| 30 | * | ||
| 31 | * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff | ||
| 32 | * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff | ||
| 33 | * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff | ||
| 34 | * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff | ||
| 35 | * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff | ||
| 36 | * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff | ||
| 37 | * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff | ||
| 38 | * | ||
| 39 | * Note that not all PXA2xx chips implement all those addresses, and the | ||
| 40 | * kernel only maps the minimum needed range of this mapping. | ||
| 41 | */ | ||
| 42 | #define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) | ||
| 43 | #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) | ||
| 44 | |||
| 45 | #ifndef __ASSEMBLY__ | ||
| 46 | |||
| 47 | # define __REG(x) (*((volatile u32 *)io_p2v(x))) | ||
| 48 | |||
| 49 | /* With indexed regs we don't want to feed the index through io_p2v() | ||
| 50 | especially if it is a variable, otherwise horrible code will result. */ | ||
| 51 | # define __REG2(x,y) \ | ||
| 52 | (*(volatile u32 *)((u32)&__REG(x) + (y))) | ||
| 53 | |||
| 54 | # define __PREG(x) (io_v2p((u32)&(x))) | ||
| 55 | |||
| 56 | #else | ||
| 57 | |||
| 58 | # define __REG(x) io_p2v(x) | ||
| 59 | # define __PREG(x) io_v2p(x) | ||
| 60 | |||
| 61 | #endif | ||
| 62 | |||
| 63 | #ifndef __ASSEMBLY__ | ||
| 64 | |||
| 65 | #ifdef CONFIG_PXA25x | ||
| 66 | #define __cpu_is_pxa21x(id) \ | ||
| 67 | ({ \ | ||
| 68 | unsigned int _id = (id) >> 4 & 0xf3f; \ | ||
| 69 | _id == 0x212; \ | ||
| 70 | }) | ||
| 71 | |||
| 72 | #define __cpu_is_pxa255(id) \ | ||
| 73 | ({ \ | ||
| 74 | unsigned int _id = (id) >> 4 & 0xfff; \ | ||
| 75 | _id == 0x2d0; \ | ||
| 76 | }) | ||
| 77 | |||
| 78 | #define __cpu_is_pxa25x(id) \ | ||
| 79 | ({ \ | ||
| 80 | unsigned int _id = (id) >> 4 & 0xfff; \ | ||
| 81 | _id == 0x2d0 || _id == 0x290; \ | ||
| 82 | }) | ||
| 83 | #else | ||
| 84 | #define __cpu_is_pxa21x(id) (0) | ||
| 85 | #define __cpu_is_pxa255(id) (0) | ||
| 86 | #define __cpu_is_pxa25x(id) (0) | ||
| 87 | #endif | ||
| 88 | |||
| 89 | #ifdef CONFIG_PXA27x | ||
| 90 | #define __cpu_is_pxa27x(id) \ | ||
| 91 | ({ \ | ||
| 92 | unsigned int _id = (id) >> 4 & 0xfff; \ | ||
| 93 | _id == 0x411; \ | ||
| 94 | }) | ||
| 95 | #else | ||
| 96 | #define __cpu_is_pxa27x(id) (0) | ||
| 97 | #endif | ||
| 98 | |||
| 99 | #ifdef CONFIG_CPU_PXA300 | ||
| 100 | #define __cpu_is_pxa300(id) \ | ||
| 101 | ({ \ | ||
| 102 | unsigned int _id = (id) >> 4 & 0xfff; \ | ||
| 103 | _id == 0x688; \ | ||
| 104 | }) | ||
| 105 | #else | ||
| 106 | #define __cpu_is_pxa300(id) (0) | ||
| 107 | #endif | ||
| 108 | |||
| 109 | #ifdef CONFIG_CPU_PXA310 | ||
| 110 | #define __cpu_is_pxa310(id) \ | ||
| 111 | ({ \ | ||
| 112 | unsigned int _id = (id) >> 4 & 0xfff; \ | ||
| 113 | _id == 0x689; \ | ||
| 114 | }) | ||
| 115 | #else | ||
| 116 | #define __cpu_is_pxa310(id) (0) | ||
| 117 | #endif | ||
| 118 | |||
| 119 | #ifdef CONFIG_CPU_PXA320 | ||
| 120 | #define __cpu_is_pxa320(id) \ | ||
| 121 | ({ \ | ||
| 122 | unsigned int _id = (id) >> 4 & 0xfff; \ | ||
| 123 | _id == 0x603 || _id == 0x682; \ | ||
| 124 | }) | ||
| 125 | #else | ||
| 126 | #define __cpu_is_pxa320(id) (0) | ||
| 127 | #endif | ||
| 128 | |||
| 129 | #ifdef CONFIG_CPU_PXA930 | ||
| 130 | #define __cpu_is_pxa930(id) \ | ||
| 131 | ({ \ | ||
| 132 | unsigned int _id = (id) >> 4 & 0xfff; \ | ||
| 133 | _id == 0x683; \ | ||
| 134 | }) | ||
| 135 | #else | ||
| 136 | #define __cpu_is_pxa930(id) (0) | ||
| 137 | #endif | ||
| 138 | |||
| 139 | #define cpu_is_pxa21x() \ | ||
| 140 | ({ \ | ||
| 141 | __cpu_is_pxa21x(read_cpuid_id()); \ | ||
| 142 | }) | ||
| 143 | |||
| 144 | #define cpu_is_pxa255() \ | ||
| 145 | ({ \ | ||
| 146 | __cpu_is_pxa255(read_cpuid_id()); \ | ||
| 147 | }) | ||
| 148 | |||
| 149 | #define cpu_is_pxa25x() \ | ||
| 150 | ({ \ | ||
| 151 | __cpu_is_pxa25x(read_cpuid_id()); \ | ||
| 152 | }) | ||
| 153 | |||
| 154 | #define cpu_is_pxa27x() \ | ||
| 155 | ({ \ | ||
| 156 | __cpu_is_pxa27x(read_cpuid_id()); \ | ||
| 157 | }) | ||
| 158 | |||
| 159 | #define cpu_is_pxa300() \ | ||
| 160 | ({ \ | ||
| 161 | __cpu_is_pxa300(read_cpuid_id()); \ | ||
| 162 | }) | ||
| 163 | |||
| 164 | #define cpu_is_pxa310() \ | ||
| 165 | ({ \ | ||
| 166 | __cpu_is_pxa310(read_cpuid_id()); \ | ||
| 167 | }) | ||
| 168 | |||
| 169 | #define cpu_is_pxa320() \ | ||
| 170 | ({ \ | ||
| 171 | __cpu_is_pxa320(read_cpuid_id()); \ | ||
| 172 | }) | ||
| 173 | |||
| 174 | #define cpu_is_pxa930() \ | ||
| 175 | ({ \ | ||
| 176 | unsigned int id = read_cpuid(CPUID_ID); \ | ||
| 177 | __cpu_is_pxa930(id); \ | ||
| 178 | }) | ||
| 179 | |||
| 180 | /* | ||
| 181 | * CPUID Core Generation Bit | ||
| 182 | * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x | ||
| 183 | * == 0x3 for pxa300/pxa310/pxa320 | ||
| 184 | */ | ||
| 185 | #define __cpu_is_pxa2xx(id) \ | ||
| 186 | ({ \ | ||
| 187 | unsigned int _id = (id) >> 13 & 0x7; \ | ||
| 188 | _id <= 0x2; \ | ||
| 189 | }) | ||
| 190 | |||
| 191 | #define __cpu_is_pxa3xx(id) \ | ||
| 192 | ({ \ | ||
| 193 | unsigned int _id = (id) >> 13 & 0x7; \ | ||
| 194 | _id == 0x3; \ | ||
| 195 | }) | ||
| 196 | |||
| 197 | #define cpu_is_pxa2xx() \ | ||
| 198 | ({ \ | ||
| 199 | __cpu_is_pxa2xx(read_cpuid_id()); \ | ||
| 200 | }) | ||
| 201 | |||
| 202 | #define cpu_is_pxa3xx() \ | ||
| 203 | ({ \ | ||
| 204 | __cpu_is_pxa3xx(read_cpuid_id()); \ | ||
| 205 | }) | ||
| 206 | |||
| 207 | /* | ||
| 208 | * Handy routine to set GPIO alternate functions | ||
| 209 | */ | ||
| 210 | extern int pxa_gpio_mode( int gpio_mode ); | ||
| 211 | |||
| 212 | /* | ||
| 213 | * Return GPIO level, nonzero means high, zero is low | ||
| 214 | */ | ||
| 215 | extern int pxa_gpio_get_value(unsigned gpio); | ||
| 216 | |||
| 217 | /* | ||
| 218 | * Set output GPIO level | ||
| 219 | */ | ||
| 220 | extern void pxa_gpio_set_value(unsigned gpio, int value); | ||
| 221 | |||
| 222 | /* | ||
| 223 | * return current memory and LCD clock frequency in units of 10kHz | ||
| 224 | */ | ||
| 225 | extern unsigned int get_memclk_frequency_10khz(void); | ||
| 226 | |||
| 227 | /* | ||
| 228 | * register GPIO as reset generator | ||
| 229 | */ | ||
| 230 | extern int init_gpio_reset(int gpio); | ||
| 231 | |||
| 232 | #endif | ||
| 233 | |||
| 234 | #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) | ||
| 235 | #define PCIBIOS_MIN_IO 0 | ||
| 236 | #define PCIBIOS_MIN_MEM 0 | ||
| 237 | #define pcibios_assign_all_busses() 1 | ||
| 238 | #endif | ||
| 239 | |||
| 240 | #endif /* _ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-pxa/i2c.h b/include/asm-arm/arch-pxa/i2c.h deleted file mode 100644 index 80596b013443..000000000000 --- a/include/asm-arm/arch-pxa/i2c.h +++ /dev/null | |||
| @@ -1,77 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * i2c_pxa.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002 Intrinsyc Software Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | #ifndef _I2C_PXA_H_ | ||
| 12 | #define _I2C_PXA_H_ | ||
| 13 | |||
| 14 | #if 0 | ||
| 15 | #define DEF_TIMEOUT 3 | ||
| 16 | #else | ||
| 17 | /* need a longer timeout if we're dealing with the fact we may well be | ||
| 18 | * looking at a multi-master environment | ||
| 19 | */ | ||
| 20 | #define DEF_TIMEOUT 32 | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #define BUS_ERROR (-EREMOTEIO) | ||
| 24 | #define XFER_NAKED (-ECONNREFUSED) | ||
| 25 | #define I2C_RETRY (-2000) /* an error has occurred retry transmit */ | ||
| 26 | |||
| 27 | /* ICR initialize bit values | ||
| 28 | * | ||
| 29 | * 15. FM 0 (100 Khz operation) | ||
| 30 | * 14. UR 0 (No unit reset) | ||
| 31 | * 13. SADIE 0 (Disables the unit from interrupting on slave addresses | ||
| 32 | * matching its slave address) | ||
| 33 | * 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration | ||
| 34 | * in master mode) | ||
| 35 | * 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode) | ||
| 36 | * 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent) | ||
| 37 | * 9. IRFIE 1 (Enable interrupts from full buffer received) | ||
| 38 | * 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty) | ||
| 39 | * 7. GCD 1 (Disables i2c unit response to general call messages as a slave) | ||
| 40 | * 6. IUE 0 (Disable unit until we change settings) | ||
| 41 | * 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL) | ||
| 42 | * 4. MA 0 (Only send stop with the ICR stop bit) | ||
| 43 | * 3. TB 0 (We are not transmitting a byte initially) | ||
| 44 | * 2. ACKNAK 0 (Send an ACK after the unit receives a byte) | ||
| 45 | * 1. STOP 0 (Do not send a STOP) | ||
| 46 | * 0. START 0 (Do not send a START) | ||
| 47 | * | ||
| 48 | */ | ||
| 49 | #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) | ||
| 50 | |||
| 51 | /* I2C status register init values | ||
| 52 | * | ||
| 53 | * 10. BED 1 (Clear bus error detected) | ||
| 54 | * 9. SAD 1 (Clear slave address detected) | ||
| 55 | * 7. IRF 1 (Clear IDBR Receive Full) | ||
| 56 | * 6. ITE 1 (Clear IDBR Transmit Empty) | ||
| 57 | * 5. ALD 1 (Clear Arbitration Loss Detected) | ||
| 58 | * 4. SSD 1 (Clear Slave Stop Detected) | ||
| 59 | */ | ||
| 60 | #define I2C_ISR_INIT 0x7FF /* status register init */ | ||
| 61 | |||
| 62 | struct i2c_slave_client; | ||
| 63 | |||
| 64 | struct i2c_pxa_platform_data { | ||
| 65 | unsigned int slave_addr; | ||
| 66 | struct i2c_slave_client *slave; | ||
| 67 | unsigned int class; | ||
| 68 | int use_pio; | ||
| 69 | }; | ||
| 70 | |||
| 71 | extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info); | ||
| 72 | |||
| 73 | #ifdef CONFIG_PXA27x | ||
| 74 | extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info); | ||
| 75 | #endif | ||
| 76 | |||
| 77 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/idp.h b/include/asm-arm/arch-pxa/idp.h deleted file mode 100644 index 21aa8ac35c1c..000000000000 --- a/include/asm-arm/arch-pxa/idp.h +++ /dev/null | |||
| @@ -1,199 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/idp.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc. | ||
| 9 | * | ||
| 10 | * 2001-09-13: Cliff Brake <cbrake@accelent.com> | ||
| 11 | * Initial code | ||
| 12 | * | ||
| 13 | * 2005-02-15: Cliff Brake <cliff.brake@gmail.com> | ||
| 14 | * <http://www.vibren.com> <http://bec-systems.com> | ||
| 15 | * Changes for 2.6 kernel. | ||
| 16 | */ | ||
| 17 | |||
| 18 | |||
| 19 | /* | ||
| 20 | * Note: this file must be safe to include in assembly files | ||
| 21 | * | ||
| 22 | * Support for the Vibren PXA255 IDP requires rev04 or later | ||
| 23 | * IDP hardware. | ||
| 24 | */ | ||
| 25 | |||
| 26 | |||
| 27 | #define IDP_FLASH_PHYS (PXA_CS0_PHYS) | ||
| 28 | #define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS) | ||
| 29 | #define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS) | ||
| 30 | #define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000) | ||
| 31 | #define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000) | ||
| 32 | #define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000) | ||
| 33 | #define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000) | ||
| 34 | |||
| 35 | |||
| 36 | /* | ||
| 37 | * virtual memory map | ||
| 38 | */ | ||
| 39 | |||
| 40 | #define IDP_COREVOLT_VIRT (0xf0000000) | ||
| 41 | #define IDP_COREVOLT_SIZE (1*1024*1024) | ||
| 42 | |||
| 43 | #define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE) | ||
| 44 | #define IDP_CPLD_SIZE (1*1024*1024) | ||
| 45 | |||
| 46 | #if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000 | ||
| 47 | #error Your custom IO space is getting a bit large !! | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT) | ||
| 51 | #define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS) | ||
| 52 | |||
| 53 | #ifndef __ASSEMBLY__ | ||
| 54 | # define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x))) | ||
| 55 | #else | ||
| 56 | # define __CPLD_REG(x) CPLD_P2V(x) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | /* board level registers in the CPLD: (offsets from CPLD_VIRT) */ | ||
| 60 | |||
| 61 | #define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00) | ||
| 62 | #define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04) | ||
| 63 | #define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08) | ||
| 64 | #define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C) | ||
| 65 | #define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10) | ||
| 66 | #define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14) | ||
| 67 | #define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18) | ||
| 68 | #define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C) | ||
| 69 | #define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20) | ||
| 70 | #define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24) | ||
| 71 | #define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28) | ||
| 72 | #define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C) | ||
| 73 | #define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30) | ||
| 74 | #define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34) | ||
| 75 | |||
| 76 | #define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50) | ||
| 77 | #define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54) | ||
| 78 | #define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58) | ||
| 79 | #define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C) | ||
| 80 | |||
| 81 | /* FPGA register virtual addresses */ | ||
| 82 | |||
| 83 | #define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV) | ||
| 84 | #define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR) | ||
| 85 | #define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL) | ||
| 86 | #define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH) | ||
| 87 | #define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW) | ||
| 88 | #define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN) | ||
| 89 | #define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR) | ||
| 90 | #define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE) | ||
| 91 | #define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR) | ||
| 92 | #define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE) | ||
| 93 | #define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR) | ||
| 94 | #define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL) | ||
| 95 | #define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD) | ||
| 96 | #define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE) | ||
| 97 | |||
| 98 | #define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW) | ||
| 99 | #define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS) | ||
| 100 | #define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS) | ||
| 101 | #define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS) | ||
| 102 | |||
| 103 | |||
| 104 | /* | ||
| 105 | * Bit masks for various registers | ||
| 106 | */ | ||
| 107 | |||
| 108 | // IDP_CPLD_PCCARD_PWR | ||
| 109 | #define PCC0_PWR0 (1 << 0) | ||
| 110 | #define PCC0_PWR1 (1 << 1) | ||
| 111 | #define PCC0_PWR2 (1 << 2) | ||
| 112 | #define PCC0_PWR3 (1 << 3) | ||
| 113 | #define PCC1_PWR0 (1 << 4) | ||
| 114 | #define PCC1_PWR1 (1 << 5) | ||
| 115 | #define PCC1_PWR2 (1 << 6) | ||
| 116 | #define PCC1_PWR3 (1 << 7) | ||
| 117 | |||
| 118 | // IDP_CPLD_PCCARD_EN | ||
| 119 | #define PCC0_RESET (1 << 6) | ||
| 120 | #define PCC1_RESET (1 << 7) | ||
| 121 | #define PCC0_ENABLE (1 << 0) | ||
| 122 | #define PCC1_ENABLE (1 << 1) | ||
| 123 | |||
| 124 | // IDP_CPLD_PCCARDx_STATUS | ||
| 125 | #define _PCC_WRPROT (1 << 7) // 7-4 read as low true | ||
| 126 | #define _PCC_RESET (1 << 6) | ||
| 127 | #define _PCC_IRQ (1 << 5) | ||
| 128 | #define _PCC_INPACK (1 << 4) | ||
| 129 | #define PCC_BVD2 (1 << 3) | ||
| 130 | #define PCC_BVD1 (1 << 2) | ||
| 131 | #define PCC_VS2 (1 << 1) | ||
| 132 | #define PCC_VS1 (1 << 0) | ||
| 133 | |||
| 134 | #define PCC_DETECT(x) (GPLR(7 + (x)) & GPIO_bit(7 + (x))) | ||
| 135 | |||
| 136 | /* A listing of interrupts used by external hardware devices */ | ||
| 137 | |||
| 138 | #define TOUCH_PANEL_IRQ IRQ_GPIO(5) | ||
| 139 | #define IDE_IRQ IRQ_GPIO(21) | ||
| 140 | |||
| 141 | #define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING | ||
| 142 | |||
| 143 | #define ETHERNET_IRQ IRQ_GPIO(4) | ||
| 144 | #define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING | ||
| 145 | |||
| 146 | #define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING | ||
| 147 | |||
| 148 | #define PCMCIA_S0_CD_VALID IRQ_GPIO(7) | ||
| 149 | #define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH | ||
| 150 | |||
| 151 | #define PCMCIA_S1_CD_VALID IRQ_GPIO(8) | ||
| 152 | #define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH | ||
| 153 | |||
| 154 | #define PCMCIA_S0_RDYINT IRQ_GPIO(19) | ||
| 155 | #define PCMCIA_S1_RDYINT IRQ_GPIO(22) | ||
| 156 | |||
| 157 | |||
| 158 | /* | ||
| 159 | * Macros for LED Driver | ||
| 160 | */ | ||
| 161 | |||
| 162 | /* leds 0 = ON */ | ||
| 163 | #define IDP_HB_LED (1<<5) | ||
| 164 | #define IDP_BUSY_LED (1<<6) | ||
| 165 | |||
| 166 | #define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED) | ||
| 167 | |||
| 168 | /* | ||
| 169 | * macros for MTD driver | ||
| 170 | */ | ||
| 171 | |||
| 172 | #define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1)) | ||
| 173 | #define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1)) | ||
| 174 | |||
| 175 | /* | ||
| 176 | * macros for matrix keyboard driver | ||
| 177 | */ | ||
| 178 | |||
| 179 | #define KEYBD_MATRIX_NUMBER_INPUTS 7 | ||
| 180 | #define KEYBD_MATRIX_NUMBER_OUTPUTS 14 | ||
| 181 | |||
| 182 | #define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE | ||
| 183 | #define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE | ||
| 184 | |||
| 185 | #define KEYBD_MATRIX_SETTLING_TIME_US 100 | ||
| 186 | #define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2 | ||
| 187 | |||
| 188 | #define KEYBD_MATRIX_SET_OUTPUTS(outputs) \ | ||
| 189 | {\ | ||
| 190 | IDP_CPLD_KB_COL_LOW = outputs;\ | ||
| 191 | IDP_CPLD_KB_COL_HIGH = outputs >> 7;\ | ||
| 192 | } | ||
| 193 | |||
| 194 | #define KEYBD_MATRIX_GET_INPUTS(inputs) \ | ||
| 195 | {\ | ||
| 196 | inputs = (IDP_CPLD_KB_ROW & 0x7f);\ | ||
| 197 | } | ||
| 198 | |||
| 199 | |||
diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h deleted file mode 100644 index af34e0f2f7dc..000000000000 --- a/include/asm-arm/arch-pxa/io.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/io.h | ||
| 3 | * | ||
| 4 | * Copied from asm/arch/sa1100/io.h | ||
| 5 | */ | ||
| 6 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 7 | #define __ASM_ARM_ARCH_IO_H | ||
| 8 | |||
| 9 | #include <asm/arch/hardware.h> | ||
| 10 | |||
| 11 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 12 | |||
| 13 | /* | ||
| 14 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
| 15 | * drivers out there that might just work if we fake them... | ||
| 16 | */ | ||
| 17 | #define __io(a) ((void __iomem *)(a)) | ||
| 18 | #define __mem_pci(a) (a) | ||
| 19 | |||
| 20 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h deleted file mode 100644 index 0a50c3c763df..000000000000 --- a/include/asm-arm/arch-pxa/irda.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | #ifndef ASMARM_ARCH_IRDA_H | ||
| 2 | #define ASMARM_ARCH_IRDA_H | ||
| 3 | |||
| 4 | /* board specific transceiver capabilities */ | ||
| 5 | |||
| 6 | #define IR_OFF 1 | ||
| 7 | #define IR_SIRMODE 2 | ||
| 8 | #define IR_FIRMODE 4 | ||
| 9 | |||
| 10 | struct pxaficp_platform_data { | ||
| 11 | int transceiver_cap; | ||
| 12 | void (*transceiver_mode)(struct device *dev, int mode); | ||
| 13 | int (*startup)(struct device *dev); | ||
| 14 | void (*shutdown)(struct device *dev); | ||
| 15 | }; | ||
| 16 | |||
| 17 | extern void pxa_set_ficp_info(struct pxaficp_platform_data *info); | ||
| 18 | |||
| 19 | #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) | ||
| 20 | void pxa2xx_transceiver_mode(struct device *dev, int mode); | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h deleted file mode 100644 index 9413121b0ed9..000000000000 --- a/include/asm-arm/arch-pxa/irqs.h +++ /dev/null | |||
| @@ -1,264 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/irqs.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Jun 15, 2001 | ||
| 6 | * Copyright: MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | |||
| 14 | #define PXA_IRQ(x) (x) | ||
| 15 | |||
| 16 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 17 | #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ | ||
| 18 | #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ | ||
| 19 | #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ | ||
| 20 | #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */ | ||
| 21 | #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ | ||
| 22 | #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ | ||
| 23 | #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ | ||
| 27 | #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ | ||
| 28 | #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ | ||
| 29 | #define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */ | ||
| 30 | #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ | ||
| 31 | #define IRQ_USB PXA_IRQ(11) /* USB Service */ | ||
| 32 | #define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ | ||
| 33 | #define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */ | ||
| 34 | #define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ | ||
| 35 | #define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ | ||
| 36 | #define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ | ||
| 37 | #define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */ | ||
| 38 | #define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */ | ||
| 39 | #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ | ||
| 40 | #define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ | ||
| 41 | #define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ | ||
| 42 | #define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ | ||
| 43 | #define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ | ||
| 44 | #define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ | ||
| 45 | #define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */ | ||
| 46 | #define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */ | ||
| 47 | #define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */ | ||
| 48 | #define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */ | ||
| 49 | #define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */ | ||
| 50 | #define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */ | ||
| 51 | #define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */ | ||
| 52 | #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ | ||
| 53 | #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ | ||
| 54 | |||
| 55 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 56 | #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ | ||
| 57 | #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ | ||
| 58 | #endif | ||
| 59 | |||
| 60 | #ifdef CONFIG_PXA3xx | ||
| 61 | #define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */ | ||
| 62 | #define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ | ||
| 63 | #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ | ||
| 64 | #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ | ||
| 65 | #define IRQ_GRPHICS PXA_IRQ(39) /* Graphics Controller */ | ||
| 66 | #define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ | ||
| 67 | #define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ | ||
| 68 | #define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ | ||
| 69 | #define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ | ||
| 70 | #define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */ | ||
| 71 | #define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ | ||
| 72 | #define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ | ||
| 73 | #define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #define PXA_GPIO_IRQ_BASE (64) | ||
| 77 | #define PXA_GPIO_IRQ_NUM (128) | ||
| 78 | |||
| 79 | #define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) | ||
| 80 | #define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) | ||
| 81 | |||
| 82 | #define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) | ||
| 83 | #define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) | ||
| 84 | |||
| 85 | /* | ||
| 86 | * The next 16 interrupts are for board specific purposes. Since | ||
| 87 | * the kernel can only run on one machine at a time, we can re-use | ||
| 88 | * these. If you need more, increase IRQ_BOARD_END, but keep it | ||
| 89 | * within sensible limits. | ||
| 90 | */ | ||
| 91 | #define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM) | ||
| 92 | #define IRQ_BOARD_END (IRQ_BOARD_START + 16) | ||
| 93 | |||
| 94 | #define IRQ_SA1111_START (IRQ_BOARD_END) | ||
| 95 | #define IRQ_GPAIN0 (IRQ_BOARD_END + 0) | ||
| 96 | #define IRQ_GPAIN1 (IRQ_BOARD_END + 1) | ||
| 97 | #define IRQ_GPAIN2 (IRQ_BOARD_END + 2) | ||
| 98 | #define IRQ_GPAIN3 (IRQ_BOARD_END + 3) | ||
| 99 | #define IRQ_GPBIN0 (IRQ_BOARD_END + 4) | ||
| 100 | #define IRQ_GPBIN1 (IRQ_BOARD_END + 5) | ||
| 101 | #define IRQ_GPBIN2 (IRQ_BOARD_END + 6) | ||
| 102 | #define IRQ_GPBIN3 (IRQ_BOARD_END + 7) | ||
| 103 | #define IRQ_GPBIN4 (IRQ_BOARD_END + 8) | ||
| 104 | #define IRQ_GPBIN5 (IRQ_BOARD_END + 9) | ||
| 105 | #define IRQ_GPCIN0 (IRQ_BOARD_END + 10) | ||
| 106 | #define IRQ_GPCIN1 (IRQ_BOARD_END + 11) | ||
| 107 | #define IRQ_GPCIN2 (IRQ_BOARD_END + 12) | ||
| 108 | #define IRQ_GPCIN3 (IRQ_BOARD_END + 13) | ||
| 109 | #define IRQ_GPCIN4 (IRQ_BOARD_END + 14) | ||
| 110 | #define IRQ_GPCIN5 (IRQ_BOARD_END + 15) | ||
| 111 | #define IRQ_GPCIN6 (IRQ_BOARD_END + 16) | ||
| 112 | #define IRQ_GPCIN7 (IRQ_BOARD_END + 17) | ||
| 113 | #define IRQ_MSTXINT (IRQ_BOARD_END + 18) | ||
| 114 | #define IRQ_MSRXINT (IRQ_BOARD_END + 19) | ||
| 115 | #define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20) | ||
| 116 | #define IRQ_TPTXINT (IRQ_BOARD_END + 21) | ||
| 117 | #define IRQ_TPRXINT (IRQ_BOARD_END + 22) | ||
| 118 | #define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23) | ||
| 119 | #define SSPXMTINT (IRQ_BOARD_END + 24) | ||
| 120 | #define SSPRCVINT (IRQ_BOARD_END + 25) | ||
| 121 | #define SSPROR (IRQ_BOARD_END + 26) | ||
| 122 | #define AUDXMTDMADONEA (IRQ_BOARD_END + 32) | ||
| 123 | #define AUDRCVDMADONEA (IRQ_BOARD_END + 33) | ||
| 124 | #define AUDXMTDMADONEB (IRQ_BOARD_END + 34) | ||
| 125 | #define AUDRCVDMADONEB (IRQ_BOARD_END + 35) | ||
| 126 | #define AUDTFSR (IRQ_BOARD_END + 36) | ||
| 127 | #define AUDRFSR (IRQ_BOARD_END + 37) | ||
| 128 | #define AUDTUR (IRQ_BOARD_END + 38) | ||
| 129 | #define AUDROR (IRQ_BOARD_END + 39) | ||
| 130 | #define AUDDTS (IRQ_BOARD_END + 40) | ||
| 131 | #define AUDRDD (IRQ_BOARD_END + 41) | ||
| 132 | #define AUDSTO (IRQ_BOARD_END + 42) | ||
| 133 | #define IRQ_USBPWR (IRQ_BOARD_END + 43) | ||
| 134 | #define IRQ_HCIM (IRQ_BOARD_END + 44) | ||
| 135 | #define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45) | ||
| 136 | #define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46) | ||
| 137 | #define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47) | ||
| 138 | #define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48) | ||
| 139 | #define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49) | ||
| 140 | #define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50) | ||
| 141 | #define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51) | ||
| 142 | #define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52) | ||
| 143 | #define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53) | ||
| 144 | #define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) | ||
| 145 | |||
| 146 | #define IRQ_LOCOMO_START (IRQ_BOARD_END) | ||
| 147 | #define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) | ||
| 148 | #define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) | ||
| 149 | #define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) | ||
| 150 | #define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) | ||
| 151 | #define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4) | ||
| 152 | #define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5) | ||
| 153 | #define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6) | ||
| 154 | #define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7) | ||
| 155 | #define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8) | ||
| 156 | #define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9) | ||
| 157 | #define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10) | ||
| 158 | #define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11) | ||
| 159 | #define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12) | ||
| 160 | #define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13) | ||
| 161 | #define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14) | ||
| 162 | #define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15) | ||
| 163 | #define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16) | ||
| 164 | #define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17) | ||
| 165 | #define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18) | ||
| 166 | #define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19) | ||
| 167 | #define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20) | ||
| 168 | #define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21) | ||
| 169 | |||
| 170 | /* | ||
| 171 | * Figure out the MAX IRQ number. | ||
| 172 | * | ||
| 173 | * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. | ||
| 174 | * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1 | ||
| 175 | * Otherwise, we have the standard IRQs only. | ||
| 176 | */ | ||
| 177 | #ifdef CONFIG_SA1111 | ||
| 178 | #define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) | ||
| 179 | #elif defined(CONFIG_SHARP_LOCOMO) | ||
| 180 | #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) | ||
| 181 | #elif defined(CONFIG_ARCH_LUBBOCK) || \ | ||
| 182 | defined(CONFIG_MACH_LOGICPD_PXA270) || \ | ||
| 183 | defined(CONFIG_MACH_TOSA) || \ | ||
| 184 | defined(CONFIG_MACH_MAINSTONE) || \ | ||
| 185 | defined(CONFIG_MACH_PCM027) || \ | ||
| 186 | defined(CONFIG_MACH_MAGICIAN) | ||
| 187 | #define NR_IRQS (IRQ_BOARD_END) | ||
| 188 | #elif defined(CONFIG_MACH_ZYLONITE) | ||
| 189 | #define NR_IRQS (IRQ_BOARD_START + 32) | ||
| 190 | #else | ||
| 191 | #define NR_IRQS (IRQ_BOARD_START) | ||
| 192 | #endif | ||
| 193 | |||
| 194 | /* | ||
| 195 | * Board specific IRQs. Define them here. | ||
| 196 | * Do not surround them with ifdefs. | ||
| 197 | */ | ||
| 198 | #define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) | ||
| 199 | #define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) | ||
| 200 | #define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) | ||
| 201 | #define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ | ||
| 202 | #define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) | ||
| 203 | #define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) | ||
| 204 | #define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) | ||
| 205 | #define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ | ||
| 206 | #define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) | ||
| 207 | |||
| 208 | #define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) | ||
| 209 | #define LPD270_USBC_IRQ LPD270_IRQ(2) | ||
| 210 | #define LPD270_ETHERNET_IRQ LPD270_IRQ(3) | ||
| 211 | #define LPD270_AC97_IRQ LPD270_IRQ(4) | ||
| 212 | |||
| 213 | #define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) | ||
| 214 | #define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) | ||
| 215 | #define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) | ||
| 216 | #define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) | ||
| 217 | #define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) | ||
| 218 | #define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) | ||
| 219 | #define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) | ||
| 220 | #define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) | ||
| 221 | #define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) | ||
| 222 | #define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) | ||
| 223 | #define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) | ||
| 224 | #define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) | ||
| 225 | #define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) | ||
| 226 | #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) | ||
| 227 | #define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) | ||
| 228 | |||
| 229 | /* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ | ||
| 230 | #define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) | ||
| 231 | #define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) | ||
| 232 | #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) | ||
| 233 | #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) | ||
| 234 | |||
| 235 | /* phyCORE-PXA270 (PCM027) Interrupts */ | ||
| 236 | #define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) | ||
| 237 | #define PCM027_BTDET_IRQ PCM027_IRQ(0) | ||
| 238 | #define PCM027_FF_RI_IRQ PCM027_IRQ(1) | ||
| 239 | #define PCM027_MMCDET_IRQ PCM027_IRQ(2) | ||
| 240 | #define PCM027_PM_5V_IRQ PCM027_IRQ(3) | ||
| 241 | |||
| 242 | /* ITE8152 irqs */ | ||
| 243 | /* add IT8152 IRQs beyond BOARD_END */ | ||
| 244 | #ifdef CONFIG_PCI_HOST_ITE8152 | ||
| 245 | #define IT8152_IRQ(x) (IRQ_BOARD_END + (x)) | ||
| 246 | |||
| 247 | /* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ | ||
| 248 | #define IT8152_LD_IRQ_COUNT 9 | ||
| 249 | #define IT8152_LP_IRQ_COUNT 16 | ||
| 250 | #define IT8152_PD_IRQ_COUNT 15 | ||
| 251 | |||
| 252 | /* Priorities: */ | ||
| 253 | #define IT8152_PD_IRQ(i) IT8152_IRQ(i) | ||
| 254 | #define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT) | ||
| 255 | #define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT) | ||
| 256 | |||
| 257 | #define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1) | ||
| 258 | |||
| 259 | #if NR_IRQS < (IT8152_LAST_IRQ+1) | ||
| 260 | #undef NR_IRQS | ||
| 261 | #define NR_IRQS (IT8152_LAST_IRQ+1) | ||
| 262 | #endif | ||
| 263 | |||
| 264 | #endif /* CONFIG_PCI_HOST_ITE8152 */ | ||
diff --git a/include/asm-arm/arch-pxa/littleton.h b/include/asm-arm/arch-pxa/littleton.h deleted file mode 100644 index 79d209b826f4..000000000000 --- a/include/asm-arm/arch-pxa/littleton.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_ZYLONITE_H | ||
| 2 | #define __ASM_ARCH_ZYLONITE_H | ||
| 3 | |||
| 4 | #define LITTLETON_ETH_PHYS 0x30000000 | ||
| 5 | |||
| 6 | #endif /* __ASM_ARCH_ZYLONITE_H */ | ||
diff --git a/include/asm-arm/arch-pxa/lpd270.h b/include/asm-arm/arch-pxa/lpd270.h deleted file mode 100644 index 501d240ac120..000000000000 --- a/include/asm-arm/arch-pxa/lpd270.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pxa/lpd270.h | ||
| 3 | * | ||
| 4 | * Author: Lennert Buytenhek | ||
| 5 | * Created: Feb 10, 2006 | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_LPD270_H | ||
| 13 | #define __ASM_ARCH_LPD270_H | ||
| 14 | |||
| 15 | #define LPD270_CPLD_PHYS PXA_CS2_PHYS | ||
| 16 | #define LPD270_CPLD_VIRT 0xf0000000 | ||
| 17 | #define LPD270_CPLD_SIZE 0x00100000 | ||
| 18 | |||
| 19 | #define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000) | ||
| 20 | |||
| 21 | /* CPLD registers */ | ||
| 22 | #define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x))) | ||
| 23 | #define LPD270_CONTROL LPD270_CPLD_REG(0x00) | ||
| 24 | #define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04) | ||
| 25 | #define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08) | ||
| 26 | #define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14) | ||
| 27 | #define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20) | ||
| 28 | #define LPD270_MODE_PINS LPD270_CPLD_REG(0x24) | ||
| 29 | #define LPD270_EGPIO LPD270_CPLD_REG(0x30) | ||
| 30 | #define LPD270_INT_MASK LPD270_CPLD_REG(0x40) | ||
| 31 | #define LPD270_INT_STATUS LPD270_CPLD_REG(0x50) | ||
| 32 | |||
| 33 | #define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ | ||
| 34 | #define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ | ||
| 35 | #define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */ | ||
| 36 | |||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/lubbock.h b/include/asm-arm/arch-pxa/lubbock.h deleted file mode 100644 index 11ee73593fc3..000000000000 --- a/include/asm-arm/arch-pxa/lubbock.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/lubbock.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Jun 15, 2001 | ||
| 6 | * Copyright: MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #define LUBBOCK_ETH_PHYS PXA_CS3_PHYS | ||
| 14 | |||
| 15 | #define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS | ||
| 16 | #define LUBBOCK_FPGA_VIRT (0xf0000000) | ||
| 17 | #define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT) | ||
| 18 | #define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS) | ||
| 19 | |||
| 20 | #ifndef __ASSEMBLY__ | ||
| 21 | # define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x))) | ||
| 22 | #else | ||
| 23 | # define __LUB_REG(x) LUB_P2V(x) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | /* FPGA register virtual addresses */ | ||
| 27 | #define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) | ||
| 28 | #define LUB_HEXLED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010) | ||
| 29 | #define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) | ||
| 30 | #define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) | ||
| 31 | #define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) | ||
| 32 | #define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) | ||
| 33 | #define LUB_MISC_RD __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090) | ||
| 34 | #define LUB_IRQ_MASK_EN __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0) | ||
| 35 | #define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0) | ||
| 36 | #define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) | ||
| 37 | |||
| 38 | #ifndef __ASSEMBLY__ | ||
| 39 | extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); | ||
| 40 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h deleted file mode 100644 index 169b374f9921..000000000000 --- a/include/asm-arm/arch-pxa/magician.h +++ /dev/null | |||
| @@ -1,117 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * GPIO and IRQ definitions for HTC Magician PDA phones | ||
| 3 | * | ||
| 4 | * Copyright (c) 2007 Philipp Zabel | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _MAGICIAN_H_ | ||
| 13 | #define _MAGICIAN_H_ | ||
| 14 | |||
| 15 | #include <asm/arch/irqs.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * PXA GPIOs | ||
| 19 | */ | ||
| 20 | |||
| 21 | #define GPIO0_MAGICIAN_KEY_POWER 0 | ||
| 22 | #define GPIO9_MAGICIAN_UNKNOWN 9 | ||
| 23 | #define GPIO10_MAGICIAN_GSM_IRQ 10 | ||
| 24 | #define GPIO11_MAGICIAN_GSM_OUT1 11 | ||
| 25 | #define GPIO13_MAGICIAN_CPLD_IRQ 13 | ||
| 26 | #define GPIO18_MAGICIAN_UNKNOWN 18 | ||
| 27 | #define GPIO22_MAGICIAN_VIBRA_EN 22 | ||
| 28 | #define GPIO26_MAGICIAN_GSM_POWER 26 | ||
| 29 | #define GPIO27_MAGICIAN_USBC_PUEN 27 | ||
| 30 | #define GPIO30_MAGICIAN_nCHARGE_EN 30 | ||
| 31 | #define GPIO37_MAGICIAN_KEY_HANGUP 37 | ||
| 32 | #define GPIO38_MAGICIAN_KEY_CONTACTS 38 | ||
| 33 | #define GPIO40_MAGICIAN_GSM_OUT2 40 | ||
| 34 | #define GPIO48_MAGICIAN_UNKNOWN 48 | ||
| 35 | #define GPIO56_MAGICIAN_UNKNOWN 56 | ||
| 36 | #define GPIO57_MAGICIAN_CAM_RESET 57 | ||
| 37 | #define GPIO75_MAGICIAN_SAMSUNG_POWER 75 | ||
| 38 | #define GPIO83_MAGICIAN_nIR_EN 83 | ||
| 39 | #define GPIO86_MAGICIAN_GSM_RESET 86 | ||
| 40 | #define GPIO87_MAGICIAN_GSM_SELECT 87 | ||
| 41 | #define GPIO90_MAGICIAN_KEY_CALENDAR 90 | ||
| 42 | #define GPIO91_MAGICIAN_KEY_CAMERA 91 | ||
| 43 | #define GPIO93_MAGICIAN_KEY_UP 93 | ||
| 44 | #define GPIO94_MAGICIAN_KEY_DOWN 94 | ||
| 45 | #define GPIO95_MAGICIAN_KEY_LEFT 95 | ||
| 46 | #define GPIO96_MAGICIAN_KEY_RIGHT 96 | ||
| 47 | #define GPIO97_MAGICIAN_KEY_ENTER 97 | ||
| 48 | #define GPIO98_MAGICIAN_KEY_RECORD 98 | ||
| 49 | #define GPIO99_MAGICIAN_HEADPHONE_IN 99 | ||
| 50 | #define GPIO100_MAGICIAN_KEY_VOL_UP 100 | ||
| 51 | #define GPIO101_MAGICIAN_KEY_VOL_DOWN 101 | ||
| 52 | #define GPIO102_MAGICIAN_KEY_PHONE 102 | ||
| 53 | #define GPIO103_MAGICIAN_LED_KP 103 | ||
| 54 | #define GPIO104_MAGICIAN_LCD_POWER_1 104 | ||
| 55 | #define GPIO105_MAGICIAN_LCD_POWER_2 105 | ||
| 56 | #define GPIO106_MAGICIAN_LCD_POWER_3 106 | ||
| 57 | #define GPIO107_MAGICIAN_DS1WM_IRQ 107 | ||
| 58 | #define GPIO108_MAGICIAN_GSM_READY 108 | ||
| 59 | #define GPIO114_MAGICIAN_UNKNOWN 114 | ||
| 60 | #define GPIO115_MAGICIAN_nPEN_IRQ 115 | ||
| 61 | #define GPIO116_MAGICIAN_nCAM_EN 116 | ||
| 62 | #define GPIO119_MAGICIAN_UNKNOWN 119 | ||
| 63 | #define GPIO120_MAGICIAN_UNKNOWN 120 | ||
| 64 | |||
| 65 | /* | ||
| 66 | * CPLD IRQs | ||
| 67 | */ | ||
| 68 | |||
| 69 | #define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0) | ||
| 70 | #define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1) | ||
| 71 | #define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) | ||
| 72 | #define IRQ_MAGICIAN_AC (IRQ_BOARD_START + 3) | ||
| 73 | |||
| 74 | /* | ||
| 75 | * CPLD EGPIOs | ||
| 76 | */ | ||
| 77 | |||
| 78 | #define MAGICIAN_EGPIO_BASE 0x80 /* GPIO_BOARD_START */ | ||
| 79 | #define MAGICIAN_EGPIO(reg,bit) \ | ||
| 80 | (MAGICIAN_EGPIO_BASE + 8*reg + bit) | ||
| 81 | |||
| 82 | /* output */ | ||
| 83 | |||
| 84 | #define EGPIO_MAGICIAN_TOPPOLY_POWER MAGICIAN_EGPIO(0, 2) | ||
| 85 | #define EGPIO_MAGICIAN_LED_POWER MAGICIAN_EGPIO(0, 5) | ||
| 86 | #define EGPIO_MAGICIAN_GSM_RESET MAGICIAN_EGPIO(0, 6) | ||
| 87 | #define EGPIO_MAGICIAN_LCD_POWER MAGICIAN_EGPIO(0, 7) | ||
| 88 | #define EGPIO_MAGICIAN_SPK_POWER MAGICIAN_EGPIO(1, 0) | ||
| 89 | #define EGPIO_MAGICIAN_EP_POWER MAGICIAN_EGPIO(1, 1) | ||
| 90 | #define EGPIO_MAGICIAN_IN_SEL0 MAGICIAN_EGPIO(1, 2) | ||
| 91 | #define EGPIO_MAGICIAN_IN_SEL1 MAGICIAN_EGPIO(1, 3) | ||
| 92 | #define EGPIO_MAGICIAN_MIC_POWER MAGICIAN_EGPIO(1, 4) | ||
| 93 | #define EGPIO_MAGICIAN_CODEC_RESET MAGICIAN_EGPIO(1, 5) | ||
| 94 | #define EGPIO_MAGICIAN_CODEC_POWER MAGICIAN_EGPIO(1, 6) | ||
| 95 | #define EGPIO_MAGICIAN_BL_POWER MAGICIAN_EGPIO(1, 7) | ||
| 96 | #define EGPIO_MAGICIAN_SD_POWER MAGICIAN_EGPIO(2, 0) | ||
| 97 | #define EGPIO_MAGICIAN_CARKIT_MIC MAGICIAN_EGPIO(2, 1) | ||
| 98 | #define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL MAGICIAN_EGPIO(2, 2) | ||
| 99 | #define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3) | ||
| 100 | #define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4) | ||
| 101 | #define EGPIO_MAGICIAN_CHARGE_EN MAGICIAN_EGPIO(2, 5) | ||
| 102 | #define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7) | ||
| 103 | |||
| 104 | /* input */ | ||
| 105 | |||
| 106 | #define EGPIO_MAGICIAN_CABLE_STATE_AC MAGICIAN_EGPIO(4, 0) | ||
| 107 | #define EGPIO_MAGICIAN_CABLE_STATE_USB MAGICIAN_EGPIO(4, 1) | ||
| 108 | |||
| 109 | #define EGPIO_MAGICIAN_BOARD_ID0 MAGICIAN_EGPIO(5, 0) | ||
| 110 | #define EGPIO_MAGICIAN_BOARD_ID1 MAGICIAN_EGPIO(5, 1) | ||
| 111 | #define EGPIO_MAGICIAN_BOARD_ID2 MAGICIAN_EGPIO(5, 2) | ||
| 112 | #define EGPIO_MAGICIAN_LCD_SELECT MAGICIAN_EGPIO(5, 3) | ||
| 113 | #define EGPIO_MAGICIAN_nSD_READONLY MAGICIAN_EGPIO(5, 4) | ||
| 114 | |||
| 115 | #define EGPIO_MAGICIAN_EP_INSERT MAGICIAN_EGPIO(6, 1) | ||
| 116 | |||
| 117 | #endif /* _MAGICIAN_H_ */ | ||
diff --git a/include/asm-arm/arch-pxa/mainstone.h b/include/asm-arm/arch-pxa/mainstone.h deleted file mode 100644 index 14c862adcaa1..000000000000 --- a/include/asm-arm/arch-pxa/mainstone.h +++ /dev/null | |||
| @@ -1,120 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/mainstone.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Nov 14, 2002 | ||
| 6 | * Copyright: MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef ASM_ARCH_MAINSTONE_H | ||
| 14 | #define ASM_ARCH_MAINSTONE_H | ||
| 15 | |||
| 16 | #define MST_ETH_PHYS PXA_CS4_PHYS | ||
| 17 | |||
| 18 | #define MST_FPGA_PHYS PXA_CS2_PHYS | ||
| 19 | #define MST_FPGA_VIRT (0xf0000000) | ||
| 20 | #define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT) | ||
| 21 | #define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS) | ||
| 22 | |||
| 23 | #ifndef __ASSEMBLY__ | ||
| 24 | # define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x))) | ||
| 25 | #else | ||
| 26 | # define __MST_REG(x) MST_P2V(x) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | /* board level registers in the FPGA */ | ||
| 30 | |||
| 31 | #define MST_LEDDAT1 __MST_REG(0x08000010) | ||
| 32 | #define MST_LEDDAT2 __MST_REG(0x08000014) | ||
| 33 | #define MST_LEDCTRL __MST_REG(0x08000040) | ||
| 34 | #define MST_GPSWR __MST_REG(0x08000060) | ||
| 35 | #define MST_MSCWR1 __MST_REG(0x08000080) | ||
| 36 | #define MST_MSCWR2 __MST_REG(0x08000084) | ||
| 37 | #define MST_MSCWR3 __MST_REG(0x08000088) | ||
| 38 | #define MST_MSCRD __MST_REG(0x08000090) | ||
| 39 | #define MST_INTMSKENA __MST_REG(0x080000c0) | ||
| 40 | #define MST_INTSETCLR __MST_REG(0x080000d0) | ||
| 41 | #define MST_PCMCIA0 __MST_REG(0x080000e0) | ||
| 42 | #define MST_PCMCIA1 __MST_REG(0x080000e4) | ||
| 43 | |||
| 44 | #define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */ | ||
| 45 | #define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */ | ||
| 46 | #define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */ | ||
| 47 | #define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */ | ||
| 48 | #define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */ | ||
| 49 | #define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */ | ||
| 50 | #define MST_MSCWR1_BB_SEL (1 << 9) /* PCMCIA/Baseband multiplexer */ | ||
| 51 | #define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */ | ||
| 52 | #define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */ | ||
| 53 | |||
| 54 | #define MST_MSCWR1_IRDA_MASK (3 << 5) /* IrDA transceiver mode */ | ||
| 55 | #define MST_MSCWR1_IRDA_FULL (0 << 5) /* full distance power */ | ||
| 56 | #define MST_MSCWR1_IRDA_OFF (1 << 5) /* shutdown */ | ||
| 57 | #define MST_MSCWR1_IRDA_MED (2 << 5) /* 2/3 distance power */ | ||
| 58 | #define MST_MSCWR1_IRDA_LOW (3 << 5) /* 1/3 distance power */ | ||
| 59 | |||
| 60 | #define MST_MSCWR1_IRDA_FIR (1 << 4) /* IrDA transceiver SIR/FIR */ | ||
| 61 | #define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */ | ||
| 62 | #define MST_MSCWR1_PDC_CTL (1 << 2) /* reserved */ | ||
| 63 | #define MST_MSCWR1_MTR_ON (1 << 1) /* Silent alert motor */ | ||
| 64 | #define MST_MSCWR1_SYSRESET (1 << 0) /* System reset */ | ||
| 65 | |||
| 66 | #define MST_MSCWR2_USB_OTG_RST (1 << 6) /* USB On The Go reset */ | ||
| 67 | #define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */ | ||
| 68 | #define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */ | ||
| 69 | #define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */ | ||
| 70 | #define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */ | ||
| 71 | #define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */ | ||
| 72 | #define MST_MSCWR2_RADIO_WAKE (1 << 0) /* Radio module wake-up signal */ | ||
| 73 | |||
| 74 | #define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */ | ||
| 75 | #define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */ | ||
| 76 | #define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */ | ||
| 77 | |||
| 78 | #define MST_MSCRD_nPENIRQ (1 << 9) /* ADI7873* nPENIRQ signal */ | ||
| 79 | #define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */ | ||
| 80 | #define MST_MSCRD_nMMC_CD (1 << 7) /* SD/MMC card detection signal */ | ||
| 81 | #define MST_MSCRD_nUSIM_CD (1 << 6) /* USIM card detection signal */ | ||
| 82 | #define MST_MSCRD_USB_CBL (1 << 5) /* USB client cable status */ | ||
| 83 | #define MST_MSCRD_TS_BUSY (1 << 4) /* ADI7873 busy */ | ||
| 84 | #define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */ | ||
| 85 | #define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */ | ||
| 86 | #define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */ | ||
| 87 | #define MST_MSCRD_nMMC_WP (1 << 0) /* SD/MMC write-protect status */ | ||
| 88 | |||
| 89 | #define MST_INT_S1_IRQ (1 << 15) /* PCMCIA socket 1 IRQ */ | ||
| 90 | #define MST_INT_S1_STSCHG (1 << 14) /* PCMCIA socket 1 status changed */ | ||
| 91 | #define MST_INT_S1_CD (1 << 13) /* PCMCIA socket 1 card detection */ | ||
| 92 | #define MST_INT_S0_IRQ (1 << 11) /* PCMCIA socket 0 IRQ */ | ||
| 93 | #define MST_INT_S0_STSCHG (1 << 10) /* PCMCIA socket 0 status changed */ | ||
| 94 | #define MST_INT_S0_CD (1 << 9) /* PCMCIA socket 0 card detection */ | ||
| 95 | #define MST_INT_nEXBRD_INT (1 << 7) /* Expansion board IRQ */ | ||
| 96 | #define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */ | ||
| 97 | #define MST_INT_PENIRQ (1 << 5) /* ADI7873* touch-screen IRQ */ | ||
| 98 | #define MST_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ | ||
| 99 | #define MST_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ | ||
| 100 | #define MST_INT_USBC (1 << 2) /* USB client cable detection IRQ */ | ||
| 101 | #define MST_INT_USIM (1 << 1) /* USIM card detection IRQ */ | ||
| 102 | #define MST_INT_MMC (1 << 0) /* MMC/SD card detection IRQ */ | ||
| 103 | |||
| 104 | #define MST_PCMCIA_nIRQ (1 << 10) /* IRQ / ready signal */ | ||
| 105 | #define MST_PCMCIA_nSPKR_BVD2 (1 << 9) /* VDD sense / digital speaker */ | ||
| 106 | #define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8) /* VDD sense / card status changed */ | ||
| 107 | #define MST_PCMCIA_nVS2 (1 << 7) /* VSS voltage sense */ | ||
| 108 | #define MST_PCMCIA_nVS1 (1 << 6) /* VSS voltage sense */ | ||
| 109 | #define MST_PCMCIA_nCD (1 << 5) /* Card detection signal */ | ||
| 110 | #define MST_PCMCIA_RESET (1 << 4) /* Card reset signal */ | ||
| 111 | #define MST_PCMCIA_PWR_MASK (0x000f) /* MAX1602 power-supply controls */ | ||
| 112 | |||
| 113 | #define MST_PCMCIA_PWR_VPP_0 0x0 /* voltage VPP = 0V */ | ||
| 114 | #define MST_PCMCIA_PWR_VPP_120 0x2 /* voltage VPP = 12V*/ | ||
| 115 | #define MST_PCMCIA_PWR_VPP_VCC 0x1 /* voltage VPP = VCC */ | ||
| 116 | #define MST_PCMCIA_PWR_VCC_0 0x0 /* voltage VCC = 0V */ | ||
| 117 | #define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ | ||
| 118 | #define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ | ||
| 119 | |||
| 120 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h deleted file mode 100644 index bee81d66c184..000000000000 --- a/include/asm-arm/arch-pxa/memory.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/memory.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Copyright: (C) 2001 MontaVista Software Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 13 | #define __ASM_ARCH_MEMORY_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Physical DRAM offset. | ||
| 17 | */ | ||
| 18 | #define PHYS_OFFSET UL(0xa0000000) | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Virtual view <-> DMA view memory address translations | ||
| 22 | * virt_to_bus: Used to translate the virtual address to an | ||
| 23 | * address suitable to be passed to set_dma_addr | ||
| 24 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 25 | * to an address that the kernel can use. | ||
| 26 | */ | ||
| 27 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 28 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 29 | |||
| 30 | /* | ||
| 31 | * The nodes are matched with the physical SDRAM banks as follows: | ||
| 32 | * | ||
| 33 | * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff | ||
| 34 | * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff | ||
| 35 | * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff | ||
| 36 | * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff | ||
| 37 | * | ||
| 38 | * This needs a node mem size of 26 bits. | ||
| 39 | */ | ||
| 40 | #define NODE_MEM_SIZE_BITS 26 | ||
| 41 | |||
| 42 | #if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) | ||
| 43 | void cmx270_pci_adjust_zones(int node, unsigned long *size, | ||
| 44 | unsigned long *holes); | ||
| 45 | |||
| 46 | #define arch_adjust_zones(node, size, holes) \ | ||
| 47 | cmx270_pci_adjust_zones(node, size, holes) | ||
| 48 | |||
| 49 | #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) | ||
| 50 | #endif | ||
| 51 | |||
| 52 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/mfp-pxa25x.h b/include/asm-arm/arch-pxa/mfp-pxa25x.h deleted file mode 100644 index 0499323010ba..000000000000 --- a/include/asm-arm/arch-pxa/mfp-pxa25x.h +++ /dev/null | |||
| @@ -1,161 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA25X_H | ||
| 2 | #define __ASM_ARCH_MFP_PXA25X_H | ||
| 3 | |||
| 4 | #include <asm/arch/mfp.h> | ||
| 5 | #include <asm/arch/mfp-pxa2xx.h> | ||
| 6 | |||
| 7 | /* GPIO */ | ||
| 8 | #define GPIO2_GPIO MFP_CFG_IN(GPIO2, AF0) | ||
| 9 | #define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) | ||
| 10 | #define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) | ||
| 11 | #define GPIO5_GPIO MFP_CFG_IN(GPIO5, AF0) | ||
| 12 | #define GPIO6_GPIO MFP_CFG_IN(GPIO6, AF0) | ||
| 13 | #define GPIO7_GPIO MFP_CFG_IN(GPIO7, AF0) | ||
| 14 | #define GPIO8_GPIO MFP_CFG_IN(GPIO8, AF0) | ||
| 15 | |||
| 16 | #define GPIO1_RST MFP_CFG_IN(GPIO1, AF1) | ||
| 17 | |||
| 18 | /* Crystal and Clock Signals */ | ||
| 19 | #define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) | ||
| 20 | #define GPIO70_RTC_CLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW) | ||
| 21 | #define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW) | ||
| 22 | #define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) | ||
| 23 | #define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW) | ||
| 24 | #define GPIO12_32KHz MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) | ||
| 25 | #define GPIO72_32kHz MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW) | ||
| 26 | |||
| 27 | /* SDRAM and Static Memory I/O Signals */ | ||
| 28 | #define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) | ||
| 29 | #define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) | ||
| 30 | #define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) | ||
| 31 | #define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) | ||
| 32 | #define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) | ||
| 33 | |||
| 34 | /* Miscellaneous I/O and DMA Signals */ | ||
| 35 | #define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) | ||
| 36 | #define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) | ||
| 37 | #define GPIO19_DREQ_1 MFP_CFG_IN(GPIO19, AF1) | ||
| 38 | |||
| 39 | /* Alternate Bus Master Mode I/O Signals */ | ||
| 40 | #define GPIO13_MBGNT MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW) | ||
| 41 | #define GPIO73_MBGNT MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW) | ||
| 42 | #define GPIO14_MBREQ MFP_CFG_IN(GPIO14, AF1) | ||
| 43 | #define GPIO66_MBREQ MFP_CFG_IN(GPIO66, AF1) | ||
| 44 | |||
| 45 | /* PC CARD */ | ||
| 46 | #define GPIO52_nPCE_1 MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH) | ||
| 47 | #define GPIO53_nPCE_2 MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH) | ||
| 48 | #define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) | ||
| 49 | #define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) | ||
| 50 | #define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) | ||
| 51 | #define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) | ||
| 52 | #define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) | ||
| 53 | #define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) | ||
| 54 | #define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) | ||
| 55 | #define GPIO54_nPSKTSEL MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) | ||
| 56 | |||
| 57 | /* FFUART */ | ||
| 58 | #define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) | ||
| 59 | #define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) | ||
| 60 | #define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) | ||
| 61 | #define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) | ||
| 62 | #define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) | ||
| 63 | #define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) | ||
| 64 | #define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) | ||
| 65 | #define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) | ||
| 66 | |||
| 67 | /* BTUART */ | ||
| 68 | #define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) | ||
| 69 | #define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) | ||
| 70 | #define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) | ||
| 71 | #define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) | ||
| 72 | |||
| 73 | /* STUART */ | ||
| 74 | #define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) | ||
| 75 | #define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) | ||
| 76 | |||
| 77 | /* HWUART */ | ||
| 78 | #define GPIO42_HWUART_RXD MFP_CFG_IN(GPIO42, AF3) | ||
| 79 | #define GPIO43_HWUART_TXD MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH) | ||
| 80 | #define GPIO44_HWUART_CTS MFP_CFG_IN(GPIO44, AF3) | ||
| 81 | #define GPIO45_HWUART_RTS MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH) | ||
| 82 | #define GPIO48_HWUART_TXD MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH) | ||
| 83 | #define GPIO49_HWUART_RXD MFP_CFG_IN(GPIO49, AF1) | ||
| 84 | #define GPIO50_HWUART_CTS MFP_CFG_IN(GPIO50, AF1) | ||
| 85 | #define GPIO51_HWUART_RTS MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH) | ||
| 86 | |||
| 87 | /* FICP */ | ||
| 88 | #define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) | ||
| 89 | #define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) | ||
| 90 | |||
| 91 | /* PWM 0/1 */ | ||
| 92 | #define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) | ||
| 93 | #define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) | ||
| 94 | |||
| 95 | /* AC97 */ | ||
| 96 | #define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) | ||
| 97 | #define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) | ||
| 98 | #define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) | ||
| 99 | #define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) | ||
| 100 | #define GPIO32_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO32, AF1) | ||
| 101 | |||
| 102 | /* I2S */ | ||
| 103 | #define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) | ||
| 104 | #define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) | ||
| 105 | #define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) | ||
| 106 | #define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) | ||
| 107 | #define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) | ||
| 108 | #define GPIO32_I2S_SYSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) | ||
| 109 | |||
| 110 | /* SSP 1 */ | ||
| 111 | #define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) | ||
| 112 | #define GPIO24_SSP1_SFRM MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW) | ||
| 113 | #define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) | ||
| 114 | #define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) | ||
| 115 | #define GPIO27_SSP1_EXTCLK MFP_CFG_IN(GPIO27, AF1) | ||
| 116 | |||
| 117 | /* SSP 2 - NSSP */ | ||
| 118 | #define GPIO81_SSP2_CLK_OUT MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) | ||
| 119 | #define GPIO81_SSP2_CLK_IN MFP_CFG_IN(GPIO81, AF1) | ||
| 120 | #define GPIO82_SSP2_FRM_OUT MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW) | ||
| 121 | #define GPIO82_SSP2_FRM_IN MFP_CFG_IN(GPIO82, AF1) | ||
| 122 | #define GPIO83_SSP2_TXD MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW) | ||
| 123 | #define GPIO83_SSP2_RXD MFP_CFG_IN(GPIO83, AF2) | ||
| 124 | #define GPIO84_SSP2_TXD MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW) | ||
| 125 | #define GPIO84_SSP2_RXD MFP_CFG_IN(GPIO84, AF2) | ||
| 126 | |||
| 127 | /* MMC */ | ||
| 128 | #define GPIO6_MMC_CLK MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW) | ||
| 129 | #define GPIO8_MMC_CS0 MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW) | ||
| 130 | #define GPIO9_MMC_CS1 MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) | ||
| 131 | #define GPIO34_MMC_CS0 MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW) | ||
| 132 | #define GPIO39_MMC_CS1 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) | ||
| 133 | #define GPIO53_MMC_CLK MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) | ||
| 134 | #define GPIO54_MMC_CLK MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW) | ||
| 135 | #define GPIO69_MMC_CLK MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW) | ||
| 136 | #define GPIO67_MMC_CS0 MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW) | ||
| 137 | #define GPIO68_MMC_CS1 MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW) | ||
| 138 | |||
| 139 | /* LCD */ | ||
| 140 | #define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) | ||
| 141 | #define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) | ||
| 142 | #define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) | ||
| 143 | #define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) | ||
| 144 | #define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) | ||
| 145 | #define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) | ||
| 146 | #define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) | ||
| 147 | #define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) | ||
| 148 | #define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) | ||
| 149 | #define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) | ||
| 150 | #define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) | ||
| 151 | #define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) | ||
| 152 | #define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) | ||
| 153 | #define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) | ||
| 154 | #define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) | ||
| 155 | #define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) | ||
| 156 | #define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) | ||
| 157 | #define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) | ||
| 158 | #define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) | ||
| 159 | #define GPIO77_LCD_ACBIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) | ||
| 160 | |||
| 161 | #endif /* __ASM_ARCH_MFP_PXA25X_H */ | ||
diff --git a/include/asm-arm/arch-pxa/mfp-pxa27x.h b/include/asm-arm/arch-pxa/mfp-pxa27x.h deleted file mode 100644 index bc73ab84167c..000000000000 --- a/include/asm-arm/arch-pxa/mfp-pxa27x.h +++ /dev/null | |||
| @@ -1,433 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA27X_H | ||
| 2 | #define __ASM_ARCH_MFP_PXA27X_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * NOTE: for those special-function bidirectional GPIOs, as described | ||
| 6 | * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input | ||
| 7 | * alternative is preserved, the direction is actually selected by the | ||
| 8 | * specific controller, and this should work in most cases. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/arch/mfp.h> | ||
| 12 | #include <asm/arch/mfp-pxa2xx.h> | ||
| 13 | |||
| 14 | /* GPIO */ | ||
| 15 | #define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) | ||
| 16 | #define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) | ||
| 17 | #define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF0) | ||
| 18 | #define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF0) | ||
| 19 | #define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF0) | ||
| 20 | #define GPIO90_GPIO MFP_CFG_IN(GPIO90, AF0) | ||
| 21 | #define GPIO91_GPIO MFP_CFG_IN(GPIO91, AF0) | ||
| 22 | #define GPIO92_GPIO MFP_CFG_IN(GPIO92, AF0) | ||
| 23 | #define GPIO93_GPIO MFP_CFG_IN(GPIO93, AF0) | ||
| 24 | #define GPIO94_GPIO MFP_CFG_IN(GPIO94, AF0) | ||
| 25 | #define GPIO95_GPIO MFP_CFG_IN(GPIO95, AF0) | ||
| 26 | #define GPIO96_GPIO MFP_CFG_IN(GPIO96, AF0) | ||
| 27 | #define GPIO97_GPIO MFP_CFG_IN(GPIO97, AF0) | ||
| 28 | #define GPIO98_GPIO MFP_CFG_IN(GPIO98, AF0) | ||
| 29 | #define GPIO99_GPIO MFP_CFG_IN(GPIO99, AF0) | ||
| 30 | #define GPIO100_GPIO MFP_CFG_IN(GPIO100, AF0) | ||
| 31 | #define GPIO101_GPIO MFP_CFG_IN(GPIO101, AF0) | ||
| 32 | #define GPIO102_GPIO MFP_CFG_IN(GPIO102, AF0) | ||
| 33 | #define GPIO103_GPIO MFP_CFG_IN(GPIO103, AF0) | ||
| 34 | #define GPIO104_GPIO MFP_CFG_IN(GPIO104, AF0) | ||
| 35 | #define GPIO105_GPIO MFP_CFG_IN(GPIO105, AF0) | ||
| 36 | #define GPIO106_GPIO MFP_CFG_IN(GPIO106, AF0) | ||
| 37 | #define GPIO107_GPIO MFP_CFG_IN(GPIO107, AF0) | ||
| 38 | #define GPIO108_GPIO MFP_CFG_IN(GPIO108, AF0) | ||
| 39 | #define GPIO109_GPIO MFP_CFG_IN(GPIO109, AF0) | ||
| 40 | #define GPIO110_GPIO MFP_CFG_IN(GPIO110, AF0) | ||
| 41 | #define GPIO111_GPIO MFP_CFG_IN(GPIO111, AF0) | ||
| 42 | #define GPIO112_GPIO MFP_CFG_IN(GPIO112, AF0) | ||
| 43 | #define GPIO113_GPIO MFP_CFG_IN(GPIO113, AF0) | ||
| 44 | #define GPIO114_GPIO MFP_CFG_IN(GPIO114, AF0) | ||
| 45 | #define GPIO115_GPIO MFP_CFG_IN(GPIO115, AF0) | ||
| 46 | #define GPIO116_GPIO MFP_CFG_IN(GPIO116, AF0) | ||
| 47 | #define GPIO117_GPIO MFP_CFG_IN(GPIO117, AF0) | ||
| 48 | #define GPIO118_GPIO MFP_CFG_IN(GPIO118, AF0) | ||
| 49 | #define GPIO119_GPIO MFP_CFG_IN(GPIO119, AF0) | ||
| 50 | #define GPIO120_GPIO MFP_CFG_IN(GPIO120, AF0) | ||
| 51 | |||
| 52 | /* Crystal and Clock Signals */ | ||
| 53 | #define GPIO9_HZ_CLK MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) | ||
| 54 | #define GPIO10_HZ_CLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) | ||
| 55 | #define GPIO11_48_MHz MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW) | ||
| 56 | #define GPIO12_48_MHz MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW) | ||
| 57 | #define GPIO13_CLK_EXT MFP_CFG_IN(GPIO13, AF1) | ||
| 58 | |||
| 59 | /* OS Timer Signals */ | ||
| 60 | #define GPIO11_EXT_SYNC_0 MFP_CFG_IN(GPIO11, AF1) | ||
| 61 | #define GPIO12_EXT_SYNC_1 MFP_CFG_IN(GPIO12, AF1) | ||
| 62 | #define GPIO9_CHOUT_0 MFP_CFG_OUT(GPIO9, AF3, DRIVE_LOW) | ||
| 63 | #define GPIO10_CHOUT_1 MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW) | ||
| 64 | #define GPIO11_CHOUT_0 MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) | ||
| 65 | #define GPIO12_CHOUT_1 MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) | ||
| 66 | |||
| 67 | /* SDRAM and Static Memory I/O Signals */ | ||
| 68 | #define GPIO20_nSDCS_2 MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH) | ||
| 69 | #define GPIO21_nSDCS_3 MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH) | ||
| 70 | #define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) | ||
| 71 | #define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) | ||
| 72 | #define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) | ||
| 73 | #define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) | ||
| 74 | #define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) | ||
| 75 | |||
| 76 | /* Miscellaneous I/O and DMA Signals */ | ||
| 77 | #define GPIO21_DVAL_0 MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH) | ||
| 78 | #define GPIO116_DVAL_0 MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH) | ||
| 79 | #define GPIO33_DVAL_1 MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH) | ||
| 80 | #define GPIO96_DVAL_1 MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH) | ||
| 81 | #define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) | ||
| 82 | #define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) | ||
| 83 | #define GPIO115_DREQ_0 MFP_CFG_IN(GPIO115, AF1) | ||
| 84 | #define GPIO80_DREQ_1 MFP_CFG_IN(GPIO80, AF1) | ||
| 85 | #define GPIO97_DREQ_1 MFP_CFG_IN(GPIO97, AF2) | ||
| 86 | #define GPIO85_DREQ_2 MFP_CFG_IN(GPIO85, AF2) | ||
| 87 | #define GPIO100_DREQ_2 MFP_CFG_IN(GPIO100, AF2) | ||
| 88 | |||
| 89 | /* Alternate Bus Master Mode I/O Signals */ | ||
| 90 | #define GPIO20_MBREQ MFP_CFG_IN(GPIO20, AF2) | ||
| 91 | #define GPIO80_MBREQ MFP_CFG_IN(GPIO80, AF2) | ||
| 92 | #define GPIO96_MBREQ MFP_CFG_IN(GPIO96, AF2) | ||
| 93 | #define GPIO115_MBREQ MFP_CFG_IN(GPIO115, AF3) | ||
| 94 | #define GPIO21_MBGNT MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW) | ||
| 95 | #define GPIO33_MBGNT MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW) | ||
| 96 | #define GPIO97_MBGNT MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW) | ||
| 97 | #define GPIO116_MBGNT MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW) | ||
| 98 | |||
| 99 | /* PC CARD */ | ||
| 100 | #define GPIO15_nPCE_1 MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH) | ||
| 101 | #define GPIO85_nPCE_1 MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH) | ||
| 102 | #define GPIO86_nPCE_1 MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH) | ||
| 103 | #define GPIO102_nPCE_1 MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH) | ||
| 104 | #define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) | ||
| 105 | #define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH) | ||
| 106 | #define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1) | ||
| 107 | #define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) | ||
| 108 | #define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) | ||
| 109 | #define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) | ||
| 110 | #define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) | ||
| 111 | #define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) | ||
| 112 | #define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) | ||
| 113 | #define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) | ||
| 114 | #define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH) | ||
| 115 | #define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH) | ||
| 116 | |||
| 117 | /* I2C */ | ||
| 118 | #define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1) | ||
| 119 | #define GPIO118_I2C_SDA MFP_CFG_IN(GPIO118, AF1) | ||
| 120 | |||
| 121 | /* FFUART */ | ||
| 122 | #define GPIO9_FFUART_CTS MFP_CFG_IN(GPIO9, AF3) | ||
| 123 | #define GPIO26_FFUART_CTS MFP_CFG_IN(GPIO26, AF3) | ||
| 124 | #define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) | ||
| 125 | #define GPIO100_FFUART_CTS MFP_CFG_IN(GPIO100, AF3) | ||
| 126 | #define GPIO10_FFUART_DCD MFP_CFG_IN(GPIO10, AF1) | ||
| 127 | #define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) | ||
| 128 | #define GPIO33_FFUART_DSR MFP_CFG_IN(GPIO33, AF2) | ||
| 129 | #define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) | ||
| 130 | #define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) | ||
| 131 | #define GPIO89_FFUART_RI MFP_CFG_IN(GPIO89, AF3) | ||
| 132 | #define GPIO19_FFUART_RXD MFP_CFG_IN(GPIO19, AF3) | ||
| 133 | #define GPIO33_FFUART_RXD MFP_CFG_IN(GPIO33, AF1) | ||
| 134 | #define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) | ||
| 135 | #define GPIO41_FFUART_RXD MFP_CFG_IN(GPIO41, AF1) | ||
| 136 | #define GPIO53_FFUART_RXD MFP_CFG_IN(GPIO53, AF1) | ||
| 137 | #define GPIO85_FFUART_RXD MFP_CFG_IN(GPIO85, AF1) | ||
| 138 | #define GPIO96_FFUART_RXD MFP_CFG_IN(GPIO96, AF3) | ||
| 139 | #define GPIO102_FFUART_RXD MFP_CFG_IN(GPIO102, AF3) | ||
| 140 | #define GPIO16_FFUART_TXD MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH) | ||
| 141 | #define GPIO37_FFUART_TXD MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH) | ||
| 142 | #define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) | ||
| 143 | #define GPIO83_FFUART_TXD MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH) | ||
| 144 | #define GPIO99_FFUART_TXD MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH) | ||
| 145 | #define GPIO27_FFUART_RTS MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH) | ||
| 146 | #define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) | ||
| 147 | #define GPIO83_FFUART_RTS MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH) | ||
| 148 | #define GPIO98_FFUART_RTS MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH) | ||
| 149 | #define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) | ||
| 150 | #define GPIO82_FFUART_DTR MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH) | ||
| 151 | |||
| 152 | /* BTUART */ | ||
| 153 | #define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) | ||
| 154 | #define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) | ||
| 155 | #define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) | ||
| 156 | #define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) | ||
| 157 | |||
| 158 | /* STUART */ | ||
| 159 | #define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) | ||
| 160 | #define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) | ||
| 161 | |||
| 162 | /* FICP */ | ||
| 163 | #define GPIO42_FICP_RXD MFP_CFG_IN(GPIO42, AF2) | ||
| 164 | #define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) | ||
| 165 | #define GPIO43_FICP_TXD MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH) | ||
| 166 | #define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) | ||
| 167 | |||
| 168 | /* PWM 0/1/2/3 */ | ||
| 169 | #define GPIO11_PWM2_OUT MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW) | ||
| 170 | #define GPIO12_PWM3_OUT MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW) | ||
| 171 | #define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) | ||
| 172 | #define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) | ||
| 173 | #define GPIO38_PWM1_OUT MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW) | ||
| 174 | #define GPIO46_PWM2_OUT MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW) | ||
| 175 | #define GPIO47_PWM3_OUT MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW) | ||
| 176 | #define GPIO79_PWM2_OUT MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW) | ||
| 177 | #define GPIO80_PWM3_OUT MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW) | ||
| 178 | #define GPIO115_PWM1_OUT MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW) | ||
| 179 | |||
| 180 | /* AC97 */ | ||
| 181 | #define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) | ||
| 182 | #define GPIO94_AC97_SYNC MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW) | ||
| 183 | #define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) | ||
| 184 | #define GPIO93_AC97_SDATA_OUT MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW) | ||
| 185 | #define GPIO45_AC97_SYSCLK MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW) | ||
| 186 | #define GPIO89_AC97_SYSCLK MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW) | ||
| 187 | #define GPIO98_AC97_SYSCLK MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW) | ||
| 188 | #define GPIO95_AC97_nRESET MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW) | ||
| 189 | #define GPIO113_AC97_nRESET MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW) | ||
| 190 | #define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) | ||
| 191 | #define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) | ||
| 192 | #define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2) | ||
| 193 | #define GPIO99_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO99, AF2) | ||
| 194 | |||
| 195 | /* I2S */ | ||
| 196 | #define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) | ||
| 197 | #define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) | ||
| 198 | #define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) | ||
| 199 | #define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) | ||
| 200 | #define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) | ||
| 201 | #define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW) | ||
| 202 | |||
| 203 | /* SSP 1 */ | ||
| 204 | #define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) | ||
| 205 | #define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3) | ||
| 206 | #define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW) | ||
| 207 | #define GPIO53_SSP1_SYSCLK MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW) | ||
| 208 | #define GPIO24_SSP1_SFRM MFP_CFG_IN(GPIO24, AF2) | ||
| 209 | #define GPIO28_SSP1_SFRM MFP_CFG_IN(GPIO28, AF3) | ||
| 210 | #define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) | ||
| 211 | #define GPIO57_SSP1_TXD MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW) | ||
| 212 | #define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) | ||
| 213 | #define GPIO27_SSP1_SCLKEN MFP_CFG_IN(GPIO27, AF2) | ||
| 214 | |||
| 215 | /* SSP 2 */ | ||
| 216 | #define GPIO19_SSP2_SCLK MFP_CFG_IN(GPIO19, AF1) | ||
| 217 | #define GPIO22_SSP2_SCLK MFP_CFG_IN(GPIO22, AF3) | ||
| 218 | #define GPIO29_SSP2_SCLK MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW) | ||
| 219 | #define GPIO36_SSP2_SCLK MFP_CFG_IN(GPIO36, AF2) | ||
| 220 | #define GPIO50_SSP2_SCLK MFP_CFG_IN(GPIO50, AF3) | ||
| 221 | #define GPIO22_SSP2_SYSCLK MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW) | ||
| 222 | #define GPIO14_SSP2_SFRM MFP_CFG_IN(GPIO14, AF2) | ||
| 223 | #define GPIO37_SSP2_SFRM MFP_CFG_IN(GPIO37, AF2) | ||
| 224 | #define GPIO87_SSP2_SFRM MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW) | ||
| 225 | #define GPIO88_SSP2_SFRM MFP_CFG_IN(GPIO88, AF3) | ||
| 226 | #define GPIO13_SSP2_TXD MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW) | ||
| 227 | #define GPIO38_SSP2_TXD MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW) | ||
| 228 | #define GPIO87_SSP2_TXD MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW) | ||
| 229 | #define GPIO89_SSP2_TXD MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW) | ||
| 230 | #define GPIO11_SSP2_RXD MFP_CFG_IN(GPIO11, AF2) | ||
| 231 | #define GPIO29_SSP2_RXD MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW) | ||
| 232 | #define GPIO40_SSP2_RXD MFP_CFG_IN(GPIO40, AF1) | ||
| 233 | #define GPIO86_SSP2_RXD MFP_CFG_IN(GPIO86, AF1) | ||
| 234 | #define GPIO88_SSP2_RXD MFP_CFG_IN(GPIO88, AF2) | ||
| 235 | #define GPIO22_SSP2_EXTCLK MFP_CFG_IN(GPIO22, AF1) | ||
| 236 | #define GPIO27_SSP2_EXTCLK MFP_CFG_IN(GPIO27, AF1) | ||
| 237 | #define GPIO22_SSP2_SCLKEN MFP_CFG_IN(GPIO22, AF2) | ||
| 238 | #define GPIO23_SSP2_SCLKEN MFP_CFG_IN(GPIO23, AF2) | ||
| 239 | |||
| 240 | /* SSP 3 */ | ||
| 241 | #define GPIO34_SSP3_SCLK MFP_CFG_IN(GPIO34, AF3) | ||
| 242 | #define GPIO40_SSP3_SCLK MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW) | ||
| 243 | #define GPIO52_SSP3_SCLK MFP_CFG_IN(GPIO52, AF2) | ||
| 244 | #define GPIO84_SSP3_SCLK MFP_CFG_IN(GPIO84, AF1) | ||
| 245 | #define GPIO45_SSP3_SYSCLK MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW) | ||
| 246 | #define GPIO35_SSP3_SFRM MFP_CFG_IN(GPIO35, AF3) | ||
| 247 | #define GPIO39_SSP3_SFRM MFP_CFG_IN(GPIO39, AF3) | ||
| 248 | #define GPIO83_SSP3_SFRM MFP_CFG_IN(GPIO83, AF1) | ||
| 249 | #define GPIO35_SSP3_TXD MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW) | ||
| 250 | #define GPIO38_SSP3_TXD MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW) | ||
| 251 | #define GPIO81_SSP3_TXD MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) | ||
| 252 | #define GPIO41_SSP3_RXD MFP_CFG_IN(GPIO41, AF3) | ||
| 253 | #define GPIO82_SSP3_RXD MFP_CFG_IN(GPIO82, AF1) | ||
| 254 | #define GPIO89_SSP3_RXD MFP_CFG_IN(GPIO89, AF1) | ||
| 255 | |||
| 256 | /* MMC */ | ||
| 257 | #define GPIO32_MMC_CLK MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW) | ||
| 258 | #define GPIO92_MMC_DAT_0 MFP_CFG_IN(GPIO92, AF1) | ||
| 259 | #define GPIO109_MMC_DAT_1 MFP_CFG_IN(GPIO109, AF1) | ||
| 260 | #define GPIO110_MMC_DAT_2 MFP_CFG_IN(GPIO110, AF1) | ||
| 261 | #define GPIO111_MMC_DAT_3 MFP_CFG_IN(GPIO111, AF1) | ||
| 262 | #define GPIO112_MMC_CMD MFP_CFG_IN(GPIO112, AF1) | ||
| 263 | |||
| 264 | /* LCD */ | ||
| 265 | #define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) | ||
| 266 | #define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) | ||
| 267 | #define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) | ||
| 268 | #define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) | ||
| 269 | #define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) | ||
| 270 | #define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) | ||
| 271 | #define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) | ||
| 272 | #define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) | ||
| 273 | #define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) | ||
| 274 | #define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) | ||
| 275 | #define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) | ||
| 276 | #define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) | ||
| 277 | #define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) | ||
| 278 | #define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) | ||
| 279 | #define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) | ||
| 280 | #define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) | ||
| 281 | #define GPIO86_LCD_LDD_16 MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW) | ||
| 282 | #define GPIO87_LCD_LDD_17 MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW) | ||
| 283 | #define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) | ||
| 284 | #define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) | ||
| 285 | #define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) | ||
| 286 | #define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) | ||
| 287 | #define GPIO14_LCD_VSYNC MFP_CFG_IN(GPIO14, AF1) | ||
| 288 | #define GPIO19_LCD_CS MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW) | ||
| 289 | |||
| 290 | /* Keypad */ | ||
| 291 | #define GPIO93_KP_DKIN_0 MFP_CFG_IN(GPIO93, AF1) | ||
| 292 | #define GPIO94_KP_DKIN_1 MFP_CFG_IN(GPIO94, AF1) | ||
| 293 | #define GPIO95_KP_DKIN_2 MFP_CFG_IN(GPIO95, AF1) | ||
| 294 | #define GPIO96_KP_DKIN_3 MFP_CFG_IN(GPIO96, AF1) | ||
| 295 | #define GPIO97_KP_DKIN_4 MFP_CFG_IN(GPIO97, AF1) | ||
| 296 | #define GPIO98_KP_DKIN_5 MFP_CFG_IN(GPIO98, AF1) | ||
| 297 | #define GPIO99_KP_DKIN_6 MFP_CFG_IN(GPIO99, AF1) | ||
| 298 | #define GPIO13_KP_KDIN_7 MFP_CFG_IN(GPIO13, AF2) | ||
| 299 | #define GPIO100_KP_MKIN_0 MFP_CFG_IN(GPIO100, AF1) | ||
| 300 | #define GPIO101_KP_MKIN_1 MFP_CFG_IN(GPIO101, AF1) | ||
| 301 | #define GPIO102_KP_MKIN_2 MFP_CFG_IN(GPIO102, AF1) | ||
| 302 | #define GPIO34_KP_MKIN_3 MFP_CFG_IN(GPIO34, AF2) | ||
| 303 | #define GPIO37_KP_MKIN_3 MFP_CFG_IN(GPIO37, AF3) | ||
| 304 | #define GPIO97_KP_MKIN_3 MFP_CFG_IN(GPIO97, AF3) | ||
| 305 | #define GPIO98_KP_MKIN_4 MFP_CFG_IN(GPIO98, AF3) | ||
| 306 | #define GPIO38_KP_MKIN_4 MFP_CFG_IN(GPIO38, AF2) | ||
| 307 | #define GPIO39_KP_MKIN_4 MFP_CFG_IN(GPIO39, AF1) | ||
| 308 | #define GPIO16_KP_MKIN_5 MFP_CFG_IN(GPIO16, AF1) | ||
| 309 | #define GPIO90_KP_MKIN_5 MFP_CFG_IN(GPIO90, AF1) | ||
| 310 | #define GPIO99_KP_MKIN_5 MFP_CFG_IN(GPIO99, AF3) | ||
| 311 | #define GPIO17_KP_MKIN_6 MFP_CFG_IN(GPIO17, AF1) | ||
| 312 | #define GPIO91_KP_MKIN_6 MFP_CFG_IN(GPIO91, AF1) | ||
| 313 | #define GPIO95_KP_MKIN_6 MFP_CFG_IN(GPIO95, AF3) | ||
| 314 | #define GPIO13_KP_MKIN_7 MFP_CFG_IN(GPIO13, AF3) | ||
| 315 | #define GPIO36_KP_MKIN_7 MFP_CFG_IN(GPIO36, AF3) | ||
| 316 | #define GPIO103_KP_MKOUT_0 MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH) | ||
| 317 | #define GPIO104_KP_MKOUT_1 MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH) | ||
| 318 | #define GPIO105_KP_MKOUT_2 MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH) | ||
| 319 | #define GPIO106_KP_MKOUT_3 MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH) | ||
| 320 | #define GPIO107_KP_MKOUT_4 MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH) | ||
| 321 | #define GPIO108_KP_MKOUT_5 MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH) | ||
| 322 | #define GPIO35_KP_MKOUT_6 MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH) | ||
| 323 | #define GPIO22_KP_MKOUT_7 MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH) | ||
| 324 | #define GPIO40_KP_MKOUT_6 MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH) | ||
| 325 | #define GPIO41_KP_MKOUT_7 MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH) | ||
| 326 | #define GPIO96_KP_MKOUT_6 MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH) | ||
| 327 | |||
| 328 | /* USB P3 */ | ||
| 329 | #define GPIO10_USB_P3_5 MFP_CFG_IN(GPIO10, AF3) | ||
| 330 | #define GPIO11_USB_P3_1 MFP_CFG_IN(GPIO11, AF3) | ||
| 331 | #define GPIO30_USB_P3_2 MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) | ||
| 332 | #define GPIO31_USB_P3_6 MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) | ||
| 333 | #define GPIO56_USB_P3_4 MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) | ||
| 334 | #define GPIO86_USB_P3_5 MFP_CFG_IN(GPIO86, AF3) | ||
| 335 | #define GPIO87_USB_P3_1 MFP_CFG_IN(GPIO87, AF3) | ||
| 336 | #define GPIO90_USB_P3_5 MFP_CFG_IN(GPIO90, AF2) | ||
| 337 | #define GPIO91_USB_P3_1 MFP_CFG_IN(GPIO91, AF2) | ||
| 338 | #define GPIO113_USB_P3_3 MFP_CFG_IN(GPIO113, AF3) | ||
| 339 | |||
| 340 | /* USB P2 */ | ||
| 341 | #define GPIO34_USB_P2_2 MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW) | ||
| 342 | #define GPIO35_USB_P2_1 MFP_CFG_IN(GPIO35, AF2) | ||
| 343 | #define GPIO36_USB_P2_4 MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW) | ||
| 344 | #define GPIO37_USB_P2_8 MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW) | ||
| 345 | #define GPIO38_USB_P2_3 MFP_CFG_IN(GPIO38, AF3) | ||
| 346 | #define GPIO39_USB_P2_6 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) | ||
| 347 | #define GPIO40_USB_P2_5 MFP_CFG_IN(GPIO40, AF3) | ||
| 348 | #define GPIO41_USB_P2_7 MFP_CFG_IN(GPIO41, AF2) | ||
| 349 | #define GPIO53_USB_P2_3 MFP_CFG_IN(GPIO53, AF2) | ||
| 350 | |||
| 351 | /* USB Host Port 1/2 */ | ||
| 352 | #define GPIO88_USBH1_PWR MFP_CFG_IN(GPIO88, AF1) | ||
| 353 | #define GPIO89_USBH1_PEN MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW) | ||
| 354 | #define GPIO119_USBH2_PWR MFP_CFG_IN(GPIO119, AF1) | ||
| 355 | #define GPIO120_USBH2_PEN MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW) | ||
| 356 | |||
| 357 | /* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */ | ||
| 358 | #define GPIO115_CIF_DD_3 MFP_CFG_IN(GPIO115, AF2) | ||
| 359 | #define GPIO116_CIF_DD_2 MFP_CFG_IN(GPIO116, AF1) | ||
| 360 | #define GPIO12_CIF_DD_7 MFP_CFG_IN(GPIO12, AF2) | ||
| 361 | #define GPIO17_CIF_DD_6 MFP_CFG_IN(GPIO17, AF2) | ||
| 362 | #define GPIO23_CIF_MCLK MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW) | ||
| 363 | #define GPIO24_CIF_FV MFP_CFG_IN(GPIO24, AF1) | ||
| 364 | #define GPIO25_CIF_LV MFP_CFG_IN(GPIO25, AF1) | ||
| 365 | #define GPIO26_CIF_PCLK MFP_CFG_IN(GPIO26, AF2) | ||
| 366 | #define GPIO27_CIF_DD_0 MFP_CFG_IN(GPIO27, AF3) | ||
| 367 | #define GPIO42_CIF_MCLK MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW) | ||
| 368 | #define GPIO43_CIF_FV MFP_CFG_IN(GPIO43, AF3) | ||
| 369 | #define GPIO44_CIF_LV MFP_CFG_IN(GPIO44, AF3) | ||
| 370 | #define GPIO45_CIF_PCLK MFP_CFG_IN(GPIO45, AF3) | ||
| 371 | #define GPIO47_CIF_DD_0 MFP_CFG_IN(GPIO47, AF1) | ||
| 372 | #define GPIO48_CIF_DD_5 MFP_CFG_IN(GPIO48, AF1) | ||
| 373 | #define GPIO50_CIF_DD_3 MFP_CFG_IN(GPIO50, AF1) | ||
| 374 | #define GPIO51_CIF_DD_2 MFP_CFG_IN(GPIO51, AF1) | ||
| 375 | #define GPIO52_CIF_DD_4 MFP_CFG_IN(GPIO52, AF1) | ||
| 376 | #define GPIO53_CIF_MCLK MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW) | ||
| 377 | #define GPIO54_CIF_PCLK MFP_CFG_IN(GPIO54, AF3) | ||
| 378 | #define GPIO55_CIF_DD_1 MFP_CFG_IN(GPIO55, AF1) | ||
| 379 | #define GPIO81_CIF_DD_0 MFP_CFG_IN(GPIO81, AF2) | ||
| 380 | #define GPIO82_CIF_DD_5 MFP_CFG_IN(GPIO82, AF3) | ||
| 381 | #define GPIO83_CIF_DD_4 MFP_CFG_IN(GPIO83, AF3) | ||
| 382 | #define GPIO84_CIF_FV MFP_CFG_IN(GPIO84, AF3) | ||
| 383 | #define GPIO85_CIF_LV MFP_CFG_IN(GPIO85, AF3) | ||
| 384 | #define GPIO90_CIF_DD_4 MFP_CFG_IN(GPIO90, AF3) | ||
| 385 | #define GPIO91_CIF_DD_5 MFP_CFG_IN(GPIO91, AF3) | ||
| 386 | #define GPIO93_CIF_DD_6 MFP_CFG_IN(GPIO93, AF2) | ||
| 387 | #define GPIO94_CIF_DD_5 MFP_CFG_IN(GPIO94, AF2) | ||
| 388 | #define GPIO95_CIF_DD_4 MFP_CFG_IN(GPIO95, AF2) | ||
| 389 | #define GPIO98_CIF_DD_0 MFP_CFG_IN(GPIO98, AF2) | ||
| 390 | #define GPIO103_CIF_DD_3 MFP_CFG_IN(GPIO103, AF1) | ||
| 391 | #define GPIO104_CIF_DD_2 MFP_CFG_IN(GPIO104, AF1) | ||
| 392 | #define GPIO105_CIF_DD_1 MFP_CFG_IN(GPIO105, AF1) | ||
| 393 | #define GPIO106_CIF_DD_9 MFP_CFG_IN(GPIO106, AF1) | ||
| 394 | #define GPIO107_CIF_DD_8 MFP_CFG_IN(GPIO107, AF1) | ||
| 395 | #define GPIO108_CIF_DD_7 MFP_CFG_IN(GPIO108, AF1) | ||
| 396 | #define GPIO114_CIF_DD_1 MFP_CFG_IN(GPIO114, AF1) | ||
| 397 | |||
| 398 | /* Universal Subscriber ID Interface */ | ||
| 399 | #define GPIO114_UVS0 MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW) | ||
| 400 | #define GPIO115_nUVS1 MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW) | ||
| 401 | #define GPIO116_nUVS2 MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW) | ||
| 402 | #define GPIO14_UCLK MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW) | ||
| 403 | #define GPIO91_UCLK MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW) | ||
| 404 | #define GPIO19_nURST MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW) | ||
| 405 | #define GPIO90_nURST MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW) | ||
| 406 | #define GPIO116_UDET MFP_CFG_IN(GPIO116, AF3) | ||
| 407 | #define GPIO114_UEN MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW) | ||
| 408 | #define GPIO115_UEN MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW) | ||
| 409 | |||
| 410 | /* Mobile Scalable Link (MSL) Interface */ | ||
| 411 | #define GPIO81_BB_OB_DAT_0 MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW) | ||
| 412 | #define GPIO48_BB_OB_DAT_1 MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW) | ||
| 413 | #define GPIO50_BB_OB_DAT_2 MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW) | ||
| 414 | #define GPIO51_BB_OB_DAT_3 MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW) | ||
| 415 | #define GPIO52_BB_OB_CLK MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW) | ||
| 416 | #define GPIO53_BB_OB_STB MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) | ||
| 417 | #define GPIO54_BB_OB_WAIT MFP_CFG_IN(GPIO54, AF2) | ||
| 418 | #define GPIO82_BB_IB_DAT_0 MFP_CFG_IN(GPIO82, AF2) | ||
| 419 | #define GPIO55_BB_IB_DAT_1 MFP_CFG_IN(GPIO55, AF2) | ||
| 420 | #define GPIO56_BB_IB_DAT_2 MFP_CFG_IN(GPIO56, AF2) | ||
| 421 | #define GPIO57_BB_IB_DAT_3 MFP_CFG_IN(GPIO57, AF2) | ||
| 422 | #define GPIO83_BB_IB_CLK MFP_CFG_IN(GPIO83, AF2) | ||
| 423 | #define GPIO84_BB_IB_STB MFP_CFG_IN(GPIO84, AF2) | ||
| 424 | #define GPIO85_BB_IB_WAIT MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW) | ||
| 425 | |||
| 426 | /* Memory Stick Host Controller */ | ||
| 427 | #define GPIO92_MSBS MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW) | ||
| 428 | #define GPIO109_MSSDIO MFP_CFG_IN(GPIO109, AF2) | ||
| 429 | #define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2) | ||
| 430 | #define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) | ||
| 431 | |||
| 432 | extern int keypad_set_wake(unsigned int on); | ||
| 433 | #endif /* __ASM_ARCH_MFP_PXA27X_H */ | ||
diff --git a/include/asm-arm/arch-pxa/mfp-pxa2xx.h b/include/asm-arm/arch-pxa/mfp-pxa2xx.h deleted file mode 100644 index 8de1c0dae624..000000000000 --- a/include/asm-arm/arch-pxa/mfp-pxa2xx.h +++ /dev/null | |||
| @@ -1,133 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA2XX_H | ||
| 2 | #define __ASM_ARCH_MFP_PXA2XX_H | ||
| 3 | |||
| 4 | #include <asm/arch/mfp.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: | ||
| 8 | * | ||
| 9 | * MFP_PIN(x) | ||
| 10 | * MFP_AFx | ||
| 11 | * MFP_LPM_DRIVE_{LOW, HIGH} | ||
| 12 | * MFP_LPM_EDGE_x | ||
| 13 | * | ||
| 14 | * other MFP_x bit definitions will be ignored | ||
| 15 | * | ||
| 16 | * and adds the below two bits specifically for pxa2xx: | ||
| 17 | * | ||
| 18 | * bit 23 - Input/Output (PXA2xx specific) | ||
| 19 | * bit 24 - Wakeup Enable(PXA2xx specific) | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define MFP_DIR_IN (0x0 << 23) | ||
| 23 | #define MFP_DIR_OUT (0x1 << 23) | ||
| 24 | #define MFP_DIR_MASK (0x1 << 23) | ||
| 25 | #define MFP_DIR(x) (((x) >> 23) & 0x1) | ||
| 26 | |||
| 27 | #define MFP_LPM_CAN_WAKEUP (0x1 << 24) | ||
| 28 | #define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) | ||
| 29 | #define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL) | ||
| 30 | #define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH) | ||
| 31 | |||
| 32 | /* specifically for enabling wakeup on keypad GPIOs */ | ||
| 33 | #define WAKEUP_ON_LEVEL_HIGH (MFP_LPM_CAN_WAKEUP) | ||
| 34 | |||
| 35 | #define MFP_CFG_IN(pin, af) \ | ||
| 36 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ | ||
| 37 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN)) | ||
| 38 | |||
| 39 | /* NOTE: pins configured as output _must_ provide a low power state, | ||
| 40 | * and this state should help to minimize the power dissipation. | ||
| 41 | */ | ||
| 42 | #define MFP_CFG_OUT(pin, af, state) \ | ||
| 43 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ | ||
| 44 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) | ||
| 45 | |||
| 46 | /* Common configurations for pxa25x and pxa27x | ||
| 47 | * | ||
| 48 | * Note: pins configured as GPIO are always initialized to input | ||
| 49 | * so not to cause any side effect | ||
| 50 | */ | ||
| 51 | #define GPIO0_GPIO MFP_CFG_IN(GPIO0, AF0) | ||
| 52 | #define GPIO1_GPIO MFP_CFG_IN(GPIO1, AF0) | ||
| 53 | #define GPIO9_GPIO MFP_CFG_IN(GPIO9, AF0) | ||
| 54 | #define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0) | ||
| 55 | #define GPIO11_GPIO MFP_CFG_IN(GPIO11, AF0) | ||
| 56 | #define GPIO12_GPIO MFP_CFG_IN(GPIO12, AF0) | ||
| 57 | #define GPIO13_GPIO MFP_CFG_IN(GPIO13, AF0) | ||
| 58 | #define GPIO14_GPIO MFP_CFG_IN(GPIO14, AF0) | ||
| 59 | #define GPIO15_GPIO MFP_CFG_IN(GPIO15, AF0) | ||
| 60 | #define GPIO16_GPIO MFP_CFG_IN(GPIO16, AF0) | ||
| 61 | #define GPIO17_GPIO MFP_CFG_IN(GPIO17, AF0) | ||
| 62 | #define GPIO18_GPIO MFP_CFG_IN(GPIO18, AF0) | ||
| 63 | #define GPIO19_GPIO MFP_CFG_IN(GPIO19, AF0) | ||
| 64 | #define GPIO20_GPIO MFP_CFG_IN(GPIO20, AF0) | ||
| 65 | #define GPIO21_GPIO MFP_CFG_IN(GPIO21, AF0) | ||
| 66 | #define GPIO22_GPIO MFP_CFG_IN(GPIO22, AF0) | ||
| 67 | #define GPIO23_GPIO MFP_CFG_IN(GPIO23, AF0) | ||
| 68 | #define GPIO24_GPIO MFP_CFG_IN(GPIO24, AF0) | ||
| 69 | #define GPIO25_GPIO MFP_CFG_IN(GPIO25, AF0) | ||
| 70 | #define GPIO26_GPIO MFP_CFG_IN(GPIO26, AF0) | ||
| 71 | #define GPIO27_GPIO MFP_CFG_IN(GPIO27, AF0) | ||
| 72 | #define GPIO28_GPIO MFP_CFG_IN(GPIO28, AF0) | ||
| 73 | #define GPIO29_GPIO MFP_CFG_IN(GPIO29, AF0) | ||
| 74 | #define GPIO30_GPIO MFP_CFG_IN(GPIO30, AF0) | ||
| 75 | #define GPIO31_GPIO MFP_CFG_IN(GPIO31, AF0) | ||
| 76 | #define GPIO32_GPIO MFP_CFG_IN(GPIO32, AF0) | ||
| 77 | #define GPIO33_GPIO MFP_CFG_IN(GPIO33, AF0) | ||
| 78 | #define GPIO34_GPIO MFP_CFG_IN(GPIO34, AF0) | ||
| 79 | #define GPIO35_GPIO MFP_CFG_IN(GPIO35, AF0) | ||
| 80 | #define GPIO36_GPIO MFP_CFG_IN(GPIO36, AF0) | ||
| 81 | #define GPIO37_GPIO MFP_CFG_IN(GPIO37, AF0) | ||
| 82 | #define GPIO38_GPIO MFP_CFG_IN(GPIO38, AF0) | ||
| 83 | #define GPIO39_GPIO MFP_CFG_IN(GPIO39, AF0) | ||
| 84 | #define GPIO40_GPIO MFP_CFG_IN(GPIO40, AF0) | ||
| 85 | #define GPIO41_GPIO MFP_CFG_IN(GPIO41, AF0) | ||
| 86 | #define GPIO42_GPIO MFP_CFG_IN(GPIO42, AF0) | ||
| 87 | #define GPIO43_GPIO MFP_CFG_IN(GPIO43, AF0) | ||
| 88 | #define GPIO44_GPIO MFP_CFG_IN(GPIO44, AF0) | ||
| 89 | #define GPIO45_GPIO MFP_CFG_IN(GPIO45, AF0) | ||
| 90 | #define GPIO46_GPIO MFP_CFG_IN(GPIO46, AF0) | ||
| 91 | #define GPIO47_GPIO MFP_CFG_IN(GPIO47, AF0) | ||
| 92 | #define GPIO48_GPIO MFP_CFG_IN(GPIO48, AF0) | ||
| 93 | #define GPIO49_GPIO MFP_CFG_IN(GPIO49, AF0) | ||
| 94 | #define GPIO50_GPIO MFP_CFG_IN(GPIO50, AF0) | ||
| 95 | #define GPIO51_GPIO MFP_CFG_IN(GPIO51, AF0) | ||
| 96 | #define GPIO52_GPIO MFP_CFG_IN(GPIO52, AF0) | ||
| 97 | #define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0) | ||
| 98 | #define GPIO54_GPIO MFP_CFG_IN(GPIO54, AF0) | ||
| 99 | #define GPIO55_GPIO MFP_CFG_IN(GPIO55, AF0) | ||
| 100 | #define GPIO56_GPIO MFP_CFG_IN(GPIO56, AF0) | ||
| 101 | #define GPIO57_GPIO MFP_CFG_IN(GPIO57, AF0) | ||
| 102 | #define GPIO58_GPIO MFP_CFG_IN(GPIO58, AF0) | ||
| 103 | #define GPIO59_GPIO MFP_CFG_IN(GPIO59, AF0) | ||
| 104 | #define GPIO60_GPIO MFP_CFG_IN(GPIO60, AF0) | ||
| 105 | #define GPIO61_GPIO MFP_CFG_IN(GPIO61, AF0) | ||
| 106 | #define GPIO62_GPIO MFP_CFG_IN(GPIO62, AF0) | ||
| 107 | #define GPIO63_GPIO MFP_CFG_IN(GPIO63, AF0) | ||
| 108 | #define GPIO64_GPIO MFP_CFG_IN(GPIO64, AF0) | ||
| 109 | #define GPIO65_GPIO MFP_CFG_IN(GPIO65, AF0) | ||
| 110 | #define GPIO66_GPIO MFP_CFG_IN(GPIO66, AF0) | ||
| 111 | #define GPIO67_GPIO MFP_CFG_IN(GPIO67, AF0) | ||
| 112 | #define GPIO68_GPIO MFP_CFG_IN(GPIO68, AF0) | ||
| 113 | #define GPIO69_GPIO MFP_CFG_IN(GPIO69, AF0) | ||
| 114 | #define GPIO70_GPIO MFP_CFG_IN(GPIO70, AF0) | ||
| 115 | #define GPIO71_GPIO MFP_CFG_IN(GPIO71, AF0) | ||
| 116 | #define GPIO72_GPIO MFP_CFG_IN(GPIO72, AF0) | ||
| 117 | #define GPIO73_GPIO MFP_CFG_IN(GPIO73, AF0) | ||
| 118 | #define GPIO74_GPIO MFP_CFG_IN(GPIO74, AF0) | ||
| 119 | #define GPIO75_GPIO MFP_CFG_IN(GPIO75, AF0) | ||
| 120 | #define GPIO76_GPIO MFP_CFG_IN(GPIO76, AF0) | ||
| 121 | #define GPIO77_GPIO MFP_CFG_IN(GPIO77, AF0) | ||
| 122 | #define GPIO78_GPIO MFP_CFG_IN(GPIO78, AF0) | ||
| 123 | #define GPIO79_GPIO MFP_CFG_IN(GPIO79, AF0) | ||
| 124 | #define GPIO80_GPIO MFP_CFG_IN(GPIO80, AF0) | ||
| 125 | #define GPIO81_GPIO MFP_CFG_IN(GPIO81, AF0) | ||
| 126 | #define GPIO82_GPIO MFP_CFG_IN(GPIO82, AF0) | ||
| 127 | #define GPIO83_GPIO MFP_CFG_IN(GPIO83, AF0) | ||
| 128 | #define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0) | ||
| 129 | |||
| 130 | extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num); | ||
| 131 | extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm); | ||
| 132 | extern int gpio_set_wake(unsigned int gpio, unsigned int on); | ||
| 133 | #endif /* __ASM_ARCH_MFP_PXA2XX_H */ | ||
diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h deleted file mode 100644 index bb410313556f..000000000000 --- a/include/asm-arm/arch-pxa/mfp-pxa300.h +++ /dev/null | |||
| @@ -1,575 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/mfp-pxa300.h | ||
| 3 | * | ||
| 4 | * PXA300/PXA310 specific MFP configuration definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Marvell International Ltd. | ||
| 7 | * 2007-08-21: eric miao <eric.miao@marvell.com> | ||
| 8 | * initial version | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_MFP_PXA300_H | ||
| 16 | #define __ASM_ARCH_MFP_PXA300_H | ||
| 17 | |||
| 18 | #include <asm/arch/mfp.h> | ||
| 19 | #include <asm/arch/mfp-pxa3xx.h> | ||
| 20 | |||
| 21 | /* GPIO */ | ||
| 22 | #define GPIO46_GPIO MFP_CFG(GPIO46, AF1) | ||
| 23 | #define GPIO49_GPIO MFP_CFG(GPIO49, AF3) | ||
| 24 | #define GPIO50_GPIO MFP_CFG(GPIO50, AF2) | ||
| 25 | #define GPIO51_GPIO MFP_CFG(GPIO51, AF3) | ||
| 26 | #define GPIO52_GPIO MFP_CFG(GPIO52, AF3) | ||
| 27 | #define GPIO56_GPIO MFP_CFG(GPIO56, AF0) | ||
| 28 | #define GPIO58_GPIO MFP_CFG(GPIO58, AF0) | ||
| 29 | #define GPIO59_GPIO MFP_CFG(GPIO59, AF0) | ||
| 30 | #define GPIO60_GPIO MFP_CFG(GPIO60, AF0) | ||
| 31 | #define GPIO61_GPIO MFP_CFG(GPIO61, AF0) | ||
| 32 | #define GPIO62_GPIO MFP_CFG(GPIO62, AF0) | ||
| 33 | |||
| 34 | #ifdef CONFIG_CPU_PXA310 | ||
| 35 | #define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) | ||
| 36 | #define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) | ||
| 37 | #define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) | ||
| 38 | #define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) | ||
| 39 | #define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) | ||
| 40 | #define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | /* Chip Select */ | ||
| 44 | #define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) | ||
| 45 | |||
| 46 | /* AC97 */ | ||
| 47 | #define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1) | ||
| 48 | #define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1) | ||
| 49 | #define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1) | ||
| 50 | #define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1) | ||
| 51 | #define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1) | ||
| 52 | #define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3) | ||
| 53 | #define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2) | ||
| 54 | #define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3) | ||
| 55 | #define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2) | ||
| 56 | #define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1) | ||
| 57 | #define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1) | ||
| 58 | |||
| 59 | /* I2C */ | ||
| 60 | #define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH) | ||
| 61 | #define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH) | ||
| 62 | |||
| 63 | /* QCI */ | ||
| 64 | #define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X) | ||
| 65 | #define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X) | ||
| 66 | #define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X) | ||
| 67 | #define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X) | ||
| 68 | #define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X) | ||
| 69 | #define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X) | ||
| 70 | #define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X) | ||
| 71 | #define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X) | ||
| 72 | #define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X) | ||
| 73 | #define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X) | ||
| 74 | #define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X) | ||
| 75 | #define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X) | ||
| 76 | #define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X) | ||
| 77 | #define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X) | ||
| 78 | |||
| 79 | /* KEYPAD */ | ||
| 80 | #define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT) | ||
| 81 | #define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT) | ||
| 82 | #define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT) | ||
| 83 | #define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT) | ||
| 84 | #define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT) | ||
| 85 | #define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT) | ||
| 86 | #define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT) | ||
| 87 | #define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT) | ||
| 88 | #define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT) | ||
| 89 | #define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT) | ||
| 90 | #define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT) | ||
| 91 | #define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT) | ||
| 92 | #define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT) | ||
| 93 | #define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT) | ||
| 94 | #define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT) | ||
| 95 | #define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT) | ||
| 96 | #define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT) | ||
| 97 | #define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT) | ||
| 98 | #define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT) | ||
| 99 | #define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT) | ||
| 100 | #define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT) | ||
| 101 | #define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT) | ||
| 102 | #define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT) | ||
| 103 | #define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT) | ||
| 104 | #define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) | ||
| 105 | #define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) | ||
| 106 | #define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) | ||
| 107 | #define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) | ||
| 108 | #define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT) | ||
| 109 | #define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) | ||
| 110 | #define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT) | ||
| 111 | #define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) | ||
| 112 | #define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) | ||
| 113 | #define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) | ||
| 114 | #define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT) | ||
| 115 | |||
| 116 | #define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT) | ||
| 117 | #define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT) | ||
| 118 | #define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT) | ||
| 119 | #define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT) | ||
| 120 | #define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT) | ||
| 121 | #define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT) | ||
| 122 | #define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT) | ||
| 123 | #define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT) | ||
| 124 | #define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT) | ||
| 125 | #define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT) | ||
| 126 | #define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT) | ||
| 127 | #define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT) | ||
| 128 | #define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT) | ||
| 129 | #define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT) | ||
| 130 | #define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT) | ||
| 131 | #define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT) | ||
| 132 | #define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) | ||
| 133 | #define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT) | ||
| 134 | #define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT) | ||
| 135 | |||
| 136 | #define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) | ||
| 137 | #define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH) | ||
| 138 | #define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH) | ||
| 139 | #define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) | ||
| 140 | #define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH) | ||
| 141 | #define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH) | ||
| 142 | #define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH) | ||
| 143 | #define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH) | ||
| 144 | #define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH) | ||
| 145 | #define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) | ||
| 146 | #define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) | ||
| 147 | #define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH) | ||
| 148 | #define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH) | ||
| 149 | #define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH) | ||
| 150 | #define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH) | ||
| 151 | #define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) | ||
| 152 | #define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) | ||
| 153 | #define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) | ||
| 154 | #define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) | ||
| 155 | #define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) | ||
| 156 | #define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH) | ||
| 157 | #define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) | ||
| 158 | #define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH) | ||
| 159 | #define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH) | ||
| 160 | |||
| 161 | /* LCD */ | ||
| 162 | #define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X) | ||
| 163 | #define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X) | ||
| 164 | #define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X) | ||
| 165 | #define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X) | ||
| 166 | #define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X) | ||
| 167 | #define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X) | ||
| 168 | #define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X) | ||
| 169 | #define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X) | ||
| 170 | #define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X) | ||
| 171 | #define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X) | ||
| 172 | #define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X) | ||
| 173 | #define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X) | ||
| 174 | #define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X) | ||
| 175 | #define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X) | ||
| 176 | #define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X) | ||
| 177 | #define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X) | ||
| 178 | #define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X) | ||
| 179 | #define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X) | ||
| 180 | #define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X) | ||
| 181 | #define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X) | ||
| 182 | #define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X) | ||
| 183 | #define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS02X) | ||
| 184 | #define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X) | ||
| 185 | #define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X) | ||
| 186 | |||
| 187 | #define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X) | ||
| 188 | #define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X) | ||
| 189 | #define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X) | ||
| 190 | |||
| 191 | /* Mini-LCD */ | ||
| 192 | #define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X) | ||
| 193 | #define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X) | ||
| 194 | #define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X) | ||
| 195 | #define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X) | ||
| 196 | #define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X) | ||
| 197 | #define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X) | ||
| 198 | #define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X) | ||
| 199 | #define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X) | ||
| 200 | #define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X) | ||
| 201 | #define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X) | ||
| 202 | #define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X) | ||
| 203 | #define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X) | ||
| 204 | #define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X) | ||
| 205 | #define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X) | ||
| 206 | #define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X) | ||
| 207 | #define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X) | ||
| 208 | #define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X) | ||
| 209 | #define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X) | ||
| 210 | #define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X) | ||
| 211 | #define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X) | ||
| 212 | |||
| 213 | /* MMC1 */ | ||
| 214 | #define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) | ||
| 215 | #define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) | ||
| 216 | #define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH) | ||
| 217 | #define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH) | ||
| 218 | #define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH) | ||
| 219 | #define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH) | ||
| 220 | #define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) | ||
| 221 | #define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) | ||
| 222 | |||
| 223 | /* MMC2 */ | ||
| 224 | #define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH) | ||
| 225 | #define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH) | ||
| 226 | #define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH) | ||
| 227 | #define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH) | ||
| 228 | #define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH) | ||
| 229 | #define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH) | ||
| 230 | #define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) | ||
| 231 | #define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) | ||
| 232 | #define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) | ||
| 233 | #define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) | ||
| 234 | #define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH) | ||
| 235 | #define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH) | ||
| 236 | |||
| 237 | /* SSP1 */ | ||
| 238 | #define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1) | ||
| 239 | #define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1) | ||
| 240 | #define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6) | ||
| 241 | #define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2) | ||
| 242 | #define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5) | ||
| 243 | #define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5) | ||
| 244 | #define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1) | ||
| 245 | #define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1) | ||
| 246 | #define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7) | ||
| 247 | #define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2) | ||
| 248 | #define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2) | ||
| 249 | #define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7) | ||
| 250 | #define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5) | ||
| 251 | #define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4) | ||
| 252 | #define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5) | ||
| 253 | #define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6) | ||
| 254 | #define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1) | ||
| 255 | #define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6) | ||
| 256 | #define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6) | ||
| 257 | #define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1) | ||
| 258 | |||
| 259 | /* SSP2 */ | ||
| 260 | #define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2) | ||
| 261 | #define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2) | ||
| 262 | #define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2) | ||
| 263 | #define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2) | ||
| 264 | #define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2) | ||
| 265 | #define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6) | ||
| 266 | #define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6) | ||
| 267 | #define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2) | ||
| 268 | #define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2) | ||
| 269 | #define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2) | ||
| 270 | #define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7) | ||
| 271 | #define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5) | ||
| 272 | #define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4) | ||
| 273 | #define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2) | ||
| 274 | #define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5) | ||
| 275 | #define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5) | ||
| 276 | #define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2) | ||
| 277 | #define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7) | ||
| 278 | #define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6) | ||
| 279 | #define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4) | ||
| 280 | #define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2) | ||
| 281 | #define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2) | ||
| 282 | #define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4) | ||
| 283 | #define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7) | ||
| 284 | |||
| 285 | /* SSP3 */ | ||
| 286 | #define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW) | ||
| 287 | #define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT) | ||
| 288 | #define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW) | ||
| 289 | #define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT) | ||
| 290 | #define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) | ||
| 291 | #define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT) | ||
| 292 | #define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW) | ||
| 293 | #define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT) | ||
| 294 | #define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW) | ||
| 295 | #define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT) | ||
| 296 | #define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW) | ||
| 297 | #define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) | ||
| 298 | |||
| 299 | /* SSP4 */ | ||
| 300 | #define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) | ||
| 301 | #define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) | ||
| 302 | #define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH) | ||
| 303 | #define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH) | ||
| 304 | #define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH) | ||
| 305 | #define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH) | ||
| 306 | |||
| 307 | /* UART1 */ | ||
| 308 | #define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT) | ||
| 309 | #define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT) | ||
| 310 | #define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT) | ||
| 311 | #define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT) | ||
| 312 | #define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT) | ||
| 313 | #define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT) | ||
| 314 | |||
| 315 | #define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT) | ||
| 316 | #define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT) | ||
| 317 | #define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT) | ||
| 318 | #define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT) | ||
| 319 | #define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT) | ||
| 320 | #define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) | ||
| 321 | |||
| 322 | #define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT) | ||
| 323 | #define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT) | ||
| 324 | #define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT) | ||
| 325 | #define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT) | ||
| 326 | #define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT) | ||
| 327 | #define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT) | ||
| 328 | |||
| 329 | #define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT) | ||
| 330 | #define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT) | ||
| 331 | #define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT) | ||
| 332 | #define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT) | ||
| 333 | #define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT) | ||
| 334 | #define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT) | ||
| 335 | |||
| 336 | #define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT) | ||
| 337 | #define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT) | ||
| 338 | #define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT) | ||
| 339 | |||
| 340 | #define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT) | ||
| 341 | #define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT) | ||
| 342 | #define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT) | ||
| 343 | |||
| 344 | #define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) | ||
| 345 | #define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT) | ||
| 346 | #define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT) | ||
| 347 | #define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT) | ||
| 348 | #define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT) | ||
| 349 | #define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT) | ||
| 350 | #define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT) | ||
| 351 | #define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT) | ||
| 352 | |||
| 353 | #define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT) | ||
| 354 | #define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) | ||
| 355 | #define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT) | ||
| 356 | #define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT) | ||
| 357 | #define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT) | ||
| 358 | #define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT) | ||
| 359 | #define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT) | ||
| 360 | |||
| 361 | /* UART2 */ | ||
| 362 | #define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT) | ||
| 363 | #define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT) | ||
| 364 | #define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT) | ||
| 365 | #define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT) | ||
| 366 | |||
| 367 | #define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT) | ||
| 368 | #define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT) | ||
| 369 | #define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT) | ||
| 370 | #define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT) | ||
| 371 | |||
| 372 | #define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT) | ||
| 373 | #define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT) | ||
| 374 | #define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT) | ||
| 375 | #define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT) | ||
| 376 | |||
| 377 | #define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT) | ||
| 378 | #define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT) | ||
| 379 | #define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT) | ||
| 380 | #define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT) | ||
| 381 | |||
| 382 | /* UART3 */ | ||
| 383 | #define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT) | ||
| 384 | #define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT) | ||
| 385 | #define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT) | ||
| 386 | #define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT) | ||
| 387 | |||
| 388 | #define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT) | ||
| 389 | #define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT) | ||
| 390 | #define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT) | ||
| 391 | #define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT) | ||
| 392 | |||
| 393 | #define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT) | ||
| 394 | #define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT) | ||
| 395 | #define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT) | ||
| 396 | #define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT) | ||
| 397 | #define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT) | ||
| 398 | #define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) | ||
| 399 | |||
| 400 | #define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT) | ||
| 401 | #define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT) | ||
| 402 | #define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT) | ||
| 403 | #define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT) | ||
| 404 | #define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT) | ||
| 405 | #define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) | ||
| 406 | |||
| 407 | /* USB Host */ | ||
| 408 | #define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1) | ||
| 409 | #define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1) | ||
| 410 | |||
| 411 | /* USB P3 */ | ||
| 412 | #define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2) | ||
| 413 | #define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2) | ||
| 414 | #define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2) | ||
| 415 | #define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2) | ||
| 416 | #define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2) | ||
| 417 | #define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2) | ||
| 418 | |||
| 419 | /* PWM */ | ||
| 420 | #define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1) | ||
| 421 | #define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1) | ||
| 422 | #define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1) | ||
| 423 | #define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1) | ||
| 424 | |||
| 425 | /* CIR */ | ||
| 426 | #define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5) | ||
| 427 | #define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3) | ||
| 428 | |||
| 429 | #define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5) | ||
| 430 | #define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2) | ||
| 431 | |||
| 432 | #define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1) | ||
| 433 | #define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7) | ||
| 434 | #define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6) | ||
| 435 | #define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6) | ||
| 436 | #define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6) | ||
| 437 | #define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6) | ||
| 438 | #define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2) | ||
| 439 | #define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3) | ||
| 440 | #define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7) | ||
| 441 | #define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6) | ||
| 442 | |||
| 443 | #define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1) | ||
| 444 | |||
| 445 | #define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1) | ||
| 446 | #define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1) | ||
| 447 | #define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1) | ||
| 448 | #define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1) | ||
| 449 | |||
| 450 | #define GPIO9_SCIO MFP_CFG(GPIO9, AF1) | ||
| 451 | #define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4) | ||
| 452 | #define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1) | ||
| 453 | |||
| 454 | /* | ||
| 455 | * PXA300 specific MFP configurations | ||
| 456 | */ | ||
| 457 | #ifdef CONFIG_CPU_PXA300 | ||
| 458 | #define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2) | ||
| 459 | #define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3) | ||
| 460 | #define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4) | ||
| 461 | #define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4) | ||
| 462 | #define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5) | ||
| 463 | #define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2) | ||
| 464 | #define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2) | ||
| 465 | #define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2) | ||
| 466 | #define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2) | ||
| 467 | #define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2) | ||
| 468 | #define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2) | ||
| 469 | #define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2) | ||
| 470 | |||
| 471 | /* U2D UTMI */ | ||
| 472 | #define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1) | ||
| 473 | #define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3) | ||
| 474 | #define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1) | ||
| 475 | #define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5) | ||
| 476 | #define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3) | ||
| 477 | #define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2) | ||
| 478 | #define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5) | ||
| 479 | #define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3) | ||
| 480 | #define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2) | ||
| 481 | #define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1) | ||
| 482 | #define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5) | ||
| 483 | #define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1) | ||
| 484 | #define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3) | ||
| 485 | #define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3) | ||
| 486 | #define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3) | ||
| 487 | #define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4) | ||
| 488 | #define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3) | ||
| 489 | #define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3) | ||
| 490 | #define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3) | ||
| 491 | #define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4) | ||
| 492 | #define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2) | ||
| 493 | #define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7) | ||
| 494 | #define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4) | ||
| 495 | #define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2) | ||
| 496 | #define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3) | ||
| 497 | #define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5) | ||
| 498 | #define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1) | ||
| 499 | #define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2) | ||
| 500 | #define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3) | ||
| 501 | #define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3) | ||
| 502 | #define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2) | ||
| 503 | #define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3) | ||
| 504 | #define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5) | ||
| 505 | #define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3) | ||
| 506 | #define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5) | ||
| 507 | #define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3) | ||
| 508 | #define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4) | ||
| 509 | #define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3) | ||
| 510 | #define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7) | ||
| 511 | #define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5) | ||
| 512 | #define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3) | ||
| 513 | #define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5) | ||
| 514 | #define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3) | ||
| 515 | #define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3) | ||
| 516 | #define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3) | ||
| 517 | #define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3) | ||
| 518 | #define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3) | ||
| 519 | #define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3) | ||
| 520 | #define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3) | ||
| 521 | #define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3) | ||
| 522 | #define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3) | ||
| 523 | #define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3) | ||
| 524 | #define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3) | ||
| 525 | #define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3) | ||
| 526 | #define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3) | ||
| 527 | #define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3) | ||
| 528 | #define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3) | ||
| 529 | #define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3) | ||
| 530 | #endif /* CONFIG_CPU_PXA300 */ | ||
| 531 | |||
| 532 | /* | ||
| 533 | * PXA310 specific MFP configurations | ||
| 534 | */ | ||
| 535 | #ifdef CONFIG_CPU_PXA310 | ||
| 536 | /* USB P2 */ | ||
| 537 | #define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1) | ||
| 538 | #define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1) | ||
| 539 | #define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1) | ||
| 540 | #define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1) | ||
| 541 | #define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1) | ||
| 542 | #define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1) | ||
| 543 | |||
| 544 | /* MMC1 */ | ||
| 545 | #define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3) | ||
| 546 | #define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3) | ||
| 547 | |||
| 548 | /* MMC3 */ | ||
| 549 | #define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2) | ||
| 550 | #define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2) | ||
| 551 | #define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1) | ||
| 552 | #define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1) | ||
| 553 | #define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1) | ||
| 554 | #define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1) | ||
| 555 | #define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1) | ||
| 556 | #define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1) | ||
| 557 | |||
| 558 | /* ULPI */ | ||
| 559 | #define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1) | ||
| 560 | #define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3) | ||
| 561 | #define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3) | ||
| 562 | #define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3) | ||
| 563 | #define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3) | ||
| 564 | #define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3) | ||
| 565 | #define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3) | ||
| 566 | #define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3) | ||
| 567 | #define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3) | ||
| 568 | #define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1) | ||
| 569 | |||
| 570 | #define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X) | ||
| 571 | #define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X) | ||
| 572 | #define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X) | ||
| 573 | #endif /* CONFIG_CPU_PXA310 */ | ||
| 574 | |||
| 575 | #endif /* __ASM_ARCH_MFP_PXA300_H */ | ||
diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h deleted file mode 100644 index 576aa46d90fc..000000000000 --- a/include/asm-arm/arch-pxa/mfp-pxa320.h +++ /dev/null | |||
| @@ -1,447 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/mfp-pxa320.h | ||
| 3 | * | ||
| 4 | * PXA320 specific MFP configuration definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Marvell International Ltd. | ||
| 7 | * 2007-08-21: eric miao <eric.miao@marvell.com> | ||
| 8 | * initial version | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_MFP_PXA320_H | ||
| 16 | #define __ASM_ARCH_MFP_PXA320_H | ||
| 17 | |||
| 18 | #include <asm/arch/mfp.h> | ||
| 19 | #include <asm/arch/mfp-pxa3xx.h> | ||
| 20 | |||
| 21 | /* GPIO */ | ||
| 22 | #define GPIO46_GPIO MFP_CFG(GPIO46, AF0) | ||
| 23 | #define GPIO49_GPIO MFP_CFG(GPIO49, AF0) | ||
| 24 | #define GPIO50_GPIO MFP_CFG(GPIO50, AF0) | ||
| 25 | #define GPIO51_GPIO MFP_CFG(GPIO51, AF0) | ||
| 26 | #define GPIO52_GPIO MFP_CFG(GPIO52, AF0) | ||
| 27 | |||
| 28 | #define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) | ||
| 29 | #define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) | ||
| 30 | #define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) | ||
| 31 | #define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) | ||
| 32 | #define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) | ||
| 33 | #define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) | ||
| 34 | #define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0) | ||
| 35 | #define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0) | ||
| 36 | #define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0) | ||
| 37 | #define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0) | ||
| 38 | #define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) | ||
| 39 | |||
| 40 | /* Chip Select */ | ||
| 41 | #define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) | ||
| 42 | |||
| 43 | /* AC97 */ | ||
| 44 | #define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1) | ||
| 45 | #define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1) | ||
| 46 | #define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1) | ||
| 47 | #define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1) | ||
| 48 | #define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1) | ||
| 49 | #define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2) | ||
| 50 | #define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2) | ||
| 51 | #define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3) | ||
| 52 | #define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3) | ||
| 53 | #define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1) | ||
| 54 | #define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1) | ||
| 55 | |||
| 56 | /* I2C */ | ||
| 57 | #define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH) | ||
| 58 | #define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH) | ||
| 59 | |||
| 60 | /* QCI */ | ||
| 61 | #define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X) | ||
| 62 | #define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X) | ||
| 63 | #define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X) | ||
| 64 | #define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X) | ||
| 65 | #define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X) | ||
| 66 | #define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X) | ||
| 67 | #define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X) | ||
| 68 | #define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X) | ||
| 69 | #define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X) | ||
| 70 | #define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X) | ||
| 71 | #define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X) | ||
| 72 | #define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X) | ||
| 73 | #define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X) | ||
| 74 | #define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X) | ||
| 75 | |||
| 76 | #define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5) | ||
| 77 | |||
| 78 | #define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3) | ||
| 79 | #define GPIO0_DRQ MFP_CFG(GPIO0, AF2) | ||
| 80 | #define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5) | ||
| 81 | #define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6) | ||
| 82 | #define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1) | ||
| 83 | #define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4) | ||
| 84 | #define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1) | ||
| 85 | #define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1) | ||
| 86 | |||
| 87 | #define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT) | ||
| 88 | #define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT) | ||
| 89 | #define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT) | ||
| 90 | #define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT) | ||
| 91 | |||
| 92 | #define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT) | ||
| 93 | #define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT) | ||
| 94 | #define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT) | ||
| 95 | #define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT) | ||
| 96 | #define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT) | ||
| 97 | #define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT) | ||
| 98 | #define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT) | ||
| 99 | #define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT) | ||
| 100 | |||
| 101 | #define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT) | ||
| 102 | #define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT) | ||
| 103 | #define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT) | ||
| 104 | #define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT) | ||
| 105 | #define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT) | ||
| 106 | #define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT) | ||
| 107 | #define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT) | ||
| 108 | #define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT) | ||
| 109 | |||
| 110 | #define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT) | ||
| 111 | #define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT) | ||
| 112 | |||
| 113 | #define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) | ||
| 114 | #define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) | ||
| 115 | #define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) | ||
| 116 | #define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) | ||
| 117 | #define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) | ||
| 118 | #define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) | ||
| 119 | #define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) | ||
| 120 | #define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) | ||
| 121 | |||
| 122 | #define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT) | ||
| 123 | #define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT) | ||
| 124 | #define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT) | ||
| 125 | #define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT) | ||
| 126 | #define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT) | ||
| 127 | #define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT) | ||
| 128 | #define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT) | ||
| 129 | #define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT) | ||
| 130 | |||
| 131 | #define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH) | ||
| 132 | #define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH) | ||
| 133 | #define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) | ||
| 134 | #define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) | ||
| 135 | #define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) | ||
| 136 | #define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH) | ||
| 137 | |||
| 138 | #define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) | ||
| 139 | #define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) | ||
| 140 | #define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) | ||
| 141 | #define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) | ||
| 142 | #define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) | ||
| 143 | #define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH) | ||
| 144 | #define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH) | ||
| 145 | #define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) | ||
| 146 | |||
| 147 | /* LCD */ | ||
| 148 | #define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X) | ||
| 149 | #define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X) | ||
| 150 | #define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X) | ||
| 151 | #define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X) | ||
| 152 | #define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X) | ||
| 153 | #define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X) | ||
| 154 | #define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X) | ||
| 155 | #define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X) | ||
| 156 | #define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X) | ||
| 157 | #define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X) | ||
| 158 | #define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X) | ||
| 159 | #define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X) | ||
| 160 | #define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X) | ||
| 161 | #define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X) | ||
| 162 | #define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X) | ||
| 163 | #define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X) | ||
| 164 | #define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X) | ||
| 165 | #define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X) | ||
| 166 | #define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X) | ||
| 167 | #define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X) | ||
| 168 | #define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X) | ||
| 169 | #define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X) | ||
| 170 | #define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X) | ||
| 171 | #define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X) | ||
| 172 | #define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X) | ||
| 173 | #define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X) | ||
| 174 | |||
| 175 | #define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X) | ||
| 176 | #define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X) | ||
| 177 | #define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X) | ||
| 178 | #define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X) | ||
| 179 | #define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X) | ||
| 180 | #define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X) | ||
| 181 | #define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X) | ||
| 182 | #define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X) | ||
| 183 | #define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X) | ||
| 184 | #define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X) | ||
| 185 | #define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X) | ||
| 186 | #define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X) | ||
| 187 | #define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X) | ||
| 188 | #define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X) | ||
| 189 | #define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X) | ||
| 190 | #define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X) | ||
| 191 | #define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X) | ||
| 192 | #define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X) | ||
| 193 | #define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X) | ||
| 194 | #define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X) | ||
| 195 | #define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X) | ||
| 196 | #define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X) | ||
| 197 | #define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X) | ||
| 198 | #define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X) | ||
| 199 | |||
| 200 | /* MMC1 */ | ||
| 201 | #define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH) | ||
| 202 | #define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH) | ||
| 203 | #define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH) | ||
| 204 | #define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH) | ||
| 205 | #define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH) | ||
| 206 | #define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) | ||
| 207 | #define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) | ||
| 208 | #define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) | ||
| 209 | #define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) | ||
| 210 | #define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH) | ||
| 211 | #define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH) | ||
| 212 | #define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH) | ||
| 213 | #define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH) | ||
| 214 | |||
| 215 | #define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH) | ||
| 216 | #define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH) | ||
| 217 | #define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH) | ||
| 218 | #define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH) | ||
| 219 | #define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) | ||
| 220 | #define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) | ||
| 221 | |||
| 222 | #define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH) | ||
| 223 | #define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH) | ||
| 224 | #define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH) | ||
| 225 | #define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH) | ||
| 226 | #define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH) | ||
| 227 | #define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH) | ||
| 228 | #define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH) | ||
| 229 | #define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH) | ||
| 230 | #define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH) | ||
| 231 | #define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) | ||
| 232 | #define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH) | ||
| 233 | #define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) | ||
| 234 | |||
| 235 | /* 1-Wire */ | ||
| 236 | #define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT) | ||
| 237 | #define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) | ||
| 238 | |||
| 239 | /* SSP1 */ | ||
| 240 | #define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1) | ||
| 241 | #define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1) | ||
| 242 | #define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1) | ||
| 243 | #define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1) | ||
| 244 | #define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6) | ||
| 245 | #define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1) | ||
| 246 | #define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1) | ||
| 247 | #define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6) | ||
| 248 | |||
| 249 | /* SSP2 */ | ||
| 250 | #define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2) | ||
| 251 | #define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2) | ||
| 252 | #define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2) | ||
| 253 | #define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2) | ||
| 254 | #define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2) | ||
| 255 | #define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5) | ||
| 256 | #define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2) | ||
| 257 | #define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2) | ||
| 258 | #define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5) | ||
| 259 | |||
| 260 | #define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT) | ||
| 261 | #define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW) | ||
| 262 | #define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT) | ||
| 263 | #define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW) | ||
| 264 | #define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT) | ||
| 265 | #define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW) | ||
| 266 | #define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT) | ||
| 267 | #define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW) | ||
| 268 | #define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT) | ||
| 269 | #define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW) | ||
| 270 | #define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT) | ||
| 271 | #define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW) | ||
| 272 | |||
| 273 | #define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH) | ||
| 274 | #define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH) | ||
| 275 | #define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH) | ||
| 276 | #define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH) | ||
| 277 | #define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) | ||
| 278 | #define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) | ||
| 279 | #define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH) | ||
| 280 | |||
| 281 | /* UART1 */ | ||
| 282 | #define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT) | ||
| 283 | #define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT) | ||
| 284 | #define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT) | ||
| 285 | #define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT) | ||
| 286 | #define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT) | ||
| 287 | #define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT) | ||
| 288 | #define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT) | ||
| 289 | #define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT) | ||
| 290 | #define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT) | ||
| 291 | #define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT) | ||
| 292 | #define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT) | ||
| 293 | #define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT) | ||
| 294 | #define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT) | ||
| 295 | #define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT) | ||
| 296 | #define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT) | ||
| 297 | #define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT) | ||
| 298 | #define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT) | ||
| 299 | #define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT) | ||
| 300 | #define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT) | ||
| 301 | #define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT) | ||
| 302 | #define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT) | ||
| 303 | #define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT) | ||
| 304 | #define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT) | ||
| 305 | #define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT) | ||
| 306 | #define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT) | ||
| 307 | #define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT) | ||
| 308 | #define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT) | ||
| 309 | #define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT) | ||
| 310 | |||
| 311 | /* UART2 */ | ||
| 312 | #define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT) | ||
| 313 | #define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT) | ||
| 314 | #define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT) | ||
| 315 | #define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT) | ||
| 316 | #define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) | ||
| 317 | #define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) | ||
| 318 | #define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT) | ||
| 319 | #define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT) | ||
| 320 | |||
| 321 | /* UART3 */ | ||
| 322 | #define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT) | ||
| 323 | #define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT) | ||
| 324 | #define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT) | ||
| 325 | #define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT) | ||
| 326 | #define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT) | ||
| 327 | #define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT) | ||
| 328 | #define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT) | ||
| 329 | #define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) | ||
| 330 | #define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) | ||
| 331 | #define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT) | ||
| 332 | #define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT) | ||
| 333 | #define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) | ||
| 334 | #define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT) | ||
| 335 | #define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT) | ||
| 336 | #define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT) | ||
| 337 | #define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT) | ||
| 338 | #define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT) | ||
| 339 | #define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT) | ||
| 340 | #define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT) | ||
| 341 | #define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT) | ||
| 342 | |||
| 343 | |||
| 344 | /* USB 2.0 UTMI */ | ||
| 345 | #define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1) | ||
| 346 | #define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3) | ||
| 347 | #define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1) | ||
| 348 | #define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5) | ||
| 349 | #define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3) | ||
| 350 | #define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2) | ||
| 351 | #define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5) | ||
| 352 | #define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3) | ||
| 353 | #define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1) | ||
| 354 | #define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5) | ||
| 355 | #define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1) | ||
| 356 | #define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3) | ||
| 357 | #define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3) | ||
| 358 | #define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3) | ||
| 359 | #define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4) | ||
| 360 | #define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3) | ||
| 361 | #define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3) | ||
| 362 | #define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3) | ||
| 363 | |||
| 364 | #define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3) | ||
| 365 | #define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3) | ||
| 366 | #define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3) | ||
| 367 | #define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3) | ||
| 368 | #define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3) | ||
| 369 | #define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3) | ||
| 370 | #define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3) | ||
| 371 | #define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3) | ||
| 372 | |||
| 373 | #define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3) | ||
| 374 | #define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3) | ||
| 375 | #define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3) | ||
| 376 | #define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3) | ||
| 377 | #define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3) | ||
| 378 | #define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3) | ||
| 379 | #define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3) | ||
| 380 | #define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3) | ||
| 381 | |||
| 382 | #define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4) | ||
| 383 | #define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2) | ||
| 384 | #define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7) | ||
| 385 | |||
| 386 | #define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4) | ||
| 387 | #define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2) | ||
| 388 | #define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4) | ||
| 389 | #define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5) | ||
| 390 | |||
| 391 | #define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1) | ||
| 392 | #define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2) | ||
| 393 | #define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3) | ||
| 394 | |||
| 395 | #define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3) | ||
| 396 | #define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2) | ||
| 397 | #define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3) | ||
| 398 | |||
| 399 | #define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5) | ||
| 400 | #define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3) | ||
| 401 | #define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7) | ||
| 402 | #define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5) | ||
| 403 | |||
| 404 | #define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4) | ||
| 405 | #define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5) | ||
| 406 | #define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7) | ||
| 407 | |||
| 408 | #define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5) | ||
| 409 | #define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3) | ||
| 410 | #define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5) | ||
| 411 | |||
| 412 | /* USB Host 1.1 */ | ||
| 413 | #define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1) | ||
| 414 | #define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1) | ||
| 415 | |||
| 416 | /* USB P2 */ | ||
| 417 | #define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2) | ||
| 418 | #define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4) | ||
| 419 | #define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4) | ||
| 420 | #define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2) | ||
| 421 | #define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2) | ||
| 422 | #define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2) | ||
| 423 | #define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2) | ||
| 424 | #define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2) | ||
| 425 | #define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2) | ||
| 426 | #define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2) | ||
| 427 | |||
| 428 | /* USB P3 */ | ||
| 429 | #define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2) | ||
| 430 | #define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2) | ||
| 431 | #define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2) | ||
| 432 | #define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2) | ||
| 433 | #define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2) | ||
| 434 | #define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2) | ||
| 435 | |||
| 436 | #define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6) | ||
| 437 | #define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6) | ||
| 438 | |||
| 439 | #define GPIO2_RDY MFP_CFG(GPIO2, AF1) | ||
| 440 | #define GPIO5_NPIOR MFP_CFG(GPIO5, AF3) | ||
| 441 | |||
| 442 | #define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1) | ||
| 443 | #define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1) | ||
| 444 | #define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1) | ||
| 445 | #define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1) | ||
| 446 | |||
| 447 | #endif /* __ASM_ARCH_MFP_PXA320_H */ | ||
diff --git a/include/asm-arm/arch-pxa/mfp-pxa3xx.h b/include/asm-arm/arch-pxa/mfp-pxa3xx.h deleted file mode 100644 index 1f6b35c015d0..000000000000 --- a/include/asm-arm/arch-pxa/mfp-pxa3xx.h +++ /dev/null | |||
| @@ -1,252 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA3XX_H | ||
| 2 | #define __ASM_ARCH_MFP_PXA3XX_H | ||
| 3 | |||
| 4 | #define MFPR_BASE (0x40e10000) | ||
| 5 | #define MFPR_SIZE (PAGE_SIZE) | ||
| 6 | |||
| 7 | /* MFPR register bit definitions */ | ||
| 8 | #define MFPR_PULL_SEL (0x1 << 15) | ||
| 9 | #define MFPR_PULLUP_EN (0x1 << 14) | ||
| 10 | #define MFPR_PULLDOWN_EN (0x1 << 13) | ||
| 11 | #define MFPR_SLEEP_SEL (0x1 << 9) | ||
| 12 | #define MFPR_SLEEP_OE_N (0x1 << 7) | ||
| 13 | #define MFPR_EDGE_CLEAR (0x1 << 6) | ||
| 14 | #define MFPR_EDGE_FALL_EN (0x1 << 5) | ||
| 15 | #define MFPR_EDGE_RISE_EN (0x1 << 4) | ||
| 16 | |||
| 17 | #define MFPR_SLEEP_DATA(x) ((x) << 8) | ||
| 18 | #define MFPR_DRIVE(x) (((x) & 0x7) << 10) | ||
| 19 | #define MFPR_AF_SEL(x) (((x) & 0x7) << 0) | ||
| 20 | |||
| 21 | #define MFPR_EDGE_NONE (0) | ||
| 22 | #define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN) | ||
| 23 | #define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN) | ||
| 24 | #define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL) | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Table that determines the low power modes outputs, with actual settings | ||
| 28 | * used in parentheses for don't-care values. Except for the float output, | ||
| 29 | * the configured driven and pulled levels match, so if there is a need for | ||
| 30 | * non-LPM pulled output, the same configuration could probably be used. | ||
| 31 | * | ||
| 32 | * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel | ||
| 33 | * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) | ||
| 34 | * | ||
| 35 | * Input 0 X(0) X(0) X(0) 0 | ||
| 36 | * Drive 0 0 0 0 X(1) 0 | ||
| 37 | * Drive 1 0 1 X(1) 0 0 | ||
| 38 | * Pull hi (1) 1 X(1) 1 0 0 | ||
| 39 | * Pull lo (0) 1 X(0) 0 1 0 | ||
| 40 | * Z (float) 1 X(0) 0 0 0 | ||
| 41 | */ | ||
| 42 | #define MFPR_LPM_INPUT (0) | ||
| 43 | #define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN) | ||
| 44 | #define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN) | ||
| 45 | #define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N) | ||
| 46 | #define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N) | ||
| 47 | #define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N) | ||
| 48 | #define MFPR_LPM_MASK (0xe080) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * The pullup and pulldown state of the MFP pin at run mode is by default | ||
| 52 | * determined by the selected alternate function. In case that some buggy | ||
| 53 | * devices need to override this default behavior, the definitions below | ||
| 54 | * indicates the setting of corresponding MFPR bits | ||
| 55 | * | ||
| 56 | * Definition pull_sel pullup_en pulldown_en | ||
| 57 | * MFPR_PULL_NONE 0 0 0 | ||
| 58 | * MFPR_PULL_LOW 1 0 1 | ||
| 59 | * MFPR_PULL_HIGH 1 1 0 | ||
| 60 | * MFPR_PULL_BOTH 1 1 1 | ||
| 61 | */ | ||
| 62 | #define MFPR_PULL_NONE (0) | ||
| 63 | #define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) | ||
| 64 | #define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) | ||
| 65 | #define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) | ||
| 66 | |||
| 67 | /* PXA3xx common MFP configurations - processor specific ones defined | ||
| 68 | * in mfp-pxa300.h and mfp-pxa320.h | ||
| 69 | */ | ||
| 70 | #define GPIO0_GPIO MFP_CFG(GPIO0, AF0) | ||
| 71 | #define GPIO1_GPIO MFP_CFG(GPIO1, AF0) | ||
| 72 | #define GPIO2_GPIO MFP_CFG(GPIO2, AF0) | ||
| 73 | #define GPIO3_GPIO MFP_CFG(GPIO3, AF0) | ||
| 74 | #define GPIO4_GPIO MFP_CFG(GPIO4, AF0) | ||
| 75 | #define GPIO5_GPIO MFP_CFG(GPIO5, AF0) | ||
| 76 | #define GPIO6_GPIO MFP_CFG(GPIO6, AF0) | ||
| 77 | #define GPIO7_GPIO MFP_CFG(GPIO7, AF0) | ||
| 78 | #define GPIO8_GPIO MFP_CFG(GPIO8, AF0) | ||
| 79 | #define GPIO9_GPIO MFP_CFG(GPIO9, AF0) | ||
| 80 | #define GPIO10_GPIO MFP_CFG(GPIO10, AF0) | ||
| 81 | #define GPIO11_GPIO MFP_CFG(GPIO11, AF0) | ||
| 82 | #define GPIO12_GPIO MFP_CFG(GPIO12, AF0) | ||
| 83 | #define GPIO13_GPIO MFP_CFG(GPIO13, AF0) | ||
| 84 | #define GPIO14_GPIO MFP_CFG(GPIO14, AF0) | ||
| 85 | #define GPIO15_GPIO MFP_CFG(GPIO15, AF0) | ||
| 86 | #define GPIO16_GPIO MFP_CFG(GPIO16, AF0) | ||
| 87 | #define GPIO17_GPIO MFP_CFG(GPIO17, AF0) | ||
| 88 | #define GPIO18_GPIO MFP_CFG(GPIO18, AF0) | ||
| 89 | #define GPIO19_GPIO MFP_CFG(GPIO19, AF0) | ||
| 90 | #define GPIO20_GPIO MFP_CFG(GPIO20, AF0) | ||
| 91 | #define GPIO21_GPIO MFP_CFG(GPIO21, AF0) | ||
| 92 | #define GPIO22_GPIO MFP_CFG(GPIO22, AF0) | ||
| 93 | #define GPIO23_GPIO MFP_CFG(GPIO23, AF0) | ||
| 94 | #define GPIO24_GPIO MFP_CFG(GPIO24, AF0) | ||
| 95 | #define GPIO25_GPIO MFP_CFG(GPIO25, AF0) | ||
| 96 | #define GPIO26_GPIO MFP_CFG(GPIO26, AF0) | ||
| 97 | #define GPIO27_GPIO MFP_CFG(GPIO27, AF0) | ||
| 98 | #define GPIO28_GPIO MFP_CFG(GPIO28, AF0) | ||
| 99 | #define GPIO29_GPIO MFP_CFG(GPIO29, AF0) | ||
| 100 | #define GPIO30_GPIO MFP_CFG(GPIO30, AF0) | ||
| 101 | #define GPIO31_GPIO MFP_CFG(GPIO31, AF0) | ||
| 102 | #define GPIO32_GPIO MFP_CFG(GPIO32, AF0) | ||
| 103 | #define GPIO33_GPIO MFP_CFG(GPIO33, AF0) | ||
| 104 | #define GPIO34_GPIO MFP_CFG(GPIO34, AF0) | ||
| 105 | #define GPIO35_GPIO MFP_CFG(GPIO35, AF0) | ||
| 106 | #define GPIO36_GPIO MFP_CFG(GPIO36, AF0) | ||
| 107 | #define GPIO37_GPIO MFP_CFG(GPIO37, AF0) | ||
| 108 | #define GPIO38_GPIO MFP_CFG(GPIO38, AF0) | ||
| 109 | #define GPIO39_GPIO MFP_CFG(GPIO39, AF0) | ||
| 110 | #define GPIO40_GPIO MFP_CFG(GPIO40, AF0) | ||
| 111 | #define GPIO41_GPIO MFP_CFG(GPIO41, AF0) | ||
| 112 | #define GPIO42_GPIO MFP_CFG(GPIO42, AF0) | ||
| 113 | #define GPIO43_GPIO MFP_CFG(GPIO43, AF0) | ||
| 114 | #define GPIO44_GPIO MFP_CFG(GPIO44, AF0) | ||
| 115 | #define GPIO45_GPIO MFP_CFG(GPIO45, AF0) | ||
| 116 | |||
| 117 | #define GPIO47_GPIO MFP_CFG(GPIO47, AF0) | ||
| 118 | #define GPIO48_GPIO MFP_CFG(GPIO48, AF0) | ||
| 119 | |||
| 120 | #define GPIO53_GPIO MFP_CFG(GPIO53, AF0) | ||
| 121 | #define GPIO54_GPIO MFP_CFG(GPIO54, AF0) | ||
| 122 | #define GPIO55_GPIO MFP_CFG(GPIO55, AF0) | ||
| 123 | |||
| 124 | #define GPIO57_GPIO MFP_CFG(GPIO57, AF0) | ||
| 125 | |||
| 126 | #define GPIO63_GPIO MFP_CFG(GPIO63, AF0) | ||
| 127 | #define GPIO64_GPIO MFP_CFG(GPIO64, AF0) | ||
| 128 | #define GPIO65_GPIO MFP_CFG(GPIO65, AF0) | ||
| 129 | #define GPIO66_GPIO MFP_CFG(GPIO66, AF0) | ||
| 130 | #define GPIO67_GPIO MFP_CFG(GPIO67, AF0) | ||
| 131 | #define GPIO68_GPIO MFP_CFG(GPIO68, AF0) | ||
| 132 | #define GPIO69_GPIO MFP_CFG(GPIO69, AF0) | ||
| 133 | #define GPIO70_GPIO MFP_CFG(GPIO70, AF0) | ||
| 134 | #define GPIO71_GPIO MFP_CFG(GPIO71, AF0) | ||
| 135 | #define GPIO72_GPIO MFP_CFG(GPIO72, AF0) | ||
| 136 | #define GPIO73_GPIO MFP_CFG(GPIO73, AF0) | ||
| 137 | #define GPIO74_GPIO MFP_CFG(GPIO74, AF0) | ||
| 138 | #define GPIO75_GPIO MFP_CFG(GPIO75, AF0) | ||
| 139 | #define GPIO76_GPIO MFP_CFG(GPIO76, AF0) | ||
| 140 | #define GPIO77_GPIO MFP_CFG(GPIO77, AF0) | ||
| 141 | #define GPIO78_GPIO MFP_CFG(GPIO78, AF0) | ||
| 142 | #define GPIO79_GPIO MFP_CFG(GPIO79, AF0) | ||
| 143 | #define GPIO80_GPIO MFP_CFG(GPIO80, AF0) | ||
| 144 | #define GPIO81_GPIO MFP_CFG(GPIO81, AF0) | ||
| 145 | #define GPIO82_GPIO MFP_CFG(GPIO82, AF0) | ||
| 146 | #define GPIO83_GPIO MFP_CFG(GPIO83, AF0) | ||
| 147 | #define GPIO84_GPIO MFP_CFG(GPIO84, AF0) | ||
| 148 | #define GPIO85_GPIO MFP_CFG(GPIO85, AF0) | ||
| 149 | #define GPIO86_GPIO MFP_CFG(GPIO86, AF0) | ||
| 150 | #define GPIO87_GPIO MFP_CFG(GPIO87, AF0) | ||
| 151 | #define GPIO88_GPIO MFP_CFG(GPIO88, AF0) | ||
| 152 | #define GPIO89_GPIO MFP_CFG(GPIO89, AF0) | ||
| 153 | #define GPIO90_GPIO MFP_CFG(GPIO90, AF0) | ||
| 154 | #define GPIO91_GPIO MFP_CFG(GPIO91, AF0) | ||
| 155 | #define GPIO92_GPIO MFP_CFG(GPIO92, AF0) | ||
| 156 | #define GPIO93_GPIO MFP_CFG(GPIO93, AF0) | ||
| 157 | #define GPIO94_GPIO MFP_CFG(GPIO94, AF0) | ||
| 158 | #define GPIO95_GPIO MFP_CFG(GPIO95, AF0) | ||
| 159 | #define GPIO96_GPIO MFP_CFG(GPIO96, AF0) | ||
| 160 | #define GPIO97_GPIO MFP_CFG(GPIO97, AF0) | ||
| 161 | #define GPIO98_GPIO MFP_CFG(GPIO98, AF0) | ||
| 162 | #define GPIO99_GPIO MFP_CFG(GPIO99, AF0) | ||
| 163 | #define GPIO100_GPIO MFP_CFG(GPIO100, AF0) | ||
| 164 | #define GPIO101_GPIO MFP_CFG(GPIO101, AF0) | ||
| 165 | #define GPIO102_GPIO MFP_CFG(GPIO102, AF0) | ||
| 166 | #define GPIO103_GPIO MFP_CFG(GPIO103, AF0) | ||
| 167 | #define GPIO104_GPIO MFP_CFG(GPIO104, AF0) | ||
| 168 | #define GPIO105_GPIO MFP_CFG(GPIO105, AF0) | ||
| 169 | #define GPIO106_GPIO MFP_CFG(GPIO106, AF0) | ||
| 170 | #define GPIO107_GPIO MFP_CFG(GPIO107, AF0) | ||
| 171 | #define GPIO108_GPIO MFP_CFG(GPIO108, AF0) | ||
| 172 | #define GPIO109_GPIO MFP_CFG(GPIO109, AF0) | ||
| 173 | #define GPIO110_GPIO MFP_CFG(GPIO110, AF0) | ||
| 174 | #define GPIO111_GPIO MFP_CFG(GPIO111, AF0) | ||
| 175 | #define GPIO112_GPIO MFP_CFG(GPIO112, AF0) | ||
| 176 | #define GPIO113_GPIO MFP_CFG(GPIO113, AF0) | ||
| 177 | #define GPIO114_GPIO MFP_CFG(GPIO114, AF0) | ||
| 178 | #define GPIO115_GPIO MFP_CFG(GPIO115, AF0) | ||
| 179 | #define GPIO116_GPIO MFP_CFG(GPIO116, AF0) | ||
| 180 | #define GPIO117_GPIO MFP_CFG(GPIO117, AF0) | ||
| 181 | #define GPIO118_GPIO MFP_CFG(GPIO118, AF0) | ||
| 182 | #define GPIO119_GPIO MFP_CFG(GPIO119, AF0) | ||
| 183 | #define GPIO120_GPIO MFP_CFG(GPIO120, AF0) | ||
| 184 | #define GPIO121_GPIO MFP_CFG(GPIO121, AF0) | ||
| 185 | #define GPIO122_GPIO MFP_CFG(GPIO122, AF0) | ||
| 186 | #define GPIO123_GPIO MFP_CFG(GPIO123, AF0) | ||
| 187 | #define GPIO124_GPIO MFP_CFG(GPIO124, AF0) | ||
| 188 | #define GPIO125_GPIO MFP_CFG(GPIO125, AF0) | ||
| 189 | #define GPIO126_GPIO MFP_CFG(GPIO126, AF0) | ||
| 190 | #define GPIO127_GPIO MFP_CFG(GPIO127, AF0) | ||
| 191 | |||
| 192 | #define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0) | ||
| 193 | #define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0) | ||
| 194 | #define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0) | ||
| 195 | #define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0) | ||
| 196 | #define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0) | ||
| 197 | #define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) | ||
| 198 | #define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) | ||
| 199 | |||
| 200 | /* | ||
| 201 | * each MFP pin will have a MFPR register, since the offset of the | ||
| 202 | * register varies between processors, the processor specific code | ||
| 203 | * should initialize the pin offsets by pxa3xx_mfp_init_addr() | ||
| 204 | * | ||
| 205 | * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map" | ||
| 206 | * structure, which represents a range of MFP pins from "start" to | ||
| 207 | * "end", with the offset begining at "offset", to define a single | ||
| 208 | * pin, let "end" = -1 | ||
| 209 | * | ||
| 210 | * use | ||
| 211 | * | ||
| 212 | * MFP_ADDR_X() to define a range of pins | ||
| 213 | * MFP_ADDR() to define a single pin | ||
| 214 | * MFP_ADDR_END to signal the end of pin offset definitions | ||
| 215 | */ | ||
| 216 | struct pxa3xx_mfp_addr_map { | ||
| 217 | unsigned int start; | ||
| 218 | unsigned int end; | ||
| 219 | unsigned long offset; | ||
| 220 | }; | ||
| 221 | |||
| 222 | #define MFP_ADDR_X(start, end, offset) \ | ||
| 223 | { MFP_PIN_##start, MFP_PIN_##end, offset } | ||
| 224 | |||
| 225 | #define MFP_ADDR(pin, offset) \ | ||
| 226 | { MFP_PIN_##pin, -1, offset } | ||
| 227 | |||
| 228 | #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } | ||
| 229 | |||
| 230 | /* | ||
| 231 | * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access | ||
| 232 | * to the MFPR register | ||
| 233 | */ | ||
| 234 | unsigned long pxa3xx_mfp_read(int mfp); | ||
| 235 | void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val); | ||
| 236 | |||
| 237 | /* | ||
| 238 | * pxa3xx_mfp_config - configure the MFPR registers | ||
| 239 | * | ||
| 240 | * used by board specific initialization code | ||
| 241 | */ | ||
| 242 | void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num); | ||
| 243 | |||
| 244 | /* | ||
| 245 | * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin | ||
| 246 | * index and MFPR register offset | ||
| 247 | * | ||
| 248 | * used by processor specific code | ||
| 249 | */ | ||
| 250 | void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); | ||
| 251 | void __init pxa3xx_init_mfp(void); | ||
| 252 | #endif /* __ASM_ARCH_MFP_PXA3XX_H */ | ||
diff --git a/include/asm-arm/arch-pxa/mfp-pxa930.h b/include/asm-arm/arch-pxa/mfp-pxa930.h deleted file mode 100644 index c4e945ab1923..000000000000 --- a/include/asm-arm/arch-pxa/mfp-pxa930.h +++ /dev/null | |||
| @@ -1,491 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/mfp-pxa930.h | ||
| 3 | * | ||
| 4 | * PXA930 specific MFP configuration definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007-2008 Marvell International Ltd. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_MFP_PXA9xx_H | ||
| 14 | #define __ASM_ARCH_MFP_PXA9xx_H | ||
| 15 | |||
| 16 | #include <asm/arch/mfp.h> | ||
| 17 | #include <asm/arch/mfp-pxa3xx.h> | ||
| 18 | |||
| 19 | /* GPIO */ | ||
| 20 | #define GPIO46_GPIO MFP_CFG(GPIO46, AF0) | ||
| 21 | #define GPIO49_GPIO MFP_CFG(GPIO49, AF0) | ||
| 22 | #define GPIO50_GPIO MFP_CFG(GPIO50, AF0) | ||
| 23 | #define GPIO51_GPIO MFP_CFG(GPIO51, AF0) | ||
| 24 | #define GPIO52_GPIO MFP_CFG(GPIO52, AF0) | ||
| 25 | #define GPIO56_GPIO MFP_CFG(GPIO56, AF0) | ||
| 26 | #define GPIO58_GPIO MFP_CFG(GPIO58, AF0) | ||
| 27 | #define GPIO59_GPIO MFP_CFG(GPIO59, AF0) | ||
| 28 | #define GPIO60_GPIO MFP_CFG(GPIO60, AF0) | ||
| 29 | #define GPIO61_GPIO MFP_CFG(GPIO61, AF0) | ||
| 30 | #define GPIO62_GPIO MFP_CFG(GPIO62, AF0) | ||
| 31 | |||
| 32 | #define GSIM_UCLK_GPIO_79 MFP_CFG(GSIM_UCLK, AF0) | ||
| 33 | #define GSIM_UIO_GPIO_80 MFP_CFG(GSIM_UIO, AF0) | ||
| 34 | #define GSIM_nURST_GPIO_81 MFP_CFG(GSIM_nURST, AF0) | ||
| 35 | #define GSIM_UDET_GPIO_82 MFP_CFG(GSIM_UDET, AF0) | ||
| 36 | |||
| 37 | #define DF_IO15_GPIO_28 MFP_CFG(DF_IO15, AF0) | ||
| 38 | #define DF_IO14_GPIO_29 MFP_CFG(DF_IO14, AF0) | ||
| 39 | #define DF_IO13_GPIO_30 MFP_CFG(DF_IO13, AF0) | ||
| 40 | #define DF_IO12_GPIO_31 MFP_CFG(DF_IO12, AF0) | ||
| 41 | #define DF_IO11_GPIO_32 MFP_CFG(DF_IO11, AF0) | ||
| 42 | #define DF_IO10_GPIO_33 MFP_CFG(DF_IO10, AF0) | ||
| 43 | #define DF_IO9_GPIO_34 MFP_CFG(DF_IO9, AF0) | ||
| 44 | #define DF_IO8_GPIO_35 MFP_CFG(DF_IO8, AF0) | ||
| 45 | #define DF_IO7_GPIO_36 MFP_CFG(DF_IO7, AF0) | ||
| 46 | #define DF_IO6_GPIO_37 MFP_CFG(DF_IO6, AF0) | ||
| 47 | #define DF_IO5_GPIO_38 MFP_CFG(DF_IO5, AF0) | ||
| 48 | #define DF_IO4_GPIO_39 MFP_CFG(DF_IO4, AF0) | ||
| 49 | #define DF_IO3_GPIO_40 MFP_CFG(DF_IO3, AF0) | ||
| 50 | #define DF_IO2_GPIO_41 MFP_CFG(DF_IO2, AF0) | ||
| 51 | #define DF_IO1_GPIO_42 MFP_CFG(DF_IO1, AF0) | ||
| 52 | #define DF_IO0_GPIO_43 MFP_CFG(DF_IO0, AF0) | ||
| 53 | #define DF_nCS0_GPIO_44 MFP_CFG(DF_nCS0, AF0) | ||
| 54 | #define DF_nCS1_GPIO_45 MFP_CFG(DF_nCS1, AF0) | ||
| 55 | #define DF_nWE_GPIO_46 MFP_CFG(DF_nWE, AF0) | ||
| 56 | #define DF_nRE_nOE_GPIO_47 MFP_CFG(DF_nRE_nOE, AF0) | ||
| 57 | #define DF_CLE_nOE_GPIO_48 MFP_CFG(DF_CLE_nOE, AF0) | ||
| 58 | #define DF_nADV1_ALE_GPIO_49 MFP_CFG(DF_nADV1_ALE, AF0) | ||
| 59 | #define DF_nADV2_ALE_GPIO_50 MFP_CFG(DF_nADV2_ALE, AF0) | ||
| 60 | #define DF_INT_RnB_GPIO_51 MFP_CFG(DF_INT_RnB, AF0) | ||
| 61 | #define DF_SCLK_E_GPIO_52 MFP_CFG(DF_SCLK_E, AF0) | ||
| 62 | |||
| 63 | #define DF_ADDR0_GPIO_53 MFP_CFG(DF_ADDR0, AF0) | ||
| 64 | #define DF_ADDR1_GPIO_54 MFP_CFG(DF_ADDR1, AF0) | ||
| 65 | #define DF_ADDR2_GPIO_55 MFP_CFG(DF_ADDR2, AF0) | ||
| 66 | #define DF_ADDR3_GPIO_56 MFP_CFG(DF_ADDR3, AF0) | ||
| 67 | #define nXCVREN_GPIO_57 MFP_CFG(nXCVREN, AF0) | ||
| 68 | #define nLUA_GPIO_58 MFP_CFG(nLUA, AF0) | ||
| 69 | #define nLLA_GPIO_59 MFP_CFG(nLLA, AF0) | ||
| 70 | #define nBE0_GPIO_60 MFP_CFG(nBE0, AF0) | ||
| 71 | #define nBE1_GPIO_61 MFP_CFG(nBE1, AF0) | ||
| 72 | #define RDY_GPIO_62 MFP_CFG(RDY, AF0) | ||
| 73 | |||
| 74 | /* Chip Select */ | ||
| 75 | #define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH) | ||
| 76 | #define DF_nCS1_nCS3 MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH) | ||
| 77 | |||
| 78 | /* AC97 */ | ||
| 79 | #define GPIO83_BAC97_SYSCLK MFP_CFG(GPIO83, AF3) | ||
| 80 | #define GPIO84_BAC97_SDATA_IN0 MFP_CFG(GPIO84, AF3) | ||
| 81 | #define GPIO85_BAC97_BITCLK MFP_CFG(GPIO85, AF3) | ||
| 82 | #define GPIO86_BAC97_nRESET MFP_CFG(GPIO86, AF3) | ||
| 83 | #define GPIO87_BAC97_SYNC MFP_CFG(GPIO87, AF3) | ||
| 84 | #define GPIO88_BAC97_SDATA_OUT MFP_CFG(GPIO88, AF3) | ||
| 85 | |||
| 86 | /* I2C */ | ||
| 87 | #define GPIO39_CI2C_SCL MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH) | ||
| 88 | #define GPIO40_CI2C_SDA MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH) | ||
| 89 | |||
| 90 | #define GPIO51_CI2C_SCL MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH) | ||
| 91 | #define GPIO52_CI2C_SDA MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH) | ||
| 92 | |||
| 93 | #define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH) | ||
| 94 | #define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH) | ||
| 95 | |||
| 96 | #define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH) | ||
| 97 | #define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH) | ||
| 98 | |||
| 99 | #define GPIO89_CI2C_SCL MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH) | ||
| 100 | #define GPIO90_CI2C_SDA MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH) | ||
| 101 | |||
| 102 | #define GPIO95_CI2C_SCL MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) | ||
| 103 | #define GPIO96_CI2C_SDA MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) | ||
| 104 | |||
| 105 | #define GPIO97_CI2C_SCL MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH) | ||
| 106 | #define GPIO98_CI2C_SDA MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH) | ||
| 107 | |||
| 108 | /* QCI */ | ||
| 109 | #define GPIO63_CI_DD_9 MFP_CFG_LPM(GPIO63, AF1, PULL_LOW) | ||
| 110 | #define GPIO64_CI_DD_8 MFP_CFG_LPM(GPIO64, AF1, PULL_LOW) | ||
| 111 | #define GPIO65_CI_DD_7 MFP_CFG_LPM(GPIO65, AF1, PULL_LOW) | ||
| 112 | #define GPIO66_CI_DD_6 MFP_CFG_LPM(GPIO66, AF1, PULL_LOW) | ||
| 113 | #define GPIO67_CI_DD_5 MFP_CFG_LPM(GPIO67, AF1, PULL_LOW) | ||
| 114 | #define GPIO68_CI_DD_4 MFP_CFG_LPM(GPIO68, AF1, PULL_LOW) | ||
| 115 | #define GPIO69_CI_DD_3 MFP_CFG_LPM(GPIO69, AF1, PULL_LOW) | ||
| 116 | #define GPIO70_CI_DD_2 MFP_CFG_LPM(GPIO70, AF1, PULL_LOW) | ||
| 117 | #define GPIO71_CI_DD_1 MFP_CFG_LPM(GPIO71, AF1, PULL_LOW) | ||
| 118 | #define GPIO72_CI_DD_0 MFP_CFG_LPM(GPIO72, AF1, PULL_LOW) | ||
| 119 | #define GPIO73_CI_HSYNC MFP_CFG_LPM(GPIO73, AF1, PULL_LOW) | ||
| 120 | #define GPIO74_CI_VSYNC MFP_CFG_LPM(GPIO74, AF1, PULL_LOW) | ||
| 121 | #define GPIO75_CI_MCLK MFP_CFG_LPM(GPIO75, AF1, PULL_LOW) | ||
| 122 | #define GPIO76_CI_PCLK MFP_CFG_LPM(GPIO76, AF1, PULL_LOW) | ||
| 123 | |||
| 124 | /* KEYPAD */ | ||
| 125 | #define GPIO4_KP_DKIN_4 MFP_CFG_LPM(GPIO4, AF3, FLOAT) | ||
| 126 | #define GPIO5_KP_DKIN_5 MFP_CFG_LPM(GPIO5, AF3, FLOAT) | ||
| 127 | #define GPIO6_KP_DKIN_6 MFP_CFG_LPM(GPIO6, AF3, FLOAT) | ||
| 128 | #define GPIO7_KP_DKIN_7 MFP_CFG_LPM(GPIO7, AF3, FLOAT) | ||
| 129 | #define GPIO8_KP_DKIN_4 MFP_CFG_LPM(GPIO8, AF3, FLOAT) | ||
| 130 | #define GPIO9_KP_DKIN_5 MFP_CFG_LPM(GPIO9, AF3, FLOAT) | ||
| 131 | #define GPIO10_KP_DKIN_6 MFP_CFG_LPM(GPIO10, AF3, FLOAT) | ||
| 132 | #define GPIO11_KP_DKIN_7 MFP_CFG_LPM(GPIO11, AF3, FLOAT) | ||
| 133 | |||
| 134 | #define GPIO12_KP_DKIN_0 MFP_CFG_LPM(GPIO12, AF2, FLOAT) | ||
| 135 | #define GPIO13_KP_DKIN_1 MFP_CFG_LPM(GPIO13, AF2, FLOAT) | ||
| 136 | #define GPIO14_KP_DKIN_2 MFP_CFG_LPM(GPIO14, AF2, FLOAT) | ||
| 137 | #define GPIO15_KP_DKIN_3 MFP_CFG_LPM(GPIO15, AF2, FLOAT) | ||
| 138 | |||
| 139 | #define GPIO41_KP_DKIN_0 MFP_CFG_LPM(GPIO41, AF2, FLOAT) | ||
| 140 | #define GPIO42_KP_DKIN_1 MFP_CFG_LPM(GPIO42, AF2, FLOAT) | ||
| 141 | #define GPIO43_KP_DKIN_2 MFP_CFG_LPM(GPIO43, AF2, FLOAT) | ||
| 142 | #define GPIO44_KP_DKIN_3 MFP_CFG_LPM(GPIO44, AF2, FLOAT) | ||
| 143 | #define GPIO41_KP_DKIN_4 MFP_CFG_LPM(GPIO41, AF4, FLOAT) | ||
| 144 | #define GPIO42_KP_DKIN_5 MFP_CFG_LPM(GPIO42, AF4, FLOAT) | ||
| 145 | |||
| 146 | #define GPIO0_KP_MKIN_0 MFP_CFG_LPM(GPIO0, AF1, FLOAT) | ||
| 147 | #define GPIO2_KP_MKIN_1 MFP_CFG_LPM(GPIO2, AF1, FLOAT) | ||
| 148 | #define GPIO4_KP_MKIN_2 MFP_CFG_LPM(GPIO4, AF1, FLOAT) | ||
| 149 | #define GPIO6_KP_MKIN_3 MFP_CFG_LPM(GPIO6, AF1, FLOAT) | ||
| 150 | #define GPIO8_KP_MKIN_4 MFP_CFG_LPM(GPIO8, AF1, FLOAT) | ||
| 151 | #define GPIO10_KP_MKIN_5 MFP_CFG_LPM(GPIO10, AF1, FLOAT) | ||
| 152 | #define GPIO12_KP_MKIN_6 MFP_CFG_LPM(GPIO12, AF1, FLOAT) | ||
| 153 | #define GPIO14_KP_MKIN_7 MFP_CFG(GPIO14, AF1) | ||
| 154 | #define GPIO35_KP_MKIN_5 MFP_CFG(GPIO35, AF4) | ||
| 155 | |||
| 156 | #define GPIO1_KP_MKOUT_0 MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH) | ||
| 157 | #define GPIO3_KP_MKOUT_1 MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH) | ||
| 158 | #define GPIO5_KP_MKOUT_2 MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH) | ||
| 159 | #define GPIO7_KP_MKOUT_3 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) | ||
| 160 | #define GPIO9_KP_MKOUT_4 MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH) | ||
| 161 | #define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH) | ||
| 162 | #define GPIO13_KP_MKOUT_6 MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH) | ||
| 163 | #define GPIO15_KP_MKOUT_7 MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH) | ||
| 164 | #define GPIO36_KP_MKOUT_5 MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH) | ||
| 165 | |||
| 166 | /* LCD */ | ||
| 167 | #define GPIO17_LCD_FCLK_RD MFP_CFG(GPIO17, AF1) | ||
| 168 | #define GPIO18_LCD_LCLK_A0 MFP_CFG(GPIO18, AF1) | ||
| 169 | #define GPIO19_LCD_PCLK_WR MFP_CFG(GPIO19, AF1) | ||
| 170 | #define GPIO20_LCD_BIAS MFP_CFG(GPIO20, AF1) | ||
| 171 | #define GPIO21_LCD_CS MFP_CFG(GPIO21, AF1) | ||
| 172 | #define GPIO22_LCD_CS2 MFP_CFG(GPIO22, AF2) | ||
| 173 | #define GPIO22_LCD_VSYNC MFP_CFG(GPIO22, AF1) | ||
| 174 | #define GPIO23_LCD_DD0 MFP_CFG(GPIO23, AF1) | ||
| 175 | #define GPIO24_LCD_DD1 MFP_CFG(GPIO24, AF1) | ||
| 176 | #define GPIO25_LCD_DD2 MFP_CFG(GPIO25, AF1) | ||
| 177 | #define GPIO26_LCD_DD3 MFP_CFG(GPIO26, AF1) | ||
| 178 | #define GPIO27_LCD_DD4 MFP_CFG(GPIO27, AF1) | ||
| 179 | #define GPIO28_LCD_DD5 MFP_CFG(GPIO28, AF1) | ||
| 180 | #define GPIO29_LCD_DD6 MFP_CFG(GPIO29, AF1) | ||
| 181 | #define GPIO30_LCD_DD7 MFP_CFG(GPIO30, AF1) | ||
| 182 | #define GPIO31_LCD_DD8 MFP_CFG(GPIO31, AF1) | ||
| 183 | #define GPIO32_LCD_DD9 MFP_CFG(GPIO32, AF1) | ||
| 184 | #define GPIO33_LCD_DD10 MFP_CFG(GPIO33, AF1) | ||
| 185 | #define GPIO34_LCD_DD11 MFP_CFG(GPIO34, AF1) | ||
| 186 | #define GPIO35_LCD_DD12 MFP_CFG(GPIO35, AF1) | ||
| 187 | #define GPIO36_LCD_DD13 MFP_CFG(GPIO36, AF1) | ||
| 188 | #define GPIO37_LCD_DD14 MFP_CFG(GPIO37, AF1) | ||
| 189 | #define GPIO38_LCD_DD15 MFP_CFG(GPIO38, AF1) | ||
| 190 | #define GPIO39_LCD_DD16 MFP_CFG(GPIO39, AF1) | ||
| 191 | #define GPIO40_LCD_DD17 MFP_CFG(GPIO40, AF1) | ||
| 192 | #define GPIO41_LCD_CS2 MFP_CFG(GPIO41, AF3) | ||
| 193 | #define GPIO42_LCD_VSYNC2 MFP_CFG(GPIO42, AF3) | ||
| 194 | #define GPIO44_LCD_DD7 MFP_CFG(GPIO44, AF1) | ||
| 195 | |||
| 196 | /* Mini-LCD */ | ||
| 197 | #define GPIO17_MLCD_FCLK MFP_CFG(GPIO17, AF3) | ||
| 198 | #define GPIO18_MLCD_LCLK MFP_CFG(GPIO18, AF3) | ||
| 199 | #define GPIO19_MLCD_PCLK MFP_CFG(GPIO19, AF3) | ||
| 200 | #define GPIO20_MLCD_BIAS MFP_CFG(GPIO20, AF3) | ||
| 201 | #define GPIO23_MLCD_DD0 MFP_CFG(GPIO23, AF3) | ||
| 202 | #define GPIO24_MLCD_DD1 MFP_CFG(GPIO24, AF3) | ||
| 203 | #define GPIO25_MLCD_DD2 MFP_CFG(GPIO25, AF3) | ||
| 204 | #define GPIO26_MLCD_DD3 MFP_CFG(GPIO26, AF3) | ||
| 205 | #define GPIO27_MLCD_DD4 MFP_CFG(GPIO27, AF3) | ||
| 206 | #define GPIO28_MLCD_DD5 MFP_CFG(GPIO28, AF3) | ||
| 207 | #define GPIO29_MLCD_DD6 MFP_CFG(GPIO29, AF3) | ||
| 208 | #define GPIO30_MLCD_DD7 MFP_CFG(GPIO30, AF3) | ||
| 209 | #define GPIO31_MLCD_DD8 MFP_CFG(GPIO31, AF3) | ||
| 210 | #define GPIO32_MLCD_DD9 MFP_CFG(GPIO32, AF3) | ||
| 211 | #define GPIO33_MLCD_DD10 MFP_CFG(GPIO33, AF3) | ||
| 212 | #define GPIO34_MLCD_DD11 MFP_CFG(GPIO34, AF3) | ||
| 213 | #define GPIO35_MLCD_DD12 MFP_CFG(GPIO35, AF3) | ||
| 214 | #define GPIO36_MLCD_DD13 MFP_CFG(GPIO36, AF3) | ||
| 215 | #define GPIO37_MLCD_DD14 MFP_CFG(GPIO37, AF3) | ||
| 216 | #define GPIO38_MLCD_DD15 MFP_CFG(GPIO38, AF3) | ||
| 217 | #define GPIO44_MLCD_DD7 MFP_CFG(GPIO44, AF5) | ||
| 218 | |||
| 219 | /* MMC1 */ | ||
| 220 | #define GPIO10_MMC1_DAT3 MFP_CFG(GPIO10, AF4) | ||
| 221 | #define GPIO11_MMC1_DAT2 MFP_CFG(GPIO11, AF4) | ||
| 222 | #define GPIO12_MMC1_DAT1 MFP_CFG(GPIO12, AF4) | ||
| 223 | #define GPIO13_MMC1_DAT0 MFP_CFG(GPIO13, AF4) | ||
| 224 | #define GPIO14_MMC1_CMD MFP_CFG(GPIO14, AF4) | ||
| 225 | #define GPIO15_MMC1_CLK MFP_CFG(GPIO15, AF4) | ||
| 226 | #define GPIO55_MMC1_CMD MFP_CFG(GPIO55, AF3) | ||
| 227 | #define GPIO56_MMC1_CLK MFP_CFG(GPIO56, AF3) | ||
| 228 | #define GPIO57_MMC1_DAT0 MFP_CFG(GPIO57, AF3) | ||
| 229 | #define GPIO58_MMC1_DAT1 MFP_CFG(GPIO58, AF3) | ||
| 230 | #define GPIO59_MMC1_DAT2 MFP_CFG(GPIO59, AF3) | ||
| 231 | #define GPIO60_MMC1_DAT3 MFP_CFG(GPIO60, AF3) | ||
| 232 | |||
| 233 | #define DF_ADDR0_MMC1_CLK MFP_CFG(DF_ADDR0, AF2) | ||
| 234 | #define DF_ADDR1_MMC1_CMD MFP_CFG(DF_ADDR1, AF2) | ||
| 235 | #define DF_ADDR2_MMC1_DAT0 MFP_CFG(DF_ADDR2, AF2) | ||
| 236 | #define DF_ADDR3_MMC1_DAT1 MFP_CFG(DF_ADDR3, AF3) | ||
| 237 | #define nXCVREN_MMC1_DAT2 MFP_CFG(nXCVREN, AF2) | ||
| 238 | |||
| 239 | /* MMC2 */ | ||
| 240 | #define GPIO31_MMC2_CMD MFP_CFG(GPIO31, AF7) | ||
| 241 | #define GPIO32_MMC2_CLK MFP_CFG(GPIO32, AF7) | ||
| 242 | #define GPIO33_MMC2_DAT0 MFP_CFG(GPIO33, AF7) | ||
| 243 | #define GPIO34_MMC2_DAT1 MFP_CFG(GPIO34, AF7) | ||
| 244 | #define GPIO35_MMC2_DAT2 MFP_CFG(GPIO35, AF7) | ||
| 245 | #define GPIO36_MMC2_DAT3 MFP_CFG(GPIO36, AF7) | ||
| 246 | |||
| 247 | #define GPIO101_MMC2_DAT3 MFP_CFG(GPIO101, AF1) | ||
| 248 | #define GPIO102_MMC2_DAT2 MFP_CFG(GPIO102, AF1) | ||
| 249 | #define GPIO103_MMC2_DAT1 MFP_CFG(GPIO103, AF1) | ||
| 250 | #define GPIO104_MMC2_DAT0 MFP_CFG(GPIO104, AF1) | ||
| 251 | #define GPIO105_MMC2_CMD MFP_CFG(GPIO105, AF1) | ||
| 252 | #define GPIO106_MMC2_CLK MFP_CFG(GPIO106, AF1) | ||
| 253 | |||
| 254 | #define DF_IO10_MMC2_DAT3 MFP_CFG(DF_IO10, AF3) | ||
| 255 | #define DF_IO11_MMC2_DAT2 MFP_CFG(DF_IO11, AF3) | ||
| 256 | #define DF_IO12_MMC2_DAT1 MFP_CFG(DF_IO12, AF3) | ||
| 257 | #define DF_IO13_MMC2_DAT0 MFP_CFG(DF_IO13, AF3) | ||
| 258 | #define DF_IO14_MMC2_CLK MFP_CFG(DF_IO14, AF3) | ||
| 259 | #define DF_IO15_MMC2_CMD MFP_CFG(DF_IO15, AF3) | ||
| 260 | |||
| 261 | /* BSSP1 */ | ||
| 262 | #define GPIO12_BSSP1_CLK MFP_CFG(GPIO12, AF3) | ||
| 263 | #define GPIO13_BSSP1_FRM MFP_CFG(GPIO13, AF3) | ||
| 264 | #define GPIO14_BSSP1_RXD MFP_CFG(GPIO14, AF3) | ||
| 265 | #define GPIO15_BSSP1_TXD MFP_CFG(GPIO15, AF3) | ||
| 266 | #define GPIO97_BSSP1_CLK MFP_CFG(GPIO97, AF5) | ||
| 267 | #define GPIO98_BSSP1_FRM MFP_CFG(GPIO98, AF5) | ||
| 268 | |||
| 269 | /* BSSP2 */ | ||
| 270 | #define GPIO84_BSSP2_SDATA_IN MFP_CFG(GPIO84, AF1) | ||
| 271 | #define GPIO85_BSSP2_BITCLK MFP_CFG(GPIO85, AF1) | ||
| 272 | #define GPIO86_BSSP2_SYSCLK MFP_CFG(GPIO86, AF1) | ||
| 273 | #define GPIO87_BSSP2_SYNC MFP_CFG(GPIO87, AF1) | ||
| 274 | #define GPIO88_BSSP2_DATA_OUT MFP_CFG(GPIO88, AF1) | ||
| 275 | #define GPIO86_BSSP2_SDATA_IN MFP_CFG(GPIO86, AF4) | ||
| 276 | |||
| 277 | /* BSSP3 */ | ||
| 278 | #define GPIO79_BSSP3_CLK MFP_CFG(GPIO79, AF1) | ||
| 279 | #define GPIO80_BSSP3_FRM MFP_CFG(GPIO80, AF1) | ||
| 280 | #define GPIO81_BSSP3_TXD MFP_CFG(GPIO81, AF1) | ||
| 281 | #define GPIO82_BSSP3_RXD MFP_CFG(GPIO82, AF1) | ||
| 282 | #define GPIO83_BSSP3_SYSCLK MFP_CFG(GPIO83, AF1) | ||
| 283 | |||
| 284 | /* BSSP4 */ | ||
| 285 | #define GPIO43_BSSP4_CLK MFP_CFG(GPIO43, AF4) | ||
| 286 | #define GPIO44_BSSP4_FRM MFP_CFG(GPIO44, AF4) | ||
| 287 | #define GPIO45_BSSP4_TXD MFP_CFG(GPIO45, AF4) | ||
| 288 | #define GPIO46_BSSP4_RXD MFP_CFG(GPIO46, AF4) | ||
| 289 | |||
| 290 | #define GPIO51_BSSP4_CLK MFP_CFG(GPIO51, AF4) | ||
| 291 | #define GPIO52_BSSP4_FRM MFP_CFG(GPIO52, AF4) | ||
| 292 | #define GPIO53_BSSP4_TXD MFP_CFG(GPIO53, AF4) | ||
| 293 | #define GPIO54_BSSP4_RXD MFP_CFG(GPIO54, AF4) | ||
| 294 | |||
| 295 | /* GSSP1 */ | ||
| 296 | #define GPIO79_GSSP1_CLK MFP_CFG(GPIO79, AF2) | ||
| 297 | #define GPIO80_GSSP1_FRM MFP_CFG(GPIO80, AF2) | ||
| 298 | #define GPIO81_GSSP1_TXD MFP_CFG(GPIO81, AF2) | ||
| 299 | #define GPIO82_GSSP1_RXD MFP_CFG(GPIO82, AF2) | ||
| 300 | #define GPIO83_GSSP1_SYSCLK MFP_CFG(GPIO83, AF2) | ||
| 301 | |||
| 302 | #define GPIO93_GSSP1_CLK MFP_CFG(GPIO93, AF4) | ||
| 303 | #define GPIO94_GSSP1_FRM MFP_CFG(GPIO94, AF4) | ||
| 304 | #define GPIO95_GSSP1_TXD MFP_CFG(GPIO95, AF4) | ||
| 305 | #define GPIO96_GSSP1_RXD MFP_CFG(GPIO96, AF4) | ||
| 306 | |||
| 307 | /* GSSP2 */ | ||
| 308 | #define GPIO47_GSSP2_CLK MFP_CFG(GPIO47, AF4) | ||
| 309 | #define GPIO48_GSSP2_FRM MFP_CFG(GPIO48, AF4) | ||
| 310 | #define GPIO49_GSSP2_RXD MFP_CFG(GPIO49, AF4) | ||
| 311 | #define GPIO50_GSSP2_TXD MFP_CFG(GPIO50, AF4) | ||
| 312 | |||
| 313 | #define GPIO69_GSSP2_CLK MFP_CFG(GPIO69, AF4) | ||
| 314 | #define GPIO70_GSSP2_FRM MFP_CFG(GPIO70, AF4) | ||
| 315 | #define GPIO71_GSSP2_RXD MFP_CFG(GPIO71, AF4) | ||
| 316 | #define GPIO72_GSSP2_TXD MFP_CFG(GPIO72, AF4) | ||
| 317 | |||
| 318 | #define GPIO84_GSSP2_RXD MFP_CFG(GPIO84, AF2) | ||
| 319 | #define GPIO85_GSSP2_CLK MFP_CFG(GPIO85, AF2) | ||
| 320 | #define GPIO86_GSSP2_SYSCLK MFP_CFG(GPIO86, AF2) | ||
| 321 | #define GPIO87_GSSP2_FRM MFP_CFG(GPIO87, AF2) | ||
| 322 | #define GPIO88_GSSP2_TXD MFP_CFG(GPIO88, AF2) | ||
| 323 | #define GPIO86_GSSP2_RXD MFP_CFG(GPIO86, AF5) | ||
| 324 | |||
| 325 | #define GPIO103_GSSP2_CLK MFP_CFG(GPIO103, AF2) | ||
| 326 | #define GPIO104_GSSP2_FRM MFP_CFG(GPIO104, AF2) | ||
| 327 | #define GPIO105_GSSP2_RXD MFP_CFG(GPIO105, AF2) | ||
| 328 | #define GPIO106_GSSP2_TXD MFP_CFG(GPIO106, AF2) | ||
| 329 | |||
| 330 | /* UART1 - FFUART */ | ||
| 331 | #define GPIO47_UART1_DSR_N MFP_CFG(GPIO47, AF1) | ||
| 332 | #define GPIO48_UART1_DTR_N MFP_CFG(GPIO48, AF1) | ||
| 333 | #define GPIO49_UART1_RI MFP_CFG(GPIO49, AF1) | ||
| 334 | #define GPIO50_UART1_DCD MFP_CFG(GPIO50, AF1) | ||
| 335 | #define GPIO51_UART1_CTS MFP_CFG(GPIO51, AF1) | ||
| 336 | #define GPIO52_UART1_RTS MFP_CFG(GPIO52, AF1) | ||
| 337 | #define GPIO53_UART1_RXD MFP_CFG(GPIO53, AF1) | ||
| 338 | #define GPIO54_UART1_TXD MFP_CFG(GPIO54, AF1) | ||
| 339 | |||
| 340 | #define GPIO63_UART1_TXD MFP_CFG(GPIO63, AF2) | ||
| 341 | #define GPIO64_UART1_RXD MFP_CFG(GPIO64, AF2) | ||
| 342 | #define GPIO65_UART1_DSR MFP_CFG(GPIO65, AF2) | ||
| 343 | #define GPIO66_UART1_DTR MFP_CFG(GPIO66, AF2) | ||
| 344 | #define GPIO67_UART1_RI MFP_CFG(GPIO67, AF2) | ||
| 345 | #define GPIO68_UART1_DCD MFP_CFG(GPIO68, AF2) | ||
| 346 | #define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2) | ||
| 347 | #define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2) | ||
| 348 | |||
| 349 | /* UART2 - BTUART */ | ||
| 350 | #define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1) | ||
| 351 | #define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1) | ||
| 352 | #define GPIO93_UART2_CTS MFP_CFG(GPIO93, AF1) | ||
| 353 | #define GPIO94_UART2_RTS MFP_CFG(GPIO94, AF1) | ||
| 354 | |||
| 355 | /* UART3 - STUART */ | ||
| 356 | #define GPIO43_UART3_RTS MFP_CFG(GPIO43, AF3) | ||
| 357 | #define GPIO44_UART3_CTS MFP_CFG(GPIO44, AF3) | ||
| 358 | #define GPIO45_UART3_RXD MFP_CFG(GPIO45, AF3) | ||
| 359 | #define GPIO46_UART3_TXD MFP_CFG(GPIO46, AF3) | ||
| 360 | |||
| 361 | #define GPIO75_UART3_RTS MFP_CFG(GPIO75, AF5) | ||
| 362 | #define GPIO76_UART3_CTS MFP_CFG(GPIO76, AF5) | ||
| 363 | #define GPIO77_UART3_TXD MFP_CFG(GPIO77, AF5) | ||
| 364 | #define GPIO78_UART3_RXD MFP_CFG(GPIO78, AF5) | ||
| 365 | |||
| 366 | /* DFI */ | ||
| 367 | #define DF_IO0_DF_IO0 MFP_CFG(DF_IO0, AF2) | ||
| 368 | #define DF_IO1_DF_IO1 MFP_CFG(DF_IO1, AF2) | ||
| 369 | #define DF_IO2_DF_IO2 MFP_CFG(DF_IO2, AF2) | ||
| 370 | #define DF_IO3_DF_IO3 MFP_CFG(DF_IO3, AF2) | ||
| 371 | #define DF_IO4_DF_IO4 MFP_CFG(DF_IO4, AF2) | ||
| 372 | #define DF_IO5_DF_IO5 MFP_CFG(DF_IO5, AF2) | ||
| 373 | #define DF_IO6_DF_IO6 MFP_CFG(DF_IO6, AF2) | ||
| 374 | #define DF_IO7_DF_IO7 MFP_CFG(DF_IO7, AF2) | ||
| 375 | #define DF_IO8_DF_IO8 MFP_CFG(DF_IO8, AF2) | ||
| 376 | #define DF_IO9_DF_IO9 MFP_CFG(DF_IO9, AF2) | ||
| 377 | #define DF_IO10_DF_IO10 MFP_CFG(DF_IO10, AF2) | ||
| 378 | #define DF_IO11_DF_IO11 MFP_CFG(DF_IO11, AF2) | ||
| 379 | #define DF_IO12_DF_IO12 MFP_CFG(DF_IO12, AF2) | ||
| 380 | #define DF_IO13_DF_IO13 MFP_CFG(DF_IO13, AF2) | ||
| 381 | #define DF_IO14_DF_IO14 MFP_CFG(DF_IO14, AF2) | ||
| 382 | #define DF_IO15_DF_IO15 MFP_CFG(DF_IO15, AF2) | ||
| 383 | #define DF_nADV1_ALE_DF_nADV1 MFP_CFG(DF_nADV1_ALE, AF2) | ||
| 384 | #define DF_nADV2_ALE_DF_nADV2 MFP_CFG(DF_nADV2_ALE, AF2) | ||
| 385 | #define DF_nCS0_DF_nCS0 MFP_CFG(DF_nCS0, AF2) | ||
| 386 | #define DF_nCS1_DF_nCS1 MFP_CFG(DF_nCS1, AF2) | ||
| 387 | #define DF_nRE_nOE_DF_nOE MFP_CFG(DF_nRE_nOE, AF2) | ||
| 388 | #define DF_nWE_DF_nWE MFP_CFG(DF_nWE, AF2) | ||
| 389 | |||
| 390 | /* DFI - NAND */ | ||
| 391 | #define DF_CLE_nOE_ND_CLE MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH) | ||
| 392 | #define DF_INT_RnB_ND_INT_RnB MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW) | ||
| 393 | #define DF_IO0_ND_IO0 MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW) | ||
| 394 | #define DF_IO1_ND_IO1 MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW) | ||
| 395 | #define DF_IO2_ND_IO2 MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW) | ||
| 396 | #define DF_IO3_ND_IO3 MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW) | ||
| 397 | #define DF_IO4_ND_IO4 MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW) | ||
| 398 | #define DF_IO5_ND_IO5 MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW) | ||
| 399 | #define DF_IO6_ND_IO6 MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW) | ||
| 400 | #define DF_IO7_ND_IO7 MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW) | ||
| 401 | #define DF_IO8_ND_IO8 MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW) | ||
| 402 | #define DF_IO9_ND_IO9 MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW) | ||
| 403 | #define DF_IO10_ND_IO10 MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW) | ||
| 404 | #define DF_IO11_ND_IO11 MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW) | ||
| 405 | #define DF_IO12_ND_IO12 MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW) | ||
| 406 | #define DF_IO13_ND_IO13 MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW) | ||
| 407 | #define DF_IO14_ND_IO14 MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW) | ||
| 408 | #define DF_IO15_ND_IO15 MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW) | ||
| 409 | #define DF_nADV1_ALE_ND_ALE MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH) | ||
| 410 | #define DF_nADV2_ALE_ND_ALE MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH) | ||
| 411 | #define DF_nADV2_ALE_nCS3 MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH) | ||
| 412 | #define DF_nCS0_ND_nCS0 MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH) | ||
| 413 | #define DF_nCS1_ND_nCS1 MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH) | ||
| 414 | #define DF_nRE_nOE_ND_nRE MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH) | ||
| 415 | #define DF_nWE_ND_nWE MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH) | ||
| 416 | |||
| 417 | /* PWM */ | ||
| 418 | #define GPIO41_PWM0 MFP_CFG_LPM(GPIO41, AF1, PULL_LOW) | ||
| 419 | #define GPIO42_PWM1 MFP_CFG_LPM(GPIO42, AF1, PULL_LOW) | ||
| 420 | #define GPIO43_PWM3 MFP_CFG_LPM(GPIO43, AF1, PULL_LOW) | ||
| 421 | #define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW) | ||
| 422 | #define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW) | ||
| 423 | #define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW) | ||
| 424 | |||
| 425 | /* CIR */ | ||
| 426 | #define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1) | ||
| 427 | #define GPIO77_CIR_OUT MFP_CFG(GPIO77, AF3) | ||
| 428 | |||
| 429 | /* USB P2 */ | ||
| 430 | #define GPIO0_USB_P2_7 MFP_CFG(GPIO0, AF3) | ||
| 431 | #define GPIO15_USB_P2_7 MFP_CFG(GPIO15, AF5) | ||
| 432 | #define GPIO16_USB_P2_7 MFP_CFG(GPIO16, AF2) | ||
| 433 | #define GPIO48_USB_P2_7 MFP_CFG(GPIO48, AF7) | ||
| 434 | #define GPIO49_USB_P2_7 MFP_CFG(GPIO49, AF6) | ||
| 435 | #define DF_IO9_USB_P2_7 MFP_CFG(DF_IO9, AF3) | ||
| 436 | |||
| 437 | #define GPIO48_USB_P2_8 MFP_CFG(GPIO48, AF2) | ||
| 438 | #define GPIO50_USB_P2_7 MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT) | ||
| 439 | #define GPIO51_USB_P2_5 MFP_CFG(GPIO51, AF2) | ||
| 440 | #define GPIO47_USB_P2_4 MFP_CFG(GPIO47, AF2) | ||
| 441 | #define GPIO53_USB_P2_3 MFP_CFG(GPIO53, AF2) | ||
| 442 | #define GPIO54_USB_P2_6 MFP_CFG(GPIO54, AF2) | ||
| 443 | #define GPIO49_USB_P2_2 MFP_CFG(GPIO49, AF2) | ||
| 444 | #define GPIO52_USB_P2_1 MFP_CFG(GPIO52, AF2) | ||
| 445 | |||
| 446 | #define GPIO63_USB_P2_8 MFP_CFG(GPIO63, AF3) | ||
| 447 | #define GPIO64_USB_P2_7 MFP_CFG(GPIO64, AF3) | ||
| 448 | #define GPIO65_USB_P2_6 MFP_CFG(GPIO65, AF3) | ||
| 449 | #define GPIO66_USG_P2_5 MFP_CFG(GPIO66, AF3) | ||
| 450 | #define GPIO67_USB_P2_4 MFP_CFG(GPIO67, AF3) | ||
| 451 | #define GPIO68_USB_P2_3 MFP_CFG(GPIO68, AF3) | ||
| 452 | #define GPIO69_USB_P2_2 MFP_CFG(GPIO69, AF3) | ||
| 453 | #define GPIO70_USB_P2_1 MFP_CFG(GPIO70, AF3) | ||
| 454 | |||
| 455 | /* ULPI */ | ||
| 456 | #define GPIO31_USB_ULPI_D0 MFP_CFG(GPIO31, AF4) | ||
| 457 | #define GPIO30_USB_ULPI_D1 MFP_CFG(GPIO30, AF7) | ||
| 458 | #define GPIO33_USB_ULPI_D2 MFP_CFG(GPIO33, AF5) | ||
| 459 | #define GPIO34_USB_ULPI_D3 MFP_CFG(GPIO34, AF5) | ||
| 460 | #define GPIO35_USB_ULPI_D4 MFP_CFG(GPIO35, AF5) | ||
| 461 | #define GPIO36_USB_ULPI_D5 MFP_CFG(GPIO36, AF5) | ||
| 462 | #define GPIO41_USB_ULPI_D6 MFP_CFG(GPIO41, AF5) | ||
| 463 | #define GPIO42_USB_ULPI_D7 MFP_CFG(GPIO42, AF5) | ||
| 464 | #define GPIO37_USB_ULPI_DIR MFP_CFG(GPIO37, AF4) | ||
| 465 | #define GPIO38_USB_ULPI_CLK MFP_CFG(GPIO38, AF4) | ||
| 466 | #define GPIO39_USB_ULPI_STP MFP_CFG(GPIO39, AF4) | ||
| 467 | #define GPIO40_USB_ULPI_NXT MFP_CFG(GPIO40, AF4) | ||
| 468 | |||
| 469 | #define GPIO3_CLK26MOUTDMD MFP_CFG(GPIO3, AF3) | ||
| 470 | #define GPIO40_CLK26MOUTDMD MFP_CFG(GPIO40, AF7) | ||
| 471 | #define GPIO94_CLK26MOUTDMD MFP_CFG(GPIO94, AF5) | ||
| 472 | #define GPIO104_CLK26MOUTDMD MFP_CFG(GPIO104, AF4) | ||
| 473 | #define DF_ADDR1_CLK26MOUTDMD MFP_CFG(DF_ADDR2, AF3) | ||
| 474 | #define DF_ADDR3_CLK26MOUTDMD MFP_CFG(DF_ADDR3, AF3) | ||
| 475 | |||
| 476 | #define GPIO14_CLK26MOUT MFP_CFG(GPIO14, AF5) | ||
| 477 | #define GPIO38_CLK26MOUT MFP_CFG(GPIO38, AF7) | ||
| 478 | #define GPIO92_CLK26MOUT MFP_CFG(GPIO92, AF5) | ||
| 479 | #define GPIO105_CLK26MOUT MFP_CFG(GPIO105, AF4) | ||
| 480 | |||
| 481 | #define GPIO2_CLK13MOUTDMD MFP_CFG(GPIO2, AF3) | ||
| 482 | #define GPIO39_CLK13MOUTDMD MFP_CFG(GPIO39, AF7) | ||
| 483 | #define GPIO50_CLK13MOUTDMD MFP_CFG(GPIO50, AF3) | ||
| 484 | #define GPIO93_CLK13MOUTDMD MFP_CFG(GPIO93, AF5) | ||
| 485 | #define GPIO103_CLK13MOUTDMD MFP_CFG(GPIO103, AF4) | ||
| 486 | #define DF_ADDR2_CLK13MOUTDMD MFP_CFG(DF_ADDR2, AF3) | ||
| 487 | |||
| 488 | /* 1 wire */ | ||
| 489 | #define GPIO95_OW_DQ_IN MFP_CFG(GPIO95, AF5) | ||
| 490 | |||
| 491 | #endif /* __ASM_ARCH_MFP_PXA9xx_H */ | ||
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h deleted file mode 100644 index e7d58798da67..000000000000 --- a/include/asm-arm/arch-pxa/mfp.h +++ /dev/null | |||
| @@ -1,319 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/mfp.h | ||
| 3 | * | ||
| 4 | * Multi-Function Pin Definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Marvell International Ltd. | ||
| 7 | * | ||
| 8 | * 2007-8-21: eric miao <eric.miao@marvell.com> | ||
| 9 | * initial version | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_MFP_H | ||
| 17 | #define __ASM_ARCH_MFP_H | ||
| 18 | |||
| 19 | #define mfp_to_gpio(m) ((m) % 128) | ||
| 20 | |||
| 21 | /* list of all the configurable MFP pins */ | ||
| 22 | enum { | ||
| 23 | MFP_PIN_INVALID = -1, | ||
| 24 | |||
| 25 | MFP_PIN_GPIO0 = 0, | ||
| 26 | MFP_PIN_GPIO1, | ||
| 27 | MFP_PIN_GPIO2, | ||
| 28 | MFP_PIN_GPIO3, | ||
| 29 | MFP_PIN_GPIO4, | ||
| 30 | MFP_PIN_GPIO5, | ||
| 31 | MFP_PIN_GPIO6, | ||
| 32 | MFP_PIN_GPIO7, | ||
| 33 | MFP_PIN_GPIO8, | ||
| 34 | MFP_PIN_GPIO9, | ||
| 35 | MFP_PIN_GPIO10, | ||
| 36 | MFP_PIN_GPIO11, | ||
| 37 | MFP_PIN_GPIO12, | ||
| 38 | MFP_PIN_GPIO13, | ||
| 39 | MFP_PIN_GPIO14, | ||
| 40 | MFP_PIN_GPIO15, | ||
| 41 | MFP_PIN_GPIO16, | ||
| 42 | MFP_PIN_GPIO17, | ||
| 43 | MFP_PIN_GPIO18, | ||
| 44 | MFP_PIN_GPIO19, | ||
| 45 | MFP_PIN_GPIO20, | ||
| 46 | MFP_PIN_GPIO21, | ||
| 47 | MFP_PIN_GPIO22, | ||
| 48 | MFP_PIN_GPIO23, | ||
| 49 | MFP_PIN_GPIO24, | ||
| 50 | MFP_PIN_GPIO25, | ||
| 51 | MFP_PIN_GPIO26, | ||
| 52 | MFP_PIN_GPIO27, | ||
| 53 | MFP_PIN_GPIO28, | ||
| 54 | MFP_PIN_GPIO29, | ||
| 55 | MFP_PIN_GPIO30, | ||
| 56 | MFP_PIN_GPIO31, | ||
| 57 | MFP_PIN_GPIO32, | ||
| 58 | MFP_PIN_GPIO33, | ||
| 59 | MFP_PIN_GPIO34, | ||
| 60 | MFP_PIN_GPIO35, | ||
| 61 | MFP_PIN_GPIO36, | ||
| 62 | MFP_PIN_GPIO37, | ||
| 63 | MFP_PIN_GPIO38, | ||
| 64 | MFP_PIN_GPIO39, | ||
| 65 | MFP_PIN_GPIO40, | ||
| 66 | MFP_PIN_GPIO41, | ||
| 67 | MFP_PIN_GPIO42, | ||
| 68 | MFP_PIN_GPIO43, | ||
| 69 | MFP_PIN_GPIO44, | ||
| 70 | MFP_PIN_GPIO45, | ||
| 71 | MFP_PIN_GPIO46, | ||
| 72 | MFP_PIN_GPIO47, | ||
| 73 | MFP_PIN_GPIO48, | ||
| 74 | MFP_PIN_GPIO49, | ||
| 75 | MFP_PIN_GPIO50, | ||
| 76 | MFP_PIN_GPIO51, | ||
| 77 | MFP_PIN_GPIO52, | ||
| 78 | MFP_PIN_GPIO53, | ||
| 79 | MFP_PIN_GPIO54, | ||
| 80 | MFP_PIN_GPIO55, | ||
| 81 | MFP_PIN_GPIO56, | ||
| 82 | MFP_PIN_GPIO57, | ||
| 83 | MFP_PIN_GPIO58, | ||
| 84 | MFP_PIN_GPIO59, | ||
| 85 | MFP_PIN_GPIO60, | ||
| 86 | MFP_PIN_GPIO61, | ||
| 87 | MFP_PIN_GPIO62, | ||
| 88 | MFP_PIN_GPIO63, | ||
| 89 | MFP_PIN_GPIO64, | ||
| 90 | MFP_PIN_GPIO65, | ||
| 91 | MFP_PIN_GPIO66, | ||
| 92 | MFP_PIN_GPIO67, | ||
| 93 | MFP_PIN_GPIO68, | ||
| 94 | MFP_PIN_GPIO69, | ||
| 95 | MFP_PIN_GPIO70, | ||
| 96 | MFP_PIN_GPIO71, | ||
| 97 | MFP_PIN_GPIO72, | ||
| 98 | MFP_PIN_GPIO73, | ||
| 99 | MFP_PIN_GPIO74, | ||
| 100 | MFP_PIN_GPIO75, | ||
| 101 | MFP_PIN_GPIO76, | ||
| 102 | MFP_PIN_GPIO77, | ||
| 103 | MFP_PIN_GPIO78, | ||
| 104 | MFP_PIN_GPIO79, | ||
| 105 | MFP_PIN_GPIO80, | ||
| 106 | MFP_PIN_GPIO81, | ||
| 107 | MFP_PIN_GPIO82, | ||
| 108 | MFP_PIN_GPIO83, | ||
| 109 | MFP_PIN_GPIO84, | ||
| 110 | MFP_PIN_GPIO85, | ||
| 111 | MFP_PIN_GPIO86, | ||
| 112 | MFP_PIN_GPIO87, | ||
| 113 | MFP_PIN_GPIO88, | ||
| 114 | MFP_PIN_GPIO89, | ||
| 115 | MFP_PIN_GPIO90, | ||
| 116 | MFP_PIN_GPIO91, | ||
| 117 | MFP_PIN_GPIO92, | ||
| 118 | MFP_PIN_GPIO93, | ||
| 119 | MFP_PIN_GPIO94, | ||
| 120 | MFP_PIN_GPIO95, | ||
| 121 | MFP_PIN_GPIO96, | ||
| 122 | MFP_PIN_GPIO97, | ||
| 123 | MFP_PIN_GPIO98, | ||
| 124 | MFP_PIN_GPIO99, | ||
| 125 | MFP_PIN_GPIO100, | ||
| 126 | MFP_PIN_GPIO101, | ||
| 127 | MFP_PIN_GPIO102, | ||
| 128 | MFP_PIN_GPIO103, | ||
| 129 | MFP_PIN_GPIO104, | ||
| 130 | MFP_PIN_GPIO105, | ||
| 131 | MFP_PIN_GPIO106, | ||
| 132 | MFP_PIN_GPIO107, | ||
| 133 | MFP_PIN_GPIO108, | ||
| 134 | MFP_PIN_GPIO109, | ||
| 135 | MFP_PIN_GPIO110, | ||
| 136 | MFP_PIN_GPIO111, | ||
| 137 | MFP_PIN_GPIO112, | ||
| 138 | MFP_PIN_GPIO113, | ||
| 139 | MFP_PIN_GPIO114, | ||
| 140 | MFP_PIN_GPIO115, | ||
| 141 | MFP_PIN_GPIO116, | ||
| 142 | MFP_PIN_GPIO117, | ||
| 143 | MFP_PIN_GPIO118, | ||
| 144 | MFP_PIN_GPIO119, | ||
| 145 | MFP_PIN_GPIO120, | ||
| 146 | MFP_PIN_GPIO121, | ||
| 147 | MFP_PIN_GPIO122, | ||
| 148 | MFP_PIN_GPIO123, | ||
| 149 | MFP_PIN_GPIO124, | ||
| 150 | MFP_PIN_GPIO125, | ||
| 151 | MFP_PIN_GPIO126, | ||
| 152 | MFP_PIN_GPIO127, | ||
| 153 | MFP_PIN_GPIO0_2, | ||
| 154 | MFP_PIN_GPIO1_2, | ||
| 155 | MFP_PIN_GPIO2_2, | ||
| 156 | MFP_PIN_GPIO3_2, | ||
| 157 | MFP_PIN_GPIO4_2, | ||
| 158 | MFP_PIN_GPIO5_2, | ||
| 159 | MFP_PIN_GPIO6_2, | ||
| 160 | MFP_PIN_GPIO7_2, | ||
| 161 | MFP_PIN_GPIO8_2, | ||
| 162 | MFP_PIN_GPIO9_2, | ||
| 163 | MFP_PIN_GPIO10_2, | ||
| 164 | MFP_PIN_GPIO11_2, | ||
| 165 | MFP_PIN_GPIO12_2, | ||
| 166 | MFP_PIN_GPIO13_2, | ||
| 167 | MFP_PIN_GPIO14_2, | ||
| 168 | MFP_PIN_GPIO15_2, | ||
| 169 | MFP_PIN_GPIO16_2, | ||
| 170 | MFP_PIN_GPIO17_2, | ||
| 171 | |||
| 172 | MFP_PIN_ULPI_STP, | ||
| 173 | MFP_PIN_ULPI_NXT, | ||
| 174 | MFP_PIN_ULPI_DIR, | ||
| 175 | |||
| 176 | MFP_PIN_nXCVREN, | ||
| 177 | MFP_PIN_DF_CLE_nOE, | ||
| 178 | MFP_PIN_DF_nADV1_ALE, | ||
| 179 | MFP_PIN_DF_SCLK_E, | ||
| 180 | MFP_PIN_DF_SCLK_S, | ||
| 181 | MFP_PIN_nBE0, | ||
| 182 | MFP_PIN_nBE1, | ||
| 183 | MFP_PIN_DF_nADV2_ALE, | ||
| 184 | MFP_PIN_DF_INT_RnB, | ||
| 185 | MFP_PIN_DF_nCS0, | ||
| 186 | MFP_PIN_DF_nCS1, | ||
| 187 | MFP_PIN_nLUA, | ||
| 188 | MFP_PIN_nLLA, | ||
| 189 | MFP_PIN_DF_nWE, | ||
| 190 | MFP_PIN_DF_ALE_nWE, | ||
| 191 | MFP_PIN_DF_nRE_nOE, | ||
| 192 | MFP_PIN_DF_ADDR0, | ||
| 193 | MFP_PIN_DF_ADDR1, | ||
| 194 | MFP_PIN_DF_ADDR2, | ||
| 195 | MFP_PIN_DF_ADDR3, | ||
| 196 | MFP_PIN_DF_IO0, | ||
| 197 | MFP_PIN_DF_IO1, | ||
| 198 | MFP_PIN_DF_IO2, | ||
| 199 | MFP_PIN_DF_IO3, | ||
| 200 | MFP_PIN_DF_IO4, | ||
| 201 | MFP_PIN_DF_IO5, | ||
| 202 | MFP_PIN_DF_IO6, | ||
| 203 | MFP_PIN_DF_IO7, | ||
| 204 | MFP_PIN_DF_IO8, | ||
| 205 | MFP_PIN_DF_IO9, | ||
| 206 | MFP_PIN_DF_IO10, | ||
| 207 | MFP_PIN_DF_IO11, | ||
| 208 | MFP_PIN_DF_IO12, | ||
| 209 | MFP_PIN_DF_IO13, | ||
| 210 | MFP_PIN_DF_IO14, | ||
| 211 | MFP_PIN_DF_IO15, | ||
| 212 | |||
| 213 | /* additional pins on PXA930 */ | ||
| 214 | MFP_PIN_GSIM_UIO, | ||
| 215 | MFP_PIN_GSIM_UCLK, | ||
| 216 | MFP_PIN_GSIM_UDET, | ||
| 217 | MFP_PIN_GSIM_nURST, | ||
| 218 | MFP_PIN_PMIC_INT, | ||
| 219 | MFP_PIN_RDY, | ||
| 220 | |||
| 221 | MFP_PIN_MAX, | ||
| 222 | }; | ||
| 223 | |||
| 224 | /* | ||
| 225 | * a possible MFP configuration is represented by a 32-bit integer | ||
| 226 | * | ||
| 227 | * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) | ||
| 228 | * bit 10..12 - Alternate Function Selection | ||
| 229 | * bit 13..15 - Drive Strength | ||
| 230 | * bit 16..18 - Low Power Mode State | ||
| 231 | * bit 19..20 - Low Power Mode Edge Detection | ||
| 232 | * bit 21..22 - Run Mode Pull State | ||
| 233 | * | ||
| 234 | * to facilitate the definition, the following macros are provided | ||
| 235 | * | ||
| 236 | * MFP_CFG_DEFAULT - default MFP configuration value, with | ||
| 237 | * alternate function = 0, | ||
| 238 | * drive strength = fast 3mA (MFP_DS03X) | ||
| 239 | * low power mode = default | ||
| 240 | * edge detection = none | ||
| 241 | * | ||
| 242 | * MFP_CFG - default MFPR value with alternate function | ||
| 243 | * MFP_CFG_DRV - default MFPR value with alternate function and | ||
| 244 | * pin drive strength | ||
| 245 | * MFP_CFG_LPM - default MFPR value with alternate function and | ||
| 246 | * low power mode | ||
| 247 | * MFP_CFG_X - default MFPR value with alternate function, | ||
| 248 | * pin drive strength and low power mode | ||
| 249 | */ | ||
| 250 | |||
| 251 | typedef unsigned long mfp_cfg_t; | ||
| 252 | |||
| 253 | #define MFP_PIN(x) ((x) & 0x3ff) | ||
| 254 | |||
| 255 | #define MFP_AF0 (0x0 << 10) | ||
| 256 | #define MFP_AF1 (0x1 << 10) | ||
| 257 | #define MFP_AF2 (0x2 << 10) | ||
| 258 | #define MFP_AF3 (0x3 << 10) | ||
| 259 | #define MFP_AF4 (0x4 << 10) | ||
| 260 | #define MFP_AF5 (0x5 << 10) | ||
| 261 | #define MFP_AF6 (0x6 << 10) | ||
| 262 | #define MFP_AF7 (0x7 << 10) | ||
| 263 | #define MFP_AF_MASK (0x7 << 10) | ||
| 264 | #define MFP_AF(x) (((x) >> 10) & 0x7) | ||
| 265 | |||
| 266 | #define MFP_DS01X (0x0 << 13) | ||
| 267 | #define MFP_DS02X (0x1 << 13) | ||
| 268 | #define MFP_DS03X (0x2 << 13) | ||
| 269 | #define MFP_DS04X (0x3 << 13) | ||
| 270 | #define MFP_DS06X (0x4 << 13) | ||
| 271 | #define MFP_DS08X (0x5 << 13) | ||
| 272 | #define MFP_DS10X (0x6 << 13) | ||
| 273 | #define MFP_DS13X (0x7 << 13) | ||
| 274 | #define MFP_DS_MASK (0x7 << 13) | ||
| 275 | #define MFP_DS(x) (((x) >> 13) & 0x7) | ||
| 276 | |||
| 277 | #define MFP_LPM_INPUT (0x0 << 16) | ||
| 278 | #define MFP_LPM_DRIVE_LOW (0x1 << 16) | ||
| 279 | #define MFP_LPM_DRIVE_HIGH (0x2 << 16) | ||
| 280 | #define MFP_LPM_PULL_LOW (0x3 << 16) | ||
| 281 | #define MFP_LPM_PULL_HIGH (0x4 << 16) | ||
| 282 | #define MFP_LPM_FLOAT (0x5 << 16) | ||
| 283 | #define MFP_LPM_STATE_MASK (0x7 << 16) | ||
| 284 | #define MFP_LPM_STATE(x) (((x) >> 16) & 0x7) | ||
| 285 | |||
| 286 | #define MFP_LPM_EDGE_NONE (0x0 << 19) | ||
| 287 | #define MFP_LPM_EDGE_RISE (0x1 << 19) | ||
| 288 | #define MFP_LPM_EDGE_FALL (0x2 << 19) | ||
| 289 | #define MFP_LPM_EDGE_BOTH (0x3 << 19) | ||
| 290 | #define MFP_LPM_EDGE_MASK (0x3 << 19) | ||
| 291 | #define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3) | ||
| 292 | |||
| 293 | #define MFP_PULL_NONE (0x0 << 21) | ||
| 294 | #define MFP_PULL_LOW (0x1 << 21) | ||
| 295 | #define MFP_PULL_HIGH (0x2 << 21) | ||
| 296 | #define MFP_PULL_BOTH (0x3 << 21) | ||
| 297 | #define MFP_PULL_MASK (0x3 << 21) | ||
| 298 | #define MFP_PULL(x) (((x) >> 21) & 0x3) | ||
| 299 | |||
| 300 | #define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\ | ||
| 301 | MFP_LPM_EDGE_NONE | MFP_PULL_NONE) | ||
| 302 | |||
| 303 | #define MFP_CFG(pin, af) \ | ||
| 304 | ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\ | ||
| 305 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af)) | ||
| 306 | |||
| 307 | #define MFP_CFG_DRV(pin, af, drv) \ | ||
| 308 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\ | ||
| 309 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv)) | ||
| 310 | |||
| 311 | #define MFP_CFG_LPM(pin, af, lpm) \ | ||
| 312 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\ | ||
| 313 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm)) | ||
| 314 | |||
| 315 | #define MFP_CFG_X(pin, af, drv, lpm) \ | ||
| 316 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ | ||
| 317 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) | ||
| 318 | |||
| 319 | #endif /* __ASM_ARCH_MFP_H */ | ||
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h deleted file mode 100644 index 6d1304c9270f..000000000000 --- a/include/asm-arm/arch-pxa/mmc.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | #ifndef ASMARM_ARCH_MMC_H | ||
| 2 | #define ASMARM_ARCH_MMC_H | ||
| 3 | |||
| 4 | #include <linux/mmc/host.h> | ||
| 5 | #include <linux/interrupt.h> | ||
| 6 | |||
| 7 | struct device; | ||
| 8 | struct mmc_host; | ||
| 9 | |||
| 10 | struct pxamci_platform_data { | ||
| 11 | unsigned int ocr_mask; /* available voltages */ | ||
| 12 | unsigned long detect_delay; /* delay in jiffies before detecting cards after interrupt */ | ||
| 13 | int (*init)(struct device *, irq_handler_t , void *); | ||
| 14 | int (*get_ro)(struct device *); | ||
| 15 | void (*setpower)(struct device *, unsigned int); | ||
| 16 | void (*exit)(struct device *, void *); | ||
| 17 | }; | ||
| 18 | |||
| 19 | extern void pxa_set_mci_info(struct pxamci_platform_data *info); | ||
| 20 | extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info); | ||
| 21 | extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info); | ||
| 22 | |||
| 23 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/mtd-xip.h b/include/asm-arm/arch-pxa/mtd-xip.h deleted file mode 100644 index 8704dbceb432..000000000000 --- a/include/asm-arm/arch-pxa/mtd-xip.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * MTD primitives for XIP support. Architecture specific functions | ||
| 3 | * | ||
| 4 | * Do not include this file directly. It's included from linux/mtd/xip.h | ||
| 5 | * | ||
| 6 | * Author: Nicolas Pitre | ||
| 7 | * Created: Nov 2, 2004 | ||
| 8 | * Copyright: (C) 2004 MontaVista Software, Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $ | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ARCH_PXA_MTD_XIP_H__ | ||
| 18 | #define __ARCH_PXA_MTD_XIP_H__ | ||
| 19 | |||
| 20 | #include <asm/arch/pxa-regs.h> | ||
| 21 | |||
| 22 | #define xip_irqpending() (ICIP & ICMR) | ||
| 23 | |||
| 24 | /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ | ||
| 25 | #define xip_currtime() (OSCR) | ||
| 26 | #define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * xip_cpu_idle() is used when waiting for a delay equal or larger than | ||
| 30 | * the system timer tick period. This should put the CPU into idle mode | ||
| 31 | * to save power and to be woken up only when some interrupts are pending. | ||
| 32 | * As above, this should not rely upon standard kernel code. | ||
| 33 | */ | ||
| 34 | |||
| 35 | #define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1)) | ||
| 36 | |||
| 37 | #endif /* __ARCH_PXA_MTD_XIP_H__ */ | ||
diff --git a/include/asm-arm/arch-pxa/ohci.h b/include/asm-arm/arch-pxa/ohci.h deleted file mode 100644 index e848a47128cd..000000000000 --- a/include/asm-arm/arch-pxa/ohci.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | #ifndef ASMARM_ARCH_OHCI_H | ||
| 2 | #define ASMARM_ARCH_OHCI_H | ||
| 3 | |||
| 4 | struct device; | ||
| 5 | |||
| 6 | struct pxaohci_platform_data { | ||
| 7 | int (*init)(struct device *); | ||
| 8 | void (*exit)(struct device *); | ||
| 9 | |||
| 10 | int port_mode; | ||
| 11 | #define PMM_NPS_MODE 1 | ||
| 12 | #define PMM_GLOBAL_MODE 2 | ||
| 13 | #define PMM_PERPORT_MODE 3 | ||
| 14 | |||
| 15 | int power_budget; | ||
| 16 | }; | ||
| 17 | |||
| 18 | extern void pxa_set_ohci_info(struct pxaohci_platform_data *info); | ||
| 19 | |||
| 20 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/palmtx.h b/include/asm-arm/arch-pxa/palmtx.h deleted file mode 100644 index 1e8bccbda510..000000000000 --- a/include/asm-arm/arch-pxa/palmtx.h +++ /dev/null | |||
| @@ -1,106 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * GPIOs and interrupts for Palm T|X Handheld Computer | ||
| 3 | * | ||
| 4 | * Based on palmld-gpio.h by Alex Osborne | ||
| 5 | * | ||
| 6 | * Authors: Marek Vasut <marek.vasut@gmail.com> | ||
| 7 | * Cristiano P. <cristianop@users.sourceforge.net> | ||
| 8 | * Jan Herman <2hp@seznam.cz> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef _INCLUDE_PALMTX_H_ | ||
| 17 | #define _INCLUDE_PALMTX_H_ | ||
| 18 | |||
| 19 | /** HERE ARE GPIOs **/ | ||
| 20 | |||
| 21 | /* GPIOs */ | ||
| 22 | #define GPIO_NR_PALMTX_GPIO_RESET 1 | ||
| 23 | |||
| 24 | #define GPIO_NR_PALMTX_POWER_DETECT 12 /* 90 */ | ||
| 25 | #define GPIO_NR_PALMTX_HOTSYNC_BUTTON_N 10 | ||
| 26 | #define GPIO_NR_PALMTX_EARPHONE_DETECT 107 | ||
| 27 | |||
| 28 | /* SD/MMC */ | ||
| 29 | #define GPIO_NR_PALMTX_SD_DETECT_N 14 | ||
| 30 | #define GPIO_NR_PALMTX_SD_POWER 114 /* probably */ | ||
| 31 | #define GPIO_NR_PALMTX_SD_READONLY 115 /* probably */ | ||
| 32 | |||
| 33 | /* TOUCHSCREEN */ | ||
| 34 | #define GPIO_NR_PALMTX_WM9712_IRQ 27 | ||
| 35 | |||
| 36 | /* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ | ||
| 37 | #define GPIO_NR_PALMTX_IR_DISABLE 40 | ||
| 38 | |||
| 39 | /* USB */ | ||
| 40 | #define GPIO_NR_PALMTX_USB_DETECT_N 13 | ||
| 41 | #define GPIO_NR_PALMTX_USB_POWER 95 | ||
| 42 | #define GPIO_NR_PALMTX_USB_PULLUP 93 | ||
| 43 | |||
| 44 | /* LCD/BACKLIGHT */ | ||
| 45 | #define GPIO_NR_PALMTX_BL_POWER 84 | ||
| 46 | #define GPIO_NR_PALMTX_LCD_POWER 96 | ||
| 47 | |||
| 48 | /* LCD BORDER */ | ||
| 49 | #define GPIO_NR_PALMTX_BORDER_SWITCH 98 | ||
| 50 | #define GPIO_NR_PALMTX_BORDER_SELECT 22 | ||
| 51 | |||
| 52 | /* BLUETOOTH */ | ||
| 53 | #define GPIO_NR_PALMTX_BT_POWER 17 | ||
| 54 | #define GPIO_NR_PALMTX_BT_RESET 83 | ||
| 55 | |||
| 56 | /* PCMCIA (WiFi) */ | ||
| 57 | #define GPIO_NR_PALMTX_PCMCIA_POWER1 94 | ||
| 58 | #define GPIO_NR_PALMTX_PCMCIA_POWER2 108 | ||
| 59 | #define GPIO_NR_PALMTX_PCMCIA_RESET 79 | ||
| 60 | #define GPIO_NR_PALMTX_PCMCIA_READY 116 | ||
| 61 | |||
| 62 | /* NAND Flash ... this GPIO may be incorrect! */ | ||
| 63 | #define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79 | ||
| 64 | |||
| 65 | /* INTERRUPTS */ | ||
| 66 | #define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N) | ||
| 67 | #define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ) | ||
| 68 | #define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT) | ||
| 69 | #define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET) | ||
| 70 | |||
| 71 | /** HERE ARE INIT VALUES **/ | ||
| 72 | |||
| 73 | /* Various addresses */ | ||
| 74 | #define PALMTX_PCMCIA_PHYS 0x28000000 | ||
| 75 | #define PALMTX_PCMCIA_VIRT 0xf0000000 | ||
| 76 | #define PALMTX_PCMCIA_SIZE 0x100000 | ||
| 77 | |||
| 78 | #define PALMTX_PHYS_RAM_START 0xa0000000 | ||
| 79 | #define PALMTX_PHYS_IO_START 0x40000000 | ||
| 80 | |||
| 81 | #define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */ | ||
| 82 | #define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */ | ||
| 83 | |||
| 84 | /* TOUCHSCREEN */ | ||
| 85 | #define AC97_LINK_FRAME 21 | ||
| 86 | |||
| 87 | |||
| 88 | /* BATTERY */ | ||
| 89 | #define PALMTX_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ | ||
| 90 | #define PALMTX_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ | ||
| 91 | #define PALMTX_BAT_MAX_CURRENT 0 /* unknokn */ | ||
| 92 | #define PALMTX_BAT_MIN_CURRENT 0 /* unknown */ | ||
| 93 | #define PALMTX_BAT_MAX_CHARGE 1 /* unknown */ | ||
| 94 | #define PALMTX_BAT_MIN_CHARGE 1 /* unknown */ | ||
| 95 | #define PALMTX_MAX_LIFE_MINS 360 /* on-life in minutes */ | ||
| 96 | |||
| 97 | #define PALMTX_BAT_MEASURE_DELAY (HZ * 1) | ||
| 98 | |||
| 99 | /* BACKLIGHT */ | ||
| 100 | #define PALMTX_MAX_INTENSITY 0xFE | ||
| 101 | #define PALMTX_DEFAULT_INTENSITY 0x7E | ||
| 102 | #define PALMTX_LIMIT_MASK 0x7F | ||
| 103 | #define PALMTX_PRESCALER 0x3F | ||
| 104 | #define PALMTX_PERIOD_NS 3500 | ||
| 105 | |||
| 106 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/pcm027.h b/include/asm-arm/arch-pxa/pcm027.h deleted file mode 100644 index 7beae1472c3e..000000000000 --- a/include/asm-arm/arch-pxa/pcm027.h +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/pcm027.h | ||
| 3 | * | ||
| 4 | * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de> | ||
| 5 | * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Definitions of CPU card resources only | ||
| 24 | */ | ||
| 25 | |||
| 26 | /* I2C RTC */ | ||
| 27 | #define PCM027_RTC_IRQ_GPIO 0 | ||
| 28 | #define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) | ||
| 29 | #define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING | ||
| 30 | #define ADR_PCM027_RTC 0x51 /* I2C address */ | ||
| 31 | |||
| 32 | /* I2C EEPROM */ | ||
| 33 | #define ADR_PCM027_EEPROM 0x54 /* I2C address */ | ||
| 34 | |||
| 35 | /* Ethernet chip (SMSC91C111) */ | ||
| 36 | #define PCM027_ETH_IRQ_GPIO 52 | ||
| 37 | #define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO) | ||
| 38 | #define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING | ||
| 39 | #define PCM027_ETH_PHYS PXA_CS5_PHYS | ||
| 40 | #define PCM027_ETH_SIZE (1*1024*1024) | ||
| 41 | |||
| 42 | /* CAN controller SJA1000 (unsupported yet) */ | ||
| 43 | #define PCM027_CAN_IRQ_GPIO 114 | ||
| 44 | #define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO) | ||
| 45 | #define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING | ||
| 46 | #define PCM027_CAN_PHYS 0x22000000 | ||
| 47 | #define PCM027_CAN_SIZE 0x100 | ||
| 48 | |||
| 49 | /* SPI GPIO expander (unsupported yet) */ | ||
| 50 | #define PCM027_EGPIO_IRQ_GPIO 27 | ||
| 51 | #define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO) | ||
| 52 | #define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING | ||
| 53 | #define PCM027_EGPIO_CS 24 | ||
| 54 | /* | ||
| 55 | * TODO: Switch this pin from dedicated usage to GPIO if | ||
| 56 | * more than the MAX7301 device is connected to this SPI bus | ||
| 57 | */ | ||
| 58 | #define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD | ||
| 59 | |||
| 60 | /* Flash memory */ | ||
| 61 | #define PCM027_FLASH_PHYS 0x00000000 | ||
| 62 | #define PCM027_FLASH_SIZE 0x02000000 | ||
| 63 | |||
| 64 | /* onboard LEDs connected to GPIO */ | ||
| 65 | #define PCM027_LED_CPU 90 | ||
| 66 | #define PCM027_LED_HEARD_BEAT 91 | ||
| 67 | |||
| 68 | /* | ||
| 69 | * This CPU module needs a baseboard to work. After basic initializing | ||
| 70 | * its own devices, it calls baseboard's init function. | ||
| 71 | * TODO: Add your own basebaord init function and call it from | ||
| 72 | * inside pcm027_init(). This example here is for the developmen board. | ||
| 73 | * Refer pcm990-baseboard.c | ||
| 74 | */ | ||
| 75 | extern void pcm990_baseboard_init(void); | ||
diff --git a/include/asm-arm/arch-pxa/pcm990_baseboard.h b/include/asm-arm/arch-pxa/pcm990_baseboard.h deleted file mode 100644 index 2e2013179063..000000000000 --- a/include/asm-arm/arch-pxa/pcm990_baseboard.h +++ /dev/null | |||
| @@ -1,275 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-pxa/pcm990_baseboard.h | ||
| 3 | * | ||
| 4 | * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de> | ||
| 5 | * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <asm/arch/pcm027.h> | ||
| 23 | |||
| 24 | /* | ||
| 25 | * definitions relevant only when the PCM-990 | ||
| 26 | * development base board is in use | ||
| 27 | */ | ||
| 28 | |||
| 29 | /* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ | ||
| 30 | #define PCM990_CTRL_INT_IRQ_GPIO 9 | ||
| 31 | #define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO) | ||
| 32 | #define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING | ||
| 33 | #define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ | ||
| 34 | #define PCM990_CTRL_BASE 0xea000000 | ||
| 35 | #define PCM990_CTRL_SIZE (1*1024*1024) | ||
| 36 | |||
| 37 | #define PCM990_CTRL_PWR_IRQ_GPIO 14 | ||
| 38 | #define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO) | ||
| 39 | #define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING | ||
| 40 | |||
| 41 | /* visible CPLD (U7) registers */ | ||
| 42 | #define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */ | ||
| 43 | #define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */ | ||
| 44 | #define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */ | ||
| 45 | #define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */ | ||
| 46 | |||
| 47 | #define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */ | ||
| 48 | #define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */ | ||
| 49 | #define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */ | ||
| 50 | #define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */ | ||
| 51 | |||
| 52 | #define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */ | ||
| 53 | #define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */ | ||
| 54 | #define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */ | ||
| 55 | #define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */ | ||
| 56 | |||
| 57 | #define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */ | ||
| 58 | #define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ | ||
| 59 | #define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */ | ||
| 60 | #define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ | ||
| 61 | #define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ | ||
| 62 | |||
| 63 | #define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */ | ||
| 64 | #define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */ | ||
| 65 | |||
| 66 | #define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */ | ||
| 67 | #define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */ | ||
| 68 | #define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */ | ||
| 69 | #define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ | ||
| 70 | #define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ | ||
| 71 | |||
| 72 | #define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */ | ||
| 73 | #define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */ | ||
| 74 | #define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */ | ||
| 75 | #define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */ | ||
| 76 | #define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */ | ||
| 77 | |||
| 78 | #define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */ | ||
| 79 | #define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */ | ||
| 80 | #define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */ | ||
| 81 | #define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */ | ||
| 82 | #define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */ | ||
| 83 | |||
| 84 | #define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */ | ||
| 85 | #define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */ | ||
| 86 | #define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */ | ||
| 87 | #define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */ | ||
| 88 | #define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */ | ||
| 89 | |||
| 90 | #define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */ | ||
| 91 | #define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */ | ||
| 92 | #define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */ | ||
| 93 | #define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */ | ||
| 94 | |||
| 95 | #define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */ | ||
| 96 | #define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */ | ||
| 97 | #define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */ | ||
| 98 | |||
| 99 | #define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */ | ||
| 100 | #define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */ | ||
| 101 | #define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */ | ||
| 102 | #define PCM990_CTRL_ACPRES 0x0004 /* DC Present */ | ||
| 103 | #define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */ | ||
| 104 | |||
| 105 | #define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE) | ||
| 106 | #define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS) | ||
| 107 | |||
| 108 | #ifndef __ASSEMBLY__ | ||
| 109 | # define __PCM990_CTRL_REG(x) \ | ||
| 110 | (*((volatile unsigned char *)PCM990_CTRL_P2V(x))) | ||
| 111 | #else | ||
| 112 | # define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x) | ||
| 113 | #endif | ||
| 114 | |||
| 115 | #define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7) | ||
| 116 | #define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6) | ||
| 117 | #define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0) | ||
| 118 | #define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1) | ||
| 119 | #define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2) | ||
| 120 | #define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) | ||
| 121 | #define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4) | ||
| 122 | #define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) | ||
| 123 | #define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6) | ||
| 124 | #define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7) | ||
| 125 | #define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8) | ||
| 126 | #define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9) | ||
| 127 | #define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10) | ||
| 128 | #define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11) | ||
| 129 | |||
| 130 | |||
| 131 | /* | ||
| 132 | * IDE | ||
| 133 | */ | ||
| 134 | #define PCM990_IDE_IRQ_GPIO 13 | ||
| 135 | #define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO) | ||
| 136 | #define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING | ||
| 137 | #define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ | ||
| 138 | #define PCM990_IDE_PLD_BASE 0xee000000 | ||
| 139 | #define PCM990_IDE_PLD_SIZE (1*1024*1024) | ||
| 140 | |||
| 141 | /* visible CPLD (U6) registers */ | ||
| 142 | #define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */ | ||
| 143 | #define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */ | ||
| 144 | #define PCM990_IDE_STBY 0x0008 /* R System StandBy */ | ||
| 145 | |||
| 146 | #define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */ | ||
| 147 | #define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */ | ||
| 148 | #define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */ | ||
| 149 | #define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */ | ||
| 150 | |||
| 151 | #define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */ | ||
| 152 | #define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */ | ||
| 153 | #define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */ | ||
| 154 | #define PCM990_IDE_RDY 0x0008 /* RDY */ | ||
| 155 | |||
| 156 | #define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */ | ||
| 157 | #define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */ | ||
| 158 | #define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */ | ||
| 159 | #define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */ | ||
| 160 | |||
| 161 | #define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */ | ||
| 162 | #define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */ | ||
| 163 | #define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */ | ||
| 164 | #define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */ | ||
| 165 | |||
| 166 | #define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE) | ||
| 167 | #define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS) | ||
| 168 | |||
| 169 | #ifndef __ASSEMBLY__ | ||
| 170 | # define __PCM990_IDE_PLD_REG(x) \ | ||
| 171 | (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x))) | ||
| 172 | #else | ||
| 173 | # define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x) | ||
| 174 | #endif | ||
| 175 | |||
| 176 | #define PCM990_IDE0 \ | ||
| 177 | __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0) | ||
| 178 | #define PCM990_IDE1 \ | ||
| 179 | __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1) | ||
| 180 | #define PCM990_IDE2 \ | ||
| 181 | __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2) | ||
| 182 | #define PCM990_IDE3 \ | ||
| 183 | __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3) | ||
| 184 | #define PCM990_IDE4 \ | ||
| 185 | __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4) | ||
| 186 | |||
| 187 | /* | ||
| 188 | * Compact Flash | ||
| 189 | */ | ||
| 190 | #define PCM990_CF_IRQ_GPIO 11 | ||
| 191 | #define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO) | ||
| 192 | #define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING | ||
| 193 | |||
| 194 | #define PCM990_CF_CD_GPIO 12 | ||
| 195 | #define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO) | ||
| 196 | #define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING | ||
| 197 | |||
| 198 | #define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ | ||
| 199 | #define PCM990_CF_PLD_BASE 0xef000000 | ||
| 200 | #define PCM990_CF_PLD_SIZE (1*1024*1024) | ||
| 201 | #define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE) | ||
| 202 | #define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS) | ||
| 203 | |||
| 204 | /* visible CPLD (U6) registers */ | ||
| 205 | #define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */ | ||
| 206 | #define PCM990_CF_REG0_LED 0x0001 /* RW LED on */ | ||
| 207 | #define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */ | ||
| 208 | #define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */ | ||
| 209 | #define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */ | ||
| 210 | |||
| 211 | #define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */ | ||
| 212 | #define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */ | ||
| 213 | #define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */ | ||
| 214 | |||
| 215 | #define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */ | ||
| 216 | #define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */ | ||
| 217 | #define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */ | ||
| 218 | #define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */ | ||
| 219 | |||
| 220 | #define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */ | ||
| 221 | #define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */ | ||
| 222 | #define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */ | ||
| 223 | #define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */ | ||
| 224 | #define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */ | ||
| 225 | |||
| 226 | #define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */ | ||
| 227 | #define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */ | ||
| 228 | #define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */ | ||
| 229 | #define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */ | ||
| 230 | #define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */ | ||
| 231 | |||
| 232 | #define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */ | ||
| 233 | #define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */ | ||
| 234 | #define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */ | ||
| 235 | #define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */ | ||
| 236 | #define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */ | ||
| 237 | |||
| 238 | #define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */ | ||
| 239 | #define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ | ||
| 240 | #define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ | ||
| 241 | |||
| 242 | #ifndef __ASSEMBLY__ | ||
| 243 | # define __PCM990_CF_PLD_REG(x) \ | ||
| 244 | (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x))) | ||
| 245 | #else | ||
| 246 | # define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x) | ||
| 247 | #endif | ||
| 248 | |||
| 249 | #define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0) | ||
| 250 | #define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1) | ||
| 251 | #define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2) | ||
| 252 | #define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3) | ||
| 253 | #define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4) | ||
| 254 | #define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5) | ||
| 255 | #define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6) | ||
| 256 | |||
| 257 | /* | ||
| 258 | * Wolfson AC97 Touch | ||
| 259 | */ | ||
| 260 | #define PCM990_AC97_IRQ_GPIO 10 | ||
| 261 | #define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO) | ||
| 262 | #define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING | ||
| 263 | |||
| 264 | /* | ||
| 265 | * MMC phyCORE | ||
| 266 | */ | ||
| 267 | #define PCM990_MMC0_IRQ_GPIO 9 | ||
| 268 | #define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO) | ||
| 269 | #define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING | ||
| 270 | |||
| 271 | /* | ||
| 272 | * USB phyCore | ||
| 273 | */ | ||
| 274 | #define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN) | ||
| 275 | #define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT) | ||
diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h deleted file mode 100644 index 261e5bc958db..000000000000 --- a/include/asm-arm/arch-pxa/pm.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2005 Richard Purdie | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/suspend.h> | ||
| 11 | |||
| 12 | struct pxa_cpu_pm_fns { | ||
| 13 | int save_count; | ||
| 14 | void (*save)(unsigned long *); | ||
| 15 | void (*restore)(unsigned long *); | ||
| 16 | int (*valid)(suspend_state_t state); | ||
| 17 | void (*enter)(suspend_state_t state); | ||
| 18 | }; | ||
| 19 | |||
| 20 | extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; | ||
| 21 | |||
| 22 | /* sleep.S */ | ||
| 23 | extern void pxa25x_cpu_suspend(unsigned int); | ||
| 24 | extern void pxa27x_cpu_suspend(unsigned int); | ||
| 25 | extern void pxa_cpu_resume(void); | ||
| 26 | |||
| 27 | extern int pxa_pm_enter(suspend_state_t state); | ||
diff --git a/include/asm-arm/arch-pxa/poodle.h b/include/asm-arm/arch-pxa/poodle.h deleted file mode 100644 index 4d6a40315764..000000000000 --- a/include/asm-arm/arch-pxa/poodle.h +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/poodle.h | ||
| 3 | * | ||
| 4 | * May be copied or modified under the terms of the GNU General Public | ||
| 5 | * License. See linux/COPYING for more information. | ||
| 6 | * | ||
| 7 | * Based on: | ||
| 8 | * linux/include/asm-arm/arch-sa1100/collie.h | ||
| 9 | * | ||
| 10 | * ChangeLog: | ||
| 11 | * 04-06-2001 Lineo Japan, Inc. | ||
| 12 | * 04-16-2001 SHARP Corporation | ||
| 13 | * Update to 2.6 John Lenz | ||
| 14 | */ | ||
| 15 | #ifndef __ASM_ARCH_POODLE_H | ||
| 16 | #define __ASM_ARCH_POODLE_H 1 | ||
| 17 | |||
| 18 | /* | ||
| 19 | * GPIOs | ||
| 20 | */ | ||
| 21 | /* PXA GPIOs */ | ||
| 22 | #define POODLE_GPIO_ON_KEY (0) | ||
| 23 | #define POODLE_GPIO_AC_IN (1) | ||
| 24 | #define POODLE_GPIO_CO 16 | ||
| 25 | #define POODLE_GPIO_TP_INT (5) | ||
| 26 | #define POODLE_GPIO_WAKEUP (11) /* change battery */ | ||
| 27 | #define POODLE_GPIO_GA_INT (10) | ||
| 28 | #define POODLE_GPIO_IR_ON (22) | ||
| 29 | #define POODLE_GPIO_HP_IN (4) | ||
| 30 | #define POODLE_GPIO_CF_IRQ (17) | ||
| 31 | #define POODLE_GPIO_CF_CD (14) | ||
| 32 | #define POODLE_GPIO_CF_STSCHG (14) | ||
| 33 | #define POODLE_GPIO_SD_PWR (33) | ||
| 34 | #define POODLE_GPIO_SD_PWR1 (3) | ||
| 35 | #define POODLE_GPIO_nSD_CLK (6) | ||
| 36 | #define POODLE_GPIO_nSD_WP (7) | ||
| 37 | #define POODLE_GPIO_nSD_INT (8) | ||
| 38 | #define POODLE_GPIO_nSD_DETECT (9) | ||
| 39 | #define POODLE_GPIO_MAIN_BAT_LOW (13) | ||
| 40 | #define POODLE_GPIO_BAT_COVER (13) | ||
| 41 | #define POODLE_GPIO_USB_PULLUP (20) | ||
| 42 | #define POODLE_GPIO_ADC_TEMP_ON (21) | ||
| 43 | #define POODLE_GPIO_BYPASS_ON (36) | ||
| 44 | #define POODLE_GPIO_CHRG_ON (38) | ||
| 45 | #define POODLE_GPIO_CHRG_FULL (16) | ||
| 46 | #define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */ | ||
| 47 | |||
| 48 | /* PXA GPIOs */ | ||
| 49 | #define POODLE_IRQ_GPIO_ON_KEY IRQ_GPIO(0) | ||
| 50 | #define POODLE_IRQ_GPIO_AC_IN IRQ_GPIO(1) | ||
| 51 | #define POODLE_IRQ_GPIO_HP_IN IRQ_GPIO(4) | ||
| 52 | #define POODLE_IRQ_GPIO_CO IRQ_GPIO(16) | ||
| 53 | #define POODLE_IRQ_GPIO_TP_INT IRQ_GPIO(5) | ||
| 54 | #define POODLE_IRQ_GPIO_WAKEUP IRQ_GPIO(11) | ||
| 55 | #define POODLE_IRQ_GPIO_GA_INT IRQ_GPIO(10) | ||
| 56 | #define POODLE_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) | ||
| 57 | #define POODLE_IRQ_GPIO_CF_CD IRQ_GPIO(14) | ||
| 58 | #define POODLE_IRQ_GPIO_nSD_INT IRQ_GPIO(8) | ||
| 59 | #define POODLE_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) | ||
| 60 | #define POODLE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(13) | ||
| 61 | |||
| 62 | /* SCOOP GPIOs */ | ||
| 63 | #define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11 | ||
| 64 | #define POODLE_SCOOP_CP401 SCOOP_GPCR_PA13 | ||
| 65 | #define POODLE_SCOOP_VPEN SCOOP_GPCR_PA18 | ||
| 66 | #define POODLE_SCOOP_L_PCLK SCOOP_GPCR_PA20 | ||
| 67 | #define POODLE_SCOOP_L_LCLK SCOOP_GPCR_PA21 | ||
| 68 | #define POODLE_SCOOP_HS_OUT SCOOP_GPCR_PA22 | ||
| 69 | |||
| 70 | #define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) | ||
| 71 | #define POODLE_SCOOP_IO_OUT ( 0 ) | ||
| 72 | |||
| 73 | extern struct platform_device poodle_locomo_device; | ||
| 74 | |||
| 75 | #endif /* __ASM_ARCH_POODLE_H */ | ||
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h deleted file mode 100644 index dce9308626b7..000000000000 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ /dev/null | |||
| @@ -1,1070 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/pxa-regs.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Jun 15, 2001 | ||
| 6 | * Copyright: MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __PXA_REGS_H | ||
| 14 | #define __PXA_REGS_H | ||
| 15 | |||
| 16 | |||
| 17 | /* | ||
| 18 | * PXA Chip selects | ||
| 19 | */ | ||
| 20 | |||
| 21 | #define PXA_CS0_PHYS 0x00000000 | ||
| 22 | #define PXA_CS1_PHYS 0x04000000 | ||
| 23 | #define PXA_CS2_PHYS 0x08000000 | ||
| 24 | #define PXA_CS3_PHYS 0x0C000000 | ||
| 25 | #define PXA_CS4_PHYS 0x10000000 | ||
| 26 | #define PXA_CS5_PHYS 0x14000000 | ||
| 27 | |||
| 28 | |||
| 29 | /* | ||
| 30 | * Personal Computer Memory Card International Association (PCMCIA) sockets | ||
| 31 | */ | ||
| 32 | |||
| 33 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | ||
| 34 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | ||
| 35 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | ||
| 36 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | ||
| 37 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | ||
| 38 | |||
| 39 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | ||
| 40 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | ||
| 41 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | ||
| 42 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | ||
| 43 | |||
| 44 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | ||
| 45 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | ||
| 46 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | ||
| 47 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | ||
| 48 | |||
| 49 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | ||
| 50 | (0x20000000 + (Nb)*PCMCIASp) | ||
| 51 | #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ | ||
| 52 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | ||
| 53 | (_PCMCIA (Nb) + 2*PCMCIAPrtSp) | ||
| 54 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | ||
| 55 | (_PCMCIA (Nb) + 3*PCMCIAPrtSp) | ||
| 56 | |||
| 57 | #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ | ||
| 58 | #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ | ||
| 59 | #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ | ||
| 60 | #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ | ||
| 61 | |||
| 62 | #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ | ||
| 63 | #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ | ||
| 64 | #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ | ||
| 65 | #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ | ||
| 66 | |||
| 67 | |||
| 68 | |||
| 69 | /* | ||
| 70 | * DMA Controller | ||
| 71 | */ | ||
| 72 | |||
| 73 | #define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */ | ||
| 74 | #define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */ | ||
| 75 | #define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */ | ||
| 76 | #define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */ | ||
| 77 | #define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */ | ||
| 78 | #define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */ | ||
| 79 | #define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */ | ||
| 80 | #define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */ | ||
| 81 | #define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */ | ||
| 82 | #define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */ | ||
| 83 | #define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */ | ||
| 84 | #define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */ | ||
| 85 | #define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */ | ||
| 86 | #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */ | ||
| 87 | #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */ | ||
| 88 | #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */ | ||
| 89 | |||
| 90 | #define DCSR(x) __REG2(0x40000000, (x) << 2) | ||
| 91 | |||
| 92 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ | ||
| 93 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ | ||
| 94 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | ||
| 95 | #ifdef CONFIG_PXA27x | ||
| 96 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ | ||
| 97 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | ||
| 98 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | ||
| 99 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ | ||
| 100 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ | ||
| 101 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | ||
| 102 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ | ||
| 103 | #endif | ||
| 104 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ | ||
| 105 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | ||
| 106 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | ||
| 107 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | ||
| 108 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | ||
| 109 | |||
| 110 | #define DALGN __REG(0x400000a0) /* DMA Alignment Register */ | ||
| 111 | #define DINT __REG(0x400000f0) /* DMA Interrupt Register */ | ||
| 112 | |||
| 113 | #define DRCMR(n) (*(((n) < 64) ? \ | ||
| 114 | &__REG2(0x40000100, ((n) & 0x3f) << 2) : \ | ||
| 115 | &__REG2(0x40001100, ((n) & 0x3f) << 2))) | ||
| 116 | |||
| 117 | #define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */ | ||
| 118 | #define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */ | ||
| 119 | #define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */ | ||
| 120 | #define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */ | ||
| 121 | #define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */ | ||
| 122 | #define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */ | ||
| 123 | #define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */ | ||
| 124 | #define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */ | ||
| 125 | #define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */ | ||
| 126 | #define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */ | ||
| 127 | #define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */ | ||
| 128 | #define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */ | ||
| 129 | #define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */ | ||
| 130 | #define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */ | ||
| 131 | #define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */ | ||
| 132 | #define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */ | ||
| 133 | #define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */ | ||
| 134 | #define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */ | ||
| 135 | #define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */ | ||
| 136 | #define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */ | ||
| 137 | #define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */ | ||
| 138 | #define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */ | ||
| 139 | #define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */ | ||
| 140 | #define DRCMR23 __REG(0x4000015c) /* Reserved */ | ||
| 141 | #define DRCMR24 __REG(0x40000160) /* Reserved */ | ||
| 142 | #define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */ | ||
| 143 | #define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */ | ||
| 144 | #define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */ | ||
| 145 | #define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */ | ||
| 146 | #define DRCMR29 __REG(0x40000174) /* Reserved */ | ||
| 147 | #define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */ | ||
| 148 | #define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */ | ||
| 149 | #define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */ | ||
| 150 | #define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */ | ||
| 151 | #define DRCMR34 __REG(0x40000188) /* Reserved */ | ||
| 152 | #define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */ | ||
| 153 | #define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */ | ||
| 154 | #define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */ | ||
| 155 | #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */ | ||
| 156 | #define DRCMR39 __REG(0x4000019C) /* Reserved */ | ||
| 157 | #define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */ | ||
| 158 | #define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */ | ||
| 159 | #define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */ | ||
| 160 | #define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */ | ||
| 161 | #define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */ | ||
| 162 | |||
| 163 | #define DRCMRRXSADR DRCMR2 | ||
| 164 | #define DRCMRTXSADR DRCMR3 | ||
| 165 | #define DRCMRRXBTRBR DRCMR4 | ||
| 166 | #define DRCMRTXBTTHR DRCMR5 | ||
| 167 | #define DRCMRRXFFRBR DRCMR6 | ||
| 168 | #define DRCMRTXFFTHR DRCMR7 | ||
| 169 | #define DRCMRRXMCDR DRCMR8 | ||
| 170 | #define DRCMRRXMODR DRCMR9 | ||
| 171 | #define DRCMRTXMODR DRCMR10 | ||
| 172 | #define DRCMRRXPCDR DRCMR11 | ||
| 173 | #define DRCMRTXPCDR DRCMR12 | ||
| 174 | #define DRCMRRXSSDR DRCMR13 | ||
| 175 | #define DRCMRTXSSDR DRCMR14 | ||
| 176 | #define DRCMRRXSS2DR DRCMR15 | ||
| 177 | #define DRCMRTXSS2DR DRCMR16 | ||
| 178 | #define DRCMRRXICDR DRCMR17 | ||
| 179 | #define DRCMRTXICDR DRCMR18 | ||
| 180 | #define DRCMRRXSTRBR DRCMR19 | ||
| 181 | #define DRCMRTXSTTHR DRCMR20 | ||
| 182 | #define DRCMRRXMMC DRCMR21 | ||
| 183 | #define DRCMRTXMMC DRCMR22 | ||
| 184 | #define DRCMRRXSS3DR DRCMR66 | ||
| 185 | #define DRCMRTXSS3DR DRCMR67 | ||
| 186 | #define DRCMRUDC(x) DRCMR((x) + 24) | ||
| 187 | |||
| 188 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ | ||
| 189 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ | ||
| 190 | |||
| 191 | #define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */ | ||
| 192 | #define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */ | ||
| 193 | #define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */ | ||
| 194 | #define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */ | ||
| 195 | #define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */ | ||
| 196 | #define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */ | ||
| 197 | #define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */ | ||
| 198 | #define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */ | ||
| 199 | #define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */ | ||
| 200 | #define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */ | ||
| 201 | #define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */ | ||
| 202 | #define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */ | ||
| 203 | #define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */ | ||
| 204 | #define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */ | ||
| 205 | #define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */ | ||
| 206 | #define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */ | ||
| 207 | #define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */ | ||
| 208 | #define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */ | ||
| 209 | #define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */ | ||
| 210 | #define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */ | ||
| 211 | #define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */ | ||
| 212 | #define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */ | ||
| 213 | #define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */ | ||
| 214 | #define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */ | ||
| 215 | #define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */ | ||
| 216 | #define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */ | ||
| 217 | #define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */ | ||
| 218 | #define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */ | ||
| 219 | #define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */ | ||
| 220 | #define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */ | ||
| 221 | #define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */ | ||
| 222 | #define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */ | ||
| 223 | #define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */ | ||
| 224 | #define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */ | ||
| 225 | #define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */ | ||
| 226 | #define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */ | ||
| 227 | #define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */ | ||
| 228 | #define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */ | ||
| 229 | #define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */ | ||
| 230 | #define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */ | ||
| 231 | #define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */ | ||
| 232 | #define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */ | ||
| 233 | #define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */ | ||
| 234 | #define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */ | ||
| 235 | #define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */ | ||
| 236 | #define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */ | ||
| 237 | #define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */ | ||
| 238 | #define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */ | ||
| 239 | #define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */ | ||
| 240 | #define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */ | ||
| 241 | #define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */ | ||
| 242 | #define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */ | ||
| 243 | #define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */ | ||
| 244 | #define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */ | ||
| 245 | #define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */ | ||
| 246 | #define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */ | ||
| 247 | #define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */ | ||
| 248 | #define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */ | ||
| 249 | #define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */ | ||
| 250 | #define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */ | ||
| 251 | #define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */ | ||
| 252 | #define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */ | ||
| 253 | #define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */ | ||
| 254 | #define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */ | ||
| 255 | |||
| 256 | #define DDADR(x) __REG2(0x40000200, (x) << 4) | ||
| 257 | #define DSADR(x) __REG2(0x40000204, (x) << 4) | ||
| 258 | #define DTADR(x) __REG2(0x40000208, (x) << 4) | ||
| 259 | #define DCMD(x) __REG2(0x4000020c, (x) << 4) | ||
| 260 | |||
| 261 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ | ||
| 262 | #define DDADR_STOP (1 << 0) /* Stop (read / write) */ | ||
| 263 | |||
| 264 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ | ||
| 265 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ | ||
| 266 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ | ||
| 267 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ | ||
| 268 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | ||
| 269 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | ||
| 270 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ | ||
| 271 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ | ||
| 272 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ | ||
| 273 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ | ||
| 274 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ | ||
| 275 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ | ||
| 276 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | ||
| 277 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | ||
| 278 | |||
| 279 | |||
| 280 | /* | ||
| 281 | * UARTs | ||
| 282 | */ | ||
| 283 | |||
| 284 | /* Full Function UART (FFUART) */ | ||
| 285 | #define FFUART FFRBR | ||
| 286 | #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ | ||
| 287 | #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ | ||
| 288 | #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ | ||
| 289 | #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ | ||
| 290 | #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ | ||
| 291 | #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ | ||
| 292 | #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ | ||
| 293 | #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ | ||
| 294 | #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ | ||
| 295 | #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ | ||
| 296 | #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ | ||
| 297 | #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
| 298 | #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
| 299 | |||
| 300 | /* Bluetooth UART (BTUART) */ | ||
| 301 | #define BTUART BTRBR | ||
| 302 | #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ | ||
| 303 | #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ | ||
| 304 | #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ | ||
| 305 | #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ | ||
| 306 | #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ | ||
| 307 | #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ | ||
| 308 | #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ | ||
| 309 | #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ | ||
| 310 | #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ | ||
| 311 | #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ | ||
| 312 | #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ | ||
| 313 | #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
| 314 | #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
| 315 | |||
| 316 | /* Standard UART (STUART) */ | ||
| 317 | #define STUART STRBR | ||
| 318 | #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ | ||
| 319 | #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ | ||
| 320 | #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ | ||
| 321 | #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ | ||
| 322 | #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ | ||
| 323 | #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ | ||
| 324 | #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ | ||
| 325 | #define STLSR __REG(0x40700014) /* Line Status Register (read only) */ | ||
| 326 | #define STMSR __REG(0x40700018) /* Reserved */ | ||
| 327 | #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ | ||
| 328 | #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ | ||
| 329 | #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
| 330 | #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
| 331 | |||
| 332 | /* Hardware UART (HWUART) */ | ||
| 333 | #define HWUART HWRBR | ||
| 334 | #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ | ||
| 335 | #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ | ||
| 336 | #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ | ||
| 337 | #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ | ||
| 338 | #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ | ||
| 339 | #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ | ||
| 340 | #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ | ||
| 341 | #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ | ||
| 342 | #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ | ||
| 343 | #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ | ||
| 344 | #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ | ||
| 345 | #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ | ||
| 346 | #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ | ||
| 347 | #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ | ||
| 348 | #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ | ||
| 349 | #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ | ||
| 350 | |||
| 351 | #define IER_DMAE (1 << 7) /* DMA Requests Enable */ | ||
| 352 | #define IER_UUE (1 << 6) /* UART Unit Enable */ | ||
| 353 | #define IER_NRZE (1 << 5) /* NRZ coding Enable */ | ||
| 354 | #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ | ||
| 355 | #define IER_MIE (1 << 3) /* Modem Interrupt Enable */ | ||
| 356 | #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ | ||
| 357 | #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ | ||
| 358 | #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ | ||
| 359 | |||
| 360 | #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ | ||
| 361 | #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ | ||
| 362 | #define IIR_TOD (1 << 3) /* Time Out Detected */ | ||
| 363 | #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ | ||
| 364 | #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ | ||
| 365 | #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ | ||
| 366 | |||
| 367 | #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ | ||
| 368 | #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ | ||
| 369 | #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ | ||
| 370 | #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ | ||
| 371 | #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ | ||
| 372 | #define FCR_ITL_1 (0) | ||
| 373 | #define FCR_ITL_8 (FCR_ITL1) | ||
| 374 | #define FCR_ITL_16 (FCR_ITL2) | ||
| 375 | #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) | ||
| 376 | |||
| 377 | #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ | ||
| 378 | #define LCR_SB (1 << 6) /* Set Break */ | ||
| 379 | #define LCR_STKYP (1 << 5) /* Sticky Parity */ | ||
| 380 | #define LCR_EPS (1 << 4) /* Even Parity Select */ | ||
| 381 | #define LCR_PEN (1 << 3) /* Parity Enable */ | ||
| 382 | #define LCR_STB (1 << 2) /* Stop Bit */ | ||
| 383 | #define LCR_WLS1 (1 << 1) /* Word Length Select */ | ||
| 384 | #define LCR_WLS0 (1 << 0) /* Word Length Select */ | ||
| 385 | |||
| 386 | #define LSR_FIFOE (1 << 7) /* FIFO Error Status */ | ||
| 387 | #define LSR_TEMT (1 << 6) /* Transmitter Empty */ | ||
| 388 | #define LSR_TDRQ (1 << 5) /* Transmit Data Request */ | ||
| 389 | #define LSR_BI (1 << 4) /* Break Interrupt */ | ||
| 390 | #define LSR_FE (1 << 3) /* Framing Error */ | ||
| 391 | #define LSR_PE (1 << 2) /* Parity Error */ | ||
| 392 | #define LSR_OE (1 << 1) /* Overrun Error */ | ||
| 393 | #define LSR_DR (1 << 0) /* Data Ready */ | ||
| 394 | |||
| 395 | #define MCR_LOOP (1 << 4) | ||
| 396 | #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ | ||
| 397 | #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ | ||
| 398 | #define MCR_RTS (1 << 1) /* Request to Send */ | ||
| 399 | #define MCR_DTR (1 << 0) /* Data Terminal Ready */ | ||
| 400 | |||
| 401 | #define MSR_DCD (1 << 7) /* Data Carrier Detect */ | ||
| 402 | #define MSR_RI (1 << 6) /* Ring Indicator */ | ||
| 403 | #define MSR_DSR (1 << 5) /* Data Set Ready */ | ||
| 404 | #define MSR_CTS (1 << 4) /* Clear To Send */ | ||
| 405 | #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ | ||
| 406 | #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ | ||
| 407 | #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ | ||
| 408 | #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ | ||
| 409 | |||
| 410 | /* | ||
| 411 | * IrSR (Infrared Selection Register) | ||
| 412 | */ | ||
| 413 | #define STISR_RXPL (1 << 4) /* Receive Data Polarity */ | ||
| 414 | #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ | ||
| 415 | #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ | ||
| 416 | #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ | ||
| 417 | #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ | ||
| 418 | |||
| 419 | |||
| 420 | /* | ||
| 421 | * I2C registers | ||
| 422 | */ | ||
| 423 | |||
| 424 | #define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */ | ||
| 425 | #define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */ | ||
| 426 | #define ICR __REG(0x40301690) /* I2C Control Register - ICR */ | ||
| 427 | #define ISR __REG(0x40301698) /* I2C Status Register - ISR */ | ||
| 428 | #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ | ||
| 429 | |||
| 430 | #define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */ | ||
| 431 | #define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */ | ||
| 432 | #define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */ | ||
| 433 | #define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */ | ||
| 434 | #define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */ | ||
| 435 | |||
| 436 | #define ICR_START (1 << 0) /* start bit */ | ||
| 437 | #define ICR_STOP (1 << 1) /* stop bit */ | ||
| 438 | #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ | ||
| 439 | #define ICR_TB (1 << 3) /* transfer byte bit */ | ||
| 440 | #define ICR_MA (1 << 4) /* master abort */ | ||
| 441 | #define ICR_SCLE (1 << 5) /* master clock enable */ | ||
| 442 | #define ICR_IUE (1 << 6) /* unit enable */ | ||
| 443 | #define ICR_GCD (1 << 7) /* general call disable */ | ||
| 444 | #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ | ||
| 445 | #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ | ||
| 446 | #define ICR_BEIE (1 << 10) /* enable bus error ints */ | ||
| 447 | #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ | ||
| 448 | #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ | ||
| 449 | #define ICR_SADIE (1 << 13) /* slave address detected int enable */ | ||
| 450 | #define ICR_UR (1 << 14) /* unit reset */ | ||
| 451 | |||
| 452 | #define ISR_RWM (1 << 0) /* read/write mode */ | ||
| 453 | #define ISR_ACKNAK (1 << 1) /* ack/nak status */ | ||
| 454 | #define ISR_UB (1 << 2) /* unit busy */ | ||
| 455 | #define ISR_IBB (1 << 3) /* bus busy */ | ||
| 456 | #define ISR_SSD (1 << 4) /* slave stop detected */ | ||
| 457 | #define ISR_ALD (1 << 5) /* arbitration loss detected */ | ||
| 458 | #define ISR_ITE (1 << 6) /* tx buffer empty */ | ||
| 459 | #define ISR_IRF (1 << 7) /* rx buffer full */ | ||
| 460 | #define ISR_GCAD (1 << 8) /* general call address detected */ | ||
| 461 | #define ISR_SAD (1 << 9) /* slave address detected */ | ||
| 462 | #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ | ||
| 463 | |||
| 464 | |||
| 465 | /* | ||
| 466 | * Serial Audio Controller | ||
| 467 | */ | ||
| 468 | |||
| 469 | #define SACR0 __REG(0x40400000) /* Global Control Register */ | ||
| 470 | #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ | ||
| 471 | #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ | ||
| 472 | #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ | ||
| 473 | #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ | ||
| 474 | #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ | ||
| 475 | #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ | ||
| 476 | |||
| 477 | #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ | ||
| 478 | #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ | ||
| 479 | #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ | ||
| 480 | #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ | ||
| 481 | #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ | ||
| 482 | #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */ | ||
| 483 | #define SACR0_ENB (1 << 0) /* Enable I2S Link */ | ||
| 484 | #define SACR1_ENLBF (1 << 5) /* Enable Loopback */ | ||
| 485 | #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */ | ||
| 486 | #define SACR1_DREC (1 << 3) /* Disable Recording Function */ | ||
| 487 | #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */ | ||
| 488 | |||
| 489 | #define SASR0_I2SOFF (1 << 7) /* Controller Status */ | ||
| 490 | #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */ | ||
| 491 | #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */ | ||
| 492 | #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */ | ||
| 493 | #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */ | ||
| 494 | #define SASR0_BSY (1 << 2) /* I2S Busy */ | ||
| 495 | #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */ | ||
| 496 | #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */ | ||
| 497 | |||
| 498 | #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */ | ||
| 499 | #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */ | ||
| 500 | |||
| 501 | #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */ | ||
| 502 | #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */ | ||
| 503 | #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ | ||
| 504 | #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ | ||
| 505 | |||
| 506 | /* | ||
| 507 | * AC97 Controller registers | ||
| 508 | */ | ||
| 509 | |||
| 510 | #define POCR __REG(0x40500000) /* PCM Out Control Register */ | ||
| 511 | #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | ||
| 512 | #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
| 513 | |||
| 514 | #define PICR __REG(0x40500004) /* PCM In Control Register */ | ||
| 515 | #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | ||
| 516 | #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
| 517 | |||
| 518 | #define MCCR __REG(0x40500008) /* Mic In Control Register */ | ||
| 519 | #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ | ||
| 520 | #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
| 521 | |||
| 522 | #define GCR __REG(0x4050000C) /* Global Control Register */ | ||
| 523 | #ifdef CONFIG_PXA3xx | ||
| 524 | #define GCR_CLKBPB (1 << 31) /* Internal clock enable */ | ||
| 525 | #endif | ||
| 526 | #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ | ||
| 527 | #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ | ||
| 528 | #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ | ||
| 529 | #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ | ||
| 530 | #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ | ||
| 531 | #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ | ||
| 532 | #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ | ||
| 533 | #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ | ||
| 534 | #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ | ||
| 535 | #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ | ||
| 536 | #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ | ||
| 537 | |||
| 538 | #define POSR __REG(0x40500010) /* PCM Out Status Register */ | ||
| 539 | #define POSR_FIFOE (1 << 4) /* FIFO error */ | ||
| 540 | #define POSR_FSR (1 << 2) /* FIFO Service Request */ | ||
| 541 | |||
| 542 | #define PISR __REG(0x40500014) /* PCM In Status Register */ | ||
| 543 | #define PISR_FIFOE (1 << 4) /* FIFO error */ | ||
| 544 | #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | ||
| 545 | #define PISR_FSR (1 << 2) /* FIFO Service Request */ | ||
| 546 | |||
| 547 | #define MCSR __REG(0x40500018) /* Mic In Status Register */ | ||
| 548 | #define MCSR_FIFOE (1 << 4) /* FIFO error */ | ||
| 549 | #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | ||
| 550 | #define MCSR_FSR (1 << 2) /* FIFO Service Request */ | ||
| 551 | |||
| 552 | #define GSR __REG(0x4050001C) /* Global Status Register */ | ||
| 553 | #define GSR_CDONE (1 << 19) /* Command Done */ | ||
| 554 | #define GSR_SDONE (1 << 18) /* Status Done */ | ||
| 555 | #define GSR_RDCS (1 << 15) /* Read Completion Status */ | ||
| 556 | #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ | ||
| 557 | #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ | ||
| 558 | #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ | ||
| 559 | #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ | ||
| 560 | #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ | ||
| 561 | #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ | ||
| 562 | #define GSR_PCR (1 << 8) /* Primary Codec Ready */ | ||
| 563 | #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ | ||
| 564 | #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ | ||
| 565 | #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ | ||
| 566 | #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ | ||
| 567 | #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ | ||
| 568 | #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ | ||
| 569 | #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ | ||
| 570 | |||
| 571 | #define CAR __REG(0x40500020) /* CODEC Access Register */ | ||
| 572 | #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ | ||
| 573 | |||
| 574 | #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ | ||
| 575 | #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ | ||
| 576 | |||
| 577 | #define MOCR __REG(0x40500100) /* Modem Out Control Register */ | ||
| 578 | #define MOCR_FEIE (1 << 3) /* FIFO Error */ | ||
| 579 | #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
| 580 | |||
| 581 | #define MICR __REG(0x40500108) /* Modem In Control Register */ | ||
| 582 | #define MICR_FEIE (1 << 3) /* FIFO Error */ | ||
| 583 | #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ | ||
| 584 | |||
| 585 | #define MOSR __REG(0x40500110) /* Modem Out Status Register */ | ||
| 586 | #define MOSR_FIFOE (1 << 4) /* FIFO error */ | ||
| 587 | #define MOSR_FSR (1 << 2) /* FIFO Service Request */ | ||
| 588 | |||
| 589 | #define MISR __REG(0x40500118) /* Modem In Status Register */ | ||
| 590 | #define MISR_FIFOE (1 << 4) /* FIFO error */ | ||
| 591 | #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ | ||
| 592 | #define MISR_FSR (1 << 2) /* FIFO Service Request */ | ||
| 593 | |||
| 594 | #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ | ||
| 595 | |||
| 596 | #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ | ||
| 597 | #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ | ||
| 598 | #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ | ||
| 599 | #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ | ||
| 600 | |||
| 601 | |||
| 602 | /* | ||
| 603 | * Fast Infrared Communication Port | ||
| 604 | */ | ||
| 605 | |||
| 606 | #define FICP __REG(0x40800000) /* Start of FICP area */ | ||
| 607 | #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ | ||
| 608 | #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ | ||
| 609 | #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ | ||
| 610 | #define ICDR __REG(0x4080000c) /* ICP Data Register */ | ||
| 611 | #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ | ||
| 612 | #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ | ||
| 613 | |||
| 614 | #define ICCR0_AME (1 << 7) /* Address match enable */ | ||
| 615 | #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ | ||
| 616 | #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ | ||
| 617 | #define ICCR0_RXE (1 << 4) /* Receive enable */ | ||
| 618 | #define ICCR0_TXE (1 << 3) /* Transmit enable */ | ||
| 619 | #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ | ||
| 620 | #define ICCR0_LBM (1 << 1) /* Loopback mode */ | ||
| 621 | #define ICCR0_ITR (1 << 0) /* IrDA transmission */ | ||
| 622 | |||
| 623 | #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ | ||
| 624 | #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ | ||
| 625 | #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ | ||
| 626 | #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ | ||
| 627 | #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ | ||
| 628 | #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ | ||
| 629 | |||
| 630 | #ifdef CONFIG_PXA27x | ||
| 631 | #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ | ||
| 632 | #endif | ||
| 633 | #define ICSR0_FRE (1 << 5) /* Framing error */ | ||
| 634 | #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ | ||
| 635 | #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ | ||
| 636 | #define ICSR0_RAB (1 << 2) /* Receiver abort */ | ||
| 637 | #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ | ||
| 638 | #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ | ||
| 639 | |||
| 640 | #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ | ||
| 641 | #define ICSR1_CRE (1 << 5) /* CRC error */ | ||
| 642 | #define ICSR1_EOF (1 << 4) /* End of frame */ | ||
| 643 | #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ | ||
| 644 | #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ | ||
| 645 | #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ | ||
| 646 | #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ | ||
| 647 | |||
| 648 | |||
| 649 | /* | ||
| 650 | * Real Time Clock | ||
| 651 | */ | ||
| 652 | |||
| 653 | #define RCNR __REG(0x40900000) /* RTC Count Register */ | ||
| 654 | #define RTAR __REG(0x40900004) /* RTC Alarm Register */ | ||
| 655 | #define RTSR __REG(0x40900008) /* RTC Status Register */ | ||
| 656 | #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ | ||
| 657 | #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ | ||
| 658 | |||
| 659 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ | ||
| 660 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ | ||
| 661 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ | ||
| 662 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ | ||
| 663 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ | ||
| 664 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ | ||
| 665 | |||
| 666 | |||
| 667 | /* | ||
| 668 | * OS Timer & Match Registers | ||
| 669 | */ | ||
| 670 | |||
| 671 | #define OSMR0 __REG(0x40A00000) /* */ | ||
| 672 | #define OSMR1 __REG(0x40A00004) /* */ | ||
| 673 | #define OSMR2 __REG(0x40A00008) /* */ | ||
| 674 | #define OSMR3 __REG(0x40A0000C) /* */ | ||
| 675 | #define OSMR4 __REG(0x40A00080) /* */ | ||
| 676 | #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ | ||
| 677 | #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ | ||
| 678 | #define OMCR4 __REG(0x40A000C0) /* */ | ||
| 679 | #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ | ||
| 680 | #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ | ||
| 681 | #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ | ||
| 682 | |||
| 683 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ | ||
| 684 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ | ||
| 685 | #define OSSR_M1 (1 << 1) /* Match status channel 1 */ | ||
| 686 | #define OSSR_M0 (1 << 0) /* Match status channel 0 */ | ||
| 687 | |||
| 688 | #define OWER_WME (1 << 0) /* Watchdog Match Enable */ | ||
| 689 | |||
| 690 | #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ | ||
| 691 | #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ | ||
| 692 | #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ | ||
| 693 | #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ | ||
| 694 | |||
| 695 | |||
| 696 | /* | ||
| 697 | * Pulse Width Modulator | ||
| 698 | */ | ||
| 699 | |||
| 700 | #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ | ||
| 701 | #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ | ||
| 702 | #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ | ||
| 703 | |||
| 704 | #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ | ||
| 705 | #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ | ||
| 706 | #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ | ||
| 707 | |||
| 708 | |||
| 709 | /* | ||
| 710 | * Interrupt Controller | ||
| 711 | */ | ||
| 712 | |||
| 713 | #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ | ||
| 714 | #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ | ||
| 715 | #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ | ||
| 716 | #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ | ||
| 717 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | ||
| 718 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | ||
| 719 | |||
| 720 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | ||
| 721 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | ||
| 722 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | ||
| 723 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | ||
| 724 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | ||
| 725 | |||
| 726 | /* | ||
| 727 | * General Purpose I/O | ||
| 728 | */ | ||
| 729 | |||
| 730 | #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) | ||
| 731 | #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) | ||
| 732 | #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) | ||
| 733 | #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) | ||
| 734 | |||
| 735 | #define GPLR_OFFSET 0x00 | ||
| 736 | #define GPDR_OFFSET 0x0C | ||
| 737 | #define GPSR_OFFSET 0x18 | ||
| 738 | #define GPCR_OFFSET 0x24 | ||
| 739 | #define GRER_OFFSET 0x30 | ||
| 740 | #define GFER_OFFSET 0x3C | ||
| 741 | #define GEDR_OFFSET 0x48 | ||
| 742 | |||
| 743 | #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ | ||
| 744 | #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ | ||
| 745 | #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ | ||
| 746 | |||
| 747 | #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ | ||
| 748 | #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ | ||
| 749 | #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ | ||
| 750 | |||
| 751 | #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ | ||
| 752 | #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ | ||
| 753 | #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ | ||
| 754 | |||
| 755 | #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ | ||
| 756 | #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ | ||
| 757 | #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ | ||
| 758 | |||
| 759 | #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ | ||
| 760 | #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ | ||
| 761 | #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ | ||
| 762 | |||
| 763 | #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ | ||
| 764 | #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ | ||
| 765 | #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ | ||
| 766 | |||
| 767 | #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ | ||
| 768 | #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ | ||
| 769 | #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ | ||
| 770 | |||
| 771 | #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ | ||
| 772 | #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ | ||
| 773 | #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ | ||
| 774 | #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ | ||
| 775 | #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ | ||
| 776 | #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */ | ||
| 777 | #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ | ||
| 778 | #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ | ||
| 779 | |||
| 780 | #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ | ||
| 781 | #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ | ||
| 782 | #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ | ||
| 783 | #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ | ||
| 784 | #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ | ||
| 785 | #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ | ||
| 786 | #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ | ||
| 787 | |||
| 788 | /* More handy macros. The argument is a literal GPIO number. */ | ||
| 789 | |||
| 790 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) | ||
| 791 | |||
| 792 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 793 | |||
| 794 | /* Interrupt Controller */ | ||
| 795 | |||
| 796 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | ||
| 797 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | ||
| 798 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | ||
| 799 | #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) | ||
| 800 | #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) | ||
| 801 | #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) | ||
| 802 | #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) | ||
| 803 | #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) | ||
| 804 | |||
| 805 | #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) | ||
| 806 | #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) | ||
| 807 | #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) | ||
| 808 | #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) | ||
| 809 | #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) | ||
| 810 | #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) | ||
| 811 | #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) | ||
| 812 | #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ | ||
| 813 | ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) | ||
| 814 | #else | ||
| 815 | |||
| 816 | #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | ||
| 817 | #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | ||
| 818 | #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | ||
| 819 | #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) | ||
| 820 | #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) | ||
| 821 | #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) | ||
| 822 | #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) | ||
| 823 | #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) | ||
| 824 | |||
| 825 | #endif | ||
| 826 | |||
| 827 | /* | ||
| 828 | * Power Manager - see pxa2xx-regs.h | ||
| 829 | */ | ||
| 830 | |||
| 831 | /* | ||
| 832 | * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h | ||
| 833 | */ | ||
| 834 | |||
| 835 | /* | ||
| 836 | * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h | ||
| 837 | */ | ||
| 838 | |||
| 839 | /* | ||
| 840 | * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h | ||
| 841 | */ | ||
| 842 | |||
| 843 | #ifdef CONFIG_PXA27x | ||
| 844 | |||
| 845 | /* Camera Interface */ | ||
| 846 | #define CICR0 __REG(0x50000000) | ||
| 847 | #define CICR1 __REG(0x50000004) | ||
| 848 | #define CICR2 __REG(0x50000008) | ||
| 849 | #define CICR3 __REG(0x5000000C) | ||
| 850 | #define CICR4 __REG(0x50000010) | ||
| 851 | #define CISR __REG(0x50000014) | ||
| 852 | #define CIFR __REG(0x50000018) | ||
| 853 | #define CITOR __REG(0x5000001C) | ||
| 854 | #define CIBR0 __REG(0x50000028) | ||
| 855 | #define CIBR1 __REG(0x50000030) | ||
| 856 | #define CIBR2 __REG(0x50000038) | ||
| 857 | |||
| 858 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | ||
| 859 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | ||
| 860 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | ||
| 861 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | ||
| 862 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | ||
| 863 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | ||
| 864 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | ||
| 865 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | ||
| 866 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | ||
| 867 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | ||
| 868 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | ||
| 869 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | ||
| 870 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | ||
| 871 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | ||
| 872 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | ||
| 873 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | ||
| 874 | |||
| 875 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | ||
| 876 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | ||
| 877 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | ||
| 878 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | ||
| 879 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | ||
| 880 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | ||
| 881 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | ||
| 882 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | ||
| 883 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | ||
| 884 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | ||
| 885 | |||
| 886 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | ||
| 887 | wait count mask */ | ||
| 888 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | ||
| 889 | wait count mask */ | ||
| 890 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | ||
| 891 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | ||
| 892 | wait count mask */ | ||
| 893 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | ||
| 894 | wait count mask */ | ||
| 895 | |||
| 896 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | ||
| 897 | wait count mask */ | ||
| 898 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | ||
| 899 | wait count mask */ | ||
| 900 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | ||
| 901 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | ||
| 902 | wait count mask */ | ||
| 903 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | ||
| 904 | |||
| 905 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | ||
| 906 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | ||
| 907 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | ||
| 908 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | ||
| 909 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | ||
| 910 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | ||
| 911 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | ||
| 912 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | ||
| 913 | |||
| 914 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | ||
| 915 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | ||
| 916 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | ||
| 917 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | ||
| 918 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | ||
| 919 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | ||
| 920 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | ||
| 921 | #define CISR_EOL (1 << 8) /* End of line */ | ||
| 922 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | ||
| 923 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | ||
| 924 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | ||
| 925 | #define CISR_SOF (1 << 4) /* Start of frame */ | ||
| 926 | #define CISR_EOF (1 << 3) /* End of frame */ | ||
| 927 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | ||
| 928 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | ||
| 929 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | ||
| 930 | |||
| 931 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | ||
| 932 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | ||
| 933 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | ||
| 934 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | ||
| 935 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | ||
| 936 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | ||
| 937 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | ||
| 938 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | ||
| 939 | |||
| 940 | #define SRAM_SIZE 0x40000 /* 4x64K */ | ||
| 941 | |||
| 942 | #define SRAM_MEM_PHYS 0x5C000000 | ||
| 943 | |||
| 944 | #define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */ | ||
| 945 | #define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */ | ||
| 946 | |||
| 947 | #define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */ | ||
| 948 | #define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */ | ||
| 949 | #define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */ | ||
| 950 | #define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */ | ||
| 951 | |||
| 952 | #define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */ | ||
| 953 | #define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */ | ||
| 954 | #define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */ | ||
| 955 | #define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */ | ||
| 956 | |||
| 957 | #define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */ | ||
| 958 | #define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */ | ||
| 959 | #define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */ | ||
| 960 | #define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */ | ||
| 961 | |||
| 962 | #define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */ | ||
| 963 | #define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */ | ||
| 964 | #define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */ | ||
| 965 | #define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */ | ||
| 966 | |||
| 967 | #define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */ | ||
| 968 | #define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */ | ||
| 969 | #define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */ | ||
| 970 | #define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */ | ||
| 971 | |||
| 972 | #define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */ | ||
| 973 | |||
| 974 | #define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */ | ||
| 975 | #define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */ | ||
| 976 | #define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */ | ||
| 977 | |||
| 978 | #define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */ | ||
| 979 | #define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */ | ||
| 980 | #define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */ | ||
| 981 | |||
| 982 | #define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */ | ||
| 983 | #define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */ | ||
| 984 | #define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */ | ||
| 985 | |||
| 986 | #define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */ | ||
| 987 | #define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */ | ||
| 988 | #define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */ | ||
| 989 | |||
| 990 | #endif | ||
| 991 | |||
| 992 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 993 | /* | ||
| 994 | * UHC: USB Host Controller (OHCI-like) register definitions | ||
| 995 | */ | ||
| 996 | #define UHC_BASE_PHYS (0x4C000000) | ||
| 997 | #define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */ | ||
| 998 | #define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */ | ||
| 999 | #define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */ | ||
| 1000 | #define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */ | ||
| 1001 | #define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */ | ||
| 1002 | #define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */ | ||
| 1003 | #define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */ | ||
| 1004 | #define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */ | ||
| 1005 | #define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */ | ||
| 1006 | #define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */ | ||
| 1007 | #define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */ | ||
| 1008 | #define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */ | ||
| 1009 | #define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */ | ||
| 1010 | #define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */ | ||
| 1011 | #define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */ | ||
| 1012 | #define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */ | ||
| 1013 | #define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */ | ||
| 1014 | #define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */ | ||
| 1015 | |||
| 1016 | #define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */ | ||
| 1017 | #define UHCRHDA_NOCP (1 << 12) /* No over current protection */ | ||
| 1018 | |||
| 1019 | #define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */ | ||
| 1020 | #define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */ | ||
| 1021 | #define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */ | ||
| 1022 | #define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */ | ||
| 1023 | #define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */ | ||
| 1024 | |||
| 1025 | #define UHCSTAT __REG(0x4C000060) /* UHC Status Register */ | ||
| 1026 | #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ | ||
| 1027 | #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ | ||
| 1028 | #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ | ||
| 1029 | #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ | ||
| 1030 | #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ | ||
| 1031 | #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ | ||
| 1032 | #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ | ||
| 1033 | #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ | ||
| 1034 | #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ | ||
| 1035 | |||
| 1036 | #define UHCHR __REG(0x4C000064) /* UHC Reset Register */ | ||
| 1037 | #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ | ||
| 1038 | #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ | ||
| 1039 | #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ | ||
| 1040 | #define UHCHR_PCPL (1 << 7) /* Power control polarity low */ | ||
| 1041 | #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */ | ||
| 1042 | #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ | ||
| 1043 | #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ | ||
| 1044 | #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ | ||
| 1045 | #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */ | ||
| 1046 | #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ | ||
| 1047 | #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ | ||
| 1048 | |||
| 1049 | #define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/ | ||
| 1050 | #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ | ||
| 1051 | #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ | ||
| 1052 | #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ | ||
| 1053 | #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ | ||
| 1054 | #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort | ||
| 1055 | Interrupt Enable*/ | ||
| 1056 | #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ | ||
| 1057 | #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ | ||
| 1058 | |||
| 1059 | #define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */ | ||
| 1060 | |||
| 1061 | #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ | ||
| 1062 | |||
| 1063 | /* PWRMODE register M field values */ | ||
| 1064 | |||
| 1065 | #define PWRMODE_IDLE 0x1 | ||
| 1066 | #define PWRMODE_STANDBY 0x2 | ||
| 1067 | #define PWRMODE_SLEEP 0x3 | ||
| 1068 | #define PWRMODE_DEEPSLEEP 0x7 | ||
| 1069 | |||
| 1070 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h deleted file mode 100644 index 1b80a4805a60..000000000000 --- a/include/asm-arm/arch-pxa/pxa25x-udc.h +++ /dev/null | |||
| @@ -1,163 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_PXA25X_UDC_H | ||
| 2 | #define _ASM_ARCH_PXA25X_UDC_H | ||
| 3 | |||
| 4 | #ifdef _ASM_ARCH_PXA27X_UDC_H | ||
| 5 | #error "You can't include both PXA25x and PXA27x UDC support" | ||
| 6 | #endif | ||
| 7 | |||
| 8 | #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ | ||
| 9 | #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ | ||
| 10 | #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ | ||
| 11 | |||
| 12 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ | ||
| 13 | #define UDCCR_UDE (1 << 0) /* UDC enable */ | ||
| 14 | #define UDCCR_UDA (1 << 1) /* UDC active */ | ||
| 15 | #define UDCCR_RSM (1 << 2) /* Device resume */ | ||
| 16 | #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ | ||
| 17 | #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ | ||
| 18 | #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ | ||
| 19 | #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ | ||
| 20 | #define UDCCR_REM (1 << 7) /* Reset interrupt mask */ | ||
| 21 | |||
| 22 | #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ | ||
| 23 | #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ | ||
| 24 | #define UDCCS0_IPR (1 << 1) /* IN packet ready */ | ||
| 25 | #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ | ||
| 26 | #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ | ||
| 27 | #define UDCCS0_SST (1 << 4) /* Sent stall */ | ||
| 28 | #define UDCCS0_FST (1 << 5) /* Force stall */ | ||
| 29 | #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ | ||
| 30 | #define UDCCS0_SA (1 << 7) /* Setup active */ | ||
| 31 | |||
| 32 | /* Bulk IN - Endpoint 1,6,11 */ | ||
| 33 | #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ | ||
| 34 | #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ | ||
| 35 | #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ | ||
| 36 | |||
| 37 | #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ | ||
| 38 | #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ | ||
| 39 | #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ | ||
| 40 | #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
| 41 | #define UDCCS_BI_SST (1 << 4) /* Sent stall */ | ||
| 42 | #define UDCCS_BI_FST (1 << 5) /* Force stall */ | ||
| 43 | #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ | ||
| 44 | |||
| 45 | /* Bulk OUT - Endpoint 2,7,12 */ | ||
| 46 | #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ | ||
| 47 | #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ | ||
| 48 | #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ | ||
| 49 | |||
| 50 | #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ | ||
| 51 | #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ | ||
| 52 | #define UDCCS_BO_DME (1 << 3) /* DMA enable */ | ||
| 53 | #define UDCCS_BO_SST (1 << 4) /* Sent stall */ | ||
| 54 | #define UDCCS_BO_FST (1 << 5) /* Force stall */ | ||
| 55 | #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ | ||
| 56 | #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ | ||
| 57 | |||
| 58 | /* Isochronous IN - Endpoint 3,8,13 */ | ||
| 59 | #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ | ||
| 60 | #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ | ||
| 61 | #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ | ||
| 62 | |||
| 63 | #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ | ||
| 64 | #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ | ||
| 65 | #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ | ||
| 66 | #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
| 67 | #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ | ||
| 68 | |||
| 69 | /* Isochronous OUT - Endpoint 4,9,14 */ | ||
| 70 | #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ | ||
| 71 | #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ | ||
| 72 | #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ | ||
| 73 | |||
| 74 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ | ||
| 75 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ | ||
| 76 | #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ | ||
| 77 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ | ||
| 78 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ | ||
| 79 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ | ||
| 80 | |||
| 81 | /* Interrupt IN - Endpoint 5,10,15 */ | ||
| 82 | #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ | ||
| 83 | #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ | ||
| 84 | #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ | ||
| 85 | |||
| 86 | #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ | ||
| 87 | #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ | ||
| 88 | #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ | ||
| 89 | #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ | ||
| 90 | #define UDCCS_INT_SST (1 << 4) /* Sent stall */ | ||
| 91 | #define UDCCS_INT_FST (1 << 5) /* Force stall */ | ||
| 92 | #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ | ||
| 93 | |||
| 94 | #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ | ||
| 95 | #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ | ||
| 96 | #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ | ||
| 97 | #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ | ||
| 98 | #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ | ||
| 99 | #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ | ||
| 100 | #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ | ||
| 101 | #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ | ||
| 102 | #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ | ||
| 103 | #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ | ||
| 104 | #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ | ||
| 105 | #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ | ||
| 106 | #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ | ||
| 107 | #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ | ||
| 108 | #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ | ||
| 109 | #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ | ||
| 110 | #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ | ||
| 111 | #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ | ||
| 112 | #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ | ||
| 113 | #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ | ||
| 114 | #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ | ||
| 115 | #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ | ||
| 116 | #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ | ||
| 117 | #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ | ||
| 118 | |||
| 119 | #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ | ||
| 120 | |||
| 121 | #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ | ||
| 122 | #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ | ||
| 123 | #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ | ||
| 124 | #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ | ||
| 125 | #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ | ||
| 126 | #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ | ||
| 127 | #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ | ||
| 128 | #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ | ||
| 129 | |||
| 130 | #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ | ||
| 131 | |||
| 132 | #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ | ||
| 133 | #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ | ||
| 134 | #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ | ||
| 135 | #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ | ||
| 136 | #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ | ||
| 137 | #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ | ||
| 138 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ | ||
| 139 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ | ||
| 140 | |||
| 141 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ | ||
| 142 | |||
| 143 | #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ | ||
| 144 | #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ | ||
| 145 | #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ | ||
| 146 | #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ | ||
| 147 | #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ | ||
| 148 | #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ | ||
| 149 | #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ | ||
| 150 | #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ | ||
| 151 | |||
| 152 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ | ||
| 153 | |||
| 154 | #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ | ||
| 155 | #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ | ||
| 156 | #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ | ||
| 157 | #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ | ||
| 158 | #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ | ||
| 159 | #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ | ||
| 160 | #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ | ||
| 161 | #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ | ||
| 162 | |||
| 163 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h deleted file mode 100644 index ab1443f8bd89..000000000000 --- a/include/asm-arm/arch-pxa/pxa27x-udc.h +++ /dev/null | |||
| @@ -1,257 +0,0 @@ | |||
| 1 | #ifndef _ASM_ARCH_PXA27X_UDC_H | ||
| 2 | #define _ASM_ARCH_PXA27X_UDC_H | ||
| 3 | |||
| 4 | #ifdef _ASM_ARCH_PXA25X_UDC_H | ||
| 5 | #error You cannot include both PXA25x and PXA27x UDC support | ||
| 6 | #endif | ||
| 7 | |||
| 8 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ | ||
| 9 | #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ | ||
| 10 | #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation | ||
| 11 | Protocol Port Support */ | ||
| 12 | #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol | ||
| 13 | Support */ | ||
| 14 | #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol | ||
| 15 | Enable */ | ||
| 16 | #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ | ||
| 17 | #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ | ||
| 18 | #define UDCCR_ACN_S 11 | ||
| 19 | #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ | ||
| 20 | #define UDCCR_AIN_S 8 | ||
| 21 | #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface | ||
| 22 | Setting Number */ | ||
| 23 | #define UDCCR_AAISN_S 5 | ||
| 24 | #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active | ||
| 25 | Configuration */ | ||
| 26 | #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration | ||
| 27 | Error */ | ||
| 28 | #define UDCCR_UDR (1 << 2) /* UDC Resume */ | ||
| 29 | #define UDCCR_UDA (1 << 1) /* UDC Active */ | ||
| 30 | #define UDCCR_UDE (1 << 0) /* UDC Enable */ | ||
| 31 | |||
| 32 | #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ | ||
| 33 | #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ | ||
| 34 | #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ | ||
| 35 | #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ | ||
| 36 | |||
| 37 | #define UDC_INT_FIFOERROR (0x2) | ||
| 38 | #define UDC_INT_PACKETCMP (0x1) | ||
| 39 | |||
| 40 | #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) | ||
| 41 | #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ | ||
| 42 | #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ | ||
| 43 | #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ | ||
| 44 | #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ | ||
| 45 | #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ | ||
| 46 | |||
| 47 | #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ | ||
| 48 | #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ | ||
| 49 | #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) | ||
| 50 | #define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ | ||
| 51 | #define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ | ||
| 52 | #define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ | ||
| 53 | #define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ | ||
| 54 | #define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ | ||
| 55 | |||
| 56 | #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ | ||
| 57 | #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ | ||
| 58 | #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ | ||
| 59 | #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt | ||
| 60 | Rising Edge Interrupt Enable */ | ||
| 61 | #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt | ||
| 62 | Falling Edge Interrupt Enable */ | ||
| 63 | #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge | ||
| 64 | Interrupt Enable */ | ||
| 65 | #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge | ||
| 66 | Interrupt Enable */ | ||
| 67 | #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge | ||
| 68 | Interrupt Enable */ | ||
| 69 | #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge | ||
| 70 | Interrupt Enable */ | ||
| 71 | #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge | ||
| 72 | Interrupt Enable */ | ||
| 73 | #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge | ||
| 74 | Interrupt Enable */ | ||
| 75 | #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising | ||
| 76 | Edge Interrupt Enable */ | ||
| 77 | #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling | ||
| 78 | Edge Interrupt Enable */ | ||
| 79 | #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge | ||
| 80 | Interrupt Enable */ | ||
| 81 | #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge | ||
| 82 | Interrupt Enable */ | ||
| 83 | |||
| 84 | #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ | ||
| 85 | #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */ | ||
| 86 | |||
| 87 | #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ | ||
| 88 | #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ | ||
| 89 | #define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ | ||
| 90 | #define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ | ||
| 91 | #define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ | ||
| 92 | #define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ | ||
| 93 | #define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ | ||
| 94 | #define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ | ||
| 95 | #define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ | ||
| 96 | #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ | ||
| 97 | #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ | ||
| 98 | #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ | ||
| 99 | #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ | ||
| 100 | #define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */ | ||
| 101 | |||
| 102 | #define UDCCSN(x) __REG2(0x40600100, (x) << 2) | ||
| 103 | #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ | ||
| 104 | #define UDCCSR0_SA (1 << 7) /* Setup Active */ | ||
| 105 | #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ | ||
| 106 | #define UDCCSR0_FST (1 << 5) /* Force Stall */ | ||
| 107 | #define UDCCSR0_SST (1 << 4) /* Sent Stall */ | ||
| 108 | #define UDCCSR0_DME (1 << 3) /* DMA Enable */ | ||
| 109 | #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ | ||
| 110 | #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ | ||
| 111 | #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ | ||
| 112 | |||
| 113 | #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ | ||
| 114 | #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ | ||
| 115 | #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ | ||
| 116 | #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ | ||
| 117 | #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ | ||
| 118 | #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ | ||
| 119 | #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ | ||
| 120 | #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ | ||
| 121 | #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ | ||
| 122 | #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ | ||
| 123 | #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ | ||
| 124 | #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ | ||
| 125 | #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ | ||
| 126 | #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ | ||
| 127 | #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ | ||
| 128 | #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ | ||
| 129 | #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ | ||
| 130 | #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ | ||
| 131 | #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ | ||
| 132 | #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ | ||
| 133 | #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ | ||
| 134 | #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ | ||
| 135 | #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ | ||
| 136 | |||
| 137 | #define UDCCSR_DPE (1 << 9) /* Data Packet Error */ | ||
| 138 | #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ | ||
| 139 | #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ | ||
| 140 | #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ | ||
| 141 | #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ | ||
| 142 | #define UDCCSR_FST (1 << 5) /* Force STALL */ | ||
| 143 | #define UDCCSR_SST (1 << 4) /* Sent STALL */ | ||
| 144 | #define UDCCSR_DME (1 << 3) /* DMA Enable */ | ||
| 145 | #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ | ||
| 146 | #define UDCCSR_PC (1 << 1) /* Packet Complete */ | ||
| 147 | #define UDCCSR_FS (1 << 0) /* FIFO needs service */ | ||
| 148 | |||
| 149 | #define UDCBCN(x) __REG2(0x40600200, (x)<<2) | ||
| 150 | #define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ | ||
| 151 | #define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ | ||
| 152 | #define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ | ||
| 153 | #define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ | ||
| 154 | #define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ | ||
| 155 | #define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ | ||
| 156 | #define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ | ||
| 157 | #define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ | ||
| 158 | #define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ | ||
| 159 | #define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ | ||
| 160 | #define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ | ||
| 161 | #define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ | ||
| 162 | #define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ | ||
| 163 | #define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ | ||
| 164 | #define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ | ||
| 165 | #define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ | ||
| 166 | #define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ | ||
| 167 | #define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ | ||
| 168 | #define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ | ||
| 169 | #define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ | ||
| 170 | #define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ | ||
| 171 | #define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ | ||
| 172 | #define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ | ||
| 173 | #define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ | ||
| 174 | |||
| 175 | #define UDCDN(x) __REG2(0x40600300, (x)<<2) | ||
| 176 | #define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) | ||
| 177 | #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) | ||
| 178 | #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ | ||
| 179 | #define UDCDRA __REG(0x40600304) /* Data Register - EPA */ | ||
| 180 | #define UDCDRB __REG(0x40600308) /* Data Register - EPB */ | ||
| 181 | #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ | ||
| 182 | #define UDCDRD __REG(0x40600310) /* Data Register - EPD */ | ||
| 183 | #define UDCDRE __REG(0x40600314) /* Data Register - EPE */ | ||
| 184 | #define UDCDRF __REG(0x40600318) /* Data Register - EPF */ | ||
| 185 | #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ | ||
| 186 | #define UDCDRH __REG(0x40600320) /* Data Register - EPH */ | ||
| 187 | #define UDCDRI __REG(0x40600324) /* Data Register - EPI */ | ||
| 188 | #define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ | ||
| 189 | #define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ | ||
| 190 | #define UDCDRL __REG(0x40600330) /* Data Register - EPL */ | ||
| 191 | #define UDCDRM __REG(0x40600334) /* Data Register - EPM */ | ||
| 192 | #define UDCDRN __REG(0x40600338) /* Data Register - EPN */ | ||
| 193 | #define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ | ||
| 194 | #define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ | ||
| 195 | #define UDCDRR __REG(0x40600344) /* Data Register - EPR */ | ||
| 196 | #define UDCDRS __REG(0x40600348) /* Data Register - EPS */ | ||
| 197 | #define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ | ||
| 198 | #define UDCDRU __REG(0x40600350) /* Data Register - EPU */ | ||
| 199 | #define UDCDRV __REG(0x40600354) /* Data Register - EPV */ | ||
| 200 | #define UDCDRW __REG(0x40600358) /* Data Register - EPW */ | ||
| 201 | #define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ | ||
| 202 | |||
| 203 | #define UDCCN(x) __REG2(0x40600400, (x)<<2) | ||
| 204 | #define UDCCRA __REG(0x40600404) /* Configuration register EPA */ | ||
| 205 | #define UDCCRB __REG(0x40600408) /* Configuration register EPB */ | ||
| 206 | #define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ | ||
| 207 | #define UDCCRD __REG(0x40600410) /* Configuration register EPD */ | ||
| 208 | #define UDCCRE __REG(0x40600414) /* Configuration register EPE */ | ||
| 209 | #define UDCCRF __REG(0x40600418) /* Configuration register EPF */ | ||
| 210 | #define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ | ||
| 211 | #define UDCCRH __REG(0x40600420) /* Configuration register EPH */ | ||
| 212 | #define UDCCRI __REG(0x40600424) /* Configuration register EPI */ | ||
| 213 | #define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ | ||
| 214 | #define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ | ||
| 215 | #define UDCCRL __REG(0x40600430) /* Configuration register EPL */ | ||
| 216 | #define UDCCRM __REG(0x40600434) /* Configuration register EPM */ | ||
| 217 | #define UDCCRN __REG(0x40600438) /* Configuration register EPN */ | ||
| 218 | #define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ | ||
| 219 | #define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ | ||
| 220 | #define UDCCRR __REG(0x40600444) /* Configuration register EPR */ | ||
| 221 | #define UDCCRS __REG(0x40600448) /* Configuration register EPS */ | ||
| 222 | #define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ | ||
| 223 | #define UDCCRU __REG(0x40600450) /* Configuration register EPU */ | ||
| 224 | #define UDCCRV __REG(0x40600454) /* Configuration register EPV */ | ||
| 225 | #define UDCCRW __REG(0x40600458) /* Configuration register EPW */ | ||
| 226 | #define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ | ||
| 227 | |||
| 228 | #define UDCCONR_CN (0x03 << 25) /* Configuration Number */ | ||
| 229 | #define UDCCONR_CN_S (25) | ||
| 230 | #define UDCCONR_IN (0x07 << 22) /* Interface Number */ | ||
| 231 | #define UDCCONR_IN_S (22) | ||
| 232 | #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ | ||
| 233 | #define UDCCONR_AISN_S (19) | ||
| 234 | #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ | ||
| 235 | #define UDCCONR_EN_S (15) | ||
| 236 | #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ | ||
| 237 | #define UDCCONR_ET_S (13) | ||
| 238 | #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ | ||
| 239 | #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ | ||
| 240 | #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ | ||
| 241 | #define UDCCONR_ET_NU (0x00 << 13) /* Not used */ | ||
| 242 | #define UDCCONR_ED (1 << 12) /* Endpoint Direction */ | ||
| 243 | #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ | ||
| 244 | #define UDCCONR_MPS_S (2) | ||
| 245 | #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ | ||
| 246 | #define UDCCONR_EE (1 << 0) /* Endpoint Enable */ | ||
| 247 | |||
| 248 | |||
| 249 | #define UDC_INT_FIFOERROR (0x2) | ||
| 250 | #define UDC_INT_PACKETCMP (0x1) | ||
| 251 | |||
| 252 | #define UDC_FNR_MASK (0x7ff) | ||
| 253 | |||
| 254 | #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) | ||
| 255 | #define UDC_BCR_MASK (0x3ff) | ||
| 256 | |||
| 257 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/pxa27x_keypad.h b/include/asm-arm/arch-pxa/pxa27x_keypad.h deleted file mode 100644 index d5a48a96dea7..000000000000 --- a/include/asm-arm/arch-pxa/pxa27x_keypad.h +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_PXA27x_KEYPAD_H | ||
| 2 | #define __ASM_ARCH_PXA27x_KEYPAD_H | ||
| 3 | |||
| 4 | #include <linux/input.h> | ||
| 5 | |||
| 6 | #define MAX_MATRIX_KEY_ROWS (8) | ||
| 7 | #define MAX_MATRIX_KEY_COLS (8) | ||
| 8 | |||
| 9 | /* pxa3xx keypad platform specific parameters | ||
| 10 | * | ||
| 11 | * NOTE: | ||
| 12 | * 1. direct_key_num indicates the number of keys in the direct keypad | ||
| 13 | * _plus_ the number of rotary-encoder sensor inputs, this can be | ||
| 14 | * left as 0 if only rotary encoders are enabled, the driver will | ||
| 15 | * automatically calculate this | ||
| 16 | * | ||
| 17 | * 2. direct_key_map is the key code map for the direct keys, if rotary | ||
| 18 | * encoder(s) are enabled, direct key 0/1(2/3) will be ignored | ||
| 19 | * | ||
| 20 | * 3. rotary can be either interpreted as a relative input event (e.g. | ||
| 21 | * REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT) | ||
| 22 | * | ||
| 23 | * 4. matrix key and direct key will use the same debounce_interval by | ||
| 24 | * default, which should be sufficient in most cases | ||
| 25 | */ | ||
| 26 | struct pxa27x_keypad_platform_data { | ||
| 27 | |||
| 28 | /* code map for the matrix keys */ | ||
| 29 | unsigned int matrix_key_rows; | ||
| 30 | unsigned int matrix_key_cols; | ||
| 31 | unsigned int *matrix_key_map; | ||
| 32 | int matrix_key_map_size; | ||
| 33 | |||
| 34 | /* direct keys */ | ||
| 35 | int direct_key_num; | ||
| 36 | unsigned int direct_key_map[8]; | ||
| 37 | |||
| 38 | /* rotary encoders 0 */ | ||
| 39 | int enable_rotary0; | ||
| 40 | int rotary0_rel_code; | ||
| 41 | int rotary0_up_key; | ||
| 42 | int rotary0_down_key; | ||
| 43 | |||
| 44 | /* rotary encoders 1 */ | ||
| 45 | int enable_rotary1; | ||
| 46 | int rotary1_rel_code; | ||
| 47 | int rotary1_up_key; | ||
| 48 | int rotary1_down_key; | ||
| 49 | |||
| 50 | /* key debounce interval */ | ||
| 51 | unsigned int debounce_interval; | ||
| 52 | }; | ||
| 53 | |||
| 54 | #define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val)) | ||
| 55 | |||
| 56 | extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info); | ||
| 57 | |||
| 58 | #endif /* __ASM_ARCH_PXA27x_KEYPAD_H */ | ||
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h deleted file mode 100644 index 6ef1dd09970b..000000000000 --- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h +++ /dev/null | |||
| @@ -1,368 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_PXA2XX_GPIO_H | ||
| 2 | #define __ASM_ARCH_PXA2XX_GPIO_H | ||
| 3 | |||
| 4 | #warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h | ||
| 5 | |||
| 6 | /* GPIO alternate function assignments */ | ||
| 7 | |||
| 8 | #define GPIO1_RST 1 /* reset */ | ||
| 9 | #define GPIO6_MMCCLK 6 /* MMC Clock */ | ||
| 10 | #define GPIO7_48MHz 7 /* 48 MHz clock output */ | ||
| 11 | #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ | ||
| 12 | #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ | ||
| 13 | #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ | ||
| 14 | #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ | ||
| 15 | #define GPIO12_32KHz 12 /* 32 kHz out */ | ||
| 16 | #define GPIO12_CIF_DD_7 12 /* Camera data pin 7 */ | ||
| 17 | #define GPIO13_MBGNT 13 /* memory controller grant */ | ||
| 18 | #define GPIO14_MBREQ 14 /* alternate bus master request */ | ||
| 19 | #define GPIO15_nCS_1 15 /* chip select 1 */ | ||
| 20 | #define GPIO16_PWM0 16 /* PWM0 output */ | ||
| 21 | #define GPIO17_PWM1 17 /* PWM1 output */ | ||
| 22 | #define GPIO17_CIF_DD_6 17 /* Camera data pin 6 */ | ||
| 23 | #define GPIO18_RDY 18 /* Ext. Bus Ready */ | ||
| 24 | #define GPIO19_DREQ1 19 /* External DMA Request */ | ||
| 25 | #define GPIO20_DREQ0 20 /* External DMA Request */ | ||
| 26 | #define GPIO23_SCLK 23 /* SSP clock */ | ||
| 27 | #define GPIO23_CIF_MCLK 23 /* Camera Master Clock */ | ||
| 28 | #define GPIO24_SFRM 24 /* SSP Frame */ | ||
| 29 | #define GPIO24_CIF_FV 24 /* Camera frame start signal */ | ||
| 30 | #define GPIO25_STXD 25 /* SSP transmit */ | ||
| 31 | #define GPIO25_CIF_LV 25 /* Camera line start signal */ | ||
| 32 | #define GPIO26_SRXD 26 /* SSP receive */ | ||
| 33 | #define GPIO26_CIF_PCLK 26 /* Camera Pixel Clock */ | ||
| 34 | #define GPIO27_SEXTCLK 27 /* SSP ext_clk */ | ||
| 35 | #define GPIO27_CIF_DD_0 27 /* Camera data pin 0 */ | ||
| 36 | #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ | ||
| 37 | #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ | ||
| 38 | #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ | ||
| 39 | #define GPIO31_SYNC 31 /* AC97/I2S sync */ | ||
| 40 | #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ | ||
| 41 | #define GPIO32_SYSCLK 32 /* I2S System Clock */ | ||
| 42 | #define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */ | ||
| 43 | #define GPIO33_nCS_5 33 /* chip select 5 */ | ||
| 44 | #define GPIO34_FFRXD 34 /* FFUART receive */ | ||
| 45 | #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ | ||
| 46 | #define GPIO35_FFCTS 35 /* FFUART Clear to send */ | ||
| 47 | #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ | ||
| 48 | #define GPIO37_FFDSR 37 /* FFUART data set ready */ | ||
| 49 | #define GPIO38_FFRI 38 /* FFUART Ring Indicator */ | ||
| 50 | #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ | ||
| 51 | #define GPIO39_FFTXD 39 /* FFUART transmit data */ | ||
| 52 | #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ | ||
| 53 | #define GPIO41_FFRTS 41 /* FFUART request to send */ | ||
| 54 | #define GPIO42_BTRXD 42 /* BTUART receive data */ | ||
| 55 | #define GPIO42_HWRXD 42 /* HWUART receive data */ | ||
| 56 | #define GPIO42_CIF_MCLK 42 /* Camera Master Clock */ | ||
| 57 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ | ||
| 58 | #define GPIO43_HWTXD 43 /* HWUART transmit data */ | ||
| 59 | #define GPIO43_CIF_FV 43 /* Camera frame start signal */ | ||
| 60 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ | ||
| 61 | #define GPIO44_HWCTS 44 /* HWUART clear to send */ | ||
| 62 | #define GPIO44_CIF_LV 44 /* Camera line start signal */ | ||
| 63 | #define GPIO45_BTRTS 45 /* BTUART request to send */ | ||
| 64 | #define GPIO45_HWRTS 45 /* HWUART request to send */ | ||
| 65 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ | ||
| 66 | #define GPIO45_CIF_PCLK 45 /* Camera Pixel Clock */ | ||
| 67 | #define GPIO46_ICPRXD 46 /* ICP receive data */ | ||
| 68 | #define GPIO46_STRXD 46 /* STD_UART receive data */ | ||
| 69 | #define GPIO47_ICPTXD 47 /* ICP transmit data */ | ||
| 70 | #define GPIO47_STTXD 47 /* STD_UART transmit data */ | ||
| 71 | #define GPIO47_CIF_DD_0 47 /* Camera data pin 0 */ | ||
| 72 | #define GPIO48_nPOE 48 /* Output Enable for Card Space */ | ||
| 73 | #define GPIO48_CIF_DD_5 48 /* Camera data pin 5 */ | ||
| 74 | #define GPIO49_nPWE 49 /* Write Enable for Card Space */ | ||
| 75 | #define GPIO50_nPIOR 50 /* I/O Read for Card Space */ | ||
| 76 | #define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */ | ||
| 77 | #define GPIO51_nPIOW 51 /* I/O Write for Card Space */ | ||
| 78 | #define GPIO51_CIF_DD_2 51 /* Camera data pin 2 */ | ||
| 79 | #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ | ||
| 80 | #define GPIO52_CIF_DD_4 52 /* Camera data pin 4 */ | ||
| 81 | #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ | ||
| 82 | #define GPIO53_MMCCLK 53 /* MMC Clock */ | ||
| 83 | #define GPIO53_CIF_MCLK 53 /* Camera Master Clock */ | ||
| 84 | #define GPIO54_MMCCLK 54 /* MMC Clock */ | ||
| 85 | #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ | ||
| 86 | #define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */ | ||
| 87 | #define GPIO54_CIF_PCLK 54 /* Camera Pixel Clock */ | ||
| 88 | #define GPIO55_nPREG 55 /* Card Address bit 26 */ | ||
| 89 | #define GPIO55_CIF_DD_1 55 /* Camera data pin 1 */ | ||
| 90 | #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ | ||
| 91 | #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ | ||
| 92 | #define GPIO58_LDD_0 58 /* LCD data pin 0 */ | ||
| 93 | #define GPIO59_LDD_1 59 /* LCD data pin 1 */ | ||
| 94 | #define GPIO60_LDD_2 60 /* LCD data pin 2 */ | ||
| 95 | #define GPIO61_LDD_3 61 /* LCD data pin 3 */ | ||
| 96 | #define GPIO62_LDD_4 62 /* LCD data pin 4 */ | ||
| 97 | #define GPIO63_LDD_5 63 /* LCD data pin 5 */ | ||
| 98 | #define GPIO64_LDD_6 64 /* LCD data pin 6 */ | ||
| 99 | #define GPIO65_LDD_7 65 /* LCD data pin 7 */ | ||
| 100 | #define GPIO66_LDD_8 66 /* LCD data pin 8 */ | ||
| 101 | #define GPIO66_MBREQ 66 /* alternate bus master req */ | ||
| 102 | #define GPIO67_LDD_9 67 /* LCD data pin 9 */ | ||
| 103 | #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ | ||
| 104 | #define GPIO68_LDD_10 68 /* LCD data pin 10 */ | ||
| 105 | #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ | ||
| 106 | #define GPIO69_LDD_11 69 /* LCD data pin 11 */ | ||
| 107 | #define GPIO69_MMCCLK 69 /* MMC_CLK */ | ||
| 108 | #define GPIO70_LDD_12 70 /* LCD data pin 12 */ | ||
| 109 | #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ | ||
| 110 | #define GPIO71_LDD_13 71 /* LCD data pin 13 */ | ||
| 111 | #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ | ||
| 112 | #define GPIO72_LDD_14 72 /* LCD data pin 14 */ | ||
| 113 | #define GPIO72_32kHz 72 /* 32 kHz clock */ | ||
| 114 | #define GPIO73_LDD_15 73 /* LCD data pin 15 */ | ||
| 115 | #define GPIO73_MBGNT 73 /* Memory controller grant */ | ||
| 116 | #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ | ||
| 117 | #define GPIO75_LCD_LCLK 75 /* LCD line clock */ | ||
| 118 | #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ | ||
| 119 | #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ | ||
| 120 | #define GPIO78_nCS_2 78 /* chip select 2 */ | ||
| 121 | #define GPIO79_nCS_3 79 /* chip select 3 */ | ||
| 122 | #define GPIO80_nCS_4 80 /* chip select 4 */ | ||
| 123 | #define GPIO81_NSCLK 81 /* NSSP clock */ | ||
| 124 | #define GPIO81_CIF_DD_0 81 /* Camera data pin 0 */ | ||
| 125 | #define GPIO82_NSFRM 82 /* NSSP Frame */ | ||
| 126 | #define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */ | ||
| 127 | #define GPIO83_NSTXD 83 /* NSSP transmit */ | ||
| 128 | #define GPIO83_CIF_DD_4 83 /* Camera data pin 4 */ | ||
| 129 | #define GPIO84_NSRXD 84 /* NSSP receive */ | ||
| 130 | #define GPIO84_CIF_FV 84 /* Camera frame start signal */ | ||
| 131 | #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ | ||
| 132 | #define GPIO85_CIF_LV 85 /* Camera line start signal */ | ||
| 133 | #define GPIO90_CIF_DD_4 90 /* Camera data pin 4 */ | ||
| 134 | #define GPIO91_CIF_DD_5 91 /* Camera data pin 5 */ | ||
| 135 | #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ | ||
| 136 | #define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */ | ||
| 137 | #define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */ | ||
| 138 | #define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */ | ||
| 139 | #define GPIO96_FFRXD 96 /* FFUART recieve */ | ||
| 140 | #define GPIO98_FFRTS 98 /* FFUART request to send */ | ||
| 141 | #define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */ | ||
| 142 | #define GPIO99_FFTXD 99 /* FFUART transmit data */ | ||
| 143 | #define GPIO100_FFCTS 100 /* FFUART Clear to send */ | ||
| 144 | #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ | ||
| 145 | #define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */ | ||
| 146 | #define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */ | ||
| 147 | #define GPIO105_CIF_DD_1 105 /* Camera data pin 1 */ | ||
| 148 | #define GPIO106_CIF_DD_9 106 /* Camera data pin 9 */ | ||
| 149 | #define GPIO107_CIF_DD_8 107 /* Camera data pin 8 */ | ||
| 150 | #define GPIO108_CIF_DD_7 108 /* Camera data pin 7 */ | ||
| 151 | #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ | ||
| 152 | #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ | ||
| 153 | #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ | ||
| 154 | #define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */ | ||
| 155 | #define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */ | ||
| 156 | #define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ | ||
| 157 | #define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ | ||
| 158 | #define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ | ||
| 159 | #define GPIO114_CIF_DD_1 114 /* Camera data pin 1 */ | ||
| 160 | #define GPIO115_CIF_DD_3 115 /* Camera data pin 3 */ | ||
| 161 | #define GPIO116_CIF_DD_2 116 /* Camera data pin 2 */ | ||
| 162 | |||
| 163 | /* GPIO alternate function mode & direction */ | ||
| 164 | |||
| 165 | #define GPIO_IN 0x000 | ||
| 166 | #define GPIO_OUT 0x080 | ||
| 167 | #define GPIO_ALT_FN_1_IN 0x100 | ||
| 168 | #define GPIO_ALT_FN_1_OUT 0x180 | ||
| 169 | #define GPIO_ALT_FN_2_IN 0x200 | ||
| 170 | #define GPIO_ALT_FN_2_OUT 0x280 | ||
| 171 | #define GPIO_ALT_FN_3_IN 0x300 | ||
| 172 | #define GPIO_ALT_FN_3_OUT 0x380 | ||
| 173 | #define GPIO_MD_MASK_NR 0x07f | ||
| 174 | #define GPIO_MD_MASK_DIR 0x080 | ||
| 175 | #define GPIO_MD_MASK_FN 0x300 | ||
| 176 | #define GPIO_DFLT_LOW 0x400 | ||
| 177 | #define GPIO_DFLT_HIGH 0x800 | ||
| 178 | |||
| 179 | #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) | ||
| 180 | #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) | ||
| 181 | #define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT) | ||
| 182 | #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) | ||
| 183 | #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) | ||
| 184 | #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) | ||
| 185 | #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) | ||
| 186 | #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) | ||
| 187 | #define GPIO12_CIF_DD_7_MD (12 | GPIO_ALT_FN_2_IN) | ||
| 188 | #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) | ||
| 189 | #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) | ||
| 190 | #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) | ||
| 191 | #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) | ||
| 192 | #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) | ||
| 193 | #define GPIO17_CIF_DD_6_MD (17 | GPIO_ALT_FN_2_IN) | ||
| 194 | #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) | ||
| 195 | #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) | ||
| 196 | #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) | ||
| 197 | #define GPIO23_CIF_MCLK_MD (23 | GPIO_ALT_FN_1_OUT) | ||
| 198 | #define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) | ||
| 199 | #define GPIO24_CIF_FV_MD (24 | GPIO_ALT_FN_1_OUT) | ||
| 200 | #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) | ||
| 201 | #define GPIO25_CIF_LV_MD (25 | GPIO_ALT_FN_1_OUT) | ||
| 202 | #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) | ||
| 203 | #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) | ||
| 204 | #define GPIO26_CIF_PCLK_MD (26 | GPIO_ALT_FN_2_IN) | ||
| 205 | #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) | ||
| 206 | #define GPIO27_CIF_DD_0_MD (27 | GPIO_ALT_FN_3_IN) | ||
| 207 | #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) | ||
| 208 | #define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) | ||
| 209 | #define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) | ||
| 210 | #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) | ||
| 211 | #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) | ||
| 212 | #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) | ||
| 213 | #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) | ||
| 214 | #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) | ||
| 215 | #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) | ||
| 216 | #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) | ||
| 217 | #define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT) | ||
| 218 | #define GPIO32_MMCCLK_MD (32 | GPIO_ALT_FN_2_OUT) | ||
| 219 | #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) | ||
| 220 | #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) | ||
| 221 | #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) | ||
| 222 | #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) | ||
| 223 | #define GPIO35_KP_MKOUT6_MD (35 | GPIO_ALT_FN_2_OUT) | ||
| 224 | #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) | ||
| 225 | #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) | ||
| 226 | #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) | ||
| 227 | #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) | ||
| 228 | #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) | ||
| 229 | #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) | ||
| 230 | #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) | ||
| 231 | #define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT) | ||
| 232 | #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) | ||
| 233 | #define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) | ||
| 234 | #define GPIO42_CIF_MCLK_MD (42 | GPIO_ALT_FN_3_OUT) | ||
| 235 | #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) | ||
| 236 | #define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) | ||
| 237 | #define GPIO43_CIF_FV_MD (43 | GPIO_ALT_FN_3_OUT) | ||
| 238 | #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) | ||
| 239 | #define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) | ||
| 240 | #define GPIO44_CIF_LV_MD (44 | GPIO_ALT_FN_3_OUT) | ||
| 241 | #define GPIO45_CIF_PCLK_MD (45 | GPIO_ALT_FN_3_IN) | ||
| 242 | #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) | ||
| 243 | #define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) | ||
| 244 | #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) | ||
| 245 | #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) | ||
| 246 | #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) | ||
| 247 | #define GPIO47_CIF_DD_0_MD (47 | GPIO_ALT_FN_1_IN) | ||
| 248 | #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) | ||
| 249 | #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) | ||
| 250 | #define GPIO48_CIF_DD_5_MD (48 | GPIO_ALT_FN_1_IN) | ||
| 251 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
| 252 | #define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) | ||
| 253 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
| 254 | #define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) | ||
| 255 | #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) | ||
| 256 | #define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 257 | #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) | ||
| 258 | #define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 259 | #define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 260 | #define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) | ||
| 261 | #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) | ||
| 262 | #define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) | ||
| 263 | #define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) | ||
| 264 | #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) | ||
| 265 | #define GPIO52_CIF_DD_4_MD (52 | GPIO_ALT_FN_1_IN) | ||
| 266 | #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) | ||
| 267 | #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) | ||
| 268 | #define GPIO53_CIF_MCLK_MD (53 | GPIO_ALT_FN_2_OUT) | ||
| 269 | #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) | ||
| 270 | #define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT) | ||
| 271 | #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) | ||
| 272 | #define GPIO54_CIF_PCLK_MD (54 | GPIO_ALT_FN_3_IN) | ||
| 273 | #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) | ||
| 274 | #define GPIO55_CIF_DD_1_MD (55 | GPIO_ALT_FN_1_IN) | ||
| 275 | #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) | ||
| 276 | #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) | ||
| 277 | #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) | ||
| 278 | #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) | ||
| 279 | #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) | ||
| 280 | #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) | ||
| 281 | #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) | ||
| 282 | #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) | ||
| 283 | #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) | ||
| 284 | #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) | ||
| 285 | #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) | ||
| 286 | #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) | ||
| 287 | #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) | ||
| 288 | #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) | ||
| 289 | #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) | ||
| 290 | #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) | ||
| 291 | #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) | ||
| 292 | #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) | ||
| 293 | #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) | ||
| 294 | #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) | ||
| 295 | #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) | ||
| 296 | #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) | ||
| 297 | #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) | ||
| 298 | #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) | ||
| 299 | #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) | ||
| 300 | #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) | ||
| 301 | #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) | ||
| 302 | #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) | ||
| 303 | #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) | ||
| 304 | #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) | ||
| 305 | #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) | ||
| 306 | #define GPIO78_nPCE_2_MD (78 | GPIO_ALT_FN_1_OUT) | ||
| 307 | #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) | ||
| 308 | #define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT) | ||
| 309 | #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) | ||
| 310 | #define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT) | ||
| 311 | #define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN) | ||
| 312 | #define GPIO81_CIF_DD_0_MD (81 | GPIO_ALT_FN_2_IN) | ||
| 313 | #define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT) | ||
| 314 | #define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN) | ||
| 315 | #define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN) | ||
| 316 | #define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) | ||
| 317 | #define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) | ||
| 318 | #define GPIO83_CIF_DD_4_MD (83 | GPIO_ALT_FN_3_IN) | ||
| 319 | #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) | ||
| 320 | #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) | ||
| 321 | #define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN) | ||
| 322 | #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) | ||
| 323 | #define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN) | ||
| 324 | #define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT) | ||
| 325 | #define GPIO88_USBH1_PWR_MD (88 | GPIO_ALT_FN_1_IN) | ||
| 326 | #define GPIO89_USBH1_PEN_MD (89 | GPIO_ALT_FN_2_OUT) | ||
| 327 | #define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN) | ||
| 328 | #define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN) | ||
| 329 | #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) | ||
| 330 | #define GPIO93_CIF_DD_6_MD (93 | GPIO_ALT_FN_2_IN) | ||
| 331 | #define GPIO94_CIF_DD_5_MD (94 | GPIO_ALT_FN_2_IN) | ||
| 332 | #define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN) | ||
| 333 | #define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN) | ||
| 334 | #define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN) | ||
| 335 | #define GPIO96_FFRXD_MD (96 | GPIO_ALT_FN_3_IN) | ||
| 336 | #define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN) | ||
| 337 | #define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN) | ||
| 338 | #define GPIO98_FFRTS_MD (98 | GPIO_ALT_FN_3_OUT) | ||
| 339 | #define GPIO99_FFTXD_MD (99 | GPIO_ALT_FN_3_OUT) | ||
| 340 | #define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN) | ||
| 341 | #define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN) | ||
| 342 | #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) | ||
| 343 | #define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN) | ||
| 344 | #define GPIO103_CIF_DD_3_MD (103 | GPIO_ALT_FN_1_IN) | ||
| 345 | #define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT) | ||
| 346 | #define GPIO104_CIF_DD_2_MD (104 | GPIO_ALT_FN_1_IN) | ||
| 347 | #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) | ||
| 348 | #define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT) | ||
| 349 | #define GPIO105_CIF_DD_1_MD (105 | GPIO_ALT_FN_1_IN) | ||
| 350 | #define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT) | ||
| 351 | #define GPIO106_CIF_DD_9_MD (106 | GPIO_ALT_FN_1_IN) | ||
| 352 | #define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT) | ||
| 353 | #define GPIO107_CIF_DD_8_MD (107 | GPIO_ALT_FN_1_IN) | ||
| 354 | #define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT) | ||
| 355 | #define GPIO108_CIF_DD_7_MD (108 | GPIO_ALT_FN_1_IN) | ||
| 356 | #define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT) | ||
| 357 | #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) | ||
| 358 | #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) | ||
| 359 | #define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) | ||
| 360 | #define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT) | ||
| 361 | #define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT) | ||
| 362 | #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) | ||
| 363 | #define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) | ||
| 364 | #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) | ||
| 365 | #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) | ||
| 366 | #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) | ||
| 367 | |||
| 368 | #endif /* __ASM_ARCH_PXA2XX_GPIO_H */ | ||
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h deleted file mode 100644 index 73e0a329cf7f..000000000000 --- a/include/asm-arm/arch-pxa/pxa2xx-regs.h +++ /dev/null | |||
| @@ -1,246 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/pxa2xx-regs.h | ||
| 3 | * | ||
| 4 | * Taken from pxa-regs.h by Russell King | ||
| 5 | * | ||
| 6 | * Author: Nicolas Pitre | ||
| 7 | * Copyright: MontaVista Software Inc. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __PXA2XX_REGS_H | ||
| 15 | #define __PXA2XX_REGS_H | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Memory controller | ||
| 19 | */ | ||
| 20 | |||
| 21 | #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ | ||
| 22 | #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ | ||
| 23 | #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ | ||
| 24 | #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ | ||
| 25 | #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ | ||
| 26 | #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ | ||
| 27 | #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ | ||
| 28 | #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ | ||
| 29 | #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ | ||
| 30 | #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ | ||
| 31 | #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ | ||
| 32 | #define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ | ||
| 33 | #define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ | ||
| 34 | #define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ | ||
| 35 | #define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ | ||
| 36 | #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ | ||
| 37 | #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ | ||
| 38 | |||
| 39 | /* | ||
| 40 | * More handy macros for PCMCIA | ||
| 41 | * | ||
| 42 | * Arg is socket number | ||
| 43 | */ | ||
| 44 | #define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ | ||
| 45 | #define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ | ||
| 46 | #define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ | ||
| 47 | |||
| 48 | /* MECR register defines */ | ||
| 49 | #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ | ||
| 50 | #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ | ||
| 51 | |||
| 52 | #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ | ||
| 53 | #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ | ||
| 54 | #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ | ||
| 55 | #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ | ||
| 56 | #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ | ||
| 57 | #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ | ||
| 58 | #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ | ||
| 59 | #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ | ||
| 60 | #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ | ||
| 61 | #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ | ||
| 62 | #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ | ||
| 63 | #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ | ||
| 64 | #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ | ||
| 65 | #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ | ||
| 66 | |||
| 67 | |||
| 68 | #ifdef CONFIG_PXA27x | ||
| 69 | |||
| 70 | #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ | ||
| 71 | |||
| 72 | #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ | ||
| 73 | #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ | ||
| 74 | #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ | ||
| 75 | #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ | ||
| 76 | #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ | ||
| 77 | #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ | ||
| 78 | #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ | ||
| 79 | #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ | ||
| 80 | #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ | ||
| 81 | |||
| 82 | #endif | ||
| 83 | |||
| 84 | |||
| 85 | /* | ||
| 86 | * Power Manager | ||
| 87 | */ | ||
| 88 | |||
| 89 | #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ | ||
| 90 | #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ | ||
| 91 | #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ | ||
| 92 | #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ | ||
| 93 | #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ | ||
| 94 | #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ | ||
| 95 | #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ | ||
| 96 | #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ | ||
| 97 | #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ | ||
| 98 | #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ | ||
| 99 | #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ | ||
| 100 | #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ | ||
| 101 | #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ | ||
| 102 | |||
| 103 | #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ | ||
| 104 | #define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ | ||
| 105 | #define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ | ||
| 106 | #define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ | ||
| 107 | #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ | ||
| 108 | #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ | ||
| 109 | #define PCMD(x) __REG2(0x40F00080, (x)<<2) | ||
| 110 | #define PCMD0 __REG(0x40F00080 + 0 * 4) | ||
| 111 | #define PCMD1 __REG(0x40F00080 + 1 * 4) | ||
| 112 | #define PCMD2 __REG(0x40F00080 + 2 * 4) | ||
| 113 | #define PCMD3 __REG(0x40F00080 + 3 * 4) | ||
| 114 | #define PCMD4 __REG(0x40F00080 + 4 * 4) | ||
| 115 | #define PCMD5 __REG(0x40F00080 + 5 * 4) | ||
| 116 | #define PCMD6 __REG(0x40F00080 + 6 * 4) | ||
| 117 | #define PCMD7 __REG(0x40F00080 + 7 * 4) | ||
| 118 | #define PCMD8 __REG(0x40F00080 + 8 * 4) | ||
| 119 | #define PCMD9 __REG(0x40F00080 + 9 * 4) | ||
| 120 | #define PCMD10 __REG(0x40F00080 + 10 * 4) | ||
| 121 | #define PCMD11 __REG(0x40F00080 + 11 * 4) | ||
| 122 | #define PCMD12 __REG(0x40F00080 + 12 * 4) | ||
| 123 | #define PCMD13 __REG(0x40F00080 + 13 * 4) | ||
| 124 | #define PCMD14 __REG(0x40F00080 + 14 * 4) | ||
| 125 | #define PCMD15 __REG(0x40F00080 + 15 * 4) | ||
| 126 | #define PCMD16 __REG(0x40F00080 + 16 * 4) | ||
| 127 | #define PCMD17 __REG(0x40F00080 + 17 * 4) | ||
| 128 | #define PCMD18 __REG(0x40F00080 + 18 * 4) | ||
| 129 | #define PCMD19 __REG(0x40F00080 + 19 * 4) | ||
| 130 | #define PCMD20 __REG(0x40F00080 + 20 * 4) | ||
| 131 | #define PCMD21 __REG(0x40F00080 + 21 * 4) | ||
| 132 | #define PCMD22 __REG(0x40F00080 + 22 * 4) | ||
| 133 | #define PCMD23 __REG(0x40F00080 + 23 * 4) | ||
| 134 | #define PCMD24 __REG(0x40F00080 + 24 * 4) | ||
| 135 | #define PCMD25 __REG(0x40F00080 + 25 * 4) | ||
| 136 | #define PCMD26 __REG(0x40F00080 + 26 * 4) | ||
| 137 | #define PCMD27 __REG(0x40F00080 + 27 * 4) | ||
| 138 | #define PCMD28 __REG(0x40F00080 + 28 * 4) | ||
| 139 | #define PCMD29 __REG(0x40F00080 + 29 * 4) | ||
| 140 | #define PCMD30 __REG(0x40F00080 + 30 * 4) | ||
| 141 | #define PCMD31 __REG(0x40F00080 + 31 * 4) | ||
| 142 | |||
| 143 | #define PCMD_MBC (1<<12) | ||
| 144 | #define PCMD_DCE (1<<11) | ||
| 145 | #define PCMD_LC (1<<10) | ||
| 146 | /* FIXME: PCMD_SQC need be checked. */ | ||
| 147 | #define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, | ||
| 148 | bit 9 should be 0 all day. */ | ||
| 149 | #define PVCR_VCSA (0x1<<14) | ||
| 150 | #define PVCR_CommandDelay (0xf80) | ||
| 151 | #define PCFR_PI2C_EN (0x1 << 6) | ||
| 152 | |||
| 153 | #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ | ||
| 154 | #define PSSR_RDH (1 << 5) /* Read Disable Hold */ | ||
| 155 | #define PSSR_PH (1 << 4) /* Peripheral Control Hold */ | ||
| 156 | #define PSSR_STS (1 << 3) /* Standby Mode Status */ | ||
| 157 | #define PSSR_VFS (1 << 2) /* VDD Fault Status */ | ||
| 158 | #define PSSR_BFS (1 << 1) /* Battery Fault Status */ | ||
| 159 | #define PSSR_SSS (1 << 0) /* Software Sleep Status */ | ||
| 160 | |||
| 161 | #define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ | ||
| 162 | |||
| 163 | #define PCFR_RO (1 << 15) /* RDH Override */ | ||
| 164 | #define PCFR_PO (1 << 14) /* PH Override */ | ||
| 165 | #define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ | ||
| 166 | #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ | ||
| 167 | #define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ | ||
| 168 | #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ | ||
| 169 | #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ | ||
| 170 | #define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ | ||
| 171 | #define PCFR_DS (1 << 3) /* Deep Sleep Mode */ | ||
| 172 | #define PCFR_FS (1 << 2) /* Float Static Chip Selects */ | ||
| 173 | #define PCFR_FP (1 << 1) /* Float PCMCIA controls */ | ||
| 174 | #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ | ||
| 175 | |||
| 176 | #define RCSR_GPR (1 << 3) /* GPIO Reset */ | ||
| 177 | #define RCSR_SMR (1 << 2) /* Sleep Mode */ | ||
| 178 | #define RCSR_WDR (1 << 1) /* Watchdog Reset */ | ||
| 179 | #define RCSR_HWR (1 << 0) /* Hardware Reset */ | ||
| 180 | |||
| 181 | #define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ | ||
| 182 | #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ | ||
| 183 | #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ | ||
| 184 | #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ | ||
| 185 | #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ | ||
| 186 | #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ | ||
| 187 | #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ | ||
| 188 | #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ | ||
| 189 | #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ | ||
| 190 | #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ | ||
| 191 | #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ | ||
| 192 | #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ | ||
| 193 | #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ | ||
| 194 | #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ | ||
| 195 | #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ | ||
| 196 | #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ | ||
| 197 | #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ | ||
| 198 | #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ | ||
| 199 | |||
| 200 | /* | ||
| 201 | * PXA2xx specific Core clock definitions | ||
| 202 | */ | ||
| 203 | #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ | ||
| 204 | #define CCSR __REG(0x4130000C) /* Core Clock Status Register */ | ||
| 205 | #define CKEN __REG(0x41300004) /* Clock Enable Register */ | ||
| 206 | #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ | ||
| 207 | |||
| 208 | #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ | ||
| 209 | #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ | ||
| 210 | #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ | ||
| 211 | |||
| 212 | #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ | ||
| 213 | #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ | ||
| 214 | #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ | ||
| 215 | #define CKEN_MEMC (22) /* Memory Controller Clock Enable */ | ||
| 216 | #define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ | ||
| 217 | #define CKEN_IM (20) /* Internal Memory Clock Enable */ | ||
| 218 | #define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ | ||
| 219 | #define CKEN_USIM (18) /* USIM Unit Clock Enable */ | ||
| 220 | #define CKEN_MSL (17) /* MSL Unit Clock Enable */ | ||
| 221 | #define CKEN_LCD (16) /* LCD Unit Clock Enable */ | ||
| 222 | #define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ | ||
| 223 | #define CKEN_I2C (14) /* I2C Unit Clock Enable */ | ||
| 224 | #define CKEN_FICP (13) /* FICP Unit Clock Enable */ | ||
| 225 | #define CKEN_MMC (12) /* MMC Unit Clock Enable */ | ||
| 226 | #define CKEN_USB (11) /* USB Unit Clock Enable */ | ||
| 227 | #define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ | ||
| 228 | #define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ | ||
| 229 | #define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ | ||
| 230 | #define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ | ||
| 231 | #define CKEN_I2S (8) /* I2S Unit Clock Enable */ | ||
| 232 | #define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ | ||
| 233 | #define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ | ||
| 234 | #define CKEN_STUART (5) /* STUART Unit Clock Enable */ | ||
| 235 | #define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ | ||
| 236 | #define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ | ||
| 237 | #define CKEN_SSP (3) /* SSP Unit Clock Enable */ | ||
| 238 | #define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ | ||
| 239 | #define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ | ||
| 240 | #define CKEN_PWM1 (1) /* PWM1 Clock Enable */ | ||
| 241 | #define CKEN_PWM0 (0) /* PWM0 Clock Enable */ | ||
| 242 | |||
| 243 | #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ | ||
| 244 | #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ | ||
| 245 | |||
| 246 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h deleted file mode 100644 index 2206cb61a9f9..000000000000 --- a/include/asm-arm/arch-pxa/pxa2xx_spi.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef PXA2XX_SPI_H_ | ||
| 20 | #define PXA2XX_SPI_H_ | ||
| 21 | |||
| 22 | #define PXA2XX_CS_ASSERT (0x01) | ||
| 23 | #define PXA2XX_CS_DEASSERT (0x02) | ||
| 24 | |||
| 25 | /* device.platform_data for SSP controller devices */ | ||
| 26 | struct pxa2xx_spi_master { | ||
| 27 | u32 clock_enable; | ||
| 28 | u16 num_chipselect; | ||
| 29 | u8 enable_dma; | ||
| 30 | }; | ||
| 31 | |||
| 32 | /* spi_board_info.controller_data for SPI slave devices, | ||
| 33 | * copied to spi_device.platform_data ... mostly for dma tuning | ||
| 34 | */ | ||
| 35 | struct pxa2xx_spi_chip { | ||
| 36 | u8 tx_threshold; | ||
| 37 | u8 rx_threshold; | ||
| 38 | u8 dma_burst_size; | ||
| 39 | u32 timeout; | ||
| 40 | u8 enable_loopback; | ||
| 41 | void (*cs_control)(u32 command); | ||
| 42 | }; | ||
| 43 | |||
| 44 | extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info); | ||
| 45 | |||
| 46 | #endif /*PXA2XX_SPI_H_*/ | ||
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h deleted file mode 100644 index fe9364c83a28..000000000000 --- a/include/asm-arm/arch-pxa/pxa3xx-regs.h +++ /dev/null | |||
| @@ -1,183 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h | ||
| 3 | * | ||
| 4 | * PXA3xx specific register definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Marvell International Ltd. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_PXA3XX_REGS_H | ||
| 14 | #define __ASM_ARCH_PXA3XX_REGS_H | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Oscillator Configuration Register (OSCC) | ||
| 18 | */ | ||
| 19 | #define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ | ||
| 20 | |||
| 21 | #define OSCC_PEN (1 << 11) /* 13MHz POUT */ | ||
| 22 | |||
| 23 | |||
| 24 | /* | ||
| 25 | * Service Power Management Unit (MPMU) | ||
| 26 | */ | ||
| 27 | #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ | ||
| 28 | #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ | ||
| 29 | #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ | ||
| 30 | #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ | ||
| 31 | #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ | ||
| 32 | #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ | ||
| 33 | #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ | ||
| 34 | #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ | ||
| 35 | #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ | ||
| 36 | #define PCMD(x) __REG(0x40F50110 + ((x) << 2)) | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Slave Power Managment Unit | ||
| 40 | */ | ||
| 41 | #define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ | ||
| 42 | #define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ | ||
| 43 | #define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ | ||
| 44 | #define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ | ||
| 45 | #define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ | ||
| 46 | #define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ | ||
| 47 | #define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ | ||
| 48 | #define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ | ||
| 49 | #define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ | ||
| 50 | #define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ | ||
| 51 | #define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ | ||
| 52 | #define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ | ||
| 53 | #define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ | ||
| 54 | #define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ | ||
| 55 | |||
| 56 | /* | ||
| 57 | * Application Subsystem Configuration bits. | ||
| 58 | */ | ||
| 59 | #define ASCR_RDH (1 << 31) | ||
| 60 | #define ASCR_D1S (1 << 2) | ||
| 61 | #define ASCR_D2S (1 << 1) | ||
| 62 | #define ASCR_D3S (1 << 0) | ||
| 63 | |||
| 64 | /* | ||
| 65 | * Application Reset Status bits. | ||
| 66 | */ | ||
| 67 | #define ARSR_GPR (1 << 3) | ||
| 68 | #define ARSR_LPMR (1 << 2) | ||
| 69 | #define ARSR_WDT (1 << 1) | ||
| 70 | #define ARSR_HWR (1 << 0) | ||
| 71 | |||
| 72 | /* | ||
| 73 | * Application Subsystem Wake-Up bits. | ||
| 74 | */ | ||
| 75 | #define ADXER_WRTC (1 << 31) /* RTC */ | ||
| 76 | #define ADXER_WOST (1 << 30) /* OS Timer */ | ||
| 77 | #define ADXER_WTSI (1 << 29) /* Touchscreen */ | ||
| 78 | #define ADXER_WUSBH (1 << 28) /* USB host */ | ||
| 79 | #define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */ | ||
| 80 | #define ADXER_WMSL0 (1 << 24) /* MSL port 0*/ | ||
| 81 | #define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */ | ||
| 82 | #define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */ | ||
| 83 | #define ADXER_WKP (1 << 21) /* Keypad */ | ||
| 84 | #define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */ | ||
| 85 | #define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */ | ||
| 86 | #define ADXER_WOTG (1 << 16) /* USBOTG input */ | ||
| 87 | #define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */ | ||
| 88 | #define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */ | ||
| 89 | #define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */ | ||
| 90 | #define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */ | ||
| 91 | #define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */ | ||
| 92 | #define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */ | ||
| 93 | #define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */ | ||
| 94 | #define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */ | ||
| 95 | #define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */ | ||
| 96 | #define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */ | ||
| 97 | #define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */ | ||
| 98 | #define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */ | ||
| 99 | #define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */ | ||
| 100 | #define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */ | ||
| 101 | #define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */ | ||
| 102 | #define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */ | ||
| 103 | |||
| 104 | /* | ||
| 105 | * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320. | ||
| 106 | */ | ||
| 107 | #define ADXR_L2 (1 << 8) | ||
| 108 | #define ADXR_R5 (1 << 5) | ||
| 109 | #define ADXR_R4 (1 << 4) | ||
| 110 | #define ADXR_R3 (1 << 3) | ||
| 111 | #define ADXR_R2 (1 << 2) | ||
| 112 | #define ADXR_R1 (1 << 1) | ||
| 113 | #define ADXR_R0 (1 << 0) | ||
| 114 | |||
| 115 | /* | ||
| 116 | * Values for PWRMODE CP15 register | ||
| 117 | */ | ||
| 118 | #define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */ | ||
| 119 | #define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */ | ||
| 120 | #define PXA3xx_PM_S0D2C2 0x03 /* aka standby */ | ||
| 121 | #define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */ | ||
| 122 | #define PXA3xx_PM_S0D0C1 0x01 | ||
| 123 | |||
| 124 | /* | ||
| 125 | * Application Subsystem Clock | ||
| 126 | */ | ||
| 127 | #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ | ||
| 128 | #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ | ||
| 129 | #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ | ||
| 130 | #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ | ||
| 131 | #define CKENB __REG(0x41340010) /* B Clock Enable Register */ | ||
| 132 | #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ | ||
| 133 | |||
| 134 | /* | ||
| 135 | * Clock Enable Bit | ||
| 136 | */ | ||
| 137 | #define CKEN_LCD 1 /* < LCD Clock Enable */ | ||
| 138 | #define CKEN_USBH 2 /* < USB host clock enable */ | ||
| 139 | #define CKEN_CAMERA 3 /* < Camera interface clock enable */ | ||
| 140 | #define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ | ||
| 141 | #define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ | ||
| 142 | #define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ | ||
| 143 | #define CKEN_SMC 9 /* < Static Memory Controller clock enable */ | ||
| 144 | #define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ | ||
| 145 | #define CKEN_BOOT 11 /* < Boot rom clock enable */ | ||
| 146 | #define CKEN_MMC1 12 /* < MMC1 Clock enable */ | ||
| 147 | #define CKEN_MMC2 13 /* < MMC2 clock enable */ | ||
| 148 | #define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ | ||
| 149 | #define CKEN_CIR 15 /* < Consumer IR Clock Enable */ | ||
| 150 | #define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ | ||
| 151 | #define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ | ||
| 152 | #define CKEN_TPM 19 /* < TPM clock enable */ | ||
| 153 | #define CKEN_UDC 20 /* < UDC clock enable */ | ||
| 154 | #define CKEN_BTUART 21 /* < BTUART clock enable */ | ||
| 155 | #define CKEN_FFUART 22 /* < FFUART clock enable */ | ||
| 156 | #define CKEN_STUART 23 /* < STUART clock enable */ | ||
| 157 | #define CKEN_AC97 24 /* < AC97 clock enable */ | ||
| 158 | #define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ | ||
| 159 | #define CKEN_SSP1 26 /* < SSP1 clock enable */ | ||
| 160 | #define CKEN_SSP2 27 /* < SSP2 clock enable */ | ||
| 161 | #define CKEN_SSP3 28 /* < SSP3 clock enable */ | ||
| 162 | #define CKEN_SSP4 29 /* < SSP4 clock enable */ | ||
| 163 | #define CKEN_MSL0 30 /* < MSL0 clock enable */ | ||
| 164 | #define CKEN_PWM0 32 /* < PWM[0] clock enable */ | ||
| 165 | #define CKEN_PWM1 33 /* < PWM[1] clock enable */ | ||
| 166 | #define CKEN_I2C 36 /* < I2C clock enable */ | ||
| 167 | #define CKEN_INTC 38 /* < Interrupt controller clock enable */ | ||
| 168 | #define CKEN_GPIO 39 /* < GPIO clock enable */ | ||
| 169 | #define CKEN_1WIRE 40 /* < 1-wire clock enable */ | ||
| 170 | #define CKEN_HSIO2 41 /* < HSIO2 clock enable */ | ||
| 171 | #define CKEN_MINI_IM 48 /* < Mini-IM */ | ||
| 172 | #define CKEN_MINI_LCD 49 /* < Mini LCD */ | ||
| 173 | |||
| 174 | #if defined(CONFIG_CPU_PXA310) | ||
| 175 | #define CKEN_MMC3 5 /* < MMC3 Clock Enable */ | ||
| 176 | #define CKEN_MVED 43 /* < MVED clock enable */ | ||
| 177 | #endif | ||
| 178 | |||
| 179 | /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ | ||
| 180 | #define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */ | ||
| 181 | #define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */ | ||
| 182 | |||
| 183 | #endif /* __ASM_ARCH_PXA3XX_REGS_H */ | ||
diff --git a/include/asm-arm/arch-pxa/pxa3xx_nand.h b/include/asm-arm/arch-pxa/pxa3xx_nand.h deleted file mode 100644 index eb4b190b6657..000000000000 --- a/include/asm-arm/arch-pxa/pxa3xx_nand.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_PXA3XX_NAND_H | ||
| 2 | #define __ASM_ARCH_PXA3XX_NAND_H | ||
| 3 | |||
| 4 | #include <linux/mtd/mtd.h> | ||
| 5 | #include <linux/mtd/partitions.h> | ||
| 6 | |||
| 7 | struct pxa3xx_nand_platform_data { | ||
| 8 | |||
| 9 | /* the data flash bus is shared between the Static Memory | ||
| 10 | * Controller and the Data Flash Controller, the arbiter | ||
| 11 | * controls the ownership of the bus | ||
| 12 | */ | ||
| 13 | int enable_arbiter; | ||
| 14 | |||
| 15 | struct mtd_partition *parts; | ||
| 16 | unsigned int nr_parts; | ||
| 17 | }; | ||
| 18 | |||
| 19 | extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info); | ||
| 20 | #endif /* __ASM_ARCH_PXA3XX_NAND_H */ | ||
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h deleted file mode 100644 index daf018d0c604..000000000000 --- a/include/asm-arm/arch-pxa/pxafb.h +++ /dev/null | |||
| @@ -1,151 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/pxafb.h | ||
| 3 | * | ||
| 4 | * Support for the xscale frame buffer. | ||
| 5 | * | ||
| 6 | * Author: Jean-Frederic Clere | ||
| 7 | * Created: Sep 22, 2003 | ||
| 8 | * Copyright: jfclere@sinix.net | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/fb.h> | ||
| 16 | #include <asm/arch/regs-lcd.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Supported LCD connections | ||
| 20 | * | ||
| 21 | * bits 0 - 3: for LCD panel type: | ||
| 22 | * | ||
| 23 | * STN - for passive matrix | ||
| 24 | * DSTN - for dual scan passive matrix | ||
| 25 | * TFT - for active matrix | ||
| 26 | * | ||
| 27 | * bits 4 - 9 : for bus width | ||
| 28 | * bits 10-17 : for AC Bias Pin Frequency | ||
| 29 | * bit 18 : for output enable polarity | ||
| 30 | * bit 19 : for pixel clock edge | ||
| 31 | */ | ||
| 32 | #define LCD_CONN_TYPE(_x) ((_x) & 0x0f) | ||
| 33 | #define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f) | ||
| 34 | |||
| 35 | #define LCD_TYPE_UNKNOWN 0 | ||
| 36 | #define LCD_TYPE_MONO_STN 1 | ||
| 37 | #define LCD_TYPE_MONO_DSTN 2 | ||
| 38 | #define LCD_TYPE_COLOR_STN 3 | ||
| 39 | #define LCD_TYPE_COLOR_DSTN 4 | ||
| 40 | #define LCD_TYPE_COLOR_TFT 5 | ||
| 41 | #define LCD_TYPE_SMART_PANEL 6 | ||
| 42 | #define LCD_TYPE_MAX 7 | ||
| 43 | |||
| 44 | #define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN) | ||
| 45 | #define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN) | ||
| 46 | #define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN) | ||
| 47 | #define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN) | ||
| 48 | #define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN) | ||
| 49 | #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT) | ||
| 50 | #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT) | ||
| 51 | #define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL) | ||
| 52 | #define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL) | ||
| 53 | #define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL) | ||
| 54 | |||
| 55 | #define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10) | ||
| 56 | #define LCD_BIAS_ACTIVE_HIGH (0 << 17) | ||
| 57 | #define LCD_BIAS_ACTIVE_LOW (1 << 17) | ||
| 58 | #define LCD_PCLK_EDGE_RISE (0 << 18) | ||
| 59 | #define LCD_PCLK_EDGE_FALL (1 << 18) | ||
| 60 | |||
| 61 | /* | ||
| 62 | * This structure describes the machine which we are running on. | ||
| 63 | * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine | ||
| 64 | * of linux/drivers/video/pxafb.c | ||
| 65 | */ | ||
| 66 | struct pxafb_mode_info { | ||
| 67 | u_long pixclock; | ||
| 68 | |||
| 69 | u_short xres; | ||
| 70 | u_short yres; | ||
| 71 | |||
| 72 | u_char bpp; | ||
| 73 | u_int cmap_greyscale:1, | ||
| 74 | depth:8, | ||
| 75 | unused:23; | ||
| 76 | |||
| 77 | /* Parallel Mode Timing */ | ||
| 78 | u_char hsync_len; | ||
| 79 | u_char left_margin; | ||
| 80 | u_char right_margin; | ||
| 81 | |||
| 82 | u_char vsync_len; | ||
| 83 | u_char upper_margin; | ||
| 84 | u_char lower_margin; | ||
| 85 | u_char sync; | ||
| 86 | |||
| 87 | /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details | ||
| 88 | * Note: | ||
| 89 | * 1. all parameters in nanosecond (ns) | ||
| 90 | * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits | ||
| 91 | * in pxa27x and pxa3xx, initialize them to the same value or | ||
| 92 | * the larger one will be used | ||
| 93 | * 3. same to {rd,wr}_pulse_width | ||
| 94 | */ | ||
| 95 | unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */ | ||
| 96 | unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */ | ||
| 97 | unsigned wr_pulse_width; /* L_PCLK_WR pulse width */ | ||
| 98 | unsigned rd_pulse_width; /* L_FCLK_RD pulse width */ | ||
| 99 | unsigned cmd_inh_time; /* Command Inhibit time between two writes */ | ||
| 100 | unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */ | ||
| 101 | }; | ||
| 102 | |||
| 103 | struct pxafb_mach_info { | ||
| 104 | struct pxafb_mode_info *modes; | ||
| 105 | unsigned int num_modes; | ||
| 106 | |||
| 107 | unsigned int lcd_conn; | ||
| 108 | |||
| 109 | u_int fixed_modes:1, | ||
| 110 | cmap_inverse:1, | ||
| 111 | cmap_static:1, | ||
| 112 | unused:29; | ||
| 113 | |||
| 114 | /* The following should be defined in LCCR0 | ||
| 115 | * LCCR0_Act or LCCR0_Pas Active or Passive | ||
| 116 | * LCCR0_Sngl or LCCR0_Dual Single/Dual panel | ||
| 117 | * LCCR0_Mono or LCCR0_Color Mono/Color | ||
| 118 | * LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode) | ||
| 119 | * LCCR0_DMADel(Tcpu) (optional) DMA request delay | ||
| 120 | * | ||
| 121 | * The following should not be defined in LCCR0: | ||
| 122 | * LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM | ||
| 123 | * LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB | ||
| 124 | */ | ||
| 125 | u_int lccr0; | ||
| 126 | /* The following should be defined in LCCR3 | ||
| 127 | * LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity | ||
| 128 | * LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type | ||
| 129 | * LCCR3_Acb(X) AB Bias pin frequency | ||
| 130 | * LCCR3_DPC (optional) Double Pixel Clock mode (untested) | ||
| 131 | * | ||
| 132 | * The following should not be defined in LCCR3 | ||
| 133 | * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp | ||
| 134 | */ | ||
| 135 | u_int lccr3; | ||
| 136 | /* The following should be defined in LCCR4 | ||
| 137 | * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2 | ||
| 138 | * | ||
| 139 | * All other bits in LCCR4 should be left alone. | ||
| 140 | */ | ||
| 141 | u_int lccr4; | ||
| 142 | void (*pxafb_backlight_power)(int); | ||
| 143 | void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); | ||
| 144 | void (*smart_update)(struct fb_info *); | ||
| 145 | }; | ||
| 146 | void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info); | ||
| 147 | void set_pxa_fb_parent(struct device *parent_dev); | ||
| 148 | unsigned long pxafb_get_hsync_time(struct device *dev); | ||
| 149 | |||
| 150 | extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); | ||
| 151 | extern int pxafb_smart_flush(struct fb_info *info); | ||
diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h deleted file mode 100644 index 820a189684a9..000000000000 --- a/include/asm-arm/arch-pxa/regs-lcd.h +++ /dev/null | |||
| @@ -1,180 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_REGS_LCD_H | ||
| 2 | #define __ASM_ARCH_REGS_LCD_H | ||
| 3 | |||
| 4 | #include <asm/arch/bitfield.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * LCD Controller Registers and Bits Definitions | ||
| 8 | */ | ||
| 9 | #define LCCR0 (0x000) /* LCD Controller Control Register 0 */ | ||
| 10 | #define LCCR1 (0x004) /* LCD Controller Control Register 1 */ | ||
| 11 | #define LCCR2 (0x008) /* LCD Controller Control Register 2 */ | ||
| 12 | #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ | ||
| 13 | #define LCCR4 (0x010) /* LCD Controller Control Register 4 */ | ||
| 14 | #define LCCR5 (0x014) /* LCD Controller Control Register 5 */ | ||
| 15 | #define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ | ||
| 16 | #define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ | ||
| 17 | #define LCSR (0x038) /* LCD Controller Status Register */ | ||
| 18 | #define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ | ||
| 19 | #define TMEDRGBR (0x040) /* TMED RGB Seed Register */ | ||
| 20 | #define TMEDCR (0x044) /* TMED Control Register */ | ||
| 21 | |||
| 22 | #define CMDCR (0x100) /* Command Control Register */ | ||
| 23 | #define PRSR (0x104) /* Panel Read Status Register */ | ||
| 24 | |||
| 25 | #define LCCR3_1BPP (0 << 24) | ||
| 26 | #define LCCR3_2BPP (1 << 24) | ||
| 27 | #define LCCR3_4BPP (2 << 24) | ||
| 28 | #define LCCR3_8BPP (3 << 24) | ||
| 29 | #define LCCR3_16BPP (4 << 24) | ||
| 30 | #define LCCR3_18BPP (5 << 24) | ||
| 31 | #define LCCR3_18BPP_P (6 << 24) | ||
| 32 | #define LCCR3_19BPP (7 << 24) | ||
| 33 | #define LCCR3_19BPP_P (1 << 29) | ||
| 34 | #define LCCR3_24BPP ((1 << 29) | (1 << 24)) | ||
| 35 | #define LCCR3_25BPP ((1 << 29) | (2 << 24)) | ||
| 36 | |||
| 37 | #define LCCR3_PDFOR_0 (0 << 30) | ||
| 38 | #define LCCR3_PDFOR_1 (1 << 30) | ||
| 39 | #define LCCR3_PDFOR_2 (2 << 30) | ||
| 40 | #define LCCR3_PDFOR_3 (3 << 30) | ||
| 41 | |||
| 42 | #define LCCR4_PAL_FOR_0 (0 << 15) | ||
| 43 | #define LCCR4_PAL_FOR_1 (1 << 15) | ||
| 44 | #define LCCR4_PAL_FOR_2 (2 << 15) | ||
| 45 | #define LCCR4_PAL_FOR_MASK (3 << 15) | ||
| 46 | |||
| 47 | #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ | ||
| 48 | #define FSADR0 (0x204) /* DMA Channel 0 Frame Source Address Register */ | ||
| 49 | #define FIDR0 (0x208) /* DMA Channel 0 Frame ID Register */ | ||
| 50 | #define LDCMD0 (0x20C) /* DMA Channel 0 Command Register */ | ||
| 51 | #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ | ||
| 52 | #define FSADR1 (0x214) /* DMA Channel 1 Frame Source Address Register */ | ||
| 53 | #define FIDR1 (0x218) /* DMA Channel 1 Frame ID Register */ | ||
| 54 | #define LDCMD1 (0x21C) /* DMA Channel 1 Command Register */ | ||
| 55 | #define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ | ||
| 56 | #define FSADR6 (0x264) /* DMA Channel 6 Frame Source Address Register */ | ||
| 57 | #define FIDR6 (0x268) /* DMA Channel 6 Frame ID Register */ | ||
| 58 | |||
| 59 | #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ | ||
| 60 | #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ | ||
| 61 | #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ | ||
| 62 | #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ | ||
| 63 | #define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */ | ||
| 64 | #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ | ||
| 65 | #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ | ||
| 66 | |||
| 67 | #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ | ||
| 68 | #define LCCR0_SFM (1 << 4) /* Start of frame mask */ | ||
| 69 | #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ | ||
| 70 | #define LCCR0_EFM (1 << 6) /* End of Frame mask */ | ||
| 71 | #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */ | ||
| 72 | #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ | ||
| 73 | #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ | ||
| 74 | #define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */ | ||
| 75 | #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */ | ||
| 76 | #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */ | ||
| 77 | #define LCCR0_DIS (1 << 10) /* LCD Disable */ | ||
| 78 | #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ | ||
| 79 | #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ | ||
| 80 | #define LCCR0_PDD_S 12 | ||
| 81 | #define LCCR0_BM (1 << 20) /* Branch mask */ | ||
| 82 | #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ | ||
| 83 | #define LCCR0_LCDT (1 << 22) /* LCD panel type */ | ||
| 84 | #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ | ||
| 85 | #define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ | ||
| 86 | #define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ | ||
| 87 | #define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ | ||
| 88 | |||
| 89 | #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ | ||
| 90 | #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) | ||
| 91 | |||
| 92 | #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ | ||
| 93 | #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW)) | ||
| 94 | |||
| 95 | #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */ | ||
| 96 | #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW)) | ||
| 97 | |||
| 98 | #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ | ||
| 99 | #define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW)) | ||
| 100 | |||
| 101 | #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ | ||
| 102 | #define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP)) | ||
| 103 | |||
| 104 | #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */ | ||
| 105 | #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW)) | ||
| 106 | |||
| 107 | #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ | ||
| 108 | #define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW)) | ||
| 109 | |||
| 110 | #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ | ||
| 111 | #define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW)) | ||
| 112 | |||
| 113 | #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ | ||
| 114 | #define LCCR3_API_S 16 | ||
| 115 | #define LCCR3_VSP (1 << 20) /* vertical sync polarity */ | ||
| 116 | #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ | ||
| 117 | #define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */ | ||
| 118 | #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ | ||
| 119 | #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ | ||
| 120 | |||
| 121 | #define LCCR3_OEP (1 << 23) /* Output Enable Polarity */ | ||
| 122 | #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ | ||
| 123 | #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ | ||
| 124 | |||
| 125 | #define LCCR3_DPC (1 << 27) /* double pixel clock mode */ | ||
| 126 | #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ | ||
| 127 | #define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD))) | ||
| 128 | |||
| 129 | #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ | ||
| 130 | #define LCCR3_Bpp(Bpp) (((Bpp) << FShft (LCCR3_BPP))) | ||
| 131 | |||
| 132 | #define LCCR3_ACB Fld (8, 8) /* AC Bias */ | ||
| 133 | #define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB))) | ||
| 134 | |||
| 135 | #define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */ | ||
| 136 | #define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */ | ||
| 137 | |||
| 138 | #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */ | ||
| 139 | #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */ | ||
| 140 | |||
| 141 | #define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */ | ||
| 142 | #define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */ | ||
| 143 | #define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */ | ||
| 144 | #define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */ | ||
| 145 | |||
| 146 | #define LCSR_LDD (1 << 0) /* LCD Disable Done */ | ||
| 147 | #define LCSR_SOF (1 << 1) /* Start of frame */ | ||
| 148 | #define LCSR_BER (1 << 2) /* Bus error */ | ||
| 149 | #define LCSR_ABC (1 << 3) /* AC Bias count */ | ||
| 150 | #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ | ||
| 151 | #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ | ||
| 152 | #define LCSR_OU (1 << 6) /* output FIFO underrun */ | ||
| 153 | #define LCSR_QD (1 << 7) /* quick disable */ | ||
| 154 | #define LCSR_EOF (1 << 8) /* end of frame */ | ||
| 155 | #define LCSR_BS (1 << 9) /* branch status */ | ||
| 156 | #define LCSR_SINT (1 << 10) /* subsequent interrupt */ | ||
| 157 | #define LCSR_RD_ST (1 << 11) /* read status */ | ||
| 158 | #define LCSR_CMD_INT (1 << 12) /* command interrupt */ | ||
| 159 | |||
| 160 | #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ | ||
| 161 | |||
| 162 | /* smartpanel related */ | ||
| 163 | #define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ | ||
| 164 | #define PRSR_A0 (1 << 8) /* Read Data Source */ | ||
| 165 | #define PRSR_ST_OK (1 << 9) /* Status OK */ | ||
| 166 | #define PRSR_CON_NT (1 << 10) /* Continue to Next Command */ | ||
| 167 | |||
| 168 | #define SMART_CMD_A0 (0x1 << 8) | ||
| 169 | #define SMART_CMD_READ_STATUS_REG (0x0 << 9) | ||
| 170 | #define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0) | ||
| 171 | #define SMART_CMD_WRITE_COMMAND (0x1 << 9) | ||
| 172 | #define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0) | ||
| 173 | #define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0) | ||
| 174 | #define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9) | ||
| 175 | #define SMART_CMD_NOOP (0x4 << 9) | ||
| 176 | #define SMART_CMD_INTERRUPT (0x5 << 9) | ||
| 177 | |||
| 178 | #define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) | ||
| 179 | #define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) | ||
| 180 | #endif /* __ASM_ARCH_REGS_LCD_H */ | ||
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h deleted file mode 100644 index 3c04cde2cf1f..000000000000 --- a/include/asm-arm/arch-pxa/regs-ssp.h +++ /dev/null | |||
| @@ -1,127 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_REGS_SSP_H | ||
| 2 | #define __ASM_ARCH_REGS_SSP_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * SSP Serial Port Registers | ||
| 6 | * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. | ||
| 7 | * PXA255, PXA26x and PXA27x have extra ports, registers and bits. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define SSCR0 (0x00) /* SSP Control Register 0 */ | ||
| 11 | #define SSCR1 (0x04) /* SSP Control Register 1 */ | ||
| 12 | #define SSSR (0x08) /* SSP Status Register */ | ||
| 13 | #define SSITR (0x0C) /* SSP Interrupt Test Register */ | ||
| 14 | #define SSDR (0x10) /* SSP Data Write/Data Read Register */ | ||
| 15 | |||
| 16 | #define SSTO (0x28) /* SSP Time Out Register */ | ||
| 17 | #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ | ||
| 18 | #define SSTSA (0x30) /* SSP Tx Timeslot Active */ | ||
| 19 | #define SSRSA (0x34) /* SSP Rx Timeslot Active */ | ||
| 20 | #define SSTSS (0x38) /* SSP Timeslot Status */ | ||
| 21 | #define SSACD (0x3C) /* SSP Audio Clock Divider */ | ||
| 22 | |||
| 23 | #if defined(CONFIG_PXA3xx) | ||
| 24 | #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ | ||
| 25 | #endif | ||
| 26 | |||
| 27 | /* Common PXA2xx bits first */ | ||
| 28 | #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ | ||
| 29 | #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ | ||
| 30 | #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ | ||
| 31 | #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ | ||
| 32 | #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ | ||
| 33 | #define SSCR0_National (0x2 << 4) /* National Microwire */ | ||
| 34 | #define SSCR0_ECS (1 << 6) /* External clock select */ | ||
| 35 | #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ | ||
| 36 | |||
| 37 | #if defined(CONFIG_PXA25x) | ||
| 38 | #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ | ||
| 39 | #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ | ||
| 40 | |||
| 41 | #elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 42 | #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ | ||
| 43 | #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ | ||
| 44 | #define SSCR0_EDSS (1 << 20) /* Extended data size select */ | ||
| 45 | #define SSCR0_NCS (1 << 21) /* Network clock select */ | ||
| 46 | #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ | ||
| 47 | #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ | ||
| 48 | #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ | ||
| 49 | #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ | ||
| 50 | #define SSCR0_ADC (1 << 30) /* Audio clock select */ | ||
| 51 | #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ | ||
| 52 | #endif | ||
| 53 | |||
| 54 | #if defined(CONFIG_PXA3xx) | ||
| 55 | #define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ | ||
| 56 | #endif | ||
| 57 | |||
| 58 | #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ | ||
| 59 | #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ | ||
| 60 | #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ | ||
| 61 | #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ | ||
| 62 | #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ | ||
| 63 | #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ | ||
| 64 | #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ | ||
| 65 | #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ | ||
| 66 | #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ | ||
| 67 | #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ | ||
| 68 | |||
| 69 | #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ | ||
| 70 | #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ | ||
| 71 | #define SSSR_BSY (1 << 4) /* SSP Busy */ | ||
| 72 | #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ | ||
| 73 | #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ | ||
| 74 | #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ | ||
| 75 | |||
| 76 | #define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */ | ||
| 77 | #define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */ | ||
| 78 | #define SSCR0_NCS (1 << 21) /* Network Clock Select */ | ||
| 79 | #define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */ | ||
| 80 | |||
| 81 | /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ | ||
| 82 | #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ | ||
| 83 | #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ | ||
| 84 | #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ | ||
| 85 | #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ | ||
| 86 | #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ | ||
| 87 | #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ | ||
| 88 | #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ | ||
| 89 | #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ | ||
| 90 | #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ | ||
| 91 | #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ | ||
| 92 | #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ | ||
| 93 | #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ | ||
| 94 | #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ | ||
| 95 | #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ | ||
| 96 | #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ | ||
| 97 | #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */ | ||
| 98 | #define SSCR1_IFS (1 << 16) /* Invert Frame Signal */ | ||
| 99 | #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ | ||
| 100 | #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ | ||
| 101 | |||
| 102 | #define SSSR_BCE (1 << 23) /* Bit Count Error */ | ||
| 103 | #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ | ||
| 104 | #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ | ||
| 105 | #define SSSR_EOC (1 << 20) /* End Of Chain */ | ||
| 106 | #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ | ||
| 107 | #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ | ||
| 108 | |||
| 109 | #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ | ||
| 110 | #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ | ||
| 111 | #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ | ||
| 112 | #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ | ||
| 113 | #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ | ||
| 114 | #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ | ||
| 115 | #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ | ||
| 116 | #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ | ||
| 117 | #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ | ||
| 118 | |||
| 119 | #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ | ||
| 120 | #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ | ||
| 121 | #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ | ||
| 122 | #if defined(CONFIG_PXA3xx) | ||
| 123 | #define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ | ||
| 124 | #endif | ||
| 125 | |||
| 126 | |||
| 127 | #endif /* __ASM_ARCH_REGS_SSP_H */ | ||
diff --git a/include/asm-arm/arch-pxa/sharpsl.h b/include/asm-arm/arch-pxa/sharpsl.h deleted file mode 100644 index 3b1d4a72d4d1..000000000000 --- a/include/asm-arm/arch-pxa/sharpsl.h +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * SharpSL SSP Driver | ||
| 3 | */ | ||
| 4 | |||
| 5 | unsigned long corgi_ssp_ads7846_putget(unsigned long); | ||
| 6 | unsigned long corgi_ssp_ads7846_get(void); | ||
| 7 | void corgi_ssp_ads7846_put(unsigned long data); | ||
| 8 | void corgi_ssp_ads7846_lock(void); | ||
| 9 | void corgi_ssp_ads7846_unlock(void); | ||
| 10 | void corgi_ssp_lcdtg_send (unsigned char adrs, unsigned char data); | ||
| 11 | void corgi_ssp_blduty_set(int duty); | ||
| 12 | int corgi_ssp_max1111_get(unsigned long data); | ||
| 13 | |||
| 14 | /* | ||
| 15 | * SharpSL Touchscreen Driver | ||
| 16 | */ | ||
| 17 | |||
| 18 | struct corgits_machinfo { | ||
| 19 | unsigned long (*get_hsync_invperiod)(void); | ||
| 20 | void (*put_hsync)(void); | ||
| 21 | void (*wait_hsync)(void); | ||
| 22 | }; | ||
| 23 | |||
| 24 | |||
| 25 | /* | ||
| 26 | * SharpSL Backlight | ||
| 27 | */ | ||
| 28 | extern void corgibl_limit_intensity(int limit); | ||
| 29 | |||
| 30 | |||
| 31 | /* | ||
| 32 | * SharpSL Battery/PM Driver | ||
| 33 | */ | ||
| 34 | extern void sharpsl_battery_kick(void); | ||
diff --git a/include/asm-arm/arch-pxa/spitz.h b/include/asm-arm/arch-pxa/spitz.h deleted file mode 100644 index bd14365f7ed5..000000000000 --- a/include/asm-arm/arch-pxa/spitz.h +++ /dev/null | |||
| @@ -1,158 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Hardware specific definitions for SL-Cx000 series of PDAs | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Alexander Wykes | ||
| 5 | * Copyright (c) 2005 Richard Purdie | ||
| 6 | * | ||
| 7 | * Based on Sharp's 2.4 kernel patches | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | #ifndef __ASM_ARCH_SPITZ_H | ||
| 15 | #define __ASM_ARCH_SPITZ_H 1 | ||
| 16 | #endif | ||
| 17 | |||
| 18 | #include <linux/fb.h> | ||
| 19 | |||
| 20 | /* Spitz/Akita GPIOs */ | ||
| 21 | |||
| 22 | #define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */ | ||
| 23 | #define SPITZ_GPIO_RESET (1) | ||
| 24 | #define SPITZ_GPIO_nSD_DETECT (9) | ||
| 25 | #define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */ | ||
| 26 | #define SPITZ_GPIO_AK_INT (13) /* Remote Control */ | ||
| 27 | #define SPITZ_GPIO_ADS7846_CS (14) | ||
| 28 | #define SPITZ_GPIO_SYNC (16) | ||
| 29 | #define SPITZ_GPIO_MAX1111_CS (20) | ||
| 30 | #define SPITZ_GPIO_FATAL_BAT (21) | ||
| 31 | #define SPITZ_GPIO_HSYNC (22) | ||
| 32 | #define SPITZ_GPIO_nSD_CLK (32) | ||
| 33 | #define SPITZ_GPIO_USB_DEVICE (35) | ||
| 34 | #define SPITZ_GPIO_USB_HOST (37) | ||
| 35 | #define SPITZ_GPIO_USB_CONNECT (41) | ||
| 36 | #define SPITZ_GPIO_LCDCON_CS (53) | ||
| 37 | #define SPITZ_GPIO_nPCE (54) | ||
| 38 | #define SPITZ_GPIO_nSD_WP (81) | ||
| 39 | #define SPITZ_GPIO_ON_RESET (89) | ||
| 40 | #define SPITZ_GPIO_BAT_COVER (90) | ||
| 41 | #define SPITZ_GPIO_CF_CD (94) | ||
| 42 | #define SPITZ_GPIO_ON_KEY (95) | ||
| 43 | #define SPITZ_GPIO_SWA (97) | ||
| 44 | #define SPITZ_GPIO_SWB (96) | ||
| 45 | #define SPITZ_GPIO_CHRG_FULL (101) | ||
| 46 | #define SPITZ_GPIO_CO (101) | ||
| 47 | #define SPITZ_GPIO_CF_IRQ (105) | ||
| 48 | #define SPITZ_GPIO_AC_IN (115) | ||
| 49 | #define SPITZ_GPIO_HP_IN (116) | ||
| 50 | |||
| 51 | /* Spitz Only GPIOs */ | ||
| 52 | |||
| 53 | #define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */ | ||
| 54 | #define SPITZ_GPIO_CF2_CD (93) | ||
| 55 | |||
| 56 | |||
| 57 | /* Spitz/Akita Keyboard Definitions */ | ||
| 58 | |||
| 59 | #define SPITZ_KEY_STROBE_NUM (11) | ||
| 60 | #define SPITZ_KEY_SENSE_NUM (7) | ||
| 61 | #define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000 | ||
| 62 | #define SPITZ_GPIO_G1_STROBE_BIT 0x00100000 | ||
| 63 | #define SPITZ_GPIO_G2_STROBE_BIT 0x01000000 | ||
| 64 | #define SPITZ_GPIO_G3_STROBE_BIT 0x00041880 | ||
| 65 | #define SPITZ_GPIO_G0_SENSE_BIT 0x00021000 | ||
| 66 | #define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4 | ||
| 67 | #define SPITZ_GPIO_G2_SENSE_BIT 0x08000000 | ||
| 68 | #define SPITZ_GPIO_G3_SENSE_BIT 0x00000000 | ||
| 69 | |||
| 70 | #define SPITZ_GPIO_KEY_STROBE0 88 | ||
| 71 | #define SPITZ_GPIO_KEY_STROBE1 23 | ||
| 72 | #define SPITZ_GPIO_KEY_STROBE2 24 | ||
| 73 | #define SPITZ_GPIO_KEY_STROBE3 25 | ||
| 74 | #define SPITZ_GPIO_KEY_STROBE4 26 | ||
| 75 | #define SPITZ_GPIO_KEY_STROBE5 27 | ||
| 76 | #define SPITZ_GPIO_KEY_STROBE6 52 | ||
| 77 | #define SPITZ_GPIO_KEY_STROBE7 103 | ||
| 78 | #define SPITZ_GPIO_KEY_STROBE8 107 | ||
| 79 | #define SPITZ_GPIO_KEY_STROBE9 108 | ||
| 80 | #define SPITZ_GPIO_KEY_STROBE10 114 | ||
| 81 | |||
| 82 | #define SPITZ_GPIO_KEY_SENSE0 12 | ||
| 83 | #define SPITZ_GPIO_KEY_SENSE1 17 | ||
| 84 | #define SPITZ_GPIO_KEY_SENSE2 91 | ||
| 85 | #define SPITZ_GPIO_KEY_SENSE3 34 | ||
| 86 | #define SPITZ_GPIO_KEY_SENSE4 36 | ||
| 87 | #define SPITZ_GPIO_KEY_SENSE5 38 | ||
| 88 | #define SPITZ_GPIO_KEY_SENSE6 39 | ||
| 89 | |||
| 90 | |||
| 91 | /* Spitz Scoop Device (No. 1) GPIOs */ | ||
| 92 | /* Suspend States in comments */ | ||
| 93 | #define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */ | ||
| 94 | #define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */ | ||
| 95 | #define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */ | ||
| 96 | #define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */ | ||
| 97 | #define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */ | ||
| 98 | #define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */ | ||
| 99 | #define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */ | ||
| 100 | #define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */ | ||
| 101 | #define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */ | ||
| 102 | |||
| 103 | #define SPITZ_SCP_IO_DIR (SPITZ_SCP_LED_GREEN | SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \ | ||
| 104 | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_LED_ORANGE | \ | ||
| 105 | SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) | ||
| 106 | #define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R) | ||
| 107 | #define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) | ||
| 108 | #define SPITZ_SCP_SUS_SET 0 | ||
| 109 | |||
| 110 | /* Spitz Scoop Device (No. 2) GPIOs */ | ||
| 111 | /* Suspend States in comments */ | ||
| 112 | #define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */ | ||
| 113 | #define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */ | ||
| 114 | #define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */ | ||
| 115 | #define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */ | ||
| 116 | #define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */ | ||
| 117 | #define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */ | ||
| 118 | #define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */ | ||
| 119 | #define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */ | ||
| 120 | #define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */ | ||
| 121 | |||
| 122 | #define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \ | ||
| 123 | SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ | ||
| 124 | SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) | ||
| 125 | |||
| 126 | #define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1) | ||
| 127 | #define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ | ||
| 128 | SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) | ||
| 129 | #define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1) | ||
| 130 | |||
| 131 | |||
| 132 | /* Spitz IRQ Definitions */ | ||
| 133 | |||
| 134 | #define SPITZ_IRQ_GPIO_KEY_INT IRQ_GPIO(SPITZ_GPIO_KEY_INT) | ||
| 135 | #define SPITZ_IRQ_GPIO_AC_IN IRQ_GPIO(SPITZ_GPIO_AC_IN) | ||
| 136 | #define SPITZ_IRQ_GPIO_AK_INT IRQ_GPIO(SPITZ_GPIO_AK_INT) | ||
| 137 | #define SPITZ_IRQ_GPIO_HP_IN IRQ_GPIO(SPITZ_GPIO_HP_IN) | ||
| 138 | #define SPITZ_IRQ_GPIO_TP_INT IRQ_GPIO(SPITZ_GPIO_TP_INT) | ||
| 139 | #define SPITZ_IRQ_GPIO_SYNC IRQ_GPIO(SPITZ_GPIO_SYNC) | ||
| 140 | #define SPITZ_IRQ_GPIO_ON_KEY IRQ_GPIO(SPITZ_GPIO_ON_KEY) | ||
| 141 | #define SPITZ_IRQ_GPIO_SWA IRQ_GPIO(SPITZ_GPIO_SWA) | ||
| 142 | #define SPITZ_IRQ_GPIO_SWB IRQ_GPIO(SPITZ_GPIO_SWB) | ||
| 143 | #define SPITZ_IRQ_GPIO_BAT_COVER IRQ_GPIO(SPITZ_GPIO_BAT_COVER) | ||
| 144 | #define SPITZ_IRQ_GPIO_FATAL_BAT IRQ_GPIO(SPITZ_GPIO_FATAL_BAT) | ||
| 145 | #define SPITZ_IRQ_GPIO_CO IRQ_GPIO(SPITZ_GPIO_CO) | ||
| 146 | #define SPITZ_IRQ_GPIO_CF_IRQ IRQ_GPIO(SPITZ_GPIO_CF_IRQ) | ||
| 147 | #define SPITZ_IRQ_GPIO_CF_CD IRQ_GPIO(SPITZ_GPIO_CF_CD) | ||
| 148 | #define SPITZ_IRQ_GPIO_CF2_IRQ IRQ_GPIO(SPITZ_GPIO_CF2_IRQ) | ||
| 149 | #define SPITZ_IRQ_GPIO_nSD_INT IRQ_GPIO(SPITZ_GPIO_nSD_INT) | ||
| 150 | #define SPITZ_IRQ_GPIO_nSD_DETECT IRQ_GPIO(SPITZ_GPIO_nSD_DETECT) | ||
| 151 | |||
| 152 | /* | ||
| 153 | * Shared data structures | ||
| 154 | */ | ||
| 155 | extern struct platform_device spitzscoop_device; | ||
| 156 | extern struct platform_device spitzscoop2_device; | ||
| 157 | extern struct platform_device spitzssp_device; | ||
| 158 | extern struct sharpsl_charger_machinfo spitz_pm_machinfo; | ||
diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h deleted file mode 100644 index a012882c9ee6..000000000000 --- a/include/asm-arm/arch-pxa/ssp.h +++ /dev/null | |||
| @@ -1,83 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * ssp.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 Russell King, All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This driver supports the following PXA CPU/SSP ports:- | ||
| 11 | * | ||
| 12 | * PXA250 SSP | ||
| 13 | * PXA255 SSP, NSSP | ||
| 14 | * PXA26x SSP, NSSP, ASSP | ||
| 15 | * PXA27x SSP1, SSP2, SSP3 | ||
| 16 | * PXA3xx SSP1, SSP2, SSP3, SSP4 | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_SSP_H | ||
| 20 | #define __ASM_ARCH_SSP_H | ||
| 21 | |||
| 22 | #include <linux/list.h> | ||
| 23 | |||
| 24 | enum pxa_ssp_type { | ||
| 25 | SSP_UNDEFINED = 0, | ||
| 26 | PXA25x_SSP, /* pxa 210, 250, 255, 26x */ | ||
| 27 | PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ | ||
| 28 | PXA27x_SSP, | ||
| 29 | }; | ||
| 30 | |||
| 31 | struct ssp_device { | ||
| 32 | struct platform_device *pdev; | ||
| 33 | struct list_head node; | ||
| 34 | |||
| 35 | struct clk *clk; | ||
| 36 | void __iomem *mmio_base; | ||
| 37 | unsigned long phys_base; | ||
| 38 | |||
| 39 | const char *label; | ||
| 40 | int port_id; | ||
| 41 | int type; | ||
| 42 | int use_count; | ||
| 43 | int irq; | ||
| 44 | int drcmr_rx; | ||
| 45 | int drcmr_tx; | ||
| 46 | }; | ||
| 47 | |||
| 48 | /* | ||
| 49 | * SSP initialisation flags | ||
| 50 | */ | ||
| 51 | #define SSP_NO_IRQ 0x1 /* don't register an irq handler in SSP driver */ | ||
| 52 | |||
| 53 | struct ssp_state { | ||
| 54 | u32 cr0; | ||
| 55 | u32 cr1; | ||
| 56 | u32 to; | ||
| 57 | u32 psp; | ||
| 58 | }; | ||
| 59 | |||
| 60 | struct ssp_dev { | ||
| 61 | struct ssp_device *ssp; | ||
| 62 | u32 port; | ||
| 63 | u32 mode; | ||
| 64 | u32 flags; | ||
| 65 | u32 psp_flags; | ||
| 66 | u32 speed; | ||
| 67 | int irq; | ||
| 68 | }; | ||
| 69 | |||
| 70 | int ssp_write_word(struct ssp_dev *dev, u32 data); | ||
| 71 | int ssp_read_word(struct ssp_dev *dev, u32 *data); | ||
| 72 | int ssp_flush(struct ssp_dev *dev); | ||
| 73 | void ssp_enable(struct ssp_dev *dev); | ||
| 74 | void ssp_disable(struct ssp_dev *dev); | ||
| 75 | void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp); | ||
| 76 | void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp); | ||
| 77 | int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags); | ||
| 78 | int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); | ||
| 79 | void ssp_exit(struct ssp_dev *dev); | ||
| 80 | |||
| 81 | struct ssp_device *ssp_request(int port, const char *label); | ||
| 82 | void ssp_free(struct ssp_device *); | ||
| 83 | #endif /* __ASM_ARCH_SSP_H */ | ||
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h deleted file mode 100644 index 6956fc5235f8..000000000000 --- a/include/asm-arm/arch-pxa/system.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/system.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Jun 15, 2001 | ||
| 6 | * Copyright: MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <asm/proc-fns.h> | ||
| 14 | #include "hardware.h" | ||
| 15 | #include "pxa2xx-regs.h" | ||
| 16 | #include "pxa-regs.h" | ||
| 17 | |||
| 18 | static inline void arch_idle(void) | ||
| 19 | { | ||
| 20 | cpu_do_idle(); | ||
| 21 | } | ||
| 22 | |||
| 23 | |||
| 24 | void arch_reset(char mode); | ||
diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h deleted file mode 100644 index 8d882f0b6a16..000000000000 --- a/include/asm-arm/arch-pxa/timex.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/timex.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Jun 15, 2001 | ||
| 6 | * Copyright: MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | |||
| 14 | #if defined(CONFIG_PXA25x) | ||
| 15 | /* PXA250/210 timer base */ | ||
| 16 | #define CLOCK_TICK_RATE 3686400 | ||
| 17 | #elif defined(CONFIG_PXA27x) | ||
| 18 | /* PXA27x timer base */ | ||
| 19 | #ifdef CONFIG_MACH_MAINSTONE | ||
| 20 | #define CLOCK_TICK_RATE 3249600 | ||
| 21 | #else | ||
| 22 | #define CLOCK_TICK_RATE 3250000 | ||
| 23 | #endif | ||
| 24 | #else | ||
| 25 | #define CLOCK_TICK_RATE 3250000 | ||
| 26 | #endif | ||
diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h deleted file mode 100644 index a72803f0461b..000000000000 --- a/include/asm-arm/arch-pxa/tosa.h +++ /dev/null | |||
| @@ -1,198 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Hardware specific definitions for Sharp SL-C6000x series of PDAs | ||
| 3 | * | ||
| 4 | * Copyright (c) 2005 Dirk Opfer | ||
| 5 | * | ||
| 6 | * Based on Sharp's 2.4 kernel patches | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #ifndef _ASM_ARCH_TOSA_H_ | ||
| 14 | #define _ASM_ARCH_TOSA_H_ 1 | ||
| 15 | |||
| 16 | /* TOSA Chip selects */ | ||
| 17 | #define TOSA_LCDC_PHYS PXA_CS4_PHYS | ||
| 18 | /* Internel Scoop */ | ||
| 19 | #define TOSA_CF_PHYS (PXA_CS2_PHYS + 0x00800000) | ||
| 20 | /* Jacket Scoop */ | ||
| 21 | #define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000) | ||
| 22 | |||
| 23 | /* | ||
| 24 | * SCOOP2 internal GPIOs | ||
| 25 | */ | ||
| 26 | #define TOSA_SCOOP_GPIO_BASE NR_BUILTIN_GPIO | ||
| 27 | #define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 | ||
| 28 | #define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1) | ||
| 29 | #define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2) | ||
| 30 | #define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3) | ||
| 31 | #define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4) | ||
| 32 | #define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16 | ||
| 33 | #define TOSA_GPIO_BT_RESET (TOSA_SCOOP_GPIO_BASE + 6) | ||
| 34 | #define TOSA_GPIO_BT_PWR_EN (TOSA_SCOOP_GPIO_BASE + 7) | ||
| 35 | #define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 | ||
| 36 | |||
| 37 | /* GPIO Direction 1 : output mode / 0:input mode */ | ||
| 38 | #define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \ | ||
| 39 | TOSA_SCOOP_AUD_PWR_ON) | ||
| 40 | |||
| 41 | /* | ||
| 42 | * SCOOP2 jacket GPIOs | ||
| 43 | */ | ||
| 44 | #define TOSA_SCOOP_JC_GPIO_BASE (NR_BUILTIN_GPIO + 12) | ||
| 45 | #define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0) | ||
| 46 | #define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1) | ||
| 47 | #define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2) | ||
| 48 | #define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3) | ||
| 49 | #define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4) | ||
| 50 | #define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5) | ||
| 51 | #define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 | ||
| 52 | #define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7) | ||
| 53 | #define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 | ||
| 54 | |||
| 55 | /* GPIO Direction 1 : output mode / 0:input mode */ | ||
| 56 | #define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL) | ||
| 57 | |||
| 58 | /* | ||
| 59 | * TC6393XB GPIOs | ||
| 60 | */ | ||
| 61 | #define TOSA_TC6393XB_GPIO_BASE (NR_BUILTIN_GPIO + 2 * 12) | ||
| 62 | #define TOSA_TC6393XB_GPIO(i) (TOSA_TC6393XB_GPIO_BASE + (i)) | ||
| 63 | #define TOSA_TC6393XB_GPIO_BIT(gpio) (1 << (gpio - TOSA_TC6393XB_GPIO_BASE)) | ||
| 64 | |||
| 65 | #define TOSA_GPIO_TG_ON (TOSA_TC6393XB_GPIO_BASE + 0) | ||
| 66 | #define TOSA_GPIO_L_MUTE (TOSA_TC6393XB_GPIO_BASE + 1) | ||
| 67 | #define TOSA_GPIO_BL_C20MA (TOSA_TC6393XB_GPIO_BASE + 3) | ||
| 68 | #define TOSA_GPIO_CARD_VCC_ON (TOSA_TC6393XB_GPIO_BASE + 4) | ||
| 69 | #define TOSA_GPIO_CHARGE_OFF (TOSA_TC6393XB_GPIO_BASE + 6) | ||
| 70 | #define TOSA_GPIO_CHARGE_OFF_JC (TOSA_TC6393XB_GPIO_BASE + 7) | ||
| 71 | #define TOSA_GPIO_BAT0_V_ON (TOSA_TC6393XB_GPIO_BASE + 9) | ||
| 72 | #define TOSA_GPIO_BAT1_V_ON (TOSA_TC6393XB_GPIO_BASE + 10) | ||
| 73 | #define TOSA_GPIO_BU_CHRG_ON (TOSA_TC6393XB_GPIO_BASE + 11) | ||
| 74 | #define TOSA_GPIO_BAT_SW_ON (TOSA_TC6393XB_GPIO_BASE + 12) | ||
| 75 | #define TOSA_GPIO_BAT0_TH_ON (TOSA_TC6393XB_GPIO_BASE + 14) | ||
| 76 | #define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15) | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Timing Generator | ||
| 80 | */ | ||
| 81 | #define TG_PNLCTL 0x00 | ||
| 82 | #define TG_TPOSCTL 0x01 | ||
| 83 | #define TG_DUTYCTL 0x02 | ||
| 84 | #define TG_GPOSR 0x03 | ||
| 85 | #define TG_GPODR1 0x04 | ||
| 86 | #define TG_GPODR2 0x05 | ||
| 87 | #define TG_PINICTL 0x06 | ||
| 88 | #define TG_HPOSCTL 0x07 | ||
| 89 | |||
| 90 | /* | ||
| 91 | * PXA GPIOs | ||
| 92 | */ | ||
| 93 | #define TOSA_GPIO_POWERON (0) | ||
| 94 | #define TOSA_GPIO_RESET (1) | ||
| 95 | #define TOSA_GPIO_AC_IN (2) | ||
| 96 | #define TOSA_GPIO_RECORD_BTN (3) | ||
| 97 | #define TOSA_GPIO_SYNC (4) /* Cradle SYNC Button */ | ||
| 98 | #define TOSA_GPIO_USB_IN (5) | ||
| 99 | #define TOSA_GPIO_JACKET_DETECT (7) | ||
| 100 | #define TOSA_GPIO_nSD_DETECT (9) | ||
| 101 | #define TOSA_GPIO_nSD_INT (10) | ||
| 102 | #define TOSA_GPIO_TC6393XB_CLK (11) | ||
| 103 | #define TOSA_GPIO_BAT1_CRG (12) | ||
| 104 | #define TOSA_GPIO_CF_CD (13) | ||
| 105 | #define TOSA_GPIO_BAT0_CRG (14) | ||
| 106 | #define TOSA_GPIO_TC6393XB_INT (15) | ||
| 107 | #define TOSA_GPIO_BAT0_LOW (17) | ||
| 108 | #define TOSA_GPIO_TC6393XB_RDY (18) | ||
| 109 | #define TOSA_GPIO_ON_RESET (19) | ||
| 110 | #define TOSA_GPIO_EAR_IN (20) | ||
| 111 | #define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */ | ||
| 112 | #define TOSA_GPIO_ON_KEY (22) | ||
| 113 | #define TOSA_GPIO_VGA_LINE (27) | ||
| 114 | #define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */ | ||
| 115 | #define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */ | ||
| 116 | #define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */ | ||
| 117 | #define TOSA_GPIO_IRDA_TX (47) | ||
| 118 | #define TOSA_GPIO_TG_SPI_SCLK (81) | ||
| 119 | #define TOSA_GPIO_TG_SPI_CS (82) | ||
| 120 | #define TOSA_GPIO_TG_SPI_MOSI (83) | ||
| 121 | #define TOSA_GPIO_BAT1_LOW (84) | ||
| 122 | |||
| 123 | #define TOSA_GPIO_HP_IN GPIO_EAR_IN | ||
| 124 | |||
| 125 | #define TOSA_GPIO_MAIN_BAT_LOW GPIO_BAT0_LOW | ||
| 126 | |||
| 127 | #define TOSA_KEY_STROBE_NUM (11) | ||
| 128 | #define TOSA_KEY_SENSE_NUM (7) | ||
| 129 | |||
| 130 | #define TOSA_GPIO_HIGH_STROBE_BIT (0xfc000000) | ||
| 131 | #define TOSA_GPIO_LOW_STROBE_BIT (0x0000001f) | ||
| 132 | #define TOSA_GPIO_ALL_SENSE_BIT (0x00000fe0) | ||
| 133 | #define TOSA_GPIO_ALL_SENSE_RSHIFT (5) | ||
| 134 | #define TOSA_GPIO_STROBE_BIT(a) GPIO_bit(58+(a)) | ||
| 135 | #define TOSA_GPIO_SENSE_BIT(a) GPIO_bit(69+(a)) | ||
| 136 | #define TOSA_GAFR_HIGH_STROBE_BIT (0xfff00000) | ||
| 137 | #define TOSA_GAFR_LOW_STROBE_BIT (0x000003ff) | ||
| 138 | #define TOSA_GAFR_ALL_SENSE_BIT (0x00fffc00) | ||
| 139 | #define TOSA_GPIO_KEY_SENSE(a) (69+(a)) | ||
| 140 | #define TOSA_GPIO_KEY_STROBE(a) (58+(a)) | ||
| 141 | |||
| 142 | /* | ||
| 143 | * Interrupts | ||
| 144 | */ | ||
| 145 | #define TOSA_IRQ_GPIO_WAKEUP IRQ_GPIO(TOSA_GPIO_WAKEUP) | ||
| 146 | #define TOSA_IRQ_GPIO_AC_IN IRQ_GPIO(TOSA_GPIO_AC_IN) | ||
| 147 | #define TOSA_IRQ_GPIO_RECORD_BTN IRQ_GPIO(TOSA_GPIO_RECORD_BTN) | ||
| 148 | #define TOSA_IRQ_GPIO_SYNC IRQ_GPIO(TOSA_GPIO_SYNC) | ||
| 149 | #define TOSA_IRQ_GPIO_USB_IN IRQ_GPIO(TOSA_GPIO_USB_IN) | ||
| 150 | #define TOSA_IRQ_GPIO_JACKET_DETECT IRQ_GPIO(TOSA_GPIO_JACKET_DETECT) | ||
| 151 | #define TOSA_IRQ_GPIO_nSD_INT IRQ_GPIO(TOSA_GPIO_nSD_INT) | ||
| 152 | #define TOSA_IRQ_GPIO_nSD_DETECT IRQ_GPIO(TOSA_GPIO_nSD_DETECT) | ||
| 153 | #define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) | ||
| 154 | #define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) | ||
| 155 | #define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) | ||
| 156 | #define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT) | ||
| 157 | #define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) | ||
| 158 | #define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) | ||
| 159 | #define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) | ||
| 160 | #define TOSA_IRQ_GPIO_ON_KEY IRQ_GPIO(TOSA_GPIO_ON_KEY) | ||
| 161 | #define TOSA_IRQ_GPIO_VGA_LINE IRQ_GPIO(TOSA_GPIO_VGA_LINE) | ||
| 162 | #define TOSA_IRQ_GPIO_TP_INT IRQ_GPIO(TOSA_GPIO_TP_INT) | ||
| 163 | #define TOSA_IRQ_GPIO_JC_CF_IRQ IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ) | ||
| 164 | #define TOSA_IRQ_GPIO_BAT_LOCKED IRQ_GPIO(TOSA_GPIO_BAT_LOCKED) | ||
| 165 | #define TOSA_IRQ_GPIO_BAT1_LOW IRQ_GPIO(TOSA_GPIO_BAT1_LOW) | ||
| 166 | #define TOSA_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(69+(a)) | ||
| 167 | |||
| 168 | #define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW) | ||
| 169 | |||
| 170 | #define TOSA_KEY_SYNC KEY_102ND /* ??? */ | ||
| 171 | |||
| 172 | #ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES | ||
| 173 | #define TOSA_KEY_RECORD KEY_YEN | ||
| 174 | #define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA | ||
| 175 | #define TOSA_KEY_CANCEL KEY_ESC | ||
| 176 | #define TOSA_KEY_CENTER KEY_HIRAGANA | ||
| 177 | #define TOSA_KEY_OK KEY_HENKAN | ||
| 178 | #define TOSA_KEY_CALENDAR KEY_KATAKANAHIRAGANA | ||
| 179 | #define TOSA_KEY_HOMEPAGE KEY_HANGEUL | ||
| 180 | #define TOSA_KEY_LIGHT KEY_MUHENKAN | ||
| 181 | #define TOSA_KEY_MENU KEY_HANJA | ||
| 182 | #define TOSA_KEY_FN KEY_RIGHTALT | ||
| 183 | #define TOSA_KEY_MAIL KEY_ZENKAKUHANKAKU | ||
| 184 | #else | ||
| 185 | #define TOSA_KEY_RECORD KEY_RECORD | ||
| 186 | #define TOSA_KEY_ADDRESSBOOK KEY_ADDRESSBOOK | ||
| 187 | #define TOSA_KEY_CANCEL KEY_CANCEL | ||
| 188 | #define TOSA_KEY_CENTER KEY_SELECT /* ??? */ | ||
| 189 | #define TOSA_KEY_OK KEY_OK | ||
| 190 | #define TOSA_KEY_CALENDAR KEY_CALENDAR | ||
| 191 | #define TOSA_KEY_HOMEPAGE KEY_HOMEPAGE | ||
| 192 | #define TOSA_KEY_LIGHT KEY_KBDILLUMTOGGLE | ||
| 193 | #define TOSA_KEY_MENU KEY_MENU | ||
| 194 | #define TOSA_KEY_FN KEY_FN | ||
| 195 | #define TOSA_KEY_MAIL KEY_MAIL | ||
| 196 | #endif | ||
| 197 | |||
| 198 | #endif /* _ASM_ARCH_TOSA_H_ */ | ||
diff --git a/include/asm-arm/arch-pxa/tosa_bt.h b/include/asm-arm/arch-pxa/tosa_bt.h deleted file mode 100644 index efc3c3d3b75d..000000000000 --- a/include/asm-arm/arch-pxa/tosa_bt.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Tosa bluetooth built-in chip control. | ||
| 3 | * | ||
| 4 | * Later it may be shared with some other platforms. | ||
| 5 | * | ||
| 6 | * Copyright (c) 2008 Dmitry Baryshkov | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #ifndef TOSA_BT_H | ||
| 14 | #define TOSA_BT_H | ||
| 15 | |||
| 16 | struct tosa_bt_data { | ||
| 17 | int gpio_pwr; | ||
| 18 | int gpio_reset; | ||
| 19 | }; | ||
| 20 | |||
| 21 | #endif | ||
| 22 | |||
diff --git a/include/asm-arm/arch-pxa/trizeps4.h b/include/asm-arm/arch-pxa/trizeps4.h deleted file mode 100644 index 641d0ec110bb..000000000000 --- a/include/asm-arm/arch-pxa/trizeps4.h +++ /dev/null | |||
| @@ -1,106 +0,0 @@ | |||
| 1 | /************************************************************************ | ||
| 2 | * Include file for TRIZEPS4 SoM and ConXS eval-board | ||
| 3 | * Copyright (c) Jürgen Schindele | ||
| 4 | * 2006 | ||
| 5 | ************************************************************************/ | ||
| 6 | |||
| 7 | /* | ||
| 8 | * Includes/Defines | ||
| 9 | */ | ||
| 10 | #ifndef _TRIPEPS4_H_ | ||
| 11 | #define _TRIPEPS4_H_ | ||
| 12 | |||
| 13 | /* physical memory regions */ | ||
| 14 | #define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ | ||
| 15 | #define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ | ||
| 16 | #define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ | ||
| 17 | #define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ | ||
| 18 | #define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ | ||
| 19 | |||
| 20 | #define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board CSFR register */ | ||
| 21 | #define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic chip on ConXS-Board BOCR register */ | ||
| 22 | #define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic chip on ConXS-Board IRCR register*/ | ||
| 23 | #define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic chip on ConXS-Board UPSR register*/ | ||
| 24 | #define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* Logic chip on ConXS-Board DICR register*/ | ||
| 25 | |||
| 26 | /* virtual memory regions */ | ||
| 27 | #define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ | ||
| 28 | |||
| 29 | #define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */ | ||
| 30 | #define TRIZEPS4_CFSR_VIRT 0xF0100000 | ||
| 31 | #define TRIZEPS4_BOCR_VIRT 0xF0200000 | ||
| 32 | #define TRIZEPS4_DICR_VIRT 0xF0300000 | ||
| 33 | #define TRIZEPS4_IRCR_VIRT 0xF0400000 | ||
| 34 | #define TRIZEPS4_UPSR_VIRT 0xF0500000 | ||
| 35 | |||
| 36 | /* size of flash */ | ||
| 37 | #define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ | ||
| 38 | |||
| 39 | /* Ethernet Controller Davicom DM9000 */ | ||
| 40 | #define GPIO_DM9000 101 | ||
| 41 | #define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000) | ||
| 42 | |||
| 43 | /* UCB1400 audio / TS-controller */ | ||
| 44 | #define GPIO_UCB1400 1 | ||
| 45 | #define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400) | ||
| 46 | |||
| 47 | /* PCMCIA socket Compact Flash */ | ||
| 48 | #define GPIO_PCD 11 /* PCMCIA Card Detect */ | ||
| 49 | #define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD) | ||
| 50 | #define GPIO_PRDY 13 /* READY / nINT */ | ||
| 51 | #define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY) | ||
| 52 | |||
| 53 | /* MMC socket */ | ||
| 54 | #define GPIO_MMC_DET 12 | ||
| 55 | #define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET) | ||
| 56 | |||
| 57 | /* LEDS using tx2 / rx2 */ | ||
| 58 | #define GPIO_SYS_BUSY_LED 46 | ||
| 59 | #define GPIO_HEARTBEAT_LED 47 | ||
| 60 | |||
| 61 | /* Off-module PIC on ConXS board */ | ||
| 62 | #define GPIO_PIC 0 | ||
| 63 | #define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC) | ||
| 64 | |||
| 65 | #define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) | ||
| 66 | #define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) | ||
| 67 | |||
| 68 | #define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) | ||
| 69 | #define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) | ||
| 70 | |||
| 71 | #define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) | ||
| 72 | #define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) | ||
| 73 | |||
| 74 | #ifndef __ASSEMBLY__ | ||
| 75 | #define ConXS_CFSR (*((volatile unsigned short *)CFSR_P2V(0x0C000000))) | ||
| 76 | #define ConXS_BCR (*((volatile unsigned short *)BCR_P2V(0x0E000000))) | ||
| 77 | #define ConXS_DCR (*((volatile unsigned short *)DCR_P2V(0x0F800000))) | ||
| 78 | #else | ||
| 79 | #define ConXS_CFSR CFSR_P2V(0x0C000000) | ||
| 80 | #define ConXS_BCR BCR_P2V(0x0E000000) | ||
| 81 | #define ConXS_DCR DCR_P2V(0x0F800000) | ||
| 82 | #endif | ||
| 83 | |||
| 84 | #define ConXS_CFSR_BVD_MASK 0x0003 | ||
| 85 | #define ConXS_CFSR_BVD1 (1 << 0) | ||
| 86 | #define ConXS_CFSR_BVD2 (1 << 1) | ||
| 87 | #define ConXS_CFSR_VS_MASK 0x000C | ||
| 88 | #define ConXS_CFSR_VS1 (1 << 2) | ||
| 89 | #define ConXS_CFSR_VS2 (1 << 3) | ||
| 90 | #define ConXS_CFSR_VS_5V (0x3 << 2) | ||
| 91 | #define ConXS_CFSR_VS_3V3 0x0 | ||
| 92 | |||
| 93 | #define ConXS_BCR_S0_POW_EN0 (1 << 0) | ||
| 94 | #define ConXS_BCR_S0_POW_EN1 (1 << 1) | ||
| 95 | #define ConXS_BCR_L_DISP (1 << 4) | ||
| 96 | #define ConXS_BCR_CF_BUF_EN (1 << 5) | ||
| 97 | #define ConXS_BCR_CF_RESET (1 << 7) | ||
| 98 | #define ConXS_BCR_S0_VCC_3V3 0x1 | ||
| 99 | #define ConXS_BCR_S0_VCC_5V0 0x2 | ||
| 100 | #define ConXS_BCR_S0_VPP_12V 0x4 | ||
| 101 | #define ConXS_BCR_S0_VPP_3V3 0x8 | ||
| 102 | |||
| 103 | #define ConXS_IRCR_MODE (1 << 0) | ||
| 104 | #define ConXS_IRCR_SD (1 << 1) | ||
| 105 | |||
| 106 | #endif /* _TRIPEPS4_H_ */ | ||
diff --git a/include/asm-arm/arch-pxa/udc.h b/include/asm-arm/arch-pxa/udc.h deleted file mode 100644 index 27aa3a91012f..000000000000 --- a/include/asm-arm/arch-pxa/udc.h +++ /dev/null | |||
| @@ -1,8 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/udc.h | ||
| 3 | * | ||
| 4 | */ | ||
| 5 | #include <asm/mach/udc_pxa2xx.h> | ||
| 6 | |||
| 7 | extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); | ||
| 8 | |||
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h deleted file mode 100644 index f4551269aaf2..000000000000 --- a/include/asm-arm/arch-pxa/uncompress.h +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/uncompress.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Copyright: (C) 2001 MontaVista Software Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/serial_reg.h> | ||
| 13 | #include <asm/arch/pxa-regs.h> | ||
| 14 | #include <asm/mach-types.h> | ||
| 15 | |||
| 16 | #define __REG(x) ((volatile unsigned long *)x) | ||
| 17 | |||
| 18 | static volatile unsigned long *UART = FFUART; | ||
| 19 | |||
| 20 | static inline void putc(char c) | ||
| 21 | { | ||
| 22 | if (!(UART[UART_IER] & IER_UUE)) | ||
| 23 | return; | ||
| 24 | while (!(UART[UART_LSR] & LSR_TDRQ)) | ||
| 25 | barrier(); | ||
| 26 | UART[UART_TX] = c; | ||
| 27 | } | ||
| 28 | |||
| 29 | /* | ||
| 30 | * This does not append a newline | ||
| 31 | */ | ||
| 32 | static inline void flush(void) | ||
| 33 | { | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline void arch_decomp_setup(void) | ||
| 37 | { | ||
| 38 | if (machine_is_littleton()) | ||
| 39 | UART = STUART; | ||
| 40 | } | ||
| 41 | |||
| 42 | /* | ||
| 43 | * nothing to do | ||
| 44 | */ | ||
| 45 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-pxa/vmalloc.h b/include/asm-arm/arch-pxa/vmalloc.h deleted file mode 100644 index 5bb450c7aa2c..000000000000 --- a/include/asm-arm/arch-pxa/vmalloc.h +++ /dev/null | |||
| @@ -1,11 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-pxa/vmalloc.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Copyright: (C) 2001 MontaVista Software Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #define VMALLOC_END (0xe8000000) | ||
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h deleted file mode 100644 index 0d35ca04731e..000000000000 --- a/include/asm-arm/arch-pxa/zylonite.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | #ifndef __ASM_ARCH_ZYLONITE_H | ||
| 2 | #define __ASM_ARCH_ZYLONITE_H | ||
| 3 | |||
| 4 | #define ZYLONITE_ETH_PHYS 0x14000000 | ||
| 5 | |||
| 6 | #define EXT_GPIO(x) (128 + (x)) | ||
| 7 | |||
| 8 | /* the following variables are processor specific and initialized | ||
| 9 | * by the corresponding zylonite_pxa3xx_init() | ||
| 10 | */ | ||
| 11 | struct platform_mmc_slot { | ||
| 12 | int gpio_cd; | ||
| 13 | int gpio_wp; | ||
| 14 | }; | ||
| 15 | |||
| 16 | extern struct platform_mmc_slot zylonite_mmc_slot[]; | ||
| 17 | |||
| 18 | extern int gpio_eth_irq; | ||
| 19 | extern int gpio_debug_led1; | ||
| 20 | extern int gpio_debug_led2; | ||
| 21 | |||
| 22 | extern int wm9713_irq; | ||
| 23 | |||
| 24 | extern int lcd_id; | ||
| 25 | extern int lcd_orientation; | ||
| 26 | |||
| 27 | #ifdef CONFIG_CPU_PXA300 | ||
| 28 | extern void zylonite_pxa300_init(void); | ||
| 29 | #else | ||
| 30 | static inline void zylonite_pxa300_init(void) | ||
| 31 | { | ||
| 32 | if (cpu_is_pxa300() || cpu_is_pxa310()) | ||
| 33 | panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__); | ||
| 34 | } | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #ifdef CONFIG_CPU_PXA320 | ||
| 38 | extern void zylonite_pxa320_init(void); | ||
| 39 | #else | ||
| 40 | static inline void zylonite_pxa320_init(void) | ||
| 41 | { | ||
| 42 | if (cpu_is_pxa320()) | ||
| 43 | panic("%s: PXA320 not supported\n", __FUNCTION__); | ||
| 44 | } | ||
| 45 | #endif | ||
| 46 | |||
| 47 | #endif /* __ASM_ARCH_ZYLONITE_H */ | ||
diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h deleted file mode 100644 index 206f7a752882..000000000000 --- a/include/asm-arm/arch-realview/board-eb.h +++ /dev/null | |||
| @@ -1,191 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-realview/board-eb.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_BOARD_EB_H | ||
| 22 | #define __ASM_ARCH_BOARD_EB_H | ||
| 23 | |||
| 24 | #include <asm/arch/platform.h> | ||
| 25 | |||
| 26 | /* | ||
| 27 | * RealView EB + ARM11MPCore peripheral addresses | ||
| 28 | */ | ||
| 29 | #define REALVIEW_EB_UART0_BASE 0x10009000 /* UART 0 */ | ||
| 30 | #define REALVIEW_EB_UART1_BASE 0x1000A000 /* UART 1 */ | ||
| 31 | #define REALVIEW_EB_UART2_BASE 0x1000B000 /* UART 2 */ | ||
| 32 | #define REALVIEW_EB_UART3_BASE 0x1000C000 /* UART 3 */ | ||
| 33 | #define REALVIEW_EB_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ | ||
| 34 | #define REALVIEW_EB_WATCHDOG_BASE 0x10010000 /* watchdog interface */ | ||
| 35 | #define REALVIEW_EB_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ | ||
| 36 | #define REALVIEW_EB_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ | ||
| 37 | #define REALVIEW_EB_GPIO0_BASE 0x10013000 /* GPIO port 0 */ | ||
| 38 | #define REALVIEW_EB_RTC_BASE 0x10017000 /* Real Time Clock */ | ||
| 39 | #define REALVIEW_EB_CLCD_BASE 0x10020000 /* CLCD */ | ||
| 40 | #define REALVIEW_EB_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ | ||
| 41 | #define REALVIEW_EB_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ | ||
| 42 | #define REALVIEW_EB_SMC_BASE 0x10080000 /* Static memory controller */ | ||
| 43 | |||
| 44 | #define REALVIEW_EB_FLASH_BASE 0x40000000 | ||
| 45 | #define REALVIEW_EB_FLASH_SIZE SZ_64M | ||
| 46 | #define REALVIEW_EB_ETH_BASE 0x4E000000 /* Ethernet */ | ||
| 47 | #define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */ | ||
| 48 | |||
| 49 | #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB | ||
| 50 | #define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */ | ||
| 51 | #define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ | ||
| 52 | #define REALVIEW_EB11MP_TWD_BASE 0x10100700 | ||
| 53 | #define REALVIEW_EB11MP_TWD_SIZE 0x00000100 | ||
| 54 | #define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ | ||
| 55 | #define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */ | ||
| 56 | #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */ | ||
| 57 | #else | ||
| 58 | #define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */ | ||
| 59 | #define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */ | ||
| 60 | #define REALVIEW_EB11MP_TWD_BASE 0x1F000700 | ||
| 61 | #define REALVIEW_EB11MP_TWD_SIZE 0x00000100 | ||
| 62 | #define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */ | ||
| 63 | #define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */ | ||
| 64 | #define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */ | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #define IRQ_EB_GIC_START 32 | ||
| 68 | |||
| 69 | /* | ||
| 70 | * RealView EB interrupt sources | ||
| 71 | */ | ||
| 72 | #define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */ | ||
| 73 | #define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */ | ||
| 74 | #define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */ | ||
| 75 | #define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */ | ||
| 76 | #define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */ | ||
| 77 | #define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */ | ||
| 78 | #define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */ | ||
| 79 | #define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */ | ||
| 80 | #define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */ | ||
| 81 | /* 9 reserved */ | ||
| 82 | #define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */ | ||
| 83 | #define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */ | ||
| 84 | #define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */ | ||
| 85 | #define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */ | ||
| 86 | #define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */ | ||
| 87 | #define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */ | ||
| 88 | #define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */ | ||
| 89 | #define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */ | ||
| 90 | #define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */ | ||
| 91 | #define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */ | ||
| 92 | #define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */ | ||
| 93 | #define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */ | ||
| 94 | #define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */ | ||
| 95 | #define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */ | ||
| 96 | #define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */ | ||
| 97 | #define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */ | ||
| 98 | #define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */ | ||
| 99 | #define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */ | ||
| 100 | #define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */ | ||
| 101 | #define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */ | ||
| 102 | #define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */ | ||
| 103 | #define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */ | ||
| 104 | |||
| 105 | /* | ||
| 106 | * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile) | ||
| 107 | */ | ||
| 108 | #define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0) | ||
| 109 | #define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1) | ||
| 110 | #define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2) | ||
| 111 | #define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3) | ||
| 112 | #define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4) | ||
| 113 | #define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5) | ||
| 114 | #define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6) | ||
| 115 | #define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7) | ||
| 116 | #define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8) | ||
| 117 | #define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9) | ||
| 118 | #define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */ | ||
| 119 | #define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */ | ||
| 120 | #define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */ | ||
| 121 | #define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */ | ||
| 122 | #define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14) | ||
| 123 | #define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15) | ||
| 124 | |||
| 125 | #define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17) | ||
| 126 | #define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18) | ||
| 127 | #define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19) | ||
| 128 | #define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20) | ||
| 129 | #define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21) | ||
| 130 | #define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22) | ||
| 131 | #define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23) | ||
| 132 | #define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24) | ||
| 133 | #define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25) | ||
| 134 | #define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26) | ||
| 135 | #define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27) | ||
| 136 | #define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28) | ||
| 137 | |||
| 138 | #define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29) | ||
| 139 | #define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30) | ||
| 140 | #define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31) | ||
| 141 | |||
| 142 | #define IRQ_EB11MP_UART2 -1 | ||
| 143 | #define IRQ_EB11MP_UART3 -1 | ||
| 144 | #define IRQ_EB11MP_CLCD -1 | ||
| 145 | #define IRQ_EB11MP_DMA -1 | ||
| 146 | #define IRQ_EB11MP_WDOG -1 | ||
| 147 | #define IRQ_EB11MP_GPIO0 -1 | ||
| 148 | #define IRQ_EB11MP_GPIO1 -1 | ||
| 149 | #define IRQ_EB11MP_GPIO2 -1 | ||
| 150 | #define IRQ_EB11MP_SCI -1 | ||
| 151 | #define IRQ_EB11MP_SSP -1 | ||
| 152 | |||
| 153 | #define NR_GIC_EB11MP 2 | ||
| 154 | |||
| 155 | /* | ||
| 156 | * Only define NR_IRQS if less than NR_IRQS_EB | ||
| 157 | */ | ||
| 158 | #define NR_IRQS_EB (IRQ_EB_GIC_START + 96) | ||
| 159 | |||
| 160 | #if defined(CONFIG_MACH_REALVIEW_EB) \ | ||
| 161 | && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB)) | ||
| 162 | #undef NR_IRQS | ||
| 163 | #define NR_IRQS NR_IRQS_EB | ||
| 164 | #endif | ||
| 165 | |||
| 166 | #if defined(CONFIG_REALVIEW_EB_ARM11MP) \ | ||
| 167 | && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP)) | ||
| 168 | #undef MAX_GIC_NR | ||
| 169 | #define MAX_GIC_NR NR_GIC_EB11MP | ||
| 170 | #endif | ||
| 171 | |||
| 172 | /* | ||
| 173 | * Core tile identification (REALVIEW_SYS_PROCID) | ||
| 174 | */ | ||
| 175 | #define REALVIEW_EB_PROC_MASK 0xFF000000 | ||
| 176 | #define REALVIEW_EB_PROC_ARM7TDMI 0x00000000 | ||
| 177 | #define REALVIEW_EB_PROC_ARM9 0x02000000 | ||
| 178 | #define REALVIEW_EB_PROC_ARM11 0x04000000 | ||
| 179 | #define REALVIEW_EB_PROC_ARM11MP 0x06000000 | ||
| 180 | |||
| 181 | #define check_eb_proc(proc_type) \ | ||
| 182 | ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \ | ||
| 183 | == proc_type) | ||
| 184 | |||
| 185 | #ifdef CONFIG_REALVIEW_EB_ARM11MP | ||
| 186 | #define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP) | ||
| 187 | #else | ||
| 188 | #define core_tile_eb11mp() 0 | ||
| 189 | #endif | ||
| 190 | |||
| 191 | #endif /* __ASM_ARCH_BOARD_EB_H */ | ||
diff --git a/include/asm-arm/arch-realview/board-pb1176.h b/include/asm-arm/arch-realview/board-pb1176.h deleted file mode 100644 index 48ce9c833705..000000000000 --- a/include/asm-arm/arch-realview/board-pb1176.h +++ /dev/null | |||
| @@ -1,152 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-realview/board-pb1176.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_BOARD_PB1176_H | ||
| 22 | #define __ASM_ARCH_BOARD_PB1176_H | ||
| 23 | |||
| 24 | #include <asm/arch/platform.h> | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Peripheral addresses | ||
| 28 | */ | ||
| 29 | #define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */ | ||
| 30 | #define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */ | ||
| 31 | #define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */ | ||
| 32 | #define REALVIEW_PB1176_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ | ||
| 33 | #define REALVIEW_PB1176_FLASH_BASE 0x30000000 | ||
| 34 | #define REALVIEW_PB1176_FLASH_SIZE SZ_64M | ||
| 35 | |||
| 36 | #define REALVIEW_PB1176_TIMER0_1_BASE 0x10104000 /* Timer 0 and 1 */ | ||
| 37 | #define REALVIEW_PB1176_TIMER2_3_BASE 0x10105000 /* Timer 2 and 3 */ | ||
| 38 | #define REALVIEW_PB1176_TIMER4_5_BASE 0x10106000 /* Timer 4 and 5 */ | ||
| 39 | #define REALVIEW_PB1176_WATCHDOG_BASE 0x10107000 /* watchdog interface */ | ||
| 40 | #define REALVIEW_PB1176_RTC_BASE 0x10108000 /* Real Time Clock */ | ||
| 41 | #define REALVIEW_PB1176_GPIO0_BASE 0x1010A000 /* GPIO port 0 */ | ||
| 42 | #define REALVIEW_PB1176_SSP_BASE 0x1010B000 /* Synchronous Serial Port */ | ||
| 43 | #define REALVIEW_PB1176_UART0_BASE 0x1010C000 /* UART 0 */ | ||
| 44 | #define REALVIEW_PB1176_UART1_BASE 0x1010D000 /* UART 1 */ | ||
| 45 | #define REALVIEW_PB1176_UART2_BASE 0x1010E000 /* UART 2 */ | ||
| 46 | #define REALVIEW_PB1176_UART3_BASE 0x1010F000 /* UART 3 */ | ||
| 47 | #define REALVIEW_PB1176_CLCD_BASE 0x10112000 /* CLCD */ | ||
| 48 | #define REALVIEW_PB1176_ETH_BASE 0x3A000000 /* Ethernet */ | ||
| 49 | #define REALVIEW_PB1176_USB_BASE 0x3B000000 /* USB */ | ||
| 50 | |||
| 51 | /* | ||
| 52 | * PCI regions | ||
| 53 | */ | ||
| 54 | #define REALVIEW_PB1176_PCI_BASE 0x60000000 /* PCI self config */ | ||
| 55 | #define REALVIEW_PB1176_PCI_CFG_BASE 0x61000000 /* PCI config */ | ||
| 56 | #define REALVIEW_PB1176_PCI_IO_BASE0 0x62000000 /* PCI IO region */ | ||
| 57 | #define REALVIEW_PB1176_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */ | ||
| 58 | #define REALVIEW_PB1176_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */ | ||
| 59 | #define REALVIEW_PB1176_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */ | ||
| 60 | |||
| 61 | #define REALVIEW_PB1176_PCI_BASE_SIZE 0x01000000 /* 16MB */ | ||
| 62 | #define REALVIEW_PB1176_PCI_CFG_BASE_SIZE 0x01000000 /* 16MB */ | ||
| 63 | #define REALVIEW_PB1176_PCI_IO_BASE0_SIZE 0x01000000 /* 16MB */ | ||
| 64 | #define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE 0x01000000 /* 16MB */ | ||
| 65 | #define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE 0x04000000 /* 64MB */ | ||
| 66 | #define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE 0x08000000 /* 128MB */ | ||
| 67 | |||
| 68 | #define REALVIEW_DC1176_GIC_CPU_BASE 0x10120000 /* GIC CPU interface, on devchip */ | ||
| 69 | #define REALVIEW_DC1176_GIC_DIST_BASE 0x10121000 /* GIC distributor, on devchip */ | ||
| 70 | #define REALVIEW_PB1176_GIC_CPU_BASE 0x10040000 /* GIC CPU interface, on FPGA */ | ||
| 71 | #define REALVIEW_PB1176_GIC_DIST_BASE 0x10041000 /* GIC distributor, on FPGA */ | ||
| 72 | #define REALVIEW_PB1176_L220_BASE 0x10110000 /* L220 registers */ | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Irqs | ||
| 76 | */ | ||
| 77 | #define IRQ_DC1176_GIC_START 32 | ||
| 78 | #define IRQ_PB1176_GIC_START 64 | ||
| 79 | |||
| 80 | /* | ||
| 81 | * ARM1176 DevChip interrupt sources (primary GIC) | ||
| 82 | */ | ||
| 83 | #define IRQ_DC1176_WATCHDOG (IRQ_DC1176_GIC_START + 0) /* Watchdog timer */ | ||
| 84 | #define IRQ_DC1176_SOFTINT (IRQ_DC1176_GIC_START + 1) /* Software interrupt */ | ||
| 85 | #define IRQ_DC1176_COMMRx (IRQ_DC1176_GIC_START + 2) /* Debug Comm Rx interrupt */ | ||
| 86 | #define IRQ_DC1176_COMMTx (IRQ_DC1176_GIC_START + 3) /* Debug Comm Tx interrupt */ | ||
| 87 | #define IRQ_DC1176_TIMER0 (IRQ_DC1176_GIC_START + 8) /* Timer 0 */ | ||
| 88 | #define IRQ_DC1176_TIMER1 (IRQ_DC1176_GIC_START + 9) /* Timer 1 */ | ||
| 89 | #define IRQ_DC1176_TIMER2 (IRQ_DC1176_GIC_START + 10) /* Timer 2 */ | ||
| 90 | #define IRQ_DC1176_APC (IRQ_DC1176_GIC_START + 11) | ||
| 91 | #define IRQ_DC1176_IEC (IRQ_DC1176_GIC_START + 12) | ||
| 92 | #define IRQ_DC1176_L2CC (IRQ_DC1176_GIC_START + 13) | ||
| 93 | #define IRQ_DC1176_RTC (IRQ_DC1176_GIC_START + 14) | ||
| 94 | #define IRQ_DC1176_CLCD (IRQ_DC1176_GIC_START + 15) /* CLCD controller */ | ||
| 95 | #define IRQ_DC1176_UART0 (IRQ_DC1176_GIC_START + 18) /* UART 0 on development chip */ | ||
| 96 | #define IRQ_DC1176_UART1 (IRQ_DC1176_GIC_START + 19) /* UART 1 on development chip */ | ||
| 97 | #define IRQ_DC1176_UART2 (IRQ_DC1176_GIC_START + 20) /* UART 2 on development chip */ | ||
| 98 | #define IRQ_DC1176_UART3 (IRQ_DC1176_GIC_START + 21) /* UART 3 on development chip */ | ||
| 99 | |||
| 100 | #define IRQ_DC1176_PB_IRQ2 (IRQ_DC1176_GIC_START + 30) /* tile GIC */ | ||
| 101 | #define IRQ_DC1176_PB_IRQ1 (IRQ_DC1176_GIC_START + 31) /* main GIC */ | ||
| 102 | |||
| 103 | /* | ||
| 104 | * RealView PB1176 interrupt sources (secondary GIC) | ||
| 105 | */ | ||
| 106 | #define IRQ_PB1176_MMCI0A (IRQ_PB1176_GIC_START + 1) /* Multimedia Card 0A */ | ||
| 107 | #define IRQ_PB1176_MMCI0B (IRQ_PB1176_GIC_START + 2) /* Multimedia Card 0A */ | ||
| 108 | #define IRQ_PB1176_KMI0 (IRQ_PB1176_GIC_START + 3) /* Keyboard/Mouse port 0 */ | ||
| 109 | #define IRQ_PB1176_KMI1 (IRQ_PB1176_GIC_START + 4) /* Keyboard/Mouse port 1 */ | ||
| 110 | #define IRQ_PB1176_SCI (IRQ_PB1176_GIC_START + 5) | ||
| 111 | #define IRQ_PB1176_UART4 (IRQ_PB1176_GIC_START + 6) /* UART 4 on baseboard */ | ||
| 112 | #define IRQ_PB1176_CHARLCD (IRQ_PB1176_GIC_START + 7) /* Character LCD */ | ||
| 113 | #define IRQ_PB1176_GPIO1 (IRQ_PB1176_GIC_START + 8) | ||
| 114 | #define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9) | ||
| 115 | #define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */ | ||
| 116 | #define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */ | ||
| 117 | |||
| 118 | #define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16) | ||
| 119 | |||
| 120 | #define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */ | ||
| 121 | |||
| 122 | #define IRQ_PB1176_TIMER0_1 (IRQ_PB1176_GIC_START + 22) | ||
| 123 | #define IRQ_PB1176_TIMER2_3 (IRQ_PB1176_GIC_START + 23) | ||
| 124 | #define IRQ_PB1176_DMAC (IRQ_PB1176_GIC_START + 24) /* DMA controller */ | ||
| 125 | #define IRQ_PB1176_RTC (IRQ_PB1176_GIC_START + 25) /* Real Time Clock */ | ||
| 126 | |||
| 127 | #define IRQ_PB1176_GPIO0 -1 | ||
| 128 | #define IRQ_PB1176_SSP -1 | ||
| 129 | #define IRQ_PB1176_SCTL -1 | ||
| 130 | |||
| 131 | #define NR_GIC_PB1176 2 | ||
| 132 | |||
| 133 | /* | ||
| 134 | * Only define NR_IRQS if less than NR_IRQS_PB1176 | ||
| 135 | */ | ||
| 136 | #define NR_IRQS_PB1176 (IRQ_DC1176_GIC_START + 96) | ||
| 137 | |||
| 138 | #if defined(CONFIG_MACH_REALVIEW_PB1176) | ||
| 139 | |||
| 140 | #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176) | ||
| 141 | #undef NR_IRQS | ||
| 142 | #define NR_IRQS NR_IRQS_PB1176 | ||
| 143 | #endif | ||
| 144 | |||
| 145 | #if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176) | ||
| 146 | #undef MAX_GIC_NR | ||
| 147 | #define MAX_GIC_NR NR_GIC_PB1176 | ||
| 148 | #endif | ||
| 149 | |||
| 150 | #endif /* CONFIG_MACH_REALVIEW_PB1176 */ | ||
| 151 | |||
| 152 | #endif /* __ASM_ARCH_BOARD_PB1176_H */ | ||
diff --git a/include/asm-arm/arch-realview/board-pb11mp.h b/include/asm-arm/arch-realview/board-pb11mp.h deleted file mode 100644 index a1294d915fa8..000000000000 --- a/include/asm-arm/arch-realview/board-pb11mp.h +++ /dev/null | |||
| @@ -1,186 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-realview/board-pb11mp.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_BOARD_PB11MP_H | ||
| 22 | #define __ASM_ARCH_BOARD_PB11MP_H | ||
| 23 | |||
| 24 | #include <asm/arch/platform.h> | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Peripheral addresses | ||
| 28 | */ | ||
| 29 | #define REALVIEW_PB11MP_UART0_BASE 0x10009000 /* UART 0 */ | ||
| 30 | #define REALVIEW_PB11MP_UART1_BASE 0x1000A000 /* UART 1 */ | ||
| 31 | #define REALVIEW_PB11MP_UART2_BASE 0x1000B000 /* UART 2 */ | ||
| 32 | #define REALVIEW_PB11MP_UART3_BASE 0x1000C000 /* UART 3 */ | ||
| 33 | #define REALVIEW_PB11MP_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ | ||
| 34 | #define REALVIEW_PB11MP_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ | ||
| 35 | #define REALVIEW_PB11MP_WATCHDOG_BASE 0x10010000 /* watchdog interface */ | ||
| 36 | #define REALVIEW_PB11MP_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ | ||
| 37 | #define REALVIEW_PB11MP_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ | ||
| 38 | #define REALVIEW_PB11MP_GPIO0_BASE 0x10013000 /* GPIO port 0 */ | ||
| 39 | #define REALVIEW_PB11MP_RTC_BASE 0x10017000 /* Real Time Clock */ | ||
| 40 | #define REALVIEW_PB11MP_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ | ||
| 41 | #define REALVIEW_PB11MP_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ | ||
| 42 | #define REALVIEW_PB11MP_SCTL_BASE 0x1001A000 /* System Controller */ | ||
| 43 | #define REALVIEW_PB11MP_CLCD_BASE 0x10020000 /* CLCD */ | ||
| 44 | #define REALVIEW_PB11MP_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ | ||
| 45 | #define REALVIEW_PB11MP_DMC_BASE 0x100E0000 /* DMC configuration */ | ||
| 46 | #define REALVIEW_PB11MP_SMC_BASE 0x100E1000 /* SMC configuration */ | ||
| 47 | #define REALVIEW_PB11MP_CAN_BASE 0x100E2000 /* CAN bus */ | ||
| 48 | #define REALVIEW_PB11MP_CF_BASE 0x18000000 /* Compact flash */ | ||
| 49 | #define REALVIEW_PB11MP_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */ | ||
| 50 | #define REALVIEW_PB11MP_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ | ||
| 51 | #define REALVIEW_PB11MP_FLASH0_BASE 0x40000000 | ||
| 52 | #define REALVIEW_PB11MP_FLASH0_SIZE SZ_64M | ||
| 53 | #define REALVIEW_PB11MP_FLASH1_BASE 0x44000000 | ||
| 54 | #define REALVIEW_PB11MP_FLASH1_SIZE SZ_64M | ||
| 55 | #define REALVIEW_PB11MP_ETH_BASE 0x4E000000 /* Ethernet */ | ||
| 56 | #define REALVIEW_PB11MP_USB_BASE 0x4F000000 /* USB */ | ||
| 57 | #define REALVIEW_PB11MP_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */ | ||
| 58 | #define REALVIEW_PB11MP_LT_BASE 0xC0000000 /* Logic Tile expansion */ | ||
| 59 | #define REALVIEW_PB11MP_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */ | ||
| 60 | #define REALVIEW_PB11MP_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ | ||
| 61 | |||
| 62 | #define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 | ||
| 63 | |||
| 64 | /* | ||
| 65 | * PB11MPCore PCI regions | ||
| 66 | */ | ||
| 67 | #define REALVIEW_PB11MP_PCI_BASE 0x90040000 /* PCI-X Unit base */ | ||
| 68 | #define REALVIEW_PB11MP_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ | ||
| 69 | #define REALVIEW_PB11MP_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ | ||
| 70 | |||
| 71 | #define REALVIEW_PB11MP_PCI_BASE_SIZE 0x10000 /* 16 Kb */ | ||
| 72 | #define REALVIEW_PB11MP_PCI_IO_SIZE 0x1000 /* 4 Kb */ | ||
| 73 | #define REALVIEW_PB11MP_PCI_MEM_SIZE 0x20000000 /* 512 MB */ | ||
| 74 | |||
| 75 | /* | ||
| 76 | * Testchip peripheral and fpga gic regions | ||
| 77 | */ | ||
| 78 | #define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */ | ||
| 79 | #define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */ | ||
| 80 | #define REALVIEW_TC11MP_TWD_BASE 0x1F000700 | ||
| 81 | #define REALVIEW_TC11MP_TWD_SIZE 0x00000100 | ||
| 82 | #define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */ | ||
| 83 | #define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */ | ||
| 84 | |||
| 85 | /* | ||
| 86 | * Irqs | ||
| 87 | */ | ||
| 88 | #define IRQ_TC11MP_GIC_START 32 | ||
| 89 | #define IRQ_PB11MP_GIC_START 64 | ||
| 90 | |||
| 91 | /* | ||
| 92 | * ARM11MPCore test chip interrupt sources (primary GIC on the test chip) | ||
| 93 | */ | ||
| 94 | #define IRQ_TC11MP_AACI (IRQ_TC11MP_GIC_START + 0) | ||
| 95 | #define IRQ_TC11MP_TIMER0_1 (IRQ_TC11MP_GIC_START + 1) | ||
| 96 | #define IRQ_TC11MP_TIMER2_3 (IRQ_TC11MP_GIC_START + 2) | ||
| 97 | #define IRQ_TC11MP_USB (IRQ_TC11MP_GIC_START + 3) | ||
| 98 | #define IRQ_TC11MP_UART0 (IRQ_TC11MP_GIC_START + 4) | ||
| 99 | #define IRQ_TC11MP_UART1 (IRQ_TC11MP_GIC_START + 5) | ||
| 100 | #define IRQ_TC11MP_RTC (IRQ_TC11MP_GIC_START + 6) | ||
| 101 | #define IRQ_TC11MP_KMI0 (IRQ_TC11MP_GIC_START + 7) | ||
| 102 | #define IRQ_TC11MP_KMI1 (IRQ_TC11MP_GIC_START + 8) | ||
| 103 | #define IRQ_TC11MP_ETH (IRQ_TC11MP_GIC_START + 9) | ||
| 104 | #define IRQ_TC11MP_PB_IRQ1 (IRQ_TC11MP_GIC_START + 10) /* main GIC */ | ||
| 105 | #define IRQ_TC11MP_PB_IRQ2 (IRQ_TC11MP_GIC_START + 11) /* tile GIC */ | ||
| 106 | #define IRQ_TC11MP_PB_FIQ1 (IRQ_TC11MP_GIC_START + 12) /* main GIC */ | ||
| 107 | #define IRQ_TC11MP_PB_FIQ2 (IRQ_TC11MP_GIC_START + 13) /* tile GIC */ | ||
| 108 | #define IRQ_TC11MP_MMCI0A (IRQ_TC11MP_GIC_START + 14) | ||
| 109 | #define IRQ_TC11MP_MMCI0B (IRQ_TC11MP_GIC_START + 15) | ||
| 110 | |||
| 111 | #define IRQ_TC11MP_PMU_CPU0 (IRQ_TC11MP_GIC_START + 17) | ||
| 112 | #define IRQ_TC11MP_PMU_CPU1 (IRQ_TC11MP_GIC_START + 18) | ||
| 113 | #define IRQ_TC11MP_PMU_CPU2 (IRQ_TC11MP_GIC_START + 19) | ||
| 114 | #define IRQ_TC11MP_PMU_CPU3 (IRQ_TC11MP_GIC_START + 20) | ||
| 115 | #define IRQ_TC11MP_PMU_SCU0 (IRQ_TC11MP_GIC_START + 21) | ||
| 116 | #define IRQ_TC11MP_PMU_SCU1 (IRQ_TC11MP_GIC_START + 22) | ||
| 117 | #define IRQ_TC11MP_PMU_SCU2 (IRQ_TC11MP_GIC_START + 23) | ||
| 118 | #define IRQ_TC11MP_PMU_SCU3 (IRQ_TC11MP_GIC_START + 24) | ||
| 119 | #define IRQ_TC11MP_PMU_SCU4 (IRQ_TC11MP_GIC_START + 25) | ||
| 120 | #define IRQ_TC11MP_PMU_SCU5 (IRQ_TC11MP_GIC_START + 26) | ||
| 121 | #define IRQ_TC11MP_PMU_SCU6 (IRQ_TC11MP_GIC_START + 27) | ||
| 122 | #define IRQ_TC11MP_PMU_SCU7 (IRQ_TC11MP_GIC_START + 28) | ||
| 123 | |||
| 124 | #define IRQ_TC11MP_L220_EVENT (IRQ_TC11MP_GIC_START + 29) | ||
| 125 | #define IRQ_TC11MP_L220_SLAVE (IRQ_TC11MP_GIC_START + 30) | ||
| 126 | #define IRQ_TC11MP_L220_DECODE (IRQ_TC11MP_GIC_START + 31) | ||
| 127 | |||
| 128 | /* | ||
| 129 | * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board) | ||
| 130 | */ | ||
| 131 | #define IRQ_PB11MP_WATCHDOG (IRQ_PB11MP_GIC_START + 0) /* Watchdog timer */ | ||
| 132 | #define IRQ_PB11MP_SOFT (IRQ_PB11MP_GIC_START + 1) /* Software interrupt */ | ||
| 133 | #define IRQ_PB11MP_COMMRx (IRQ_PB11MP_GIC_START + 2) /* Debug Comm Rx interrupt */ | ||
| 134 | #define IRQ_PB11MP_COMMTx (IRQ_PB11MP_GIC_START + 3) /* Debug Comm Tx interrupt */ | ||
| 135 | #define IRQ_PB11MP_GPIO0 (IRQ_PB11MP_GIC_START + 6) /* GPIO 0 */ | ||
| 136 | #define IRQ_PB11MP_GPIO1 (IRQ_PB11MP_GIC_START + 7) /* GPIO 1 */ | ||
| 137 | #define IRQ_PB11MP_GPIO2 (IRQ_PB11MP_GIC_START + 8) /* GPIO 2 */ | ||
| 138 | /* 9 reserved */ | ||
| 139 | #define IRQ_PB11MP_RTC_GIC1 (IRQ_PB11MP_GIC_START + 10) /* Real Time Clock */ | ||
| 140 | #define IRQ_PB11MP_SSP (IRQ_PB11MP_GIC_START + 11) /* Synchronous Serial Port */ | ||
| 141 | #define IRQ_PB11MP_UART0_GIC1 (IRQ_PB11MP_GIC_START + 12) /* UART 0 on development chip */ | ||
| 142 | #define IRQ_PB11MP_UART1_GIC1 (IRQ_PB11MP_GIC_START + 13) /* UART 1 on development chip */ | ||
| 143 | #define IRQ_PB11MP_UART2 (IRQ_PB11MP_GIC_START + 14) /* UART 2 on development chip */ | ||
| 144 | #define IRQ_PB11MP_UART3 (IRQ_PB11MP_GIC_START + 15) /* UART 3 on development chip */ | ||
| 145 | #define IRQ_PB11MP_SCI (IRQ_PB11MP_GIC_START + 16) /* Smart Card Interface */ | ||
| 146 | #define IRQ_PB11MP_MMCI0A_GIC1 (IRQ_PB11MP_GIC_START + 17) /* Multimedia Card 0A */ | ||
| 147 | #define IRQ_PB11MP_MMCI0B_GIC1 (IRQ_PB11MP_GIC_START + 18) /* Multimedia Card 0B */ | ||
| 148 | #define IRQ_PB11MP_AACI_GIC1 (IRQ_PB11MP_GIC_START + 19) /* Audio Codec */ | ||
| 149 | #define IRQ_PB11MP_KMI0_GIC1 (IRQ_PB11MP_GIC_START + 20) /* Keyboard/Mouse port 0 */ | ||
| 150 | #define IRQ_PB11MP_KMI1_GIC1 (IRQ_PB11MP_GIC_START + 21) /* Keyboard/Mouse port 1 */ | ||
| 151 | #define IRQ_PB11MP_CHARLCD (IRQ_PB11MP_GIC_START + 22) /* Character LCD */ | ||
| 152 | #define IRQ_PB11MP_CLCD (IRQ_PB11MP_GIC_START + 23) /* CLCD controller */ | ||
| 153 | #define IRQ_PB11MP_DMAC (IRQ_PB11MP_GIC_START + 24) /* DMA controller */ | ||
| 154 | #define IRQ_PB11MP_PWRFAIL (IRQ_PB11MP_GIC_START + 25) /* Power failure */ | ||
| 155 | #define IRQ_PB11MP_PISMO (IRQ_PB11MP_GIC_START + 26) /* PISMO interface */ | ||
| 156 | #define IRQ_PB11MP_DoC (IRQ_PB11MP_GIC_START + 27) /* Disk on Chip memory controller */ | ||
| 157 | #define IRQ_PB11MP_ETH_GIC1 (IRQ_PB11MP_GIC_START + 28) /* Ethernet controller */ | ||
| 158 | #define IRQ_PB11MP_USB_GIC1 (IRQ_PB11MP_GIC_START + 29) /* USB controller */ | ||
| 159 | #define IRQ_PB11MP_TSPEN (IRQ_PB11MP_GIC_START + 30) /* Touchscreen pen */ | ||
| 160 | #define IRQ_PB11MP_TSKPAD (IRQ_PB11MP_GIC_START + 31) /* Touchscreen keypad */ | ||
| 161 | |||
| 162 | #define IRQ_PB11MP_SMC -1 | ||
| 163 | #define IRQ_PB11MP_SCTL -1 | ||
| 164 | |||
| 165 | #define NR_GIC_PB11MP 2 | ||
| 166 | |||
| 167 | /* | ||
| 168 | * Only define NR_IRQS if less than NR_IRQS_PB11MP | ||
| 169 | */ | ||
| 170 | #define NR_IRQS_PB11MP (IRQ_TC11MP_GIC_START + 96) | ||
| 171 | |||
| 172 | #if defined(CONFIG_MACH_REALVIEW_PB11MP) | ||
| 173 | |||
| 174 | #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP) | ||
| 175 | #undef NR_IRQS | ||
| 176 | #define NR_IRQS NR_IRQS_PB11MP | ||
| 177 | #endif | ||
| 178 | |||
| 179 | #if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP) | ||
| 180 | #undef MAX_GIC_NR | ||
| 181 | #define MAX_GIC_NR NR_GIC_PB11MP | ||
| 182 | #endif | ||
| 183 | |||
| 184 | #endif /* CONFIG_MACH_REALVIEW_PB11MP */ | ||
| 185 | |||
| 186 | #endif /* __ASM_ARCH_BOARD_PB11MP_H */ | ||
diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S deleted file mode 100644 index c8c860c3c26e..000000000000 --- a/include/asm-arm/arch-realview/debug-macro.S +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-realview/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | moveq \rx, #0x10000000 | ||
| 18 | movne \rx, #0xf0000000 @ virtual base | ||
| 19 | orr \rx, \rx, #0x00009000 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | #include <asm/hardware/debug-pl01x.S> | ||
diff --git a/include/asm-arm/arch-realview/dma.h b/include/asm-arm/arch-realview/dma.h deleted file mode 100644 index 8342e3f9d6ec..000000000000 --- a/include/asm-arm/arch-realview/dma.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-realview/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited. | ||
| 5 | * Copyright (C) 1997,1998 Russell King | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S deleted file mode 100644 index 31a39a7cdaa9..000000000000 --- a/include/asm-arm/arch-realview/entry-macro.S +++ /dev/null | |||
| @@ -1,81 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-realview/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for RealView platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | #include <asm/hardware/gic.h> | ||
| 12 | |||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro get_irqnr_preamble, base, tmp | ||
| 17 | ldr \base, =gic_cpu_base_addr | ||
| 18 | ldr \base, [\base] | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 22 | .endm | ||
| 23 | |||
| 24 | /* | ||
| 25 | * The interrupt numbering scheme is defined in the | ||
| 26 | * interrupt controller spec. To wit: | ||
| 27 | * | ||
| 28 | * Interrupts 0-15 are IPI | ||
| 29 | * 16-28 are reserved | ||
| 30 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
| 31 | * 32-1020 are global | ||
| 32 | * 1021-1022 are reserved | ||
| 33 | * 1023 is "spurious" (no interrupt) | ||
| 34 | * | ||
| 35 | * For now, we ignore all local interrupts so only return an interrupt if it's | ||
| 36 | * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. | ||
| 37 | * | ||
| 38 | * A simple read from the controller will tell us the number of the highest | ||
| 39 | * priority enabled interrupt. We then just need to check whether it is in the | ||
| 40 | * valid range for an IRQ (30-1020 inclusive). | ||
| 41 | */ | ||
| 42 | |||
| 43 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 44 | |||
| 45 | ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ | ||
| 46 | |||
| 47 | ldr \tmp, =1021 | ||
| 48 | |||
| 49 | bic \irqnr, \irqstat, #0x1c00 | ||
| 50 | |||
| 51 | cmp \irqnr, #29 | ||
| 52 | cmpcc \irqnr, \irqnr | ||
| 53 | cmpne \irqnr, \tmp | ||
| 54 | cmpcs \irqnr, \irqnr | ||
| 55 | |||
| 56 | .endm | ||
| 57 | |||
| 58 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 59 | * register) is preserved from the macro above. | ||
| 60 | * If there is an IPI, we immediately signal end of interrupt on the | ||
| 61 | * controller, since this requires the original irqstat value which | ||
| 62 | * we won't easily be able to recreate later. | ||
| 63 | */ | ||
| 64 | |||
| 65 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 66 | bic \irqnr, \irqstat, #0x1c00 | ||
| 67 | cmp \irqnr, #16 | ||
| 68 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 69 | cmpcs \irqnr, \irqnr | ||
| 70 | .endm | ||
| 71 | |||
| 72 | /* As above, this assumes that irqstat and base are preserved.. */ | ||
| 73 | |||
| 74 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 75 | bic \irqnr, \irqstat, #0x1c00 | ||
| 76 | mov \tmp, #0 | ||
| 77 | cmp \irqnr, #29 | ||
| 78 | moveq \tmp, #1 | ||
| 79 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
| 80 | cmp \tmp, #0 | ||
| 81 | .endm | ||
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h deleted file mode 100644 index 1ee8313ceb6a..000000000000 --- a/include/asm-arm/arch-realview/hardware.h +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-realview/hardware.h | ||
| 3 | * | ||
| 4 | * This file contains the hardware definitions of the RealView boards. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003 ARM Limited. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 23 | #define __ASM_ARCH_HARDWARE_H | ||
| 24 | |||
| 25 | #include <asm/sizes.h> | ||
| 26 | |||
| 27 | /* macro to get at IO space when running virtually */ | ||
| 28 | #define IO_ADDRESS(x) (((x) & 0x0fffffff) + 0xf0000000) | ||
| 29 | #define __io_address(n) __io(IO_ADDRESS(n)) | ||
| 30 | |||
| 31 | #endif | ||
diff --git a/include/asm-arm/arch-realview/io.h b/include/asm-arm/arch-realview/io.h deleted file mode 100644 index c70f1dfbe135..000000000000 --- a/include/asm-arm/arch-realview/io.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-realview/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 21 | #define __ASM_ARM_ARCH_IO_H | ||
| 22 | |||
| 23 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 24 | |||
| 25 | static inline void __iomem *__io(unsigned long addr) | ||
| 26 | { | ||
| 27 | return (void __iomem *)addr; | ||
| 28 | } | ||
| 29 | |||
| 30 | #define __io(a) __io(a) | ||
| 31 | #define __mem_pci(a) (a) | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h deleted file mode 100644 index ccbac59235c6..000000000000 --- a/include/asm-arm/arch-realview/irqs.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-realview/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | #ifndef __ASM_ARCH_IRQS_H | ||
| 23 | #define __ASM_ARCH_IRQS_H | ||
| 24 | |||
| 25 | #include <asm/arch/board-eb.h> | ||
| 26 | #include <asm/arch/board-pb11mp.h> | ||
| 27 | #include <asm/arch/board-pb1176.h> | ||
| 28 | |||
| 29 | #define IRQ_LOCALTIMER 29 | ||
| 30 | #define IRQ_LOCALWDOG 30 | ||
| 31 | |||
| 32 | #define IRQ_GIC_START 32 | ||
| 33 | |||
| 34 | #ifndef NR_IRQS | ||
| 35 | #error "NR_IRQS not defined by the board-specific files" | ||
| 36 | #endif | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-realview/memory.h b/include/asm-arm/arch-realview/memory.h deleted file mode 100644 index ed370abb638f..000000000000 --- a/include/asm-arm/arch-realview/memory.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-realview/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 21 | #define __ASM_ARCH_MEMORY_H | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Physical DRAM offset. | ||
| 25 | */ | ||
| 26 | #define PHYS_OFFSET UL(0x00000000) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Virtual view <-> DMA view memory address translations | ||
| 30 | * virt_to_bus: Used to translate the virtual address to an | ||
| 31 | * address suitable to be passed to set_dma_addr | ||
| 32 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 33 | * to an address that the kernel can use. | ||
| 34 | */ | ||
| 35 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET) | ||
| 36 | #define __bus_to_virt(x) ((x) + PAGE_OFFSET) | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h deleted file mode 100644 index 424c0aaf46a0..000000000000 --- a/include/asm-arm/arch-realview/platform.h +++ /dev/null | |||
| @@ -1,293 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-realview/platform.h | ||
| 3 | * | ||
| 4 | * Copyright (c) ARM Limited 2003. All rights reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_PLATFORM_H | ||
| 22 | #define __ASM_ARCH_PLATFORM_H | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Memory definitions | ||
| 26 | */ | ||
| 27 | #define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/ | ||
| 28 | #define REALVIEW_BOOT_ROM_HI 0x30000000 | ||
| 29 | #define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */ | ||
| 30 | #define REALVIEW_BOOT_ROM_SIZE SZ_64M | ||
| 31 | |||
| 32 | #define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */ | ||
| 33 | #define REALVIEW_SSRAM_SIZE SZ_2M | ||
| 34 | |||
| 35 | /* | ||
| 36 | * SDRAM | ||
| 37 | */ | ||
| 38 | #define REALVIEW_SDRAM_BASE 0x00000000 | ||
| 39 | |||
| 40 | /* | ||
| 41 | * Logic expansion modules | ||
| 42 | * | ||
| 43 | */ | ||
| 44 | |||
| 45 | |||
| 46 | /* ------------------------------------------------------------------------ | ||
| 47 | * RealView Registers | ||
| 48 | * ------------------------------------------------------------------------ | ||
| 49 | * | ||
| 50 | */ | ||
| 51 | #define REALVIEW_SYS_ID_OFFSET 0x00 | ||
| 52 | #define REALVIEW_SYS_SW_OFFSET 0x04 | ||
| 53 | #define REALVIEW_SYS_LED_OFFSET 0x08 | ||
| 54 | #define REALVIEW_SYS_OSC0_OFFSET 0x0C | ||
| 55 | |||
| 56 | #define REALVIEW_SYS_OSC1_OFFSET 0x10 | ||
| 57 | #define REALVIEW_SYS_OSC2_OFFSET 0x14 | ||
| 58 | #define REALVIEW_SYS_OSC3_OFFSET 0x18 | ||
| 59 | #define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */ | ||
| 60 | |||
| 61 | #define REALVIEW_SYS_LOCK_OFFSET 0x20 | ||
| 62 | #define REALVIEW_SYS_100HZ_OFFSET 0x24 | ||
| 63 | #define REALVIEW_SYS_CFGDATA1_OFFSET 0x28 | ||
| 64 | #define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C | ||
| 65 | #define REALVIEW_SYS_FLAGS_OFFSET 0x30 | ||
| 66 | #define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 | ||
| 67 | #define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34 | ||
| 68 | #define REALVIEW_SYS_NVFLAGS_OFFSET 0x38 | ||
| 69 | #define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38 | ||
| 70 | #define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C | ||
| 71 | #define REALVIEW_SYS_RESETCTL_OFFSET 0x40 | ||
| 72 | #define REALVIEW_SYS_PCICTL_OFFSET 0x44 | ||
| 73 | #define REALVIEW_SYS_MCI_OFFSET 0x48 | ||
| 74 | #define REALVIEW_SYS_FLASH_OFFSET 0x4C | ||
| 75 | #define REALVIEW_SYS_CLCD_OFFSET 0x50 | ||
| 76 | #define REALVIEW_SYS_CLCDSER_OFFSET 0x54 | ||
| 77 | #define REALVIEW_SYS_BOOTCS_OFFSET 0x58 | ||
| 78 | #define REALVIEW_SYS_24MHz_OFFSET 0x5C | ||
| 79 | #define REALVIEW_SYS_MISC_OFFSET 0x60 | ||
| 80 | #define REALVIEW_SYS_IOSEL_OFFSET 0x70 | ||
| 81 | #define REALVIEW_SYS_PROCID_OFFSET 0x84 | ||
| 82 | #define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0 | ||
| 83 | #define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4 | ||
| 84 | #define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8 | ||
| 85 | #define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC | ||
| 86 | #define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0 | ||
| 87 | |||
| 88 | #define REALVIEW_SYS_BASE 0x10000000 | ||
| 89 | #define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) | ||
| 90 | #define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET) | ||
| 91 | #define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET) | ||
| 92 | #define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET) | ||
| 93 | #define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET) | ||
| 94 | |||
| 95 | #define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET) | ||
| 96 | #define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET) | ||
| 97 | #define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET) | ||
| 98 | #define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET) | ||
| 99 | #define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET) | ||
| 100 | #define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET) | ||
| 101 | #define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET) | ||
| 102 | #define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET) | ||
| 103 | #define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET) | ||
| 104 | #define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET) | ||
| 105 | #define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET) | ||
| 106 | #define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET) | ||
| 107 | #define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET) | ||
| 108 | #define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET) | ||
| 109 | #define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET) | ||
| 110 | #define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET) | ||
| 111 | #define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET) | ||
| 112 | #define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) | ||
| 113 | #define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) | ||
| 114 | #define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) | ||
| 115 | #define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET) | ||
| 116 | #define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) | ||
| 117 | #define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) | ||
| 118 | #define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) | ||
| 119 | #define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET) | ||
| 120 | #define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET) | ||
| 121 | |||
| 122 | /* | ||
| 123 | * Values for REALVIEW_SYS_RESET_CTRL | ||
| 124 | */ | ||
| 125 | #define REALVIEW_SYS_CTRL_RESET_CONFIGCLR 0x01 | ||
| 126 | #define REALVIEW_SYS_CTRL_RESET_CONFIGINIT 0x02 | ||
| 127 | #define REALVIEW_SYS_CTRL_RESET_DLLRESET 0x03 | ||
| 128 | #define REALVIEW_SYS_CTRL_RESET_PLLRESET 0x04 | ||
| 129 | #define REALVIEW_SYS_CTRL_RESET_POR 0x05 | ||
| 130 | #define REALVIEW_SYS_CTRL_RESET_DoC 0x06 | ||
| 131 | |||
| 132 | #define REALVIEW_SYS_CTRL_LED (1 << 0) | ||
| 133 | |||
| 134 | |||
| 135 | /* ------------------------------------------------------------------------ | ||
| 136 | * RealView control registers | ||
| 137 | * ------------------------------------------------------------------------ | ||
| 138 | */ | ||
| 139 | |||
| 140 | /* | ||
| 141 | * REALVIEW_IDFIELD | ||
| 142 | * | ||
| 143 | * 31:24 = manufacturer (0x41 = ARM) | ||
| 144 | * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) | ||
| 145 | * 15:12 = FPGA (0x3 = XVC600 or XVC600E) | ||
| 146 | * 11:4 = build value | ||
| 147 | * 3:0 = revision number (0x1 = rev B (AHB)) | ||
| 148 | */ | ||
| 149 | |||
| 150 | /* | ||
| 151 | * REALVIEW_SYS_LOCK | ||
| 152 | * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, | ||
| 153 | * SYS_CLD, SYS_BOOTCS | ||
| 154 | */ | ||
| 155 | #define REALVIEW_SYS_LOCK_LOCKED (1 << 16) | ||
| 156 | #define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ | ||
| 157 | |||
| 158 | /* | ||
| 159 | * REALVIEW_SYS_FLASH | ||
| 160 | */ | ||
| 161 | #define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ | ||
| 162 | |||
| 163 | /* | ||
| 164 | * REALVIEW_INTREG | ||
| 165 | * - used to acknowledge and control MMCI and UART interrupts | ||
| 166 | */ | ||
| 167 | #define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ | ||
| 168 | #define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ | ||
| 169 | #define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */ | ||
| 170 | /* write 1 to acknowledge and clear */ | ||
| 171 | #define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ | ||
| 172 | #define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ | ||
| 173 | |||
| 174 | /* | ||
| 175 | * RealView common peripheral addresses | ||
| 176 | */ | ||
| 177 | #define REALVIEW_SCTL_BASE 0x10001000 /* System controller */ | ||
| 178 | #define REALVIEW_I2C_BASE 0x10002000 /* I2C control */ | ||
| 179 | #define REALVIEW_AACI_BASE 0x10004000 /* Audio */ | ||
| 180 | #define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */ | ||
| 181 | #define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */ | ||
| 182 | #define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */ | ||
| 183 | #define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */ | ||
| 184 | #define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */ | ||
| 185 | #define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */ | ||
| 186 | #define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */ | ||
| 187 | #define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */ | ||
| 188 | #define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ | ||
| 189 | |||
| 190 | /* PCI space */ | ||
| 191 | #define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */ | ||
| 192 | #define REALVIEW_PCI_CFG_BASE 0x42000000 | ||
| 193 | #define REALVIEW_PCI_MEM_BASE0 0x44000000 | ||
| 194 | #define REALVIEW_PCI_MEM_BASE1 0x50000000 | ||
| 195 | #define REALVIEW_PCI_MEM_BASE2 0x60000000 | ||
| 196 | /* Sizes of above maps */ | ||
| 197 | #define REALVIEW_PCI_BASE_SIZE 0x01000000 | ||
| 198 | #define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000 | ||
| 199 | #define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */ | ||
| 200 | #define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */ | ||
| 201 | #define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */ | ||
| 202 | |||
| 203 | #define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ | ||
| 204 | #define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */ | ||
| 205 | |||
| 206 | /* | ||
| 207 | * Disk on Chip | ||
| 208 | */ | ||
| 209 | #define REALVIEW_DOC_BASE 0x2C000000 | ||
| 210 | #define REALVIEW_DOC_SIZE (16 << 20) | ||
| 211 | #define REALVIEW_DOC_PAGE_SIZE 512 | ||
| 212 | #define REALVIEW_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE) | ||
| 213 | |||
| 214 | #define ERASE_UNIT_PAGES 32 | ||
| 215 | #define START_PAGE 0x80 | ||
| 216 | |||
| 217 | /* | ||
| 218 | * LED settings, bits [7:0] | ||
| 219 | */ | ||
| 220 | #define REALVIEW_SYS_LED0 (1 << 0) | ||
| 221 | #define REALVIEW_SYS_LED1 (1 << 1) | ||
| 222 | #define REALVIEW_SYS_LED2 (1 << 2) | ||
| 223 | #define REALVIEW_SYS_LED3 (1 << 3) | ||
| 224 | #define REALVIEW_SYS_LED4 (1 << 4) | ||
| 225 | #define REALVIEW_SYS_LED5 (1 << 5) | ||
| 226 | #define REALVIEW_SYS_LED6 (1 << 6) | ||
| 227 | #define REALVIEW_SYS_LED7 (1 << 7) | ||
| 228 | |||
| 229 | #define ALL_LEDS 0xFF | ||
| 230 | |||
| 231 | #define LED_BANK REALVIEW_SYS_LED | ||
| 232 | |||
| 233 | /* | ||
| 234 | * Control registers | ||
| 235 | */ | ||
| 236 | #define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */ | ||
| 237 | #define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */ | ||
| 238 | #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ | ||
| 239 | #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ | ||
| 240 | |||
| 241 | /* | ||
| 242 | * Application Flash | ||
| 243 | * | ||
| 244 | */ | ||
| 245 | #define FLASH_BASE REALVIEW_FLASH_BASE | ||
| 246 | #define FLASH_SIZE REALVIEW_FLASH_SIZE | ||
| 247 | #define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) | ||
| 248 | #define FLASH_BLOCK_SIZE SZ_128K | ||
| 249 | |||
| 250 | /* | ||
| 251 | * Boot Flash | ||
| 252 | * | ||
| 253 | */ | ||
| 254 | #define EPROM_BASE REALVIEW_BOOT_ROM_HI | ||
| 255 | #define EPROM_SIZE REALVIEW_BOOT_ROM_SIZE | ||
| 256 | #define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) | ||
| 257 | |||
| 258 | /* | ||
| 259 | * Clean base - dummy | ||
| 260 | * | ||
| 261 | */ | ||
| 262 | #define CLEAN_BASE EPROM_BASE | ||
| 263 | |||
| 264 | /* | ||
| 265 | * System controller bit assignment | ||
| 266 | */ | ||
| 267 | #define REALVIEW_REFCLK 0 | ||
| 268 | #define REALVIEW_TIMCLK 1 | ||
| 269 | |||
| 270 | #define REALVIEW_TIMER1_EnSel 15 | ||
| 271 | #define REALVIEW_TIMER2_EnSel 17 | ||
| 272 | #define REALVIEW_TIMER3_EnSel 19 | ||
| 273 | #define REALVIEW_TIMER4_EnSel 21 | ||
| 274 | |||
| 275 | |||
| 276 | #define MAX_TIMER 2 | ||
| 277 | #define MAX_PERIOD 699050 | ||
| 278 | #define TICKS_PER_uSEC 1 | ||
| 279 | |||
| 280 | /* | ||
| 281 | * These are useconds NOT ticks. | ||
| 282 | * | ||
| 283 | */ | ||
| 284 | #define mSEC_1 1000 | ||
| 285 | #define mSEC_5 (mSEC_1 * 5) | ||
| 286 | #define mSEC_10 (mSEC_1 * 10) | ||
| 287 | #define mSEC_25 (mSEC_1 * 25) | ||
| 288 | #define SEC_1 (mSEC_1 * 1000) | ||
| 289 | |||
| 290 | #define REALVIEW_CSR_BASE 0x10000000 | ||
| 291 | #define REALVIEW_CSR_SIZE 0x10000000 | ||
| 292 | |||
| 293 | #endif /* __ASM_ARCH_PLATFORM_H */ | ||
diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h deleted file mode 100644 index d55802d645af..000000000000 --- a/include/asm-arm/arch-realview/scu.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | #ifndef __ASMARM_ARCH_SCU_H | ||
| 2 | #define __ASMARM_ARCH_SCU_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * SCU registers | ||
| 6 | */ | ||
| 7 | #define SCU_CTRL 0x00 | ||
| 8 | #define SCU_CONFIG 0x04 | ||
| 9 | #define SCU_CPU_STATUS 0x08 | ||
| 10 | #define SCU_INVALIDATE 0x0c | ||
| 11 | #define SCU_FPGA_REVISION 0x10 | ||
| 12 | |||
| 13 | #endif | ||
diff --git a/include/asm-arm/arch-realview/smp.h b/include/asm-arm/arch-realview/smp.h deleted file mode 100644 index 515819efd046..000000000000 --- a/include/asm-arm/arch-realview/smp.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | #ifndef ASMARM_ARCH_SMP_H | ||
| 2 | #define ASMARM_ARCH_SMP_H | ||
| 3 | |||
| 4 | |||
| 5 | #include <asm/hardware/gic.h> | ||
| 6 | |||
| 7 | #define hard_smp_processor_id() \ | ||
| 8 | ({ \ | ||
| 9 | unsigned int cpunum; \ | ||
| 10 | __asm__("mrc p15, 0, %0, c0, c0, 5" \ | ||
| 11 | : "=r" (cpunum)); \ | ||
| 12 | cpunum &= 0x0F; \ | ||
| 13 | }) | ||
| 14 | |||
| 15 | /* | ||
| 16 | * We use IRQ1 as the IPI | ||
| 17 | */ | ||
| 18 | static inline void smp_cross_call(cpumask_t callmap) | ||
| 19 | { | ||
| 20 | gic_raise_softirq(callmap, 1); | ||
| 21 | } | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Do nothing on MPcore. | ||
| 25 | */ | ||
| 26 | static inline void smp_cross_call_done(cpumask_t callmap) | ||
| 27 | { | ||
| 28 | } | ||
| 29 | |||
| 30 | #endif | ||
diff --git a/include/asm-arm/arch-realview/system.h b/include/asm-arm/arch-realview/system.h deleted file mode 100644 index bff3d3fcf846..000000000000 --- a/include/asm-arm/arch-realview/system.h +++ /dev/null | |||
| @@ -1,51 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-realview/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 22 | #define __ASM_ARCH_SYSTEM_H | ||
| 23 | |||
| 24 | #include <asm/arch/hardware.h> | ||
| 25 | #include <asm/io.h> | ||
| 26 | #include <asm/arch/platform.h> | ||
| 27 | |||
| 28 | static inline void arch_idle(void) | ||
| 29 | { | ||
| 30 | /* | ||
| 31 | * This should do all the clock switching | ||
| 32 | * and wait for interrupt tricks | ||
| 33 | */ | ||
| 34 | cpu_do_idle(); | ||
| 35 | } | ||
| 36 | |||
| 37 | static inline void arch_reset(char mode) | ||
| 38 | { | ||
| 39 | void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET; | ||
| 40 | unsigned int val; | ||
| 41 | |||
| 42 | /* | ||
| 43 | * To reset, we hit the on-board reset register | ||
| 44 | * in the system FPGA | ||
| 45 | */ | ||
| 46 | val = __raw_readl(hdr_ctrl); | ||
| 47 | val |= REALVIEW_SYS_CTRL_RESET_CONFIGCLR; | ||
| 48 | __raw_writel(val, hdr_ctrl); | ||
| 49 | } | ||
| 50 | |||
| 51 | #endif | ||
diff --git a/include/asm-arm/arch-realview/timex.h b/include/asm-arm/arch-realview/timex.h deleted file mode 100644 index 5b9d82d0a5e0..000000000000 --- a/include/asm-arm/arch-realview/timex.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-realview/timex.h | ||
| 3 | * | ||
| 4 | * RealView architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003 ARM Limited | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define CLOCK_TICK_RATE (50000000 / 16) | ||
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h deleted file mode 100644 index 3f7ae2e0260d..000000000000 --- a/include/asm-arm/arch-realview/uncompress.h +++ /dev/null | |||
| @@ -1,72 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-realview/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #include <asm/arch/hardware.h> | ||
| 21 | #include <asm/mach-types.h> | ||
| 22 | |||
| 23 | #include <asm/arch/board-eb.h> | ||
| 24 | #include <asm/arch/board-pb11mp.h> | ||
| 25 | #include <asm/arch/board-pb1176.h> | ||
| 26 | |||
| 27 | #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) | ||
| 28 | #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) | ||
| 29 | #define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) | ||
| 30 | #define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Return the UART base address | ||
| 34 | */ | ||
| 35 | static inline unsigned long get_uart_base(void) | ||
| 36 | { | ||
| 37 | if (machine_is_realview_eb()) | ||
| 38 | return REALVIEW_EB_UART0_BASE; | ||
| 39 | else if (machine_is_realview_pb11mp()) | ||
| 40 | return REALVIEW_PB11MP_UART0_BASE; | ||
| 41 | else if (machine_is_realview_pb1176()) | ||
| 42 | return REALVIEW_PB1176_UART0_BASE; | ||
| 43 | else | ||
| 44 | return 0; | ||
| 45 | } | ||
| 46 | |||
| 47 | /* | ||
| 48 | * This does not append a newline | ||
| 49 | */ | ||
| 50 | static inline void putc(int c) | ||
| 51 | { | ||
| 52 | unsigned long base = get_uart_base(); | ||
| 53 | |||
| 54 | while (AMBA_UART_FR(base) & (1 << 5)) | ||
| 55 | barrier(); | ||
| 56 | |||
| 57 | AMBA_UART_DR(base) = c; | ||
| 58 | } | ||
| 59 | |||
| 60 | static inline void flush(void) | ||
| 61 | { | ||
| 62 | unsigned long base = get_uart_base(); | ||
| 63 | |||
| 64 | while (AMBA_UART_FR(base) & (1 << 3)) | ||
| 65 | barrier(); | ||
| 66 | } | ||
| 67 | |||
| 68 | /* | ||
| 69 | * nothing to do | ||
| 70 | */ | ||
| 71 | #define arch_decomp_setup() | ||
| 72 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-realview/vmalloc.h b/include/asm-arm/arch-realview/vmalloc.h deleted file mode 100644 index 0ad49af186af..000000000000 --- a/include/asm-arm/arch-realview/vmalloc.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-realview/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * Copyright (C) 2000 Russell King. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #define VMALLOC_END (PAGE_OFFSET + 0x18000000) | ||
diff --git a/include/asm-arm/arch-rpc/acornfb.h b/include/asm-arm/arch-rpc/acornfb.h deleted file mode 100644 index ecb7733a0949..000000000000 --- a/include/asm-arm/arch-rpc/acornfb.h +++ /dev/null | |||
| @@ -1,140 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-rpc/acornfb.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * AcornFB architecture specific code | ||
| 11 | */ | ||
| 12 | |||
| 13 | #define acornfb_bandwidth(var) ((var)->pixclock * 8 / (var)->bits_per_pixel) | ||
| 14 | |||
| 15 | static inline int | ||
| 16 | acornfb_valid_pixrate(struct fb_var_screeninfo *var) | ||
| 17 | { | ||
| 18 | u_long limit; | ||
| 19 | |||
| 20 | if (!var->pixclock) | ||
| 21 | return 0; | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Limits below are taken from RISC OS bandwidthlimit file | ||
| 25 | */ | ||
| 26 | if (current_par.using_vram) { | ||
| 27 | if (current_par.vram_half_sam == 2048) | ||
| 28 | limit = 6578; | ||
| 29 | else | ||
| 30 | limit = 13157; | ||
| 31 | } else { | ||
| 32 | limit = 26315; | ||
| 33 | } | ||
| 34 | |||
| 35 | return acornfb_bandwidth(var) >= limit; | ||
| 36 | } | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Try to find the best PLL parameters for the pixel clock. | ||
| 40 | * This algorithm seems to give best predictable results, | ||
| 41 | * and produces the same values as detailed in the VIDC20 | ||
| 42 | * data sheet. | ||
| 43 | */ | ||
| 44 | static inline u_int | ||
| 45 | acornfb_vidc20_find_pll(u_int pixclk) | ||
| 46 | { | ||
| 47 | u_int r, best_r = 2, best_v = 2; | ||
| 48 | int best_d = 0x7fffffff; | ||
| 49 | |||
| 50 | for (r = 2; r <= 32; r++) { | ||
| 51 | u_int rr, v, p; | ||
| 52 | int d; | ||
| 53 | |||
| 54 | rr = 41667 * r; | ||
| 55 | |||
| 56 | v = (rr + pixclk / 2) / pixclk; | ||
| 57 | |||
| 58 | if (v > 32 || v < 2) | ||
| 59 | continue; | ||
| 60 | |||
| 61 | p = (rr + v / 2) / v; | ||
| 62 | |||
| 63 | d = pixclk - p; | ||
| 64 | |||
| 65 | if (d < 0) | ||
| 66 | d = -d; | ||
| 67 | |||
| 68 | if (d < best_d) { | ||
| 69 | best_d = d; | ||
| 70 | best_v = v - 1; | ||
| 71 | best_r = r - 1; | ||
| 72 | } | ||
| 73 | |||
| 74 | if (d == 0) | ||
| 75 | break; | ||
| 76 | } | ||
| 77 | |||
| 78 | return best_v << 8 | best_r; | ||
| 79 | } | ||
| 80 | |||
| 81 | static inline void | ||
| 82 | acornfb_vidc20_find_rates(struct vidc_timing *vidc, | ||
| 83 | struct fb_var_screeninfo *var) | ||
| 84 | { | ||
| 85 | u_int div; | ||
| 86 | |||
| 87 | /* Select pixel-clock divisor to keep PLL in range */ | ||
| 88 | div = var->pixclock / 9090; /*9921*/ | ||
| 89 | |||
| 90 | /* Limit divisor */ | ||
| 91 | if (div == 0) | ||
| 92 | div = 1; | ||
| 93 | if (div > 8) | ||
| 94 | div = 8; | ||
| 95 | |||
| 96 | /* Encode divisor to VIDC20 setting */ | ||
| 97 | switch (div) { | ||
| 98 | case 1: vidc->control |= VIDC20_CTRL_PIX_CK; break; | ||
| 99 | case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break; | ||
| 100 | case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break; | ||
| 101 | case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break; | ||
| 102 | case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break; | ||
| 103 | case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break; | ||
| 104 | case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break; | ||
| 105 | case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break; | ||
| 106 | } | ||
| 107 | |||
| 108 | /* | ||
| 109 | * With VRAM, the FIFO can be set to the highest possible setting | ||
| 110 | * because there are no latency considerations for other memory | ||
| 111 | * accesses. However, in 64 bit bus mode the FIFO preload value | ||
| 112 | * must not be set to VIDC20_CTRL_FIFO_28 because this will let | ||
| 113 | * the FIFO overflow. See VIDC20 manual page 33 (6.0 Setting the | ||
| 114 | * FIFO preload value). | ||
| 115 | */ | ||
| 116 | if (current_par.using_vram) { | ||
| 117 | if (current_par.vram_half_sam == 2048) | ||
| 118 | vidc->control |= VIDC20_CTRL_FIFO_24; | ||
| 119 | else | ||
| 120 | vidc->control |= VIDC20_CTRL_FIFO_28; | ||
| 121 | } else { | ||
| 122 | unsigned long bandwidth = acornfb_bandwidth(var); | ||
| 123 | |||
| 124 | /* Encode bandwidth as VIDC20 setting */ | ||
| 125 | if (bandwidth > 33334) /* < 30.0MB/s */ | ||
| 126 | vidc->control |= VIDC20_CTRL_FIFO_16; | ||
| 127 | else if (bandwidth > 26666) /* < 37.5MB/s */ | ||
| 128 | vidc->control |= VIDC20_CTRL_FIFO_20; | ||
| 129 | else if (bandwidth > 22222) /* < 45.0MB/s */ | ||
| 130 | vidc->control |= VIDC20_CTRL_FIFO_24; | ||
| 131 | else /* > 45.0MB/s */ | ||
| 132 | vidc->control |= VIDC20_CTRL_FIFO_28; | ||
| 133 | } | ||
| 134 | |||
| 135 | /* Find the PLL values */ | ||
| 136 | vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div); | ||
| 137 | } | ||
| 138 | |||
| 139 | #define acornfb_default_control() (VIDC20_CTRL_PIX_VCLK) | ||
| 140 | #define acornfb_default_econtrol() (VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3)) | ||
diff --git a/include/asm-arm/arch-rpc/debug-macro.S b/include/asm-arm/arch-rpc/debug-macro.S deleted file mode 100644 index c634c8d8f4a1..000000000000 --- a/include/asm-arm/arch-rpc/debug-macro.S +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-rpc/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | moveq \rx, #0x03000000 | ||
| 18 | movne \rx, #0xe0000000 | ||
| 19 | orr \rx, \rx, #0x00010000 | ||
| 20 | orr \rx, \rx, #0x00000fe0 | ||
| 21 | .endm | ||
| 22 | |||
| 23 | #define UART_SHIFT 2 | ||
| 24 | #define FLOW_CONTROL | ||
| 25 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/include/asm-arm/arch-rpc/dma.h b/include/asm-arm/arch-rpc/dma.h deleted file mode 100644 index d24a27e30b93..000000000000 --- a/include/asm-arm/arch-rpc/dma.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-rpc/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARCH_DMA_H | ||
| 11 | #define __ASM_ARCH_DMA_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * This is the maximum DMA address that can be DMAd to. | ||
| 15 | * There should not be more than (0xd0000000 - 0xc0000000) | ||
| 16 | * bytes of RAM. | ||
| 17 | */ | ||
| 18 | #define MAX_DMA_ADDRESS 0xd0000000 | ||
| 19 | #define MAX_DMA_CHANNELS 8 | ||
| 20 | |||
| 21 | #define DMA_0 0 | ||
| 22 | #define DMA_1 1 | ||
| 23 | #define DMA_2 2 | ||
| 24 | #define DMA_3 3 | ||
| 25 | #define DMA_S0 4 | ||
| 26 | #define DMA_S1 5 | ||
| 27 | #define DMA_VIRTUAL_FLOPPY 6 | ||
| 28 | #define DMA_VIRTUAL_SOUND 7 | ||
| 29 | |||
| 30 | #define DMA_FLOPPY DMA_VIRTUAL_FLOPPY | ||
| 31 | |||
| 32 | #endif /* _ASM_ARCH_DMA_H */ | ||
| 33 | |||
diff --git a/include/asm-arm/arch-rpc/entry-macro.S b/include/asm-arm/arch-rpc/entry-macro.S deleted file mode 100644 index 5bd55557ccca..000000000000 --- a/include/asm-arm/arch-rpc/entry-macro.S +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | #include <asm/arch/hardware.h> | ||
| 2 | #include <asm/hardware/entry-macro-iomd.S> | ||
| 3 | |||
| 4 | .equ ioc_base_high, IOC_BASE & 0xff000000 | ||
| 5 | .equ ioc_base_low, IOC_BASE & 0x00ff0000 | ||
| 6 | |||
| 7 | .macro get_irqnr_preamble, base, tmp | ||
| 8 | mov \base, #ioc_base_high @ point at IOC | ||
| 9 | .if ioc_base_low | ||
| 10 | orr \base, \base, #ioc_base_low | ||
| 11 | .endif | ||
| 12 | .endm | ||
| 13 | |||
| 14 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 15 | .endm | ||
| 16 | |||
diff --git a/include/asm-arm/arch-rpc/hardware.h b/include/asm-arm/arch-rpc/hardware.h deleted file mode 100644 index 7480f4e8d974..000000000000 --- a/include/asm-arm/arch-rpc/hardware.h +++ /dev/null | |||
| @@ -1,83 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-rpc/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996-1999 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This file contains the hardware definitions of the RiscPC series machines. | ||
| 11 | */ | ||
| 12 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 13 | #define __ASM_ARCH_HARDWARE_H | ||
| 14 | |||
| 15 | #include <asm/arch/memory.h> | ||
| 16 | |||
| 17 | #ifndef __ASSEMBLY__ | ||
| 18 | #define IOMEM(x) ((void __iomem *)(unsigned long)(x)) | ||
| 19 | #else | ||
| 20 | #define IOMEM(x) x | ||
| 21 | #endif /* __ASSEMBLY__ */ | ||
| 22 | |||
| 23 | /* | ||
| 24 | * What hardware must be present | ||
| 25 | */ | ||
| 26 | #define HAS_IOMD | ||
| 27 | #define HAS_VIDC20 | ||
| 28 | |||
| 29 | /* Hardware addresses of major areas. | ||
| 30 | * *_START is the physical address | ||
| 31 | * *_SIZE is the size of the region | ||
| 32 | * *_BASE is the virtual address | ||
| 33 | */ | ||
| 34 | #define RAM_SIZE 0x10000000 | ||
| 35 | #define RAM_START 0x10000000 | ||
| 36 | |||
| 37 | #define EASI_SIZE 0x08000000 /* EASI I/O */ | ||
| 38 | #define EASI_START 0x08000000 | ||
| 39 | #define EASI_BASE 0xe5000000 | ||
| 40 | |||
| 41 | #define IO_START 0x03000000 /* I/O */ | ||
| 42 | #define IO_SIZE 0x01000000 | ||
| 43 | #define IO_BASE IOMEM(0xe0000000) | ||
| 44 | |||
| 45 | #define SCREEN_START 0x02000000 /* VRAM */ | ||
| 46 | #define SCREEN_END 0xdfc00000 | ||
| 47 | #define SCREEN_BASE 0xdf800000 | ||
| 48 | |||
| 49 | #define UNCACHEABLE_ADDR 0xdf010000 | ||
| 50 | |||
| 51 | /* | ||
| 52 | * IO Addresses | ||
| 53 | */ | ||
| 54 | #define VIDC_BASE IOMEM(0xe0400000) | ||
| 55 | #define EXPMASK_BASE 0xe0360000 | ||
| 56 | #define IOMD_BASE IOMEM(0xe0200000) | ||
| 57 | #define IOC_BASE IOMEM(0xe0200000) | ||
| 58 | #define PCIO_BASE IOMEM(0xe0010000) | ||
| 59 | #define FLOPPYDMA_BASE IOMEM(0xe002a000) | ||
| 60 | |||
| 61 | #define vidc_writel(val) __raw_writel(val, VIDC_BASE) | ||
| 62 | |||
| 63 | #define IO_EC_EASI_BASE 0x81400000 | ||
| 64 | #define IO_EC_IOC4_BASE 0x8009c000 | ||
| 65 | #define IO_EC_IOC_BASE 0x80090000 | ||
| 66 | #define IO_EC_MEMC8_BASE 0x8000ac00 | ||
| 67 | #define IO_EC_MEMC_BASE 0x80000000 | ||
| 68 | |||
| 69 | #define NETSLOT_BASE 0x0302b000 | ||
| 70 | #define NETSLOT_SIZE 0x00001000 | ||
| 71 | |||
| 72 | #define PODSLOT_IOC0_BASE 0x03240000 | ||
| 73 | #define PODSLOT_IOC4_BASE 0x03270000 | ||
| 74 | #define PODSLOT_IOC_SIZE (1 << 14) | ||
| 75 | #define PODSLOT_MEMC_BASE 0x03000000 | ||
| 76 | #define PODSLOT_MEMC_SIZE (1 << 14) | ||
| 77 | #define PODSLOT_EASI_BASE 0x08000000 | ||
| 78 | #define PODSLOT_EASI_SIZE (1 << 24) | ||
| 79 | |||
| 80 | #define EXPMASK_STATUS (EXPMASK_BASE + 0x00) | ||
| 81 | #define EXPMASK_ENABLE (EXPMASK_BASE + 0x04) | ||
| 82 | |||
| 83 | #endif | ||
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h deleted file mode 100644 index 0d10d4591a45..000000000000 --- a/include/asm-arm/arch-rpc/io.h +++ /dev/null | |||
| @@ -1,258 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-rpc/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * Modifications: | ||
| 11 | * 06-Dec-1997 RMK Created. | ||
| 12 | */ | ||
| 13 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 14 | #define __ASM_ARM_ARCH_IO_H | ||
| 15 | |||
| 16 | #include <asm/arch/hardware.h> | ||
| 17 | |||
| 18 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 19 | |||
| 20 | /* | ||
| 21 | * GCC is totally crap at loading/storing data. We try to persuade it | ||
| 22 | * to do the right thing by using these whereever possible instead of | ||
| 23 | * the above. | ||
| 24 | */ | ||
| 25 | #define __arch_base_getb(b,o) \ | ||
| 26 | ({ \ | ||
| 27 | unsigned int __v, __r = (b); \ | ||
| 28 | __asm__ __volatile__( \ | ||
| 29 | "ldrb %0, [%1, %2]" \ | ||
| 30 | : "=r" (__v) \ | ||
| 31 | : "r" (__r), "Ir" (o)); \ | ||
| 32 | __v; \ | ||
| 33 | }) | ||
| 34 | |||
| 35 | #define __arch_base_getl(b,o) \ | ||
| 36 | ({ \ | ||
| 37 | unsigned int __v, __r = (b); \ | ||
| 38 | __asm__ __volatile__( \ | ||
| 39 | "ldr %0, [%1, %2]" \ | ||
| 40 | : "=r" (__v) \ | ||
| 41 | : "r" (__r), "Ir" (o)); \ | ||
| 42 | __v; \ | ||
| 43 | }) | ||
| 44 | |||
| 45 | #define __arch_base_putb(v,b,o) \ | ||
| 46 | ({ \ | ||
| 47 | unsigned int __r = (b); \ | ||
| 48 | __asm__ __volatile__( \ | ||
| 49 | "strb %0, [%1, %2]" \ | ||
| 50 | : \ | ||
| 51 | : "r" (v), "r" (__r), "Ir" (o));\ | ||
| 52 | }) | ||
| 53 | |||
| 54 | #define __arch_base_putl(v,b,o) \ | ||
| 55 | ({ \ | ||
| 56 | unsigned int __r = (b); \ | ||
| 57 | __asm__ __volatile__( \ | ||
| 58 | "str %0, [%1, %2]" \ | ||
| 59 | : \ | ||
| 60 | : "r" (v), "r" (__r), "Ir" (o));\ | ||
| 61 | }) | ||
| 62 | |||
| 63 | /* | ||
| 64 | * We use two different types of addressing - PC style addresses, and ARM | ||
| 65 | * addresses. PC style accesses the PC hardware with the normal PC IO | ||
| 66 | * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ | ||
| 67 | * and are translated to the start of IO. Note that all addresses are | ||
| 68 | * shifted left! | ||
| 69 | */ | ||
| 70 | #define __PORT_PCIO(x) (!((x) & 0x80000000)) | ||
| 71 | |||
| 72 | /* | ||
| 73 | * Dynamic IO functions. | ||
| 74 | */ | ||
| 75 | static inline void __outb (unsigned int value, unsigned int port) | ||
| 76 | { | ||
| 77 | unsigned long temp; | ||
| 78 | __asm__ __volatile__( | ||
| 79 | "tst %2, #0x80000000\n\t" | ||
| 80 | "mov %0, %4\n\t" | ||
| 81 | "addeq %0, %0, %3\n\t" | ||
| 82 | "strb %1, [%0, %2, lsl #2] @ outb" | ||
| 83 | : "=&r" (temp) | ||
| 84 | : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) | ||
| 85 | : "cc"); | ||
| 86 | } | ||
| 87 | |||
| 88 | static inline void __outw (unsigned int value, unsigned int port) | ||
| 89 | { | ||
| 90 | unsigned long temp; | ||
| 91 | __asm__ __volatile__( | ||
| 92 | "tst %2, #0x80000000\n\t" | ||
| 93 | "mov %0, %4\n\t" | ||
| 94 | "addeq %0, %0, %3\n\t" | ||
| 95 | "str %1, [%0, %2, lsl #2] @ outw" | ||
| 96 | : "=&r" (temp) | ||
| 97 | : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) | ||
| 98 | : "cc"); | ||
| 99 | } | ||
| 100 | |||
| 101 | static inline void __outl (unsigned int value, unsigned int port) | ||
| 102 | { | ||
| 103 | unsigned long temp; | ||
| 104 | __asm__ __volatile__( | ||
| 105 | "tst %2, #0x80000000\n\t" | ||
| 106 | "mov %0, %4\n\t" | ||
| 107 | "addeq %0, %0, %3\n\t" | ||
| 108 | "str %1, [%0, %2, lsl #2] @ outl" | ||
| 109 | : "=&r" (temp) | ||
| 110 | : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) | ||
| 111 | : "cc"); | ||
| 112 | } | ||
| 113 | |||
| 114 | #define DECLARE_DYN_IN(sz,fnsuffix,instr) \ | ||
| 115 | static inline unsigned sz __in##fnsuffix (unsigned int port) \ | ||
| 116 | { \ | ||
| 117 | unsigned long temp, value; \ | ||
| 118 | __asm__ __volatile__( \ | ||
| 119 | "tst %2, #0x80000000\n\t" \ | ||
| 120 | "mov %0, %4\n\t" \ | ||
| 121 | "addeq %0, %0, %3\n\t" \ | ||
| 122 | "ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \ | ||
| 123 | : "=&r" (temp), "=r" (value) \ | ||
| 124 | : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \ | ||
| 125 | : "cc"); \ | ||
| 126 | return (unsigned sz)value; \ | ||
| 127 | } | ||
| 128 | |||
| 129 | static inline void __iomem *__deprecated __ioaddr(unsigned int port) | ||
| 130 | { | ||
| 131 | void __iomem *ret; | ||
| 132 | if (__PORT_PCIO(port)) | ||
| 133 | ret = PCIO_BASE; | ||
| 134 | else | ||
| 135 | ret = IO_BASE; | ||
| 136 | return ret + (port << 2); | ||
| 137 | } | ||
| 138 | |||
| 139 | #define DECLARE_IO(sz,fnsuffix,instr) \ | ||
| 140 | DECLARE_DYN_IN(sz,fnsuffix,instr) | ||
| 141 | |||
| 142 | DECLARE_IO(char,b,"b") | ||
| 143 | DECLARE_IO(short,w,"") | ||
| 144 | DECLARE_IO(int,l,"") | ||
| 145 | |||
| 146 | #undef DECLARE_IO | ||
| 147 | #undef DECLARE_DYN_IN | ||
| 148 | |||
| 149 | /* | ||
| 150 | * Constant address IO functions | ||
| 151 | * | ||
| 152 | * These have to be macros for the 'J' constraint to work - | ||
| 153 | * +/-4096 immediate operand. | ||
| 154 | */ | ||
| 155 | #define __outbc(value,port) \ | ||
| 156 | ({ \ | ||
| 157 | if (__PORT_PCIO((port))) \ | ||
| 158 | __asm__ __volatile__( \ | ||
| 159 | "strb %0, [%1, %2] @ outbc" \ | ||
| 160 | : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 161 | else \ | ||
| 162 | __asm__ __volatile__( \ | ||
| 163 | "strb %0, [%1, %2] @ outbc" \ | ||
| 164 | : : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 165 | }) | ||
| 166 | |||
| 167 | #define __inbc(port) \ | ||
| 168 | ({ \ | ||
| 169 | unsigned char result; \ | ||
| 170 | if (__PORT_PCIO((port))) \ | ||
| 171 | __asm__ __volatile__( \ | ||
| 172 | "ldrb %0, [%1, %2] @ inbc" \ | ||
| 173 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 174 | else \ | ||
| 175 | __asm__ __volatile__( \ | ||
| 176 | "ldrb %0, [%1, %2] @ inbc" \ | ||
| 177 | : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 178 | result; \ | ||
| 179 | }) | ||
| 180 | |||
| 181 | #define __outwc(value,port) \ | ||
| 182 | ({ \ | ||
| 183 | unsigned long __v = value; \ | ||
| 184 | if (__PORT_PCIO((port))) \ | ||
| 185 | __asm__ __volatile__( \ | ||
| 186 | "str %0, [%1, %2] @ outwc" \ | ||
| 187 | : : "r" (__v|__v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 188 | else \ | ||
| 189 | __asm__ __volatile__( \ | ||
| 190 | "str %0, [%1, %2] @ outwc" \ | ||
| 191 | : : "r" (__v|__v<<16), "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 192 | }) | ||
| 193 | |||
| 194 | #define __inwc(port) \ | ||
| 195 | ({ \ | ||
| 196 | unsigned short result; \ | ||
| 197 | if (__PORT_PCIO((port))) \ | ||
| 198 | __asm__ __volatile__( \ | ||
| 199 | "ldr %0, [%1, %2] @ inwc" \ | ||
| 200 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 201 | else \ | ||
| 202 | __asm__ __volatile__( \ | ||
| 203 | "ldr %0, [%1, %2] @ inwc" \ | ||
| 204 | : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 205 | result & 0xffff; \ | ||
| 206 | }) | ||
| 207 | |||
| 208 | #define __outlc(value,port) \ | ||
| 209 | ({ \ | ||
| 210 | unsigned long __v = value; \ | ||
| 211 | if (__PORT_PCIO((port))) \ | ||
| 212 | __asm__ __volatile__( \ | ||
| 213 | "str %0, [%1, %2] @ outlc" \ | ||
| 214 | : : "r" (__v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 215 | else \ | ||
| 216 | __asm__ __volatile__( \ | ||
| 217 | "str %0, [%1, %2] @ outlc" \ | ||
| 218 | : : "r" (__v), "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 219 | }) | ||
| 220 | |||
| 221 | #define __inlc(port) \ | ||
| 222 | ({ \ | ||
| 223 | unsigned long result; \ | ||
| 224 | if (__PORT_PCIO((port))) \ | ||
| 225 | __asm__ __volatile__( \ | ||
| 226 | "ldr %0, [%1, %2] @ inlc" \ | ||
| 227 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
| 228 | else \ | ||
| 229 | __asm__ __volatile__( \ | ||
| 230 | "ldr %0, [%1, %2] @ inlc" \ | ||
| 231 | : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ | ||
| 232 | result; \ | ||
| 233 | }) | ||
| 234 | |||
| 235 | #define __ioaddrc(port) __ioaddr(port) | ||
| 236 | |||
| 237 | #define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) | ||
| 238 | #define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) | ||
| 239 | #define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) | ||
| 240 | #define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) | ||
| 241 | #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) | ||
| 242 | #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) | ||
| 243 | #define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) | ||
| 244 | /* the following macro is deprecated */ | ||
| 245 | #define ioaddr(port) ((unsigned long)__ioaddr((port))) | ||
| 246 | |||
| 247 | #define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) | ||
| 248 | #define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) | ||
| 249 | |||
| 250 | #define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) | ||
| 251 | #define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) | ||
| 252 | |||
| 253 | /* | ||
| 254 | * 1:1 mapping for ioremapped regions. | ||
| 255 | */ | ||
| 256 | #define __mem_pci(x) (x) | ||
| 257 | |||
| 258 | #endif | ||
diff --git a/include/asm-arm/arch-rpc/irqs.h b/include/asm-arm/arch-rpc/irqs.h deleted file mode 100644 index 27c35b05b27d..000000000000 --- a/include/asm-arm/arch-rpc/irqs.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-rpc/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #define IRQ_PRINTER 0 | ||
| 12 | #define IRQ_BATLOW 1 | ||
| 13 | #define IRQ_FLOPPYINDEX 2 | ||
| 14 | #define IRQ_VSYNCPULSE 3 | ||
| 15 | #define IRQ_POWERON 4 | ||
| 16 | #define IRQ_TIMER0 5 | ||
| 17 | #define IRQ_TIMER1 6 | ||
| 18 | #define IRQ_IMMEDIATE 7 | ||
| 19 | #define IRQ_EXPCARDFIQ 8 | ||
| 20 | #define IRQ_HARDDISK 9 | ||
| 21 | #define IRQ_SERIALPORT 10 | ||
| 22 | #define IRQ_FLOPPYDISK 12 | ||
| 23 | #define IRQ_EXPANSIONCARD 13 | ||
| 24 | #define IRQ_KEYBOARDTX 14 | ||
| 25 | #define IRQ_KEYBOARDRX 15 | ||
| 26 | |||
| 27 | #define IRQ_DMA0 16 | ||
| 28 | #define IRQ_DMA1 17 | ||
| 29 | #define IRQ_DMA2 18 | ||
| 30 | #define IRQ_DMA3 19 | ||
| 31 | #define IRQ_DMAS0 20 | ||
| 32 | #define IRQ_DMAS1 21 | ||
| 33 | |||
| 34 | #define FIQ_FLOPPYDATA 0 | ||
| 35 | #define FIQ_ECONET 2 | ||
| 36 | #define FIQ_SERIALPORT 4 | ||
| 37 | #define FIQ_EXPANSIONCARD 6 | ||
| 38 | #define FIQ_FORCE 7 | ||
| 39 | |||
| 40 | /* | ||
| 41 | * This is the offset of the FIQ "IRQ" numbers | ||
| 42 | */ | ||
| 43 | #define FIQ_START 64 | ||
| 44 | |||
| 45 | #define IRQ_TIMER IRQ_TIMER0 | ||
| 46 | |||
diff --git a/include/asm-arm/arch-rpc/memory.h b/include/asm-arm/arch-rpc/memory.h deleted file mode 100644 index 303c424ce673..000000000000 --- a/include/asm-arm/arch-rpc/memory.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-rpc/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996,1997,1998 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * Changelog: | ||
| 11 | * 20-Oct-1996 RMK Created | ||
| 12 | * 31-Dec-1997 RMK Fixed definitions to reduce warnings | ||
| 13 | * 11-Jan-1998 RMK Uninlined to reduce hits on cache | ||
| 14 | * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt | ||
| 15 | * 21-Mar-1999 RMK Renamed to memory.h | ||
| 16 | * RMK Added TASK_SIZE and PAGE_OFFSET | ||
| 17 | */ | ||
| 18 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 19 | #define __ASM_ARCH_MEMORY_H | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Physical DRAM offset. | ||
| 23 | */ | ||
| 24 | #define PHYS_OFFSET UL(0x10000000) | ||
| 25 | |||
| 26 | /* | ||
| 27 | * These are exactly the same on the RiscPC as the | ||
| 28 | * physical memory view. | ||
| 29 | */ | ||
| 30 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 31 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 32 | |||
| 33 | /* | ||
| 34 | * Cache flushing area - ROM | ||
| 35 | */ | ||
| 36 | #define FLUSH_BASE_PHYS 0x00000000 | ||
| 37 | #define FLUSH_BASE 0xdf000000 | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-rpc/system.h b/include/asm-arm/arch-rpc/system.h deleted file mode 100644 index ca3277d1d5ea..000000000000 --- a/include/asm-arm/arch-rpc/system.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-rpc/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996-1999 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | #include <asm/hardware/iomd.h> | ||
| 12 | #include <asm/io.h> | ||
| 13 | |||
| 14 | static inline void arch_idle(void) | ||
| 15 | { | ||
| 16 | cpu_do_idle(); | ||
| 17 | } | ||
| 18 | |||
| 19 | static inline void arch_reset(char mode) | ||
| 20 | { | ||
| 21 | iomd_writeb(0, IOMD_ROMCR0); | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Jump into the ROM | ||
| 25 | */ | ||
| 26 | cpu_reset(0); | ||
| 27 | } | ||
diff --git a/include/asm-arm/arch-rpc/timex.h b/include/asm-arm/arch-rpc/timex.h deleted file mode 100644 index ed7df64d960b..000000000000 --- a/include/asm-arm/arch-rpc/timex.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-rpc/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997, 1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * RiscPC architecture timex specifications | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * On the RiscPC, the clock ticks at 2MHz. | ||
| 15 | */ | ||
| 16 | #define CLOCK_TICK_RATE 2000000 | ||
| 17 | |||
diff --git a/include/asm-arm/arch-rpc/uncompress.h b/include/asm-arm/arch-rpc/uncompress.h deleted file mode 100644 index 844e4d469fb2..000000000000 --- a/include/asm-arm/arch-rpc/uncompress.h +++ /dev/null | |||
| @@ -1,198 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-rpc/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #define VIDMEM ((char *)SCREEN_START) | ||
| 11 | |||
| 12 | #include <asm/arch/hardware.h> | ||
| 13 | #include <asm/io.h> | ||
| 14 | #include <asm/setup.h> | ||
| 15 | #include <asm/page.h> | ||
| 16 | |||
| 17 | int video_size_row; | ||
| 18 | unsigned char bytes_per_char_h; | ||
| 19 | extern unsigned long con_charconvtable[256]; | ||
| 20 | |||
| 21 | struct param_struct { | ||
| 22 | unsigned long page_size; | ||
| 23 | unsigned long nr_pages; | ||
| 24 | unsigned long ramdisk_size; | ||
| 25 | unsigned long mountrootrdonly; | ||
| 26 | unsigned long rootdev; | ||
| 27 | unsigned long video_num_cols; | ||
| 28 | unsigned long video_num_rows; | ||
| 29 | unsigned long video_x; | ||
| 30 | unsigned long video_y; | ||
| 31 | unsigned long memc_control_reg; | ||
| 32 | unsigned char sounddefault; | ||
| 33 | unsigned char adfsdrives; | ||
| 34 | unsigned char bytes_per_char_h; | ||
| 35 | unsigned char bytes_per_char_v; | ||
| 36 | unsigned long unused[256/4-11]; | ||
| 37 | }; | ||
| 38 | |||
| 39 | static const unsigned long palette_4[16] = { | ||
| 40 | 0x00000000, | ||
| 41 | 0x000000cc, | ||
| 42 | 0x0000cc00, /* Green */ | ||
| 43 | 0x0000cccc, /* Yellow */ | ||
| 44 | 0x00cc0000, /* Blue */ | ||
| 45 | 0x00cc00cc, /* Magenta */ | ||
| 46 | 0x00cccc00, /* Cyan */ | ||
| 47 | 0x00cccccc, /* White */ | ||
| 48 | 0x00000000, | ||
| 49 | 0x000000ff, | ||
| 50 | 0x0000ff00, | ||
| 51 | 0x0000ffff, | ||
| 52 | 0x00ff0000, | ||
| 53 | 0x00ff00ff, | ||
| 54 | 0x00ffff00, | ||
| 55 | 0x00ffffff | ||
| 56 | }; | ||
| 57 | |||
| 58 | #define palette_setpixel(p) *(unsigned long *)(IO_START+0x00400000) = 0x10000000|((p) & 255) | ||
| 59 | #define palette_write(v) *(unsigned long *)(IO_START+0x00400000) = 0x00000000|((v) & 0x00ffffff) | ||
| 60 | |||
| 61 | /* | ||
| 62 | * params_phys is a linker defined symbol - see | ||
| 63 | * arch/arm/boot/compressed/Makefile | ||
| 64 | */ | ||
| 65 | extern __attribute__((pure)) struct param_struct *params(void); | ||
| 66 | #define params (params()) | ||
| 67 | |||
| 68 | #ifndef STANDALONE_DEBUG | ||
| 69 | static unsigned long video_num_cols; | ||
| 70 | static unsigned long video_num_rows; | ||
| 71 | static unsigned long video_x; | ||
| 72 | static unsigned long video_y; | ||
| 73 | static unsigned char bytes_per_char_v; | ||
| 74 | static int white; | ||
| 75 | |||
| 76 | /* | ||
| 77 | * This does not append a newline | ||
| 78 | */ | ||
| 79 | static void putc(int c) | ||
| 80 | { | ||
| 81 | extern void ll_write_char(char *, char c, char white); | ||
| 82 | int x,y; | ||
| 83 | char *ptr; | ||
| 84 | |||
| 85 | x = video_x; | ||
| 86 | y = video_y; | ||
| 87 | |||
| 88 | if (c == '\n') { | ||
| 89 | if (++y >= video_num_rows) | ||
| 90 | y--; | ||
| 91 | } else if (c == '\r') { | ||
| 92 | x = 0; | ||
| 93 | } else { | ||
| 94 | ptr = VIDMEM + ((y*video_num_cols*bytes_per_char_v+x)*bytes_per_char_h); | ||
| 95 | ll_write_char(ptr, c, white); | ||
| 96 | if (++x >= video_num_cols) { | ||
| 97 | x = 0; | ||
| 98 | if ( ++y >= video_num_rows ) { | ||
| 99 | y--; | ||
| 100 | } | ||
| 101 | } | ||
| 102 | } | ||
| 103 | |||
| 104 | video_x = x; | ||
| 105 | video_y = y; | ||
| 106 | } | ||
| 107 | |||
| 108 | static inline void flush(void) | ||
| 109 | { | ||
| 110 | } | ||
| 111 | |||
| 112 | static void error(char *x); | ||
| 113 | |||
| 114 | /* | ||
| 115 | * Setup for decompression | ||
| 116 | */ | ||
| 117 | static void arch_decomp_setup(void) | ||
| 118 | { | ||
| 119 | int i; | ||
| 120 | struct tag *t = (struct tag *)params; | ||
| 121 | unsigned int nr_pages = 0, page_size = PAGE_SIZE; | ||
| 122 | |||
| 123 | if (t->hdr.tag == ATAG_CORE) | ||
| 124 | { | ||
| 125 | for (; t->hdr.size; t = tag_next(t)) | ||
| 126 | { | ||
| 127 | if (t->hdr.tag == ATAG_VIDEOTEXT) | ||
| 128 | { | ||
| 129 | video_num_rows = t->u.videotext.video_lines; | ||
| 130 | video_num_cols = t->u.videotext.video_cols; | ||
| 131 | bytes_per_char_h = t->u.videotext.video_points; | ||
| 132 | bytes_per_char_v = t->u.videotext.video_points; | ||
| 133 | video_x = t->u.videotext.x; | ||
| 134 | video_y = t->u.videotext.y; | ||
| 135 | } | ||
| 136 | |||
| 137 | if (t->hdr.tag == ATAG_MEM) | ||
| 138 | { | ||
| 139 | page_size = PAGE_SIZE; | ||
| 140 | nr_pages += (t->u.mem.size / PAGE_SIZE); | ||
| 141 | } | ||
| 142 | } | ||
| 143 | } | ||
| 144 | else | ||
| 145 | { | ||
| 146 | nr_pages = params->nr_pages; | ||
| 147 | page_size = params->page_size; | ||
| 148 | video_num_rows = params->video_num_rows; | ||
| 149 | video_num_cols = params->video_num_cols; | ||
| 150 | video_x = params->video_x; | ||
| 151 | video_y = params->video_y; | ||
| 152 | bytes_per_char_h = params->bytes_per_char_h; | ||
| 153 | bytes_per_char_v = params->bytes_per_char_v; | ||
| 154 | } | ||
| 155 | |||
| 156 | video_size_row = video_num_cols * bytes_per_char_h; | ||
| 157 | |||
| 158 | if (bytes_per_char_h == 4) | ||
| 159 | for (i = 0; i < 256; i++) | ||
| 160 | con_charconvtable[i] = | ||
| 161 | (i & 128 ? 1 << 0 : 0) | | ||
| 162 | (i & 64 ? 1 << 4 : 0) | | ||
| 163 | (i & 32 ? 1 << 8 : 0) | | ||
| 164 | (i & 16 ? 1 << 12 : 0) | | ||
| 165 | (i & 8 ? 1 << 16 : 0) | | ||
| 166 | (i & 4 ? 1 << 20 : 0) | | ||
| 167 | (i & 2 ? 1 << 24 : 0) | | ||
| 168 | (i & 1 ? 1 << 28 : 0); | ||
| 169 | else | ||
| 170 | for (i = 0; i < 16; i++) | ||
| 171 | con_charconvtable[i] = | ||
| 172 | (i & 8 ? 1 << 0 : 0) | | ||
| 173 | (i & 4 ? 1 << 8 : 0) | | ||
| 174 | (i & 2 ? 1 << 16 : 0) | | ||
| 175 | (i & 1 ? 1 << 24 : 0); | ||
| 176 | |||
| 177 | |||
| 178 | palette_setpixel(0); | ||
| 179 | if (bytes_per_char_h == 1) { | ||
| 180 | palette_write (0); | ||
| 181 | palette_write (0x00ffffff); | ||
| 182 | for (i = 2; i < 256; i++) | ||
| 183 | palette_write (0); | ||
| 184 | white = 1; | ||
| 185 | } else { | ||
| 186 | for (i = 0; i < 256; i++) | ||
| 187 | palette_write (i < 16 ? palette_4[i] : 0); | ||
| 188 | white = 7; | ||
| 189 | } | ||
| 190 | |||
| 191 | if (nr_pages * page_size < 4096*1024) error("<4M of mem\n"); | ||
| 192 | } | ||
| 193 | #endif | ||
| 194 | |||
| 195 | /* | ||
| 196 | * nothing to do | ||
| 197 | */ | ||
| 198 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-rpc/vmalloc.h b/include/asm-arm/arch-rpc/vmalloc.h deleted file mode 100644 index 077046bb2f36..000000000000 --- a/include/asm-arm/arch-rpc/vmalloc.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-rpc/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #define VMALLOC_END (PAGE_OFFSET + 0x1c000000) | ||
diff --git a/include/asm-arm/arch-s3c2400/map.h b/include/asm-arm/arch-s3c2400/map.h deleted file mode 100644 index 1184d907b31e..000000000000 --- a/include/asm-arm/arch-s3c2400/map.h +++ /dev/null | |||
| @@ -1,66 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2400/map.h | ||
| 2 | * | ||
| 3 | * Copyright 2003,2007 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * Copyright 2003, Lucas Correia Villa Real | ||
| 8 | * | ||
| 9 | * S3C2400 - Memory map definitions | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #define S3C2400_PA_MEMCTRL (0x14000000) | ||
| 17 | #define S3C2400_PA_USBHOST (0x14200000) | ||
| 18 | #define S3C2400_PA_IRQ (0x14400000) | ||
| 19 | #define S3C2400_PA_DMA (0x14600000) | ||
| 20 | #define S3C2400_PA_CLKPWR (0x14800000) | ||
| 21 | #define S3C2400_PA_LCD (0x14A00000) | ||
| 22 | #define S3C2400_PA_UART (0x15000000) | ||
| 23 | #define S3C2400_PA_TIMER (0x15100000) | ||
| 24 | #define S3C2400_PA_USBDEV (0x15200140) | ||
| 25 | #define S3C2400_PA_WATCHDOG (0x15300000) | ||
| 26 | #define S3C2400_PA_IIC (0x15400000) | ||
| 27 | #define S3C2400_PA_IIS (0x15508000) | ||
| 28 | #define S3C2400_PA_GPIO (0x15600000) | ||
| 29 | #define S3C2400_PA_RTC (0x15700040) | ||
| 30 | #define S3C2400_PA_ADC (0x15800000) | ||
| 31 | #define S3C2400_PA_SPI (0x15900000) | ||
| 32 | |||
| 33 | #define S3C2400_PA_MMC (0x15A00000) | ||
| 34 | #define S3C2400_SZ_MMC SZ_1M | ||
| 35 | |||
| 36 | /* physical addresses of all the chip-select areas */ | ||
| 37 | |||
| 38 | #define S3C2400_CS0 (0x00000000) | ||
| 39 | #define S3C2400_CS1 (0x02000000) | ||
| 40 | #define S3C2400_CS2 (0x04000000) | ||
| 41 | #define S3C2400_CS3 (0x06000000) | ||
| 42 | #define S3C2400_CS4 (0x08000000) | ||
| 43 | #define S3C2400_CS5 (0x0A000000) | ||
| 44 | #define S3C2400_CS6 (0x0C000000) | ||
| 45 | #define S3C2400_CS7 (0x0E000000) | ||
| 46 | |||
| 47 | #define S3C2400_SDRAM_PA (S3C2400_CS6) | ||
| 48 | |||
| 49 | /* Use a single interface for common resources between S3C24XX cpus */ | ||
| 50 | |||
| 51 | #define S3C24XX_PA_IRQ S3C2400_PA_IRQ | ||
| 52 | #define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL | ||
| 53 | #define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST | ||
| 54 | #define S3C24XX_PA_DMA S3C2400_PA_DMA | ||
| 55 | #define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR | ||
| 56 | #define S3C24XX_PA_LCD S3C2400_PA_LCD | ||
| 57 | #define S3C24XX_PA_UART S3C2400_PA_UART | ||
| 58 | #define S3C24XX_PA_TIMER S3C2400_PA_TIMER | ||
| 59 | #define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV | ||
| 60 | #define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG | ||
| 61 | #define S3C24XX_PA_IIC S3C2400_PA_IIC | ||
| 62 | #define S3C24XX_PA_IIS S3C2400_PA_IIS | ||
| 63 | #define S3C24XX_PA_GPIO S3C2400_PA_GPIO | ||
| 64 | #define S3C24XX_PA_RTC S3C2400_PA_RTC | ||
| 65 | #define S3C24XX_PA_ADC S3C2400_PA_ADC | ||
| 66 | #define S3C24XX_PA_SPI S3C2400_PA_SPI | ||
diff --git a/include/asm-arm/arch-s3c2400/memory.h b/include/asm-arm/arch-s3c2400/memory.h deleted file mode 100644 index fb0381dde704..000000000000 --- a/include/asm-arm/arch-s3c2400/memory.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2400/memory.h | ||
| 2 | * from linux/include/asm-arm/arch-rpc/memory.h | ||
| 3 | * | ||
| 4 | * Copyright 2007 Simtec Electronics | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * | ||
| 8 | * Copyright (C) 1996,1997,1998 Russell King. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 16 | #define __ASM_ARCH_MEMORY_H | ||
| 17 | |||
| 18 | #define PHYS_OFFSET UL(0x0C000000) | ||
| 19 | |||
| 20 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 21 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 22 | |||
| 23 | #endif | ||
diff --git a/include/asm-arm/arch-s3c2410/anubis-cpld.h b/include/asm-arm/arch-s3c2410/anubis-cpld.h deleted file mode 100644 index 168b93fee529..000000000000 --- a/include/asm-arm/arch-s3c2410/anubis-cpld.h +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/anubis-cpld.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2005 Simtec Electronics | ||
| 4 | * http://www.simtec.co.uk/products/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * ANUBIS - CPLD control constants | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_ANUBISCPLD_H | ||
| 15 | #define __ASM_ARCH_ANUBISCPLD_H | ||
| 16 | |||
| 17 | /* CTRL2 - NAND WP control, IDE Reset assert/check */ | ||
| 18 | |||
| 19 | #define ANUBIS_CTRL1_NANDSEL (0x3) | ||
| 20 | |||
| 21 | /* IDREG - revision */ | ||
| 22 | |||
| 23 | #define ANUBIS_IDREG_REVMASK (0x7) | ||
| 24 | |||
| 25 | #endif /* __ASM_ARCH_ANUBISCPLD_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/anubis-irq.h b/include/asm-arm/arch-s3c2410/anubis-irq.h deleted file mode 100644 index cd77a70d45c0..000000000000 --- a/include/asm-arm/arch-s3c2410/anubis-irq.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/anubis-irq.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2005 Simtec Electronics | ||
| 4 | * http://www.simtec.co.uk/products/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * ANUBIS - IRQ Number definitions | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_ANUBISIRQ_H | ||
| 15 | #define __ASM_ARCH_ANUBISIRQ_H | ||
| 16 | |||
| 17 | #define IRQ_IDE0 IRQ_EINT2 | ||
| 18 | #define IRQ_IDE1 IRQ_EINT3 | ||
| 19 | #define IRQ_ASIX IRQ_EINT1 | ||
| 20 | |||
| 21 | #endif /* __ASM_ARCH_ANUBISIRQ_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h deleted file mode 100644 index 830d114261da..000000000000 --- a/include/asm-arm/arch-s3c2410/anubis-map.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/anubis-map.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2005 Simtec Electronics | ||
| 4 | * http://www.simtec.co.uk/products/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * ANUBIS - Memory map definitions | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /* needs arch/map.h including with this */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_ANUBISMAP_H | ||
| 17 | #define __ASM_ARCH_ANUBISMAP_H | ||
| 18 | |||
| 19 | /* start peripherals off after the S3C2410 */ | ||
| 20 | |||
| 21 | #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) | ||
| 22 | |||
| 23 | #define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) | ||
| 24 | |||
| 25 | /* we put the CPLD registers next, to get them out of the way */ | ||
| 26 | |||
| 27 | #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */ | ||
| 28 | #define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) | ||
| 29 | |||
| 30 | #define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */ | ||
| 31 | #define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3<<23)) | ||
| 32 | |||
| 33 | #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) | ||
| 34 | #define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) | ||
| 35 | #define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000) | ||
| 36 | #define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000) | ||
| 37 | |||
| 38 | #endif /* __ASM_ARCH_ANUBISMAP_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/audio.h b/include/asm-arm/arch-s3c2410/audio.h deleted file mode 100644 index 0a6977fb5770..000000000000 --- a/include/asm-arm/arch-s3c2410/audio.h +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/audio.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * S3C24XX - Audio platfrom_device info | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_AUDIO_H | ||
| 15 | #define __ASM_ARCH_AUDIO_H __FILE__ | ||
| 16 | |||
| 17 | /* struct s3c24xx_iis_ops | ||
| 18 | * | ||
| 19 | * called from the s3c24xx audio core to deal with the architecture | ||
| 20 | * or the codec's setup and control. | ||
| 21 | * | ||
| 22 | * the pointer to itself is passed through in case the caller wants to | ||
| 23 | * embed this in an larger structure for easy reference to it's context. | ||
| 24 | */ | ||
| 25 | |||
| 26 | struct s3c24xx_iis_ops { | ||
| 27 | struct module *owner; | ||
| 28 | |||
| 29 | int (*startup)(struct s3c24xx_iis_ops *me); | ||
| 30 | void (*shutdown)(struct s3c24xx_iis_ops *me); | ||
| 31 | int (*suspend)(struct s3c24xx_iis_ops *me); | ||
| 32 | int (*resume)(struct s3c24xx_iis_ops *me); | ||
| 33 | |||
| 34 | int (*open)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm); | ||
| 35 | int (*close)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm); | ||
| 36 | int (*prepare)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm, struct snd_pcm_runtime *rt); | ||
| 37 | }; | ||
| 38 | |||
| 39 | struct s3c24xx_platdata_iis { | ||
| 40 | const char *codec_clk; | ||
| 41 | struct s3c24xx_iis_ops *ops; | ||
| 42 | int (*match_dev)(struct device *dev); | ||
| 43 | }; | ||
| 44 | |||
| 45 | #endif /* __ASM_ARCH_AUDIO_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/bast-cpld.h b/include/asm-arm/arch-s3c2410/bast-cpld.h deleted file mode 100644 index 034d2c5a47c4..000000000000 --- a/include/asm-arm/arch-s3c2410/bast-cpld.h +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/bast-cpld.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * BAST - CPLD control constants | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_BASTCPLD_H | ||
| 14 | #define __ASM_ARCH_BASTCPLD_H | ||
| 15 | |||
| 16 | /* CTRL1 - Audio LR routing */ | ||
| 17 | |||
| 18 | #define BAST_CPLD_CTRL1_LRCOFF (0x00) | ||
| 19 | #define BAST_CPLD_CTRL1_LRCADC (0x01) | ||
| 20 | #define BAST_CPLD_CTRL1_LRCDAC (0x02) | ||
| 21 | #define BAST_CPLD_CTRL1_LRCARM (0x03) | ||
| 22 | #define BAST_CPLD_CTRL1_LRMASK (0x03) | ||
| 23 | |||
| 24 | /* CTRL2 - NAND WP control, IDE Reset assert/check */ | ||
| 25 | |||
| 26 | #define BAST_CPLD_CTRL2_WNAND (0x04) | ||
| 27 | #define BAST_CPLD_CTLR2_IDERST (0x08) | ||
| 28 | |||
| 29 | /* CTRL3 - rom write control, CPLD identity */ | ||
| 30 | |||
| 31 | #define BAST_CPLD_CTRL3_IDMASK (0x0e) | ||
| 32 | #define BAST_CPLD_CTRL3_ROMWEN (0x01) | ||
| 33 | |||
| 34 | /* CTRL4 - 8bit LCD interface control/status */ | ||
| 35 | |||
| 36 | #define BAST_CPLD_CTRL4_LLAT (0x01) | ||
| 37 | #define BAST_CPLD_CTRL4_LCDRW (0x02) | ||
| 38 | #define BAST_CPLD_CTRL4_LCDCMD (0x04) | ||
| 39 | #define BAST_CPLD_CTRL4_LCDE2 (0x01) | ||
| 40 | |||
| 41 | /* CTRL5 - DMA routing */ | ||
| 42 | |||
| 43 | #define BAST_CPLD_DMA0_PRIIDE (0<<0) | ||
| 44 | #define BAST_CPLD_DMA0_SECIDE (1<<0) | ||
| 45 | #define BAST_CPLD_DMA0_ISA15 (2<<0) | ||
| 46 | #define BAST_CPLD_DMA0_ISA36 (3<<0) | ||
| 47 | |||
| 48 | #define BAST_CPLD_DMA1_PRIIDE (0<<2) | ||
| 49 | #define BAST_CPLD_DMA1_SECIDE (1<<2) | ||
| 50 | #define BAST_CPLD_DMA1_ISA15 (2<<2) | ||
| 51 | #define BAST_CPLD_DMA1_ISA36 (3<<2) | ||
| 52 | |||
| 53 | #endif /* __ASM_ARCH_BASTCPLD_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/bast-irq.h b/include/asm-arm/arch-s3c2410/bast-irq.h deleted file mode 100644 index 726c0466f85a..000000000000 --- a/include/asm-arm/arch-s3c2410/bast-irq.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/bast-irq.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * Machine BAST - IRQ Number definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_BASTIRQ_H | ||
| 14 | #define __ASM_ARCH_BASTIRQ_H | ||
| 15 | |||
| 16 | /* irq numbers to onboard peripherals */ | ||
| 17 | |||
| 18 | #define IRQ_USBOC IRQ_EINT18 | ||
| 19 | #define IRQ_IDE0 IRQ_EINT16 | ||
| 20 | #define IRQ_IDE1 IRQ_EINT17 | ||
| 21 | #define IRQ_PCSERIAL1 IRQ_EINT15 | ||
| 22 | #define IRQ_PCSERIAL2 IRQ_EINT14 | ||
| 23 | #define IRQ_PCPARALLEL IRQ_EINT13 | ||
| 24 | #define IRQ_ASIX IRQ_EINT11 | ||
| 25 | #define IRQ_DM9000 IRQ_EINT10 | ||
| 26 | #define IRQ_ISA IRQ_EINT9 | ||
| 27 | #define IRQ_SMALERT IRQ_EINT8 | ||
| 28 | |||
| 29 | #endif /* __ASM_ARCH_BASTIRQ_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/bast-map.h b/include/asm-arm/arch-s3c2410/bast-map.h deleted file mode 100644 index 86ac1c108db8..000000000000 --- a/include/asm-arm/arch-s3c2410/bast-map.h +++ /dev/null | |||
| @@ -1,146 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/bast-map.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * Machine BAST - Memory map definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* needs arch/map.h including with this */ | ||
| 14 | |||
| 15 | /* ok, we've used up to 0x13000000, now we need to find space for the | ||
| 16 | * peripherals that live in the nGCS[x] areas, which are quite numerous | ||
| 17 | * in their space. We also have the board's CPLD to find register space | ||
| 18 | * for. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_BASTMAP_H | ||
| 22 | #define __ASM_ARCH_BASTMAP_H | ||
| 23 | |||
| 24 | #define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) | ||
| 25 | |||
| 26 | /* we put the CPLD registers next, to get them out of the way */ | ||
| 27 | |||
| 28 | #define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */ | ||
| 29 | #define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000) | ||
| 30 | |||
| 31 | #define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */ | ||
| 32 | #define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000) | ||
| 33 | |||
| 34 | #define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */ | ||
| 35 | #define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000) | ||
| 36 | |||
| 37 | #define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */ | ||
| 38 | #define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000) | ||
| 39 | |||
| 40 | /* next, we have the PC104 ISA interrupt registers */ | ||
| 41 | |||
| 42 | #define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ | ||
| 43 | #define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000) | ||
| 44 | |||
| 45 | #define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ | ||
| 46 | #define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000) | ||
| 47 | |||
| 48 | #define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ | ||
| 49 | #define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000) | ||
| 50 | |||
| 51 | #define BAST_PA_LCD_RCMD1 (0x8800000) | ||
| 52 | #define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000) | ||
| 53 | |||
| 54 | #define BAST_PA_LCD_WCMD1 (0x8000000) | ||
| 55 | #define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000) | ||
| 56 | |||
| 57 | #define BAST_PA_LCD_RDATA1 (0x9800000) | ||
| 58 | #define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000) | ||
| 59 | |||
| 60 | #define BAST_PA_LCD_WDATA1 (0x9000000) | ||
| 61 | #define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000) | ||
| 62 | |||
| 63 | #define BAST_PA_LCD_RCMD2 (0xA800000) | ||
| 64 | #define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000) | ||
| 65 | |||
| 66 | #define BAST_PA_LCD_WCMD2 (0xA000000) | ||
| 67 | #define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000) | ||
| 68 | |||
| 69 | #define BAST_PA_LCD_RDATA2 (0xB800000) | ||
| 70 | #define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000) | ||
| 71 | |||
| 72 | #define BAST_PA_LCD_WDATA2 (0xB000000) | ||
| 73 | #define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000) | ||
| 74 | |||
| 75 | |||
| 76 | /* 0xE0000000 contains the IO space that is split by speed and | ||
| 77 | * wether the access is for 8 or 16bit IO... this ensures that | ||
| 78 | * the correct access is made | ||
| 79 | * | ||
| 80 | * 0x10000000 of space, partitioned as so: | ||
| 81 | * | ||
| 82 | * 0x00000000 to 0x04000000 8bit, slow | ||
| 83 | * 0x04000000 to 0x08000000 16bit, slow | ||
| 84 | * 0x08000000 to 0x0C000000 16bit, net | ||
| 85 | * 0x0C000000 to 0x10000000 16bit, fast | ||
| 86 | * | ||
| 87 | * each of these spaces has the following in: | ||
| 88 | * | ||
| 89 | * 0x00000000 to 0x01000000 16MB ISA IO space | ||
| 90 | * 0x01000000 to 0x02000000 16MB ISA memory space | ||
| 91 | * 0x02000000 to 0x02100000 1MB IDE primary channel | ||
| 92 | * 0x02100000 to 0x02200000 1MB IDE primary channel aux | ||
| 93 | * 0x02200000 to 0x02400000 1MB IDE secondary channel | ||
| 94 | * 0x02300000 to 0x02400000 1MB IDE secondary channel aux | ||
| 95 | * 0x02400000 to 0x02500000 1MB ASIX ethernet controller | ||
| 96 | * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller | ||
| 97 | * 0x02600000 to 0x02700000 1MB PC SuperIO controller | ||
| 98 | * | ||
| 99 | * the phyiscal layout of the zones are: | ||
| 100 | * nGCS2 - 8bit, slow | ||
| 101 | * nGCS3 - 16bit, slow | ||
| 102 | * nGCS4 - 16bit, net | ||
| 103 | * nGCS5 - 16bit, fast | ||
| 104 | */ | ||
| 105 | |||
| 106 | #define BAST_VA_MULTISPACE (0xE0000000) | ||
| 107 | |||
| 108 | #define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000) | ||
| 109 | #define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000) | ||
| 110 | #define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000) | ||
| 111 | #define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000) | ||
| 112 | #define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000) | ||
| 113 | #define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000) | ||
| 114 | #define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000) | ||
| 115 | #define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000) | ||
| 116 | #define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000) | ||
| 117 | |||
| 118 | #define BAST_VA_MULTISPACE (0xE0000000) | ||
| 119 | |||
| 120 | #define BAST_VAM_CS2 (0x00000000) | ||
| 121 | #define BAST_VAM_CS3 (0x04000000) | ||
| 122 | #define BAST_VAM_CS4 (0x08000000) | ||
| 123 | #define BAST_VAM_CS5 (0x0C000000) | ||
| 124 | |||
| 125 | /* physical offset addresses for the peripherals */ | ||
| 126 | |||
| 127 | #define BAST_PA_ISAIO (0x00000000) | ||
| 128 | #define BAST_PA_ASIXNET (0x01000000) | ||
| 129 | #define BAST_PA_SUPERIO (0x01800000) | ||
| 130 | #define BAST_PA_IDEPRI (0x02000000) | ||
| 131 | #define BAST_PA_IDEPRIAUX (0x02800000) | ||
| 132 | #define BAST_PA_IDESEC (0x03000000) | ||
| 133 | #define BAST_PA_IDESECAUX (0x03800000) | ||
| 134 | #define BAST_PA_ISAMEM (0x04000000) | ||
| 135 | #define BAST_PA_DM9000 (0x05000000) | ||
| 136 | |||
| 137 | /* some configurations for the peripherals */ | ||
| 138 | |||
| 139 | #define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2) | ||
| 140 | /* */ | ||
| 141 | |||
| 142 | #define BAST_ASIXNET_CS BAST_VAM_CS5 | ||
| 143 | #define BAST_IDE_CS BAST_VAM_CS5 | ||
| 144 | #define BAST_DM9000_CS BAST_VAM_CS4 | ||
| 145 | |||
| 146 | #endif /* __ASM_ARCH_BASTMAP_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/bast-pmu.h b/include/asm-arm/arch-s3c2410/bast-pmu.h deleted file mode 100644 index 37a11fe54a78..000000000000 --- a/include/asm-arm/arch-s3c2410/bast-pmu.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/bast-pmu.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Vincent Sanders <vince@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * Machine BAST - Power Management chip | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_BASTPMU_H | ||
| 15 | #define __ASM_ARCH_BASTPMU_H "08_OCT_2004" | ||
| 16 | |||
| 17 | #define BASTPMU_REG_IDENT (0x00) | ||
| 18 | #define BASTPMU_REG_VERSION (0x01) | ||
| 19 | #define BASTPMU_REG_DDCCTRL (0x02) | ||
| 20 | #define BASTPMU_REG_POWER (0x03) | ||
| 21 | #define BASTPMU_REG_RESET (0x04) | ||
| 22 | #define BASTPMU_REG_GWO (0x05) | ||
| 23 | #define BASTPMU_REG_WOL (0x06) | ||
| 24 | #define BASTPMU_REG_WOR (0x07) | ||
| 25 | #define BASTPMU_REG_UID (0x09) | ||
| 26 | |||
| 27 | #define BASTPMU_EEPROM (0xC0) | ||
| 28 | |||
| 29 | #define BASTPMU_EEP_UID (BASTPMU_EEPROM + 0) | ||
| 30 | #define BASTPMU_EEP_WOL (BASTPMU_EEPROM + 8) | ||
| 31 | #define BASTPMU_EEP_WOR (BASTPMU_EEPROM + 9) | ||
| 32 | |||
| 33 | #define BASTPMU_IDENT_0 0x53 | ||
| 34 | #define BASTPMU_IDENT_1 0x42 | ||
| 35 | #define BASTPMU_IDENT_2 0x50 | ||
| 36 | #define BASTPMU_IDENT_3 0x4d | ||
| 37 | |||
| 38 | #define BASTPMU_RESET_GUARD (0x55) | ||
| 39 | |||
| 40 | #endif /* __ASM_ARCH_BASTPMU_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S deleted file mode 100644 index 89076c322726..000000000000 --- a/include/asm-arm/arch-s3c2410/debug-macro.S +++ /dev/null | |||
| @@ -1,102 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Copyright (C) 2005 Simtec Electronics | ||
| 7 | * | ||
| 8 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <asm/arch/map.h> | ||
| 16 | #include <asm/arch/regs-gpio.h> | ||
| 17 | #include <asm/plat-s3c/regs-serial.h> | ||
| 18 | |||
| 19 | #define S3C2410_UART1_OFF (0x4000) | ||
| 20 | #define SHIFT_2440TXF (14-9) | ||
| 21 | |||
| 22 | .macro addruart, rx | ||
| 23 | mrc p15, 0, \rx, c1, c0 | ||
| 24 | tst \rx, #1 | ||
| 25 | ldreq \rx, = S3C24XX_PA_UART | ||
| 26 | ldrne \rx, = S3C24XX_VA_UART | ||
| 27 | #if CONFIG_DEBUG_S3C_UART != 0 | ||
| 28 | add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) | ||
| 29 | #endif | ||
| 30 | .endm | ||
| 31 | |||
| 32 | .macro fifo_full_s3c24xx rd, rx | ||
| 33 | @ check for arm920 vs arm926. currently assume all arm926 | ||
| 34 | @ devices have an 64 byte FIFO identical to the s3c2440 | ||
| 35 | mrc p15, 0, \rd, c0, c0 | ||
| 36 | and \rd, \rd, #0xff0 | ||
| 37 | teq \rd, #0x260 | ||
| 38 | beq 1004f | ||
| 39 | mrc p15, 0, \rd, c1, c0 | ||
| 40 | tst \rd, #1 | ||
| 41 | addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) | ||
| 42 | addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) | ||
| 43 | bic \rd, \rd, #0xff000 | ||
| 44 | ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] | ||
| 45 | and \rd, \rd, #0x00ff0000 | ||
| 46 | teq \rd, #0x00440000 @ is it 2440? | ||
| 47 | 1004: | ||
| 48 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | ||
| 49 | moveq \rd, \rd, lsr #SHIFT_2440TXF | ||
| 50 | tst \rd, #S3C2410_UFSTAT_TXFULL | ||
| 51 | .endm | ||
| 52 | |||
| 53 | .macro fifo_full_s3c2410 rd, rx | ||
| 54 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | ||
| 55 | tst \rd, #S3C2410_UFSTAT_TXFULL | ||
| 56 | .endm | ||
| 57 | |||
| 58 | /* fifo level reading */ | ||
| 59 | |||
| 60 | .macro fifo_level_s3c24xx rd, rx | ||
| 61 | @ check for arm920 vs arm926. currently assume all arm926 | ||
| 62 | @ devices have an 64 byte FIFO identical to the s3c2440 | ||
| 63 | mrc p15, 0, \rd, c0, c0 | ||
| 64 | and \rd, \rd, #0xff0 | ||
| 65 | teq \rd, #0x260 | ||
| 66 | beq 10000f | ||
| 67 | mrc p15, 0, \rd, c1, c0 | ||
| 68 | tst \rd, #1 | ||
| 69 | addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART) | ||
| 70 | addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART) | ||
| 71 | bic \rd, \rd, #0xff000 | ||
| 72 | ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ] | ||
| 73 | and \rd, \rd, #0x00ff0000 | ||
| 74 | teq \rd, #0x00440000 @ is it 2440? | ||
| 75 | |||
| 76 | 10000: | ||
| 77 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | ||
| 78 | andne \rd, \rd, #S3C2410_UFSTAT_TXMASK | ||
| 79 | andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK | ||
| 80 | .endm | ||
| 81 | |||
| 82 | .macro fifo_level_s3c2410 rd, rx | ||
| 83 | ldr \rd, [ \rx, # S3C2410_UFSTAT ] | ||
| 84 | and \rd, \rd, #S3C2410_UFSTAT_TXMASK | ||
| 85 | .endm | ||
| 86 | |||
| 87 | /* Select the correct implementation depending on the configuration. The | ||
| 88 | * S3C2440 will get selected by default, as these are the most widely | ||
| 89 | * used variants of these | ||
| 90 | */ | ||
| 91 | |||
| 92 | #if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY) | ||
| 93 | #define fifo_full fifo_full_s3c2410 | ||
| 94 | #define fifo_level fifo_level_s3c2410 | ||
| 95 | #elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY) | ||
| 96 | #define fifo_full fifo_full_s3c24xx | ||
| 97 | #define fifo_level fifo_level_s3c24xx | ||
| 98 | #endif | ||
| 99 | |||
| 100 | /* include the reset of the code which will do the work */ | ||
| 101 | |||
| 102 | #include <asm/plat-s3c/debug-macro.S> | ||
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h deleted file mode 100644 index 86eaa0c2dc1e..000000000000 --- a/include/asm-arm/arch-s3c2410/dma.h +++ /dev/null | |||
| @@ -1,453 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/dma.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2003,2004,2006 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * Samsung S3C241XX DMA support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_DMA_H | ||
| 14 | #define __ASM_ARCH_DMA_H __FILE__ | ||
| 15 | |||
| 16 | #include <linux/sysdev.h> | ||
| 17 | #include <asm/arch/hardware.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * This is the maximum DMA address(physical address) that can be DMAd to. | ||
| 21 | * | ||
| 22 | */ | ||
| 23 | #define MAX_DMA_ADDRESS 0x40000000 | ||
| 24 | #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ | ||
| 25 | |||
| 26 | /* We use `virtual` dma channels to hide the fact we have only a limited | ||
| 27 | * number of DMA channels, and not of all of them (dependant on the device) | ||
| 28 | * can be attached to any DMA source. We therefore let the DMA core handle | ||
| 29 | * the allocation of hardware channels to clients. | ||
| 30 | */ | ||
| 31 | |||
| 32 | enum dma_ch { | ||
| 33 | DMACH_XD0, | ||
| 34 | DMACH_XD1, | ||
| 35 | DMACH_SDI, | ||
| 36 | DMACH_SPI0, | ||
| 37 | DMACH_SPI1, | ||
| 38 | DMACH_UART0, | ||
| 39 | DMACH_UART1, | ||
| 40 | DMACH_UART2, | ||
| 41 | DMACH_TIMER, | ||
| 42 | DMACH_I2S_IN, | ||
| 43 | DMACH_I2S_OUT, | ||
| 44 | DMACH_PCM_IN, | ||
| 45 | DMACH_PCM_OUT, | ||
| 46 | DMACH_MIC_IN, | ||
| 47 | DMACH_USB_EP1, | ||
| 48 | DMACH_USB_EP2, | ||
| 49 | DMACH_USB_EP3, | ||
| 50 | DMACH_USB_EP4, | ||
| 51 | DMACH_UART0_SRC2, /* s3c2412 second uart sources */ | ||
| 52 | DMACH_UART1_SRC2, | ||
| 53 | DMACH_UART2_SRC2, | ||
| 54 | DMACH_UART3, /* s3c2443 has extra uart */ | ||
| 55 | DMACH_UART3_SRC2, | ||
| 56 | DMACH_MAX, /* the end entry */ | ||
| 57 | }; | ||
| 58 | |||
| 59 | #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ | ||
| 60 | |||
| 61 | /* we have 4 dma channels */ | ||
| 62 | #ifndef CONFIG_CPU_S3C2443 | ||
| 63 | #define S3C2410_DMA_CHANNELS (4) | ||
| 64 | #else | ||
| 65 | #define S3C2410_DMA_CHANNELS (6) | ||
| 66 | #endif | ||
| 67 | |||
| 68 | /* types */ | ||
| 69 | |||
| 70 | enum s3c2410_dma_state { | ||
| 71 | S3C2410_DMA_IDLE, | ||
| 72 | S3C2410_DMA_RUNNING, | ||
| 73 | S3C2410_DMA_PAUSED | ||
| 74 | }; | ||
| 75 | |||
| 76 | |||
| 77 | /* enum s3c2410_dma_loadst | ||
| 78 | * | ||
| 79 | * This represents the state of the DMA engine, wrt to the loaded / running | ||
| 80 | * transfers. Since we don't have any way of knowing exactly the state of | ||
| 81 | * the DMA transfers, we need to know the state to make decisions on wether | ||
| 82 | * we can | ||
| 83 | * | ||
| 84 | * S3C2410_DMA_NONE | ||
| 85 | * | ||
| 86 | * There are no buffers loaded (the channel should be inactive) | ||
| 87 | * | ||
| 88 | * S3C2410_DMA_1LOADED | ||
| 89 | * | ||
| 90 | * There is one buffer loaded, however it has not been confirmed to be | ||
| 91 | * loaded by the DMA engine. This may be because the channel is not | ||
| 92 | * yet running, or the DMA driver decided that it was too costly to | ||
| 93 | * sit and wait for it to happen. | ||
| 94 | * | ||
| 95 | * S3C2410_DMA_1RUNNING | ||
| 96 | * | ||
| 97 | * The buffer has been confirmed running, and not finisged | ||
| 98 | * | ||
| 99 | * S3C2410_DMA_1LOADED_1RUNNING | ||
| 100 | * | ||
| 101 | * There is a buffer waiting to be loaded by the DMA engine, and one | ||
| 102 | * currently running. | ||
| 103 | */ | ||
| 104 | |||
| 105 | enum s3c2410_dma_loadst { | ||
| 106 | S3C2410_DMALOAD_NONE, | ||
| 107 | S3C2410_DMALOAD_1LOADED, | ||
| 108 | S3C2410_DMALOAD_1RUNNING, | ||
| 109 | S3C2410_DMALOAD_1LOADED_1RUNNING, | ||
| 110 | }; | ||
| 111 | |||
| 112 | enum s3c2410_dma_buffresult { | ||
| 113 | S3C2410_RES_OK, | ||
| 114 | S3C2410_RES_ERR, | ||
| 115 | S3C2410_RES_ABORT | ||
| 116 | }; | ||
| 117 | |||
| 118 | enum s3c2410_dmasrc { | ||
| 119 | S3C2410_DMASRC_HW, /* source is memory */ | ||
| 120 | S3C2410_DMASRC_MEM /* source is hardware */ | ||
| 121 | }; | ||
| 122 | |||
| 123 | /* enum s3c2410_chan_op | ||
| 124 | * | ||
| 125 | * operation codes passed to the DMA code by the user, and also used | ||
| 126 | * to inform the current channel owner of any changes to the system state | ||
| 127 | */ | ||
| 128 | |||
| 129 | enum s3c2410_chan_op { | ||
| 130 | S3C2410_DMAOP_START, | ||
| 131 | S3C2410_DMAOP_STOP, | ||
| 132 | S3C2410_DMAOP_PAUSE, | ||
| 133 | S3C2410_DMAOP_RESUME, | ||
| 134 | S3C2410_DMAOP_FLUSH, | ||
| 135 | S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ | ||
| 136 | S3C2410_DMAOP_STARTED, /* indicate channel started */ | ||
| 137 | }; | ||
| 138 | |||
| 139 | /* flags */ | ||
| 140 | |||
| 141 | #define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about | ||
| 142 | * waiting for reloads */ | ||
| 143 | #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ | ||
| 144 | |||
| 145 | /* dma buffer */ | ||
| 146 | |||
| 147 | struct s3c2410_dma_client { | ||
| 148 | char *name; | ||
| 149 | }; | ||
| 150 | |||
| 151 | /* s3c2410_dma_buf_s | ||
| 152 | * | ||
| 153 | * internally used buffer structure to describe a queued or running | ||
| 154 | * buffer. | ||
| 155 | */ | ||
| 156 | |||
| 157 | struct s3c2410_dma_buf; | ||
| 158 | struct s3c2410_dma_buf { | ||
| 159 | struct s3c2410_dma_buf *next; | ||
| 160 | int magic; /* magic */ | ||
| 161 | int size; /* buffer size in bytes */ | ||
| 162 | dma_addr_t data; /* start of DMA data */ | ||
| 163 | dma_addr_t ptr; /* where the DMA got to [1] */ | ||
| 164 | void *id; /* client's id */ | ||
| 165 | }; | ||
| 166 | |||
| 167 | /* [1] is this updated for both recv/send modes? */ | ||
| 168 | |||
| 169 | struct s3c2410_dma_chan; | ||
| 170 | |||
| 171 | /* s3c2410_dma_cbfn_t | ||
| 172 | * | ||
| 173 | * buffer callback routine type | ||
| 174 | */ | ||
| 175 | |||
| 176 | typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *, | ||
| 177 | void *buf, int size, | ||
| 178 | enum s3c2410_dma_buffresult result); | ||
| 179 | |||
| 180 | typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *, | ||
| 181 | enum s3c2410_chan_op ); | ||
| 182 | |||
| 183 | struct s3c2410_dma_stats { | ||
| 184 | unsigned long loads; | ||
| 185 | unsigned long timeout_longest; | ||
| 186 | unsigned long timeout_shortest; | ||
| 187 | unsigned long timeout_avg; | ||
| 188 | unsigned long timeout_failed; | ||
| 189 | }; | ||
| 190 | |||
| 191 | struct s3c2410_dma_map; | ||
| 192 | |||
| 193 | /* struct s3c2410_dma_chan | ||
| 194 | * | ||
| 195 | * full state information for each DMA channel | ||
| 196 | */ | ||
| 197 | |||
| 198 | struct s3c2410_dma_chan { | ||
| 199 | /* channel state flags and information */ | ||
| 200 | unsigned char number; /* number of this dma channel */ | ||
| 201 | unsigned char in_use; /* channel allocated */ | ||
| 202 | unsigned char irq_claimed; /* irq claimed for channel */ | ||
| 203 | unsigned char irq_enabled; /* irq enabled for channel */ | ||
| 204 | unsigned char xfer_unit; /* size of an transfer */ | ||
| 205 | |||
| 206 | /* channel state */ | ||
| 207 | |||
| 208 | enum s3c2410_dma_state state; | ||
| 209 | enum s3c2410_dma_loadst load_state; | ||
| 210 | struct s3c2410_dma_client *client; | ||
| 211 | |||
| 212 | /* channel configuration */ | ||
| 213 | enum s3c2410_dmasrc source; | ||
| 214 | unsigned long dev_addr; | ||
| 215 | unsigned long load_timeout; | ||
| 216 | unsigned int flags; /* channel flags */ | ||
| 217 | unsigned int hw_cfg; /* last hw config */ | ||
| 218 | |||
| 219 | struct s3c24xx_dma_map *map; /* channel hw maps */ | ||
| 220 | |||
| 221 | /* channel's hardware position and configuration */ | ||
| 222 | void __iomem *regs; /* channels registers */ | ||
| 223 | void __iomem *addr_reg; /* data address register */ | ||
| 224 | unsigned int irq; /* channel irq */ | ||
| 225 | unsigned long dcon; /* default value of DCON */ | ||
| 226 | |||
| 227 | /* driver handles */ | ||
| 228 | s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ | ||
| 229 | s3c2410_dma_opfn_t op_fn; /* channel op callback */ | ||
| 230 | |||
| 231 | /* stats gathering */ | ||
| 232 | struct s3c2410_dma_stats *stats; | ||
| 233 | struct s3c2410_dma_stats stats_store; | ||
| 234 | |||
| 235 | /* buffer list and information */ | ||
| 236 | struct s3c2410_dma_buf *curr; /* current dma buffer */ | ||
| 237 | struct s3c2410_dma_buf *next; /* next buffer to load */ | ||
| 238 | struct s3c2410_dma_buf *end; /* end of queue */ | ||
| 239 | |||
| 240 | /* system device */ | ||
| 241 | struct sys_device dev; | ||
| 242 | }; | ||
| 243 | |||
| 244 | /* the currently allocated channel information */ | ||
| 245 | extern struct s3c2410_dma_chan s3c2410_chans[]; | ||
| 246 | |||
| 247 | /* note, we don't really use dma_device_t at the moment */ | ||
| 248 | typedef unsigned long dma_device_t; | ||
| 249 | |||
| 250 | /* functions --------------------------------------------------------------- */ | ||
| 251 | |||
| 252 | /* s3c2410_dma_request | ||
| 253 | * | ||
| 254 | * request a dma channel exclusivley | ||
| 255 | */ | ||
| 256 | |||
| 257 | extern int s3c2410_dma_request(dmach_t channel, | ||
| 258 | struct s3c2410_dma_client *, void *dev); | ||
| 259 | |||
| 260 | |||
| 261 | /* s3c2410_dma_ctrl | ||
| 262 | * | ||
| 263 | * change the state of the dma channel | ||
| 264 | */ | ||
| 265 | |||
| 266 | extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op); | ||
| 267 | |||
| 268 | /* s3c2410_dma_setflags | ||
| 269 | * | ||
| 270 | * set the channel's flags to a given state | ||
| 271 | */ | ||
| 272 | |||
| 273 | extern int s3c2410_dma_setflags(dmach_t channel, | ||
| 274 | unsigned int flags); | ||
| 275 | |||
| 276 | /* s3c2410_dma_free | ||
| 277 | * | ||
| 278 | * free the dma channel (will also abort any outstanding operations) | ||
| 279 | */ | ||
| 280 | |||
| 281 | extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *); | ||
| 282 | |||
| 283 | /* s3c2410_dma_enqueue | ||
| 284 | * | ||
| 285 | * place the given buffer onto the queue of operations for the channel. | ||
| 286 | * The buffer must be allocated from dma coherent memory, or the Dcache/WB | ||
| 287 | * drained before the buffer is given to the DMA system. | ||
| 288 | */ | ||
| 289 | |||
| 290 | extern int s3c2410_dma_enqueue(dmach_t channel, void *id, | ||
| 291 | dma_addr_t data, int size); | ||
| 292 | |||
| 293 | /* s3c2410_dma_config | ||
| 294 | * | ||
| 295 | * configure the dma channel | ||
| 296 | */ | ||
| 297 | |||
| 298 | extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon); | ||
| 299 | |||
| 300 | /* s3c2410_dma_devconfig | ||
| 301 | * | ||
| 302 | * configure the device we're talking to | ||
| 303 | */ | ||
| 304 | |||
| 305 | extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, | ||
| 306 | int hwcfg, unsigned long devaddr); | ||
| 307 | |||
| 308 | /* s3c2410_dma_getposition | ||
| 309 | * | ||
| 310 | * get the position that the dma transfer is currently at | ||
| 311 | */ | ||
| 312 | |||
| 313 | extern int s3c2410_dma_getposition(dmach_t channel, | ||
| 314 | dma_addr_t *src, dma_addr_t *dest); | ||
| 315 | |||
| 316 | extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn); | ||
| 317 | extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); | ||
| 318 | |||
| 319 | /* DMA Register definitions */ | ||
| 320 | |||
| 321 | #define S3C2410_DMA_DISRC (0x00) | ||
| 322 | #define S3C2410_DMA_DISRCC (0x04) | ||
| 323 | #define S3C2410_DMA_DIDST (0x08) | ||
| 324 | #define S3C2410_DMA_DIDSTC (0x0C) | ||
| 325 | #define S3C2410_DMA_DCON (0x10) | ||
| 326 | #define S3C2410_DMA_DSTAT (0x14) | ||
| 327 | #define S3C2410_DMA_DCSRC (0x18) | ||
| 328 | #define S3C2410_DMA_DCDST (0x1C) | ||
| 329 | #define S3C2410_DMA_DMASKTRIG (0x20) | ||
| 330 | #define S3C2412_DMA_DMAREQSEL (0x24) | ||
| 331 | #define S3C2443_DMA_DMAREQSEL (0x24) | ||
| 332 | |||
| 333 | #define S3C2410_DISRCC_INC (1<<0) | ||
| 334 | #define S3C2410_DISRCC_APB (1<<1) | ||
| 335 | |||
| 336 | #define S3C2410_DMASKTRIG_STOP (1<<2) | ||
| 337 | #define S3C2410_DMASKTRIG_ON (1<<1) | ||
| 338 | #define S3C2410_DMASKTRIG_SWTRIG (1<<0) | ||
| 339 | |||
| 340 | #define S3C2410_DCON_DEMAND (0<<31) | ||
| 341 | #define S3C2410_DCON_HANDSHAKE (1<<31) | ||
| 342 | #define S3C2410_DCON_SYNC_PCLK (0<<30) | ||
| 343 | #define S3C2410_DCON_SYNC_HCLK (1<<30) | ||
| 344 | |||
| 345 | #define S3C2410_DCON_INTREQ (1<<29) | ||
| 346 | |||
| 347 | #define S3C2410_DCON_CH0_XDREQ0 (0<<24) | ||
| 348 | #define S3C2410_DCON_CH0_UART0 (1<<24) | ||
| 349 | #define S3C2410_DCON_CH0_SDI (2<<24) | ||
| 350 | #define S3C2410_DCON_CH0_TIMER (3<<24) | ||
| 351 | #define S3C2410_DCON_CH0_USBEP1 (4<<24) | ||
| 352 | |||
| 353 | #define S3C2410_DCON_CH1_XDREQ1 (0<<24) | ||
| 354 | #define S3C2410_DCON_CH1_UART1 (1<<24) | ||
| 355 | #define S3C2410_DCON_CH1_I2SSDI (2<<24) | ||
| 356 | #define S3C2410_DCON_CH1_SPI (3<<24) | ||
| 357 | #define S3C2410_DCON_CH1_USBEP2 (4<<24) | ||
| 358 | |||
| 359 | #define S3C2410_DCON_CH2_I2SSDO (0<<24) | ||
| 360 | #define S3C2410_DCON_CH2_I2SSDI (1<<24) | ||
| 361 | #define S3C2410_DCON_CH2_SDI (2<<24) | ||
| 362 | #define S3C2410_DCON_CH2_TIMER (3<<24) | ||
| 363 | #define S3C2410_DCON_CH2_USBEP3 (4<<24) | ||
| 364 | |||
| 365 | #define S3C2410_DCON_CH3_UART2 (0<<24) | ||
| 366 | #define S3C2410_DCON_CH3_SDI (1<<24) | ||
| 367 | #define S3C2410_DCON_CH3_SPI (2<<24) | ||
| 368 | #define S3C2410_DCON_CH3_TIMER (3<<24) | ||
| 369 | #define S3C2410_DCON_CH3_USBEP4 (4<<24) | ||
| 370 | |||
| 371 | #define S3C2410_DCON_SRCSHIFT (24) | ||
| 372 | #define S3C2410_DCON_SRCMASK (7<<24) | ||
| 373 | |||
| 374 | #define S3C2410_DCON_BYTE (0<<20) | ||
| 375 | #define S3C2410_DCON_HALFWORD (1<<20) | ||
| 376 | #define S3C2410_DCON_WORD (2<<20) | ||
| 377 | |||
| 378 | #define S3C2410_DCON_AUTORELOAD (0<<22) | ||
| 379 | #define S3C2410_DCON_NORELOAD (1<<22) | ||
| 380 | #define S3C2410_DCON_HWTRIG (1<<23) | ||
| 381 | |||
| 382 | #ifdef CONFIG_CPU_S3C2440 | ||
| 383 | #define S3C2440_DIDSTC_CHKINT (1<<2) | ||
| 384 | |||
| 385 | #define S3C2440_DCON_CH0_I2SSDO (5<<24) | ||
| 386 | #define S3C2440_DCON_CH0_PCMIN (6<<24) | ||
| 387 | |||
| 388 | #define S3C2440_DCON_CH1_PCMOUT (5<<24) | ||
| 389 | #define S3C2440_DCON_CH1_SDI (6<<24) | ||
| 390 | |||
| 391 | #define S3C2440_DCON_CH2_PCMIN (5<<24) | ||
| 392 | #define S3C2440_DCON_CH2_MICIN (6<<24) | ||
| 393 | |||
| 394 | #define S3C2440_DCON_CH3_MICIN (5<<24) | ||
| 395 | #define S3C2440_DCON_CH3_PCMOUT (6<<24) | ||
| 396 | #endif | ||
| 397 | |||
| 398 | #ifdef CONFIG_CPU_S3C2412 | ||
| 399 | |||
| 400 | #define S3C2412_DMAREQSEL_SRC(x) ((x)<<1) | ||
| 401 | |||
| 402 | #define S3C2412_DMAREQSEL_HW (1) | ||
| 403 | |||
| 404 | #define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0) | ||
| 405 | #define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1) | ||
| 406 | #define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2) | ||
| 407 | #define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3) | ||
| 408 | #define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4) | ||
| 409 | #define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5) | ||
| 410 | #define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9) | ||
| 411 | #define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10) | ||
| 412 | #define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13) | ||
| 413 | #define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14) | ||
| 414 | #define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15) | ||
| 415 | #define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16) | ||
| 416 | #define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17) | ||
| 417 | #define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18) | ||
| 418 | #define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19) | ||
| 419 | #define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20) | ||
| 420 | #define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21) | ||
| 421 | #define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) | ||
| 422 | #define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) | ||
| 423 | #define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) | ||
| 424 | |||
| 425 | #endif | ||
| 426 | |||
| 427 | #define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) | ||
| 428 | |||
| 429 | #define S3C2443_DMAREQSEL_HW (1) | ||
| 430 | |||
| 431 | #define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0) | ||
| 432 | #define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1) | ||
| 433 | #define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2) | ||
| 434 | #define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3) | ||
| 435 | #define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4) | ||
| 436 | #define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5) | ||
| 437 | #define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9) | ||
| 438 | #define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10) | ||
| 439 | #define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17) | ||
| 440 | #define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18) | ||
| 441 | #define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19) | ||
| 442 | #define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20) | ||
| 443 | #define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21) | ||
| 444 | #define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22) | ||
| 445 | #define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23) | ||
| 446 | #define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24) | ||
| 447 | #define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) | ||
| 448 | #define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) | ||
| 449 | #define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) | ||
| 450 | #define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) | ||
| 451 | #define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) | ||
| 452 | |||
| 453 | #endif /* __ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S deleted file mode 100644 index f70d051b267b..000000000000 --- a/include/asm-arm/arch-s3c2410/entry-macro.S +++ /dev/null | |||
| @@ -1,78 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-s3c2410/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for S3C2410-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /* We have a problem that the INTOFFSET register does not always | ||
| 12 | * show one interrupt. Occasionally we get two interrupts through | ||
| 13 | * the prioritiser, and this causes the INTOFFSET register to show | ||
| 14 | * what looks like the logical-or of the two interrupt numbers. | ||
| 15 | * | ||
| 16 | * Thanks to Klaus, Shannon, et al for helping to debug this problem | ||
| 17 | */ | ||
| 18 | |||
| 19 | #define INTPND (0x10) | ||
| 20 | #define INTOFFSET (0x14) | ||
| 21 | |||
| 22 | #include <asm/arch/hardware.h> | ||
| 23 | #include <asm/irq.h> | ||
| 24 | |||
| 25 | .macro get_irqnr_preamble, base, tmp | ||
| 26 | .endm | ||
| 27 | |||
| 28 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 29 | .endm | ||
| 30 | |||
| 31 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 32 | |||
| 33 | mov \base, #S3C24XX_VA_IRQ | ||
| 34 | |||
| 35 | @@ try the interrupt offset register, since it is there | ||
| 36 | |||
| 37 | ldr \irqstat, [ \base, #INTPND ] | ||
| 38 | teq \irqstat, #0 | ||
| 39 | beq 1002f | ||
| 40 | ldr \irqnr, [ \base, #INTOFFSET ] | ||
| 41 | mov \tmp, #1 | ||
| 42 | tst \irqstat, \tmp, lsl \irqnr | ||
| 43 | bne 1001f | ||
| 44 | |||
| 45 | @@ the number specified is not a valid irq, so try | ||
| 46 | @@ and work it out for ourselves | ||
| 47 | |||
| 48 | mov \irqnr, #0 @@ start here | ||
| 49 | |||
| 50 | @@ work out which irq (if any) we got | ||
| 51 | |||
| 52 | movs \tmp, \irqstat, lsl#16 | ||
| 53 | addeq \irqnr, \irqnr, #16 | ||
| 54 | moveq \irqstat, \irqstat, lsr#16 | ||
| 55 | tst \irqstat, #0xff | ||
| 56 | addeq \irqnr, \irqnr, #8 | ||
| 57 | moveq \irqstat, \irqstat, lsr#8 | ||
| 58 | tst \irqstat, #0xf | ||
| 59 | addeq \irqnr, \irqnr, #4 | ||
| 60 | moveq \irqstat, \irqstat, lsr#4 | ||
| 61 | tst \irqstat, #0x3 | ||
| 62 | addeq \irqnr, \irqnr, #2 | ||
| 63 | moveq \irqstat, \irqstat, lsr#2 | ||
| 64 | tst \irqstat, #0x1 | ||
| 65 | addeq \irqnr, \irqnr, #1 | ||
| 66 | |||
| 67 | @@ we have the value | ||
| 68 | 1001: | ||
| 69 | adds \irqnr, \irqnr, #IRQ_EINT0 | ||
| 70 | 1002: | ||
| 71 | @@ exit here, Z flag unset if IRQ | ||
| 72 | |||
| 73 | .endm | ||
| 74 | |||
| 75 | /* currently don't need an disable_fiq macro */ | ||
| 76 | |||
| 77 | .macro disable_fiq | ||
| 78 | .endm | ||
diff --git a/include/asm-arm/arch-s3c2410/fb.h b/include/asm-arm/arch-s3c2410/fb.h deleted file mode 100644 index 5d0262601a7e..000000000000 --- a/include/asm-arm/arch-s3c2410/fb.h +++ /dev/null | |||
| @@ -1,74 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/fb.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org> | ||
| 4 | * | ||
| 5 | * Inspired by pxafb.h | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARM_FB_H | ||
| 13 | #define __ASM_ARM_FB_H | ||
| 14 | |||
| 15 | #include <asm/arch/regs-lcd.h> | ||
| 16 | |||
| 17 | struct s3c2410fb_hw { | ||
| 18 | unsigned long lcdcon1; | ||
| 19 | unsigned long lcdcon2; | ||
| 20 | unsigned long lcdcon3; | ||
| 21 | unsigned long lcdcon4; | ||
| 22 | unsigned long lcdcon5; | ||
| 23 | }; | ||
| 24 | |||
| 25 | /* LCD description */ | ||
| 26 | struct s3c2410fb_display { | ||
| 27 | /* LCD type */ | ||
| 28 | unsigned type; | ||
| 29 | |||
| 30 | /* Screen size */ | ||
| 31 | unsigned short width; | ||
| 32 | unsigned short height; | ||
| 33 | |||
| 34 | /* Screen info */ | ||
| 35 | unsigned short xres; | ||
| 36 | unsigned short yres; | ||
| 37 | unsigned short bpp; | ||
| 38 | |||
| 39 | unsigned pixclock; /* pixclock in picoseconds */ | ||
| 40 | unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */ | ||
| 41 | unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */ | ||
| 42 | unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */ | ||
| 43 | unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */ | ||
| 44 | unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */ | ||
| 45 | unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */ | ||
| 46 | |||
| 47 | /* lcd configuration registers */ | ||
| 48 | unsigned long lcdcon5; | ||
| 49 | }; | ||
| 50 | |||
| 51 | struct s3c2410fb_mach_info { | ||
| 52 | |||
| 53 | struct s3c2410fb_display *displays; /* attached diplays info */ | ||
| 54 | unsigned num_displays; /* number of defined displays */ | ||
| 55 | unsigned default_display; | ||
| 56 | |||
| 57 | /* GPIOs */ | ||
| 58 | |||
| 59 | unsigned long gpcup; | ||
| 60 | unsigned long gpcup_mask; | ||
| 61 | unsigned long gpccon; | ||
| 62 | unsigned long gpccon_mask; | ||
| 63 | unsigned long gpdup; | ||
| 64 | unsigned long gpdup_mask; | ||
| 65 | unsigned long gpdcon; | ||
| 66 | unsigned long gpdcon_mask; | ||
| 67 | |||
| 68 | /* lpc3600 control register */ | ||
| 69 | unsigned long lpcsel; | ||
| 70 | }; | ||
| 71 | |||
| 72 | extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *); | ||
| 73 | |||
| 74 | #endif /* __ASM_ARM_FB_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/gpio.h b/include/asm-arm/arch-s3c2410/gpio.h deleted file mode 100644 index 18e10d2c35ea..000000000000 --- a/include/asm-arm/arch-s3c2410/gpio.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/gpio.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2008 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * S3C2410 - GPIO lib support | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #define gpio_get_value __gpio_get_value | ||
| 15 | #define gpio_set_value __gpio_set_value | ||
| 16 | #define gpio_cansleep __gpio_cansleep | ||
| 17 | |||
| 18 | #include <asm-generic/gpio.h> | ||
diff --git a/include/asm-arm/arch-s3c2410/h1940-latch.h b/include/asm-arm/arch-s3c2410/h1940-latch.h deleted file mode 100644 index c3de5ab102eb..000000000000 --- a/include/asm-arm/arch-s3c2410/h1940-latch.h +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/h1940-latch.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2005 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * iPAQ H1940 series - latch definitions | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_H1940_LATCH_H | ||
| 15 | #define __ASM_ARCH_H1940_LATCH_H | ||
| 16 | |||
| 17 | |||
| 18 | #ifndef __ASSEMBLY__ | ||
| 19 | #define H1940_LATCH ((void __force __iomem *)0xF8000000) | ||
| 20 | #else | ||
| 21 | #define H1940_LATCH 0xF8000000 | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #define H1940_PA_LATCH (S3C2410_CS2) | ||
| 25 | |||
| 26 | /* SD layer latch */ | ||
| 27 | |||
| 28 | #define H1940_LATCH_SDQ1 (1<<16) | ||
| 29 | #define H1940_LATCH_LCD_P1 (1<<17) | ||
| 30 | #define H1940_LATCH_LCD_P2 (1<<18) | ||
| 31 | #define H1940_LATCH_LCD_P3 (1<<19) | ||
| 32 | #define H1940_LATCH_MAX1698_nSHUTDOWN (1<<20) /* LCD backlight */ | ||
| 33 | #define H1940_LATCH_LED_RED (1<<21) | ||
| 34 | #define H1940_LATCH_SDQ7 (1<<22) | ||
| 35 | #define H1940_LATCH_USB_DP (1<<23) | ||
| 36 | |||
| 37 | /* CPU layer latch */ | ||
| 38 | |||
| 39 | #define H1940_LATCH_UDA_POWER (1<<24) | ||
| 40 | #define H1940_LATCH_AUDIO_POWER (1<<25) | ||
| 41 | #define H1940_LATCH_SM803_ENABLE (1<<26) | ||
| 42 | #define H1940_LATCH_LCD_P4 (1<<27) | ||
| 43 | #define H1940_LATCH_CPUQ5 (1<<28) /* untraced */ | ||
| 44 | #define H1940_LATCH_BLUETOOTH_POWER (1<<29) /* active high */ | ||
| 45 | #define H1940_LATCH_LED_GREEN (1<<30) | ||
| 46 | #define H1940_LATCH_LED_FLASH (1<<31) | ||
| 47 | |||
| 48 | /* default settings */ | ||
| 49 | |||
| 50 | #define H1940_LATCH_DEFAULT \ | ||
| 51 | H1940_LATCH_LCD_P4 | \ | ||
| 52 | H1940_LATCH_SM803_ENABLE | \ | ||
| 53 | H1940_LATCH_SDQ1 | \ | ||
| 54 | H1940_LATCH_LCD_P1 | \ | ||
| 55 | H1940_LATCH_LCD_P2 | \ | ||
| 56 | H1940_LATCH_LCD_P3 | \ | ||
| 57 | H1940_LATCH_MAX1698_nSHUTDOWN | \ | ||
| 58 | H1940_LATCH_CPUQ5 | ||
| 59 | |||
| 60 | /* control functions */ | ||
| 61 | |||
| 62 | extern void h1940_latch_control(unsigned int clear, unsigned int set); | ||
| 63 | |||
| 64 | #endif /* __ASM_ARCH_H1940_LATCH_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/h1940.h b/include/asm-arm/arch-s3c2410/h1940.h deleted file mode 100644 index 6135592e60f2..000000000000 --- a/include/asm-arm/arch-s3c2410/h1940.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/h1940.h | ||
| 2 | * | ||
| 3 | * Copyright 2006 Ben Dooks <ben-linux@fluff.org> | ||
| 4 | * | ||
| 5 | * H1940 definitions | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_H1940_H | ||
| 13 | #define __ASM_ARCH_H1940_H | ||
| 14 | |||
| 15 | #define H1940_SUSPEND_CHECKSUM (0x30003ff8) | ||
| 16 | #define H1940_SUSPEND_RESUMEAT (0x30081000) | ||
| 17 | #define H1940_SUSPEND_CHECK (0x30080000) | ||
| 18 | |||
| 19 | extern void h1940_pm_return(void); | ||
| 20 | |||
| 21 | #endif /* __ASM_ARCH_H1940_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h deleted file mode 100644 index 6dd10be43145..000000000000 --- a/include/asm-arm/arch-s3c2410/hardware.h +++ /dev/null | |||
| @@ -1,137 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/hardware.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C2410 - hardware | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 14 | #define __ASM_ARCH_HARDWARE_H | ||
| 15 | |||
| 16 | #ifndef __ASSEMBLY__ | ||
| 17 | |||
| 18 | /* external functions for GPIO support | ||
| 19 | * | ||
| 20 | * These allow various different clients to access the same GPIO | ||
| 21 | * registers without conflicting. If your driver only owns the entire | ||
| 22 | * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. | ||
| 23 | */ | ||
| 24 | |||
| 25 | /* s3c2410_gpio_cfgpin | ||
| 26 | * | ||
| 27 | * set the configuration of the given pin to the value passed. | ||
| 28 | * | ||
| 29 | * eg: | ||
| 30 | * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); | ||
| 31 | * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); | ||
| 32 | */ | ||
| 33 | |||
| 34 | extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); | ||
| 35 | |||
| 36 | extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); | ||
| 37 | |||
| 38 | /* s3c2410_gpio_getirq | ||
| 39 | * | ||
| 40 | * turn the given pin number into the corresponding IRQ number | ||
| 41 | * | ||
| 42 | * returns: | ||
| 43 | * < 0 = no interrupt for this pin | ||
| 44 | * >=0 = interrupt number for the pin | ||
| 45 | */ | ||
| 46 | |||
| 47 | extern int s3c2410_gpio_getirq(unsigned int pin); | ||
| 48 | |||
| 49 | /* s3c2410_gpio_irq2pin | ||
| 50 | * | ||
| 51 | * turn the given irq number into the corresponding GPIO number | ||
| 52 | * | ||
| 53 | * returns: | ||
| 54 | * < 0 = no pin | ||
| 55 | * >=0 = gpio pin number | ||
| 56 | */ | ||
| 57 | |||
| 58 | extern int s3c2410_gpio_irq2pin(unsigned int irq); | ||
| 59 | |||
| 60 | #ifdef CONFIG_CPU_S3C2400 | ||
| 61 | |||
| 62 | extern int s3c2400_gpio_getirq(unsigned int pin); | ||
| 63 | |||
| 64 | #endif /* CONFIG_CPU_S3C2400 */ | ||
| 65 | |||
| 66 | /* s3c2410_gpio_irqfilter | ||
| 67 | * | ||
| 68 | * set the irq filtering on the given pin | ||
| 69 | * | ||
| 70 | * on = 0 => disable filtering | ||
| 71 | * 1 => enable filtering | ||
| 72 | * | ||
| 73 | * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with | ||
| 74 | * width of filter (0 through 63) | ||
| 75 | * | ||
| 76 | * | ||
| 77 | */ | ||
| 78 | |||
| 79 | extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, | ||
| 80 | unsigned int config); | ||
| 81 | |||
| 82 | /* s3c2410_gpio_pullup | ||
| 83 | * | ||
| 84 | * configure the pull-up control on the given pin | ||
| 85 | * | ||
| 86 | * to = 1 => disable the pull-up | ||
| 87 | * 0 => enable the pull-up | ||
| 88 | * | ||
| 89 | * eg; | ||
| 90 | * | ||
| 91 | * s3c2410_gpio_pullup(S3C2410_GPB0, 0); | ||
| 92 | * s3c2410_gpio_pullup(S3C2410_GPE8, 0); | ||
| 93 | */ | ||
| 94 | |||
| 95 | extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); | ||
| 96 | |||
| 97 | /* s3c2410_gpio_getpull | ||
| 98 | * | ||
| 99 | * Read the state of the pull-up on a given pin | ||
| 100 | * | ||
| 101 | * return: | ||
| 102 | * < 0 => error code | ||
| 103 | * 0 => enabled | ||
| 104 | * 1 => disabled | ||
| 105 | */ | ||
| 106 | |||
| 107 | extern int s3c2410_gpio_getpull(unsigned int pin); | ||
| 108 | |||
| 109 | extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); | ||
| 110 | |||
| 111 | extern unsigned int s3c2410_gpio_getpin(unsigned int pin); | ||
| 112 | |||
| 113 | extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); | ||
| 114 | |||
| 115 | #ifdef CONFIG_CPU_S3C2440 | ||
| 116 | |||
| 117 | extern int s3c2440_set_dsc(unsigned int pin, unsigned int value); | ||
| 118 | |||
| 119 | #endif /* CONFIG_CPU_S3C2440 */ | ||
| 120 | |||
| 121 | #ifdef CONFIG_CPU_S3C2412 | ||
| 122 | |||
| 123 | extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state); | ||
| 124 | |||
| 125 | #endif /* CONFIG_CPU_S3C2412 */ | ||
| 126 | |||
| 127 | #endif /* __ASSEMBLY__ */ | ||
| 128 | |||
| 129 | #include <asm/sizes.h> | ||
| 130 | #include <asm/arch/map.h> | ||
| 131 | |||
| 132 | /* machine specific hardware definitions should go after this */ | ||
| 133 | |||
| 134 | /* currently here until moved into config (todo) */ | ||
| 135 | #define CONFIG_NO_MULTIWORD_IO | ||
| 136 | |||
| 137 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/idle.h b/include/asm-arm/arch-s3c2410/idle.h deleted file mode 100644 index eed450608f9c..000000000000 --- a/include/asm-arm/arch-s3c2410/idle.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/idle.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2410 CPU Idle controls | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_IDLE_H | ||
| 14 | #define __ASM_ARCH_IDLE_H __FILE__ | ||
| 15 | |||
| 16 | /* This allows the over-ride of the default idle code, in case there | ||
| 17 | * is any other things to be done over idle (like DVS) | ||
| 18 | */ | ||
| 19 | |||
| 20 | extern void (*s3c24xx_idle)(void); | ||
| 21 | |||
| 22 | extern void s3c24xx_default_idle(void); | ||
| 23 | |||
| 24 | #endif /* __ASM_ARCH_IDLE_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h deleted file mode 100644 index 3756c993776c..000000000000 --- a/include/asm-arm/arch-s3c2410/io.h +++ /dev/null | |||
| @@ -1,218 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-s3c2410/io.h | ||
| 3 | * from linux/include/asm-arm/arch-rpc/io.h | ||
| 4 | * | ||
| 5 | * Copyright (C) 1997 Russell King | ||
| 6 | * (C) 2003 Simtec Electronics | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 10 | #define __ASM_ARM_ARCH_IO_H | ||
| 11 | |||
| 12 | #include <asm/arch/hardware.h> | ||
| 13 | |||
| 14 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 15 | |||
| 16 | /* | ||
| 17 | * We use two different types of addressing - PC style addresses, and ARM | ||
| 18 | * addresses. PC style accesses the PC hardware with the normal PC IO | ||
| 19 | * addresses, eg 0x3f8 for serial#1. ARM addresses are above A28 | ||
| 20 | * and are translated to the start of IO. Note that all addresses are | ||
| 21 | * not shifted left! | ||
| 22 | */ | ||
| 23 | |||
| 24 | #define __PORT_PCIO(x) ((x) < (1<<28)) | ||
| 25 | |||
| 26 | #define PCIO_BASE (S3C24XX_VA_ISA_WORD) | ||
| 27 | #define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE) | ||
| 28 | #define PCIO_BASE_w (S3C24XX_VA_ISA_WORD) | ||
| 29 | #define PCIO_BASE_l (S3C24XX_VA_ISA_WORD) | ||
| 30 | /* | ||
| 31 | * Dynamic IO functions - let the compiler | ||
| 32 | * optimize the expressions | ||
| 33 | */ | ||
| 34 | |||
| 35 | #define DECLARE_DYN_OUT(sz,fnsuffix,instr) \ | ||
| 36 | static inline void __out##fnsuffix (unsigned int val, unsigned int port) \ | ||
| 37 | { \ | ||
| 38 | unsigned long temp; \ | ||
| 39 | __asm__ __volatile__( \ | ||
| 40 | "cmp %2, #(1<<28)\n\t" \ | ||
| 41 | "mov %0, %2\n\t" \ | ||
| 42 | "addcc %0, %0, %3\n\t" \ | ||
| 43 | "str" instr " %1, [%0, #0 ] @ out" #fnsuffix \ | ||
| 44 | : "=&r" (temp) \ | ||
| 45 | : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ | ||
| 46 | : "cc"); \ | ||
| 47 | } | ||
| 48 | |||
| 49 | |||
| 50 | #define DECLARE_DYN_IN(sz,fnsuffix,instr) \ | ||
| 51 | static inline unsigned sz __in##fnsuffix (unsigned int port) \ | ||
| 52 | { \ | ||
| 53 | unsigned long temp, value; \ | ||
| 54 | __asm__ __volatile__( \ | ||
| 55 | "cmp %2, #(1<<28)\n\t" \ | ||
| 56 | "mov %0, %2\n\t" \ | ||
| 57 | "addcc %0, %0, %3\n\t" \ | ||
| 58 | "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \ | ||
| 59 | : "=&r" (temp), "=r" (value) \ | ||
| 60 | : "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ | ||
| 61 | : "cc"); \ | ||
| 62 | return (unsigned sz)value; \ | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline void __iomem *__ioaddr (unsigned long port) | ||
| 66 | { | ||
| 67 | return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port; | ||
| 68 | } | ||
| 69 | |||
| 70 | #define DECLARE_IO(sz,fnsuffix,instr) \ | ||
| 71 | DECLARE_DYN_IN(sz,fnsuffix,instr) \ | ||
| 72 | DECLARE_DYN_OUT(sz,fnsuffix,instr) | ||
| 73 | |||
| 74 | DECLARE_IO(char,b,"b") | ||
| 75 | DECLARE_IO(short,w,"h") | ||
| 76 | DECLARE_IO(int,l,"") | ||
| 77 | |||
| 78 | #undef DECLARE_IO | ||
| 79 | #undef DECLARE_DYN_IN | ||
| 80 | |||
| 81 | /* | ||
| 82 | * Constant address IO functions | ||
| 83 | * | ||
| 84 | * These have to be macros for the 'J' constraint to work - | ||
| 85 | * +/-4096 immediate operand. | ||
| 86 | */ | ||
| 87 | #define __outbc(value,port) \ | ||
| 88 | ({ \ | ||
| 89 | if (__PORT_PCIO((port))) \ | ||
| 90 | __asm__ __volatile__( \ | ||
| 91 | "strb %0, [%1, %2] @ outbc" \ | ||
| 92 | : : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \ | ||
| 93 | else \ | ||
| 94 | __asm__ __volatile__( \ | ||
| 95 | "strb %0, [%1, #0] @ outbc" \ | ||
| 96 | : : "r" (value), "r" ((port))); \ | ||
| 97 | }) | ||
| 98 | |||
| 99 | #define __inbc(port) \ | ||
| 100 | ({ \ | ||
| 101 | unsigned char result; \ | ||
| 102 | if (__PORT_PCIO((port))) \ | ||
| 103 | __asm__ __volatile__( \ | ||
| 104 | "ldrb %0, [%1, %2] @ inbc" \ | ||
| 105 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ | ||
| 106 | else \ | ||
| 107 | __asm__ __volatile__( \ | ||
| 108 | "ldrb %0, [%1, #0] @ inbc" \ | ||
| 109 | : "=r" (result) : "r" ((port))); \ | ||
| 110 | result; \ | ||
| 111 | }) | ||
| 112 | |||
| 113 | #define __outwc(value,port) \ | ||
| 114 | ({ \ | ||
| 115 | unsigned long v = value; \ | ||
| 116 | if (__PORT_PCIO((port))) { \ | ||
| 117 | if ((port) < 256 && (port) > -256) \ | ||
| 118 | __asm__ __volatile__( \ | ||
| 119 | "strh %0, [%1, %2] @ outwc" \ | ||
| 120 | : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ | ||
| 121 | else if ((port) > 0) \ | ||
| 122 | __asm__ __volatile__( \ | ||
| 123 | "strh %0, [%1, %2] @ outwc" \ | ||
| 124 | : : "r" (v), \ | ||
| 125 | "r" (PCIO_BASE + ((port) & ~0xff)), \ | ||
| 126 | "Jr" (((port) & 0xff))); \ | ||
| 127 | else \ | ||
| 128 | __asm__ __volatile__( \ | ||
| 129 | "strh %0, [%1, #0] @ outwc" \ | ||
| 130 | : : "r" (v), \ | ||
| 131 | "r" (PCIO_BASE + (port))); \ | ||
| 132 | } else \ | ||
| 133 | __asm__ __volatile__( \ | ||
| 134 | "strh %0, [%1, #0] @ outwc" \ | ||
| 135 | : : "r" (v), "r" ((port))); \ | ||
| 136 | }) | ||
| 137 | |||
| 138 | #define __inwc(port) \ | ||
| 139 | ({ \ | ||
| 140 | unsigned short result; \ | ||
| 141 | if (__PORT_PCIO((port))) { \ | ||
| 142 | if ((port) < 256 && (port) > -256 ) \ | ||
| 143 | __asm__ __volatile__( \ | ||
| 144 | "ldrh %0, [%1, %2] @ inwc" \ | ||
| 145 | : "=r" (result) \ | ||
| 146 | : "r" (PCIO_BASE), \ | ||
| 147 | "Jr" ((port))); \ | ||
| 148 | else if ((port) > 0) \ | ||
| 149 | __asm__ __volatile__( \ | ||
| 150 | "ldrh %0, [%1, %2] @ inwc" \ | ||
| 151 | : "=r" (result) \ | ||
| 152 | : "r" (PCIO_BASE + ((port) & ~0xff)), \ | ||
| 153 | "Jr" (((port) & 0xff))); \ | ||
| 154 | else \ | ||
| 155 | __asm__ __volatile__( \ | ||
| 156 | "ldrh %0, [%1, #0] @ inwc" \ | ||
| 157 | : "=r" (result) \ | ||
| 158 | : "r" (PCIO_BASE + ((port)))); \ | ||
| 159 | } else \ | ||
| 160 | __asm__ __volatile__( \ | ||
| 161 | "ldrh %0, [%1, #0] @ inwc" \ | ||
| 162 | : "=r" (result) : "r" ((port))); \ | ||
| 163 | result; \ | ||
| 164 | }) | ||
| 165 | |||
| 166 | #define __outlc(value,port) \ | ||
| 167 | ({ \ | ||
| 168 | unsigned long v = value; \ | ||
| 169 | if (__PORT_PCIO((port))) \ | ||
| 170 | __asm__ __volatile__( \ | ||
| 171 | "str %0, [%1, %2] @ outlc" \ | ||
| 172 | : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ | ||
| 173 | else \ | ||
| 174 | __asm__ __volatile__( \ | ||
| 175 | "str %0, [%1, #0] @ outlc" \ | ||
| 176 | : : "r" (v), "r" ((port))); \ | ||
| 177 | }) | ||
| 178 | |||
| 179 | #define __inlc(port) \ | ||
| 180 | ({ \ | ||
| 181 | unsigned long result; \ | ||
| 182 | if (__PORT_PCIO((port))) \ | ||
| 183 | __asm__ __volatile__( \ | ||
| 184 | "ldr %0, [%1, %2] @ inlc" \ | ||
| 185 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ | ||
| 186 | else \ | ||
| 187 | __asm__ __volatile__( \ | ||
| 188 | "ldr %0, [%1, #0] @ inlc" \ | ||
| 189 | : "=r" (result) : "r" ((port))); \ | ||
| 190 | result; \ | ||
| 191 | }) | ||
| 192 | |||
| 193 | #define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port))) | ||
| 194 | |||
| 195 | #define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) | ||
| 196 | #define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) | ||
| 197 | #define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) | ||
| 198 | #define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) | ||
| 199 | #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) | ||
| 200 | #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) | ||
| 201 | #define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) | ||
| 202 | /* the following macro is deprecated */ | ||
| 203 | #define ioaddr(port) __ioaddr((port)) | ||
| 204 | |||
| 205 | #define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) | ||
| 206 | #define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) | ||
| 207 | #define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l) | ||
| 208 | |||
| 209 | #define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) | ||
| 210 | #define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) | ||
| 211 | #define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l) | ||
| 212 | |||
| 213 | /* | ||
| 214 | * 1:1 mapping for ioremapped regions. | ||
| 215 | */ | ||
| 216 | #define __mem_pci(x) (x) | ||
| 217 | |||
| 218 | #endif | ||
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h deleted file mode 100644 index f5435d8c3769..000000000000 --- a/include/asm-arm/arch-s3c2410/irqs.h +++ /dev/null | |||
| @@ -1,166 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/irqs.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_IRQS_H | ||
| 13 | #define __ASM_ARCH_IRQS_H __FILE__ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARM_IRQ_H | ||
| 16 | #error "Do not include this directly, instead #include <asm/irq.h>" | ||
| 17 | #endif | ||
| 18 | |||
| 19 | /* we keep the first set of CPU IRQs out of the range of | ||
| 20 | * the ISA space, so that the PC104 has them to itself | ||
| 21 | * and we don't end up having to do horrible things to the | ||
| 22 | * standard ISA drivers.... | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define S3C2410_CPUIRQ_OFFSET (16) | ||
| 26 | |||
| 27 | #define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) | ||
| 28 | |||
| 29 | /* main cpu interrupts */ | ||
| 30 | #define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ | ||
| 31 | #define IRQ_EINT1 S3C2410_IRQ(1) | ||
| 32 | #define IRQ_EINT2 S3C2410_IRQ(2) | ||
| 33 | #define IRQ_EINT3 S3C2410_IRQ(3) | ||
| 34 | #define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ | ||
| 35 | #define IRQ_EINT8t23 S3C2410_IRQ(5) | ||
| 36 | #define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ | ||
| 37 | #define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */ | ||
| 38 | #define IRQ_BATT_FLT S3C2410_IRQ(7) | ||
| 39 | #define IRQ_TICK S3C2410_IRQ(8) /* 24 */ | ||
| 40 | #define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */ | ||
| 41 | #define IRQ_TIMER0 S3C2410_IRQ(10) | ||
| 42 | #define IRQ_TIMER1 S3C2410_IRQ(11) | ||
| 43 | #define IRQ_TIMER2 S3C2410_IRQ(12) | ||
| 44 | #define IRQ_TIMER3 S3C2410_IRQ(13) | ||
| 45 | #define IRQ_TIMER4 S3C2410_IRQ(14) | ||
| 46 | #define IRQ_UART2 S3C2410_IRQ(15) | ||
| 47 | #define IRQ_LCD S3C2410_IRQ(16) /* 32 */ | ||
| 48 | #define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */ | ||
| 49 | #define IRQ_DMA1 S3C2410_IRQ(18) | ||
| 50 | #define IRQ_DMA2 S3C2410_IRQ(19) | ||
| 51 | #define IRQ_DMA3 S3C2410_IRQ(20) | ||
| 52 | #define IRQ_SDI S3C2410_IRQ(21) | ||
| 53 | #define IRQ_SPI0 S3C2410_IRQ(22) | ||
| 54 | #define IRQ_UART1 S3C2410_IRQ(23) | ||
| 55 | #define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ | ||
| 56 | #define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ | ||
| 57 | #define IRQ_USBD S3C2410_IRQ(25) | ||
| 58 | #define IRQ_USBH S3C2410_IRQ(26) | ||
| 59 | #define IRQ_IIC S3C2410_IRQ(27) | ||
| 60 | #define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ | ||
| 61 | #define IRQ_SPI1 S3C2410_IRQ(29) | ||
| 62 | #define IRQ_RTC S3C2410_IRQ(30) | ||
| 63 | #define IRQ_ADCPARENT S3C2410_IRQ(31) | ||
| 64 | |||
| 65 | /* interrupts generated from the external interrupts sources */ | ||
| 66 | #define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ | ||
| 67 | #define IRQ_EINT5 S3C2410_IRQ(33) | ||
| 68 | #define IRQ_EINT6 S3C2410_IRQ(34) | ||
| 69 | #define IRQ_EINT7 S3C2410_IRQ(35) | ||
| 70 | #define IRQ_EINT8 S3C2410_IRQ(36) | ||
| 71 | #define IRQ_EINT9 S3C2410_IRQ(37) | ||
| 72 | #define IRQ_EINT10 S3C2410_IRQ(38) | ||
| 73 | #define IRQ_EINT11 S3C2410_IRQ(39) | ||
| 74 | #define IRQ_EINT12 S3C2410_IRQ(40) | ||
| 75 | #define IRQ_EINT13 S3C2410_IRQ(41) | ||
| 76 | #define IRQ_EINT14 S3C2410_IRQ(42) | ||
| 77 | #define IRQ_EINT15 S3C2410_IRQ(43) | ||
| 78 | #define IRQ_EINT16 S3C2410_IRQ(44) | ||
| 79 | #define IRQ_EINT17 S3C2410_IRQ(45) | ||
| 80 | #define IRQ_EINT18 S3C2410_IRQ(46) | ||
| 81 | #define IRQ_EINT19 S3C2410_IRQ(47) | ||
| 82 | #define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ | ||
| 83 | #define IRQ_EINT21 S3C2410_IRQ(49) | ||
| 84 | #define IRQ_EINT22 S3C2410_IRQ(50) | ||
| 85 | #define IRQ_EINT23 S3C2410_IRQ(51) | ||
| 86 | |||
| 87 | |||
| 88 | #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) | ||
| 89 | |||
| 90 | #define IRQ_LCD_FIFO S3C2410_IRQ(52) | ||
| 91 | #define IRQ_LCD_FRAME S3C2410_IRQ(53) | ||
| 92 | |||
| 93 | /* IRQs for the interal UARTs, and ADC | ||
| 94 | * these need to be ordered in number of appearance in the | ||
| 95 | * SUBSRC mask register | ||
| 96 | */ | ||
| 97 | |||
| 98 | #define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) | ||
| 99 | |||
| 100 | #define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ | ||
| 101 | #define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) | ||
| 102 | #define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) | ||
| 103 | |||
| 104 | #define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ | ||
| 105 | #define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) | ||
| 106 | #define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) | ||
| 107 | |||
| 108 | #define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ | ||
| 109 | #define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) | ||
| 110 | #define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) | ||
| 111 | |||
| 112 | #define IRQ_TC S3C2410_IRQSUB(9) | ||
| 113 | #define IRQ_ADC S3C2410_IRQSUB(10) | ||
| 114 | |||
| 115 | /* extra irqs for s3c2412 */ | ||
| 116 | |||
| 117 | #define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) | ||
| 118 | |||
| 119 | #define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) | ||
| 120 | #define IRQ_S3C2412_CF S3C2410_IRQSUB(14) | ||
| 121 | |||
| 122 | /* extra irqs for s3c2440 */ | ||
| 123 | |||
| 124 | #define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ | ||
| 125 | #define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */ | ||
| 126 | #define IRQ_S3C2440_WDT S3C2410_IRQSUB(13) | ||
| 127 | #define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14) | ||
| 128 | |||
| 129 | /* irqs for s3c2443 */ | ||
| 130 | |||
| 131 | #define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */ | ||
| 132 | #define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */ | ||
| 133 | #define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */ | ||
| 134 | #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ | ||
| 135 | #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ | ||
| 136 | |||
| 137 | #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) | ||
| 138 | #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) | ||
| 139 | #define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) | ||
| 140 | #define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17) | ||
| 141 | |||
| 142 | #define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18) | ||
| 143 | #define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19) | ||
| 144 | #define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20) | ||
| 145 | #define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21) | ||
| 146 | #define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22) | ||
| 147 | #define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23) | ||
| 148 | |||
| 149 | /* UART3 */ | ||
| 150 | #define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24) | ||
| 151 | #define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25) | ||
| 152 | #define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26) | ||
| 153 | |||
| 154 | #define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) | ||
| 155 | #define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) | ||
| 156 | |||
| 157 | #ifdef CONFIG_CPU_S3C2443 | ||
| 158 | #define NR_IRQS (IRQ_S3C2443_AC97+1) | ||
| 159 | #else | ||
| 160 | #define NR_IRQS (IRQ_S3C2440_AC97+1) | ||
| 161 | #endif | ||
| 162 | |||
| 163 | /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ | ||
| 164 | #define FIQ_START IRQ_EINT0 | ||
| 165 | |||
| 166 | #endif /* __ASM_ARCH_IRQ_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/leds-gpio.h b/include/asm-arm/arch-s3c2410/leds-gpio.h deleted file mode 100644 index 800846ebddba..000000000000 --- a/include/asm-arm/arch-s3c2410/leds-gpio.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/leds-gpio.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2006 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * S3C24XX - LEDs GPIO connector | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_LEDSGPIO_H | ||
| 15 | #define __ASM_ARCH_LEDSGPIO_H "leds-gpio.h" | ||
| 16 | |||
| 17 | #define S3C24XX_LEDF_ACTLOW (1<<0) /* LED is on when GPIO low */ | ||
| 18 | #define S3C24XX_LEDF_TRISTATE (1<<1) /* tristate to turn off */ | ||
| 19 | |||
| 20 | struct s3c24xx_led_platdata { | ||
| 21 | unsigned int gpio; | ||
| 22 | unsigned int flags; | ||
| 23 | |||
| 24 | char *name; | ||
| 25 | char *def_trigger; | ||
| 26 | }; | ||
| 27 | |||
| 28 | #endif /* __ASM_ARCH_LEDSGPIO_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h deleted file mode 100644 index b33ed3b05ef5..000000000000 --- a/include/asm-arm/arch-s3c2410/map.h +++ /dev/null | |||
| @@ -1,178 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/map.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C2410 - Memory map definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_MAP_H | ||
| 14 | #define __ASM_ARCH_MAP_H | ||
| 15 | |||
| 16 | #include <asm/plat-s3c/map.h> | ||
| 17 | |||
| 18 | #define S3C2410_ADDR(x) S3C_ADDR(x) | ||
| 19 | |||
| 20 | /* interrupt controller is the first thing we put in, to make | ||
| 21 | * the assembly code for the irq detection easier | ||
| 22 | */ | ||
| 23 | #define S3C24XX_VA_IRQ S3C_VA_IRQ | ||
| 24 | #define S3C2410_PA_IRQ (0x4A000000) | ||
| 25 | #define S3C24XX_SZ_IRQ SZ_1M | ||
| 26 | |||
| 27 | /* memory controller registers */ | ||
| 28 | #define S3C24XX_VA_MEMCTRL S3C_VA_MEM | ||
| 29 | #define S3C2410_PA_MEMCTRL (0x48000000) | ||
| 30 | #define S3C24XX_SZ_MEMCTRL SZ_1M | ||
| 31 | |||
| 32 | /* USB host controller */ | ||
| 33 | #define S3C2410_PA_USBHOST (0x49000000) | ||
| 34 | #define S3C24XX_SZ_USBHOST SZ_1M | ||
| 35 | |||
| 36 | /* DMA controller */ | ||
| 37 | #define S3C2410_PA_DMA (0x4B000000) | ||
| 38 | #define S3C24XX_SZ_DMA SZ_1M | ||
| 39 | |||
| 40 | /* Clock and Power management */ | ||
| 41 | #define S3C24XX_VA_CLKPWR S3C_VA_SYS | ||
| 42 | #define S3C2410_PA_CLKPWR (0x4C000000) | ||
| 43 | #define S3C24XX_SZ_CLKPWR SZ_1M | ||
| 44 | |||
| 45 | /* LCD controller */ | ||
| 46 | #define S3C2410_PA_LCD (0x4D000000) | ||
| 47 | #define S3C24XX_SZ_LCD SZ_1M | ||
| 48 | |||
| 49 | /* NAND flash controller */ | ||
| 50 | #define S3C2410_PA_NAND (0x4E000000) | ||
| 51 | #define S3C24XX_SZ_NAND SZ_1M | ||
| 52 | |||
| 53 | /* UARTs */ | ||
| 54 | #define S3C24XX_VA_UART S3C_VA_UART | ||
| 55 | #define S3C2410_PA_UART (0x50000000) | ||
| 56 | #define S3C24XX_SZ_UART SZ_1M | ||
| 57 | |||
| 58 | /* Timers */ | ||
| 59 | #define S3C24XX_VA_TIMER S3C_VA_TIMER | ||
| 60 | #define S3C2410_PA_TIMER (0x51000000) | ||
| 61 | #define S3C24XX_SZ_TIMER SZ_1M | ||
| 62 | |||
| 63 | /* USB Device port */ | ||
| 64 | #define S3C2410_PA_USBDEV (0x52000000) | ||
| 65 | #define S3C24XX_SZ_USBDEV SZ_1M | ||
| 66 | |||
| 67 | /* Watchdog */ | ||
| 68 | #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG | ||
| 69 | #define S3C2410_PA_WATCHDOG (0x53000000) | ||
| 70 | #define S3C24XX_SZ_WATCHDOG SZ_1M | ||
| 71 | |||
| 72 | /* IIC hardware controller */ | ||
| 73 | #define S3C2410_PA_IIC (0x54000000) | ||
| 74 | #define S3C24XX_SZ_IIC SZ_1M | ||
| 75 | |||
| 76 | /* IIS controller */ | ||
| 77 | #define S3C2410_PA_IIS (0x55000000) | ||
| 78 | #define S3C24XX_SZ_IIS SZ_1M | ||
| 79 | |||
| 80 | /* GPIO ports */ | ||
| 81 | |||
| 82 | /* the calculation for the VA of this must ensure that | ||
| 83 | * it is the same distance apart from the UART in the | ||
| 84 | * phsyical address space, as the initial mapping for the IO | ||
| 85 | * is done as a 1:1 maping. This puts it (currently) at | ||
| 86 | * 0xFA800000, which is not in the way of any current mapping | ||
| 87 | * by the base system. | ||
| 88 | */ | ||
| 89 | |||
| 90 | #define S3C2410_PA_GPIO (0x56000000) | ||
| 91 | #define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) | ||
| 92 | #define S3C24XX_SZ_GPIO SZ_1M | ||
| 93 | |||
| 94 | /* RTC */ | ||
| 95 | #define S3C2410_PA_RTC (0x57000000) | ||
| 96 | #define S3C24XX_SZ_RTC SZ_1M | ||
| 97 | |||
| 98 | /* ADC */ | ||
| 99 | #define S3C2410_PA_ADC (0x58000000) | ||
| 100 | #define S3C24XX_SZ_ADC SZ_1M | ||
| 101 | |||
| 102 | /* SPI */ | ||
| 103 | #define S3C2410_PA_SPI (0x59000000) | ||
| 104 | #define S3C24XX_SZ_SPI SZ_1M | ||
| 105 | |||
| 106 | /* SDI */ | ||
| 107 | #define S3C2410_PA_SDI (0x5A000000) | ||
| 108 | #define S3C24XX_SZ_SDI SZ_1M | ||
| 109 | |||
| 110 | /* CAMIF */ | ||
| 111 | #define S3C2440_PA_CAMIF (0x4F000000) | ||
| 112 | #define S3C2440_SZ_CAMIF SZ_1M | ||
| 113 | |||
| 114 | /* AC97 */ | ||
| 115 | |||
| 116 | #define S3C2440_PA_AC97 (0x5B000000) | ||
| 117 | #define S3C2440_SZ_AC97 SZ_1M | ||
| 118 | |||
| 119 | /* S3C2443 High-speed SD/MMC */ | ||
| 120 | #define S3C2443_PA_HSMMC (0x4A800000) | ||
| 121 | #define S3C2443_SZ_HSMMC (256) | ||
| 122 | |||
| 123 | /* ISA style IO, for each machine to sort out mappings for, if it | ||
| 124 | * implements it. We reserve two 16M regions for ISA. | ||
| 125 | */ | ||
| 126 | |||
| 127 | #define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) | ||
| 128 | #define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) | ||
| 129 | |||
| 130 | /* physical addresses of all the chip-select areas */ | ||
| 131 | |||
| 132 | #define S3C2410_CS0 (0x00000000) | ||
| 133 | #define S3C2410_CS1 (0x08000000) | ||
| 134 | #define S3C2410_CS2 (0x10000000) | ||
| 135 | #define S3C2410_CS3 (0x18000000) | ||
| 136 | #define S3C2410_CS4 (0x20000000) | ||
| 137 | #define S3C2410_CS5 (0x28000000) | ||
| 138 | #define S3C2410_CS6 (0x30000000) | ||
| 139 | #define S3C2410_CS7 (0x38000000) | ||
| 140 | |||
| 141 | #define S3C2410_SDRAM_PA (S3C2410_CS6) | ||
| 142 | |||
| 143 | /* Use a single interface for common resources between S3C24XX cpus */ | ||
| 144 | |||
| 145 | #define S3C24XX_PA_IRQ S3C2410_PA_IRQ | ||
| 146 | #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL | ||
| 147 | #define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST | ||
| 148 | #define S3C24XX_PA_DMA S3C2410_PA_DMA | ||
| 149 | #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR | ||
| 150 | #define S3C24XX_PA_LCD S3C2410_PA_LCD | ||
| 151 | #define S3C24XX_PA_UART S3C2410_PA_UART | ||
| 152 | #define S3C24XX_PA_TIMER S3C2410_PA_TIMER | ||
| 153 | #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV | ||
| 154 | #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG | ||
| 155 | #define S3C24XX_PA_IIC S3C2410_PA_IIC | ||
| 156 | #define S3C24XX_PA_IIS S3C2410_PA_IIS | ||
| 157 | #define S3C24XX_PA_GPIO S3C2410_PA_GPIO | ||
| 158 | #define S3C24XX_PA_RTC S3C2410_PA_RTC | ||
| 159 | #define S3C24XX_PA_ADC S3C2410_PA_ADC | ||
| 160 | #define S3C24XX_PA_SPI S3C2410_PA_SPI | ||
| 161 | |||
| 162 | /* deal with the registers that move under the 2412/2413 */ | ||
| 163 | |||
| 164 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | ||
| 165 | #ifndef __ASSEMBLY__ | ||
| 166 | extern void __iomem *s3c24xx_va_gpio2; | ||
| 167 | #endif | ||
| 168 | #ifdef CONFIG_CPU_S3C2412_ONLY | ||
| 169 | #define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) | ||
| 170 | #else | ||
| 171 | #define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 | ||
| 172 | #endif | ||
| 173 | #else | ||
| 174 | #define s3c24xx_va_gpio2 S3C24XX_VA_GPIO | ||
| 175 | #define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO | ||
| 176 | #endif | ||
| 177 | |||
| 178 | #endif /* __ASM_ARCH_MAP_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h deleted file mode 100644 index 533e2436e707..000000000000 --- a/include/asm-arm/arch-s3c2410/memory.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/memory.h | ||
| 2 | * from linux/include/asm-arm/arch-rpc/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996,1997,1998 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 12 | #define __ASM_ARCH_MEMORY_H | ||
| 13 | |||
| 14 | #define PHYS_OFFSET UL(0x30000000) | ||
| 15 | |||
| 16 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 17 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 18 | |||
| 19 | #endif | ||
diff --git a/include/asm-arm/arch-s3c2410/osiris-cpld.h b/include/asm-arm/arch-s3c2410/osiris-cpld.h deleted file mode 100644 index 229ab2351db6..000000000000 --- a/include/asm-arm/arch-s3c2410/osiris-cpld.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/osiris-cpld.h | ||
| 2 | * | ||
| 3 | * Copyright 2005 Simtec Electronics | ||
| 4 | * http://www.simtec.co.uk/products/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * OSIRIS - CPLD control constants | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_OSIRISCPLD_H | ||
| 15 | #define __ASM_ARCH_OSIRISCPLD_H | ||
| 16 | |||
| 17 | /* CTRL0 - NAND WP control */ | ||
| 18 | |||
| 19 | #define OSIRIS_CTRL0_NANDSEL (0x3) | ||
| 20 | #define OSIRIS_CTRL0_BOOT_INT (1<<3) | ||
| 21 | #define OSIRIS_CTRL0_PCMCIA (1<<4) | ||
| 22 | #define OSIRIS_CTRL0_FIX8 (1<<5) | ||
| 23 | #define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6) | ||
| 24 | #define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7) | ||
| 25 | |||
| 26 | #define OSIRIS_CTRL1_FIX8 (1<<0) | ||
| 27 | |||
| 28 | #define OSIRIS_ID_REVMASK (0x7) | ||
| 29 | |||
| 30 | #endif /* __ASM_ARCH_OSIRISCPLD_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h deleted file mode 100644 index b5c74d2b9aaa..000000000000 --- a/include/asm-arm/arch-s3c2410/osiris-map.h +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/osiris-map.h | ||
| 2 | * | ||
| 3 | * (c) 2005 Simtec Electronics | ||
| 4 | * http://www.simtec.co.uk/products/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * OSIRIS - Memory map definitions | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | /* needs arch/map.h including with this */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_OSIRISMAP_H | ||
| 17 | #define __ASM_ARCH_OSIRISMAP_H | ||
| 18 | |||
| 19 | /* start peripherals off after the S3C2410 */ | ||
| 20 | |||
| 21 | #define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000)) | ||
| 22 | |||
| 23 | #define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26)) | ||
| 24 | |||
| 25 | /* we put the CPLD registers next, to get them out of the way */ | ||
| 26 | |||
| 27 | #define OSIRIS_VA_CTRL0 OSIRIS_IOADDR(0x00000000) | ||
| 28 | #define OSIRIS_PA_CTRL0 (OSIRIS_PA_CPLD) | ||
| 29 | |||
| 30 | #define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00100000) | ||
| 31 | #define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD + (1<<23)) | ||
| 32 | |||
| 33 | #define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00200000) | ||
| 34 | #define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (2<<23)) | ||
| 35 | |||
| 36 | #define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00300000) | ||
| 37 | #define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23)) | ||
| 38 | |||
| 39 | #define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000) | ||
| 40 | #define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23)) | ||
| 41 | |||
| 42 | #endif /* __ASM_ARCH_OSIRISMAP_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/otom-map.h b/include/asm-arm/arch-s3c2410/otom-map.h deleted file mode 100644 index e40c93429854..000000000000 --- a/include/asm-arm/arch-s3c2410/otom-map.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/otom-map.h | ||
| 2 | * | ||
| 3 | * (c) 2005 Guillaume GOURAT / NexVision | ||
| 4 | * guillaume.gourat@nexvision.fr | ||
| 5 | * | ||
| 6 | * NexVision OTOM board memory map definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* needs arch/map.h including with this */ | ||
| 14 | |||
| 15 | /* ok, we've used up to 0x01300000, now we need to find space for the | ||
| 16 | * peripherals that live in the nGCS[x] areas, which are quite numerous | ||
| 17 | * in their space. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARCH_OTOMMAP_H | ||
| 21 | #define __ASM_ARCH_OTOMMAP_H | ||
| 22 | |||
| 23 | #define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */ | ||
| 24 | #define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */ | ||
| 25 | |||
| 26 | /* physical offset addresses for the peripherals */ | ||
| 27 | |||
| 28 | #define OTOM_PA_FLASH0_BASE (S3C2410_CS0) /* Bank 0 */ | ||
| 29 | |||
| 30 | #endif /* __ASM_ARCH_OTOMMAP_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h deleted file mode 100644 index 37661358b42b..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ /dev/null | |||
| @@ -1,197 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-clock.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2410 clock register definitions | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARM_REGS_CLOCK | ||
| 14 | #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $" | ||
| 15 | |||
| 16 | #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) | ||
| 17 | |||
| 18 | #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s))) | ||
| 19 | |||
| 20 | #define S3C2410_LOCKTIME S3C2410_CLKREG(0x00) | ||
| 21 | #define S3C2410_MPLLCON S3C2410_CLKREG(0x04) | ||
| 22 | #define S3C2410_UPLLCON S3C2410_CLKREG(0x08) | ||
| 23 | #define S3C2410_CLKCON S3C2410_CLKREG(0x0C) | ||
| 24 | #define S3C2410_CLKSLOW S3C2410_CLKREG(0x10) | ||
| 25 | #define S3C2410_CLKDIVN S3C2410_CLKREG(0x14) | ||
| 26 | |||
| 27 | #define S3C2410_CLKCON_IDLE (1<<2) | ||
| 28 | #define S3C2410_CLKCON_POWER (1<<3) | ||
| 29 | #define S3C2410_CLKCON_NAND (1<<4) | ||
| 30 | #define S3C2410_CLKCON_LCDC (1<<5) | ||
| 31 | #define S3C2410_CLKCON_USBH (1<<6) | ||
| 32 | #define S3C2410_CLKCON_USBD (1<<7) | ||
| 33 | #define S3C2410_CLKCON_PWMT (1<<8) | ||
| 34 | #define S3C2410_CLKCON_SDI (1<<9) | ||
| 35 | #define S3C2410_CLKCON_UART0 (1<<10) | ||
| 36 | #define S3C2410_CLKCON_UART1 (1<<11) | ||
| 37 | #define S3C2410_CLKCON_UART2 (1<<12) | ||
| 38 | #define S3C2410_CLKCON_GPIO (1<<13) | ||
| 39 | #define S3C2410_CLKCON_RTC (1<<14) | ||
| 40 | #define S3C2410_CLKCON_ADC (1<<15) | ||
| 41 | #define S3C2410_CLKCON_IIC (1<<16) | ||
| 42 | #define S3C2410_CLKCON_IIS (1<<17) | ||
| 43 | #define S3C2410_CLKCON_SPI (1<<18) | ||
| 44 | |||
| 45 | #define S3C2410_PLLCON_MDIVSHIFT 12 | ||
| 46 | #define S3C2410_PLLCON_PDIVSHIFT 4 | ||
| 47 | #define S3C2410_PLLCON_SDIVSHIFT 0 | ||
| 48 | #define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) | ||
| 49 | #define S3C2410_PLLCON_PDIVMASK ((1<<5)-1) | ||
| 50 | #define S3C2410_PLLCON_SDIVMASK 3 | ||
| 51 | |||
| 52 | /* DCLKCON register addresses in gpio.h */ | ||
| 53 | |||
| 54 | #define S3C2410_DCLKCON_DCLK0EN (1<<0) | ||
| 55 | #define S3C2410_DCLKCON_DCLK0_PCLK (0<<1) | ||
| 56 | #define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) | ||
| 57 | #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) | ||
| 58 | #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) | ||
| 59 | #define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4) | ||
| 60 | #define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8) | ||
| 61 | |||
| 62 | #define S3C2410_DCLKCON_DCLK1EN (1<<16) | ||
| 63 | #define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) | ||
| 64 | #define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) | ||
| 65 | #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) | ||
| 66 | #define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24) | ||
| 67 | #define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20) | ||
| 68 | #define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24) | ||
| 69 | |||
| 70 | #define S3C2410_CLKDIVN_PDIVN (1<<0) | ||
| 71 | #define S3C2410_CLKDIVN_HDIVN (1<<1) | ||
| 72 | |||
| 73 | #define S3C2410_CLKSLOW_UCLK_OFF (1<<7) | ||
| 74 | #define S3C2410_CLKSLOW_MPLL_OFF (1<<5) | ||
| 75 | #define S3C2410_CLKSLOW_SLOW (1<<4) | ||
| 76 | #define S3C2410_CLKSLOW_SLOWVAL(x) (x) | ||
| 77 | #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) | ||
| 78 | |||
| 79 | #ifndef __ASSEMBLY__ | ||
| 80 | |||
| 81 | #include <asm/div64.h> | ||
| 82 | |||
| 83 | static inline unsigned int | ||
| 84 | s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) | ||
| 85 | { | ||
| 86 | unsigned int mdiv, pdiv, sdiv; | ||
| 87 | uint64_t fvco; | ||
| 88 | |||
| 89 | mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; | ||
| 90 | pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; | ||
| 91 | sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT; | ||
| 92 | |||
| 93 | mdiv &= S3C2410_PLLCON_MDIVMASK; | ||
| 94 | pdiv &= S3C2410_PLLCON_PDIVMASK; | ||
| 95 | sdiv &= S3C2410_PLLCON_SDIVMASK; | ||
| 96 | |||
| 97 | fvco = (uint64_t)baseclk * (mdiv + 8); | ||
| 98 | do_div(fvco, (pdiv + 2) << sdiv); | ||
| 99 | |||
| 100 | return (unsigned int)fvco; | ||
| 101 | } | ||
| 102 | |||
| 103 | #endif /* __ASSEMBLY__ */ | ||
| 104 | |||
| 105 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) | ||
| 106 | |||
| 107 | /* extra registers */ | ||
| 108 | #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) | ||
| 109 | |||
| 110 | #define S3C2440_CLKCON_CAMERA (1<<19) | ||
| 111 | #define S3C2440_CLKCON_AC97 (1<<20) | ||
| 112 | |||
| 113 | #define S3C2440_CLKDIVN_PDIVN (1<<0) | ||
| 114 | #define S3C2440_CLKDIVN_HDIVN_MASK (3<<1) | ||
| 115 | #define S3C2440_CLKDIVN_HDIVN_1 (0<<1) | ||
| 116 | #define S3C2440_CLKDIVN_HDIVN_2 (1<<1) | ||
| 117 | #define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1) | ||
| 118 | #define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1) | ||
| 119 | #define S3C2440_CLKDIVN_UCLK (1<<3) | ||
| 120 | |||
| 121 | #define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0) | ||
| 122 | #define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4) | ||
| 123 | #define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) | ||
| 124 | #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) | ||
| 125 | #define S3C2440_CAMDIVN_DVSEN (1<<12) | ||
| 126 | |||
| 127 | #define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) | ||
| 128 | |||
| 129 | #endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ | ||
| 130 | |||
| 131 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | ||
| 132 | |||
| 133 | #define S3C2412_OSCSET S3C2410_CLKREG(0x18) | ||
| 134 | #define S3C2412_CLKSRC S3C2410_CLKREG(0x1C) | ||
| 135 | |||
| 136 | #define S3C2412_PLLCON_OFF (1<<20) | ||
| 137 | |||
| 138 | #define S3C2412_CLKDIVN_PDIVN (1<<2) | ||
| 139 | #define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) | ||
| 140 | #define S3C2412_CLKDIVN_ARMDIVN (1<<3) | ||
| 141 | #define S3C2412_CLKDIVN_DVSEN (1<<4) | ||
| 142 | #define S3C2412_CLKDIVN_HALFHCLK (1<<5) | ||
| 143 | #define S3C2412_CLKDIVN_USB48DIV (1<<6) | ||
| 144 | #define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8) | ||
| 145 | #define S3C2412_CLKDIVN_UARTDIV_SHIFT (8) | ||
| 146 | #define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12) | ||
| 147 | #define S3C2412_CLKDIVN_I2SDIV_SHIFT (12) | ||
| 148 | #define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16) | ||
| 149 | #define S3C2412_CLKDIVN_CAMDIV_SHIFT (16) | ||
| 150 | |||
| 151 | #define S3C2412_CLKCON_WDT (1<<28) | ||
| 152 | #define S3C2412_CLKCON_SPI (1<<27) | ||
| 153 | #define S3C2412_CLKCON_IIS (1<<26) | ||
| 154 | #define S3C2412_CLKCON_IIC (1<<25) | ||
| 155 | #define S3C2412_CLKCON_ADC (1<<24) | ||
| 156 | #define S3C2412_CLKCON_RTC (1<<23) | ||
| 157 | #define S3C2412_CLKCON_GPIO (1<<22) | ||
| 158 | #define S3C2412_CLKCON_UART2 (1<<21) | ||
| 159 | #define S3C2412_CLKCON_UART1 (1<<20) | ||
| 160 | #define S3C2412_CLKCON_UART0 (1<<19) | ||
| 161 | #define S3C2412_CLKCON_SDI (1<<18) | ||
| 162 | #define S3C2412_CLKCON_PWMT (1<<17) | ||
| 163 | #define S3C2412_CLKCON_USBD (1<<16) | ||
| 164 | #define S3C2412_CLKCON_CAMCLK (1<<15) | ||
| 165 | #define S3C2412_CLKCON_UARTCLK (1<<14) | ||
| 166 | /* missing 13 */ | ||
| 167 | #define S3C2412_CLKCON_USB_HOST48 (1<<12) | ||
| 168 | #define S3C2412_CLKCON_USB_DEV48 (1<<11) | ||
| 169 | #define S3C2412_CLKCON_HCLKdiv2 (1<<10) | ||
| 170 | #define S3C2412_CLKCON_HCLKx2 (1<<9) | ||
| 171 | #define S3C2412_CLKCON_SDRAM (1<<8) | ||
| 172 | /* missing 7 */ | ||
| 173 | #define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH | ||
| 174 | #define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC | ||
| 175 | #define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND | ||
| 176 | #define S3C2412_CLKCON_DMA3 (1<<3) | ||
| 177 | #define S3C2412_CLKCON_DMA2 (1<<2) | ||
| 178 | #define S3C2412_CLKCON_DMA1 (1<<1) | ||
| 179 | #define S3C2412_CLKCON_DMA0 (1<<0) | ||
| 180 | |||
| 181 | /* clock sourec controls */ | ||
| 182 | |||
| 183 | #define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0) | ||
| 184 | #define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0) | ||
| 185 | #define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3) | ||
| 186 | #define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4) | ||
| 187 | #define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5) | ||
| 188 | #define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8) | ||
| 189 | #define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) | ||
| 190 | #define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) | ||
| 191 | #define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) | ||
| 192 | #define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12) | ||
| 193 | #define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14) | ||
| 194 | |||
| 195 | #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ | ||
| 196 | |||
| 197 | #endif /* __ASM_ARM_REGS_CLOCK */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h deleted file mode 100644 index 1235df70f34e..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-dsc.h +++ /dev/null | |||
| @@ -1,184 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-dsc.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2440/S3C2412 Signal Drive Strength Control | ||
| 11 | */ | ||
| 12 | |||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_REGS_DSC_H | ||
| 15 | #define __ASM_ARCH_REGS_DSC_H "2440-dsc" | ||
| 16 | |||
| 17 | #if defined(CONFIG_CPU_S3C2412) | ||
| 18 | #define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) | ||
| 19 | #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) | ||
| 20 | #endif | ||
| 21 | |||
| 22 | #if defined(CONFIG_CPU_S3C244X) | ||
| 23 | |||
| 24 | #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) | ||
| 25 | #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) | ||
| 26 | |||
| 27 | #define S3C2440_SELECT_DSC0 (0) | ||
| 28 | #define S3C2440_SELECT_DSC1 (1<<31) | ||
| 29 | |||
| 30 | #define S3C2440_DSC_GETSHIFT(x) ((x) & 31) | ||
| 31 | |||
| 32 | #define S3C2440_DSC0_DISABLE (1<<31) | ||
| 33 | |||
| 34 | #define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8) | ||
| 35 | #define S3C2440_DSC0_ADDR_12mA (0<<8) | ||
| 36 | #define S3C2440_DSC0_ADDR_10mA (1<<8) | ||
| 37 | #define S3C2440_DSC0_ADDR_8mA (2<<8) | ||
| 38 | #define S3C2440_DSC0_ADDR_6mA (3<<8) | ||
| 39 | #define S3C2440_DSC0_ADDR_MASK (3<<8) | ||
| 40 | |||
| 41 | /* D24..D31 */ | ||
| 42 | #define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6) | ||
| 43 | #define S3C2440_DSC0_DATA3_12mA (0<<6) | ||
| 44 | #define S3C2440_DSC0_DATA3_10mA (1<<6) | ||
| 45 | #define S3C2440_DSC0_DATA3_8mA (2<<6) | ||
| 46 | #define S3C2440_DSC0_DATA3_6mA (3<<6) | ||
| 47 | #define S3C2440_DSC0_DATA3_MASK (3<<6) | ||
| 48 | |||
| 49 | /* D16..D23 */ | ||
| 50 | #define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4) | ||
| 51 | #define S3C2440_DSC0_DATA2_12mA (0<<4) | ||
| 52 | #define S3C2440_DSC0_DATA2_10mA (1<<4) | ||
| 53 | #define S3C2440_DSC0_DATA2_8mA (2<<4) | ||
| 54 | #define S3C2440_DSC0_DATA2_6mA (3<<4) | ||
| 55 | #define S3C2440_DSC0_DATA2_MASK (3<<4) | ||
| 56 | |||
| 57 | /* D8..D15 */ | ||
| 58 | #define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2) | ||
| 59 | #define S3C2440_DSC0_DATA1_12mA (0<<2) | ||
| 60 | #define S3C2440_DSC0_DATA1_10mA (1<<2) | ||
| 61 | #define S3C2440_DSC0_DATA1_8mA (2<<2) | ||
| 62 | #define S3C2440_DSC0_DATA1_6mA (3<<2) | ||
| 63 | #define S3C2440_DSC0_DATA1_MASK (3<<2) | ||
| 64 | |||
| 65 | /* D0..D7 */ | ||
| 66 | #define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0) | ||
| 67 | #define S3C2440_DSC0_DATA0_12mA (0<<0) | ||
| 68 | #define S3C2440_DSC0_DATA0_10mA (1<<0) | ||
| 69 | #define S3C2440_DSC0_DATA0_8mA (2<<0) | ||
| 70 | #define S3C2440_DSC0_DATA0_6mA (3<<0) | ||
| 71 | #define S3C2440_DSC0_DATA0_MASK (3<<0) | ||
| 72 | |||
| 73 | #define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28) | ||
| 74 | #define S3C2440_DSC1_SCK1_12mA (0<<28) | ||
| 75 | #define S3C2440_DSC1_SCK1_10mA (1<<28) | ||
| 76 | #define S3C2440_DSC1_SCK1_8mA (2<<28) | ||
| 77 | #define S3C2440_DSC1_SCK1_6mA (3<<28) | ||
| 78 | #define S3C2440_DSC1_SCK1_MASK (3<<28) | ||
| 79 | |||
| 80 | #define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26) | ||
| 81 | #define S3C2440_DSC1_SCK0_12mA (0<<26) | ||
| 82 | #define S3C2440_DSC1_SCK0_10mA (1<<26) | ||
| 83 | #define S3C2440_DSC1_SCK0_8mA (2<<26) | ||
| 84 | #define S3C2440_DSC1_SCK0_6mA (3<<26) | ||
| 85 | #define S3C2440_DSC1_SCK0_MASK (3<<26) | ||
| 86 | |||
| 87 | #define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24) | ||
| 88 | #define S3C2440_DSC1_SCKE_10mA (0<<24) | ||
| 89 | #define S3C2440_DSC1_SCKE_8mA (1<<24) | ||
| 90 | #define S3C2440_DSC1_SCKE_6mA (2<<24) | ||
| 91 | #define S3C2440_DSC1_SCKE_4mA (3<<24) | ||
| 92 | #define S3C2440_DSC1_SCKE_MASK (3<<24) | ||
| 93 | |||
| 94 | /* SDRAM nRAS/nCAS */ | ||
| 95 | #define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22) | ||
| 96 | #define S3C2440_DSC1_SDR_10mA (0<<22) | ||
| 97 | #define S3C2440_DSC1_SDR_8mA (1<<22) | ||
| 98 | #define S3C2440_DSC1_SDR_6mA (2<<22) | ||
| 99 | #define S3C2440_DSC1_SDR_4mA (3<<22) | ||
| 100 | #define S3C2440_DSC1_SDR_MASK (3<<22) | ||
| 101 | |||
| 102 | /* NAND Flash Controller */ | ||
| 103 | #define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20) | ||
| 104 | #define S3C2440_DSC1_NFC_10mA (0<<20) | ||
| 105 | #define S3C2440_DSC1_NFC_8mA (1<<20) | ||
| 106 | #define S3C2440_DSC1_NFC_6mA (2<<20) | ||
| 107 | #define S3C2440_DSC1_NFC_4mA (3<<20) | ||
| 108 | #define S3C2440_DSC1_NFC_MASK (3<<20) | ||
| 109 | |||
| 110 | /* nBE[0..3] */ | ||
| 111 | #define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18) | ||
| 112 | #define S3C2440_DSC1_nBE_10mA (0<<18) | ||
| 113 | #define S3C2440_DSC1_nBE_8mA (1<<18) | ||
| 114 | #define S3C2440_DSC1_nBE_6mA (2<<18) | ||
| 115 | #define S3C2440_DSC1_nBE_4mA (3<<18) | ||
| 116 | #define S3C2440_DSC1_nBE_MASK (3<<18) | ||
| 117 | |||
| 118 | #define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16) | ||
| 119 | #define S3C2440_DSC1_WOE_10mA (0<<16) | ||
| 120 | #define S3C2440_DSC1_WOE_8mA (1<<16) | ||
| 121 | #define S3C2440_DSC1_WOE_6mA (2<<16) | ||
| 122 | #define S3C2440_DSC1_WOE_4mA (3<<16) | ||
| 123 | #define S3C2440_DSC1_WOE_MASK (3<<16) | ||
| 124 | |||
| 125 | #define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14) | ||
| 126 | #define S3C2440_DSC1_CS7_10mA (0<<14) | ||
| 127 | #define S3C2440_DSC1_CS7_8mA (1<<14) | ||
| 128 | #define S3C2440_DSC1_CS7_6mA (2<<14) | ||
| 129 | #define S3C2440_DSC1_CS7_4mA (3<<14) | ||
| 130 | #define S3C2440_DSC1_CS7_MASK (3<<14) | ||
| 131 | |||
| 132 | #define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12) | ||
| 133 | #define S3C2440_DSC1_CS6_10mA (0<<12) | ||
| 134 | #define S3C2440_DSC1_CS6_8mA (1<<12) | ||
| 135 | #define S3C2440_DSC1_CS6_6mA (2<<12) | ||
| 136 | #define S3C2440_DSC1_CS6_4mA (3<<12) | ||
| 137 | #define S3C2440_DSC1_CS6_MASK (3<<12) | ||
| 138 | |||
| 139 | #define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10) | ||
| 140 | #define S3C2440_DSC1_CS5_10mA (0<<10) | ||
| 141 | #define S3C2440_DSC1_CS5_8mA (1<<10) | ||
| 142 | #define S3C2440_DSC1_CS5_6mA (2<<10) | ||
| 143 | #define S3C2440_DSC1_CS5_4mA (3<<10) | ||
| 144 | #define S3C2440_DSC1_CS5_MASK (3<<10) | ||
| 145 | |||
| 146 | #define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8) | ||
| 147 | #define S3C2440_DSC1_CS4_10mA (0<<8) | ||
| 148 | #define S3C2440_DSC1_CS4_8mA (1<<8) | ||
| 149 | #define S3C2440_DSC1_CS4_6mA (2<<8) | ||
| 150 | #define S3C2440_DSC1_CS4_4mA (3<<8) | ||
| 151 | #define S3C2440_DSC1_CS4_MASK (3<<8) | ||
| 152 | |||
| 153 | #define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6) | ||
| 154 | #define S3C2440_DSC1_CS3_10mA (0<<6) | ||
| 155 | #define S3C2440_DSC1_CS3_8mA (1<<6) | ||
| 156 | #define S3C2440_DSC1_CS3_6mA (2<<6) | ||
| 157 | #define S3C2440_DSC1_CS3_4mA (3<<6) | ||
| 158 | #define S3C2440_DSC1_CS3_MASK (3<<6) | ||
| 159 | |||
| 160 | #define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4) | ||
| 161 | #define S3C2440_DSC1_CS2_10mA (0<<4) | ||
| 162 | #define S3C2440_DSC1_CS2_8mA (1<<4) | ||
| 163 | #define S3C2440_DSC1_CS2_6mA (2<<4) | ||
| 164 | #define S3C2440_DSC1_CS2_4mA (3<<4) | ||
| 165 | #define S3C2440_DSC1_CS2_MASK (3<<4) | ||
| 166 | |||
| 167 | #define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2) | ||
| 168 | #define S3C2440_DSC1_CS1_10mA (0<<2) | ||
| 169 | #define S3C2440_DSC1_CS1_8mA (1<<2) | ||
| 170 | #define S3C2440_DSC1_CS1_6mA (2<<2) | ||
| 171 | #define S3C2440_DSC1_CS1_4mA (3<<2) | ||
| 172 | #define S3C2440_DSC1_CS1_MASK (3<<2) | ||
| 173 | |||
| 174 | #define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0) | ||
| 175 | #define S3C2440_DSC1_CS0_10mA (0<<0) | ||
| 176 | #define S3C2440_DSC1_CS0_8mA (1<<0) | ||
| 177 | #define S3C2440_DSC1_CS0_6mA (2<<0) | ||
| 178 | #define S3C2440_DSC1_CS0_4mA (3<<0) | ||
| 179 | #define S3C2440_DSC1_CS0_MASK (3<<0) | ||
| 180 | |||
| 181 | #endif /* CONFIG_CPU_S3C2440 */ | ||
| 182 | |||
| 183 | #endif /* __ASM_ARCH_REGS_DSC_H */ | ||
| 184 | |||
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h deleted file mode 100644 index 497dd06e2c99..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ /dev/null | |||
| @@ -1,1163 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-gpio.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2410 GPIO register definitions | ||
| 11 | */ | ||
| 12 | |||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_REGS_GPIO_H | ||
| 15 | #define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $" | ||
| 16 | |||
| 17 | #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) | ||
| 18 | |||
| 19 | #define S3C2410_GPIO_BANKA (32*0) | ||
| 20 | #define S3C2410_GPIO_BANKB (32*1) | ||
| 21 | #define S3C2410_GPIO_BANKC (32*2) | ||
| 22 | #define S3C2410_GPIO_BANKD (32*3) | ||
| 23 | #define S3C2410_GPIO_BANKE (32*4) | ||
| 24 | #define S3C2410_GPIO_BANKF (32*5) | ||
| 25 | #define S3C2410_GPIO_BANKG (32*6) | ||
| 26 | #define S3C2410_GPIO_BANKH (32*7) | ||
| 27 | |||
| 28 | #ifdef CONFIG_CPU_S3C2400 | ||
| 29 | #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) | ||
| 30 | #define S3C24XX_MISCCR S3C2400_MISCCR | ||
| 31 | #else | ||
| 32 | #define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) | ||
| 33 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) | ||
| 34 | #endif /* CONFIG_CPU_S3C2400 */ | ||
| 35 | |||
| 36 | |||
| 37 | /* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */ | ||
| 38 | |||
| 39 | #define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32) | ||
| 40 | #define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2)) | ||
| 41 | #define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \ | ||
| 42 | (2 * (S3C2400_BANKNUM(pin)-2))) | ||
| 43 | |||
| 44 | #define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \ | ||
| 45 | S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \ | ||
| 46 | S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO) | ||
| 47 | |||
| 48 | |||
| 49 | #define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO) | ||
| 50 | #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31) | ||
| 51 | |||
| 52 | /* general configuration options */ | ||
| 53 | |||
| 54 | #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) | ||
| 55 | #define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ | ||
| 56 | #define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) | ||
| 57 | #define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ | ||
| 58 | #define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ | ||
| 59 | #define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ | ||
| 60 | |||
| 61 | /* register address for the GPIO registers. | ||
| 62 | * S3C24XX_GPIOREG2 is for the second set of registers in the | ||
| 63 | * GPIO which move between s3c2410 and s3c2412 type systems */ | ||
| 64 | |||
| 65 | #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) | ||
| 66 | #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) | ||
| 67 | |||
| 68 | |||
| 69 | /* configure GPIO ports A..G */ | ||
| 70 | |||
| 71 | /* port A - S3C2410: 22bits, zero in bit X makes pin X output | ||
| 72 | * S3C2400: 18bits, zero in bit X makes pin X output | ||
| 73 | * 1 makes port special function, this is default | ||
| 74 | */ | ||
| 75 | #define S3C2410_GPACON S3C2410_GPIOREG(0x00) | ||
| 76 | #define S3C2410_GPADAT S3C2410_GPIOREG(0x04) | ||
| 77 | |||
| 78 | #define S3C2400_GPACON S3C2410_GPIOREG(0x00) | ||
| 79 | #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) | ||
| 80 | |||
| 81 | #define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) | ||
| 82 | #define S3C2410_GPA0_OUT (0<<0) | ||
| 83 | #define S3C2410_GPA0_ADDR0 (1<<0) | ||
| 84 | |||
| 85 | #define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1) | ||
| 86 | #define S3C2410_GPA1_OUT (0<<1) | ||
| 87 | #define S3C2410_GPA1_ADDR16 (1<<1) | ||
| 88 | |||
| 89 | #define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2) | ||
| 90 | #define S3C2410_GPA2_OUT (0<<2) | ||
| 91 | #define S3C2410_GPA2_ADDR17 (1<<2) | ||
| 92 | |||
| 93 | #define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3) | ||
| 94 | #define S3C2410_GPA3_OUT (0<<3) | ||
| 95 | #define S3C2410_GPA3_ADDR18 (1<<3) | ||
| 96 | |||
| 97 | #define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4) | ||
| 98 | #define S3C2410_GPA4_OUT (0<<4) | ||
| 99 | #define S3C2410_GPA4_ADDR19 (1<<4) | ||
| 100 | |||
| 101 | #define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5) | ||
| 102 | #define S3C2410_GPA5_OUT (0<<5) | ||
| 103 | #define S3C2410_GPA5_ADDR20 (1<<5) | ||
| 104 | |||
| 105 | #define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6) | ||
| 106 | #define S3C2410_GPA6_OUT (0<<6) | ||
| 107 | #define S3C2410_GPA6_ADDR21 (1<<6) | ||
| 108 | |||
| 109 | #define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7) | ||
| 110 | #define S3C2410_GPA7_OUT (0<<7) | ||
| 111 | #define S3C2410_GPA7_ADDR22 (1<<7) | ||
| 112 | |||
| 113 | #define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8) | ||
| 114 | #define S3C2410_GPA8_OUT (0<<8) | ||
| 115 | #define S3C2410_GPA8_ADDR23 (1<<8) | ||
| 116 | |||
| 117 | #define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9) | ||
| 118 | #define S3C2410_GPA9_OUT (0<<9) | ||
| 119 | #define S3C2410_GPA9_ADDR24 (1<<9) | ||
| 120 | |||
| 121 | #define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) | ||
| 122 | #define S3C2410_GPA10_OUT (0<<10) | ||
| 123 | #define S3C2410_GPA10_ADDR25 (1<<10) | ||
| 124 | #define S3C2400_GPA10_SCKE (1<<10) | ||
| 125 | |||
| 126 | #define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) | ||
| 127 | #define S3C2410_GPA11_OUT (0<<11) | ||
| 128 | #define S3C2410_GPA11_ADDR26 (1<<11) | ||
| 129 | #define S3C2400_GPA11_nCAS0 (1<<11) | ||
| 130 | |||
| 131 | #define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) | ||
| 132 | #define S3C2410_GPA12_OUT (0<<12) | ||
| 133 | #define S3C2410_GPA12_nGCS1 (1<<12) | ||
| 134 | #define S3C2400_GPA12_nCAS1 (1<<12) | ||
| 135 | |||
| 136 | #define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) | ||
| 137 | #define S3C2410_GPA13_OUT (0<<13) | ||
| 138 | #define S3C2410_GPA13_nGCS2 (1<<13) | ||
| 139 | #define S3C2400_GPA13_nGCS1 (1<<13) | ||
| 140 | |||
| 141 | #define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) | ||
| 142 | #define S3C2410_GPA14_OUT (0<<14) | ||
| 143 | #define S3C2410_GPA14_nGCS3 (1<<14) | ||
| 144 | #define S3C2400_GPA14_nGCS2 (1<<14) | ||
| 145 | |||
| 146 | #define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) | ||
| 147 | #define S3C2410_GPA15_OUT (0<<15) | ||
| 148 | #define S3C2410_GPA15_nGCS4 (1<<15) | ||
| 149 | #define S3C2400_GPA15_nGCS3 (1<<15) | ||
| 150 | |||
| 151 | #define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) | ||
| 152 | #define S3C2410_GPA16_OUT (0<<16) | ||
| 153 | #define S3C2410_GPA16_nGCS5 (1<<16) | ||
| 154 | #define S3C2400_GPA16_nGCS4 (1<<16) | ||
| 155 | |||
| 156 | #define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) | ||
| 157 | #define S3C2410_GPA17_OUT (0<<17) | ||
| 158 | #define S3C2410_GPA17_CLE (1<<17) | ||
| 159 | #define S3C2400_GPA17_nGCS5 (1<<17) | ||
| 160 | |||
| 161 | #define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) | ||
| 162 | #define S3C2410_GPA18_OUT (0<<18) | ||
| 163 | #define S3C2410_GPA18_ALE (1<<18) | ||
| 164 | |||
| 165 | #define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19) | ||
| 166 | #define S3C2410_GPA19_OUT (0<<19) | ||
| 167 | #define S3C2410_GPA19_nFWE (1<<19) | ||
| 168 | |||
| 169 | #define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20) | ||
| 170 | #define S3C2410_GPA20_OUT (0<<20) | ||
| 171 | #define S3C2410_GPA20_nFRE (1<<20) | ||
| 172 | |||
| 173 | #define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21) | ||
| 174 | #define S3C2410_GPA21_OUT (0<<21) | ||
| 175 | #define S3C2410_GPA21_nRSTOUT (1<<21) | ||
| 176 | |||
| 177 | #define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22) | ||
| 178 | #define S3C2410_GPA22_OUT (0<<22) | ||
| 179 | #define S3C2410_GPA22_nFCE (1<<22) | ||
| 180 | |||
| 181 | /* 0x08 and 0x0c are reserved on S3C2410 */ | ||
| 182 | |||
| 183 | /* S3C2410: | ||
| 184 | * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. | ||
| 185 | * 00 = input, 01 = output, 10=special function, 11=reserved | ||
| 186 | |||
| 187 | * S3C2400: | ||
| 188 | * GPB is 16 IO pins, each configured by 2 bits each in GPBCON. | ||
| 189 | * 00 = input, 01 = output, 10=data, 11=special function | ||
| 190 | |||
| 191 | * bit 0,1 = pin 0, 2,3= pin 1... | ||
| 192 | * | ||
| 193 | * CPBUP = pull up resistor control, 1=disabled, 0=enabled | ||
| 194 | */ | ||
| 195 | |||
| 196 | #define S3C2410_GPBCON S3C2410_GPIOREG(0x10) | ||
| 197 | #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) | ||
| 198 | #define S3C2410_GPBUP S3C2410_GPIOREG(0x18) | ||
| 199 | |||
| 200 | #define S3C2400_GPBCON S3C2410_GPIOREG(0x08) | ||
| 201 | #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) | ||
| 202 | #define S3C2400_GPBUP S3C2410_GPIOREG(0x10) | ||
| 203 | |||
| 204 | /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ | ||
| 205 | |||
| 206 | #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) | ||
| 207 | #define S3C2410_GPB0_INP (0x00 << 0) | ||
| 208 | #define S3C2410_GPB0_OUTP (0x01 << 0) | ||
| 209 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) | ||
| 210 | #define S3C2400_GPB0_DATA16 (0x02 << 0) | ||
| 211 | |||
| 212 | #define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) | ||
| 213 | #define S3C2410_GPB1_INP (0x00 << 2) | ||
| 214 | #define S3C2410_GPB1_OUTP (0x01 << 2) | ||
| 215 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) | ||
| 216 | #define S3C2400_GPB1_DATA17 (0x02 << 2) | ||
| 217 | |||
| 218 | #define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) | ||
| 219 | #define S3C2410_GPB2_INP (0x00 << 4) | ||
| 220 | #define S3C2410_GPB2_OUTP (0x01 << 4) | ||
| 221 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) | ||
| 222 | #define S3C2400_GPB2_DATA18 (0x02 << 4) | ||
| 223 | #define S3C2400_GPB2_TCLK1 (0x03 << 4) | ||
| 224 | |||
| 225 | #define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) | ||
| 226 | #define S3C2410_GPB3_INP (0x00 << 6) | ||
| 227 | #define S3C2410_GPB3_OUTP (0x01 << 6) | ||
| 228 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) | ||
| 229 | #define S3C2400_GPB3_DATA19 (0x02 << 6) | ||
| 230 | #define S3C2400_GPB3_TXD1 (0x03 << 6) | ||
| 231 | |||
| 232 | #define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) | ||
| 233 | #define S3C2410_GPB4_INP (0x00 << 8) | ||
| 234 | #define S3C2410_GPB4_OUTP (0x01 << 8) | ||
| 235 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) | ||
| 236 | #define S3C2400_GPB4_DATA20 (0x02 << 8) | ||
| 237 | #define S3C2410_GPB4_MASK (0x03 << 8) | ||
| 238 | #define S3C2400_GPB4_RXD1 (0x03 << 8) | ||
| 239 | #define S3C2400_GPB4_MASK (0x03 << 8) | ||
| 240 | |||
| 241 | #define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) | ||
| 242 | #define S3C2410_GPB5_INP (0x00 << 10) | ||
| 243 | #define S3C2410_GPB5_OUTP (0x01 << 10) | ||
| 244 | #define S3C2410_GPB5_nXBACK (0x02 << 10) | ||
| 245 | #define S3C2443_GPB5_XBACK (0x03 << 10) | ||
| 246 | #define S3C2400_GPB5_DATA21 (0x02 << 10) | ||
| 247 | #define S3C2400_GPB5_nCTS1 (0x03 << 10) | ||
| 248 | |||
| 249 | #define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) | ||
| 250 | #define S3C2410_GPB6_INP (0x00 << 12) | ||
| 251 | #define S3C2410_GPB6_OUTP (0x01 << 12) | ||
| 252 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) | ||
| 253 | #define S3C2443_GPB6_XBREQ (0x03 << 12) | ||
| 254 | #define S3C2400_GPB6_DATA22 (0x02 << 12) | ||
| 255 | #define S3C2400_GPB6_nRTS1 (0x03 << 12) | ||
| 256 | |||
| 257 | #define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) | ||
| 258 | #define S3C2410_GPB7_INP (0x00 << 14) | ||
| 259 | #define S3C2410_GPB7_OUTP (0x01 << 14) | ||
| 260 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) | ||
| 261 | #define S3C2443_GPB7_XDACK1 (0x03 << 14) | ||
| 262 | #define S3C2400_GPB7_DATA23 (0x02 << 14) | ||
| 263 | |||
| 264 | #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) | ||
| 265 | #define S3C2410_GPB8_INP (0x00 << 16) | ||
| 266 | #define S3C2410_GPB8_OUTP (0x01 << 16) | ||
| 267 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) | ||
| 268 | #define S3C2400_GPB8_DATA24 (0x02 << 16) | ||
| 269 | |||
| 270 | #define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) | ||
| 271 | #define S3C2410_GPB9_INP (0x00 << 18) | ||
| 272 | #define S3C2410_GPB9_OUTP (0x01 << 18) | ||
| 273 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) | ||
| 274 | #define S3C2443_GPB9_XDACK0 (0x03 << 18) | ||
| 275 | #define S3C2400_GPB9_DATA25 (0x02 << 18) | ||
| 276 | #define S3C2400_GPB9_I2SSDI (0x03 << 18) | ||
| 277 | |||
| 278 | #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) | ||
| 279 | #define S3C2410_GPB10_INP (0x00 << 20) | ||
| 280 | #define S3C2410_GPB10_OUTP (0x01 << 20) | ||
| 281 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) | ||
| 282 | #define S3C2443_GPB10_XDREQ0 (0x03 << 20) | ||
| 283 | #define S3C2400_GPB10_DATA26 (0x02 << 20) | ||
| 284 | #define S3C2400_GPB10_nSS (0x03 << 20) | ||
| 285 | |||
| 286 | #define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11) | ||
| 287 | #define S3C2400_GPB11_INP (0x00 << 22) | ||
| 288 | #define S3C2400_GPB11_OUTP (0x01 << 22) | ||
| 289 | #define S3C2400_GPB11_DATA27 (0x02 << 22) | ||
| 290 | |||
| 291 | #define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12) | ||
| 292 | #define S3C2400_GPB12_INP (0x00 << 24) | ||
| 293 | #define S3C2400_GPB12_OUTP (0x01 << 24) | ||
| 294 | #define S3C2400_GPB12_DATA28 (0x02 << 24) | ||
| 295 | |||
| 296 | #define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13) | ||
| 297 | #define S3C2400_GPB13_INP (0x00 << 26) | ||
| 298 | #define S3C2400_GPB13_OUTP (0x01 << 26) | ||
| 299 | #define S3C2400_GPB13_DATA29 (0x02 << 26) | ||
| 300 | |||
| 301 | #define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14) | ||
| 302 | #define S3C2400_GPB14_INP (0x00 << 28) | ||
| 303 | #define S3C2400_GPB14_OUTP (0x01 << 28) | ||
| 304 | #define S3C2400_GPB14_DATA30 (0x02 << 28) | ||
| 305 | |||
| 306 | #define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15) | ||
| 307 | #define S3C2400_GPB15_INP (0x00 << 30) | ||
| 308 | #define S3C2400_GPB15_OUTP (0x01 << 30) | ||
| 309 | #define S3C2400_GPB15_DATA31 (0x02 << 30) | ||
| 310 | |||
| 311 | #define S3C2410_GPB_PUPDIS(x) (1<<(x)) | ||
| 312 | |||
| 313 | /* Port C consits of 16 GPIO/Special function | ||
| 314 | * | ||
| 315 | * almost identical setup to port b, but the special functions are mostly | ||
| 316 | * to do with the video system's sync/etc. | ||
| 317 | */ | ||
| 318 | |||
| 319 | #define S3C2410_GPCCON S3C2410_GPIOREG(0x20) | ||
| 320 | #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) | ||
| 321 | #define S3C2410_GPCUP S3C2410_GPIOREG(0x28) | ||
| 322 | |||
| 323 | #define S3C2400_GPCCON S3C2410_GPIOREG(0x14) | ||
| 324 | #define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) | ||
| 325 | #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) | ||
| 326 | |||
| 327 | #define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) | ||
| 328 | #define S3C2410_GPC0_INP (0x00 << 0) | ||
| 329 | #define S3C2410_GPC0_OUTP (0x01 << 0) | ||
| 330 | #define S3C2410_GPC0_LEND (0x02 << 0) | ||
| 331 | #define S3C2400_GPC0_VD0 (0x02 << 0) | ||
| 332 | |||
| 333 | #define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) | ||
| 334 | #define S3C2410_GPC1_INP (0x00 << 2) | ||
| 335 | #define S3C2410_GPC1_OUTP (0x01 << 2) | ||
| 336 | #define S3C2410_GPC1_VCLK (0x02 << 2) | ||
| 337 | #define S3C2400_GPC1_VD1 (0x02 << 2) | ||
| 338 | |||
| 339 | #define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) | ||
| 340 | #define S3C2410_GPC2_INP (0x00 << 4) | ||
| 341 | #define S3C2410_GPC2_OUTP (0x01 << 4) | ||
| 342 | #define S3C2410_GPC2_VLINE (0x02 << 4) | ||
| 343 | #define S3C2400_GPC2_VD2 (0x02 << 4) | ||
| 344 | |||
| 345 | #define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) | ||
| 346 | #define S3C2410_GPC3_INP (0x00 << 6) | ||
| 347 | #define S3C2410_GPC3_OUTP (0x01 << 6) | ||
| 348 | #define S3C2410_GPC3_VFRAME (0x02 << 6) | ||
| 349 | #define S3C2400_GPC3_VD3 (0x02 << 6) | ||
| 350 | |||
| 351 | #define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) | ||
| 352 | #define S3C2410_GPC4_INP (0x00 << 8) | ||
| 353 | #define S3C2410_GPC4_OUTP (0x01 << 8) | ||
| 354 | #define S3C2410_GPC4_VM (0x02 << 8) | ||
| 355 | #define S3C2400_GPC4_VD4 (0x02 << 8) | ||
| 356 | |||
| 357 | #define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) | ||
| 358 | #define S3C2410_GPC5_INP (0x00 << 10) | ||
| 359 | #define S3C2410_GPC5_OUTP (0x01 << 10) | ||
| 360 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) | ||
| 361 | #define S3C2400_GPC5_VD5 (0x02 << 10) | ||
| 362 | |||
| 363 | #define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) | ||
| 364 | #define S3C2410_GPC6_INP (0x00 << 12) | ||
| 365 | #define S3C2410_GPC6_OUTP (0x01 << 12) | ||
| 366 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) | ||
| 367 | #define S3C2400_GPC6_VD6 (0x02 << 12) | ||
| 368 | |||
| 369 | #define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) | ||
| 370 | #define S3C2410_GPC7_INP (0x00 << 14) | ||
| 371 | #define S3C2410_GPC7_OUTP (0x01 << 14) | ||
| 372 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) | ||
| 373 | #define S3C2400_GPC7_VD7 (0x02 << 14) | ||
| 374 | |||
| 375 | #define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) | ||
| 376 | #define S3C2410_GPC8_INP (0x00 << 16) | ||
| 377 | #define S3C2410_GPC8_OUTP (0x01 << 16) | ||
| 378 | #define S3C2410_GPC8_VD0 (0x02 << 16) | ||
| 379 | #define S3C2400_GPC8_VD8 (0x02 << 16) | ||
| 380 | |||
| 381 | #define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) | ||
| 382 | #define S3C2410_GPC9_INP (0x00 << 18) | ||
| 383 | #define S3C2410_GPC9_OUTP (0x01 << 18) | ||
| 384 | #define S3C2410_GPC9_VD1 (0x02 << 18) | ||
| 385 | #define S3C2400_GPC9_VD9 (0x02 << 18) | ||
| 386 | |||
| 387 | #define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) | ||
| 388 | #define S3C2410_GPC10_INP (0x00 << 20) | ||
| 389 | #define S3C2410_GPC10_OUTP (0x01 << 20) | ||
| 390 | #define S3C2410_GPC10_VD2 (0x02 << 20) | ||
| 391 | #define S3C2400_GPC10_VD10 (0x02 << 20) | ||
| 392 | |||
| 393 | #define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) | ||
| 394 | #define S3C2410_GPC11_INP (0x00 << 22) | ||
| 395 | #define S3C2410_GPC11_OUTP (0x01 << 22) | ||
| 396 | #define S3C2410_GPC11_VD3 (0x02 << 22) | ||
| 397 | #define S3C2400_GPC11_VD11 (0x02 << 22) | ||
| 398 | |||
| 399 | #define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) | ||
| 400 | #define S3C2410_GPC12_INP (0x00 << 24) | ||
| 401 | #define S3C2410_GPC12_OUTP (0x01 << 24) | ||
| 402 | #define S3C2410_GPC12_VD4 (0x02 << 24) | ||
| 403 | #define S3C2400_GPC12_VD12 (0x02 << 24) | ||
| 404 | |||
| 405 | #define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) | ||
| 406 | #define S3C2410_GPC13_INP (0x00 << 26) | ||
| 407 | #define S3C2410_GPC13_OUTP (0x01 << 26) | ||
| 408 | #define S3C2410_GPC13_VD5 (0x02 << 26) | ||
| 409 | #define S3C2400_GPC13_VD13 (0x02 << 26) | ||
| 410 | |||
| 411 | #define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) | ||
| 412 | #define S3C2410_GPC14_INP (0x00 << 28) | ||
| 413 | #define S3C2410_GPC14_OUTP (0x01 << 28) | ||
| 414 | #define S3C2410_GPC14_VD6 (0x02 << 28) | ||
| 415 | #define S3C2400_GPC14_VD14 (0x02 << 28) | ||
| 416 | |||
| 417 | #define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) | ||
| 418 | #define S3C2410_GPC15_INP (0x00 << 30) | ||
| 419 | #define S3C2410_GPC15_OUTP (0x01 << 30) | ||
| 420 | #define S3C2410_GPC15_VD7 (0x02 << 30) | ||
| 421 | #define S3C2400_GPC15_VD15 (0x02 << 30) | ||
| 422 | |||
| 423 | #define S3C2410_GPC_PUPDIS(x) (1<<(x)) | ||
| 424 | |||
| 425 | /* | ||
| 426 | * S3C2410: Port D consists of 16 GPIO/Special function | ||
| 427 | * | ||
| 428 | * almost identical setup to port b, but the special functions are mostly | ||
| 429 | * to do with the video system's data. | ||
| 430 | * | ||
| 431 | * S3C2400: Port D consists of 11 GPIO/Special function | ||
| 432 | * | ||
| 433 | * almost identical setup to port c | ||
| 434 | */ | ||
| 435 | |||
| 436 | #define S3C2410_GPDCON S3C2410_GPIOREG(0x30) | ||
| 437 | #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) | ||
| 438 | #define S3C2410_GPDUP S3C2410_GPIOREG(0x38) | ||
| 439 | |||
| 440 | #define S3C2400_GPDCON S3C2410_GPIOREG(0x20) | ||
| 441 | #define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) | ||
| 442 | #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) | ||
| 443 | |||
| 444 | #define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) | ||
| 445 | #define S3C2410_GPD0_INP (0x00 << 0) | ||
| 446 | #define S3C2410_GPD0_OUTP (0x01 << 0) | ||
| 447 | #define S3C2410_GPD0_VD8 (0x02 << 0) | ||
| 448 | #define S3C2400_GPD0_VFRAME (0x02 << 0) | ||
| 449 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) | ||
| 450 | |||
| 451 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) | ||
| 452 | #define S3C2410_GPD1_INP (0x00 << 2) | ||
| 453 | #define S3C2410_GPD1_OUTP (0x01 << 2) | ||
| 454 | #define S3C2410_GPD1_VD9 (0x02 << 2) | ||
| 455 | #define S3C2400_GPD1_VM (0x02 << 2) | ||
| 456 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) | ||
| 457 | |||
| 458 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) | ||
| 459 | #define S3C2410_GPD2_INP (0x00 << 4) | ||
| 460 | #define S3C2410_GPD2_OUTP (0x01 << 4) | ||
| 461 | #define S3C2410_GPD2_VD10 (0x02 << 4) | ||
| 462 | #define S3C2400_GPD2_VLINE (0x02 << 4) | ||
| 463 | |||
| 464 | #define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) | ||
| 465 | #define S3C2410_GPD3_INP (0x00 << 6) | ||
| 466 | #define S3C2410_GPD3_OUTP (0x01 << 6) | ||
| 467 | #define S3C2410_GPD3_VD11 (0x02 << 6) | ||
| 468 | #define S3C2400_GPD3_VCLK (0x02 << 6) | ||
| 469 | |||
| 470 | #define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) | ||
| 471 | #define S3C2410_GPD4_INP (0x00 << 8) | ||
| 472 | #define S3C2410_GPD4_OUTP (0x01 << 8) | ||
| 473 | #define S3C2410_GPD4_VD12 (0x02 << 8) | ||
| 474 | #define S3C2400_GPD4_LEND (0x02 << 8) | ||
| 475 | |||
| 476 | #define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) | ||
| 477 | #define S3C2410_GPD5_INP (0x00 << 10) | ||
| 478 | #define S3C2410_GPD5_OUTP (0x01 << 10) | ||
| 479 | #define S3C2410_GPD5_VD13 (0x02 << 10) | ||
| 480 | #define S3C2400_GPD5_TOUT0 (0x02 << 10) | ||
| 481 | |||
| 482 | #define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) | ||
| 483 | #define S3C2410_GPD6_INP (0x00 << 12) | ||
| 484 | #define S3C2410_GPD6_OUTP (0x01 << 12) | ||
| 485 | #define S3C2410_GPD6_VD14 (0x02 << 12) | ||
| 486 | #define S3C2400_GPD6_TOUT1 (0x02 << 12) | ||
| 487 | |||
| 488 | #define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) | ||
| 489 | #define S3C2410_GPD7_INP (0x00 << 14) | ||
| 490 | #define S3C2410_GPD7_OUTP (0x01 << 14) | ||
| 491 | #define S3C2410_GPD7_VD15 (0x02 << 14) | ||
| 492 | #define S3C2400_GPD7_TOUT2 (0x02 << 14) | ||
| 493 | |||
| 494 | #define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) | ||
| 495 | #define S3C2410_GPD8_INP (0x00 << 16) | ||
| 496 | #define S3C2410_GPD8_OUTP (0x01 << 16) | ||
| 497 | #define S3C2410_GPD8_VD16 (0x02 << 16) | ||
| 498 | #define S3C2400_GPD8_TOUT3 (0x02 << 16) | ||
| 499 | |||
| 500 | #define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) | ||
| 501 | #define S3C2410_GPD9_INP (0x00 << 18) | ||
| 502 | #define S3C2410_GPD9_OUTP (0x01 << 18) | ||
| 503 | #define S3C2410_GPD9_VD17 (0x02 << 18) | ||
| 504 | #define S3C2400_GPD9_TCLK0 (0x02 << 18) | ||
| 505 | #define S3C2410_GPD9_MASK (0x03 << 18) | ||
| 506 | |||
| 507 | #define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) | ||
| 508 | #define S3C2410_GPD10_INP (0x00 << 20) | ||
| 509 | #define S3C2410_GPD10_OUTP (0x01 << 20) | ||
| 510 | #define S3C2410_GPD10_VD18 (0x02 << 20) | ||
| 511 | #define S3C2400_GPD10_nWAIT (0x02 << 20) | ||
| 512 | |||
| 513 | #define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) | ||
| 514 | #define S3C2410_GPD11_INP (0x00 << 22) | ||
| 515 | #define S3C2410_GPD11_OUTP (0x01 << 22) | ||
| 516 | #define S3C2410_GPD11_VD19 (0x02 << 22) | ||
| 517 | |||
| 518 | #define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12) | ||
| 519 | #define S3C2410_GPD12_INP (0x00 << 24) | ||
| 520 | #define S3C2410_GPD12_OUTP (0x01 << 24) | ||
| 521 | #define S3C2410_GPD12_VD20 (0x02 << 24) | ||
| 522 | |||
| 523 | #define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13) | ||
| 524 | #define S3C2410_GPD13_INP (0x00 << 26) | ||
| 525 | #define S3C2410_GPD13_OUTP (0x01 << 26) | ||
| 526 | #define S3C2410_GPD13_VD21 (0x02 << 26) | ||
| 527 | |||
| 528 | #define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14) | ||
| 529 | #define S3C2410_GPD14_INP (0x00 << 28) | ||
| 530 | #define S3C2410_GPD14_OUTP (0x01 << 28) | ||
| 531 | #define S3C2410_GPD14_VD22 (0x02 << 28) | ||
| 532 | #define S3C2410_GPD14_nSS1 (0x03 << 28) | ||
| 533 | |||
| 534 | #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) | ||
| 535 | #define S3C2410_GPD15_INP (0x00 << 30) | ||
| 536 | #define S3C2410_GPD15_OUTP (0x01 << 30) | ||
| 537 | #define S3C2410_GPD15_VD23 (0x02 << 30) | ||
| 538 | #define S3C2410_GPD15_nSS0 (0x03 << 30) | ||
| 539 | |||
| 540 | #define S3C2410_GPD_PUPDIS(x) (1<<(x)) | ||
| 541 | |||
| 542 | /* S3C2410: | ||
| 543 | * Port E consists of 16 GPIO/Special function | ||
| 544 | * | ||
| 545 | * again, the same as port B, but dealing with I2S, SDI, and | ||
| 546 | * more miscellaneous functions | ||
| 547 | * | ||
| 548 | * S3C2400: | ||
| 549 | * Port E consists of 12 GPIO/Special function | ||
| 550 | * | ||
| 551 | * GPIO / interrupt inputs | ||
| 552 | */ | ||
| 553 | |||
| 554 | #define S3C2410_GPECON S3C2410_GPIOREG(0x40) | ||
| 555 | #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) | ||
| 556 | #define S3C2410_GPEUP S3C2410_GPIOREG(0x48) | ||
| 557 | |||
| 558 | #define S3C2400_GPECON S3C2410_GPIOREG(0x2C) | ||
| 559 | #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) | ||
| 560 | #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) | ||
| 561 | |||
| 562 | #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) | ||
| 563 | #define S3C2410_GPE0_INP (0x00 << 0) | ||
| 564 | #define S3C2410_GPE0_OUTP (0x01 << 0) | ||
| 565 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) | ||
| 566 | #define S3C2443_GPE0_AC_nRESET (0x03 << 0) | ||
| 567 | #define S3C2400_GPE0_EINT0 (0x02 << 0) | ||
| 568 | #define S3C2410_GPE0_MASK (0x03 << 0) | ||
| 569 | |||
| 570 | #define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) | ||
| 571 | #define S3C2410_GPE1_INP (0x00 << 2) | ||
| 572 | #define S3C2410_GPE1_OUTP (0x01 << 2) | ||
| 573 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) | ||
| 574 | #define S3C2443_GPE1_AC_SYNC (0x03 << 2) | ||
| 575 | #define S3C2400_GPE1_EINT1 (0x02 << 2) | ||
| 576 | #define S3C2400_GPE1_nSS (0x03 << 2) | ||
| 577 | #define S3C2410_GPE1_MASK (0x03 << 2) | ||
| 578 | |||
| 579 | #define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) | ||
| 580 | #define S3C2410_GPE2_INP (0x00 << 4) | ||
| 581 | #define S3C2410_GPE2_OUTP (0x01 << 4) | ||
| 582 | #define S3C2410_GPE2_CDCLK (0x02 << 4) | ||
| 583 | #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) | ||
| 584 | #define S3C2400_GPE2_EINT2 (0x02 << 4) | ||
| 585 | #define S3C2400_GPE2_I2SSDI (0x03 << 4) | ||
| 586 | |||
| 587 | #define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) | ||
| 588 | #define S3C2410_GPE3_INP (0x00 << 6) | ||
| 589 | #define S3C2410_GPE3_OUTP (0x01 << 6) | ||
| 590 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) | ||
| 591 | #define S3C2443_GPE3_AC_SDI (0x03 << 6) | ||
| 592 | #define S3C2400_GPE3_EINT3 (0x02 << 6) | ||
| 593 | #define S3C2400_GPE3_nCTS1 (0x03 << 6) | ||
| 594 | #define S3C2410_GPE3_nSS0 (0x03 << 6) | ||
| 595 | #define S3C2410_GPE3_MASK (0x03 << 6) | ||
| 596 | |||
| 597 | #define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4) | ||
| 598 | #define S3C2410_GPE4_INP (0x00 << 8) | ||
| 599 | #define S3C2410_GPE4_OUTP (0x01 << 8) | ||
| 600 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) | ||
| 601 | #define S3C2443_GPE4_AC_SDO (0x03 << 8) | ||
| 602 | #define S3C2400_GPE4_EINT4 (0x02 << 8) | ||
| 603 | #define S3C2400_GPE4_nRTS1 (0x03 << 8) | ||
| 604 | #define S3C2410_GPE4_I2SSDI (0x03 << 8) | ||
| 605 | #define S3C2410_GPE4_MASK (0x03 << 8) | ||
| 606 | |||
| 607 | #define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5) | ||
| 608 | #define S3C2410_GPE5_INP (0x00 << 10) | ||
| 609 | #define S3C2410_GPE5_OUTP (0x01 << 10) | ||
| 610 | #define S3C2410_GPE5_SDCLK (0x02 << 10) | ||
| 611 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) | ||
| 612 | #define S3C2400_GPE5_EINT5 (0x02 << 10) | ||
| 613 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) | ||
| 614 | |||
| 615 | #define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) | ||
| 616 | #define S3C2410_GPE6_INP (0x00 << 12) | ||
| 617 | #define S3C2410_GPE6_OUTP (0x01 << 12) | ||
| 618 | #define S3C2410_GPE6_SDCMD (0x02 << 12) | ||
| 619 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) | ||
| 620 | #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) | ||
| 621 | #define S3C2400_GPE6_EINT6 (0x02 << 12) | ||
| 622 | |||
| 623 | #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) | ||
| 624 | #define S3C2410_GPE7_INP (0x00 << 14) | ||
| 625 | #define S3C2410_GPE7_OUTP (0x01 << 14) | ||
| 626 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) | ||
| 627 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) | ||
| 628 | #define S3C2443_GPE7_AC_SDI (0x03 << 14) | ||
| 629 | #define S3C2400_GPE7_EINT7 (0x02 << 14) | ||
| 630 | |||
| 631 | #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) | ||
| 632 | #define S3C2410_GPE8_INP (0x00 << 16) | ||
| 633 | #define S3C2410_GPE8_OUTP (0x01 << 16) | ||
| 634 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) | ||
| 635 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) | ||
| 636 | #define S3C2443_GPE8_AC_SDO (0x03 << 16) | ||
| 637 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) | ||
| 638 | |||
| 639 | #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) | ||
| 640 | #define S3C2410_GPE9_INP (0x00 << 18) | ||
| 641 | #define S3C2410_GPE9_OUTP (0x01 << 18) | ||
| 642 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) | ||
| 643 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) | ||
| 644 | #define S3C2443_GPE9_AC_SYNC (0x03 << 18) | ||
| 645 | #define S3C2400_GPE9_nXDACK1 (0x02 << 18) | ||
| 646 | #define S3C2400_GPE9_nXBACK (0x03 << 18) | ||
| 647 | |||
| 648 | #define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) | ||
| 649 | #define S3C2410_GPE10_INP (0x00 << 20) | ||
| 650 | #define S3C2410_GPE10_OUTP (0x01 << 20) | ||
| 651 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) | ||
| 652 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) | ||
| 653 | #define S3C2443_GPE10_AC_nRESET (0x03 << 20) | ||
| 654 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) | ||
| 655 | |||
| 656 | #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) | ||
| 657 | #define S3C2410_GPE11_INP (0x00 << 22) | ||
| 658 | #define S3C2410_GPE11_OUTP (0x01 << 22) | ||
| 659 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) | ||
| 660 | #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) | ||
| 661 | #define S3C2400_GPE11_nXBREQ (0x03 << 22) | ||
| 662 | |||
| 663 | #define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) | ||
| 664 | #define S3C2410_GPE12_INP (0x00 << 24) | ||
| 665 | #define S3C2410_GPE12_OUTP (0x01 << 24) | ||
| 666 | #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) | ||
| 667 | |||
| 668 | #define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13) | ||
| 669 | #define S3C2410_GPE13_INP (0x00 << 26) | ||
| 670 | #define S3C2410_GPE13_OUTP (0x01 << 26) | ||
| 671 | #define S3C2410_GPE13_SPICLK0 (0x02 << 26) | ||
| 672 | |||
| 673 | #define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14) | ||
| 674 | #define S3C2410_GPE14_INP (0x00 << 28) | ||
| 675 | #define S3C2410_GPE14_OUTP (0x01 << 28) | ||
| 676 | #define S3C2410_GPE14_IICSCL (0x02 << 28) | ||
| 677 | #define S3C2410_GPE14_MASK (0x03 << 28) | ||
| 678 | |||
| 679 | #define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15) | ||
| 680 | #define S3C2410_GPE15_INP (0x00 << 30) | ||
| 681 | #define S3C2410_GPE15_OUTP (0x01 << 30) | ||
| 682 | #define S3C2410_GPE15_IICSDA (0x02 << 30) | ||
| 683 | #define S3C2410_GPE15_MASK (0x03 << 30) | ||
| 684 | |||
| 685 | #define S3C2440_GPE0_ACSYNC (0x03 << 0) | ||
| 686 | #define S3C2440_GPE1_ACBITCLK (0x03 << 2) | ||
| 687 | #define S3C2440_GPE2_ACRESET (0x03 << 4) | ||
| 688 | #define S3C2440_GPE3_ACIN (0x03 << 6) | ||
| 689 | #define S3C2440_GPE4_ACOUT (0x03 << 8) | ||
| 690 | |||
| 691 | #define S3C2410_GPE_PUPDIS(x) (1<<(x)) | ||
| 692 | |||
| 693 | /* S3C2410: | ||
| 694 | * Port F consists of 8 GPIO/Special function | ||
| 695 | * | ||
| 696 | * GPIO / interrupt inputs | ||
| 697 | * | ||
| 698 | * GPFCON has 2 bits for each of the input pins on port F | ||
| 699 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined | ||
| 700 | * | ||
| 701 | * pull up works like all other ports. | ||
| 702 | * | ||
| 703 | * S3C2400: | ||
| 704 | * Port F consists of 7 GPIO/Special function | ||
| 705 | * | ||
| 706 | * GPIO/serial/misc pins | ||
| 707 | */ | ||
| 708 | |||
| 709 | #define S3C2410_GPFCON S3C2410_GPIOREG(0x50) | ||
| 710 | #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) | ||
| 711 | #define S3C2410_GPFUP S3C2410_GPIOREG(0x58) | ||
| 712 | |||
| 713 | #define S3C2400_GPFCON S3C2410_GPIOREG(0x38) | ||
| 714 | #define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) | ||
| 715 | #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) | ||
| 716 | |||
| 717 | #define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) | ||
| 718 | #define S3C2410_GPF0_INP (0x00 << 0) | ||
| 719 | #define S3C2410_GPF0_OUTP (0x01 << 0) | ||
| 720 | #define S3C2410_GPF0_EINT0 (0x02 << 0) | ||
| 721 | #define S3C2400_GPF0_RXD0 (0x02 << 0) | ||
| 722 | |||
| 723 | #define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) | ||
| 724 | #define S3C2410_GPF1_INP (0x00 << 2) | ||
| 725 | #define S3C2410_GPF1_OUTP (0x01 << 2) | ||
| 726 | #define S3C2410_GPF1_EINT1 (0x02 << 2) | ||
| 727 | #define S3C2400_GPF1_RXD1 (0x02 << 2) | ||
| 728 | #define S3C2400_GPF1_IICSDA (0x03 << 2) | ||
| 729 | |||
| 730 | #define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) | ||
| 731 | #define S3C2410_GPF2_INP (0x00 << 4) | ||
| 732 | #define S3C2410_GPF2_OUTP (0x01 << 4) | ||
| 733 | #define S3C2410_GPF2_EINT2 (0x02 << 4) | ||
| 734 | #define S3C2400_GPF2_TXD0 (0x02 << 4) | ||
| 735 | |||
| 736 | #define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) | ||
| 737 | #define S3C2410_GPF3_INP (0x00 << 6) | ||
| 738 | #define S3C2410_GPF3_OUTP (0x01 << 6) | ||
| 739 | #define S3C2410_GPF3_EINT3 (0x02 << 6) | ||
| 740 | #define S3C2400_GPF3_TXD1 (0x02 << 6) | ||
| 741 | #define S3C2400_GPF3_IICSCL (0x03 << 6) | ||
| 742 | |||
| 743 | #define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) | ||
| 744 | #define S3C2410_GPF4_INP (0x00 << 8) | ||
| 745 | #define S3C2410_GPF4_OUTP (0x01 << 8) | ||
| 746 | #define S3C2410_GPF4_EINT4 (0x02 << 8) | ||
| 747 | #define S3C2400_GPF4_nRTS0 (0x02 << 8) | ||
| 748 | #define S3C2400_GPF4_nXBACK (0x03 << 8) | ||
| 749 | |||
| 750 | #define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) | ||
| 751 | #define S3C2410_GPF5_INP (0x00 << 10) | ||
| 752 | #define S3C2410_GPF5_OUTP (0x01 << 10) | ||
| 753 | #define S3C2410_GPF5_EINT5 (0x02 << 10) | ||
| 754 | #define S3C2400_GPF5_nCTS0 (0x02 << 10) | ||
| 755 | #define S3C2400_GPF5_nXBREQ (0x03 << 10) | ||
| 756 | |||
| 757 | #define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) | ||
| 758 | #define S3C2410_GPF6_INP (0x00 << 12) | ||
| 759 | #define S3C2410_GPF6_OUTP (0x01 << 12) | ||
| 760 | #define S3C2410_GPF6_EINT6 (0x02 << 12) | ||
| 761 | #define S3C2400_GPF6_CLKOUT (0x02 << 12) | ||
| 762 | |||
| 763 | #define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) | ||
| 764 | #define S3C2410_GPF7_INP (0x00 << 14) | ||
| 765 | #define S3C2410_GPF7_OUTP (0x01 << 14) | ||
| 766 | #define S3C2410_GPF7_EINT7 (0x02 << 14) | ||
| 767 | |||
| 768 | #define S3C2410_GPF_PUPDIS(x) (1<<(x)) | ||
| 769 | |||
| 770 | /* S3C2410: | ||
| 771 | * Port G consists of 8 GPIO/IRQ/Special function | ||
| 772 | * | ||
| 773 | * GPGCON has 2 bits for each of the input pins on port F | ||
| 774 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | ||
| 775 | * | ||
| 776 | * pull up works like all other ports. | ||
| 777 | * | ||
| 778 | * S3C2400: | ||
| 779 | * Port G consists of 10 GPIO/Special function | ||
| 780 | */ | ||
| 781 | |||
| 782 | #define S3C2410_GPGCON S3C2410_GPIOREG(0x60) | ||
| 783 | #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) | ||
| 784 | #define S3C2410_GPGUP S3C2410_GPIOREG(0x68) | ||
| 785 | |||
| 786 | #define S3C2400_GPGCON S3C2410_GPIOREG(0x44) | ||
| 787 | #define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) | ||
| 788 | #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) | ||
| 789 | |||
| 790 | #define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) | ||
| 791 | #define S3C2410_GPG0_INP (0x00 << 0) | ||
| 792 | #define S3C2410_GPG0_OUTP (0x01 << 0) | ||
| 793 | #define S3C2410_GPG0_EINT8 (0x02 << 0) | ||
| 794 | #define S3C2400_GPG0_I2SLRCK (0x02 << 0) | ||
| 795 | |||
| 796 | #define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) | ||
| 797 | #define S3C2410_GPG1_INP (0x00 << 2) | ||
| 798 | #define S3C2410_GPG1_OUTP (0x01 << 2) | ||
| 799 | #define S3C2410_GPG1_EINT9 (0x02 << 2) | ||
| 800 | #define S3C2400_GPG1_I2SSCLK (0x02 << 2) | ||
| 801 | |||
| 802 | #define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) | ||
| 803 | #define S3C2410_GPG2_INP (0x00 << 4) | ||
| 804 | #define S3C2410_GPG2_OUTP (0x01 << 4) | ||
| 805 | #define S3C2410_GPG2_EINT10 (0x02 << 4) | ||
| 806 | #define S3C2410_GPG2_nSS0 (0x03 << 4) | ||
| 807 | #define S3C2400_GPG2_CDCLK (0x02 << 4) | ||
| 808 | |||
| 809 | #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) | ||
| 810 | #define S3C2410_GPG3_INP (0x00 << 6) | ||
| 811 | #define S3C2410_GPG3_OUTP (0x01 << 6) | ||
| 812 | #define S3C2410_GPG3_EINT11 (0x02 << 6) | ||
| 813 | #define S3C2410_GPG3_nSS1 (0x03 << 6) | ||
| 814 | #define S3C2400_GPG3_I2SSDO (0x02 << 6) | ||
| 815 | #define S3C2400_GPG3_I2SSDI (0x03 << 6) | ||
| 816 | |||
| 817 | #define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) | ||
| 818 | #define S3C2410_GPG4_INP (0x00 << 8) | ||
| 819 | #define S3C2410_GPG4_OUTP (0x01 << 8) | ||
| 820 | #define S3C2410_GPG4_EINT12 (0x02 << 8) | ||
| 821 | #define S3C2400_GPG4_MMCCLK (0x02 << 8) | ||
| 822 | #define S3C2400_GPG4_I2SSDI (0x03 << 8) | ||
| 823 | #define S3C2410_GPG4_LCDPWREN (0x03 << 8) | ||
| 824 | #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) | ||
| 825 | |||
| 826 | #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) | ||
| 827 | #define S3C2410_GPG5_INP (0x00 << 10) | ||
| 828 | #define S3C2410_GPG5_OUTP (0x01 << 10) | ||
| 829 | #define S3C2410_GPG5_EINT13 (0x02 << 10) | ||
| 830 | #define S3C2400_GPG5_MMCCMD (0x02 << 10) | ||
| 831 | #define S3C2400_GPG5_IICSDA (0x03 << 10) | ||
| 832 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ | ||
| 833 | |||
| 834 | #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) | ||
| 835 | #define S3C2410_GPG6_INP (0x00 << 12) | ||
| 836 | #define S3C2410_GPG6_OUTP (0x01 << 12) | ||
| 837 | #define S3C2410_GPG6_EINT14 (0x02 << 12) | ||
| 838 | #define S3C2400_GPG6_MMCDAT (0x02 << 12) | ||
| 839 | #define S3C2400_GPG6_IICSCL (0x03 << 12) | ||
| 840 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) | ||
| 841 | |||
| 842 | #define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) | ||
| 843 | #define S3C2410_GPG7_INP (0x00 << 14) | ||
| 844 | #define S3C2410_GPG7_OUTP (0x01 << 14) | ||
| 845 | #define S3C2410_GPG7_EINT15 (0x02 << 14) | ||
| 846 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) | ||
| 847 | #define S3C2400_GPG7_SPIMISO (0x02 << 14) | ||
| 848 | #define S3C2400_GPG7_IICSDA (0x03 << 14) | ||
| 849 | |||
| 850 | #define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) | ||
| 851 | #define S3C2410_GPG8_INP (0x00 << 16) | ||
| 852 | #define S3C2410_GPG8_OUTP (0x01 << 16) | ||
| 853 | #define S3C2410_GPG8_EINT16 (0x02 << 16) | ||
| 854 | #define S3C2400_GPG8_SPIMOSI (0x02 << 16) | ||
| 855 | #define S3C2400_GPG8_IICSCL (0x03 << 16) | ||
| 856 | |||
| 857 | #define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) | ||
| 858 | #define S3C2410_GPG9_INP (0x00 << 18) | ||
| 859 | #define S3C2410_GPG9_OUTP (0x01 << 18) | ||
| 860 | #define S3C2410_GPG9_EINT17 (0x02 << 18) | ||
| 861 | #define S3C2400_GPG9_SPICLK (0x02 << 18) | ||
| 862 | #define S3C2400_GPG9_MMCCLK (0x03 << 18) | ||
| 863 | |||
| 864 | #define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) | ||
| 865 | #define S3C2410_GPG10_INP (0x00 << 20) | ||
| 866 | #define S3C2410_GPG10_OUTP (0x01 << 20) | ||
| 867 | #define S3C2410_GPG10_EINT18 (0x02 << 20) | ||
| 868 | |||
| 869 | #define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11) | ||
| 870 | #define S3C2410_GPG11_INP (0x00 << 22) | ||
| 871 | #define S3C2410_GPG11_OUTP (0x01 << 22) | ||
| 872 | #define S3C2410_GPG11_EINT19 (0x02 << 22) | ||
| 873 | #define S3C2410_GPG11_TCLK1 (0x03 << 22) | ||
| 874 | #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) | ||
| 875 | |||
| 876 | #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) | ||
| 877 | #define S3C2410_GPG12_INP (0x00 << 24) | ||
| 878 | #define S3C2410_GPG12_OUTP (0x01 << 24) | ||
| 879 | #define S3C2410_GPG12_EINT20 (0x02 << 24) | ||
| 880 | #define S3C2410_GPG12_XMON (0x03 << 24) | ||
| 881 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) | ||
| 882 | #define S3C2443_GPG12_nINPACK (0x03 << 24) | ||
| 883 | |||
| 884 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) | ||
| 885 | #define S3C2410_GPG13_INP (0x00 << 26) | ||
| 886 | #define S3C2410_GPG13_OUTP (0x01 << 26) | ||
| 887 | #define S3C2410_GPG13_EINT21 (0x02 << 26) | ||
| 888 | #define S3C2410_GPG13_nXPON (0x03 << 26) | ||
| 889 | #define S3C2443_GPG13_CF_nREG (0x03 << 26) | ||
| 890 | |||
| 891 | #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) | ||
| 892 | #define S3C2410_GPG14_INP (0x00 << 28) | ||
| 893 | #define S3C2410_GPG14_OUTP (0x01 << 28) | ||
| 894 | #define S3C2410_GPG14_EINT22 (0x02 << 28) | ||
| 895 | #define S3C2410_GPG14_YMON (0x03 << 28) | ||
| 896 | #define S3C2443_GPG14_CF_RESET (0x03 << 28) | ||
| 897 | |||
| 898 | #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) | ||
| 899 | #define S3C2410_GPG15_INP (0x00 << 30) | ||
| 900 | #define S3C2410_GPG15_OUTP (0x01 << 30) | ||
| 901 | #define S3C2410_GPG15_EINT23 (0x02 << 30) | ||
| 902 | #define S3C2410_GPG15_nYPON (0x03 << 30) | ||
| 903 | #define S3C2443_GPG15_CF_PWR (0x03 << 30) | ||
| 904 | |||
| 905 | #define S3C2410_GPG_PUPDIS(x) (1<<(x)) | ||
| 906 | |||
| 907 | /* Port H consists of11 GPIO/serial/Misc pins | ||
| 908 | * | ||
| 909 | * GPGCON has 2 bits for each of the input pins on port F | ||
| 910 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | ||
| 911 | * | ||
| 912 | * pull up works like all other ports. | ||
| 913 | */ | ||
| 914 | |||
| 915 | #define S3C2410_GPHCON S3C2410_GPIOREG(0x70) | ||
| 916 | #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) | ||
| 917 | #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) | ||
| 918 | |||
| 919 | #define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0) | ||
| 920 | #define S3C2410_GPH0_INP (0x00 << 0) | ||
| 921 | #define S3C2410_GPH0_OUTP (0x01 << 0) | ||
| 922 | #define S3C2410_GPH0_nCTS0 (0x02 << 0) | ||
| 923 | |||
| 924 | #define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1) | ||
| 925 | #define S3C2410_GPH1_INP (0x00 << 2) | ||
| 926 | #define S3C2410_GPH1_OUTP (0x01 << 2) | ||
| 927 | #define S3C2410_GPH1_nRTS0 (0x02 << 2) | ||
| 928 | |||
| 929 | #define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2) | ||
| 930 | #define S3C2410_GPH2_INP (0x00 << 4) | ||
| 931 | #define S3C2410_GPH2_OUTP (0x01 << 4) | ||
| 932 | #define S3C2410_GPH2_TXD0 (0x02 << 4) | ||
| 933 | |||
| 934 | #define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3) | ||
| 935 | #define S3C2410_GPH3_INP (0x00 << 6) | ||
| 936 | #define S3C2410_GPH3_OUTP (0x01 << 6) | ||
| 937 | #define S3C2410_GPH3_RXD0 (0x02 << 6) | ||
| 938 | |||
| 939 | #define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4) | ||
| 940 | #define S3C2410_GPH4_INP (0x00 << 8) | ||
| 941 | #define S3C2410_GPH4_OUTP (0x01 << 8) | ||
| 942 | #define S3C2410_GPH4_TXD1 (0x02 << 8) | ||
| 943 | |||
| 944 | #define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5) | ||
| 945 | #define S3C2410_GPH5_INP (0x00 << 10) | ||
| 946 | #define S3C2410_GPH5_OUTP (0x01 << 10) | ||
| 947 | #define S3C2410_GPH5_RXD1 (0x02 << 10) | ||
| 948 | |||
| 949 | #define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6) | ||
| 950 | #define S3C2410_GPH6_INP (0x00 << 12) | ||
| 951 | #define S3C2410_GPH6_OUTP (0x01 << 12) | ||
| 952 | #define S3C2410_GPH6_TXD2 (0x02 << 12) | ||
| 953 | #define S3C2410_GPH6_nRTS1 (0x03 << 12) | ||
| 954 | |||
| 955 | #define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7) | ||
| 956 | #define S3C2410_GPH7_INP (0x00 << 14) | ||
| 957 | #define S3C2410_GPH7_OUTP (0x01 << 14) | ||
| 958 | #define S3C2410_GPH7_RXD2 (0x02 << 14) | ||
| 959 | #define S3C2410_GPH7_nCTS1 (0x03 << 14) | ||
| 960 | |||
| 961 | #define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8) | ||
| 962 | #define S3C2410_GPH8_INP (0x00 << 16) | ||
| 963 | #define S3C2410_GPH8_OUTP (0x01 << 16) | ||
| 964 | #define S3C2410_GPH8_UCLK (0x02 << 16) | ||
| 965 | |||
| 966 | #define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9) | ||
| 967 | #define S3C2410_GPH9_INP (0x00 << 18) | ||
| 968 | #define S3C2410_GPH9_OUTP (0x01 << 18) | ||
| 969 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) | ||
| 970 | #define S3C2442_GPH9_nSPICS0 (0x03 << 18) | ||
| 971 | |||
| 972 | #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) | ||
| 973 | #define S3C2410_GPH10_INP (0x00 << 20) | ||
| 974 | #define S3C2410_GPH10_OUTP (0x01 << 20) | ||
| 975 | #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) | ||
| 976 | |||
| 977 | /* The S3C2412 and S3C2413 move the GPJ register set to after | ||
| 978 | * GPH, which means all registers after 0x80 are now offset by 0x10 | ||
| 979 | * for the 2412/2413 from the 2410/2440/2442 | ||
| 980 | */ | ||
| 981 | |||
| 982 | /* miscellaneous control */ | ||
| 983 | #define S3C2400_MISCCR S3C2410_GPIOREG(0x54) | ||
| 984 | #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) | ||
| 985 | #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) | ||
| 986 | |||
| 987 | #define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84) | ||
| 988 | |||
| 989 | /* see clock.h for dclk definitions */ | ||
| 990 | |||
| 991 | /* pullup control on databus */ | ||
| 992 | #define S3C2410_MISCCR_SPUCR_HEN (0<<0) | ||
| 993 | #define S3C2410_MISCCR_SPUCR_HDIS (1<<0) | ||
| 994 | #define S3C2410_MISCCR_SPUCR_LEN (0<<1) | ||
| 995 | #define S3C2410_MISCCR_SPUCR_LDIS (1<<1) | ||
| 996 | |||
| 997 | #define S3C2400_MISCCR_SPUCR_LEN (0<<0) | ||
| 998 | #define S3C2400_MISCCR_SPUCR_LDIS (1<<0) | ||
| 999 | #define S3C2400_MISCCR_SPUCR_HEN (0<<1) | ||
| 1000 | #define S3C2400_MISCCR_SPUCR_HDIS (1<<1) | ||
| 1001 | |||
| 1002 | #define S3C2400_MISCCR_HZ_STOPEN (0<<2) | ||
| 1003 | #define S3C2400_MISCCR_HZ_STOPPREV (1<<2) | ||
| 1004 | |||
| 1005 | #define S3C2410_MISCCR_USBDEV (0<<3) | ||
| 1006 | #define S3C2410_MISCCR_USBHOST (1<<3) | ||
| 1007 | |||
| 1008 | #define S3C2410_MISCCR_CLK0_MPLL (0<<4) | ||
| 1009 | #define S3C2410_MISCCR_CLK0_UPLL (1<<4) | ||
| 1010 | #define S3C2410_MISCCR_CLK0_FCLK (2<<4) | ||
| 1011 | #define S3C2410_MISCCR_CLK0_HCLK (3<<4) | ||
| 1012 | #define S3C2410_MISCCR_CLK0_PCLK (4<<4) | ||
| 1013 | #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) | ||
| 1014 | #define S3C2410_MISCCR_CLK0_MASK (7<<4) | ||
| 1015 | |||
| 1016 | #define S3C2412_MISCCR_CLK0_RTC (2<<4) | ||
| 1017 | |||
| 1018 | #define S3C2410_MISCCR_CLK1_MPLL (0<<8) | ||
| 1019 | #define S3C2410_MISCCR_CLK1_UPLL (1<<8) | ||
| 1020 | #define S3C2410_MISCCR_CLK1_FCLK (2<<8) | ||
| 1021 | #define S3C2410_MISCCR_CLK1_HCLK (3<<8) | ||
| 1022 | #define S3C2410_MISCCR_CLK1_PCLK (4<<8) | ||
| 1023 | #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) | ||
| 1024 | #define S3C2410_MISCCR_CLK1_MASK (7<<8) | ||
| 1025 | |||
| 1026 | #define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) | ||
| 1027 | |||
| 1028 | #define S3C2410_MISCCR_USBSUSPND0 (1<<12) | ||
| 1029 | #define S3C2410_MISCCR_USBSUSPND1 (1<<13) | ||
| 1030 | |||
| 1031 | #define S3C2410_MISCCR_nRSTCON (1<<16) | ||
| 1032 | |||
| 1033 | #define S3C2410_MISCCR_nEN_SCLK0 (1<<17) | ||
| 1034 | #define S3C2410_MISCCR_nEN_SCLK1 (1<<18) | ||
| 1035 | #define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ | ||
| 1036 | #define S3C2410_MISCCR_SDSLEEP (7<<17) | ||
| 1037 | |||
| 1038 | /* external interrupt control... */ | ||
| 1039 | /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 | ||
| 1040 | * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 | ||
| 1041 | * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 | ||
| 1042 | * | ||
| 1043 | * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 | ||
| 1044 | * | ||
| 1045 | * Samsung datasheet p9-25 | ||
| 1046 | */ | ||
| 1047 | #define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58) | ||
| 1048 | #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) | ||
| 1049 | #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) | ||
| 1050 | #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) | ||
| 1051 | |||
| 1052 | #define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) | ||
| 1053 | #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) | ||
| 1054 | #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) | ||
| 1055 | |||
| 1056 | /* values for S3C2410_EXTINT0/1/2 */ | ||
| 1057 | #define S3C2410_EXTINT_LOWLEV (0x00) | ||
| 1058 | #define S3C2410_EXTINT_HILEV (0x01) | ||
| 1059 | #define S3C2410_EXTINT_FALLEDGE (0x02) | ||
| 1060 | #define S3C2410_EXTINT_RISEEDGE (0x04) | ||
| 1061 | #define S3C2410_EXTINT_BOTHEDGE (0x06) | ||
| 1062 | |||
| 1063 | /* interrupt filtering conrrol for EINT16..EINT23 */ | ||
| 1064 | #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) | ||
| 1065 | #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) | ||
| 1066 | #define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) | ||
| 1067 | #define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) | ||
| 1068 | |||
| 1069 | #define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) | ||
| 1070 | #define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) | ||
| 1071 | #define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) | ||
| 1072 | #define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) | ||
| 1073 | |||
| 1074 | /* values for interrupt filtering */ | ||
| 1075 | #define S3C2410_EINTFLT_PCLK (0x00) | ||
| 1076 | #define S3C2410_EINTFLT_EXTCLK (1<<7) | ||
| 1077 | #define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) | ||
| 1078 | |||
| 1079 | /* removed EINTxxxx defs from here, not meant for this */ | ||
| 1080 | |||
| 1081 | /* GSTATUS have miscellaneous information in them | ||
| 1082 | * | ||
| 1083 | * These move between s3c2410 and s3c2412 style systems. | ||
| 1084 | */ | ||
| 1085 | |||
| 1086 | #define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) | ||
| 1087 | #define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) | ||
| 1088 | #define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) | ||
| 1089 | #define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) | ||
| 1090 | #define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) | ||
| 1091 | |||
| 1092 | #define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) | ||
| 1093 | #define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) | ||
| 1094 | #define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) | ||
| 1095 | #define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) | ||
| 1096 | #define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) | ||
| 1097 | |||
| 1098 | #define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) | ||
| 1099 | #define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) | ||
| 1100 | #define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) | ||
| 1101 | #define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) | ||
| 1102 | #define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) | ||
| 1103 | |||
| 1104 | #define S3C2410_GSTATUS0_nWAIT (1<<3) | ||
| 1105 | #define S3C2410_GSTATUS0_NCON (1<<2) | ||
| 1106 | #define S3C2410_GSTATUS0_RnB (1<<1) | ||
| 1107 | #define S3C2410_GSTATUS0_nBATTFLT (1<<0) | ||
| 1108 | |||
| 1109 | #define S3C2410_GSTATUS1_IDMASK (0xffff0000) | ||
| 1110 | #define S3C2410_GSTATUS1_2410 (0x32410000) | ||
| 1111 | #define S3C2410_GSTATUS1_2412 (0x32412001) | ||
| 1112 | #define S3C2410_GSTATUS1_2440 (0x32440000) | ||
| 1113 | #define S3C2410_GSTATUS1_2442 (0x32440aaa) | ||
| 1114 | |||
| 1115 | #define S3C2410_GSTATUS2_WTRESET (1<<2) | ||
| 1116 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) | ||
| 1117 | #define S3C2410_GSTATUS2_PONRESET (1<<0) | ||
| 1118 | |||
| 1119 | /* open drain control register */ | ||
| 1120 | #define S3C2400_OPENCR S3C2410_GPIOREG(0x50) | ||
| 1121 | |||
| 1122 | #define S3C2400_OPENCR_OPC_RXD1DIS (0<<0) | ||
| 1123 | #define S3C2400_OPENCR_OPC_RXD1EN (1<<0) | ||
| 1124 | #define S3C2400_OPENCR_OPC_TXD1DIS (0<<1) | ||
| 1125 | #define S3C2400_OPENCR_OPC_TXD1EN (1<<1) | ||
| 1126 | #define S3C2400_OPENCR_OPC_CMDDIS (0<<2) | ||
| 1127 | #define S3C2400_OPENCR_OPC_CMDEN (1<<2) | ||
| 1128 | #define S3C2400_OPENCR_OPC_DATDIS (0<<3) | ||
| 1129 | #define S3C2400_OPENCR_OPC_DATEN (1<<3) | ||
| 1130 | #define S3C2400_OPENCR_OPC_MISODIS (0<<4) | ||
| 1131 | #define S3C2400_OPENCR_OPC_MISOEN (1<<4) | ||
| 1132 | #define S3C2400_OPENCR_OPC_MOSIDIS (0<<5) | ||
| 1133 | #define S3C2400_OPENCR_OPC_MOSIEN (1<<5) | ||
| 1134 | |||
| 1135 | /* 2412/2413 sleep configuration registers */ | ||
| 1136 | |||
| 1137 | #define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) | ||
| 1138 | #define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) | ||
| 1139 | #define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) | ||
| 1140 | #define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) | ||
| 1141 | #define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) | ||
| 1142 | #define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) | ||
| 1143 | |||
| 1144 | /* definitions for each pin bit */ | ||
| 1145 | #define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) | ||
| 1146 | #define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) | ||
| 1147 | #define S3C2412_GPIO_SLPCON_IN ( 0x02 ) | ||
| 1148 | #define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) | ||
| 1149 | |||
| 1150 | #define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) | ||
| 1151 | #define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) | ||
| 1152 | #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) | ||
| 1153 | #define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) | ||
| 1154 | #define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ | ||
| 1155 | #define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) | ||
| 1156 | |||
| 1157 | #define S3C2412_SLPCON_ALL_LOW (0x0) | ||
| 1158 | #define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) | ||
| 1159 | #define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) | ||
| 1160 | #define S3C2412_SLPCON_ALL_PULL (0x33333333) | ||
| 1161 | |||
| 1162 | #endif /* __ASM_ARCH_REGS_GPIO_H */ | ||
| 1163 | |||
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h deleted file mode 100644 index 0362332faaf0..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-gpioj.h +++ /dev/null | |||
| @@ -1,106 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-gpioj.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2440 GPIO J register definitions | ||
| 11 | */ | ||
| 12 | |||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_REGS_GPIOJ_H | ||
| 15 | #define __ASM_ARCH_REGS_GPIOJ_H "gpioj" | ||
| 16 | |||
| 17 | /* Port J consists of 13 GPIO/Camera pins | ||
| 18 | * | ||
| 19 | * GPJCON has 2 bits for each of the input pins on port F | ||
| 20 | * 00 = 0 input, 1 output, 2 Camera | ||
| 21 | * | ||
| 22 | * pull up works like all other ports. | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define S3C2440_GPIO_BANKJ (416) | ||
| 26 | |||
| 27 | #define S3C2440_GPJCON S3C2410_GPIOREG(0xd0) | ||
| 28 | #define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4) | ||
| 29 | #define S3C2440_GPJUP S3C2410_GPIOREG(0xd8) | ||
| 30 | |||
| 31 | #define S3C2413_GPJCON S3C2410_GPIOREG(0x80) | ||
| 32 | #define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) | ||
| 33 | #define S3C2413_GPJUP S3C2410_GPIOREG(0x88) | ||
| 34 | #define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) | ||
| 35 | |||
| 36 | #define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0) | ||
| 37 | #define S3C2440_GPJ0_INP (0x00 << 0) | ||
| 38 | #define S3C2440_GPJ0_OUTP (0x01 << 0) | ||
| 39 | #define S3C2440_GPJ0_CAMDATA0 (0x02 << 0) | ||
| 40 | |||
| 41 | #define S3C2440_GPJ1 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1) | ||
| 42 | #define S3C2440_GPJ1_INP (0x00 << 2) | ||
| 43 | #define S3C2440_GPJ1_OUTP (0x01 << 2) | ||
| 44 | #define S3C2440_GPJ1_CAMDATA1 (0x02 << 2) | ||
| 45 | |||
| 46 | #define S3C2440_GPJ2 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2) | ||
| 47 | #define S3C2440_GPJ2_INP (0x00 << 4) | ||
| 48 | #define S3C2440_GPJ2_OUTP (0x01 << 4) | ||
| 49 | #define S3C2440_GPJ2_CAMDATA2 (0x02 << 4) | ||
| 50 | |||
| 51 | #define S3C2440_GPJ3 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3) | ||
| 52 | #define S3C2440_GPJ3_INP (0x00 << 6) | ||
| 53 | #define S3C2440_GPJ3_OUTP (0x01 << 6) | ||
| 54 | #define S3C2440_GPJ3_CAMDATA3 (0x02 << 6) | ||
| 55 | |||
| 56 | #define S3C2440_GPJ4 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4) | ||
| 57 | #define S3C2440_GPJ4_INP (0x00 << 8) | ||
| 58 | #define S3C2440_GPJ4_OUTP (0x01 << 8) | ||
| 59 | #define S3C2440_GPJ4_CAMDATA4 (0x02 << 8) | ||
| 60 | |||
| 61 | #define S3C2440_GPJ5 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5) | ||
| 62 | #define S3C2440_GPJ5_INP (0x00 << 10) | ||
| 63 | #define S3C2440_GPJ5_OUTP (0x01 << 10) | ||
| 64 | #define S3C2440_GPJ5_CAMDATA5 (0x02 << 10) | ||
| 65 | |||
| 66 | #define S3C2440_GPJ6 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6) | ||
| 67 | #define S3C2440_GPJ6_INP (0x00 << 12) | ||
| 68 | #define S3C2440_GPJ6_OUTP (0x01 << 12) | ||
| 69 | #define S3C2440_GPJ6_CAMDATA6 (0x02 << 12) | ||
| 70 | |||
| 71 | #define S3C2440_GPJ7 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7) | ||
| 72 | #define S3C2440_GPJ7_INP (0x00 << 14) | ||
| 73 | #define S3C2440_GPJ7_OUTP (0x01 << 14) | ||
| 74 | #define S3C2440_GPJ7_CAMDATA7 (0x02 << 14) | ||
| 75 | |||
| 76 | #define S3C2440_GPJ8 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8) | ||
| 77 | #define S3C2440_GPJ8_INP (0x00 << 16) | ||
| 78 | #define S3C2440_GPJ8_OUTP (0x01 << 16) | ||
| 79 | #define S3C2440_GPJ8_CAMPCLK (0x02 << 16) | ||
| 80 | |||
| 81 | #define S3C2440_GPJ9 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9) | ||
| 82 | #define S3C2440_GPJ9_INP (0x00 << 18) | ||
| 83 | #define S3C2440_GPJ9_OUTP (0x01 << 18) | ||
| 84 | #define S3C2440_GPJ9_CAMVSYNC (0x02 << 18) | ||
| 85 | |||
| 86 | #define S3C2440_GPJ10 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10) | ||
| 87 | #define S3C2440_GPJ10_INP (0x00 << 20) | ||
| 88 | #define S3C2440_GPJ10_OUTP (0x01 << 20) | ||
| 89 | #define S3C2440_GPJ10_CAMHREF (0x02 << 20) | ||
| 90 | |||
| 91 | #define S3C2440_GPJ11 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11) | ||
| 92 | #define S3C2440_GPJ11_INP (0x00 << 22) | ||
| 93 | #define S3C2440_GPJ11_OUTP (0x01 << 22) | ||
| 94 | #define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22) | ||
| 95 | |||
| 96 | #define S3C2440_GPJ12 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12) | ||
| 97 | #define S3C2440_GPJ12_INP (0x00 << 24) | ||
| 98 | #define S3C2440_GPJ12_OUTP (0x01 << 24) | ||
| 99 | #define S3C2440_GPJ12_CAMRESET (0x02 << 24) | ||
| 100 | |||
| 101 | #define S3C2443_GPJ13 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13) | ||
| 102 | #define S3C2443_GPJ14 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14) | ||
| 103 | #define S3C2443_GPJ15 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15) | ||
| 104 | |||
| 105 | #endif /* __ASM_ARCH_REGS_GPIOJ_H */ | ||
| 106 | |||
diff --git a/include/asm-arm/arch-s3c2410/regs-irq.h b/include/asm-arm/arch-s3c2410/regs-irq.h deleted file mode 100644 index 498184cb8adc..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-irq.h +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-irq.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | |||
| 12 | #ifndef ___ASM_ARCH_REGS_IRQ_H | ||
| 13 | #define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $" | ||
| 14 | |||
| 15 | /* interrupt controller */ | ||
| 16 | |||
| 17 | #define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ) | ||
| 18 | #define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO) | ||
| 19 | #define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2) | ||
| 20 | |||
| 21 | #define S3C2410_SRCPND S3C2410_IRQREG(0x000) | ||
| 22 | #define S3C2410_INTMOD S3C2410_IRQREG(0x004) | ||
| 23 | #define S3C2410_INTMSK S3C2410_IRQREG(0x008) | ||
| 24 | #define S3C2410_PRIORITY S3C2410_IRQREG(0x00C) | ||
| 25 | #define S3C2410_INTPND S3C2410_IRQREG(0x010) | ||
| 26 | #define S3C2410_INTOFFSET S3C2410_IRQREG(0x014) | ||
| 27 | #define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018) | ||
| 28 | #define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C) | ||
| 29 | |||
| 30 | /* mask: 0=enable, 1=disable | ||
| 31 | * 1 bit EINT, 4=EINT4, 23=EINT23 | ||
| 32 | * EINT0,1,2,3 are not handled here. | ||
| 33 | */ | ||
| 34 | |||
| 35 | #define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4) | ||
| 36 | #define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8) | ||
| 37 | #define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4) | ||
| 38 | #define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8) | ||
| 39 | |||
| 40 | #define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4) | ||
| 41 | #define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8) | ||
| 42 | |||
| 43 | #endif /* ___ASM_ARCH_REGS_IRQ_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h deleted file mode 100644 index bd854845697f..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-lcd.h +++ /dev/null | |||
| @@ -1,162 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-lcd.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | |||
| 12 | #ifndef ___ASM_ARCH_REGS_LCD_H | ||
| 13 | #define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $" | ||
| 14 | |||
| 15 | #define S3C2410_LCDREG(x) (x) | ||
| 16 | |||
| 17 | /* LCD control registers */ | ||
| 18 | #define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) | ||
| 19 | #define S3C2410_LCDCON2 S3C2410_LCDREG(0x04) | ||
| 20 | #define S3C2410_LCDCON3 S3C2410_LCDREG(0x08) | ||
| 21 | #define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C) | ||
| 22 | #define S3C2410_LCDCON5 S3C2410_LCDREG(0x10) | ||
| 23 | |||
| 24 | #define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) | ||
| 25 | #define S3C2410_LCDCON1_MMODE (1<<7) | ||
| 26 | #define S3C2410_LCDCON1_DSCAN4 (0<<5) | ||
| 27 | #define S3C2410_LCDCON1_STN4 (1<<5) | ||
| 28 | #define S3C2410_LCDCON1_STN8 (2<<5) | ||
| 29 | #define S3C2410_LCDCON1_TFT (3<<5) | ||
| 30 | |||
| 31 | #define S3C2410_LCDCON1_STN1BPP (0<<1) | ||
| 32 | #define S3C2410_LCDCON1_STN2GREY (1<<1) | ||
| 33 | #define S3C2410_LCDCON1_STN4GREY (2<<1) | ||
| 34 | #define S3C2410_LCDCON1_STN8BPP (3<<1) | ||
| 35 | #define S3C2410_LCDCON1_STN12BPP (4<<1) | ||
| 36 | |||
| 37 | #define S3C2410_LCDCON1_TFT1BPP (8<<1) | ||
| 38 | #define S3C2410_LCDCON1_TFT2BPP (9<<1) | ||
| 39 | #define S3C2410_LCDCON1_TFT4BPP (10<<1) | ||
| 40 | #define S3C2410_LCDCON1_TFT8BPP (11<<1) | ||
| 41 | #define S3C2410_LCDCON1_TFT16BPP (12<<1) | ||
| 42 | #define S3C2410_LCDCON1_TFT24BPP (13<<1) | ||
| 43 | |||
| 44 | #define S3C2410_LCDCON1_ENVID (1) | ||
| 45 | |||
| 46 | #define S3C2410_LCDCON1_MODEMASK 0x1E | ||
| 47 | |||
| 48 | #define S3C2410_LCDCON2_VBPD(x) ((x) << 24) | ||
| 49 | #define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) | ||
| 50 | #define S3C2410_LCDCON2_VFPD(x) ((x) << 6) | ||
| 51 | #define S3C2410_LCDCON2_VSPW(x) ((x) << 0) | ||
| 52 | |||
| 53 | #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) | ||
| 54 | #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) | ||
| 55 | #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) | ||
| 56 | |||
| 57 | #define S3C2410_LCDCON3_HBPD(x) ((x) << 19) | ||
| 58 | #define S3C2410_LCDCON3_WDLY(x) ((x) << 19) | ||
| 59 | #define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) | ||
| 60 | #define S3C2410_LCDCON3_HFPD(x) ((x) << 0) | ||
| 61 | #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) | ||
| 62 | |||
| 63 | #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) | ||
| 64 | #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) | ||
| 65 | |||
| 66 | /* LDCCON4 changes for STN mode on the S3C2412 */ | ||
| 67 | |||
| 68 | #define S3C2410_LCDCON4_MVAL(x) ((x) << 8) | ||
| 69 | #define S3C2410_LCDCON4_HSPW(x) ((x) << 0) | ||
| 70 | #define S3C2410_LCDCON4_WLH(x) ((x) << 0) | ||
| 71 | |||
| 72 | #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) | ||
| 73 | |||
| 74 | #define S3C2410_LCDCON5_BPP24BL (1<<12) | ||
| 75 | #define S3C2410_LCDCON5_FRM565 (1<<11) | ||
| 76 | #define S3C2410_LCDCON5_INVVCLK (1<<10) | ||
| 77 | #define S3C2410_LCDCON5_INVVLINE (1<<9) | ||
| 78 | #define S3C2410_LCDCON5_INVVFRAME (1<<8) | ||
| 79 | #define S3C2410_LCDCON5_INVVD (1<<7) | ||
| 80 | #define S3C2410_LCDCON5_INVVDEN (1<<6) | ||
| 81 | #define S3C2410_LCDCON5_INVPWREN (1<<5) | ||
| 82 | #define S3C2410_LCDCON5_INVLEND (1<<4) | ||
| 83 | #define S3C2410_LCDCON5_PWREN (1<<3) | ||
| 84 | #define S3C2410_LCDCON5_ENLEND (1<<2) | ||
| 85 | #define S3C2410_LCDCON5_BSWP (1<<1) | ||
| 86 | #define S3C2410_LCDCON5_HWSWP (1<<0) | ||
| 87 | |||
| 88 | /* framebuffer start addressed */ | ||
| 89 | #define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14) | ||
| 90 | #define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18) | ||
| 91 | #define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C) | ||
| 92 | |||
| 93 | #define S3C2410_LCDBANK(x) ((x) << 21) | ||
| 94 | #define S3C2410_LCDBASEU(x) (x) | ||
| 95 | |||
| 96 | #define S3C2410_OFFSIZE(x) ((x) << 11) | ||
| 97 | #define S3C2410_PAGEWIDTH(x) (x) | ||
| 98 | |||
| 99 | /* colour lookup and miscellaneous controls */ | ||
| 100 | |||
| 101 | #define S3C2410_REDLUT S3C2410_LCDREG(0x20) | ||
| 102 | #define S3C2410_GREENLUT S3C2410_LCDREG(0x24) | ||
| 103 | #define S3C2410_BLUELUT S3C2410_LCDREG(0x28) | ||
| 104 | |||
| 105 | #define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) | ||
| 106 | #define S3C2410_TPAL S3C2410_LCDREG(0x50) | ||
| 107 | |||
| 108 | #define S3C2410_TPAL_EN (1<<24) | ||
| 109 | |||
| 110 | /* interrupt info */ | ||
| 111 | #define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) | ||
| 112 | #define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) | ||
| 113 | #define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) | ||
| 114 | #define S3C2410_LCDINT_FIWSEL (1<<2) | ||
| 115 | #define S3C2410_LCDINT_FRSYNC (1<<1) | ||
| 116 | #define S3C2410_LCDINT_FICNT (1<<0) | ||
| 117 | |||
| 118 | /* s3c2442 extra stn registers */ | ||
| 119 | |||
| 120 | #define S3C2442_REDLUT S3C2410_LCDREG(0x20) | ||
| 121 | #define S3C2442_GREENLUT S3C2410_LCDREG(0x24) | ||
| 122 | #define S3C2442_BLUELUT S3C2410_LCDREG(0x28) | ||
| 123 | #define S3C2442_DITHMODE S3C2410_LCDREG(0x20) | ||
| 124 | |||
| 125 | #define S3C2410_LPCSEL S3C2410_LCDREG(0x60) | ||
| 126 | |||
| 127 | #define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) | ||
| 128 | |||
| 129 | /* S3C2412 registers */ | ||
| 130 | |||
| 131 | #define S3C2412_TPAL S3C2410_LCDREG(0x20) | ||
| 132 | |||
| 133 | #define S3C2412_LCDINTPND S3C2410_LCDREG(0x24) | ||
| 134 | #define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28) | ||
| 135 | #define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C) | ||
| 136 | |||
| 137 | #define S3C2412_TCONSEL S3C2410_LCDREG(0x30) | ||
| 138 | |||
| 139 | #define S3C2412_LCDCON6 S3C2410_LCDREG(0x34) | ||
| 140 | #define S3C2412_LCDCON7 S3C2410_LCDREG(0x38) | ||
| 141 | #define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C) | ||
| 142 | #define S3C2412_LCDCON9 S3C2410_LCDREG(0x40) | ||
| 143 | |||
| 144 | #define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4)) | ||
| 145 | #define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4)) | ||
| 146 | #define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4)) | ||
| 147 | |||
| 148 | #define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4)) | ||
| 149 | |||
| 150 | /* general registers */ | ||
| 151 | |||
| 152 | /* base of the LCD registers, where INTPND, INTSRC and then INTMSK | ||
| 153 | * are available. */ | ||
| 154 | |||
| 155 | #define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54) | ||
| 156 | #define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24) | ||
| 157 | |||
| 158 | #define S3C24XX_LCDINTPND (0x00) | ||
| 159 | #define S3C24XX_LCDSRCPND (0x04) | ||
| 160 | #define S3C24XX_LCDINTMSK (0x08) | ||
| 161 | |||
| 162 | #endif /* ___ASM_ARCH_REGS_LCD_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h deleted file mode 100644 index 312ff93b63c6..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-mem.h +++ /dev/null | |||
| @@ -1,220 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-mem.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2410 Memory Control register definitions | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARM_MEMREGS_H | ||
| 14 | #define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $" | ||
| 15 | |||
| 16 | #ifndef S3C2410_MEMREG | ||
| 17 | #define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | /* bus width, and wait state control */ | ||
| 21 | #define S3C2410_BWSCON S3C2410_MEMREG(0x0000) | ||
| 22 | |||
| 23 | /* bank zero config - note, pinstrapped from OM pins! */ | ||
| 24 | #define S3C2410_BWSCON_DW0_16 (1<<1) | ||
| 25 | #define S3C2410_BWSCON_DW0_32 (2<<1) | ||
| 26 | |||
| 27 | /* bank one configs */ | ||
| 28 | #define S3C2410_BWSCON_DW1_8 (0<<4) | ||
| 29 | #define S3C2410_BWSCON_DW1_16 (1<<4) | ||
| 30 | #define S3C2410_BWSCON_DW1_32 (2<<4) | ||
| 31 | #define S3C2410_BWSCON_WS1 (1<<6) | ||
| 32 | #define S3C2410_BWSCON_ST1 (1<<7) | ||
| 33 | |||
| 34 | /* bank 2 configurations */ | ||
| 35 | #define S3C2410_BWSCON_DW2_8 (0<<8) | ||
| 36 | #define S3C2410_BWSCON_DW2_16 (1<<8) | ||
| 37 | #define S3C2410_BWSCON_DW2_32 (2<<8) | ||
| 38 | #define S3C2410_BWSCON_WS2 (1<<10) | ||
| 39 | #define S3C2410_BWSCON_ST2 (1<<11) | ||
| 40 | |||
| 41 | /* bank 3 configurations */ | ||
| 42 | #define S3C2410_BWSCON_DW3_8 (0<<12) | ||
| 43 | #define S3C2410_BWSCON_DW3_16 (1<<12) | ||
| 44 | #define S3C2410_BWSCON_DW3_32 (2<<12) | ||
| 45 | #define S3C2410_BWSCON_WS3 (1<<14) | ||
| 46 | #define S3C2410_BWSCON_ST3 (1<<15) | ||
| 47 | |||
| 48 | /* bank 4 configurations */ | ||
| 49 | #define S3C2410_BWSCON_DW4_8 (0<<16) | ||
| 50 | #define S3C2410_BWSCON_DW4_16 (1<<16) | ||
| 51 | #define S3C2410_BWSCON_DW4_32 (2<<16) | ||
| 52 | #define S3C2410_BWSCON_WS4 (1<<18) | ||
| 53 | #define S3C2410_BWSCON_ST4 (1<<19) | ||
| 54 | |||
| 55 | /* bank 5 configurations */ | ||
| 56 | #define S3C2410_BWSCON_DW5_8 (0<<20) | ||
| 57 | #define S3C2410_BWSCON_DW5_16 (1<<20) | ||
| 58 | #define S3C2410_BWSCON_DW5_32 (2<<20) | ||
| 59 | #define S3C2410_BWSCON_WS5 (1<<22) | ||
| 60 | #define S3C2410_BWSCON_ST5 (1<<23) | ||
| 61 | |||
| 62 | /* bank 6 configurations */ | ||
| 63 | #define S3C2410_BWSCON_DW6_8 (0<<24) | ||
| 64 | #define S3C2410_BWSCON_DW6_16 (1<<24) | ||
| 65 | #define S3C2410_BWSCON_DW6_32 (2<<24) | ||
| 66 | #define S3C2410_BWSCON_WS6 (1<<26) | ||
| 67 | #define S3C2410_BWSCON_ST6 (1<<27) | ||
| 68 | |||
| 69 | /* bank 7 configurations */ | ||
| 70 | #define S3C2410_BWSCON_DW7_8 (0<<28) | ||
| 71 | #define S3C2410_BWSCON_DW7_16 (1<<28) | ||
| 72 | #define S3C2410_BWSCON_DW7_32 (2<<28) | ||
| 73 | #define S3C2410_BWSCON_WS7 (1<<30) | ||
| 74 | #define S3C2410_BWSCON_ST7 (1<<31) | ||
| 75 | |||
| 76 | /* memory set (rom, ram) */ | ||
| 77 | #define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004) | ||
| 78 | #define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008) | ||
| 79 | #define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C) | ||
| 80 | #define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010) | ||
| 81 | #define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014) | ||
| 82 | #define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018) | ||
| 83 | #define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C) | ||
| 84 | #define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020) | ||
| 85 | |||
| 86 | /* bank configuration registers */ | ||
| 87 | |||
| 88 | #define S3C2410_BANKCON_PMCnorm (0x00) | ||
| 89 | #define S3C2410_BANKCON_PMC4 (0x01) | ||
| 90 | #define S3C2410_BANKCON_PMC8 (0x02) | ||
| 91 | #define S3C2410_BANKCON_PMC16 (0x03) | ||
| 92 | |||
| 93 | /* bank configurations for banks 0..7, note banks | ||
| 94 | * 6 and 7 have differnt configurations depending on | ||
| 95 | * the memory type bits */ | ||
| 96 | |||
| 97 | #define S3C2410_BANKCON_Tacp2 (0x0 << 2) | ||
| 98 | #define S3C2410_BANKCON_Tacp3 (0x1 << 2) | ||
| 99 | #define S3C2410_BANKCON_Tacp4 (0x2 << 2) | ||
| 100 | #define S3C2410_BANKCON_Tacp6 (0x3 << 2) | ||
| 101 | #define S3C2410_BANKCON_Tacp_SHIFT (2) | ||
| 102 | |||
| 103 | #define S3C2410_BANKCON_Tcah0 (0x0 << 4) | ||
| 104 | #define S3C2410_BANKCON_Tcah1 (0x1 << 4) | ||
| 105 | #define S3C2410_BANKCON_Tcah2 (0x2 << 4) | ||
| 106 | #define S3C2410_BANKCON_Tcah4 (0x3 << 4) | ||
| 107 | #define S3C2410_BANKCON_Tcah_SHIFT (4) | ||
| 108 | |||
| 109 | #define S3C2410_BANKCON_Tcoh0 (0x0 << 6) | ||
| 110 | #define S3C2410_BANKCON_Tcoh1 (0x1 << 6) | ||
| 111 | #define S3C2410_BANKCON_Tcoh2 (0x2 << 6) | ||
| 112 | #define S3C2410_BANKCON_Tcoh4 (0x3 << 6) | ||
| 113 | #define S3C2410_BANKCON_Tcoh_SHIFT (6) | ||
| 114 | |||
| 115 | #define S3C2410_BANKCON_Tacc1 (0x0 << 8) | ||
| 116 | #define S3C2410_BANKCON_Tacc2 (0x1 << 8) | ||
| 117 | #define S3C2410_BANKCON_Tacc3 (0x2 << 8) | ||
| 118 | #define S3C2410_BANKCON_Tacc4 (0x3 << 8) | ||
| 119 | #define S3C2410_BANKCON_Tacc6 (0x4 << 8) | ||
| 120 | #define S3C2410_BANKCON_Tacc8 (0x5 << 8) | ||
| 121 | #define S3C2410_BANKCON_Tacc10 (0x6 << 8) | ||
| 122 | #define S3C2410_BANKCON_Tacc14 (0x7 << 8) | ||
| 123 | #define S3C2410_BANKCON_Tacc_SHIFT (8) | ||
| 124 | |||
| 125 | #define S3C2410_BANKCON_Tcos0 (0x0 << 11) | ||
| 126 | #define S3C2410_BANKCON_Tcos1 (0x1 << 11) | ||
| 127 | #define S3C2410_BANKCON_Tcos2 (0x2 << 11) | ||
| 128 | #define S3C2410_BANKCON_Tcos4 (0x3 << 11) | ||
| 129 | #define S3C2410_BANKCON_Tcos_SHIFT (11) | ||
| 130 | |||
| 131 | #define S3C2410_BANKCON_Tacs0 (0x0 << 13) | ||
| 132 | #define S3C2410_BANKCON_Tacs1 (0x1 << 13) | ||
| 133 | #define S3C2410_BANKCON_Tacs2 (0x2 << 13) | ||
| 134 | #define S3C2410_BANKCON_Tacs4 (0x3 << 13) | ||
| 135 | #define S3C2410_BANKCON_Tacs_SHIFT (13) | ||
| 136 | |||
| 137 | #define S3C2410_BANKCON_SRAM (0x0 << 15) | ||
| 138 | #define S3C2400_BANKCON_EDODRAM (0x2 << 15) | ||
| 139 | #define S3C2410_BANKCON_SDRAM (0x3 << 15) | ||
| 140 | |||
| 141 | /* next bits only for EDO DRAM in 6,7 */ | ||
| 142 | #define S3C2400_BANKCON_EDO_Trcd1 (0x00 << 4) | ||
| 143 | #define S3C2400_BANKCON_EDO_Trcd2 (0x01 << 4) | ||
| 144 | #define S3C2400_BANKCON_EDO_Trcd3 (0x02 << 4) | ||
| 145 | #define S3C2400_BANKCON_EDO_Trcd4 (0x03 << 4) | ||
| 146 | |||
| 147 | /* CAS pulse width */ | ||
| 148 | #define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3) | ||
| 149 | #define S3C2400_BANKCON_EDO_PULSE2 (0x01 << 3) | ||
| 150 | |||
| 151 | /* CAS pre-charge */ | ||
| 152 | #define S3C2400_BANKCON_EDO_TCP1 (0x00 << 2) | ||
| 153 | #define S3C2400_BANKCON_EDO_TCP2 (0x01 << 2) | ||
| 154 | |||
| 155 | /* control column address select */ | ||
| 156 | #define S3C2400_BANKCON_EDO_SCANb8 (0x00 << 0) | ||
| 157 | #define S3C2400_BANKCON_EDO_SCANb9 (0x01 << 0) | ||
| 158 | #define S3C2400_BANKCON_EDO_SCANb10 (0x02 << 0) | ||
| 159 | #define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0) | ||
| 160 | |||
| 161 | /* next bits only for SDRAM in 6,7 */ | ||
| 162 | #define S3C2410_BANKCON_Trcd2 (0x00 << 2) | ||
| 163 | #define S3C2410_BANKCON_Trcd3 (0x01 << 2) | ||
| 164 | #define S3C2410_BANKCON_Trcd4 (0x02 << 2) | ||
| 165 | |||
| 166 | /* control column address select */ | ||
| 167 | #define S3C2410_BANKCON_SCANb8 (0x00 << 0) | ||
| 168 | #define S3C2410_BANKCON_SCANb9 (0x01 << 0) | ||
| 169 | #define S3C2410_BANKCON_SCANb10 (0x02 << 0) | ||
| 170 | |||
| 171 | #define S3C2410_REFRESH S3C2410_MEMREG(0x0024) | ||
| 172 | #define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028) | ||
| 173 | #define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C) | ||
| 174 | #define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030) | ||
| 175 | |||
| 176 | /* refresh control */ | ||
| 177 | |||
| 178 | #define S3C2410_REFRESH_REFEN (1<<23) | ||
| 179 | #define S3C2410_REFRESH_SELF (1<<22) | ||
| 180 | #define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1) | ||
| 181 | |||
| 182 | #define S3C2410_REFRESH_TRP_MASK (3<<20) | ||
| 183 | #define S3C2410_REFRESH_TRP_2clk (0<<20) | ||
| 184 | #define S3C2410_REFRESH_TRP_3clk (1<<20) | ||
| 185 | #define S3C2410_REFRESH_TRP_4clk (2<<20) | ||
| 186 | |||
| 187 | #define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20) | ||
| 188 | #define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20) | ||
| 189 | #define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20) | ||
| 190 | #define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20) | ||
| 191 | #define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20) | ||
| 192 | |||
| 193 | #define S3C2410_REFRESH_TSRC_MASK (3<<18) | ||
| 194 | #define S3C2410_REFRESH_TSRC_4clk (0<<18) | ||
| 195 | #define S3C2410_REFRESH_TSRC_5clk (1<<18) | ||
| 196 | #define S3C2410_REFRESH_TSRC_6clk (2<<18) | ||
| 197 | #define S3C2410_REFRESH_TSRC_7clk (3<<18) | ||
| 198 | |||
| 199 | |||
| 200 | /* mode select register(s) */ | ||
| 201 | |||
| 202 | #define S3C2410_MRSRB_CL1 (0x00 << 4) | ||
| 203 | #define S3C2410_MRSRB_CL2 (0x02 << 4) | ||
| 204 | #define S3C2410_MRSRB_CL3 (0x03 << 4) | ||
| 205 | |||
| 206 | /* bank size register */ | ||
| 207 | #define S3C2410_BANKSIZE_128M (0x2 << 0) | ||
| 208 | #define S3C2410_BANKSIZE_64M (0x1 << 0) | ||
| 209 | #define S3C2410_BANKSIZE_32M (0x0 << 0) | ||
| 210 | #define S3C2410_BANKSIZE_16M (0x7 << 0) | ||
| 211 | #define S3C2410_BANKSIZE_8M (0x6 << 0) | ||
| 212 | #define S3C2410_BANKSIZE_4M (0x5 << 0) | ||
| 213 | #define S3C2410_BANKSIZE_2M (0x4 << 0) | ||
| 214 | #define S3C2410_BANKSIZE_MASK (0x7 << 0) | ||
| 215 | #define S3C2400_BANKSIZE_MASK (0x4 << 0) | ||
| 216 | #define S3C2410_BANKSIZE_SCLK_EN (1<<4) | ||
| 217 | #define S3C2410_BANKSIZE_SCKE_EN (1<<5) | ||
| 218 | #define S3C2410_BANKSIZE_BURST (1<<7) | ||
| 219 | |||
| 220 | #endif /* __ASM_ARM_MEMREGS_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-power.h b/include/asm-arm/arch-s3c2410/regs-power.h deleted file mode 100644 index 13d13b7cfe98..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-power.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-power.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C24XX power control register definitions | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARM_REGS_PWR | ||
| 14 | #define __ASM_ARM_REGS_PWR __FILE__ | ||
| 15 | |||
| 16 | #define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR) | ||
| 17 | |||
| 18 | #define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) | ||
| 19 | #define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) | ||
| 20 | |||
| 21 | #define S3C2412_INFORM0 S3C24XX_PWRREG(0x70) | ||
| 22 | #define S3C2412_INFORM1 S3C24XX_PWRREG(0x74) | ||
| 23 | #define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) | ||
| 24 | #define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) | ||
| 25 | |||
| 26 | #define S3C2412_PWRCFG_BATF_IRQ (1<<0) | ||
| 27 | #define S3C2412_PWRCFG_BATF_IGNORE (2<<0) | ||
| 28 | #define S3C2412_PWRCFG_BATF_SLEEP (3<<0) | ||
| 29 | #define S3C2412_PWRCFG_BATF_MASK (3<<0) | ||
| 30 | |||
| 31 | #define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6) | ||
| 32 | #define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6) | ||
| 33 | #define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6) | ||
| 34 | #define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6) | ||
| 35 | #define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6) | ||
| 36 | |||
| 37 | #define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8) | ||
| 38 | #define S3C2412_PWRCFG_NAND_NORST (1<<9) | ||
| 39 | |||
| 40 | #endif /* __ASM_ARM_REGS_PWR */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h b/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h deleted file mode 100644 index c8c793e78936..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2008 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * S3C2412 memory register definitions | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARM_REGS_S3C2412_MEM | ||
| 15 | #define __ASM_ARM_REGS_S3C2412_MEM | ||
| 16 | |||
| 17 | #ifndef S3C2412_MEMREG | ||
| 18 | #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #define S3C2412_BANKCFG S3C2412_MEMREG(0x00) | ||
| 22 | #define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) | ||
| 23 | #define S3C2412_BANKCON2 S3C2412_MEMREG(0x08) | ||
| 24 | #define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C) | ||
| 25 | |||
| 26 | #define S3C2412_REFRESH S3C2412_MEMREG(0x10) | ||
| 27 | #define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) | ||
| 28 | |||
| 29 | #endif /* __ASM_ARM_REGS_S3C2412_MEM */ | ||
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412.h b/include/asm-arm/arch-s3c2410/regs-s3c2412.h deleted file mode 100644 index 783b18f5bcea..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-s3c2412.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-s3c2412.h | ||
| 2 | * | ||
| 3 | * Copyright 2007 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * S3C2412 specific register definitions | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_REGS_S3C2412_H | ||
| 15 | #define __ASM_ARCH_REGS_S3C2412_H "s3c2412" | ||
| 16 | |||
| 17 | #define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) | ||
| 18 | #define S3C2412_SWRST_RESET (0x533C2412) | ||
| 19 | |||
| 20 | /* see regs-power.h for the other registers in the power block. */ | ||
| 21 | |||
| 22 | #endif /* __ASM_ARCH_REGS_S3C2412_H */ | ||
| 23 | |||
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h deleted file mode 100644 index c1414658d1c5..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h +++ /dev/null | |||
| @@ -1,195 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2007 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * S3C2443 clock register definitions | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARM_REGS_S3C2443_CLOCK | ||
| 15 | #define __ASM_ARM_REGS_S3C2443_CLOCK | ||
| 16 | |||
| 17 | #define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) | ||
| 18 | |||
| 19 | #define S3C2443_PLLCON_MDIVSHIFT 16 | ||
| 20 | #define S3C2443_PLLCON_PDIVSHIFT 8 | ||
| 21 | #define S3C2443_PLLCON_SDIVSHIFT 0 | ||
| 22 | #define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1) | ||
| 23 | #define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1) | ||
| 24 | #define S3C2443_PLLCON_SDIVMASK (3) | ||
| 25 | |||
| 26 | #define S3C2443_MPLLCON S3C2443_CLKREG(0x10) | ||
| 27 | #define S3C2443_EPLLCON S3C2443_CLKREG(0x18) | ||
| 28 | #define S3C2443_CLKSRC S3C2443_CLKREG(0x20) | ||
| 29 | #define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24) | ||
| 30 | #define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28) | ||
| 31 | #define S3C2443_HCLKCON S3C2443_CLKREG(0x30) | ||
| 32 | #define S3C2443_PCLKCON S3C2443_CLKREG(0x34) | ||
| 33 | #define S3C2443_SCLKCON S3C2443_CLKREG(0x38) | ||
| 34 | #define S3C2443_PWRMODE S3C2443_CLKREG(0x40) | ||
| 35 | #define S3C2443_SWRST S3C2443_CLKREG(0x44) | ||
| 36 | #define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50) | ||
| 37 | #define S3C2443_SYSID S3C2443_CLKREG(0x5C) | ||
| 38 | #define S3C2443_PWRCFG S3C2443_CLKREG(0x60) | ||
| 39 | #define S3C2443_RSTCON S3C2443_CLKREG(0x64) | ||
| 40 | |||
| 41 | #define S3C2443_SWRST_RESET (0x533c2443) | ||
| 42 | |||
| 43 | #define S3C2443_PLLCON_OFF (1<<24) | ||
| 44 | |||
| 45 | #define S3C2443_CLKSRC_I2S_EXT (1<<14) | ||
| 46 | #define S3C2443_CLKSRC_I2S_EPLLDIV (0<<14) | ||
| 47 | #define S3C2443_CLKSRC_I2S_EPLLREF (2<<14) | ||
| 48 | #define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14) | ||
| 49 | #define S3C2443_CLKSRC_I2S_MASK (3<<14) | ||
| 50 | |||
| 51 | #define S3C2443_CLKSRC_EPLLREF_XTAL (2<<8) | ||
| 52 | #define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<8) | ||
| 53 | #define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<8) | ||
| 54 | #define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<8) | ||
| 55 | #define S3C2443_CLKSRC_EPLLREF_MASK (3<<8) | ||
| 56 | |||
| 57 | #define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6) | ||
| 58 | #define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4) | ||
| 59 | #define S3C2443_CLKSRC_EXTCLK_DIV (1<<3) | ||
| 60 | |||
| 61 | #define S3C2443_CLKDIV0_DVS (1<<13) | ||
| 62 | #define S3C2443_CLKDIV0_HALF_HCLK (1<<3) | ||
| 63 | #define S3C2443_CLKDIV0_HALF_PCLK (1<<2) | ||
| 64 | |||
| 65 | #define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0) | ||
| 66 | |||
| 67 | #define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6) | ||
| 68 | #define S3C2443_CLKDIV0_EXTDIV_SHIFT (6) | ||
| 69 | |||
| 70 | #define S3C2443_CLKDIV0_PREDIV_MASK (3<<4) | ||
| 71 | #define S3C2443_CLKDIV0_PREDIV_SHIFT (4) | ||
| 72 | |||
| 73 | #define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9) | ||
| 74 | #define S3C2443_CLKDIV0_ARMDIV_SHIFT (9) | ||
| 75 | #define S3C2443_CLKDIV0_ARMDIV_1 (0<<9) | ||
| 76 | #define S3C2443_CLKDIV0_ARMDIV_2 (8<<9) | ||
| 77 | #define S3C2443_CLKDIV0_ARMDIV_3 (2<<9) | ||
| 78 | #define S3C2443_CLKDIV0_ARMDIV_4 (9<<9) | ||
| 79 | #define S3C2443_CLKDIV0_ARMDIV_6 (10<<9) | ||
| 80 | #define S3C2443_CLKDIV0_ARMDIV_8 (11<<9) | ||
| 81 | #define S3C2443_CLKDIV0_ARMDIV_12 (13<<9) | ||
| 82 | #define S3C2443_CLKDIV0_ARMDIV_16 (15<<9) | ||
| 83 | |||
| 84 | /* S3C2443_CLKDIV1 */ | ||
| 85 | |||
| 86 | #define S3C2443_CLKDIV1_CAMDIV_MASK (15<<26) | ||
| 87 | #define S3C2443_CLKDIV1_CAMDIV_SHIFT (26) | ||
| 88 | |||
| 89 | #define S3C2443_CLKDIV1_HSSPIDIV_MASK (3<<24) | ||
| 90 | #define S3C2443_CLKDIV1_HSSPIDIV_SHIFT (24) | ||
| 91 | |||
| 92 | #define S3C2443_CLKDIV1_DISPDIV_MASK (0xff<<16) | ||
| 93 | #define S3C2443_CLKDIV1_DISPDIV_SHIFT (16) | ||
| 94 | |||
| 95 | #define S3C2443_CLKDIV1_I2SDIV_MASK (15<<12) | ||
| 96 | #define S3C2443_CLKDIV1_I2SDIV_SHIFT (12) | ||
| 97 | |||
| 98 | #define S3C2443_CLKDIV1_UARTDIV_MASK (15<<8) | ||
| 99 | #define S3C2443_CLKDIV1_UARTDIV_SHIFT (8) | ||
| 100 | |||
| 101 | #define S3C2443_CLKDIV1_HSMMCDIV_MASK (3<<6) | ||
| 102 | #define S3C2443_CLKDIV1_HSMMCDIV_SHIFT (6) | ||
| 103 | |||
| 104 | #define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4) | ||
| 105 | #define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4) | ||
| 106 | |||
| 107 | #define S3C2443_CLKCON_NAND | ||
| 108 | |||
| 109 | #define S3C2443_HCLKCON_DMA0 (1<<0) | ||
| 110 | #define S3C2443_HCLKCON_DMA1 (1<<1) | ||
| 111 | #define S3C2443_HCLKCON_DMA2 (1<<2) | ||
| 112 | #define S3C2443_HCLKCON_DMA3 (1<<3) | ||
| 113 | #define S3C2443_HCLKCON_DMA4 (1<<4) | ||
| 114 | #define S3C2443_HCLKCON_DMA5 (1<<5) | ||
| 115 | #define S3C2443_HCLKCON_CAMIF (1<<8) | ||
| 116 | #define S3C2443_HCLKCON_DISP (1<<9) | ||
| 117 | #define S3C2443_HCLKCON_LCDC (1<<10) | ||
| 118 | #define S3C2443_HCLKCON_USBH (1<<11) | ||
| 119 | #define S3C2443_HCLKCON_USBD (1<<12) | ||
| 120 | #define S3C2443_HCLKCON_HSMMC (1<<16) | ||
| 121 | #define S3C2443_HCLKCON_CFC (1<<17) | ||
| 122 | #define S3C2443_HCLKCON_SSMC (1<<18) | ||
| 123 | #define S3C2443_HCLKCON_DRAMC (1<<19) | ||
| 124 | |||
| 125 | #define S3C2443_PCLKCON_UART0 (1<<0) | ||
| 126 | #define S3C2443_PCLKCON_UART1 (1<<1) | ||
| 127 | #define S3C2443_PCLKCON_UART2 (1<<2) | ||
| 128 | #define S3C2443_PCLKCON_UART3 (1<<3) | ||
| 129 | #define S3C2443_PCLKCON_IIC (1<<4) | ||
| 130 | #define S3C2443_PCLKCON_SDI (1<<5) | ||
| 131 | #define S3C2443_PCLKCON_ADC (1<<7) | ||
| 132 | #define S3C2443_PCLKCON_AC97 (1<<8) | ||
| 133 | #define S3C2443_PCLKCON_IIS (1<<9) | ||
| 134 | #define S3C2443_PCLKCON_PWMT (1<<10) | ||
| 135 | #define S3C2443_PCLKCON_WDT (1<<11) | ||
| 136 | #define S3C2443_PCLKCON_RTC (1<<12) | ||
| 137 | #define S3C2443_PCLKCON_GPIO (1<<13) | ||
| 138 | #define S3C2443_PCLKCON_SPI0 (1<<14) | ||
| 139 | #define S3C2443_PCLKCON_SPI1 (1<<15) | ||
| 140 | |||
| 141 | #define S3C2443_SCLKCON_DDRCLK (1<<16) | ||
| 142 | #define S3C2443_SCLKCON_SSMCCLK (1<<15) | ||
| 143 | #define S3C2443_SCLKCON_HSSPICLK (1<<14) | ||
| 144 | #define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13) | ||
| 145 | #define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12) | ||
| 146 | #define S3C2443_SCLKCON_CAMCLK (1<<11) | ||
| 147 | #define S3C2443_SCLKCON_DISPCLK (1<<10) | ||
| 148 | #define S3C2443_SCLKCON_I2SCLK (1<<9) | ||
| 149 | #define S3C2443_SCLKCON_UARTCLK (1<<8) | ||
| 150 | #define S3C2443_SCLKCON_USBHOST (1<<1) | ||
| 151 | |||
| 152 | #include <asm/div64.h> | ||
| 153 | |||
| 154 | static inline unsigned int | ||
| 155 | s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk) | ||
| 156 | { | ||
| 157 | unsigned int mdiv, pdiv, sdiv; | ||
| 158 | uint64_t fvco; | ||
| 159 | |||
| 160 | mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; | ||
| 161 | pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; | ||
| 162 | sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; | ||
| 163 | |||
| 164 | mdiv &= S3C2443_PLLCON_MDIVMASK; | ||
| 165 | pdiv &= S3C2443_PLLCON_PDIVMASK; | ||
| 166 | sdiv &= S3C2443_PLLCON_SDIVMASK; | ||
| 167 | |||
| 168 | fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); | ||
| 169 | do_div(fvco, pdiv << sdiv); | ||
| 170 | |||
| 171 | return (unsigned int)fvco; | ||
| 172 | } | ||
| 173 | |||
| 174 | static inline unsigned int | ||
| 175 | s3c2443_get_epll(unsigned int pllval, unsigned int baseclk) | ||
| 176 | { | ||
| 177 | unsigned int mdiv, pdiv, sdiv; | ||
| 178 | uint64_t fvco; | ||
| 179 | |||
| 180 | mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; | ||
| 181 | pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; | ||
| 182 | sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; | ||
| 183 | |||
| 184 | mdiv &= S3C2443_PLLCON_MDIVMASK; | ||
| 185 | pdiv &= S3C2443_PLLCON_PDIVMASK; | ||
| 186 | sdiv &= S3C2443_PLLCON_SDIVMASK; | ||
| 187 | |||
| 188 | fvco = (uint64_t)baseclk * (mdiv + 8); | ||
| 189 | do_div(fvco, (pdiv + 2) << sdiv); | ||
| 190 | |||
| 191 | return (unsigned int)fvco; | ||
| 192 | } | ||
| 193 | |||
| 194 | #endif /* __ASM_ARM_REGS_S3C2443_CLOCK */ | ||
| 195 | |||
diff --git a/include/asm-arm/arch-s3c2410/regs-sdi.h b/include/asm-arm/arch-s3c2410/regs-sdi.h deleted file mode 100644 index bfb222fa4abb..000000000000 --- a/include/asm-arm/arch-s3c2410/regs-sdi.h +++ /dev/null | |||
| @@ -1,127 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-sdi.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2410 MMC/SDIO register definitions | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARM_REGS_SDI | ||
| 14 | #define __ASM_ARM_REGS_SDI "regs-sdi.h" | ||
| 15 | |||
| 16 | #define S3C2410_SDICON (0x00) | ||
| 17 | #define S3C2410_SDIPRE (0x04) | ||
| 18 | #define S3C2410_SDICMDARG (0x08) | ||
| 19 | #define S3C2410_SDICMDCON (0x0C) | ||
| 20 | #define S3C2410_SDICMDSTAT (0x10) | ||
| 21 | #define S3C2410_SDIRSP0 (0x14) | ||
| 22 | #define S3C2410_SDIRSP1 (0x18) | ||
| 23 | #define S3C2410_SDIRSP2 (0x1C) | ||
| 24 | #define S3C2410_SDIRSP3 (0x20) | ||
| 25 | #define S3C2410_SDITIMER (0x24) | ||
| 26 | #define S3C2410_SDIBSIZE (0x28) | ||
| 27 | #define S3C2410_SDIDCON (0x2C) | ||
| 28 | #define S3C2410_SDIDCNT (0x30) | ||
| 29 | #define S3C2410_SDIDSTA (0x34) | ||
| 30 | #define S3C2410_SDIFSTA (0x38) | ||
| 31 | |||
| 32 | #define S3C2410_SDIDATA (0x3C) | ||
| 33 | #define S3C2410_SDIIMSK (0x40) | ||
| 34 | |||
| 35 | #define S3C2440_SDIDATA (0x40) | ||
| 36 | #define S3C2440_SDIIMSK (0x3C) | ||
| 37 | |||
| 38 | #define S3C2440_SDICON_SDRESET (1<<8) | ||
| 39 | #define S3C2440_SDICON_MMCCLOCK (1<<5) | ||
| 40 | #define S3C2410_SDICON_BYTEORDER (1<<4) | ||
| 41 | #define S3C2410_SDICON_SDIOIRQ (1<<3) | ||
| 42 | #define S3C2410_SDICON_RWAITEN (1<<2) | ||
| 43 | #define S3C2410_SDICON_FIFORESET (1<<1) | ||
| 44 | #define S3C2410_SDICON_CLOCKTYPE (1<<0) | ||
| 45 | |||
| 46 | #define S3C2410_SDICMDCON_ABORT (1<<12) | ||
| 47 | #define S3C2410_SDICMDCON_WITHDATA (1<<11) | ||
| 48 | #define S3C2410_SDICMDCON_LONGRSP (1<<10) | ||
| 49 | #define S3C2410_SDICMDCON_WAITRSP (1<<9) | ||
| 50 | #define S3C2410_SDICMDCON_CMDSTART (1<<8) | ||
| 51 | #define S3C2410_SDICMDCON_SENDERHOST (1<<6) | ||
| 52 | #define S3C2410_SDICMDCON_INDEX (0x3f) | ||
| 53 | |||
| 54 | #define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) | ||
| 55 | #define S3C2410_SDICMDSTAT_CMDSENT (1<<11) | ||
| 56 | #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) | ||
| 57 | #define S3C2410_SDICMDSTAT_RSPFIN (1<<9) | ||
| 58 | #define S3C2410_SDICMDSTAT_XFERING (1<<8) | ||
| 59 | #define S3C2410_SDICMDSTAT_INDEX (0xff) | ||
| 60 | |||
| 61 | #define S3C2440_SDIDCON_DS_BYTE (0<<22) | ||
| 62 | #define S3C2440_SDIDCON_DS_HALFWORD (1<<22) | ||
| 63 | #define S3C2440_SDIDCON_DS_WORD (2<<22) | ||
| 64 | #define S3C2410_SDIDCON_IRQPERIOD (1<<21) | ||
| 65 | #define S3C2410_SDIDCON_TXAFTERRESP (1<<20) | ||
| 66 | #define S3C2410_SDIDCON_RXAFTERCMD (1<<19) | ||
| 67 | #define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) | ||
| 68 | #define S3C2410_SDIDCON_BLOCKMODE (1<<17) | ||
| 69 | #define S3C2410_SDIDCON_WIDEBUS (1<<16) | ||
| 70 | #define S3C2410_SDIDCON_DMAEN (1<<15) | ||
| 71 | #define S3C2410_SDIDCON_STOP (1<<14) | ||
| 72 | #define S3C2440_SDIDCON_DATSTART (1<<14) | ||
| 73 | #define S3C2410_SDIDCON_DATMODE (3<<12) | ||
| 74 | #define S3C2410_SDIDCON_BLKNUM (0x7ff) | ||
| 75 | |||
| 76 | /* constants for S3C2410_SDIDCON_DATMODE */ | ||
| 77 | #define S3C2410_SDIDCON_XFER_READY (0<<12) | ||
| 78 | #define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) | ||
| 79 | #define S3C2410_SDIDCON_XFER_RXSTART (2<<12) | ||
| 80 | #define S3C2410_SDIDCON_XFER_TXSTART (3<<12) | ||
| 81 | |||
| 82 | #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF) | ||
| 83 | #define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) | ||
| 84 | |||
| 85 | #define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) | ||
| 86 | #define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) | ||
| 87 | #define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ | ||
| 88 | #define S3C2410_SDIDSTA_CRCFAIL (1<<7) | ||
| 89 | #define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) | ||
| 90 | #define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) | ||
| 91 | #define S3C2410_SDIDSTA_XFERFINISH (1<<4) | ||
| 92 | #define S3C2410_SDIDSTA_BUSYFINISH (1<<3) | ||
| 93 | #define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ | ||
| 94 | #define S3C2410_SDIDSTA_TXDATAON (1<<1) | ||
| 95 | #define S3C2410_SDIDSTA_RXDATAON (1<<0) | ||
| 96 | |||
| 97 | #define S3C2440_SDIFSTA_FIFORESET (1<<16) | ||
| 98 | #define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ | ||
| 99 | #define S3C2410_SDIFSTA_TFDET (1<<13) | ||
| 100 | #define S3C2410_SDIFSTA_RFDET (1<<12) | ||
| 101 | #define S3C2410_SDIFSTA_TFHALF (1<<11) | ||
| 102 | #define S3C2410_SDIFSTA_TFEMPTY (1<<10) | ||
| 103 | #define S3C2410_SDIFSTA_RFLAST (1<<9) | ||
| 104 | #define S3C2410_SDIFSTA_RFFULL (1<<8) | ||
| 105 | #define S3C2410_SDIFSTA_RFHALF (1<<7) | ||
| 106 | #define S3C2410_SDIFSTA_COUNTMASK (0x7f) | ||
| 107 | |||
| 108 | #define S3C2410_SDIIMSK_RESPONSECRC (1<<17) | ||
| 109 | #define S3C2410_SDIIMSK_CMDSENT (1<<16) | ||
| 110 | #define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) | ||
| 111 | #define S3C2410_SDIIMSK_RESPONSEND (1<<14) | ||
| 112 | #define S3C2410_SDIIMSK_READWAIT (1<<13) | ||
| 113 | #define S3C2410_SDIIMSK_SDIOIRQ (1<<12) | ||
| 114 | #define S3C2410_SDIIMSK_FIFOFAIL (1<<11) | ||
| 115 | #define S3C2410_SDIIMSK_CRCSTATUS (1<<10) | ||
| 116 | #define S3C2410_SDIIMSK_DATACRC (1<<9) | ||
| 117 | #define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) | ||
| 118 | #define S3C2410_SDIIMSK_DATAFINISH (1<<7) | ||
| 119 | #define S3C2410_SDIIMSK_BUSYFINISH (1<<6) | ||
| 120 | #define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ | ||
| 121 | #define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) | ||
| 122 | #define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) | ||
| 123 | #define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) | ||
| 124 | #define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) | ||
| 125 | #define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) | ||
| 126 | |||
| 127 | #endif /* __ASM_ARM_REGS_SDI */ | ||
diff --git a/include/asm-arm/arch-s3c2410/reset.h b/include/asm-arm/arch-s3c2410/reset.h deleted file mode 100644 index 4f866cdecab0..000000000000 --- a/include/asm-arm/arch-s3c2410/reset.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/reset.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2007 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * S3C2410 CPU reset controls | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_RESET_H | ||
| 15 | #define __ASM_ARCH_RESET_H __FILE__ | ||
| 16 | |||
| 17 | /* This allows the over-ride of the default reset code | ||
| 18 | */ | ||
| 19 | |||
| 20 | extern void (*s3c24xx_reset_hook)(void); | ||
| 21 | |||
| 22 | #endif /* __ASM_ARCH_RESET_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/spi-gpio.h b/include/asm-arm/arch-s3c2410/spi-gpio.h deleted file mode 100644 index 73803731142a..000000000000 --- a/include/asm-arm/arch-s3c2410/spi-gpio.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/spi-gpio.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2006 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C2410 - SPI Controller platfrom_device info | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_SPIGPIO_H | ||
| 14 | #define __ASM_ARCH_SPIGPIO_H __FILE__ | ||
| 15 | |||
| 16 | struct s3c2410_spigpio_info { | ||
| 17 | unsigned long pin_clk; | ||
| 18 | unsigned long pin_mosi; | ||
| 19 | unsigned long pin_miso; | ||
| 20 | |||
| 21 | int bus_num; | ||
| 22 | |||
| 23 | void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs); | ||
| 24 | }; | ||
| 25 | |||
| 26 | |||
| 27 | #endif /* __ASM_ARCH_SPIGPIO_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/spi.h b/include/asm-arm/arch-s3c2410/spi.h deleted file mode 100644 index 442169887d3b..000000000000 --- a/include/asm-arm/arch-s3c2410/spi.h +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/spi.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2006 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C2410 - SPI Controller platform_device info | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_SPI_H | ||
| 14 | #define __ASM_ARCH_SPI_H __FILE__ | ||
| 15 | |||
| 16 | struct s3c2410_spi_info { | ||
| 17 | unsigned long pin_cs; /* simple gpio cs */ | ||
| 18 | unsigned int num_cs; /* total chipselects */ | ||
| 19 | int bus_num; /* bus number to use. */ | ||
| 20 | |||
| 21 | void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); | ||
| 22 | }; | ||
| 23 | |||
| 24 | |||
| 25 | #endif /* __ASM_ARCH_SPI_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/system-reset.h b/include/asm-arm/arch-s3c2410/system-reset.h deleted file mode 100644 index beeec770dcf7..000000000000 --- a/include/asm-arm/arch-s3c2410/system-reset.h +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/system-reset.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2008 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C2410 - System define for arch_reset() function | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <asm/arch/hardware.h> | ||
| 14 | #include <asm/io.h> | ||
| 15 | |||
| 16 | #include <asm/plat-s3c/regs-watchdog.h> | ||
| 17 | #include <asm/arch/regs-clock.h> | ||
| 18 | |||
| 19 | #include <linux/clk.h> | ||
| 20 | #include <linux/err.h> | ||
| 21 | |||
| 22 | extern void (*s3c24xx_reset_hook)(void); | ||
| 23 | |||
| 24 | static void | ||
| 25 | arch_reset(char mode) | ||
| 26 | { | ||
| 27 | struct clk *wdtclk; | ||
| 28 | |||
| 29 | if (mode == 's') { | ||
| 30 | cpu_reset(0); | ||
| 31 | } | ||
| 32 | |||
| 33 | if (s3c24xx_reset_hook) | ||
| 34 | s3c24xx_reset_hook(); | ||
| 35 | |||
| 36 | printk("arch_reset: attempting watchdog reset\n"); | ||
| 37 | |||
| 38 | __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ | ||
| 39 | |||
| 40 | wdtclk = clk_get(NULL, "watchdog"); | ||
| 41 | if (!IS_ERR(wdtclk)) { | ||
| 42 | clk_enable(wdtclk); | ||
| 43 | } else | ||
| 44 | printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); | ||
| 45 | |||
| 46 | /* put initial values into count and data */ | ||
| 47 | __raw_writel(0x80, S3C2410_WTCNT); | ||
| 48 | __raw_writel(0x80, S3C2410_WTDAT); | ||
| 49 | |||
| 50 | /* set the watchdog to go and reset... */ | ||
| 51 | __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | | ||
| 52 | S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); | ||
| 53 | |||
| 54 | /* wait for reset to assert... */ | ||
| 55 | mdelay(500); | ||
| 56 | |||
| 57 | printk(KERN_ERR "Watchdog reset failed to assert reset\n"); | ||
| 58 | |||
| 59 | /* delay to allow the serial port to show the message */ | ||
| 60 | mdelay(50); | ||
| 61 | |||
| 62 | /* we'll take a jump through zero as a poor second */ | ||
| 63 | cpu_reset(0); | ||
| 64 | } | ||
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h deleted file mode 100644 index 98f690e7d33e..000000000000 --- a/include/asm-arm/arch-s3c2410/system.h +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/system.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C2410 - System function defines and includes | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <asm/arch/hardware.h> | ||
| 14 | #include <asm/io.h> | ||
| 15 | |||
| 16 | #include <asm/arch/map.h> | ||
| 17 | #include <asm/arch/idle.h> | ||
| 18 | #include <asm/arch/reset.h> | ||
| 19 | |||
| 20 | #include <asm/arch/regs-clock.h> | ||
| 21 | |||
| 22 | void (*s3c24xx_idle)(void); | ||
| 23 | void (*s3c24xx_reset_hook)(void); | ||
| 24 | |||
| 25 | void s3c24xx_default_idle(void) | ||
| 26 | { | ||
| 27 | unsigned long tmp; | ||
| 28 | int i; | ||
| 29 | |||
| 30 | /* idle the system by using the idle mode which will wait for an | ||
| 31 | * interrupt to happen before restarting the system. | ||
| 32 | */ | ||
| 33 | |||
| 34 | /* Warning: going into idle state upsets jtag scanning */ | ||
| 35 | |||
| 36 | __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE, | ||
| 37 | S3C2410_CLKCON); | ||
| 38 | |||
| 39 | /* the samsung port seems to do a loop and then unset idle.. */ | ||
| 40 | for (i = 0; i < 50; i++) { | ||
| 41 | tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */ | ||
| 42 | } | ||
| 43 | |||
| 44 | /* this bit is not cleared on re-start... */ | ||
| 45 | |||
| 46 | __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE, | ||
| 47 | S3C2410_CLKCON); | ||
| 48 | } | ||
| 49 | |||
| 50 | static void arch_idle(void) | ||
| 51 | { | ||
| 52 | if (s3c24xx_idle != NULL) | ||
| 53 | (s3c24xx_idle)(); | ||
| 54 | else | ||
| 55 | s3c24xx_default_idle(); | ||
| 56 | } | ||
| 57 | |||
| 58 | #include <asm/arch/system-reset.h> | ||
diff --git a/include/asm-arm/arch-s3c2410/timex.h b/include/asm-arm/arch-s3c2410/timex.h deleted file mode 100644 index c16a99c5a59a..000000000000 --- a/include/asm-arm/arch-s3c2410/timex.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/timex.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C2410 - time parameters | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 14 | #define __ASM_ARCH_TIMEX_H | ||
| 15 | |||
| 16 | /* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it | ||
| 17 | * a variable is useless. It seems as long as we make our timers an | ||
| 18 | * exact multiple of HZ, any value that makes a 1->1 correspondence | ||
| 19 | * for the time conversion functions to/from jiffies is acceptable. | ||
| 20 | */ | ||
| 21 | |||
| 22 | |||
| 23 | #define CLOCK_TICK_RATE 12000000 | ||
| 24 | |||
| 25 | |||
| 26 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h deleted file mode 100644 index 48a5731ee988..000000000000 --- a/include/asm-arm/arch-s3c2410/uncompress.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/uncompress.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003, 2007 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * S3C2410 - uncompress code | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
| 15 | #define __ASM_ARCH_UNCOMPRESS_H | ||
| 16 | |||
| 17 | #include <asm/arch/regs-gpio.h> | ||
| 18 | #include <asm/arch/map.h> | ||
| 19 | |||
| 20 | /* working in physical space... */ | ||
| 21 | #undef S3C2410_GPIOREG | ||
| 22 | #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x))) | ||
| 23 | |||
| 24 | #include <asm/plat-s3c/uncompress.h> | ||
| 25 | |||
| 26 | static inline int is_arm926(void) | ||
| 27 | { | ||
| 28 | unsigned int cpuid; | ||
| 29 | |||
| 30 | asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid)); | ||
| 31 | |||
| 32 | return ((cpuid & 0xff0) == 0x260); | ||
| 33 | } | ||
| 34 | |||
| 35 | static void arch_detect_cpu(void) | ||
| 36 | { | ||
| 37 | unsigned int cpuid; | ||
| 38 | |||
| 39 | cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1); | ||
| 40 | cpuid &= S3C2410_GSTATUS1_IDMASK; | ||
| 41 | |||
| 42 | if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || | ||
| 43 | cpuid == S3C2410_GSTATUS1_2442) { | ||
| 44 | fifo_mask = S3C2440_UFSTAT_TXMASK; | ||
| 45 | fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; | ||
| 46 | } else { | ||
| 47 | fifo_mask = S3C2410_UFSTAT_TXMASK; | ||
| 48 | fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT; | ||
| 49 | } | ||
| 50 | } | ||
| 51 | |||
| 52 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/usb-control.h b/include/asm-arm/arch-s3c2410/usb-control.h deleted file mode 100644 index 5bfa376e33dc..000000000000 --- a/include/asm-arm/arch-s3c2410/usb-control.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/usb-control.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C2410 - usb port information | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_USBCONTROL_H | ||
| 14 | #define __ASM_ARCH_USBCONTROL_H "include/asm-arm/arch-s3c2410/usb-control.h" | ||
| 15 | |||
| 16 | #define S3C_HCDFLG_USED (1) | ||
| 17 | |||
| 18 | struct s3c2410_hcd_port { | ||
| 19 | unsigned char flags; | ||
| 20 | unsigned char power; | ||
| 21 | unsigned char oc_status; | ||
| 22 | unsigned char oc_changed; | ||
| 23 | }; | ||
| 24 | |||
| 25 | struct s3c2410_hcd_info { | ||
| 26 | struct usb_hcd *hcd; | ||
| 27 | struct s3c2410_hcd_port port[2]; | ||
| 28 | |||
| 29 | void (*power_control)(int port, int to); | ||
| 30 | void (*enable_oc)(struct s3c2410_hcd_info *, int on); | ||
| 31 | void (*report_oc)(struct s3c2410_hcd_info *, int ports); | ||
| 32 | }; | ||
| 33 | |||
| 34 | static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports) | ||
| 35 | { | ||
| 36 | if (info->report_oc != NULL) { | ||
| 37 | (info->report_oc)(info, ports); | ||
| 38 | } | ||
| 39 | } | ||
| 40 | |||
| 41 | #endif /*__ASM_ARCH_USBCONTROL_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/vmalloc.h b/include/asm-arm/arch-s3c2410/vmalloc.h deleted file mode 100644 index 0ae3bdb7e03b..000000000000 --- a/include/asm-arm/arch-s3c2410/vmalloc.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/vmalloc.h | ||
| 2 | * | ||
| 3 | * from linux/include/asm-arm/arch-iop3xx/vmalloc.h | ||
| 4 | * | ||
| 5 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
| 6 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | * S3C2410 vmalloc definition | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_VMALLOC_H | ||
| 16 | #define __ASM_ARCH_VMALLOC_H | ||
| 17 | |||
| 18 | #define VMALLOC_END (0xE0000000) | ||
| 19 | |||
| 20 | #endif /* __ASM_ARCH_VMALLOC_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/vr1000-cpld.h b/include/asm-arm/arch-s3c2410/vr1000-cpld.h deleted file mode 100644 index 0557b0a5ab1d..000000000000 --- a/include/asm-arm/arch-s3c2410/vr1000-cpld.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/vr1000-cpld.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * VR1000 - CPLD control constants | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_VR1000CPLD_H | ||
| 14 | #define __ASM_ARCH_VR1000CPLD_H | ||
| 15 | |||
| 16 | #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */ | ||
| 17 | |||
| 18 | #endif /* __ASM_ARCH_VR1000CPLD_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/vr1000-irq.h b/include/asm-arm/arch-s3c2410/vr1000-irq.h deleted file mode 100644 index 890937083c61..000000000000 --- a/include/asm-arm/arch-s3c2410/vr1000-irq.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/vr1000-irq.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * Machine VR1000 - IRQ Number definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_VR1000IRQ_H | ||
| 14 | #define __ASM_ARCH_VR1000IRQ_H | ||
| 15 | |||
| 16 | /* irq numbers to onboard peripherals */ | ||
| 17 | |||
| 18 | #define IRQ_USBOC IRQ_EINT19 | ||
| 19 | #define IRQ_IDE0 IRQ_EINT16 | ||
| 20 | #define IRQ_IDE1 IRQ_EINT17 | ||
| 21 | #define IRQ_VR1000_SERIAL IRQ_EINT12 | ||
| 22 | #define IRQ_VR1000_DM9000A IRQ_EINT10 | ||
| 23 | #define IRQ_VR1000_DM9000N IRQ_EINT9 | ||
| 24 | #define IRQ_SMALERT IRQ_EINT8 | ||
| 25 | |||
| 26 | #endif /* __ASM_ARCH_VR1000IRQ_H */ | ||
diff --git a/include/asm-arm/arch-s3c2410/vr1000-map.h b/include/asm-arm/arch-s3c2410/vr1000-map.h deleted file mode 100644 index 92a56a724a8c..000000000000 --- a/include/asm-arm/arch-s3c2410/vr1000-map.h +++ /dev/null | |||
| @@ -1,110 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/vr1000-map.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * Machine VR1000 - Memory map definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* needs arch/map.h including with this */ | ||
| 14 | |||
| 15 | /* ok, we've used up to 0x13000000, now we need to find space for the | ||
| 16 | * peripherals that live in the nGCS[x] areas, which are quite numerous | ||
| 17 | * in their space. We also have the board's CPLD to find register space | ||
| 18 | * for. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_VR1000MAP_H | ||
| 22 | #define __ASM_ARCH_VR1000MAP_H | ||
| 23 | |||
| 24 | #include <asm/arch/bast-map.h> | ||
| 25 | |||
| 26 | #define VR1000_IOADDR(x) BAST_IOADDR(x) | ||
| 27 | |||
| 28 | /* we put the CPLD registers next, to get them out of the way */ | ||
| 29 | |||
| 30 | #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */ | ||
| 31 | #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000) | ||
| 32 | |||
| 33 | #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */ | ||
| 34 | #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000) | ||
| 35 | |||
| 36 | #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */ | ||
| 37 | #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000) | ||
| 38 | |||
| 39 | #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */ | ||
| 40 | #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000) | ||
| 41 | |||
| 42 | /* next, we have the PC104 ISA interrupt registers */ | ||
| 43 | |||
| 44 | #define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ | ||
| 45 | #define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000) | ||
| 46 | |||
| 47 | #define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ | ||
| 48 | #define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000) | ||
| 49 | |||
| 50 | #define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ | ||
| 51 | #define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000) | ||
| 52 | |||
| 53 | /* 0xE0000000 contains the IO space that is split by speed and | ||
| 54 | * wether the access is for 8 or 16bit IO... this ensures that | ||
| 55 | * the correct access is made | ||
| 56 | * | ||
| 57 | * 0x10000000 of space, partitioned as so: | ||
| 58 | * | ||
| 59 | * 0x00000000 to 0x04000000 8bit, slow | ||
| 60 | * 0x04000000 to 0x08000000 16bit, slow | ||
| 61 | * 0x08000000 to 0x0C000000 16bit, net | ||
| 62 | * 0x0C000000 to 0x10000000 16bit, fast | ||
| 63 | * | ||
| 64 | * each of these spaces has the following in: | ||
| 65 | * | ||
| 66 | * 0x02000000 to 0x02100000 1MB IDE primary channel | ||
| 67 | * 0x02100000 to 0x02200000 1MB IDE primary channel aux | ||
| 68 | * 0x02200000 to 0x02400000 1MB IDE secondary channel | ||
| 69 | * 0x02300000 to 0x02400000 1MB IDE secondary channel aux | ||
| 70 | * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers | ||
| 71 | * 0x02600000 to 0x02700000 1MB | ||
| 72 | * | ||
| 73 | * the phyiscal layout of the zones are: | ||
| 74 | * nGCS2 - 8bit, slow | ||
| 75 | * nGCS3 - 16bit, slow | ||
| 76 | * nGCS4 - 16bit, net | ||
| 77 | * nGCS5 - 16bit, fast | ||
| 78 | */ | ||
| 79 | |||
| 80 | #define VR1000_VA_MULTISPACE (0xE0000000) | ||
| 81 | |||
| 82 | #define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000) | ||
| 83 | #define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000) | ||
| 84 | #define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000) | ||
| 85 | #define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000) | ||
| 86 | #define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000) | ||
| 87 | #define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000) | ||
| 88 | #define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000) | ||
| 89 | #define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000) | ||
| 90 | #define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000) | ||
| 91 | |||
| 92 | /* physical offset addresses for the peripherals */ | ||
| 93 | |||
| 94 | #define VR1000_PA_IDEPRI (0x02000000) | ||
| 95 | #define VR1000_PA_IDEPRIAUX (0x02800000) | ||
| 96 | #define VR1000_PA_IDESEC (0x03000000) | ||
| 97 | #define VR1000_PA_IDESECAUX (0x03800000) | ||
| 98 | #define VR1000_PA_DM9000 (0x05000000) | ||
| 99 | |||
| 100 | #define VR1000_PA_SERIAL (0x11800000) | ||
| 101 | #define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000)) | ||
| 102 | |||
| 103 | /* VR1000 ram is in CS1, with A26..A24 = 2_101 */ | ||
| 104 | #define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000) | ||
| 105 | |||
| 106 | /* some configurations for the peripherals */ | ||
| 107 | |||
| 108 | #define VR1000_DM9000_CS VR1000_VAM_CS4 | ||
| 109 | |||
| 110 | #endif /* __ASM_ARCH_VR1000MAP_H */ | ||
diff --git a/include/asm-arm/arch-sa1100/SA-1100.h b/include/asm-arm/arch-sa1100/SA-1100.h deleted file mode 100644 index 62aaf04a3906..000000000000 --- a/include/asm-arm/arch-sa1100/SA-1100.h +++ /dev/null | |||
| @@ -1,2072 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * FILE SA-1100.h | ||
| 3 | * | ||
| 4 | * Version 1.2 | ||
| 5 | * Author Copyright (c) Marc A. Viredaz, 1998 | ||
| 6 | * DEC Western Research Laboratory, Palo Alto, CA | ||
| 7 | * Date January 1998 (April 1997) | ||
| 8 | * System StrongARM SA-1100 | ||
| 9 | * Language C or ARM Assembly | ||
| 10 | * Purpose Definition of constants related to the StrongARM | ||
| 11 | * SA-1100 microprocessor (Advanced RISC Machine (ARM) | ||
| 12 | * architecture version 4). This file is based on the | ||
| 13 | * StrongARM SA-1100 data sheet version 2.2. | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | |||
| 18 | /* Be sure that virtual mapping is defined right */ | ||
| 19 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 20 | #error You must include hardware.h not SA-1100.h | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #include "bitfield.h" | ||
| 24 | |||
| 25 | /* | ||
| 26 | * SA1100 CS line to physical address | ||
| 27 | */ | ||
| 28 | |||
| 29 | #define SA1100_CS0_PHYS 0x00000000 | ||
| 30 | #define SA1100_CS1_PHYS 0x08000000 | ||
| 31 | #define SA1100_CS2_PHYS 0x10000000 | ||
| 32 | #define SA1100_CS3_PHYS 0x18000000 | ||
| 33 | #define SA1100_CS4_PHYS 0x40000000 | ||
| 34 | #define SA1100_CS5_PHYS 0x48000000 | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Personal Computer Memory Card International Association (PCMCIA) sockets | ||
| 38 | */ | ||
| 39 | |||
| 40 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | ||
| 41 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | ||
| 42 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | ||
| 43 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | ||
| 44 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | ||
| 45 | |||
| 46 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | ||
| 47 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | ||
| 48 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | ||
| 49 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | ||
| 50 | |||
| 51 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | ||
| 52 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | ||
| 53 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | ||
| 54 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | ||
| 55 | |||
| 56 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | ||
| 57 | (0x20000000 + (Nb)*PCMCIASp) | ||
| 58 | #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ | ||
| 59 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | ||
| 60 | (_PCMCIA (Nb) + 2*PCMCIAPrtSp) | ||
| 61 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | ||
| 62 | (_PCMCIA (Nb) + 3*PCMCIAPrtSp) | ||
| 63 | |||
| 64 | #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ | ||
| 65 | #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ | ||
| 66 | #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ | ||
| 67 | #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ | ||
| 68 | |||
| 69 | #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ | ||
| 70 | #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ | ||
| 71 | #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ | ||
| 72 | #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ | ||
| 73 | |||
| 74 | |||
| 75 | /* | ||
| 76 | * Universal Serial Bus (USB) Device Controller (UDC) control registers | ||
| 77 | * | ||
| 78 | * Registers | ||
| 79 | * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device | ||
| 80 | * Controller (UDC) Control Register (read/write). | ||
| 81 | * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device | ||
| 82 | * Controller (UDC) Address Register (read/write). | ||
| 83 | * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device | ||
| 84 | * Controller (UDC) Output Maximum Packet size register | ||
| 85 | * (read/write). | ||
| 86 | * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device | ||
| 87 | * Controller (UDC) Input Maximum Packet size register | ||
| 88 | * (read/write). | ||
| 89 | * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device | ||
| 90 | * Controller (UDC) Control/Status register end-point 0 | ||
| 91 | * (read/write). | ||
| 92 | * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device | ||
| 93 | * Controller (UDC) Control/Status register end-point 1 | ||
| 94 | * (output, read/write). | ||
| 95 | * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device | ||
| 96 | * Controller (UDC) Control/Status register end-point 2 | ||
| 97 | * (input, read/write). | ||
| 98 | * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device | ||
| 99 | * Controller (UDC) Data register end-point 0 | ||
| 100 | * (read/write). | ||
| 101 | * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device | ||
| 102 | * Controller (UDC) Write Count register end-point 0 | ||
| 103 | * (read). | ||
| 104 | * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device | ||
| 105 | * Controller (UDC) Data Register (read/write). | ||
| 106 | * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device | ||
| 107 | * Controller (UDC) Status Register (read/write). | ||
| 108 | */ | ||
| 109 | |||
| 110 | #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */ | ||
| 111 | #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */ | ||
| 112 | #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */ | ||
| 113 | #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */ | ||
| 114 | #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ | ||
| 115 | #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */ | ||
| 116 | #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */ | ||
| 117 | #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */ | ||
| 118 | #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */ | ||
| 119 | #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */ | ||
| 120 | #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */ | ||
| 121 | |||
| 122 | #define UDCCR_UDD 0x00000001 /* UDC Disable */ | ||
| 123 | #define UDCCR_UDA 0x00000002 /* UDC Active (read) */ | ||
| 124 | #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ | ||
| 125 | #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ | ||
| 126 | /* (disable) */ | ||
| 127 | #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ | ||
| 128 | /* (disable) */ | ||
| 129 | #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ | ||
| 130 | /* (disable) */ | ||
| 131 | #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ | ||
| 132 | /* (disable) */ | ||
| 133 | #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ | ||
| 134 | #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ | ||
| 135 | |||
| 136 | #define UDCAR_ADD Fld (7, 0) /* function ADDress */ | ||
| 137 | |||
| 138 | #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ | ||
| 139 | /* [byte] */ | ||
| 140 | #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ | ||
| 141 | /* [1..256 byte] */ \ | ||
| 142 | (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) | ||
| 143 | |||
| 144 | #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ | ||
| 145 | /* [byte] */ | ||
| 146 | #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ | ||
| 147 | /* [1..256 byte] */ \ | ||
| 148 | (((Size) - 1) << FShft (UDCIMP_INMAXP)) | ||
| 149 | |||
| 150 | #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ | ||
| 151 | #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ | ||
| 152 | #define UDCCS0_SST 0x00000004 /* Sent STall */ | ||
| 153 | #define UDCCS0_FST 0x00000008 /* Force STall */ | ||
| 154 | #define UDCCS0_DE 0x00000010 /* Data End */ | ||
| 155 | #define UDCCS0_SE 0x00000020 /* Setup End (read) */ | ||
| 156 | #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ | ||
| 157 | /* (write) */ | ||
| 158 | #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ | ||
| 159 | |||
| 160 | #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ | ||
| 161 | /* Service request (read) */ | ||
| 162 | #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ | ||
| 163 | #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ | ||
| 164 | #define UDCCS1_SST 0x00000008 /* Sent STall */ | ||
| 165 | #define UDCCS1_FST 0x00000010 /* Force STall */ | ||
| 166 | #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ | ||
| 167 | |||
| 168 | #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ | ||
| 169 | /* Service request (read) */ | ||
| 170 | #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ | ||
| 171 | #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ | ||
| 172 | #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ | ||
| 173 | #define UDCCS2_SST 0x00000010 /* Sent STall */ | ||
| 174 | #define UDCCS2_FST 0x00000020 /* Force STall */ | ||
| 175 | |||
| 176 | #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ | ||
| 177 | |||
| 178 | #define UDCWC_WC Fld (4, 0) /* Write Count */ | ||
| 179 | |||
| 180 | #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ | ||
| 181 | |||
| 182 | #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ | ||
| 183 | #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ | ||
| 184 | #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ | ||
| 185 | #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ | ||
| 186 | #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ | ||
| 187 | #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ | ||
| 188 | |||
| 189 | |||
| 190 | /* | ||
| 191 | * Universal Asynchronous Receiver/Transmitter (UART) control registers | ||
| 192 | * | ||
| 193 | * Registers | ||
| 194 | * Ser1UTCR0 Serial port 1 Universal Asynchronous | ||
| 195 | * Receiver/Transmitter (UART) Control Register 0 | ||
| 196 | * (read/write). | ||
| 197 | * Ser1UTCR1 Serial port 1 Universal Asynchronous | ||
| 198 | * Receiver/Transmitter (UART) Control Register 1 | ||
| 199 | * (read/write). | ||
| 200 | * Ser1UTCR2 Serial port 1 Universal Asynchronous | ||
| 201 | * Receiver/Transmitter (UART) Control Register 2 | ||
| 202 | * (read/write). | ||
| 203 | * Ser1UTCR3 Serial port 1 Universal Asynchronous | ||
| 204 | * Receiver/Transmitter (UART) Control Register 3 | ||
| 205 | * (read/write). | ||
| 206 | * Ser1UTDR Serial port 1 Universal Asynchronous | ||
| 207 | * Receiver/Transmitter (UART) Data Register | ||
| 208 | * (read/write). | ||
| 209 | * Ser1UTSR0 Serial port 1 Universal Asynchronous | ||
| 210 | * Receiver/Transmitter (UART) Status Register 0 | ||
| 211 | * (read/write). | ||
| 212 | * Ser1UTSR1 Serial port 1 Universal Asynchronous | ||
| 213 | * Receiver/Transmitter (UART) Status Register 1 (read). | ||
| 214 | * | ||
| 215 | * Ser2UTCR0 Serial port 2 Universal Asynchronous | ||
| 216 | * Receiver/Transmitter (UART) Control Register 0 | ||
| 217 | * (read/write). | ||
| 218 | * Ser2UTCR1 Serial port 2 Universal Asynchronous | ||
| 219 | * Receiver/Transmitter (UART) Control Register 1 | ||
| 220 | * (read/write). | ||
| 221 | * Ser2UTCR2 Serial port 2 Universal Asynchronous | ||
| 222 | * Receiver/Transmitter (UART) Control Register 2 | ||
| 223 | * (read/write). | ||
| 224 | * Ser2UTCR3 Serial port 2 Universal Asynchronous | ||
| 225 | * Receiver/Transmitter (UART) Control Register 3 | ||
| 226 | * (read/write). | ||
| 227 | * Ser2UTCR4 Serial port 2 Universal Asynchronous | ||
| 228 | * Receiver/Transmitter (UART) Control Register 4 | ||
| 229 | * (read/write). | ||
| 230 | * Ser2UTDR Serial port 2 Universal Asynchronous | ||
| 231 | * Receiver/Transmitter (UART) Data Register | ||
| 232 | * (read/write). | ||
| 233 | * Ser2UTSR0 Serial port 2 Universal Asynchronous | ||
| 234 | * Receiver/Transmitter (UART) Status Register 0 | ||
| 235 | * (read/write). | ||
| 236 | * Ser2UTSR1 Serial port 2 Universal Asynchronous | ||
| 237 | * Receiver/Transmitter (UART) Status Register 1 (read). | ||
| 238 | * | ||
| 239 | * Ser3UTCR0 Serial port 3 Universal Asynchronous | ||
| 240 | * Receiver/Transmitter (UART) Control Register 0 | ||
| 241 | * (read/write). | ||
| 242 | * Ser3UTCR1 Serial port 3 Universal Asynchronous | ||
| 243 | * Receiver/Transmitter (UART) Control Register 1 | ||
| 244 | * (read/write). | ||
| 245 | * Ser3UTCR2 Serial port 3 Universal Asynchronous | ||
| 246 | * Receiver/Transmitter (UART) Control Register 2 | ||
| 247 | * (read/write). | ||
| 248 | * Ser3UTCR3 Serial port 3 Universal Asynchronous | ||
| 249 | * Receiver/Transmitter (UART) Control Register 3 | ||
| 250 | * (read/write). | ||
| 251 | * Ser3UTDR Serial port 3 Universal Asynchronous | ||
| 252 | * Receiver/Transmitter (UART) Data Register | ||
| 253 | * (read/write). | ||
| 254 | * Ser3UTSR0 Serial port 3 Universal Asynchronous | ||
| 255 | * Receiver/Transmitter (UART) Status Register 0 | ||
| 256 | * (read/write). | ||
| 257 | * Ser3UTSR1 Serial port 3 Universal Asynchronous | ||
| 258 | * Receiver/Transmitter (UART) Status Register 1 (read). | ||
| 259 | * | ||
| 260 | * Clocks | ||
| 261 | * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz | ||
| 262 | * or 3.5795 MHz). | ||
| 263 | * fua, Tua Frequency, period of the UART communication. | ||
| 264 | */ | ||
| 265 | |||
| 266 | #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ | ||
| 267 | #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ | ||
| 268 | #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ | ||
| 269 | #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ | ||
| 270 | #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ | ||
| 271 | #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ | ||
| 272 | #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ | ||
| 273 | #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ | ||
| 274 | |||
| 275 | #define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ | ||
| 276 | #define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ | ||
| 277 | #define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ | ||
| 278 | #define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ | ||
| 279 | #define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ | ||
| 280 | #define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ | ||
| 281 | #define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ | ||
| 282 | |||
| 283 | #define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ | ||
| 284 | #define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ | ||
| 285 | #define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ | ||
| 286 | #define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ | ||
| 287 | #define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ | ||
| 288 | #define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ | ||
| 289 | #define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ | ||
| 290 | #define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ | ||
| 291 | |||
| 292 | #define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ | ||
| 293 | #define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ | ||
| 294 | #define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ | ||
| 295 | #define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ | ||
| 296 | #define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ | ||
| 297 | #define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ | ||
| 298 | #define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ | ||
| 299 | |||
| 300 | /* Those are still used in some places */ | ||
| 301 | #define _Ser1UTCR0 __PREG(Ser1UTCR0) | ||
| 302 | #define _Ser2UTCR0 __PREG(Ser2UTCR0) | ||
| 303 | #define _Ser3UTCR0 __PREG(Ser3UTCR0) | ||
| 304 | |||
| 305 | /* Register offsets */ | ||
| 306 | #define UTCR0 0x00 | ||
| 307 | #define UTCR1 0x04 | ||
| 308 | #define UTCR2 0x08 | ||
| 309 | #define UTCR3 0x0c | ||
| 310 | #define UTDR 0x14 | ||
| 311 | #define UTSR0 0x1c | ||
| 312 | #define UTSR1 0x20 | ||
| 313 | |||
| 314 | #define UTCR0_PE 0x00000001 /* Parity Enable */ | ||
| 315 | #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ | ||
| 316 | #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ | ||
| 317 | #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ | ||
| 318 | #define UTCR0_SBS 0x00000004 /* Stop Bit Select */ | ||
| 319 | #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ | ||
| 320 | #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ | ||
| 321 | #define UTCR0_DSS 0x00000008 /* Data Size Select */ | ||
| 322 | #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ | ||
| 323 | #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ | ||
| 324 | #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ | ||
| 325 | /* (ser. port 1: GPIO [18], */ | ||
| 326 | /* ser. port 3: GPIO [20]) */ | ||
| 327 | #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ | ||
| 328 | #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ | ||
| 329 | #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ | ||
| 330 | #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ | ||
| 331 | #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ | ||
| 332 | #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ | ||
| 333 | #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ | ||
| 334 | (UTCR0_1StpBit + UTCR0_8BitData) | ||
| 335 | |||
| 336 | #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ | ||
| 337 | #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ | ||
| 338 | /* fua = fxtl/(16*(BRD[11:0] + 1)) */ | ||
| 339 | /* Tua = 16*(BRD [11:0] + 1)*Txtl */ | ||
| 340 | #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ | ||
| 341 | (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ | ||
| 342 | FShft (UTCR1_BRD)) | ||
| 343 | #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ | ||
| 344 | (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ | ||
| 345 | FShft (UTCR2_BRD)) | ||
| 346 | /* fua = fxtl/(16*Floor (Div/16)) */ | ||
| 347 | /* Tua = 16*Floor (Div/16)*Txtl */ | ||
| 348 | #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ | ||
| 349 | (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ | ||
| 350 | FShft (UTCR1_BRD)) | ||
| 351 | #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ | ||
| 352 | (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ | ||
| 353 | FShft (UTCR2_BRD)) | ||
| 354 | /* fua = fxtl/(16*Ceil (Div/16)) */ | ||
| 355 | /* Tua = 16*Ceil (Div/16)*Txtl */ | ||
| 356 | |||
| 357 | #define UTCR3_RXE 0x00000001 /* Receive Enable */ | ||
| 358 | #define UTCR3_TXE 0x00000002 /* Transmit Enable */ | ||
| 359 | #define UTCR3_BRK 0x00000004 /* BReaK mode */ | ||
| 360 | #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ | ||
| 361 | /* more Interrupt Enable */ | ||
| 362 | #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ | ||
| 363 | /* Interrupt Enable */ | ||
| 364 | #define UTCR3_LBM 0x00000020 /* Look-Back Mode */ | ||
| 365 | #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ | ||
| 366 | /* TIE, LBM can be set or cleared) */ \ | ||
| 367 | (UTCR3_RXE + UTCR3_TXE) | ||
| 368 | |||
| 369 | #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ | ||
| 370 | /* (HP-SIR) modulation Enable */ | ||
| 371 | #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ | ||
| 372 | #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ | ||
| 373 | #define UTCR4_LPM 0x00000002 /* Low-Power Mode */ | ||
| 374 | #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ | ||
| 375 | #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ | ||
| 376 | |||
| 377 | #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ | ||
| 378 | #if 0 /* Hidden receive FIFO bits */ | ||
| 379 | #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ | ||
| 380 | #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ | ||
| 381 | #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ | ||
| 382 | #endif /* 0 */ | ||
| 383 | |||
| 384 | #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ | ||
| 385 | /* Service request (read) */ | ||
| 386 | #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ | ||
| 387 | /* more Service request (read) */ | ||
| 388 | #define UTSR0_RID 0x00000004 /* Receiver IDle */ | ||
| 389 | #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ | ||
| 390 | #define UTSR0_REB 0x00000010 /* Receive End of Break */ | ||
| 391 | #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ | ||
| 392 | |||
| 393 | #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ | ||
| 394 | #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ | ||
| 395 | #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ | ||
| 396 | #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ | ||
| 397 | #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ | ||
| 398 | #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ | ||
| 399 | |||
| 400 | |||
| 401 | /* | ||
| 402 | * Synchronous Data Link Controller (SDLC) control registers | ||
| 403 | * | ||
| 404 | * Registers | ||
| 405 | * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 406 | * Control Register 0 (read/write). | ||
| 407 | * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 408 | * Control Register 1 (read/write). | ||
| 409 | * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 410 | * Control Register 2 (read/write). | ||
| 411 | * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 412 | * Control Register 3 (read/write). | ||
| 413 | * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 414 | * Control Register 4 (read/write). | ||
| 415 | * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 416 | * Data Register (read/write). | ||
| 417 | * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 418 | * Status Register 0 (read/write). | ||
| 419 | * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) | ||
| 420 | * Status Register 1 (read/write). | ||
| 421 | * | ||
| 422 | * Clocks | ||
| 423 | * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz | ||
| 424 | * or 3.5795 MHz). | ||
| 425 | * fsd, Tsd Frequency, period of the SDLC communication. | ||
| 426 | */ | ||
| 427 | |||
| 428 | #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */ | ||
| 429 | #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */ | ||
| 430 | #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */ | ||
| 431 | #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */ | ||
| 432 | #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */ | ||
| 433 | #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */ | ||
| 434 | #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */ | ||
| 435 | #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */ | ||
| 436 | |||
| 437 | #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ | ||
| 438 | #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ | ||
| 439 | #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ | ||
| 440 | #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ | ||
| 441 | #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ | ||
| 442 | #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ | ||
| 443 | #define SDCR0_LBM 0x00000004 /* Look-Back Mode */ | ||
| 444 | #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ | ||
| 445 | #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ | ||
| 446 | #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ | ||
| 447 | #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ | ||
| 448 | #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ | ||
| 449 | /* (GPIO [16]) */ | ||
| 450 | #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ | ||
| 451 | #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ | ||
| 452 | #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ | ||
| 453 | #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ | ||
| 454 | #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ | ||
| 455 | #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ | ||
| 456 | #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ | ||
| 457 | #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ | ||
| 458 | |||
| 459 | #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ | ||
| 460 | /* (GPIO [17]) */ | ||
| 461 | #define SDCR1_TXE 0x00000002 /* Transmit Enable */ | ||
| 462 | #define SDCR1_RXE 0x00000004 /* Receive Enable */ | ||
| 463 | #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ | ||
| 464 | /* more Interrupt Enable */ | ||
| 465 | #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ | ||
| 466 | /* Interrupt Enable */ | ||
| 467 | #define SDCR1_AME 0x00000020 /* Address Match Enable */ | ||
| 468 | #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ | ||
| 469 | #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ | ||
| 470 | #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ | ||
| 471 | #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ | ||
| 472 | |||
| 473 | #define SDCR2_AMV Fld (8, 0) /* Address Match Value */ | ||
| 474 | |||
| 475 | #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ | ||
| 476 | #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ | ||
| 477 | /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ | ||
| 478 | /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ | ||
| 479 | #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ | ||
| 480 | (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ | ||
| 481 | FShft (SDCR3_BRD)) | ||
| 482 | #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ | ||
| 483 | (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ | ||
| 484 | FShft (SDCR4_BRD)) | ||
| 485 | /* fsd = fxtl/(16*Floor (Div/16)) */ | ||
| 486 | /* Tsd = 16*Floor (Div/16)*Txtl */ | ||
| 487 | #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ | ||
| 488 | (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ | ||
| 489 | FShft (SDCR3_BRD)) | ||
| 490 | #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ | ||
| 491 | (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ | ||
| 492 | FShft (SDCR4_BRD)) | ||
| 493 | /* fsd = fxtl/(16*Ceil (Div/16)) */ | ||
| 494 | /* Tsd = 16*Ceil (Div/16)*Txtl */ | ||
| 495 | |||
| 496 | #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ | ||
| 497 | #if 0 /* Hidden receive FIFO bits */ | ||
| 498 | #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ | ||
| 499 | #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ | ||
| 500 | #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ | ||
| 501 | #endif /* 0 */ | ||
| 502 | |||
| 503 | #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ | ||
| 504 | #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ | ||
| 505 | #define SDSR0_RAB 0x00000004 /* Receive ABort */ | ||
| 506 | #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ | ||
| 507 | /* Service request (read) */ | ||
| 508 | #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ | ||
| 509 | /* more Service request (read) */ | ||
| 510 | |||
| 511 | #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ | ||
| 512 | #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ | ||
| 513 | #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ | ||
| 514 | #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ | ||
| 515 | #define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ | ||
| 516 | #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ | ||
| 517 | #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ | ||
| 518 | #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ | ||
| 519 | |||
| 520 | |||
| 521 | /* | ||
| 522 | * High-Speed Serial to Parallel controller (HSSP) control registers | ||
| 523 | * | ||
| 524 | * Registers | ||
| 525 | * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel | ||
| 526 | * controller (HSSP) Control Register 0 (read/write). | ||
| 527 | * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel | ||
| 528 | * controller (HSSP) Control Register 1 (read/write). | ||
| 529 | * Ser2HSDR Serial port 2 High-Speed Serial to Parallel | ||
| 530 | * controller (HSSP) Data Register (read/write). | ||
| 531 | * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel | ||
| 532 | * controller (HSSP) Status Register 0 (read/write). | ||
| 533 | * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel | ||
| 534 | * controller (HSSP) Status Register 1 (read). | ||
| 535 | * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel | ||
| 536 | * controller (HSSP) Control Register 2 (read/write). | ||
| 537 | * [The HSCR2 register is only implemented in | ||
| 538 | * versions 2.0 (rev. = 8) and higher of the StrongARM | ||
| 539 | * SA-1100.] | ||
| 540 | */ | ||
| 541 | |||
| 542 | #define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */ | ||
| 543 | #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */ | ||
| 544 | #define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */ | ||
| 545 | #define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */ | ||
| 546 | #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */ | ||
| 547 | #define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */ | ||
| 548 | |||
| 549 | #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ | ||
| 550 | #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ | ||
| 551 | #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ | ||
| 552 | #define HSCR0_LBM 0x00000002 /* Look-Back Mode */ | ||
| 553 | #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ | ||
| 554 | #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ | ||
| 555 | #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ | ||
| 556 | #define HSCR0_TXE 0x00000008 /* Transmit Enable */ | ||
| 557 | #define HSCR0_RXE 0x00000010 /* Receive Enable */ | ||
| 558 | #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ | ||
| 559 | /* more Interrupt Enable */ | ||
| 560 | #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ | ||
| 561 | /* Interrupt Enable */ | ||
| 562 | #define HSCR0_AME 0x00000080 /* Address Match Enable */ | ||
| 563 | |||
| 564 | #define HSCR1_AMV Fld (8, 0) /* Address Match Value */ | ||
| 565 | |||
| 566 | #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ | ||
| 567 | #if 0 /* Hidden receive FIFO bits */ | ||
| 568 | #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ | ||
| 569 | #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ | ||
| 570 | #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ | ||
| 571 | #endif /* 0 */ | ||
| 572 | |||
| 573 | #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ | ||
| 574 | #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ | ||
| 575 | #define HSSR0_RAB 0x00000004 /* Receive ABort */ | ||
| 576 | #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ | ||
| 577 | /* Service request (read) */ | ||
| 578 | #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ | ||
| 579 | /* more Service request (read) */ | ||
| 580 | #define HSSR0_FRE 0x00000020 /* receive FRaming Error */ | ||
| 581 | |||
| 582 | #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ | ||
| 583 | #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ | ||
| 584 | #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ | ||
| 585 | #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ | ||
| 586 | #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ | ||
| 587 | #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ | ||
| 588 | #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ | ||
| 589 | |||
| 590 | #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ | ||
| 591 | #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ | ||
| 592 | /* (inverted) */ | ||
| 593 | #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ | ||
| 594 | /* (non-inverted) */ | ||
| 595 | #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ | ||
| 596 | #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ | ||
| 597 | /* (inverted) */ | ||
| 598 | #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ | ||
| 599 | /* (non-inverted) */ | ||
| 600 | |||
| 601 | |||
| 602 | /* | ||
| 603 | * Multi-media Communications Port (MCP) control registers | ||
| 604 | * | ||
| 605 | * Registers | ||
| 606 | * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) | ||
| 607 | * Control Register 0 (read/write). | ||
| 608 | * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) | ||
| 609 | * Data Register 0 (audio, read/write). | ||
| 610 | * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) | ||
| 611 | * Data Register 1 (telecom, read/write). | ||
| 612 | * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) | ||
| 613 | * Data Register 2 (CODEC registers, read/write). | ||
| 614 | * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) | ||
| 615 | * Status Register (read/write). | ||
| 616 | * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) | ||
| 617 | * Control Register 1 (read/write). | ||
| 618 | * [The MCCR1 register is only implemented in | ||
| 619 | * versions 2.0 (rev. = 8) and higher of the StrongARM | ||
| 620 | * SA-1100.] | ||
| 621 | * | ||
| 622 | * Clocks | ||
| 623 | * fmc, Tmc Frequency, period of the MCP communication (10 MHz, | ||
| 624 | * 12 MHz, or GPIO [21]). | ||
| 625 | * faud, Taud Frequency, period of the audio sampling. | ||
| 626 | * ftcm, Ttcm Frequency, period of the telecom sampling. | ||
| 627 | */ | ||
| 628 | |||
| 629 | #define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */ | ||
| 630 | #define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */ | ||
| 631 | #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */ | ||
| 632 | #define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */ | ||
| 633 | #define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */ | ||
| 634 | #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */ | ||
| 635 | |||
| 636 | #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ | ||
| 637 | /* [6..127] */ | ||
| 638 | /* faud = fmc/(32*ASD) */ | ||
| 639 | /* Taud = 32*ASD*Tmc */ | ||
| 640 | #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ | ||
| 641 | /* [192..4064] */ \ | ||
| 642 | ((Div)/32 << FShft (MCCR0_ASD)) | ||
| 643 | /* faud = fmc/(32*Floor (Div/32)) */ | ||
| 644 | /* Taud = 32*Floor (Div/32)*Tmc */ | ||
| 645 | #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ | ||
| 646 | (((Div) + 31)/32 << FShft (MCCR0_ASD)) | ||
| 647 | /* faud = fmc/(32*Ceil (Div/32)) */ | ||
| 648 | /* Taud = 32*Ceil (Div/32)*Tmc */ | ||
| 649 | #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ | ||
| 650 | /* Divisor/32 [16..127] */ | ||
| 651 | /* ftcm = fmc/(32*TSD) */ | ||
| 652 | /* Ttcm = 32*TSD*Tmc */ | ||
| 653 | #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ | ||
| 654 | /* [512..4064] */ \ | ||
| 655 | ((Div)/32 << FShft (MCCR0_TSD)) | ||
| 656 | /* ftcm = fmc/(32*Floor (Div/32)) */ | ||
| 657 | /* Ttcm = 32*Floor (Div/32)*Tmc */ | ||
| 658 | #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ | ||
| 659 | (((Div) + 31)/32 << FShft (MCCR0_TSD)) | ||
| 660 | /* ftcm = fmc/(32*Ceil (Div/32)) */ | ||
| 661 | /* Ttcm = 32*Ceil (Div/32)*Tmc */ | ||
| 662 | #define MCCR0_MCE 0x00010000 /* MCP Enable */ | ||
| 663 | #define MCCR0_ECS 0x00020000 /* External Clock Select */ | ||
| 664 | #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ | ||
| 665 | #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ | ||
| 666 | #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ | ||
| 667 | /* sampling/storing Mode */ | ||
| 668 | #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ | ||
| 669 | #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ | ||
| 670 | #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ | ||
| 671 | /* or less interrupt Enable */ | ||
| 672 | #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ | ||
| 673 | /* or more interrupt Enable */ | ||
| 674 | #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ | ||
| 675 | /* or less interrupt Enable */ | ||
| 676 | #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ | ||
| 677 | /* more interrupt Enable */ | ||
| 678 | #define MCCR0_LBM 0x00800000 /* Look-Back Mode */ | ||
| 679 | #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ | ||
| 680 | #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ | ||
| 681 | (((Div) - 1) << FShft (MCCR0_ECP)) | ||
| 682 | |||
| 683 | #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ | ||
| 684 | /* FIFOs */ | ||
| 685 | |||
| 686 | #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ | ||
| 687 | /* FIFOs */ | ||
| 688 | |||
| 689 | /* receive/transmit CODEC reg. */ | ||
| 690 | /* FIFOs: */ | ||
| 691 | #define MCDR2_DATA Fld (16, 0) /* reg. DATA */ | ||
| 692 | #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ | ||
| 693 | #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ | ||
| 694 | #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ | ||
| 695 | #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ | ||
| 696 | |||
| 697 | #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ | ||
| 698 | /* or less Service request (read) */ | ||
| 699 | #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ | ||
| 700 | /* more Service request (read) */ | ||
| 701 | #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ | ||
| 702 | /* or less Service request (read) */ | ||
| 703 | #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ | ||
| 704 | /* or more Service request (read) */ | ||
| 705 | #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ | ||
| 706 | #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ | ||
| 707 | #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ | ||
| 708 | #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ | ||
| 709 | #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ | ||
| 710 | /* (read) */ | ||
| 711 | #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ | ||
| 712 | /* (read) */ | ||
| 713 | #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ | ||
| 714 | /* (read) */ | ||
| 715 | #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ | ||
| 716 | /* (read) */ | ||
| 717 | #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ | ||
| 718 | /* (read) */ | ||
| 719 | #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ | ||
| 720 | /* (read) */ | ||
| 721 | #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ | ||
| 722 | #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ | ||
| 723 | |||
| 724 | #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ | ||
| 725 | #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ | ||
| 726 | /* (11.981 MHz) */ | ||
| 727 | #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ | ||
| 728 | /* (9.585 MHz) */ | ||
| 729 | |||
| 730 | |||
| 731 | /* | ||
| 732 | * Synchronous Serial Port (SSP) control registers | ||
| 733 | * | ||
| 734 | * Registers | ||
| 735 | * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control | ||
| 736 | * Register 0 (read/write). | ||
| 737 | * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control | ||
| 738 | * Register 1 (read/write). | ||
| 739 | * [Bits SPO and SP are only implemented in versions 2.0 | ||
| 740 | * (rev. = 8) and higher of the StrongARM SA-1100.] | ||
| 741 | * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data | ||
| 742 | * Register (read/write). | ||
| 743 | * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status | ||
| 744 | * Register (read/write). | ||
| 745 | * | ||
| 746 | * Clocks | ||
| 747 | * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz | ||
| 748 | * or 3.5795 MHz). | ||
| 749 | * fss, Tss Frequency, period of the SSP communication. | ||
| 750 | */ | ||
| 751 | |||
| 752 | #define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */ | ||
| 753 | #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */ | ||
| 754 | #define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */ | ||
| 755 | #define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */ | ||
| 756 | |||
| 757 | #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ | ||
| 758 | #define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ | ||
| 759 | (((Size) - 1) << FShft (SSCR0_DSS)) | ||
| 760 | #define SSCR0_FRF Fld (2, 4) /* FRame Format */ | ||
| 761 | #define SSCR0_Motorola /* Motorola Serial Peripheral */ \ | ||
| 762 | /* Interface (SPI) format */ \ | ||
| 763 | (0 << FShft (SSCR0_FRF)) | ||
| 764 | #define SSCR0_TI /* Texas Instruments Synchronous */ \ | ||
| 765 | /* Serial format */ \ | ||
| 766 | (1 << FShft (SSCR0_FRF)) | ||
| 767 | #define SSCR0_National /* National Microwire format */ \ | ||
| 768 | (2 << FShft (SSCR0_FRF)) | ||
| 769 | #define SSCR0_SSE 0x00000080 /* SSP Enable */ | ||
| 770 | #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ | ||
| 771 | /* fss = fxtl/(2*(SCR + 1)) */ | ||
| 772 | /* Tss = 2*(SCR + 1)*Txtl */ | ||
| 773 | #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ | ||
| 774 | (((Div) - 2)/2 << FShft (SSCR0_SCR)) | ||
| 775 | /* fss = fxtl/(2*Floor (Div/2)) */ | ||
| 776 | /* Tss = 2*Floor (Div/2)*Txtl */ | ||
| 777 | #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ | ||
| 778 | (((Div) - 1)/2 << FShft (SSCR0_SCR)) | ||
| 779 | /* fss = fxtl/(2*Ceil (Div/2)) */ | ||
| 780 | /* Tss = 2*Ceil (Div/2)*Txtl */ | ||
| 781 | |||
| 782 | #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ | ||
| 783 | /* Interrupt Enable */ | ||
| 784 | #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ | ||
| 785 | /* Interrupt Enable */ | ||
| 786 | #define SSCR1_LBM 0x00000004 /* Look-Back Mode */ | ||
| 787 | #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ | ||
| 788 | #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ | ||
| 789 | #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ | ||
| 790 | #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ | ||
| 791 | #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ | ||
| 792 | /* after frame (SFRM, 1st edge) */ | ||
| 793 | #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ | ||
| 794 | /* after frame (SFRM, 1st edge) */ | ||
| 795 | #define SSCR1_ECS 0x00000020 /* External Clock Select */ | ||
| 796 | #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ | ||
| 797 | #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ | ||
| 798 | |||
| 799 | #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ | ||
| 800 | |||
| 801 | #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ | ||
| 802 | #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ | ||
| 803 | #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ | ||
| 804 | #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ | ||
| 805 | /* Service request (read) */ | ||
| 806 | #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ | ||
| 807 | /* Service request (read) */ | ||
| 808 | #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ | ||
| 809 | |||
| 810 | |||
| 811 | /* | ||
| 812 | * Operating System (OS) timer control registers | ||
| 813 | * | ||
| 814 | * Registers | ||
| 815 | * OSMR0 Operating System (OS) timer Match Register 0 | ||
| 816 | * (read/write). | ||
| 817 | * OSMR1 Operating System (OS) timer Match Register 1 | ||
| 818 | * (read/write). | ||
| 819 | * OSMR2 Operating System (OS) timer Match Register 2 | ||
| 820 | * (read/write). | ||
| 821 | * OSMR3 Operating System (OS) timer Match Register 3 | ||
| 822 | * (read/write). | ||
| 823 | * OSCR Operating System (OS) timer Counter Register | ||
| 824 | * (read/write). | ||
| 825 | * OSSR Operating System (OS) timer Status Register | ||
| 826 | * (read/write). | ||
| 827 | * OWER Operating System (OS) timer Watch-dog Enable Register | ||
| 828 | * (read/write). | ||
| 829 | * OIER Operating System (OS) timer Interrupt Enable Register | ||
| 830 | * (read/write). | ||
| 831 | */ | ||
| 832 | |||
| 833 | #define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */ | ||
| 834 | #define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */ | ||
| 835 | #define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */ | ||
| 836 | #define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */ | ||
| 837 | #define OSCR __REG(0x90000010) /* OS timer Counter Reg. */ | ||
| 838 | #define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */ | ||
| 839 | #define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */ | ||
| 840 | #define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */ | ||
| 841 | |||
| 842 | #define OSSR_M(Nb) /* Match detected [0..3] */ \ | ||
| 843 | (0x00000001 << (Nb)) | ||
| 844 | #define OSSR_M0 OSSR_M (0) /* Match detected 0 */ | ||
| 845 | #define OSSR_M1 OSSR_M (1) /* Match detected 1 */ | ||
| 846 | #define OSSR_M2 OSSR_M (2) /* Match detected 2 */ | ||
| 847 | #define OSSR_M3 OSSR_M (3) /* Match detected 3 */ | ||
| 848 | |||
| 849 | #define OWER_WME 0x00000001 /* Watch-dog Match Enable */ | ||
| 850 | /* (set only) */ | ||
| 851 | |||
| 852 | #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ | ||
| 853 | (0x00000001 << (Nb)) | ||
| 854 | #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ | ||
| 855 | #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ | ||
| 856 | #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ | ||
| 857 | #define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ | ||
| 858 | |||
| 859 | |||
| 860 | /* | ||
| 861 | * Real-Time Clock (RTC) control registers | ||
| 862 | * | ||
| 863 | * Registers | ||
| 864 | * RTAR Real-Time Clock (RTC) Alarm Register (read/write). | ||
| 865 | * RCNR Real-Time Clock (RTC) CouNt Register (read/write). | ||
| 866 | * RTTR Real-Time Clock (RTC) Trim Register (read/write). | ||
| 867 | * RTSR Real-Time Clock (RTC) Status Register (read/write). | ||
| 868 | * | ||
| 869 | * Clocks | ||
| 870 | * frtx, Trtx Frequency, period of the real-time clock crystal | ||
| 871 | * (32.768 kHz nominal). | ||
| 872 | * frtc, Trtc Frequency, period of the real-time clock counter | ||
| 873 | * (1 Hz nominal). | ||
| 874 | */ | ||
| 875 | |||
| 876 | #define RTAR __REG(0x90010000) /* RTC Alarm Reg. */ | ||
| 877 | #define RCNR __REG(0x90010004) /* RTC CouNt Reg. */ | ||
| 878 | #define RTTR __REG(0x90010008) /* RTC Trim Reg. */ | ||
| 879 | #define RTSR __REG(0x90010010) /* RTC Status Reg. */ | ||
| 880 | |||
| 881 | #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ | ||
| 882 | #define RTTR_D Fld (10, 16) /* trim Delete count */ | ||
| 883 | /* frtc = (1023*(C + 1) - D)*frtx/ */ | ||
| 884 | /* (1023*(C + 1)^2) */ | ||
| 885 | /* Trtc = (1023*(C + 1)^2)*Trtx/ */ | ||
| 886 | /* (1023*(C + 1) - D) */ | ||
| 887 | |||
| 888 | #define RTSR_AL 0x00000001 /* ALarm detected */ | ||
| 889 | #define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ | ||
| 890 | #define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ | ||
| 891 | #define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ | ||
| 892 | |||
| 893 | |||
| 894 | /* | ||
| 895 | * Power Manager (PM) control registers | ||
| 896 | * | ||
| 897 | * Registers | ||
| 898 | * PMCR Power Manager (PM) Control Register (read/write). | ||
| 899 | * PSSR Power Manager (PM) Sleep Status Register (read/write). | ||
| 900 | * PSPR Power Manager (PM) Scratch-Pad Register (read/write). | ||
| 901 | * PWER Power Manager (PM) Wake-up Enable Register | ||
| 902 | * (read/write). | ||
| 903 | * PCFR Power Manager (PM) general ConFiguration Register | ||
| 904 | * (read/write). | ||
| 905 | * PPCR Power Manager (PM) Phase-Locked Loop (PLL) | ||
| 906 | * Configuration Register (read/write). | ||
| 907 | * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) | ||
| 908 | * Sleep state Register (read/write, see GPIO pins). | ||
| 909 | * POSR Power Manager (PM) Oscillator Status Register (read). | ||
| 910 | * | ||
| 911 | * Clocks | ||
| 912 | * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz | ||
| 913 | * or 3.5795 MHz). | ||
| 914 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 915 | */ | ||
| 916 | |||
| 917 | #define PMCR __REG(0x90020000) /* PM Control Reg. */ | ||
| 918 | #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */ | ||
| 919 | #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */ | ||
| 920 | #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */ | ||
| 921 | #define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */ | ||
| 922 | #define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */ | ||
| 923 | #define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */ | ||
| 924 | #define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */ | ||
| 925 | |||
| 926 | #define PMCR_SF 0x00000001 /* Sleep Force (set only) */ | ||
| 927 | |||
| 928 | #define PSSR_SS 0x00000001 /* Software Sleep */ | ||
| 929 | #define PSSR_BFS 0x00000002 /* Battery Fault Status */ | ||
| 930 | /* (BATT_FAULT) */ | ||
| 931 | #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ | ||
| 932 | #define PSSR_DH 0x00000008 /* DRAM control Hold */ | ||
| 933 | #define PSSR_PH 0x00000010 /* Peripheral control Hold */ | ||
| 934 | |||
| 935 | #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ | ||
| 936 | #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ | ||
| 937 | #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ | ||
| 938 | #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ | ||
| 939 | #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ | ||
| 940 | #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ | ||
| 941 | #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ | ||
| 942 | #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ | ||
| 943 | #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ | ||
| 944 | #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ | ||
| 945 | #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ | ||
| 946 | #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ | ||
| 947 | #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ | ||
| 948 | #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ | ||
| 949 | #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ | ||
| 950 | #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ | ||
| 951 | #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ | ||
| 952 | #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ | ||
| 953 | #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ | ||
| 954 | #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ | ||
| 955 | #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ | ||
| 956 | #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ | ||
| 957 | #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ | ||
| 958 | #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ | ||
| 959 | #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ | ||
| 960 | #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ | ||
| 961 | #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ | ||
| 962 | #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ | ||
| 963 | #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ | ||
| 964 | #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ | ||
| 965 | |||
| 966 | #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ | ||
| 967 | #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ | ||
| 968 | #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ | ||
| 969 | #define PCFR_FP 0x00000002 /* Float PCMCIA pins */ | ||
| 970 | #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ | ||
| 971 | #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ | ||
| 972 | #define PCFR_FS 0x00000004 /* Float Static memory pins */ | ||
| 973 | #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ | ||
| 974 | #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ | ||
| 975 | #define PCFR_FO 0x00000008 /* Force RTC oscillator */ | ||
| 976 | /* (32.768 kHz) enable On */ | ||
| 977 | |||
| 978 | #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ | ||
| 979 | #define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ | ||
| 980 | (0x00 << FShft (PPCR_CCF)) | ||
| 981 | #define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ | ||
| 982 | (0x01 << FShft (PPCR_CCF)) | ||
| 983 | #define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ | ||
| 984 | (0x02 << FShft (PPCR_CCF)) | ||
| 985 | #define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ | ||
| 986 | (0x03 << FShft (PPCR_CCF)) | ||
| 987 | #define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ | ||
| 988 | (0x04 << FShft (PPCR_CCF)) | ||
| 989 | #define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ | ||
| 990 | (0x05 << FShft (PPCR_CCF)) | ||
| 991 | #define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ | ||
| 992 | (0x06 << FShft (PPCR_CCF)) | ||
| 993 | #define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ | ||
| 994 | (0x07 << FShft (PPCR_CCF)) | ||
| 995 | #define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ | ||
| 996 | (0x08 << FShft (PPCR_CCF)) | ||
| 997 | #define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ | ||
| 998 | (0x09 << FShft (PPCR_CCF)) | ||
| 999 | #define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ | ||
| 1000 | (0x0A << FShft (PPCR_CCF)) | ||
| 1001 | #define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ | ||
| 1002 | (0x0B << FShft (PPCR_CCF)) | ||
| 1003 | #define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ | ||
| 1004 | (0x0C << FShft (PPCR_CCF)) | ||
| 1005 | #define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ | ||
| 1006 | (0x0D << FShft (PPCR_CCF)) | ||
| 1007 | #define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ | ||
| 1008 | (0x0E << FShft (PPCR_CCF)) | ||
| 1009 | #define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ | ||
| 1010 | (0x0F << FShft (PPCR_CCF)) | ||
| 1011 | /* 3.6864 MHz crystal (fxtl): */ | ||
| 1012 | #define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ | ||
| 1013 | #define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ | ||
| 1014 | #define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ | ||
| 1015 | #define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ | ||
| 1016 | #define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ | ||
| 1017 | #define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ | ||
| 1018 | #define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ | ||
| 1019 | #define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ | ||
| 1020 | #define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ | ||
| 1021 | #define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ | ||
| 1022 | #define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ | ||
| 1023 | #define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ | ||
| 1024 | #define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ | ||
| 1025 | #define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ | ||
| 1026 | #define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ | ||
| 1027 | #define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ | ||
| 1028 | /* 3.5795 MHz crystal (fxtl): */ | ||
| 1029 | #define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ | ||
| 1030 | #define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ | ||
| 1031 | #define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ | ||
| 1032 | #define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ | ||
| 1033 | #define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ | ||
| 1034 | #define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ | ||
| 1035 | #define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ | ||
| 1036 | #define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ | ||
| 1037 | #define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ | ||
| 1038 | #define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ | ||
| 1039 | #define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ | ||
| 1040 | #define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ | ||
| 1041 | #define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ | ||
| 1042 | #define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ | ||
| 1043 | #define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ | ||
| 1044 | #define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ | ||
| 1045 | |||
| 1046 | #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ | ||
| 1047 | |||
| 1048 | |||
| 1049 | /* | ||
| 1050 | * Reset Controller (RC) control registers | ||
| 1051 | * | ||
| 1052 | * Registers | ||
| 1053 | * RSRR Reset Controller (RC) Software Reset Register | ||
| 1054 | * (read/write). | ||
| 1055 | * RCSR Reset Controller (RC) Status Register (read/write). | ||
| 1056 | */ | ||
| 1057 | |||
| 1058 | #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */ | ||
| 1059 | #define RCSR __REG(0x90030004) /* RC Status Reg. */ | ||
| 1060 | |||
| 1061 | #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ | ||
| 1062 | |||
| 1063 | #define RCSR_HWR 0x00000001 /* HardWare Reset */ | ||
| 1064 | #define RCSR_SWR 0x00000002 /* SoftWare Reset */ | ||
| 1065 | #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ | ||
| 1066 | #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ | ||
| 1067 | |||
| 1068 | |||
| 1069 | /* | ||
| 1070 | * Test unit control registers | ||
| 1071 | * | ||
| 1072 | * Registers | ||
| 1073 | * TUCR Test Unit Control Register (read/write). | ||
| 1074 | */ | ||
| 1075 | |||
| 1076 | #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */ | ||
| 1077 | |||
| 1078 | #define TUCR_TIC 0x00000040 /* TIC mode */ | ||
| 1079 | #define TUCR_TTST 0x00000080 /* Trim TeST mode */ | ||
| 1080 | #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ | ||
| 1081 | /* Check */ | ||
| 1082 | #define TUCR_PMD 0x00000200 /* Power Management Disable */ | ||
| 1083 | #define TUCR_MR 0x00000400 /* Memory Request mode */ | ||
| 1084 | #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ | ||
| 1085 | #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ | ||
| 1086 | /* grant (MBGNT) on GPIO [22:21] */ | ||
| 1087 | #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ | ||
| 1088 | #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ | ||
| 1089 | #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ | ||
| 1090 | #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ | ||
| 1091 | #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ | ||
| 1092 | #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ | ||
| 1093 | #define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ | ||
| 1094 | (0 << FShft (TUCR_TSEL)) | ||
| 1095 | #define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ | ||
| 1096 | (1 << FShft (TUCR_TSEL)) | ||
| 1097 | #define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ | ||
| 1098 | (2 << FShft (TUCR_TSEL)) | ||
| 1099 | #define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ | ||
| 1100 | (3 << FShft (TUCR_TSEL)) | ||
| 1101 | #define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ | ||
| 1102 | /* Clocks on GPIO [26:27] */ \ | ||
| 1103 | (4 << FShft (TUCR_TSEL)) | ||
| 1104 | #define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ | ||
| 1105 | /* (Alternative) */ \ | ||
| 1106 | (5 << FShft (TUCR_TSEL)) | ||
| 1107 | #define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ | ||
| 1108 | (6 << FShft (TUCR_TSEL)) | ||
| 1109 | #define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ | ||
| 1110 | (7 << FShft (TUCR_TSEL)) | ||
| 1111 | |||
| 1112 | |||
| 1113 | /* | ||
| 1114 | * General-Purpose Input/Output (GPIO) control registers | ||
| 1115 | * | ||
| 1116 | * Registers | ||
| 1117 | * GPLR General-Purpose Input/Output (GPIO) Pin Level | ||
| 1118 | * Register (read). | ||
| 1119 | * GPDR General-Purpose Input/Output (GPIO) Pin Direction | ||
| 1120 | * Register (read/write). | ||
| 1121 | * GPSR General-Purpose Input/Output (GPIO) Pin output Set | ||
| 1122 | * Register (write). | ||
| 1123 | * GPCR General-Purpose Input/Output (GPIO) Pin output Clear | ||
| 1124 | * Register (write). | ||
| 1125 | * GRER General-Purpose Input/Output (GPIO) Rising-Edge | ||
| 1126 | * detect Register (read/write). | ||
| 1127 | * GFER General-Purpose Input/Output (GPIO) Falling-Edge | ||
| 1128 | * detect Register (read/write). | ||
| 1129 | * GEDR General-Purpose Input/Output (GPIO) Edge Detect | ||
| 1130 | * status Register (read/write). | ||
| 1131 | * GAFR General-Purpose Input/Output (GPIO) Alternate | ||
| 1132 | * Function Register (read/write). | ||
| 1133 | * | ||
| 1134 | * Clock | ||
| 1135 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 1136 | */ | ||
| 1137 | |||
| 1138 | #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */ | ||
| 1139 | #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */ | ||
| 1140 | #define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */ | ||
| 1141 | #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ | ||
| 1142 | #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */ | ||
| 1143 | #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */ | ||
| 1144 | #define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */ | ||
| 1145 | #define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */ | ||
| 1146 | |||
| 1147 | #define GPIO_MIN (0) | ||
| 1148 | #define GPIO_MAX (27) | ||
| 1149 | |||
| 1150 | #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ | ||
| 1151 | (0x00000001 << (Nb)) | ||
| 1152 | #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ | ||
| 1153 | #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ | ||
| 1154 | #define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ | ||
| 1155 | #define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ | ||
| 1156 | #define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ | ||
| 1157 | #define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ | ||
| 1158 | #define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ | ||
| 1159 | #define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ | ||
| 1160 | #define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ | ||
| 1161 | #define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ | ||
| 1162 | #define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ | ||
| 1163 | #define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ | ||
| 1164 | #define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ | ||
| 1165 | #define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ | ||
| 1166 | #define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ | ||
| 1167 | #define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ | ||
| 1168 | #define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ | ||
| 1169 | #define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ | ||
| 1170 | #define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ | ||
| 1171 | #define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ | ||
| 1172 | #define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ | ||
| 1173 | #define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ | ||
| 1174 | #define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ | ||
| 1175 | #define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ | ||
| 1176 | #define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ | ||
| 1177 | #define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ | ||
| 1178 | #define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ | ||
| 1179 | #define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ | ||
| 1180 | |||
| 1181 | #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ | ||
| 1182 | GPIO_GPIO ((Nb) - 6) | ||
| 1183 | #define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ | ||
| 1184 | #define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ | ||
| 1185 | #define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ | ||
| 1186 | #define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ | ||
| 1187 | #define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ | ||
| 1188 | #define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ | ||
| 1189 | #define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ | ||
| 1190 | #define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ | ||
| 1191 | /* ser. port 4: */ | ||
| 1192 | #define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ | ||
| 1193 | #define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ | ||
| 1194 | #define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ | ||
| 1195 | #define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ | ||
| 1196 | /* ser. port 1: */ | ||
| 1197 | #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ | ||
| 1198 | #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ | ||
| 1199 | #define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ | ||
| 1200 | #define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ | ||
| 1201 | #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ | ||
| 1202 | /* ser. port 4: */ | ||
| 1203 | #define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ | ||
| 1204 | /* ser. port 3: */ | ||
| 1205 | #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ | ||
| 1206 | /* ser. port 4: */ | ||
| 1207 | #define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ | ||
| 1208 | /* test controller: */ | ||
| 1209 | #define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ | ||
| 1210 | #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ | ||
| 1211 | #define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ | ||
| 1212 | #define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ | ||
| 1213 | #define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ | ||
| 1214 | #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ | ||
| 1215 | #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ | ||
| 1216 | #define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ | ||
| 1217 | |||
| 1218 | #define GPDR_In 0 /* Input */ | ||
| 1219 | #define GPDR_Out 1 /* Output */ | ||
| 1220 | |||
| 1221 | |||
| 1222 | /* | ||
| 1223 | * Interrupt Controller (IC) control registers | ||
| 1224 | * | ||
| 1225 | * Registers | ||
| 1226 | * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) | ||
| 1227 | * Pending register (read). | ||
| 1228 | * ICMR Interrupt Controller (IC) Mask Register (read/write). | ||
| 1229 | * ICLR Interrupt Controller (IC) Level Register (read/write). | ||
| 1230 | * ICCR Interrupt Controller (IC) Control Register | ||
| 1231 | * (read/write). | ||
| 1232 | * [The ICCR register is only implemented in versions 2.0 | ||
| 1233 | * (rev. = 8) and higher of the StrongARM SA-1100.] | ||
| 1234 | * ICFP Interrupt Controller (IC) Fast Interrupt reQuest | ||
| 1235 | * (FIQ) Pending register (read). | ||
| 1236 | * ICPR Interrupt Controller (IC) Pending Register (read). | ||
| 1237 | * [The ICPR register is active low (inverted) in | ||
| 1238 | * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the | ||
| 1239 | * StrongARM SA-1100, it is active high (non-inverted) in | ||
| 1240 | * versions 2.0 (rev. = 8) and higher.] | ||
| 1241 | */ | ||
| 1242 | |||
| 1243 | #define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */ | ||
| 1244 | #define ICMR __REG(0x90050004) /* IC Mask Reg. */ | ||
| 1245 | #define ICLR __REG(0x90050008) /* IC Level Reg. */ | ||
| 1246 | #define ICCR __REG(0x9005000C) /* IC Control Reg. */ | ||
| 1247 | #define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */ | ||
| 1248 | #define ICPR __REG(0x90050020) /* IC Pending Reg. */ | ||
| 1249 | |||
| 1250 | #define IC_GPIO(Nb) /* GPIO [0..10] */ \ | ||
| 1251 | (0x00000001 << (Nb)) | ||
| 1252 | #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ | ||
| 1253 | #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ | ||
| 1254 | #define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ | ||
| 1255 | #define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ | ||
| 1256 | #define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ | ||
| 1257 | #define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ | ||
| 1258 | #define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ | ||
| 1259 | #define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ | ||
| 1260 | #define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ | ||
| 1261 | #define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ | ||
| 1262 | #define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ | ||
| 1263 | #define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ | ||
| 1264 | #define IC_LCD 0x00001000 /* LCD controller */ | ||
| 1265 | #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ | ||
| 1266 | #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ | ||
| 1267 | #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ | ||
| 1268 | #define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ | ||
| 1269 | #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ | ||
| 1270 | #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ | ||
| 1271 | #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ | ||
| 1272 | #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ | ||
| 1273 | (0x00100000 << (Nb)) | ||
| 1274 | #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ | ||
| 1275 | #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ | ||
| 1276 | #define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ | ||
| 1277 | #define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ | ||
| 1278 | #define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ | ||
| 1279 | #define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ | ||
| 1280 | #define IC_OST(Nb) /* OS Timer match [0..3] */ \ | ||
| 1281 | (0x04000000 << (Nb)) | ||
| 1282 | #define IC_OST0 IC_OST (0) /* OS Timer match 0 */ | ||
| 1283 | #define IC_OST1 IC_OST (1) /* OS Timer match 1 */ | ||
| 1284 | #define IC_OST2 IC_OST (2) /* OS Timer match 2 */ | ||
| 1285 | #define IC_OST3 IC_OST (3) /* OS Timer match 3 */ | ||
| 1286 | #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ | ||
| 1287 | #define IC_RTCAlrm 0x80000000 /* RTC Alarm */ | ||
| 1288 | |||
| 1289 | #define ICLR_IRQ 0 /* Interrupt ReQuest */ | ||
| 1290 | #define ICLR_FIQ 1 /* Fast Interrupt reQuest */ | ||
| 1291 | |||
| 1292 | #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ | ||
| 1293 | /* Mask */ | ||
| 1294 | #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ | ||
| 1295 | /* (ICMR ignored) */ | ||
| 1296 | #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ | ||
| 1297 | /* enable (ICMR used) */ | ||
| 1298 | |||
| 1299 | |||
| 1300 | /* | ||
| 1301 | * Peripheral Pin Controller (PPC) control registers | ||
| 1302 | * | ||
| 1303 | * Registers | ||
| 1304 | * PPDR Peripheral Pin Controller (PPC) Pin Direction | ||
| 1305 | * Register (read/write). | ||
| 1306 | * PPSR Peripheral Pin Controller (PPC) Pin State Register | ||
| 1307 | * (read/write). | ||
| 1308 | * PPAR Peripheral Pin Controller (PPC) Pin Assignment | ||
| 1309 | * Register (read/write). | ||
| 1310 | * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin | ||
| 1311 | * Direction Register (read/write). | ||
| 1312 | * PPFR Peripheral Pin Controller (PPC) Pin Flag Register | ||
| 1313 | * (read). | ||
| 1314 | */ | ||
| 1315 | |||
| 1316 | #define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */ | ||
| 1317 | #define PPSR __REG(0x90060004) /* PPC Pin State Reg. */ | ||
| 1318 | #define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */ | ||
| 1319 | #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */ | ||
| 1320 | #define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */ | ||
| 1321 | |||
| 1322 | #define PPC_LDD(Nb) /* LCD Data [0..7] */ \ | ||
| 1323 | (0x00000001 << (Nb)) | ||
| 1324 | #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ | ||
| 1325 | #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ | ||
| 1326 | #define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ | ||
| 1327 | #define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ | ||
| 1328 | #define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ | ||
| 1329 | #define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ | ||
| 1330 | #define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ | ||
| 1331 | #define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ | ||
| 1332 | #define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ | ||
| 1333 | #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ | ||
| 1334 | #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ | ||
| 1335 | #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ | ||
| 1336 | /* ser. port 1: */ | ||
| 1337 | #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ | ||
| 1338 | #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ | ||
| 1339 | /* ser. port 2: */ | ||
| 1340 | #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ | ||
| 1341 | #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ | ||
| 1342 | /* ser. port 3: */ | ||
| 1343 | #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ | ||
| 1344 | #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ | ||
| 1345 | /* ser. port 4: */ | ||
| 1346 | #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ | ||
| 1347 | #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ | ||
| 1348 | #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ | ||
| 1349 | #define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ | ||
| 1350 | |||
| 1351 | #define PPDR_In 0 /* Input */ | ||
| 1352 | #define PPDR_Out 1 /* Output */ | ||
| 1353 | |||
| 1354 | /* ser. port 1: */ | ||
| 1355 | #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ | ||
| 1356 | #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ | ||
| 1357 | #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ | ||
| 1358 | /* ser. port 4: */ | ||
| 1359 | #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ | ||
| 1360 | #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ | ||
| 1361 | /* & SFRM_C */ | ||
| 1362 | #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ | ||
| 1363 | |||
| 1364 | #define PSDR_OutL 0 /* Output Low in sleep mode */ | ||
| 1365 | #define PSDR_Flt 1 /* Floating (input) in sleep mode */ | ||
| 1366 | |||
| 1367 | #define PPFR_LCD 0x00000001 /* LCD controller */ | ||
| 1368 | #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ | ||
| 1369 | #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ | ||
| 1370 | #define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ | ||
| 1371 | #define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ | ||
| 1372 | #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ | ||
| 1373 | #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ | ||
| 1374 | #define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ | ||
| 1375 | #define PPFR_PerEn 0 /* Peripheral Enabled */ | ||
| 1376 | #define PPFR_PPCEn 1 /* PPC Enabled */ | ||
| 1377 | |||
| 1378 | |||
| 1379 | /* | ||
| 1380 | * Dynamic Random-Access Memory (DRAM) control registers | ||
| 1381 | * | ||
| 1382 | * Registers | ||
| 1383 | * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) | ||
| 1384 | * CoNFiGuration register (read/write). | ||
| 1385 | * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) | ||
| 1386 | * Column Address Strobe (CAS) shift register 0 | ||
| 1387 | * (read/write). | ||
| 1388 | * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) | ||
| 1389 | * Column Address Strobe (CAS) shift register 1 | ||
| 1390 | * (read/write). | ||
| 1391 | * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) | ||
| 1392 | * Column Address Strobe (CAS) shift register 2 | ||
| 1393 | * (read/write). | ||
| 1394 | * | ||
| 1395 | * Clocks | ||
| 1396 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 1397 | * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). | ||
| 1398 | * fcas, Tcas Frequency, period of the DRAM CAS shift registers. | ||
| 1399 | */ | ||
| 1400 | |||
| 1401 | #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */ | ||
| 1402 | #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */ | ||
| 1403 | #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */ | ||
| 1404 | #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */ | ||
| 1405 | |||
| 1406 | /* SA1100 MDCNFG values */ | ||
| 1407 | #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ | ||
| 1408 | (0x00000001 << (Nb)) | ||
| 1409 | #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ | ||
| 1410 | #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ | ||
| 1411 | #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ | ||
| 1412 | #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ | ||
| 1413 | #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ | ||
| 1414 | #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ | ||
| 1415 | (((Add) - 9) << FShft (MDCNFG_DRAC)) | ||
| 1416 | #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ | ||
| 1417 | /* (fcas = fcpu/2) */ | ||
| 1418 | #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ | ||
| 1419 | #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ | ||
| 1420 | (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) | ||
| 1421 | #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ | ||
| 1422 | (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) | ||
| 1423 | #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ | ||
| 1424 | #define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ | ||
| 1425 | (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) | ||
| 1426 | #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ | ||
| 1427 | (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) | ||
| 1428 | #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ | ||
| 1429 | #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ | ||
| 1430 | ((Tcpu) << FShft (MDCNFG_TDL)) | ||
| 1431 | #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ | ||
| 1432 | /* [Tmem] */ | ||
| 1433 | #define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ | ||
| 1434 | /* [0..262136 Tcpu] */ \ | ||
| 1435 | ((Tcpu)/8 << FShft (MDCNFG_DRI)) | ||
| 1436 | |||
| 1437 | /* SA1110 MDCNFG values */ | ||
| 1438 | #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ | ||
| 1439 | #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ | ||
| 1440 | #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ | ||
| 1441 | #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ | ||
| 1442 | #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ | ||
| 1443 | /* bank 0/1 */ | ||
| 1444 | #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ | ||
| 1445 | #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ | ||
| 1446 | #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ | ||
| 1447 | /* deassertion 0/1 */ | ||
| 1448 | #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ | ||
| 1449 | #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ | ||
| 1450 | #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ | ||
| 1451 | #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ | ||
| 1452 | #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ | ||
| 1453 | #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ | ||
| 1454 | /* bank 0/1 */ | ||
| 1455 | #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ | ||
| 1456 | #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ | ||
| 1457 | #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ | ||
| 1458 | /* deassertion 0/1 */ | ||
| 1459 | #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ | ||
| 1460 | |||
| 1461 | |||
| 1462 | /* | ||
| 1463 | * Static memory control registers | ||
| 1464 | * | ||
| 1465 | * Registers | ||
| 1466 | * MSC0 Memory system: Static memory Control register 0 | ||
| 1467 | * (read/write). | ||
| 1468 | * MSC1 Memory system: Static memory Control register 1 | ||
| 1469 | * (read/write). | ||
| 1470 | * | ||
| 1471 | * Clocks | ||
| 1472 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 1473 | * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). | ||
| 1474 | */ | ||
| 1475 | |||
| 1476 | #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */ | ||
| 1477 | #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */ | ||
| 1478 | #define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */ | ||
| 1479 | |||
| 1480 | #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ | ||
| 1481 | Fld (16, ((Nb) Modulo 2)*16) | ||
| 1482 | #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ | ||
| 1483 | #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ | ||
| 1484 | #define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ | ||
| 1485 | #define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ | ||
| 1486 | |||
| 1487 | #define MSC_RT Fld (2, 0) /* ROM/static memory Type */ | ||
| 1488 | #define MSC_NonBrst /* Non-Burst static memory */ \ | ||
| 1489 | (0 << FShft (MSC_RT)) | ||
| 1490 | #define MSC_SRAM /* 32-bit byte-writable SRAM */ \ | ||
| 1491 | (1 << FShft (MSC_RT)) | ||
| 1492 | #define MSC_Brst4 /* Burst-of-4 static memory */ \ | ||
| 1493 | (2 << FShft (MSC_RT)) | ||
| 1494 | #define MSC_Brst8 /* Burst-of-8 static memory */ \ | ||
| 1495 | (3 << FShft (MSC_RT)) | ||
| 1496 | #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ | ||
| 1497 | #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ | ||
| 1498 | #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ | ||
| 1499 | #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ | ||
| 1500 | /* First access - 1(.5) [Tmem] */ | ||
| 1501 | #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ | ||
| 1502 | /* static memory) [3..65 Tcpu] */ \ | ||
| 1503 | ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) | ||
| 1504 | #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ | ||
| 1505 | ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) | ||
| 1506 | #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ | ||
| 1507 | /* static memory) [2..64 Tcpu] */ \ | ||
| 1508 | ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) | ||
| 1509 | #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ | ||
| 1510 | ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) | ||
| 1511 | #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ | ||
| 1512 | /* Next access - 1 [Tmem] */ | ||
| 1513 | #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ | ||
| 1514 | /* static memory) [2..64 Tcpu] */ \ | ||
| 1515 | ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) | ||
| 1516 | #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ | ||
| 1517 | ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) | ||
| 1518 | #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ | ||
| 1519 | /* static memory) [2..64 Tcpu] */ \ | ||
| 1520 | ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) | ||
| 1521 | #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ | ||
| 1522 | ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) | ||
| 1523 | #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ | ||
| 1524 | /* time/2 [Tmem] */ | ||
| 1525 | #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ | ||
| 1526 | (((Tcpu)/4) << FShft (MSC_RRR)) | ||
| 1527 | #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ | ||
| 1528 | ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) | ||
| 1529 | |||
| 1530 | |||
| 1531 | /* | ||
| 1532 | * Personal Computer Memory Card International Association (PCMCIA) control | ||
| 1533 | * register | ||
| 1534 | * | ||
| 1535 | * Register | ||
| 1536 | * MECR Memory system: Expansion memory bus (PCMCIA) | ||
| 1537 | * Configuration Register (read/write). | ||
| 1538 | * | ||
| 1539 | * Clocks | ||
| 1540 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 1541 | * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). | ||
| 1542 | * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). | ||
| 1543 | */ | ||
| 1544 | |||
| 1545 | /* Memory system: */ | ||
| 1546 | #define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */ | ||
| 1547 | |||
| 1548 | #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ | ||
| 1549 | Fld (15, (Nb)*16) | ||
| 1550 | #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ | ||
| 1551 | #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ | ||
| 1552 | |||
| 1553 | #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ | ||
| 1554 | #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ | ||
| 1555 | ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) | ||
| 1556 | #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ | ||
| 1557 | ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) | ||
| 1558 | #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ | ||
| 1559 | /* [Tmem] */ | ||
| 1560 | #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ | ||
| 1561 | ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) | ||
| 1562 | #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ | ||
| 1563 | ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) | ||
| 1564 | #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ | ||
| 1565 | #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ | ||
| 1566 | ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) | ||
| 1567 | #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ | ||
| 1568 | ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) | ||
| 1569 | |||
| 1570 | /* | ||
| 1571 | * On SA1110 only | ||
| 1572 | */ | ||
| 1573 | |||
| 1574 | #define MDREFR __REG(0xA000001C) | ||
| 1575 | |||
| 1576 | #define MDREFR_TRASR Fld (4, 0) | ||
| 1577 | #define MDREFR_DRI Fld (12, 4) | ||
| 1578 | #define MDREFR_E0PIN (1 << 16) | ||
| 1579 | #define MDREFR_K0RUN (1 << 17) | ||
| 1580 | #define MDREFR_K0DB2 (1 << 18) | ||
| 1581 | #define MDREFR_E1PIN (1 << 20) | ||
| 1582 | #define MDREFR_K1RUN (1 << 21) | ||
| 1583 | #define MDREFR_K1DB2 (1 << 22) | ||
| 1584 | #define MDREFR_K2RUN (1 << 25) | ||
| 1585 | #define MDREFR_K2DB2 (1 << 26) | ||
| 1586 | #define MDREFR_EAPD (1 << 28) | ||
| 1587 | #define MDREFR_KAPD (1 << 29) | ||
| 1588 | #define MDREFR_SLFRSH (1 << 31) | ||
| 1589 | |||
| 1590 | |||
| 1591 | /* | ||
| 1592 | * Direct Memory Access (DMA) control registers | ||
| 1593 | * | ||
| 1594 | * Registers | ||
| 1595 | * DDAR0 Direct Memory Access (DMA) Device Address Register | ||
| 1596 | * channel 0 (read/write). | ||
| 1597 | * DCSR0 Direct Memory Access (DMA) Control and Status | ||
| 1598 | * Register channel 0 (read/write). | ||
| 1599 | * DBSA0 Direct Memory Access (DMA) Buffer Start address | ||
| 1600 | * register A channel 0 (read/write). | ||
| 1601 | * DBTA0 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1602 | * register A channel 0 (read/write). | ||
| 1603 | * DBSB0 Direct Memory Access (DMA) Buffer Start address | ||
| 1604 | * register B channel 0 (read/write). | ||
| 1605 | * DBTB0 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1606 | * register B channel 0 (read/write). | ||
| 1607 | * | ||
| 1608 | * DDAR1 Direct Memory Access (DMA) Device Address Register | ||
| 1609 | * channel 1 (read/write). | ||
| 1610 | * DCSR1 Direct Memory Access (DMA) Control and Status | ||
| 1611 | * Register channel 1 (read/write). | ||
| 1612 | * DBSA1 Direct Memory Access (DMA) Buffer Start address | ||
| 1613 | * register A channel 1 (read/write). | ||
| 1614 | * DBTA1 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1615 | * register A channel 1 (read/write). | ||
| 1616 | * DBSB1 Direct Memory Access (DMA) Buffer Start address | ||
| 1617 | * register B channel 1 (read/write). | ||
| 1618 | * DBTB1 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1619 | * register B channel 1 (read/write). | ||
| 1620 | * | ||
| 1621 | * DDAR2 Direct Memory Access (DMA) Device Address Register | ||
| 1622 | * channel 2 (read/write). | ||
| 1623 | * DCSR2 Direct Memory Access (DMA) Control and Status | ||
| 1624 | * Register channel 2 (read/write). | ||
| 1625 | * DBSA2 Direct Memory Access (DMA) Buffer Start address | ||
| 1626 | * register A channel 2 (read/write). | ||
| 1627 | * DBTA2 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1628 | * register A channel 2 (read/write). | ||
| 1629 | * DBSB2 Direct Memory Access (DMA) Buffer Start address | ||
| 1630 | * register B channel 2 (read/write). | ||
| 1631 | * DBTB2 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1632 | * register B channel 2 (read/write). | ||
| 1633 | * | ||
| 1634 | * DDAR3 Direct Memory Access (DMA) Device Address Register | ||
| 1635 | * channel 3 (read/write). | ||
| 1636 | * DCSR3 Direct Memory Access (DMA) Control and Status | ||
| 1637 | * Register channel 3 (read/write). | ||
| 1638 | * DBSA3 Direct Memory Access (DMA) Buffer Start address | ||
| 1639 | * register A channel 3 (read/write). | ||
| 1640 | * DBTA3 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1641 | * register A channel 3 (read/write). | ||
| 1642 | * DBSB3 Direct Memory Access (DMA) Buffer Start address | ||
| 1643 | * register B channel 3 (read/write). | ||
| 1644 | * DBTB3 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1645 | * register B channel 3 (read/write). | ||
| 1646 | * | ||
| 1647 | * DDAR4 Direct Memory Access (DMA) Device Address Register | ||
| 1648 | * channel 4 (read/write). | ||
| 1649 | * DCSR4 Direct Memory Access (DMA) Control and Status | ||
| 1650 | * Register channel 4 (read/write). | ||
| 1651 | * DBSA4 Direct Memory Access (DMA) Buffer Start address | ||
| 1652 | * register A channel 4 (read/write). | ||
| 1653 | * DBTA4 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1654 | * register A channel 4 (read/write). | ||
| 1655 | * DBSB4 Direct Memory Access (DMA) Buffer Start address | ||
| 1656 | * register B channel 4 (read/write). | ||
| 1657 | * DBTB4 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1658 | * register B channel 4 (read/write). | ||
| 1659 | * | ||
| 1660 | * DDAR5 Direct Memory Access (DMA) Device Address Register | ||
| 1661 | * channel 5 (read/write). | ||
| 1662 | * DCSR5 Direct Memory Access (DMA) Control and Status | ||
| 1663 | * Register channel 5 (read/write). | ||
| 1664 | * DBSA5 Direct Memory Access (DMA) Buffer Start address | ||
| 1665 | * register A channel 5 (read/write). | ||
| 1666 | * DBTA5 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1667 | * register A channel 5 (read/write). | ||
| 1668 | * DBSB5 Direct Memory Access (DMA) Buffer Start address | ||
| 1669 | * register B channel 5 (read/write). | ||
| 1670 | * DBTB5 Direct Memory Access (DMA) Buffer Transfer count | ||
| 1671 | * register B channel 5 (read/write). | ||
| 1672 | */ | ||
| 1673 | |||
| 1674 | #define DMASp 0x00000020 /* DMA control reg. Space [byte] */ | ||
| 1675 | |||
| 1676 | #define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */ | ||
| 1677 | #define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */ | ||
| 1678 | #define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */ | ||
| 1679 | #define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */ | ||
| 1680 | #define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */ | ||
| 1681 | #define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */ | ||
| 1682 | #define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */ | ||
| 1683 | #define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */ | ||
| 1684 | |||
| 1685 | #define DDAR_RW 0x00000001 /* device data Read/Write */ | ||
| 1686 | #define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ | ||
| 1687 | /* (memory -> device) */ | ||
| 1688 | #define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ | ||
| 1689 | /* (device -> memory) */ | ||
| 1690 | #define DDAR_E 0x00000002 /* big/little Endian device */ | ||
| 1691 | #define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ | ||
| 1692 | #define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ | ||
| 1693 | #define DDAR_BS 0x00000004 /* device Burst Size */ | ||
| 1694 | #define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ | ||
| 1695 | #define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ | ||
| 1696 | #define DDAR_DW 0x00000008 /* device Data Width */ | ||
| 1697 | #define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ | ||
| 1698 | #define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ | ||
| 1699 | #define DDAR_DS Fld (4, 4) /* Device Select */ | ||
| 1700 | #define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ | ||
| 1701 | (0x0 << FShft (DDAR_DS)) | ||
| 1702 | #define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ | ||
| 1703 | (0x1 << FShft (DDAR_DS)) | ||
| 1704 | #define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ | ||
| 1705 | (0x2 << FShft (DDAR_DS)) | ||
| 1706 | #define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ | ||
| 1707 | (0x3 << FShft (DDAR_DS)) | ||
| 1708 | #define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ | ||
| 1709 | (0x4 << FShft (DDAR_DS)) | ||
| 1710 | #define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ | ||
| 1711 | (0x5 << FShft (DDAR_DS)) | ||
| 1712 | #define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ | ||
| 1713 | (0x6 << FShft (DDAR_DS)) | ||
| 1714 | #define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ | ||
| 1715 | (0x7 << FShft (DDAR_DS)) | ||
| 1716 | #define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ | ||
| 1717 | (0x8 << FShft (DDAR_DS)) | ||
| 1718 | #define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ | ||
| 1719 | (0x9 << FShft (DDAR_DS)) | ||
| 1720 | #define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ | ||
| 1721 | /* (audio) */ \ | ||
| 1722 | (0xA << FShft (DDAR_DS)) | ||
| 1723 | #define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ | ||
| 1724 | /* (audio) */ \ | ||
| 1725 | (0xB << FShft (DDAR_DS)) | ||
| 1726 | #define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ | ||
| 1727 | /* (telecom) */ \ | ||
| 1728 | (0xC << FShft (DDAR_DS)) | ||
| 1729 | #define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ | ||
| 1730 | /* (telecom) */ \ | ||
| 1731 | (0xD << FShft (DDAR_DS)) | ||
| 1732 | #define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ | ||
| 1733 | (0xE << FShft (DDAR_DS)) | ||
| 1734 | #define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ | ||
| 1735 | (0xF << FShft (DDAR_DS)) | ||
| 1736 | #define DDAR_DA Fld (24, 8) /* Device Address */ | ||
| 1737 | #define DDAR_DevAdd(Add) /* Device Address */ \ | ||
| 1738 | (((Add) & 0xF0000000) | \ | ||
| 1739 | (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) | ||
| 1740 | #define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ | ||
| 1741 | (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ | ||
| 1742 | DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR))) | ||
| 1743 | #define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ | ||
| 1744 | (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ | ||
| 1745 | DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR))) | ||
| 1746 | #define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ | ||
| 1747 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1748 | DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR))) | ||
| 1749 | #define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ | ||
| 1750 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1751 | DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR))) | ||
| 1752 | #define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ | ||
| 1753 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1754 | DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR))) | ||
| 1755 | #define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ | ||
| 1756 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1757 | DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR))) | ||
| 1758 | #define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ | ||
| 1759 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1760 | DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR))) | ||
| 1761 | #define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ | ||
| 1762 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1763 | DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR))) | ||
| 1764 | #define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ | ||
| 1765 | (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ | ||
| 1766 | DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR))) | ||
| 1767 | #define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ | ||
| 1768 | (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ | ||
| 1769 | DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR))) | ||
| 1770 | #define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ | ||
| 1771 | (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1772 | DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR))) | ||
| 1773 | #define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ | ||
| 1774 | (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ | ||
| 1775 | DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR))) | ||
| 1776 | #define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ | ||
| 1777 | (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1778 | DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0))) | ||
| 1779 | #define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ | ||
| 1780 | (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1781 | DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0))) | ||
| 1782 | #define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ | ||
| 1783 | /* (telecom) */ \ | ||
| 1784 | (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1785 | DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1))) | ||
| 1786 | #define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ | ||
| 1787 | /* (telecom) */ \ | ||
| 1788 | (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1789 | DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1))) | ||
| 1790 | #define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ | ||
| 1791 | (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1792 | DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR))) | ||
| 1793 | #define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ | ||
| 1794 | (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ | ||
| 1795 | DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR))) | ||
| 1796 | |||
| 1797 | #define DCSR_RUN 0x00000001 /* DMA RUNing */ | ||
| 1798 | #define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ | ||
| 1799 | #define DCSR_ERROR 0x00000004 /* DMA ERROR */ | ||
| 1800 | #define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ | ||
| 1801 | #define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ | ||
| 1802 | #define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ | ||
| 1803 | #define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ | ||
| 1804 | #define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ | ||
| 1805 | #define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ | ||
| 1806 | #define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ | ||
| 1807 | |||
| 1808 | #define DBT_TC Fld (13, 0) /* Transfer Count */ | ||
| 1809 | #define DBTA_TCA DBT_TC /* Transfer Count buffer A */ | ||
| 1810 | #define DBTB_TCB DBT_TC /* Transfer Count buffer B */ | ||
| 1811 | |||
| 1812 | |||
| 1813 | /* | ||
| 1814 | * Liquid Crystal Display (LCD) control registers | ||
| 1815 | * | ||
| 1816 | * Registers | ||
| 1817 | * LCCR0 Liquid Crystal Display (LCD) Control Register 0 | ||
| 1818 | * (read/write). | ||
| 1819 | * [Bits LDM, BAM, and ERM are only implemented in | ||
| 1820 | * versions 2.0 (rev. = 8) and higher of the StrongARM | ||
| 1821 | * SA-1100.] | ||
| 1822 | * LCSR Liquid Crystal Display (LCD) Status Register | ||
| 1823 | * (read/write). | ||
| 1824 | * [Bit LDD can be only read in versions 1.0 (rev. = 1) | ||
| 1825 | * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be | ||
| 1826 | * read and written (cleared) in versions 2.0 (rev. = 8) | ||
| 1827 | * and higher.] | ||
| 1828 | * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access | ||
| 1829 | * (DMA) Base Address Register channel 1 (read/write). | ||
| 1830 | * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access | ||
| 1831 | * (DMA) Current Address Register channel 1 (read). | ||
| 1832 | * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access | ||
| 1833 | * (DMA) Base Address Register channel 2 (read/write). | ||
| 1834 | * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access | ||
| 1835 | * (DMA) Current Address Register channel 2 (read). | ||
| 1836 | * LCCR1 Liquid Crystal Display (LCD) Control Register 1 | ||
| 1837 | * (read/write). | ||
| 1838 | * [The LCCR1 register can be only written in | ||
| 1839 | * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the | ||
| 1840 | * StrongARM SA-1100, it can be written and read in | ||
| 1841 | * versions 2.0 (rev. = 8) and higher.] | ||
| 1842 | * LCCR2 Liquid Crystal Display (LCD) Control Register 2 | ||
| 1843 | * (read/write). | ||
| 1844 | * [The LCCR1 register can be only written in | ||
| 1845 | * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the | ||
| 1846 | * StrongARM SA-1100, it can be written and read in | ||
| 1847 | * versions 2.0 (rev. = 8) and higher.] | ||
| 1848 | * LCCR3 Liquid Crystal Display (LCD) Control Register 3 | ||
| 1849 | * (read/write). | ||
| 1850 | * [The LCCR1 register can be only written in | ||
| 1851 | * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the | ||
| 1852 | * StrongARM SA-1100, it can be written and read in | ||
| 1853 | * versions 2.0 (rev. = 8) and higher. Bit PCP is only | ||
| 1854 | * implemented in versions 2.0 (rev. = 8) and higher of | ||
| 1855 | * the StrongARM SA-1100.] | ||
| 1856 | * | ||
| 1857 | * Clocks | ||
| 1858 | * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). | ||
| 1859 | * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). | ||
| 1860 | * fpix, Tpix Frequency, period of the pixel clock. | ||
| 1861 | * fln, Tln Frequency, period of the line clock. | ||
| 1862 | * fac, Tac Frequency, period of the AC bias clock. | ||
| 1863 | */ | ||
| 1864 | |||
| 1865 | #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ | ||
| 1866 | #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ | ||
| 1867 | /* [byte] */ \ | ||
| 1868 | (16*LCD_PEntrySp) | ||
| 1869 | #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ | ||
| 1870 | /* [byte] */ \ | ||
| 1871 | (256*LCD_PEntrySp) | ||
| 1872 | #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ | ||
| 1873 | /* dummy-Palette Space [byte] */ \ | ||
| 1874 | (16*LCD_PEntrySp) | ||
| 1875 | |||
| 1876 | #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ | ||
| 1877 | #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ | ||
| 1878 | #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ | ||
| 1879 | #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ | ||
| 1880 | #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ | ||
| 1881 | #define LCD_4Bit /* LCD 4-Bit pixel mode */ \ | ||
| 1882 | (0 << FShft (LCD_PBS)) | ||
| 1883 | #define LCD_8Bit /* LCD 8-Bit pixel mode */ \ | ||
| 1884 | (1 << FShft (LCD_PBS)) | ||
| 1885 | #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ | ||
| 1886 | (2 << FShft (LCD_PBS)) | ||
| 1887 | |||
| 1888 | #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ | ||
| 1889 | #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ | ||
| 1890 | #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ | ||
| 1891 | #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ | ||
| 1892 | #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ | ||
| 1893 | #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ | ||
| 1894 | #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ | ||
| 1895 | #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ | ||
| 1896 | #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ | ||
| 1897 | #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ | ||
| 1898 | #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ | ||
| 1899 | #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ | ||
| 1900 | #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ | ||
| 1901 | #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ | ||
| 1902 | #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ | ||
| 1903 | #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ | ||
| 1904 | /* (Alternative) */ | ||
| 1905 | |||
| 1906 | #define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */ | ||
| 1907 | #define LCSR __REG(0xB0100004) /* LCD Status Reg. */ | ||
| 1908 | #define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */ | ||
| 1909 | #define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */ | ||
| 1910 | #define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */ | ||
| 1911 | #define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */ | ||
| 1912 | #define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */ | ||
| 1913 | #define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */ | ||
| 1914 | #define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */ | ||
| 1915 | |||
| 1916 | #define LCCR0_LEN 0x00000001 /* LCD ENable */ | ||
| 1917 | #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ | ||
| 1918 | #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ | ||
| 1919 | #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ | ||
| 1920 | #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ | ||
| 1921 | /* Select */ | ||
| 1922 | #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ | ||
| 1923 | #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ | ||
| 1924 | #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ | ||
| 1925 | /* interrupt Mask (disable) */ | ||
| 1926 | #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ | ||
| 1927 | /* interrupt Mask (disable) */ | ||
| 1928 | #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ | ||
| 1929 | /* IUU, OOL, OUL, OOU, and OUU) */ | ||
| 1930 | /* interrupt Mask (disable) */ | ||
| 1931 | #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ | ||
| 1932 | #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ | ||
| 1933 | #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ | ||
| 1934 | #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ | ||
| 1935 | #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ | ||
| 1936 | #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ | ||
| 1937 | #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ | ||
| 1938 | /* display mode) */ | ||
| 1939 | #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ | ||
| 1940 | /* display */ | ||
| 1941 | #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ | ||
| 1942 | /* display */ | ||
| 1943 | #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ | ||
| 1944 | /* [Tmem] */ | ||
| 1945 | #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ | ||
| 1946 | /* [0..510 Tcpu] */ \ | ||
| 1947 | ((Tcpu)/2 << FShft (LCCR0_PDD)) | ||
| 1948 | |||
| 1949 | #define LCSR_LDD 0x00000001 /* LCD Disable Done */ | ||
| 1950 | #define LCSR_BAU 0x00000002 /* Base Address Update (read) */ | ||
| 1951 | #define LCSR_BER 0x00000004 /* Bus ERror */ | ||
| 1952 | #define LCSR_ABC 0x00000008 /* AC Bias clock Count */ | ||
| 1953 | #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ | ||
| 1954 | /* panel */ | ||
| 1955 | #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ | ||
| 1956 | /* panel */ | ||
| 1957 | #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ | ||
| 1958 | /* panel */ | ||
| 1959 | #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ | ||
| 1960 | /* panel */ | ||
| 1961 | #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ | ||
| 1962 | /* panel */ | ||
| 1963 | #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ | ||
| 1964 | /* panel */ | ||
| 1965 | #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ | ||
| 1966 | /* panel */ | ||
| 1967 | #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ | ||
| 1968 | /* panel */ | ||
| 1969 | |||
| 1970 | #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ | ||
| 1971 | #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ | ||
| 1972 | (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) | ||
| 1973 | #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ | ||
| 1974 | /* pulse Width - 1 [Tpix] (L_LCLK) */ | ||
| 1975 | #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ | ||
| 1976 | /* pulse Width [1..64 Tpix] */ \ | ||
| 1977 | (((Tpix) - 1) << FShft (LCCR1_HSW)) | ||
| 1978 | #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ | ||
| 1979 | /* count - 1 [Tpix] */ | ||
| 1980 | #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ | ||
| 1981 | /* [1..256 Tpix] */ \ | ||
| 1982 | (((Tpix) - 1) << FShft (LCCR1_ELW)) | ||
| 1983 | #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ | ||
| 1984 | /* Wait count - 1 [Tpix] */ | ||
| 1985 | #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ | ||
| 1986 | /* [1..256 Tpix] */ \ | ||
| 1987 | (((Tpix) - 1) << FShft (LCCR1_BLW)) | ||
| 1988 | |||
| 1989 | #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ | ||
| 1990 | #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ | ||
| 1991 | (((Line) - 1) << FShft (LCCR2_LPP)) | ||
| 1992 | #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ | ||
| 1993 | /* Width - 1 [Tln] (L_FCLK) */ | ||
| 1994 | #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ | ||
| 1995 | /* Width [1..64 Tln] */ \ | ||
| 1996 | (((Tln) - 1) << FShft (LCCR2_VSW)) | ||
| 1997 | #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ | ||
| 1998 | /* count [Tln] */ | ||
| 1999 | #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ | ||
| 2000 | /* [0..255 Tln] */ \ | ||
| 2001 | ((Tln) << FShft (LCCR2_EFW)) | ||
| 2002 | #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ | ||
| 2003 | /* Wait count [Tln] */ | ||
| 2004 | #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ | ||
| 2005 | /* [0..255 Tln] */ \ | ||
| 2006 | ((Tln) << FShft (LCCR2_BFW)) | ||
| 2007 | |||
| 2008 | #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ | ||
| 2009 | /* [1..255] (L_PCLK) */ | ||
| 2010 | /* fpix = fcpu/(2*(PCD + 2)) */ | ||
| 2011 | /* Tpix = 2*(PCD + 2)*Tcpu */ | ||
| 2012 | #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ | ||
| 2013 | (((Div) - 4)/2 << FShft (LCCR3_PCD)) | ||
| 2014 | /* fpix = fcpu/(2*Floor (Div/2)) */ | ||
| 2015 | /* Tpix = 2*Floor (Div/2)*Tcpu */ | ||
| 2016 | #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ | ||
| 2017 | (((Div) - 3)/2 << FShft (LCCR3_PCD)) | ||
| 2018 | /* fpix = fcpu/(2*Ceil (Div/2)) */ | ||
| 2019 | /* Tpix = 2*Ceil (Div/2)*Tcpu */ | ||
| 2020 | #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ | ||
| 2021 | /* [Tln] (L_BIAS) */ | ||
| 2022 | #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ | ||
| 2023 | (((Div) - 2)/2 << FShft (LCCR3_ACB)) | ||
| 2024 | /* fac = fln/(2*Floor (Div/2)) */ | ||
| 2025 | /* Tac = 2*Floor (Div/2)*Tln */ | ||
| 2026 | #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ | ||
| 2027 | (((Div) - 1)/2 << FShft (LCCR3_ACB)) | ||
| 2028 | /* fac = fln/(2*Ceil (Div/2)) */ | ||
| 2029 | /* Tac = 2*Ceil (Div/2)*Tln */ | ||
| 2030 | #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ | ||
| 2031 | /* Interrupt */ | ||
| 2032 | #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ | ||
| 2033 | /* Off */ \ | ||
| 2034 | (0 << FShft (LCCR3_API)) | ||
| 2035 | #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ | ||
| 2036 | /* [1..15] */ \ | ||
| 2037 | ((Trans) << FShft (LCCR3_API)) | ||
| 2038 | #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ | ||
| 2039 | /* Polarity (L_FCLK) */ | ||
| 2040 | #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ | ||
| 2041 | /* active High */ | ||
| 2042 | #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ | ||
| 2043 | /* active Low */ | ||
| 2044 | #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ | ||
| 2045 | /* pulse Polarity (L_LCLK) */ | ||
| 2046 | #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ | ||
| 2047 | /* pulse active High */ | ||
| 2048 | #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ | ||
| 2049 | /* pulse active Low */ | ||
| 2050 | #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ | ||
| 2051 | #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ | ||
| 2052 | #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ | ||
| 2053 | #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ | ||
| 2054 | /* active display mode) */ | ||
| 2055 | #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ | ||
| 2056 | #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ | ||
| 2057 | |||
| 2058 | #ifndef __ASSEMBLY__ | ||
| 2059 | extern unsigned int processor_id; | ||
| 2060 | #endif | ||
| 2061 | |||
| 2062 | #define CPU_REVISION (processor_id & 15) | ||
| 2063 | #define CPU_SA1110_A0 (0) | ||
| 2064 | #define CPU_SA1110_B0 (4) | ||
| 2065 | #define CPU_SA1110_B1 (5) | ||
| 2066 | #define CPU_SA1110_B2 (6) | ||
| 2067 | #define CPU_SA1110_B4 (8) | ||
| 2068 | |||
| 2069 | #define CPU_SA1100_ID (0x4401a110) | ||
| 2070 | #define CPU_SA1100_MASK (0xfffffff0) | ||
| 2071 | #define CPU_SA1110_ID (0x6901b110) | ||
| 2072 | #define CPU_SA1110_MASK (0xfffffff0) | ||
diff --git a/include/asm-arm/arch-sa1100/SA-1101.h b/include/asm-arm/arch-sa1100/SA-1101.h deleted file mode 100644 index 65ca8c79e6d2..000000000000 --- a/include/asm-arm/arch-sa1100/SA-1101.h +++ /dev/null | |||
| @@ -1,925 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * SA-1101.h | ||
| 3 | * | ||
| 4 | * Copyright (c) Peter Danielsson 1999 | ||
| 5 | * | ||
| 6 | * Definition of constants related to the sa1101 | ||
| 7 | * support chip for the sa1100 | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | |||
| 12 | /* Be sure that virtual mapping is defined right */ | ||
| 13 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 14 | #error You must include hardware.h not SA-1101.h | ||
| 15 | #endif | ||
| 16 | |||
| 17 | #ifndef SA1101_BASE | ||
| 18 | #error You must define SA-1101 physical base address | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #ifndef LANGUAGE | ||
| 22 | # ifdef __ASSEMBLY__ | ||
| 23 | # define LANGUAGE Assembly | ||
| 24 | # else | ||
| 25 | # define LANGUAGE C | ||
| 26 | # endif | ||
| 27 | #endif | ||
| 28 | |||
| 29 | /* | ||
| 30 | * We have mapped the sa1101 depending on the value of SA1101_BASE. | ||
| 31 | * It then appears from 0xf4000000. | ||
| 32 | */ | ||
| 33 | |||
| 34 | #define SA1101_p2v( x ) ((x) - SA1101_BASE + 0xf4000000) | ||
| 35 | #define SA1101_v2p( x ) ((x) - 0xf4000000 + SA1101_BASE) | ||
| 36 | |||
| 37 | #ifndef SA1101_p2v | ||
| 38 | #define SA1101_p2v(PhAdd) (PhAdd) | ||
| 39 | #endif | ||
| 40 | |||
| 41 | #include <asm/arch/bitfield.h> | ||
| 42 | |||
| 43 | #define C 0 | ||
| 44 | #define Assembly 1 | ||
| 45 | |||
| 46 | |||
| 47 | /* | ||
| 48 | * Memory map | ||
| 49 | */ | ||
| 50 | |||
| 51 | #define __SHMEM_CONTROL0 0x00000000 | ||
| 52 | #define __SYSTEM_CONTROL1 0x00000400 | ||
| 53 | #define __ARBITER 0x00020000 | ||
| 54 | #define __SYSTEM_CONTROL2 0x00040000 | ||
| 55 | #define __SYSTEM_CONTROL3 0x00060000 | ||
| 56 | #define __PARALLEL_PORT 0x00080000 | ||
| 57 | #define __VIDMEM_CONTROL 0x00100000 | ||
| 58 | #define __UPDATE_FIFO 0x00120000 | ||
| 59 | #define __SHMEM_CONTROL1 0x00140000 | ||
| 60 | #define __INTERRUPT_CONTROL 0x00160000 | ||
| 61 | #define __USB_CONTROL 0x00180000 | ||
| 62 | #define __TRACK_INTERFACE 0x001a0000 | ||
| 63 | #define __MOUSE_INTERFACE 0x001b0000 | ||
| 64 | #define __KEYPAD_INTERFACE 0x001c0000 | ||
| 65 | #define __PCMCIA_INTERFACE 0x001e0000 | ||
| 66 | #define __VGA_CONTROL 0x00200000 | ||
| 67 | #define __GPIO_INTERFACE 0x00300000 | ||
| 68 | |||
| 69 | /* | ||
| 70 | * Macro that calculates real address for registers in the SA-1101 | ||
| 71 | */ | ||
| 72 | |||
| 73 | #define _SA1101( x ) ((x) + SA1101_BASE) | ||
| 74 | |||
| 75 | /* | ||
| 76 | * Interface and shared memory controller registers | ||
| 77 | * | ||
| 78 | * Registers | ||
| 79 | * SKCR SA-1101 control register (read/write) | ||
| 80 | * SMCR Shared Memory Controller Register | ||
| 81 | * SNPR Snoop Register | ||
| 82 | */ | ||
| 83 | |||
| 84 | #define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */ | ||
| 85 | #define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */ | ||
| 86 | #define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */ | ||
| 87 | |||
| 88 | #if LANGUAGE == C | ||
| 89 | #define SKCR (*((volatile Word *) SA1101_p2v (_SKCR))) | ||
| 90 | #define SMCR (*((volatile Word *) SA1101_p2v (_SMCR))) | ||
| 91 | #define SNPR (*((volatile Word *) SA1101_p2v (_SNPR))) | ||
| 92 | |||
| 93 | #define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */ | ||
| 94 | #define SKCR_BCLKEn 0x0002 /* Enables BCLK */ | ||
| 95 | #define SKCR_Sleep 0x0004 /* Sleep Mode */ | ||
| 96 | #define SKCR_IRefEn 0x0008 /* DAC Iref input enable */ | ||
| 97 | #define SKCR_VCOON 0x0010 /* VCO bias */ | ||
| 98 | #define SKCR_ScanTestEn 0x0020 /* Enables scan test */ | ||
| 99 | #define SKCR_ClockTestEn 0x0040 /* Enables clock test */ | ||
| 100 | |||
| 101 | #define SMCR_DCAC Fld(2,0) /* Number of column address bits */ | ||
| 102 | #define SMCR_DRAC Fld(2,2) /* Number of row address bits */ | ||
| 103 | #define SMCR_ArbiterBias 0x0008 /* favor video or USB */ | ||
| 104 | #define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */ | ||
| 105 | |||
| 106 | #define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \ | ||
| 107 | (( (x) - 8 ) << FShft (SMCR_DCAC)) | ||
| 108 | #define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\ | ||
| 109 | (( (x) - 9 ) << FShft (SMCR_DRAC)) | ||
| 110 | |||
| 111 | #define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */ | ||
| 112 | #define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */ | ||
| 113 | #define SNPR_WholeBank (1 << 23) /* Whole bank bit */ | ||
| 114 | #define SNPR_BankSelect Fld(2,27) /* Bank select */ | ||
| 115 | #define SNPR_SnoopEn (1 << 31) /* Enable snoop operation */ | ||
| 116 | |||
| 117 | #define SNPR_Set_VFBsize( x ) /* set frame buffer size (in kb) */ \ | ||
| 118 | ( (x) << FShft (SNPR_VFBsize)) | ||
| 119 | #define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \ | ||
| 120 | (( (x) + 1 ) << FShft (SNPR_BankSelect )) | ||
| 121 | |||
| 122 | #endif /* LANGUAGE == C */ | ||
| 123 | |||
| 124 | /* | ||
| 125 | * Video Memory Controller | ||
| 126 | * | ||
| 127 | * Registers | ||
| 128 | * VMCCR Configuration register | ||
| 129 | * VMCAR VMC address register | ||
| 130 | * VMCDR VMC data register | ||
| 131 | * | ||
| 132 | */ | ||
| 133 | |||
| 134 | #define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */ | ||
| 135 | #define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */ | ||
| 136 | #define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */ | ||
| 137 | |||
| 138 | #if LANGUAGE == C | ||
| 139 | #define VMCCR (*((volatile Word *) SA1101_p2v (_VMCCR))) | ||
| 140 | #define VMCAR (*((volatile Word *) SA1101_p2v (_VMCAR))) | ||
| 141 | #define VMCDR (*((volatile Word *) SA1101_p2v (_VMCDR))) | ||
| 142 | |||
| 143 | #define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */ | ||
| 144 | #define VMCCR_Config 0x0001 /* DRAM size */ | ||
| 145 | #define VMCCR_RefPeriod Fld(2,3) /* Refresh period */ | ||
| 146 | #define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */ | ||
| 147 | #define VMCCR_SleepState (1<<9) /* State of interface pins in sleep*/ | ||
| 148 | #define VMCCR_RefTest (1<<10) /* refresh test */ | ||
| 149 | #define VMCCR_RefLow Fld(6,11) /* refresh low counter */ | ||
| 150 | #define VMCCR_RefHigh Fld(7,17) /* refresh high counter */ | ||
| 151 | #define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */ | ||
| 152 | #define VMCCR_ForceSelfRef (1<<31) /* Force self refresh */ | ||
| 153 | |||
| 154 | #endif LANGUAGE == C | ||
| 155 | |||
| 156 | |||
| 157 | /* Update FIFO | ||
| 158 | * | ||
| 159 | * Registers | ||
| 160 | * UFCR Update FIFO Control Register | ||
| 161 | * UFSR Update FIFO Status Register | ||
| 162 | * UFLVLR update FIFO level register | ||
| 163 | * UFDR update FIFO data register | ||
| 164 | */ | ||
| 165 | |||
| 166 | #define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */ | ||
| 167 | #define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */ | ||
| 168 | #define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */ | ||
| 169 | #define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */ | ||
| 170 | |||
| 171 | #if LANGUAGE == C | ||
| 172 | |||
| 173 | #define UFCR (*((volatile Word *) SA1101_p2v (_UFCR))) | ||
| 174 | #define UFSR (*((volatile Word *) SA1101_p2v (_UFSR))) | ||
| 175 | #define UFLVLR (*((volatile Word *) SA1101_p2v (_UFLVLR))) | ||
| 176 | #define UFDR (*((volatile Word *) SA1101_p2v (_UFDR))) | ||
| 177 | |||
| 178 | |||
| 179 | #define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */ | ||
| 180 | |||
| 181 | #define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */ | ||
| 182 | |||
| 183 | #endif /* LANGUAGE == C */ | ||
| 184 | |||
| 185 | /* System Controller | ||
| 186 | * | ||
| 187 | * Registers | ||
| 188 | * SKPCR Power Control Register | ||
| 189 | * SKCDR Clock Divider Register | ||
| 190 | * DACDR1 DAC1 Data register | ||
| 191 | * DACDR2 DAC2 Data register | ||
| 192 | */ | ||
| 193 | |||
| 194 | #define _SKPCR _SA1101(0x00000400) | ||
| 195 | #define _SKCDR _SA1101(0x00040000) | ||
| 196 | #define _DACDR1 _SA1101(0x00060000) | ||
| 197 | #define _DACDR2 _SA1101(0x00060400) | ||
| 198 | |||
| 199 | #if LANGUAGE == C | ||
| 200 | #define SKPCR (*((volatile Word *) SA1101_p2v (_SKPCR))) | ||
| 201 | #define SKCDR (*((volatile Word *) SA1101_p2v (_SKCDR))) | ||
| 202 | #define DACDR1 (*((volatile Word *) SA1101_p2v (_DACDR1))) | ||
| 203 | #define DACDR2 (*((volatile Word *) SA1101_p2v (_DACDR2))) | ||
| 204 | |||
| 205 | #define SKPCR_UCLKEn 0x01 /* USB Enable */ | ||
| 206 | #define SKPCR_PCLKEn 0x02 /* PS/2 Enable */ | ||
| 207 | #define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */ | ||
| 208 | #define SKPCR_VCLKEn 0x08 /* Video Controller Enable */ | ||
| 209 | #define SKPCR_PICLKEn 0x10 /* parallel port Enable */ | ||
| 210 | #define SKPCR_DCLKEn 0x20 /* DACs Enable */ | ||
| 211 | #define SKPCR_nKPADEn 0x40 /* Multiplexer */ | ||
| 212 | |||
| 213 | #define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */ | ||
| 214 | #define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */ | ||
| 215 | #define SKDCR_BCLKEn (1<<9) /* BCLK Divider */ | ||
| 216 | #define SKDCR_UTESTCLKEn (1<<10) /* Route USB clock during test mode */ | ||
| 217 | #define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */ | ||
| 218 | #define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */ | ||
| 219 | #define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */ | ||
| 220 | #define SKDCR_ChargePump (1<<25) /* Charge pump control */ | ||
| 221 | #define SKDCR_ClkTestMode (1<<26) /* Clock output test mode */ | ||
| 222 | #define SKDCR_ClkTestEn (1<<27) /* Test clock generator */ | ||
| 223 | #define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */ | ||
| 224 | |||
| 225 | #define DACDR_DACCount Fld(8,0) /* Count value */ | ||
| 226 | #define DACDR1_DACCount DACDR_DACCount | ||
| 227 | #define DACDR2_DACCount DACDR_DACCount | ||
| 228 | |||
| 229 | #endif /* LANGUAGE == C */ | ||
| 230 | |||
| 231 | /* | ||
| 232 | * Parallel Port Interface | ||
| 233 | * | ||
| 234 | * Registers | ||
| 235 | * IEEE_Config IEEE mode selection and programmable attributes | ||
| 236 | * IEEE_Control Controls the states of IEEE port control outputs | ||
| 237 | * IEEE_Data Forward transfer data register | ||
| 238 | * IEEE_Addr Forward transfer address register | ||
| 239 | * IEEE_Status Port IO signal status register | ||
| 240 | * IEEE_IntStatus Port interrupts status register | ||
| 241 | * IEEE_FifoLevels Rx and Tx FIFO interrupt generation levels | ||
| 242 | * IEEE_InitTime Forward timeout counter initial value | ||
| 243 | * IEEE_TimerStatus Forward timeout counter current value | ||
| 244 | * IEEE_FifoReset Reset forward transfer FIFO | ||
| 245 | * IEEE_ReloadValue Counter reload value | ||
| 246 | * IEEE_TestControl Control testmode | ||
| 247 | * IEEE_TestDataIn Test data register | ||
| 248 | * IEEE_TestDataInEn Enable test data | ||
| 249 | * IEEE_TestCtrlIn Test control signals | ||
| 250 | * IEEE_TestCtrlInEn Enable test control signals | ||
| 251 | * IEEE_TestDataStat Current data bus value | ||
| 252 | * | ||
| 253 | */ | ||
| 254 | |||
| 255 | /* | ||
| 256 | * The control registers are defined as offsets from a base address | ||
| 257 | */ | ||
| 258 | |||
| 259 | #define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT ) | ||
| 260 | |||
| 261 | #define _IEEE_Config _IEEE( 0x0000 ) | ||
| 262 | #define _IEEE_Control _IEEE( 0x0400 ) | ||
| 263 | #define _IEEE_Data _IEEE( 0x4000 ) | ||
| 264 | #define _IEEE_Addr _IEEE( 0x0800 ) | ||
| 265 | #define _IEEE_Status _IEEE( 0x0c00 ) | ||
| 266 | #define _IEEE_IntStatus _IEEE( 0x1000 ) | ||
| 267 | #define _IEEE_FifoLevels _IEEE( 0x1400 ) | ||
| 268 | #define _IEEE_InitTime _IEEE( 0x1800 ) | ||
| 269 | #define _IEEE_TimerStatus _IEEE( 0x1c00 ) | ||
| 270 | #define _IEEE_FifoReset _IEEE( 0x2000 ) | ||
| 271 | #define _IEEE_ReloadValue _IEEE( 0x3c00 ) | ||
| 272 | #define _IEEE_TestControl _IEEE( 0x2400 ) | ||
| 273 | #define _IEEE_TestDataIn _IEEE( 0x2800 ) | ||
| 274 | #define _IEEE_TestDataInEn _IEEE( 0x2c00 ) | ||
| 275 | #define _IEEE_TestCtrlIn _IEEE( 0x3000 ) | ||
| 276 | #define _IEEE_TestCtrlInEn _IEEE( 0x3400 ) | ||
| 277 | #define _IEEE_TestDataStat _IEEE( 0x3800 ) | ||
| 278 | |||
| 279 | |||
| 280 | #if LANGUAGE == C | ||
| 281 | #define IEEE_Config (*((volatile Word *) SA1101_p2v (_IEEE_Config))) | ||
| 282 | #define IEEE_Control (*((volatile Word *) SA1101_p2v (_IEEE_Control))) | ||
| 283 | #define IEEE_Data (*((volatile Word *) SA1101_p2v (_IEEE_Data))) | ||
| 284 | #define IEEE_Addr (*((volatile Word *) SA1101_p2v (_IEEE_Addr))) | ||
| 285 | #define IEEE_Status (*((volatile Word *) SA1101_p2v (_IEEE_Status))) | ||
| 286 | #define IEEE_IntStatus (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus))) | ||
| 287 | #define IEEE_FifoLevels (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels))) | ||
| 288 | #define IEEE_InitTime (*((volatile Word *) SA1101_p2v (_IEEE_InitTime))) | ||
| 289 | #define IEEE_TimerStatus (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus))) | ||
| 290 | #define IEEE_FifoReset (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset))) | ||
| 291 | #define IEEE_ReloadValue (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue))) | ||
| 292 | #define IEEE_TestControl (*((volatile Word *) SA1101_p2v (_IEEE_TestControl))) | ||
| 293 | #define IEEE_TestDataIn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn))) | ||
| 294 | #define IEEE_TestDataInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn))) | ||
| 295 | #define IEEE_TestCtrlIn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn))) | ||
| 296 | #define IEEE_TestCtrlInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn))) | ||
| 297 | #define IEEE_TestDataStat (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat))) | ||
| 298 | |||
| 299 | |||
| 300 | #define IEEE_Config_M Fld(3,0) /* Mode select */ | ||
| 301 | #define IEEE_Config_D 0x04 /* FIFO access enable */ | ||
| 302 | #define IEEE_Config_B 0x08 /* 9-bit word enable */ | ||
| 303 | #define IEEE_Config_T 0x10 /* Data transfer enable */ | ||
| 304 | #define IEEE_Config_A 0x20 /* Data transfer direction */ | ||
| 305 | #define IEEE_Config_E 0x40 /* Timer enable */ | ||
| 306 | #define IEEE_Control_A 0x08 /* AutoFd output */ | ||
| 307 | #define IEEE_Control_E 0x04 /* Selectin output */ | ||
| 308 | #define IEEE_Control_T 0x02 /* Strobe output */ | ||
| 309 | #define IEEE_Control_I 0x01 /* Port init output */ | ||
| 310 | #define IEEE_Data_C (1<<31) /* Byte count */ | ||
| 311 | #define IEEE_Data_Db Fld(9,16) /* Data byte 2 */ | ||
| 312 | #define IEEE_Data_Da Fld(9,0) /* Data byte 1 */ | ||
| 313 | #define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */ | ||
| 314 | #define IEEE_Status_A 0x0100 /* nAutoFd port output status */ | ||
| 315 | #define IEEE_Status_E 0x0080 /* nSelectIn port output status */ | ||
| 316 | #define IEEE_Status_T 0x0040 /* nStrobe port output status */ | ||
| 317 | #define IEEE_Status_I 0x0020 /* nInit port output status */ | ||
| 318 | #define IEEE_Status_B 0x0010 /* Busy port inout status */ | ||
| 319 | #define IEEE_Status_S 0x0008 /* Select port input status */ | ||
| 320 | #define IEEE_Status_K 0x0004 /* nAck port input status */ | ||
| 321 | #define IEEE_Status_F 0x0002 /* nFault port input status */ | ||
| 322 | #define IEEE_Status_R 0x0001 /* pError port input status */ | ||
| 323 | |||
| 324 | #define IEEE_IntStatus_IntReqDat 0x0100 | ||
| 325 | #define IEEE_IntStatus_IntReqEmp 0x0080 | ||
| 326 | #define IEEE_IntStatus_IntReqInt 0x0040 | ||
| 327 | #define IEEE_IntStatus_IntReqRav 0x0020 | ||
| 328 | #define IEEE_IntStatus_IntReqTim 0x0010 | ||
| 329 | #define IEEE_IntStatus_RevAddrComp 0x0008 | ||
| 330 | #define IEEE_IntStatus_RevDataComp 0x0004 | ||
| 331 | #define IEEE_IntStatus_FwdAddrComp 0x0002 | ||
| 332 | #define IEEE_IntStatus_FwdDataComp 0x0001 | ||
| 333 | #define IEEE_FifoLevels_RevFifoLevel 2 | ||
| 334 | #define IEEE_FifoLevels_FwdFifoLevel 1 | ||
| 335 | #define IEEE_InitTime_TimValInit Fld(22,0) | ||
| 336 | #define IEEE_TimerStatus_TimValStat Fld(22,0) | ||
| 337 | #define IEEE_ReloadValue_Reload Fld(4,0) | ||
| 338 | |||
| 339 | #define IEEE_TestControl_RegClk 0x04 | ||
| 340 | #define IEEE_TestControl_ClockSelect Fld(2,1) | ||
| 341 | #define IEEE_TestControl_TimerTestModeEn 0x01 | ||
| 342 | #define IEEE_TestCtrlIn_PError 0x10 | ||
| 343 | #define IEEE_TestCtrlIn_nFault 0x08 | ||
| 344 | #define IEEE_TestCtrlIn_nAck 0x04 | ||
| 345 | #define IEEE_TestCtrlIn_PSel 0x02 | ||
| 346 | #define IEEE_TestCtrlIn_Busy 0x01 | ||
| 347 | |||
| 348 | #endif /* LANGUAGE == C */ | ||
| 349 | |||
| 350 | /* | ||
| 351 | * VGA Controller | ||
| 352 | * | ||
| 353 | * Registers | ||
| 354 | * VideoControl Video Control Register | ||
| 355 | * VgaTiming0 VGA Timing Register 0 | ||
| 356 | * VgaTiming1 VGA Timing Register 1 | ||
| 357 | * VgaTiming2 VGA Timing Register 2 | ||
| 358 | * VgaTiming3 VGA Timing Register 3 | ||
| 359 | * VgaBorder VGA Border Color Register | ||
| 360 | * VgaDBAR VGADMA Base Address Register | ||
| 361 | * VgaDCAR VGADMA Channel Current Address Register | ||
| 362 | * VgaStatus VGA Status Register | ||
| 363 | * VgaInterruptMask VGA Interrupt Mask Register | ||
| 364 | * VgaPalette VGA Palette Registers | ||
| 365 | * DacControl DAC Control Register | ||
| 366 | * VgaTest VGA Controller Test Register | ||
| 367 | */ | ||
| 368 | |||
| 369 | #define _VGA( x ) _SA1101( ( x ) + __VGA_CONTROL ) | ||
| 370 | |||
| 371 | #define _VideoControl _VGA( 0x0000 ) | ||
| 372 | #define _VgaTiming0 _VGA( 0x0400 ) | ||
| 373 | #define _VgaTiming1 _VGA( 0x0800 ) | ||
| 374 | #define _VgaTiming2 _VGA( 0x0c00 ) | ||
| 375 | #define _VgaTiming3 _VGA( 0x1000 ) | ||
| 376 | #define _VgaBorder _VGA( 0x1400 ) | ||
| 377 | #define _VgaDBAR _VGA( 0x1800 ) | ||
| 378 | #define _VgaDCAR _VGA( 0x1c00 ) | ||
| 379 | #define _VgaStatus _VGA( 0x2000 ) | ||
| 380 | #define _VgaInterruptMask _VGA( 0x2400 ) | ||
| 381 | #define _VgaPalette _VGA( 0x40000 ) | ||
| 382 | #define _DacControl _VGA( 0x3000 ) | ||
| 383 | #define _VgaTest _VGA( 0x2c00 ) | ||
| 384 | |||
| 385 | #if (LANGUAGE == C) | ||
| 386 | #define VideoControl (*((volatile Word *) SA1101_p2v (_VideoControl))) | ||
| 387 | #define VgaTiming0 (*((volatile Word *) SA1101_p2v (_VgaTiming0))) | ||
| 388 | #define VgaTiming1 (*((volatile Word *) SA1101_p2v (_VgaTiming1))) | ||
| 389 | #define VgaTiming2 (*((volatile Word *) SA1101_p2v (_VgaTiming2))) | ||
| 390 | #define VgaTiming3 (*((volatile Word *) SA1101_p2v (_VgaTiming3))) | ||
| 391 | #define VgaBorder (*((volatile Word *) SA1101_p2v (_VgaBorder))) | ||
| 392 | #define VgaDBAR (*((volatile Word *) SA1101_p2v (_VgaDBAR))) | ||
| 393 | #define VgaDCAR (*((volatile Word *) SA1101_p2v (_VgaDCAR))) | ||
| 394 | #define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus))) | ||
| 395 | #define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask))) | ||
| 396 | #define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette))) | ||
| 397 | #define DacControl (*((volatile Word *) SA1101_p2v (_DacControl))) | ||
| 398 | #define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest))) | ||
| 399 | |||
| 400 | #define VideoControl_VgaEn 0x00000000 | ||
| 401 | #define VideoControl_BGR 0x00000001 | ||
| 402 | #define VideoControl_VCompVal Fld(2,2) | ||
| 403 | #define VideoControl_VgaReq Fld(4,4) | ||
| 404 | #define VideoControl_VBurstL Fld(4,8) | ||
| 405 | #define VideoControl_VMode (1<<12) | ||
| 406 | #define VideoControl_PalRead (1<<13) | ||
| 407 | |||
| 408 | #define VgaTiming0_PPL Fld(6,2) | ||
| 409 | #define VgaTiming0_HSW Fld(8,8) | ||
| 410 | #define VgaTiming0_HFP Fld(8,16) | ||
| 411 | #define VgaTiming0_HBP Fld(8,24) | ||
| 412 | |||
| 413 | #define VgaTiming1_LPS Fld(10,0) | ||
| 414 | #define VgaTiming1_VSW Fld(6,10) | ||
| 415 | #define VgaTiming1_VFP Fld(8,16) | ||
| 416 | #define VgaTiming1_VBP Fld(8,24) | ||
| 417 | |||
| 418 | #define VgaTiming2_IVS 0x01 | ||
| 419 | #define VgaTiming2_IHS 0x02 | ||
| 420 | #define VgaTiming2_CVS 0x04 | ||
| 421 | #define VgaTiming2_CHS 0x08 | ||
| 422 | |||
| 423 | #define VgaTiming3_HBS Fld(8,0) | ||
| 424 | #define VgaTiming3_HBE Fld(8,8) | ||
| 425 | #define VgaTiming3_VBS Fld(8,16) | ||
| 426 | #define VgaTiming3_VBE Fld(8,24) | ||
| 427 | |||
| 428 | #define VgaBorder_BCOL Fld(24,0) | ||
| 429 | |||
| 430 | #define VgaStatus_VFUF 0x01 | ||
| 431 | #define VgaStatus_VNext 0x02 | ||
| 432 | #define VgaStatus_VComp 0x04 | ||
| 433 | |||
| 434 | #define VgaInterruptMask_VFUFMask 0x00 | ||
| 435 | #define VgaInterruptMask_VNextMask 0x01 | ||
| 436 | #define VgaInterruptMask_VCompMask 0x02 | ||
| 437 | |||
| 438 | #define VgaPalette_R Fld(8,0) | ||
| 439 | #define VgaPalette_G Fld(8,8) | ||
| 440 | #define VgaPalette_B Fld(8,16) | ||
| 441 | |||
| 442 | #define DacControl_DACON 0x0001 | ||
| 443 | #define DacControl_COMPON 0x0002 | ||
| 444 | #define DacControl_PEDON 0x0004 | ||
| 445 | #define DacControl_RTrim Fld(5,4) | ||
| 446 | #define DacControl_GTrim Fld(5,9) | ||
| 447 | #define DacControl_BTrim Fld(5,14) | ||
| 448 | |||
| 449 | #define VgaTest_TDAC 0x00 | ||
| 450 | #define VgaTest_Datatest Fld(4,1) | ||
| 451 | #define VgaTest_DACTESTDAC 0x10 | ||
| 452 | #define VgaTest_DACTESTOUT Fld(3,5) | ||
| 453 | |||
| 454 | #endif /* LANGUAGE == C */ | ||
| 455 | |||
| 456 | /* | ||
| 457 | * USB Host Interface Controller | ||
| 458 | * | ||
| 459 | * Registers | ||
| 460 | * Revision | ||
| 461 | * Control | ||
| 462 | * CommandStatus | ||
| 463 | * InterruptStatus | ||
| 464 | * InterruptEnable | ||
| 465 | * HCCA | ||
| 466 | * PeriodCurrentED | ||
| 467 | * ControlHeadED | ||
| 468 | * BulkHeadED | ||
| 469 | * BulkCurrentED | ||
| 470 | * DoneHead | ||
| 471 | * FmInterval | ||
| 472 | * FmRemaining | ||
| 473 | * FmNumber | ||
| 474 | * PeriodicStart | ||
| 475 | * LSThreshold | ||
| 476 | * RhDescriptorA | ||
| 477 | * RhDescriptorB | ||
| 478 | * RhStatus | ||
| 479 | * RhPortStatus | ||
| 480 | * USBStatus | ||
| 481 | * USBReset | ||
| 482 | * USTAR | ||
| 483 | * USWER | ||
| 484 | * USRFR | ||
| 485 | * USNFR | ||
| 486 | * USTCSR | ||
| 487 | * USSR | ||
| 488 | * | ||
| 489 | */ | ||
| 490 | |||
| 491 | #define _USB( x ) _SA1101( ( x ) + __USB_CONTROL ) | ||
| 492 | |||
| 493 | |||
| 494 | #define _Revision _USB( 0x0000 ) | ||
| 495 | #define _Control _USB( 0x0888 ) | ||
| 496 | #define _CommandStatus _USB( 0x0c00 ) | ||
| 497 | #define _InterruptStatus _USB( 0x1000 ) | ||
| 498 | #define _InterruptEnable _USB( 0x1400 ) | ||
| 499 | #define _HCCA _USB( 0x1800 ) | ||
| 500 | #define _PeriodCurrentED _USB( 0x1c00 ) | ||
| 501 | #define _ControlHeadED _USB( 0x2000 ) | ||
| 502 | #define _BulkHeadED _USB( 0x2800 ) | ||
| 503 | #define _BulkCurrentED _USB( 0x2c00 ) | ||
| 504 | #define _DoneHead _USB( 0x3000 ) | ||
| 505 | #define _FmInterval _USB( 0x3400 ) | ||
| 506 | #define _FmRemaining _USB( 0x3800 ) | ||
| 507 | #define _FmNumber _USB( 0x3c00 ) | ||
| 508 | #define _PeriodicStart _USB( 0x4000 ) | ||
| 509 | #define _LSThreshold _USB( 0x4400 ) | ||
| 510 | #define _RhDescriptorA _USB( 0x4800 ) | ||
| 511 | #define _RhDescriptorB _USB( 0x4c00 ) | ||
| 512 | #define _RhStatus _USB( 0x5000 ) | ||
| 513 | #define _RhPortStatus _USB( 0x5400 ) | ||
| 514 | #define _USBStatus _USB( 0x11800 ) | ||
| 515 | #define _USBReset _USB( 0x11c00 ) | ||
| 516 | |||
| 517 | #define _USTAR _USB( 0x10400 ) | ||
| 518 | #define _USWER _USB( 0x10800 ) | ||
| 519 | #define _USRFR _USB( 0x10c00 ) | ||
| 520 | #define _USNFR _USB( 0x11000 ) | ||
| 521 | #define _USTCSR _USB( 0x11400 ) | ||
| 522 | #define _USSR _USB( 0x11800 ) | ||
| 523 | |||
| 524 | |||
| 525 | #if (LANGUAGE == C) | ||
| 526 | |||
| 527 | #define Revision (*((volatile Word *) SA1101_p2v (_Revision))) | ||
| 528 | #define Control (*((volatile Word *) SA1101_p2v (_Control))) | ||
| 529 | #define CommandStatus (*((volatile Word *) SA1101_p2v (_CommandStatus))) | ||
| 530 | #define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus))) | ||
| 531 | #define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable))) | ||
| 532 | #define HCCA (*((volatile Word *) SA1101_p2v (_HCCA))) | ||
| 533 | #define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED))) | ||
| 534 | #define ControlHeadED (*((volatile Word *) SA1101_p2v (_ControlHeadED))) | ||
| 535 | #define BulkHeadED (*((volatile Word *) SA1101_p2v (_BulkHeadED))) | ||
| 536 | #define BulkCurrentED (*((volatile Word *) SA1101_p2v (_BulkCurrentED))) | ||
| 537 | #define DoneHead (*((volatile Word *) SA1101_p2v (_DoneHead))) | ||
| 538 | #define FmInterval (*((volatile Word *) SA1101_p2v (_FmInterval))) | ||
| 539 | #define FmRemaining (*((volatile Word *) SA1101_p2v (_FmRemaining))) | ||
| 540 | #define FmNumber (*((volatile Word *) SA1101_p2v (_FmNumber))) | ||
| 541 | #define PeriodicStart (*((volatile Word *) SA1101_p2v (_PeriodicStart))) | ||
| 542 | #define LSThreshold (*((volatile Word *) SA1101_p2v (_LSThreshold))) | ||
| 543 | #define RhDescriptorA (*((volatile Word *) SA1101_p2v (_RhDescriptorA))) | ||
| 544 | #define RhDescriptorB (*((volatile Word *) SA1101_p2v (_RhDescriptorB))) | ||
| 545 | #define RhStatus (*((volatile Word *) SA1101_p2v (_RhStatus))) | ||
| 546 | #define RhPortStatus (*((volatile Word *) SA1101_p2v (_RhPortStatus))) | ||
| 547 | #define USBStatus (*((volatile Word *) SA1101_p2v (_USBStatus))) | ||
| 548 | #define USBReset (*((volatile Word *) SA1101_p2v (_USBReset))) | ||
| 549 | #define USTAR (*((volatile Word *) SA1101_p2v (_USTAR))) | ||
| 550 | #define USWER (*((volatile Word *) SA1101_p2v (_USWER))) | ||
| 551 | #define USRFR (*((volatile Word *) SA1101_p2v (_USRFR))) | ||
| 552 | #define USNFR (*((volatile Word *) SA1101_p2v (_USNFR))) | ||
| 553 | #define USTCSR (*((volatile Word *) SA1101_p2v (_USTCSR))) | ||
| 554 | #define USSR (*((volatile Word *) SA1101_p2v (_USSR))) | ||
| 555 | |||
| 556 | |||
| 557 | #define USBStatus_IrqHciRmtWkp (1<<7) | ||
| 558 | #define USBStatus_IrqHciBuffAcc (1<<8) | ||
| 559 | #define USBStatus_nIrqHciM (1<<9) | ||
| 560 | #define USBStatus_nHciMFClr (1<<10) | ||
| 561 | |||
| 562 | #define USBReset_ForceIfReset 0x01 | ||
| 563 | #define USBReset_ForceHcReset 0x02 | ||
| 564 | #define USBReset_ClkGenReset 0x04 | ||
| 565 | |||
| 566 | #define USTCR_RdBstCntrl Fld(3,0) | ||
| 567 | #define USTCR_ByteEnable Fld(4,3) | ||
| 568 | #define USTCR_WriteEn (1<<7) | ||
| 569 | #define USTCR_FifoCir (1<<8) | ||
| 570 | #define USTCR_TestXferSel (1<<9) | ||
| 571 | #define USTCR_FifoCirAtEnd (1<<10) | ||
| 572 | #define USTCR_nSimScaleDownClk (1<<11) | ||
| 573 | |||
| 574 | #define USSR_nAppMDEmpty 0x01 | ||
| 575 | #define USSR_nAppMDFirst 0x02 | ||
| 576 | #define USSR_nAppMDLast 0x04 | ||
| 577 | #define USSR_nAppMDFull 0x08 | ||
| 578 | #define USSR_nAppMAFull 0x10 | ||
| 579 | #define USSR_XferReq 0x20 | ||
| 580 | #define USSR_XferEnd 0x40 | ||
| 581 | |||
| 582 | #endif /* LANGUAGE == C */ | ||
| 583 | |||
| 584 | |||
| 585 | /* | ||
| 586 | * Interrupt Controller | ||
| 587 | * | ||
| 588 | * Registers | ||
| 589 | * INTTEST0 Test register 0 | ||
| 590 | * INTTEST1 Test register 1 | ||
| 591 | * INTENABLE0 Interrupt Enable register 0 | ||
| 592 | * INTENABLE1 Interrupt Enable register 1 | ||
| 593 | * INTPOL0 Interrupt Polarity selection 0 | ||
| 594 | * INTPOL1 Interrupt Polarity selection 1 | ||
| 595 | * INTTSTSEL Interrupt source selection | ||
| 596 | * INTSTATCLR0 Interrupt Status 0 | ||
| 597 | * INTSTATCLR1 Interrupt Status 1 | ||
| 598 | * INTSET0 Interrupt Set 0 | ||
| 599 | * INTSET1 Interrupt Set 1 | ||
| 600 | */ | ||
| 601 | |||
| 602 | #define _INT( x ) _SA1101( ( x ) + __INTERRUPT_CONTROL) | ||
| 603 | |||
| 604 | #define _INTTEST0 _INT( 0x1000 ) | ||
| 605 | #define _INTTEST1 _INT( 0x1400 ) | ||
| 606 | #define _INTENABLE0 _INT( 0x2000 ) | ||
| 607 | #define _INTENABLE1 _INT( 0x2400 ) | ||
| 608 | #define _INTPOL0 _INT( 0x3000 ) | ||
| 609 | #define _INTPOL1 _INT( 0x3400 ) | ||
| 610 | #define _INTTSTSEL _INT( 0x5000 ) | ||
| 611 | #define _INTSTATCLR0 _INT( 0x6000 ) | ||
| 612 | #define _INTSTATCLR1 _INT( 0x6400 ) | ||
| 613 | #define _INTSET0 _INT( 0x7000 ) | ||
| 614 | #define _INTSET1 _INT( 0x7400 ) | ||
| 615 | |||
| 616 | #if ( LANGUAGE == C ) | ||
| 617 | #define INTTEST0 (*((volatile Word *) SA1101_p2v (_INTTEST0))) | ||
| 618 | #define INTTEST1 (*((volatile Word *) SA1101_p2v (_INTTEST1))) | ||
| 619 | #define INTENABLE0 (*((volatile Word *) SA1101_p2v (_INTENABLE0))) | ||
| 620 | #define INTENABLE1 (*((volatile Word *) SA1101_p2v (_INTENABLE1))) | ||
| 621 | #define INTPOL0 (*((volatile Word *) SA1101_p2v (_INTPOL0))) | ||
| 622 | #define INTPOL1 (*((volatile Word *) SA1101_p2v (_INTPOL1))) | ||
| 623 | #define INTTSTSEL (*((volatile Word *) SA1101_p2v (_INTTSTSEL))) | ||
| 624 | #define INTSTATCLR0 (*((volatile Word *) SA1101_p2v (_INTSTATCLR0))) | ||
| 625 | #define INTSTATCLR1 (*((volatile Word *) SA1101_p2v (_INTSTATCLR1))) | ||
| 626 | #define INTSET0 (*((volatile Word *) SA1101_p2v (_INTSET0))) | ||
| 627 | #define INTSET1 (*((volatile Word *) SA1101_p2v (_INTSET1))) | ||
| 628 | |||
| 629 | #endif /* LANGUAGE == C */ | ||
| 630 | |||
| 631 | /* | ||
| 632 | * PS/2 Trackpad and Mouse Interfaces | ||
| 633 | * | ||
| 634 | * Registers (prefix kbd applies to trackpad interface, mse to mouse) | ||
| 635 | * KBDCR Control Register | ||
| 636 | * KBDSTAT Status Register | ||
| 637 | * KBDDATA Transmit/Receive Data register | ||
| 638 | * KBDCLKDIV Clock Division Register | ||
| 639 | * KBDPRECNT Clock Precount Register | ||
| 640 | * KBDTEST1 Test register 1 | ||
| 641 | * KBDTEST2 Test register 2 | ||
| 642 | * KBDTEST3 Test register 3 | ||
| 643 | * KBDTEST4 Test register 4 | ||
| 644 | * MSECR | ||
| 645 | * MSESTAT | ||
| 646 | * MSEDATA | ||
| 647 | * MSECLKDIV | ||
| 648 | * MSEPRECNT | ||
| 649 | * MSETEST1 | ||
| 650 | * MSETEST2 | ||
| 651 | * MSETEST3 | ||
| 652 | * MSETEST4 | ||
| 653 | * | ||
| 654 | */ | ||
| 655 | |||
| 656 | #define _KBD( x ) _SA1101( ( x ) + __TRACK_INTERFACE ) | ||
| 657 | #define _MSE( x ) _SA1101( ( x ) + __MOUSE_INTERFACE ) | ||
| 658 | |||
| 659 | #define _KBDCR _KBD( 0x0000 ) | ||
| 660 | #define _KBDSTAT _KBD( 0x0400 ) | ||
| 661 | #define _KBDDATA _KBD( 0x0800 ) | ||
| 662 | #define _KBDCLKDIV _KBD( 0x0c00 ) | ||
| 663 | #define _KBDPRECNT _KBD( 0x1000 ) | ||
| 664 | #define _KBDTEST1 _KBD( 0x2000 ) | ||
| 665 | #define _KBDTEST2 _KBD( 0x2400 ) | ||
| 666 | #define _KBDTEST3 _KBD( 0x2800 ) | ||
| 667 | #define _KBDTEST4 _KBD( 0x2c00 ) | ||
| 668 | #define _MSECR _MSE( 0x0000 ) | ||
| 669 | #define _MSESTAT _MSE( 0x0400 ) | ||
| 670 | #define _MSEDATA _MSE( 0x0800 ) | ||
| 671 | #define _MSECLKDIV _MSE( 0x0c00 ) | ||
| 672 | #define _MSEPRECNT _MSE( 0x1000 ) | ||
| 673 | #define _MSETEST1 _MSE( 0x2000 ) | ||
| 674 | #define _MSETEST2 _MSE( 0x2400 ) | ||
| 675 | #define _MSETEST3 _MSE( 0x2800 ) | ||
| 676 | #define _MSETEST4 _MSE( 0x2c00 ) | ||
| 677 | |||
| 678 | #if ( LANGUAGE == C ) | ||
| 679 | |||
| 680 | #define KBDCR (*((volatile Word *) SA1101_p2v (_KBDCR))) | ||
| 681 | #define KBDSTAT (*((volatile Word *) SA1101_p2v (_KBDSTAT))) | ||
| 682 | #define KBDDATA (*((volatile Word *) SA1101_p2v (_KBDDATA))) | ||
| 683 | #define KBDCLKDIV (*((volatile Word *) SA1101_p2v (_KBDCLKDIV))) | ||
| 684 | #define KBDPRECNT (*((volatile Word *) SA1101_p2v (_KBDPRECNT))) | ||
| 685 | #define KBDTEST1 (*((volatile Word *) SA1101_p2v (_KBDTEST1))) | ||
| 686 | #define KBDTEST2 (*((volatile Word *) SA1101_p2v (_KBDTEST2))) | ||
| 687 | #define KBDTEST3 (*((volatile Word *) SA1101_p2v (_KBDTEST3))) | ||
| 688 | #define KBDTEST4 (*((volatile Word *) SA1101_p2v (_KBDTEST4))) | ||
| 689 | #define MSECR (*((volatile Word *) SA1101_p2v (_MSECR))) | ||
| 690 | #define MSESTAT (*((volatile Word *) SA1101_p2v (_MSESTAT))) | ||
| 691 | #define MSEDATA (*((volatile Word *) SA1101_p2v (_MSEDATA))) | ||
| 692 | #define MSECLKDIV (*((volatile Word *) SA1101_p2v (_MSECLKDIV))) | ||
| 693 | #define MSEPRECNT (*((volatile Word *) SA1101_p2v (_MSEPRECNT))) | ||
| 694 | #define MSETEST1 (*((volatile Word *) SA1101_p2v (_MSETEST1))) | ||
| 695 | #define MSETEST2 (*((volatile Word *) SA1101_p2v (_MSETEST2))) | ||
| 696 | #define MSETEST3 (*((volatile Word *) SA1101_p2v (_MSETEST3))) | ||
| 697 | #define MSETEST4 (*((volatile Word *) SA1101_p2v (_MSETEST4))) | ||
| 698 | |||
| 699 | |||
| 700 | #define KBDCR_ENA 0x08 | ||
| 701 | #define KBDCR_FKD 0x02 | ||
| 702 | #define KBDCR_FKC 0x01 | ||
| 703 | |||
| 704 | #define KBDSTAT_TXE 0x80 | ||
| 705 | #define KBDSTAT_TXB 0x40 | ||
| 706 | #define KBDSTAT_RXF 0x20 | ||
| 707 | #define KBDSTAT_RXB 0x10 | ||
| 708 | #define KBDSTAT_ENA 0x08 | ||
| 709 | #define KBDSTAT_RXP 0x04 | ||
| 710 | #define KBDSTAT_KBD 0x02 | ||
| 711 | #define KBDSTAT_KBC 0x01 | ||
| 712 | |||
| 713 | #define KBDCLKDIV_DivVal Fld(4,0) | ||
| 714 | |||
| 715 | #define MSECR_ENA 0x08 | ||
| 716 | #define MSECR_FKD 0x02 | ||
| 717 | #define MSECR_FKC 0x01 | ||
| 718 | |||
| 719 | #define MSESTAT_TXE 0x80 | ||
| 720 | #define MSESTAT_TXB 0x40 | ||
| 721 | #define MSESTAT_RXF 0x20 | ||
| 722 | #define MSESTAT_RXB 0x10 | ||
| 723 | #define MSESTAT_ENA 0x08 | ||
| 724 | #define MSESTAT_RXP 0x04 | ||
| 725 | #define MSESTAT_MSD 0x02 | ||
| 726 | #define MSESTAT_MSC 0x01 | ||
| 727 | |||
| 728 | #define MSECLKDIV_DivVal Fld(4,0) | ||
| 729 | |||
| 730 | #define KBDTEST1_CD 0x80 | ||
| 731 | #define KBDTEST1_RC1 0x40 | ||
| 732 | #define KBDTEST1_MC 0x20 | ||
| 733 | #define KBDTEST1_C Fld(2,3) | ||
| 734 | #define KBDTEST1_T2 0x40 | ||
| 735 | #define KBDTEST1_T1 0x20 | ||
| 736 | #define KBDTEST1_T0 0x10 | ||
| 737 | #define KBDTEST2_TICBnRES 0x08 | ||
| 738 | #define KBDTEST2_RKC 0x04 | ||
| 739 | #define KBDTEST2_RKD 0x02 | ||
| 740 | #define KBDTEST2_SEL 0x01 | ||
| 741 | #define KBDTEST3_ms_16 0x80 | ||
| 742 | #define KBDTEST3_us_64 0x40 | ||
| 743 | #define KBDTEST3_us_16 0x20 | ||
| 744 | #define KBDTEST3_DIV8 0x10 | ||
| 745 | #define KBDTEST3_DIn 0x08 | ||
| 746 | #define KBDTEST3_CIn 0x04 | ||
| 747 | #define KBDTEST3_KD 0x02 | ||
| 748 | #define KBDTEST3_KC 0x01 | ||
| 749 | #define KBDTEST4_BC12 0x80 | ||
| 750 | #define KBDTEST4_BC11 0x40 | ||
| 751 | #define KBDTEST4_TRES 0x20 | ||
| 752 | #define KBDTEST4_CLKOE 0x10 | ||
| 753 | #define KBDTEST4_CRES 0x08 | ||
| 754 | #define KBDTEST4_RXB 0x04 | ||
| 755 | #define KBDTEST4_TXB 0x02 | ||
| 756 | #define KBDTEST4_SRX 0x01 | ||
| 757 | |||
| 758 | #define MSETEST1_CD 0x80 | ||
| 759 | #define MSETEST1_RC1 0x40 | ||
| 760 | #define MSETEST1_MC 0x20 | ||
| 761 | #define MSETEST1_C Fld(2,3) | ||
| 762 | #define MSETEST1_T2 0x40 | ||
| 763 | #define MSETEST1_T1 0x20 | ||
| 764 | #define MSETEST1_T0 0x10 | ||
| 765 | #define MSETEST2_TICBnRES 0x08 | ||
| 766 | #define MSETEST2_RKC 0x04 | ||
| 767 | #define MSETEST2_RKD 0x02 | ||
| 768 | #define MSETEST2_SEL 0x01 | ||
| 769 | #define MSETEST3_ms_16 0x80 | ||
| 770 | #define MSETEST3_us_64 0x40 | ||
| 771 | #define MSETEST3_us_16 0x20 | ||
| 772 | #define MSETEST3_DIV8 0x10 | ||
| 773 | #define MSETEST3_DIn 0x08 | ||
| 774 | #define MSETEST3_CIn 0x04 | ||
| 775 | #define MSETEST3_KD 0x02 | ||
| 776 | #define MSETEST3_KC 0x01 | ||
| 777 | #define MSETEST4_BC12 0x80 | ||
| 778 | #define MSETEST4_BC11 0x40 | ||
| 779 | #define MSETEST4_TRES 0x20 | ||
| 780 | #define MSETEST4_CLKOE 0x10 | ||
| 781 | #define MSETEST4_CRES 0x08 | ||
| 782 | #define MSETEST4_RXB 0x04 | ||
| 783 | #define MSETEST4_TXB 0x02 | ||
| 784 | #define MSETEST4_SRX 0x01 | ||
| 785 | |||
| 786 | #endif /* LANGUAGE == C */ | ||
| 787 | |||
| 788 | |||
| 789 | /* | ||
| 790 | * General-Purpose I/O Interface | ||
| 791 | * | ||
| 792 | * Registers | ||
| 793 | * PADWR Port A Data Write Register | ||
| 794 | * PBDWR Port B Data Write Register | ||
| 795 | * PADRR Port A Data Read Register | ||
| 796 | * PBDRR Port B Data Read Register | ||
| 797 | * PADDR Port A Data Direction Register | ||
| 798 | * PBDDR Port B Data Direction Register | ||
| 799 | * PASSR Port A Sleep State Register | ||
| 800 | * PBSSR Port B Sleep State Register | ||
| 801 | * | ||
| 802 | */ | ||
| 803 | |||
| 804 | #define _PIO( x ) _SA1101( ( x ) + __GPIO_INTERFACE ) | ||
| 805 | |||
| 806 | #define _PADWR _PIO( 0x0000 ) | ||
| 807 | #define _PBDWR _PIO( 0x0400 ) | ||
| 808 | #define _PADRR _PIO( 0x0000 ) | ||
| 809 | #define _PBDRR _PIO( 0x0400 ) | ||
| 810 | #define _PADDR _PIO( 0x0800 ) | ||
| 811 | #define _PBDDR _PIO( 0x0c00 ) | ||
| 812 | #define _PASSR _PIO( 0x1000 ) | ||
| 813 | #define _PBSSR _PIO( 0x1400 ) | ||
| 814 | |||
| 815 | |||
| 816 | #if ( LANGUAGE == C ) | ||
| 817 | |||
| 818 | |||
| 819 | #define PADWR (*((volatile Word *) SA1101_p2v (_PADWR))) | ||
| 820 | #define PBDWR (*((volatile Word *) SA1101_p2v (_PBDWR))) | ||
| 821 | #define PADRR (*((volatile Word *) SA1101_p2v (_PADRR))) | ||
| 822 | #define PBDRR (*((volatile Word *) SA1101_p2v (_PBDRR))) | ||
| 823 | #define PADDR (*((volatile Word *) SA1101_p2v (_PADDR))) | ||
| 824 | #define PBDDR (*((volatile Word *) SA1101_p2v (_PBDDR))) | ||
| 825 | #define PASSR (*((volatile Word *) SA1101_p2v (_PASSR))) | ||
| 826 | #define PBSSR (*((volatile Word *) SA1101_p2v (_PBSSR))) | ||
| 827 | |||
| 828 | #endif | ||
| 829 | |||
| 830 | |||
| 831 | |||
| 832 | /* | ||
| 833 | * Keypad Interface | ||
| 834 | * | ||
| 835 | * Registers | ||
| 836 | * PXDWR | ||
| 837 | * PXDRR | ||
| 838 | * PYDWR | ||
| 839 | * PYDRR | ||
| 840 | * | ||
| 841 | */ | ||
| 842 | |||
| 843 | #define _KEYPAD( x ) _SA1101( ( x ) + __KEYPAD_INTERFACE ) | ||
| 844 | |||
| 845 | #define _PXDWR _KEYPAD( 0x0000 ) | ||
| 846 | #define _PXDRR _KEYPAD( 0x0000 ) | ||
| 847 | #define _PYDWR _KEYPAD( 0x0400 ) | ||
| 848 | #define _PYDRR _KEYPAD( 0x0400 ) | ||
| 849 | |||
| 850 | #if ( LANGUAGE == C ) | ||
| 851 | |||
| 852 | |||
| 853 | #define PXDWR (*((volatile Word *) SA1101_p2v (_PXDWR))) | ||
| 854 | #define PXDRR (*((volatile Word *) SA1101_p2v (_PXDRR))) | ||
| 855 | #define PYDWR (*((volatile Word *) SA1101_p2v (_PYDWR))) | ||
| 856 | #define PYDRR (*((volatile Word *) SA1101_p2v (_PYDRR))) | ||
| 857 | |||
| 858 | #endif | ||
| 859 | |||
| 860 | |||
| 861 | |||
| 862 | /* | ||
| 863 | * PCMCIA Interface | ||
| 864 | * | ||
| 865 | * Registers | ||
| 866 | * PCSR Status Register | ||
| 867 | * PCCR Control Register | ||
| 868 | * PCSSR Sleep State Register | ||
| 869 | * | ||
| 870 | */ | ||
| 871 | |||
| 872 | #define _CARD( x ) _SA1101( ( x ) + __PCMCIA_INTERFACE ) | ||
| 873 | |||
| 874 | #define _PCSR _CARD( 0x0000 ) | ||
| 875 | #define _PCCR _CARD( 0x0400 ) | ||
| 876 | #define _PCSSR _CARD( 0x0800 ) | ||
| 877 | |||
| 878 | #if ( LANGUAGE == C ) | ||
| 879 | #define PCSR (*((volatile Word *) SA1101_p2v (_PCSR))) | ||
| 880 | #define PCCR (*((volatile Word *) SA1101_p2v (_PCCR))) | ||
| 881 | #define PCSSR (*((volatile Word *) SA1101_p2v (_PCSSR))) | ||
| 882 | |||
| 883 | #define PCSR_S0_ready 0x0001 | ||
| 884 | #define PCSR_S1_ready 0x0002 | ||
| 885 | #define PCSR_S0_detected 0x0004 | ||
| 886 | #define PCSR_S1_detected 0x0008 | ||
| 887 | #define PCSR_S0_VS1 0x0010 | ||
| 888 | #define PCSR_S0_VS2 0x0020 | ||
| 889 | #define PCSR_S1_VS1 0x0040 | ||
| 890 | #define PCSR_S1_VS2 0x0080 | ||
| 891 | #define PCSR_S0_WP 0x0100 | ||
| 892 | #define PCSR_S1_WP 0x0200 | ||
| 893 | #define PCSR_S0_BVD1_nSTSCHG 0x0400 | ||
| 894 | #define PCSR_S0_BVD2_nSPKR 0x0800 | ||
| 895 | #define PCSR_S1_BVD1_nSTSCHG 0x1000 | ||
| 896 | #define PCSR_S1_BVD2_nSPKR 0x2000 | ||
| 897 | |||
| 898 | #define PCCR_S0_VPP0 0x0001 | ||
| 899 | #define PCCR_S0_VPP1 0x0002 | ||
| 900 | #define PCCR_S0_VCC0 0x0004 | ||
| 901 | #define PCCR_S0_VCC1 0x0008 | ||
| 902 | #define PCCR_S1_VPP0 0x0010 | ||
| 903 | #define PCCR_S1_VPP1 0x0020 | ||
| 904 | #define PCCR_S1_VCC0 0x0040 | ||
| 905 | #define PCCR_S1_VCC1 0x0080 | ||
| 906 | #define PCCR_S0_reset 0x0100 | ||
| 907 | #define PCCR_S1_reset 0x0200 | ||
| 908 | #define PCCR_S0_float 0x0400 | ||
| 909 | #define PCCR_S1_float 0x0800 | ||
| 910 | |||
| 911 | #define PCSSR_S0_VCC0 0x0001 | ||
| 912 | #define PCSSR_S0_VCC1 0x0002 | ||
| 913 | #define PCSSR_S0_VPP0 0x0004 | ||
| 914 | #define PCSSR_S0_VPP1 0x0008 | ||
| 915 | #define PCSSR_S0_control 0x0010 | ||
| 916 | #define PCSSR_S1_VCC0 0x0020 | ||
| 917 | #define PCSSR_S1_VCC1 0x0040 | ||
| 918 | #define PCSSR_S1_VPP0 0x0080 | ||
| 919 | #define PCSSR_S1_VPP1 0x0100 | ||
| 920 | #define PCSSR_S1_control 0x0200 | ||
| 921 | |||
| 922 | #endif | ||
| 923 | |||
| 924 | #undef C | ||
| 925 | #undef Assembly | ||
diff --git a/include/asm-arm/arch-sa1100/SA-1111.h b/include/asm-arm/arch-sa1100/SA-1111.h deleted file mode 100644 index c38f60915cb6..000000000000 --- a/include/asm-arm/arch-sa1100/SA-1111.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Moved to new location | ||
| 3 | */ | ||
| 4 | #warning using old SA-1111.h - update to <asm/hardware/sa1111.h> | ||
| 5 | #include <asm/hardware/sa1111.h> | ||
diff --git a/include/asm-arm/arch-sa1100/assabet.h b/include/asm-arm/arch-sa1100/assabet.h deleted file mode 100644 index d6a1bb5b4944..000000000000 --- a/include/asm-arm/arch-sa1100/assabet.h +++ /dev/null | |||
| @@ -1,105 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/assabet.h | ||
| 3 | * | ||
| 4 | * Created 2000/06/05 by Nicolas Pitre <nico@cam.org> | ||
| 5 | * | ||
| 6 | * This file contains the hardware specific definitions for Assabet | ||
| 7 | * Only include this file from SA1100-specific files. | ||
| 8 | * | ||
| 9 | * 2000/05/23 John Dorsey <john+@cs.cmu.edu> | ||
| 10 | * Definitions for Neponset added. | ||
| 11 | */ | ||
| 12 | #ifndef __ASM_ARCH_ASSABET_H | ||
| 13 | #define __ASM_ARCH_ASSABET_H | ||
| 14 | |||
| 15 | |||
| 16 | /* System Configuration Register flags */ | ||
| 17 | |||
| 18 | #define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */ | ||
| 19 | #define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */ | ||
| 20 | #define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */ | ||
| 21 | #define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */ | ||
| 22 | #define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */ | ||
| 23 | #define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */ | ||
| 24 | |||
| 25 | #define ASSABET_SCR_INIT -1 | ||
| 26 | |||
| 27 | extern unsigned long SCR_value; | ||
| 28 | |||
| 29 | #ifdef CONFIG_ASSABET_NEPONSET | ||
| 30 | #define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0) | ||
| 31 | #else | ||
| 32 | #define machine_has_neponset() (0) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | /* Board Control Register */ | ||
| 36 | |||
| 37 | #define ASSABET_BCR_BASE 0xf1000000 | ||
| 38 | #define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE)) | ||
| 39 | |||
| 40 | #define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */ | ||
| 41 | #define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */ | ||
| 42 | #define ASSABET_BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ | ||
| 43 | #define ASSABET_BCR_CODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */ | ||
| 44 | #define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */ | ||
| 45 | #define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */ | ||
| 46 | #define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */ | ||
| 47 | #define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */ | ||
| 48 | #define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */ | ||
| 49 | #define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */ | ||
| 50 | #define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */ | ||
| 51 | #define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */ | ||
| 52 | #define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */ | ||
| 53 | #define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */ | ||
| 54 | #define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */ | ||
| 55 | #define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */ | ||
| 56 | #define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */ | ||
| 57 | #define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */ | ||
| 58 | #define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */ | ||
| 59 | #define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */ | ||
| 60 | #define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */ | ||
| 61 | #define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */ | ||
| 62 | #define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */ | ||
| 63 | #define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */ | ||
| 64 | #define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */ | ||
| 65 | |||
| 66 | #ifdef CONFIG_SA1100_ASSABET | ||
| 67 | extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); | ||
| 68 | #else | ||
| 69 | #define ASSABET_BCR_frob(x,y) do { } while (0) | ||
| 70 | #endif | ||
| 71 | |||
| 72 | #define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x)) | ||
| 73 | #define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0) | ||
| 74 | |||
| 75 | #define ASSABET_BSR_BASE 0xf1000000 | ||
| 76 | #define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE)) | ||
| 77 | |||
| 78 | #define ASSABET_BSR_RS232_VALID (1 << 24) | ||
| 79 | #define ASSABET_BSR_COM_DCD (1 << 25) | ||
| 80 | #define ASSABET_BSR_COM_CTS (1 << 26) | ||
| 81 | #define ASSABET_BSR_COM_DSR (1 << 27) | ||
| 82 | #define ASSABET_BSR_RAD_CTS (1 << 28) | ||
| 83 | #define ASSABET_BSR_RAD_DSR (1 << 29) | ||
| 84 | #define ASSABET_BSR_RAD_DCD (1 << 30) | ||
| 85 | #define ASSABET_BSR_RAD_RI (1 << 31) | ||
| 86 | |||
| 87 | |||
| 88 | /* GPIOs for which the generic definition doesn't say much */ | ||
| 89 | #define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ | ||
| 90 | #define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ | ||
| 91 | #define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ | ||
| 92 | #define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */ | ||
| 93 | #define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */ | ||
| 94 | #define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */ | ||
| 95 | #define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ | ||
| 96 | #define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */ | ||
| 97 | #define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ | ||
| 98 | #define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ | ||
| 99 | |||
| 100 | #define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21 | ||
| 101 | #define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22 | ||
| 102 | #define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24 | ||
| 103 | #define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25 | ||
| 104 | |||
| 105 | #endif | ||
diff --git a/include/asm-arm/arch-sa1100/badge4.h b/include/asm-arm/arch-sa1100/badge4.h deleted file mode 100644 index d93a9a83b25d..000000000000 --- a/include/asm-arm/arch-sa1100/badge4.h +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/badge4.h | ||
| 3 | * | ||
| 4 | * Tim Connors <connors@hpl.hp.com> | ||
| 5 | * Christopher Hoover <ch@hpl.hp.com> | ||
| 6 | * | ||
| 7 | * Copyright (C) 2002 Hewlett-Packard Company | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 16 | #error "include <asm/arch/hardware.h> instead" | ||
| 17 | #endif | ||
| 18 | |||
| 19 | #define BADGE4_SA1111_BASE (0x48000000) | ||
| 20 | |||
| 21 | /* GPIOs on the BadgePAD 4 */ | ||
| 22 | #define BADGE4_GPIO_INT_1111 GPIO_GPIO0 /* SA-1111 IRQ */ | ||
| 23 | |||
| 24 | #define BADGE4_GPIO_INT_VID GPIO_GPIO1 /* Video expansion */ | ||
| 25 | #define BADGE4_GPIO_LGP2 GPIO_GPIO2 /* GPIO_LDD8 */ | ||
| 26 | #define BADGE4_GPIO_LGP3 GPIO_GPIO3 /* GPIO_LDD9 */ | ||
| 27 | #define BADGE4_GPIO_LGP4 GPIO_GPIO4 /* GPIO_LDD10 */ | ||
| 28 | #define BADGE4_GPIO_LGP5 GPIO_GPIO5 /* GPIO_LDD11 */ | ||
| 29 | #define BADGE4_GPIO_LGP6 GPIO_GPIO6 /* GPIO_LDD12 */ | ||
| 30 | #define BADGE4_GPIO_LGP7 GPIO_GPIO7 /* GPIO_LDD13 */ | ||
| 31 | #define BADGE4_GPIO_LGP8 GPIO_GPIO8 /* GPIO_LDD14 */ | ||
| 32 | #define BADGE4_GPIO_LGP9 GPIO_GPIO9 /* GPIO_LDD15 */ | ||
| 33 | #define BADGE4_GPIO_GPA_VID GPIO_GPIO10 /* Video expansion */ | ||
| 34 | #define BADGE4_GPIO_GPB_VID GPIO_GPIO11 /* Video expansion */ | ||
| 35 | #define BADGE4_GPIO_GPC_VID GPIO_GPIO12 /* Video expansion */ | ||
| 36 | |||
| 37 | #define BADGE4_GPIO_UART_HS1 GPIO_GPIO13 | ||
| 38 | #define BADGE4_GPIO_UART_HS2 GPIO_GPIO14 | ||
| 39 | |||
| 40 | #define BADGE4_GPIO_MUXSEL0 GPIO_GPIO15 | ||
| 41 | #define BADGE4_GPIO_TESTPT_J7 GPIO_GPIO16 | ||
| 42 | |||
| 43 | #define BADGE4_GPIO_SDSDA GPIO_GPIO17 /* SDRAM SPD Data */ | ||
| 44 | #define BADGE4_GPIO_SDSCL GPIO_GPIO18 /* SDRAM SPD Clock */ | ||
| 45 | #define BADGE4_GPIO_SDTYP0 GPIO_GPIO19 /* SDRAM Type Control */ | ||
| 46 | #define BADGE4_GPIO_SDTYP1 GPIO_GPIO20 /* SDRAM Type Control */ | ||
| 47 | |||
| 48 | #define BADGE4_GPIO_BGNT_1111 GPIO_GPIO21 /* GPIO_MBGNT */ | ||
| 49 | #define BADGE4_GPIO_BREQ_1111 GPIO_GPIO22 /* GPIO_TREQA */ | ||
| 50 | |||
| 51 | #define BADGE4_GPIO_TESTPT_J6 GPIO_GPIO23 | ||
| 52 | |||
| 53 | #define BADGE4_GPIO_PCMEN5V GPIO_GPIO24 /* 5V power */ | ||
| 54 | |||
| 55 | #define BADGE4_GPIO_SA1111_NRST GPIO_GPIO25 /* SA-1111 nRESET */ | ||
| 56 | |||
| 57 | #define BADGE4_GPIO_TESTPT_J5 GPIO_GPIO26 | ||
| 58 | |||
| 59 | #define BADGE4_GPIO_CLK_1111 GPIO_GPIO27 /* GPIO_32_768kHz */ | ||
| 60 | |||
| 61 | /* Interrupts on the BadgePAD 4 */ | ||
| 62 | #define BADGE4_IRQ_GPIO_SA1111 IRQ_GPIO0 /* SA-1111 interrupt */ | ||
| 63 | |||
| 64 | |||
| 65 | /* PCM5ENV Usage tracking */ | ||
| 66 | |||
| 67 | #define BADGE4_5V_PCMCIA_SOCK0 (1<<0) | ||
| 68 | #define BADGE4_5V_PCMCIA_SOCK1 (1<<1) | ||
| 69 | #define BADGE4_5V_PCMCIA_SOCK(n) (1<<(n)) | ||
| 70 | #define BADGE4_5V_USB (1<<2) | ||
| 71 | #define BADGE4_5V_INITIALLY (1<<3) | ||
| 72 | |||
| 73 | #ifndef __ASSEMBLY__ | ||
| 74 | extern void badge4_set_5V(unsigned subsystem, int on); | ||
| 75 | #endif | ||
diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h deleted file mode 100644 index f1f0e3387d9c..000000000000 --- a/include/asm-arm/arch-sa1100/bitfield.h +++ /dev/null | |||
| @@ -1,113 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * FILE bitfield.h | ||
| 3 | * | ||
| 4 | * Version 1.1 | ||
| 5 | * Author Copyright (c) Marc A. Viredaz, 1998 | ||
| 6 | * DEC Western Research Laboratory, Palo Alto, CA | ||
| 7 | * Date April 1998 (April 1997) | ||
| 8 | * System Advanced RISC Machine (ARM) | ||
| 9 | * Language C or ARM Assembly | ||
| 10 | * Purpose Definition of macros to operate on bit fields. | ||
| 11 | */ | ||
| 12 | |||
| 13 | |||
| 14 | |||
| 15 | #ifndef __BITFIELD_H | ||
| 16 | #define __BITFIELD_H | ||
| 17 | |||
| 18 | #ifndef __ASSEMBLY__ | ||
| 19 | #define UData(Data) ((unsigned long) (Data)) | ||
| 20 | #else | ||
| 21 | #define UData(Data) (Data) | ||
| 22 | #endif | ||
| 23 | |||
| 24 | |||
| 25 | /* | ||
| 26 | * MACRO: Fld | ||
| 27 | * | ||
| 28 | * Purpose | ||
| 29 | * The macro "Fld" encodes a bit field, given its size and its shift value | ||
| 30 | * with respect to bit 0. | ||
| 31 | * | ||
| 32 | * Note | ||
| 33 | * A more intuitive way to encode bit fields would have been to use their | ||
| 34 | * mask. However, extracting size and shift value information from a bit | ||
| 35 | * field's mask is cumbersome and might break the assembler (255-character | ||
| 36 | * line-size limit). | ||
| 37 | * | ||
| 38 | * Input | ||
| 39 | * Size Size of the bit field, in number of bits. | ||
| 40 | * Shft Shift value of the bit field with respect to bit 0. | ||
| 41 | * | ||
| 42 | * Output | ||
| 43 | * Fld Encoded bit field. | ||
| 44 | */ | ||
| 45 | |||
| 46 | #define Fld(Size, Shft) (((Size) << 16) + (Shft)) | ||
| 47 | |||
| 48 | |||
| 49 | /* | ||
| 50 | * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit | ||
| 51 | * | ||
| 52 | * Purpose | ||
| 53 | * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return | ||
| 54 | * the size, shift value, mask, aligned mask, and first bit of a | ||
| 55 | * bit field. | ||
| 56 | * | ||
| 57 | * Input | ||
| 58 | * Field Encoded bit field (using the macro "Fld"). | ||
| 59 | * | ||
| 60 | * Output | ||
| 61 | * FSize Size of the bit field, in number of bits. | ||
| 62 | * FShft Shift value of the bit field with respect to bit 0. | ||
| 63 | * FMsk Mask for the bit field. | ||
| 64 | * FAlnMsk Mask for the bit field, aligned on bit 0. | ||
| 65 | * F1stBit First bit of the bit field. | ||
| 66 | */ | ||
| 67 | |||
| 68 | #define FSize(Field) ((Field) >> 16) | ||
| 69 | #define FShft(Field) ((Field) & 0x0000FFFF) | ||
| 70 | #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) | ||
| 71 | #define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) | ||
| 72 | #define F1stBit(Field) (UData (1) << FShft (Field)) | ||
| 73 | |||
| 74 | |||
| 75 | /* | ||
| 76 | * MACRO: FInsrt | ||
| 77 | * | ||
| 78 | * Purpose | ||
| 79 | * The macro "FInsrt" inserts a value into a bit field by shifting the | ||
| 80 | * former appropriately. | ||
| 81 | * | ||
| 82 | * Input | ||
| 83 | * Value Bit-field value. | ||
| 84 | * Field Encoded bit field (using the macro "Fld"). | ||
| 85 | * | ||
| 86 | * Output | ||
| 87 | * FInsrt Bit-field value positioned appropriately. | ||
| 88 | */ | ||
| 89 | |||
| 90 | #define FInsrt(Value, Field) \ | ||
| 91 | (UData (Value) << FShft (Field)) | ||
| 92 | |||
| 93 | |||
| 94 | /* | ||
| 95 | * MACRO: FExtr | ||
| 96 | * | ||
| 97 | * Purpose | ||
| 98 | * The macro "FExtr" extracts the value of a bit field by masking and | ||
| 99 | * shifting it appropriately. | ||
| 100 | * | ||
| 101 | * Input | ||
| 102 | * Data Data containing the bit-field to be extracted. | ||
| 103 | * Field Encoded bit field (using the macro "Fld"). | ||
| 104 | * | ||
| 105 | * Output | ||
| 106 | * FExtr Bit-field value. | ||
| 107 | */ | ||
| 108 | |||
| 109 | #define FExtr(Data, Field) \ | ||
| 110 | ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) | ||
| 111 | |||
| 112 | |||
| 113 | #endif /* __BITFIELD_H */ | ||
diff --git a/include/asm-arm/arch-sa1100/cerf.h b/include/asm-arm/arch-sa1100/cerf.h deleted file mode 100644 index 9a19c3d07c1e..000000000000 --- a/include/asm-arm/arch-sa1100/cerf.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-sa1100/cerf.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * Apr-2003 : Removed some old PDA crud [FB] | ||
| 9 | */ | ||
| 10 | #ifndef _INCLUDE_CERF_H_ | ||
| 11 | #define _INCLUDE_CERF_H_ | ||
| 12 | |||
| 13 | |||
| 14 | #define CERF_ETH_IO 0xf0000000 | ||
| 15 | #define CERF_ETH_IRQ IRQ_GPIO26 | ||
| 16 | |||
| 17 | #define CERF_GPIO_CF_BVD2 GPIO_GPIO (19) | ||
| 18 | #define CERF_GPIO_CF_BVD1 GPIO_GPIO (20) | ||
| 19 | #define CERF_GPIO_CF_RESET GPIO_GPIO (21) | ||
| 20 | #define CERF_GPIO_CF_IRQ GPIO_GPIO (22) | ||
| 21 | #define CERF_GPIO_CF_CD GPIO_GPIO (23) | ||
| 22 | |||
| 23 | #define CERF_IRQ_GPIO_CF_BVD2 IRQ_GPIO19 | ||
| 24 | #define CERF_IRQ_GPIO_CF_BVD1 IRQ_GPIO20 | ||
| 25 | #define CERF_IRQ_GPIO_CF_IRQ IRQ_GPIO22 | ||
| 26 | #define CERF_IRQ_GPIO_CF_CD IRQ_GPIO23 | ||
| 27 | |||
| 28 | #endif // _INCLUDE_CERF_H_ | ||
diff --git a/include/asm-arm/arch-sa1100/collie.h b/include/asm-arm/arch-sa1100/collie.h deleted file mode 100644 index 762eba535813..000000000000 --- a/include/asm-arm/arch-sa1100/collie.h +++ /dev/null | |||
| @@ -1,88 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/collie.h | ||
| 3 | * | ||
| 4 | * This file contains the hardware specific definitions for Assabet | ||
| 5 | * Only include this file from SA1100-specific files. | ||
| 6 | * | ||
| 7 | * ChangeLog: | ||
| 8 | * 04-06-2001 Lineo Japan, Inc. | ||
| 9 | * 04-16-2001 SHARP Corporation | ||
| 10 | * 07-07-2002 Chris Larson <clarson@digi.com> | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #ifndef __ASM_ARCH_COLLIE_H | ||
| 14 | #define __ASM_ARCH_COLLIE_H | ||
| 15 | |||
| 16 | |||
| 17 | #define COLLIE_SCP_CHARGE_ON SCOOP_GPCR_PA11 | ||
| 18 | #define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 | ||
| 19 | #define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 | ||
| 20 | #define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 | ||
| 21 | #define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 | ||
| 22 | #define COLLIE_SCP_5VON SCOOP_GPCR_PA16 | ||
| 23 | #define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 | ||
| 24 | #define COLLIE_SCP_VPEN SCOOP_GPCR_PA18 | ||
| 25 | #define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 | ||
| 26 | |||
| 27 | #define COLLIE_SCOOP_IO_DIR ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ | ||
| 28 | COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \ | ||
| 29 | COLLIE_SCP_LB_VOL_CHG ) | ||
| 30 | #define COLLIE_SCOOP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \ | ||
| 31 | COLLIE_SCP_CHARGE_ON ) | ||
| 32 | |||
| 33 | /* GPIOs for which the generic definition doesn't say much */ | ||
| 34 | |||
| 35 | #define COLLIE_GPIO_ON_KEY GPIO_GPIO (0) | ||
| 36 | #define COLLIE_GPIO_AC_IN GPIO_GPIO (1) | ||
| 37 | #define COLLIE_GPIO_SDIO_INT GPIO_GPIO (11) | ||
| 38 | #define COLLIE_GPIO_CF_IRQ GPIO_GPIO (14) | ||
| 39 | #define COLLIE_GPIO_nREMOCON_INT GPIO_GPIO (15) | ||
| 40 | #define COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO (16) | ||
| 41 | #define COLLIE_GPIO_nMIC_ON GPIO_GPIO (17) | ||
| 42 | #define COLLIE_GPIO_nREMOCON_ON GPIO_GPIO (18) | ||
| 43 | #define COLLIE_GPIO_CO GPIO_GPIO (20) | ||
| 44 | #define COLLIE_GPIO_MCP_CLK GPIO_GPIO (21) | ||
| 45 | #define COLLIE_GPIO_CF_CD GPIO_GPIO (22) | ||
| 46 | #define COLLIE_GPIO_UCB1x00_IRQ GPIO_GPIO (23) | ||
| 47 | #define COLLIE_GPIO_WAKEUP GPIO_GPIO (24) | ||
| 48 | #define COLLIE_GPIO_GA_INT GPIO_GPIO (25) | ||
| 49 | #define COLLIE_GPIO_MAIN_BAT_LOW GPIO_GPIO (26) | ||
| 50 | |||
| 51 | /* Interrupts */ | ||
| 52 | |||
| 53 | #define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0 | ||
| 54 | #define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1 | ||
| 55 | #define COLLIE_IRQ_GPIO_SDIO_IRQ IRQ_GPIO11 | ||
| 56 | #define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14 | ||
| 57 | #define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15 | ||
| 58 | #define COLLIE_IRQ_GPIO_CO IRQ_GPIO20 | ||
| 59 | #define COLLIE_IRQ_GPIO_CF_CD IRQ_GPIO22 | ||
| 60 | #define COLLIE_IRQ_GPIO_UCB1x00_IRQ IRQ_GPIO23 | ||
| 61 | #define COLLIE_IRQ_GPIO_WAKEUP IRQ_GPIO24 | ||
| 62 | #define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25 | ||
| 63 | #define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26 | ||
| 64 | |||
| 65 | #define COLLIE_LCM_IRQ_GPIO_RTS IRQ_LOCOMO_GPIO0 | ||
| 66 | #define COLLIE_LCM_IRQ_GPIO_CTS IRQ_LOCOMO_GPIO1 | ||
| 67 | #define COLLIE_LCM_IRQ_GPIO_DSR IRQ_LOCOMO_GPIO2 | ||
| 68 | #define COLLIE_LCM_IRQ_GPIO_DTR IRQ_LOCOMO_GPIO3 | ||
| 69 | #define COLLIE_LCM_IRQ_GPIO_nSD_DETECT IRQ_LOCOMO_GPIO13 | ||
| 70 | #define COLLIE_LCM_IRQ_GPIO_nSD_WP IRQ_LOCOMO_GPIO14 | ||
| 71 | |||
| 72 | /* GPIO's on the TC35143AF (Toshiba Analog Frontend) */ | ||
| 73 | #define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 /* GPIO0=Version */ | ||
| 74 | #define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1 /* GPIO1=TBL_CHK */ | ||
| 75 | #define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2 /* GPIO2=VPNE_ON */ | ||
| 76 | #define COLLIE_TC35143_GPIO_IR_ON UCB_IO_3 /* GPIO3=IR_ON */ | ||
| 77 | #define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4 /* GPIO4=AMP_ON */ | ||
| 78 | #define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5 /* GPIO5=Version */ | ||
| 79 | #define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5 /* GPIO5=fs 8k LPF */ | ||
| 80 | #define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6 /* GPIO6=BUZZER BIAS */ | ||
| 81 | #define COLLIE_TC35143_GPIO_MBAT_ON UCB_IO_7 /* GPIO7=MBAT_ON */ | ||
| 82 | #define COLLIE_TC35143_GPIO_BBAT_ON UCB_IO_8 /* GPIO8=BBAT_ON */ | ||
| 83 | #define COLLIE_TC35143_GPIO_TMP_ON UCB_IO_9 /* GPIO9=TMP_ON */ | ||
| 84 | #define COLLIE_TC35143_GPIO_IN ( UCB_IO_0 | UCB_IO_2 | UCB_IO_5 ) | ||
| 85 | #define COLLIE_TC35143_GPIO_OUT ( UCB_IO_1 | UCB_IO_3 | UCB_IO_4 | UCB_IO_6 | \ | ||
| 86 | UCB_IO_7 | UCB_IO_8 | UCB_IO_9 ) | ||
| 87 | |||
| 88 | #endif | ||
diff --git a/include/asm-arm/arch-sa1100/debug-macro.S b/include/asm-arm/arch-sa1100/debug-macro.S deleted file mode 100644 index 1b7753654bd4..000000000000 --- a/include/asm-arm/arch-sa1100/debug-macro.S +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-sa1100/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #include <asm/arch/hardware.h> | ||
| 14 | |||
| 15 | .macro addruart,rx | ||
| 16 | mrc p15, 0, \rx, c1, c0 | ||
| 17 | tst \rx, #1 @ MMU enabled? | ||
| 18 | moveq \rx, #0x80000000 @ physical base address | ||
| 19 | movne \rx, #0xf8000000 @ virtual address | ||
| 20 | |||
| 21 | @ We probe for the active serial port here, coherently with | ||
| 22 | @ the comment in include/asm-arm/arch-sa1100/uncompress.h. | ||
| 23 | @ We assume r1 can be clobbered. | ||
| 24 | |||
| 25 | @ see if Ser3 is active | ||
| 26 | add \rx, \rx, #0x00050000 | ||
| 27 | ldr r1, [\rx, #UTCR3] | ||
| 28 | tst r1, #UTCR3_TXE | ||
| 29 | |||
| 30 | @ if Ser3 is inactive, then try Ser1 | ||
| 31 | addeq \rx, \rx, #(0x00010000 - 0x00050000) | ||
| 32 | ldreq r1, [\rx, #UTCR3] | ||
| 33 | tsteq r1, #UTCR3_TXE | ||
| 34 | |||
| 35 | @ if Ser1 is inactive, then try Ser2 | ||
| 36 | addeq \rx, \rx, #(0x00030000 - 0x00010000) | ||
| 37 | ldreq r1, [\rx, #UTCR3] | ||
| 38 | tsteq r1, #UTCR3_TXE | ||
| 39 | |||
| 40 | @ if all ports are inactive, then there is nothing we can do | ||
| 41 | moveq pc, lr | ||
| 42 | .endm | ||
| 43 | |||
| 44 | .macro senduart,rd,rx | ||
| 45 | str \rd, [\rx, #UTDR] | ||
| 46 | .endm | ||
| 47 | |||
| 48 | .macro waituart,rd,rx | ||
| 49 | 1001: ldr \rd, [\rx, #UTSR1] | ||
| 50 | tst \rd, #UTSR1_TNF | ||
| 51 | beq 1001b | ||
| 52 | .endm | ||
| 53 | |||
| 54 | .macro busyuart,rd,rx | ||
| 55 | 1001: ldr \rd, [\rx, #UTSR1] | ||
| 56 | tst \rd, #UTSR1_TBY | ||
| 57 | bne 1001b | ||
| 58 | .endm | ||
diff --git a/include/asm-arm/arch-sa1100/dma.h b/include/asm-arm/arch-sa1100/dma.h deleted file mode 100644 index 6b7917a2e77a..000000000000 --- a/include/asm-arm/arch-sa1100/dma.h +++ /dev/null | |||
| @@ -1,117 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/dma.h | ||
| 3 | * | ||
| 4 | * Generic SA1100 DMA support | ||
| 5 | * | ||
| 6 | * Copyright (C) 2000 Nicolas Pitre | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ASM_ARCH_DMA_H | ||
| 11 | #define __ASM_ARCH_DMA_H | ||
| 12 | |||
| 13 | #include "hardware.h" | ||
| 14 | |||
| 15 | |||
| 16 | /* | ||
| 17 | * The SA1100 has six internal DMA channels. | ||
| 18 | */ | ||
| 19 | #define SA1100_DMA_CHANNELS 6 | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Maximum physical DMA buffer size | ||
| 23 | */ | ||
| 24 | #define MAX_DMA_SIZE 0x1fff | ||
| 25 | #define CUT_DMA_SIZE 0x1000 | ||
| 26 | |||
| 27 | /* | ||
| 28 | * All possible SA1100 devices a DMA channel can be attached to. | ||
| 29 | */ | ||
| 30 | typedef enum { | ||
| 31 | DMA_Ser0UDCWr = DDAR_Ser0UDCWr, /* Ser. port 0 UDC Write */ | ||
| 32 | DMA_Ser0UDCRd = DDAR_Ser0UDCRd, /* Ser. port 0 UDC Read */ | ||
| 33 | DMA_Ser1UARTWr = DDAR_Ser1UARTWr, /* Ser. port 1 UART Write */ | ||
| 34 | DMA_Ser1UARTRd = DDAR_Ser1UARTRd, /* Ser. port 1 UART Read */ | ||
| 35 | DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr, /* Ser. port 1 SDLC Write */ | ||
| 36 | DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd, /* Ser. port 1 SDLC Read */ | ||
| 37 | DMA_Ser2UARTWr = DDAR_Ser2UARTWr, /* Ser. port 2 UART Write */ | ||
| 38 | DMA_Ser2UARTRd = DDAR_Ser2UARTRd, /* Ser. port 2 UART Read */ | ||
| 39 | DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr, /* Ser. port 2 HSSP Write */ | ||
| 40 | DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd, /* Ser. port 2 HSSP Read */ | ||
| 41 | DMA_Ser3UARTWr = DDAR_Ser3UARTWr, /* Ser. port 3 UART Write */ | ||
| 42 | DMA_Ser3UARTRd = DDAR_Ser3UARTRd, /* Ser. port 3 UART Read */ | ||
| 43 | DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr, /* Ser. port 4 MCP 0 Write (audio) */ | ||
| 44 | DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd, /* Ser. port 4 MCP 0 Read (audio) */ | ||
| 45 | DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr, /* Ser. port 4 MCP 1 Write */ | ||
| 46 | DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd, /* Ser. port 4 MCP 1 Read */ | ||
| 47 | DMA_Ser4SSPWr = DDAR_Ser4SSPWr, /* Ser. port 4 SSP Write (16 bits) */ | ||
| 48 | DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ | ||
| 49 | } dma_device_t; | ||
| 50 | |||
| 51 | typedef struct { | ||
| 52 | volatile u_long DDAR; | ||
| 53 | volatile u_long SetDCSR; | ||
| 54 | volatile u_long ClrDCSR; | ||
| 55 | volatile u_long RdDCSR; | ||
| 56 | volatile dma_addr_t DBSA; | ||
| 57 | volatile u_long DBTA; | ||
| 58 | volatile dma_addr_t DBSB; | ||
| 59 | volatile u_long DBTB; | ||
| 60 | } dma_regs_t; | ||
| 61 | |||
| 62 | typedef void (*dma_callback_t)(void *data); | ||
| 63 | |||
| 64 | /* | ||
| 65 | * DMA function prototypes | ||
| 66 | */ | ||
| 67 | |||
| 68 | extern int sa1100_request_dma( dma_device_t device, const char *device_id, | ||
| 69 | dma_callback_t callback, void *data, | ||
| 70 | dma_regs_t **regs ); | ||
| 71 | extern void sa1100_free_dma( dma_regs_t *regs ); | ||
| 72 | extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size ); | ||
| 73 | extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs); | ||
| 74 | extern void sa1100_reset_dma(dma_regs_t *regs); | ||
| 75 | |||
| 76 | /** | ||
| 77 | * sa1100_stop_dma - stop DMA in progress | ||
| 78 | * @regs: identifier for the channel to use | ||
| 79 | * | ||
| 80 | * This stops DMA without clearing buffer pointers. Unlike | ||
| 81 | * sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma() | ||
| 82 | * or sa1100_get_dma_pos(). | ||
| 83 | * | ||
| 84 | * The @regs identifier is provided by a successful call to | ||
| 85 | * sa1100_request_dma(). | ||
| 86 | **/ | ||
| 87 | |||
| 88 | #define sa1100_stop_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN) | ||
| 89 | |||
| 90 | /** | ||
| 91 | * sa1100_resume_dma - resume DMA on a stopped channel | ||
| 92 | * @regs: identifier for the channel to use | ||
| 93 | * | ||
| 94 | * This resumes DMA on a channel previously stopped with | ||
| 95 | * sa1100_stop_dma(). | ||
| 96 | * | ||
| 97 | * The @regs identifier is provided by a successful call to | ||
| 98 | * sa1100_request_dma(). | ||
| 99 | **/ | ||
| 100 | |||
| 101 | #define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN) | ||
| 102 | |||
| 103 | /** | ||
| 104 | * sa1100_clear_dma - clear DMA pointers | ||
| 105 | * @regs: identifier for the channel to use | ||
| 106 | * | ||
| 107 | * This clear any DMA state so the DMA engine is ready to restart | ||
| 108 | * with new buffers through sa1100_start_dma(). Any buffers in flight | ||
| 109 | * are discarded. | ||
| 110 | * | ||
| 111 | * The @regs identifier is provided by a successful call to | ||
| 112 | * sa1100_request_dma(). | ||
| 113 | **/ | ||
| 114 | |||
| 115 | #define sa1100_clear_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB) | ||
| 116 | |||
| 117 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-sa1100/entry-macro.S b/include/asm-arm/arch-sa1100/entry-macro.S deleted file mode 100644 index 127db4aaf4f2..000000000000 --- a/include/asm-arm/arch-sa1100/entry-macro.S +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-sa1100/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for SA1100-based platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | .macro disable_fiq | ||
| 12 | .endm | ||
| 13 | |||
| 14 | .macro get_irqnr_preamble, base, tmp | ||
| 15 | mov \base, #0xfa000000 @ ICIP = 0xfa050000 | ||
| 16 | add \base, \base, #0x00050000 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 23 | ldr \irqstat, [\base] @ get irqs | ||
| 24 | ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 | ||
| 25 | ands \irqstat, \irqstat, \irqnr | ||
| 26 | mov \irqnr, #0 | ||
| 27 | beq 1001f | ||
| 28 | tst \irqstat, #0xff | ||
| 29 | moveq \irqstat, \irqstat, lsr #8 | ||
| 30 | addeq \irqnr, \irqnr, #8 | ||
| 31 | tsteq \irqstat, #0xff | ||
| 32 | moveq \irqstat, \irqstat, lsr #8 | ||
| 33 | addeq \irqnr, \irqnr, #8 | ||
| 34 | tsteq \irqstat, #0xff | ||
| 35 | moveq \irqstat, \irqstat, lsr #8 | ||
| 36 | addeq \irqnr, \irqnr, #8 | ||
| 37 | tst \irqstat, #0x0f | ||
| 38 | moveq \irqstat, \irqstat, lsr #4 | ||
| 39 | addeq \irqnr, \irqnr, #4 | ||
| 40 | tst \irqstat, #0x03 | ||
| 41 | moveq \irqstat, \irqstat, lsr #2 | ||
| 42 | addeq \irqnr, \irqnr, #2 | ||
| 43 | tst \irqstat, #0x01 | ||
| 44 | addeqs \irqnr, \irqnr, #1 | ||
| 45 | 1001: | ||
| 46 | .endm | ||
| 47 | |||
diff --git a/include/asm-arm/arch-sa1100/gpio.h b/include/asm-arm/arch-sa1100/gpio.h deleted file mode 100644 index e66ecf74e807..000000000000 --- a/include/asm-arm/arch-sa1100/gpio.h +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/gpio.h | ||
| 3 | * | ||
| 4 | * SA1100 GPIO wrappers for arch-neutral GPIO calls | ||
| 5 | * | ||
| 6 | * Written by Philipp Zabel <philipp.zabel@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | * | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef __ASM_ARCH_SA1100_GPIO_H | ||
| 25 | #define __ASM_ARCH_SA1100_GPIO_H | ||
| 26 | |||
| 27 | #include <asm/arch/hardware.h> | ||
| 28 | #include <asm/irq.h> | ||
| 29 | #include <asm-generic/gpio.h> | ||
| 30 | |||
| 31 | static inline int gpio_get_value(unsigned gpio) | ||
| 32 | { | ||
| 33 | if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) | ||
| 34 | return GPLR & GPIO_GPIO(gpio); | ||
| 35 | else | ||
| 36 | return __gpio_get_value(gpio); | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 40 | { | ||
| 41 | if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) | ||
| 42 | if (value) | ||
| 43 | GPSR = GPIO_GPIO(gpio); | ||
| 44 | else | ||
| 45 | GPCR = GPIO_GPIO(gpio); | ||
| 46 | else | ||
| 47 | __gpio_set_value(gpio, value); | ||
| 48 | } | ||
| 49 | |||
| 50 | #define gpio_cansleep __gpio_cansleep | ||
| 51 | |||
| 52 | static inline unsigned gpio_to_irq(unsigned gpio) | ||
| 53 | { | ||
| 54 | if (gpio < 11) | ||
| 55 | return IRQ_GPIO0 + gpio; | ||
| 56 | else | ||
| 57 | return IRQ_GPIO11 - 11 + gpio; | ||
| 58 | } | ||
| 59 | |||
| 60 | static inline unsigned irq_to_gpio(unsigned irq) | ||
| 61 | { | ||
| 62 | if (irq < IRQ_GPIO11_27) | ||
| 63 | return irq - IRQ_GPIO0; | ||
| 64 | else | ||
| 65 | return irq - IRQ_GPIO11 + 11; | ||
| 66 | } | ||
| 67 | |||
| 68 | #endif | ||
diff --git a/include/asm-arm/arch-sa1100/h3600.h b/include/asm-arm/arch-sa1100/h3600.h deleted file mode 100644 index 3ca0ecf095e6..000000000000 --- a/include/asm-arm/arch-sa1100/h3600.h +++ /dev/null | |||
| @@ -1,169 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Definitions for H3600 Handheld Computer | ||
| 4 | * | ||
| 5 | * Copyright 2000 Compaq Computer Corporation. | ||
| 6 | * | ||
| 7 | * Use consistent with the GNU GPL is permitted, | ||
| 8 | * provided that this copyright notice is | ||
| 9 | * preserved in its entirety in all copies and derived works. | ||
| 10 | * | ||
| 11 | * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, | ||
| 12 | * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS | ||
| 13 | * FITNESS FOR ANY PARTICULAR PURPOSE. | ||
| 14 | * | ||
| 15 | * Author: Jamey Hicks. | ||
| 16 | * | ||
| 17 | * History: | ||
| 18 | * | ||
| 19 | * 2001-10-?? Andrew Christian Added support for iPAQ H3800 | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _INCLUDE_H3600_H_ | ||
| 24 | #define _INCLUDE_H3600_H_ | ||
| 25 | |||
| 26 | typedef int __bitwise pm_request_t; | ||
| 27 | |||
| 28 | #define PM_SUSPEND ((__force pm_request_t) 1) /* enter D1-D3 */ | ||
| 29 | #define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */ | ||
| 30 | |||
| 31 | /* generalized support for H3xxx series Compaq Pocket PC's */ | ||
| 32 | #define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) | ||
| 33 | |||
| 34 | /* Physical memory regions corresponding to chip selects */ | ||
| 35 | #define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) | ||
| 36 | #define H3600_BANK_2_PHYS SA1100_CS2_PHYS | ||
| 37 | #define H3600_BANK_4_PHYS SA1100_CS4_PHYS | ||
| 38 | |||
| 39 | /* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */ | ||
| 40 | #define H3600_EGPIO_VIRT 0xf0000000 | ||
| 41 | #define H3600_BANK_2_VIRT 0xf1000000 | ||
| 42 | #define H3600_BANK_4_VIRT 0xf3800000 | ||
| 43 | |||
| 44 | /* | ||
| 45 | Machine-independent GPIO definitions | ||
| 46 | --- these are common across all current iPAQ platforms | ||
| 47 | */ | ||
| 48 | |||
| 49 | #define GPIO_H3600_NPOWER_BUTTON GPIO_GPIO (0) /* Also known as the "off button" */ | ||
| 50 | |||
| 51 | #define GPIO_H3600_PCMCIA_CD1 GPIO_GPIO (10) | ||
| 52 | #define GPIO_H3600_PCMCIA_IRQ1 GPIO_GPIO (11) | ||
| 53 | |||
| 54 | /* UDA1341 L3 Interface */ | ||
| 55 | #define GPIO_H3600_L3_DATA GPIO_GPIO (14) | ||
| 56 | #define GPIO_H3600_L3_MODE GPIO_GPIO (15) | ||
| 57 | #define GPIO_H3600_L3_CLOCK GPIO_GPIO (16) | ||
| 58 | |||
| 59 | #define GPIO_H3600_PCMCIA_CD0 GPIO_GPIO (17) | ||
| 60 | #define GPIO_H3600_SYS_CLK GPIO_GPIO (19) | ||
| 61 | #define GPIO_H3600_PCMCIA_IRQ0 GPIO_GPIO (21) | ||
| 62 | |||
| 63 | #define GPIO_H3600_COM_DCD GPIO_GPIO (23) | ||
| 64 | #define GPIO_H3600_OPT_IRQ GPIO_GPIO (24) | ||
| 65 | #define GPIO_H3600_COM_CTS GPIO_GPIO (25) | ||
| 66 | #define GPIO_H3600_COM_RTS GPIO_GPIO (26) | ||
| 67 | |||
| 68 | #define IRQ_GPIO_H3600_NPOWER_BUTTON IRQ_GPIO0 | ||
| 69 | #define IRQ_GPIO_H3600_PCMCIA_CD1 IRQ_GPIO10 | ||
| 70 | #define IRQ_GPIO_H3600_PCMCIA_IRQ1 IRQ_GPIO11 | ||
| 71 | #define IRQ_GPIO_H3600_PCMCIA_CD0 IRQ_GPIO17 | ||
| 72 | #define IRQ_GPIO_H3600_PCMCIA_IRQ0 IRQ_GPIO21 | ||
| 73 | #define IRQ_GPIO_H3600_COM_DCD IRQ_GPIO23 | ||
| 74 | #define IRQ_GPIO_H3600_OPT_IRQ IRQ_GPIO24 | ||
| 75 | #define IRQ_GPIO_H3600_COM_CTS IRQ_GPIO25 | ||
| 76 | |||
| 77 | |||
| 78 | #ifndef __ASSEMBLY__ | ||
| 79 | |||
| 80 | enum ipaq_egpio_type { | ||
| 81 | IPAQ_EGPIO_LCD_POWER, /* Power to the LCD panel */ | ||
| 82 | IPAQ_EGPIO_CODEC_NRESET, /* Clear to reset the audio codec (remember to return high) */ | ||
| 83 | IPAQ_EGPIO_AUDIO_ON, /* Audio power */ | ||
| 84 | IPAQ_EGPIO_QMUTE, /* Audio muting */ | ||
| 85 | IPAQ_EGPIO_OPT_NVRAM_ON, /* Non-volatile RAM on extension sleeves (SPI interface) */ | ||
| 86 | IPAQ_EGPIO_OPT_ON, /* Power to extension sleeves */ | ||
| 87 | IPAQ_EGPIO_CARD_RESET, /* Reset PCMCIA cards on extension sleeve (???) */ | ||
| 88 | IPAQ_EGPIO_OPT_RESET, /* Reset option pack (???) */ | ||
| 89 | IPAQ_EGPIO_IR_ON, /* IR sensor/emitter power */ | ||
| 90 | IPAQ_EGPIO_IR_FSEL, /* IR speed selection 1->fast, 0->slow */ | ||
| 91 | IPAQ_EGPIO_RS232_ON, /* Maxim RS232 chip power */ | ||
| 92 | IPAQ_EGPIO_VPP_ON, /* Turn on power to flash programming */ | ||
| 93 | IPAQ_EGPIO_LCD_ENABLE, /* Enable/disable LCD controller */ | ||
| 94 | }; | ||
| 95 | |||
| 96 | struct ipaq_model_ops { | ||
| 97 | const char *generic_name; | ||
| 98 | void (*control)(enum ipaq_egpio_type, int); | ||
| 99 | unsigned long (*read)(void); | ||
| 100 | void (*blank_callback)(int blank); | ||
| 101 | int (*pm_callback)(int req); /* Primary model callback */ | ||
| 102 | int (*pm_callback_aux)(int req); /* Secondary callback (used by HAL modules) */ | ||
| 103 | }; | ||
| 104 | |||
| 105 | extern struct ipaq_model_ops ipaq_model_ops; | ||
| 106 | |||
| 107 | static __inline__ const char * h3600_generic_name(void) | ||
| 108 | { | ||
| 109 | return ipaq_model_ops.generic_name; | ||
| 110 | } | ||
| 111 | |||
| 112 | static __inline__ void assign_h3600_egpio(enum ipaq_egpio_type x, int level) | ||
| 113 | { | ||
| 114 | if (ipaq_model_ops.control) | ||
| 115 | ipaq_model_ops.control(x,level); | ||
| 116 | } | ||
| 117 | |||
| 118 | static __inline__ void clr_h3600_egpio(enum ipaq_egpio_type x) | ||
| 119 | { | ||
| 120 | if (ipaq_model_ops.control) | ||
| 121 | ipaq_model_ops.control(x,0); | ||
| 122 | } | ||
| 123 | |||
| 124 | static __inline__ void set_h3600_egpio(enum ipaq_egpio_type x) | ||
| 125 | { | ||
| 126 | if (ipaq_model_ops.control) | ||
| 127 | ipaq_model_ops.control(x,1); | ||
| 128 | } | ||
| 129 | |||
| 130 | static __inline__ unsigned long read_h3600_egpio(void) | ||
| 131 | { | ||
| 132 | if (ipaq_model_ops.read) | ||
| 133 | return ipaq_model_ops.read(); | ||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | static __inline__ int h3600_register_blank_callback(void (*f)(int)) | ||
| 138 | { | ||
| 139 | ipaq_model_ops.blank_callback = f; | ||
| 140 | return 0; | ||
| 141 | } | ||
| 142 | |||
| 143 | static __inline__ void h3600_unregister_blank_callback(void (*f)(int)) | ||
| 144 | { | ||
| 145 | ipaq_model_ops.blank_callback = NULL; | ||
| 146 | } | ||
| 147 | |||
| 148 | |||
| 149 | static __inline__ int h3600_register_pm_callback(int (*f)(int)) | ||
| 150 | { | ||
| 151 | ipaq_model_ops.pm_callback_aux = f; | ||
| 152 | return 0; | ||
| 153 | } | ||
| 154 | |||
| 155 | static __inline__ void h3600_unregister_pm_callback(int (*f)(int)) | ||
| 156 | { | ||
| 157 | ipaq_model_ops.pm_callback_aux = NULL; | ||
| 158 | } | ||
| 159 | |||
| 160 | static __inline__ int h3600_power_management(int req) | ||
| 161 | { | ||
| 162 | if (ipaq_model_ops.pm_callback) | ||
| 163 | return ipaq_model_ops.pm_callback(req); | ||
| 164 | return 0; | ||
| 165 | } | ||
| 166 | |||
| 167 | #endif /* ASSEMBLY */ | ||
| 168 | |||
| 169 | #endif /* _INCLUDE_H3600_H_ */ | ||
diff --git a/include/asm-arm/arch-sa1100/h3600_gpio.h b/include/asm-arm/arch-sa1100/h3600_gpio.h deleted file mode 100644 index 62b0b7879685..000000000000 --- a/include/asm-arm/arch-sa1100/h3600_gpio.h +++ /dev/null | |||
| @@ -1,540 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Definitions for H3600 Handheld Computer | ||
| 4 | * | ||
| 5 | * Copyright 2000 Compaq Computer Corporation. | ||
| 6 | * | ||
| 7 | * Use consistent with the GNU GPL is permitted, | ||
| 8 | * provided that this copyright notice is | ||
| 9 | * preserved in its entirety in all copies and derived works. | ||
| 10 | * | ||
| 11 | * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, | ||
| 12 | * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS | ||
| 13 | * FITNESS FOR ANY PARTICULAR PURPOSE. | ||
| 14 | * | ||
| 15 | * Author: Jamey Hicks. | ||
| 16 | * | ||
| 17 | * History: | ||
| 18 | * | ||
| 19 | * 2001-10-?? Andrew Christian Added support for iPAQ H3800 | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _INCLUDE_H3600_GPIO_H_ | ||
| 24 | #define _INCLUDE_H3600_GPIO_H_ | ||
| 25 | |||
| 26 | /* | ||
| 27 | * GPIO lines that are common across ALL iPAQ models are in "h3600.h" | ||
| 28 | * This file contains machine-specific definitions | ||
| 29 | */ | ||
| 30 | |||
| 31 | #define GPIO_H3600_SUSPEND GPIO_GPIO (0) | ||
| 32 | /* GPIO[2:9] used by LCD on H3600/3800, used as GPIO on H3100 */ | ||
| 33 | #define GPIO_H3100_BT_ON GPIO_GPIO (2) | ||
| 34 | #define GPIO_H3100_GPIO3 GPIO_GPIO (3) | ||
| 35 | #define GPIO_H3100_QMUTE GPIO_GPIO (4) | ||
| 36 | #define GPIO_H3100_LCD_3V_ON GPIO_GPIO (5) | ||
| 37 | #define GPIO_H3100_AUD_ON GPIO_GPIO (6) | ||
| 38 | #define GPIO_H3100_AUD_PWR_ON GPIO_GPIO (7) | ||
| 39 | #define GPIO_H3100_IR_ON GPIO_GPIO (8) | ||
| 40 | #define GPIO_H3100_IR_FSEL GPIO_GPIO (9) | ||
| 41 | |||
| 42 | /* for H3600, audio sample rate clock generator */ | ||
| 43 | #define GPIO_H3600_CLK_SET0 GPIO_GPIO (12) | ||
| 44 | #define GPIO_H3600_CLK_SET1 GPIO_GPIO (13) | ||
| 45 | |||
| 46 | #define GPIO_H3600_ACTION_BUTTON GPIO_GPIO (18) | ||
| 47 | #define GPIO_H3600_SOFT_RESET GPIO_GPIO (20) /* Also known as BATT_FAULT */ | ||
| 48 | #define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) | ||
| 49 | #define GPIO_H3600_OPT_DET GPIO_GPIO (27) | ||
| 50 | |||
| 51 | /* H3800 specific pins */ | ||
| 52 | #define GPIO_H3800_AC_IN GPIO_GPIO (12) | ||
| 53 | #define GPIO_H3800_COM_DSR GPIO_GPIO (13) | ||
| 54 | #define GPIO_H3800_MMC_INT GPIO_GPIO (18) | ||
| 55 | #define GPIO_H3800_NOPT_IND GPIO_GPIO (20) /* Almost exactly the same as GPIO_H3600_OPT_DET */ | ||
| 56 | #define GPIO_H3800_OPT_BAT_FAULT GPIO_GPIO (22) | ||
| 57 | #define GPIO_H3800_CLK_OUT GPIO_GPIO (27) | ||
| 58 | |||
| 59 | /****************************************************/ | ||
| 60 | |||
| 61 | #define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 | ||
| 62 | #define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 | ||
| 63 | |||
| 64 | #define IRQ_GPIO_H3800_MMC_INT IRQ_GPIO18 | ||
| 65 | #define IRQ_GPIO_H3800_NOPT_IND IRQ_GPIO20 /* almost same as OPT_DET */ | ||
| 66 | |||
| 67 | /* H3100 / 3600 EGPIO pins */ | ||
| 68 | #define EGPIO_H3600_VPP_ON (1 << 0) | ||
| 69 | #define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ | ||
| 70 | #define EGPIO_H3600_OPT_RESET (1 << 2) /* reset the attached option pack. active high. */ | ||
| 71 | #define EGPIO_H3600_CODEC_NRESET (1 << 3) /* reset the onboard UDA1341. active low. */ | ||
| 72 | #define EGPIO_H3600_OPT_NVRAM_ON (1 << 4) /* apply power to optionpack nvram, active high. */ | ||
| 73 | #define EGPIO_H3600_OPT_ON (1 << 5) /* full power to option pack. active high. */ | ||
| 74 | #define EGPIO_H3600_LCD_ON (1 << 6) /* enable 3.3V to LCD. active high. */ | ||
| 75 | #define EGPIO_H3600_RS232_ON (1 << 7) /* UART3 transceiver force on. Active high. */ | ||
| 76 | |||
| 77 | /* H3600 only EGPIO pins */ | ||
| 78 | #define EGPIO_H3600_LCD_PCI (1 << 8) /* LCD control IC enable. active high. */ | ||
| 79 | #define EGPIO_H3600_IR_ON (1 << 9) /* apply power to IR module. active high. */ | ||
| 80 | #define EGPIO_H3600_AUD_AMP_ON (1 << 10) /* apply power to audio power amp. active high. */ | ||
| 81 | #define EGPIO_H3600_AUD_PWR_ON (1 << 11) /* apply power to reset of audio circuit. active high. */ | ||
| 82 | #define EGPIO_H3600_QMUTE (1 << 12) /* mute control for onboard UDA1341. active high. */ | ||
| 83 | #define EGPIO_H3600_IR_FSEL (1 << 13) /* IR speed select: 1->fast, 0->slow */ | ||
| 84 | #define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ | ||
| 85 | #define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ | ||
| 86 | |||
| 87 | /********************* H3800, ASIC #2 ********************/ | ||
| 88 | |||
| 89 | #define _H3800_ASIC2_Base (H3600_EGPIO_VIRT) | ||
| 90 | #define H3800_ASIC2_OFFSET(s,x,y) \ | ||
| 91 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) | ||
| 92 | #define H3800_ASIC2_NOFFSET(s,x,n,y) \ | ||
| 93 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) | ||
| 94 | |||
| 95 | #define _H3800_ASIC2_GPIO_Base 0x0000 | ||
| 96 | #define _H3800_ASIC2_GPIO_Direction 0x0000 /* R/W, 16 bits 1:input, 0:output */ | ||
| 97 | #define _H3800_ASIC2_GPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ | ||
| 98 | #define _H3800_ASIC2_GPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ | ||
| 99 | #define _H3800_ASIC2_GPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ | ||
| 100 | #define _H3800_ASIC2_GPIO_InterruptClear 0x0010 /* W, 12 bits */ | ||
| 101 | #define _H3800_ASIC2_GPIO_InterruptFlag 0x0010 /* R, 12 bits - reads int status */ | ||
| 102 | #define _H3800_ASIC2_GPIO_Data 0x0014 /* R/W, 16 bits */ | ||
| 103 | #define _H3800_ASIC2_GPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ | ||
| 104 | #define _H3800_ASIC2_GPIO_InterruptEnable 0x001c /* R/W, 12 bits 1:enable interrupt */ | ||
| 105 | #define _H3800_ASIC2_GPIO_Alternate 0x003c /* R/W, 12+1 bits - set alternate functions */ | ||
| 106 | |||
| 107 | #define H3800_ASIC2_GPIO_Direction H3800_ASIC2_OFFSET( u16, GPIO, Direction ) | ||
| 108 | #define H3800_ASIC2_GPIO_InterruptType H3800_ASIC2_OFFSET( u16, GPIO, InterruptType ) | ||
| 109 | #define H3800_ASIC2_GPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType ) | ||
| 110 | #define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType ) | ||
| 111 | #define H3800_ASIC2_GPIO_InterruptClear H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear ) | ||
| 112 | #define H3800_ASIC2_GPIO_InterruptFlag H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag ) | ||
| 113 | #define H3800_ASIC2_GPIO_Data H3800_ASIC2_OFFSET( u16, GPIO, Data ) | ||
| 114 | #define H3800_ASIC2_GPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut ) | ||
| 115 | #define H3800_ASIC2_GPIO_InterruptEnable H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable ) | ||
| 116 | #define H3800_ASIC2_GPIO_Alternate H3800_ASIC2_OFFSET( u16, GPIO, Alternate ) | ||
| 117 | |||
| 118 | #define GPIO_H3800_ASIC2_IN_Y1_N (1 << 0) /* Output: Touchscreen Y1 */ | ||
| 119 | #define GPIO_H3800_ASIC2_IN_X0 (1 << 1) /* Output: Touchscreen X0 */ | ||
| 120 | #define GPIO_H3800_ASIC2_IN_Y0 (1 << 2) /* Output: Touchscreen Y0 */ | ||
| 121 | #define GPIO_H3800_ASIC2_IN_X1_N (1 << 3) /* Output: Touchscreen X1 */ | ||
| 122 | #define GPIO_H3800_ASIC2_BT_RST (1 << 4) /* Output: Bluetooth reset */ | ||
| 123 | #define GPIO_H3800_ASIC2_PEN_IRQ (1 << 5) /* Input : Pen down */ | ||
| 124 | #define GPIO_H3800_ASIC2_SD_DETECT (1 << 6) /* Input : SD detect */ | ||
| 125 | #define GPIO_H3800_ASIC2_EAR_IN_N (1 << 7) /* Input : Audio jack plug inserted */ | ||
| 126 | #define GPIO_H3800_ASIC2_OPT_PCM_RESET (1 << 8) /* Output: */ | ||
| 127 | #define GPIO_H3800_ASIC2_OPT_RESET (1 << 9) /* Output: */ | ||
| 128 | #define GPIO_H3800_ASIC2_USB_DETECT_N (1 << 10) /* Input : */ | ||
| 129 | #define GPIO_H3800_ASIC2_SD_CON_SLT (1 << 11) /* Input : */ | ||
| 130 | |||
| 131 | #define _H3800_ASIC2_KPIO_Base 0x0200 | ||
| 132 | #define _H3800_ASIC2_KPIO_Direction 0x0000 /* R/W, 12 bits 1:input, 0:output */ | ||
| 133 | #define _H3800_ASIC2_KPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ | ||
| 134 | #define _H3800_ASIC2_KPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ | ||
| 135 | #define _H3800_ASIC2_KPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ | ||
| 136 | #define _H3800_ASIC2_KPIO_InterruptClear 0x0010 /* W, 20 bits - 8 special */ | ||
| 137 | #define _H3800_ASIC2_KPIO_InterruptFlag 0x0010 /* R, 20 bits - 8 special - reads int status */ | ||
| 138 | #define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */ | ||
| 139 | #define _H3800_ASIC2_KPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ | ||
| 140 | #define _H3800_ASIC2_KPIO_InterruptEnable 0x001c /* R/W, 20 bits - 8 special */ | ||
| 141 | #define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */ | ||
| 142 | |||
| 143 | #define H3800_ASIC2_KPIO_Direction H3800_ASIC2_OFFSET( u16, KPIO, Direction ) | ||
| 144 | #define H3800_ASIC2_KPIO_InterruptType H3800_ASIC2_OFFSET( u16, KPIO, InterruptType ) | ||
| 145 | #define H3800_ASIC2_KPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType ) | ||
| 146 | #define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType ) | ||
| 147 | #define H3800_ASIC2_KPIO_InterruptClear H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear ) | ||
| 148 | #define H3800_ASIC2_KPIO_InterruptFlag H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag ) | ||
| 149 | #define H3800_ASIC2_KPIO_Data H3800_ASIC2_OFFSET( u16, KPIO, Data ) | ||
| 150 | #define H3800_ASIC2_KPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut ) | ||
| 151 | #define H3800_ASIC2_KPIO_InterruptEnable H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable ) | ||
| 152 | #define H3800_ASIC2_KPIO_Alternate H3800_ASIC2_OFFSET( u16, KPIO, Alternate ) | ||
| 153 | |||
| 154 | #define H3800_ASIC2_KPIO_SPI_INT ( 1 << 16 ) | ||
| 155 | #define H3800_ASIC2_KPIO_OWM_INT ( 1 << 17 ) | ||
| 156 | #define H3800_ASIC2_KPIO_ADC_INT ( 1 << 18 ) | ||
| 157 | #define H3800_ASIC2_KPIO_UART_0_INT ( 1 << 19 ) | ||
| 158 | #define H3800_ASIC2_KPIO_UART_1_INT ( 1 << 20 ) | ||
| 159 | #define H3800_ASIC2_KPIO_TIMER_0_INT ( 1 << 21 ) | ||
| 160 | #define H3800_ASIC2_KPIO_TIMER_1_INT ( 1 << 22 ) | ||
| 161 | #define H3800_ASIC2_KPIO_TIMER_2_INT ( 1 << 23 ) | ||
| 162 | |||
| 163 | #define KPIO_H3800_ASIC2_RECORD_BTN_N (1 << 0) /* Record button */ | ||
| 164 | #define KPIO_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Keypad */ | ||
| 165 | #define KPIO_H3800_ASIC2_KEY_5W2_N (1 << 2) /* */ | ||
| 166 | #define KPIO_H3800_ASIC2_KEY_5W3_N (1 << 3) /* */ | ||
| 167 | #define KPIO_H3800_ASIC2_KEY_5W4_N (1 << 4) /* */ | ||
| 168 | #define KPIO_H3800_ASIC2_KEY_5W5_N (1 << 5) /* */ | ||
| 169 | #define KPIO_H3800_ASIC2_KEY_LEFT_N (1 << 6) /* */ | ||
| 170 | #define KPIO_H3800_ASIC2_KEY_RIGHT_N (1 << 7) /* */ | ||
| 171 | #define KPIO_H3800_ASIC2_KEY_AP1_N (1 << 8) /* Old "Calendar" */ | ||
| 172 | #define KPIO_H3800_ASIC2_KEY_AP2_N (1 << 9) /* Old "Schedule" */ | ||
| 173 | #define KPIO_H3800_ASIC2_KEY_AP3_N (1 << 10) /* Old "Q" */ | ||
| 174 | #define KPIO_H3800_ASIC2_KEY_AP4_N (1 << 11) /* Old "Undo" */ | ||
| 175 | |||
| 176 | /* Alternate KPIO functions (set by default) */ | ||
| 177 | #define KPIO_ALT_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Action key */ | ||
| 178 | #define KPIO_ALT_H3800_ASIC2_KEY_5W2_N (1 << 2) /* J1 of keypad input */ | ||
| 179 | #define KPIO_ALT_H3800_ASIC2_KEY_5W3_N (1 << 3) /* J2 of keypad input */ | ||
| 180 | #define KPIO_ALT_H3800_ASIC2_KEY_5W4_N (1 << 4) /* J3 of keypad input */ | ||
| 181 | #define KPIO_ALT_H3800_ASIC2_KEY_5W5_N (1 << 5) /* J4 of keypad input */ | ||
| 182 | |||
| 183 | #define _H3800_ASIC2_SPI_Base 0x0400 | ||
| 184 | #define _H3800_ASIC2_SPI_Control 0x0000 /* R/W 8 bits */ | ||
| 185 | #define _H3800_ASIC2_SPI_Data 0x0004 /* R/W 8 bits */ | ||
| 186 | #define _H3800_ASIC2_SPI_ChipSelectDisabled 0x0008 /* W 8 bits */ | ||
| 187 | |||
| 188 | #define H3800_ASIC2_SPI_Control H3800_ASIC2_OFFSET( u8, SPI, Control ) | ||
| 189 | #define H3800_ASIC2_SPI_Data H3800_ASIC2_OFFSET( u8, SPI, Data ) | ||
| 190 | #define H3800_ASIC2_SPI_ChipSelectDisabled H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled ) | ||
| 191 | |||
| 192 | #define _H3800_ASIC2_PWM_0_Base 0x0600 | ||
| 193 | #define _H3800_ASIC2_PWM_1_Base 0x0700 | ||
| 194 | #define _H3800_ASIC2_PWM_TimeBase 0x0000 /* R/W 6 bits */ | ||
| 195 | #define _H3800_ASIC2_PWM_PeriodTime 0x0004 /* R/W 12 bits */ | ||
| 196 | #define _H3800_ASIC2_PWM_DutyTime 0x0008 /* R/W 12 bits */ | ||
| 197 | |||
| 198 | #define H3800_ASIC2_PWM_0_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 0, TimeBase ) | ||
| 199 | #define H3800_ASIC2_PWM_0_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime ) | ||
| 200 | #define H3800_ASIC2_PWM_0_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime ) | ||
| 201 | |||
| 202 | #define H3800_ASIC2_PWM_1_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 1, TimeBase ) | ||
| 203 | #define H3800_ASIC2_PWM_1_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime ) | ||
| 204 | #define H3800_ASIC2_PWM_1_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime ) | ||
| 205 | |||
| 206 | #define H3800_ASIC2_PWM_TIMEBASE_MASK 0xf /* Low 4 bits sets time base, max = 8 */ | ||
| 207 | #define H3800_ASIC2_PWM_TIMEBASE_ENABLE ( 1 << 4 ) /* Enable clock */ | ||
| 208 | #define H3800_ASIC2_PWM_TIMEBASE_CLEAR ( 1 << 5 ) /* Clear the PWM */ | ||
| 209 | |||
| 210 | #define _H3800_ASIC2_LED_0_Base 0x0800 | ||
| 211 | #define _H3800_ASIC2_LED_1_Base 0x0880 | ||
| 212 | #define _H3800_ASIC2_LED_2_Base 0x0900 | ||
| 213 | #define _H3800_ASIC2_LED_TimeBase 0x0000 /* R/W 7 bits */ | ||
| 214 | #define _H3800_ASIC2_LED_PeriodTime 0x0004 /* R/W 12 bits */ | ||
| 215 | #define _H3800_ASIC2_LED_DutyTime 0x0008 /* R/W 12 bits */ | ||
| 216 | #define _H3800_ASIC2_LED_AutoStopCount 0x000c /* R/W 16 bits */ | ||
| 217 | |||
| 218 | #define H3800_ASIC2_LED_0_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 0, TimeBase ) | ||
| 219 | #define H3800_ASIC2_LED_0_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime ) | ||
| 220 | #define H3800_ASIC2_LED_0_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime ) | ||
| 221 | #define H3800_ASIC2_LED_0_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock ) | ||
| 222 | |||
| 223 | #define H3800_ASIC2_LED_1_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 1, TimeBase ) | ||
| 224 | #define H3800_ASIC2_LED_1_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime ) | ||
| 225 | #define H3800_ASIC2_LED_1_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime ) | ||
| 226 | #define H3800_ASIC2_LED_1_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock ) | ||
| 227 | |||
| 228 | #define H3800_ASIC2_LED_2_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 2, TimeBase ) | ||
| 229 | #define H3800_ASIC2_LED_2_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime ) | ||
| 230 | #define H3800_ASIC2_LED_2_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime ) | ||
| 231 | #define H3800_ASIC2_LED_2_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock ) | ||
| 232 | |||
| 233 | #define H3800_ASIC2_LED_TIMEBASE_MASK 0x0f /* Low 4 bits sets time base, max = 13 */ | ||
| 234 | #define H3800_ASIC2_LED_TIMEBASE_BLINK ( 1 << 4 ) /* Enable blinking */ | ||
| 235 | #define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP ( 1 << 5 ) | ||
| 236 | #define H3800_ASIC2_LED_TIMEBASE_ALWAYS ( 1 << 6 ) /* Enable blink always */ | ||
| 237 | |||
| 238 | #define _H3800_ASIC2_UART_0_Base 0x0A00 | ||
| 239 | #define _H3800_ASIC2_UART_1_Base 0x0C00 | ||
| 240 | #define _H3800_ASIC2_UART_Receive 0x0000 /* R 8 bits */ | ||
| 241 | #define _H3800_ASIC2_UART_Transmit 0x0000 /* W 8 bits */ | ||
| 242 | #define _H3800_ASIC2_UART_IntEnable 0x0004 /* R/W 8 bits */ | ||
| 243 | #define _H3800_ASIC2_UART_IntVerify 0x0008 /* R/W 8 bits */ | ||
| 244 | #define _H3800_ASIC2_UART_FIFOControl 0x000c /* R/W 8 bits */ | ||
| 245 | #define _H3800_ASIC2_UART_LineControl 0x0010 /* R/W 8 bits */ | ||
| 246 | #define _H3800_ASIC2_UART_ModemStatus 0x0014 /* R/W 8 bits */ | ||
| 247 | #define _H3800_ASIC2_UART_LineStatus 0x0018 /* R/W 8 bits */ | ||
| 248 | #define _H3800_ASIC2_UART_ScratchPad 0x001c /* R/W 8 bits */ | ||
| 249 | #define _H3800_ASIC2_UART_DivisorLatchL 0x0020 /* R/W 8 bits */ | ||
| 250 | #define _H3800_ASIC2_UART_DivisorLatchH 0x0024 /* R/W 8 bits */ | ||
| 251 | |||
| 252 | #define H3800_ASIC2_UART_0_Receive H3800_ASIC2_NOFFSET( u8, UART, 0, Receive ) | ||
| 253 | #define H3800_ASIC2_UART_0_Transmit H3800_ASIC2_NOFFSET( u8, UART, 0, Transmit ) | ||
| 254 | #define H3800_ASIC2_UART_0_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 0, IntEnable ) | ||
| 255 | #define H3800_ASIC2_UART_0_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 0, IntVerify ) | ||
| 256 | #define H3800_ASIC2_UART_0_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 0, FIFOControl ) | ||
| 257 | #define H3800_ASIC2_UART_0_LineControl H3800_ASIC2_NOFFSET( u8, UART, 0, LineControl ) | ||
| 258 | #define H3800_ASIC2_UART_0_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 0, ModemStatus ) | ||
| 259 | #define H3800_ASIC2_UART_0_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 0, LineStatus ) | ||
| 260 | #define H3800_ASIC2_UART_0_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 0, ScratchPad ) | ||
| 261 | #define H3800_ASIC2_UART_0_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchL ) | ||
| 262 | #define H3800_ASIC2_UART_0_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchH ) | ||
| 263 | |||
| 264 | #define H3800_ASIC2_UART_1_Receive H3800_ASIC2_NOFFSET( u8, UART, 1, Receive ) | ||
| 265 | #define H3800_ASIC2_UART_1_Transmit H3800_ASIC2_NOFFSET( u8, UART, 1, Transmit ) | ||
| 266 | #define H3800_ASIC2_UART_1_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 1, IntEnable ) | ||
| 267 | #define H3800_ASIC2_UART_1_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 1, IntVerify ) | ||
| 268 | #define H3800_ASIC2_UART_1_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 1, FIFOControl ) | ||
| 269 | #define H3800_ASIC2_UART_1_LineControl H3800_ASIC2_NOFFSET( u8, UART, 1, LineControl ) | ||
| 270 | #define H3800_ASIC2_UART_1_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 1, ModemStatus ) | ||
| 271 | #define H3800_ASIC2_UART_1_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 1, LineStatus ) | ||
| 272 | #define H3800_ASIC2_UART_1_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 1, ScratchPad ) | ||
| 273 | #define H3800_ASIC2_UART_1_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchL ) | ||
| 274 | #define H3800_ASIC2_UART_1_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchH ) | ||
| 275 | |||
| 276 | #define _H3800_ASIC2_TIMER_Base 0x0E00 | ||
| 277 | #define _H3800_ASIC2_TIMER_Command 0x0000 /* R/W 8 bits */ | ||
| 278 | |||
| 279 | #define H3800_ASIC2_TIMER_Command H3800_ASIC2_OFFSET( u8, Timer, Command ) | ||
| 280 | |||
| 281 | #define H3800_ASIC2_TIMER_GAT_0 ( 1 << 0 ) /* Gate enable, counter 0 */ | ||
| 282 | #define H3800_ASIC2_TIMER_GAT_1 ( 1 << 1 ) /* Gate enable, counter 1 */ | ||
| 283 | #define H3800_ASIC2_TIMER_GAT_2 ( 1 << 2 ) /* Gate enable, counter 2 */ | ||
| 284 | #define H3800_ASIC2_TIMER_CLK_0 ( 1 << 3 ) /* Clock enable, counter 0 */ | ||
| 285 | #define H3800_ASIC2_TIMER_CLK_1 ( 1 << 4 ) /* Clock enable, counter 1 */ | ||
| 286 | #define H3800_ASIC2_TIMER_CLK_2 ( 1 << 5 ) /* Clock enable, counter 2 */ | ||
| 287 | #define H3800_ASIC2_TIMER_MODE_0 ( 1 << 6 ) /* Mode 0 enable, counter 0 */ | ||
| 288 | #define H3800_ASIC2_TIMER_MODE_1 ( 1 << 7 ) /* Mode 0 enable, counter 1 */ | ||
| 289 | |||
| 290 | #define _H3800_ASIC2_CLOCK_Base 0x1000 | ||
| 291 | #define _H3800_ASIC2_CLOCK_Enable 0x0000 /* R/W 18 bits */ | ||
| 292 | |||
| 293 | #define H3800_ASIC2_CLOCK_Enable H3800_ASIC2_OFFSET( u32, CLOCK, Enable ) | ||
| 294 | |||
| 295 | #define H3800_ASIC2_CLOCK_AUDIO_1 0x0001 /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */ | ||
| 296 | #define H3800_ASIC2_CLOCK_AUDIO_2 0x0002 /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */ | ||
| 297 | #define H3800_ASIC2_CLOCK_AUDIO_3 0x0004 /* Enable 5.6 MHz clock for 11 kHZ sample rate */ | ||
| 298 | #define H3800_ASIC2_CLOCK_AUDIO_4 0x0008 /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */ | ||
| 299 | #define H3800_ASIC2_CLOCK_ADC ( 1 << 4 ) /* 1.024 MHz clock to ADC */ | ||
| 300 | #define H3800_ASIC2_CLOCK_SPI ( 1 << 5 ) /* 4.096 MHz clock to SPI */ | ||
| 301 | #define H3800_ASIC2_CLOCK_OWM ( 1 << 6 ) /* 4.096 MHz clock to OWM */ | ||
| 302 | #define H3800_ASIC2_CLOCK_PWM ( 1 << 7 ) /* 2.048 MHz clock to PWM */ | ||
| 303 | #define H3800_ASIC2_CLOCK_UART_1 ( 1 << 8 ) /* 24.576 MHz clock to UART1 (turn off bit 16) */ | ||
| 304 | #define H3800_ASIC2_CLOCK_UART_0 ( 1 << 9 ) /* 24.576 MHz clock to UART0 (turn off bit 17) */ | ||
| 305 | #define H3800_ASIC2_CLOCK_SD_1 ( 1 << 10 ) /* 16.934 MHz to SD */ | ||
| 306 | #define H3800_ASIC2_CLOCK_SD_2 ( 2 << 10 ) /* 24.576 MHz to SD */ | ||
| 307 | #define H3800_ASIC2_CLOCK_SD_3 ( 3 << 10 ) /* 33.869 MHz to SD */ | ||
| 308 | #define H3800_ASIC2_CLOCK_SD_4 ( 4 << 10 ) /* 49.152 MHz to SD */ | ||
| 309 | #define H3800_ASIC2_CLOCK_EX0 ( 1 << 13 ) /* Enable 32.768 kHz crystal */ | ||
| 310 | #define H3800_ASIC2_CLOCK_EX1 ( 1 << 14 ) /* Enable 24.576 MHz crystal */ | ||
| 311 | #define H3800_ASIC2_CLOCK_EX2 ( 1 << 15 ) /* Enable 33.869 MHz crystal */ | ||
| 312 | #define H3800_ASIC2_CLOCK_SLOW_UART_1 ( 1 << 16 ) /* Enable 3.686 MHz to UART1 (turn off bit 8) */ | ||
| 313 | #define H3800_ASIC2_CLOCK_SLOW_UART_0 ( 1 << 17 ) /* Enable 3.686 MHz to UART0 (turn off bit 9) */ | ||
| 314 | |||
| 315 | #define _H3800_ASIC2_ADC_Base 0x1200 | ||
| 316 | #define _H3800_ASIC2_ADC_Multiplexer 0x0000 /* R/W 4 bits - low 3 bits set channel */ | ||
| 317 | #define _H3800_ASIC2_ADC_ControlStatus 0x0004 /* R/W 8 bits */ | ||
| 318 | #define _H3800_ASIC2_ADC_Data 0x0008 /* R 10 bits */ | ||
| 319 | |||
| 320 | #define H3800_ASIC2_ADC_Multiplexer H3800_ASIC2_OFFSET( u8, ADC, Multiplexer ) | ||
| 321 | #define H3800_ASIC2_ADC_ControlStatus H3800_ASIC2_OFFSET( u8, ADC, ControlStatus ) | ||
| 322 | #define H3800_ASIC2_ADC_Data H3800_ASIC2_OFFSET( u16, ADC, Data ) | ||
| 323 | |||
| 324 | #define H3600_ASIC2_ADC_MUX_CHANNEL_MASK 0x07 /* Low 3 bits sets channel. max = 4 */ | ||
| 325 | #define H3600_ASIC2_ADC_MUX_CLKEN ( 1 << 3 ) /* Enable clock */ | ||
| 326 | |||
| 327 | #define H3600_ASIC2_ADC_CSR_ADPS_MASK 0x0f /* Low 4 bits sets prescale, max = 8 */ | ||
| 328 | #define H3600_ASIC2_ADC_CSR_FREE_RUN ( 1 << 4 ) | ||
| 329 | #define H3600_ASIC2_ADC_CSR_INT_ENABLE ( 1 << 5 ) | ||
| 330 | #define H3600_ASIC2_ADC_CSR_START ( 1 << 6 ) /* Set to start conversion. Goes to 0 when done */ | ||
| 331 | #define H3600_ASIC2_ADC_CSR_ENABLE ( 1 << 7 ) /* 1:power up ADC, 0:power down */ | ||
| 332 | |||
| 333 | |||
| 334 | #define _H3800_ASIC2_INTR_Base 0x1600 | ||
| 335 | #define _H3800_ASIC2_INTR_MaskAndFlag 0x0000 /* R/(W) 8bits */ | ||
| 336 | #define _H3800_ASIC2_INTR_ClockPrescale 0x0004 /* R/(W) 5bits */ | ||
| 337 | #define _H3800_ASIC2_INTR_TimerSet 0x0008 /* R/(W) 8bits */ | ||
| 338 | |||
| 339 | #define H3800_ASIC2_INTR_MaskAndFlag H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag ) | ||
| 340 | #define H3800_ASIC2_INTR_ClockPrescale H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale ) | ||
| 341 | #define H3800_ASIC2_INTR_TimerSet H3800_ASIC2_OFFSET( u8, INTR, TimerSet ) | ||
| 342 | |||
| 343 | #define H3800_ASIC2_INTR_GLOBAL_MASK ( 1 << 0 ) /* Global interrupt mask */ | ||
| 344 | #define H3800_ASIC2_INTR_POWER_ON_RESET ( 1 << 1 ) /* 01: Power on reset (bits 1 & 2 ) */ | ||
| 345 | #define H3800_ASIC2_INTR_EXTERNAL_RESET ( 2 << 1 ) /* 10: External reset (bits 1 & 2 ) */ | ||
| 346 | #define H3800_ASIC2_INTR_MASK_UART_0 ( 1 << 4 ) | ||
| 347 | #define H3800_ASIC2_INTR_MASK_UART_1 ( 1 << 5 ) | ||
| 348 | #define H3800_ASIC2_INTR_MASK_TIMER ( 1 << 6 ) | ||
| 349 | #define H3800_ASIC2_INTR_MASK_OWM ( 1 << 7 ) | ||
| 350 | |||
| 351 | #define H3800_ASIC2_INTR_CLOCK_PRESCALE 0x0f /* 4 bits, max 14 */ | ||
| 352 | #define H3800_ASIC2_INTR_SET ( 1 << 4 ) /* Time base enable */ | ||
| 353 | |||
| 354 | |||
| 355 | #define _H3800_ASIC2_OWM_Base 0x1800 | ||
| 356 | #define _H3800_ASIC2_OWM_Command 0x0000 /* R/W 4 bits command register */ | ||
| 357 | #define _H3800_ASIC2_OWM_Data 0x0004 /* R/W 8 bits, transmit / receive buffer */ | ||
| 358 | #define _H3800_ASIC2_OWM_Interrupt 0x0008 /* R/W Command register */ | ||
| 359 | #define _H3800_ASIC2_OWM_InterruptEnable 0x000c /* R/W Command register */ | ||
| 360 | #define _H3800_ASIC2_OWM_ClockDivisor 0x0010 /* R/W 5 bits of divisor and pre-scale */ | ||
| 361 | |||
| 362 | #define H3800_ASIC2_OWM_Command H3800_ASIC2_OFFSET( u8, OWM, Command ) | ||
| 363 | #define H3800_ASIC2_OWM_Data H3800_ASIC2_OFFSET( u8, OWM, Data ) | ||
| 364 | #define H3800_ASIC2_OWM_Interrupt H3800_ASIC2_OFFSET( u8, OWM, Interrupt ) | ||
| 365 | #define H3800_ASIC2_OWM_InterruptEnable H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable ) | ||
| 366 | #define H3800_ASIC2_OWM_ClockDivisor H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor ) | ||
| 367 | |||
| 368 | #define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 ) /* Set to force reset on 1-wire bus */ | ||
| 369 | #define H3800_ASIC2_OWM_CMD_SRA ( 1 << 1 ) /* Set to switch to Search ROM accelerator mode */ | ||
| 370 | #define H3800_ASIC2_OWM_CMD_DQ_OUTPUT ( 1 << 2 ) /* Write only - forces bus low */ | ||
| 371 | #define H3800_ASIC2_OWM_CMD_DQ_INPUT ( 1 << 3 ) /* Read only - reflects state of bus */ | ||
| 372 | |||
| 373 | #define H3800_ASIC2_OWM_INT_PD ( 1 << 0 ) /* Presence detect */ | ||
| 374 | #define H3800_ASIC2_OWM_INT_PDR ( 1 << 1 ) /* Presence detect result */ | ||
| 375 | #define H3800_ASIC2_OWM_INT_TBE ( 1 << 2 ) /* Transmit buffer empty */ | ||
| 376 | #define H3800_ASIC2_OWM_INT_TEMT ( 1 << 3 ) /* Transmit shift register empty */ | ||
| 377 | #define H3800_ASIC2_OWM_INT_RBF ( 1 << 4 ) /* Receive buffer full */ | ||
| 378 | |||
| 379 | #define H3800_ASIC2_OWM_INTEN_EPD ( 1 << 0 ) /* Enable receive buffer full interrupt */ | ||
| 380 | #define H3800_ASIC2_OWM_INTEN_IAS ( 1 << 1 ) /* Enable transmit shift register empty interrupt */ | ||
| 381 | #define H3800_ASIC2_OWM_INTEN_ETBE ( 1 << 2 ) /* Enable transmit buffer empty interrupt */ | ||
| 382 | #define H3800_ASIC2_OWM_INTEN_ETMT ( 1 << 3 ) /* INTR active state */ | ||
| 383 | #define H3800_ASIC2_OWM_INTEN_ERBF ( 1 << 4 ) /* Enable presence detect interrupt */ | ||
| 384 | |||
| 385 | #define _H3800_ASIC2_FlashCtl_Base 0x1A00 | ||
| 386 | |||
| 387 | /****************************************************/ | ||
| 388 | /* H3800, ASIC #1 | ||
| 389 | * This ASIC is accesed through ASIC #2, and | ||
| 390 | * mapped into the 1c00 - 1f00 region | ||
| 391 | */ | ||
| 392 | |||
| 393 | #define H3800_ASIC1_OFFSET(s,x,y) \ | ||
| 394 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1)))) | ||
| 395 | |||
| 396 | #define _H3800_ASIC1_MMC_Base 0x1c00 | ||
| 397 | |||
| 398 | #define _H3800_ASIC1_MMC_StartStopClock 0x00 /* R/W 8bit */ | ||
| 399 | #define _H3800_ASIC1_MMC_Status 0x02 /* R See below, default 0x0040 */ | ||
| 400 | #define _H3800_ASIC1_MMC_ClockRate 0x04 /* R/W 8bit, low 3 bits are clock divisor */ | ||
| 401 | #define _H3800_ASIC1_MMC_SPIRegister 0x08 /* R/W 8bit, see below */ | ||
| 402 | #define _H3800_ASIC1_MMC_CmdDataCont 0x0a /* R/W 8bit, write to start MMC adapter */ | ||
| 403 | #define _H3800_ASIC1_MMC_ResponseTimeout 0x0c /* R/W 8bit, clocks before response timeout */ | ||
| 404 | #define _H3800_ASIC1_MMC_ReadTimeout 0x0e /* R/W 16bit, clocks before received data timeout */ | ||
| 405 | #define _H3800_ASIC1_MMC_BlockLength 0x10 /* R/W 10bit */ | ||
| 406 | #define _H3800_ASIC1_MMC_NumOfBlocks 0x12 /* R/W 16bit, in block mode, number of blocks */ | ||
| 407 | #define _H3800_ASIC1_MMC_InterruptMask 0x1a /* R/W 8bit */ | ||
| 408 | #define _H3800_ASIC1_MMC_CommandNumber 0x1c /* R/W 6 bits */ | ||
| 409 | #define _H3800_ASIC1_MMC_ArgumentH 0x1e /* R/W 16 bits */ | ||
| 410 | #define _H3800_ASIC1_MMC_ArgumentL 0x20 /* R/W 16 bits */ | ||
| 411 | #define _H3800_ASIC1_MMC_ResFifo 0x22 /* R 8 x 16 bits - contains response FIFO */ | ||
| 412 | #define _H3800_ASIC1_MMC_BufferPartFull 0x28 /* R/W 8 bits */ | ||
| 413 | |||
| 414 | #define H3800_ASIC1_MMC_StartStopClock H3800_ASIC1_OFFSET( u8, MMC, StartStopClock ) | ||
| 415 | #define H3800_ASIC1_MMC_Status H3800_ASIC1_OFFSET( u16, MMC, Status ) | ||
| 416 | #define H3800_ASIC1_MMC_ClockRate H3800_ASIC1_OFFSET( u8, MMC, ClockRate ) | ||
| 417 | #define H3800_ASIC1_MMC_SPIRegister H3800_ASIC1_OFFSET( u8, MMC, SPIRegister ) | ||
| 418 | #define H3800_ASIC1_MMC_CmdDataCont H3800_ASIC1_OFFSET( u8, MMC, CmdDataCont ) | ||
| 419 | #define H3800_ASIC1_MMC_ResponseTimeout H3800_ASIC1_OFFSET( u8, MMC, ResponseTimeout ) | ||
| 420 | #define H3800_ASIC1_MMC_ReadTimeout H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout ) | ||
| 421 | #define H3800_ASIC1_MMC_BlockLength H3800_ASIC1_OFFSET( u16, MMC, BlockLength ) | ||
| 422 | #define H3800_ASIC1_MMC_NumOfBlocks H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks ) | ||
| 423 | #define H3800_ASIC1_MMC_InterruptMask H3800_ASIC1_OFFSET( u8, MMC, InterruptMask ) | ||
| 424 | #define H3800_ASIC1_MMC_CommandNumber H3800_ASIC1_OFFSET( u8, MMC, CommandNumber ) | ||
| 425 | #define H3800_ASIC1_MMC_ArgumentH H3800_ASIC1_OFFSET( u16, MMC, ArgumentH ) | ||
| 426 | #define H3800_ASIC1_MMC_ArgumentL H3800_ASIC1_OFFSET( u16, MMC, ArgumentL ) | ||
| 427 | #define H3800_ASIC1_MMC_ResFifo H3800_ASIC1_OFFSET( u16, MMC, ResFifo ) | ||
| 428 | #define H3800_ASIC1_MMC_BufferPartFull H3800_ASIC1_OFFSET( u8, MMC, BufferPartFull ) | ||
| 429 | |||
| 430 | #define H3800_ASIC1_MMC_STOP_CLOCK (1 << 0) /* Write to "StartStopClock" register */ | ||
| 431 | #define H3800_ASIC1_MMC_START_CLOCK (1 << 1) | ||
| 432 | |||
| 433 | #define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT (1 << 0) | ||
| 434 | #define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT (1 << 1) | ||
| 435 | #define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR (1 << 2) | ||
| 436 | #define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR (1 << 3) | ||
| 437 | #define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR (1 << 4) /* SPI data token error received */ | ||
| 438 | #define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR (1 << 5) | ||
| 439 | #define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY (1 << 6) | ||
| 440 | #define H3800_ASIC1_MMC_STATUS_FIFO_FULL (1 << 7) | ||
| 441 | #define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE (1 << 8) /* MultiMediaCard clock stopped */ | ||
| 442 | #define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE (1 << 11) /* Write operation, indicates transfer finished */ | ||
| 443 | #define H3800_ASIC1_MMC_STATUS_END_PROGRAM (1 << 12) /* End write and read operations */ | ||
| 444 | #define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE (1 << 13) /* End command response */ | ||
| 445 | |||
| 446 | #define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE (1 << 0) /* Enables SPI mode */ | ||
| 447 | #define H3800_ASIC1_MMC_SPI_REG_CRC_ON (1 << 1) /* 1:turn on CRC */ | ||
| 448 | #define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE (1 << 2) /* 1:turn on SPI CS */ | ||
| 449 | #define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK 0x38 /* Bits 3,4,5 are the SPI CS relative address */ | ||
| 450 | |||
| 451 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE 0x00 | ||
| 452 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1 0x01 | ||
| 453 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2 0x02 | ||
| 454 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3 0x03 | ||
| 455 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE (1 << 2) /* This command contains a data transfer */ | ||
| 456 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE (1 << 3) /* This data transfer is a write */ | ||
| 457 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE (1 << 4) /* This data transfer is in stream mode */ | ||
| 458 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT (1 << 5) /* Busy signal expected after current cmd */ | ||
| 459 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE (1 << 6) /* Enables the 80 bits for initializing card */ | ||
| 460 | |||
| 461 | #define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE (1 << 0) | ||
| 462 | #define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE (1 << 1) | ||
| 463 | #define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE (1 << 2) | ||
| 464 | #define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY (1 << 3) | ||
| 465 | |||
| 466 | #define H3800_ASIC1_MMC_BUFFER_PART_FULL (1 << 0) | ||
| 467 | |||
| 468 | /********* GPIO **********/ | ||
| 469 | |||
| 470 | #define _H3800_ASIC1_GPIO_Base 0x1e00 | ||
| 471 | |||
| 472 | #define _H3800_ASIC1_GPIO_Mask 0x30 /* R/W 0:don't mask, 1:mask interrupt */ | ||
| 473 | #define _H3800_ASIC1_GPIO_Direction 0x32 /* R/W 0:input, 1:output */ | ||
| 474 | #define _H3800_ASIC1_GPIO_Out 0x34 /* R/W 0:output low, 1:output high */ | ||
| 475 | #define _H3800_ASIC1_GPIO_TriggerType 0x36 /* R/W 0:level, 1:edge */ | ||
| 476 | #define _H3800_ASIC1_GPIO_EdgeTrigger 0x38 /* R/W 0:falling, 1:rising */ | ||
| 477 | #define _H3800_ASIC1_GPIO_LevelTrigger 0x3A /* R/W 0:low, 1:high level detect */ | ||
| 478 | #define _H3800_ASIC1_GPIO_LevelStatus 0x3C /* R/W 0:none, 1:detect */ | ||
| 479 | #define _H3800_ASIC1_GPIO_EdgeStatus 0x3E /* R/W 0:none, 1:detect */ | ||
| 480 | #define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */ | ||
| 481 | #define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */ | ||
| 482 | #define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */ | ||
| 483 | #define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:output in sleep mode */ | ||
| 484 | #define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */ | ||
| 485 | #define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */ | ||
| 486 | #define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */ | ||
| 487 | #define _H3800_ASIC1_GPIO_BattFaultOut 0x4E /* R/W level 0:low, 1:high in batt_fault */ | ||
| 488 | |||
| 489 | #define H3800_ASIC1_GPIO_Mask H3800_ASIC1_OFFSET( u16, GPIO, Mask ) | ||
| 490 | #define H3800_ASIC1_GPIO_Direction H3800_ASIC1_OFFSET( u16, GPIO, Direction ) | ||
| 491 | #define H3800_ASIC1_GPIO_Out H3800_ASIC1_OFFSET( u16, GPIO, Out ) | ||
| 492 | #define H3800_ASIC1_GPIO_TriggerType H3800_ASIC1_OFFSET( u16, GPIO, TriggerType ) | ||
| 493 | #define H3800_ASIC1_GPIO_EdgeTrigger H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger ) | ||
| 494 | #define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger ) | ||
| 495 | #define H3800_ASIC1_GPIO_LevelStatus H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus ) | ||
| 496 | #define H3800_ASIC1_GPIO_EdgeStatus H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus ) | ||
| 497 | #define H3800_ASIC1_GPIO_State H3800_ASIC1_OFFSET( u8, GPIO, State ) | ||
| 498 | #define H3800_ASIC1_GPIO_Reset H3800_ASIC1_OFFSET( u8, GPIO, Reset ) | ||
| 499 | #define H3800_ASIC1_GPIO_SleepMask H3800_ASIC1_OFFSET( u16, GPIO, SleepMask ) | ||
| 500 | #define H3800_ASIC1_GPIO_SleepDir H3800_ASIC1_OFFSET( u16, GPIO, SleepDir ) | ||
| 501 | #define H3800_ASIC1_GPIO_SleepOut H3800_ASIC1_OFFSET( u16, GPIO, SleepOut ) | ||
| 502 | #define H3800_ASIC1_GPIO_Status H3800_ASIC1_OFFSET( u16, GPIO, Status ) | ||
| 503 | #define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir ) | ||
| 504 | #define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut ) | ||
| 505 | |||
| 506 | #define H3800_ASIC1_GPIO_STATE_MASK (1 << 0) | ||
| 507 | #define H3800_ASIC1_GPIO_STATE_DIRECTION (1 << 1) | ||
| 508 | #define H3800_ASIC1_GPIO_STATE_OUT (1 << 2) | ||
| 509 | #define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE (1 << 3) | ||
| 510 | #define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER (1 << 4) | ||
| 511 | #define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER (1 << 5) | ||
| 512 | |||
| 513 | #define H3800_ASIC1_GPIO_RESET_SOFTWARE (1 << 0) | ||
| 514 | #define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP (1 << 1) | ||
| 515 | #define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON (1 << 2) | ||
| 516 | |||
| 517 | /* These are all outputs */ | ||
| 518 | #define GPIO_H3800_ASIC1_IR_ON_N (1 << 0) /* Apply power to the IR Module */ | ||
| 519 | #define GPIO_H3800_ASIC1_SD_PWR_ON (1 << 1) /* Secure Digital power on */ | ||
| 520 | #define GPIO_H3800_ASIC1_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */ | ||
| 521 | #define GPIO_H3800_ASIC1_PULSE_GEN (1 << 3) /* Goes to speaker / earphone */ | ||
| 522 | #define GPIO_H3800_ASIC1_CH_TIMER (1 << 4) /* */ | ||
| 523 | #define GPIO_H3800_ASIC1_LCD_5V_ON (1 << 5) /* Enables LCD_5V */ | ||
| 524 | #define GPIO_H3800_ASIC1_LCD_ON (1 << 6) /* Enables LCD_3V */ | ||
| 525 | #define GPIO_H3800_ASIC1_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */ | ||
| 526 | #define GPIO_H3800_ASIC1_VGH_ON (1 << 8) /* Drives VGH on the LCD (+9??) */ | ||
| 527 | #define GPIO_H3800_ASIC1_VGL_ON (1 << 9) /* Drivers VGL on the LCD (-6??) */ | ||
| 528 | #define GPIO_H3800_ASIC1_FL_PWR_ON (1 << 10) /* Frontlight power on */ | ||
| 529 | #define GPIO_H3800_ASIC1_BT_PWR_ON (1 << 11) /* Bluetooth power on */ | ||
| 530 | #define GPIO_H3800_ASIC1_SPK_ON (1 << 12) /* */ | ||
| 531 | #define GPIO_H3800_ASIC1_EAR_ON_N (1 << 13) /* */ | ||
| 532 | #define GPIO_H3800_ASIC1_AUD_PWR_ON (1 << 14) /* */ | ||
| 533 | |||
| 534 | /* Write enable for the flash */ | ||
| 535 | |||
| 536 | #define _H3800_ASIC1_FlashWP_Base 0x1F00 | ||
| 537 | #define _H3800_ASIC1_FlashWP_VPP_ON 0x00 /* R 1: write, 0: protect */ | ||
| 538 | #define H3800_ASIC1_FlashWP_VPP_ON H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON ) | ||
| 539 | |||
| 540 | #endif /* _INCLUDE_H3600_GPIO_H_ */ | ||
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h deleted file mode 100644 index 1abd7cfc8bce..000000000000 --- a/include/asm-arm/arch-sa1100/hardware.h +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1998 Nicolas Pitre <nico@cam.org> | ||
| 5 | * | ||
| 6 | * This file contains the hardware definitions for SA1100 architecture | ||
| 7 | * | ||
| 8 | * 2000/05/23 John Dorsey <john+@cs.cmu.edu> | ||
| 9 | * Definitions for SA1111 added. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 13 | #define __ASM_ARCH_HARDWARE_H | ||
| 14 | |||
| 15 | |||
| 16 | #define UNCACHEABLE_ADDR 0xfa050000 | ||
| 17 | |||
| 18 | |||
| 19 | /* | ||
| 20 | * SA1100 internal I/O mappings | ||
| 21 | * | ||
| 22 | * We have the following mapping: | ||
| 23 | * phys virt | ||
| 24 | * 80000000 f8000000 | ||
| 25 | * 90000000 fa000000 | ||
| 26 | * a0000000 fc000000 | ||
| 27 | * b0000000 fe000000 | ||
| 28 | */ | ||
| 29 | |||
| 30 | #define VIO_BASE 0xf8000000 /* virtual start of IO space */ | ||
| 31 | #define VIO_SHIFT 3 /* x = IO space shrink power */ | ||
| 32 | #define PIO_START 0x80000000 /* physical start of IO space */ | ||
| 33 | |||
| 34 | #define io_p2v( x ) \ | ||
| 35 | ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE ) | ||
| 36 | #define io_v2p( x ) \ | ||
| 37 | ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) | ||
| 38 | |||
| 39 | #ifndef __ASSEMBLY__ | ||
| 40 | |||
| 41 | # define __REG(x) (*((volatile unsigned long *)io_p2v(x))) | ||
| 42 | # define __PREG(x) (io_v2p((unsigned long)&(x))) | ||
| 43 | |||
| 44 | #else | ||
| 45 | |||
| 46 | # define __REG(x) io_p2v(x) | ||
| 47 | # define __PREG(x) io_v2p(x) | ||
| 48 | |||
| 49 | #endif | ||
| 50 | |||
| 51 | #include "SA-1100.h" | ||
| 52 | |||
| 53 | #ifdef CONFIG_SA1101 | ||
| 54 | #include "SA-1101.h" | ||
| 55 | #endif | ||
| 56 | |||
| 57 | #endif /* _ASM_ARCH_HARDWARE_H */ | ||
diff --git a/include/asm-arm/arch-sa1100/ide.h b/include/asm-arm/arch-sa1100/ide.h deleted file mode 100644 index 24972f30195a..000000000000 --- a/include/asm-arm/arch-sa1100/ide.h +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/ide.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 1998 Hugo Fiennes & Nicolas Pitre | ||
| 5 | * | ||
| 6 | * 18-aug-2000: Cleanup by Erik Mouw (J.A.K.Mouw@its.tudelft.nl) | ||
| 7 | * Get rid of the special ide_init_hwif_ports() functions | ||
| 8 | * and make a generalised function that can be used by all | ||
| 9 | * architectures. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <asm/irq.h> | ||
| 13 | #include <asm/arch/hardware.h> | ||
| 14 | #include <asm/mach-types.h> | ||
| 15 | |||
| 16 | #error "This code is broken and needs update to match with current ide support" | ||
| 17 | |||
| 18 | |||
| 19 | /* | ||
| 20 | * Set up a hw structure for a specified data port, control port and IRQ. | ||
| 21 | * This should follow whatever the default interface uses. | ||
| 22 | */ | ||
| 23 | static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, | ||
| 24 | unsigned long ctrl_port, int *irq) | ||
| 25 | { | ||
| 26 | unsigned long reg = data_port; | ||
| 27 | int i; | ||
| 28 | int regincr = 1; | ||
| 29 | |||
| 30 | /* The Empeg board has the first two address lines unused */ | ||
| 31 | if (machine_is_empeg()) | ||
| 32 | regincr = 1 << 2; | ||
| 33 | |||
| 34 | /* The LART doesn't use A0 for IDE */ | ||
| 35 | if (machine_is_lart()) | ||
| 36 | regincr = 1 << 1; | ||
| 37 | |||
| 38 | memset(hw, 0, sizeof(*hw)); | ||
| 39 | |||
| 40 | for (i = 0; i <= 7; i++) { | ||
| 41 | hw->io_ports_array[i] = reg; | ||
| 42 | reg += regincr; | ||
| 43 | } | ||
| 44 | |||
| 45 | hw->io_ports.ctl_addr = ctrl_port; | ||
| 46 | |||
| 47 | if (irq) | ||
| 48 | *irq = 0; | ||
| 49 | } | ||
| 50 | |||
| 51 | /* | ||
| 52 | * This registers the standard ports for this architecture with the IDE | ||
| 53 | * driver. | ||
| 54 | */ | ||
| 55 | static __inline__ void | ||
| 56 | ide_init_default_hwifs(void) | ||
| 57 | { | ||
| 58 | if (machine_is_lart()) { | ||
| 59 | #ifdef CONFIG_SA1100_LART | ||
| 60 | hw_regs_t hw; | ||
| 61 | |||
| 62 | /* Enable GPIO as interrupt line */ | ||
| 63 | GPDR &= ~LART_GPIO_IDE; | ||
| 64 | set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING); | ||
| 65 | |||
| 66 | /* set PCMCIA interface timing */ | ||
| 67 | MECR = 0x00060006; | ||
| 68 | |||
| 69 | /* init the interface */ | ||
| 70 | ide_init_hwif_ports(&hw, PCMCIA_IO_0_BASE + 0x0000, PCMCIA_IO_0_BASE + 0x1000, NULL); | ||
| 71 | hw.irq = LART_IRQ_IDE; | ||
| 72 | ide_register_hw(&hw); | ||
| 73 | #endif | ||
| 74 | } | ||
| 75 | } | ||
diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h deleted file mode 100644 index 0756269404b1..000000000000 --- a/include/asm-arm/arch-sa1100/io.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997-1999 Russell King | ||
| 5 | * | ||
| 6 | * Modifications: | ||
| 7 | * 06-12-1997 RMK Created. | ||
| 8 | * 07-04-1999 RMK Major cleanup | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 11 | #define __ASM_ARM_ARCH_IO_H | ||
| 12 | |||
| 13 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 14 | |||
| 15 | /* | ||
| 16 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
| 17 | * drivers out there that might just work if we fake them... | ||
| 18 | */ | ||
| 19 | static inline void __iomem *__io(unsigned long addr) | ||
| 20 | { | ||
| 21 | return (void __iomem *)addr; | ||
| 22 | } | ||
| 23 | #define __io(a) __io(a) | ||
| 24 | #define __mem_pci(a) (a) | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/include/asm-arm/arch-sa1100/irqs.h b/include/asm-arm/arch-sa1100/irqs.h deleted file mode 100644 index 7bf80484bb77..000000000000 --- a/include/asm-arm/arch-sa1100/irqs.h +++ /dev/null | |||
| @@ -1,197 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996 Russell King | ||
| 5 | * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus). | ||
| 6 | * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation) | ||
| 7 | * | ||
| 8 | * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #define IRQ_GPIO0 0 | ||
| 12 | #define IRQ_GPIO1 1 | ||
| 13 | #define IRQ_GPIO2 2 | ||
| 14 | #define IRQ_GPIO3 3 | ||
| 15 | #define IRQ_GPIO4 4 | ||
| 16 | #define IRQ_GPIO5 5 | ||
| 17 | #define IRQ_GPIO6 6 | ||
| 18 | #define IRQ_GPIO7 7 | ||
| 19 | #define IRQ_GPIO8 8 | ||
| 20 | #define IRQ_GPIO9 9 | ||
| 21 | #define IRQ_GPIO10 10 | ||
| 22 | #define IRQ_GPIO11_27 11 | ||
| 23 | #define IRQ_LCD 12 /* LCD controller */ | ||
| 24 | #define IRQ_Ser0UDC 13 /* Ser. port 0 UDC */ | ||
| 25 | #define IRQ_Ser1SDLC 14 /* Ser. port 1 SDLC */ | ||
| 26 | #define IRQ_Ser1UART 15 /* Ser. port 1 UART */ | ||
| 27 | #define IRQ_Ser2ICP 16 /* Ser. port 2 ICP */ | ||
| 28 | #define IRQ_Ser3UART 17 /* Ser. port 3 UART */ | ||
| 29 | #define IRQ_Ser4MCP 18 /* Ser. port 4 MCP */ | ||
| 30 | #define IRQ_Ser4SSP 19 /* Ser. port 4 SSP */ | ||
| 31 | #define IRQ_DMA0 20 /* DMA controller channel 0 */ | ||
| 32 | #define IRQ_DMA1 21 /* DMA controller channel 1 */ | ||
| 33 | #define IRQ_DMA2 22 /* DMA controller channel 2 */ | ||
| 34 | #define IRQ_DMA3 23 /* DMA controller channel 3 */ | ||
| 35 | #define IRQ_DMA4 24 /* DMA controller channel 4 */ | ||
| 36 | #define IRQ_DMA5 25 /* DMA controller channel 5 */ | ||
| 37 | #define IRQ_OST0 26 /* OS Timer match 0 */ | ||
| 38 | #define IRQ_OST1 27 /* OS Timer match 1 */ | ||
| 39 | #define IRQ_OST2 28 /* OS Timer match 2 */ | ||
| 40 | #define IRQ_OST3 29 /* OS Timer match 3 */ | ||
| 41 | #define IRQ_RTC1Hz 30 /* RTC 1 Hz clock */ | ||
| 42 | #define IRQ_RTCAlrm 31 /* RTC Alarm */ | ||
| 43 | |||
| 44 | #define IRQ_GPIO11 32 | ||
| 45 | #define IRQ_GPIO12 33 | ||
| 46 | #define IRQ_GPIO13 34 | ||
| 47 | #define IRQ_GPIO14 35 | ||
| 48 | #define IRQ_GPIO15 36 | ||
| 49 | #define IRQ_GPIO16 37 | ||
| 50 | #define IRQ_GPIO17 38 | ||
| 51 | #define IRQ_GPIO18 39 | ||
| 52 | #define IRQ_GPIO19 40 | ||
| 53 | #define IRQ_GPIO20 41 | ||
| 54 | #define IRQ_GPIO21 42 | ||
| 55 | #define IRQ_GPIO22 43 | ||
| 56 | #define IRQ_GPIO23 44 | ||
| 57 | #define IRQ_GPIO24 45 | ||
| 58 | #define IRQ_GPIO25 46 | ||
| 59 | #define IRQ_GPIO26 47 | ||
| 60 | #define IRQ_GPIO27 48 | ||
| 61 | |||
| 62 | /* | ||
| 63 | * The next 16 interrupts are for board specific purposes. Since | ||
| 64 | * the kernel can only run on one machine at a time, we can re-use | ||
| 65 | * these. If you need more, increase IRQ_BOARD_END, but keep it | ||
| 66 | * within sensible limits. IRQs 49 to 64 are available. | ||
| 67 | */ | ||
| 68 | #define IRQ_BOARD_START 49 | ||
| 69 | #define IRQ_BOARD_END 65 | ||
| 70 | |||
| 71 | #define IRQ_SA1111_START (IRQ_BOARD_END) | ||
| 72 | #define IRQ_GPAIN0 (IRQ_BOARD_END + 0) | ||
| 73 | #define IRQ_GPAIN1 (IRQ_BOARD_END + 1) | ||
| 74 | #define IRQ_GPAIN2 (IRQ_BOARD_END + 2) | ||
| 75 | #define IRQ_GPAIN3 (IRQ_BOARD_END + 3) | ||
| 76 | #define IRQ_GPBIN0 (IRQ_BOARD_END + 4) | ||
| 77 | #define IRQ_GPBIN1 (IRQ_BOARD_END + 5) | ||
| 78 | #define IRQ_GPBIN2 (IRQ_BOARD_END + 6) | ||
| 79 | #define IRQ_GPBIN3 (IRQ_BOARD_END + 7) | ||
| 80 | #define IRQ_GPBIN4 (IRQ_BOARD_END + 8) | ||
| 81 | #define IRQ_GPBIN5 (IRQ_BOARD_END + 9) | ||
| 82 | #define IRQ_GPCIN0 (IRQ_BOARD_END + 10) | ||
| 83 | #define IRQ_GPCIN1 (IRQ_BOARD_END + 11) | ||
| 84 | #define IRQ_GPCIN2 (IRQ_BOARD_END + 12) | ||
| 85 | #define IRQ_GPCIN3 (IRQ_BOARD_END + 13) | ||
| 86 | #define IRQ_GPCIN4 (IRQ_BOARD_END + 14) | ||
| 87 | #define IRQ_GPCIN5 (IRQ_BOARD_END + 15) | ||
| 88 | #define IRQ_GPCIN6 (IRQ_BOARD_END + 16) | ||
| 89 | #define IRQ_GPCIN7 (IRQ_BOARD_END + 17) | ||
| 90 | #define IRQ_MSTXINT (IRQ_BOARD_END + 18) | ||
| 91 | #define IRQ_MSRXINT (IRQ_BOARD_END + 19) | ||
| 92 | #define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20) | ||
| 93 | #define IRQ_TPTXINT (IRQ_BOARD_END + 21) | ||
| 94 | #define IRQ_TPRXINT (IRQ_BOARD_END + 22) | ||
| 95 | #define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23) | ||
| 96 | #define SSPXMTINT (IRQ_BOARD_END + 24) | ||
| 97 | #define SSPRCVINT (IRQ_BOARD_END + 25) | ||
| 98 | #define SSPROR (IRQ_BOARD_END + 26) | ||
| 99 | #define AUDXMTDMADONEA (IRQ_BOARD_END + 32) | ||
| 100 | #define AUDRCVDMADONEA (IRQ_BOARD_END + 33) | ||
| 101 | #define AUDXMTDMADONEB (IRQ_BOARD_END + 34) | ||
| 102 | #define AUDRCVDMADONEB (IRQ_BOARD_END + 35) | ||
| 103 | #define AUDTFSR (IRQ_BOARD_END + 36) | ||
| 104 | #define AUDRFSR (IRQ_BOARD_END + 37) | ||
| 105 | #define AUDTUR (IRQ_BOARD_END + 38) | ||
| 106 | #define AUDROR (IRQ_BOARD_END + 39) | ||
| 107 | #define AUDDTS (IRQ_BOARD_END + 40) | ||
| 108 | #define AUDRDD (IRQ_BOARD_END + 41) | ||
| 109 | #define AUDSTO (IRQ_BOARD_END + 42) | ||
| 110 | #define IRQ_USBPWR (IRQ_BOARD_END + 43) | ||
| 111 | #define IRQ_HCIM (IRQ_BOARD_END + 44) | ||
| 112 | #define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45) | ||
| 113 | #define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46) | ||
| 114 | #define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47) | ||
| 115 | #define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48) | ||
| 116 | #define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49) | ||
| 117 | #define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50) | ||
| 118 | #define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51) | ||
| 119 | #define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52) | ||
| 120 | #define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53) | ||
| 121 | #define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) | ||
| 122 | |||
| 123 | #define IRQ_LOCOMO_START (IRQ_BOARD_END) | ||
| 124 | #define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) | ||
| 125 | #define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) | ||
| 126 | #define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) | ||
| 127 | #define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) | ||
| 128 | #define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4) | ||
| 129 | #define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5) | ||
| 130 | #define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6) | ||
| 131 | #define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7) | ||
| 132 | #define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8) | ||
| 133 | #define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9) | ||
| 134 | #define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10) | ||
| 135 | #define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11) | ||
| 136 | #define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12) | ||
| 137 | #define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13) | ||
| 138 | #define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14) | ||
| 139 | #define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15) | ||
| 140 | #define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16) | ||
| 141 | #define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17) | ||
| 142 | #define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18) | ||
| 143 | #define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19) | ||
| 144 | #define IRQ_LOCOMO_SPI_REND (IRQ_BOARD_END + 20) | ||
| 145 | #define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21) | ||
| 146 | |||
| 147 | /* | ||
| 148 | * Figure out the MAX IRQ number. | ||
| 149 | * | ||
| 150 | * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. | ||
| 151 | * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1 | ||
| 152 | * Otherwise, we have the standard IRQs only. | ||
| 153 | */ | ||
| 154 | #ifdef CONFIG_SA1111 | ||
| 155 | #define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) | ||
| 156 | #elif defined(CONFIG_SA1100_H3800) | ||
| 157 | #define NR_IRQS (IRQ_BOARD_END) | ||
| 158 | #elif defined(CONFIG_SHARP_LOCOMO) | ||
| 159 | #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) | ||
| 160 | #else | ||
| 161 | #define NR_IRQS (IRQ_BOARD_START) | ||
| 162 | #endif | ||
| 163 | |||
| 164 | /* | ||
| 165 | * Board specific IRQs. Define them here. | ||
| 166 | * Do not surround them with ifdefs. | ||
| 167 | */ | ||
| 168 | #define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0) | ||
| 169 | #define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1) | ||
| 170 | #define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2) | ||
| 171 | |||
| 172 | /* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ | ||
| 173 | #define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) | ||
| 174 | #define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) | ||
| 175 | #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) | ||
| 176 | #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) | ||
| 177 | |||
| 178 | /* H3800-specific IRQs (CONFIG_SA1100_H3800) */ | ||
| 179 | #define H3800_KPIO_IRQ_START (IRQ_BOARD_START) | ||
| 180 | #define IRQ_H3800_KEY (IRQ_BOARD_START + 0) | ||
| 181 | #define IRQ_H3800_SPI (IRQ_BOARD_START + 1) | ||
| 182 | #define IRQ_H3800_OWM (IRQ_BOARD_START + 2) | ||
| 183 | #define IRQ_H3800_ADC (IRQ_BOARD_START + 3) | ||
| 184 | #define IRQ_H3800_UART_0 (IRQ_BOARD_START + 4) | ||
| 185 | #define IRQ_H3800_UART_1 (IRQ_BOARD_START + 5) | ||
| 186 | #define IRQ_H3800_TIMER_0 (IRQ_BOARD_START + 6) | ||
| 187 | #define IRQ_H3800_TIMER_1 (IRQ_BOARD_START + 7) | ||
| 188 | #define IRQ_H3800_TIMER_2 (IRQ_BOARD_START + 8) | ||
| 189 | #define H3800_KPIO_IRQ_COUNT 9 | ||
| 190 | |||
| 191 | #define H3800_GPIO_IRQ_START (IRQ_BOARD_START + 9) | ||
| 192 | #define IRQ_H3800_PEN (IRQ_BOARD_START + 9) | ||
| 193 | #define IRQ_H3800_SD_DETECT (IRQ_BOARD_START + 10) | ||
| 194 | #define IRQ_H3800_EAR_IN (IRQ_BOARD_START + 11) | ||
| 195 | #define IRQ_H3800_USB_DETECT (IRQ_BOARD_START + 12) | ||
| 196 | #define IRQ_H3800_SD_CON_SLT (IRQ_BOARD_START + 13) | ||
| 197 | #define H3800_GPIO_IRQ_COUNT 5 | ||
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h deleted file mode 100644 index 45d2bb59f9d0..000000000000 --- a/include/asm-arm/arch-sa1100/jornada720.h +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-sa1100/jornada720.h | ||
| 3 | * | ||
| 4 | * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728 | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> | ||
| 7 | * Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* HP Jornada 7xx microprocessor commands */ | ||
| 16 | #define GETBATTERYDATA 0xc0 | ||
| 17 | #define GETSCANKEYCODE 0x90 | ||
| 18 | #define GETTOUCHSAMPLES 0xa0 | ||
| 19 | #define GETCONTRAST 0xD0 | ||
| 20 | #define SETCONTRAST 0xD1 | ||
| 21 | #define GETBRIGHTNESS 0xD2 | ||
| 22 | #define SETBRIGHTNESS 0xD3 | ||
| 23 | #define CONTRASTOFF 0xD8 | ||
| 24 | #define BRIGHTNESSOFF 0xD9 | ||
| 25 | #define PWMOFF 0xDF | ||
| 26 | #define TXDUMMY 0x11 | ||
| 27 | #define ERRORCODE 0x00 | ||
diff --git a/include/asm-arm/arch-sa1100/lart.h b/include/asm-arm/arch-sa1100/lart.h deleted file mode 100644 index 8a5482d908db..000000000000 --- a/include/asm-arm/arch-sa1100/lart.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | #ifndef _INCLUDE_LART_H | ||
| 2 | #define _INCLUDE_LART_H | ||
| 3 | |||
| 4 | #define LART_GPIO_ETH0 GPIO_GPIO0 | ||
| 5 | #define LART_IRQ_ETH0 IRQ_GPIO0 | ||
| 6 | |||
| 7 | #define LART_GPIO_IDE GPIO_GPIO1 | ||
| 8 | #define LART_IRQ_IDE IRQ_GPIO1 | ||
| 9 | |||
| 10 | #define LART_GPIO_UCB1200 GPIO_GPIO18 | ||
| 11 | #define LART_IRQ_UCB1200 IRQ_GPIO18 | ||
| 12 | |||
| 13 | #endif | ||
diff --git a/include/asm-arm/arch-sa1100/mcp.h b/include/asm-arm/arch-sa1100/mcp.h deleted file mode 100644 index f58a22755c61..000000000000 --- a/include/asm-arm/arch-sa1100/mcp.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/mcp.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARM_ARCH_MCP_H | ||
| 11 | #define __ASM_ARM_ARCH_MCP_H | ||
| 12 | |||
| 13 | #include <linux/types.h> | ||
| 14 | |||
| 15 | struct mcp_plat_data { | ||
| 16 | u32 mccr0; | ||
| 17 | u32 mccr1; | ||
| 18 | unsigned int sclk_rate; | ||
| 19 | }; | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h deleted file mode 100644 index 0e907fc6d42a..000000000000 --- a/include/asm-arm/arch-sa1100/memory.h +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999-2000 Nicolas Pitre <nico@cam.org> | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 8 | #define __ASM_ARCH_MEMORY_H | ||
| 9 | |||
| 10 | #include <asm/sizes.h> | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Physical DRAM offset is 0xc0000000 on the SA1100 | ||
| 14 | */ | ||
| 15 | #define PHYS_OFFSET UL(0xc0000000) | ||
| 16 | |||
| 17 | #ifndef __ASSEMBLY__ | ||
| 18 | |||
| 19 | #ifdef CONFIG_SA1111 | ||
| 20 | void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); | ||
| 21 | |||
| 22 | #define arch_adjust_zones(node, size, holes) \ | ||
| 23 | sa1111_adjust_zones(node, size, holes) | ||
| 24 | |||
| 25 | #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) | ||
| 26 | |||
| 27 | #endif | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* | ||
| 31 | * Virtual view <-> DMA view memory address translations | ||
| 32 | * virt_to_bus: Used to translate the virtual address to an | ||
| 33 | * address suitable to be passed to set_dma_addr | ||
| 34 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 35 | * to an address that the kernel can use. | ||
| 36 | * | ||
| 37 | * On the SA1100, bus addresses are equivalent to physical addresses. | ||
| 38 | */ | ||
| 39 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 40 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Because of the wide memory address space between physical RAM banks on the | ||
| 44 | * SA1100, it's much convenient to use Linux's NUMA support to implement our | ||
| 45 | * memory map representation. Assuming all memory nodes have equal access | ||
| 46 | * characteristics, we then have generic discontiguous memory support. | ||
| 47 | * | ||
| 48 | * Of course, all this isn't mandatory for SA1100 implementations with only | ||
| 49 | * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. | ||
| 50 | * | ||
| 51 | * The nodes are matched with the physical memory bank addresses which are | ||
| 52 | * incidentally the same as virtual addresses. | ||
| 53 | * | ||
| 54 | * node 0: 0xc0000000 - 0xc7ffffff | ||
| 55 | * node 1: 0xc8000000 - 0xcfffffff | ||
| 56 | * node 2: 0xd0000000 - 0xd7ffffff | ||
| 57 | * node 3: 0xd8000000 - 0xdfffffff | ||
| 58 | */ | ||
| 59 | #define NODE_MEM_SIZE_BITS 27 | ||
| 60 | |||
| 61 | /* | ||
| 62 | * Cache flushing area - SA1100 zero bank | ||
| 63 | */ | ||
| 64 | #define FLUSH_BASE_PHYS 0xe0000000 | ||
| 65 | #define FLUSH_BASE 0xf5000000 | ||
| 66 | #define FLUSH_BASE_MINICACHE 0xf5100000 | ||
| 67 | |||
| 68 | #endif | ||
diff --git a/include/asm-arm/arch-sa1100/mtd-xip.h b/include/asm-arm/arch-sa1100/mtd-xip.h deleted file mode 100644 index 80cfdac2b944..000000000000 --- a/include/asm-arm/arch-sa1100/mtd-xip.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * MTD primitives for XIP support. Architecture specific functions | ||
| 3 | * | ||
| 4 | * Do not include this file directly. It's included from linux/mtd/xip.h | ||
| 5 | * | ||
| 6 | * Author: Nicolas Pitre | ||
| 7 | * Created: Nov 2, 2004 | ||
| 8 | * Copyright: (C) 2004 MontaVista Software, Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $ | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ARCH_SA1100_MTD_XIP_H__ | ||
| 18 | #define __ARCH_SA1100_MTD_XIP_H__ | ||
| 19 | |||
| 20 | #define xip_irqpending() (ICIP & ICMR) | ||
| 21 | |||
| 22 | /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ | ||
| 23 | #define xip_currtime() (OSCR) | ||
| 24 | #define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4) | ||
| 25 | |||
| 26 | #endif /* __ARCH_SA1100_MTD_XIP_H__ */ | ||
diff --git a/include/asm-arm/arch-sa1100/neponset.h b/include/asm-arm/arch-sa1100/neponset.h deleted file mode 100644 index 09ec9e2bd182..000000000000 --- a/include/asm-arm/arch-sa1100/neponset.h +++ /dev/null | |||
| @@ -1,74 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/neponset.h | ||
| 3 | * | ||
| 4 | * Created 2000/06/05 by Nicolas Pitre <nico@cam.org> | ||
| 5 | * | ||
| 6 | * This file contains the hardware specific definitions for Assabet | ||
| 7 | * Only include this file from SA1100-specific files. | ||
| 8 | * | ||
| 9 | * 2000/05/23 John Dorsey <john+@cs.cmu.edu> | ||
| 10 | * Definitions for Neponset added. | ||
| 11 | */ | ||
| 12 | #ifndef __ASM_ARCH_NEPONSET_H | ||
| 13 | #define __ASM_ARCH_NEPONSET_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Neponset definitions: | ||
| 17 | */ | ||
| 18 | |||
| 19 | #define NEPONSET_CPLD_BASE (0x10000000) | ||
| 20 | #define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000) | ||
| 21 | #define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE) | ||
| 22 | |||
| 23 | #define _IRR 0x10000024 /* Interrupt Reason Register */ | ||
| 24 | #define _AUD_CTL 0x100000c0 /* Audio controls (RW) */ | ||
| 25 | #define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */ | ||
| 26 | #define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */ | ||
| 27 | #define _NCR_0 0x100000a0 /* Control Register (RW) */ | ||
| 28 | #define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */ | ||
| 29 | #define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */ | ||
| 30 | #define _SWPK 0x10000020 /* Switch pack (RO) */ | ||
| 31 | #define _WHOAMI 0x10000000 /* System ID Register (RO) */ | ||
| 32 | |||
| 33 | #define _LEDS 0x10000010 /* LEDs [31:0] (WO) */ | ||
| 34 | |||
| 35 | #define IRR (*((volatile u_char *) Nep_p2v(_IRR))) | ||
| 36 | #define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL))) | ||
| 37 | #define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0))) | ||
| 38 | #define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1))) | ||
| 39 | #define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0))) | ||
| 40 | #define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT))) | ||
| 41 | #define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN))) | ||
| 42 | #define SWPK (*((volatile u_char *) Nep_p2v(_SWPK))) | ||
| 43 | #define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI))) | ||
| 44 | |||
| 45 | #define LEDS (*((volatile Word *) Nep_p2v(_LEDS))) | ||
| 46 | |||
| 47 | #define IRR_ETHERNET (1<<0) | ||
| 48 | #define IRR_USAR (1<<1) | ||
| 49 | #define IRR_SA1111 (1<<2) | ||
| 50 | |||
| 51 | #define AUD_SEL_1341 (1<<0) | ||
| 52 | #define AUD_MUTE_1341 (1<<1) | ||
| 53 | |||
| 54 | #define MDM_CTL0_RTS1 (1 << 0) | ||
| 55 | #define MDM_CTL0_DTR1 (1 << 1) | ||
| 56 | #define MDM_CTL0_RTS2 (1 << 2) | ||
| 57 | #define MDM_CTL0_DTR2 (1 << 3) | ||
| 58 | |||
| 59 | #define MDM_CTL1_CTS1 (1 << 0) | ||
| 60 | #define MDM_CTL1_DSR1 (1 << 1) | ||
| 61 | #define MDM_CTL1_DCD1 (1 << 2) | ||
| 62 | #define MDM_CTL1_CTS2 (1 << 3) | ||
| 63 | #define MDM_CTL1_DSR2 (1 << 4) | ||
| 64 | #define MDM_CTL1_DCD2 (1 << 5) | ||
| 65 | |||
| 66 | #define NCR_GP01_OFF (1<<0) | ||
| 67 | #define NCR_TP_PWR_EN (1<<1) | ||
| 68 | #define NCR_MS_PWR_EN (1<<2) | ||
| 69 | #define NCR_ENET_OSC_EN (1<<3) | ||
| 70 | #define NCR_SPI_KB_WK_UP (1<<4) | ||
| 71 | #define NCR_A0VPP (1<<5) | ||
| 72 | #define NCR_A1VPP (1<<6) | ||
| 73 | |||
| 74 | #endif | ||
diff --git a/include/asm-arm/arch-sa1100/shannon.h b/include/asm-arm/arch-sa1100/shannon.h deleted file mode 100644 index ec27d6e12140..000000000000 --- a/include/asm-arm/arch-sa1100/shannon.h +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | #ifndef _INCLUDE_SHANNON_H | ||
| 2 | #define _INCLUDE_SHANNON_H | ||
| 3 | |||
| 4 | /* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT, | ||
| 5 | * written by <forsyth@vitanuova.com> */ | ||
| 6 | |||
| 7 | #define SHANNON_GPIO_SPI_FLASH GPIO_GPIO (0) /* Output - Driven low, enables SPI to flash */ | ||
| 8 | #define SHANNON_GPIO_SPI_DSP GPIO_GPIO (1) /* Output - Driven low, enables SPI to DSP */ | ||
| 9 | /* lcd lower = GPIO 2-9 */ | ||
| 10 | #define SHANNON_GPIO_SPI_OUTPUT GPIO_GPIO (10) /* Output - SPI output to DSP */ | ||
| 11 | #define SHANNON_GPIO_SPI_INPUT GPIO_GPIO (11) /* Input - SPI input from DSP */ | ||
| 12 | #define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */ | ||
| 13 | #define SHANNON_GPIO_SPI_FRAME GPIO_GPIO (13) /* Output - Frame marker - not used */ | ||
| 14 | #define SHANNON_GPIO_SPI_RTS GPIO_GPIO (14) /* Input - SPI Ready to Send */ | ||
| 15 | #define SHANNON_IRQ_GPIO_SPI_RTS IRQ_GPIO14 | ||
| 16 | #define SHANNON_GPIO_SPI_CTS GPIO_GPIO (15) /* Output - SPI Clear to Send */ | ||
| 17 | #define SHANNON_GPIO_IRQ_CODEC GPIO_GPIO (16) /* in, irq from ucb1200 */ | ||
| 18 | #define SHANNON_IRQ_GPIO_IRQ_CODEC IRQ_GPIO16 | ||
| 19 | #define SHANNON_GPIO_DSP_RESET GPIO_GPIO (17) /* Output - Drive low to reset the DSP */ | ||
| 20 | #define SHANNON_GPIO_CODEC_RESET GPIO_GPIO (18) /* Output - Drive low to reset the UCB1x00 */ | ||
| 21 | #define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ | ||
| 22 | #define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ | ||
| 23 | #define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ | ||
| 24 | #define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */ | ||
| 25 | /* XXX GPIO 23 unaccounted for */ | ||
| 26 | #define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */ | ||
| 27 | #define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24 | ||
| 28 | #define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */ | ||
| 29 | #define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25 | ||
| 30 | #define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */ | ||
| 31 | #define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26 | ||
| 32 | #define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */ | ||
| 33 | #define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27 | ||
| 34 | |||
| 35 | /* MCP UCB codec GPIO pins... */ | ||
| 36 | |||
| 37 | #define SHANNON_UCB_GPIO_BACKLIGHT 9 | ||
| 38 | #define SHANNON_UCB_GPIO_BRIGHT_MASK 7 | ||
| 39 | #define SHANNON_UCB_GPIO_BRIGHT 6 | ||
| 40 | #define SHANNON_UCB_GPIO_CONTRAST_MASK 0x3f | ||
| 41 | #define SHANNON_UCB_GPIO_CONTRAST 0 | ||
| 42 | |||
| 43 | #endif | ||
diff --git a/include/asm-arm/arch-sa1100/simpad.h b/include/asm-arm/arch-sa1100/simpad.h deleted file mode 100644 index 034301d23f60..000000000000 --- a/include/asm-arm/arch-sa1100/simpad.h +++ /dev/null | |||
| @@ -1,112 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/simpad.h | ||
| 3 | * | ||
| 4 | * based of assabet.h same as HUW_Webpanel | ||
| 5 | * | ||
| 6 | * This file contains the hardware specific definitions for SIMpad | ||
| 7 | * | ||
| 8 | * 2001/05/14 Juergen Messerer <juergen.messerer@freesurf.ch> | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_SIMPAD_H | ||
| 12 | #define __ASM_ARCH_SIMPAD_H | ||
| 13 | |||
| 14 | |||
| 15 | #define GPIO_UART1_RTS GPIO_GPIO14 | ||
| 16 | #define GPIO_UART1_DTR GPIO_GPIO7 | ||
| 17 | #define GPIO_UART1_CTS GPIO_GPIO8 | ||
| 18 | #define GPIO_UART1_DCD GPIO_GPIO23 | ||
| 19 | #define GPIO_UART1_DSR GPIO_GPIO6 | ||
| 20 | |||
| 21 | #define GPIO_UART3_RTS GPIO_GPIO12 | ||
| 22 | #define GPIO_UART3_DTR GPIO_GPIO16 | ||
| 23 | #define GPIO_UART3_CTS GPIO_GPIO13 | ||
| 24 | #define GPIO_UART3_DCD GPIO_GPIO18 | ||
| 25 | #define GPIO_UART3_DSR GPIO_GPIO17 | ||
| 26 | |||
| 27 | #define GPIO_POWER_BUTTON GPIO_GPIO0 | ||
| 28 | #define GPIO_UCB1300_IRQ GPIO_GPIO22 /* UCB GPIO and touchscreen */ | ||
| 29 | |||
| 30 | #define IRQ_UART1_CTS IRQ_GPIO15 | ||
| 31 | #define IRQ_UART1_DCD GPIO_GPIO23 | ||
| 32 | #define IRQ_UART1_DSR GPIO_GPIO6 | ||
| 33 | #define IRQ_UART3_CTS GPIO_GPIO13 | ||
| 34 | #define IRQ_UART3_DCD GPIO_GPIO18 | ||
| 35 | #define IRQ_UART3_DSR GPIO_GPIO17 | ||
| 36 | |||
| 37 | #define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22 | ||
| 38 | #define IRQ_GPIO_POWER_BUTTON IRQ_GPIO0 | ||
| 39 | |||
| 40 | |||
| 41 | /*--- PCMCIA ---*/ | ||
| 42 | #define GPIO_CF_CD GPIO_GPIO24 | ||
| 43 | #define GPIO_CF_IRQ GPIO_GPIO1 | ||
| 44 | #define IRQ_GPIO_CF_IRQ IRQ_GPIO1 | ||
| 45 | #define IRQ_GPIO_CF_CD IRQ_GPIO24 | ||
| 46 | |||
| 47 | /*--- SmartCard ---*/ | ||
| 48 | #define GPIO_SMART_CARD GPIO_GPIO10 | ||
| 49 | #define IRQ_GPIO_SMARD_CARD IRQ_GPIO10 | ||
| 50 | |||
| 51 | // CS3 Latch is write only, a shadow is necessary | ||
| 52 | |||
| 53 | #define CS3BUSTYPE unsigned volatile long | ||
| 54 | #define CS3_BASE 0xf1000000 | ||
| 55 | |||
| 56 | #define VCC_5V_EN 0x0001 // For 5V PCMCIA | ||
| 57 | #define VCC_3V_EN 0x0002 // FOR 3.3V PCMCIA | ||
| 58 | #define EN1 0x0004 // This is only for EPROM's | ||
| 59 | #define EN0 0x0008 // Both should be enable for 3.3V or 5V | ||
| 60 | #define DISPLAY_ON 0x0010 | ||
| 61 | #define PCMCIA_BUFF_DIS 0x0020 | ||
| 62 | #define MQ_RESET 0x0040 | ||
| 63 | #define PCMCIA_RESET 0x0080 | ||
| 64 | #define DECT_POWER_ON 0x0100 | ||
| 65 | #define IRDA_SD 0x0200 // Shutdown for powersave | ||
| 66 | #define RS232_ON 0x0400 | ||
| 67 | #define SD_MEDIAQ 0x0800 // Shutdown for powersave | ||
| 68 | #define LED2_ON 0x1000 | ||
| 69 | #define IRDA_MODE 0x2000 // Fast/Slow IrDA mode | ||
| 70 | #define ENABLE_5V 0x4000 // Enable 5V circuit | ||
| 71 | #define RESET_SIMCARD 0x8000 | ||
| 72 | |||
| 73 | #define RS232_ENABLE 0x0440 | ||
| 74 | #define PCMCIAMASK 0x402f | ||
| 75 | |||
| 76 | |||
| 77 | struct simpad_battery { | ||
| 78 | unsigned char ac_status; /* line connected yes/no */ | ||
| 79 | unsigned char status; /* battery loading yes/no */ | ||
| 80 | unsigned char percentage; /* percentage loaded */ | ||
| 81 | unsigned short life; /* life till empty */ | ||
| 82 | }; | ||
| 83 | |||
| 84 | /* These should match the apm_bios.h definitions */ | ||
| 85 | #define SIMPAD_AC_STATUS_AC_OFFLINE 0x00 | ||
| 86 | #define SIMPAD_AC_STATUS_AC_ONLINE 0x01 | ||
| 87 | #define SIMPAD_AC_STATUS_AC_BACKUP 0x02 /* What does this mean? */ | ||
| 88 | #define SIMPAD_AC_STATUS_AC_UNKNOWN 0xff | ||
| 89 | |||
| 90 | /* These bitfields are rarely "or'd" together */ | ||
| 91 | #define SIMPAD_BATT_STATUS_HIGH 0x01 | ||
| 92 | #define SIMPAD_BATT_STATUS_LOW 0x02 | ||
| 93 | #define SIMPAD_BATT_STATUS_CRITICAL 0x04 | ||
| 94 | #define SIMPAD_BATT_STATUS_CHARGING 0x08 | ||
| 95 | #define SIMPAD_BATT_STATUS_CHARGE_MAIN 0x10 | ||
| 96 | #define SIMPAD_BATT_STATUS_DEAD 0x20 /* Battery will not charge */ | ||
| 97 | #define SIMPAD_BATT_NOT_INSTALLED 0x20 /* For expansion pack batteries */ | ||
| 98 | #define SIMPAD_BATT_STATUS_FULL 0x40 /* Battery fully charged (and connected to AC) */ | ||
| 99 | #define SIMPAD_BATT_STATUS_NOBATT 0x80 | ||
| 100 | #define SIMPAD_BATT_STATUS_UNKNOWN 0xff | ||
| 101 | |||
| 102 | extern int simpad_get_battery(struct simpad_battery* ); | ||
| 103 | |||
| 104 | #endif // __ASM_ARCH_SIMPAD_H | ||
| 105 | |||
| 106 | |||
| 107 | |||
| 108 | |||
| 109 | |||
| 110 | |||
| 111 | |||
| 112 | |||
diff --git a/include/asm-arm/arch-sa1100/system.h b/include/asm-arm/arch-sa1100/system.h deleted file mode 100644 index 63375a0c0145..000000000000 --- a/include/asm-arm/arch-sa1100/system.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/system.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 1999 Nicolas Pitre <nico@cam.org> | ||
| 5 | */ | ||
| 6 | #include <asm/arch/hardware.h> | ||
| 7 | |||
| 8 | static inline void arch_idle(void) | ||
| 9 | { | ||
| 10 | cpu_do_idle(); | ||
| 11 | } | ||
| 12 | |||
| 13 | static inline void arch_reset(char mode) | ||
| 14 | { | ||
| 15 | if (mode == 's') { | ||
| 16 | /* Jump into ROM at address 0 */ | ||
| 17 | cpu_reset(0); | ||
| 18 | } else { | ||
| 19 | /* Use on-chip reset capability */ | ||
| 20 | RSRR = RSRR_SWR; | ||
| 21 | } | ||
| 22 | } | ||
diff --git a/include/asm-arm/arch-sa1100/timex.h b/include/asm-arm/arch-sa1100/timex.h deleted file mode 100644 index 837be9b797dd..000000000000 --- a/include/asm-arm/arch-sa1100/timex.h +++ /dev/null | |||
| @@ -1,12 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/timex.h | ||
| 3 | * | ||
| 4 | * SA1100 architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 1998 | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* | ||
| 10 | * SA1100 timer | ||
| 11 | */ | ||
| 12 | #define CLOCK_TICK_RATE 3686400 | ||
diff --git a/include/asm-arm/arch-sa1100/uncompress.h b/include/asm-arm/arch-sa1100/uncompress.h deleted file mode 100644 index 17e64d232e7d..000000000000 --- a/include/asm-arm/arch-sa1100/uncompress.h +++ /dev/null | |||
| @@ -1,50 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/uncompress.h | ||
| 3 | * | ||
| 4 | * (C) 1999 Nicolas Pitre <nico@cam.org> | ||
| 5 | * | ||
| 6 | * Reorganised to be machine independent. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include "hardware.h" | ||
| 10 | |||
| 11 | /* | ||
| 12 | * The following code assumes the serial port has already been | ||
| 13 | * initialized by the bootloader. We search for the first enabled | ||
| 14 | * port in the most probable order. If you didn't setup a port in | ||
| 15 | * your bootloader then nothing will appear (which might be desired). | ||
| 16 | */ | ||
| 17 | |||
| 18 | #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) | ||
| 19 | |||
| 20 | static void putc(int c) | ||
| 21 | { | ||
| 22 | unsigned long serial_port; | ||
| 23 | |||
| 24 | do { | ||
| 25 | serial_port = _Ser3UTCR0; | ||
| 26 | if (UART(UTCR3) & UTCR3_TXE) break; | ||
| 27 | serial_port = _Ser1UTCR0; | ||
| 28 | if (UART(UTCR3) & UTCR3_TXE) break; | ||
| 29 | serial_port = _Ser2UTCR0; | ||
| 30 | if (UART(UTCR3) & UTCR3_TXE) break; | ||
| 31 | return; | ||
| 32 | } while (0); | ||
| 33 | |||
| 34 | /* wait for space in the UART's transmitter */ | ||
| 35 | while (!(UART(UTSR1) & UTSR1_TNF)) | ||
| 36 | barrier(); | ||
| 37 | |||
| 38 | /* send the character out. */ | ||
| 39 | UART(UTDR) = c; | ||
| 40 | } | ||
| 41 | |||
| 42 | static inline void flush(void) | ||
| 43 | { | ||
| 44 | } | ||
| 45 | |||
| 46 | /* | ||
| 47 | * Nothing to do for these | ||
| 48 | */ | ||
| 49 | #define arch_decomp_setup() | ||
| 50 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-sa1100/vmalloc.h b/include/asm-arm/arch-sa1100/vmalloc.h deleted file mode 100644 index 2fb1c6f3aa1b..000000000000 --- a/include/asm-arm/arch-sa1100/vmalloc.h +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-sa1100/vmalloc.h | ||
| 3 | */ | ||
| 4 | #define VMALLOC_END (0xe8000000) | ||
diff --git a/include/asm-arm/arch-shark/debug-macro.S b/include/asm-arm/arch-shark/debug-macro.S deleted file mode 100644 index 7cb37f78825e..000000000000 --- a/include/asm-arm/arch-shark/debug-macro.S +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-shark/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mov \rx, #0xe0000000 | ||
| 16 | orr \rx, \rx, #0x000003f8 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro senduart,rd,rx | ||
| 20 | strb \rd, [\rx] | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro busyuart,rd,rx | ||
| 24 | mov \rd, #0 | ||
| 25 | 1001: add \rd, \rd, #1 | ||
| 26 | teq \rd, #0x10000 | ||
| 27 | bne 1001b | ||
| 28 | .endm | ||
| 29 | |||
| 30 | .macro waituart,rd,rx | ||
| 31 | .endm | ||
diff --git a/include/asm-arm/arch-shark/dma.h b/include/asm-arm/arch-shark/dma.h deleted file mode 100644 index fc985d5e62af..000000000000 --- a/include/asm-arm/arch-shark/dma.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-shark/dma.h | ||
| 3 | * | ||
| 4 | * by Alexander Schulz | ||
| 5 | */ | ||
| 6 | #ifndef __ASM_ARCH_DMA_H | ||
| 7 | #define __ASM_ARCH_DMA_H | ||
| 8 | |||
| 9 | /* Use only the lowest 4MB, nothing else works. | ||
| 10 | * The rest is not DMAable. See dev / .properties | ||
| 11 | * in OpenFirmware. | ||
| 12 | */ | ||
| 13 | #define MAX_DMA_ADDRESS 0xC0400000 | ||
| 14 | #define MAX_DMA_CHANNELS 8 | ||
| 15 | #define DMA_ISA_CASCADE 4 | ||
| 16 | |||
| 17 | #endif /* _ASM_ARCH_DMA_H */ | ||
| 18 | |||
diff --git a/include/asm-arm/arch-shark/entry-macro.S b/include/asm-arm/arch-shark/entry-macro.S deleted file mode 100644 index 82463f30f3df..000000000000 --- a/include/asm-arm/arch-shark/entry-macro.S +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-shark/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for Shark platform | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | .macro disable_fiq | ||
| 11 | .endm | ||
| 12 | |||
| 13 | .macro get_irqnr_preamble, base, tmp | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 20 | mov r4, #0xe0000000 | ||
| 21 | |||
| 22 | mov \irqstat, #0x0C | ||
| 23 | strb \irqstat, [r4, #0x20] @outb(0x0C, 0x20) /* Poll command */ | ||
| 24 | ldrb \irqnr, [r4, #0x20] @irq = inb(0x20) & 7 | ||
| 25 | and \irqstat, \irqnr, #0x80 | ||
| 26 | teq \irqstat, #0 | ||
| 27 | beq 43f | ||
| 28 | and \irqnr, \irqnr, #7 | ||
| 29 | teq \irqnr, #2 | ||
| 30 | bne 44f | ||
| 31 | 43: mov \irqstat, #0x0C | ||
| 32 | strb \irqstat, [r4, #0xa0] @outb(0x0C, 0xA0) /* Poll command */ | ||
| 33 | ldrb \irqnr, [r4, #0xa0] @irq = (inb(0xA0) & 7) + 8 | ||
| 34 | and \irqstat, \irqnr, #0x80 | ||
| 35 | teq \irqstat, #0 | ||
| 36 | beq 44f | ||
| 37 | and \irqnr, \irqnr, #7 | ||
| 38 | add \irqnr, \irqnr, #8 | ||
| 39 | 44: teq \irqstat, #0 | ||
| 40 | .endm | ||
| 41 | |||
diff --git a/include/asm-arm/arch-shark/hardware.h b/include/asm-arm/arch-shark/hardware.h deleted file mode 100644 index ecba45260898..000000000000 --- a/include/asm-arm/arch-shark/hardware.h +++ /dev/null | |||
| @@ -1,51 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-shark/hardware.h | ||
| 3 | * | ||
| 4 | * by Alexander Schulz | ||
| 5 | * | ||
| 6 | * derived from: | ||
| 7 | * linux/include/asm-arm/arch-ebsa110/hardware.h | ||
| 8 | * Copyright (C) 1996-1999 Russell King. | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 11 | #define __ASM_ARCH_HARDWARE_H | ||
| 12 | |||
| 13 | #ifndef __ASSEMBLY__ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Mapping areas | ||
| 17 | */ | ||
| 18 | #define IO_BASE 0xe0000000 | ||
| 19 | |||
| 20 | #else | ||
| 21 | |||
| 22 | #define IO_BASE 0 | ||
| 23 | |||
| 24 | #endif | ||
| 25 | |||
| 26 | #define IO_SIZE 0x08000000 | ||
| 27 | #define IO_START 0x40000000 | ||
| 28 | #define ROMCARD_SIZE 0x08000000 | ||
| 29 | #define ROMCARD_START 0x10000000 | ||
| 30 | |||
| 31 | #define PCIO_BASE 0xe0000000 | ||
| 32 | |||
| 33 | |||
| 34 | /* defines for the Framebuffer */ | ||
| 35 | #define FB_START 0x06000000 | ||
| 36 | #define FB_SIZE 0x01000000 | ||
| 37 | |||
| 38 | #define UNCACHEABLE_ADDR 0xdf010000 | ||
| 39 | |||
| 40 | #define SEQUOIA_LED_GREEN (1<<6) | ||
| 41 | #define SEQUOIA_LED_AMBER (1<<5) | ||
| 42 | #define SEQUOIA_LED_BACK (1<<7) | ||
| 43 | |||
| 44 | #define pcibios_assign_all_busses() 1 | ||
| 45 | |||
| 46 | #define PCIBIOS_MIN_IO 0x6000 | ||
| 47 | #define PCIBIOS_MIN_MEM 0x50000000 | ||
| 48 | #define PCIMEM_BASE 0xe8000000 | ||
| 49 | |||
| 50 | #endif | ||
| 51 | |||
diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h deleted file mode 100644 index b11d7860a9d3..000000000000 --- a/include/asm-arm/arch-shark/io.h +++ /dev/null | |||
| @@ -1,56 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-shark/io.h | ||
| 3 | * | ||
| 4 | * by Alexander Schulz | ||
| 5 | * | ||
| 6 | * derived from: | ||
| 7 | * linux/include/asm-arm/arch-ebsa110/io.h | ||
| 8 | * Copyright (C) 1997,1998 Russell King | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 12 | #define __ASM_ARM_ARCH_IO_H | ||
| 13 | |||
| 14 | #include <asm/arch/hardware.h> | ||
| 15 | |||
| 16 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 17 | |||
| 18 | /* | ||
| 19 | * We use two different types of addressing - PC style addresses, and ARM | ||
| 20 | * addresses. PC style accesses the PC hardware with the normal PC IO | ||
| 21 | * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ | ||
| 22 | * and are translated to the start of IO. | ||
| 23 | */ | ||
| 24 | #define __PORT_PCIO(x) (!((x) & 0x80000000)) | ||
| 25 | |||
| 26 | #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) | ||
| 27 | |||
| 28 | |||
| 29 | static inline unsigned int __ioaddr (unsigned int port) \ | ||
| 30 | { \ | ||
| 31 | if (__PORT_PCIO(port)) \ | ||
| 32 | return (unsigned int)(PCIO_BASE + (port)); \ | ||
| 33 | else \ | ||
| 34 | return (unsigned int)(IO_BASE + (port)); \ | ||
| 35 | } | ||
| 36 | |||
| 37 | #define __mem_pci(addr) (addr) | ||
| 38 | |||
| 39 | /* | ||
| 40 | * Translated address IO functions | ||
| 41 | * | ||
| 42 | * IO address has already been translated to a virtual address | ||
| 43 | */ | ||
| 44 | #define outb_t(v,p) \ | ||
| 45 | (*(volatile unsigned char *)(p) = (v)) | ||
| 46 | |||
| 47 | #define inb_t(p) \ | ||
| 48 | (*(volatile unsigned char *)(p)) | ||
| 49 | |||
| 50 | #define outl_t(v,p) \ | ||
| 51 | (*(volatile unsigned long *)(p) = (v)) | ||
| 52 | |||
| 53 | #define inl_t(p) \ | ||
| 54 | (*(volatile unsigned long *)(p)) | ||
| 55 | |||
| 56 | #endif | ||
diff --git a/include/asm-arm/arch-shark/irqs.h b/include/asm-arm/arch-shark/irqs.h deleted file mode 100644 index b36cc975b290..000000000000 --- a/include/asm-arm/arch-shark/irqs.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-shark/irqs.h | ||
| 3 | * | ||
| 4 | * by Alexander Schulz | ||
| 5 | */ | ||
| 6 | |||
| 7 | #define NR_IRQS 16 | ||
| 8 | |||
| 9 | #define IRQ_ISA_KEYBOARD 1 | ||
| 10 | #define RTC_IRQ 8 | ||
| 11 | #define I8042_KBD_IRQ 1 | ||
| 12 | #define I8042_AUX_IRQ 12 | ||
| 13 | #define IRQ_HARDDISK 14 | ||
diff --git a/include/asm-arm/arch-shark/memory.h b/include/asm-arm/arch-shark/memory.h deleted file mode 100644 index 6968d6103ea0..000000000000 --- a/include/asm-arm/arch-shark/memory.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-shark/memory.h | ||
| 3 | * | ||
| 4 | * by Alexander Schulz | ||
| 5 | * | ||
| 6 | * derived from: | ||
| 7 | * linux/include/asm-arm/arch-ebsa110/memory.h | ||
| 8 | * Copyright (c) 1996-1999 Russell King. | ||
| 9 | */ | ||
| 10 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 11 | #define __ASM_ARCH_MEMORY_H | ||
| 12 | |||
| 13 | #include <asm/sizes.h> | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Physical DRAM offset. | ||
| 17 | */ | ||
| 18 | #define PHYS_OFFSET UL(0x08000000) | ||
| 19 | |||
| 20 | #ifndef __ASSEMBLY__ | ||
| 21 | |||
| 22 | static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size) | ||
| 23 | { | ||
| 24 | if (node != 0) return; | ||
| 25 | /* Only the first 4 MB (=1024 Pages) are usable for DMA */ | ||
| 26 | zone_size[1] = zone_size[0] - 1024; | ||
| 27 | zone_size[0] = 1024; | ||
| 28 | zhole_size[1] = zhole_size[0]; | ||
| 29 | zhole_size[0] = 0; | ||
| 30 | } | ||
| 31 | |||
| 32 | #define arch_adjust_zones(node, size, holes) \ | ||
| 33 | __arch_adjust_zones(node, size, holes) | ||
| 34 | |||
| 35 | #define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1) | ||
| 36 | |||
| 37 | #endif | ||
| 38 | |||
| 39 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 40 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Cache flushing area | ||
| 44 | */ | ||
| 45 | #define FLUSH_BASE_PHYS 0x80000000 | ||
| 46 | #define FLUSH_BASE 0xdf000000 | ||
| 47 | |||
| 48 | #endif | ||
diff --git a/include/asm-arm/arch-shark/system.h b/include/asm-arm/arch-shark/system.h deleted file mode 100644 index f12d771ab4ce..000000000000 --- a/include/asm-arm/arch-shark/system.h +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-shark/system.h | ||
| 3 | * | ||
| 4 | * by Alexander Schulz | ||
| 5 | */ | ||
| 6 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 7 | #define __ASM_ARCH_SYSTEM_H | ||
| 8 | |||
| 9 | #include <asm/io.h> | ||
| 10 | |||
| 11 | static void arch_reset(char mode) | ||
| 12 | { | ||
| 13 | short temp; | ||
| 14 | local_irq_disable(); | ||
| 15 | /* Reset the Machine via pc[3] of the sequoia chipset */ | ||
| 16 | outw(0x09,0x24); | ||
| 17 | temp=inw(0x26); | ||
| 18 | temp = temp | (1<<3) | (1<<10); | ||
| 19 | outw(0x09,0x24); | ||
| 20 | outw(temp,0x26); | ||
| 21 | |||
| 22 | } | ||
| 23 | |||
| 24 | static inline void arch_idle(void) | ||
| 25 | { | ||
| 26 | } | ||
| 27 | |||
| 28 | #endif | ||
diff --git a/include/asm-arm/arch-shark/timex.h b/include/asm-arm/arch-shark/timex.h deleted file mode 100644 index 0d02d255513b..000000000000 --- a/include/asm-arm/arch-shark/timex.h +++ /dev/null | |||
| @@ -1,7 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-shark/timex.h | ||
| 3 | * | ||
| 4 | * by Alexander Schulz | ||
| 5 | */ | ||
| 6 | |||
| 7 | #define CLOCK_TICK_RATE 1193180 | ||
diff --git a/include/asm-arm/arch-shark/uncompress.h b/include/asm-arm/arch-shark/uncompress.h deleted file mode 100644 index 7eca6534f1bb..000000000000 --- a/include/asm-arm/arch-shark/uncompress.h +++ /dev/null | |||
| @@ -1,51 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-shark/uncompress.h | ||
| 3 | * by Alexander Schulz | ||
| 4 | * | ||
| 5 | * derived from: | ||
| 6 | * linux/include/asm-arm/arch-ebsa285/uncompress.h | ||
| 7 | * Copyright (C) 1996,1997,1998 Russell King | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define SERIAL_BASE ((volatile unsigned char *)0x400003f8) | ||
| 11 | |||
| 12 | static inline void putc(int c) | ||
| 13 | { | ||
| 14 | int t; | ||
| 15 | |||
| 16 | SERIAL_BASE[0] = c; | ||
| 17 | t=0x10000; | ||
| 18 | while (t--); | ||
| 19 | } | ||
| 20 | |||
| 21 | static inline void flush(void) | ||
| 22 | { | ||
| 23 | } | ||
| 24 | |||
| 25 | #ifdef DEBUG | ||
| 26 | static void putn(unsigned long z) | ||
| 27 | { | ||
| 28 | int i; | ||
| 29 | char x; | ||
| 30 | |||
| 31 | putc('0'); | ||
| 32 | putc('x'); | ||
| 33 | for (i=0;i<8;i++) { | ||
| 34 | x='0'+((z>>((7-i)*4))&0xf); | ||
| 35 | if (x>'9') x=x-'0'+'A'-10; | ||
| 36 | putc(x); | ||
| 37 | } | ||
| 38 | } | ||
| 39 | |||
| 40 | static void putr() | ||
| 41 | { | ||
| 42 | putc('\n'); | ||
| 43 | putc('\r'); | ||
| 44 | } | ||
| 45 | #endif | ||
| 46 | |||
| 47 | /* | ||
| 48 | * nothing to do | ||
| 49 | */ | ||
| 50 | #define arch_decomp_setup() | ||
| 51 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-shark/vmalloc.h b/include/asm-arm/arch-shark/vmalloc.h deleted file mode 100644 index fac37c636b38..000000000000 --- a/include/asm-arm/arch-shark/vmalloc.h +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-shark/vmalloc.h | ||
| 3 | */ | ||
| 4 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||
diff --git a/include/asm-arm/arch-versatile/debug-macro.S b/include/asm-arm/arch-versatile/debug-macro.S deleted file mode 100644 index fe106d184e62..000000000000 --- a/include/asm-arm/arch-versatile/debug-macro.S +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/arch-versatile/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | moveq \rx, #0x10000000 | ||
| 18 | movne \rx, #0xf1000000 @ virtual base | ||
| 19 | orr \rx, \rx, #0x001F0000 | ||
| 20 | orr \rx, \rx, #0x00001000 | ||
| 21 | .endm | ||
| 22 | |||
| 23 | #include <asm/hardware/debug-pl01x.S> | ||
diff --git a/include/asm-arm/arch-versatile/dma.h b/include/asm-arm/arch-versatile/dma.h deleted file mode 100644 index 642577348623..000000000000 --- a/include/asm-arm/arch-versatile/dma.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-versatile/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited. | ||
| 5 | * Copyright (C) 1997,1998 Russell King | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S deleted file mode 100644 index cd114169c3e6..000000000000 --- a/include/asm-arm/arch-versatile/entry-macro.S +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-versatile/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for Versatile platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/hardware.h> | ||
| 11 | #include <asm/hardware/vic.h> | ||
| 12 | |||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro get_irqnr_preamble, base, tmp | ||
| 17 | ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) | ||
| 18 | .endm | ||
| 19 | |||
| 20 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 24 | ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status | ||
| 25 | mov \irqnr, #0 | ||
| 26 | teq \irqstat, #0 | ||
| 27 | beq 1003f | ||
| 28 | |||
| 29 | 1001: tst \irqstat, #15 | ||
| 30 | bne 1002f | ||
| 31 | add \irqnr, \irqnr, #4 | ||
| 32 | movs \irqstat, \irqstat, lsr #4 | ||
| 33 | bne 1001b | ||
| 34 | 1002: tst \irqstat, #1 | ||
| 35 | bne 1003f | ||
| 36 | add \irqnr, \irqnr, #1 | ||
| 37 | movs \irqstat, \irqstat, lsr #1 | ||
| 38 | bne 1002b | ||
| 39 | 1003: /* EQ will be set if no irqs pending */ | ||
| 40 | |||
| 41 | @ clz \irqnr, \irqstat | ||
| 42 | @1003: /* EQ will be set if we reach MAXIRQNUM */ | ||
| 43 | .endm | ||
| 44 | |||
diff --git a/include/asm-arm/arch-versatile/hardware.h b/include/asm-arm/arch-versatile/hardware.h deleted file mode 100644 index edc06598d187..000000000000 --- a/include/asm-arm/arch-versatile/hardware.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-versatile/hardware.h | ||
| 3 | * | ||
| 4 | * This file contains the hardware definitions of the Versatile boards. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003 ARM Limited. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 23 | #define __ASM_ARCH_HARDWARE_H | ||
| 24 | |||
| 25 | #include <asm/sizes.h> | ||
| 26 | #include <asm/arch/platform.h> | ||
| 27 | |||
| 28 | /* | ||
| 29 | * PCI space virtual addresses | ||
| 30 | */ | ||
| 31 | #define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul | ||
| 32 | #define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul | ||
| 33 | |||
| 34 | #if 0 | ||
| 35 | #define VERSATILE_PCI_VIRT_MEM_BASE0 0xf4000000 | ||
| 36 | #define VERSATILE_PCI_VIRT_MEM_BASE1 0xf5000000 | ||
| 37 | #define VERSATILE_PCI_VIRT_MEM_BASE2 0xf6000000 | ||
| 38 | |||
| 39 | #define PCIO_BASE VERSATILE_PCI_VIRT_MEM_BASE0 | ||
| 40 | #define PCIMEM_BASE VERSATILE_PCI_VIRT_MEM_BASE1 | ||
| 41 | #endif | ||
| 42 | |||
| 43 | /* CIK guesswork */ | ||
| 44 | #define PCIBIOS_MIN_IO 0x44000000 | ||
| 45 | #define PCIBIOS_MIN_MEM 0x50000000 | ||
| 46 | |||
| 47 | #define pcibios_assign_all_busses() 1 | ||
| 48 | |||
| 49 | /* macro to get at IO space when running virtually */ | ||
| 50 | #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) | ||
| 51 | |||
| 52 | #endif | ||
diff --git a/include/asm-arm/arch-versatile/io.h b/include/asm-arm/arch-versatile/io.h deleted file mode 100644 index c4d01948e00b..000000000000 --- a/include/asm-arm/arch-versatile/io.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-versatile/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 21 | #define __ASM_ARM_ARCH_IO_H | ||
| 22 | |||
| 23 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 24 | |||
| 25 | static inline void __iomem *__io(unsigned long addr) | ||
| 26 | { | ||
| 27 | return (void __iomem *)addr; | ||
| 28 | } | ||
| 29 | #define __io(a) __io(a) | ||
| 30 | #define __mem_pci(a) (a) | ||
| 31 | |||
| 32 | #endif | ||
diff --git a/include/asm-arm/arch-versatile/irqs.h b/include/asm-arm/arch-versatile/irqs.h deleted file mode 100644 index f7263b99403b..000000000000 --- a/include/asm-arm/arch-versatile/irqs.h +++ /dev/null | |||
| @@ -1,211 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-versatile/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <asm/arch/platform.h> | ||
| 23 | |||
| 24 | /* | ||
| 25 | * IRQ interrupts definitions are the same as the INT definitions | ||
| 26 | * held within platform.h | ||
| 27 | */ | ||
| 28 | #define IRQ_VIC_START 0 | ||
| 29 | #define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT) | ||
| 30 | #define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT) | ||
| 31 | #define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx) | ||
| 32 | #define IRQ_COMMTx (IRQ_VIC_START + INT_COMMTx) | ||
| 33 | #define IRQ_TIMERINT0_1 (IRQ_VIC_START + INT_TIMERINT0_1) | ||
| 34 | #define IRQ_TIMERINT2_3 (IRQ_VIC_START + INT_TIMERINT2_3) | ||
| 35 | #define IRQ_GPIOINT0 (IRQ_VIC_START + INT_GPIOINT0) | ||
| 36 | #define IRQ_GPIOINT1 (IRQ_VIC_START + INT_GPIOINT1) | ||
| 37 | #define IRQ_GPIOINT2 (IRQ_VIC_START + INT_GPIOINT2) | ||
| 38 | #define IRQ_GPIOINT3 (IRQ_VIC_START + INT_GPIOINT3) | ||
| 39 | #define IRQ_RTCINT (IRQ_VIC_START + INT_RTCINT) | ||
| 40 | #define IRQ_SSPINT (IRQ_VIC_START + INT_SSPINT) | ||
| 41 | #define IRQ_UARTINT0 (IRQ_VIC_START + INT_UARTINT0) | ||
| 42 | #define IRQ_UARTINT1 (IRQ_VIC_START + INT_UARTINT1) | ||
| 43 | #define IRQ_UARTINT2 (IRQ_VIC_START + INT_UARTINT2) | ||
| 44 | #define IRQ_SCIINT (IRQ_VIC_START + INT_SCIINT) | ||
| 45 | #define IRQ_CLCDINT (IRQ_VIC_START + INT_CLCDINT) | ||
| 46 | #define IRQ_DMAINT (IRQ_VIC_START + INT_DMAINT) | ||
| 47 | #define IRQ_PWRFAILINT (IRQ_VIC_START + INT_PWRFAILINT) | ||
| 48 | #define IRQ_MBXINT (IRQ_VIC_START + INT_MBXINT) | ||
| 49 | #define IRQ_GNDINT (IRQ_VIC_START + INT_GNDINT) | ||
| 50 | #define IRQ_VICSOURCE21 (IRQ_VIC_START + INT_VICSOURCE21) | ||
| 51 | #define IRQ_VICSOURCE22 (IRQ_VIC_START + INT_VICSOURCE22) | ||
| 52 | #define IRQ_VICSOURCE23 (IRQ_VIC_START + INT_VICSOURCE23) | ||
| 53 | #define IRQ_VICSOURCE24 (IRQ_VIC_START + INT_VICSOURCE24) | ||
| 54 | #define IRQ_VICSOURCE25 (IRQ_VIC_START + INT_VICSOURCE25) | ||
| 55 | #define IRQ_VICSOURCE26 (IRQ_VIC_START + INT_VICSOURCE26) | ||
| 56 | #define IRQ_VICSOURCE27 (IRQ_VIC_START + INT_VICSOURCE27) | ||
| 57 | #define IRQ_VICSOURCE28 (IRQ_VIC_START + INT_VICSOURCE28) | ||
| 58 | #define IRQ_VICSOURCE29 (IRQ_VIC_START + INT_VICSOURCE29) | ||
| 59 | #define IRQ_VICSOURCE30 (IRQ_VIC_START + INT_VICSOURCE30) | ||
| 60 | #define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31) | ||
| 61 | #define IRQ_VIC_END (IRQ_VIC_START + 31) | ||
| 62 | |||
| 63 | #define IRQMASK_WDOGINT INTMASK_WDOGINT | ||
| 64 | #define IRQMASK_SOFTINT INTMASK_SOFTINT | ||
| 65 | #define IRQMASK_COMMRx INTMASK_COMMRx | ||
| 66 | #define IRQMASK_COMMTx INTMASK_COMMTx | ||
| 67 | #define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 | ||
| 68 | #define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 | ||
| 69 | #define IRQMASK_GPIOINT0 INTMASK_GPIOINT0 | ||
| 70 | #define IRQMASK_GPIOINT1 INTMASK_GPIOINT1 | ||
| 71 | #define IRQMASK_GPIOINT2 INTMASK_GPIOINT2 | ||
| 72 | #define IRQMASK_GPIOINT3 INTMASK_GPIOINT3 | ||
| 73 | #define IRQMASK_RTCINT INTMASK_RTCINT | ||
| 74 | #define IRQMASK_SSPINT INTMASK_SSPINT | ||
| 75 | #define IRQMASK_UARTINT0 INTMASK_UARTINT0 | ||
| 76 | #define IRQMASK_UARTINT1 INTMASK_UARTINT1 | ||
| 77 | #define IRQMASK_UARTINT2 INTMASK_UARTINT2 | ||
| 78 | #define IRQMASK_SCIINT INTMASK_SCIINT | ||
| 79 | #define IRQMASK_CLCDINT INTMASK_CLCDINT | ||
| 80 | #define IRQMASK_DMAINT INTMASK_DMAINT | ||
| 81 | #define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT | ||
| 82 | #define IRQMASK_MBXINT INTMASK_MBXINT | ||
| 83 | #define IRQMASK_GNDINT INTMASK_GNDINT | ||
| 84 | #define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21 | ||
| 85 | #define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22 | ||
| 86 | #define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23 | ||
| 87 | #define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24 | ||
| 88 | #define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25 | ||
| 89 | #define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26 | ||
| 90 | #define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27 | ||
| 91 | #define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28 | ||
| 92 | #define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29 | ||
| 93 | #define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30 | ||
| 94 | #define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31 | ||
| 95 | |||
| 96 | /* | ||
| 97 | * FIQ interrupts definitions are the same as the INT definitions. | ||
| 98 | */ | ||
| 99 | #define FIQ_WDOGINT INT_WDOGINT | ||
| 100 | #define FIQ_SOFTINT INT_SOFTINT | ||
| 101 | #define FIQ_COMMRx INT_COMMRx | ||
| 102 | #define FIQ_COMMTx INT_COMMTx | ||
| 103 | #define FIQ_TIMERINT0_1 INT_TIMERINT0_1 | ||
| 104 | #define FIQ_TIMERINT2_3 INT_TIMERINT2_3 | ||
| 105 | #define FIQ_GPIOINT0 INT_GPIOINT0 | ||
| 106 | #define FIQ_GPIOINT1 INT_GPIOINT1 | ||
| 107 | #define FIQ_GPIOINT2 INT_GPIOINT2 | ||
| 108 | #define FIQ_GPIOINT3 INT_GPIOINT3 | ||
| 109 | #define FIQ_RTCINT INT_RTCINT | ||
| 110 | #define FIQ_SSPINT INT_SSPINT | ||
| 111 | #define FIQ_UARTINT0 INT_UARTINT0 | ||
| 112 | #define FIQ_UARTINT1 INT_UARTINT1 | ||
| 113 | #define FIQ_UARTINT2 INT_UARTINT2 | ||
| 114 | #define FIQ_SCIINT INT_SCIINT | ||
| 115 | #define FIQ_CLCDINT INT_CLCDINT | ||
| 116 | #define FIQ_DMAINT INT_DMAINT | ||
| 117 | #define FIQ_PWRFAILINT INT_PWRFAILINT | ||
| 118 | #define FIQ_MBXINT INT_MBXINT | ||
| 119 | #define FIQ_GNDINT INT_GNDINT | ||
| 120 | #define FIQ_VICSOURCE21 INT_VICSOURCE21 | ||
| 121 | #define FIQ_VICSOURCE22 INT_VICSOURCE22 | ||
| 122 | #define FIQ_VICSOURCE23 INT_VICSOURCE23 | ||
| 123 | #define FIQ_VICSOURCE24 INT_VICSOURCE24 | ||
| 124 | #define FIQ_VICSOURCE25 INT_VICSOURCE25 | ||
| 125 | #define FIQ_VICSOURCE26 INT_VICSOURCE26 | ||
| 126 | #define FIQ_VICSOURCE27 INT_VICSOURCE27 | ||
| 127 | #define FIQ_VICSOURCE28 INT_VICSOURCE28 | ||
| 128 | #define FIQ_VICSOURCE29 INT_VICSOURCE29 | ||
| 129 | #define FIQ_VICSOURCE30 INT_VICSOURCE30 | ||
| 130 | #define FIQ_VICSOURCE31 INT_VICSOURCE31 | ||
| 131 | |||
| 132 | |||
| 133 | #define FIQMASK_WDOGINT INTMASK_WDOGINT | ||
| 134 | #define FIQMASK_SOFTINT INTMASK_SOFTINT | ||
| 135 | #define FIQMASK_COMMRx INTMASK_COMMRx | ||
| 136 | #define FIQMASK_COMMTx INTMASK_COMMTx | ||
| 137 | #define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 | ||
| 138 | #define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 | ||
| 139 | #define FIQMASK_GPIOINT0 INTMASK_GPIOINT0 | ||
| 140 | #define FIQMASK_GPIOINT1 INTMASK_GPIOINT1 | ||
| 141 | #define FIQMASK_GPIOINT2 INTMASK_GPIOINT2 | ||
| 142 | #define FIQMASK_GPIOINT3 INTMASK_GPIOINT3 | ||
| 143 | #define FIQMASK_RTCINT INTMASK_RTCINT | ||
| 144 | #define FIQMASK_SSPINT INTMASK_SSPINT | ||
| 145 | #define FIQMASK_UARTINT0 INTMASK_UARTINT0 | ||
| 146 | #define FIQMASK_UARTINT1 INTMASK_UARTINT1 | ||
| 147 | #define FIQMASK_UARTINT2 INTMASK_UARTINT2 | ||
| 148 | #define FIQMASK_SCIINT INTMASK_SCIINT | ||
| 149 | #define FIQMASK_CLCDINT INTMASK_CLCDINT | ||
| 150 | #define FIQMASK_DMAINT INTMASK_DMAINT | ||
| 151 | #define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT | ||
| 152 | #define FIQMASK_MBXINT INTMASK_MBXINT | ||
| 153 | #define FIQMASK_GNDINT INTMASK_GNDINT | ||
| 154 | #define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21 | ||
| 155 | #define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22 | ||
| 156 | #define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23 | ||
| 157 | #define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24 | ||
| 158 | #define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25 | ||
| 159 | #define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26 | ||
| 160 | #define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27 | ||
| 161 | #define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28 | ||
| 162 | #define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29 | ||
| 163 | #define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30 | ||
| 164 | #define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31 | ||
| 165 | |||
| 166 | /* | ||
| 167 | * Secondary interrupt controller | ||
| 168 | */ | ||
| 169 | #define IRQ_SIC_START 32 | ||
| 170 | #define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B) | ||
| 171 | #define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B) | ||
| 172 | #define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0) | ||
| 173 | #define IRQ_SIC_KMI1 (IRQ_SIC_START + SIC_INT_KMI1) | ||
| 174 | #define IRQ_SIC_SCI3 (IRQ_SIC_START + SIC_INT_SCI3) | ||
| 175 | #define IRQ_SIC_UART3 (IRQ_SIC_START + SIC_INT_UART3) | ||
| 176 | #define IRQ_SIC_CLCD (IRQ_SIC_START + SIC_INT_CLCD) | ||
| 177 | #define IRQ_SIC_TOUCH (IRQ_SIC_START + SIC_INT_TOUCH) | ||
| 178 | #define IRQ_SIC_KEYPAD (IRQ_SIC_START + SIC_INT_KEYPAD) | ||
| 179 | #define IRQ_SIC_DoC (IRQ_SIC_START + SIC_INT_DoC) | ||
| 180 | #define IRQ_SIC_MMCI0A (IRQ_SIC_START + SIC_INT_MMCI0A) | ||
| 181 | #define IRQ_SIC_MMCI1A (IRQ_SIC_START + SIC_INT_MMCI1A) | ||
| 182 | #define IRQ_SIC_AACI (IRQ_SIC_START + SIC_INT_AACI) | ||
| 183 | #define IRQ_SIC_ETH (IRQ_SIC_START + SIC_INT_ETH) | ||
| 184 | #define IRQ_SIC_USB (IRQ_SIC_START + SIC_INT_USB) | ||
| 185 | #define IRQ_SIC_PCI0 (IRQ_SIC_START + SIC_INT_PCI0) | ||
| 186 | #define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1) | ||
| 187 | #define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2) | ||
| 188 | #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) | ||
| 189 | #define IRQ_SIC_END 63 | ||
| 190 | |||
| 191 | #define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B | ||
| 192 | #define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B | ||
| 193 | #define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0 | ||
| 194 | #define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1 | ||
| 195 | #define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3 | ||
| 196 | #define SIC_IRQMASK_UART3 SIC_INTMASK_UART3 | ||
| 197 | #define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD | ||
| 198 | #define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH | ||
| 199 | #define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD | ||
| 200 | #define SIC_IRQMASK_DoC SIC_INTMASK_DoC | ||
| 201 | #define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A | ||
| 202 | #define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A | ||
| 203 | #define SIC_IRQMASK_AACI SIC_INTMASK_AACI | ||
| 204 | #define SIC_IRQMASK_ETH SIC_INTMASK_ETH | ||
| 205 | #define SIC_IRQMASK_USB SIC_INTMASK_USB | ||
| 206 | #define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0 | ||
| 207 | #define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1 | ||
| 208 | #define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2 | ||
| 209 | #define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3 | ||
| 210 | |||
| 211 | #define NR_IRQS 64 | ||
diff --git a/include/asm-arm/arch-versatile/memory.h b/include/asm-arm/arch-versatile/memory.h deleted file mode 100644 index a9370976cc5e..000000000000 --- a/include/asm-arm/arch-versatile/memory.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-versatile/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 21 | #define __ASM_ARCH_MEMORY_H | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Physical DRAM offset. | ||
| 25 | */ | ||
| 26 | #define PHYS_OFFSET UL(0x00000000) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Virtual view <-> DMA view memory address translations | ||
| 30 | * virt_to_bus: Used to translate the virtual address to an | ||
| 31 | * address suitable to be passed to set_dma_addr | ||
| 32 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 33 | * to an address that the kernel can use. | ||
| 34 | */ | ||
| 35 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET) | ||
| 36 | #define __bus_to_virt(x) ((x) + PAGE_OFFSET) | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-versatile/platform.h b/include/asm-arm/arch-versatile/platform.h deleted file mode 100644 index 2af9d7c9c63c..000000000000 --- a/include/asm-arm/arch-versatile/platform.h +++ /dev/null | |||
| @@ -1,510 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-versatile/platform.h | ||
| 3 | * | ||
| 4 | * Copyright (c) ARM Limited 2003. All rights reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __address_h | ||
| 22 | #define __address_h 1 | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Memory definitions | ||
| 26 | */ | ||
| 27 | #define VERSATILE_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/ | ||
| 28 | #define VERSATILE_BOOT_ROM_HI 0x30000000 | ||
| 29 | #define VERSATILE_BOOT_ROM_BASE VERSATILE_BOOT_ROM_HI /* Normal position */ | ||
| 30 | #define VERSATILE_BOOT_ROM_SIZE SZ_64M | ||
| 31 | |||
| 32 | #define VERSATILE_SSRAM_BASE /* VERSATILE_SSMC_BASE ? */ | ||
| 33 | #define VERSATILE_SSRAM_SIZE SZ_2M | ||
| 34 | |||
| 35 | #define VERSATILE_FLASH_BASE 0x34000000 | ||
| 36 | #define VERSATILE_FLASH_SIZE SZ_64M | ||
| 37 | |||
| 38 | /* | ||
| 39 | * SDRAM | ||
| 40 | */ | ||
| 41 | #define VERSATILE_SDRAM_BASE 0x00000000 | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Logic expansion modules | ||
| 45 | * | ||
| 46 | */ | ||
| 47 | |||
| 48 | |||
| 49 | /* ------------------------------------------------------------------------ | ||
| 50 | * Versatile Registers | ||
| 51 | * ------------------------------------------------------------------------ | ||
| 52 | * | ||
| 53 | */ | ||
| 54 | #define VERSATILE_SYS_ID_OFFSET 0x00 | ||
| 55 | #define VERSATILE_SYS_SW_OFFSET 0x04 | ||
| 56 | #define VERSATILE_SYS_LED_OFFSET 0x08 | ||
| 57 | #define VERSATILE_SYS_OSC0_OFFSET 0x0C | ||
| 58 | |||
| 59 | #if defined(CONFIG_ARCH_VERSATILE_PB) | ||
| 60 | #define VERSATILE_SYS_OSC1_OFFSET 0x10 | ||
| 61 | #define VERSATILE_SYS_OSC2_OFFSET 0x14 | ||
| 62 | #define VERSATILE_SYS_OSC3_OFFSET 0x18 | ||
| 63 | #define VERSATILE_SYS_OSC4_OFFSET 0x1C | ||
| 64 | #elif defined(CONFIG_MACH_VERSATILE_AB) | ||
| 65 | #define VERSATILE_SYS_OSC1_OFFSET 0x1C | ||
| 66 | #endif | ||
| 67 | |||
| 68 | #define VERSATILE_SYS_OSCCLCD_OFFSET 0x1c | ||
| 69 | |||
| 70 | #define VERSATILE_SYS_LOCK_OFFSET 0x20 | ||
| 71 | #define VERSATILE_SYS_100HZ_OFFSET 0x24 | ||
| 72 | #define VERSATILE_SYS_CFGDATA1_OFFSET 0x28 | ||
| 73 | #define VERSATILE_SYS_CFGDATA2_OFFSET 0x2C | ||
| 74 | #define VERSATILE_SYS_FLAGS_OFFSET 0x30 | ||
| 75 | #define VERSATILE_SYS_FLAGSSET_OFFSET 0x30 | ||
| 76 | #define VERSATILE_SYS_FLAGSCLR_OFFSET 0x34 | ||
| 77 | #define VERSATILE_SYS_NVFLAGS_OFFSET 0x38 | ||
| 78 | #define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38 | ||
| 79 | #define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C | ||
| 80 | #define VERSATILE_SYS_RESETCTL_OFFSET 0x40 | ||
| 81 | #define VERSATILE_SYS_PCICTL_OFFSET 0x44 | ||
| 82 | #define VERSATILE_SYS_MCI_OFFSET 0x48 | ||
| 83 | #define VERSATILE_SYS_FLASH_OFFSET 0x4C | ||
| 84 | #define VERSATILE_SYS_CLCD_OFFSET 0x50 | ||
| 85 | #define VERSATILE_SYS_CLCDSER_OFFSET 0x54 | ||
| 86 | #define VERSATILE_SYS_BOOTCS_OFFSET 0x58 | ||
| 87 | #define VERSATILE_SYS_24MHz_OFFSET 0x5C | ||
| 88 | #define VERSATILE_SYS_MISC_OFFSET 0x60 | ||
| 89 | #define VERSATILE_SYS_TEST_OSC0_OFFSET 0x80 | ||
| 90 | #define VERSATILE_SYS_TEST_OSC1_OFFSET 0x84 | ||
| 91 | #define VERSATILE_SYS_TEST_OSC2_OFFSET 0x88 | ||
| 92 | #define VERSATILE_SYS_TEST_OSC3_OFFSET 0x8C | ||
| 93 | #define VERSATILE_SYS_TEST_OSC4_OFFSET 0x90 | ||
| 94 | |||
| 95 | #define VERSATILE_SYS_BASE 0x10000000 | ||
| 96 | #define VERSATILE_SYS_ID (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET) | ||
| 97 | #define VERSATILE_SYS_SW (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET) | ||
| 98 | #define VERSATILE_SYS_LED (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET) | ||
| 99 | #define VERSATILE_SYS_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET) | ||
| 100 | #define VERSATILE_SYS_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET) | ||
| 101 | |||
| 102 | #if defined(CONFIG_ARCH_VERSATILE_PB) | ||
| 103 | #define VERSATILE_SYS_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET) | ||
| 104 | #define VERSATILE_SYS_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET) | ||
| 105 | #define VERSATILE_SYS_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET) | ||
| 106 | #endif | ||
| 107 | |||
| 108 | #define VERSATILE_SYS_LOCK (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET) | ||
| 109 | #define VERSATILE_SYS_100HZ (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET) | ||
| 110 | #define VERSATILE_SYS_CFGDATA1 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET) | ||
| 111 | #define VERSATILE_SYS_CFGDATA2 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET) | ||
| 112 | #define VERSATILE_SYS_FLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET) | ||
| 113 | #define VERSATILE_SYS_FLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET) | ||
| 114 | #define VERSATILE_SYS_FLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET) | ||
| 115 | #define VERSATILE_SYS_NVFLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET) | ||
| 116 | #define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET) | ||
| 117 | #define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET) | ||
| 118 | #define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET) | ||
| 119 | #define VERSATILE_SYS_PCICTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PCICTL_OFFSET) | ||
| 120 | #define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET) | ||
| 121 | #define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) | ||
| 122 | #define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET) | ||
| 123 | #define VERSATILE_SYS_CLCDSER (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET) | ||
| 124 | #define VERSATILE_SYS_BOOTCS (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET) | ||
| 125 | #define VERSATILE_SYS_24MHz (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET) | ||
| 126 | #define VERSATILE_SYS_MISC (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET) | ||
| 127 | #define VERSATILE_SYS_TEST_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET) | ||
| 128 | #define VERSATILE_SYS_TEST_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET) | ||
| 129 | #define VERSATILE_SYS_TEST_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET) | ||
| 130 | #define VERSATILE_SYS_TEST_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET) | ||
| 131 | #define VERSATILE_SYS_TEST_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET) | ||
| 132 | |||
| 133 | /* | ||
| 134 | * Values for VERSATILE_SYS_RESET_CTRL | ||
| 135 | */ | ||
| 136 | #define VERSATILE_SYS_CTRL_RESET_CONFIGCLR 0x01 | ||
| 137 | #define VERSATILE_SYS_CTRL_RESET_CONFIGINIT 0x02 | ||
| 138 | #define VERSATILE_SYS_CTRL_RESET_DLLRESET 0x03 | ||
| 139 | #define VERSATILE_SYS_CTRL_RESET_PLLRESET 0x04 | ||
| 140 | #define VERSATILE_SYS_CTRL_RESET_POR 0x05 | ||
| 141 | #define VERSATILE_SYS_CTRL_RESET_DoC 0x06 | ||
| 142 | |||
| 143 | #define VERSATILE_SYS_CTRL_LED (1 << 0) | ||
| 144 | |||
| 145 | |||
| 146 | /* ------------------------------------------------------------------------ | ||
| 147 | * Versatile control registers | ||
| 148 | * ------------------------------------------------------------------------ | ||
| 149 | */ | ||
| 150 | |||
| 151 | /* | ||
| 152 | * VERSATILE_IDFIELD | ||
| 153 | * | ||
| 154 | * 31:24 = manufacturer (0x41 = ARM) | ||
| 155 | * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) | ||
| 156 | * 15:12 = FPGA (0x3 = XVC600 or XVC600E) | ||
| 157 | * 11:4 = build value | ||
| 158 | * 3:0 = revision number (0x1 = rev B (AHB)) | ||
| 159 | */ | ||
| 160 | |||
| 161 | /* | ||
| 162 | * VERSATILE_SYS_LOCK | ||
| 163 | * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, | ||
| 164 | * SYS_CLD, SYS_BOOTCS | ||
| 165 | */ | ||
| 166 | #define VERSATILE_SYS_LOCK_LOCKED (1 << 16) | ||
| 167 | #define VERSATILE_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ | ||
| 168 | |||
| 169 | /* | ||
| 170 | * VERSATILE_SYS_FLASH | ||
| 171 | */ | ||
| 172 | #define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ | ||
| 173 | |||
| 174 | /* | ||
| 175 | * VERSATILE_INTREG | ||
| 176 | * - used to acknowledge and control MMCI and UART interrupts | ||
| 177 | */ | ||
| 178 | #define VERSATILE_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ | ||
| 179 | #define VERSATILE_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ | ||
| 180 | #define VERSATILE_INTREG_CARDIN 0x08 /* MMCI card in detect */ | ||
| 181 | /* write 1 to acknowledge and clear */ | ||
| 182 | #define VERSATILE_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ | ||
| 183 | #define VERSATILE_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ | ||
| 184 | |||
| 185 | /* | ||
| 186 | * VERSATILE peripheral addresses | ||
| 187 | */ | ||
| 188 | #define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */ | ||
| 189 | #define VERSATILE_I2C_BASE 0x10002000 /* I2C control */ | ||
| 190 | #define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */ | ||
| 191 | #define VERSATILE_AACI_BASE 0x10004000 /* Audio */ | ||
| 192 | #define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */ | ||
| 193 | #define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */ | ||
| 194 | #define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */ | ||
| 195 | #define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */ | ||
| 196 | #define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */ | ||
| 197 | #define VERSATILE_SCI1_BASE 0x1000A000 | ||
| 198 | #define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */ | ||
| 199 | /* 0x1000C000 - 0x1000CFFF = reserved */ | ||
| 200 | #define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */ | ||
| 201 | #define VERSATILE_USB_BASE 0x10020000 /* USB */ | ||
| 202 | /* 0x10030000 - 0x100FFFFF = reserved */ | ||
| 203 | #define VERSATILE_SMC_BASE 0x10100000 /* SMC */ | ||
| 204 | #define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */ | ||
| 205 | #define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */ | ||
| 206 | #define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */ | ||
| 207 | #define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */ | ||
| 208 | #define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */ | ||
| 209 | /* 0x10000000 - 0x100FFFFF */ | ||
| 210 | #define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */ | ||
| 211 | #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ | ||
| 212 | #define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */ | ||
| 213 | #define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */ | ||
| 214 | #define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */ | ||
| 215 | #define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */ | ||
| 216 | #define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */ | ||
| 217 | #define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */ | ||
| 218 | #define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */ | ||
| 219 | #define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */ | ||
| 220 | /* 0x101E9000 - reserved */ | ||
| 221 | #define VERSATILE_SCI_BASE 0x101F0000 /* Smart card controller */ | ||
| 222 | #define VERSATILE_UART0_BASE 0x101F1000 /* Uart 0 */ | ||
| 223 | #define VERSATILE_UART1_BASE 0x101F2000 /* Uart 1 */ | ||
| 224 | #define VERSATILE_UART2_BASE 0x101F3000 /* Uart 2 */ | ||
| 225 | #define VERSATILE_SSP_BASE 0x101F4000 /* Synchronous Serial Port */ | ||
| 226 | |||
| 227 | #define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */ | ||
| 228 | #define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */ | ||
| 229 | #define VERSATILE_MBX_BASE 0x40000000 /* MBX */ | ||
| 230 | |||
| 231 | /* PCI space */ | ||
| 232 | #define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */ | ||
| 233 | #define VERSATILE_PCI_CFG_BASE 0x42000000 | ||
| 234 | #define VERSATILE_PCI_MEM_BASE0 0x44000000 | ||
| 235 | #define VERSATILE_PCI_MEM_BASE1 0x50000000 | ||
| 236 | #define VERSATILE_PCI_MEM_BASE2 0x60000000 | ||
| 237 | /* Sizes of above maps */ | ||
| 238 | #define VERSATILE_PCI_BASE_SIZE 0x01000000 | ||
| 239 | #define VERSATILE_PCI_CFG_BASE_SIZE 0x02000000 | ||
| 240 | #define VERSATILE_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */ | ||
| 241 | #define VERSATILE_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */ | ||
| 242 | #define VERSATILE_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */ | ||
| 243 | |||
| 244 | #define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ | ||
| 245 | #define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */ | ||
| 246 | |||
| 247 | /* | ||
| 248 | * Disk on Chip | ||
| 249 | */ | ||
| 250 | #define VERSATILE_DOC_BASE 0x2C000000 | ||
| 251 | #define VERSATILE_DOC_SIZE (16 << 20) | ||
| 252 | #define VERSATILE_DOC_PAGE_SIZE 512 | ||
| 253 | #define VERSATILE_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE) | ||
| 254 | |||
| 255 | #define ERASE_UNIT_PAGES 32 | ||
| 256 | #define START_PAGE 0x80 | ||
| 257 | |||
| 258 | /* | ||
| 259 | * LED settings, bits [7:0] | ||
| 260 | */ | ||
| 261 | #define VERSATILE_SYS_LED0 (1 << 0) | ||
| 262 | #define VERSATILE_SYS_LED1 (1 << 1) | ||
| 263 | #define VERSATILE_SYS_LED2 (1 << 2) | ||
| 264 | #define VERSATILE_SYS_LED3 (1 << 3) | ||
| 265 | #define VERSATILE_SYS_LED4 (1 << 4) | ||
| 266 | #define VERSATILE_SYS_LED5 (1 << 5) | ||
| 267 | #define VERSATILE_SYS_LED6 (1 << 6) | ||
| 268 | #define VERSATILE_SYS_LED7 (1 << 7) | ||
| 269 | |||
| 270 | #define ALL_LEDS 0xFF | ||
| 271 | |||
| 272 | #define LED_BANK VERSATILE_SYS_LED | ||
| 273 | |||
| 274 | /* | ||
| 275 | * Control registers | ||
| 276 | */ | ||
| 277 | #define VERSATILE_IDFIELD_OFFSET 0x0 /* Versatile build information */ | ||
| 278 | #define VERSATILE_FLASHPROG_OFFSET 0x4 /* Flash devices */ | ||
| 279 | #define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */ | ||
| 280 | #define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */ | ||
| 281 | |||
| 282 | |||
| 283 | /* ------------------------------------------------------------------------ | ||
| 284 | * Versatile Interrupt Controller - control registers | ||
| 285 | * ------------------------------------------------------------------------ | ||
| 286 | * | ||
| 287 | * Offsets from interrupt controller base | ||
| 288 | * | ||
| 289 | * System Controller interrupt controller base is | ||
| 290 | * | ||
| 291 | * VERSATILE_IC_BASE | ||
| 292 | * | ||
| 293 | * Core Module interrupt controller base is | ||
| 294 | * | ||
| 295 | * VERSATILE_SYS_IC | ||
| 296 | * | ||
| 297 | */ | ||
| 298 | /* VIC definitions in include/asm-arm/hardware/vic.h */ | ||
| 299 | |||
| 300 | #define SIC_IRQ_STATUS 0 | ||
| 301 | #define SIC_IRQ_RAW_STATUS 0x04 | ||
| 302 | #define SIC_IRQ_ENABLE 0x08 | ||
| 303 | #define SIC_IRQ_ENABLE_SET 0x08 | ||
| 304 | #define SIC_IRQ_ENABLE_CLEAR 0x0C | ||
| 305 | #define SIC_INT_SOFT_SET 0x10 | ||
| 306 | #define SIC_INT_SOFT_CLEAR 0x14 | ||
| 307 | #define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */ | ||
| 308 | #define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */ | ||
| 309 | #define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */ | ||
| 310 | |||
| 311 | /* ------------------------------------------------------------------------ | ||
| 312 | * Interrupts - bit assignment (primary) | ||
| 313 | * ------------------------------------------------------------------------ | ||
| 314 | */ | ||
| 315 | |||
| 316 | #define INT_WDOGINT 0 /* Watchdog timer */ | ||
| 317 | #define INT_SOFTINT 1 /* Software interrupt */ | ||
| 318 | #define INT_COMMRx 2 /* Debug Comm Rx interrupt */ | ||
| 319 | #define INT_COMMTx 3 /* Debug Comm Tx interrupt */ | ||
| 320 | #define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ | ||
| 321 | #define INT_TIMERINT2_3 5 /* Timer 2 and 3 */ | ||
| 322 | #define INT_GPIOINT0 6 /* GPIO 0 */ | ||
| 323 | #define INT_GPIOINT1 7 /* GPIO 1 */ | ||
| 324 | #define INT_GPIOINT2 8 /* GPIO 2 */ | ||
| 325 | #define INT_GPIOINT3 9 /* GPIO 3 */ | ||
| 326 | #define INT_RTCINT 10 /* Real Time Clock */ | ||
| 327 | #define INT_SSPINT 11 /* Synchronous Serial Port */ | ||
| 328 | #define INT_UARTINT0 12 /* UART 0 on development chip */ | ||
| 329 | #define INT_UARTINT1 13 /* UART 1 on development chip */ | ||
| 330 | #define INT_UARTINT2 14 /* UART 2 on development chip */ | ||
| 331 | #define INT_SCIINT 15 /* Smart Card Interface */ | ||
| 332 | #define INT_CLCDINT 16 /* CLCD controller */ | ||
| 333 | #define INT_DMAINT 17 /* DMA controller */ | ||
| 334 | #define INT_PWRFAILINT 18 /* Power failure */ | ||
| 335 | #define INT_MBXINT 19 /* Graphics processor */ | ||
| 336 | #define INT_GNDINT 20 /* Reserved */ | ||
| 337 | /* External interrupt signals from logic tiles or secondary controller */ | ||
| 338 | #define INT_VICSOURCE21 21 /* Disk on Chip */ | ||
| 339 | #define INT_VICSOURCE22 22 /* MCI0A */ | ||
| 340 | #define INT_VICSOURCE23 23 /* MCI1A */ | ||
| 341 | #define INT_VICSOURCE24 24 /* AACI */ | ||
| 342 | #define INT_VICSOURCE25 25 /* Ethernet */ | ||
| 343 | #define INT_VICSOURCE26 26 /* USB */ | ||
| 344 | #define INT_VICSOURCE27 27 /* PCI 0 */ | ||
| 345 | #define INT_VICSOURCE28 28 /* PCI 1 */ | ||
| 346 | #define INT_VICSOURCE29 29 /* PCI 2 */ | ||
| 347 | #define INT_VICSOURCE30 30 /* PCI 3 */ | ||
| 348 | #define INT_VICSOURCE31 31 /* SIC source */ | ||
| 349 | |||
| 350 | /* | ||
| 351 | * Interrupt bit positions | ||
| 352 | * | ||
| 353 | */ | ||
| 354 | #define INTMASK_WDOGINT (1 << INT_WDOGINT) | ||
| 355 | #define INTMASK_SOFTINT (1 << INT_SOFTINT) | ||
| 356 | #define INTMASK_COMMRx (1 << INT_COMMRx) | ||
| 357 | #define INTMASK_COMMTx (1 << INT_COMMTx) | ||
| 358 | #define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1) | ||
| 359 | #define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3) | ||
| 360 | #define INTMASK_GPIOINT0 (1 << INT_GPIOINT0) | ||
| 361 | #define INTMASK_GPIOINT1 (1 << INT_GPIOINT1) | ||
| 362 | #define INTMASK_GPIOINT2 (1 << INT_GPIOINT2) | ||
| 363 | #define INTMASK_GPIOINT3 (1 << INT_GPIOINT3) | ||
| 364 | #define INTMASK_RTCINT (1 << INT_RTCINT) | ||
| 365 | #define INTMASK_SSPINT (1 << INT_SSPINT) | ||
| 366 | #define INTMASK_UARTINT0 (1 << INT_UARTINT0) | ||
| 367 | #define INTMASK_UARTINT1 (1 << INT_UARTINT1) | ||
| 368 | #define INTMASK_UARTINT2 (1 << INT_UARTINT2) | ||
| 369 | #define INTMASK_SCIINT (1 << INT_SCIINT) | ||
| 370 | #define INTMASK_CLCDINT (1 << INT_CLCDINT) | ||
| 371 | #define INTMASK_DMAINT (1 << INT_DMAINT) | ||
| 372 | #define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT) | ||
| 373 | #define INTMASK_MBXINT (1 << INT_MBXINT) | ||
| 374 | #define INTMASK_GNDINT (1 << INT_GNDINT) | ||
| 375 | #define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21) | ||
| 376 | #define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22) | ||
| 377 | #define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23) | ||
| 378 | #define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24) | ||
| 379 | #define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25) | ||
| 380 | #define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26) | ||
| 381 | #define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27) | ||
| 382 | #define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28) | ||
| 383 | #define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29) | ||
| 384 | #define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30) | ||
| 385 | #define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31) | ||
| 386 | |||
| 387 | |||
| 388 | #define VERSATILE_SC_VALID_INT 0x003FFFFF | ||
| 389 | |||
| 390 | #define MAXIRQNUM 31 | ||
| 391 | #define MAXFIQNUM 31 | ||
| 392 | #define MAXSWINUM 31 | ||
| 393 | |||
| 394 | /* ------------------------------------------------------------------------ | ||
| 395 | * Interrupts - bit assignment (secondary) | ||
| 396 | * ------------------------------------------------------------------------ | ||
| 397 | */ | ||
| 398 | #define SIC_INT_MMCI0B 1 /* Multimedia Card 0B */ | ||
| 399 | #define SIC_INT_MMCI1B 2 /* Multimedia Card 1B */ | ||
| 400 | #define SIC_INT_KMI0 3 /* Keyboard/Mouse port 0 */ | ||
| 401 | #define SIC_INT_KMI1 4 /* Keyboard/Mouse port 1 */ | ||
| 402 | #define SIC_INT_SCI3 5 /* Smart Card interface */ | ||
| 403 | #define SIC_INT_UART3 6 /* UART 3 empty or data available */ | ||
| 404 | #define SIC_INT_CLCD 7 /* Character LCD */ | ||
| 405 | #define SIC_INT_TOUCH 8 /* Touchscreen */ | ||
| 406 | #define SIC_INT_KEYPAD 9 /* Key pressed on display keypad */ | ||
| 407 | /* 10:20 - reserved */ | ||
| 408 | #define SIC_INT_DoC 21 /* Disk on Chip memory controller */ | ||
| 409 | #define SIC_INT_MMCI0A 22 /* MMC 0A */ | ||
| 410 | #define SIC_INT_MMCI1A 23 /* MMC 1A */ | ||
| 411 | #define SIC_INT_AACI 24 /* Audio Codec */ | ||
| 412 | #define SIC_INT_ETH 25 /* Ethernet controller */ | ||
| 413 | #define SIC_INT_USB 26 /* USB controller */ | ||
| 414 | #define SIC_INT_PCI0 27 | ||
| 415 | #define SIC_INT_PCI1 28 | ||
| 416 | #define SIC_INT_PCI2 29 | ||
| 417 | #define SIC_INT_PCI3 30 | ||
| 418 | |||
| 419 | |||
| 420 | #define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B) | ||
| 421 | #define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B) | ||
| 422 | #define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0) | ||
| 423 | #define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1) | ||
| 424 | #define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3) | ||
| 425 | #define SIC_INTMASK_UART3 (1 << SIC_INT_UART3) | ||
| 426 | #define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD) | ||
| 427 | #define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH) | ||
| 428 | #define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD) | ||
| 429 | #define SIC_INTMASK_DoC (1 << SIC_INT_DoC) | ||
| 430 | #define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A) | ||
| 431 | #define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A) | ||
| 432 | #define SIC_INTMASK_AACI (1 << SIC_INT_AACI) | ||
| 433 | #define SIC_INTMASK_ETH (1 << SIC_INT_ETH) | ||
| 434 | #define SIC_INTMASK_USB (1 << SIC_INT_USB) | ||
| 435 | #define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0) | ||
| 436 | #define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1) | ||
| 437 | #define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2) | ||
| 438 | #define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3) | ||
| 439 | /* | ||
| 440 | * Application Flash | ||
| 441 | * | ||
| 442 | */ | ||
| 443 | #define FLASH_BASE VERSATILE_FLASH_BASE | ||
| 444 | #define FLASH_SIZE VERSATILE_FLASH_SIZE | ||
| 445 | #define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) | ||
| 446 | #define FLASH_BLOCK_SIZE SZ_128K | ||
| 447 | |||
| 448 | /* | ||
| 449 | * Boot Flash | ||
| 450 | * | ||
| 451 | */ | ||
| 452 | #define EPROM_BASE VERSATILE_BOOT_ROM_HI | ||
| 453 | #define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE | ||
| 454 | #define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) | ||
| 455 | |||
| 456 | /* | ||
| 457 | * Clean base - dummy | ||
| 458 | * | ||
| 459 | */ | ||
| 460 | #define CLEAN_BASE EPROM_BASE | ||
| 461 | |||
| 462 | /* | ||
| 463 | * System controller bit assignment | ||
| 464 | */ | ||
| 465 | #define VERSATILE_REFCLK 0 | ||
| 466 | #define VERSATILE_TIMCLK 1 | ||
| 467 | |||
| 468 | #define VERSATILE_TIMER1_EnSel 15 | ||
| 469 | #define VERSATILE_TIMER2_EnSel 17 | ||
| 470 | #define VERSATILE_TIMER3_EnSel 19 | ||
| 471 | #define VERSATILE_TIMER4_EnSel 21 | ||
| 472 | |||
| 473 | |||
| 474 | #define MAX_TIMER 2 | ||
| 475 | #define MAX_PERIOD 699050 | ||
| 476 | #define TICKS_PER_uSEC 1 | ||
| 477 | |||
| 478 | /* | ||
| 479 | * These are useconds NOT ticks. | ||
| 480 | * | ||
| 481 | */ | ||
| 482 | #define mSEC_1 1000 | ||
| 483 | #define mSEC_5 (mSEC_1 * 5) | ||
| 484 | #define mSEC_10 (mSEC_1 * 10) | ||
| 485 | #define mSEC_25 (mSEC_1 * 25) | ||
| 486 | #define SEC_1 (mSEC_1 * 1000) | ||
| 487 | |||
| 488 | #define VERSATILE_CSR_BASE 0x10000000 | ||
| 489 | #define VERSATILE_CSR_SIZE 0x10000000 | ||
| 490 | |||
| 491 | #ifdef CONFIG_MACH_VERSATILE_AB | ||
| 492 | /* | ||
| 493 | * IB2 Versatile/AB expansion board definitions | ||
| 494 | */ | ||
| 495 | #define VERSATILE_IB2_CAMERA_BANK VERSATILE_IB2_BASE | ||
| 496 | #define VERSATILE_IB2_KBD_DATAREG (VERSATILE_IB2_BASE + 0x01000000) | ||
| 497 | |||
| 498 | /* VICINTSOURCE27 */ | ||
| 499 | #define VERSATILE_IB2_INT_BASE (VERSATILE_IB2_BASE + 0x02000000) | ||
| 500 | #define VERSATILE_IB2_IER (VERSATILE_IB2_INT_BASE + 0) | ||
| 501 | #define VERSATILE_IB2_ISR (VERSATILE_IB2_INT_BASE + 4) | ||
| 502 | |||
| 503 | #define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000) | ||
| 504 | #define VERSATILE_IB2_CTRL (VERSATILE_IB2_CTL_BASE + 0) | ||
| 505 | #define VERSATILE_IB2_STAT (VERSATILE_IB2_CTL_BASE + 4) | ||
| 506 | #endif | ||
| 507 | |||
| 508 | #endif | ||
| 509 | |||
| 510 | /* END */ | ||
diff --git a/include/asm-arm/arch-versatile/system.h b/include/asm-arm/arch-versatile/system.h deleted file mode 100644 index 3ea4e07b58c8..000000000000 --- a/include/asm-arm/arch-versatile/system.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-versatile/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 22 | #define __ASM_ARCH_SYSTEM_H | ||
| 23 | |||
| 24 | #include <asm/arch/hardware.h> | ||
| 25 | #include <asm/io.h> | ||
| 26 | #include <asm/arch/platform.h> | ||
| 27 | |||
| 28 | static inline void arch_idle(void) | ||
| 29 | { | ||
| 30 | /* | ||
| 31 | * This should do all the clock switching | ||
| 32 | * and wait for interrupt tricks | ||
| 33 | */ | ||
| 34 | cpu_do_idle(); | ||
| 35 | } | ||
| 36 | |||
| 37 | static inline void arch_reset(char mode) | ||
| 38 | { | ||
| 39 | u32 val; | ||
| 40 | |||
| 41 | val = __raw_readl(IO_ADDRESS(VERSATILE_SYS_RESETCTL)) & ~0x7; | ||
| 42 | val |= 0x105; | ||
| 43 | |||
| 44 | __raw_writel(0xa05f, IO_ADDRESS(VERSATILE_SYS_LOCK)); | ||
| 45 | __raw_writel(val, IO_ADDRESS(VERSATILE_SYS_RESETCTL)); | ||
| 46 | __raw_writel(0, IO_ADDRESS(VERSATILE_SYS_LOCK)); | ||
| 47 | } | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/include/asm-arm/arch-versatile/timex.h b/include/asm-arm/arch-versatile/timex.h deleted file mode 100644 index 38fd04fc9141..000000000000 --- a/include/asm-arm/arch-versatile/timex.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-versatile/timex.h | ||
| 3 | * | ||
| 4 | * Versatile architecture timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003 ARM Limited | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define CLOCK_TICK_RATE (50000000 / 16) | ||
diff --git a/include/asm-arm/arch-versatile/uncompress.h b/include/asm-arm/arch-versatile/uncompress.h deleted file mode 100644 index 7215133d0514..000000000000 --- a/include/asm-arm/arch-versatile/uncompress.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-versatile/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #define AMBA_UART_DR (*(volatile unsigned char *)0x101F1000) | ||
| 21 | #define AMBA_UART_LCRH (*(volatile unsigned char *)0x101F102C) | ||
| 22 | #define AMBA_UART_CR (*(volatile unsigned char *)0x101F1030) | ||
| 23 | #define AMBA_UART_FR (*(volatile unsigned char *)0x101F1018) | ||
| 24 | |||
| 25 | /* | ||
| 26 | * This does not append a newline | ||
| 27 | */ | ||
| 28 | static inline void putc(int c) | ||
| 29 | { | ||
| 30 | while (AMBA_UART_FR & (1 << 5)) | ||
| 31 | barrier(); | ||
| 32 | |||
| 33 | AMBA_UART_DR = c; | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline void flush(void) | ||
| 37 | { | ||
| 38 | while (AMBA_UART_FR & (1 << 3)) | ||
| 39 | barrier(); | ||
| 40 | } | ||
| 41 | |||
| 42 | /* | ||
| 43 | * nothing to do | ||
| 44 | */ | ||
| 45 | #define arch_decomp_setup() | ||
| 46 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-versatile/vmalloc.h b/include/asm-arm/arch-versatile/vmalloc.h deleted file mode 100644 index ac780df62156..000000000000 --- a/include/asm-arm/arch-versatile/vmalloc.h +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-versatile/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 ARM Limited | ||
| 5 | * Copyright (C) 2000 Russell King. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #define VMALLOC_END (PAGE_OFFSET + 0x18000000) | ||
diff --git a/include/asm-arm/plat-s3c/iic.h b/include/asm-arm/plat-s3c/iic.h index d08a1f2863e4..5106acaa1d0e 100644 --- a/include/asm-arm/plat-s3c/iic.h +++ b/include/asm-arm/plat-s3c/iic.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/iic.h | 1 | /* arch/arm/mach-s3c2410/include/mach/iic.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004 Simtec Electronics | 3 | * Copyright (c) 2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
diff --git a/include/asm-arm/plat-s3c/nand.h b/include/asm-arm/plat-s3c/nand.h index ad6bbe90616e..f4dcd14af059 100644 --- a/include/asm-arm/plat-s3c/nand.h +++ b/include/asm-arm/plat-s3c/nand.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/nand.h | 1 | /* arch/arm/mach-s3c2410/include/mach/nand.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004 Simtec Electronics | 3 | * Copyright (c) 2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
diff --git a/include/asm-arm/plat-s3c/regs-ac97.h b/include/asm-arm/plat-s3c/regs-ac97.h index b004dee6bcaf..c3878f7acb83 100644 --- a/include/asm-arm/plat-s3c/regs-ac97.h +++ b/include/asm-arm/plat-s3c/regs-ac97.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-ac97.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-ac97.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
diff --git a/include/asm-arm/plat-s3c/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h index c7f231963e76..4323cccc86cd 100644 --- a/include/asm-arm/plat-s3c/regs-adc.h +++ b/include/asm-arm/plat-s3c/regs-adc.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-adc.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-adc.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004 Shannon Holland <holland@loser.net> | 3 | * Copyright (c) 2004 Shannon Holland <holland@loser.net> |
| 4 | * | 4 | * |
diff --git a/include/asm-arm/plat-s3c/regs-iic.h b/include/asm-arm/plat-s3c/regs-iic.h index 2ae29522f253..2f7c17de8ac8 100644 --- a/include/asm-arm/plat-s3c/regs-iic.h +++ b/include/asm-arm/plat-s3c/regs-iic.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-iic.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-iic.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
diff --git a/include/asm-arm/plat-s3c/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h index d742205ac172..09f0b5503f5b 100644 --- a/include/asm-arm/plat-s3c/regs-nand.h +++ b/include/asm-arm/plat-s3c/regs-nand.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-nand.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-nand.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
diff --git a/include/asm-arm/plat-s3c/regs-rtc.h b/include/asm-arm/plat-s3c/regs-rtc.h index 93b03c49710a..d5837cf8e402 100644 --- a/include/asm-arm/plat-s3c/regs-rtc.h +++ b/include/asm-arm/plat-s3c/regs-rtc.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-rtc.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-rtc.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
diff --git a/include/asm-arm/plat-s3c/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h index 923e114db663..a0daa647b92c 100644 --- a/include/asm-arm/plat-s3c/regs-serial.h +++ b/include/asm-arm/plat-s3c/regs-serial.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-serial.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-serial.h |
| 2 | * | 2 | * |
| 3 | * From linux/include/asm-arm/hardware/serial_s3c2410.h | 3 | * From linux/include/asm-arm/hardware/serial_s3c2410.h |
| 4 | * | 4 | * |
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h index b5bc692f3489..b4366ea39677 100644 --- a/include/asm-arm/plat-s3c/regs-timer.h +++ b/include/asm-arm/plat-s3c/regs-timer.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-timer.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-timer.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
diff --git a/include/asm-arm/plat-s3c/regs-watchdog.h b/include/asm-arm/plat-s3c/regs-watchdog.h index 56c4193b7a46..1229f076c0a0 100644 --- a/include/asm-arm/plat-s3c/regs-watchdog.h +++ b/include/asm-arm/plat-s3c/regs-watchdog.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-watchdog.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
diff --git a/include/asm-arm/plat-s3c24xx/regs-iis.h b/include/asm-arm/plat-s3c24xx/regs-iis.h index eaf77916a602..a6f1d5df13b4 100644 --- a/include/asm-arm/plat-s3c24xx/regs-iis.h +++ b/include/asm-arm/plat-s3c24xx/regs-iis.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-iis.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-iis.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h index ea565b007d04..2b35479ee35c 100644 --- a/include/asm-arm/plat-s3c24xx/regs-spi.h +++ b/include/asm-arm/plat-s3c24xx/regs-spi.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-spi.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-spi.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004 Fetron GmbH | 3 | * Copyright (c) 2004 Fetron GmbH |
| 4 | * | 4 | * |
diff --git a/include/asm-arm/plat-s3c24xx/regs-udc.h b/include/asm-arm/plat-s3c24xx/regs-udc.h index e1e9805d2d9a..f0dd4a41b37b 100644 --- a/include/asm-arm/plat-s3c24xx/regs-udc.h +++ b/include/asm-arm/plat-s3c24xx/regs-udc.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/regs-udc.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-udc.h |
| 2 | * | 2 | * |
| 3 | * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> | 3 | * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> |
| 4 | * | 4 | * |
diff --git a/include/asm-arm/plat-s3c24xx/udc.h b/include/asm-arm/plat-s3c24xx/udc.h index b8aa6cb69b58..546bb4008f49 100644 --- a/include/asm-arm/plat-s3c24xx/udc.h +++ b/include/asm-arm/plat-s3c24xx/udc.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/include/asm-arm/arch-s3c2410/udc.h | 1 | /* arch/arm/mach-s3c2410/include/mach/udc.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> | 3 | * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> |
| 4 | * | 4 | * |