diff options
Diffstat (limited to 'include')
440 files changed, 31989 insertions, 2556 deletions
diff --git a/include/asm-alpha/a.out-core.h b/include/asm-alpha/a.out-core.h new file mode 100644 index 000000000000..9e33e92e524c --- /dev/null +++ b/include/asm-alpha/a.out-core.h | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | /* a.out coredump register dumper | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_A_OUT_CORE_H | ||
| 13 | #define _ASM_A_OUT_CORE_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #include <linux/user.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Fill in the user structure for an ECOFF core dump. | ||
| 21 | */ | ||
| 22 | static inline void aout_dump_thread(struct pt_regs *pt, struct user *dump) | ||
| 23 | { | ||
| 24 | /* switch stack follows right below pt_regs: */ | ||
| 25 | struct switch_stack * sw = ((struct switch_stack *) pt) - 1; | ||
| 26 | |||
| 27 | dump->magic = CMAGIC; | ||
| 28 | dump->start_code = current->mm->start_code; | ||
| 29 | dump->start_data = current->mm->start_data; | ||
| 30 | dump->start_stack = rdusp() & ~(PAGE_SIZE - 1); | ||
| 31 | dump->u_tsize = ((current->mm->end_code - dump->start_code) | ||
| 32 | >> PAGE_SHIFT); | ||
| 33 | dump->u_dsize = ((current->mm->brk + PAGE_SIZE-1 - dump->start_data) | ||
| 34 | >> PAGE_SHIFT); | ||
| 35 | dump->u_ssize = (current->mm->start_stack - dump->start_stack | ||
| 36 | + PAGE_SIZE-1) >> PAGE_SHIFT; | ||
| 37 | |||
| 38 | /* | ||
| 39 | * We store the registers in an order/format that is | ||
| 40 | * compatible with DEC Unix/OSF/1 as this makes life easier | ||
| 41 | * for gdb. | ||
| 42 | */ | ||
| 43 | dump->regs[EF_V0] = pt->r0; | ||
| 44 | dump->regs[EF_T0] = pt->r1; | ||
| 45 | dump->regs[EF_T1] = pt->r2; | ||
| 46 | dump->regs[EF_T2] = pt->r3; | ||
| 47 | dump->regs[EF_T3] = pt->r4; | ||
| 48 | dump->regs[EF_T4] = pt->r5; | ||
| 49 | dump->regs[EF_T5] = pt->r6; | ||
| 50 | dump->regs[EF_T6] = pt->r7; | ||
| 51 | dump->regs[EF_T7] = pt->r8; | ||
| 52 | dump->regs[EF_S0] = sw->r9; | ||
| 53 | dump->regs[EF_S1] = sw->r10; | ||
| 54 | dump->regs[EF_S2] = sw->r11; | ||
| 55 | dump->regs[EF_S3] = sw->r12; | ||
| 56 | dump->regs[EF_S4] = sw->r13; | ||
| 57 | dump->regs[EF_S5] = sw->r14; | ||
| 58 | dump->regs[EF_S6] = sw->r15; | ||
| 59 | dump->regs[EF_A3] = pt->r19; | ||
| 60 | dump->regs[EF_A4] = pt->r20; | ||
| 61 | dump->regs[EF_A5] = pt->r21; | ||
| 62 | dump->regs[EF_T8] = pt->r22; | ||
| 63 | dump->regs[EF_T9] = pt->r23; | ||
| 64 | dump->regs[EF_T10] = pt->r24; | ||
| 65 | dump->regs[EF_T11] = pt->r25; | ||
| 66 | dump->regs[EF_RA] = pt->r26; | ||
| 67 | dump->regs[EF_T12] = pt->r27; | ||
| 68 | dump->regs[EF_AT] = pt->r28; | ||
| 69 | dump->regs[EF_SP] = rdusp(); | ||
| 70 | dump->regs[EF_PS] = pt->ps; | ||
| 71 | dump->regs[EF_PC] = pt->pc; | ||
| 72 | dump->regs[EF_GP] = pt->gp; | ||
| 73 | dump->regs[EF_A0] = pt->r16; | ||
| 74 | dump->regs[EF_A1] = pt->r17; | ||
| 75 | dump->regs[EF_A2] = pt->r18; | ||
| 76 | memcpy((char *)dump->regs + EF_SIZE, sw->fp, 32 * 8); | ||
| 77 | } | ||
| 78 | |||
| 79 | #endif /* __KERNEL__ */ | ||
| 80 | #endif /* _ASM_A_OUT_CORE_H */ | ||
diff --git a/include/asm-alpha/a.out.h b/include/asm-alpha/a.out.h index e43cf61649a9..02ce8473870a 100644 --- a/include/asm-alpha/a.out.h +++ b/include/asm-alpha/a.out.h | |||
| @@ -98,11 +98,5 @@ struct exec | |||
| 98 | set_personality (((BFPM->sh_bang || EX.ah.entry < 0x100000000L \ | 98 | set_personality (((BFPM->sh_bang || EX.ah.entry < 0x100000000L \ |
| 99 | ? ADDR_LIMIT_32BIT : 0) | PER_OSF4)) | 99 | ? ADDR_LIMIT_32BIT : 0) | PER_OSF4)) |
| 100 | 100 | ||
| 101 | #define STACK_TOP \ | 101 | #endif /* __KERNEL__ */ |
| 102 | (current->personality & ADDR_LIMIT_32BIT ? 0x80000000 : 0x00120000000UL) | ||
| 103 | |||
| 104 | #define STACK_TOP_MAX 0x00120000000UL | ||
| 105 | |||
| 106 | #endif | ||
| 107 | |||
| 108 | #endif /* __A_OUT_GNU_H__ */ | 102 | #endif /* __A_OUT_GNU_H__ */ |
diff --git a/include/asm-alpha/page.h b/include/asm-alpha/page.h index 05f09f997d82..22ff9762d17b 100644 --- a/include/asm-alpha/page.h +++ b/include/asm-alpha/page.h | |||
| @@ -62,6 +62,8 @@ typedef unsigned long pgprot_t; | |||
| 62 | 62 | ||
| 63 | #endif /* STRICT_MM_TYPECHECKS */ | 63 | #endif /* STRICT_MM_TYPECHECKS */ |
| 64 | 64 | ||
| 65 | typedef struct page *pgtable_t; | ||
| 66 | |||
| 65 | #ifdef USE_48_BIT_KSEG | 67 | #ifdef USE_48_BIT_KSEG |
| 66 | #define PAGE_OFFSET 0xffff800000000000UL | 68 | #define PAGE_OFFSET 0xffff800000000000UL |
| 67 | #else | 69 | #else |
diff --git a/include/asm-alpha/param.h b/include/asm-alpha/param.h index 214e7996346f..0982f1d39499 100644 --- a/include/asm-alpha/param.h +++ b/include/asm-alpha/param.h | |||
| @@ -5,15 +5,7 @@ | |||
| 5 | hardware ignores reprogramming. We also need userland buy-in to the | 5 | hardware ignores reprogramming. We also need userland buy-in to the |
| 6 | change in HZ, since this is visible in the wait4 resources etc. */ | 6 | change in HZ, since this is visible in the wait4 resources etc. */ |
| 7 | 7 | ||
| 8 | 8 | #define HZ CONFIG_HZ | |
| 9 | #ifndef HZ | ||
| 10 | # ifndef CONFIG_ALPHA_RAWHIDE | ||
| 11 | # define HZ 1024 | ||
| 12 | # else | ||
| 13 | # define HZ 1200 | ||
| 14 | # endif | ||
| 15 | #endif | ||
| 16 | |||
| 17 | #define USER_HZ HZ | 9 | #define USER_HZ HZ |
| 18 | 10 | ||
| 19 | #define EXEC_PAGESIZE 8192 | 11 | #define EXEC_PAGESIZE 8192 |
diff --git a/include/asm-alpha/pgalloc.h b/include/asm-alpha/pgalloc.h index fdbedacc7375..fd090155dccd 100644 --- a/include/asm-alpha/pgalloc.h +++ b/include/asm-alpha/pgalloc.h | |||
| @@ -11,10 +11,11 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | static inline void | 13 | static inline void |
| 14 | pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte) | 14 | pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t pte) |
| 15 | { | 15 | { |
| 16 | pmd_set(pmd, (pte_t *)(page_to_pa(pte) + PAGE_OFFSET)); | 16 | pmd_set(pmd, (pte_t *)(page_to_pa(pte) + PAGE_OFFSET)); |
| 17 | } | 17 | } |
| 18 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 18 | 19 | ||
| 19 | static inline void | 20 | static inline void |
| 20 | pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) | 21 | pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) |
| @@ -57,18 +58,23 @@ pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 57 | free_page((unsigned long)pte); | 58 | free_page((unsigned long)pte); |
| 58 | } | 59 | } |
| 59 | 60 | ||
| 60 | static inline struct page * | 61 | static inline pgtable_t |
| 61 | pte_alloc_one(struct mm_struct *mm, unsigned long addr) | 62 | pte_alloc_one(struct mm_struct *mm, unsigned long address) |
| 62 | { | 63 | { |
| 63 | pte_t *pte = pte_alloc_one_kernel(mm, addr); | 64 | pte_t *pte = pte_alloc_one_kernel(mm, address); |
| 64 | if (pte) | 65 | struct page *page; |
| 65 | return virt_to_page(pte); | 66 | |
| 66 | return NULL; | 67 | if (!pte) |
| 68 | return NULL; | ||
| 69 | page = virt_to_page(pte); | ||
| 70 | pgtable_page_ctor(page); | ||
| 71 | return page; | ||
| 67 | } | 72 | } |
| 68 | 73 | ||
| 69 | static inline void | 74 | static inline void |
| 70 | pte_free(struct mm_struct *mm, struct page *page) | 75 | pte_free(struct mm_struct *mm, pgtable_t page) |
| 71 | { | 76 | { |
| 77 | pgtable_page_dtor(page); | ||
| 72 | __free_page(page); | 78 | __free_page(page); |
| 73 | } | 79 | } |
| 74 | 80 | ||
diff --git a/include/asm-alpha/processor.h b/include/asm-alpha/processor.h index 425b7b6d28cb..94afe5859301 100644 --- a/include/asm-alpha/processor.h +++ b/include/asm-alpha/processor.h | |||
| @@ -20,6 +20,11 @@ | |||
| 20 | */ | 20 | */ |
| 21 | #define TASK_SIZE (0x40000000000UL) | 21 | #define TASK_SIZE (0x40000000000UL) |
| 22 | 22 | ||
| 23 | #define STACK_TOP \ | ||
| 24 | (current->personality & ADDR_LIMIT_32BIT ? 0x80000000 : 0x00120000000UL) | ||
| 25 | |||
| 26 | #define STACK_TOP_MAX 0x00120000000UL | ||
| 27 | |||
| 23 | /* This decides where the kernel will search for a free chunk of vm | 28 | /* This decides where the kernel will search for a free chunk of vm |
| 24 | * space during mmap's. | 29 | * space during mmap's. |
| 25 | */ | 30 | */ |
diff --git a/include/asm-arm/a.out-core.h b/include/asm-arm/a.out-core.h new file mode 100644 index 000000000000..93d04acaa31f --- /dev/null +++ b/include/asm-arm/a.out-core.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* a.out coredump register dumper | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_A_OUT_CORE_H | ||
| 13 | #define _ASM_A_OUT_CORE_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #include <linux/user.h> | ||
| 18 | #include <linux/elfcore.h> | ||
| 19 | |||
| 20 | /* | ||
| 21 | * fill in the user structure for an a.out core dump | ||
| 22 | */ | ||
| 23 | static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) | ||
| 24 | { | ||
| 25 | struct task_struct *tsk = current; | ||
| 26 | |||
| 27 | dump->magic = CMAGIC; | ||
| 28 | dump->start_code = tsk->mm->start_code; | ||
| 29 | dump->start_stack = regs->ARM_sp & ~(PAGE_SIZE - 1); | ||
| 30 | |||
| 31 | dump->u_tsize = (tsk->mm->end_code - tsk->mm->start_code) >> PAGE_SHIFT; | ||
| 32 | dump->u_dsize = (tsk->mm->brk - tsk->mm->start_data + PAGE_SIZE - 1) >> PAGE_SHIFT; | ||
| 33 | dump->u_ssize = 0; | ||
| 34 | |||
| 35 | dump->u_debugreg[0] = tsk->thread.debug.bp[0].address; | ||
| 36 | dump->u_debugreg[1] = tsk->thread.debug.bp[1].address; | ||
| 37 | dump->u_debugreg[2] = tsk->thread.debug.bp[0].insn.arm; | ||
| 38 | dump->u_debugreg[3] = tsk->thread.debug.bp[1].insn.arm; | ||
| 39 | dump->u_debugreg[4] = tsk->thread.debug.nsaved; | ||
| 40 | |||
| 41 | if (dump->start_stack < 0x04000000) | ||
| 42 | dump->u_ssize = (0x04000000 - dump->start_stack) >> PAGE_SHIFT; | ||
| 43 | |||
| 44 | dump->regs = *regs; | ||
| 45 | dump->u_fpvalid = dump_fpu (regs, &dump->u_fp); | ||
| 46 | } | ||
| 47 | |||
| 48 | #endif /* __KERNEL__ */ | ||
| 49 | #endif /* _ASM_A_OUT_CORE_H */ | ||
diff --git a/include/asm-arm/a.out.h b/include/asm-arm/a.out.h index d7165e86df25..79489fdcc8b8 100644 --- a/include/asm-arm/a.out.h +++ b/include/asm-arm/a.out.h | |||
| @@ -27,12 +27,6 @@ struct exec | |||
| 27 | 27 | ||
| 28 | #define M_ARM 103 | 28 | #define M_ARM 103 |
| 29 | 29 | ||
| 30 | #ifdef __KERNEL__ | ||
| 31 | #define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \ | ||
| 32 | TASK_SIZE : TASK_SIZE_26) | ||
| 33 | #define STACK_TOP_MAX TASK_SIZE | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef LIBRARY_START_TEXT | 30 | #ifndef LIBRARY_START_TEXT |
| 37 | #define LIBRARY_START_TEXT (0x00c00000) | 31 | #define LIBRARY_START_TEXT (0x00c00000) |
| 38 | #endif | 32 | #endif |
diff --git a/include/asm-arm/arch-omap/board-apollon.h b/include/asm-arm/arch-omap/board-apollon.h index dcb587b311f1..547125a4695e 100644 --- a/include/asm-arm/arch-omap/board-apollon.h +++ b/include/asm-arm/arch-omap/board-apollon.h | |||
| @@ -29,6 +29,8 @@ | |||
| 29 | #ifndef __ASM_ARCH_OMAP_APOLLON_H | 29 | #ifndef __ASM_ARCH_OMAP_APOLLON_H |
| 30 | #define __ASM_ARCH_OMAP_APOLLON_H | 30 | #define __ASM_ARCH_OMAP_APOLLON_H |
| 31 | 31 | ||
| 32 | extern void apollon_mmc_init(void); | ||
| 33 | |||
| 32 | /* Placeholder for APOLLON specific defines */ | 34 | /* Placeholder for APOLLON specific defines */ |
| 33 | #define APOLLON_ETHR_GPIO_IRQ 74 | 35 | #define APOLLON_ETHR_GPIO_IRQ 74 |
| 34 | 36 | ||
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h index b2888ef9e9b4..c322796d0d26 100644 --- a/include/asm-arm/arch-omap/board-h2.h +++ b/include/asm-arm/arch-omap/board-h2.h | |||
| @@ -34,5 +34,8 @@ | |||
| 34 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | 34 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ |
| 35 | #define OMAP1610_ETHR_START 0x04000300 | 35 | #define OMAP1610_ETHR_START 0x04000300 |
| 36 | 36 | ||
| 37 | extern void h2_mmc_init(void); | ||
| 38 | extern void h2_mmc_slot_cover_handler(void *arg, int state); | ||
| 39 | |||
| 37 | #endif /* __ASM_ARCH_OMAP_H2_H */ | 40 | #endif /* __ASM_ARCH_OMAP_H2_H */ |
| 38 | 41 | ||
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h index 761ea0a17897..1c2b55c61ca0 100644 --- a/include/asm-arm/arch-omap/board-h3.h +++ b/include/asm-arm/arch-omap/board-h3.h | |||
| @@ -36,5 +36,7 @@ | |||
| 36 | 36 | ||
| 37 | #define NR_IRQS (MAXIRQNUM + 1) | 37 | #define NR_IRQS (MAXIRQNUM + 1) |
| 38 | 38 | ||
| 39 | extern void __init h3_mmc_init(void); | ||
| 40 | extern void h3_mmc_slot_cover_handler(void *arg, int state); | ||
| 39 | 41 | ||
| 40 | #endif /* __ASM_ARCH_OMAP_H3_H */ | 42 | #endif /* __ASM_ARCH_OMAP_H3_H */ |
diff --git a/include/asm-arm/arch-omap/board-sx1.h b/include/asm-arm/arch-omap/board-sx1.h index 2bb8dd6e2d14..355adbdaae33 100644 --- a/include/asm-arm/arch-omap/board-sx1.h +++ b/include/asm-arm/arch-omap/board-sx1.h | |||
| @@ -41,6 +41,12 @@ int sx1_getkeylight(u8 *keylight); | |||
| 41 | 41 | ||
| 42 | int sx1_setmmipower(u8 onoff); | 42 | int sx1_setmmipower(u8 onoff); |
| 43 | int sx1_setusbpower(u8 onoff); | 43 | int sx1_setusbpower(u8 onoff); |
| 44 | int sx1_setmmcpower(u8 onoff); | 44 | int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value); |
| 45 | int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value); | ||
| 46 | |||
| 47 | /* MMC prototypes */ | ||
| 48 | |||
| 49 | extern void sx1_mmc_init(void); | ||
| 50 | extern void sx1_mmc_slot_cover_handler(void *arg, int state); | ||
| 45 | 51 | ||
| 46 | #endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */ | 52 | #endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */ |
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h index 08d58abd8218..442aecbb8f44 100644 --- a/include/asm-arm/arch-omap/common.h +++ b/include/asm-arm/arch-omap/common.h | |||
| @@ -27,10 +27,21 @@ | |||
| 27 | #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H | 27 | #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H |
| 28 | #define __ARCH_ARM_MACH_OMAP_COMMON_H | 28 | #define __ARCH_ARM_MACH_OMAP_COMMON_H |
| 29 | 29 | ||
| 30 | #ifdef CONFIG_I2C_OMAP | ||
| 31 | #include <linux/i2c.h> | ||
| 32 | #endif | ||
| 33 | |||
| 30 | struct sys_timer; | 34 | struct sys_timer; |
| 31 | 35 | ||
| 32 | extern void omap_map_common_io(void); | 36 | extern void omap_map_common_io(void); |
| 33 | extern struct sys_timer omap_timer; | 37 | extern struct sys_timer omap_timer; |
| 34 | extern void omap_serial_init(void); | 38 | extern void omap_serial_init(void); |
| 39 | #ifdef CONFIG_I2C_OMAP | ||
| 40 | extern int omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
| 41 | struct i2c_board_info const *info, | ||
| 42 | unsigned len); | ||
| 43 | #else | ||
| 44 | #define omap_register_i2c_bus(a, b, c, d) 0 | ||
| 45 | #endif | ||
| 35 | 46 | ||
| 36 | #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ | 47 | #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ |
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h index ec7eb675d922..e8a4cf52778b 100644 --- a/include/asm-arm/arch-omap/cpu.h +++ b/include/asm-arm/arch-omap/cpu.h | |||
| @@ -28,7 +28,7 @@ | |||
| 28 | 28 | ||
| 29 | extern unsigned int system_rev; | 29 | extern unsigned int system_rev; |
| 30 | 30 | ||
| 31 | #define omap2_cpu_rev() ((system_rev >> 8) & 0x0f) | 31 | #define omap2_cpu_rev() ((system_rev >> 12) & 0x0f) |
| 32 | 32 | ||
| 33 | /* | 33 | /* |
| 34 | * Test if multicore OMAP support is needed | 34 | * Test if multicore OMAP support is needed |
| @@ -61,12 +61,33 @@ extern unsigned int system_rev; | |||
| 61 | # define OMAP_NAME omap16xx | 61 | # define OMAP_NAME omap16xx |
| 62 | # endif | 62 | # endif |
| 63 | #endif | 63 | #endif |
| 64 | #ifdef CONFIG_ARCH_OMAP24XX | 64 | #if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)) |
| 65 | # if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) | 65 | # if (defined(OMAP_NAME) || defined(MULTI_OMAP1)) |
| 66 | # error "OMAP1 and OMAP2 can't be selected at the same time" | 66 | # error "OMAP1 and OMAP2 can't be selected at the same time" |
| 67 | # endif | ||
| 68 | #endif | ||
| 69 | #ifdef CONFIG_ARCH_OMAP2420 | ||
| 70 | # ifdef OMAP_NAME | ||
| 71 | # undef MULTI_OMAP2 | ||
| 72 | # define MULTI_OMAP2 | ||
| 67 | # else | 73 | # else |
| 74 | # define OMAP_NAME omap2420 | ||
| 75 | # endif | ||
| 76 | #endif | ||
| 77 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 78 | # ifdef OMAP_NAME | ||
| 79 | # undef MULTI_OMAP2 | ||
| 80 | # define MULTI_OMAP2 | ||
| 81 | # else | ||
| 82 | # define OMAP_NAME omap2430 | ||
| 83 | # endif | ||
| 84 | #endif | ||
| 85 | #ifdef CONFIG_ARCH_OMAP3430 | ||
| 86 | # ifdef OMAP_NAME | ||
| 68 | # undef MULTI_OMAP2 | 87 | # undef MULTI_OMAP2 |
| 69 | # define OMAP_NAME omap24xx | 88 | # define MULTI_OMAP2 |
| 89 | # else | ||
| 90 | # define OMAP_NAME omap3430 | ||
| 70 | # endif | 91 | # endif |
| 71 | #endif | 92 | #endif |
| 72 | 93 | ||
| @@ -79,8 +100,9 @@ extern unsigned int system_rev; | |||
| 79 | * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 | 100 | * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 |
| 80 | * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 | 101 | * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423 |
| 81 | * cpu_is_omap243x(): True for OMAP2430 | 102 | * cpu_is_omap243x(): True for OMAP2430 |
| 103 | * cpu_is_omap343x(): True for OMAP3430 | ||
| 82 | */ | 104 | */ |
| 83 | #define GET_OMAP_CLASS (system_rev & 0xff) | 105 | #define GET_OMAP_CLASS ((system_rev >> 24) & 0xff) |
| 84 | 106 | ||
| 85 | #define IS_OMAP_CLASS(class, id) \ | 107 | #define IS_OMAP_CLASS(class, id) \ |
| 86 | static inline int is_omap ##class (void) \ | 108 | static inline int is_omap ##class (void) \ |
| @@ -100,9 +122,11 @@ IS_OMAP_CLASS(7xx, 0x07) | |||
| 100 | IS_OMAP_CLASS(15xx, 0x15) | 122 | IS_OMAP_CLASS(15xx, 0x15) |
| 101 | IS_OMAP_CLASS(16xx, 0x16) | 123 | IS_OMAP_CLASS(16xx, 0x16) |
| 102 | IS_OMAP_CLASS(24xx, 0x24) | 124 | IS_OMAP_CLASS(24xx, 0x24) |
| 125 | IS_OMAP_CLASS(34xx, 0x34) | ||
| 103 | 126 | ||
| 104 | IS_OMAP_SUBCLASS(242x, 0x242) | 127 | IS_OMAP_SUBCLASS(242x, 0x242) |
| 105 | IS_OMAP_SUBCLASS(243x, 0x243) | 128 | IS_OMAP_SUBCLASS(243x, 0x243) |
| 129 | IS_OMAP_SUBCLASS(343x, 0x343) | ||
| 106 | 130 | ||
| 107 | #define cpu_is_omap7xx() 0 | 131 | #define cpu_is_omap7xx() 0 |
| 108 | #define cpu_is_omap15xx() 0 | 132 | #define cpu_is_omap15xx() 0 |
| @@ -110,6 +134,8 @@ IS_OMAP_SUBCLASS(243x, 0x243) | |||
| 110 | #define cpu_is_omap24xx() 0 | 134 | #define cpu_is_omap24xx() 0 |
| 111 | #define cpu_is_omap242x() 0 | 135 | #define cpu_is_omap242x() 0 |
| 112 | #define cpu_is_omap243x() 0 | 136 | #define cpu_is_omap243x() 0 |
| 137 | #define cpu_is_omap34xx() 0 | ||
| 138 | #define cpu_is_omap343x() 0 | ||
| 113 | 139 | ||
| 114 | #if defined(MULTI_OMAP1) | 140 | #if defined(MULTI_OMAP1) |
| 115 | # if defined(CONFIG_ARCH_OMAP730) | 141 | # if defined(CONFIG_ARCH_OMAP730) |
| @@ -137,14 +163,44 @@ IS_OMAP_SUBCLASS(243x, 0x243) | |||
| 137 | # undef cpu_is_omap16xx | 163 | # undef cpu_is_omap16xx |
| 138 | # define cpu_is_omap16xx() 1 | 164 | # define cpu_is_omap16xx() 1 |
| 139 | # endif | 165 | # endif |
| 166 | #endif | ||
| 167 | |||
| 168 | #if defined(MULTI_OMAP2) | ||
| 140 | # if defined(CONFIG_ARCH_OMAP24XX) | 169 | # if defined(CONFIG_ARCH_OMAP24XX) |
| 141 | # undef cpu_is_omap24xx | 170 | # undef cpu_is_omap24xx |
| 142 | # undef cpu_is_omap242x | 171 | # undef cpu_is_omap242x |
| 143 | # undef cpu_is_omap243x | 172 | # undef cpu_is_omap243x |
| 144 | # define cpu_is_omap24xx() 1 | 173 | # define cpu_is_omap24xx() is_omap24xx() |
| 145 | # define cpu_is_omap242x() is_omap242x() | 174 | # define cpu_is_omap242x() is_omap242x() |
| 146 | # define cpu_is_omap243x() is_omap243x() | 175 | # define cpu_is_omap243x() is_omap243x() |
| 147 | # endif | 176 | # endif |
| 177 | # if defined(CONFIG_ARCH_OMAP34XX) | ||
| 178 | # undef cpu_is_omap34xx | ||
| 179 | # undef cpu_is_omap343x | ||
| 180 | # define cpu_is_omap34xx() is_omap34xx() | ||
| 181 | # define cpu_is_omap343x() is_omap343x() | ||
| 182 | # endif | ||
| 183 | #else | ||
| 184 | # if defined(CONFIG_ARCH_OMAP24XX) | ||
| 185 | # undef cpu_is_omap24xx | ||
| 186 | # define cpu_is_omap24xx() 1 | ||
| 187 | # endif | ||
| 188 | # if defined(CONFIG_ARCH_OMAP2420) | ||
| 189 | # undef cpu_is_omap242x | ||
| 190 | # define cpu_is_omap242x() 1 | ||
| 191 | # endif | ||
| 192 | # if defined(CONFIG_ARCH_OMAP2430) | ||
| 193 | # undef cpu_is_omap243x | ||
| 194 | # define cpu_is_omap243x() 1 | ||
| 195 | # endif | ||
| 196 | # if defined(CONFIG_ARCH_OMAP34XX) | ||
| 197 | # undef cpu_is_omap34xx | ||
| 198 | # define cpu_is_omap34xx() 1 | ||
| 199 | # endif | ||
| 200 | # if defined(CONFIG_ARCH_OMAP3430) | ||
| 201 | # undef cpu_is_omap343x | ||
| 202 | # define cpu_is_omap343x() 1 | ||
| 203 | # endif | ||
| 148 | #endif | 204 | #endif |
| 149 | 205 | ||
| 150 | /* | 206 | /* |
| @@ -162,6 +218,7 @@ IS_OMAP_SUBCLASS(243x, 0x243) | |||
| 162 | * cpu_is_omap2422(): True for OMAP2422 | 218 | * cpu_is_omap2422(): True for OMAP2422 |
| 163 | * cpu_is_omap2423(): True for OMAP2423 | 219 | * cpu_is_omap2423(): True for OMAP2423 |
| 164 | * cpu_is_omap2430(): True for OMAP2430 | 220 | * cpu_is_omap2430(): True for OMAP2430 |
| 221 | * cpu_is_omap3430(): True for OMAP3430 | ||
| 165 | */ | 222 | */ |
| 166 | #define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff) | 223 | #define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff) |
| 167 | 224 | ||
| @@ -183,6 +240,7 @@ IS_OMAP_TYPE(2420, 0x2420) | |||
| 183 | IS_OMAP_TYPE(2422, 0x2422) | 240 | IS_OMAP_TYPE(2422, 0x2422) |
| 184 | IS_OMAP_TYPE(2423, 0x2423) | 241 | IS_OMAP_TYPE(2423, 0x2423) |
| 185 | IS_OMAP_TYPE(2430, 0x2430) | 242 | IS_OMAP_TYPE(2430, 0x2430) |
| 243 | IS_OMAP_TYPE(3430, 0x3430) | ||
| 186 | 244 | ||
| 187 | #define cpu_is_omap310() 0 | 245 | #define cpu_is_omap310() 0 |
| 188 | #define cpu_is_omap730() 0 | 246 | #define cpu_is_omap730() 0 |
| @@ -196,6 +254,7 @@ IS_OMAP_TYPE(2430, 0x2430) | |||
| 196 | #define cpu_is_omap2422() 0 | 254 | #define cpu_is_omap2422() 0 |
| 197 | #define cpu_is_omap2423() 0 | 255 | #define cpu_is_omap2423() 0 |
| 198 | #define cpu_is_omap2430() 0 | 256 | #define cpu_is_omap2430() 0 |
| 257 | #define cpu_is_omap3430() 0 | ||
| 199 | 258 | ||
| 200 | #if defined(MULTI_OMAP1) | 259 | #if defined(MULTI_OMAP1) |
| 201 | # if defined(CONFIG_ARCH_OMAP730) | 260 | # if defined(CONFIG_ARCH_OMAP730) |
| @@ -244,9 +303,65 @@ IS_OMAP_TYPE(2430, 0x2430) | |||
| 244 | # define cpu_is_omap2430() is_omap2430() | 303 | # define cpu_is_omap2430() is_omap2430() |
| 245 | #endif | 304 | #endif |
| 246 | 305 | ||
| 306 | #if defined(CONFIG_ARCH_OMAP34XX) | ||
| 307 | # undef cpu_is_omap3430 | ||
| 308 | # define cpu_is_omap3430() is_omap3430() | ||
| 309 | #endif | ||
| 310 | |||
| 247 | /* Macros to detect if we have OMAP1 or OMAP2 */ | 311 | /* Macros to detect if we have OMAP1 or OMAP2 */ |
| 248 | #define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \ | 312 | #define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \ |
| 249 | cpu_is_omap16xx()) | 313 | cpu_is_omap16xx()) |
| 250 | #define cpu_class_is_omap2() cpu_is_omap24xx() | 314 | #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) |
| 315 | |||
| 316 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 317 | /* | ||
| 318 | * Macros to detect silicon revision of OMAP2/3 processors. | ||
| 319 | * is_sil_rev_greater_than: true if passed cpu type & its rev is greater. | ||
| 320 | * is_sil_rev_lesser_than: true if passed cpu type & its rev is lesser. | ||
| 321 | * is_sil_rev_equal_to: true if passed cpu type & its rev is equal. | ||
| 322 | * get_sil_rev: return the silicon rev value. | ||
| 323 | */ | ||
| 324 | #define get_sil_omap_type(rev) ((rev & 0xffff0000) >> 16) | ||
| 325 | #define get_sil_revision(rev) ((rev & 0x0000f000) >> 12) | ||
| 326 | |||
| 327 | #define is_sil_rev_greater_than(rev) \ | ||
| 328 | ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ | ||
| 329 | (get_sil_revision(system_rev) > get_sil_revision(rev))) | ||
| 330 | |||
| 331 | #define is_sil_rev_less_than(rev) \ | ||
| 332 | ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ | ||
| 333 | (get_sil_revision(system_rev) < get_sil_revision(rev))) | ||
| 334 | |||
| 335 | #define is_sil_rev_equal_to(rev) \ | ||
| 336 | ((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \ | ||
| 337 | (get_sil_revision(system_rev) == get_sil_revision(rev))) | ||
| 338 | |||
| 339 | #define get_sil_rev() \ | ||
| 340 | get_sil_revision(system_rev) | ||
| 341 | |||
| 342 | /* Various silicon macros defined here */ | ||
| 343 | #define OMAP2420_REV_ES1_0 0x24200000 | ||
| 344 | #define OMAP2420_REV_ES2_0 0x24201000 | ||
| 345 | #define OMAP2430_REV_ES1_0 0x24300000 | ||
| 346 | #define OMAP3430_REV_ES1_0 0x34300000 | ||
| 347 | #define OMAP3430_REV_ES2_0 0x34301000 | ||
| 348 | |||
| 349 | /* | ||
| 350 | * Macro to detect device type i.e. EMU/HS/TST/GP/BAD | ||
| 351 | */ | ||
| 352 | #define DEVICE_TYPE_TEST 0 | ||
| 353 | #define DEVICE_TYPE_EMU 1 | ||
| 354 | #define DEVICE_TYPE_SEC 2 | ||
| 355 | #define DEVICE_TYPE_GP 3 | ||
| 356 | #define DEVICE_TYPE_BAD 4 | ||
| 357 | |||
| 358 | #define get_device_type() ((system_rev & 0x700) >> 8) | ||
| 359 | #define is_device_type_test() (get_device_type() == DEVICE_TYPE_TEST) | ||
| 360 | #define is_device_type_emu() (get_device_type() == DEVICE_TYPE_EMU) | ||
| 361 | #define is_device_type_sec() (get_device_type() == DEVICE_TYPE_SEC) | ||
| 362 | #define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP) | ||
| 363 | #define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD) | ||
| 364 | |||
| 365 | #endif | ||
| 251 | 366 | ||
| 252 | #endif | 367 | #endif |
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index f33b467fddb7..24acf090030d 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h | |||
| @@ -45,22 +45,28 @@ | |||
| 45 | #define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) | 45 | #define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) |
| 46 | 46 | ||
| 47 | /* Hardware registers for omap2 */ | 47 | /* Hardware registers for omap2 */ |
| 48 | #define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000) | 48 | #if defined(CONFIG_ARCH_OMAP3) |
| 49 | #define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00) | 49 | #define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000) |
| 50 | #define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78) | 50 | #else /* CONFIG_ARCH_OMAP2 */ |
| 51 | #define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08) | 51 | #define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000) |
| 52 | #define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c) | 52 | #endif |
| 53 | #define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10) | 53 | |
| 54 | #define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14) | 54 | #define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00) |
| 55 | #define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18) | 55 | #define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78) |
| 56 | #define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c) | 56 | #define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08) |
| 57 | #define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20) | 57 | #define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c) |
| 58 | #define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24) | 58 | #define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10) |
| 59 | #define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28) | 59 | #define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14) |
| 60 | #define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64) | 60 | #define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18) |
| 61 | #define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c) | 61 | #define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c) |
| 62 | #define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70) | 62 | #define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20) |
| 63 | #define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74) | 63 | #define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24) |
| 64 | #define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28) | ||
| 65 | #define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c) | ||
| 66 | #define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64) | ||
| 67 | #define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c) | ||
| 68 | #define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70) | ||
| 69 | #define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74) | ||
| 64 | 70 | ||
| 65 | #ifdef CONFIG_ARCH_OMAP1 | 71 | #ifdef CONFIG_ARCH_OMAP1 |
| 66 | 72 | ||
| @@ -86,19 +92,19 @@ | |||
| 86 | #define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ | 92 | #define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ |
| 87 | 93 | ||
| 88 | /* Common channel specific registers for omap2 */ | 94 | /* Common channel specific registers for omap2 */ |
| 89 | #define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80) | 95 | #define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80) |
| 90 | #define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84) | 96 | #define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84) |
| 91 | #define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88) | 97 | #define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88) |
| 92 | #define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c) | 98 | #define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c) |
| 93 | #define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90) | 99 | #define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90) |
| 94 | #define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94) | 100 | #define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94) |
| 95 | #define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98) | 101 | #define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98) |
| 96 | #define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4) | 102 | #define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4) |
| 97 | #define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8) | 103 | #define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8) |
| 98 | #define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac) | 104 | #define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac) |
| 99 | #define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0) | 105 | #define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0) |
| 100 | #define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4) | 106 | #define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4) |
| 101 | #define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8) | 107 | #define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8) |
| 102 | 108 | ||
| 103 | #endif | 109 | #endif |
| 104 | 110 | ||
| @@ -113,11 +119,11 @@ | |||
| 113 | #define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) | 119 | #define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) |
| 114 | 120 | ||
| 115 | /* Channel specific registers only on omap2 */ | 121 | /* Channel specific registers only on omap2 */ |
| 116 | #define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c) | 122 | #define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c) |
| 117 | #define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0) | 123 | #define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0) |
| 118 | #define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc) | 124 | #define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc) |
| 119 | #define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0) | 125 | #define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0) |
| 120 | #define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4) | 126 | #define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4) |
| 121 | 127 | ||
| 122 | /*----------------------------------------------------------------------------*/ | 128 | /*----------------------------------------------------------------------------*/ |
| 123 | 129 | ||
| @@ -297,6 +303,10 @@ | |||
| 297 | #define OMAP_DMA_SYNC_ELEMENT 0x00 | 303 | #define OMAP_DMA_SYNC_ELEMENT 0x00 |
| 298 | #define OMAP_DMA_SYNC_FRAME 0x01 | 304 | #define OMAP_DMA_SYNC_FRAME 0x01 |
| 299 | #define OMAP_DMA_SYNC_BLOCK 0x02 | 305 | #define OMAP_DMA_SYNC_BLOCK 0x02 |
| 306 | #define OMAP_DMA_SYNC_PACKET 0x03 | ||
| 307 | |||
| 308 | #define OMAP_DMA_SRC_SYNC 0x01 | ||
| 309 | #define OMAP_DMA_DST_SYNC 0x00 | ||
| 300 | 310 | ||
| 301 | #define OMAP_DMA_PORT_EMIFF 0x00 | 311 | #define OMAP_DMA_PORT_EMIFF 0x00 |
| 302 | #define OMAP_DMA_PORT_EMIFS 0x01 | 312 | #define OMAP_DMA_PORT_EMIFS 0x01 |
| @@ -310,6 +320,29 @@ | |||
| 310 | #define OMAP_DMA_AMODE_SINGLE_IDX 0x02 | 320 | #define OMAP_DMA_AMODE_SINGLE_IDX 0x02 |
| 311 | #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 | 321 | #define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 |
| 312 | 322 | ||
| 323 | #define DMA_DEFAULT_FIFO_DEPTH 0x10 | ||
| 324 | #define DMA_DEFAULT_ARB_RATE 0x01 | ||
| 325 | /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */ | ||
| 326 | #define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */ | ||
| 327 | #define DMA_THREAD_RESERVE_ONET (0x01 << 12) | ||
| 328 | #define DMA_THREAD_RESERVE_TWOT (0x02 << 12) | ||
| 329 | #define DMA_THREAD_RESERVE_THREET (0x03 << 12) | ||
| 330 | #define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */ | ||
| 331 | #define DMA_THREAD_FIFO_75 (0x01 << 14) | ||
| 332 | #define DMA_THREAD_FIFO_25 (0x02 << 14) | ||
| 333 | #define DMA_THREAD_FIFO_50 (0x03 << 14) | ||
| 334 | |||
| 335 | /* Chaining modes*/ | ||
| 336 | #ifndef CONFIG_ARCH_OMAP1 | ||
| 337 | #define OMAP_DMA_STATIC_CHAIN 0x1 | ||
| 338 | #define OMAP_DMA_DYNAMIC_CHAIN 0x2 | ||
| 339 | #define OMAP_DMA_CHAIN_ACTIVE 0x1 | ||
| 340 | #define OMAP_DMA_CHAIN_INACTIVE 0x0 | ||
| 341 | #endif | ||
| 342 | |||
| 343 | #define DMA_CH_PRIO_HIGH 0x1 | ||
| 344 | #define DMA_CH_PRIO_LOW 0x0 /* Def */ | ||
| 345 | |||
| 313 | /* LCD DMA block numbers */ | 346 | /* LCD DMA block numbers */ |
| 314 | enum { | 347 | enum { |
| 315 | OMAP_LCD_DMA_B1_TOP, | 348 | OMAP_LCD_DMA_B1_TOP, |
| @@ -359,6 +392,13 @@ struct omap_dma_channel_params { | |||
| 359 | int src_or_dst_synch; /* source synch(1) or destination synch(0) */ | 392 | int src_or_dst_synch; /* source synch(1) or destination synch(0) */ |
| 360 | 393 | ||
| 361 | int ie; /* interrupt enabled */ | 394 | int ie; /* interrupt enabled */ |
| 395 | |||
| 396 | unsigned char read_prio;/* read priority */ | ||
| 397 | unsigned char write_prio;/* write priority */ | ||
| 398 | |||
| 399 | #ifndef CONFIG_ARCH_OMAP1 | ||
| 400 | enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */ | ||
| 401 | #endif | ||
| 362 | }; | 402 | }; |
| 363 | 403 | ||
| 364 | 404 | ||
| @@ -409,6 +449,33 @@ extern dma_addr_t omap_get_dma_dst_pos(int lch); | |||
| 409 | extern int omap_get_dma_src_addr_counter(int lch); | 449 | extern int omap_get_dma_src_addr_counter(int lch); |
| 410 | extern void omap_clear_dma(int lch); | 450 | extern void omap_clear_dma(int lch); |
| 411 | extern int omap_dma_running(void); | 451 | extern int omap_dma_running(void); |
| 452 | extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, | ||
| 453 | int tparams); | ||
| 454 | extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, | ||
| 455 | unsigned char write_prio); | ||
| 456 | |||
| 457 | /* Chaining APIs */ | ||
| 458 | #ifndef CONFIG_ARCH_OMAP1 | ||
| 459 | extern int omap_request_dma_chain(int dev_id, const char *dev_name, | ||
| 460 | void (*callback) (int chain_id, u16 ch_status, | ||
| 461 | void *data), | ||
| 462 | int *chain_id, int no_of_chans, | ||
| 463 | int chain_mode, | ||
| 464 | struct omap_dma_channel_params params); | ||
| 465 | extern int omap_free_dma_chain(int chain_id); | ||
| 466 | extern int omap_dma_chain_a_transfer(int chain_id, int src_start, | ||
| 467 | int dest_start, int elem_count, | ||
| 468 | int frame_count, void *callbk_data); | ||
| 469 | extern int omap_start_dma_chain_transfers(int chain_id); | ||
| 470 | extern int omap_stop_dma_chain_transfers(int chain_id); | ||
| 471 | extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi); | ||
| 472 | extern int omap_get_dma_chain_dst_pos(int chain_id); | ||
| 473 | extern int omap_get_dma_chain_src_pos(int chain_id); | ||
| 474 | |||
| 475 | extern int omap_modify_dma_chain_params(int chain_id, | ||
| 476 | struct omap_dma_channel_params params); | ||
| 477 | extern int omap_dma_chain_status(int chain_id); | ||
| 478 | #endif | ||
| 412 | 479 | ||
| 413 | /* LCD DMA functions */ | 480 | /* LCD DMA functions */ |
| 414 | extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), | 481 | extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), |
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h index 97b397dd7e87..164da09be095 100644 --- a/include/asm-arm/arch-omap/gpio.h +++ b/include/asm-arm/arch-omap/gpio.h | |||
| @@ -62,6 +62,8 @@ | |||
| 62 | #define OMAP_MPUIO_LATCH 0x34 | 62 | #define OMAP_MPUIO_LATCH 0x34 |
| 63 | #endif | 63 | #endif |
| 64 | 64 | ||
| 65 | #define OMAP34XX_NR_GPIOS 6 | ||
| 66 | |||
| 65 | #define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) | 67 | #define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr)) |
| 66 | #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) | 68 | #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES) |
| 67 | 69 | ||
| @@ -75,6 +77,8 @@ extern void omap_free_gpio(int gpio); | |||
| 75 | extern void omap_set_gpio_direction(int gpio, int is_input); | 77 | extern void omap_set_gpio_direction(int gpio, int is_input); |
| 76 | extern void omap_set_gpio_dataout(int gpio, int enable); | 78 | extern void omap_set_gpio_dataout(int gpio, int enable); |
| 77 | extern int omap_get_gpio_datain(int gpio); | 79 | extern int omap_get_gpio_datain(int gpio); |
| 80 | extern void omap_set_gpio_debounce(int gpio, int enable); | ||
| 81 | extern void omap_set_gpio_debounce_time(int gpio, int enable); | ||
| 78 | 82 | ||
| 79 | /*-------------------------------------------------------------------------*/ | 83 | /*-------------------------------------------------------------------------*/ |
| 80 | 84 | ||
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index 3ede58b51db2..87973654e625 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h | |||
| @@ -263,6 +263,8 @@ | |||
| 263 | #define INT_24XX_GPTIMER10 46 | 263 | #define INT_24XX_GPTIMER10 46 |
| 264 | #define INT_24XX_GPTIMER11 47 | 264 | #define INT_24XX_GPTIMER11 47 |
| 265 | #define INT_24XX_GPTIMER12 48 | 265 | #define INT_24XX_GPTIMER12 48 |
| 266 | #define INT_24XX_I2C1_IRQ 56 | ||
| 267 | #define INT_24XX_I2C2_IRQ 57 | ||
| 266 | #define INT_24XX_MCBSP1_IRQ_TX 59 | 268 | #define INT_24XX_MCBSP1_IRQ_TX 59 |
| 267 | #define INT_24XX_MCBSP1_IRQ_RX 60 | 269 | #define INT_24XX_MCBSP1_IRQ_RX 60 |
| 268 | #define INT_24XX_MCBSP2_IRQ_TX 62 | 270 | #define INT_24XX_MCBSP2_IRQ_TX 62 |
diff --git a/include/asm-arm/arch-omap/nand.h b/include/asm-arm/arch-omap/nand.h new file mode 100644 index 000000000000..17ae26e35353 --- /dev/null +++ b/include/asm-arm/arch-omap/nand.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-omap/nand.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Micron Technology Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/mtd/partitions.h> | ||
| 12 | |||
| 13 | struct omap_nand_platform_data { | ||
| 14 | unsigned int options; | ||
| 15 | int cs; | ||
| 16 | int gpio_irq; | ||
| 17 | struct mtd_partition *parts; | ||
| 18 | int nr_parts; | ||
| 19 | int (*nand_setup)(void __iomem *); | ||
| 20 | int (*dev_ready)(struct omap_nand_platform_data *); | ||
| 21 | int dma_channel; | ||
| 22 | void __iomem *gpmc_cs_baseaddr; | ||
| 23 | void __iomem *gpmc_baseaddr; | ||
| 24 | }; | ||
diff --git a/include/asm-arm/mutex.h b/include/asm-arm/mutex.h index cb29d84e690d..020bd98710a1 100644 --- a/include/asm-arm/mutex.h +++ b/include/asm-arm/mutex.h | |||
| @@ -24,7 +24,7 @@ | |||
| 24 | * reattempted until it succeeds. | 24 | * reattempted until it succeeds. |
| 25 | */ | 25 | */ |
| 26 | static inline void | 26 | static inline void |
| 27 | __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | 27 | __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *)) |
| 28 | { | 28 | { |
| 29 | int __ex_flag, __res; | 29 | int __ex_flag, __res; |
| 30 | 30 | ||
| @@ -44,7 +44,7 @@ __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | |||
| 44 | } | 44 | } |
| 45 | 45 | ||
| 46 | static inline int | 46 | static inline int |
| 47 | __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *)) | 47 | __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) |
| 48 | { | 48 | { |
| 49 | int __ex_flag, __res; | 49 | int __ex_flag, __res; |
| 50 | 50 | ||
| @@ -70,7 +70,7 @@ __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t * | |||
| 70 | * better generated assembly. | 70 | * better generated assembly. |
| 71 | */ | 71 | */ |
| 72 | static inline void | 72 | static inline void |
| 73 | __mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | 73 | __mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *)) |
| 74 | { | 74 | { |
| 75 | int __ex_flag, __res, __orig; | 75 | int __ex_flag, __res, __orig; |
| 76 | 76 | ||
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h index 31ff12f4ffb7..c86f68ee6511 100644 --- a/include/asm-arm/page.h +++ b/include/asm-arm/page.h | |||
| @@ -171,6 +171,8 @@ typedef unsigned long pgprot_t; | |||
| 171 | 171 | ||
| 172 | #endif /* STRICT_MM_TYPECHECKS */ | 172 | #endif /* STRICT_MM_TYPECHECKS */ |
| 173 | 173 | ||
| 174 | typedef struct page *pgtable_t; | ||
| 175 | |||
| 174 | #endif /* CONFIG_MMU */ | 176 | #endif /* CONFIG_MMU */ |
| 175 | 177 | ||
| 176 | #include <asm/memory.h> | 178 | #include <asm/memory.h> |
diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h index fb6c6e3222bd..163b0305dd76 100644 --- a/include/asm-arm/pgalloc.h +++ b/include/asm-arm/pgalloc.h | |||
| @@ -66,7 +66,7 @@ pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr) | |||
| 66 | return pte; | 66 | return pte; |
| 67 | } | 67 | } |
| 68 | 68 | ||
| 69 | static inline struct page * | 69 | static inline pgtable_t |
| 70 | pte_alloc_one(struct mm_struct *mm, unsigned long addr) | 70 | pte_alloc_one(struct mm_struct *mm, unsigned long addr) |
| 71 | { | 71 | { |
| 72 | struct page *pte; | 72 | struct page *pte; |
| @@ -75,6 +75,7 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr) | |||
| 75 | if (pte) { | 75 | if (pte) { |
| 76 | void *page = page_address(pte); | 76 | void *page = page_address(pte); |
| 77 | clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE); | 77 | clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE); |
| 78 | pgtable_page_ctor(pte); | ||
| 78 | } | 79 | } |
| 79 | 80 | ||
| 80 | return pte; | 81 | return pte; |
| @@ -91,8 +92,9 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 91 | } | 92 | } |
| 92 | } | 93 | } |
| 93 | 94 | ||
| 94 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 95 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 95 | { | 96 | { |
| 97 | pgtable_page_dtor(pte); | ||
| 96 | __free_page(pte); | 98 | __free_page(pte); |
| 97 | } | 99 | } |
| 98 | 100 | ||
| @@ -123,10 +125,11 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) | |||
| 123 | } | 125 | } |
| 124 | 126 | ||
| 125 | static inline void | 127 | static inline void |
| 126 | pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep) | 128 | pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep) |
| 127 | { | 129 | { |
| 128 | __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE); | 130 | __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE); |
| 129 | } | 131 | } |
| 132 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 130 | 133 | ||
| 131 | #endif /* CONFIG_MMU */ | 134 | #endif /* CONFIG_MMU */ |
| 132 | 135 | ||
diff --git a/include/asm-arm/posix_types.h b/include/asm-arm/posix_types.h index e142a2a016ca..c37379dadcb2 100644 --- a/include/asm-arm/posix_types.h +++ b/include/asm-arm/posix_types.h | |||
| @@ -51,14 +51,10 @@ typedef long long __kernel_loff_t; | |||
| 51 | #endif | 51 | #endif |
| 52 | 52 | ||
| 53 | typedef struct { | 53 | typedef struct { |
| 54 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 55 | int val[2]; | 54 | int val[2]; |
| 56 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 57 | int __val[2]; | ||
| 58 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 59 | } __kernel_fsid_t; | 55 | } __kernel_fsid_t; |
| 60 | 56 | ||
| 61 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 57 | #if defined(__KERNEL__) |
| 62 | 58 | ||
| 63 | #undef __FD_SET | 59 | #undef __FD_SET |
| 64 | #define __FD_SET(fd, fdsetp) \ | 60 | #define __FD_SET(fd, fdsetp) \ |
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h index 1bbf16182d62..bd8029e8dc67 100644 --- a/include/asm-arm/processor.h +++ b/include/asm-arm/processor.h | |||
| @@ -22,6 +22,12 @@ | |||
| 22 | #include <asm/ptrace.h> | 22 | #include <asm/ptrace.h> |
| 23 | #include <asm/types.h> | 23 | #include <asm/types.h> |
| 24 | 24 | ||
| 25 | #ifdef __KERNEL__ | ||
| 26 | #define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \ | ||
| 27 | TASK_SIZE : TASK_SIZE_26) | ||
| 28 | #define STACK_TOP_MAX TASK_SIZE | ||
| 29 | #endif | ||
| 30 | |||
| 25 | union debug_insn { | 31 | union debug_insn { |
| 26 | u32 arm; | 32 | u32 arm; |
| 27 | u16 thumb; | 33 | u16 thumb; |
diff --git a/include/asm-avr32/a.out.h b/include/asm-avr32/a.out.h index 9f398ab28ed0..e46375a34a72 100644 --- a/include/asm-avr32/a.out.h +++ b/include/asm-avr32/a.out.h | |||
| @@ -17,11 +17,4 @@ struct exec | |||
| 17 | #define N_DRSIZE(a) ((a).a_drsize) | 17 | #define N_DRSIZE(a) ((a).a_drsize) |
| 18 | #define N_SYMSIZE(a) ((a).a_syms) | 18 | #define N_SYMSIZE(a) ((a).a_syms) |
| 19 | 19 | ||
| 20 | #ifdef __KERNEL__ | ||
| 21 | |||
| 22 | #define STACK_TOP TASK_SIZE | ||
| 23 | #define STACK_TOP_MAX STACK_TOP | ||
| 24 | |||
| 25 | #endif | ||
| 26 | |||
| 27 | #endif /* __ASM_AVR32_A_OUT_H */ | 20 | #endif /* __ASM_AVR32_A_OUT_H */ |
diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h index d6993a6b6473..7597b0bd2f01 100644 --- a/include/asm-avr32/arch-at32ap/board.h +++ b/include/asm-avr32/arch-at32ap/board.h | |||
| @@ -51,6 +51,9 @@ struct platform_device * | |||
| 51 | at32_add_device_ide(unsigned int id, unsigned int extint, | 51 | at32_add_device_ide(unsigned int id, unsigned int extint, |
| 52 | struct ide_platform_data *data); | 52 | struct ide_platform_data *data); |
| 53 | 53 | ||
| 54 | /* mask says which PWM channels to mux */ | ||
| 55 | struct platform_device *at32_add_device_pwm(u32 mask); | ||
| 56 | |||
| 54 | /* depending on what's hooked up, not all SSC pins will be used */ | 57 | /* depending on what's hooked up, not all SSC pins will be used */ |
| 55 | #define ATMEL_SSC_TK 0x01 | 58 | #define ATMEL_SSC_TK 0x01 |
| 56 | #define ATMEL_SSC_TF 0x02 | 59 | #define ATMEL_SSC_TF 0x02 |
diff --git a/include/asm-avr32/page.h b/include/asm-avr32/page.h index ee23499cec34..5582968feee8 100644 --- a/include/asm-avr32/page.h +++ b/include/asm-avr32/page.h | |||
| @@ -34,6 +34,7 @@ extern void copy_page(void *to, void *from); | |||
| 34 | typedef struct { unsigned long pte; } pte_t; | 34 | typedef struct { unsigned long pte; } pte_t; |
| 35 | typedef struct { unsigned long pgd; } pgd_t; | 35 | typedef struct { unsigned long pgd; } pgd_t; |
| 36 | typedef struct { unsigned long pgprot; } pgprot_t; | 36 | typedef struct { unsigned long pgprot; } pgprot_t; |
| 37 | typedef struct page *pgtable_t; | ||
| 37 | 38 | ||
| 38 | #define pte_val(x) ((x).pte) | 39 | #define pte_val(x) ((x).pte) |
| 39 | #define pgd_val(x) ((x).pgd) | 40 | #define pgd_val(x) ((x).pgd) |
diff --git a/include/asm-avr32/pgalloc.h b/include/asm-avr32/pgalloc.h index b77e364b4c44..51fc1f6e4b17 100644 --- a/include/asm-avr32/pgalloc.h +++ b/include/asm-avr32/pgalloc.h | |||
| @@ -17,10 +17,11 @@ | |||
| 17 | set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))) | 17 | set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))) |
| 18 | 18 | ||
| 19 | static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd, | 19 | static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd, |
| 20 | struct page *pte) | 20 | pgtable_t pte) |
| 21 | { | 21 | { |
| 22 | set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte))); | 22 | set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte))); |
| 23 | } | 23 | } |
| 24 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 24 | 25 | ||
| 25 | /* | 26 | /* |
| 26 | * Allocate and free page tables | 27 | * Allocate and free page tables |
| @@ -51,7 +52,9 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, | |||
| 51 | struct page *pte; | 52 | struct page *pte; |
| 52 | 53 | ||
| 53 | pte = alloc_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO); | 54 | pte = alloc_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO); |
| 54 | 55 | if (!pte) | |
| 56 | return NULL; | ||
| 57 | pgtable_page_ctor(pte); | ||
| 55 | return pte; | 58 | return pte; |
| 56 | } | 59 | } |
| 57 | 60 | ||
| @@ -60,12 +63,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 60 | free_page((unsigned long)pte); | 63 | free_page((unsigned long)pte); |
| 61 | } | 64 | } |
| 62 | 65 | ||
| 63 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 66 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 64 | { | 67 | { |
| 68 | pgtable_page_dtor(pte); | ||
| 65 | __free_page(pte); | 69 | __free_page(pte); |
| 66 | } | 70 | } |
| 67 | 71 | ||
| 68 | #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) | 72 | #define __pte_free_tlb(tlb,pte) \ |
| 73 | do { \ | ||
| 74 | pgtable_page_dtor(pte); \ | ||
| 75 | tlb_remove_page((tlb), pte); \ | ||
| 76 | } while (0) | ||
| 69 | 77 | ||
| 70 | #define check_pgt_cache() do { } while(0) | 78 | #define check_pgt_cache() do { } while(0) |
| 71 | 79 | ||
diff --git a/include/asm-avr32/posix_types.h b/include/asm-avr32/posix_types.h index 9e255b999639..fe0c0c014389 100644 --- a/include/asm-avr32/posix_types.h +++ b/include/asm-avr32/posix_types.h | |||
| @@ -46,11 +46,7 @@ typedef long long __kernel_loff_t; | |||
| 46 | #endif | 46 | #endif |
| 47 | 47 | ||
| 48 | typedef struct { | 48 | typedef struct { |
| 49 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 50 | int val[2]; | 49 | int val[2]; |
| 51 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 52 | int __val[2]; | ||
| 53 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 54 | } __kernel_fsid_t; | 50 | } __kernel_fsid_t; |
| 55 | 51 | ||
| 56 | #if defined(__KERNEL__) | 52 | #if defined(__KERNEL__) |
diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h index 4212551c1cd9..49a88f5a9d2f 100644 --- a/include/asm-avr32/processor.h +++ b/include/asm-avr32/processor.h | |||
| @@ -13,6 +13,11 @@ | |||
| 13 | 13 | ||
| 14 | #define TASK_SIZE 0x80000000 | 14 | #define TASK_SIZE 0x80000000 |
| 15 | 15 | ||
| 16 | #ifdef __KERNEL__ | ||
| 17 | #define STACK_TOP TASK_SIZE | ||
| 18 | #define STACK_TOP_MAX STACK_TOP | ||
| 19 | #endif | ||
| 20 | |||
| 16 | #ifndef __ASSEMBLY__ | 21 | #ifndef __ASSEMBLY__ |
| 17 | 22 | ||
| 18 | static inline void *current_text_addr(void) | 23 | static inline void *current_text_addr(void) |
diff --git a/include/asm-blackfin/a.out.h b/include/asm-blackfin/a.out.h index d37a6849bf74..6c3d652ebd33 100644 --- a/include/asm-blackfin/a.out.h +++ b/include/asm-blackfin/a.out.h | |||
| @@ -16,10 +16,4 @@ struct exec { | |||
| 16 | #define N_DRSIZE(a) ((a).a_drsize) | 16 | #define N_DRSIZE(a) ((a).a_drsize) |
| 17 | #define N_SYMSIZE(a) ((a).a_syms) | 17 | #define N_SYMSIZE(a) ((a).a_syms) |
| 18 | 18 | ||
| 19 | #ifdef __KERNEL__ | ||
| 20 | |||
| 21 | #define STACK_TOP TASK_SIZE | ||
| 22 | |||
| 23 | #endif | ||
| 24 | |||
| 25 | #endif /* __BFIN_A_OUT_H__ */ | 19 | #endif /* __BFIN_A_OUT_H__ */ |
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 6ae0619d7696..5dba3a735596 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h | |||
| @@ -70,6 +70,7 @@ extern void program_IAR(void); | |||
| 70 | extern void evt14_softirq(void); | 70 | extern void evt14_softirq(void); |
| 71 | extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); | 71 | extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); |
| 72 | extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type); | 72 | extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type); |
| 73 | extern int bfin_internal_set_wake(unsigned int irq, unsigned int state); | ||
| 73 | 74 | ||
| 74 | extern asmlinkage void finish_atomic_sections (struct pt_regs *regs); | 75 | extern asmlinkage void finish_atomic_sections (struct pt_regs *regs); |
| 75 | extern char fixed_code_start; | 76 | extern char fixed_code_start; |
| @@ -121,6 +122,7 @@ extern unsigned long dpdt_swapcount_table[]; | |||
| 121 | 122 | ||
| 122 | extern unsigned long table_start, table_end; | 123 | extern unsigned long table_start, table_end; |
| 123 | 124 | ||
| 125 | extern unsigned long bfin_sic_iwr[]; | ||
| 124 | extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ | 126 | extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ |
| 125 | extern struct file_operations dpmc_fops; | 127 | extern struct file_operations dpmc_fops; |
| 126 | extern char _start; | 128 | extern char _start; |
diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h index 1a0b57f6a3d4..9fa19158e38d 100644 --- a/include/asm-blackfin/bfin5xx_spi.h +++ b/include/asm-blackfin/bfin5xx_spi.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /************************************************************ | 1 | /************************************************************ |
| 2 | * | 2 | |
| 3 | * Copyright (C) 2004, Analog Devices. All Rights Reserved | 3 | * Copyright (C) 2006-2008, Analog Devices. All Rights Reserved |
| 4 | * | 4 | * |
| 5 | * FILE bfin5xx_spi.h | 5 | * FILE bfin5xx_spi.h |
| 6 | * PROGRAMMER(S): Luke Yang (Analog Devices Inc.) | 6 | * PROGRAMMER(S): Luke Yang (Analog Devices Inc.) |
| @@ -32,42 +32,6 @@ | |||
| 32 | #define SPI_BAUD_OFF 0x14 | 32 | #define SPI_BAUD_OFF 0x14 |
| 33 | #define SPI_SHAW_OFF 0x18 | 33 | #define SPI_SHAW_OFF 0x18 |
| 34 | 34 | ||
| 35 | #define CMD_SPI_OUT_ENABLE 1 | ||
| 36 | #define CMD_SPI_SET_BAUDRATE 2 | ||
| 37 | #define CMD_SPI_SET_POLAR 3 | ||
| 38 | #define CMD_SPI_SET_PHASE 4 | ||
| 39 | #define CMD_SPI_SET_MASTER 5 | ||
| 40 | #define CMD_SPI_SET_SENDOPT 6 | ||
| 41 | #define CMD_SPI_SET_RECVOPT 7 | ||
| 42 | #define CMD_SPI_SET_ORDER 8 | ||
| 43 | #define CMD_SPI_SET_LENGTH16 9 | ||
| 44 | #define CMD_SPI_GET_STAT 11 | ||
| 45 | #define CMD_SPI_GET_CFG 12 | ||
| 46 | #define CMD_SPI_SET_CSAVAIL 13 | ||
| 47 | #define CMD_SPI_SET_CSHIGH 14 /* CS unavail */ | ||
| 48 | #define CMD_SPI_SET_CSLOW 15 /* CS avail */ | ||
| 49 | #define CMD_SPI_MISO_ENABLE 16 | ||
| 50 | #define CMD_SPI_SET_CSENABLE 17 | ||
| 51 | #define CMD_SPI_SET_CSDISABLE 18 | ||
| 52 | |||
| 53 | #define CMD_SPI_SET_TRIGGER_MODE 19 | ||
| 54 | #define CMD_SPI_SET_TRIGGER_SENSE 20 | ||
| 55 | #define CMD_SPI_SET_TRIGGER_EDGE 21 | ||
| 56 | #define CMD_SPI_SET_TRIGGER_LEVEL 22 | ||
| 57 | |||
| 58 | #define CMD_SPI_SET_TIME_SPS 23 | ||
| 59 | #define CMD_SPI_SET_TIME_SAMPLES 24 | ||
| 60 | #define CMD_SPI_GET_SYSTEMCLOCK 25 | ||
| 61 | |||
| 62 | #define CMD_SPI_SET_WRITECONTINUOUS 26 | ||
| 63 | #define CMD_SPI_SET_SKFS 27 | ||
| 64 | |||
| 65 | #define CMD_SPI_GET_ALLCONFIG 32 /* For debug */ | ||
| 66 | |||
| 67 | #define SPI_DEFAULT_BARD 0x0100 | ||
| 68 | |||
| 69 | #define SPI0_IRQ_NUM IRQ_SPI | ||
| 70 | #define SPI_ERR_TRIG -1 | ||
| 71 | 35 | ||
| 72 | #define BIT_CTL_ENABLE 0x4000 | 36 | #define BIT_CTL_ENABLE 0x4000 |
| 73 | #define BIT_CTL_OPENDRAIN 0x2000 | 37 | #define BIT_CTL_OPENDRAIN 0x2000 |
| @@ -148,6 +112,10 @@ | |||
| 148 | #define CFG_SPI_CS6VALUE 6 | 112 | #define CFG_SPI_CS6VALUE 6 |
| 149 | #define CFG_SPI_CS7VALUE 7 | 113 | #define CFG_SPI_CS7VALUE 7 |
| 150 | 114 | ||
| 115 | #define CMD_SPI_SET_BAUDRATE 2 | ||
| 116 | #define CMD_SPI_GET_SYSTEMCLOCK 25 | ||
| 117 | #define CMD_SPI_SET_WRITECONTINUOUS 26 | ||
| 118 | |||
| 151 | /* device.platform_data for SSP controller devices */ | 119 | /* device.platform_data for SSP controller devices */ |
| 152 | struct bfin5xx_spi_master { | 120 | struct bfin5xx_spi_master { |
| 153 | u16 num_chipselect; | 121 | u16 num_chipselect; |
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h index f162edb23033..686cf83a5269 100644 --- a/include/asm-blackfin/dpmc.h +++ b/include/asm-blackfin/dpmc.h | |||
| @@ -53,10 +53,10 @@ unsigned long get_pll_status(void); | |||
| 53 | void change_baud(int baud); | 53 | void change_baud(int baud); |
| 54 | void fullon_mode(void); | 54 | void fullon_mode(void); |
| 55 | void active_mode(void); | 55 | void active_mode(void); |
| 56 | void sleep_mode(u32 sic_iwr); | 56 | void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); |
| 57 | void deep_sleep(u32 sic_iwr); | 57 | void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); |
| 58 | void hibernate_mode(u32 sic_iwr); | 58 | void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); |
| 59 | void sleep_deeper(u32 sic_iwr); | 59 | void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); |
| 60 | void program_wdog_timer(unsigned long); | 60 | void program_wdog_timer(unsigned long); |
| 61 | void unmask_wdog_wakeup_evt(void); | 61 | void unmask_wdog_wakeup_evt(void); |
| 62 | void clear_wdog_wakeup_evt(void); | 62 | void clear_wdog_wakeup_evt(void); |
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h index d0426c108262..27ff532a806c 100644 --- a/include/asm-blackfin/gpio.h +++ b/include/asm-blackfin/gpio.h | |||
| @@ -376,16 +376,19 @@ struct gpio_port_t { | |||
| 376 | #endif | 376 | #endif |
| 377 | 377 | ||
| 378 | #ifdef CONFIG_PM | 378 | #ifdef CONFIG_PM |
| 379 | unsigned int bfin_pm_setup(void); | ||
| 380 | void bfin_pm_restore(void); | ||
| 381 | |||
| 382 | #ifndef CONFIG_BF54x | ||
| 379 | #define PM_WAKE_RISING 0x1 | 383 | #define PM_WAKE_RISING 0x1 |
| 380 | #define PM_WAKE_FALLING 0x2 | 384 | #define PM_WAKE_FALLING 0x2 |
| 381 | #define PM_WAKE_HIGH 0x4 | 385 | #define PM_WAKE_HIGH 0x4 |
| 382 | #define PM_WAKE_LOW 0x8 | 386 | #define PM_WAKE_LOW 0x8 |
| 383 | #define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING) | 387 | #define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING) |
| 388 | #define PM_WAKE_IGNORE 0xF0 | ||
| 384 | 389 | ||
| 385 | int gpio_pm_wakeup_request(unsigned gpio, unsigned char type); | 390 | int gpio_pm_wakeup_request(unsigned gpio, unsigned char type); |
| 386 | void gpio_pm_wakeup_free(unsigned gpio); | 391 | void gpio_pm_wakeup_free(unsigned gpio); |
| 387 | unsigned int gpio_pm_setup(void); | ||
| 388 | void gpio_pm_restore(void); | ||
| 389 | 392 | ||
| 390 | struct gpio_port_s { | 393 | struct gpio_port_s { |
| 391 | unsigned short data; | 394 | unsigned short data; |
| @@ -409,6 +412,7 @@ struct gpio_port_s { | |||
| 409 | unsigned short fer; | 412 | unsigned short fer; |
| 410 | unsigned short reserved; | 413 | unsigned short reserved; |
| 411 | }; | 414 | }; |
| 415 | #endif /*CONFIG_BF54x*/ | ||
| 412 | #endif /*CONFIG_PM*/ | 416 | #endif /*CONFIG_PM*/ |
| 413 | 417 | ||
| 414 | /*********************************************************** | 418 | /*********************************************************** |
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h index 19e84dd4c99c..3bd67da86053 100644 --- a/include/asm-blackfin/mach-bf548/blackfin.h +++ b/include/asm-blackfin/mach-bf548/blackfin.h | |||
| @@ -46,6 +46,10 @@ | |||
| 46 | #include "defBF544.h" | 46 | #include "defBF544.h" |
| 47 | #endif | 47 | #endif |
| 48 | 48 | ||
| 49 | #ifdef CONFIG_BF547 | ||
| 50 | #include "defBF547.h" | ||
| 51 | #endif | ||
| 52 | |||
| 49 | #ifdef CONFIG_BF548 | 53 | #ifdef CONFIG_BF548 |
| 50 | #include "defBF548.h" | 54 | #include "defBF548.h" |
| 51 | #endif | 55 | #endif |
| @@ -58,10 +62,12 @@ | |||
| 58 | #ifdef CONFIG_BF542 | 62 | #ifdef CONFIG_BF542 |
| 59 | #include "cdefBF542.h" | 63 | #include "cdefBF542.h" |
| 60 | #endif | 64 | #endif |
| 61 | |||
| 62 | #ifdef CONFIG_BF544 | 65 | #ifdef CONFIG_BF544 |
| 63 | #include "cdefBF544.h" | 66 | #include "cdefBF544.h" |
| 64 | #endif | 67 | #endif |
| 68 | #ifdef CONFIG_BF547 | ||
| 69 | #include "cdefBF547.h" | ||
| 70 | #endif | ||
| 65 | #ifdef CONFIG_BF548 | 71 | #ifdef CONFIG_BF548 |
| 66 | #include "cdefBF548.h" | 72 | #include "cdefBF548.h" |
| 67 | #endif | 73 | #endif |
diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h new file mode 100644 index 000000000000..d0a200b08abd --- /dev/null +++ b/include/asm-blackfin/mach-bf548/cdefBF547.h | |||
| @@ -0,0 +1,865 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf548/cdefBF547.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _CDEF_BF548_H | ||
| 32 | #define _CDEF_BF548_H | ||
| 33 | |||
| 34 | /* include all Core registers and bit definitions */ | ||
| 35 | #include "defBF548.h" | ||
| 36 | |||
| 37 | /* include core sbfin_read_()ecific register pointer definitions */ | ||
| 38 | #include <asm/mach-common/cdef_LPBlackfin.h> | ||
| 39 | |||
| 40 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ | ||
| 41 | |||
| 42 | /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ | ||
| 43 | #include "cdefBF54x_base.h" | ||
| 44 | |||
| 45 | /* The following are the #defines needed by ADSP-BF548 that are not in the common header */ | ||
| 46 | |||
| 47 | /* Timer Registers */ | ||
| 48 | |||
| 49 | #define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) | ||
| 50 | #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) | ||
| 51 | #define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) | ||
| 52 | #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) | ||
| 53 | #define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) | ||
| 54 | #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) | ||
| 55 | #define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) | ||
| 56 | #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) | ||
| 57 | #define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) | ||
| 58 | #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) | ||
| 59 | #define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) | ||
| 60 | #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) | ||
| 61 | #define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) | ||
| 62 | #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) | ||
| 63 | #define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) | ||
| 64 | #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) | ||
| 65 | #define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) | ||
| 66 | #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) | ||
| 67 | #define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) | ||
| 68 | #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) | ||
| 69 | #define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) | ||
| 70 | #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) | ||
| 71 | #define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) | ||
| 72 | #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) | ||
| 73 | |||
| 74 | /* Timer Groubfin_read_() of 3 */ | ||
| 75 | |||
| 76 | #define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) | ||
| 77 | #define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) | ||
| 78 | #define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) | ||
| 79 | #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) | ||
| 80 | #define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) | ||
| 81 | #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) | ||
| 82 | |||
| 83 | /* SPORT0 Registers */ | ||
| 84 | |||
| 85 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) | ||
| 86 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) | ||
| 87 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) | ||
| 88 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) | ||
| 89 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) | ||
| 90 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) | ||
| 91 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) | ||
| 92 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) | ||
| 93 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) | ||
| 94 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) | ||
| 95 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) | ||
| 96 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) | ||
| 97 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) | ||
| 98 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) | ||
| 99 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) | ||
| 100 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) | ||
| 101 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) | ||
| 102 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) | ||
| 103 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) | ||
| 104 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) | ||
| 105 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) | ||
| 106 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) | ||
| 107 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) | ||
| 108 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) | ||
| 109 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) | ||
| 110 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) | ||
| 111 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) | ||
| 112 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) | ||
| 113 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) | ||
| 114 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) | ||
| 115 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) | ||
| 116 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) | ||
| 117 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) | ||
| 118 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) | ||
| 119 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) | ||
| 120 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) | ||
| 121 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) | ||
| 122 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) | ||
| 123 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) | ||
| 124 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) | ||
| 125 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) | ||
| 126 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) | ||
| 127 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) | ||
| 128 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) | ||
| 129 | |||
| 130 | /* EPPI0 Registers */ | ||
| 131 | |||
| 132 | #define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) | ||
| 133 | #define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) | ||
| 134 | #define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) | ||
| 135 | #define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) | ||
| 136 | #define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) | ||
| 137 | #define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) | ||
| 138 | #define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) | ||
| 139 | #define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) | ||
| 140 | #define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) | ||
| 141 | #define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) | ||
| 142 | #define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) | ||
| 143 | #define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) | ||
| 144 | #define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) | ||
| 145 | #define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) | ||
| 146 | #define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) | ||
| 147 | #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) | ||
| 148 | #define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) | ||
| 149 | #define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) | ||
| 150 | #define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) | ||
| 151 | #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) | ||
| 152 | #define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) | ||
| 153 | #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) | ||
| 154 | #define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) | ||
| 155 | #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) | ||
| 156 | #define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) | ||
| 157 | #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) | ||
| 158 | #define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) | ||
| 159 | #define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) | ||
| 160 | |||
| 161 | /* UART2 Registers */ | ||
| 162 | |||
| 163 | #define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) | ||
| 164 | #define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) | ||
| 165 | #define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) | ||
| 166 | #define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) | ||
| 167 | #define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) | ||
| 168 | #define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) | ||
| 169 | #define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) | ||
| 170 | #define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) | ||
| 171 | #define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) | ||
| 172 | #define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) | ||
| 173 | #define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) | ||
| 174 | #define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) | ||
| 175 | #define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) | ||
| 176 | #define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) | ||
| 177 | #define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) | ||
| 178 | #define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) | ||
| 179 | #define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) | ||
| 180 | #define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) | ||
| 181 | #define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) | ||
| 182 | #define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) | ||
| 183 | #define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) | ||
| 184 | #define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) | ||
| 185 | |||
| 186 | /* Two Wire Interface Registers (TWI1) */ | ||
| 187 | |||
| 188 | #define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) | ||
| 189 | #define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) | ||
| 190 | #define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) | ||
| 191 | #define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) | ||
| 192 | #define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) | ||
| 193 | #define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) | ||
| 194 | #define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) | ||
| 195 | #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) | ||
| 196 | #define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) | ||
| 197 | #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) | ||
| 198 | #define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL) | ||
| 199 | #define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val) | ||
| 200 | #define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) | ||
| 201 | #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) | ||
| 202 | #define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) | ||
| 203 | #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) | ||
| 204 | #define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) | ||
| 205 | #define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) | ||
| 206 | #define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) | ||
| 207 | #define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) | ||
| 208 | #define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL) | ||
| 209 | #define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val) | ||
| 210 | #define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) | ||
| 211 | #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) | ||
| 212 | #define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) | ||
| 213 | #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) | ||
| 214 | #define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) | ||
| 215 | #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) | ||
| 216 | #define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) | ||
| 217 | #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) | ||
| 218 | #define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) | ||
| 219 | #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) | ||
| 220 | |||
| 221 | /* SPI2 Registers */ | ||
| 222 | |||
| 223 | #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) | ||
| 224 | #define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) | ||
| 225 | #define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) | ||
| 226 | #define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) | ||
| 227 | #define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) | ||
| 228 | #define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) | ||
| 229 | #define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) | ||
| 230 | #define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) | ||
| 231 | #define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) | ||
| 232 | #define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) | ||
| 233 | #define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) | ||
| 234 | #define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) | ||
| 235 | #define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) | ||
| 236 | #define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) | ||
| 237 | |||
| 238 | /* ATAPI Registers */ | ||
| 239 | |||
| 240 | #define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) | ||
| 241 | #define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) | ||
| 242 | #define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) | ||
| 243 | #define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) | ||
| 244 | #define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) | ||
| 245 | #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) | ||
| 246 | #define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) | ||
| 247 | #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) | ||
| 248 | #define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) | ||
| 249 | #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) | ||
| 250 | #define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) | ||
| 251 | #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) | ||
| 252 | #define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) | ||
| 253 | #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) | ||
| 254 | #define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) | ||
| 255 | #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) | ||
| 256 | #define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) | ||
| 257 | #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) | ||
| 258 | #define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) | ||
| 259 | #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) | ||
| 260 | #define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) | ||
| 261 | #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) | ||
| 262 | #define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) | ||
| 263 | #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) | ||
| 264 | #define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) | ||
| 265 | #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) | ||
| 266 | #define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) | ||
| 267 | #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) | ||
| 268 | #define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) | ||
| 269 | #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) | ||
| 270 | #define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) | ||
| 271 | #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) | ||
| 272 | #define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) | ||
| 273 | #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) | ||
| 274 | #define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) | ||
| 275 | #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) | ||
| 276 | #define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) | ||
| 277 | #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) | ||
| 278 | #define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) | ||
| 279 | #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) | ||
| 280 | #define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) | ||
| 281 | #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) | ||
| 282 | #define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) | ||
| 283 | #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) | ||
| 284 | #define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) | ||
| 285 | #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) | ||
| 286 | #define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) | ||
| 287 | #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) | ||
| 288 | #define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) | ||
| 289 | #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) | ||
| 290 | |||
| 291 | /* SDH Registers */ | ||
| 292 | |||
| 293 | #define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) | ||
| 294 | #define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) | ||
| 295 | #define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) | ||
| 296 | #define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) | ||
| 297 | #define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) | ||
| 298 | #define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) | ||
| 299 | #define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) | ||
| 300 | #define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) | ||
| 301 | #define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) | ||
| 302 | #define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) | ||
| 303 | #define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) | ||
| 304 | #define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) | ||
| 305 | #define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) | ||
| 306 | #define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) | ||
| 307 | #define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) | ||
| 308 | #define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) | ||
| 309 | #define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) | ||
| 310 | #define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) | ||
| 311 | #define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) | ||
| 312 | #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) | ||
| 313 | #define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) | ||
| 314 | #define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) | ||
| 315 | #define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) | ||
| 316 | #define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) | ||
| 317 | #define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) | ||
| 318 | #define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) | ||
| 319 | #define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) | ||
| 320 | #define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) | ||
| 321 | #define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) | ||
| 322 | #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) | ||
| 323 | #define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) | ||
| 324 | #define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) | ||
| 325 | #define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) | ||
| 326 | #define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) | ||
| 327 | #define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) | ||
| 328 | #define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) | ||
| 329 | #define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) | ||
| 330 | #define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) | ||
| 331 | #define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) | ||
| 332 | #define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) | ||
| 333 | #define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) | ||
| 334 | #define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) | ||
| 335 | #define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) | ||
| 336 | #define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) | ||
| 337 | #define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) | ||
| 338 | #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) | ||
| 339 | #define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) | ||
| 340 | #define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) | ||
| 341 | #define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) | ||
| 342 | #define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) | ||
| 343 | #define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) | ||
| 344 | #define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) | ||
| 345 | #define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) | ||
| 346 | #define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) | ||
| 347 | #define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) | ||
| 348 | #define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) | ||
| 349 | #define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) | ||
| 350 | #define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) | ||
| 351 | #define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) | ||
| 352 | #define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) | ||
| 353 | #define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) | ||
| 354 | #define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) | ||
| 355 | |||
| 356 | /* HOST Port Registers */ | ||
| 357 | |||
| 358 | #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) | ||
| 359 | #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) | ||
| 360 | #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) | ||
| 361 | #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) | ||
| 362 | #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) | ||
| 363 | #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) | ||
| 364 | |||
| 365 | /* USB Control Registers */ | ||
| 366 | |||
| 367 | #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) | ||
| 368 | #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) | ||
| 369 | #define bfin_read_USB_POWER() bfin_read16(USB_POWER) | ||
| 370 | #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) | ||
| 371 | #define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) | ||
| 372 | #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) | ||
| 373 | #define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) | ||
| 374 | #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) | ||
| 375 | #define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) | ||
| 376 | #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) | ||
| 377 | #define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) | ||
| 378 | #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) | ||
| 379 | #define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) | ||
| 380 | #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) | ||
| 381 | #define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) | ||
| 382 | #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) | ||
| 383 | #define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) | ||
| 384 | #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) | ||
| 385 | #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) | ||
| 386 | #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) | ||
| 387 | #define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) | ||
| 388 | #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) | ||
| 389 | #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) | ||
| 390 | #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) | ||
| 391 | #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) | ||
| 392 | #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) | ||
| 393 | |||
| 394 | /* USB Packet Control Registers */ | ||
| 395 | |||
| 396 | #define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) | ||
| 397 | #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) | ||
| 398 | #define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) | ||
| 399 | #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) | ||
| 400 | #define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) | ||
| 401 | #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) | ||
| 402 | #define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) | ||
| 403 | #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) | ||
| 404 | #define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) | ||
| 405 | #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) | ||
| 406 | #define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) | ||
| 407 | #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) | ||
| 408 | #define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) | ||
| 409 | #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) | ||
| 410 | #define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) | ||
| 411 | #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) | ||
| 412 | #define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) | ||
| 413 | #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) | ||
| 414 | #define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) | ||
| 415 | #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) | ||
| 416 | #define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) | ||
| 417 | #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) | ||
| 418 | #define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) | ||
| 419 | #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) | ||
| 420 | #define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) | ||
| 421 | #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) | ||
| 422 | |||
| 423 | /* USB Endbfin_read_()oint FIFO Registers */ | ||
| 424 | |||
| 425 | #define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) | ||
| 426 | #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) | ||
| 427 | #define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) | ||
| 428 | #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) | ||
| 429 | #define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) | ||
| 430 | #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) | ||
| 431 | #define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) | ||
| 432 | #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) | ||
| 433 | #define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) | ||
| 434 | #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) | ||
| 435 | #define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) | ||
| 436 | #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) | ||
| 437 | #define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) | ||
| 438 | #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) | ||
| 439 | #define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) | ||
| 440 | #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) | ||
| 441 | |||
| 442 | /* USB OTG Control Registers */ | ||
| 443 | |||
| 444 | #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) | ||
| 445 | #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) | ||
| 446 | #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) | ||
| 447 | #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) | ||
| 448 | #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) | ||
| 449 | #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) | ||
| 450 | |||
| 451 | /* USB Phy Control Registers */ | ||
| 452 | |||
| 453 | #define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) | ||
| 454 | #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) | ||
| 455 | #define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) | ||
| 456 | #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) | ||
| 457 | #define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) | ||
| 458 | #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) | ||
| 459 | #define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) | ||
| 460 | #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) | ||
| 461 | #define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) | ||
| 462 | #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) | ||
| 463 | |||
| 464 | /* (APHY_CNTRL is for ADI usage only) */ | ||
| 465 | |||
| 466 | #define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) | ||
| 467 | #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) | ||
| 468 | |||
| 469 | /* (APHY_CALIB is for ADI usage only) */ | ||
| 470 | |||
| 471 | #define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) | ||
| 472 | #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) | ||
| 473 | #define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) | ||
| 474 | #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) | ||
| 475 | |||
| 476 | /* (PHY_TEST is for ADI usage only) */ | ||
| 477 | |||
| 478 | #define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) | ||
| 479 | #define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) | ||
| 480 | #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) | ||
| 481 | #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) | ||
| 482 | #define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) | ||
| 483 | #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) | ||
| 484 | |||
| 485 | /* USB Endbfin_read_()oint 0 Control Registers */ | ||
| 486 | |||
| 487 | #define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) | ||
| 488 | #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) | ||
| 489 | #define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) | ||
| 490 | #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) | ||
| 491 | #define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) | ||
| 492 | #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) | ||
| 493 | #define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) | ||
| 494 | #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) | ||
| 495 | #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) | ||
| 496 | #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) | ||
| 497 | #define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) | ||
| 498 | #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) | ||
| 499 | #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) | ||
| 500 | #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) | ||
| 501 | #define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) | ||
| 502 | #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) | ||
| 503 | #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) | ||
| 504 | #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) | ||
| 505 | |||
| 506 | /* USB Endbfin_read_()oint 1 Control Registers */ | ||
| 507 | |||
| 508 | #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) | ||
| 509 | #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) | ||
| 510 | #define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) | ||
| 511 | #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) | ||
| 512 | #define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) | ||
| 513 | #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) | ||
| 514 | #define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) | ||
| 515 | #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) | ||
| 516 | #define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) | ||
| 517 | #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) | ||
| 518 | #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) | ||
| 519 | #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) | ||
| 520 | #define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) | ||
| 521 | #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) | ||
| 522 | #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) | ||
| 523 | #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) | ||
| 524 | #define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) | ||
| 525 | #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) | ||
| 526 | #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) | ||
| 527 | #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) | ||
| 528 | |||
| 529 | /* USB Endbfin_read_()oint 2 Control Registers */ | ||
| 530 | |||
| 531 | #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) | ||
| 532 | #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) | ||
| 533 | #define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) | ||
| 534 | #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) | ||
| 535 | #define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) | ||
| 536 | #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) | ||
| 537 | #define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) | ||
| 538 | #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) | ||
| 539 | #define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) | ||
| 540 | #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) | ||
| 541 | #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) | ||
| 542 | #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) | ||
| 543 | #define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) | ||
| 544 | #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) | ||
| 545 | #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) | ||
| 546 | #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) | ||
| 547 | #define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) | ||
| 548 | #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) | ||
| 549 | #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) | ||
| 550 | #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) | ||
| 551 | |||
| 552 | /* USB Endbfin_read_()oint 3 Control Registers */ | ||
| 553 | |||
| 554 | #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) | ||
| 555 | #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) | ||
| 556 | #define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) | ||
| 557 | #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) | ||
| 558 | #define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) | ||
| 559 | #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) | ||
| 560 | #define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) | ||
| 561 | #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) | ||
| 562 | #define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) | ||
| 563 | #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) | ||
| 564 | #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) | ||
| 565 | #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) | ||
| 566 | #define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) | ||
| 567 | #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) | ||
| 568 | #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) | ||
| 569 | #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) | ||
| 570 | #define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) | ||
| 571 | #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) | ||
| 572 | #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) | ||
| 573 | #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) | ||
| 574 | |||
| 575 | /* USB Endbfin_read_()oint 4 Control Registers */ | ||
| 576 | |||
| 577 | #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) | ||
| 578 | #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) | ||
| 579 | #define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) | ||
| 580 | #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) | ||
| 581 | #define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) | ||
| 582 | #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) | ||
| 583 | #define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) | ||
| 584 | #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) | ||
| 585 | #define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) | ||
| 586 | #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) | ||
| 587 | #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) | ||
| 588 | #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) | ||
| 589 | #define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) | ||
| 590 | #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) | ||
| 591 | #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) | ||
| 592 | #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) | ||
| 593 | #define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) | ||
| 594 | #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) | ||
| 595 | #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) | ||
| 596 | #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) | ||
| 597 | |||
| 598 | /* USB Endbfin_read_()oint 5 Control Registers */ | ||
| 599 | |||
| 600 | #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) | ||
| 601 | #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) | ||
| 602 | #define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) | ||
| 603 | #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) | ||
| 604 | #define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) | ||
| 605 | #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) | ||
| 606 | #define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) | ||
| 607 | #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) | ||
| 608 | #define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) | ||
| 609 | #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) | ||
| 610 | #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) | ||
| 611 | #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) | ||
| 612 | #define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) | ||
| 613 | #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) | ||
| 614 | #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) | ||
| 615 | #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) | ||
| 616 | #define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) | ||
| 617 | #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) | ||
| 618 | #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) | ||
| 619 | #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) | ||
| 620 | |||
| 621 | /* USB Endbfin_read_()oint 6 Control Registers */ | ||
| 622 | |||
| 623 | #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) | ||
| 624 | #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) | ||
| 625 | #define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) | ||
| 626 | #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) | ||
| 627 | #define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) | ||
| 628 | #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) | ||
| 629 | #define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) | ||
| 630 | #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) | ||
| 631 | #define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) | ||
| 632 | #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) | ||
| 633 | #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) | ||
| 634 | #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) | ||
| 635 | #define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) | ||
| 636 | #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) | ||
| 637 | #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) | ||
| 638 | #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) | ||
| 639 | #define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) | ||
| 640 | #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) | ||
| 641 | #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) | ||
| 642 | #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) | ||
| 643 | |||
| 644 | /* USB Endbfin_read_()oint 7 Control Registers */ | ||
| 645 | |||
| 646 | #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) | ||
| 647 | #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) | ||
| 648 | #define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) | ||
| 649 | #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) | ||
| 650 | #define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) | ||
| 651 | #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) | ||
| 652 | #define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) | ||
| 653 | #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) | ||
| 654 | #define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) | ||
| 655 | #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) | ||
| 656 | #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) | ||
| 657 | #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) | ||
| 658 | #define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) | ||
| 659 | #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) | ||
| 660 | #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) | ||
| 661 | #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) | ||
| 662 | #define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) | ||
| 663 | #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) | ||
| 664 | #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) | ||
| 665 | #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) | ||
| 666 | #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) | ||
| 667 | #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) | ||
| 668 | #define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) | ||
| 669 | #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) | ||
| 670 | |||
| 671 | /* USB Channel 0 Config Registers */ | ||
| 672 | |||
| 673 | #define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) | ||
| 674 | #define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) | ||
| 675 | #define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) | ||
| 676 | #define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) | ||
| 677 | #define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) | ||
| 678 | #define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) | ||
| 679 | #define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) | ||
| 680 | #define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) | ||
| 681 | #define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) | ||
| 682 | #define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) | ||
| 683 | |||
| 684 | /* USB Channel 1 Config Registers */ | ||
| 685 | |||
| 686 | #define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) | ||
| 687 | #define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) | ||
| 688 | #define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) | ||
| 689 | #define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) | ||
| 690 | #define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) | ||
| 691 | #define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) | ||
| 692 | #define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) | ||
| 693 | #define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) | ||
| 694 | #define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) | ||
| 695 | #define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) | ||
| 696 | |||
| 697 | /* USB Channel 2 Config Registers */ | ||
| 698 | |||
| 699 | #define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) | ||
| 700 | #define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) | ||
| 701 | #define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) | ||
| 702 | #define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) | ||
| 703 | #define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) | ||
| 704 | #define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) | ||
| 705 | #define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) | ||
| 706 | #define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) | ||
| 707 | #define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) | ||
| 708 | #define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) | ||
| 709 | |||
| 710 | /* USB Channel 3 Config Registers */ | ||
| 711 | |||
| 712 | #define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) | ||
| 713 | #define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) | ||
| 714 | #define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) | ||
| 715 | #define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) | ||
| 716 | #define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) | ||
| 717 | #define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) | ||
| 718 | #define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) | ||
| 719 | #define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) | ||
| 720 | #define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) | ||
| 721 | #define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) | ||
| 722 | |||
| 723 | /* USB Channel 4 Config Registers */ | ||
| 724 | |||
| 725 | #define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) | ||
| 726 | #define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) | ||
| 727 | #define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) | ||
| 728 | #define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) | ||
| 729 | #define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) | ||
| 730 | #define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) | ||
| 731 | #define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) | ||
| 732 | #define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) | ||
| 733 | #define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) | ||
| 734 | #define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) | ||
| 735 | |||
| 736 | /* USB Channel 5 Config Registers */ | ||
| 737 | |||
| 738 | #define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) | ||
| 739 | #define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) | ||
| 740 | #define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) | ||
| 741 | #define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) | ||
| 742 | #define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) | ||
| 743 | #define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) | ||
| 744 | #define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) | ||
| 745 | #define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) | ||
| 746 | #define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) | ||
| 747 | #define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) | ||
| 748 | |||
| 749 | /* USB Channel 6 Config Registers */ | ||
| 750 | |||
| 751 | #define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) | ||
| 752 | #define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) | ||
| 753 | #define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) | ||
| 754 | #define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) | ||
| 755 | #define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) | ||
| 756 | #define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) | ||
| 757 | #define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) | ||
| 758 | #define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) | ||
| 759 | #define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) | ||
| 760 | #define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) | ||
| 761 | |||
| 762 | /* USB Channel 7 Config Registers */ | ||
| 763 | |||
| 764 | #define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) | ||
| 765 | #define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) | ||
| 766 | #define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) | ||
| 767 | #define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) | ||
| 768 | #define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) | ||
| 769 | #define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) | ||
| 770 | #define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) | ||
| 771 | #define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) | ||
| 772 | #define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) | ||
| 773 | #define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) | ||
| 774 | |||
| 775 | /* Keybfin_read_()ad Registers */ | ||
| 776 | |||
| 777 | #define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) | ||
| 778 | #define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) | ||
| 779 | #define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) | ||
| 780 | #define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) | ||
| 781 | #define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) | ||
| 782 | #define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) | ||
| 783 | #define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) | ||
| 784 | #define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) | ||
| 785 | #define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) | ||
| 786 | #define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) | ||
| 787 | #define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) | ||
| 788 | #define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) | ||
| 789 | |||
| 790 | /* Pixel Combfin_read_()ositor (PIXC) Registers */ | ||
| 791 | |||
| 792 | #define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) | ||
| 793 | #define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) | ||
| 794 | #define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) | ||
| 795 | #define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) | ||
| 796 | #define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) | ||
| 797 | #define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) | ||
| 798 | #define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) | ||
| 799 | #define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) | ||
| 800 | #define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) | ||
| 801 | #define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) | ||
| 802 | #define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) | ||
| 803 | #define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) | ||
| 804 | #define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) | ||
| 805 | #define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) | ||
| 806 | #define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) | ||
| 807 | #define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) | ||
| 808 | #define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) | ||
| 809 | #define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) | ||
| 810 | #define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) | ||
| 811 | #define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) | ||
| 812 | #define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) | ||
| 813 | #define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) | ||
| 814 | #define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) | ||
| 815 | #define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) | ||
| 816 | #define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) | ||
| 817 | #define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) | ||
| 818 | #define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) | ||
| 819 | #define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) | ||
| 820 | #define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) | ||
| 821 | #define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) | ||
| 822 | #define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) | ||
| 823 | #define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) | ||
| 824 | #define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) | ||
| 825 | #define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) | ||
| 826 | #define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) | ||
| 827 | #define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) | ||
| 828 | #define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) | ||
| 829 | #define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) | ||
| 830 | |||
| 831 | /* Handshake MDMA 0 Registers */ | ||
| 832 | |||
| 833 | #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) | ||
| 834 | #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) | ||
| 835 | #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) | ||
| 836 | #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) | ||
| 837 | #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) | ||
| 838 | #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) | ||
| 839 | #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) | ||
| 840 | #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) | ||
| 841 | #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) | ||
| 842 | #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) | ||
| 843 | #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) | ||
| 844 | #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) | ||
| 845 | #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) | ||
| 846 | #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) | ||
| 847 | |||
| 848 | /* Handshake MDMA 1 Registers */ | ||
| 849 | |||
| 850 | #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) | ||
| 851 | #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) | ||
| 852 | #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) | ||
| 853 | #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) | ||
| 854 | #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) | ||
| 855 | #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) | ||
| 856 | #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) | ||
| 857 | #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) | ||
| 858 | #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) | ||
| 859 | #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) | ||
| 860 | #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) | ||
| 861 | #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) | ||
| 862 | #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) | ||
| 863 | #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) | ||
| 864 | |||
| 865 | #endif /* _CDEF_BF548_H */ | ||
diff --git a/include/asm-blackfin/mach-bf548/defBF547.h b/include/asm-blackfin/mach-bf548/defBF547.h new file mode 100644 index 000000000000..3a3a18ebb10e --- /dev/null +++ b/include/asm-blackfin/mach-bf548/defBF547.h | |||
| @@ -0,0 +1,1244 @@ | |||
| 1 | /* | ||
| 2 | * File: include/asm-blackfin/mach-bf548/defBF547.h | ||
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef _DEF_BF548_H | ||
| 32 | #define _DEF_BF548_H | ||
| 33 | |||
| 34 | /* Include all Core registers and bit definitions */ | ||
| 35 | #include <asm/mach-common/def_LPBlackfin.h> | ||
| 36 | |||
| 37 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ | ||
| 38 | |||
| 39 | /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ | ||
| 40 | #include "defBF54x_base.h" | ||
| 41 | |||
| 42 | /* The following are the #defines needed by ADSP-BF548 that are not in the common header */ | ||
| 43 | |||
| 44 | /* Timer Registers */ | ||
| 45 | |||
| 46 | #define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ | ||
| 47 | #define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ | ||
| 48 | #define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ | ||
| 49 | #define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ | ||
| 50 | #define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ | ||
| 51 | #define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ | ||
| 52 | #define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ | ||
| 53 | #define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ | ||
| 54 | #define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ | ||
| 55 | #define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ | ||
| 56 | #define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ | ||
| 57 | #define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ | ||
| 58 | |||
| 59 | /* Timer Group of 3 Registers */ | ||
| 60 | |||
| 61 | #define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ | ||
| 62 | #define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ | ||
| 63 | #define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ | ||
| 64 | |||
| 65 | /* SPORT0 Registers */ | ||
| 66 | |||
| 67 | #define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ | ||
| 68 | #define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ | ||
| 69 | #define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ | ||
| 70 | #define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ | ||
| 71 | #define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ | ||
| 72 | #define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ | ||
| 73 | #define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ | ||
| 74 | #define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ | ||
| 75 | #define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ | ||
| 76 | #define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ | ||
| 77 | #define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ | ||
| 78 | #define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ | ||
| 79 | #define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ | ||
| 80 | #define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ | ||
| 81 | #define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ | ||
| 82 | #define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ | ||
| 83 | #define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ | ||
| 84 | #define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ | ||
| 85 | #define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ | ||
| 86 | #define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ | ||
| 87 | #define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ | ||
| 88 | #define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ | ||
| 89 | |||
| 90 | /* EPPI0 Registers */ | ||
| 91 | |||
| 92 | #define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ | ||
| 93 | #define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ | ||
| 94 | #define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ | ||
| 95 | #define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ | ||
| 96 | #define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ | ||
| 97 | #define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ | ||
| 98 | #define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ | ||
| 99 | #define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ | ||
| 100 | #define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ | ||
| 101 | #define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ | ||
| 102 | #define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ | ||
| 103 | #define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ | ||
| 104 | #define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ | ||
| 105 | #define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ | ||
| 106 | |||
| 107 | /* UART2 Registers */ | ||
| 108 | |||
| 109 | #define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ | ||
| 110 | #define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ | ||
| 111 | #define UART2_GCTL 0xffc02108 /* Global Control Register */ | ||
| 112 | #define UART2_LCR 0xffc0210c /* Line Control Register */ | ||
| 113 | #define UART2_MCR 0xffc02110 /* Modem Control Register */ | ||
| 114 | #define UART2_LSR 0xffc02114 /* Line Status Register */ | ||
| 115 | #define UART2_MSR 0xffc02118 /* Modem Status Register */ | ||
| 116 | #define UART2_SCR 0xffc0211c /* Scratch Register */ | ||
| 117 | #define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ | ||
| 118 | #define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ | ||
| 119 | #define UART2_RBR 0xffc0212c /* Receive Buffer Register */ | ||
| 120 | |||
| 121 | /* Two Wire Interface Registers (TWI1) */ | ||
| 122 | |||
| 123 | #define TWI1_REGBASE 0xffc02200 | ||
| 124 | #define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ | ||
| 125 | #define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ | ||
| 126 | #define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ | ||
| 127 | #define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ | ||
| 128 | #define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ | ||
| 129 | #define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ | ||
| 130 | #define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ | ||
| 131 | #define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ | ||
| 132 | #define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ | ||
| 133 | #define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ | ||
| 134 | #define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ | ||
| 135 | #define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ | ||
| 136 | #define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ | ||
| 137 | #define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ | ||
| 138 | #define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ | ||
| 139 | #define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ | ||
| 140 | |||
| 141 | /* SPI2 Registers */ | ||
| 142 | |||
| 143 | #define SPI2_REGBASE 0xffc02400 | ||
| 144 | #define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ | ||
| 145 | #define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ | ||
| 146 | #define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ | ||
| 147 | #define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ | ||
| 148 | #define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ | ||
| 149 | #define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ | ||
| 150 | #define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ | ||
| 151 | |||
| 152 | /* ATAPI Registers */ | ||
| 153 | |||
| 154 | #define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ | ||
| 155 | #define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ | ||
| 156 | #define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ | ||
| 157 | #define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ | ||
| 158 | #define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ | ||
| 159 | #define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ | ||
| 160 | #define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ | ||
| 161 | #define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ | ||
| 162 | #define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ | ||
| 163 | #define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ | ||
| 164 | #define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ | ||
| 165 | #define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ | ||
| 166 | #define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ | ||
| 167 | #define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ | ||
| 168 | #define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ | ||
| 169 | #define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ | ||
| 170 | #define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ | ||
| 171 | #define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ | ||
| 172 | #define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ | ||
| 173 | #define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ | ||
| 174 | #define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ | ||
| 175 | #define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ | ||
| 176 | #define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ | ||
| 177 | #define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ | ||
| 178 | #define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ | ||
| 179 | |||
| 180 | /* SDH Registers */ | ||
| 181 | |||
| 182 | #define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ | ||
| 183 | #define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ | ||
| 184 | #define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ | ||
| 185 | #define SDH_COMMAND 0xffc0390c /* SDH Command */ | ||
| 186 | #define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ | ||
| 187 | #define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ | ||
| 188 | #define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ | ||
| 189 | #define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ | ||
| 190 | #define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ | ||
| 191 | #define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ | ||
| 192 | #define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ | ||
| 193 | #define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ | ||
| 194 | #define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ | ||
| 195 | #define SDH_STATUS 0xffc03934 /* SDH Status */ | ||
| 196 | #define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ | ||
| 197 | #define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ | ||
| 198 | #define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ | ||
| 199 | #define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ | ||
| 200 | #define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ | ||
| 201 | #define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ | ||
| 202 | #define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ | ||
| 203 | #define SDH_CFG 0xffc039c8 /* SDH Configuration */ | ||
| 204 | #define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ | ||
| 205 | #define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ | ||
| 206 | #define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ | ||
| 207 | #define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ | ||
| 208 | #define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ | ||
| 209 | #define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ | ||
| 210 | #define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ | ||
| 211 | #define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ | ||
| 212 | #define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ | ||
| 213 | |||
| 214 | /* HOST Port Registers */ | ||
| 215 | |||
| 216 | #define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ | ||
| 217 | #define HOST_STATUS 0xffc03a04 /* HOST Status Register */ | ||
| 218 | #define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ | ||
| 219 | |||
| 220 | /* USB Control Registers */ | ||
| 221 | |||
| 222 | #define USB_FADDR 0xffc03c00 /* Function address register */ | ||
| 223 | #define USB_POWER 0xffc03c04 /* Power management register */ | ||
| 224 | #define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ | ||
| 225 | #define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ | ||
| 226 | #define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ | ||
| 227 | #define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ | ||
| 228 | #define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ | ||
| 229 | #define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ | ||
| 230 | #define USB_FRAME 0xffc03c20 /* USB frame number */ | ||
| 231 | #define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ | ||
| 232 | #define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ | ||
| 233 | #define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ | ||
| 234 | #define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ | ||
| 235 | |||
| 236 | /* USB Packet Control Registers */ | ||
| 237 | |||
| 238 | #define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ | ||
| 239 | #define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | ||
| 240 | #define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ | ||
| 241 | #define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ | ||
| 242 | #define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ | ||
| 243 | #define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | ||
| 244 | #define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ | ||
| 245 | #define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ | ||
| 246 | #define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | ||
| 247 | #define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ | ||
| 248 | #define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ | ||
| 249 | #define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ | ||
| 250 | #define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ | ||
| 251 | |||
| 252 | /* USB Endpoint FIFO Registers */ | ||
| 253 | |||
| 254 | #define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ | ||
| 255 | #define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ | ||
| 256 | #define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ | ||
| 257 | #define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ | ||
| 258 | #define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ | ||
| 259 | #define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ | ||
| 260 | #define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ | ||
| 261 | #define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ | ||
| 262 | |||
| 263 | /* USB OTG Control Registers */ | ||
| 264 | |||
| 265 | #define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ | ||
| 266 | #define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ | ||
| 267 | #define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ | ||
| 268 | |||
| 269 | /* USB Phy Control Registers */ | ||
| 270 | |||
| 271 | #define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ | ||
| 272 | #define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ | ||
| 273 | #define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ | ||
| 274 | #define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ | ||
| 275 | #define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ | ||
| 276 | |||
| 277 | /* (APHY_CNTRL is for ADI usage only) */ | ||
| 278 | |||
| 279 | #define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ | ||
| 280 | |||
| 281 | /* (APHY_CALIB is for ADI usage only) */ | ||
| 282 | |||
| 283 | #define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ | ||
| 284 | #define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ | ||
| 285 | |||
| 286 | /* (PHY_TEST is for ADI usage only) */ | ||
| 287 | |||
| 288 | #define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ | ||
| 289 | #define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ | ||
| 290 | #define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ | ||
| 291 | |||
| 292 | /* USB Endpoint 0 Control Registers */ | ||
| 293 | |||
| 294 | #define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ | ||
| 295 | #define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ | ||
| 296 | #define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ | ||
| 297 | #define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ | ||
| 298 | #define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ | ||
| 299 | #define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ | ||
| 300 | #define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ | ||
| 301 | #define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ | ||
| 302 | #define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ | ||
| 303 | |||
| 304 | /* USB Endpoint 1 Control Registers */ | ||
| 305 | |||
| 306 | #define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ | ||
| 307 | #define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ | ||
| 308 | #define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ | ||
| 309 | #define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ | ||
| 310 | #define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ | ||
| 311 | #define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ | ||
| 312 | #define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ | ||
| 313 | #define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ | ||
| 314 | #define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ | ||
| 315 | #define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ | ||
| 316 | |||
| 317 | /* USB Endpoint 2 Control Registers */ | ||
| 318 | |||
| 319 | #define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ | ||
| 320 | #define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ | ||
| 321 | #define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ | ||
| 322 | #define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ | ||
| 323 | #define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ | ||
| 324 | #define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ | ||
| 325 | #define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ | ||
| 326 | #define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ | ||
| 327 | #define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ | ||
| 328 | #define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ | ||
| 329 | |||
| 330 | /* USB Endpoint 3 Control Registers */ | ||
| 331 | |||
| 332 | #define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ | ||
| 333 | #define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ | ||
| 334 | #define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ | ||
| 335 | #define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ | ||
| 336 | #define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ | ||
| 337 | #define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ | ||
| 338 | #define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ | ||
| 339 | #define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ | ||
| 340 | #define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ | ||
| 341 | #define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ | ||
| 342 | |||
| 343 | /* USB Endpoint 4 Control Registers */ | ||
| 344 | |||
| 345 | #define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ | ||
| 346 | #define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ | ||
| 347 | #define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ | ||
| 348 | #define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ | ||
| 349 | #define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ | ||
| 350 | #define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ | ||
| 351 | #define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ | ||
| 352 | #define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ | ||
| 353 | #define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ | ||
| 354 | #define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ | ||
| 355 | |||
| 356 | /* USB Endpoint 5 Control Registers */ | ||
| 357 | |||
| 358 | #define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ | ||
| 359 | #define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ | ||
| 360 | #define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ | ||
| 361 | #define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ | ||
| 362 | #define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ | ||
| 363 | #define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ | ||
| 364 | #define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ | ||
| 365 | #define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ | ||
| 366 | #define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ | ||
| 367 | #define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ | ||
| 368 | |||
| 369 | /* USB Endpoint 6 Control Registers */ | ||
| 370 | |||
| 371 | #define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ | ||
| 372 | #define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ | ||
| 373 | #define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ | ||
| 374 | #define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ | ||
| 375 | #define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ | ||
| 376 | #define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ | ||
| 377 | #define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ | ||
| 378 | #define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ | ||
| 379 | #define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ | ||
| 380 | #define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ | ||
| 381 | |||
| 382 | /* USB Endpoint 7 Control Registers */ | ||
| 383 | |||
| 384 | #define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ | ||
| 385 | #define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ | ||
| 386 | #define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ | ||
| 387 | #define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ | ||
| 388 | #define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ | ||
| 389 | #define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ | ||
| 390 | #define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ | ||
| 391 | #define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ | ||
| 392 | #define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ | ||
| 393 | #define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ | ||
| 394 | #define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ | ||
| 395 | #define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ | ||
| 396 | |||
| 397 | /* USB Channel 0 Config Registers */ | ||
| 398 | |||
| 399 | #define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ | ||
| 400 | #define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ | ||
| 401 | #define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ | ||
| 402 | #define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ | ||
| 403 | #define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ | ||
| 404 | |||
| 405 | /* USB Channel 1 Config Registers */ | ||
| 406 | |||
| 407 | #define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ | ||
| 408 | #define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ | ||
| 409 | #define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ | ||
| 410 | #define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ | ||
| 411 | #define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ | ||
| 412 | |||
| 413 | /* USB Channel 2 Config Registers */ | ||
| 414 | |||
| 415 | #define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ | ||
| 416 | #define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ | ||
| 417 | #define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ | ||
| 418 | #define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ | ||
| 419 | #define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ | ||
| 420 | |||
| 421 | /* USB Channel 3 Config Registers */ | ||
| 422 | |||
| 423 | #define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ | ||
| 424 | #define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ | ||
| 425 | #define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ | ||
| 426 | #define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ | ||
| 427 | #define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ | ||
| 428 | |||
| 429 | /* USB Channel 4 Config Registers */ | ||
| 430 | |||
| 431 | #define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ | ||
| 432 | #define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ | ||
| 433 | #define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ | ||
| 434 | #define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ | ||
| 435 | #define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ | ||
| 436 | |||
| 437 | /* USB Channel 5 Config Registers */ | ||
| 438 | |||
| 439 | #define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ | ||
| 440 | #define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ | ||
| 441 | #define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ | ||
| 442 | #define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ | ||
| 443 | #define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ | ||
| 444 | |||
| 445 | /* USB Channel 6 Config Registers */ | ||
| 446 | |||
| 447 | #define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ | ||
| 448 | #define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ | ||
| 449 | #define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ | ||
| 450 | #define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ | ||
| 451 | #define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ | ||
| 452 | |||
| 453 | /* USB Channel 7 Config Registers */ | ||
| 454 | |||
| 455 | #define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ | ||
| 456 | #define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ | ||
| 457 | #define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ | ||
| 458 | #define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ | ||
| 459 | #define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ | ||
| 460 | |||
| 461 | /* Keypad Registers */ | ||
| 462 | |||
| 463 | #define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ | ||
| 464 | #define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ | ||
| 465 | #define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ | ||
| 466 | #define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ | ||
| 467 | #define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ | ||
| 468 | #define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ | ||
| 469 | |||
| 470 | /* Pixel Compositor (PIXC) Registers */ | ||
| 471 | |||
| 472 | #define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ | ||
| 473 | #define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ | ||
| 474 | #define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ | ||
| 475 | #define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ | ||
| 476 | #define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ | ||
| 477 | #define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ | ||
| 478 | #define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ | ||
| 479 | #define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ | ||
| 480 | #define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ | ||
| 481 | #define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ | ||
| 482 | #define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ | ||
| 483 | #define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ | ||
| 484 | #define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ | ||
| 485 | #define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ | ||
| 486 | #define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ | ||
| 487 | #define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ | ||
| 488 | #define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ | ||
| 489 | #define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ | ||
| 490 | #define PIXC_TC 0xffc04450 /* Holds the transparent color value */ | ||
| 491 | |||
| 492 | /* Handshake MDMA 0 Registers */ | ||
| 493 | |||
| 494 | #define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ | ||
| 495 | #define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ | ||
| 496 | #define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ | ||
| 497 | #define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ | ||
| 498 | #define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ | ||
| 499 | #define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ | ||
| 500 | #define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ | ||
| 501 | |||
| 502 | /* Handshake MDMA 1 Registers */ | ||
| 503 | |||
| 504 | #define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ | ||
| 505 | #define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ | ||
| 506 | #define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ | ||
| 507 | #define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ | ||
| 508 | #define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ | ||
| 509 | #define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ | ||
| 510 | #define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ | ||
| 511 | |||
| 512 | |||
| 513 | /* ********************************************************** */ | ||
| 514 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ | ||
| 515 | /* and MULTI BIT READ MACROS */ | ||
| 516 | /* ********************************************************** */ | ||
| 517 | |||
| 518 | /* Bit masks for PIXC_CTL */ | ||
| 519 | |||
| 520 | #define PIXC_EN 0x1 /* Pixel Compositor Enable */ | ||
| 521 | #define OVR_A_EN 0x2 /* Overlay A Enable */ | ||
| 522 | #define OVR_B_EN 0x4 /* Overlay B Enable */ | ||
| 523 | #define IMG_FORM 0x8 /* Image Data Format */ | ||
| 524 | #define OVR_FORM 0x10 /* Overlay Data Format */ | ||
| 525 | #define OUT_FORM 0x20 /* Output Data Format */ | ||
| 526 | #define UDS_MOD 0x40 /* Resampling Mode */ | ||
| 527 | #define TC_EN 0x80 /* Transparent Color Enable */ | ||
| 528 | #define IMG_STAT 0x300 /* Image FIFO Status */ | ||
| 529 | #define OVR_STAT 0xc00 /* Overlay FIFO Status */ | ||
| 530 | #define WM_LVL 0x3000 /* FIFO Watermark Level */ | ||
| 531 | |||
| 532 | /* Bit masks for PIXC_AHSTART */ | ||
| 533 | |||
| 534 | #define A_HSTART 0xfff /* Horizontal Start Coordinates */ | ||
| 535 | |||
| 536 | /* Bit masks for PIXC_AHEND */ | ||
| 537 | |||
| 538 | #define A_HEND 0xfff /* Horizontal End Coordinates */ | ||
| 539 | |||
| 540 | /* Bit masks for PIXC_AVSTART */ | ||
| 541 | |||
| 542 | #define A_VSTART 0x3ff /* Vertical Start Coordinates */ | ||
| 543 | |||
| 544 | /* Bit masks for PIXC_AVEND */ | ||
| 545 | |||
| 546 | #define A_VEND 0x3ff /* Vertical End Coordinates */ | ||
| 547 | |||
| 548 | /* Bit masks for PIXC_ATRANSP */ | ||
| 549 | |||
| 550 | #define A_TRANSP 0xf /* Transparency Value */ | ||
| 551 | |||
| 552 | /* Bit masks for PIXC_BHSTART */ | ||
| 553 | |||
| 554 | #define B_HSTART 0xfff /* Horizontal Start Coordinates */ | ||
| 555 | |||
| 556 | /* Bit masks for PIXC_BHEND */ | ||
| 557 | |||
| 558 | #define B_HEND 0xfff /* Horizontal End Coordinates */ | ||
| 559 | |||
| 560 | /* Bit masks for PIXC_BVSTART */ | ||
| 561 | |||
| 562 | #define B_VSTART 0x3ff /* Vertical Start Coordinates */ | ||
| 563 | |||
| 564 | /* Bit masks for PIXC_BVEND */ | ||
| 565 | |||
| 566 | #define B_VEND 0x3ff /* Vertical End Coordinates */ | ||
| 567 | |||
| 568 | /* Bit masks for PIXC_BTRANSP */ | ||
| 569 | |||
| 570 | #define B_TRANSP 0xf /* Transparency Value */ | ||
| 571 | |||
| 572 | /* Bit masks for PIXC_INTRSTAT */ | ||
| 573 | |||
| 574 | #define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ | ||
| 575 | #define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ | ||
| 576 | #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ | ||
| 577 | #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ | ||
| 578 | |||
| 579 | /* Bit masks for PIXC_RYCON */ | ||
| 580 | |||
| 581 | #define A11 0x3ff /* A11 in the Coefficient Matrix */ | ||
| 582 | #define A12 0xffc00 /* A12 in the Coefficient Matrix */ | ||
| 583 | #define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ | ||
| 584 | #define RY_MULT4 0x40000000 /* Multiply Row by 4 */ | ||
| 585 | |||
| 586 | /* Bit masks for PIXC_GUCON */ | ||
| 587 | |||
| 588 | #define A21 0x3ff /* A21 in the Coefficient Matrix */ | ||
| 589 | #define A22 0xffc00 /* A22 in the Coefficient Matrix */ | ||
| 590 | #define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ | ||
| 591 | #define GU_MULT4 0x40000000 /* Multiply Row by 4 */ | ||
| 592 | |||
| 593 | /* Bit masks for PIXC_BVCON */ | ||
| 594 | |||
| 595 | #define A31 0x3ff /* A31 in the Coefficient Matrix */ | ||
| 596 | #define A32 0xffc00 /* A32 in the Coefficient Matrix */ | ||
| 597 | #define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ | ||
| 598 | #define BV_MULT4 0x40000000 /* Multiply Row by 4 */ | ||
| 599 | |||
| 600 | /* Bit masks for PIXC_CCBIAS */ | ||
| 601 | |||
| 602 | #define A14 0x3ff /* A14 in the Bias Vector */ | ||
| 603 | #define A24 0xffc00 /* A24 in the Bias Vector */ | ||
| 604 | #define A34 0x3ff00000 /* A34 in the Bias Vector */ | ||
| 605 | |||
| 606 | /* Bit masks for PIXC_TC */ | ||
| 607 | |||
| 608 | #define RY_TRANS 0xff /* Transparent Color - R/Y Component */ | ||
| 609 | #define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ | ||
| 610 | #define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ | ||
| 611 | |||
| 612 | /* Bit masks for HOST_CONTROL */ | ||
| 613 | |||
| 614 | #define HOST_EN 0x1 /* Host Enable */ | ||
| 615 | #define HOST_END 0x2 /* Host Endianess */ | ||
| 616 | #define DATA_SIZE 0x4 /* Data Size */ | ||
| 617 | #define HOST_RST 0x8 /* Host Reset */ | ||
| 618 | #define HRDY_OVR 0x20 /* Host Ready Override */ | ||
| 619 | #define INT_MODE 0x40 /* Interrupt Mode */ | ||
| 620 | #define BT_EN 0x80 /* Bus Timeout Enable */ | ||
| 621 | #define EHW 0x100 /* Enable Host Write */ | ||
| 622 | #define EHR 0x200 /* Enable Host Read */ | ||
| 623 | #define BDR 0x400 /* Burst DMA Requests */ | ||
| 624 | |||
| 625 | /* Bit masks for HOST_STATUS */ | ||
| 626 | |||
| 627 | #define DMA_READY 0x1 /* DMA Ready */ | ||
| 628 | #define FIFOFULL 0x2 /* FIFO Full */ | ||
| 629 | #define FIFOEMPTY 0x4 /* FIFO Empty */ | ||
| 630 | #define DMA_COMPLETE 0x8 /* DMA Complete */ | ||
| 631 | #define HSHK 0x10 /* Host Handshake */ | ||
| 632 | #define HSTIMEOUT 0x20 /* Host Timeout */ | ||
| 633 | #define HIRQ 0x40 /* Host Interrupt Request */ | ||
| 634 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ | ||
| 635 | #define DMA_DIR 0x100 /* DMA Direction */ | ||
| 636 | #define BTE 0x200 /* Bus Timeout Enabled */ | ||
| 637 | |||
| 638 | /* Bit masks for HOST_TIMEOUT */ | ||
| 639 | |||
| 640 | #define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ | ||
| 641 | |||
| 642 | /* Bit masks for KPAD_CTL */ | ||
| 643 | |||
| 644 | #define KPAD_EN 0x1 /* Keypad Enable */ | ||
| 645 | #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ | ||
| 646 | #define KPAD_ROWEN 0x1c00 /* Row Enable Width */ | ||
| 647 | #define KPAD_COLEN 0xe000 /* Column Enable Width */ | ||
| 648 | |||
| 649 | /* Bit masks for KPAD_PRESCALE */ | ||
| 650 | |||
| 651 | #define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ | ||
| 652 | |||
| 653 | /* Bit masks for KPAD_MSEL */ | ||
| 654 | |||
| 655 | #define DBON_SCALE 0xff /* Debounce Scale Value */ | ||
| 656 | #define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ | ||
| 657 | |||
| 658 | /* Bit masks for KPAD_ROWCOL */ | ||
| 659 | |||
| 660 | #define KPAD_ROW 0xff /* Rows Pressed */ | ||
| 661 | #define KPAD_COL 0xff00 /* Columns Pressed */ | ||
| 662 | |||
| 663 | /* Bit masks for KPAD_STAT */ | ||
| 664 | |||
| 665 | #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ | ||
| 666 | #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ | ||
| 667 | #define KPAD_PRESSED 0x8 /* Key press current status */ | ||
| 668 | |||
| 669 | /* Bit masks for KPAD_SOFTEVAL */ | ||
| 670 | |||
| 671 | #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ | ||
| 672 | |||
| 673 | /* Bit masks for SDH_COMMAND */ | ||
| 674 | |||
| 675 | #define CMD_IDX 0x3f /* Command Index */ | ||
| 676 | #define CMD_RSP 0x40 /* Response */ | ||
| 677 | #define CMD_L_RSP 0x80 /* Long Response */ | ||
| 678 | #define CMD_INT_E 0x100 /* Command Interrupt */ | ||
| 679 | #define CMD_PEND_E 0x200 /* Command Pending */ | ||
| 680 | #define CMD_E 0x400 /* Command Enable */ | ||
| 681 | |||
| 682 | /* Bit masks for SDH_PWR_CTL */ | ||
| 683 | |||
| 684 | #define PWR_ON 0x3 /* Power On */ | ||
| 685 | #if 0 | ||
| 686 | #define TBD 0x3c /* TBD */ | ||
| 687 | #endif | ||
| 688 | #define SD_CMD_OD 0x40 /* Open Drain Output */ | ||
| 689 | #define ROD_CTL 0x80 /* Rod Control */ | ||
| 690 | |||
| 691 | /* Bit masks for SDH_CLK_CTL */ | ||
| 692 | |||
| 693 | #define CLKDIV 0xff /* MC_CLK Divisor */ | ||
| 694 | #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ | ||
| 695 | #define PWR_SV_E 0x200 /* Power Save Enable */ | ||
| 696 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ | ||
| 697 | #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ | ||
| 698 | |||
| 699 | /* Bit masks for SDH_RESP_CMD */ | ||
| 700 | |||
| 701 | #define RESP_CMD 0x3f /* Response Command */ | ||
| 702 | |||
| 703 | /* Bit masks for SDH_DATA_CTL */ | ||
| 704 | |||
| 705 | #define DTX_E 0x1 /* Data Transfer Enable */ | ||
| 706 | #define DTX_DIR 0x2 /* Data Transfer Direction */ | ||
| 707 | #define DTX_MODE 0x4 /* Data Transfer Mode */ | ||
| 708 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ | ||
| 709 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ | ||
| 710 | |||
| 711 | /* Bit masks for SDH_STATUS */ | ||
| 712 | |||
| 713 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ | ||
| 714 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ | ||
| 715 | #define CMD_TIME_OUT 0x4 /* CMD Time Out */ | ||
| 716 | #define DAT_TIME_OUT 0x8 /* Data Time Out */ | ||
| 717 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ | ||
| 718 | #define RX_OVERRUN 0x20 /* Receive Overrun */ | ||
| 719 | #define CMD_RESP_END 0x40 /* CMD Response End */ | ||
| 720 | #define CMD_SENT 0x80 /* CMD Sent */ | ||
| 721 | #define DAT_END 0x100 /* Data End */ | ||
| 722 | #define START_BIT_ERR 0x200 /* Start Bit Error */ | ||
| 723 | #define DAT_BLK_END 0x400 /* Data Block End */ | ||
| 724 | #define CMD_ACT 0x800 /* CMD Active */ | ||
| 725 | #define TX_ACT 0x1000 /* Transmit Active */ | ||
| 726 | #define RX_ACT 0x2000 /* Receive Active */ | ||
| 727 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ | ||
| 728 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ | ||
| 729 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ | ||
| 730 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ | ||
| 731 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ | ||
| 732 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ | ||
| 733 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ | ||
| 734 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ | ||
| 735 | |||
| 736 | /* Bit masks for SDH_STATUS_CLR */ | ||
| 737 | |||
| 738 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ | ||
| 739 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ | ||
| 740 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ | ||
| 741 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ | ||
| 742 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ | ||
| 743 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ | ||
| 744 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ | ||
| 745 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ | ||
| 746 | #define DAT_END_STAT 0x100 /* Data End Status */ | ||
| 747 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ | ||
| 748 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ | ||
| 749 | |||
| 750 | /* Bit masks for SDH_MASK0 */ | ||
| 751 | |||
| 752 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ | ||
| 753 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ | ||
| 754 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ | ||
| 755 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ | ||
| 756 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ | ||
| 757 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ | ||
| 758 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ | ||
| 759 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ | ||
| 760 | #define DAT_END_MASK 0x100 /* Data End Mask */ | ||
| 761 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ | ||
| 762 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ | ||
| 763 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ | ||
| 764 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ | ||
| 765 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ | ||
| 766 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ | ||
| 767 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ | ||
| 768 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ | ||
| 769 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ | ||
| 770 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ | ||
| 771 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ | ||
| 772 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ | ||
| 773 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ | ||
| 774 | |||
| 775 | /* Bit masks for SDH_FIFO_CNT */ | ||
| 776 | |||
| 777 | #define FIFO_COUNT 0x7fff /* FIFO Count */ | ||
| 778 | |||
| 779 | /* Bit masks for SDH_E_STATUS */ | ||
| 780 | |||
| 781 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ | ||
| 782 | #define SD_CARD_DET 0x10 /* SD Card Detect */ | ||
| 783 | |||
| 784 | /* Bit masks for SDH_E_MASK */ | ||
| 785 | |||
| 786 | #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ | ||
| 787 | #define SCD_MSK 0x40 /* Mask Card Detect */ | ||
| 788 | |||
| 789 | /* Bit masks for SDH_CFG */ | ||
| 790 | |||
| 791 | #define CLKS_EN 0x1 /* Clocks Enable */ | ||
| 792 | #define SD4E 0x4 /* SDIO 4-Bit Enable */ | ||
| 793 | #define MWE 0x8 /* Moving Window Enable */ | ||
| 794 | #define SD_RST 0x10 /* SDMMC Reset */ | ||
| 795 | #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ | ||
| 796 | #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ | ||
| 797 | #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ | ||
| 798 | |||
| 799 | /* Bit masks for SDH_RD_WAIT_EN */ | ||
| 800 | |||
| 801 | #define RWR 0x1 /* Read Wait Request */ | ||
| 802 | |||
| 803 | /* Bit masks for ATAPI_CONTROL */ | ||
| 804 | |||
| 805 | #define PIO_START 0x1 /* Start PIO/Reg Op */ | ||
| 806 | #define MULTI_START 0x2 /* Start Multi-DMA Op */ | ||
| 807 | #define ULTRA_START 0x4 /* Start Ultra-DMA Op */ | ||
| 808 | #define XFER_DIR 0x8 /* Transfer Direction */ | ||
| 809 | #define IORDY_EN 0x10 /* IORDY Enable */ | ||
| 810 | #define FIFO_FLUSH 0x20 /* Flush FIFOs */ | ||
| 811 | #define SOFT_RST 0x40 /* Soft Reset */ | ||
| 812 | #define DEV_RST 0x80 /* Device Reset */ | ||
| 813 | #define TFRCNT_RST 0x100 /* Trans Count Reset */ | ||
| 814 | #define END_ON_TERM 0x200 /* End/Terminate Select */ | ||
| 815 | #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ | ||
| 816 | #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ | ||
| 817 | |||
| 818 | /* Bit masks for ATAPI_STATUS */ | ||
| 819 | |||
| 820 | #define PIO_XFER_ON 0x1 /* PIO transfer in progress */ | ||
| 821 | #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ | ||
| 822 | #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ | ||
| 823 | #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ | ||
| 824 | |||
| 825 | /* Bit masks for ATAPI_DEV_ADDR */ | ||
| 826 | |||
| 827 | #define DEV_ADDR 0x1f /* Device Address */ | ||
| 828 | |||
| 829 | /* Bit masks for ATAPI_INT_MASK */ | ||
| 830 | |||
| 831 | #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ | ||
| 832 | #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ | ||
| 833 | #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ | ||
| 834 | #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ | ||
| 835 | #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ | ||
| 836 | #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ | ||
| 837 | #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ | ||
| 838 | #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ | ||
| 839 | #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ | ||
| 840 | |||
| 841 | /* Bit masks for ATAPI_INT_STATUS */ | ||
| 842 | |||
| 843 | #define ATAPI_DEV_INT 0x1 /* Device interrupt status */ | ||
| 844 | #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ | ||
| 845 | #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ | ||
| 846 | #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ | ||
| 847 | #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ | ||
| 848 | #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ | ||
| 849 | #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ | ||
| 850 | #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ | ||
| 851 | #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ | ||
| 852 | |||
| 853 | /* Bit masks for ATAPI_LINE_STATUS */ | ||
| 854 | |||
| 855 | #define ATAPI_INTR 0x1 /* Device interrupt to host line status */ | ||
| 856 | #define ATAPI_DASP 0x2 /* Device dasp to host line status */ | ||
| 857 | #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ | ||
| 858 | #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ | ||
| 859 | #define ATAPI_ADDR 0x70 /* ATAPI address line status */ | ||
| 860 | #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ | ||
| 861 | #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ | ||
| 862 | #define ATAPI_DIOWN 0x200 /* ATAPI write line status */ | ||
| 863 | #define ATAPI_DIORN 0x400 /* ATAPI read line status */ | ||
| 864 | #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ | ||
| 865 | |||
| 866 | /* Bit masks for ATAPI_SM_STATE */ | ||
| 867 | |||
| 868 | #define PIO_CSTATE 0xf /* PIO mode state machine current state */ | ||
| 869 | #define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ | ||
| 870 | #define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ | ||
| 871 | #define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ | ||
| 872 | |||
| 873 | /* Bit masks for ATAPI_TERMINATE */ | ||
| 874 | |||
| 875 | #define ATAPI_HOST_TERM 0x1 /* Host terminationation */ | ||
| 876 | |||
| 877 | /* Bit masks for ATAPI_REG_TIM_0 */ | ||
| 878 | |||
| 879 | #define T2_REG 0xff /* End of cycle time for register access transfers */ | ||
| 880 | #define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ | ||
| 881 | |||
| 882 | /* Bit masks for ATAPI_PIO_TIM_0 */ | ||
| 883 | |||
| 884 | #define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ | ||
| 885 | #define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ | ||
| 886 | #define T4_REG 0xf000 /* DIOW data hold */ | ||
| 887 | |||
| 888 | /* Bit masks for ATAPI_PIO_TIM_1 */ | ||
| 889 | |||
| 890 | #define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ | ||
| 891 | |||
| 892 | /* Bit masks for ATAPI_MULTI_TIM_0 */ | ||
| 893 | |||
| 894 | #define TD 0xff /* DIOR/DIOW asserted pulsewidth */ | ||
| 895 | #define TM 0xff00 /* Time from address valid to DIOR/DIOW */ | ||
| 896 | |||
| 897 | /* Bit masks for ATAPI_MULTI_TIM_1 */ | ||
| 898 | |||
| 899 | #define TKW 0xff /* Selects DIOW negated pulsewidth */ | ||
| 900 | #define TKR 0xff00 /* Selects DIOR negated pulsewidth */ | ||
| 901 | |||
| 902 | /* Bit masks for ATAPI_MULTI_TIM_2 */ | ||
| 903 | |||
| 904 | #define TH 0xff /* Selects DIOW data hold */ | ||
| 905 | #define TEOC 0xff00 /* Selects end of cycle for DMA */ | ||
| 906 | |||
| 907 | /* Bit masks for ATAPI_ULTRA_TIM_0 */ | ||
| 908 | |||
| 909 | #define TACK 0xff /* Selects setup and hold times for TACK */ | ||
| 910 | #define TENV 0xff00 /* Selects envelope time */ | ||
| 911 | |||
| 912 | /* Bit masks for ATAPI_ULTRA_TIM_1 */ | ||
| 913 | |||
| 914 | #define TDVS 0xff /* Selects data valid setup time */ | ||
| 915 | #define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ | ||
| 916 | |||
| 917 | /* Bit masks for ATAPI_ULTRA_TIM_2 */ | ||
| 918 | |||
| 919 | #define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ | ||
| 920 | #define TMLI 0xff00 /* Selects interlock time */ | ||
| 921 | |||
| 922 | /* Bit masks for ATAPI_ULTRA_TIM_3 */ | ||
| 923 | |||
| 924 | #define TZAH 0xff /* Selects minimum delay required for output */ | ||
| 925 | #define READY_PAUSE 0xff00 /* Selects ready to pause */ | ||
| 926 | |||
| 927 | /* Bit masks for TIMER_ENABLE1 */ | ||
| 928 | |||
| 929 | #define TIMEN8 0x1 /* Timer 8 Enable */ | ||
| 930 | #define TIMEN9 0x2 /* Timer 9 Enable */ | ||
| 931 | #define TIMEN10 0x4 /* Timer 10 Enable */ | ||
| 932 | |||
| 933 | /* Bit masks for TIMER_DISABLE1 */ | ||
| 934 | |||
| 935 | #define TIMDIS8 0x1 /* Timer 8 Disable */ | ||
| 936 | #define TIMDIS9 0x2 /* Timer 9 Disable */ | ||
| 937 | #define TIMDIS10 0x4 /* Timer 10 Disable */ | ||
| 938 | |||
| 939 | /* Bit masks for TIMER_STATUS1 */ | ||
| 940 | |||
| 941 | #define TIMIL8 0x1 /* Timer 8 Interrupt */ | ||
| 942 | #define TIMIL9 0x2 /* Timer 9 Interrupt */ | ||
| 943 | #define TIMIL10 0x4 /* Timer 10 Interrupt */ | ||
| 944 | #define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ | ||
| 945 | #define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ | ||
| 946 | #define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ | ||
| 947 | #define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ | ||
| 948 | #define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ | ||
| 949 | #define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ | ||
| 950 | |||
| 951 | /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ | ||
| 952 | |||
| 953 | /* Bit masks for USB_FADDR */ | ||
| 954 | |||
| 955 | #define FUNCTION_ADDRESS 0x7f /* Function address */ | ||
| 956 | |||
| 957 | /* Bit masks for USB_POWER */ | ||
| 958 | |||
| 959 | #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ | ||
| 960 | #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ | ||
| 961 | #define RESUME_MODE 0x4 /* DMA Mode */ | ||
| 962 | #define RESET 0x8 /* Reset indicator */ | ||
| 963 | #define HS_MODE 0x10 /* High Speed mode indicator */ | ||
| 964 | #define HS_ENABLE 0x20 /* high Speed Enable */ | ||
| 965 | #define SOFT_CONN 0x40 /* Soft connect */ | ||
| 966 | #define ISO_UPDATE 0x80 /* Isochronous update */ | ||
| 967 | |||
| 968 | /* Bit masks for USB_INTRTX */ | ||
| 969 | |||
| 970 | #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ | ||
| 971 | #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ | ||
| 972 | #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ | ||
| 973 | #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ | ||
| 974 | #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ | ||
| 975 | #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ | ||
| 976 | #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ | ||
| 977 | #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ | ||
| 978 | |||
| 979 | /* Bit masks for USB_INTRRX */ | ||
| 980 | |||
| 981 | #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ | ||
| 982 | #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ | ||
| 983 | #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ | ||
| 984 | #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ | ||
| 985 | #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ | ||
| 986 | #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ | ||
| 987 | #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ | ||
| 988 | |||
| 989 | /* Bit masks for USB_INTRTXE */ | ||
| 990 | |||
| 991 | #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ | ||
| 992 | #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ | ||
| 993 | #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ | ||
| 994 | #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ | ||
| 995 | #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ | ||
| 996 | #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ | ||
| 997 | #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ | ||
| 998 | #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ | ||
| 999 | |||
| 1000 | /* Bit masks for USB_INTRRXE */ | ||
| 1001 | |||
| 1002 | #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ | ||
| 1003 | #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ | ||
| 1004 | #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ | ||
| 1005 | #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ | ||
| 1006 | #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ | ||
| 1007 | #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ | ||
| 1008 | #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ | ||
| 1009 | |||
| 1010 | /* Bit masks for USB_INTRUSB */ | ||
| 1011 | |||
| 1012 | #define SUSPEND_B 0x1 /* Suspend indicator */ | ||
| 1013 | #define RESUME_B 0x2 /* Resume indicator */ | ||
| 1014 | #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ | ||
| 1015 | #define SOF_B 0x8 /* Start of frame */ | ||
| 1016 | #define CONN_B 0x10 /* Connection indicator */ | ||
| 1017 | #define DISCON_B 0x20 /* Disconnect indicator */ | ||
| 1018 | #define SESSION_REQ_B 0x40 /* Session Request */ | ||
| 1019 | #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ | ||
| 1020 | |||
| 1021 | /* Bit masks for USB_INTRUSBE */ | ||
| 1022 | |||
| 1023 | #define SUSPEND_BE 0x1 /* Suspend indicator int enable */ | ||
| 1024 | #define RESUME_BE 0x2 /* Resume indicator int enable */ | ||
| 1025 | #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ | ||
| 1026 | #define SOF_BE 0x8 /* Start of frame int enable */ | ||
| 1027 | #define CONN_BE 0x10 /* Connection indicator int enable */ | ||
| 1028 | #define DISCON_BE 0x20 /* Disconnect indicator int enable */ | ||
| 1029 | #define SESSION_REQ_BE 0x40 /* Session Request int enable */ | ||
| 1030 | #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ | ||
| 1031 | |||
| 1032 | /* Bit masks for USB_FRAME */ | ||
| 1033 | |||
| 1034 | #define FRAME_NUMBER 0x7ff /* Frame number */ | ||
| 1035 | |||
| 1036 | /* Bit masks for USB_INDEX */ | ||
| 1037 | |||
| 1038 | #define SELECTED_ENDPOINT 0xf /* selected endpoint */ | ||
| 1039 | |||
| 1040 | /* Bit masks for USB_GLOBAL_CTL */ | ||
| 1041 | |||
| 1042 | #define GLOBAL_ENA 0x1 /* enables USB module */ | ||
| 1043 | #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ | ||
| 1044 | #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ | ||
| 1045 | #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ | ||
| 1046 | #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ | ||
| 1047 | #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ | ||
| 1048 | #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ | ||
| 1049 | #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ | ||
| 1050 | #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ | ||
| 1051 | #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ | ||
| 1052 | #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ | ||
| 1053 | #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ | ||
| 1054 | #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ | ||
| 1055 | #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ | ||
| 1056 | #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ | ||
| 1057 | |||
| 1058 | /* Bit masks for USB_OTG_DEV_CTL */ | ||
| 1059 | |||
| 1060 | #define SESSION 0x1 /* session indicator */ | ||
| 1061 | #define HOST_REQ 0x2 /* Host negotiation request */ | ||
| 1062 | #define HOST_MODE 0x4 /* indicates USBDRC is a host */ | ||
| 1063 | #define VBUS0 0x8 /* Vbus level indicator[0] */ | ||
| 1064 | #define VBUS1 0x10 /* Vbus level indicator[1] */ | ||
| 1065 | #define LSDEV 0x20 /* Low-speed indicator */ | ||
| 1066 | #define FSDEV 0x40 /* Full or High-speed indicator */ | ||
| 1067 | #define B_DEVICE 0x80 /* A' or 'B' device indicator */ | ||
| 1068 | |||
| 1069 | /* Bit masks for USB_OTG_VBUS_IRQ */ | ||
| 1070 | |||
| 1071 | #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ | ||
| 1072 | #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ | ||
| 1073 | #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ | ||
| 1074 | #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ | ||
| 1075 | #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ | ||
| 1076 | #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ | ||
| 1077 | |||
| 1078 | /* Bit masks for USB_OTG_VBUS_MASK */ | ||
| 1079 | |||
| 1080 | #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ | ||
| 1081 | #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ | ||
| 1082 | #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ | ||
| 1083 | #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ | ||
| 1084 | #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ | ||
| 1085 | #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ | ||
| 1086 | |||
| 1087 | /* Bit masks for USB_CSR0 */ | ||
| 1088 | |||
| 1089 | #define RXPKTRDY 0x1 /* data packet receive indicator */ | ||
| 1090 | #define TXPKTRDY 0x2 /* data packet in FIFO indicator */ | ||
| 1091 | #define STALL_SENT 0x4 /* STALL handshake sent */ | ||
| 1092 | #define DATAEND 0x8 /* Data end indicator */ | ||
| 1093 | #define SETUPEND 0x10 /* Setup end */ | ||
| 1094 | #define SENDSTALL 0x20 /* Send STALL handshake */ | ||
| 1095 | #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ | ||
| 1096 | #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ | ||
| 1097 | #define FLUSHFIFO 0x100 /* flush endpoint FIFO */ | ||
| 1098 | #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ | ||
| 1099 | #define SETUPPKT_H 0x8 /* send Setup token host mode */ | ||
| 1100 | #define ERROR_H 0x10 /* timeout error indicator host mode */ | ||
| 1101 | #define REQPKT_H 0x20 /* Request an IN transaction host mode */ | ||
| 1102 | #define STATUSPKT_H 0x40 /* Status stage transaction host mode */ | ||
| 1103 | #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ | ||
| 1104 | |||
| 1105 | /* Bit masks for USB_COUNT0 */ | ||
| 1106 | |||
| 1107 | #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ | ||
| 1108 | |||
| 1109 | /* Bit masks for USB_NAKLIMIT0 */ | ||
| 1110 | |||
| 1111 | #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ | ||
| 1112 | |||
| 1113 | /* Bit masks for USB_TX_MAX_PACKET */ | ||
| 1114 | |||
| 1115 | #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ | ||
| 1116 | |||
| 1117 | /* Bit masks for USB_RX_MAX_PACKET */ | ||
| 1118 | |||
| 1119 | #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ | ||
| 1120 | |||
| 1121 | /* Bit masks for USB_TXCSR */ | ||
| 1122 | |||
| 1123 | #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ | ||
| 1124 | #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ | ||
| 1125 | #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ | ||
| 1126 | #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ | ||
| 1127 | #define STALL_SEND_T 0x10 /* issue a Stall handshake */ | ||
| 1128 | #define STALL_SENT_T 0x20 /* Stall handshake transmitted */ | ||
| 1129 | #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ | ||
| 1130 | #define INCOMPTX_T 0x80 /* indicates that a large packet is split */ | ||
| 1131 | #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ | ||
| 1132 | #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ | ||
| 1133 | #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ | ||
| 1134 | #define ISO_T 0x4000 /* enable Isochronous transfers */ | ||
| 1135 | #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ | ||
| 1136 | #define ERROR_TH 0x4 /* error condition host mode */ | ||
| 1137 | #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ | ||
| 1138 | #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ | ||
| 1139 | |||
| 1140 | /* Bit masks for USB_TXCOUNT */ | ||
| 1141 | |||
| 1142 | #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ | ||
| 1143 | |||
| 1144 | /* Bit masks for USB_RXCSR */ | ||
| 1145 | |||
| 1146 | #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ | ||
| 1147 | #define FIFO_FULL_R 0x2 /* FIFO not empty */ | ||
| 1148 | #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ | ||
| 1149 | #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ | ||
| 1150 | #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ | ||
| 1151 | #define STALL_SEND_R 0x20 /* issue a Stall handshake */ | ||
| 1152 | #define STALL_SENT_R 0x40 /* Stall handshake transmitted */ | ||
| 1153 | #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ | ||
| 1154 | #define INCOMPRX_R 0x100 /* indicates that a large packet is split */ | ||
| 1155 | #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ | ||
| 1156 | #define DISNYET_R 0x1000 /* disable Nyet handshakes */ | ||
| 1157 | #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ | ||
| 1158 | #define ISO_R 0x4000 /* enable Isochronous transfers */ | ||
| 1159 | #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ | ||
| 1160 | #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ | ||
| 1161 | #define REQPKT_RH 0x20 /* request an IN transaction host mode */ | ||
| 1162 | #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ | ||
| 1163 | #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ | ||
| 1164 | #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ | ||
| 1165 | #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ | ||
| 1166 | |||
| 1167 | /* Bit masks for USB_RXCOUNT */ | ||
| 1168 | |||
| 1169 | #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ | ||
| 1170 | |||
| 1171 | /* Bit masks for USB_TXTYPE */ | ||
| 1172 | |||
| 1173 | #define TARGET_EP_NO_T 0xf /* EP number */ | ||
| 1174 | #define PROTOCOL_T 0xc /* transfer type */ | ||
| 1175 | |||
| 1176 | /* Bit masks for USB_TXINTERVAL */ | ||
| 1177 | |||
| 1178 | #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ | ||
| 1179 | |||
| 1180 | /* Bit masks for USB_RXTYPE */ | ||
| 1181 | |||
| 1182 | #define TARGET_EP_NO_R 0xf /* EP number */ | ||
| 1183 | #define PROTOCOL_R 0xc /* transfer type */ | ||
| 1184 | |||
| 1185 | /* Bit masks for USB_RXINTERVAL */ | ||
| 1186 | |||
| 1187 | #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ | ||
| 1188 | |||
| 1189 | /* Bit masks for USB_DMA_INTERRUPT */ | ||
| 1190 | |||
| 1191 | #define DMA0_INT 0x1 /* DMA0 pending interrupt */ | ||
| 1192 | #define DMA1_INT 0x2 /* DMA1 pending interrupt */ | ||
| 1193 | #define DMA2_INT 0x4 /* DMA2 pending interrupt */ | ||
| 1194 | #define DMA3_INT 0x8 /* DMA3 pending interrupt */ | ||
| 1195 | #define DMA4_INT 0x10 /* DMA4 pending interrupt */ | ||
| 1196 | #define DMA5_INT 0x20 /* DMA5 pending interrupt */ | ||
| 1197 | #define DMA6_INT 0x40 /* DMA6 pending interrupt */ | ||
| 1198 | #define DMA7_INT 0x80 /* DMA7 pending interrupt */ | ||
| 1199 | |||
| 1200 | /* Bit masks for USB_DMAxCONTROL */ | ||
| 1201 | |||
| 1202 | #define DMA_ENA 0x1 /* DMA enable */ | ||
| 1203 | #define DIRECTION 0x2 /* direction of DMA transfer */ | ||
| 1204 | #define MODE 0x4 /* DMA Bus error */ | ||
| 1205 | #define INT_ENA 0x8 /* Interrupt enable */ | ||
| 1206 | #define EPNUM 0xf0 /* EP number */ | ||
| 1207 | #define BUSERROR 0x100 /* DMA Bus error */ | ||
| 1208 | |||
| 1209 | /* Bit masks for USB_DMAxADDRHIGH */ | ||
| 1210 | |||
| 1211 | #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ | ||
| 1212 | |||
| 1213 | /* Bit masks for USB_DMAxADDRLOW */ | ||
| 1214 | |||
| 1215 | #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ | ||
| 1216 | |||
| 1217 | /* Bit masks for USB_DMAxCOUNTHIGH */ | ||
| 1218 | |||
| 1219 | #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ | ||
| 1220 | |||
| 1221 | /* Bit masks for USB_DMAxCOUNTLOW */ | ||
| 1222 | |||
| 1223 | #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ | ||
| 1224 | |||
| 1225 | /* Bit masks for HMDMAx_CONTROL */ | ||
| 1226 | |||
| 1227 | #define HMDMAEN 0x1 /* Handshake MDMA Enable */ | ||
| 1228 | #define REP 0x2 /* Handshake MDMA Request Polarity */ | ||
| 1229 | #define UTE 0x8 /* Urgency Threshold Enable */ | ||
| 1230 | #define OIE 0x10 /* Overflow Interrupt Enable */ | ||
| 1231 | #define BDIE 0x20 /* Block Done Interrupt Enable */ | ||
| 1232 | #define MBDI 0x40 /* Mask Block Done Interrupt */ | ||
| 1233 | #define DRQ 0x300 /* Handshake MDMA Request Type */ | ||
| 1234 | #define RBC 0x1000 /* Force Reload of BCOUNT */ | ||
| 1235 | #define PS 0x2000 /* Pin Status */ | ||
| 1236 | #define OI 0x4000 /* Overflow Interrupt Generated */ | ||
| 1237 | #define BDI 0x8000 /* Block Done Interrupt Generated */ | ||
| 1238 | |||
| 1239 | /* ******************************************* */ | ||
| 1240 | /* MULTI BIT MACRO ENUMERATIONS */ | ||
| 1241 | /* ******************************************* */ | ||
| 1242 | |||
| 1243 | |||
| 1244 | #endif /* _DEF_BF548_H */ | ||
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h index e46f56891e6a..1d7c96edb038 100644 --- a/include/asm-blackfin/mach-bf548/defBF548.h +++ b/include/asm-blackfin/mach-bf548/defBF548.h | |||
| @@ -1010,9 +1010,9 @@ | |||
| 1010 | #define DMA_READY 0x1 /* DMA Ready */ | 1010 | #define DMA_READY 0x1 /* DMA Ready */ |
| 1011 | #define FIFOFULL 0x2 /* FIFO Full */ | 1011 | #define FIFOFULL 0x2 /* FIFO Full */ |
| 1012 | #define FIFOEMPTY 0x4 /* FIFO Empty */ | 1012 | #define FIFOEMPTY 0x4 /* FIFO Empty */ |
| 1013 | #define COMPLETE 0x8 /* DMA Complete */ | 1013 | #define DMA_COMPLETE 0x8 /* DMA Complete */ |
| 1014 | #define HSHK 0x10 /* Host Handshake */ | 1014 | #define HSHK 0x10 /* Host Handshake */ |
| 1015 | #define TIMEOUT 0x20 /* Host Timeout */ | 1015 | #define HSTIMEOUT 0x20 /* Host Timeout */ |
| 1016 | #define HIRQ 0x40 /* Host Interrupt Request */ | 1016 | #define HIRQ 0x40 /* Host Interrupt Request */ |
| 1017 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ | 1017 | #define ALLOW_CNFG 0x80 /* Allow New Configuration */ |
| 1018 | #define DMA_DIR 0x100 /* DMA Direction */ | 1018 | #define DMA_DIR 0x100 /* DMA Direction */ |
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h index 4d97d3aa97cd..46ff31f20ae5 100644 --- a/include/asm-blackfin/mach-bf548/dma.h +++ b/include/asm-blackfin/mach-bf548/dma.h | |||
| @@ -51,9 +51,13 @@ | |||
| 51 | #define CH_PIXC_OVERLAY 16 | 51 | #define CH_PIXC_OVERLAY 16 |
| 52 | #define CH_PIXC_OUTPUT 17 | 52 | #define CH_PIXC_OUTPUT 17 |
| 53 | #define CH_SPORT2_RX 18 | 53 | #define CH_SPORT2_RX 18 |
| 54 | #define CH_UART2_RX 18 | ||
| 54 | #define CH_SPORT2_TX 19 | 55 | #define CH_SPORT2_TX 19 |
| 56 | #define CH_UART2_TX 19 | ||
| 55 | #define CH_SPORT3_RX 20 | 57 | #define CH_SPORT3_RX 20 |
| 58 | #define CH_UART3_RX 20 | ||
| 56 | #define CH_SPORT3_TX 21 | 59 | #define CH_SPORT3_TX 21 |
| 60 | #define CH_UART3_TX 21 | ||
| 57 | #define CH_SDH 22 | 61 | #define CH_SDH 22 |
| 58 | #define CH_NFC 22 | 62 | #define CH_NFC 22 |
| 59 | #define CH_SPI2 23 | 63 | #define CH_SPI2 23 |
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h index c34507a3f1df..ad380d1f5872 100644 --- a/include/asm-blackfin/mach-bf548/irq.h +++ b/include/asm-blackfin/mach-bf548/irq.h | |||
| @@ -99,9 +99,13 @@ Events (highest priority) EMU 0 | |||
| 99 | #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ | 99 | #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ |
| 100 | #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ | 100 | #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ |
| 101 | #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ | 101 | #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ |
| 102 | #define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */ | ||
| 102 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ | 103 | #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ |
| 104 | #define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */ | ||
| 103 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ | 105 | #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ |
| 106 | #define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */ | ||
| 104 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ | 107 | #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ |
| 108 | #define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */ | ||
| 105 | #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ | 109 | #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ |
| 106 | #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ | 110 | #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ |
| 107 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ | 111 | #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ |
| @@ -421,9 +425,13 @@ Events (highest priority) EMU 0 | |||
| 421 | /* IAR4 BIT FILEDS */ | 425 | /* IAR4 BIT FILEDS */ |
| 422 | #define IRQ_CAN0_ERR_POS 0 | 426 | #define IRQ_CAN0_ERR_POS 0 |
| 423 | #define IRQ_SPORT2_RX_POS 4 | 427 | #define IRQ_SPORT2_RX_POS 4 |
| 428 | #define IRQ_UART2_RX_POS 4 | ||
| 424 | #define IRQ_SPORT2_TX_POS 8 | 429 | #define IRQ_SPORT2_TX_POS 8 |
| 430 | #define IRQ_UART2_TX_POS 8 | ||
| 425 | #define IRQ_SPORT3_RX_POS 12 | 431 | #define IRQ_SPORT3_RX_POS 12 |
| 432 | #define IRQ_UART3_RX_POS 12 | ||
| 426 | #define IRQ_SPORT3_TX_POS 16 | 433 | #define IRQ_SPORT3_TX_POS 16 |
| 434 | #define IRQ_UART3_TX_POS 16 | ||
| 427 | #define IRQ_EPPI1_POS 20 | 435 | #define IRQ_EPPI1_POS 20 |
| 428 | #define IRQ_EPPI2_POS 24 | 436 | #define IRQ_EPPI2_POS 24 |
| 429 | #define IRQ_SPI1_POS 28 | 437 | #define IRQ_SPI1_POS 28 |
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h index 562aee39895c..362617f93845 100644 --- a/include/asm-blackfin/mach-bf561/blackfin.h +++ b/include/asm-blackfin/mach-bf561/blackfin.h | |||
| @@ -49,4 +49,24 @@ | |||
| 49 | #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() | 49 | #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() |
| 50 | #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) | 50 | #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) |
| 51 | 51 | ||
| 52 | |||
| 53 | #define SIC_IAR0 SICA_IAR0 | ||
| 54 | #define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 | ||
| 55 | #define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 | ||
| 56 | #define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 | ||
| 57 | #define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 | ||
| 58 | |||
| 59 | #define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 | ||
| 60 | #define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 | ||
| 61 | #define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0 | ||
| 62 | #define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1 | ||
| 63 | #define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0 | ||
| 64 | #define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1 | ||
| 65 | |||
| 66 | #define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) | ||
| 67 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) | ||
| 68 | #define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) | ||
| 69 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) | ||
| 70 | |||
| 71 | |||
| 52 | #endif /* _MACH_BLACKFIN_H_ */ | 72 | #endif /* _MACH_BLACKFIN_H_ */ |
diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h index c3fa50fa50b8..23aa1f8c1bd1 100644 --- a/include/asm-blackfin/posix_types.h +++ b/include/asm-blackfin/posix_types.h | |||
| @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; | |||
| 39 | #endif | 39 | #endif |
| 40 | 40 | ||
| 41 | typedef struct { | 41 | typedef struct { |
| 42 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 43 | int val[2]; | 42 | int val[2]; |
| 44 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 45 | int __val[2]; | ||
| 46 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 47 | } __kernel_fsid_t; | 43 | } __kernel_fsid_t; |
| 48 | 44 | ||
| 49 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 45 | #if defined(__KERNEL__) |
| 50 | 46 | ||
| 51 | #undef __FD_SET | 47 | #undef __FD_SET |
| 52 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) | 48 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) |
| @@ -60,6 +56,6 @@ typedef struct { | |||
| 60 | #undef __FD_ZERO | 56 | #undef __FD_ZERO |
| 61 | #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) | 57 | #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) |
| 62 | 58 | ||
| 63 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 59 | #endif /* defined(__KERNEL__) */ |
| 64 | 60 | ||
| 65 | #endif | 61 | #endif |
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h index c571e958558c..1033e5c76011 100644 --- a/include/asm-blackfin/processor.h +++ b/include/asm-blackfin/processor.h | |||
| @@ -30,6 +30,10 @@ static inline void wrusp(unsigned long usp) | |||
| 30 | extern unsigned long memory_end; | 30 | extern unsigned long memory_end; |
| 31 | #define TASK_SIZE (memory_end) | 31 | #define TASK_SIZE (memory_end) |
| 32 | 32 | ||
| 33 | #ifdef __KERNEL__ | ||
| 34 | #define STACK_TOP TASK_SIZE | ||
| 35 | #endif | ||
| 36 | |||
| 33 | #define TASK_UNMAPPED_BASE 0 | 37 | #define TASK_UNMAPPED_BASE 0 |
| 34 | 38 | ||
| 35 | struct thread_struct { | 39 | struct thread_struct { |
diff --git a/include/asm-blackfin/termios.h b/include/asm-blackfin/termios.h index e31fe859650b..d50d063c605a 100644 --- a/include/asm-blackfin/termios.h +++ b/include/asm-blackfin/termios.h | |||
| @@ -39,24 +39,6 @@ struct termio { | |||
| 39 | 39 | ||
| 40 | /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ | 40 | /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ |
| 41 | 41 | ||
| 42 | /* line disciplines */ | ||
| 43 | #define N_TTY 0 | ||
| 44 | #define N_SLIP 1 | ||
| 45 | #define N_MOUSE 2 | ||
| 46 | #define N_PPP 3 | ||
| 47 | #define N_STRIP 4 | ||
| 48 | #define N_AX25 5 | ||
| 49 | #define N_X25 6 /* X.25 async */ | ||
| 50 | #define N_6PACK 7 | ||
| 51 | #define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */ | ||
| 52 | #define N_R3964 9 /* Reserved for Simatic R3964 module */ | ||
| 53 | #define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */ | ||
| 54 | #define N_IRDA 11 /* Linux IR - http://irda.sourceforge.net/ */ | ||
| 55 | #define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */ | ||
| 56 | #define N_HDLC 13 /* synchronous HDLC */ | ||
| 57 | #define N_SYNC_PPP 14 /* synchronous PPP */ | ||
| 58 | #define N_HCI 15 /* Bluetooth HCI UART */ | ||
| 59 | |||
| 60 | #ifdef __KERNEL__ | 42 | #ifdef __KERNEL__ |
| 61 | 43 | ||
| 62 | /* intr=^C quit=^\ erase=del kill=^U | 44 | /* intr=^C quit=^\ erase=del kill=^U |
diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h index 6313aace9d59..ef18afbc2101 100644 --- a/include/asm-blackfin/trace.h +++ b/include/asm-blackfin/trace.h | |||
| @@ -46,42 +46,47 @@ extern unsigned long software_trace_buff[]; | |||
| 46 | 46 | ||
| 47 | #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON | 47 | #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON |
| 48 | 48 | ||
| 49 | #define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg) | ||
| 50 | #define TRACE_BUFFER_STOP(preg, dreg) trace_buffer_stop(preg, dreg) | ||
| 51 | |||
| 52 | #define trace_buffer_stop(preg, dreg) \ | 49 | #define trace_buffer_stop(preg, dreg) \ |
| 53 | preg.L = LO(TBUFCTL); \ | 50 | preg.L = LO(TBUFCTL); \ |
| 54 | preg.H = HI(TBUFCTL); \ | 51 | preg.H = HI(TBUFCTL); \ |
| 55 | dreg = 0x1; \ | 52 | dreg = 0x1; \ |
| 56 | [preg] = dreg; | 53 | [preg] = dreg; |
| 57 | 54 | ||
| 58 | #define trace_buffer_start(preg, dreg) \ | ||
| 59 | preg.L = LO(TBUFCTL); \ | ||
| 60 | preg.H = HI(TBUFCTL); \ | ||
| 61 | dreg = BFIN_TRACE_ON; \ | ||
| 62 | [preg] = dreg; | ||
| 63 | |||
| 64 | #define trace_buffer_init(preg, dreg) \ | 55 | #define trace_buffer_init(preg, dreg) \ |
| 65 | preg.L = LO(TBUFCTL); \ | 56 | preg.L = LO(TBUFCTL); \ |
| 66 | preg.H = HI(TBUFCTL); \ | 57 | preg.H = HI(TBUFCTL); \ |
| 67 | dreg = BFIN_TRACE_INIT; \ | 58 | dreg = BFIN_TRACE_INIT; \ |
| 68 | [preg] = dreg; | 59 | [preg] = dreg; |
| 69 | 60 | ||
| 61 | #define trace_buffer_save(preg, dreg) \ | ||
| 62 | preg.L = LO(TBUFCTL); \ | ||
| 63 | preg.H = HI(TBUFCTL); \ | ||
| 64 | dreg = [preg]; \ | ||
| 65 | [sp++] = dreg; \ | ||
| 66 | dreg = 0x1; \ | ||
| 67 | [preg] = dreg; | ||
| 68 | |||
| 69 | #define trace_buffer_restore(preg, dreg) \ | ||
| 70 | preg.L = LO(TBUFCTL); \ | ||
| 71 | preg.H = HI(TBUFCTL); \ | ||
| 72 | dreg = [sp--]; \ | ||
| 73 | [preg] = dreg; | ||
| 74 | |||
| 70 | #else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ | 75 | #else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ |
| 71 | 76 | ||
| 72 | #define trace_buffer_stop(preg, dreg) | 77 | #define trace_buffer_stop(preg, dreg) |
| 73 | #define trace_buffer_start(preg, dreg) | ||
| 74 | #define trace_buffer_init(preg, dreg) | 78 | #define trace_buffer_init(preg, dreg) |
| 79 | #define trace_buffer_save(preg, dreg) | ||
| 80 | #define trace_buffer_restore(preg, dreg) | ||
| 75 | 81 | ||
| 76 | #endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ | 82 | #endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ |
| 77 | 83 | ||
| 78 | #ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE | 84 | #ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE |
| 79 | # define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg) | 85 | # define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg) |
| 80 | # define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg) | 86 | # define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg) |
| 81 | |||
| 82 | #else | 87 | #else |
| 83 | # define DEBUG_START_HWTRACE(preg, dreg) | 88 | # define DEBUG_HWTRACE_SAVE(preg, dreg) |
| 84 | # define DEBUG_STOP_HWTRACE(preg, dreg) | 89 | # define DEBUG_HWTRACE_RESTORE(preg, dreg) |
| 85 | #endif | 90 | #endif |
| 86 | 91 | ||
| 87 | #endif /* __ASSEMBLY__ */ | 92 | #endif /* __ASSEMBLY__ */ |
diff --git a/include/asm-cris/Kbuild b/include/asm-cris/Kbuild index 14498d5a2f65..17455459c43f 100644 --- a/include/asm-cris/Kbuild +++ b/include/asm-cris/Kbuild | |||
| @@ -1,5 +1,11 @@ | |||
| 1 | include include/asm-generic/Kbuild.asm | 1 | include include/asm-generic/Kbuild.asm |
| 2 | 2 | ||
| 3 | header-y += arch-v10/ arch-v32/ | 3 | header-$(CONFIG_ETRAX_ARCH_V10) += arch-v10/ |
| 4 | header-$(CONFIG_ETRAX_ARCH_V32) += arch-v32/ | ||
| 4 | 5 | ||
| 6 | header-y += ethernet.h | ||
| 7 | header-y += rtc.h | ||
| 8 | header-y += sync_serial.h | ||
| 9 | |||
| 10 | unifdef-y += etraxgpio.h | ||
| 5 | unifdef-y += rs485.h | 11 | unifdef-y += rs485.h |
diff --git a/include/asm-cris/a.out.h b/include/asm-cris/a.out.h index 919b34a084f8..c82e9f9b75f6 100644 --- a/include/asm-cris/a.out.h +++ b/include/asm-cris/a.out.h | |||
| @@ -6,11 +6,6 @@ | |||
| 6 | * wants to know about a.out even if there is no interpreter available... | 6 | * wants to know about a.out even if there is no interpreter available... |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* grabbed from the intel stuff */ | ||
| 10 | #define STACK_TOP TASK_SIZE | ||
| 11 | #define STACK_TOP_MAX STACK_TOP | ||
| 12 | |||
| 13 | |||
| 14 | struct exec | 9 | struct exec |
| 15 | { | 10 | { |
| 16 | unsigned long a_info; /* Use macros N_MAGIC, etc for access */ | 11 | unsigned long a_info; /* Use macros N_MAGIC, etc for access */ |
| @@ -28,5 +23,4 @@ struct exec | |||
| 28 | #define N_DRSIZE(a) ((a).a_drsize) | 23 | #define N_DRSIZE(a) ((a).a_drsize) |
| 29 | #define N_SYMSIZE(a) ((a).a_syms) | 24 | #define N_SYMSIZE(a) ((a).a_syms) |
| 30 | 25 | ||
| 31 | |||
| 32 | #endif | 26 | #endif |
diff --git a/include/asm-cris/arch-v10/Kbuild b/include/asm-cris/arch-v10/Kbuild index d7f27dc0941a..60e7e1b73cec 100644 --- a/include/asm-cris/arch-v10/Kbuild +++ b/include/asm-cris/arch-v10/Kbuild | |||
| @@ -1,2 +1,5 @@ | |||
| 1 | header-y += ptrace.h | 1 | header-y += ptrace.h |
| 2 | header-y += user.h | 2 | header-y += user.h |
| 3 | header-y += svinto.h | ||
| 4 | header-y += sv_addr_ag.h | ||
| 5 | header-y += sv_addr.agh | ||
diff --git a/include/asm-cris/arch-v10/bug.h b/include/asm-cris/arch-v10/bug.h new file mode 100644 index 000000000000..3485d6b34bb0 --- /dev/null +++ b/include/asm-cris/arch-v10/bug.h | |||
| @@ -0,0 +1,66 @@ | |||
| 1 | #ifndef __ASM_CRISv10_ARCH_BUG_H | ||
| 2 | #define __ASM_CRISv10_ARCH_BUG_H | ||
| 3 | |||
| 4 | #include <linux/stringify.h> | ||
| 5 | |||
| 6 | #ifdef CONFIG_BUG | ||
| 7 | #ifdef CONFIG_DEBUG_BUGVERBOSE | ||
| 8 | /* The BUG() macro is used for marking obviously incorrect code paths. | ||
| 9 | * It will cause a message with the file name and line number to be printed, | ||
| 10 | * and then cause an oops. The message is actually printed by handle_BUG() | ||
| 11 | * in arch/cris/kernel/traps.c, and the reason we use this method of storing | ||
| 12 | * the file name and line number is that we do not want to affect the registers | ||
| 13 | * by calling printk() before causing the oops. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #define BUG_PREFIX 0x0D7F | ||
| 17 | #define BUG_MAGIC 0x00001234 | ||
| 18 | |||
| 19 | struct bug_frame { | ||
| 20 | unsigned short prefix; | ||
| 21 | unsigned int magic; | ||
| 22 | unsigned short clear; | ||
| 23 | unsigned short movu; | ||
| 24 | unsigned short line; | ||
| 25 | unsigned short jump; | ||
| 26 | unsigned char *filename; | ||
| 27 | }; | ||
| 28 | |||
| 29 | #if 0 | ||
| 30 | /* Unfortunately this version of the macro does not work due to a problem | ||
| 31 | * with the compiler (aka a bug) when compiling with -O2, which sometimes | ||
| 32 | * erroneously causes the second input to be stored in a register... | ||
| 33 | */ | ||
| 34 | #define BUG() \ | ||
| 35 | __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ | ||
| 36 | "movu.w %0,$r0\n\t" \ | ||
| 37 | "jump %1\n\t" \ | ||
| 38 | : : "i" (__LINE__), "i" (__FILE__)) | ||
| 39 | #else | ||
| 40 | /* This version will have to do for now, until the compiler is fixed. | ||
| 41 | * The drawbacks of this version are that the file name will appear multiple | ||
| 42 | * times in the .rodata section, and that __LINE__ and __FILE__ can probably | ||
| 43 | * not be used like this with newer versions of gcc. | ||
| 44 | */ | ||
| 45 | #define BUG() \ | ||
| 46 | __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ | ||
| 47 | "movu.w " __stringify(__LINE__) ",$r0\n\t"\ | ||
| 48 | "jump 0f\n\t" \ | ||
| 49 | ".section .rodata\n" \ | ||
| 50 | "0:\t.string \"" __FILE__ "\"\n\t" \ | ||
| 51 | ".previous") | ||
| 52 | #endif | ||
| 53 | |||
| 54 | #else | ||
| 55 | |||
| 56 | /* This just causes an oops. */ | ||
| 57 | #define BUG() (*(int *)0 = 0) | ||
| 58 | |||
| 59 | #endif | ||
| 60 | |||
| 61 | #define HAVE_ARCH_BUG | ||
| 62 | #endif | ||
| 63 | |||
| 64 | #include <asm-generic/bug.h> | ||
| 65 | |||
| 66 | #endif | ||
diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h index 11ef5b53d84e..c08c24265299 100644 --- a/include/asm-cris/arch-v10/io.h +++ b/include/asm-cris/arch-v10/io.h | |||
| @@ -23,7 +23,7 @@ extern volatile unsigned long *port_cse1_addr; | |||
| 23 | extern volatile unsigned long *port_csp0_addr; | 23 | extern volatile unsigned long *port_csp0_addr; |
| 24 | extern volatile unsigned long *port_csp4_addr; | 24 | extern volatile unsigned long *port_csp4_addr; |
| 25 | 25 | ||
| 26 | /* macro for setting regs through a shadow - | 26 | /* macro for setting regs through a shadow - |
| 27 | * r = register name (like R_PORT_PA_DATA) | 27 | * r = register name (like R_PORT_PA_DATA) |
| 28 | * s = shadow name (like port_pa_data_shadow) | 28 | * s = shadow name (like port_pa_data_shadow) |
| 29 | * b = bit number | 29 | * b = bit number |
| @@ -38,83 +38,89 @@ extern volatile unsigned long *port_csp4_addr; | |||
| 38 | #undef CONFIG_ETRAX_PA_LEDS | 38 | #undef CONFIG_ETRAX_PA_LEDS |
| 39 | #undef CONFIG_ETRAX_PB_LEDS | 39 | #undef CONFIG_ETRAX_PB_LEDS |
| 40 | #undef CONFIG_ETRAX_CSP0_LEDS | 40 | #undef CONFIG_ETRAX_CSP0_LEDS |
| 41 | #define LED_NETWORK_SET_G(x) | 41 | #define CRIS_LED_NETWORK_SET_G(x) |
| 42 | #define LED_NETWORK_SET_R(x) | 42 | #define CRIS_LED_NETWORK_SET_R(x) |
| 43 | #define LED_ACTIVE_SET_G(x) | 43 | #define CRIS_LED_ACTIVE_SET_G(x) |
| 44 | #define LED_ACTIVE_SET_R(x) | 44 | #define CRIS_LED_ACTIVE_SET_R(x) |
| 45 | #define LED_DISK_WRITE(x) | 45 | #define CRIS_LED_DISK_WRITE(x) |
| 46 | #define LED_DISK_READ(x) | 46 | #define CRIS_LED_DISK_READ(x) |
| 47 | #endif | 47 | #endif |
| 48 | 48 | ||
| 49 | #if !defined(CONFIG_ETRAX_CSP0_LEDS) | 49 | #if !defined(CONFIG_ETRAX_CSP0_LEDS) |
| 50 | #define LED_BIT_SET(x) | 50 | #define CRIS_LED_BIT_SET(x) |
| 51 | #define LED_BIT_CLR(x) | 51 | #define CRIS_LED_BIT_CLR(x) |
| 52 | #endif | 52 | #endif |
| 53 | 53 | ||
| 54 | #define LED_OFF 0x00 | 54 | #define CRIS_LED_OFF 0x00 |
| 55 | #define LED_GREEN 0x01 | 55 | #define CRIS_LED_GREEN 0x01 |
| 56 | #define LED_RED 0x02 | 56 | #define CRIS_LED_RED 0x02 |
| 57 | #define LED_ORANGE (LED_GREEN | LED_RED) | 57 | #define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) |
| 58 | 58 | ||
| 59 | #if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R | 59 | #if defined(CONFIG_ETRAX_NO_LEDS) |
| 60 | #define LED_NETWORK_SET(x) \ | 60 | #define CRIS_LED_NETWORK_SET(x) |
| 61 | #else | ||
| 62 | #if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R | ||
| 63 | #define CRIS_LED_NETWORK_SET(x) \ | ||
| 61 | do { \ | 64 | do { \ |
| 62 | LED_NETWORK_SET_G((x) & LED_GREEN); \ | 65 | CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ |
| 63 | } while (0) | 66 | } while (0) |
| 64 | #else | 67 | #else |
| 65 | #define LED_NETWORK_SET(x) \ | 68 | #define CRIS_LED_NETWORK_SET(x) \ |
| 66 | do { \ | 69 | do { \ |
| 67 | LED_NETWORK_SET_G((x) & LED_GREEN); \ | 70 | CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ |
| 68 | LED_NETWORK_SET_R((x) & LED_RED); \ | 71 | CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \ |
| 69 | } while (0) | 72 | } while (0) |
| 70 | #endif | 73 | #endif |
| 71 | #if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R | 74 | #if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R |
| 72 | #define LED_ACTIVE_SET(x) \ | 75 | #define CRIS_LED_ACTIVE_SET(x) \ |
| 73 | do { \ | 76 | do { \ |
| 74 | LED_ACTIVE_SET_G((x) & LED_GREEN); \ | 77 | CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ |
| 75 | } while (0) | 78 | } while (0) |
| 76 | #else | 79 | #else |
| 77 | #define LED_ACTIVE_SET(x) \ | 80 | #define CRIS_LED_ACTIVE_SET(x) \ |
| 78 | do { \ | 81 | do { \ |
| 79 | LED_ACTIVE_SET_G((x) & LED_GREEN); \ | 82 | CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ |
| 80 | LED_ACTIVE_SET_R((x) & LED_RED); \ | 83 | CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ |
| 81 | } while (0) | 84 | } while (0) |
| 82 | #endif | 85 | #endif |
| 86 | #endif | ||
| 83 | 87 | ||
| 84 | #ifdef CONFIG_ETRAX_PA_LEDS | 88 | #ifdef CONFIG_ETRAX_PA_LEDS |
| 85 | #define LED_NETWORK_SET_G(x) \ | 89 | #define CRIS_LED_NETWORK_SET_G(x) \ |
| 86 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x)) | 90 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x)) |
| 87 | #define LED_NETWORK_SET_R(x) \ | 91 | #define CRIS_LED_NETWORK_SET_R(x) \ |
| 88 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x)) | 92 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x)) |
| 89 | #define LED_ACTIVE_SET_G(x) \ | 93 | #define CRIS_LED_ACTIVE_SET_G(x) \ |
| 90 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x)) | 94 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x)) |
| 91 | #define LED_ACTIVE_SET_R(x) \ | 95 | #define CRIS_LED_ACTIVE_SET_R(x) \ |
| 92 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x)) | 96 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x)) |
| 93 | #define LED_DISK_WRITE(x) \ | 97 | #define CRIS_LED_DISK_WRITE(x) \ |
| 94 | do{\ | 98 | do{\ |
| 95 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ | 99 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ |
| 96 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ | 100 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ |
| 97 | }while(0) | 101 | }while(0) |
| 98 | #define LED_DISK_READ(x) \ | 102 | #define CRIS_LED_DISK_READ(x) \ |
| 99 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x)) | 103 | REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \ |
| 104 | CONFIG_ETRAX_LED3G, !(x)) | ||
| 100 | #endif | 105 | #endif |
| 101 | 106 | ||
| 102 | #ifdef CONFIG_ETRAX_PB_LEDS | 107 | #ifdef CONFIG_ETRAX_PB_LEDS |
| 103 | #define LED_NETWORK_SET_G(x) \ | 108 | #define CRIS_LED_NETWORK_SET_G(x) \ |
| 104 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x)) | 109 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x)) |
| 105 | #define LED_NETWORK_SET_R(x) \ | 110 | #define CRIS_LED_NETWORK_SET_R(x) \ |
| 106 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x)) | 111 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x)) |
| 107 | #define LED_ACTIVE_SET_G(x) \ | 112 | #define CRIS_LED_ACTIVE_SET_G(x) \ |
| 108 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x)) | 113 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x)) |
| 109 | #define LED_ACTIVE_SET_R(x) \ | 114 | #define CRIS_LED_ACTIVE_SET_R(x) \ |
| 110 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x)) | 115 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x)) |
| 111 | #define LED_DISK_WRITE(x) \ | 116 | #define CRIS_LED_DISK_WRITE(x) \ |
| 112 | do{\ | 117 | do{\ |
| 113 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ | 118 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ |
| 114 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ | 119 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ |
| 115 | }while(0) | 120 | }while(0) |
| 116 | #define LED_DISK_READ(x) \ | 121 | #define CRIS_LED_DISK_READ(x) \ |
| 117 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x)) | 122 | REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \ |
| 123 | CONFIG_ETRAX_LED3G, !(x)) | ||
| 118 | #endif | 124 | #endif |
| 119 | 125 | ||
| 120 | #ifdef CONFIG_ETRAX_CSP0_LEDS | 126 | #ifdef CONFIG_ETRAX_CSP0_LEDS |
| @@ -130,27 +136,27 @@ extern volatile unsigned long *port_csp4_addr; | |||
| 130 | (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\ | 136 | (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\ |
| 131 | (1 << CONFIG_ETRAX_LED12R )) | 137 | (1 << CONFIG_ETRAX_LED12R )) |
| 132 | 138 | ||
| 133 | #define LED_NETWORK_SET_G(x) \ | 139 | #define CRIS_LED_NETWORK_SET_G(x) \ |
| 134 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x)) | 140 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x)) |
| 135 | #define LED_NETWORK_SET_R(x) \ | 141 | #define CRIS_LED_NETWORK_SET_R(x) \ |
| 136 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x)) | 142 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x)) |
| 137 | #define LED_ACTIVE_SET_G(x) \ | 143 | #define CRIS_LED_ACTIVE_SET_G(x) \ |
| 138 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x)) | 144 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x)) |
| 139 | #define LED_ACTIVE_SET_R(x) \ | 145 | #define CRIS_LED_ACTIVE_SET_R(x) \ |
| 140 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x)) | 146 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x)) |
| 141 | #define LED_DISK_WRITE(x) \ | 147 | #define CRIS_LED_DISK_WRITE(x) \ |
| 142 | do{\ | 148 | do{\ |
| 143 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\ | 149 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\ |
| 144 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\ | 150 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\ |
| 145 | }while(0) | 151 | }while(0) |
| 146 | #define LED_DISK_READ(x) \ | 152 | #define CRIS_LED_DISK_READ(x) \ |
| 147 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x)) | 153 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x)) |
| 148 | #define LED_BIT_SET(x)\ | 154 | #define CRIS_LED_BIT_SET(x)\ |
| 149 | do{\ | 155 | do{\ |
| 150 | if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ | 156 | if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ |
| 151 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\ | 157 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\ |
| 152 | }while(0) | 158 | }while(0) |
| 153 | #define LED_BIT_CLR(x)\ | 159 | #define CRIS_LED_BIT_CLR(x)\ |
| 154 | do{\ | 160 | do{\ |
| 155 | if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ | 161 | if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ |
| 156 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\ | 162 | REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\ |
diff --git a/include/asm-cris/arch-v10/page.h b/include/asm-cris/arch-v10/page.h index 7d8307aed7f3..ffafc99c3472 100644 --- a/include/asm-cris/arch-v10/page.h +++ b/include/asm-cris/arch-v10/page.h | |||
| @@ -12,8 +12,8 @@ | |||
| 12 | #endif | 12 | #endif |
| 13 | 13 | ||
| 14 | /* macros to convert between really physical and virtual addresses | 14 | /* macros to convert between really physical and virtual addresses |
| 15 | * by stripping a selected bit, we can convert between KSEG_x and 0x40000000 where | 15 | * by stripping a selected bit, we can convert between KSEG_x and |
| 16 | * the DRAM really resides | 16 | * 0x40000000 where the DRAM really resides |
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #ifdef CONFIG_CRIS_LOW_MAP | 19 | #ifdef CONFIG_CRIS_LOW_MAP |
diff --git a/include/asm-cris/arch-v32/Kbuild b/include/asm-cris/arch-v32/Kbuild index d7f27dc0941a..a0ec545e242e 100644 --- a/include/asm-cris/arch-v32/Kbuild +++ b/include/asm-cris/arch-v32/Kbuild | |||
| @@ -1,2 +1,3 @@ | |||
| 1 | header-y += ptrace.h | 1 | header-y += ptrace.h |
| 2 | header-y += user.h | 2 | header-y += user.h |
| 3 | header-y += cryptocop.h | ||
diff --git a/include/asm-cris/arch-v32/atomic.h b/include/asm-cris/arch-v32/atomic.h index bbfb7a5ae315..852ceff8013f 100644 --- a/include/asm-cris/arch-v32/atomic.h +++ b/include/asm-cris/arch-v32/atomic.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | #ifndef __ASM_CRIS_ARCH_ATOMIC__ | 1 | #ifndef __ASM_CRIS_ARCH_ATOMIC__ |
| 2 | #define __ASM_CRIS_ARCH_ATOMIC__ | 2 | #define __ASM_CRIS_ARCH_ATOMIC__ |
| 3 | 3 | ||
| 4 | #include <asm/system.h> | 4 | #include <linux/spinlock_types.h> |
| 5 | 5 | ||
| 6 | extern void cris_spin_unlock(void *l, int val); | 6 | extern void cris_spin_unlock(void *l, int val); |
| 7 | extern void cris_spin_lock(void *l); | 7 | extern void cris_spin_lock(void *l); |
| @@ -18,15 +18,15 @@ extern spinlock_t cris_atomic_locks[]; | |||
| 18 | 18 | ||
| 19 | #define cris_atomic_save(addr, flags) \ | 19 | #define cris_atomic_save(addr, flags) \ |
| 20 | local_irq_save(flags); \ | 20 | local_irq_save(flags); \ |
| 21 | cris_spin_lock((void*)&cris_atomic_locks[HASH_ADDR(addr)].lock); | 21 | cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock); |
| 22 | 22 | ||
| 23 | #define cris_atomic_restore(addr, flags) \ | 23 | #define cris_atomic_restore(addr, flags) \ |
| 24 | { \ | 24 | { \ |
| 25 | spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \ | 25 | spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \ |
| 26 | __asm__ volatile ("move.d %1,%0" \ | 26 | __asm__ volatile ("move.d %1,%0" \ |
| 27 | : "=m" (lock->lock) \ | 27 | : "=m" (lock->raw_lock.slock) \ |
| 28 | : "r" (1) \ | 28 | : "r" (1) \ |
| 29 | : "memory"); \ | 29 | : "memory"); \ |
| 30 | local_irq_restore(flags); \ | 30 | local_irq_restore(flags); \ |
| 31 | } | 31 | } |
| 32 | 32 | ||
diff --git a/include/asm-cris/arch-v32/bug.h b/include/asm-cris/arch-v32/bug.h new file mode 100644 index 000000000000..0f211e135248 --- /dev/null +++ b/include/asm-cris/arch-v32/bug.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | #ifndef __ASM_CRISv32_ARCH_BUG_H | ||
| 2 | #define __ASM_CRISv32_ARCH_BUG_H | ||
| 3 | |||
| 4 | #include <linux/stringify.h> | ||
| 5 | |||
| 6 | #ifdef CONFIG_BUG | ||
| 7 | #ifdef CONFIG_DEBUG_BUGVERBOSE | ||
| 8 | /* | ||
| 9 | * The penalty for the in-band code path will be the size of break 14. | ||
| 10 | * All other stuff is done out-of-band with exception handlers. | ||
| 11 | */ | ||
| 12 | #define BUG() \ | ||
| 13 | __asm__ __volatile__ ("0: break 14\n\t" \ | ||
| 14 | ".section .fixup,\"ax\"\n" \ | ||
| 15 | "1:\n\t" \ | ||
| 16 | "move.d %0, $r10\n\t" \ | ||
| 17 | "move.d %1, $r11\n\t" \ | ||
| 18 | "jump do_BUG\n\t" \ | ||
| 19 | "nop\n\t" \ | ||
| 20 | ".previous\n\t" \ | ||
| 21 | ".section __ex_table,\"a\"\n\t" \ | ||
| 22 | ".dword 0b, 1b\n\t" \ | ||
| 23 | ".previous\n\t" \ | ||
| 24 | : : "ri" (__FILE__), "i" (__LINE__)) | ||
| 25 | #else | ||
| 26 | #define BUG() __asm__ __volatile__ ("break 14\n\t") | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #define HAVE_ARCH_BUG | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #include <asm-generic/bug.h> | ||
| 33 | #endif | ||
diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h index 80b236b15319..b3d752dfe15b 100644 --- a/include/asm-cris/arch-v32/cache.h +++ b/include/asm-cris/arch-v32/cache.h | |||
| @@ -1,8 +1,19 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_CACHE_H | 1 | #ifndef _ASM_CRIS_ARCH_CACHE_H |
| 2 | #define _ASM_CRIS_ARCH_CACHE_H | 2 | #define _ASM_CRIS_ARCH_CACHE_H |
| 3 | 3 | ||
| 4 | #include <asm/arch/hwregs/dma.h> | ||
| 5 | |||
| 4 | /* A cache-line is 32 bytes. */ | 6 | /* A cache-line is 32 bytes. */ |
| 5 | #define L1_CACHE_BYTES 32 | 7 | #define L1_CACHE_BYTES 32 |
| 6 | #define L1_CACHE_SHIFT 5 | 8 | #define L1_CACHE_SHIFT 5 |
| 7 | 9 | ||
| 10 | void flush_dma_list(dma_descr_data *descr); | ||
| 11 | void flush_dma_descr(dma_descr_data *descr, int flush_buf); | ||
| 12 | |||
| 13 | #define flush_dma_context(c) \ | ||
| 14 | flush_dma_list(phys_to_virt((c)->saved_data)); | ||
| 15 | |||
| 16 | void cris_flush_cache_range(void *buf, unsigned long len); | ||
| 17 | void cris_flush_cache(void); | ||
| 18 | |||
| 8 | #endif /* _ASM_CRIS_ARCH_CACHE_H */ | 19 | #endif /* _ASM_CRIS_ARCH_CACHE_H */ |
diff --git a/include/asm-cris/arch-v32/delay.h b/include/asm-cris/arch-v32/delay.h index b6e941e637de..e9fda03810a9 100644 --- a/include/asm-cris/arch-v32/delay.h +++ b/include/asm-cris/arch-v32/delay.h | |||
| @@ -1,6 +1,16 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_DELAY_H | 1 | #ifndef _ASM_CRIS_ARCH_DELAY_H |
| 2 | #define _ASM_CRIS_ARCH_DELAY_H | 2 | #define _ASM_CRIS_ARCH_DELAY_H |
| 3 | 3 | ||
| 4 | extern void cris_delay10ns(u32 n10ns); | ||
| 5 | #define udelay(u) cris_delay10ns((u)*100) | ||
| 6 | #define ndelay(n) cris_delay10ns(((n)+9)/10) | ||
| 7 | |||
| 8 | /* | ||
| 9 | * Not used anymore for udelay or ndelay. Referenced by | ||
| 10 | * e.g. init/calibrate.c. All other references are likely bugs; | ||
| 11 | * should be replaced by mdelay, udelay or ndelay. | ||
| 12 | */ | ||
| 13 | |||
| 4 | static inline void | 14 | static inline void |
| 5 | __delay(int loops) | 15 | __delay(int loops) |
| 6 | { | 16 | { |
diff --git a/include/asm-cris/arch-v32/hwregs/Makefile b/include/asm-cris/arch-v32/hwregs/Makefile index c9160f9949a9..f9a05d2aa061 100644 --- a/include/asm-cris/arch-v32/hwregs/Makefile +++ b/include/asm-cris/arch-v32/hwregs/Makefile | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | # $Id: Makefile,v 1.8 2004/01/07 21:16:18 johana Exp $ | ||
| 2 | # Makefile to generate or copy the latest register definitions | 1 | # Makefile to generate or copy the latest register definitions |
| 3 | # and related datastructures and helpermacros. | 2 | # and related datastructures and helpermacros. |
| 4 | # The offical place for these files is at: | 3 | # The offical place for these files is at: |
diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h index c31832d3d6be..3ce322b5c731 100644 --- a/include/asm-cris/arch-v32/hwregs/dma.h +++ b/include/asm-cris/arch-v32/hwregs/dma.h | |||
| @@ -1,5 +1,4 @@ | |||
| 1 | /* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ | 1 | /* |
| 2 | * | ||
| 3 | * DMA C definitions and help macros | 2 | * DMA C definitions and help macros |
| 4 | * | 3 | * |
| 5 | */ | 4 | */ |
| @@ -98,11 +97,11 @@ typedef struct dma_descr_data { | |||
| 98 | 97 | ||
| 99 | // give stream command | 98 | // give stream command |
| 100 | #define DMA_WR_CMD( inst, cmd_par ) \ | 99 | #define DMA_WR_CMD( inst, cmd_par ) \ |
| 101 | do { reg_dma_rw_stream_cmd r = {0}; \ | 100 | do { reg_dma_rw_stream_cmd __x = {0}; \ |
| 102 | do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \ | 101 | do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \ |
| 103 | r.cmd = (cmd_par); \ | 102 | __x.cmd = (cmd_par); \ |
| 104 | REG_WR( dma, inst, rw_stream_cmd, r ); \ | 103 | REG_WR(dma, inst, rw_stream_cmd, __x); \ |
| 105 | } while( 0 ) | 104 | } while (0) |
| 106 | 105 | ||
| 107 | // load: g,c,d:burst | 106 | // load: g,c,d:burst |
| 108 | #define DMA_START_GROUP( inst, group_descr ) \ | 107 | #define DMA_START_GROUP( inst, group_descr ) \ |
diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h index 1196d7cc783f..90fe8a28894f 100644 --- a/include/asm-cris/arch-v32/hwregs/eth_defs.h +++ b/include/asm-cris/arch-v32/hwregs/eth_defs.h | |||
| @@ -3,12 +3,12 @@ | |||
| 3 | 3 | ||
| 4 | /* | 4 | /* |
| 5 | * This file is autogenerated from | 5 | * This file is autogenerated from |
| 6 | * file: ../../inst/eth/rtl/eth_regs.r | 6 | * file: eth.r |
| 7 | * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp | 7 | * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp |
| 8 | * last modfied: Mon Apr 11 16:07:03 2005 | 8 | * last modfied: Mon Jan 9 06:06:41 2006 |
| 9 | * | 9 | * |
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r | 10 | * by /n/asic/design/tools/rdesc/rdes2c eth.r |
| 11 | * id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ | 11 | * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ |
| 12 | * Any changes here will be lost. | 12 | * Any changes here will be lost. |
| 13 | * | 13 | * |
| 14 | * -*- buffer-read-only: t -*- | 14 | * -*- buffer-read-only: t -*- |
| @@ -116,26 +116,28 @@ typedef struct { | |||
| 116 | 116 | ||
| 117 | /* Register rw_ga_lo, scope eth, type rw */ | 117 | /* Register rw_ga_lo, scope eth, type rw */ |
| 118 | typedef struct { | 118 | typedef struct { |
| 119 | unsigned int table : 32; | 119 | unsigned int tbl : 32; |
| 120 | } reg_eth_rw_ga_lo; | 120 | } reg_eth_rw_ga_lo; |
| 121 | #define REG_RD_ADDR_eth_rw_ga_lo 16 | 121 | #define REG_RD_ADDR_eth_rw_ga_lo 16 |
| 122 | #define REG_WR_ADDR_eth_rw_ga_lo 16 | 122 | #define REG_WR_ADDR_eth_rw_ga_lo 16 |
| 123 | 123 | ||
| 124 | /* Register rw_ga_hi, scope eth, type rw */ | 124 | /* Register rw_ga_hi, scope eth, type rw */ |
| 125 | typedef struct { | 125 | typedef struct { |
| 126 | unsigned int table : 32; | 126 | unsigned int tbl : 32; |
| 127 | } reg_eth_rw_ga_hi; | 127 | } reg_eth_rw_ga_hi; |
| 128 | #define REG_RD_ADDR_eth_rw_ga_hi 20 | 128 | #define REG_RD_ADDR_eth_rw_ga_hi 20 |
| 129 | #define REG_WR_ADDR_eth_rw_ga_hi 20 | 129 | #define REG_WR_ADDR_eth_rw_ga_hi 20 |
| 130 | 130 | ||
| 131 | /* Register rw_gen_ctrl, scope eth, type rw */ | 131 | /* Register rw_gen_ctrl, scope eth, type rw */ |
| 132 | typedef struct { | 132 | typedef struct { |
| 133 | unsigned int en : 1; | 133 | unsigned int en : 1; |
| 134 | unsigned int phy : 2; | 134 | unsigned int phy : 2; |
| 135 | unsigned int protocol : 1; | 135 | unsigned int protocol : 1; |
| 136 | unsigned int loopback : 1; | 136 | unsigned int loopback : 1; |
| 137 | unsigned int flow_ctrl_dis : 1; | 137 | unsigned int flow_ctrl : 1; |
| 138 | unsigned int dummy1 : 26; | 138 | unsigned int gtxclk_out : 1; |
| 139 | unsigned int phyrst_n : 1; | ||
| 140 | unsigned int dummy1 : 24; | ||
| 139 | } reg_eth_rw_gen_ctrl; | 141 | } reg_eth_rw_gen_ctrl; |
| 140 | #define REG_RD_ADDR_eth_rw_gen_ctrl 24 | 142 | #define REG_RD_ADDR_eth_rw_gen_ctrl 24 |
| 141 | #define REG_WR_ADDR_eth_rw_gen_ctrl 24 | 143 | #define REG_WR_ADDR_eth_rw_gen_ctrl 24 |
| @@ -150,22 +152,23 @@ typedef struct { | |||
| 150 | unsigned int oversize : 1; | 152 | unsigned int oversize : 1; |
| 151 | unsigned int bad_crc : 1; | 153 | unsigned int bad_crc : 1; |
| 152 | unsigned int duplex : 1; | 154 | unsigned int duplex : 1; |
| 153 | unsigned int max_size : 1; | 155 | unsigned int max_size : 16; |
| 154 | unsigned int dummy1 : 23; | 156 | unsigned int dummy1 : 8; |
| 155 | } reg_eth_rw_rec_ctrl; | 157 | } reg_eth_rw_rec_ctrl; |
| 156 | #define REG_RD_ADDR_eth_rw_rec_ctrl 28 | 158 | #define REG_RD_ADDR_eth_rw_rec_ctrl 28 |
| 157 | #define REG_WR_ADDR_eth_rw_rec_ctrl 28 | 159 | #define REG_WR_ADDR_eth_rw_rec_ctrl 28 |
| 158 | 160 | ||
| 159 | /* Register rw_tr_ctrl, scope eth, type rw */ | 161 | /* Register rw_tr_ctrl, scope eth, type rw */ |
| 160 | typedef struct { | 162 | typedef struct { |
| 161 | unsigned int crc : 1; | 163 | unsigned int crc : 1; |
| 162 | unsigned int pad : 1; | 164 | unsigned int pad : 1; |
| 163 | unsigned int retry : 1; | 165 | unsigned int retry : 1; |
| 164 | unsigned int ignore_col : 1; | 166 | unsigned int ignore_col : 1; |
| 165 | unsigned int cancel : 1; | 167 | unsigned int cancel : 1; |
| 166 | unsigned int hsh_delay : 1; | 168 | unsigned int hsh_delay : 1; |
| 167 | unsigned int ignore_crs : 1; | 169 | unsigned int ignore_crs : 1; |
| 168 | unsigned int dummy1 : 25; | 170 | unsigned int carrier_ext : 1; |
| 171 | unsigned int dummy1 : 24; | ||
| 169 | } reg_eth_rw_tr_ctrl; | 172 | } reg_eth_rw_tr_ctrl; |
| 170 | #define REG_RD_ADDR_eth_rw_tr_ctrl 32 | 173 | #define REG_RD_ADDR_eth_rw_tr_ctrl 32 |
| 171 | #define REG_WR_ADDR_eth_rw_tr_ctrl 32 | 174 | #define REG_WR_ADDR_eth_rw_tr_ctrl 32 |
| @@ -180,13 +183,10 @@ typedef struct { | |||
| 180 | 183 | ||
| 181 | /* Register rw_mgm_ctrl, scope eth, type rw */ | 184 | /* Register rw_mgm_ctrl, scope eth, type rw */ |
| 182 | typedef struct { | 185 | typedef struct { |
| 183 | unsigned int mdio : 1; | 186 | unsigned int mdio : 1; |
| 184 | unsigned int mdoe : 1; | 187 | unsigned int mdoe : 1; |
| 185 | unsigned int mdc : 1; | 188 | unsigned int mdc : 1; |
| 186 | unsigned int phyclk : 1; | 189 | unsigned int dummy1 : 29; |
| 187 | unsigned int txdata : 4; | ||
| 188 | unsigned int txen : 1; | ||
| 189 | unsigned int dummy1 : 23; | ||
| 190 | } reg_eth_rw_mgm_ctrl; | 190 | } reg_eth_rw_mgm_ctrl; |
| 191 | #define REG_RD_ADDR_eth_rw_mgm_ctrl 40 | 191 | #define REG_RD_ADDR_eth_rw_mgm_ctrl 40 |
| 192 | #define REG_WR_ADDR_eth_rw_mgm_ctrl 40 | 192 | #define REG_WR_ADDR_eth_rw_mgm_ctrl 40 |
| @@ -196,17 +196,8 @@ typedef struct { | |||
| 196 | unsigned int mdio : 1; | 196 | unsigned int mdio : 1; |
| 197 | unsigned int exc_col : 1; | 197 | unsigned int exc_col : 1; |
| 198 | unsigned int urun : 1; | 198 | unsigned int urun : 1; |
| 199 | unsigned int phyclk : 1; | 199 | unsigned int clk_125 : 1; |
| 200 | unsigned int txdata : 4; | 200 | unsigned int dummy1 : 28; |
| 201 | unsigned int txen : 1; | ||
| 202 | unsigned int col : 1; | ||
| 203 | unsigned int crs : 1; | ||
| 204 | unsigned int txclk : 1; | ||
| 205 | unsigned int rxdata : 4; | ||
| 206 | unsigned int rxer : 1; | ||
| 207 | unsigned int rxdv : 1; | ||
| 208 | unsigned int rxclk : 1; | ||
| 209 | unsigned int dummy1 : 13; | ||
| 210 | } reg_eth_r_stat; | 201 | } reg_eth_r_stat; |
| 211 | #define REG_RD_ADDR_eth_r_stat 44 | 202 | #define REG_RD_ADDR_eth_r_stat 44 |
| 212 | 203 | ||
| @@ -274,83 +265,83 @@ typedef struct { | |||
| 274 | 265 | ||
| 275 | /* Register rw_intr_mask, scope eth, type rw */ | 266 | /* Register rw_intr_mask, scope eth, type rw */ |
| 276 | typedef struct { | 267 | typedef struct { |
| 277 | unsigned int crc : 1; | 268 | unsigned int crc : 1; |
| 278 | unsigned int align : 1; | 269 | unsigned int align : 1; |
| 279 | unsigned int oversize : 1; | 270 | unsigned int oversize : 1; |
| 280 | unsigned int congestion : 1; | 271 | unsigned int congestion : 1; |
| 281 | unsigned int single_col : 1; | 272 | unsigned int single_col : 1; |
| 282 | unsigned int mult_col : 1; | 273 | unsigned int mult_col : 1; |
| 283 | unsigned int late_col : 1; | 274 | unsigned int late_col : 1; |
| 284 | unsigned int deferred : 1; | 275 | unsigned int deferred : 1; |
| 285 | unsigned int carrier_loss : 1; | 276 | unsigned int carrier_loss : 1; |
| 286 | unsigned int sqe_test_err : 1; | 277 | unsigned int sqe_test_err : 1; |
| 287 | unsigned int orun : 1; | 278 | unsigned int orun : 1; |
| 288 | unsigned int urun : 1; | 279 | unsigned int urun : 1; |
| 289 | unsigned int excessive_col : 1; | 280 | unsigned int exc_col : 1; |
| 290 | unsigned int mdio : 1; | 281 | unsigned int mdio : 1; |
| 291 | unsigned int dummy1 : 18; | 282 | unsigned int dummy1 : 18; |
| 292 | } reg_eth_rw_intr_mask; | 283 | } reg_eth_rw_intr_mask; |
| 293 | #define REG_RD_ADDR_eth_rw_intr_mask 76 | 284 | #define REG_RD_ADDR_eth_rw_intr_mask 76 |
| 294 | #define REG_WR_ADDR_eth_rw_intr_mask 76 | 285 | #define REG_WR_ADDR_eth_rw_intr_mask 76 |
| 295 | 286 | ||
| 296 | /* Register rw_ack_intr, scope eth, type rw */ | 287 | /* Register rw_ack_intr, scope eth, type rw */ |
| 297 | typedef struct { | 288 | typedef struct { |
| 298 | unsigned int crc : 1; | 289 | unsigned int crc : 1; |
| 299 | unsigned int align : 1; | 290 | unsigned int align : 1; |
| 300 | unsigned int oversize : 1; | 291 | unsigned int oversize : 1; |
| 301 | unsigned int congestion : 1; | 292 | unsigned int congestion : 1; |
| 302 | unsigned int single_col : 1; | 293 | unsigned int single_col : 1; |
| 303 | unsigned int mult_col : 1; | 294 | unsigned int mult_col : 1; |
| 304 | unsigned int late_col : 1; | 295 | unsigned int late_col : 1; |
| 305 | unsigned int deferred : 1; | 296 | unsigned int deferred : 1; |
| 306 | unsigned int carrier_loss : 1; | 297 | unsigned int carrier_loss : 1; |
| 307 | unsigned int sqe_test_err : 1; | 298 | unsigned int sqe_test_err : 1; |
| 308 | unsigned int orun : 1; | 299 | unsigned int orun : 1; |
| 309 | unsigned int urun : 1; | 300 | unsigned int urun : 1; |
| 310 | unsigned int excessive_col : 1; | 301 | unsigned int exc_col : 1; |
| 311 | unsigned int mdio : 1; | 302 | unsigned int mdio : 1; |
| 312 | unsigned int dummy1 : 18; | 303 | unsigned int dummy1 : 18; |
| 313 | } reg_eth_rw_ack_intr; | 304 | } reg_eth_rw_ack_intr; |
| 314 | #define REG_RD_ADDR_eth_rw_ack_intr 80 | 305 | #define REG_RD_ADDR_eth_rw_ack_intr 80 |
| 315 | #define REG_WR_ADDR_eth_rw_ack_intr 80 | 306 | #define REG_WR_ADDR_eth_rw_ack_intr 80 |
| 316 | 307 | ||
| 317 | /* Register r_intr, scope eth, type r */ | 308 | /* Register r_intr, scope eth, type r */ |
| 318 | typedef struct { | 309 | typedef struct { |
| 319 | unsigned int crc : 1; | 310 | unsigned int crc : 1; |
| 320 | unsigned int align : 1; | 311 | unsigned int align : 1; |
| 321 | unsigned int oversize : 1; | 312 | unsigned int oversize : 1; |
| 322 | unsigned int congestion : 1; | 313 | unsigned int congestion : 1; |
| 323 | unsigned int single_col : 1; | 314 | unsigned int single_col : 1; |
| 324 | unsigned int mult_col : 1; | 315 | unsigned int mult_col : 1; |
| 325 | unsigned int late_col : 1; | 316 | unsigned int late_col : 1; |
| 326 | unsigned int deferred : 1; | 317 | unsigned int deferred : 1; |
| 327 | unsigned int carrier_loss : 1; | 318 | unsigned int carrier_loss : 1; |
| 328 | unsigned int sqe_test_err : 1; | 319 | unsigned int sqe_test_err : 1; |
| 329 | unsigned int orun : 1; | 320 | unsigned int orun : 1; |
| 330 | unsigned int urun : 1; | 321 | unsigned int urun : 1; |
| 331 | unsigned int excessive_col : 1; | 322 | unsigned int exc_col : 1; |
| 332 | unsigned int mdio : 1; | 323 | unsigned int mdio : 1; |
| 333 | unsigned int dummy1 : 18; | 324 | unsigned int dummy1 : 18; |
| 334 | } reg_eth_r_intr; | 325 | } reg_eth_r_intr; |
| 335 | #define REG_RD_ADDR_eth_r_intr 84 | 326 | #define REG_RD_ADDR_eth_r_intr 84 |
| 336 | 327 | ||
| 337 | /* Register r_masked_intr, scope eth, type r */ | 328 | /* Register r_masked_intr, scope eth, type r */ |
| 338 | typedef struct { | 329 | typedef struct { |
| 339 | unsigned int crc : 1; | 330 | unsigned int crc : 1; |
| 340 | unsigned int align : 1; | 331 | unsigned int align : 1; |
| 341 | unsigned int oversize : 1; | 332 | unsigned int oversize : 1; |
| 342 | unsigned int congestion : 1; | 333 | unsigned int congestion : 1; |
| 343 | unsigned int single_col : 1; | 334 | unsigned int single_col : 1; |
| 344 | unsigned int mult_col : 1; | 335 | unsigned int mult_col : 1; |
| 345 | unsigned int late_col : 1; | 336 | unsigned int late_col : 1; |
| 346 | unsigned int deferred : 1; | 337 | unsigned int deferred : 1; |
| 347 | unsigned int carrier_loss : 1; | 338 | unsigned int carrier_loss : 1; |
| 348 | unsigned int sqe_test_err : 1; | 339 | unsigned int sqe_test_err : 1; |
| 349 | unsigned int orun : 1; | 340 | unsigned int orun : 1; |
| 350 | unsigned int urun : 1; | 341 | unsigned int urun : 1; |
| 351 | unsigned int excessive_col : 1; | 342 | unsigned int exc_col : 1; |
| 352 | unsigned int mdio : 1; | 343 | unsigned int mdio : 1; |
| 353 | unsigned int dummy1 : 18; | 344 | unsigned int dummy1 : 18; |
| 354 | } reg_eth_r_masked_intr; | 345 | } reg_eth_r_masked_intr; |
| 355 | #define REG_RD_ADDR_eth_r_masked_intr 88 | 346 | #define REG_RD_ADDR_eth_r_masked_intr 88 |
| 356 | 347 | ||
| @@ -360,12 +351,15 @@ enum { | |||
| 360 | regk_eth_discard = 0x00000000, | 351 | regk_eth_discard = 0x00000000, |
| 361 | regk_eth_ether = 0x00000000, | 352 | regk_eth_ether = 0x00000000, |
| 362 | regk_eth_full = 0x00000001, | 353 | regk_eth_full = 0x00000001, |
| 354 | regk_eth_gmii = 0x00000003, | ||
| 355 | regk_eth_gtxclk = 0x00000001, | ||
| 363 | regk_eth_half = 0x00000000, | 356 | regk_eth_half = 0x00000000, |
| 364 | regk_eth_hsh = 0x00000001, | 357 | regk_eth_hsh = 0x00000001, |
| 365 | regk_eth_mii = 0x00000001, | 358 | regk_eth_mii = 0x00000001, |
| 359 | regk_eth_mii_arec = 0x00000002, | ||
| 366 | regk_eth_mii_clk = 0x00000000, | 360 | regk_eth_mii_clk = 0x00000000, |
| 367 | regk_eth_mii_rec = 0x00000002, | ||
| 368 | regk_eth_no = 0x00000000, | 361 | regk_eth_no = 0x00000000, |
| 362 | regk_eth_phyrst = 0x00000000, | ||
| 369 | regk_eth_rec = 0x00000001, | 363 | regk_eth_rec = 0x00000001, |
| 370 | regk_eth_rw_ga_hi_default = 0x00000000, | 364 | regk_eth_rw_ga_hi_default = 0x00000000, |
| 371 | regk_eth_rw_ga_lo_default = 0x00000000, | 365 | regk_eth_rw_ga_lo_default = 0x00000000, |
| @@ -377,8 +371,8 @@ enum { | |||
| 377 | regk_eth_rw_ma1_lo_default = 0x00000000, | 371 | regk_eth_rw_ma1_lo_default = 0x00000000, |
| 378 | regk_eth_rw_mgm_ctrl_default = 0x00000000, | 372 | regk_eth_rw_mgm_ctrl_default = 0x00000000, |
| 379 | regk_eth_rw_test_ctrl_default = 0x00000000, | 373 | regk_eth_rw_test_ctrl_default = 0x00000000, |
| 380 | regk_eth_size1518 = 0x00000000, | 374 | regk_eth_size1518 = 0x000005ee, |
| 381 | regk_eth_size1522 = 0x00000001, | 375 | regk_eth_size1522 = 0x000005f2, |
| 382 | regk_eth_yes = 0x00000001 | 376 | regk_eth_yes = 0x00000001 |
| 383 | }; | 377 | }; |
| 384 | #endif /* __eth_defs_h */ | 378 | #endif /* __eth_defs_h */ |
diff --git a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h index 44e60233c68f..236f91efe7e8 100644 --- a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h +++ b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h | |||
| @@ -1,15 +1,17 @@ | |||
| 1 | /* $Id: reg_rdwr.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ | 1 | /* |
| 2 | * | ||
| 3 | * Read/write register macros used by *_defs.h | 2 | * Read/write register macros used by *_defs.h |
| 4 | */ | 3 | */ |
| 5 | 4 | ||
| 6 | #ifndef reg_rdwr_h | 5 | #ifndef reg_rdwr_h |
| 7 | #define reg_rdwr_h | 6 | #define reg_rdwr_h |
| 8 | 7 | ||
| 8 | #ifndef REG_READ | ||
| 9 | #define REG_READ(type, addr) (*((volatile type *) (addr))) | ||
| 10 | #endif | ||
| 9 | 11 | ||
| 10 | #define REG_READ(type, addr) *((volatile type *) (addr)) | 12 | #ifndef REG_WRITE |
| 11 | |||
| 12 | #define REG_WRITE(type, addr, val) \ | 13 | #define REG_WRITE(type, addr, val) \ |
| 13 | do { *((volatile type *) (addr)) = (val); } while(0) | 14 | do { *((volatile type *) (addr)) = (val); } while(0) |
| 15 | #endif | ||
| 14 | 16 | ||
| 15 | #endif | 17 | #endif |
diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h index 5efe4d949001..6b38912f29ba 100644 --- a/include/asm-cris/arch-v32/io.h +++ b/include/asm-cris/arch-v32/io.h | |||
| @@ -1,9 +1,10 @@ | |||
| 1 | #ifndef _ASM_ARCH_CRIS_IO_H | 1 | #ifndef _ASM_ARCH_CRIS_IO_H |
| 2 | #define _ASM_ARCH_CRIS_IO_H | 2 | #define _ASM_ARCH_CRIS_IO_H |
| 3 | 3 | ||
| 4 | #include <asm/arch/hwregs/reg_map.h> | 4 | #include <linux/spinlock.h> |
| 5 | #include <asm/arch/hwregs/reg_rdwr.h> | 5 | #include <hwregs/reg_map.h> |
| 6 | #include <asm/arch/hwregs/gio_defs.h> | 6 | #include <hwregs/reg_rdwr.h> |
| 7 | #include <hwregs/gio_defs.h> | ||
| 7 | 8 | ||
| 8 | enum crisv32_io_dir | 9 | enum crisv32_io_dir |
| 9 | { | 10 | { |
| @@ -13,10 +14,11 @@ enum crisv32_io_dir | |||
| 13 | 14 | ||
| 14 | struct crisv32_ioport | 15 | struct crisv32_ioport |
| 15 | { | 16 | { |
| 16 | unsigned long* oe; | 17 | volatile unsigned long *oe; |
| 17 | unsigned long* data; | 18 | volatile unsigned long *data; |
| 18 | unsigned long* data_in; | 19 | volatile unsigned long *data_in; |
| 19 | unsigned int pin_count; | 20 | unsigned int pin_count; |
| 21 | spinlock_t lock; | ||
| 20 | }; | 22 | }; |
| 21 | 23 | ||
| 22 | struct crisv32_iopin | 24 | struct crisv32_iopin |
| @@ -34,22 +36,36 @@ extern struct crisv32_iopin crisv32_led2_red; | |||
| 34 | extern struct crisv32_iopin crisv32_led3_green; | 36 | extern struct crisv32_iopin crisv32_led3_green; |
| 35 | extern struct crisv32_iopin crisv32_led3_red; | 37 | extern struct crisv32_iopin crisv32_led3_red; |
| 36 | 38 | ||
| 37 | static inline void crisv32_io_set(struct crisv32_iopin* iopin, | 39 | extern struct crisv32_iopin crisv32_led_net0_green; |
| 38 | int val) | 40 | extern struct crisv32_iopin crisv32_led_net0_red; |
| 41 | extern struct crisv32_iopin crisv32_led_net1_green; | ||
| 42 | extern struct crisv32_iopin crisv32_led_net1_red; | ||
| 43 | |||
| 44 | static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val) | ||
| 39 | { | 45 | { |
| 46 | long flags; | ||
| 47 | spin_lock_irqsave(&iopin->port->lock, flags); | ||
| 48 | |||
| 40 | if (val) | 49 | if (val) |
| 41 | *iopin->port->data |= iopin->bit; | 50 | *iopin->port->data |= iopin->bit; |
| 42 | else | 51 | else |
| 43 | *iopin->port->data &= ~iopin->bit; | 52 | *iopin->port->data &= ~iopin->bit; |
| 53 | |||
| 54 | spin_unlock_irqrestore(&iopin->port->lock, flags); | ||
| 44 | } | 55 | } |
| 45 | 56 | ||
| 46 | static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, | 57 | static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, |
| 47 | enum crisv32_io_dir dir) | 58 | enum crisv32_io_dir dir) |
| 48 | { | 59 | { |
| 60 | long flags; | ||
| 61 | spin_lock_irqsave(&iopin->port->lock, flags); | ||
| 62 | |||
| 49 | if (dir == crisv32_io_dir_in) | 63 | if (dir == crisv32_io_dir_in) |
| 50 | *iopin->port->oe &= ~iopin->bit; | 64 | *iopin->port->oe &= ~iopin->bit; |
| 51 | else | 65 | else |
| 52 | *iopin->port->oe |= iopin->bit; | 66 | *iopin->port->oe |= iopin->bit; |
| 67 | |||
| 68 | spin_unlock_irqrestore(&iopin->port->lock, flags); | ||
| 53 | } | 69 | } |
| 54 | 70 | ||
| 55 | static inline int crisv32_io_rd(struct crisv32_iopin* iopin) | 71 | static inline int crisv32_io_rd(struct crisv32_iopin* iopin) |
| @@ -60,38 +76,61 @@ static inline int crisv32_io_rd(struct crisv32_iopin* iopin) | |||
| 60 | int crisv32_io_get(struct crisv32_iopin* iopin, | 76 | int crisv32_io_get(struct crisv32_iopin* iopin, |
| 61 | unsigned int port, unsigned int pin); | 77 | unsigned int port, unsigned int pin); |
| 62 | int crisv32_io_get_name(struct crisv32_iopin* iopin, | 78 | int crisv32_io_get_name(struct crisv32_iopin* iopin, |
| 63 | char* name); | 79 | const char *name); |
| 64 | 80 | ||
| 65 | #define LED_OFF 0x00 | 81 | #define CRIS_LED_OFF 0x00 |
| 66 | #define LED_GREEN 0x01 | 82 | #define CRIS_LED_GREEN 0x01 |
| 67 | #define LED_RED 0x02 | 83 | #define CRIS_LED_RED 0x02 |
| 68 | #define LED_ORANGE (LED_GREEN | LED_RED) | 84 | #define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) |
| 69 | 85 | ||
| 70 | #define LED_NETWORK_SET(x) \ | 86 | #if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)) |
| 71 | do { \ | 87 | #define CRIS_LED_NETWORK_GRP0_SET(x) \ |
| 72 | LED_NETWORK_SET_G((x) & LED_GREEN); \ | 88 | do { \ |
| 73 | LED_NETWORK_SET_R((x) & LED_RED); \ | 89 | CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \ |
| 90 | CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \ | ||
| 74 | } while (0) | 91 | } while (0) |
| 75 | #define LED_ACTIVE_SET(x) \ | 92 | #else |
| 93 | #define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {} | ||
| 94 | #endif | ||
| 95 | |||
| 96 | #define CRIS_LED_NETWORK_GRP0_SET_G(x) \ | ||
| 97 | crisv32_io_set(&crisv32_led_net0_green, !(x)); | ||
| 98 | |||
| 99 | #define CRIS_LED_NETWORK_GRP0_SET_R(x) \ | ||
| 100 | crisv32_io_set(&crisv32_led_net0_red, !(x)); | ||
| 101 | |||
| 102 | #if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO) | ||
| 103 | #define CRIS_LED_NETWORK_GRP1_SET(x) \ | ||
| 104 | do { \ | ||
| 105 | CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \ | ||
| 106 | CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \ | ||
| 107 | } while (0) | ||
| 108 | #else | ||
| 109 | #define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {} | ||
| 110 | #endif | ||
| 111 | |||
| 112 | #define CRIS_LED_NETWORK_GRP1_SET_G(x) \ | ||
| 113 | crisv32_io_set(&crisv32_led_net1_green, !(x)); | ||
| 114 | |||
| 115 | #define CRIS_LED_NETWORK_GRP1_SET_R(x) \ | ||
| 116 | crisv32_io_set(&crisv32_led_net1_red, !(x)); | ||
| 117 | |||
| 118 | #define CRIS_LED_ACTIVE_SET(x) \ | ||
| 76 | do { \ | 119 | do { \ |
| 77 | LED_ACTIVE_SET_G((x) & LED_GREEN); \ | 120 | CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ |
| 78 | LED_ACTIVE_SET_R((x) & LED_RED); \ | 121 | CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ |
| 79 | } while (0) | 122 | } while (0) |
| 80 | 123 | ||
| 81 | #define LED_NETWORK_SET_G(x) \ | 124 | #define CRIS_LED_ACTIVE_SET_G(x) \ |
| 82 | crisv32_io_set(&crisv32_led1_green, !(x)); | ||
| 83 | #define LED_NETWORK_SET_R(x) \ | ||
| 84 | crisv32_io_set(&crisv32_led1_red, !(x)); | ||
| 85 | #define LED_ACTIVE_SET_G(x) \ | ||
| 86 | crisv32_io_set(&crisv32_led2_green, !(x)); | 125 | crisv32_io_set(&crisv32_led2_green, !(x)); |
| 87 | #define LED_ACTIVE_SET_R(x) \ | 126 | #define CRIS_LED_ACTIVE_SET_R(x) \ |
| 88 | crisv32_io_set(&crisv32_led2_red, !(x)); | 127 | crisv32_io_set(&crisv32_led2_red, !(x)); |
| 89 | #define LED_DISK_WRITE(x) \ | 128 | #define CRIS_LED_DISK_WRITE(x) \ |
| 90 | do{\ | 129 | do{\ |
| 91 | crisv32_io_set(&crisv32_led3_green, !(x)); \ | 130 | crisv32_io_set(&crisv32_led3_green, !(x)); \ |
| 92 | crisv32_io_set(&crisv32_led3_red, !(x)); \ | 131 | crisv32_io_set(&crisv32_led3_red, !(x)); \ |
| 93 | }while(0) | 132 | }while(0) |
| 94 | #define LED_DISK_READ(x) \ | 133 | #define CRIS_LED_DISK_READ(x) \ |
| 95 | crisv32_io_set(&crisv32_led3_green, !(x)); | 134 | crisv32_io_set(&crisv32_led3_green, !(x)); |
| 96 | 135 | ||
| 97 | #endif | 136 | #endif |
diff --git a/include/asm-cris/arch-v32/irq.h b/include/asm-cris/arch-v32/irq.h index bac94ee6bc90..9e4c9fbdfddf 100644 --- a/include/asm-cris/arch-v32/irq.h +++ b/include/asm-cris/arch-v32/irq.h | |||
| @@ -1,12 +1,17 @@ | |||
| 1 | #ifndef _ASM_ARCH_IRQ_H | 1 | #ifndef _ASM_ARCH_IRQ_H |
| 2 | #define _ASM_ARCH_IRQ_H | 2 | #define _ASM_ARCH_IRQ_H |
| 3 | 3 | ||
| 4 | #include "hwregs/intr_vect.h" | 4 | #include <hwregs/intr_vect.h> |
| 5 | 5 | ||
| 6 | /* Number of non-cpu interrupts. */ | 6 | /* Number of non-cpu interrupts. */ |
| 7 | #define NR_IRQS 0x50 /* Exceptions + IRQs */ | 7 | #define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */ |
| 8 | #define NR_REAL_IRQS 0x20 /* IRQs */ | ||
| 9 | #define FIRST_IRQ 0x31 /* Exception number for first IRQ */ | 8 | #define FIRST_IRQ 0x31 /* Exception number for first IRQ */ |
| 9 | #define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */ | ||
| 10 | #if NR_REAL_IRQS > 32 | ||
| 11 | #define MACH_IRQS 64 | ||
| 12 | #else | ||
| 13 | #define MACH_IRQS 32 | ||
| 14 | #endif | ||
| 10 | 15 | ||
| 11 | #ifndef __ASSEMBLY__ | 16 | #ifndef __ASSEMBLY__ |
| 12 | /* Global IRQ vector. */ | 17 | /* Global IRQ vector. */ |
| @@ -73,7 +78,7 @@ void set_exception_vector(int n, irqvectptr addr); | |||
| 73 | * which will acknowledge the interrupt, is run. The actual blocking is made | 78 | * which will acknowledge the interrupt, is run. The actual blocking is made |
| 74 | * by crisv32_do_IRQ. | 79 | * by crisv32_do_IRQ. |
| 75 | */ | 80 | */ |
| 76 | #define BUILD_IRQ(nr, mask) \ | 81 | #define BUILD_IRQ(nr) \ |
| 77 | void IRQ_NAME(nr); \ | 82 | void IRQ_NAME(nr); \ |
| 78 | __asm__ ( \ | 83 | __asm__ ( \ |
| 79 | ".text\n\t" \ | 84 | ".text\n\t" \ |
| @@ -81,7 +86,7 @@ __asm__ ( \ | |||
| 81 | SAVE_ALL \ | 86 | SAVE_ALL \ |
| 82 | KGDB_FIXUP \ | 87 | KGDB_FIXUP \ |
| 83 | "move.d "#nr",$r10\n\t" \ | 88 | "move.d "#nr",$r10\n\t" \ |
| 84 | "move.d $sp,$r12\n\t" \ | 89 | "move.d $sp, $r12\n\t" \ |
| 85 | "jsr crisv32_do_IRQ\n\t" \ | 90 | "jsr crisv32_do_IRQ\n\t" \ |
| 86 | "moveq 1, $r11\n\t" \ | 91 | "moveq 1, $r11\n\t" \ |
| 87 | "jump ret_from_intr\n\t" \ | 92 | "jump ret_from_intr\n\t" \ |
diff --git a/include/asm-cris/arch-v32/juliette.h b/include/asm-cris/arch-v32/juliette.h deleted file mode 100644 index f1f81725e57b..000000000000 --- a/include/asm-cris/arch-v32/juliette.h +++ /dev/null | |||
| @@ -1,326 +0,0 @@ | |||
| 1 | #ifndef _ASM_JULIETTE_H | ||
| 2 | #define _ASM_JULIETTE_H | ||
| 3 | |||
| 4 | /* juliette _IOC_TYPE, bits 8 to 15 in ioctl cmd */ | ||
| 5 | |||
| 6 | #define JULIOCTYPE 42 | ||
| 7 | |||
| 8 | /* supported ioctl _IOC_NR's */ | ||
| 9 | |||
| 10 | #define JULSTARTDMA 0x1 /* start a picture asynchronously */ | ||
| 11 | |||
| 12 | /* set parameters */ | ||
| 13 | |||
| 14 | #define SETDEFAULT 0x2 /* CCD/VIDEO/SS1M */ | ||
| 15 | #define SETPARAMETERS 0x3 /* CCD/VIDEO */ | ||
| 16 | #define SETSIZE 0x4 /* CCD/VIDEO/SS1M */ | ||
| 17 | #define SETCOMPRESSION 0x5 /* CCD/VIDEO/SS1M */ | ||
| 18 | #define SETCOLORLEVEL 0x6 /* CCD/VIDEO */ | ||
| 19 | #define SETBRIGHTNESS 0x7 /* CCD */ | ||
| 20 | #define SETROTATION 0x8 /* CCD */ | ||
| 21 | #define SETTEXT 0x9 /* CCD/VIDEO/SS1M */ | ||
| 22 | #define SETCLOCK 0xa /* CCD/VIDEO/SS1M */ | ||
| 23 | #define SETDATE 0xb /* CCD/VIDEO/SS1M */ | ||
| 24 | #define SETTIMEFORMAT 0xc /* CCD/VIDEO/SS1M */ | ||
| 25 | #define SETDATEFORMAT 0xd /* VIDEO */ | ||
| 26 | #define SETTEXTALIGNMENT 0xe /* VIDEO */ | ||
| 27 | #define SETFPS 0xf /* CCD/VIDEO/SS1M */ | ||
| 28 | #define SETVGA 0xff /* VIDEO */ | ||
| 29 | #define SETCOMMENT 0xfe /* CCD/VIDEO */ | ||
| 30 | |||
| 31 | /* get parameters */ | ||
| 32 | |||
| 33 | #define GETDRIVERTYPE 0x10 /* CCD/VIDEO/SS1M */ | ||
| 34 | #define GETNBROFCAMERAS 0x11 /* CCD/VIDEO/SS1M */ | ||
| 35 | #define GETPARAMETERS 0x12 /* CCD/VIDEO/SS1M */ | ||
| 36 | #define GETBUFFERSIZE 0x13 /* CCD/VIDEO/SS1M */ | ||
| 37 | #define GETVIDEOTYPE 0x14 /* VIDEO/SS1M */ | ||
| 38 | #define GETVIDEOSIGNAL 0x15 /* VIDEO */ | ||
| 39 | #define GETMODULATION 0x16 /* VIDEO */ | ||
| 40 | #define GETDCYVALUES 0xa0 /* CCD /SS1M */ | ||
| 41 | #define GETDCYWIDTH 0xa1 /* CCD /SS1M */ | ||
| 42 | #define GETDCYHEIGHT 0xa2 /* CCD /SS1M */ | ||
| 43 | #define GETSIZE 0xa3 /* CCD/VIDEO */ | ||
| 44 | #define GETCOMPRESSION 0xa4 /* CCD/VIDEO */ | ||
| 45 | |||
| 46 | /* detect and get parameters */ | ||
| 47 | |||
| 48 | #define DETECTMODULATION 0x17 /* VIDEO */ | ||
| 49 | #define DETECTVIDEOTYPE 0x18 /* VIDEO */ | ||
| 50 | #define DETECTVIDEOSIGNAL 0x19 /* VIDEO */ | ||
| 51 | |||
| 52 | /* configure default parameters */ | ||
| 53 | |||
| 54 | #define CONFIGUREDEFAULT 0x20 /* CCD/VIDEO/SS1M */ | ||
| 55 | #define DEFSIZE 0x21 /* CCD/VIDEO/SS1M */ | ||
| 56 | #define DEFCOMPRESSION 0x22 /* CCD/VIDEO/SS1M */ | ||
| 57 | #define DEFCOLORLEVEL 0x23 /* CCD/VIDEO */ | ||
| 58 | #define DEFBRIGHTNESS 0x24 /* CCD */ | ||
| 59 | #define DEFROTATION 0x25 /* CCD */ | ||
| 60 | #define DEFWHITEBALANCE 0x26 /* CCD */ | ||
| 61 | #define DEFEXPOSURE 0x27 /* CCD */ | ||
| 62 | #define DEFAUTOEXPWINDOW 0x28 /* CCD */ | ||
| 63 | #define DEFTEXT 0x29 /* CCD/VIDEO/SS1M */ | ||
| 64 | #define DEFCLOCK 0x2a /* CCD/VIDEO/SS1M */ | ||
| 65 | #define DEFDATE 0x2b /* CCD/VIDEO/SS1M */ | ||
| 66 | #define DEFTIMEFORMAT 0x2c /* CCD/VIDEO/SS1M */ | ||
| 67 | #define DEFDATEFORMAT 0x2d /* VIDEO */ | ||
| 68 | #define DEFTEXTALIGNMENT 0x2e /* VIDEO */ | ||
| 69 | #define DEFFPS 0x2f /* CCD/VIDEO/SS1M */ | ||
| 70 | #define DEFTEXTSTRING 0x30 /* CCD/VIDEO/SS1M */ | ||
| 71 | #define DEFHEADERINFO 0x31 /* CCD/VIDEO/SS1M */ | ||
| 72 | #define DEFWEXAR 0x32 /* CCD */ | ||
| 73 | #define DEFLINEDELAY 0x33 /* CCD */ | ||
| 74 | #define DEFDISABLEDVIDEO 0x34 /* VIDEO */ | ||
| 75 | #define DEFVIDEOTYPE 0x35 /* VIDEO */ | ||
| 76 | #define DEFMODULATION 0x36 /* VIDEO */ | ||
| 77 | #define DEFXOFFSET 0x37 /* VIDEO */ | ||
| 78 | #define DEFYOFFSET 0x38 /* VIDEO */ | ||
| 79 | #define DEFYCMODE 0x39 /* VIDEO */ | ||
| 80 | #define DEFVCRMODE 0x3a /* VIDEO */ | ||
| 81 | #define DEFSTOREDCYVALUES 0x3b /* CCD/VIDEO/SS1M */ | ||
| 82 | #define DEFWCDS 0x3c /* CCD */ | ||
| 83 | #define DEFVGA 0x3d /* VIDEO */ | ||
| 84 | #define DEFCOMMENT 0x3e /* CCD/VIDEO */ | ||
| 85 | #define DEFCOMMENTSIZE 0x3f /* CCD/VIDEO */ | ||
| 86 | #define DEFCOMMENTTEXT 0x50 /* CCD/VIDEO */ | ||
| 87 | #define DEFSTOREDCYTEXT 0x51 /* VIDEO */ | ||
| 88 | |||
| 89 | |||
| 90 | #define JULABORTDMA 0x70 /* Abort current DMA transfer */ | ||
| 91 | |||
| 92 | /* juliette general i/o port */ | ||
| 93 | |||
| 94 | #define JIO_READBITS 0x40 /* read and return current port bits */ | ||
| 95 | #define JIO_SETBITS 0x41 /* set bits marked by 1 in the argument */ | ||
| 96 | #define JIO_CLRBITS 0x42 /* clr bits marked by 1 in the argument */ | ||
| 97 | #define JIO_READDIR 0x43 /* read direction, 0=input 1=output */ | ||
| 98 | #define JIO_SETINPUT 0x44 /* set direction, 0=unchanged 1=input | ||
| 99 | returns current dir */ | ||
| 100 | #define JIO_SETOUTPUT 0x45 /* set direction, 0=unchanged 1=output | ||
| 101 | returns current dir */ | ||
| 102 | |||
| 103 | /**** YumYum internal adresses ****/ | ||
| 104 | |||
| 105 | /* Juliette buffer addresses */ | ||
| 106 | |||
| 107 | #define BUFFER1_VIDEO 0x1100 | ||
| 108 | #define BUFFER2_VIDEO 0x2800 | ||
| 109 | #define ACDC_BUFF_VIDEO 0x0aaa | ||
| 110 | #define BUFFER1 0x1700 | ||
| 111 | #define BUFFER2 0x2b01 | ||
| 112 | #define ACDC_BUFFER 0x1200 | ||
| 113 | #define BUFFER1_SS1M 0x1100 | ||
| 114 | #define BUFFER2_SS1M 0x2800 | ||
| 115 | #define ACDC_BUFF_SS1M 0x0900 | ||
| 116 | |||
| 117 | /* Juliette parameter memory addresses */ | ||
| 118 | |||
| 119 | #define PA_BUFFER_CNT 0x3f09 /* CCD/VIDEO */ | ||
| 120 | #define PA_CCD_BUFFER 0x3f10 /* CCD */ | ||
| 121 | #define PA_VIDEO_BUFFER 0x3f10 /* VIDEO */ | ||
| 122 | #define PA_DCT_BUFFER 0x3f11 /* CCD/VIDEO */ | ||
| 123 | #define PA_TEMP 0x3f12 /* CCD/VIDEO */ | ||
| 124 | #define PA_VIDEOLINE_RD 0x3f13 /* VIDEO */ | ||
| 125 | #define PA_VIDEOLINE_WR 0x3f14 /* VIDEO */ | ||
| 126 | #define PA_VI_HDELAY0 0x3f15 /* VIDEO */ | ||
| 127 | #define PA_VI_VDELAY0 0x3f16 /* VIDEO */ | ||
| 128 | #define PA_VI_HDELAY1 0x3f17 /* VIDEO */ | ||
| 129 | #define PA_VI_VDELAY1 0x3f18 /* VIDEO */ | ||
| 130 | #define PA_VI_HDELAY2 0x3f19 /* VIDEO */ | ||
| 131 | #define PA_VI_VDELAY2 0x3f1a /* VIDEO */ | ||
| 132 | #define PA_VI_HDELAY3 0x3f1b /* VIDEO */ | ||
| 133 | #define PA_VI_VDELAY3 0x3f1c /* VIDEO */ | ||
| 134 | #define PA_VI_CTRL 0x3f20 /* VIDEO */ | ||
| 135 | #define PA_JPEG_CTRL 0x3f22 /* CCD/VIDEO */ | ||
| 136 | #define PA_BUFFER_SIZE 0x3f24 /* CCD/VIDEO */ | ||
| 137 | #define PA_PAL_NTSC 0x3f25 /* VIDEO */ | ||
| 138 | #define PA_MACROBLOCKS 0x3f26 /* CCD/VIDEO */ | ||
| 139 | #define PA_COLOR 0x3f27 /* VIDEO */ | ||
| 140 | #define PA_MEMCH1CNT2 0x3f28 /* CCD/VIDEO */ | ||
| 141 | #define PA_MEMCH1CNT3 0x3f29 /* VIDEO */ | ||
| 142 | #define PA_MEMCH1STR2 0x3f2a /* CCD/VIDEO */ | ||
| 143 | #define PA_MEMCH1STR3 0x3f2b /* VIDEO */ | ||
| 144 | #define PA_BUFFERS 0x3f2c /* CCD/VIDEO */ | ||
| 145 | #define PA_PROGRAM 0x3f2d /* CCD/VIDEO */ | ||
| 146 | #define PA_ROTATION 0x3f2e /* CCD */ | ||
| 147 | #define PA_PC 0x3f30 /* CCD/VIDEO */ | ||
| 148 | #define PA_PC2 0x3f31 /* VIDEO */ | ||
| 149 | #define PA_ODD_LINE 0x3f32 /* VIDEO */ | ||
| 150 | #define PA_EXP_DELAY 0x3f34 /* CCD */ | ||
| 151 | #define PA_MACROBLOCK_CNT 0x3f35 /* CCD/VIDEO */ | ||
| 152 | #define PA_DRAM_PTR1_L 0x3f36 /* CCD/VIDEO */ | ||
| 153 | #define PA_CLPOB_CNT 0x3f37 /* CCD */ | ||
| 154 | #define PA_DRAM_PTR1_H 0x3f38 /* CCD/VIDEO */ | ||
| 155 | #define PA_DRAM_PTR2_L 0x3f3a /* VIDEO */ | ||
| 156 | #define PA_DRAM_PTR2_H 0x3f3c /* VIDEO */ | ||
| 157 | #define PA_CCD_LINE_CNT 0x3f3f /* CCD */ | ||
| 158 | #define PA_VIDEO_LINE_CNT 0x3f3f /* VIDEO */ | ||
| 159 | #define PA_TEXT 0x3f41 /* CCD/VIDEO */ | ||
| 160 | #define PA_CAMERA_CHANGED 0x3f42 /* VIDEO */ | ||
| 161 | #define PA_TEXTALIGNMENT 0x3f43 /* VIDEO */ | ||
| 162 | #define PA_DISABLED 0x3f44 /* VIDEO */ | ||
| 163 | #define PA_MACROBLOCKTEXT 0x3f45 /* VIDEO */ | ||
| 164 | #define PA_VGA 0x3f46 /* VIDEO */ | ||
| 165 | #define PA_ZERO 0x3ffe /* VIDEO */ | ||
| 166 | #define PA_NULL 0x3fff /* CCD/VIDEO */ | ||
| 167 | |||
| 168 | typedef enum { | ||
| 169 | jpeg = 0, | ||
| 170 | dummy = 1 | ||
| 171 | } request_type; | ||
| 172 | |||
| 173 | typedef enum { | ||
| 174 | hugesize = 0, | ||
| 175 | fullsize = 1, | ||
| 176 | halfsize = 2, | ||
| 177 | fieldsize = 3 | ||
| 178 | } size_type; | ||
| 179 | |||
| 180 | typedef enum { | ||
| 181 | min = 0, | ||
| 182 | low = 1, | ||
| 183 | medium = 2, | ||
| 184 | high = 3, | ||
| 185 | very_high = 4, | ||
| 186 | very_low = 5, | ||
| 187 | q1 = 6, | ||
| 188 | q2 = 7, | ||
| 189 | q3 = 8, | ||
| 190 | q4 = 9, | ||
| 191 | q5 = 10, | ||
| 192 | q6 = 11 | ||
| 193 | } compr_type; | ||
| 194 | |||
| 195 | typedef enum { | ||
| 196 | deg_0 = 0, | ||
| 197 | deg_180 = 1, | ||
| 198 | deg_90 = 2, | ||
| 199 | deg_270 = 3 | ||
| 200 | } rotation_type; | ||
| 201 | |||
| 202 | typedef enum { | ||
| 203 | auto_white = 0, | ||
| 204 | hold = 1, | ||
| 205 | fixed_outdoor = 2, | ||
| 206 | fixed_indoor = 3, | ||
| 207 | fixed_fluor = 4 | ||
| 208 | } white_balance_type; | ||
| 209 | |||
| 210 | typedef enum { | ||
| 211 | auto_exp = 0, | ||
| 212 | fixed_exp = 1 | ||
| 213 | } exposure_type; | ||
| 214 | |||
| 215 | typedef enum { | ||
| 216 | no_window = 0, | ||
| 217 | center = 1, | ||
| 218 | top = 2, | ||
| 219 | lower = 3, | ||
| 220 | left = 4, | ||
| 221 | right = 5, | ||
| 222 | spot = 6, | ||
| 223 | cw = 7 | ||
| 224 | } exp_window_type; | ||
| 225 | |||
| 226 | typedef enum { | ||
| 227 | h_24 = 0, | ||
| 228 | h_12 = 1, | ||
| 229 | h_24P = 2 | ||
| 230 | } hour_type; | ||
| 231 | |||
| 232 | typedef enum { | ||
| 233 | standard = 0, | ||
| 234 | YYYY_MM_DD = 1, | ||
| 235 | Www_Mmm_DD_YYYY = 2, | ||
| 236 | Www_DD_MM_YYYY = 3 | ||
| 237 | } date_type; | ||
| 238 | |||
| 239 | typedef enum { | ||
| 240 | left_align = 0, | ||
| 241 | center_align = 1, | ||
| 242 | right_align = 2 | ||
| 243 | } alignment_type; | ||
| 244 | |||
| 245 | typedef enum { | ||
| 246 | off = 0, | ||
| 247 | on = 1, | ||
| 248 | no = 0, | ||
| 249 | yes = 1 | ||
| 250 | } enable_type; | ||
| 251 | |||
| 252 | typedef enum { | ||
| 253 | disabled = 0, | ||
| 254 | enabled = 1, | ||
| 255 | extended = 2 | ||
| 256 | } comment_type; | ||
| 257 | |||
| 258 | typedef enum { | ||
| 259 | pal = 0, | ||
| 260 | ntsc = 1 | ||
| 261 | } video_type; | ||
| 262 | |||
| 263 | typedef enum { | ||
| 264 | pal_bghi_ntsc_m = 0, | ||
| 265 | ntsc_4_43_50hz_pal_4_43_60hz = 1, | ||
| 266 | pal_n_ntsc_4_43_60hz = 2, | ||
| 267 | ntsc_n_pal_m = 3, | ||
| 268 | secam_pal_4_43_60hz = 4 | ||
| 269 | } modulation_type; | ||
| 270 | |||
| 271 | typedef enum { | ||
| 272 | cam0 = 0, | ||
| 273 | cam1 = 1, | ||
| 274 | cam2 = 2, | ||
| 275 | cam3 = 3, | ||
| 276 | quad = 32 | ||
| 277 | } camera_type; | ||
| 278 | |||
| 279 | typedef enum { | ||
| 280 | video_driver = 0, | ||
| 281 | ccd_driver = 1 | ||
| 282 | } driver_type; | ||
| 283 | |||
| 284 | struct jul_param { | ||
| 285 | request_type req_type; | ||
| 286 | size_type size; | ||
| 287 | compr_type compression; | ||
| 288 | rotation_type rotation; | ||
| 289 | int color_level; | ||
| 290 | int brightness; | ||
| 291 | white_balance_type white_balance; | ||
| 292 | exposure_type exposure; | ||
| 293 | exp_window_type auto_exp_window; | ||
| 294 | hour_type time_format; | ||
| 295 | date_type date_format; | ||
| 296 | alignment_type text_alignment; | ||
| 297 | enable_type text; | ||
| 298 | enable_type clock; | ||
| 299 | enable_type date; | ||
| 300 | enable_type fps; | ||
| 301 | enable_type vga; | ||
| 302 | enable_type comment; | ||
| 303 | }; | ||
| 304 | |||
| 305 | struct video_param { | ||
| 306 | enable_type disabled; | ||
| 307 | modulation_type modulation; | ||
| 308 | video_type video; | ||
| 309 | enable_type signal; | ||
| 310 | enable_type vcr; | ||
| 311 | int xoffset; | ||
| 312 | int yoffset; | ||
| 313 | }; | ||
| 314 | |||
| 315 | /* The juliette_request structure is used during the JULSTARTDMA asynchronous | ||
| 316 | * picture-taking ioctl call as an argument to specify a buffer which will get | ||
| 317 | * the final picture. | ||
| 318 | */ | ||
| 319 | |||
| 320 | struct juliette_request { | ||
| 321 | char *buf; /* Pointer to the buffer to hold picture data */ | ||
| 322 | unsigned int buflen; /* Length of the above buffer */ | ||
| 323 | unsigned int size; /* Resulting length, 0 if the picture is not ready */ | ||
| 324 | }; | ||
| 325 | |||
| 326 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/arbiter.h b/include/asm-cris/arch-v32/mach-a3/arbiter.h new file mode 100644 index 000000000000..65e9d6ff0520 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/arbiter.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_ARBITER_H | ||
| 2 | #define _ASM_CRIS_ARCH_ARBITER_H | ||
| 3 | |||
| 4 | #define EXT_REGION 0 | ||
| 5 | #define INT_REGION 1 | ||
| 6 | |||
| 7 | typedef void (watch_callback)(void); | ||
| 8 | |||
| 9 | enum { | ||
| 10 | arbiter_all_dmas = 0x7fe, | ||
| 11 | arbiter_cpu = 0x1800, | ||
| 12 | arbiter_all_clients = 0x7fff | ||
| 13 | }; | ||
| 14 | |||
| 15 | enum { | ||
| 16 | arbiter_bar_all_clients = 0x1ff | ||
| 17 | }; | ||
| 18 | |||
| 19 | enum { | ||
| 20 | arbiter_all_read = 0x55, | ||
| 21 | arbiter_all_write = 0xaa, | ||
| 22 | arbiter_all_accesses = 0xff | ||
| 23 | }; | ||
| 24 | |||
| 25 | #define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli)) | ||
| 26 | |||
| 27 | int crisv32_arbiter_allocate_bandwidth(int client, int region, | ||
| 28 | unsigned long bandwidth); | ||
| 29 | int crisv32_arbiter_watch(unsigned long start, unsigned long size, | ||
| 30 | unsigned long clients, unsigned long accesses, | ||
| 31 | watch_callback * cb); | ||
| 32 | int crisv32_arbiter_unwatch(int id); | ||
| 33 | |||
| 34 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/dma.h b/include/asm-cris/arch-v32/mach-a3/dma.h new file mode 100644 index 000000000000..9e8eb13b601d --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/dma.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | #ifndef _ASM_ARCH_CRIS_DMA_H | ||
| 2 | #define _ASM_ARCH_CRIS_DMA_H | ||
| 3 | |||
| 4 | /* Defines for using and allocating dma channels. */ | ||
| 5 | |||
| 6 | #define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */ | ||
| 7 | |||
| 8 | enum dma_owner { | ||
| 9 | dma_eth, | ||
| 10 | dma_ser0, | ||
| 11 | dma_ser1, | ||
| 12 | dma_ser2, | ||
| 13 | dma_ser3, | ||
| 14 | dma_ser4, | ||
| 15 | dma_iop, | ||
| 16 | dma_sser, | ||
| 17 | dma_strp, | ||
| 18 | dma_h264, | ||
| 19 | dma_jpeg | ||
| 20 | }; | ||
| 21 | |||
| 22 | int crisv32_request_dma(unsigned int dmanr, const char *device_id, | ||
| 23 | unsigned options, unsigned bandwidth, enum dma_owner owner); | ||
| 24 | void crisv32_free_dma(unsigned int dmanr); | ||
| 25 | |||
| 26 | /* Masks used by crisv32_request_dma options: */ | ||
| 27 | #define DMA_VERBOSE_ON_ERROR 1 | ||
| 28 | #define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) | ||
| 29 | #define DMA_INT_MEM 4 | ||
| 30 | |||
| 31 | #endif /* _ASM_ARCH_CRIS_DMA_H */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h new file mode 100644 index 000000000000..02855adf63e8 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h | |||
| @@ -0,0 +1,164 @@ | |||
| 1 | #ifndef __clkgen_defs_asm_h | ||
| 2 | #define __clkgen_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: clkgen.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register r_bootsel, scope clkgen, type r */ | ||
| 54 | #define reg_clkgen_r_bootsel___boot_mode___lsb 0 | ||
| 55 | #define reg_clkgen_r_bootsel___boot_mode___width 5 | ||
| 56 | #define reg_clkgen_r_bootsel___intern_main_clk___lsb 5 | ||
| 57 | #define reg_clkgen_r_bootsel___intern_main_clk___width 1 | ||
| 58 | #define reg_clkgen_r_bootsel___intern_main_clk___bit 5 | ||
| 59 | #define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6 | ||
| 60 | #define reg_clkgen_r_bootsel___extern_usb2_clk___width 1 | ||
| 61 | #define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6 | ||
| 62 | #define reg_clkgen_r_bootsel_offset 0 | ||
| 63 | |||
| 64 | /* Register rw_clk_ctrl, scope clkgen, type rw */ | ||
| 65 | #define reg_clkgen_rw_clk_ctrl___pll___lsb 0 | ||
| 66 | #define reg_clkgen_rw_clk_ctrl___pll___width 1 | ||
| 67 | #define reg_clkgen_rw_clk_ctrl___pll___bit 0 | ||
| 68 | #define reg_clkgen_rw_clk_ctrl___cpu___lsb 1 | ||
| 69 | #define reg_clkgen_rw_clk_ctrl___cpu___width 1 | ||
| 70 | #define reg_clkgen_rw_clk_ctrl___cpu___bit 1 | ||
| 71 | #define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2 | ||
| 72 | #define reg_clkgen_rw_clk_ctrl___iop_usb___width 1 | ||
| 73 | #define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2 | ||
| 74 | #define reg_clkgen_rw_clk_ctrl___vin___lsb 3 | ||
| 75 | #define reg_clkgen_rw_clk_ctrl___vin___width 1 | ||
| 76 | #define reg_clkgen_rw_clk_ctrl___vin___bit 3 | ||
| 77 | #define reg_clkgen_rw_clk_ctrl___sclr___lsb 4 | ||
| 78 | #define reg_clkgen_rw_clk_ctrl___sclr___width 1 | ||
| 79 | #define reg_clkgen_rw_clk_ctrl___sclr___bit 4 | ||
| 80 | #define reg_clkgen_rw_clk_ctrl___h264___lsb 5 | ||
| 81 | #define reg_clkgen_rw_clk_ctrl___h264___width 1 | ||
| 82 | #define reg_clkgen_rw_clk_ctrl___h264___bit 5 | ||
| 83 | #define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6 | ||
| 84 | #define reg_clkgen_rw_clk_ctrl___ddr2___width 1 | ||
| 85 | #define reg_clkgen_rw_clk_ctrl___ddr2___bit 6 | ||
| 86 | #define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7 | ||
| 87 | #define reg_clkgen_rw_clk_ctrl___vout_hist___width 1 | ||
| 88 | #define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7 | ||
| 89 | #define reg_clkgen_rw_clk_ctrl___eth___lsb 8 | ||
| 90 | #define reg_clkgen_rw_clk_ctrl___eth___width 1 | ||
| 91 | #define reg_clkgen_rw_clk_ctrl___eth___bit 8 | ||
| 92 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9 | ||
| 93 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1 | ||
| 94 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9 | ||
| 95 | #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10 | ||
| 96 | #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1 | ||
| 97 | #define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10 | ||
| 98 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11 | ||
| 99 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1 | ||
| 100 | #define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11 | ||
| 101 | #define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12 | ||
| 102 | #define reg_clkgen_rw_clk_ctrl___jpeg___width 1 | ||
| 103 | #define reg_clkgen_rw_clk_ctrl___jpeg___bit 12 | ||
| 104 | #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13 | ||
| 105 | #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1 | ||
| 106 | #define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13 | ||
| 107 | #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14 | ||
| 108 | #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1 | ||
| 109 | #define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14 | ||
| 110 | #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15 | ||
| 111 | #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1 | ||
| 112 | #define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15 | ||
| 113 | #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16 | ||
| 114 | #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1 | ||
| 115 | #define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16 | ||
| 116 | #define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17 | ||
| 117 | #define reg_clkgen_rw_clk_ctrl___dma9_11___width 1 | ||
| 118 | #define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17 | ||
| 119 | #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18 | ||
| 120 | #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1 | ||
| 121 | #define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18 | ||
| 122 | #define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19 | ||
| 123 | #define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1 | ||
| 124 | #define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19 | ||
| 125 | #define reg_clkgen_rw_clk_ctrl_offset 4 | ||
| 126 | |||
| 127 | |||
| 128 | /* Constants */ | ||
| 129 | #define regk_clkgen_eth1000_rx 0x0000000c | ||
| 130 | #define regk_clkgen_eth1000_tx 0x0000000e | ||
| 131 | #define regk_clkgen_eth100_rx 0x0000001d | ||
| 132 | #define regk_clkgen_eth100_rx_half 0x0000001c | ||
| 133 | #define regk_clkgen_eth100_tx 0x0000001f | ||
| 134 | #define regk_clkgen_eth100_tx_half 0x0000001e | ||
| 135 | #define regk_clkgen_nand_3_2 0x00000000 | ||
| 136 | #define regk_clkgen_nand_3_2_0x30 0x00000002 | ||
| 137 | #define regk_clkgen_nand_3_2_0x30_pll 0x00000012 | ||
| 138 | #define regk_clkgen_nand_3_2_pll 0x00000010 | ||
| 139 | #define regk_clkgen_nand_3_3 0x00000001 | ||
| 140 | #define regk_clkgen_nand_3_3_0x30 0x00000003 | ||
| 141 | #define regk_clkgen_nand_3_3_0x30_pll 0x00000013 | ||
| 142 | #define regk_clkgen_nand_3_3_pll 0x00000011 | ||
| 143 | #define regk_clkgen_nand_4_2 0x00000004 | ||
| 144 | #define regk_clkgen_nand_4_2_0x30 0x00000006 | ||
| 145 | #define regk_clkgen_nand_4_2_0x30_pll 0x00000016 | ||
| 146 | #define regk_clkgen_nand_4_2_pll 0x00000014 | ||
| 147 | #define regk_clkgen_nand_4_3 0x00000005 | ||
| 148 | #define regk_clkgen_nand_4_3_0x30 0x00000007 | ||
| 149 | #define regk_clkgen_nand_4_3_0x30_pll 0x00000017 | ||
| 150 | #define regk_clkgen_nand_4_3_pll 0x00000015 | ||
| 151 | #define regk_clkgen_nand_5_2 0x00000008 | ||
| 152 | #define regk_clkgen_nand_5_2_0x30 0x0000000a | ||
| 153 | #define regk_clkgen_nand_5_2_0x30_pll 0x0000001a | ||
| 154 | #define regk_clkgen_nand_5_2_pll 0x00000018 | ||
| 155 | #define regk_clkgen_nand_5_3 0x00000009 | ||
| 156 | #define regk_clkgen_nand_5_3_0x30 0x0000000b | ||
| 157 | #define regk_clkgen_nand_5_3_0x30_pll 0x0000001b | ||
| 158 | #define regk_clkgen_nand_5_3_pll 0x00000019 | ||
| 159 | #define regk_clkgen_no 0x00000000 | ||
| 160 | #define regk_clkgen_rw_clk_ctrl_default 0x00000002 | ||
| 161 | #define regk_clkgen_ser 0x0000000d | ||
| 162 | #define regk_clkgen_ser_pll 0x0000000f | ||
| 163 | #define regk_clkgen_yes 0x00000001 | ||
| 164 | #endif /* __clkgen_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h new file mode 100644 index 000000000000..b12be03edacb --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/ddr2_defs_asm.h | |||
| @@ -0,0 +1,266 @@ | |||
| 1 | #ifndef __ddr2_defs_asm_h | ||
| 2 | #define __ddr2_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ddr2.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_cfg, scope ddr2, type rw */ | ||
| 54 | #define reg_ddr2_rw_cfg___col_width___lsb 0 | ||
| 55 | #define reg_ddr2_rw_cfg___col_width___width 4 | ||
| 56 | #define reg_ddr2_rw_cfg___nr_banks___lsb 4 | ||
| 57 | #define reg_ddr2_rw_cfg___nr_banks___width 1 | ||
| 58 | #define reg_ddr2_rw_cfg___nr_banks___bit 4 | ||
| 59 | #define reg_ddr2_rw_cfg___bw___lsb 5 | ||
| 60 | #define reg_ddr2_rw_cfg___bw___width 1 | ||
| 61 | #define reg_ddr2_rw_cfg___bw___bit 5 | ||
| 62 | #define reg_ddr2_rw_cfg___nr_ref___lsb 6 | ||
| 63 | #define reg_ddr2_rw_cfg___nr_ref___width 4 | ||
| 64 | #define reg_ddr2_rw_cfg___ref_interval___lsb 10 | ||
| 65 | #define reg_ddr2_rw_cfg___ref_interval___width 11 | ||
| 66 | #define reg_ddr2_rw_cfg___odt_ctrl___lsb 21 | ||
| 67 | #define reg_ddr2_rw_cfg___odt_ctrl___width 2 | ||
| 68 | #define reg_ddr2_rw_cfg___odt_mem___lsb 23 | ||
| 69 | #define reg_ddr2_rw_cfg___odt_mem___width 1 | ||
| 70 | #define reg_ddr2_rw_cfg___odt_mem___bit 23 | ||
| 71 | #define reg_ddr2_rw_cfg___imp_strength___lsb 24 | ||
| 72 | #define reg_ddr2_rw_cfg___imp_strength___width 1 | ||
| 73 | #define reg_ddr2_rw_cfg___imp_strength___bit 24 | ||
| 74 | #define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25 | ||
| 75 | #define reg_ddr2_rw_cfg___auto_imp_cal___width 1 | ||
| 76 | #define reg_ddr2_rw_cfg___auto_imp_cal___bit 25 | ||
| 77 | #define reg_ddr2_rw_cfg___imp_cal_override___lsb 26 | ||
| 78 | #define reg_ddr2_rw_cfg___imp_cal_override___width 1 | ||
| 79 | #define reg_ddr2_rw_cfg___imp_cal_override___bit 26 | ||
| 80 | #define reg_ddr2_rw_cfg___dll_override___lsb 27 | ||
| 81 | #define reg_ddr2_rw_cfg___dll_override___width 1 | ||
| 82 | #define reg_ddr2_rw_cfg___dll_override___bit 27 | ||
| 83 | #define reg_ddr2_rw_cfg_offset 0 | ||
| 84 | |||
| 85 | /* Register rw_timing, scope ddr2, type rw */ | ||
| 86 | #define reg_ddr2_rw_timing___wr___lsb 0 | ||
| 87 | #define reg_ddr2_rw_timing___wr___width 3 | ||
| 88 | #define reg_ddr2_rw_timing___rcd___lsb 3 | ||
| 89 | #define reg_ddr2_rw_timing___rcd___width 3 | ||
| 90 | #define reg_ddr2_rw_timing___rp___lsb 6 | ||
| 91 | #define reg_ddr2_rw_timing___rp___width 3 | ||
| 92 | #define reg_ddr2_rw_timing___ras___lsb 9 | ||
| 93 | #define reg_ddr2_rw_timing___ras___width 4 | ||
| 94 | #define reg_ddr2_rw_timing___rfc___lsb 13 | ||
| 95 | #define reg_ddr2_rw_timing___rfc___width 7 | ||
| 96 | #define reg_ddr2_rw_timing___rc___lsb 20 | ||
| 97 | #define reg_ddr2_rw_timing___rc___width 5 | ||
| 98 | #define reg_ddr2_rw_timing___rtp___lsb 25 | ||
| 99 | #define reg_ddr2_rw_timing___rtp___width 2 | ||
| 100 | #define reg_ddr2_rw_timing___rtw___lsb 27 | ||
| 101 | #define reg_ddr2_rw_timing___rtw___width 3 | ||
| 102 | #define reg_ddr2_rw_timing___wtr___lsb 30 | ||
| 103 | #define reg_ddr2_rw_timing___wtr___width 2 | ||
| 104 | #define reg_ddr2_rw_timing_offset 4 | ||
| 105 | |||
| 106 | /* Register rw_latency, scope ddr2, type rw */ | ||
| 107 | #define reg_ddr2_rw_latency___cas___lsb 0 | ||
| 108 | #define reg_ddr2_rw_latency___cas___width 3 | ||
| 109 | #define reg_ddr2_rw_latency___additive___lsb 3 | ||
| 110 | #define reg_ddr2_rw_latency___additive___width 3 | ||
| 111 | #define reg_ddr2_rw_latency_offset 8 | ||
| 112 | |||
| 113 | /* Register rw_phy_cfg, scope ddr2, type rw */ | ||
| 114 | #define reg_ddr2_rw_phy_cfg___en___lsb 0 | ||
| 115 | #define reg_ddr2_rw_phy_cfg___en___width 1 | ||
| 116 | #define reg_ddr2_rw_phy_cfg___en___bit 0 | ||
| 117 | #define reg_ddr2_rw_phy_cfg_offset 12 | ||
| 118 | |||
| 119 | /* Register rw_phy_ctrl, scope ddr2, type rw */ | ||
| 120 | #define reg_ddr2_rw_phy_ctrl___rst___lsb 0 | ||
| 121 | #define reg_ddr2_rw_phy_ctrl___rst___width 1 | ||
| 122 | #define reg_ddr2_rw_phy_ctrl___rst___bit 0 | ||
| 123 | #define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1 | ||
| 124 | #define reg_ddr2_rw_phy_ctrl___cal_rst___width 1 | ||
| 125 | #define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1 | ||
| 126 | #define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2 | ||
| 127 | #define reg_ddr2_rw_phy_ctrl___cal_start___width 1 | ||
| 128 | #define reg_ddr2_rw_phy_ctrl___cal_start___bit 2 | ||
| 129 | #define reg_ddr2_rw_phy_ctrl_offset 16 | ||
| 130 | |||
| 131 | /* Register rw_ctrl, scope ddr2, type rw */ | ||
| 132 | #define reg_ddr2_rw_ctrl___mrs_data___lsb 0 | ||
| 133 | #define reg_ddr2_rw_ctrl___mrs_data___width 16 | ||
| 134 | #define reg_ddr2_rw_ctrl___cmd___lsb 16 | ||
| 135 | #define reg_ddr2_rw_ctrl___cmd___width 8 | ||
| 136 | #define reg_ddr2_rw_ctrl_offset 20 | ||
| 137 | |||
| 138 | /* Register rw_pwr_down, scope ddr2, type rw */ | ||
| 139 | #define reg_ddr2_rw_pwr_down___self_ref___lsb 0 | ||
| 140 | #define reg_ddr2_rw_pwr_down___self_ref___width 2 | ||
| 141 | #define reg_ddr2_rw_pwr_down___phy_en___lsb 2 | ||
| 142 | #define reg_ddr2_rw_pwr_down___phy_en___width 1 | ||
| 143 | #define reg_ddr2_rw_pwr_down___phy_en___bit 2 | ||
| 144 | #define reg_ddr2_rw_pwr_down_offset 24 | ||
| 145 | |||
| 146 | /* Register r_stat, scope ddr2, type r */ | ||
| 147 | #define reg_ddr2_r_stat___dll_lock___lsb 0 | ||
| 148 | #define reg_ddr2_r_stat___dll_lock___width 1 | ||
| 149 | #define reg_ddr2_r_stat___dll_lock___bit 0 | ||
| 150 | #define reg_ddr2_r_stat___dll_delay_code___lsb 1 | ||
| 151 | #define reg_ddr2_r_stat___dll_delay_code___width 7 | ||
| 152 | #define reg_ddr2_r_stat___imp_cal_done___lsb 8 | ||
| 153 | #define reg_ddr2_r_stat___imp_cal_done___width 1 | ||
| 154 | #define reg_ddr2_r_stat___imp_cal_done___bit 8 | ||
| 155 | #define reg_ddr2_r_stat___imp_cal_fault___lsb 9 | ||
| 156 | #define reg_ddr2_r_stat___imp_cal_fault___width 1 | ||
| 157 | #define reg_ddr2_r_stat___imp_cal_fault___bit 9 | ||
| 158 | #define reg_ddr2_r_stat___cal_imp_pu___lsb 10 | ||
| 159 | #define reg_ddr2_r_stat___cal_imp_pu___width 4 | ||
| 160 | #define reg_ddr2_r_stat___cal_imp_pd___lsb 14 | ||
| 161 | #define reg_ddr2_r_stat___cal_imp_pd___width 4 | ||
| 162 | #define reg_ddr2_r_stat_offset 28 | ||
| 163 | |||
| 164 | /* Register rw_imp_ctrl, scope ddr2, type rw */ | ||
| 165 | #define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0 | ||
| 166 | #define reg_ddr2_rw_imp_ctrl___imp_pu___width 4 | ||
| 167 | #define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4 | ||
| 168 | #define reg_ddr2_rw_imp_ctrl___imp_pd___width 4 | ||
| 169 | #define reg_ddr2_rw_imp_ctrl_offset 32 | ||
| 170 | |||
| 171 | #define STRIDE_ddr2_rw_dll_ctrl 4 | ||
| 172 | /* Register rw_dll_ctrl, scope ddr2, type rw */ | ||
| 173 | #define reg_ddr2_rw_dll_ctrl___mode___lsb 0 | ||
| 174 | #define reg_ddr2_rw_dll_ctrl___mode___width 1 | ||
| 175 | #define reg_ddr2_rw_dll_ctrl___mode___bit 0 | ||
| 176 | #define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1 | ||
| 177 | #define reg_ddr2_rw_dll_ctrl___clk_delay___width 7 | ||
| 178 | #define reg_ddr2_rw_dll_ctrl_offset 36 | ||
| 179 | |||
| 180 | #define STRIDE_ddr2_rw_dqs_dll_ctrl 4 | ||
| 181 | /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ | ||
| 182 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0 | ||
| 183 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7 | ||
| 184 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7 | ||
| 185 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7 | ||
| 186 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14 | ||
| 187 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7 | ||
| 188 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21 | ||
| 189 | #define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7 | ||
| 190 | #define reg_ddr2_rw_dqs_dll_ctrl_offset 52 | ||
| 191 | |||
| 192 | |||
| 193 | /* Constants */ | ||
| 194 | #define regk_ddr2_al0 0x00000000 | ||
| 195 | #define regk_ddr2_al1 0x00000008 | ||
| 196 | #define regk_ddr2_al2 0x00000010 | ||
| 197 | #define regk_ddr2_al3 0x00000018 | ||
| 198 | #define regk_ddr2_al4 0x00000020 | ||
| 199 | #define regk_ddr2_auto 0x00000003 | ||
| 200 | #define regk_ddr2_bank4 0x00000000 | ||
| 201 | #define regk_ddr2_bank8 0x00000001 | ||
| 202 | #define regk_ddr2_bl4 0x00000002 | ||
| 203 | #define regk_ddr2_bl8 0x00000003 | ||
| 204 | #define regk_ddr2_bt_il 0x00000008 | ||
| 205 | #define regk_ddr2_bt_seq 0x00000000 | ||
| 206 | #define regk_ddr2_bw16 0x00000001 | ||
| 207 | #define regk_ddr2_bw32 0x00000000 | ||
| 208 | #define regk_ddr2_cas2 0x00000020 | ||
| 209 | #define regk_ddr2_cas3 0x00000030 | ||
| 210 | #define regk_ddr2_cas4 0x00000040 | ||
| 211 | #define regk_ddr2_cas5 0x00000050 | ||
| 212 | #define regk_ddr2_deselect 0x000000c0 | ||
| 213 | #define regk_ddr2_dic_weak 0x00000002 | ||
| 214 | #define regk_ddr2_direct 0x00000001 | ||
| 215 | #define regk_ddr2_dis 0x00000000 | ||
| 216 | #define regk_ddr2_dll_dis 0x00000001 | ||
| 217 | #define regk_ddr2_dll_en 0x00000000 | ||
| 218 | #define regk_ddr2_dll_rst 0x00000100 | ||
| 219 | #define regk_ddr2_emrs 0x00000081 | ||
| 220 | #define regk_ddr2_emrs2 0x00000082 | ||
| 221 | #define regk_ddr2_emrs3 0x00000083 | ||
| 222 | #define regk_ddr2_full 0x00000001 | ||
| 223 | #define regk_ddr2_hi_ref_rate 0x00000080 | ||
| 224 | #define regk_ddr2_mrs 0x00000080 | ||
| 225 | #define regk_ddr2_no 0x00000000 | ||
| 226 | #define regk_ddr2_nop 0x000000b8 | ||
| 227 | #define regk_ddr2_ocd_adj 0x00000200 | ||
| 228 | #define regk_ddr2_ocd_default 0x00000380 | ||
| 229 | #define regk_ddr2_ocd_drive0 0x00000100 | ||
| 230 | #define regk_ddr2_ocd_drive1 0x00000080 | ||
| 231 | #define regk_ddr2_ocd_exit 0x00000000 | ||
| 232 | #define regk_ddr2_odt_dis 0x00000000 | ||
| 233 | #define regk_ddr2_offs 0x00000000 | ||
| 234 | #define regk_ddr2_pre 0x00000090 | ||
| 235 | #define regk_ddr2_pre_all 0x00000400 | ||
| 236 | #define regk_ddr2_pwr_down_fast 0x00000000 | ||
| 237 | #define regk_ddr2_pwr_down_slow 0x00001000 | ||
| 238 | #define regk_ddr2_ref 0x00000088 | ||
| 239 | #define regk_ddr2_rtt150 0x00000040 | ||
| 240 | #define regk_ddr2_rtt50 0x00000044 | ||
| 241 | #define regk_ddr2_rtt75 0x00000004 | ||
| 242 | #define regk_ddr2_rw_cfg_default 0x00186000 | ||
| 243 | #define regk_ddr2_rw_dll_ctrl_default 0x00000000 | ||
| 244 | #define regk_ddr2_rw_dll_ctrl_size 0x00000004 | ||
| 245 | #define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000 | ||
| 246 | #define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004 | ||
| 247 | #define regk_ddr2_rw_latency_default 0x00000000 | ||
| 248 | #define regk_ddr2_rw_phy_cfg_default 0x00000000 | ||
| 249 | #define regk_ddr2_rw_pwr_down_default 0x00000000 | ||
| 250 | #define regk_ddr2_rw_timing_default 0x00000000 | ||
| 251 | #define regk_ddr2_s1Gb 0x0000001a | ||
| 252 | #define regk_ddr2_s256Mb 0x0000000f | ||
| 253 | #define regk_ddr2_s2Gb 0x00000027 | ||
| 254 | #define regk_ddr2_s4Gb 0x00000042 | ||
| 255 | #define regk_ddr2_s512Mb 0x00000015 | ||
| 256 | #define regk_ddr2_temp0_85 0x00000618 | ||
| 257 | #define regk_ddr2_temp85_95 0x0000030c | ||
| 258 | #define regk_ddr2_term150 0x00000002 | ||
| 259 | #define regk_ddr2_term50 0x00000003 | ||
| 260 | #define regk_ddr2_term75 0x00000001 | ||
| 261 | #define regk_ddr2_test 0x00000080 | ||
| 262 | #define regk_ddr2_weak 0x00000000 | ||
| 263 | #define regk_ddr2_wr2 0x00000200 | ||
| 264 | #define regk_ddr2_wr3 0x00000400 | ||
| 265 | #define regk_ddr2_yes 0x00000001 | ||
| 266 | #endif /* __ddr2_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h new file mode 100644 index 000000000000..df6714fda179 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/gio_defs_asm.h | |||
| @@ -0,0 +1,849 @@ | |||
| 1 | #ifndef __gio_defs_asm_h | ||
| 2 | #define __gio_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: gio.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register r_pa_din, scope gio, type r */ | ||
| 54 | #define reg_gio_r_pa_din___data___lsb 0 | ||
| 55 | #define reg_gio_r_pa_din___data___width 32 | ||
| 56 | #define reg_gio_r_pa_din_offset 0 | ||
| 57 | |||
| 58 | /* Register rw_pa_dout, scope gio, type rw */ | ||
| 59 | #define reg_gio_rw_pa_dout___data___lsb 0 | ||
| 60 | #define reg_gio_rw_pa_dout___data___width 32 | ||
| 61 | #define reg_gio_rw_pa_dout_offset 4 | ||
| 62 | |||
| 63 | /* Register rw_pa_oe, scope gio, type rw */ | ||
| 64 | #define reg_gio_rw_pa_oe___oe___lsb 0 | ||
| 65 | #define reg_gio_rw_pa_oe___oe___width 32 | ||
| 66 | #define reg_gio_rw_pa_oe_offset 8 | ||
| 67 | |||
| 68 | /* Register rw_pa_byte0_dout, scope gio, type rw */ | ||
| 69 | #define reg_gio_rw_pa_byte0_dout___data___lsb 0 | ||
| 70 | #define reg_gio_rw_pa_byte0_dout___data___width 8 | ||
| 71 | #define reg_gio_rw_pa_byte0_dout_offset 12 | ||
| 72 | |||
| 73 | /* Register rw_pa_byte0_oe, scope gio, type rw */ | ||
| 74 | #define reg_gio_rw_pa_byte0_oe___oe___lsb 0 | ||
| 75 | #define reg_gio_rw_pa_byte0_oe___oe___width 8 | ||
| 76 | #define reg_gio_rw_pa_byte0_oe_offset 16 | ||
| 77 | |||
| 78 | /* Register rw_pa_byte1_dout, scope gio, type rw */ | ||
| 79 | #define reg_gio_rw_pa_byte1_dout___data___lsb 0 | ||
| 80 | #define reg_gio_rw_pa_byte1_dout___data___width 8 | ||
| 81 | #define reg_gio_rw_pa_byte1_dout_offset 20 | ||
| 82 | |||
| 83 | /* Register rw_pa_byte1_oe, scope gio, type rw */ | ||
| 84 | #define reg_gio_rw_pa_byte1_oe___oe___lsb 0 | ||
| 85 | #define reg_gio_rw_pa_byte1_oe___oe___width 8 | ||
| 86 | #define reg_gio_rw_pa_byte1_oe_offset 24 | ||
| 87 | |||
| 88 | /* Register rw_pa_byte2_dout, scope gio, type rw */ | ||
| 89 | #define reg_gio_rw_pa_byte2_dout___data___lsb 0 | ||
| 90 | #define reg_gio_rw_pa_byte2_dout___data___width 8 | ||
| 91 | #define reg_gio_rw_pa_byte2_dout_offset 28 | ||
| 92 | |||
| 93 | /* Register rw_pa_byte2_oe, scope gio, type rw */ | ||
| 94 | #define reg_gio_rw_pa_byte2_oe___oe___lsb 0 | ||
| 95 | #define reg_gio_rw_pa_byte2_oe___oe___width 8 | ||
| 96 | #define reg_gio_rw_pa_byte2_oe_offset 32 | ||
| 97 | |||
| 98 | /* Register rw_pa_byte3_dout, scope gio, type rw */ | ||
| 99 | #define reg_gio_rw_pa_byte3_dout___data___lsb 0 | ||
| 100 | #define reg_gio_rw_pa_byte3_dout___data___width 8 | ||
| 101 | #define reg_gio_rw_pa_byte3_dout_offset 36 | ||
| 102 | |||
| 103 | /* Register rw_pa_byte3_oe, scope gio, type rw */ | ||
| 104 | #define reg_gio_rw_pa_byte3_oe___oe___lsb 0 | ||
| 105 | #define reg_gio_rw_pa_byte3_oe___oe___width 8 | ||
| 106 | #define reg_gio_rw_pa_byte3_oe_offset 40 | ||
| 107 | |||
| 108 | /* Register r_pb_din, scope gio, type r */ | ||
| 109 | #define reg_gio_r_pb_din___data___lsb 0 | ||
| 110 | #define reg_gio_r_pb_din___data___width 32 | ||
| 111 | #define reg_gio_r_pb_din_offset 44 | ||
| 112 | |||
| 113 | /* Register rw_pb_dout, scope gio, type rw */ | ||
| 114 | #define reg_gio_rw_pb_dout___data___lsb 0 | ||
| 115 | #define reg_gio_rw_pb_dout___data___width 32 | ||
| 116 | #define reg_gio_rw_pb_dout_offset 48 | ||
| 117 | |||
| 118 | /* Register rw_pb_oe, scope gio, type rw */ | ||
| 119 | #define reg_gio_rw_pb_oe___oe___lsb 0 | ||
| 120 | #define reg_gio_rw_pb_oe___oe___width 32 | ||
| 121 | #define reg_gio_rw_pb_oe_offset 52 | ||
| 122 | |||
| 123 | /* Register rw_pb_byte0_dout, scope gio, type rw */ | ||
| 124 | #define reg_gio_rw_pb_byte0_dout___data___lsb 0 | ||
| 125 | #define reg_gio_rw_pb_byte0_dout___data___width 8 | ||
| 126 | #define reg_gio_rw_pb_byte0_dout_offset 56 | ||
| 127 | |||
| 128 | /* Register rw_pb_byte0_oe, scope gio, type rw */ | ||
| 129 | #define reg_gio_rw_pb_byte0_oe___oe___lsb 0 | ||
| 130 | #define reg_gio_rw_pb_byte0_oe___oe___width 8 | ||
| 131 | #define reg_gio_rw_pb_byte0_oe_offset 60 | ||
| 132 | |||
| 133 | /* Register rw_pb_byte1_dout, scope gio, type rw */ | ||
| 134 | #define reg_gio_rw_pb_byte1_dout___data___lsb 0 | ||
| 135 | #define reg_gio_rw_pb_byte1_dout___data___width 8 | ||
| 136 | #define reg_gio_rw_pb_byte1_dout_offset 64 | ||
| 137 | |||
| 138 | /* Register rw_pb_byte1_oe, scope gio, type rw */ | ||
| 139 | #define reg_gio_rw_pb_byte1_oe___oe___lsb 0 | ||
| 140 | #define reg_gio_rw_pb_byte1_oe___oe___width 8 | ||
| 141 | #define reg_gio_rw_pb_byte1_oe_offset 68 | ||
| 142 | |||
| 143 | /* Register rw_pb_byte2_dout, scope gio, type rw */ | ||
| 144 | #define reg_gio_rw_pb_byte2_dout___data___lsb 0 | ||
| 145 | #define reg_gio_rw_pb_byte2_dout___data___width 8 | ||
| 146 | #define reg_gio_rw_pb_byte2_dout_offset 72 | ||
| 147 | |||
| 148 | /* Register rw_pb_byte2_oe, scope gio, type rw */ | ||
| 149 | #define reg_gio_rw_pb_byte2_oe___oe___lsb 0 | ||
| 150 | #define reg_gio_rw_pb_byte2_oe___oe___width 8 | ||
| 151 | #define reg_gio_rw_pb_byte2_oe_offset 76 | ||
| 152 | |||
| 153 | /* Register rw_pb_byte3_dout, scope gio, type rw */ | ||
| 154 | #define reg_gio_rw_pb_byte3_dout___data___lsb 0 | ||
| 155 | #define reg_gio_rw_pb_byte3_dout___data___width 8 | ||
| 156 | #define reg_gio_rw_pb_byte3_dout_offset 80 | ||
| 157 | |||
| 158 | /* Register rw_pb_byte3_oe, scope gio, type rw */ | ||
| 159 | #define reg_gio_rw_pb_byte3_oe___oe___lsb 0 | ||
| 160 | #define reg_gio_rw_pb_byte3_oe___oe___width 8 | ||
| 161 | #define reg_gio_rw_pb_byte3_oe_offset 84 | ||
| 162 | |||
| 163 | /* Register r_pc_din, scope gio, type r */ | ||
| 164 | #define reg_gio_r_pc_din___data___lsb 0 | ||
| 165 | #define reg_gio_r_pc_din___data___width 16 | ||
| 166 | #define reg_gio_r_pc_din_offset 88 | ||
| 167 | |||
| 168 | /* Register rw_pc_dout, scope gio, type rw */ | ||
| 169 | #define reg_gio_rw_pc_dout___data___lsb 0 | ||
| 170 | #define reg_gio_rw_pc_dout___data___width 16 | ||
| 171 | #define reg_gio_rw_pc_dout_offset 92 | ||
| 172 | |||
| 173 | /* Register rw_pc_oe, scope gio, type rw */ | ||
| 174 | #define reg_gio_rw_pc_oe___oe___lsb 0 | ||
| 175 | #define reg_gio_rw_pc_oe___oe___width 16 | ||
| 176 | #define reg_gio_rw_pc_oe_offset 96 | ||
| 177 | |||
| 178 | /* Register rw_pc_byte0_dout, scope gio, type rw */ | ||
| 179 | #define reg_gio_rw_pc_byte0_dout___data___lsb 0 | ||
| 180 | #define reg_gio_rw_pc_byte0_dout___data___width 8 | ||
| 181 | #define reg_gio_rw_pc_byte0_dout_offset 100 | ||
| 182 | |||
| 183 | /* Register rw_pc_byte0_oe, scope gio, type rw */ | ||
| 184 | #define reg_gio_rw_pc_byte0_oe___oe___lsb 0 | ||
| 185 | #define reg_gio_rw_pc_byte0_oe___oe___width 8 | ||
| 186 | #define reg_gio_rw_pc_byte0_oe_offset 104 | ||
| 187 | |||
| 188 | /* Register rw_pc_byte1_dout, scope gio, type rw */ | ||
| 189 | #define reg_gio_rw_pc_byte1_dout___data___lsb 0 | ||
| 190 | #define reg_gio_rw_pc_byte1_dout___data___width 8 | ||
| 191 | #define reg_gio_rw_pc_byte1_dout_offset 108 | ||
| 192 | |||
| 193 | /* Register rw_pc_byte1_oe, scope gio, type rw */ | ||
| 194 | #define reg_gio_rw_pc_byte1_oe___oe___lsb 0 | ||
| 195 | #define reg_gio_rw_pc_byte1_oe___oe___width 8 | ||
| 196 | #define reg_gio_rw_pc_byte1_oe_offset 112 | ||
| 197 | |||
| 198 | /* Register r_pd_din, scope gio, type r */ | ||
| 199 | #define reg_gio_r_pd_din___data___lsb 0 | ||
| 200 | #define reg_gio_r_pd_din___data___width 32 | ||
| 201 | #define reg_gio_r_pd_din_offset 116 | ||
| 202 | |||
| 203 | /* Register rw_intr_cfg, scope gio, type rw */ | ||
| 204 | #define reg_gio_rw_intr_cfg___intr0___lsb 0 | ||
| 205 | #define reg_gio_rw_intr_cfg___intr0___width 3 | ||
| 206 | #define reg_gio_rw_intr_cfg___intr1___lsb 3 | ||
| 207 | #define reg_gio_rw_intr_cfg___intr1___width 3 | ||
| 208 | #define reg_gio_rw_intr_cfg___intr2___lsb 6 | ||
| 209 | #define reg_gio_rw_intr_cfg___intr2___width 3 | ||
| 210 | #define reg_gio_rw_intr_cfg___intr3___lsb 9 | ||
| 211 | #define reg_gio_rw_intr_cfg___intr3___width 3 | ||
| 212 | #define reg_gio_rw_intr_cfg___intr4___lsb 12 | ||
| 213 | #define reg_gio_rw_intr_cfg___intr4___width 3 | ||
| 214 | #define reg_gio_rw_intr_cfg___intr5___lsb 15 | ||
| 215 | #define reg_gio_rw_intr_cfg___intr5___width 3 | ||
| 216 | #define reg_gio_rw_intr_cfg___intr6___lsb 18 | ||
| 217 | #define reg_gio_rw_intr_cfg___intr6___width 3 | ||
| 218 | #define reg_gio_rw_intr_cfg___intr7___lsb 21 | ||
| 219 | #define reg_gio_rw_intr_cfg___intr7___width 3 | ||
| 220 | #define reg_gio_rw_intr_cfg_offset 120 | ||
| 221 | |||
| 222 | /* Register rw_intr_pins, scope gio, type rw */ | ||
| 223 | #define reg_gio_rw_intr_pins___intr0___lsb 0 | ||
| 224 | #define reg_gio_rw_intr_pins___intr0___width 4 | ||
| 225 | #define reg_gio_rw_intr_pins___intr1___lsb 4 | ||
| 226 | #define reg_gio_rw_intr_pins___intr1___width 4 | ||
| 227 | #define reg_gio_rw_intr_pins___intr2___lsb 8 | ||
| 228 | #define reg_gio_rw_intr_pins___intr2___width 4 | ||
| 229 | #define reg_gio_rw_intr_pins___intr3___lsb 12 | ||
| 230 | #define reg_gio_rw_intr_pins___intr3___width 4 | ||
| 231 | #define reg_gio_rw_intr_pins___intr4___lsb 16 | ||
| 232 | #define reg_gio_rw_intr_pins___intr4___width 4 | ||
| 233 | #define reg_gio_rw_intr_pins___intr5___lsb 20 | ||
| 234 | #define reg_gio_rw_intr_pins___intr5___width 4 | ||
| 235 | #define reg_gio_rw_intr_pins___intr6___lsb 24 | ||
| 236 | #define reg_gio_rw_intr_pins___intr6___width 4 | ||
| 237 | #define reg_gio_rw_intr_pins___intr7___lsb 28 | ||
| 238 | #define reg_gio_rw_intr_pins___intr7___width 4 | ||
| 239 | #define reg_gio_rw_intr_pins_offset 124 | ||
| 240 | |||
| 241 | /* Register rw_intr_mask, scope gio, type rw */ | ||
| 242 | #define reg_gio_rw_intr_mask___intr0___lsb 0 | ||
| 243 | #define reg_gio_rw_intr_mask___intr0___width 1 | ||
| 244 | #define reg_gio_rw_intr_mask___intr0___bit 0 | ||
| 245 | #define reg_gio_rw_intr_mask___intr1___lsb 1 | ||
| 246 | #define reg_gio_rw_intr_mask___intr1___width 1 | ||
| 247 | #define reg_gio_rw_intr_mask___intr1___bit 1 | ||
| 248 | #define reg_gio_rw_intr_mask___intr2___lsb 2 | ||
| 249 | #define reg_gio_rw_intr_mask___intr2___width 1 | ||
| 250 | #define reg_gio_rw_intr_mask___intr2___bit 2 | ||
| 251 | #define reg_gio_rw_intr_mask___intr3___lsb 3 | ||
| 252 | #define reg_gio_rw_intr_mask___intr3___width 1 | ||
| 253 | #define reg_gio_rw_intr_mask___intr3___bit 3 | ||
| 254 | #define reg_gio_rw_intr_mask___intr4___lsb 4 | ||
| 255 | #define reg_gio_rw_intr_mask___intr4___width 1 | ||
| 256 | #define reg_gio_rw_intr_mask___intr4___bit 4 | ||
| 257 | #define reg_gio_rw_intr_mask___intr5___lsb 5 | ||
| 258 | #define reg_gio_rw_intr_mask___intr5___width 1 | ||
| 259 | #define reg_gio_rw_intr_mask___intr5___bit 5 | ||
| 260 | #define reg_gio_rw_intr_mask___intr6___lsb 6 | ||
| 261 | #define reg_gio_rw_intr_mask___intr6___width 1 | ||
| 262 | #define reg_gio_rw_intr_mask___intr6___bit 6 | ||
| 263 | #define reg_gio_rw_intr_mask___intr7___lsb 7 | ||
| 264 | #define reg_gio_rw_intr_mask___intr7___width 1 | ||
| 265 | #define reg_gio_rw_intr_mask___intr7___bit 7 | ||
| 266 | #define reg_gio_rw_intr_mask___i2c0_done___lsb 8 | ||
| 267 | #define reg_gio_rw_intr_mask___i2c0_done___width 1 | ||
| 268 | #define reg_gio_rw_intr_mask___i2c0_done___bit 8 | ||
| 269 | #define reg_gio_rw_intr_mask___i2c1_done___lsb 9 | ||
| 270 | #define reg_gio_rw_intr_mask___i2c1_done___width 1 | ||
| 271 | #define reg_gio_rw_intr_mask___i2c1_done___bit 9 | ||
| 272 | #define reg_gio_rw_intr_mask_offset 128 | ||
| 273 | |||
| 274 | /* Register rw_ack_intr, scope gio, type rw */ | ||
| 275 | #define reg_gio_rw_ack_intr___intr0___lsb 0 | ||
| 276 | #define reg_gio_rw_ack_intr___intr0___width 1 | ||
| 277 | #define reg_gio_rw_ack_intr___intr0___bit 0 | ||
| 278 | #define reg_gio_rw_ack_intr___intr1___lsb 1 | ||
| 279 | #define reg_gio_rw_ack_intr___intr1___width 1 | ||
| 280 | #define reg_gio_rw_ack_intr___intr1___bit 1 | ||
| 281 | #define reg_gio_rw_ack_intr___intr2___lsb 2 | ||
| 282 | #define reg_gio_rw_ack_intr___intr2___width 1 | ||
| 283 | #define reg_gio_rw_ack_intr___intr2___bit 2 | ||
| 284 | #define reg_gio_rw_ack_intr___intr3___lsb 3 | ||
| 285 | #define reg_gio_rw_ack_intr___intr3___width 1 | ||
| 286 | #define reg_gio_rw_ack_intr___intr3___bit 3 | ||
| 287 | #define reg_gio_rw_ack_intr___intr4___lsb 4 | ||
| 288 | #define reg_gio_rw_ack_intr___intr4___width 1 | ||
| 289 | #define reg_gio_rw_ack_intr___intr4___bit 4 | ||
| 290 | #define reg_gio_rw_ack_intr___intr5___lsb 5 | ||
| 291 | #define reg_gio_rw_ack_intr___intr5___width 1 | ||
| 292 | #define reg_gio_rw_ack_intr___intr5___bit 5 | ||
| 293 | #define reg_gio_rw_ack_intr___intr6___lsb 6 | ||
| 294 | #define reg_gio_rw_ack_intr___intr6___width 1 | ||
| 295 | #define reg_gio_rw_ack_intr___intr6___bit 6 | ||
| 296 | #define reg_gio_rw_ack_intr___intr7___lsb 7 | ||
| 297 | #define reg_gio_rw_ack_intr___intr7___width 1 | ||
| 298 | #define reg_gio_rw_ack_intr___intr7___bit 7 | ||
| 299 | #define reg_gio_rw_ack_intr___i2c0_done___lsb 8 | ||
| 300 | #define reg_gio_rw_ack_intr___i2c0_done___width 1 | ||
| 301 | #define reg_gio_rw_ack_intr___i2c0_done___bit 8 | ||
| 302 | #define reg_gio_rw_ack_intr___i2c1_done___lsb 9 | ||
| 303 | #define reg_gio_rw_ack_intr___i2c1_done___width 1 | ||
| 304 | #define reg_gio_rw_ack_intr___i2c1_done___bit 9 | ||
| 305 | #define reg_gio_rw_ack_intr_offset 132 | ||
| 306 | |||
| 307 | /* Register r_intr, scope gio, type r */ | ||
| 308 | #define reg_gio_r_intr___intr0___lsb 0 | ||
| 309 | #define reg_gio_r_intr___intr0___width 1 | ||
| 310 | #define reg_gio_r_intr___intr0___bit 0 | ||
| 311 | #define reg_gio_r_intr___intr1___lsb 1 | ||
| 312 | #define reg_gio_r_intr___intr1___width 1 | ||
| 313 | #define reg_gio_r_intr___intr1___bit 1 | ||
| 314 | #define reg_gio_r_intr___intr2___lsb 2 | ||
| 315 | #define reg_gio_r_intr___intr2___width 1 | ||
| 316 | #define reg_gio_r_intr___intr2___bit 2 | ||
| 317 | #define reg_gio_r_intr___intr3___lsb 3 | ||
| 318 | #define reg_gio_r_intr___intr3___width 1 | ||
| 319 | #define reg_gio_r_intr___intr3___bit 3 | ||
| 320 | #define reg_gio_r_intr___intr4___lsb 4 | ||
| 321 | #define reg_gio_r_intr___intr4___width 1 | ||
| 322 | #define reg_gio_r_intr___intr4___bit 4 | ||
| 323 | #define reg_gio_r_intr___intr5___lsb 5 | ||
| 324 | #define reg_gio_r_intr___intr5___width 1 | ||
| 325 | #define reg_gio_r_intr___intr5___bit 5 | ||
| 326 | #define reg_gio_r_intr___intr6___lsb 6 | ||
| 327 | #define reg_gio_r_intr___intr6___width 1 | ||
| 328 | #define reg_gio_r_intr___intr6___bit 6 | ||
| 329 | #define reg_gio_r_intr___intr7___lsb 7 | ||
| 330 | #define reg_gio_r_intr___intr7___width 1 | ||
| 331 | #define reg_gio_r_intr___intr7___bit 7 | ||
| 332 | #define reg_gio_r_intr___i2c0_done___lsb 8 | ||
| 333 | #define reg_gio_r_intr___i2c0_done___width 1 | ||
| 334 | #define reg_gio_r_intr___i2c0_done___bit 8 | ||
| 335 | #define reg_gio_r_intr___i2c1_done___lsb 9 | ||
| 336 | #define reg_gio_r_intr___i2c1_done___width 1 | ||
| 337 | #define reg_gio_r_intr___i2c1_done___bit 9 | ||
| 338 | #define reg_gio_r_intr_offset 136 | ||
| 339 | |||
| 340 | /* Register r_masked_intr, scope gio, type r */ | ||
| 341 | #define reg_gio_r_masked_intr___intr0___lsb 0 | ||
| 342 | #define reg_gio_r_masked_intr___intr0___width 1 | ||
| 343 | #define reg_gio_r_masked_intr___intr0___bit 0 | ||
| 344 | #define reg_gio_r_masked_intr___intr1___lsb 1 | ||
| 345 | #define reg_gio_r_masked_intr___intr1___width 1 | ||
| 346 | #define reg_gio_r_masked_intr___intr1___bit 1 | ||
| 347 | #define reg_gio_r_masked_intr___intr2___lsb 2 | ||
| 348 | #define reg_gio_r_masked_intr___intr2___width 1 | ||
| 349 | #define reg_gio_r_masked_intr___intr2___bit 2 | ||
| 350 | #define reg_gio_r_masked_intr___intr3___lsb 3 | ||
| 351 | #define reg_gio_r_masked_intr___intr3___width 1 | ||
| 352 | #define reg_gio_r_masked_intr___intr3___bit 3 | ||
| 353 | #define reg_gio_r_masked_intr___intr4___lsb 4 | ||
| 354 | #define reg_gio_r_masked_intr___intr4___width 1 | ||
| 355 | #define reg_gio_r_masked_intr___intr4___bit 4 | ||
| 356 | #define reg_gio_r_masked_intr___intr5___lsb 5 | ||
| 357 | #define reg_gio_r_masked_intr___intr5___width 1 | ||
| 358 | #define reg_gio_r_masked_intr___intr5___bit 5 | ||
| 359 | #define reg_gio_r_masked_intr___intr6___lsb 6 | ||
| 360 | #define reg_gio_r_masked_intr___intr6___width 1 | ||
| 361 | #define reg_gio_r_masked_intr___intr6___bit 6 | ||
| 362 | #define reg_gio_r_masked_intr___intr7___lsb 7 | ||
| 363 | #define reg_gio_r_masked_intr___intr7___width 1 | ||
| 364 | #define reg_gio_r_masked_intr___intr7___bit 7 | ||
| 365 | #define reg_gio_r_masked_intr___i2c0_done___lsb 8 | ||
| 366 | #define reg_gio_r_masked_intr___i2c0_done___width 1 | ||
| 367 | #define reg_gio_r_masked_intr___i2c0_done___bit 8 | ||
| 368 | #define reg_gio_r_masked_intr___i2c1_done___lsb 9 | ||
| 369 | #define reg_gio_r_masked_intr___i2c1_done___width 1 | ||
| 370 | #define reg_gio_r_masked_intr___i2c1_done___bit 9 | ||
| 371 | #define reg_gio_r_masked_intr_offset 140 | ||
| 372 | |||
| 373 | /* Register rw_i2c0_start, scope gio, type rw */ | ||
| 374 | #define reg_gio_rw_i2c0_start___run___lsb 0 | ||
| 375 | #define reg_gio_rw_i2c0_start___run___width 1 | ||
| 376 | #define reg_gio_rw_i2c0_start___run___bit 0 | ||
| 377 | #define reg_gio_rw_i2c0_start_offset 144 | ||
| 378 | |||
| 379 | /* Register rw_i2c0_cfg, scope gio, type rw */ | ||
| 380 | #define reg_gio_rw_i2c0_cfg___en___lsb 0 | ||
| 381 | #define reg_gio_rw_i2c0_cfg___en___width 1 | ||
| 382 | #define reg_gio_rw_i2c0_cfg___en___bit 0 | ||
| 383 | #define reg_gio_rw_i2c0_cfg___bit_order___lsb 1 | ||
| 384 | #define reg_gio_rw_i2c0_cfg___bit_order___width 1 | ||
| 385 | #define reg_gio_rw_i2c0_cfg___bit_order___bit 1 | ||
| 386 | #define reg_gio_rw_i2c0_cfg___scl_io___lsb 2 | ||
| 387 | #define reg_gio_rw_i2c0_cfg___scl_io___width 1 | ||
| 388 | #define reg_gio_rw_i2c0_cfg___scl_io___bit 2 | ||
| 389 | #define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3 | ||
| 390 | #define reg_gio_rw_i2c0_cfg___scl_inv___width 1 | ||
| 391 | #define reg_gio_rw_i2c0_cfg___scl_inv___bit 3 | ||
| 392 | #define reg_gio_rw_i2c0_cfg___sda_io___lsb 4 | ||
| 393 | #define reg_gio_rw_i2c0_cfg___sda_io___width 1 | ||
| 394 | #define reg_gio_rw_i2c0_cfg___sda_io___bit 4 | ||
| 395 | #define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5 | ||
| 396 | #define reg_gio_rw_i2c0_cfg___sda_idle___width 1 | ||
| 397 | #define reg_gio_rw_i2c0_cfg___sda_idle___bit 5 | ||
| 398 | #define reg_gio_rw_i2c0_cfg_offset 148 | ||
| 399 | |||
| 400 | /* Register rw_i2c0_ctrl, scope gio, type rw */ | ||
| 401 | #define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0 | ||
| 402 | #define reg_gio_rw_i2c0_ctrl___trf_bits___width 6 | ||
| 403 | #define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6 | ||
| 404 | #define reg_gio_rw_i2c0_ctrl___switch_dir___width 6 | ||
| 405 | #define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12 | ||
| 406 | #define reg_gio_rw_i2c0_ctrl___extra_start___width 3 | ||
| 407 | #define reg_gio_rw_i2c0_ctrl___early_end___lsb 15 | ||
| 408 | #define reg_gio_rw_i2c0_ctrl___early_end___width 1 | ||
| 409 | #define reg_gio_rw_i2c0_ctrl___early_end___bit 15 | ||
| 410 | #define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16 | ||
| 411 | #define reg_gio_rw_i2c0_ctrl___start_stop___width 1 | ||
| 412 | #define reg_gio_rw_i2c0_ctrl___start_stop___bit 16 | ||
| 413 | #define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17 | ||
| 414 | #define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1 | ||
| 415 | #define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17 | ||
| 416 | #define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18 | ||
| 417 | #define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1 | ||
| 418 | #define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18 | ||
| 419 | #define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19 | ||
| 420 | #define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1 | ||
| 421 | #define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19 | ||
| 422 | #define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20 | ||
| 423 | #define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1 | ||
| 424 | #define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20 | ||
| 425 | #define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21 | ||
| 426 | #define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1 | ||
| 427 | #define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21 | ||
| 428 | #define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22 | ||
| 429 | #define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1 | ||
| 430 | #define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22 | ||
| 431 | #define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23 | ||
| 432 | #define reg_gio_rw_i2c0_ctrl___ack_bit___width 1 | ||
| 433 | #define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23 | ||
| 434 | #define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24 | ||
| 435 | #define reg_gio_rw_i2c0_ctrl___start_bit___width 1 | ||
| 436 | #define reg_gio_rw_i2c0_ctrl___start_bit___bit 24 | ||
| 437 | #define reg_gio_rw_i2c0_ctrl___freq___lsb 25 | ||
| 438 | #define reg_gio_rw_i2c0_ctrl___freq___width 2 | ||
| 439 | #define reg_gio_rw_i2c0_ctrl_offset 152 | ||
| 440 | |||
| 441 | /* Register rw_i2c0_data, scope gio, type rw */ | ||
| 442 | #define reg_gio_rw_i2c0_data___data0___lsb 0 | ||
| 443 | #define reg_gio_rw_i2c0_data___data0___width 8 | ||
| 444 | #define reg_gio_rw_i2c0_data___data1___lsb 8 | ||
| 445 | #define reg_gio_rw_i2c0_data___data1___width 8 | ||
| 446 | #define reg_gio_rw_i2c0_data___data2___lsb 16 | ||
| 447 | #define reg_gio_rw_i2c0_data___data2___width 8 | ||
| 448 | #define reg_gio_rw_i2c0_data___data3___lsb 24 | ||
| 449 | #define reg_gio_rw_i2c0_data___data3___width 8 | ||
| 450 | #define reg_gio_rw_i2c0_data_offset 156 | ||
| 451 | |||
| 452 | /* Register rw_i2c0_data2, scope gio, type rw */ | ||
| 453 | #define reg_gio_rw_i2c0_data2___data4___lsb 0 | ||
| 454 | #define reg_gio_rw_i2c0_data2___data4___width 8 | ||
| 455 | #define reg_gio_rw_i2c0_data2___data5___lsb 8 | ||
| 456 | #define reg_gio_rw_i2c0_data2___data5___width 8 | ||
| 457 | #define reg_gio_rw_i2c0_data2___start_val___lsb 16 | ||
| 458 | #define reg_gio_rw_i2c0_data2___start_val___width 6 | ||
| 459 | #define reg_gio_rw_i2c0_data2___ack_val___lsb 22 | ||
| 460 | #define reg_gio_rw_i2c0_data2___ack_val___width 6 | ||
| 461 | #define reg_gio_rw_i2c0_data2_offset 160 | ||
| 462 | |||
| 463 | /* Register rw_i2c1_start, scope gio, type rw */ | ||
| 464 | #define reg_gio_rw_i2c1_start___run___lsb 0 | ||
| 465 | #define reg_gio_rw_i2c1_start___run___width 1 | ||
| 466 | #define reg_gio_rw_i2c1_start___run___bit 0 | ||
| 467 | #define reg_gio_rw_i2c1_start_offset 164 | ||
| 468 | |||
| 469 | /* Register rw_i2c1_cfg, scope gio, type rw */ | ||
| 470 | #define reg_gio_rw_i2c1_cfg___en___lsb 0 | ||
| 471 | #define reg_gio_rw_i2c1_cfg___en___width 1 | ||
| 472 | #define reg_gio_rw_i2c1_cfg___en___bit 0 | ||
| 473 | #define reg_gio_rw_i2c1_cfg___bit_order___lsb 1 | ||
| 474 | #define reg_gio_rw_i2c1_cfg___bit_order___width 1 | ||
| 475 | #define reg_gio_rw_i2c1_cfg___bit_order___bit 1 | ||
| 476 | #define reg_gio_rw_i2c1_cfg___scl_io___lsb 2 | ||
| 477 | #define reg_gio_rw_i2c1_cfg___scl_io___width 1 | ||
| 478 | #define reg_gio_rw_i2c1_cfg___scl_io___bit 2 | ||
| 479 | #define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3 | ||
| 480 | #define reg_gio_rw_i2c1_cfg___scl_inv___width 1 | ||
| 481 | #define reg_gio_rw_i2c1_cfg___scl_inv___bit 3 | ||
| 482 | #define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4 | ||
| 483 | #define reg_gio_rw_i2c1_cfg___sda0_io___width 1 | ||
| 484 | #define reg_gio_rw_i2c1_cfg___sda0_io___bit 4 | ||
| 485 | #define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5 | ||
| 486 | #define reg_gio_rw_i2c1_cfg___sda0_idle___width 1 | ||
| 487 | #define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5 | ||
| 488 | #define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6 | ||
| 489 | #define reg_gio_rw_i2c1_cfg___sda1_io___width 1 | ||
| 490 | #define reg_gio_rw_i2c1_cfg___sda1_io___bit 6 | ||
| 491 | #define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7 | ||
| 492 | #define reg_gio_rw_i2c1_cfg___sda1_idle___width 1 | ||
| 493 | #define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7 | ||
| 494 | #define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8 | ||
| 495 | #define reg_gio_rw_i2c1_cfg___sda2_io___width 1 | ||
| 496 | #define reg_gio_rw_i2c1_cfg___sda2_io___bit 8 | ||
| 497 | #define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9 | ||
| 498 | #define reg_gio_rw_i2c1_cfg___sda2_idle___width 1 | ||
| 499 | #define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9 | ||
| 500 | #define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10 | ||
| 501 | #define reg_gio_rw_i2c1_cfg___sda3_io___width 1 | ||
| 502 | #define reg_gio_rw_i2c1_cfg___sda3_io___bit 10 | ||
| 503 | #define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11 | ||
| 504 | #define reg_gio_rw_i2c1_cfg___sda3_idle___width 1 | ||
| 505 | #define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11 | ||
| 506 | #define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12 | ||
| 507 | #define reg_gio_rw_i2c1_cfg___sda_sel___width 2 | ||
| 508 | #define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14 | ||
| 509 | #define reg_gio_rw_i2c1_cfg___sen_idle___width 1 | ||
| 510 | #define reg_gio_rw_i2c1_cfg___sen_idle___bit 14 | ||
| 511 | #define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15 | ||
| 512 | #define reg_gio_rw_i2c1_cfg___sen_inv___width 1 | ||
| 513 | #define reg_gio_rw_i2c1_cfg___sen_inv___bit 15 | ||
| 514 | #define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16 | ||
| 515 | #define reg_gio_rw_i2c1_cfg___sen_sel___width 2 | ||
| 516 | #define reg_gio_rw_i2c1_cfg_offset 168 | ||
| 517 | |||
| 518 | /* Register rw_i2c1_ctrl, scope gio, type rw */ | ||
| 519 | #define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0 | ||
| 520 | #define reg_gio_rw_i2c1_ctrl___trf_bits___width 6 | ||
| 521 | #define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6 | ||
| 522 | #define reg_gio_rw_i2c1_ctrl___switch_dir___width 6 | ||
| 523 | #define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12 | ||
| 524 | #define reg_gio_rw_i2c1_ctrl___extra_start___width 3 | ||
| 525 | #define reg_gio_rw_i2c1_ctrl___early_end___lsb 15 | ||
| 526 | #define reg_gio_rw_i2c1_ctrl___early_end___width 1 | ||
| 527 | #define reg_gio_rw_i2c1_ctrl___early_end___bit 15 | ||
| 528 | #define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16 | ||
| 529 | #define reg_gio_rw_i2c1_ctrl___start_stop___width 1 | ||
| 530 | #define reg_gio_rw_i2c1_ctrl___start_stop___bit 16 | ||
| 531 | #define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17 | ||
| 532 | #define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1 | ||
| 533 | #define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17 | ||
| 534 | #define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18 | ||
| 535 | #define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1 | ||
| 536 | #define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18 | ||
| 537 | #define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19 | ||
| 538 | #define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1 | ||
| 539 | #define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19 | ||
| 540 | #define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20 | ||
| 541 | #define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1 | ||
| 542 | #define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20 | ||
| 543 | #define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21 | ||
| 544 | #define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1 | ||
| 545 | #define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21 | ||
| 546 | #define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22 | ||
| 547 | #define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1 | ||
| 548 | #define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22 | ||
| 549 | #define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23 | ||
| 550 | #define reg_gio_rw_i2c1_ctrl___ack_bit___width 1 | ||
| 551 | #define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23 | ||
| 552 | #define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24 | ||
| 553 | #define reg_gio_rw_i2c1_ctrl___start_bit___width 1 | ||
| 554 | #define reg_gio_rw_i2c1_ctrl___start_bit___bit 24 | ||
| 555 | #define reg_gio_rw_i2c1_ctrl___freq___lsb 25 | ||
| 556 | #define reg_gio_rw_i2c1_ctrl___freq___width 2 | ||
| 557 | #define reg_gio_rw_i2c1_ctrl_offset 172 | ||
| 558 | |||
| 559 | /* Register rw_i2c1_data, scope gio, type rw */ | ||
| 560 | #define reg_gio_rw_i2c1_data___data0___lsb 0 | ||
| 561 | #define reg_gio_rw_i2c1_data___data0___width 8 | ||
| 562 | #define reg_gio_rw_i2c1_data___data1___lsb 8 | ||
| 563 | #define reg_gio_rw_i2c1_data___data1___width 8 | ||
| 564 | #define reg_gio_rw_i2c1_data___data2___lsb 16 | ||
| 565 | #define reg_gio_rw_i2c1_data___data2___width 8 | ||
| 566 | #define reg_gio_rw_i2c1_data___data3___lsb 24 | ||
| 567 | #define reg_gio_rw_i2c1_data___data3___width 8 | ||
| 568 | #define reg_gio_rw_i2c1_data_offset 176 | ||
| 569 | |||
| 570 | /* Register rw_i2c1_data2, scope gio, type rw */ | ||
| 571 | #define reg_gio_rw_i2c1_data2___data4___lsb 0 | ||
| 572 | #define reg_gio_rw_i2c1_data2___data4___width 8 | ||
| 573 | #define reg_gio_rw_i2c1_data2___data5___lsb 8 | ||
| 574 | #define reg_gio_rw_i2c1_data2___data5___width 8 | ||
| 575 | #define reg_gio_rw_i2c1_data2___start_val___lsb 16 | ||
| 576 | #define reg_gio_rw_i2c1_data2___start_val___width 6 | ||
| 577 | #define reg_gio_rw_i2c1_data2___ack_val___lsb 22 | ||
| 578 | #define reg_gio_rw_i2c1_data2___ack_val___width 6 | ||
| 579 | #define reg_gio_rw_i2c1_data2_offset 180 | ||
| 580 | |||
| 581 | /* Register r_ppwm_stat, scope gio, type r */ | ||
| 582 | #define reg_gio_r_ppwm_stat___freq___lsb 0 | ||
| 583 | #define reg_gio_r_ppwm_stat___freq___width 2 | ||
| 584 | #define reg_gio_r_ppwm_stat_offset 184 | ||
| 585 | |||
| 586 | /* Register rw_ppwm_data, scope gio, type rw */ | ||
| 587 | #define reg_gio_rw_ppwm_data___data___lsb 0 | ||
| 588 | #define reg_gio_rw_ppwm_data___data___width 8 | ||
| 589 | #define reg_gio_rw_ppwm_data_offset 188 | ||
| 590 | |||
| 591 | /* Register rw_pwm0_ctrl, scope gio, type rw */ | ||
| 592 | #define reg_gio_rw_pwm0_ctrl___mode___lsb 0 | ||
| 593 | #define reg_gio_rw_pwm0_ctrl___mode___width 2 | ||
| 594 | #define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2 | ||
| 595 | #define reg_gio_rw_pwm0_ctrl___ccd_override___width 1 | ||
| 596 | #define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2 | ||
| 597 | #define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3 | ||
| 598 | #define reg_gio_rw_pwm0_ctrl___ccd_val___width 1 | ||
| 599 | #define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3 | ||
| 600 | #define reg_gio_rw_pwm0_ctrl_offset 192 | ||
| 601 | |||
| 602 | /* Register rw_pwm0_var, scope gio, type rw */ | ||
| 603 | #define reg_gio_rw_pwm0_var___lo___lsb 0 | ||
| 604 | #define reg_gio_rw_pwm0_var___lo___width 13 | ||
| 605 | #define reg_gio_rw_pwm0_var___hi___lsb 13 | ||
| 606 | #define reg_gio_rw_pwm0_var___hi___width 13 | ||
| 607 | #define reg_gio_rw_pwm0_var_offset 196 | ||
| 608 | |||
| 609 | /* Register rw_pwm0_data, scope gio, type rw */ | ||
| 610 | #define reg_gio_rw_pwm0_data___data___lsb 0 | ||
| 611 | #define reg_gio_rw_pwm0_data___data___width 8 | ||
| 612 | #define reg_gio_rw_pwm0_data_offset 200 | ||
| 613 | |||
| 614 | /* Register rw_pwm1_ctrl, scope gio, type rw */ | ||
| 615 | #define reg_gio_rw_pwm1_ctrl___mode___lsb 0 | ||
| 616 | #define reg_gio_rw_pwm1_ctrl___mode___width 2 | ||
| 617 | #define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2 | ||
| 618 | #define reg_gio_rw_pwm1_ctrl___ccd_override___width 1 | ||
| 619 | #define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2 | ||
| 620 | #define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3 | ||
| 621 | #define reg_gio_rw_pwm1_ctrl___ccd_val___width 1 | ||
| 622 | #define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3 | ||
| 623 | #define reg_gio_rw_pwm1_ctrl_offset 204 | ||
| 624 | |||
| 625 | /* Register rw_pwm1_var, scope gio, type rw */ | ||
| 626 | #define reg_gio_rw_pwm1_var___lo___lsb 0 | ||
| 627 | #define reg_gio_rw_pwm1_var___lo___width 13 | ||
| 628 | #define reg_gio_rw_pwm1_var___hi___lsb 13 | ||
| 629 | #define reg_gio_rw_pwm1_var___hi___width 13 | ||
| 630 | #define reg_gio_rw_pwm1_var_offset 208 | ||
| 631 | |||
| 632 | /* Register rw_pwm1_data, scope gio, type rw */ | ||
| 633 | #define reg_gio_rw_pwm1_data___data___lsb 0 | ||
| 634 | #define reg_gio_rw_pwm1_data___data___width 8 | ||
| 635 | #define reg_gio_rw_pwm1_data_offset 212 | ||
| 636 | |||
| 637 | /* Register rw_pwm2_ctrl, scope gio, type rw */ | ||
| 638 | #define reg_gio_rw_pwm2_ctrl___mode___lsb 0 | ||
| 639 | #define reg_gio_rw_pwm2_ctrl___mode___width 2 | ||
| 640 | #define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2 | ||
| 641 | #define reg_gio_rw_pwm2_ctrl___ccd_override___width 1 | ||
| 642 | #define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2 | ||
| 643 | #define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3 | ||
| 644 | #define reg_gio_rw_pwm2_ctrl___ccd_val___width 1 | ||
| 645 | #define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3 | ||
| 646 | #define reg_gio_rw_pwm2_ctrl_offset 216 | ||
| 647 | |||
| 648 | /* Register rw_pwm2_var, scope gio, type rw */ | ||
| 649 | #define reg_gio_rw_pwm2_var___lo___lsb 0 | ||
| 650 | #define reg_gio_rw_pwm2_var___lo___width 13 | ||
| 651 | #define reg_gio_rw_pwm2_var___hi___lsb 13 | ||
| 652 | #define reg_gio_rw_pwm2_var___hi___width 13 | ||
| 653 | #define reg_gio_rw_pwm2_var_offset 220 | ||
| 654 | |||
| 655 | /* Register rw_pwm2_data, scope gio, type rw */ | ||
| 656 | #define reg_gio_rw_pwm2_data___data___lsb 0 | ||
| 657 | #define reg_gio_rw_pwm2_data___data___width 8 | ||
| 658 | #define reg_gio_rw_pwm2_data_offset 224 | ||
| 659 | |||
| 660 | /* Register rw_pwm_in_cfg, scope gio, type rw */ | ||
| 661 | #define reg_gio_rw_pwm_in_cfg___pin___lsb 0 | ||
| 662 | #define reg_gio_rw_pwm_in_cfg___pin___width 3 | ||
| 663 | #define reg_gio_rw_pwm_in_cfg_offset 228 | ||
| 664 | |||
| 665 | /* Register r_pwm_in_lo, scope gio, type r */ | ||
| 666 | #define reg_gio_r_pwm_in_lo___data___lsb 0 | ||
| 667 | #define reg_gio_r_pwm_in_lo___data___width 32 | ||
| 668 | #define reg_gio_r_pwm_in_lo_offset 232 | ||
| 669 | |||
| 670 | /* Register r_pwm_in_hi, scope gio, type r */ | ||
| 671 | #define reg_gio_r_pwm_in_hi___data___lsb 0 | ||
| 672 | #define reg_gio_r_pwm_in_hi___data___width 32 | ||
| 673 | #define reg_gio_r_pwm_in_hi_offset 236 | ||
| 674 | |||
| 675 | /* Register r_pwm_in_cnt, scope gio, type r */ | ||
| 676 | #define reg_gio_r_pwm_in_cnt___data___lsb 0 | ||
| 677 | #define reg_gio_r_pwm_in_cnt___data___width 32 | ||
| 678 | #define reg_gio_r_pwm_in_cnt_offset 240 | ||
| 679 | |||
| 680 | |||
| 681 | /* Constants */ | ||
| 682 | #define regk_gio_anyedge 0x00000007 | ||
| 683 | #define regk_gio_f100k 0x00000000 | ||
| 684 | #define regk_gio_f1562 0x00000000 | ||
| 685 | #define regk_gio_f195 0x00000003 | ||
| 686 | #define regk_gio_f1m 0x00000002 | ||
| 687 | #define regk_gio_f390 0x00000002 | ||
| 688 | #define regk_gio_f400k 0x00000001 | ||
| 689 | #define regk_gio_f5m 0x00000003 | ||
| 690 | #define regk_gio_f781 0x00000001 | ||
| 691 | #define regk_gio_hi 0x00000001 | ||
| 692 | #define regk_gio_in 0x00000000 | ||
| 693 | #define regk_gio_intr_pa0 0x00000000 | ||
| 694 | #define regk_gio_intr_pa1 0x00000000 | ||
| 695 | #define regk_gio_intr_pa10 0x00000001 | ||
| 696 | #define regk_gio_intr_pa11 0x00000001 | ||
| 697 | #define regk_gio_intr_pa12 0x00000001 | ||
| 698 | #define regk_gio_intr_pa13 0x00000001 | ||
| 699 | #define regk_gio_intr_pa14 0x00000001 | ||
| 700 | #define regk_gio_intr_pa15 0x00000001 | ||
| 701 | #define regk_gio_intr_pa16 0x00000002 | ||
| 702 | #define regk_gio_intr_pa17 0x00000002 | ||
| 703 | #define regk_gio_intr_pa18 0x00000002 | ||
| 704 | #define regk_gio_intr_pa19 0x00000002 | ||
| 705 | #define regk_gio_intr_pa2 0x00000000 | ||
| 706 | #define regk_gio_intr_pa20 0x00000002 | ||
| 707 | #define regk_gio_intr_pa21 0x00000002 | ||
| 708 | #define regk_gio_intr_pa22 0x00000002 | ||
| 709 | #define regk_gio_intr_pa23 0x00000002 | ||
| 710 | #define regk_gio_intr_pa24 0x00000003 | ||
| 711 | #define regk_gio_intr_pa25 0x00000003 | ||
| 712 | #define regk_gio_intr_pa26 0x00000003 | ||
| 713 | #define regk_gio_intr_pa27 0x00000003 | ||
| 714 | #define regk_gio_intr_pa28 0x00000003 | ||
| 715 | #define regk_gio_intr_pa29 0x00000003 | ||
| 716 | #define regk_gio_intr_pa3 0x00000000 | ||
| 717 | #define regk_gio_intr_pa30 0x00000003 | ||
| 718 | #define regk_gio_intr_pa31 0x00000003 | ||
| 719 | #define regk_gio_intr_pa4 0x00000000 | ||
| 720 | #define regk_gio_intr_pa5 0x00000000 | ||
| 721 | #define regk_gio_intr_pa6 0x00000000 | ||
| 722 | #define regk_gio_intr_pa7 0x00000000 | ||
| 723 | #define regk_gio_intr_pa8 0x00000001 | ||
| 724 | #define regk_gio_intr_pa9 0x00000001 | ||
| 725 | #define regk_gio_intr_pb0 0x00000004 | ||
| 726 | #define regk_gio_intr_pb1 0x00000004 | ||
| 727 | #define regk_gio_intr_pb10 0x00000005 | ||
| 728 | #define regk_gio_intr_pb11 0x00000005 | ||
| 729 | #define regk_gio_intr_pb12 0x00000005 | ||
| 730 | #define regk_gio_intr_pb13 0x00000005 | ||
| 731 | #define regk_gio_intr_pb14 0x00000005 | ||
| 732 | #define regk_gio_intr_pb15 0x00000005 | ||
| 733 | #define regk_gio_intr_pb16 0x00000006 | ||
| 734 | #define regk_gio_intr_pb17 0x00000006 | ||
| 735 | #define regk_gio_intr_pb18 0x00000006 | ||
| 736 | #define regk_gio_intr_pb19 0x00000006 | ||
| 737 | #define regk_gio_intr_pb2 0x00000004 | ||
| 738 | #define regk_gio_intr_pb20 0x00000006 | ||
| 739 | #define regk_gio_intr_pb21 0x00000006 | ||
| 740 | #define regk_gio_intr_pb22 0x00000006 | ||
| 741 | #define regk_gio_intr_pb23 0x00000006 | ||
| 742 | #define regk_gio_intr_pb24 0x00000007 | ||
| 743 | #define regk_gio_intr_pb25 0x00000007 | ||
| 744 | #define regk_gio_intr_pb26 0x00000007 | ||
| 745 | #define regk_gio_intr_pb27 0x00000007 | ||
| 746 | #define regk_gio_intr_pb28 0x00000007 | ||
| 747 | #define regk_gio_intr_pb29 0x00000007 | ||
| 748 | #define regk_gio_intr_pb3 0x00000004 | ||
| 749 | #define regk_gio_intr_pb30 0x00000007 | ||
| 750 | #define regk_gio_intr_pb31 0x00000007 | ||
| 751 | #define regk_gio_intr_pb4 0x00000004 | ||
| 752 | #define regk_gio_intr_pb5 0x00000004 | ||
| 753 | #define regk_gio_intr_pb6 0x00000004 | ||
| 754 | #define regk_gio_intr_pb7 0x00000004 | ||
| 755 | #define regk_gio_intr_pb8 0x00000005 | ||
| 756 | #define regk_gio_intr_pb9 0x00000005 | ||
| 757 | #define regk_gio_intr_pc0 0x00000008 | ||
| 758 | #define regk_gio_intr_pc1 0x00000008 | ||
| 759 | #define regk_gio_intr_pc10 0x00000009 | ||
| 760 | #define regk_gio_intr_pc11 0x00000009 | ||
| 761 | #define regk_gio_intr_pc12 0x00000009 | ||
| 762 | #define regk_gio_intr_pc13 0x00000009 | ||
| 763 | #define regk_gio_intr_pc14 0x00000009 | ||
| 764 | #define regk_gio_intr_pc15 0x00000009 | ||
| 765 | #define regk_gio_intr_pc2 0x00000008 | ||
| 766 | #define regk_gio_intr_pc3 0x00000008 | ||
| 767 | #define regk_gio_intr_pc4 0x00000008 | ||
| 768 | #define regk_gio_intr_pc5 0x00000008 | ||
| 769 | #define regk_gio_intr_pc6 0x00000008 | ||
| 770 | #define regk_gio_intr_pc7 0x00000008 | ||
| 771 | #define regk_gio_intr_pc8 0x00000009 | ||
| 772 | #define regk_gio_intr_pc9 0x00000009 | ||
| 773 | #define regk_gio_intr_pd0 0x0000000c | ||
| 774 | #define regk_gio_intr_pd1 0x0000000c | ||
| 775 | #define regk_gio_intr_pd10 0x0000000d | ||
| 776 | #define regk_gio_intr_pd11 0x0000000d | ||
| 777 | #define regk_gio_intr_pd12 0x0000000d | ||
| 778 | #define regk_gio_intr_pd13 0x0000000d | ||
| 779 | #define regk_gio_intr_pd14 0x0000000d | ||
| 780 | #define regk_gio_intr_pd15 0x0000000d | ||
| 781 | #define regk_gio_intr_pd16 0x0000000e | ||
| 782 | #define regk_gio_intr_pd17 0x0000000e | ||
| 783 | #define regk_gio_intr_pd18 0x0000000e | ||
| 784 | #define regk_gio_intr_pd19 0x0000000e | ||
| 785 | #define regk_gio_intr_pd2 0x0000000c | ||
| 786 | #define regk_gio_intr_pd20 0x0000000e | ||
| 787 | #define regk_gio_intr_pd21 0x0000000e | ||
| 788 | #define regk_gio_intr_pd22 0x0000000e | ||
| 789 | #define regk_gio_intr_pd23 0x0000000e | ||
| 790 | #define regk_gio_intr_pd24 0x0000000f | ||
| 791 | #define regk_gio_intr_pd25 0x0000000f | ||
| 792 | #define regk_gio_intr_pd26 0x0000000f | ||
| 793 | #define regk_gio_intr_pd27 0x0000000f | ||
| 794 | #define regk_gio_intr_pd28 0x0000000f | ||
| 795 | #define regk_gio_intr_pd29 0x0000000f | ||
| 796 | #define regk_gio_intr_pd3 0x0000000c | ||
| 797 | #define regk_gio_intr_pd30 0x0000000f | ||
| 798 | #define regk_gio_intr_pd31 0x0000000f | ||
| 799 | #define regk_gio_intr_pd4 0x0000000c | ||
| 800 | #define regk_gio_intr_pd5 0x0000000c | ||
| 801 | #define regk_gio_intr_pd6 0x0000000c | ||
| 802 | #define regk_gio_intr_pd7 0x0000000c | ||
| 803 | #define regk_gio_intr_pd8 0x0000000d | ||
| 804 | #define regk_gio_intr_pd9 0x0000000d | ||
| 805 | #define regk_gio_lo 0x00000002 | ||
| 806 | #define regk_gio_lsb 0x00000000 | ||
| 807 | #define regk_gio_msb 0x00000001 | ||
| 808 | #define regk_gio_negedge 0x00000006 | ||
| 809 | #define regk_gio_no 0x00000000 | ||
| 810 | #define regk_gio_no_switch 0x0000003f | ||
| 811 | #define regk_gio_none 0x00000007 | ||
| 812 | #define regk_gio_off 0x00000000 | ||
| 813 | #define regk_gio_opendrain 0x00000000 | ||
| 814 | #define regk_gio_out 0x00000001 | ||
| 815 | #define regk_gio_posedge 0x00000005 | ||
| 816 | #define regk_gio_pwm_hfp 0x00000002 | ||
| 817 | #define regk_gio_pwm_pa0 0x00000001 | ||
| 818 | #define regk_gio_pwm_pa19 0x00000004 | ||
| 819 | #define regk_gio_pwm_pa6 0x00000002 | ||
| 820 | #define regk_gio_pwm_pa7 0x00000003 | ||
| 821 | #define regk_gio_pwm_pb26 0x00000005 | ||
| 822 | #define regk_gio_pwm_pd23 0x00000006 | ||
| 823 | #define regk_gio_pwm_pd31 0x00000007 | ||
| 824 | #define regk_gio_pwm_std 0x00000001 | ||
| 825 | #define regk_gio_pwm_var 0x00000003 | ||
| 826 | #define regk_gio_rw_i2c0_cfg_default 0x00000020 | ||
| 827 | #define regk_gio_rw_i2c0_ctrl_default 0x00010000 | ||
| 828 | #define regk_gio_rw_i2c0_start_default 0x00000000 | ||
| 829 | #define regk_gio_rw_i2c1_cfg_default 0x00000aa0 | ||
| 830 | #define regk_gio_rw_i2c1_ctrl_default 0x00010000 | ||
| 831 | #define regk_gio_rw_i2c1_start_default 0x00000000 | ||
| 832 | #define regk_gio_rw_intr_cfg_default 0x00000000 | ||
| 833 | #define regk_gio_rw_intr_mask_default 0x00000000 | ||
| 834 | #define regk_gio_rw_pa_oe_default 0x00000000 | ||
| 835 | #define regk_gio_rw_pb_oe_default 0x00000000 | ||
| 836 | #define regk_gio_rw_pc_oe_default 0x00000000 | ||
| 837 | #define regk_gio_rw_ppwm_data_default 0x00000000 | ||
| 838 | #define regk_gio_rw_pwm0_ctrl_default 0x00000000 | ||
| 839 | #define regk_gio_rw_pwm1_ctrl_default 0x00000000 | ||
| 840 | #define regk_gio_rw_pwm2_ctrl_default 0x00000000 | ||
| 841 | #define regk_gio_rw_pwm_in_cfg_default 0x00000000 | ||
| 842 | #define regk_gio_sda0 0x00000000 | ||
| 843 | #define regk_gio_sda1 0x00000001 | ||
| 844 | #define regk_gio_sda2 0x00000002 | ||
| 845 | #define regk_gio_sda3 0x00000003 | ||
| 846 | #define regk_gio_sen 0x00000000 | ||
| 847 | #define regk_gio_set 0x00000003 | ||
| 848 | #define regk_gio_yes 0x00000001 | ||
| 849 | #endif /* __gio_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h new file mode 100644 index 000000000000..c3dc9c666c46 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pinmux_defs_asm.h | |||
| @@ -0,0 +1,572 @@ | |||
| 1 | #ifndef __pinmux_defs_asm_h | ||
| 2 | #define __pinmux_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: pinmux.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_hwprot, scope pinmux, type rw */ | ||
| 54 | #define reg_pinmux_rw_hwprot___eth___lsb 0 | ||
| 55 | #define reg_pinmux_rw_hwprot___eth___width 1 | ||
| 56 | #define reg_pinmux_rw_hwprot___eth___bit 0 | ||
| 57 | #define reg_pinmux_rw_hwprot___eth_mdio___lsb 1 | ||
| 58 | #define reg_pinmux_rw_hwprot___eth_mdio___width 1 | ||
| 59 | #define reg_pinmux_rw_hwprot___eth_mdio___bit 1 | ||
| 60 | #define reg_pinmux_rw_hwprot___geth___lsb 2 | ||
| 61 | #define reg_pinmux_rw_hwprot___geth___width 1 | ||
| 62 | #define reg_pinmux_rw_hwprot___geth___bit 2 | ||
| 63 | #define reg_pinmux_rw_hwprot___tg___lsb 3 | ||
| 64 | #define reg_pinmux_rw_hwprot___tg___width 1 | ||
| 65 | #define reg_pinmux_rw_hwprot___tg___bit 3 | ||
| 66 | #define reg_pinmux_rw_hwprot___tg_clk___lsb 4 | ||
| 67 | #define reg_pinmux_rw_hwprot___tg_clk___width 1 | ||
| 68 | #define reg_pinmux_rw_hwprot___tg_clk___bit 4 | ||
| 69 | #define reg_pinmux_rw_hwprot___vout___lsb 5 | ||
| 70 | #define reg_pinmux_rw_hwprot___vout___width 1 | ||
| 71 | #define reg_pinmux_rw_hwprot___vout___bit 5 | ||
| 72 | #define reg_pinmux_rw_hwprot___vout_sync___lsb 6 | ||
| 73 | #define reg_pinmux_rw_hwprot___vout_sync___width 1 | ||
| 74 | #define reg_pinmux_rw_hwprot___vout_sync___bit 6 | ||
| 75 | #define reg_pinmux_rw_hwprot___ser1___lsb 7 | ||
| 76 | #define reg_pinmux_rw_hwprot___ser1___width 1 | ||
| 77 | #define reg_pinmux_rw_hwprot___ser1___bit 7 | ||
| 78 | #define reg_pinmux_rw_hwprot___ser2___lsb 8 | ||
| 79 | #define reg_pinmux_rw_hwprot___ser2___width 1 | ||
| 80 | #define reg_pinmux_rw_hwprot___ser2___bit 8 | ||
| 81 | #define reg_pinmux_rw_hwprot___ser3___lsb 9 | ||
| 82 | #define reg_pinmux_rw_hwprot___ser3___width 1 | ||
| 83 | #define reg_pinmux_rw_hwprot___ser3___bit 9 | ||
| 84 | #define reg_pinmux_rw_hwprot___ser4___lsb 10 | ||
| 85 | #define reg_pinmux_rw_hwprot___ser4___width 1 | ||
| 86 | #define reg_pinmux_rw_hwprot___ser4___bit 10 | ||
| 87 | #define reg_pinmux_rw_hwprot___sser___lsb 11 | ||
| 88 | #define reg_pinmux_rw_hwprot___sser___width 1 | ||
| 89 | #define reg_pinmux_rw_hwprot___sser___bit 11 | ||
| 90 | #define reg_pinmux_rw_hwprot___pwm0___lsb 12 | ||
| 91 | #define reg_pinmux_rw_hwprot___pwm0___width 1 | ||
| 92 | #define reg_pinmux_rw_hwprot___pwm0___bit 12 | ||
| 93 | #define reg_pinmux_rw_hwprot___pwm1___lsb 13 | ||
| 94 | #define reg_pinmux_rw_hwprot___pwm1___width 1 | ||
| 95 | #define reg_pinmux_rw_hwprot___pwm1___bit 13 | ||
| 96 | #define reg_pinmux_rw_hwprot___pwm2___lsb 14 | ||
| 97 | #define reg_pinmux_rw_hwprot___pwm2___width 1 | ||
| 98 | #define reg_pinmux_rw_hwprot___pwm2___bit 14 | ||
| 99 | #define reg_pinmux_rw_hwprot___timer0___lsb 15 | ||
| 100 | #define reg_pinmux_rw_hwprot___timer0___width 1 | ||
| 101 | #define reg_pinmux_rw_hwprot___timer0___bit 15 | ||
| 102 | #define reg_pinmux_rw_hwprot___timer1___lsb 16 | ||
| 103 | #define reg_pinmux_rw_hwprot___timer1___width 1 | ||
| 104 | #define reg_pinmux_rw_hwprot___timer1___bit 16 | ||
| 105 | #define reg_pinmux_rw_hwprot___pio___lsb 17 | ||
| 106 | #define reg_pinmux_rw_hwprot___pio___width 1 | ||
| 107 | #define reg_pinmux_rw_hwprot___pio___bit 17 | ||
| 108 | #define reg_pinmux_rw_hwprot___i2c0___lsb 18 | ||
| 109 | #define reg_pinmux_rw_hwprot___i2c0___width 1 | ||
| 110 | #define reg_pinmux_rw_hwprot___i2c0___bit 18 | ||
| 111 | #define reg_pinmux_rw_hwprot___i2c1___lsb 19 | ||
| 112 | #define reg_pinmux_rw_hwprot___i2c1___width 1 | ||
| 113 | #define reg_pinmux_rw_hwprot___i2c1___bit 19 | ||
| 114 | #define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20 | ||
| 115 | #define reg_pinmux_rw_hwprot___i2c1_sda1___width 1 | ||
| 116 | #define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20 | ||
| 117 | #define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21 | ||
| 118 | #define reg_pinmux_rw_hwprot___i2c1_sda2___width 1 | ||
| 119 | #define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21 | ||
| 120 | #define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22 | ||
| 121 | #define reg_pinmux_rw_hwprot___i2c1_sda3___width 1 | ||
| 122 | #define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22 | ||
| 123 | #define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23 | ||
| 124 | #define reg_pinmux_rw_hwprot___i2c1_sen___width 1 | ||
| 125 | #define reg_pinmux_rw_hwprot___i2c1_sen___bit 23 | ||
| 126 | #define reg_pinmux_rw_hwprot_offset 0 | ||
| 127 | |||
| 128 | /* Register rw_gio_pa, scope pinmux, type rw */ | ||
| 129 | #define reg_pinmux_rw_gio_pa___pa0___lsb 0 | ||
| 130 | #define reg_pinmux_rw_gio_pa___pa0___width 1 | ||
| 131 | #define reg_pinmux_rw_gio_pa___pa0___bit 0 | ||
| 132 | #define reg_pinmux_rw_gio_pa___pa1___lsb 1 | ||
| 133 | #define reg_pinmux_rw_gio_pa___pa1___width 1 | ||
| 134 | #define reg_pinmux_rw_gio_pa___pa1___bit 1 | ||
| 135 | #define reg_pinmux_rw_gio_pa___pa2___lsb 2 | ||
| 136 | #define reg_pinmux_rw_gio_pa___pa2___width 1 | ||
| 137 | #define reg_pinmux_rw_gio_pa___pa2___bit 2 | ||
| 138 | #define reg_pinmux_rw_gio_pa___pa3___lsb 3 | ||
| 139 | #define reg_pinmux_rw_gio_pa___pa3___width 1 | ||
| 140 | #define reg_pinmux_rw_gio_pa___pa3___bit 3 | ||
| 141 | #define reg_pinmux_rw_gio_pa___pa4___lsb 4 | ||
| 142 | #define reg_pinmux_rw_gio_pa___pa4___width 1 | ||
| 143 | #define reg_pinmux_rw_gio_pa___pa4___bit 4 | ||
| 144 | #define reg_pinmux_rw_gio_pa___pa5___lsb 5 | ||
| 145 | #define reg_pinmux_rw_gio_pa___pa5___width 1 | ||
| 146 | #define reg_pinmux_rw_gio_pa___pa5___bit 5 | ||
| 147 | #define reg_pinmux_rw_gio_pa___pa6___lsb 6 | ||
| 148 | #define reg_pinmux_rw_gio_pa___pa6___width 1 | ||
| 149 | #define reg_pinmux_rw_gio_pa___pa6___bit 6 | ||
| 150 | #define reg_pinmux_rw_gio_pa___pa7___lsb 7 | ||
| 151 | #define reg_pinmux_rw_gio_pa___pa7___width 1 | ||
| 152 | #define reg_pinmux_rw_gio_pa___pa7___bit 7 | ||
| 153 | #define reg_pinmux_rw_gio_pa___pa8___lsb 8 | ||
| 154 | #define reg_pinmux_rw_gio_pa___pa8___width 1 | ||
| 155 | #define reg_pinmux_rw_gio_pa___pa8___bit 8 | ||
| 156 | #define reg_pinmux_rw_gio_pa___pa9___lsb 9 | ||
| 157 | #define reg_pinmux_rw_gio_pa___pa9___width 1 | ||
| 158 | #define reg_pinmux_rw_gio_pa___pa9___bit 9 | ||
| 159 | #define reg_pinmux_rw_gio_pa___pa10___lsb 10 | ||
| 160 | #define reg_pinmux_rw_gio_pa___pa10___width 1 | ||
| 161 | #define reg_pinmux_rw_gio_pa___pa10___bit 10 | ||
| 162 | #define reg_pinmux_rw_gio_pa___pa11___lsb 11 | ||
| 163 | #define reg_pinmux_rw_gio_pa___pa11___width 1 | ||
| 164 | #define reg_pinmux_rw_gio_pa___pa11___bit 11 | ||
| 165 | #define reg_pinmux_rw_gio_pa___pa12___lsb 12 | ||
| 166 | #define reg_pinmux_rw_gio_pa___pa12___width 1 | ||
| 167 | #define reg_pinmux_rw_gio_pa___pa12___bit 12 | ||
| 168 | #define reg_pinmux_rw_gio_pa___pa13___lsb 13 | ||
| 169 | #define reg_pinmux_rw_gio_pa___pa13___width 1 | ||
| 170 | #define reg_pinmux_rw_gio_pa___pa13___bit 13 | ||
| 171 | #define reg_pinmux_rw_gio_pa___pa14___lsb 14 | ||
| 172 | #define reg_pinmux_rw_gio_pa___pa14___width 1 | ||
| 173 | #define reg_pinmux_rw_gio_pa___pa14___bit 14 | ||
| 174 | #define reg_pinmux_rw_gio_pa___pa15___lsb 15 | ||
| 175 | #define reg_pinmux_rw_gio_pa___pa15___width 1 | ||
| 176 | #define reg_pinmux_rw_gio_pa___pa15___bit 15 | ||
| 177 | #define reg_pinmux_rw_gio_pa___pa16___lsb 16 | ||
| 178 | #define reg_pinmux_rw_gio_pa___pa16___width 1 | ||
| 179 | #define reg_pinmux_rw_gio_pa___pa16___bit 16 | ||
| 180 | #define reg_pinmux_rw_gio_pa___pa17___lsb 17 | ||
| 181 | #define reg_pinmux_rw_gio_pa___pa17___width 1 | ||
| 182 | #define reg_pinmux_rw_gio_pa___pa17___bit 17 | ||
| 183 | #define reg_pinmux_rw_gio_pa___pa18___lsb 18 | ||
| 184 | #define reg_pinmux_rw_gio_pa___pa18___width 1 | ||
| 185 | #define reg_pinmux_rw_gio_pa___pa18___bit 18 | ||
| 186 | #define reg_pinmux_rw_gio_pa___pa19___lsb 19 | ||
| 187 | #define reg_pinmux_rw_gio_pa___pa19___width 1 | ||
| 188 | #define reg_pinmux_rw_gio_pa___pa19___bit 19 | ||
| 189 | #define reg_pinmux_rw_gio_pa___pa20___lsb 20 | ||
| 190 | #define reg_pinmux_rw_gio_pa___pa20___width 1 | ||
| 191 | #define reg_pinmux_rw_gio_pa___pa20___bit 20 | ||
| 192 | #define reg_pinmux_rw_gio_pa___pa21___lsb 21 | ||
| 193 | #define reg_pinmux_rw_gio_pa___pa21___width 1 | ||
| 194 | #define reg_pinmux_rw_gio_pa___pa21___bit 21 | ||
| 195 | #define reg_pinmux_rw_gio_pa___pa22___lsb 22 | ||
| 196 | #define reg_pinmux_rw_gio_pa___pa22___width 1 | ||
| 197 | #define reg_pinmux_rw_gio_pa___pa22___bit 22 | ||
| 198 | #define reg_pinmux_rw_gio_pa___pa23___lsb 23 | ||
| 199 | #define reg_pinmux_rw_gio_pa___pa23___width 1 | ||
| 200 | #define reg_pinmux_rw_gio_pa___pa23___bit 23 | ||
| 201 | #define reg_pinmux_rw_gio_pa___pa24___lsb 24 | ||
| 202 | #define reg_pinmux_rw_gio_pa___pa24___width 1 | ||
| 203 | #define reg_pinmux_rw_gio_pa___pa24___bit 24 | ||
| 204 | #define reg_pinmux_rw_gio_pa___pa25___lsb 25 | ||
| 205 | #define reg_pinmux_rw_gio_pa___pa25___width 1 | ||
| 206 | #define reg_pinmux_rw_gio_pa___pa25___bit 25 | ||
| 207 | #define reg_pinmux_rw_gio_pa___pa26___lsb 26 | ||
| 208 | #define reg_pinmux_rw_gio_pa___pa26___width 1 | ||
| 209 | #define reg_pinmux_rw_gio_pa___pa26___bit 26 | ||
| 210 | #define reg_pinmux_rw_gio_pa___pa27___lsb 27 | ||
| 211 | #define reg_pinmux_rw_gio_pa___pa27___width 1 | ||
| 212 | #define reg_pinmux_rw_gio_pa___pa27___bit 27 | ||
| 213 | #define reg_pinmux_rw_gio_pa___pa28___lsb 28 | ||
| 214 | #define reg_pinmux_rw_gio_pa___pa28___width 1 | ||
| 215 | #define reg_pinmux_rw_gio_pa___pa28___bit 28 | ||
| 216 | #define reg_pinmux_rw_gio_pa___pa29___lsb 29 | ||
| 217 | #define reg_pinmux_rw_gio_pa___pa29___width 1 | ||
| 218 | #define reg_pinmux_rw_gio_pa___pa29___bit 29 | ||
| 219 | #define reg_pinmux_rw_gio_pa___pa30___lsb 30 | ||
| 220 | #define reg_pinmux_rw_gio_pa___pa30___width 1 | ||
| 221 | #define reg_pinmux_rw_gio_pa___pa30___bit 30 | ||
| 222 | #define reg_pinmux_rw_gio_pa___pa31___lsb 31 | ||
| 223 | #define reg_pinmux_rw_gio_pa___pa31___width 1 | ||
| 224 | #define reg_pinmux_rw_gio_pa___pa31___bit 31 | ||
| 225 | #define reg_pinmux_rw_gio_pa_offset 4 | ||
| 226 | |||
| 227 | /* Register rw_gio_pb, scope pinmux, type rw */ | ||
| 228 | #define reg_pinmux_rw_gio_pb___pb0___lsb 0 | ||
| 229 | #define reg_pinmux_rw_gio_pb___pb0___width 1 | ||
| 230 | #define reg_pinmux_rw_gio_pb___pb0___bit 0 | ||
| 231 | #define reg_pinmux_rw_gio_pb___pb1___lsb 1 | ||
| 232 | #define reg_pinmux_rw_gio_pb___pb1___width 1 | ||
| 233 | #define reg_pinmux_rw_gio_pb___pb1___bit 1 | ||
| 234 | #define reg_pinmux_rw_gio_pb___pb2___lsb 2 | ||
| 235 | #define reg_pinmux_rw_gio_pb___pb2___width 1 | ||
| 236 | #define reg_pinmux_rw_gio_pb___pb2___bit 2 | ||
| 237 | #define reg_pinmux_rw_gio_pb___pb3___lsb 3 | ||
| 238 | #define reg_pinmux_rw_gio_pb___pb3___width 1 | ||
| 239 | #define reg_pinmux_rw_gio_pb___pb3___bit 3 | ||
| 240 | #define reg_pinmux_rw_gio_pb___pb4___lsb 4 | ||
| 241 | #define reg_pinmux_rw_gio_pb___pb4___width 1 | ||
| 242 | #define reg_pinmux_rw_gio_pb___pb4___bit 4 | ||
| 243 | #define reg_pinmux_rw_gio_pb___pb5___lsb 5 | ||
| 244 | #define reg_pinmux_rw_gio_pb___pb5___width 1 | ||
| 245 | #define reg_pinmux_rw_gio_pb___pb5___bit 5 | ||
| 246 | #define reg_pinmux_rw_gio_pb___pb6___lsb 6 | ||
| 247 | #define reg_pinmux_rw_gio_pb___pb6___width 1 | ||
| 248 | #define reg_pinmux_rw_gio_pb___pb6___bit 6 | ||
| 249 | #define reg_pinmux_rw_gio_pb___pb7___lsb 7 | ||
| 250 | #define reg_pinmux_rw_gio_pb___pb7___width 1 | ||
| 251 | #define reg_pinmux_rw_gio_pb___pb7___bit 7 | ||
| 252 | #define reg_pinmux_rw_gio_pb___pb8___lsb 8 | ||
| 253 | #define reg_pinmux_rw_gio_pb___pb8___width 1 | ||
| 254 | #define reg_pinmux_rw_gio_pb___pb8___bit 8 | ||
| 255 | #define reg_pinmux_rw_gio_pb___pb9___lsb 9 | ||
| 256 | #define reg_pinmux_rw_gio_pb___pb9___width 1 | ||
| 257 | #define reg_pinmux_rw_gio_pb___pb9___bit 9 | ||
| 258 | #define reg_pinmux_rw_gio_pb___pb10___lsb 10 | ||
| 259 | #define reg_pinmux_rw_gio_pb___pb10___width 1 | ||
| 260 | #define reg_pinmux_rw_gio_pb___pb10___bit 10 | ||
| 261 | #define reg_pinmux_rw_gio_pb___pb11___lsb 11 | ||
| 262 | #define reg_pinmux_rw_gio_pb___pb11___width 1 | ||
| 263 | #define reg_pinmux_rw_gio_pb___pb11___bit 11 | ||
| 264 | #define reg_pinmux_rw_gio_pb___pb12___lsb 12 | ||
| 265 | #define reg_pinmux_rw_gio_pb___pb12___width 1 | ||
| 266 | #define reg_pinmux_rw_gio_pb___pb12___bit 12 | ||
| 267 | #define reg_pinmux_rw_gio_pb___pb13___lsb 13 | ||
| 268 | #define reg_pinmux_rw_gio_pb___pb13___width 1 | ||
| 269 | #define reg_pinmux_rw_gio_pb___pb13___bit 13 | ||
| 270 | #define reg_pinmux_rw_gio_pb___pb14___lsb 14 | ||
| 271 | #define reg_pinmux_rw_gio_pb___pb14___width 1 | ||
| 272 | #define reg_pinmux_rw_gio_pb___pb14___bit 14 | ||
| 273 | #define reg_pinmux_rw_gio_pb___pb15___lsb 15 | ||
| 274 | #define reg_pinmux_rw_gio_pb___pb15___width 1 | ||
| 275 | #define reg_pinmux_rw_gio_pb___pb15___bit 15 | ||
| 276 | #define reg_pinmux_rw_gio_pb___pb16___lsb 16 | ||
| 277 | #define reg_pinmux_rw_gio_pb___pb16___width 1 | ||
| 278 | #define reg_pinmux_rw_gio_pb___pb16___bit 16 | ||
| 279 | #define reg_pinmux_rw_gio_pb___pb17___lsb 17 | ||
| 280 | #define reg_pinmux_rw_gio_pb___pb17___width 1 | ||
| 281 | #define reg_pinmux_rw_gio_pb___pb17___bit 17 | ||
| 282 | #define reg_pinmux_rw_gio_pb___pb18___lsb 18 | ||
| 283 | #define reg_pinmux_rw_gio_pb___pb18___width 1 | ||
| 284 | #define reg_pinmux_rw_gio_pb___pb18___bit 18 | ||
| 285 | #define reg_pinmux_rw_gio_pb___pb19___lsb 19 | ||
| 286 | #define reg_pinmux_rw_gio_pb___pb19___width 1 | ||
| 287 | #define reg_pinmux_rw_gio_pb___pb19___bit 19 | ||
| 288 | #define reg_pinmux_rw_gio_pb___pb20___lsb 20 | ||
| 289 | #define reg_pinmux_rw_gio_pb___pb20___width 1 | ||
| 290 | #define reg_pinmux_rw_gio_pb___pb20___bit 20 | ||
| 291 | #define reg_pinmux_rw_gio_pb___pb21___lsb 21 | ||
| 292 | #define reg_pinmux_rw_gio_pb___pb21___width 1 | ||
| 293 | #define reg_pinmux_rw_gio_pb___pb21___bit 21 | ||
| 294 | #define reg_pinmux_rw_gio_pb___pb22___lsb 22 | ||
| 295 | #define reg_pinmux_rw_gio_pb___pb22___width 1 | ||
| 296 | #define reg_pinmux_rw_gio_pb___pb22___bit 22 | ||
| 297 | #define reg_pinmux_rw_gio_pb___pb23___lsb 23 | ||
| 298 | #define reg_pinmux_rw_gio_pb___pb23___width 1 | ||
| 299 | #define reg_pinmux_rw_gio_pb___pb23___bit 23 | ||
| 300 | #define reg_pinmux_rw_gio_pb___pb24___lsb 24 | ||
| 301 | #define reg_pinmux_rw_gio_pb___pb24___width 1 | ||
| 302 | #define reg_pinmux_rw_gio_pb___pb24___bit 24 | ||
| 303 | #define reg_pinmux_rw_gio_pb___pb25___lsb 25 | ||
| 304 | #define reg_pinmux_rw_gio_pb___pb25___width 1 | ||
| 305 | #define reg_pinmux_rw_gio_pb___pb25___bit 25 | ||
| 306 | #define reg_pinmux_rw_gio_pb___pb26___lsb 26 | ||
| 307 | #define reg_pinmux_rw_gio_pb___pb26___width 1 | ||
| 308 | #define reg_pinmux_rw_gio_pb___pb26___bit 26 | ||
| 309 | #define reg_pinmux_rw_gio_pb___pb27___lsb 27 | ||
| 310 | #define reg_pinmux_rw_gio_pb___pb27___width 1 | ||
| 311 | #define reg_pinmux_rw_gio_pb___pb27___bit 27 | ||
| 312 | #define reg_pinmux_rw_gio_pb___pb28___lsb 28 | ||
| 313 | #define reg_pinmux_rw_gio_pb___pb28___width 1 | ||
| 314 | #define reg_pinmux_rw_gio_pb___pb28___bit 28 | ||
| 315 | #define reg_pinmux_rw_gio_pb___pb29___lsb 29 | ||
| 316 | #define reg_pinmux_rw_gio_pb___pb29___width 1 | ||
| 317 | #define reg_pinmux_rw_gio_pb___pb29___bit 29 | ||
| 318 | #define reg_pinmux_rw_gio_pb___pb30___lsb 30 | ||
| 319 | #define reg_pinmux_rw_gio_pb___pb30___width 1 | ||
| 320 | #define reg_pinmux_rw_gio_pb___pb30___bit 30 | ||
| 321 | #define reg_pinmux_rw_gio_pb___pb31___lsb 31 | ||
| 322 | #define reg_pinmux_rw_gio_pb___pb31___width 1 | ||
| 323 | #define reg_pinmux_rw_gio_pb___pb31___bit 31 | ||
| 324 | #define reg_pinmux_rw_gio_pb_offset 8 | ||
| 325 | |||
| 326 | /* Register rw_gio_pc, scope pinmux, type rw */ | ||
| 327 | #define reg_pinmux_rw_gio_pc___pc0___lsb 0 | ||
| 328 | #define reg_pinmux_rw_gio_pc___pc0___width 1 | ||
| 329 | #define reg_pinmux_rw_gio_pc___pc0___bit 0 | ||
| 330 | #define reg_pinmux_rw_gio_pc___pc1___lsb 1 | ||
| 331 | #define reg_pinmux_rw_gio_pc___pc1___width 1 | ||
| 332 | #define reg_pinmux_rw_gio_pc___pc1___bit 1 | ||
| 333 | #define reg_pinmux_rw_gio_pc___pc2___lsb 2 | ||
| 334 | #define reg_pinmux_rw_gio_pc___pc2___width 1 | ||
| 335 | #define reg_pinmux_rw_gio_pc___pc2___bit 2 | ||
| 336 | #define reg_pinmux_rw_gio_pc___pc3___lsb 3 | ||
| 337 | #define reg_pinmux_rw_gio_pc___pc3___width 1 | ||
| 338 | #define reg_pinmux_rw_gio_pc___pc3___bit 3 | ||
| 339 | #define reg_pinmux_rw_gio_pc___pc4___lsb 4 | ||
| 340 | #define reg_pinmux_rw_gio_pc___pc4___width 1 | ||
| 341 | #define reg_pinmux_rw_gio_pc___pc4___bit 4 | ||
| 342 | #define reg_pinmux_rw_gio_pc___pc5___lsb 5 | ||
| 343 | #define reg_pinmux_rw_gio_pc___pc5___width 1 | ||
| 344 | #define reg_pinmux_rw_gio_pc___pc5___bit 5 | ||
| 345 | #define reg_pinmux_rw_gio_pc___pc6___lsb 6 | ||
| 346 | #define reg_pinmux_rw_gio_pc___pc6___width 1 | ||
| 347 | #define reg_pinmux_rw_gio_pc___pc6___bit 6 | ||
| 348 | #define reg_pinmux_rw_gio_pc___pc7___lsb 7 | ||
| 349 | #define reg_pinmux_rw_gio_pc___pc7___width 1 | ||
| 350 | #define reg_pinmux_rw_gio_pc___pc7___bit 7 | ||
| 351 | #define reg_pinmux_rw_gio_pc___pc8___lsb 8 | ||
| 352 | #define reg_pinmux_rw_gio_pc___pc8___width 1 | ||
| 353 | #define reg_pinmux_rw_gio_pc___pc8___bit 8 | ||
| 354 | #define reg_pinmux_rw_gio_pc___pc9___lsb 9 | ||
| 355 | #define reg_pinmux_rw_gio_pc___pc9___width 1 | ||
| 356 | #define reg_pinmux_rw_gio_pc___pc9___bit 9 | ||
| 357 | #define reg_pinmux_rw_gio_pc___pc10___lsb 10 | ||
| 358 | #define reg_pinmux_rw_gio_pc___pc10___width 1 | ||
| 359 | #define reg_pinmux_rw_gio_pc___pc10___bit 10 | ||
| 360 | #define reg_pinmux_rw_gio_pc___pc11___lsb 11 | ||
| 361 | #define reg_pinmux_rw_gio_pc___pc11___width 1 | ||
| 362 | #define reg_pinmux_rw_gio_pc___pc11___bit 11 | ||
| 363 | #define reg_pinmux_rw_gio_pc___pc12___lsb 12 | ||
| 364 | #define reg_pinmux_rw_gio_pc___pc12___width 1 | ||
| 365 | #define reg_pinmux_rw_gio_pc___pc12___bit 12 | ||
| 366 | #define reg_pinmux_rw_gio_pc___pc13___lsb 13 | ||
| 367 | #define reg_pinmux_rw_gio_pc___pc13___width 1 | ||
| 368 | #define reg_pinmux_rw_gio_pc___pc13___bit 13 | ||
| 369 | #define reg_pinmux_rw_gio_pc___pc14___lsb 14 | ||
| 370 | #define reg_pinmux_rw_gio_pc___pc14___width 1 | ||
| 371 | #define reg_pinmux_rw_gio_pc___pc14___bit 14 | ||
| 372 | #define reg_pinmux_rw_gio_pc___pc15___lsb 15 | ||
| 373 | #define reg_pinmux_rw_gio_pc___pc15___width 1 | ||
| 374 | #define reg_pinmux_rw_gio_pc___pc15___bit 15 | ||
| 375 | #define reg_pinmux_rw_gio_pc_offset 12 | ||
| 376 | |||
| 377 | /* Register rw_iop_pa, scope pinmux, type rw */ | ||
| 378 | #define reg_pinmux_rw_iop_pa___pa0___lsb 0 | ||
| 379 | #define reg_pinmux_rw_iop_pa___pa0___width 1 | ||
| 380 | #define reg_pinmux_rw_iop_pa___pa0___bit 0 | ||
| 381 | #define reg_pinmux_rw_iop_pa___pa1___lsb 1 | ||
| 382 | #define reg_pinmux_rw_iop_pa___pa1___width 1 | ||
| 383 | #define reg_pinmux_rw_iop_pa___pa1___bit 1 | ||
| 384 | #define reg_pinmux_rw_iop_pa___pa2___lsb 2 | ||
| 385 | #define reg_pinmux_rw_iop_pa___pa2___width 1 | ||
| 386 | #define reg_pinmux_rw_iop_pa___pa2___bit 2 | ||
| 387 | #define reg_pinmux_rw_iop_pa___pa3___lsb 3 | ||
| 388 | #define reg_pinmux_rw_iop_pa___pa3___width 1 | ||
| 389 | #define reg_pinmux_rw_iop_pa___pa3___bit 3 | ||
| 390 | #define reg_pinmux_rw_iop_pa___pa4___lsb 4 | ||
| 391 | #define reg_pinmux_rw_iop_pa___pa4___width 1 | ||
| 392 | #define reg_pinmux_rw_iop_pa___pa4___bit 4 | ||
| 393 | #define reg_pinmux_rw_iop_pa___pa5___lsb 5 | ||
| 394 | #define reg_pinmux_rw_iop_pa___pa5___width 1 | ||
| 395 | #define reg_pinmux_rw_iop_pa___pa5___bit 5 | ||
| 396 | #define reg_pinmux_rw_iop_pa___pa6___lsb 6 | ||
| 397 | #define reg_pinmux_rw_iop_pa___pa6___width 1 | ||
| 398 | #define reg_pinmux_rw_iop_pa___pa6___bit 6 | ||
| 399 | #define reg_pinmux_rw_iop_pa___pa7___lsb 7 | ||
| 400 | #define reg_pinmux_rw_iop_pa___pa7___width 1 | ||
| 401 | #define reg_pinmux_rw_iop_pa___pa7___bit 7 | ||
| 402 | #define reg_pinmux_rw_iop_pa___pa8___lsb 8 | ||
| 403 | #define reg_pinmux_rw_iop_pa___pa8___width 1 | ||
| 404 | #define reg_pinmux_rw_iop_pa___pa8___bit 8 | ||
| 405 | #define reg_pinmux_rw_iop_pa___pa9___lsb 9 | ||
| 406 | #define reg_pinmux_rw_iop_pa___pa9___width 1 | ||
| 407 | #define reg_pinmux_rw_iop_pa___pa9___bit 9 | ||
| 408 | #define reg_pinmux_rw_iop_pa___pa10___lsb 10 | ||
| 409 | #define reg_pinmux_rw_iop_pa___pa10___width 1 | ||
| 410 | #define reg_pinmux_rw_iop_pa___pa10___bit 10 | ||
| 411 | #define reg_pinmux_rw_iop_pa___pa11___lsb 11 | ||
| 412 | #define reg_pinmux_rw_iop_pa___pa11___width 1 | ||
| 413 | #define reg_pinmux_rw_iop_pa___pa11___bit 11 | ||
| 414 | #define reg_pinmux_rw_iop_pa___pa12___lsb 12 | ||
| 415 | #define reg_pinmux_rw_iop_pa___pa12___width 1 | ||
| 416 | #define reg_pinmux_rw_iop_pa___pa12___bit 12 | ||
| 417 | #define reg_pinmux_rw_iop_pa___pa13___lsb 13 | ||
| 418 | #define reg_pinmux_rw_iop_pa___pa13___width 1 | ||
| 419 | #define reg_pinmux_rw_iop_pa___pa13___bit 13 | ||
| 420 | #define reg_pinmux_rw_iop_pa___pa14___lsb 14 | ||
| 421 | #define reg_pinmux_rw_iop_pa___pa14___width 1 | ||
| 422 | #define reg_pinmux_rw_iop_pa___pa14___bit 14 | ||
| 423 | #define reg_pinmux_rw_iop_pa___pa15___lsb 15 | ||
| 424 | #define reg_pinmux_rw_iop_pa___pa15___width 1 | ||
| 425 | #define reg_pinmux_rw_iop_pa___pa15___bit 15 | ||
| 426 | #define reg_pinmux_rw_iop_pa___pa16___lsb 16 | ||
| 427 | #define reg_pinmux_rw_iop_pa___pa16___width 1 | ||
| 428 | #define reg_pinmux_rw_iop_pa___pa16___bit 16 | ||
| 429 | #define reg_pinmux_rw_iop_pa___pa17___lsb 17 | ||
| 430 | #define reg_pinmux_rw_iop_pa___pa17___width 1 | ||
| 431 | #define reg_pinmux_rw_iop_pa___pa17___bit 17 | ||
| 432 | #define reg_pinmux_rw_iop_pa___pa18___lsb 18 | ||
| 433 | #define reg_pinmux_rw_iop_pa___pa18___width 1 | ||
| 434 | #define reg_pinmux_rw_iop_pa___pa18___bit 18 | ||
| 435 | #define reg_pinmux_rw_iop_pa___pa19___lsb 19 | ||
| 436 | #define reg_pinmux_rw_iop_pa___pa19___width 1 | ||
| 437 | #define reg_pinmux_rw_iop_pa___pa19___bit 19 | ||
| 438 | #define reg_pinmux_rw_iop_pa___pa20___lsb 20 | ||
| 439 | #define reg_pinmux_rw_iop_pa___pa20___width 1 | ||
| 440 | #define reg_pinmux_rw_iop_pa___pa20___bit 20 | ||
| 441 | #define reg_pinmux_rw_iop_pa___pa21___lsb 21 | ||
| 442 | #define reg_pinmux_rw_iop_pa___pa21___width 1 | ||
| 443 | #define reg_pinmux_rw_iop_pa___pa21___bit 21 | ||
| 444 | #define reg_pinmux_rw_iop_pa___pa22___lsb 22 | ||
| 445 | #define reg_pinmux_rw_iop_pa___pa22___width 1 | ||
| 446 | #define reg_pinmux_rw_iop_pa___pa22___bit 22 | ||
| 447 | #define reg_pinmux_rw_iop_pa___pa23___lsb 23 | ||
| 448 | #define reg_pinmux_rw_iop_pa___pa23___width 1 | ||
| 449 | #define reg_pinmux_rw_iop_pa___pa23___bit 23 | ||
| 450 | #define reg_pinmux_rw_iop_pa___pa24___lsb 24 | ||
| 451 | #define reg_pinmux_rw_iop_pa___pa24___width 1 | ||
| 452 | #define reg_pinmux_rw_iop_pa___pa24___bit 24 | ||
| 453 | #define reg_pinmux_rw_iop_pa___pa25___lsb 25 | ||
| 454 | #define reg_pinmux_rw_iop_pa___pa25___width 1 | ||
| 455 | #define reg_pinmux_rw_iop_pa___pa25___bit 25 | ||
| 456 | #define reg_pinmux_rw_iop_pa___pa26___lsb 26 | ||
| 457 | #define reg_pinmux_rw_iop_pa___pa26___width 1 | ||
| 458 | #define reg_pinmux_rw_iop_pa___pa26___bit 26 | ||
| 459 | #define reg_pinmux_rw_iop_pa___pa27___lsb 27 | ||
| 460 | #define reg_pinmux_rw_iop_pa___pa27___width 1 | ||
| 461 | #define reg_pinmux_rw_iop_pa___pa27___bit 27 | ||
| 462 | #define reg_pinmux_rw_iop_pa___pa28___lsb 28 | ||
| 463 | #define reg_pinmux_rw_iop_pa___pa28___width 1 | ||
| 464 | #define reg_pinmux_rw_iop_pa___pa28___bit 28 | ||
| 465 | #define reg_pinmux_rw_iop_pa___pa29___lsb 29 | ||
| 466 | #define reg_pinmux_rw_iop_pa___pa29___width 1 | ||
| 467 | #define reg_pinmux_rw_iop_pa___pa29___bit 29 | ||
| 468 | #define reg_pinmux_rw_iop_pa___pa30___lsb 30 | ||
| 469 | #define reg_pinmux_rw_iop_pa___pa30___width 1 | ||
| 470 | #define reg_pinmux_rw_iop_pa___pa30___bit 30 | ||
| 471 | #define reg_pinmux_rw_iop_pa___pa31___lsb 31 | ||
| 472 | #define reg_pinmux_rw_iop_pa___pa31___width 1 | ||
| 473 | #define reg_pinmux_rw_iop_pa___pa31___bit 31 | ||
| 474 | #define reg_pinmux_rw_iop_pa_offset 16 | ||
| 475 | |||
| 476 | /* Register rw_iop_pb, scope pinmux, type rw */ | ||
| 477 | #define reg_pinmux_rw_iop_pb___pb0___lsb 0 | ||
| 478 | #define reg_pinmux_rw_iop_pb___pb0___width 1 | ||
| 479 | #define reg_pinmux_rw_iop_pb___pb0___bit 0 | ||
| 480 | #define reg_pinmux_rw_iop_pb___pb1___lsb 1 | ||
| 481 | #define reg_pinmux_rw_iop_pb___pb1___width 1 | ||
| 482 | #define reg_pinmux_rw_iop_pb___pb1___bit 1 | ||
| 483 | #define reg_pinmux_rw_iop_pb___pb2___lsb 2 | ||
| 484 | #define reg_pinmux_rw_iop_pb___pb2___width 1 | ||
| 485 | #define reg_pinmux_rw_iop_pb___pb2___bit 2 | ||
| 486 | #define reg_pinmux_rw_iop_pb___pb3___lsb 3 | ||
| 487 | #define reg_pinmux_rw_iop_pb___pb3___width 1 | ||
| 488 | #define reg_pinmux_rw_iop_pb___pb3___bit 3 | ||
| 489 | #define reg_pinmux_rw_iop_pb___pb4___lsb 4 | ||
| 490 | #define reg_pinmux_rw_iop_pb___pb4___width 1 | ||
| 491 | #define reg_pinmux_rw_iop_pb___pb4___bit 4 | ||
| 492 | #define reg_pinmux_rw_iop_pb___pb5___lsb 5 | ||
| 493 | #define reg_pinmux_rw_iop_pb___pb5___width 1 | ||
| 494 | #define reg_pinmux_rw_iop_pb___pb5___bit 5 | ||
| 495 | #define reg_pinmux_rw_iop_pb___pb6___lsb 6 | ||
| 496 | #define reg_pinmux_rw_iop_pb___pb6___width 1 | ||
| 497 | #define reg_pinmux_rw_iop_pb___pb6___bit 6 | ||
| 498 | #define reg_pinmux_rw_iop_pb___pb7___lsb 7 | ||
| 499 | #define reg_pinmux_rw_iop_pb___pb7___width 1 | ||
| 500 | #define reg_pinmux_rw_iop_pb___pb7___bit 7 | ||
| 501 | #define reg_pinmux_rw_iop_pb_offset 20 | ||
| 502 | |||
| 503 | /* Register rw_iop_pio, scope pinmux, type rw */ | ||
| 504 | #define reg_pinmux_rw_iop_pio___d0___lsb 0 | ||
| 505 | #define reg_pinmux_rw_iop_pio___d0___width 1 | ||
| 506 | #define reg_pinmux_rw_iop_pio___d0___bit 0 | ||
| 507 | #define reg_pinmux_rw_iop_pio___d1___lsb 1 | ||
| 508 | #define reg_pinmux_rw_iop_pio___d1___width 1 | ||
| 509 | #define reg_pinmux_rw_iop_pio___d1___bit 1 | ||
| 510 | #define reg_pinmux_rw_iop_pio___d2___lsb 2 | ||
| 511 | #define reg_pinmux_rw_iop_pio___d2___width 1 | ||
| 512 | #define reg_pinmux_rw_iop_pio___d2___bit 2 | ||
| 513 | #define reg_pinmux_rw_iop_pio___d3___lsb 3 | ||
| 514 | #define reg_pinmux_rw_iop_pio___d3___width 1 | ||
| 515 | #define reg_pinmux_rw_iop_pio___d3___bit 3 | ||
| 516 | #define reg_pinmux_rw_iop_pio___d4___lsb 4 | ||
| 517 | #define reg_pinmux_rw_iop_pio___d4___width 1 | ||
| 518 | #define reg_pinmux_rw_iop_pio___d4___bit 4 | ||
| 519 | #define reg_pinmux_rw_iop_pio___d5___lsb 5 | ||
| 520 | #define reg_pinmux_rw_iop_pio___d5___width 1 | ||
| 521 | #define reg_pinmux_rw_iop_pio___d5___bit 5 | ||
| 522 | #define reg_pinmux_rw_iop_pio___d6___lsb 6 | ||
| 523 | #define reg_pinmux_rw_iop_pio___d6___width 1 | ||
| 524 | #define reg_pinmux_rw_iop_pio___d6___bit 6 | ||
| 525 | #define reg_pinmux_rw_iop_pio___d7___lsb 7 | ||
| 526 | #define reg_pinmux_rw_iop_pio___d7___width 1 | ||
| 527 | #define reg_pinmux_rw_iop_pio___d7___bit 7 | ||
| 528 | #define reg_pinmux_rw_iop_pio___rd_n___lsb 8 | ||
| 529 | #define reg_pinmux_rw_iop_pio___rd_n___width 1 | ||
| 530 | #define reg_pinmux_rw_iop_pio___rd_n___bit 8 | ||
| 531 | #define reg_pinmux_rw_iop_pio___wr_n___lsb 9 | ||
| 532 | #define reg_pinmux_rw_iop_pio___wr_n___width 1 | ||
| 533 | #define reg_pinmux_rw_iop_pio___wr_n___bit 9 | ||
| 534 | #define reg_pinmux_rw_iop_pio___a0___lsb 10 | ||
| 535 | #define reg_pinmux_rw_iop_pio___a0___width 1 | ||
| 536 | #define reg_pinmux_rw_iop_pio___a0___bit 10 | ||
| 537 | #define reg_pinmux_rw_iop_pio___a1___lsb 11 | ||
| 538 | #define reg_pinmux_rw_iop_pio___a1___width 1 | ||
| 539 | #define reg_pinmux_rw_iop_pio___a1___bit 11 | ||
| 540 | #define reg_pinmux_rw_iop_pio___ce0_n___lsb 12 | ||
| 541 | #define reg_pinmux_rw_iop_pio___ce0_n___width 1 | ||
| 542 | #define reg_pinmux_rw_iop_pio___ce0_n___bit 12 | ||
| 543 | #define reg_pinmux_rw_iop_pio___ce1_n___lsb 13 | ||
| 544 | #define reg_pinmux_rw_iop_pio___ce1_n___width 1 | ||
| 545 | #define reg_pinmux_rw_iop_pio___ce1_n___bit 13 | ||
| 546 | #define reg_pinmux_rw_iop_pio___ce2_n___lsb 14 | ||
| 547 | #define reg_pinmux_rw_iop_pio___ce2_n___width 1 | ||
| 548 | #define reg_pinmux_rw_iop_pio___ce2_n___bit 14 | ||
| 549 | #define reg_pinmux_rw_iop_pio___rdy___lsb 15 | ||
| 550 | #define reg_pinmux_rw_iop_pio___rdy___width 1 | ||
| 551 | #define reg_pinmux_rw_iop_pio___rdy___bit 15 | ||
| 552 | #define reg_pinmux_rw_iop_pio_offset 24 | ||
| 553 | |||
| 554 | /* Register rw_iop_usb, scope pinmux, type rw */ | ||
| 555 | #define reg_pinmux_rw_iop_usb___usb0___lsb 0 | ||
| 556 | #define reg_pinmux_rw_iop_usb___usb0___width 1 | ||
| 557 | #define reg_pinmux_rw_iop_usb___usb0___bit 0 | ||
| 558 | #define reg_pinmux_rw_iop_usb_offset 28 | ||
| 559 | |||
| 560 | |||
| 561 | /* Constants */ | ||
| 562 | #define regk_pinmux_no 0x00000000 | ||
| 563 | #define regk_pinmux_rw_gio_pa_default 0x00000000 | ||
| 564 | #define regk_pinmux_rw_gio_pb_default 0x00000000 | ||
| 565 | #define regk_pinmux_rw_gio_pc_default 0x00000000 | ||
| 566 | #define regk_pinmux_rw_hwprot_default 0x00000000 | ||
| 567 | #define regk_pinmux_rw_iop_pa_default 0x00000000 | ||
| 568 | #define regk_pinmux_rw_iop_pb_default 0x00000000 | ||
| 569 | #define regk_pinmux_rw_iop_pio_default 0x00000000 | ||
| 570 | #define regk_pinmux_rw_iop_usb_default 0x00000001 | ||
| 571 | #define regk_pinmux_yes 0x00000001 | ||
| 572 | #endif /* __pinmux_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h new file mode 100644 index 000000000000..3907ef4921c8 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/pio_defs_asm.h | |||
| @@ -0,0 +1,337 @@ | |||
| 1 | #ifndef __pio_defs_asm_h | ||
| 2 | #define __pio_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: pio.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_data, scope pio, type rw */ | ||
| 54 | #define reg_pio_rw_data_offset 64 | ||
| 55 | |||
| 56 | /* Register rw_io_access0, scope pio, type rw */ | ||
| 57 | #define reg_pio_rw_io_access0___data___lsb 0 | ||
| 58 | #define reg_pio_rw_io_access0___data___width 8 | ||
| 59 | #define reg_pio_rw_io_access0_offset 0 | ||
| 60 | |||
| 61 | /* Register rw_io_access1, scope pio, type rw */ | ||
| 62 | #define reg_pio_rw_io_access1___data___lsb 0 | ||
| 63 | #define reg_pio_rw_io_access1___data___width 8 | ||
| 64 | #define reg_pio_rw_io_access1_offset 4 | ||
| 65 | |||
| 66 | /* Register rw_io_access2, scope pio, type rw */ | ||
| 67 | #define reg_pio_rw_io_access2___data___lsb 0 | ||
| 68 | #define reg_pio_rw_io_access2___data___width 8 | ||
| 69 | #define reg_pio_rw_io_access2_offset 8 | ||
| 70 | |||
| 71 | /* Register rw_io_access3, scope pio, type rw */ | ||
| 72 | #define reg_pio_rw_io_access3___data___lsb 0 | ||
| 73 | #define reg_pio_rw_io_access3___data___width 8 | ||
| 74 | #define reg_pio_rw_io_access3_offset 12 | ||
| 75 | |||
| 76 | /* Register rw_io_access4, scope pio, type rw */ | ||
| 77 | #define reg_pio_rw_io_access4___data___lsb 0 | ||
| 78 | #define reg_pio_rw_io_access4___data___width 8 | ||
| 79 | #define reg_pio_rw_io_access4_offset 16 | ||
| 80 | |||
| 81 | /* Register rw_io_access5, scope pio, type rw */ | ||
| 82 | #define reg_pio_rw_io_access5___data___lsb 0 | ||
| 83 | #define reg_pio_rw_io_access5___data___width 8 | ||
| 84 | #define reg_pio_rw_io_access5_offset 20 | ||
| 85 | |||
| 86 | /* Register rw_io_access6, scope pio, type rw */ | ||
| 87 | #define reg_pio_rw_io_access6___data___lsb 0 | ||
| 88 | #define reg_pio_rw_io_access6___data___width 8 | ||
| 89 | #define reg_pio_rw_io_access6_offset 24 | ||
| 90 | |||
| 91 | /* Register rw_io_access7, scope pio, type rw */ | ||
| 92 | #define reg_pio_rw_io_access7___data___lsb 0 | ||
| 93 | #define reg_pio_rw_io_access7___data___width 8 | ||
| 94 | #define reg_pio_rw_io_access7_offset 28 | ||
| 95 | |||
| 96 | /* Register rw_io_access8, scope pio, type rw */ | ||
| 97 | #define reg_pio_rw_io_access8___data___lsb 0 | ||
| 98 | #define reg_pio_rw_io_access8___data___width 8 | ||
| 99 | #define reg_pio_rw_io_access8_offset 32 | ||
| 100 | |||
| 101 | /* Register rw_io_access9, scope pio, type rw */ | ||
| 102 | #define reg_pio_rw_io_access9___data___lsb 0 | ||
| 103 | #define reg_pio_rw_io_access9___data___width 8 | ||
| 104 | #define reg_pio_rw_io_access9_offset 36 | ||
| 105 | |||
| 106 | /* Register rw_io_access10, scope pio, type rw */ | ||
| 107 | #define reg_pio_rw_io_access10___data___lsb 0 | ||
| 108 | #define reg_pio_rw_io_access10___data___width 8 | ||
| 109 | #define reg_pio_rw_io_access10_offset 40 | ||
| 110 | |||
| 111 | /* Register rw_io_access11, scope pio, type rw */ | ||
| 112 | #define reg_pio_rw_io_access11___data___lsb 0 | ||
| 113 | #define reg_pio_rw_io_access11___data___width 8 | ||
| 114 | #define reg_pio_rw_io_access11_offset 44 | ||
| 115 | |||
| 116 | /* Register rw_io_access12, scope pio, type rw */ | ||
| 117 | #define reg_pio_rw_io_access12___data___lsb 0 | ||
| 118 | #define reg_pio_rw_io_access12___data___width 8 | ||
| 119 | #define reg_pio_rw_io_access12_offset 48 | ||
| 120 | |||
| 121 | /* Register rw_io_access13, scope pio, type rw */ | ||
| 122 | #define reg_pio_rw_io_access13___data___lsb 0 | ||
| 123 | #define reg_pio_rw_io_access13___data___width 8 | ||
| 124 | #define reg_pio_rw_io_access13_offset 52 | ||
| 125 | |||
| 126 | /* Register rw_io_access14, scope pio, type rw */ | ||
| 127 | #define reg_pio_rw_io_access14___data___lsb 0 | ||
| 128 | #define reg_pio_rw_io_access14___data___width 8 | ||
| 129 | #define reg_pio_rw_io_access14_offset 56 | ||
| 130 | |||
| 131 | /* Register rw_io_access15, scope pio, type rw */ | ||
| 132 | #define reg_pio_rw_io_access15___data___lsb 0 | ||
| 133 | #define reg_pio_rw_io_access15___data___width 8 | ||
| 134 | #define reg_pio_rw_io_access15_offset 60 | ||
| 135 | |||
| 136 | /* Register rw_ce0_cfg, scope pio, type rw */ | ||
| 137 | #define reg_pio_rw_ce0_cfg___lw___lsb 0 | ||
| 138 | #define reg_pio_rw_ce0_cfg___lw___width 6 | ||
| 139 | #define reg_pio_rw_ce0_cfg___ew___lsb 6 | ||
| 140 | #define reg_pio_rw_ce0_cfg___ew___width 3 | ||
| 141 | #define reg_pio_rw_ce0_cfg___zw___lsb 9 | ||
| 142 | #define reg_pio_rw_ce0_cfg___zw___width 3 | ||
| 143 | #define reg_pio_rw_ce0_cfg___aw___lsb 12 | ||
| 144 | #define reg_pio_rw_ce0_cfg___aw___width 2 | ||
| 145 | #define reg_pio_rw_ce0_cfg___mode___lsb 14 | ||
| 146 | #define reg_pio_rw_ce0_cfg___mode___width 2 | ||
| 147 | #define reg_pio_rw_ce0_cfg_offset 68 | ||
| 148 | |||
| 149 | /* Register rw_ce1_cfg, scope pio, type rw */ | ||
| 150 | #define reg_pio_rw_ce1_cfg___lw___lsb 0 | ||
| 151 | #define reg_pio_rw_ce1_cfg___lw___width 6 | ||
| 152 | #define reg_pio_rw_ce1_cfg___ew___lsb 6 | ||
| 153 | #define reg_pio_rw_ce1_cfg___ew___width 3 | ||
| 154 | #define reg_pio_rw_ce1_cfg___zw___lsb 9 | ||
| 155 | #define reg_pio_rw_ce1_cfg___zw___width 3 | ||
| 156 | #define reg_pio_rw_ce1_cfg___aw___lsb 12 | ||
| 157 | #define reg_pio_rw_ce1_cfg___aw___width 2 | ||
| 158 | #define reg_pio_rw_ce1_cfg___mode___lsb 14 | ||
| 159 | #define reg_pio_rw_ce1_cfg___mode___width 2 | ||
| 160 | #define reg_pio_rw_ce1_cfg_offset 72 | ||
| 161 | |||
| 162 | /* Register rw_ce2_cfg, scope pio, type rw */ | ||
| 163 | #define reg_pio_rw_ce2_cfg___lw___lsb 0 | ||
| 164 | #define reg_pio_rw_ce2_cfg___lw___width 6 | ||
| 165 | #define reg_pio_rw_ce2_cfg___ew___lsb 6 | ||
| 166 | #define reg_pio_rw_ce2_cfg___ew___width 3 | ||
| 167 | #define reg_pio_rw_ce2_cfg___zw___lsb 9 | ||
| 168 | #define reg_pio_rw_ce2_cfg___zw___width 3 | ||
| 169 | #define reg_pio_rw_ce2_cfg___aw___lsb 12 | ||
| 170 | #define reg_pio_rw_ce2_cfg___aw___width 2 | ||
| 171 | #define reg_pio_rw_ce2_cfg___mode___lsb 14 | ||
| 172 | #define reg_pio_rw_ce2_cfg___mode___width 2 | ||
| 173 | #define reg_pio_rw_ce2_cfg_offset 76 | ||
| 174 | |||
| 175 | /* Register rw_dout, scope pio, type rw */ | ||
| 176 | #define reg_pio_rw_dout___data___lsb 0 | ||
| 177 | #define reg_pio_rw_dout___data___width 8 | ||
| 178 | #define reg_pio_rw_dout___rd_n___lsb 8 | ||
| 179 | #define reg_pio_rw_dout___rd_n___width 1 | ||
| 180 | #define reg_pio_rw_dout___rd_n___bit 8 | ||
| 181 | #define reg_pio_rw_dout___wr_n___lsb 9 | ||
| 182 | #define reg_pio_rw_dout___wr_n___width 1 | ||
| 183 | #define reg_pio_rw_dout___wr_n___bit 9 | ||
| 184 | #define reg_pio_rw_dout___a0___lsb 10 | ||
| 185 | #define reg_pio_rw_dout___a0___width 1 | ||
| 186 | #define reg_pio_rw_dout___a0___bit 10 | ||
| 187 | #define reg_pio_rw_dout___a1___lsb 11 | ||
| 188 | #define reg_pio_rw_dout___a1___width 1 | ||
| 189 | #define reg_pio_rw_dout___a1___bit 11 | ||
| 190 | #define reg_pio_rw_dout___ce0_n___lsb 12 | ||
| 191 | #define reg_pio_rw_dout___ce0_n___width 1 | ||
| 192 | #define reg_pio_rw_dout___ce0_n___bit 12 | ||
| 193 | #define reg_pio_rw_dout___ce1_n___lsb 13 | ||
| 194 | #define reg_pio_rw_dout___ce1_n___width 1 | ||
| 195 | #define reg_pio_rw_dout___ce1_n___bit 13 | ||
| 196 | #define reg_pio_rw_dout___ce2_n___lsb 14 | ||
| 197 | #define reg_pio_rw_dout___ce2_n___width 1 | ||
| 198 | #define reg_pio_rw_dout___ce2_n___bit 14 | ||
| 199 | #define reg_pio_rw_dout___rdy___lsb 15 | ||
| 200 | #define reg_pio_rw_dout___rdy___width 1 | ||
| 201 | #define reg_pio_rw_dout___rdy___bit 15 | ||
| 202 | #define reg_pio_rw_dout_offset 80 | ||
| 203 | |||
| 204 | /* Register rw_oe, scope pio, type rw */ | ||
| 205 | #define reg_pio_rw_oe___data___lsb 0 | ||
| 206 | #define reg_pio_rw_oe___data___width 8 | ||
| 207 | #define reg_pio_rw_oe___rd_n___lsb 8 | ||
| 208 | #define reg_pio_rw_oe___rd_n___width 1 | ||
| 209 | #define reg_pio_rw_oe___rd_n___bit 8 | ||
| 210 | #define reg_pio_rw_oe___wr_n___lsb 9 | ||
| 211 | #define reg_pio_rw_oe___wr_n___width 1 | ||
| 212 | #define reg_pio_rw_oe___wr_n___bit 9 | ||
| 213 | #define reg_pio_rw_oe___a0___lsb 10 | ||
| 214 | #define reg_pio_rw_oe___a0___width 1 | ||
| 215 | #define reg_pio_rw_oe___a0___bit 10 | ||
| 216 | #define reg_pio_rw_oe___a1___lsb 11 | ||
| 217 | #define reg_pio_rw_oe___a1___width 1 | ||
| 218 | #define reg_pio_rw_oe___a1___bit 11 | ||
| 219 | #define reg_pio_rw_oe___ce0_n___lsb 12 | ||
| 220 | #define reg_pio_rw_oe___ce0_n___width 1 | ||
| 221 | #define reg_pio_rw_oe___ce0_n___bit 12 | ||
| 222 | #define reg_pio_rw_oe___ce1_n___lsb 13 | ||
| 223 | #define reg_pio_rw_oe___ce1_n___width 1 | ||
| 224 | #define reg_pio_rw_oe___ce1_n___bit 13 | ||
| 225 | #define reg_pio_rw_oe___ce2_n___lsb 14 | ||
| 226 | #define reg_pio_rw_oe___ce2_n___width 1 | ||
| 227 | #define reg_pio_rw_oe___ce2_n___bit 14 | ||
| 228 | #define reg_pio_rw_oe___rdy___lsb 15 | ||
| 229 | #define reg_pio_rw_oe___rdy___width 1 | ||
| 230 | #define reg_pio_rw_oe___rdy___bit 15 | ||
| 231 | #define reg_pio_rw_oe_offset 84 | ||
| 232 | |||
| 233 | /* Register rw_man_ctrl, scope pio, type rw */ | ||
| 234 | #define reg_pio_rw_man_ctrl___data___lsb 0 | ||
| 235 | #define reg_pio_rw_man_ctrl___data___width 8 | ||
| 236 | #define reg_pio_rw_man_ctrl___rd_n___lsb 8 | ||
| 237 | #define reg_pio_rw_man_ctrl___rd_n___width 1 | ||
| 238 | #define reg_pio_rw_man_ctrl___rd_n___bit 8 | ||
| 239 | #define reg_pio_rw_man_ctrl___wr_n___lsb 9 | ||
| 240 | #define reg_pio_rw_man_ctrl___wr_n___width 1 | ||
| 241 | #define reg_pio_rw_man_ctrl___wr_n___bit 9 | ||
| 242 | #define reg_pio_rw_man_ctrl___a0___lsb 10 | ||
| 243 | #define reg_pio_rw_man_ctrl___a0___width 1 | ||
| 244 | #define reg_pio_rw_man_ctrl___a0___bit 10 | ||
| 245 | #define reg_pio_rw_man_ctrl___a1___lsb 11 | ||
| 246 | #define reg_pio_rw_man_ctrl___a1___width 1 | ||
| 247 | #define reg_pio_rw_man_ctrl___a1___bit 11 | ||
| 248 | #define reg_pio_rw_man_ctrl___ce0_n___lsb 12 | ||
| 249 | #define reg_pio_rw_man_ctrl___ce0_n___width 1 | ||
| 250 | #define reg_pio_rw_man_ctrl___ce0_n___bit 12 | ||
| 251 | #define reg_pio_rw_man_ctrl___ce1_n___lsb 13 | ||
| 252 | #define reg_pio_rw_man_ctrl___ce1_n___width 1 | ||
| 253 | #define reg_pio_rw_man_ctrl___ce1_n___bit 13 | ||
| 254 | #define reg_pio_rw_man_ctrl___ce2_n___lsb 14 | ||
| 255 | #define reg_pio_rw_man_ctrl___ce2_n___width 1 | ||
| 256 | #define reg_pio_rw_man_ctrl___ce2_n___bit 14 | ||
| 257 | #define reg_pio_rw_man_ctrl___rdy___lsb 15 | ||
| 258 | #define reg_pio_rw_man_ctrl___rdy___width 1 | ||
| 259 | #define reg_pio_rw_man_ctrl___rdy___bit 15 | ||
| 260 | #define reg_pio_rw_man_ctrl_offset 88 | ||
| 261 | |||
| 262 | /* Register r_din, scope pio, type r */ | ||
| 263 | #define reg_pio_r_din___data___lsb 0 | ||
| 264 | #define reg_pio_r_din___data___width 8 | ||
| 265 | #define reg_pio_r_din___rd_n___lsb 8 | ||
| 266 | #define reg_pio_r_din___rd_n___width 1 | ||
| 267 | #define reg_pio_r_din___rd_n___bit 8 | ||
| 268 | #define reg_pio_r_din___wr_n___lsb 9 | ||
| 269 | #define reg_pio_r_din___wr_n___width 1 | ||
| 270 | #define reg_pio_r_din___wr_n___bit 9 | ||
| 271 | #define reg_pio_r_din___a0___lsb 10 | ||
| 272 | #define reg_pio_r_din___a0___width 1 | ||
| 273 | #define reg_pio_r_din___a0___bit 10 | ||
| 274 | #define reg_pio_r_din___a1___lsb 11 | ||
| 275 | #define reg_pio_r_din___a1___width 1 | ||
| 276 | #define reg_pio_r_din___a1___bit 11 | ||
| 277 | #define reg_pio_r_din___ce0_n___lsb 12 | ||
| 278 | #define reg_pio_r_din___ce0_n___width 1 | ||
| 279 | #define reg_pio_r_din___ce0_n___bit 12 | ||
| 280 | #define reg_pio_r_din___ce1_n___lsb 13 | ||
| 281 | #define reg_pio_r_din___ce1_n___width 1 | ||
| 282 | #define reg_pio_r_din___ce1_n___bit 13 | ||
| 283 | #define reg_pio_r_din___ce2_n___lsb 14 | ||
| 284 | #define reg_pio_r_din___ce2_n___width 1 | ||
| 285 | #define reg_pio_r_din___ce2_n___bit 14 | ||
| 286 | #define reg_pio_r_din___rdy___lsb 15 | ||
| 287 | #define reg_pio_r_din___rdy___width 1 | ||
| 288 | #define reg_pio_r_din___rdy___bit 15 | ||
| 289 | #define reg_pio_r_din_offset 92 | ||
| 290 | |||
| 291 | /* Register r_stat, scope pio, type r */ | ||
| 292 | #define reg_pio_r_stat___busy___lsb 0 | ||
| 293 | #define reg_pio_r_stat___busy___width 1 | ||
| 294 | #define reg_pio_r_stat___busy___bit 0 | ||
| 295 | #define reg_pio_r_stat_offset 96 | ||
| 296 | |||
| 297 | /* Register rw_intr_mask, scope pio, type rw */ | ||
| 298 | #define reg_pio_rw_intr_mask___rdy___lsb 0 | ||
| 299 | #define reg_pio_rw_intr_mask___rdy___width 1 | ||
| 300 | #define reg_pio_rw_intr_mask___rdy___bit 0 | ||
| 301 | #define reg_pio_rw_intr_mask_offset 100 | ||
| 302 | |||
| 303 | /* Register rw_ack_intr, scope pio, type rw */ | ||
| 304 | #define reg_pio_rw_ack_intr___rdy___lsb 0 | ||
| 305 | #define reg_pio_rw_ack_intr___rdy___width 1 | ||
| 306 | #define reg_pio_rw_ack_intr___rdy___bit 0 | ||
| 307 | #define reg_pio_rw_ack_intr_offset 104 | ||
| 308 | |||
| 309 | /* Register r_intr, scope pio, type r */ | ||
| 310 | #define reg_pio_r_intr___rdy___lsb 0 | ||
| 311 | #define reg_pio_r_intr___rdy___width 1 | ||
| 312 | #define reg_pio_r_intr___rdy___bit 0 | ||
| 313 | #define reg_pio_r_intr_offset 108 | ||
| 314 | |||
| 315 | /* Register r_masked_intr, scope pio, type r */ | ||
| 316 | #define reg_pio_r_masked_intr___rdy___lsb 0 | ||
| 317 | #define reg_pio_r_masked_intr___rdy___width 1 | ||
| 318 | #define reg_pio_r_masked_intr___rdy___bit 0 | ||
| 319 | #define reg_pio_r_masked_intr_offset 112 | ||
| 320 | |||
| 321 | |||
| 322 | /* Constants */ | ||
| 323 | #define regk_pio_a2 0x00000003 | ||
| 324 | #define regk_pio_no 0x00000000 | ||
| 325 | #define regk_pio_normal 0x00000000 | ||
| 326 | #define regk_pio_rd 0x00000001 | ||
| 327 | #define regk_pio_rw_ce0_cfg_default 0x00000000 | ||
| 328 | #define regk_pio_rw_ce1_cfg_default 0x00000000 | ||
| 329 | #define regk_pio_rw_ce2_cfg_default 0x00000000 | ||
| 330 | #define regk_pio_rw_intr_mask_default 0x00000000 | ||
| 331 | #define regk_pio_rw_man_ctrl_default 0x00000000 | ||
| 332 | #define regk_pio_rw_oe_default 0x00000000 | ||
| 333 | #define regk_pio_wr 0x00000002 | ||
| 334 | #define regk_pio_wr_ce2 0x00000003 | ||
| 335 | #define regk_pio_yes 0x00000001 | ||
| 336 | #define regk_pio_yes_all 0x000000ff | ||
| 337 | #endif /* __pio_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h new file mode 100644 index 000000000000..89439e9610e2 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h | |||
| @@ -0,0 +1,99 @@ | |||
| 1 | #ifndef __reg_map_asm_h | ||
| 2 | #define __reg_map_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: reg.rmap | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | #define regi_ccd 0xb0000000 | ||
| 14 | #define regi_ccd_top 0xb0000000 | ||
| 15 | #define regi_ccd_dp 0xb0000400 | ||
| 16 | #define regi_ccd_stat 0xb0000800 | ||
| 17 | #define regi_ccd_tg 0xb0001000 | ||
| 18 | #define regi_cfg 0xb0002000 | ||
| 19 | #define regi_clkgen 0xb0004000 | ||
| 20 | #define regi_ddr2_ctrl 0xb0006000 | ||
| 21 | #define regi_dma0 0xb0008000 | ||
| 22 | #define regi_dma1 0xb000a000 | ||
| 23 | #define regi_dma11 0xb000c000 | ||
| 24 | #define regi_dma2 0xb000e000 | ||
| 25 | #define regi_dma3 0xb0010000 | ||
| 26 | #define regi_dma4 0xb0012000 | ||
| 27 | #define regi_dma5 0xb0014000 | ||
| 28 | #define regi_dma6 0xb0016000 | ||
| 29 | #define regi_dma7 0xb0018000 | ||
| 30 | #define regi_dma9 0xb001a000 | ||
| 31 | #define regi_eth 0xb001c000 | ||
| 32 | #define regi_gio 0xb0020000 | ||
| 33 | #define regi_h264 0xb0022000 | ||
| 34 | #define regi_hist 0xb0026000 | ||
| 35 | #define regi_iop 0xb0028000 | ||
| 36 | #define regi_iop_version 0xb0028000 | ||
| 37 | #define regi_iop_fifo_in_extra 0xb0028040 | ||
| 38 | #define regi_iop_fifo_out_extra 0xb0028080 | ||
| 39 | #define regi_iop_trigger_grp0 0xb00280c0 | ||
| 40 | #define regi_iop_trigger_grp1 0xb0028100 | ||
| 41 | #define regi_iop_trigger_grp2 0xb0028140 | ||
| 42 | #define regi_iop_trigger_grp3 0xb0028180 | ||
| 43 | #define regi_iop_trigger_grp4 0xb00281c0 | ||
| 44 | #define regi_iop_trigger_grp5 0xb0028200 | ||
| 45 | #define regi_iop_trigger_grp6 0xb0028240 | ||
| 46 | #define regi_iop_trigger_grp7 0xb0028280 | ||
| 47 | #define regi_iop_crc_par 0xb0028300 | ||
| 48 | #define regi_iop_dmc_in 0xb0028380 | ||
| 49 | #define regi_iop_dmc_out 0xb0028400 | ||
| 50 | #define regi_iop_fifo_in 0xb0028480 | ||
| 51 | #define regi_iop_fifo_out 0xb0028500 | ||
| 52 | #define regi_iop_scrc_in 0xb0028580 | ||
| 53 | #define regi_iop_scrc_out 0xb0028600 | ||
| 54 | #define regi_iop_timer_grp0 0xb0028680 | ||
| 55 | #define regi_iop_timer_grp1 0xb0028700 | ||
| 56 | #define regi_iop_sap_in 0xb0028800 | ||
| 57 | #define regi_iop_sap_out 0xb0028900 | ||
| 58 | #define regi_iop_spu 0xb0028a00 | ||
| 59 | #define regi_iop_sw_cfg 0xb0028b00 | ||
| 60 | #define regi_iop_sw_cpu 0xb0028c00 | ||
| 61 | #define regi_iop_sw_mpu 0xb0028d00 | ||
| 62 | #define regi_iop_sw_spu 0xb0028e00 | ||
| 63 | #define regi_iop_mpu 0xb0029000 | ||
| 64 | #define regi_irq 0xb002a000 | ||
| 65 | #define regi_jpeg 0xb002c000 | ||
| 66 | #define regi_l2cache 0xb0030000 | ||
| 67 | #define regi_marb_bar 0xb0032000 | ||
| 68 | #define regi_marb_bar_bp0 0xb0032140 | ||
| 69 | #define regi_marb_bar_bp1 0xb0032180 | ||
| 70 | #define regi_marb_bar_bp2 0xb00321c0 | ||
| 71 | #define regi_marb_bar_bp3 0xb0032200 | ||
| 72 | #define regi_marb_foo 0xb0034000 | ||
| 73 | #define regi_marb_foo_bp0 0xb0034280 | ||
| 74 | #define regi_marb_foo_bp1 0xb00342c0 | ||
| 75 | #define regi_marb_foo_bp2 0xb0034300 | ||
| 76 | #define regi_marb_foo_bp3 0xb0034340 | ||
| 77 | #define regi_pinmux 0xb0038000 | ||
| 78 | #define regi_pio 0xb0036000 | ||
| 79 | #define regi_sclr 0xb003a000 | ||
| 80 | #define regi_sclr_fifo 0xb003c000 | ||
| 81 | #define regi_ser0 0xb003e000 | ||
| 82 | #define regi_ser1 0xb0040000 | ||
| 83 | #define regi_ser2 0xb0042000 | ||
| 84 | #define regi_ser3 0xb0044000 | ||
| 85 | #define regi_ser4 0xb0046000 | ||
| 86 | #define regi_sser 0xb0048000 | ||
| 87 | #define regi_strcop 0xb004a000 | ||
| 88 | #define regi_strdma0 0xb004e000 | ||
| 89 | #define regi_strdma1 0xb0050000 | ||
| 90 | #define regi_strdma2 0xb0052000 | ||
| 91 | #define regi_strdma3 0xb0054000 | ||
| 92 | #define regi_strdma5 0xb0056000 | ||
| 93 | #define regi_strmux 0xb004c000 | ||
| 94 | #define regi_timer0 0xb0058000 | ||
| 95 | #define regi_timer1 0xb005a000 | ||
| 96 | #define regi_trace 0xb005c000 | ||
| 97 | #define regi_vin 0xb005e000 | ||
| 98 | #define regi_vout 0xb0060000 | ||
| 99 | #endif /* __reg_map_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h new file mode 100644 index 000000000000..b129e826fc34 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h | |||
| @@ -0,0 +1,228 @@ | |||
| 1 | #ifndef __timer_defs_asm_h | ||
| 2 | #define __timer_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: timer.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_tmr0_div, scope timer, type rw */ | ||
| 54 | #define reg_timer_rw_tmr0_div_offset 0 | ||
| 55 | |||
| 56 | /* Register r_tmr0_data, scope timer, type r */ | ||
| 57 | #define reg_timer_r_tmr0_data_offset 4 | ||
| 58 | |||
| 59 | /* Register rw_tmr0_ctrl, scope timer, type rw */ | ||
| 60 | #define reg_timer_rw_tmr0_ctrl___op___lsb 0 | ||
| 61 | #define reg_timer_rw_tmr0_ctrl___op___width 2 | ||
| 62 | #define reg_timer_rw_tmr0_ctrl___freq___lsb 2 | ||
| 63 | #define reg_timer_rw_tmr0_ctrl___freq___width 3 | ||
| 64 | #define reg_timer_rw_tmr0_ctrl_offset 8 | ||
| 65 | |||
| 66 | /* Register rw_tmr1_div, scope timer, type rw */ | ||
| 67 | #define reg_timer_rw_tmr1_div_offset 16 | ||
| 68 | |||
| 69 | /* Register r_tmr1_data, scope timer, type r */ | ||
| 70 | #define reg_timer_r_tmr1_data_offset 20 | ||
| 71 | |||
| 72 | /* Register rw_tmr1_ctrl, scope timer, type rw */ | ||
| 73 | #define reg_timer_rw_tmr1_ctrl___op___lsb 0 | ||
| 74 | #define reg_timer_rw_tmr1_ctrl___op___width 2 | ||
| 75 | #define reg_timer_rw_tmr1_ctrl___freq___lsb 2 | ||
| 76 | #define reg_timer_rw_tmr1_ctrl___freq___width 3 | ||
| 77 | #define reg_timer_rw_tmr1_ctrl_offset 24 | ||
| 78 | |||
| 79 | /* Register rs_cnt_data, scope timer, type rs */ | ||
| 80 | #define reg_timer_rs_cnt_data___tmr___lsb 0 | ||
| 81 | #define reg_timer_rs_cnt_data___tmr___width 24 | ||
| 82 | #define reg_timer_rs_cnt_data___cnt___lsb 24 | ||
| 83 | #define reg_timer_rs_cnt_data___cnt___width 8 | ||
| 84 | #define reg_timer_rs_cnt_data_offset 32 | ||
| 85 | |||
| 86 | /* Register r_cnt_data, scope timer, type r */ | ||
| 87 | #define reg_timer_r_cnt_data___tmr___lsb 0 | ||
| 88 | #define reg_timer_r_cnt_data___tmr___width 24 | ||
| 89 | #define reg_timer_r_cnt_data___cnt___lsb 24 | ||
| 90 | #define reg_timer_r_cnt_data___cnt___width 8 | ||
| 91 | #define reg_timer_r_cnt_data_offset 36 | ||
| 92 | |||
| 93 | /* Register rw_cnt_cfg, scope timer, type rw */ | ||
| 94 | #define reg_timer_rw_cnt_cfg___clk___lsb 0 | ||
| 95 | #define reg_timer_rw_cnt_cfg___clk___width 2 | ||
| 96 | #define reg_timer_rw_cnt_cfg_offset 40 | ||
| 97 | |||
| 98 | /* Register rw_trig, scope timer, type rw */ | ||
| 99 | #define reg_timer_rw_trig_offset 48 | ||
| 100 | |||
| 101 | /* Register rw_trig_cfg, scope timer, type rw */ | ||
| 102 | #define reg_timer_rw_trig_cfg___tmr___lsb 0 | ||
| 103 | #define reg_timer_rw_trig_cfg___tmr___width 2 | ||
| 104 | #define reg_timer_rw_trig_cfg_offset 52 | ||
| 105 | |||
| 106 | /* Register r_time, scope timer, type r */ | ||
| 107 | #define reg_timer_r_time_offset 56 | ||
| 108 | |||
| 109 | /* Register rw_out, scope timer, type rw */ | ||
| 110 | #define reg_timer_rw_out___tmr___lsb 0 | ||
| 111 | #define reg_timer_rw_out___tmr___width 2 | ||
| 112 | #define reg_timer_rw_out_offset 60 | ||
| 113 | |||
| 114 | /* Register rw_wd_ctrl, scope timer, type rw */ | ||
| 115 | #define reg_timer_rw_wd_ctrl___cnt___lsb 0 | ||
| 116 | #define reg_timer_rw_wd_ctrl___cnt___width 8 | ||
| 117 | #define reg_timer_rw_wd_ctrl___cmd___lsb 8 | ||
| 118 | #define reg_timer_rw_wd_ctrl___cmd___width 1 | ||
| 119 | #define reg_timer_rw_wd_ctrl___cmd___bit 8 | ||
| 120 | #define reg_timer_rw_wd_ctrl___key___lsb 9 | ||
| 121 | #define reg_timer_rw_wd_ctrl___key___width 7 | ||
| 122 | #define reg_timer_rw_wd_ctrl_offset 64 | ||
| 123 | |||
| 124 | /* Register r_wd_stat, scope timer, type r */ | ||
| 125 | #define reg_timer_r_wd_stat___cnt___lsb 0 | ||
| 126 | #define reg_timer_r_wd_stat___cnt___width 8 | ||
| 127 | #define reg_timer_r_wd_stat___cmd___lsb 8 | ||
| 128 | #define reg_timer_r_wd_stat___cmd___width 1 | ||
| 129 | #define reg_timer_r_wd_stat___cmd___bit 8 | ||
| 130 | #define reg_timer_r_wd_stat_offset 68 | ||
| 131 | |||
| 132 | /* Register rw_intr_mask, scope timer, type rw */ | ||
| 133 | #define reg_timer_rw_intr_mask___tmr0___lsb 0 | ||
| 134 | #define reg_timer_rw_intr_mask___tmr0___width 1 | ||
| 135 | #define reg_timer_rw_intr_mask___tmr0___bit 0 | ||
| 136 | #define reg_timer_rw_intr_mask___tmr1___lsb 1 | ||
| 137 | #define reg_timer_rw_intr_mask___tmr1___width 1 | ||
| 138 | #define reg_timer_rw_intr_mask___tmr1___bit 1 | ||
| 139 | #define reg_timer_rw_intr_mask___cnt___lsb 2 | ||
| 140 | #define reg_timer_rw_intr_mask___cnt___width 1 | ||
| 141 | #define reg_timer_rw_intr_mask___cnt___bit 2 | ||
| 142 | #define reg_timer_rw_intr_mask___trig___lsb 3 | ||
| 143 | #define reg_timer_rw_intr_mask___trig___width 1 | ||
| 144 | #define reg_timer_rw_intr_mask___trig___bit 3 | ||
| 145 | #define reg_timer_rw_intr_mask_offset 72 | ||
| 146 | |||
| 147 | /* Register rw_ack_intr, scope timer, type rw */ | ||
| 148 | #define reg_timer_rw_ack_intr___tmr0___lsb 0 | ||
| 149 | #define reg_timer_rw_ack_intr___tmr0___width 1 | ||
| 150 | #define reg_timer_rw_ack_intr___tmr0___bit 0 | ||
| 151 | #define reg_timer_rw_ack_intr___tmr1___lsb 1 | ||
| 152 | #define reg_timer_rw_ack_intr___tmr1___width 1 | ||
| 153 | #define reg_timer_rw_ack_intr___tmr1___bit 1 | ||
| 154 | #define reg_timer_rw_ack_intr___cnt___lsb 2 | ||
| 155 | #define reg_timer_rw_ack_intr___cnt___width 1 | ||
| 156 | #define reg_timer_rw_ack_intr___cnt___bit 2 | ||
| 157 | #define reg_timer_rw_ack_intr___trig___lsb 3 | ||
| 158 | #define reg_timer_rw_ack_intr___trig___width 1 | ||
| 159 | #define reg_timer_rw_ack_intr___trig___bit 3 | ||
| 160 | #define reg_timer_rw_ack_intr_offset 76 | ||
| 161 | |||
| 162 | /* Register r_intr, scope timer, type r */ | ||
| 163 | #define reg_timer_r_intr___tmr0___lsb 0 | ||
| 164 | #define reg_timer_r_intr___tmr0___width 1 | ||
| 165 | #define reg_timer_r_intr___tmr0___bit 0 | ||
| 166 | #define reg_timer_r_intr___tmr1___lsb 1 | ||
| 167 | #define reg_timer_r_intr___tmr1___width 1 | ||
| 168 | #define reg_timer_r_intr___tmr1___bit 1 | ||
| 169 | #define reg_timer_r_intr___cnt___lsb 2 | ||
| 170 | #define reg_timer_r_intr___cnt___width 1 | ||
| 171 | #define reg_timer_r_intr___cnt___bit 2 | ||
| 172 | #define reg_timer_r_intr___trig___lsb 3 | ||
| 173 | #define reg_timer_r_intr___trig___width 1 | ||
| 174 | #define reg_timer_r_intr___trig___bit 3 | ||
| 175 | #define reg_timer_r_intr_offset 80 | ||
| 176 | |||
| 177 | /* Register r_masked_intr, scope timer, type r */ | ||
| 178 | #define reg_timer_r_masked_intr___tmr0___lsb 0 | ||
| 179 | #define reg_timer_r_masked_intr___tmr0___width 1 | ||
| 180 | #define reg_timer_r_masked_intr___tmr0___bit 0 | ||
| 181 | #define reg_timer_r_masked_intr___tmr1___lsb 1 | ||
| 182 | #define reg_timer_r_masked_intr___tmr1___width 1 | ||
| 183 | #define reg_timer_r_masked_intr___tmr1___bit 1 | ||
| 184 | #define reg_timer_r_masked_intr___cnt___lsb 2 | ||
| 185 | #define reg_timer_r_masked_intr___cnt___width 1 | ||
| 186 | #define reg_timer_r_masked_intr___cnt___bit 2 | ||
| 187 | #define reg_timer_r_masked_intr___trig___lsb 3 | ||
| 188 | #define reg_timer_r_masked_intr___trig___width 1 | ||
| 189 | #define reg_timer_r_masked_intr___trig___bit 3 | ||
| 190 | #define reg_timer_r_masked_intr_offset 84 | ||
| 191 | |||
| 192 | /* Register rw_test, scope timer, type rw */ | ||
| 193 | #define reg_timer_rw_test___dis___lsb 0 | ||
| 194 | #define reg_timer_rw_test___dis___width 1 | ||
| 195 | #define reg_timer_rw_test___dis___bit 0 | ||
| 196 | #define reg_timer_rw_test___en___lsb 1 | ||
| 197 | #define reg_timer_rw_test___en___width 1 | ||
| 198 | #define reg_timer_rw_test___en___bit 1 | ||
| 199 | #define reg_timer_rw_test_offset 88 | ||
| 200 | |||
| 201 | |||
| 202 | /* Constants */ | ||
| 203 | #define regk_timer_ext 0x00000001 | ||
| 204 | #define regk_timer_f100 0x00000007 | ||
| 205 | #define regk_timer_f29_493 0x00000004 | ||
| 206 | #define regk_timer_f32 0x00000005 | ||
| 207 | #define regk_timer_f32_768 0x00000006 | ||
| 208 | #define regk_timer_f90 0x00000003 | ||
| 209 | #define regk_timer_hold 0x00000001 | ||
| 210 | #define regk_timer_ld 0x00000000 | ||
| 211 | #define regk_timer_no 0x00000000 | ||
| 212 | #define regk_timer_off 0x00000000 | ||
| 213 | #define regk_timer_run 0x00000002 | ||
| 214 | #define regk_timer_rw_cnt_cfg_default 0x00000000 | ||
| 215 | #define regk_timer_rw_intr_mask_default 0x00000000 | ||
| 216 | #define regk_timer_rw_out_default 0x00000000 | ||
| 217 | #define regk_timer_rw_test_default 0x00000000 | ||
| 218 | #define regk_timer_rw_tmr0_ctrl_default 0x00000000 | ||
| 219 | #define regk_timer_rw_tmr1_ctrl_default 0x00000000 | ||
| 220 | #define regk_timer_rw_trig_cfg_default 0x00000000 | ||
| 221 | #define regk_timer_start 0x00000001 | ||
| 222 | #define regk_timer_stop 0x00000000 | ||
| 223 | #define regk_timer_time 0x00000001 | ||
| 224 | #define regk_timer_tmr0 0x00000002 | ||
| 225 | #define regk_timer_tmr1 0x00000003 | ||
| 226 | #define regk_timer_vclk 0x00000002 | ||
| 227 | #define regk_timer_yes 0x00000001 | ||
| 228 | #endif /* __timer_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h new file mode 100644 index 000000000000..c1e9ba93b3a3 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h | |||
| @@ -0,0 +1,159 @@ | |||
| 1 | #ifndef __clkgen_defs_h | ||
| 2 | #define __clkgen_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: clkgen.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope clkgen */ | ||
| 83 | |||
| 84 | /* Register r_bootsel, scope clkgen, type r */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int boot_mode : 5; | ||
| 87 | unsigned int intern_main_clk : 1; | ||
| 88 | unsigned int extern_usb2_clk : 1; | ||
| 89 | unsigned int dummy1 : 25; | ||
| 90 | } reg_clkgen_r_bootsel; | ||
| 91 | #define REG_RD_ADDR_clkgen_r_bootsel 0 | ||
| 92 | |||
| 93 | /* Register rw_clk_ctrl, scope clkgen, type rw */ | ||
| 94 | typedef struct { | ||
| 95 | unsigned int pll : 1; | ||
| 96 | unsigned int cpu : 1; | ||
| 97 | unsigned int iop_usb : 1; | ||
| 98 | unsigned int vin : 1; | ||
| 99 | unsigned int sclr : 1; | ||
| 100 | unsigned int h264 : 1; | ||
| 101 | unsigned int ddr2 : 1; | ||
| 102 | unsigned int vout_hist : 1; | ||
| 103 | unsigned int eth : 1; | ||
| 104 | unsigned int ccd_tg_200 : 1; | ||
| 105 | unsigned int dma0_1_eth : 1; | ||
| 106 | unsigned int ccd_tg_100 : 1; | ||
| 107 | unsigned int jpeg : 1; | ||
| 108 | unsigned int sser_ser_dma6_7 : 1; | ||
| 109 | unsigned int strdma0_2_video : 1; | ||
| 110 | unsigned int dma2_3_strcop : 1; | ||
| 111 | unsigned int dma4_5_iop : 1; | ||
| 112 | unsigned int dma9_11 : 1; | ||
| 113 | unsigned int memarb_bar_ddr : 1; | ||
| 114 | unsigned int sclr_h264 : 1; | ||
| 115 | unsigned int dummy1 : 12; | ||
| 116 | } reg_clkgen_rw_clk_ctrl; | ||
| 117 | #define REG_RD_ADDR_clkgen_rw_clk_ctrl 4 | ||
| 118 | #define REG_WR_ADDR_clkgen_rw_clk_ctrl 4 | ||
| 119 | |||
| 120 | |||
| 121 | /* Constants */ | ||
| 122 | enum { | ||
| 123 | regk_clkgen_eth1000_rx = 0x0000000c, | ||
| 124 | regk_clkgen_eth1000_tx = 0x0000000e, | ||
| 125 | regk_clkgen_eth100_rx = 0x0000001d, | ||
| 126 | regk_clkgen_eth100_rx_half = 0x0000001c, | ||
| 127 | regk_clkgen_eth100_tx = 0x0000001f, | ||
| 128 | regk_clkgen_eth100_tx_half = 0x0000001e, | ||
| 129 | regk_clkgen_nand_3_2 = 0x00000000, | ||
| 130 | regk_clkgen_nand_3_2_0x30 = 0x00000002, | ||
| 131 | regk_clkgen_nand_3_2_0x30_pll = 0x00000012, | ||
| 132 | regk_clkgen_nand_3_2_pll = 0x00000010, | ||
| 133 | regk_clkgen_nand_3_3 = 0x00000001, | ||
| 134 | regk_clkgen_nand_3_3_0x30 = 0x00000003, | ||
| 135 | regk_clkgen_nand_3_3_0x30_pll = 0x00000013, | ||
| 136 | regk_clkgen_nand_3_3_pll = 0x00000011, | ||
| 137 | regk_clkgen_nand_4_2 = 0x00000004, | ||
| 138 | regk_clkgen_nand_4_2_0x30 = 0x00000006, | ||
| 139 | regk_clkgen_nand_4_2_0x30_pll = 0x00000016, | ||
| 140 | regk_clkgen_nand_4_2_pll = 0x00000014, | ||
| 141 | regk_clkgen_nand_4_3 = 0x00000005, | ||
| 142 | regk_clkgen_nand_4_3_0x30 = 0x00000007, | ||
| 143 | regk_clkgen_nand_4_3_0x30_pll = 0x00000017, | ||
| 144 | regk_clkgen_nand_4_3_pll = 0x00000015, | ||
| 145 | regk_clkgen_nand_5_2 = 0x00000008, | ||
| 146 | regk_clkgen_nand_5_2_0x30 = 0x0000000a, | ||
| 147 | regk_clkgen_nand_5_2_0x30_pll = 0x0000001a, | ||
| 148 | regk_clkgen_nand_5_2_pll = 0x00000018, | ||
| 149 | regk_clkgen_nand_5_3 = 0x00000009, | ||
| 150 | regk_clkgen_nand_5_3_0x30 = 0x0000000b, | ||
| 151 | regk_clkgen_nand_5_3_0x30_pll = 0x0000001b, | ||
| 152 | regk_clkgen_nand_5_3_pll = 0x00000019, | ||
| 153 | regk_clkgen_no = 0x00000000, | ||
| 154 | regk_clkgen_rw_clk_ctrl_default = 0x00000002, | ||
| 155 | regk_clkgen_ser = 0x0000000d, | ||
| 156 | regk_clkgen_ser_pll = 0x0000000f, | ||
| 157 | regk_clkgen_yes = 0x00000001 | ||
| 158 | }; | ||
| 159 | #endif /* __clkgen_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h new file mode 100644 index 000000000000..0f30e8bf946d --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h | |||
| @@ -0,0 +1,281 @@ | |||
| 1 | #ifndef __ddr2_defs_h | ||
| 2 | #define __ddr2_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ddr2.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope ddr2 */ | ||
| 83 | |||
| 84 | /* Register rw_cfg, scope ddr2, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int col_width : 4; | ||
| 87 | unsigned int nr_banks : 1; | ||
| 88 | unsigned int bw : 1; | ||
| 89 | unsigned int nr_ref : 4; | ||
| 90 | unsigned int ref_interval : 11; | ||
| 91 | unsigned int odt_ctrl : 2; | ||
| 92 | unsigned int odt_mem : 1; | ||
| 93 | unsigned int imp_strength : 1; | ||
| 94 | unsigned int auto_imp_cal : 1; | ||
| 95 | unsigned int imp_cal_override : 1; | ||
| 96 | unsigned int dll_override : 1; | ||
| 97 | unsigned int dummy1 : 4; | ||
| 98 | } reg_ddr2_rw_cfg; | ||
| 99 | #define REG_RD_ADDR_ddr2_rw_cfg 0 | ||
| 100 | #define REG_WR_ADDR_ddr2_rw_cfg 0 | ||
| 101 | |||
| 102 | /* Register rw_timing, scope ddr2, type rw */ | ||
| 103 | typedef struct { | ||
| 104 | unsigned int wr : 3; | ||
| 105 | unsigned int rcd : 3; | ||
| 106 | unsigned int rp : 3; | ||
| 107 | unsigned int ras : 4; | ||
| 108 | unsigned int rfc : 7; | ||
| 109 | unsigned int rc : 5; | ||
| 110 | unsigned int rtp : 2; | ||
| 111 | unsigned int rtw : 3; | ||
| 112 | unsigned int wtr : 2; | ||
| 113 | } reg_ddr2_rw_timing; | ||
| 114 | #define REG_RD_ADDR_ddr2_rw_timing 4 | ||
| 115 | #define REG_WR_ADDR_ddr2_rw_timing 4 | ||
| 116 | |||
| 117 | /* Register rw_latency, scope ddr2, type rw */ | ||
| 118 | typedef struct { | ||
| 119 | unsigned int cas : 3; | ||
| 120 | unsigned int additive : 3; | ||
| 121 | unsigned int dummy1 : 26; | ||
| 122 | } reg_ddr2_rw_latency; | ||
| 123 | #define REG_RD_ADDR_ddr2_rw_latency 8 | ||
| 124 | #define REG_WR_ADDR_ddr2_rw_latency 8 | ||
| 125 | |||
| 126 | /* Register rw_phy_cfg, scope ddr2, type rw */ | ||
| 127 | typedef struct { | ||
| 128 | unsigned int en : 1; | ||
| 129 | unsigned int dummy1 : 31; | ||
| 130 | } reg_ddr2_rw_phy_cfg; | ||
| 131 | #define REG_RD_ADDR_ddr2_rw_phy_cfg 12 | ||
| 132 | #define REG_WR_ADDR_ddr2_rw_phy_cfg 12 | ||
| 133 | |||
| 134 | /* Register rw_phy_ctrl, scope ddr2, type rw */ | ||
| 135 | typedef struct { | ||
| 136 | unsigned int rst : 1; | ||
| 137 | unsigned int cal_rst : 1; | ||
| 138 | unsigned int cal_start : 1; | ||
| 139 | unsigned int dummy1 : 29; | ||
| 140 | } reg_ddr2_rw_phy_ctrl; | ||
| 141 | #define REG_RD_ADDR_ddr2_rw_phy_ctrl 16 | ||
| 142 | #define REG_WR_ADDR_ddr2_rw_phy_ctrl 16 | ||
| 143 | |||
| 144 | /* Register rw_ctrl, scope ddr2, type rw */ | ||
| 145 | typedef struct { | ||
| 146 | unsigned int mrs_data : 16; | ||
| 147 | unsigned int cmd : 8; | ||
| 148 | unsigned int dummy1 : 8; | ||
| 149 | } reg_ddr2_rw_ctrl; | ||
| 150 | #define REG_RD_ADDR_ddr2_rw_ctrl 20 | ||
| 151 | #define REG_WR_ADDR_ddr2_rw_ctrl 20 | ||
| 152 | |||
| 153 | /* Register rw_pwr_down, scope ddr2, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int self_ref : 2; | ||
| 156 | unsigned int phy_en : 1; | ||
| 157 | unsigned int dummy1 : 29; | ||
| 158 | } reg_ddr2_rw_pwr_down; | ||
| 159 | #define REG_RD_ADDR_ddr2_rw_pwr_down 24 | ||
| 160 | #define REG_WR_ADDR_ddr2_rw_pwr_down 24 | ||
| 161 | |||
| 162 | /* Register r_stat, scope ddr2, type r */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int dll_lock : 1; | ||
| 165 | unsigned int dll_delay_code : 7; | ||
| 166 | unsigned int imp_cal_done : 1; | ||
| 167 | unsigned int imp_cal_fault : 1; | ||
| 168 | unsigned int cal_imp_pu : 4; | ||
| 169 | unsigned int cal_imp_pd : 4; | ||
| 170 | unsigned int dummy1 : 14; | ||
| 171 | } reg_ddr2_r_stat; | ||
| 172 | #define REG_RD_ADDR_ddr2_r_stat 28 | ||
| 173 | |||
| 174 | /* Register rw_imp_ctrl, scope ddr2, type rw */ | ||
| 175 | typedef struct { | ||
| 176 | unsigned int imp_pu : 4; | ||
| 177 | unsigned int imp_pd : 4; | ||
| 178 | unsigned int dummy1 : 24; | ||
| 179 | } reg_ddr2_rw_imp_ctrl; | ||
| 180 | #define REG_RD_ADDR_ddr2_rw_imp_ctrl 32 | ||
| 181 | #define REG_WR_ADDR_ddr2_rw_imp_ctrl 32 | ||
| 182 | |||
| 183 | #define STRIDE_ddr2_rw_dll_ctrl 4 | ||
| 184 | /* Register rw_dll_ctrl, scope ddr2, type rw */ | ||
| 185 | typedef struct { | ||
| 186 | unsigned int mode : 1; | ||
| 187 | unsigned int clk_delay : 7; | ||
| 188 | unsigned int dummy1 : 24; | ||
| 189 | } reg_ddr2_rw_dll_ctrl; | ||
| 190 | #define REG_RD_ADDR_ddr2_rw_dll_ctrl 36 | ||
| 191 | #define REG_WR_ADDR_ddr2_rw_dll_ctrl 36 | ||
| 192 | |||
| 193 | #define STRIDE_ddr2_rw_dqs_dll_ctrl 4 | ||
| 194 | /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ | ||
| 195 | typedef struct { | ||
| 196 | unsigned int dqs90_delay : 7; | ||
| 197 | unsigned int dqs180_delay : 7; | ||
| 198 | unsigned int dqs270_delay : 7; | ||
| 199 | unsigned int dqs360_delay : 7; | ||
| 200 | unsigned int dummy1 : 4; | ||
| 201 | } reg_ddr2_rw_dqs_dll_ctrl; | ||
| 202 | #define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52 | ||
| 203 | #define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52 | ||
| 204 | |||
| 205 | |||
| 206 | /* Constants */ | ||
| 207 | enum { | ||
| 208 | regk_ddr2_al0 = 0x00000000, | ||
| 209 | regk_ddr2_al1 = 0x00000008, | ||
| 210 | regk_ddr2_al2 = 0x00000010, | ||
| 211 | regk_ddr2_al3 = 0x00000018, | ||
| 212 | regk_ddr2_al4 = 0x00000020, | ||
| 213 | regk_ddr2_auto = 0x00000003, | ||
| 214 | regk_ddr2_bank4 = 0x00000000, | ||
| 215 | regk_ddr2_bank8 = 0x00000001, | ||
| 216 | regk_ddr2_bl4 = 0x00000002, | ||
| 217 | regk_ddr2_bl8 = 0x00000003, | ||
| 218 | regk_ddr2_bt_il = 0x00000008, | ||
| 219 | regk_ddr2_bt_seq = 0x00000000, | ||
| 220 | regk_ddr2_bw16 = 0x00000001, | ||
| 221 | regk_ddr2_bw32 = 0x00000000, | ||
| 222 | regk_ddr2_cas2 = 0x00000020, | ||
| 223 | regk_ddr2_cas3 = 0x00000030, | ||
| 224 | regk_ddr2_cas4 = 0x00000040, | ||
| 225 | regk_ddr2_cas5 = 0x00000050, | ||
| 226 | regk_ddr2_deselect = 0x000000c0, | ||
| 227 | regk_ddr2_dic_weak = 0x00000002, | ||
| 228 | regk_ddr2_direct = 0x00000001, | ||
| 229 | regk_ddr2_dis = 0x00000000, | ||
| 230 | regk_ddr2_dll_dis = 0x00000001, | ||
| 231 | regk_ddr2_dll_en = 0x00000000, | ||
| 232 | regk_ddr2_dll_rst = 0x00000100, | ||
| 233 | regk_ddr2_emrs = 0x00000081, | ||
| 234 | regk_ddr2_emrs2 = 0x00000082, | ||
| 235 | regk_ddr2_emrs3 = 0x00000083, | ||
| 236 | regk_ddr2_full = 0x00000001, | ||
| 237 | regk_ddr2_hi_ref_rate = 0x00000080, | ||
| 238 | regk_ddr2_mrs = 0x00000080, | ||
| 239 | regk_ddr2_no = 0x00000000, | ||
| 240 | regk_ddr2_nop = 0x000000b8, | ||
| 241 | regk_ddr2_ocd_adj = 0x00000200, | ||
| 242 | regk_ddr2_ocd_default = 0x00000380, | ||
| 243 | regk_ddr2_ocd_drive0 = 0x00000100, | ||
| 244 | regk_ddr2_ocd_drive1 = 0x00000080, | ||
| 245 | regk_ddr2_ocd_exit = 0x00000000, | ||
| 246 | regk_ddr2_odt_dis = 0x00000000, | ||
| 247 | regk_ddr2_offs = 0x00000000, | ||
| 248 | regk_ddr2_pre = 0x00000090, | ||
| 249 | regk_ddr2_pre_all = 0x00000400, | ||
| 250 | regk_ddr2_pwr_down_fast = 0x00000000, | ||
| 251 | regk_ddr2_pwr_down_slow = 0x00001000, | ||
| 252 | regk_ddr2_ref = 0x00000088, | ||
| 253 | regk_ddr2_rtt150 = 0x00000040, | ||
| 254 | regk_ddr2_rtt50 = 0x00000044, | ||
| 255 | regk_ddr2_rtt75 = 0x00000004, | ||
| 256 | regk_ddr2_rw_cfg_default = 0x00186000, | ||
| 257 | regk_ddr2_rw_dll_ctrl_default = 0x00000000, | ||
| 258 | regk_ddr2_rw_dll_ctrl_size = 0x00000004, | ||
| 259 | regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000, | ||
| 260 | regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004, | ||
| 261 | regk_ddr2_rw_latency_default = 0x00000000, | ||
| 262 | regk_ddr2_rw_phy_cfg_default = 0x00000000, | ||
| 263 | regk_ddr2_rw_pwr_down_default = 0x00000000, | ||
| 264 | regk_ddr2_rw_timing_default = 0x00000000, | ||
| 265 | regk_ddr2_s1Gb = 0x0000001a, | ||
| 266 | regk_ddr2_s256Mb = 0x0000000f, | ||
| 267 | regk_ddr2_s2Gb = 0x00000027, | ||
| 268 | regk_ddr2_s4Gb = 0x00000042, | ||
| 269 | regk_ddr2_s512Mb = 0x00000015, | ||
| 270 | regk_ddr2_temp0_85 = 0x00000618, | ||
| 271 | regk_ddr2_temp85_95 = 0x0000030c, | ||
| 272 | regk_ddr2_term150 = 0x00000002, | ||
| 273 | regk_ddr2_term50 = 0x00000003, | ||
| 274 | regk_ddr2_term75 = 0x00000001, | ||
| 275 | regk_ddr2_test = 0x00000080, | ||
| 276 | regk_ddr2_weak = 0x00000000, | ||
| 277 | regk_ddr2_wr2 = 0x00000200, | ||
| 278 | regk_ddr2_wr3 = 0x00000400, | ||
| 279 | regk_ddr2_yes = 0x00000001 | ||
| 280 | }; | ||
| 281 | #endif /* __ddr2_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h new file mode 100644 index 000000000000..5d88e0db23ae --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/gio_defs.h | |||
| @@ -0,0 +1,837 @@ | |||
| 1 | #ifndef __gio_defs_h | ||
| 2 | #define __gio_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: gio.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope gio */ | ||
| 83 | |||
| 84 | /* Register r_pa_din, scope gio, type r */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int data : 32; | ||
| 87 | } reg_gio_r_pa_din; | ||
| 88 | #define REG_RD_ADDR_gio_r_pa_din 0 | ||
| 89 | |||
| 90 | /* Register rw_pa_dout, scope gio, type rw */ | ||
| 91 | typedef struct { | ||
| 92 | unsigned int data : 32; | ||
| 93 | } reg_gio_rw_pa_dout; | ||
| 94 | #define REG_RD_ADDR_gio_rw_pa_dout 4 | ||
| 95 | #define REG_WR_ADDR_gio_rw_pa_dout 4 | ||
| 96 | |||
| 97 | /* Register rw_pa_oe, scope gio, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int oe : 32; | ||
| 100 | } reg_gio_rw_pa_oe; | ||
| 101 | #define REG_RD_ADDR_gio_rw_pa_oe 8 | ||
| 102 | #define REG_WR_ADDR_gio_rw_pa_oe 8 | ||
| 103 | |||
| 104 | /* Register rw_pa_byte0_dout, scope gio, type rw */ | ||
| 105 | typedef struct { | ||
| 106 | unsigned int data : 8; | ||
| 107 | unsigned int dummy1 : 24; | ||
| 108 | } reg_gio_rw_pa_byte0_dout; | ||
| 109 | #define REG_RD_ADDR_gio_rw_pa_byte0_dout 12 | ||
| 110 | #define REG_WR_ADDR_gio_rw_pa_byte0_dout 12 | ||
| 111 | |||
| 112 | /* Register rw_pa_byte0_oe, scope gio, type rw */ | ||
| 113 | typedef struct { | ||
| 114 | unsigned int oe : 8; | ||
| 115 | unsigned int dummy1 : 24; | ||
| 116 | } reg_gio_rw_pa_byte0_oe; | ||
| 117 | #define REG_RD_ADDR_gio_rw_pa_byte0_oe 16 | ||
| 118 | #define REG_WR_ADDR_gio_rw_pa_byte0_oe 16 | ||
| 119 | |||
| 120 | /* Register rw_pa_byte1_dout, scope gio, type rw */ | ||
| 121 | typedef struct { | ||
| 122 | unsigned int data : 8; | ||
| 123 | unsigned int dummy1 : 24; | ||
| 124 | } reg_gio_rw_pa_byte1_dout; | ||
| 125 | #define REG_RD_ADDR_gio_rw_pa_byte1_dout 20 | ||
| 126 | #define REG_WR_ADDR_gio_rw_pa_byte1_dout 20 | ||
| 127 | |||
| 128 | /* Register rw_pa_byte1_oe, scope gio, type rw */ | ||
| 129 | typedef struct { | ||
| 130 | unsigned int oe : 8; | ||
| 131 | unsigned int dummy1 : 24; | ||
| 132 | } reg_gio_rw_pa_byte1_oe; | ||
| 133 | #define REG_RD_ADDR_gio_rw_pa_byte1_oe 24 | ||
| 134 | #define REG_WR_ADDR_gio_rw_pa_byte1_oe 24 | ||
| 135 | |||
| 136 | /* Register rw_pa_byte2_dout, scope gio, type rw */ | ||
| 137 | typedef struct { | ||
| 138 | unsigned int data : 8; | ||
| 139 | unsigned int dummy1 : 24; | ||
| 140 | } reg_gio_rw_pa_byte2_dout; | ||
| 141 | #define REG_RD_ADDR_gio_rw_pa_byte2_dout 28 | ||
| 142 | #define REG_WR_ADDR_gio_rw_pa_byte2_dout 28 | ||
| 143 | |||
| 144 | /* Register rw_pa_byte2_oe, scope gio, type rw */ | ||
| 145 | typedef struct { | ||
| 146 | unsigned int oe : 8; | ||
| 147 | unsigned int dummy1 : 24; | ||
| 148 | } reg_gio_rw_pa_byte2_oe; | ||
| 149 | #define REG_RD_ADDR_gio_rw_pa_byte2_oe 32 | ||
| 150 | #define REG_WR_ADDR_gio_rw_pa_byte2_oe 32 | ||
| 151 | |||
| 152 | /* Register rw_pa_byte3_dout, scope gio, type rw */ | ||
| 153 | typedef struct { | ||
| 154 | unsigned int data : 8; | ||
| 155 | unsigned int dummy1 : 24; | ||
| 156 | } reg_gio_rw_pa_byte3_dout; | ||
| 157 | #define REG_RD_ADDR_gio_rw_pa_byte3_dout 36 | ||
| 158 | #define REG_WR_ADDR_gio_rw_pa_byte3_dout 36 | ||
| 159 | |||
| 160 | /* Register rw_pa_byte3_oe, scope gio, type rw */ | ||
| 161 | typedef struct { | ||
| 162 | unsigned int oe : 8; | ||
| 163 | unsigned int dummy1 : 24; | ||
| 164 | } reg_gio_rw_pa_byte3_oe; | ||
| 165 | #define REG_RD_ADDR_gio_rw_pa_byte3_oe 40 | ||
| 166 | #define REG_WR_ADDR_gio_rw_pa_byte3_oe 40 | ||
| 167 | |||
| 168 | /* Register r_pb_din, scope gio, type r */ | ||
| 169 | typedef struct { | ||
| 170 | unsigned int data : 32; | ||
| 171 | } reg_gio_r_pb_din; | ||
| 172 | #define REG_RD_ADDR_gio_r_pb_din 44 | ||
| 173 | |||
| 174 | /* Register rw_pb_dout, scope gio, type rw */ | ||
| 175 | typedef struct { | ||
| 176 | unsigned int data : 32; | ||
| 177 | } reg_gio_rw_pb_dout; | ||
| 178 | #define REG_RD_ADDR_gio_rw_pb_dout 48 | ||
| 179 | #define REG_WR_ADDR_gio_rw_pb_dout 48 | ||
| 180 | |||
| 181 | /* Register rw_pb_oe, scope gio, type rw */ | ||
| 182 | typedef struct { | ||
| 183 | unsigned int oe : 32; | ||
| 184 | } reg_gio_rw_pb_oe; | ||
| 185 | #define REG_RD_ADDR_gio_rw_pb_oe 52 | ||
| 186 | #define REG_WR_ADDR_gio_rw_pb_oe 52 | ||
| 187 | |||
| 188 | /* Register rw_pb_byte0_dout, scope gio, type rw */ | ||
| 189 | typedef struct { | ||
| 190 | unsigned int data : 8; | ||
| 191 | unsigned int dummy1 : 24; | ||
| 192 | } reg_gio_rw_pb_byte0_dout; | ||
| 193 | #define REG_RD_ADDR_gio_rw_pb_byte0_dout 56 | ||
| 194 | #define REG_WR_ADDR_gio_rw_pb_byte0_dout 56 | ||
| 195 | |||
| 196 | /* Register rw_pb_byte0_oe, scope gio, type rw */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int oe : 8; | ||
| 199 | unsigned int dummy1 : 24; | ||
| 200 | } reg_gio_rw_pb_byte0_oe; | ||
| 201 | #define REG_RD_ADDR_gio_rw_pb_byte0_oe 60 | ||
| 202 | #define REG_WR_ADDR_gio_rw_pb_byte0_oe 60 | ||
| 203 | |||
| 204 | /* Register rw_pb_byte1_dout, scope gio, type rw */ | ||
| 205 | typedef struct { | ||
| 206 | unsigned int data : 8; | ||
| 207 | unsigned int dummy1 : 24; | ||
| 208 | } reg_gio_rw_pb_byte1_dout; | ||
| 209 | #define REG_RD_ADDR_gio_rw_pb_byte1_dout 64 | ||
| 210 | #define REG_WR_ADDR_gio_rw_pb_byte1_dout 64 | ||
| 211 | |||
| 212 | /* Register rw_pb_byte1_oe, scope gio, type rw */ | ||
| 213 | typedef struct { | ||
| 214 | unsigned int oe : 8; | ||
| 215 | unsigned int dummy1 : 24; | ||
| 216 | } reg_gio_rw_pb_byte1_oe; | ||
| 217 | #define REG_RD_ADDR_gio_rw_pb_byte1_oe 68 | ||
| 218 | #define REG_WR_ADDR_gio_rw_pb_byte1_oe 68 | ||
| 219 | |||
| 220 | /* Register rw_pb_byte2_dout, scope gio, type rw */ | ||
| 221 | typedef struct { | ||
| 222 | unsigned int data : 8; | ||
| 223 | unsigned int dummy1 : 24; | ||
| 224 | } reg_gio_rw_pb_byte2_dout; | ||
| 225 | #define REG_RD_ADDR_gio_rw_pb_byte2_dout 72 | ||
| 226 | #define REG_WR_ADDR_gio_rw_pb_byte2_dout 72 | ||
| 227 | |||
| 228 | /* Register rw_pb_byte2_oe, scope gio, type rw */ | ||
| 229 | typedef struct { | ||
| 230 | unsigned int oe : 8; | ||
| 231 | unsigned int dummy1 : 24; | ||
| 232 | } reg_gio_rw_pb_byte2_oe; | ||
| 233 | #define REG_RD_ADDR_gio_rw_pb_byte2_oe 76 | ||
| 234 | #define REG_WR_ADDR_gio_rw_pb_byte2_oe 76 | ||
| 235 | |||
| 236 | /* Register rw_pb_byte3_dout, scope gio, type rw */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int data : 8; | ||
| 239 | unsigned int dummy1 : 24; | ||
| 240 | } reg_gio_rw_pb_byte3_dout; | ||
| 241 | #define REG_RD_ADDR_gio_rw_pb_byte3_dout 80 | ||
| 242 | #define REG_WR_ADDR_gio_rw_pb_byte3_dout 80 | ||
| 243 | |||
| 244 | /* Register rw_pb_byte3_oe, scope gio, type rw */ | ||
| 245 | typedef struct { | ||
| 246 | unsigned int oe : 8; | ||
| 247 | unsigned int dummy1 : 24; | ||
| 248 | } reg_gio_rw_pb_byte3_oe; | ||
| 249 | #define REG_RD_ADDR_gio_rw_pb_byte3_oe 84 | ||
| 250 | #define REG_WR_ADDR_gio_rw_pb_byte3_oe 84 | ||
| 251 | |||
| 252 | /* Register r_pc_din, scope gio, type r */ | ||
| 253 | typedef struct { | ||
| 254 | unsigned int data : 16; | ||
| 255 | unsigned int dummy1 : 16; | ||
| 256 | } reg_gio_r_pc_din; | ||
| 257 | #define REG_RD_ADDR_gio_r_pc_din 88 | ||
| 258 | |||
| 259 | /* Register rw_pc_dout, scope gio, type rw */ | ||
| 260 | typedef struct { | ||
| 261 | unsigned int data : 16; | ||
| 262 | unsigned int dummy1 : 16; | ||
| 263 | } reg_gio_rw_pc_dout; | ||
| 264 | #define REG_RD_ADDR_gio_rw_pc_dout 92 | ||
| 265 | #define REG_WR_ADDR_gio_rw_pc_dout 92 | ||
| 266 | |||
| 267 | /* Register rw_pc_oe, scope gio, type rw */ | ||
| 268 | typedef struct { | ||
| 269 | unsigned int oe : 16; | ||
| 270 | unsigned int dummy1 : 16; | ||
| 271 | } reg_gio_rw_pc_oe; | ||
| 272 | #define REG_RD_ADDR_gio_rw_pc_oe 96 | ||
| 273 | #define REG_WR_ADDR_gio_rw_pc_oe 96 | ||
| 274 | |||
| 275 | /* Register rw_pc_byte0_dout, scope gio, type rw */ | ||
| 276 | typedef struct { | ||
| 277 | unsigned int data : 8; | ||
| 278 | unsigned int dummy1 : 24; | ||
| 279 | } reg_gio_rw_pc_byte0_dout; | ||
| 280 | #define REG_RD_ADDR_gio_rw_pc_byte0_dout 100 | ||
| 281 | #define REG_WR_ADDR_gio_rw_pc_byte0_dout 100 | ||
| 282 | |||
| 283 | /* Register rw_pc_byte0_oe, scope gio, type rw */ | ||
| 284 | typedef struct { | ||
| 285 | unsigned int oe : 8; | ||
| 286 | unsigned int dummy1 : 24; | ||
| 287 | } reg_gio_rw_pc_byte0_oe; | ||
| 288 | #define REG_RD_ADDR_gio_rw_pc_byte0_oe 104 | ||
| 289 | #define REG_WR_ADDR_gio_rw_pc_byte0_oe 104 | ||
| 290 | |||
| 291 | /* Register rw_pc_byte1_dout, scope gio, type rw */ | ||
| 292 | typedef struct { | ||
| 293 | unsigned int data : 8; | ||
| 294 | unsigned int dummy1 : 24; | ||
| 295 | } reg_gio_rw_pc_byte1_dout; | ||
| 296 | #define REG_RD_ADDR_gio_rw_pc_byte1_dout 108 | ||
| 297 | #define REG_WR_ADDR_gio_rw_pc_byte1_dout 108 | ||
| 298 | |||
| 299 | /* Register rw_pc_byte1_oe, scope gio, type rw */ | ||
| 300 | typedef struct { | ||
| 301 | unsigned int oe : 8; | ||
| 302 | unsigned int dummy1 : 24; | ||
| 303 | } reg_gio_rw_pc_byte1_oe; | ||
| 304 | #define REG_RD_ADDR_gio_rw_pc_byte1_oe 112 | ||
| 305 | #define REG_WR_ADDR_gio_rw_pc_byte1_oe 112 | ||
| 306 | |||
| 307 | /* Register r_pd_din, scope gio, type r */ | ||
| 308 | typedef struct { | ||
| 309 | unsigned int data : 32; | ||
| 310 | } reg_gio_r_pd_din; | ||
| 311 | #define REG_RD_ADDR_gio_r_pd_din 116 | ||
| 312 | |||
| 313 | /* Register rw_intr_cfg, scope gio, type rw */ | ||
| 314 | typedef struct { | ||
| 315 | unsigned int intr0 : 3; | ||
| 316 | unsigned int intr1 : 3; | ||
| 317 | unsigned int intr2 : 3; | ||
| 318 | unsigned int intr3 : 3; | ||
| 319 | unsigned int intr4 : 3; | ||
| 320 | unsigned int intr5 : 3; | ||
| 321 | unsigned int intr6 : 3; | ||
| 322 | unsigned int intr7 : 3; | ||
| 323 | unsigned int dummy1 : 8; | ||
| 324 | } reg_gio_rw_intr_cfg; | ||
| 325 | #define REG_RD_ADDR_gio_rw_intr_cfg 120 | ||
| 326 | #define REG_WR_ADDR_gio_rw_intr_cfg 120 | ||
| 327 | |||
| 328 | /* Register rw_intr_pins, scope gio, type rw */ | ||
| 329 | typedef struct { | ||
| 330 | unsigned int intr0 : 4; | ||
| 331 | unsigned int intr1 : 4; | ||
| 332 | unsigned int intr2 : 4; | ||
| 333 | unsigned int intr3 : 4; | ||
| 334 | unsigned int intr4 : 4; | ||
| 335 | unsigned int intr5 : 4; | ||
| 336 | unsigned int intr6 : 4; | ||
| 337 | unsigned int intr7 : 4; | ||
| 338 | } reg_gio_rw_intr_pins; | ||
| 339 | #define REG_RD_ADDR_gio_rw_intr_pins 124 | ||
| 340 | #define REG_WR_ADDR_gio_rw_intr_pins 124 | ||
| 341 | |||
| 342 | /* Register rw_intr_mask, scope gio, type rw */ | ||
| 343 | typedef struct { | ||
| 344 | unsigned int intr0 : 1; | ||
| 345 | unsigned int intr1 : 1; | ||
| 346 | unsigned int intr2 : 1; | ||
| 347 | unsigned int intr3 : 1; | ||
| 348 | unsigned int intr4 : 1; | ||
| 349 | unsigned int intr5 : 1; | ||
| 350 | unsigned int intr6 : 1; | ||
| 351 | unsigned int intr7 : 1; | ||
| 352 | unsigned int i2c0_done : 1; | ||
| 353 | unsigned int i2c1_done : 1; | ||
| 354 | unsigned int dummy1 : 22; | ||
| 355 | } reg_gio_rw_intr_mask; | ||
| 356 | #define REG_RD_ADDR_gio_rw_intr_mask 128 | ||
| 357 | #define REG_WR_ADDR_gio_rw_intr_mask 128 | ||
| 358 | |||
| 359 | /* Register rw_ack_intr, scope gio, type rw */ | ||
| 360 | typedef struct { | ||
| 361 | unsigned int intr0 : 1; | ||
| 362 | unsigned int intr1 : 1; | ||
| 363 | unsigned int intr2 : 1; | ||
| 364 | unsigned int intr3 : 1; | ||
| 365 | unsigned int intr4 : 1; | ||
| 366 | unsigned int intr5 : 1; | ||
| 367 | unsigned int intr6 : 1; | ||
| 368 | unsigned int intr7 : 1; | ||
| 369 | unsigned int i2c0_done : 1; | ||
| 370 | unsigned int i2c1_done : 1; | ||
| 371 | unsigned int dummy1 : 22; | ||
| 372 | } reg_gio_rw_ack_intr; | ||
| 373 | #define REG_RD_ADDR_gio_rw_ack_intr 132 | ||
| 374 | #define REG_WR_ADDR_gio_rw_ack_intr 132 | ||
| 375 | |||
| 376 | /* Register r_intr, scope gio, type r */ | ||
| 377 | typedef struct { | ||
| 378 | unsigned int intr0 : 1; | ||
| 379 | unsigned int intr1 : 1; | ||
| 380 | unsigned int intr2 : 1; | ||
| 381 | unsigned int intr3 : 1; | ||
| 382 | unsigned int intr4 : 1; | ||
| 383 | unsigned int intr5 : 1; | ||
| 384 | unsigned int intr6 : 1; | ||
| 385 | unsigned int intr7 : 1; | ||
| 386 | unsigned int i2c0_done : 1; | ||
| 387 | unsigned int i2c1_done : 1; | ||
| 388 | unsigned int dummy1 : 22; | ||
| 389 | } reg_gio_r_intr; | ||
| 390 | #define REG_RD_ADDR_gio_r_intr 136 | ||
| 391 | |||
| 392 | /* Register r_masked_intr, scope gio, type r */ | ||
| 393 | typedef struct { | ||
| 394 | unsigned int intr0 : 1; | ||
| 395 | unsigned int intr1 : 1; | ||
| 396 | unsigned int intr2 : 1; | ||
| 397 | unsigned int intr3 : 1; | ||
| 398 | unsigned int intr4 : 1; | ||
| 399 | unsigned int intr5 : 1; | ||
| 400 | unsigned int intr6 : 1; | ||
| 401 | unsigned int intr7 : 1; | ||
| 402 | unsigned int i2c0_done : 1; | ||
| 403 | unsigned int i2c1_done : 1; | ||
| 404 | unsigned int dummy1 : 22; | ||
| 405 | } reg_gio_r_masked_intr; | ||
| 406 | #define REG_RD_ADDR_gio_r_masked_intr 140 | ||
| 407 | |||
| 408 | /* Register rw_i2c0_start, scope gio, type rw */ | ||
| 409 | typedef struct { | ||
| 410 | unsigned int run : 1; | ||
| 411 | unsigned int dummy1 : 31; | ||
| 412 | } reg_gio_rw_i2c0_start; | ||
| 413 | #define REG_RD_ADDR_gio_rw_i2c0_start 144 | ||
| 414 | #define REG_WR_ADDR_gio_rw_i2c0_start 144 | ||
| 415 | |||
| 416 | /* Register rw_i2c0_cfg, scope gio, type rw */ | ||
| 417 | typedef struct { | ||
| 418 | unsigned int en : 1; | ||
| 419 | unsigned int bit_order : 1; | ||
| 420 | unsigned int scl_io : 1; | ||
| 421 | unsigned int scl_inv : 1; | ||
| 422 | unsigned int sda_io : 1; | ||
| 423 | unsigned int sda_idle : 1; | ||
| 424 | unsigned int dummy1 : 26; | ||
| 425 | } reg_gio_rw_i2c0_cfg; | ||
| 426 | #define REG_RD_ADDR_gio_rw_i2c0_cfg 148 | ||
| 427 | #define REG_WR_ADDR_gio_rw_i2c0_cfg 148 | ||
| 428 | |||
| 429 | /* Register rw_i2c0_ctrl, scope gio, type rw */ | ||
| 430 | typedef struct { | ||
| 431 | unsigned int trf_bits : 6; | ||
| 432 | unsigned int switch_dir : 6; | ||
| 433 | unsigned int extra_start : 3; | ||
| 434 | unsigned int early_end : 1; | ||
| 435 | unsigned int start_stop : 1; | ||
| 436 | unsigned int ack_dir0 : 1; | ||
| 437 | unsigned int ack_dir1 : 1; | ||
| 438 | unsigned int ack_dir2 : 1; | ||
| 439 | unsigned int ack_dir3 : 1; | ||
| 440 | unsigned int ack_dir4 : 1; | ||
| 441 | unsigned int ack_dir5 : 1; | ||
| 442 | unsigned int ack_bit : 1; | ||
| 443 | unsigned int start_bit : 1; | ||
| 444 | unsigned int freq : 2; | ||
| 445 | unsigned int dummy1 : 5; | ||
| 446 | } reg_gio_rw_i2c0_ctrl; | ||
| 447 | #define REG_RD_ADDR_gio_rw_i2c0_ctrl 152 | ||
| 448 | #define REG_WR_ADDR_gio_rw_i2c0_ctrl 152 | ||
| 449 | |||
| 450 | /* Register rw_i2c0_data, scope gio, type rw */ | ||
| 451 | typedef struct { | ||
| 452 | unsigned int data0 : 8; | ||
| 453 | unsigned int data1 : 8; | ||
| 454 | unsigned int data2 : 8; | ||
| 455 | unsigned int data3 : 8; | ||
| 456 | } reg_gio_rw_i2c0_data; | ||
| 457 | #define REG_RD_ADDR_gio_rw_i2c0_data 156 | ||
| 458 | #define REG_WR_ADDR_gio_rw_i2c0_data 156 | ||
| 459 | |||
| 460 | /* Register rw_i2c0_data2, scope gio, type rw */ | ||
| 461 | typedef struct { | ||
| 462 | unsigned int data4 : 8; | ||
| 463 | unsigned int data5 : 8; | ||
| 464 | unsigned int start_val : 6; | ||
| 465 | unsigned int ack_val : 6; | ||
| 466 | unsigned int dummy1 : 4; | ||
| 467 | } reg_gio_rw_i2c0_data2; | ||
| 468 | #define REG_RD_ADDR_gio_rw_i2c0_data2 160 | ||
| 469 | #define REG_WR_ADDR_gio_rw_i2c0_data2 160 | ||
| 470 | |||
| 471 | /* Register rw_i2c1_start, scope gio, type rw */ | ||
| 472 | typedef struct { | ||
| 473 | unsigned int run : 1; | ||
| 474 | unsigned int dummy1 : 31; | ||
| 475 | } reg_gio_rw_i2c1_start; | ||
| 476 | #define REG_RD_ADDR_gio_rw_i2c1_start 164 | ||
| 477 | #define REG_WR_ADDR_gio_rw_i2c1_start 164 | ||
| 478 | |||
| 479 | /* Register rw_i2c1_cfg, scope gio, type rw */ | ||
| 480 | typedef struct { | ||
| 481 | unsigned int en : 1; | ||
| 482 | unsigned int bit_order : 1; | ||
| 483 | unsigned int scl_io : 1; | ||
| 484 | unsigned int scl_inv : 1; | ||
| 485 | unsigned int sda0_io : 1; | ||
| 486 | unsigned int sda0_idle : 1; | ||
| 487 | unsigned int sda1_io : 1; | ||
| 488 | unsigned int sda1_idle : 1; | ||
| 489 | unsigned int sda2_io : 1; | ||
| 490 | unsigned int sda2_idle : 1; | ||
| 491 | unsigned int sda3_io : 1; | ||
| 492 | unsigned int sda3_idle : 1; | ||
| 493 | unsigned int sda_sel : 2; | ||
| 494 | unsigned int sen_idle : 1; | ||
| 495 | unsigned int sen_inv : 1; | ||
| 496 | unsigned int sen_sel : 2; | ||
| 497 | unsigned int dummy1 : 14; | ||
| 498 | } reg_gio_rw_i2c1_cfg; | ||
| 499 | #define REG_RD_ADDR_gio_rw_i2c1_cfg 168 | ||
| 500 | #define REG_WR_ADDR_gio_rw_i2c1_cfg 168 | ||
| 501 | |||
| 502 | /* Register rw_i2c1_ctrl, scope gio, type rw */ | ||
| 503 | typedef struct { | ||
| 504 | unsigned int trf_bits : 6; | ||
| 505 | unsigned int switch_dir : 6; | ||
| 506 | unsigned int extra_start : 3; | ||
| 507 | unsigned int early_end : 1; | ||
| 508 | unsigned int start_stop : 1; | ||
| 509 | unsigned int ack_dir0 : 1; | ||
| 510 | unsigned int ack_dir1 : 1; | ||
| 511 | unsigned int ack_dir2 : 1; | ||
| 512 | unsigned int ack_dir3 : 1; | ||
| 513 | unsigned int ack_dir4 : 1; | ||
| 514 | unsigned int ack_dir5 : 1; | ||
| 515 | unsigned int ack_bit : 1; | ||
| 516 | unsigned int start_bit : 1; | ||
| 517 | unsigned int freq : 2; | ||
| 518 | unsigned int dummy1 : 5; | ||
| 519 | } reg_gio_rw_i2c1_ctrl; | ||
| 520 | #define REG_RD_ADDR_gio_rw_i2c1_ctrl 172 | ||
| 521 | #define REG_WR_ADDR_gio_rw_i2c1_ctrl 172 | ||
| 522 | |||
| 523 | /* Register rw_i2c1_data, scope gio, type rw */ | ||
| 524 | typedef struct { | ||
| 525 | unsigned int data0 : 8; | ||
| 526 | unsigned int data1 : 8; | ||
| 527 | unsigned int data2 : 8; | ||
| 528 | unsigned int data3 : 8; | ||
| 529 | } reg_gio_rw_i2c1_data; | ||
| 530 | #define REG_RD_ADDR_gio_rw_i2c1_data 176 | ||
| 531 | #define REG_WR_ADDR_gio_rw_i2c1_data 176 | ||
| 532 | |||
| 533 | /* Register rw_i2c1_data2, scope gio, type rw */ | ||
| 534 | typedef struct { | ||
| 535 | unsigned int data4 : 8; | ||
| 536 | unsigned int data5 : 8; | ||
| 537 | unsigned int start_val : 6; | ||
| 538 | unsigned int ack_val : 6; | ||
| 539 | unsigned int dummy1 : 4; | ||
| 540 | } reg_gio_rw_i2c1_data2; | ||
| 541 | #define REG_RD_ADDR_gio_rw_i2c1_data2 180 | ||
| 542 | #define REG_WR_ADDR_gio_rw_i2c1_data2 180 | ||
| 543 | |||
| 544 | /* Register r_ppwm_stat, scope gio, type r */ | ||
| 545 | typedef struct { | ||
| 546 | unsigned int freq : 2; | ||
| 547 | unsigned int dummy1 : 30; | ||
| 548 | } reg_gio_r_ppwm_stat; | ||
| 549 | #define REG_RD_ADDR_gio_r_ppwm_stat 184 | ||
| 550 | |||
| 551 | /* Register rw_ppwm_data, scope gio, type rw */ | ||
| 552 | typedef struct { | ||
| 553 | unsigned int data : 8; | ||
| 554 | unsigned int dummy1 : 24; | ||
| 555 | } reg_gio_rw_ppwm_data; | ||
| 556 | #define REG_RD_ADDR_gio_rw_ppwm_data 188 | ||
| 557 | #define REG_WR_ADDR_gio_rw_ppwm_data 188 | ||
| 558 | |||
| 559 | /* Register rw_pwm0_ctrl, scope gio, type rw */ | ||
| 560 | typedef struct { | ||
| 561 | unsigned int mode : 2; | ||
| 562 | unsigned int ccd_override : 1; | ||
| 563 | unsigned int ccd_val : 1; | ||
| 564 | unsigned int dummy1 : 28; | ||
| 565 | } reg_gio_rw_pwm0_ctrl; | ||
| 566 | #define REG_RD_ADDR_gio_rw_pwm0_ctrl 192 | ||
| 567 | #define REG_WR_ADDR_gio_rw_pwm0_ctrl 192 | ||
| 568 | |||
| 569 | /* Register rw_pwm0_var, scope gio, type rw */ | ||
| 570 | typedef struct { | ||
| 571 | unsigned int lo : 13; | ||
| 572 | unsigned int hi : 13; | ||
| 573 | unsigned int dummy1 : 6; | ||
| 574 | } reg_gio_rw_pwm0_var; | ||
| 575 | #define REG_RD_ADDR_gio_rw_pwm0_var 196 | ||
| 576 | #define REG_WR_ADDR_gio_rw_pwm0_var 196 | ||
| 577 | |||
| 578 | /* Register rw_pwm0_data, scope gio, type rw */ | ||
| 579 | typedef struct { | ||
| 580 | unsigned int data : 8; | ||
| 581 | unsigned int dummy1 : 24; | ||
| 582 | } reg_gio_rw_pwm0_data; | ||
| 583 | #define REG_RD_ADDR_gio_rw_pwm0_data 200 | ||
| 584 | #define REG_WR_ADDR_gio_rw_pwm0_data 200 | ||
| 585 | |||
| 586 | /* Register rw_pwm1_ctrl, scope gio, type rw */ | ||
| 587 | typedef struct { | ||
| 588 | unsigned int mode : 2; | ||
| 589 | unsigned int ccd_override : 1; | ||
| 590 | unsigned int ccd_val : 1; | ||
| 591 | unsigned int dummy1 : 28; | ||
| 592 | } reg_gio_rw_pwm1_ctrl; | ||
| 593 | #define REG_RD_ADDR_gio_rw_pwm1_ctrl 204 | ||
| 594 | #define REG_WR_ADDR_gio_rw_pwm1_ctrl 204 | ||
| 595 | |||
| 596 | /* Register rw_pwm1_var, scope gio, type rw */ | ||
| 597 | typedef struct { | ||
| 598 | unsigned int lo : 13; | ||
| 599 | unsigned int hi : 13; | ||
| 600 | unsigned int dummy1 : 6; | ||
| 601 | } reg_gio_rw_pwm1_var; | ||
| 602 | #define REG_RD_ADDR_gio_rw_pwm1_var 208 | ||
| 603 | #define REG_WR_ADDR_gio_rw_pwm1_var 208 | ||
| 604 | |||
| 605 | /* Register rw_pwm1_data, scope gio, type rw */ | ||
| 606 | typedef struct { | ||
| 607 | unsigned int data : 8; | ||
| 608 | unsigned int dummy1 : 24; | ||
| 609 | } reg_gio_rw_pwm1_data; | ||
| 610 | #define REG_RD_ADDR_gio_rw_pwm1_data 212 | ||
| 611 | #define REG_WR_ADDR_gio_rw_pwm1_data 212 | ||
| 612 | |||
| 613 | /* Register rw_pwm2_ctrl, scope gio, type rw */ | ||
| 614 | typedef struct { | ||
| 615 | unsigned int mode : 2; | ||
| 616 | unsigned int ccd_override : 1; | ||
| 617 | unsigned int ccd_val : 1; | ||
| 618 | unsigned int dummy1 : 28; | ||
| 619 | } reg_gio_rw_pwm2_ctrl; | ||
| 620 | #define REG_RD_ADDR_gio_rw_pwm2_ctrl 216 | ||
| 621 | #define REG_WR_ADDR_gio_rw_pwm2_ctrl 216 | ||
| 622 | |||
| 623 | /* Register rw_pwm2_var, scope gio, type rw */ | ||
| 624 | typedef struct { | ||
| 625 | unsigned int lo : 13; | ||
| 626 | unsigned int hi : 13; | ||
| 627 | unsigned int dummy1 : 6; | ||
| 628 | } reg_gio_rw_pwm2_var; | ||
| 629 | #define REG_RD_ADDR_gio_rw_pwm2_var 220 | ||
| 630 | #define REG_WR_ADDR_gio_rw_pwm2_var 220 | ||
| 631 | |||
| 632 | /* Register rw_pwm2_data, scope gio, type rw */ | ||
| 633 | typedef struct { | ||
| 634 | unsigned int data : 8; | ||
| 635 | unsigned int dummy1 : 24; | ||
| 636 | } reg_gio_rw_pwm2_data; | ||
| 637 | #define REG_RD_ADDR_gio_rw_pwm2_data 224 | ||
| 638 | #define REG_WR_ADDR_gio_rw_pwm2_data 224 | ||
| 639 | |||
| 640 | /* Register rw_pwm_in_cfg, scope gio, type rw */ | ||
| 641 | typedef struct { | ||
| 642 | unsigned int pin : 3; | ||
| 643 | unsigned int dummy1 : 29; | ||
| 644 | } reg_gio_rw_pwm_in_cfg; | ||
| 645 | #define REG_RD_ADDR_gio_rw_pwm_in_cfg 228 | ||
| 646 | #define REG_WR_ADDR_gio_rw_pwm_in_cfg 228 | ||
| 647 | |||
| 648 | /* Register r_pwm_in_lo, scope gio, type r */ | ||
| 649 | typedef struct { | ||
| 650 | unsigned int data : 32; | ||
| 651 | } reg_gio_r_pwm_in_lo; | ||
| 652 | #define REG_RD_ADDR_gio_r_pwm_in_lo 232 | ||
| 653 | |||
| 654 | /* Register r_pwm_in_hi, scope gio, type r */ | ||
| 655 | typedef struct { | ||
| 656 | unsigned int data : 32; | ||
| 657 | } reg_gio_r_pwm_in_hi; | ||
| 658 | #define REG_RD_ADDR_gio_r_pwm_in_hi 236 | ||
| 659 | |||
| 660 | /* Register r_pwm_in_cnt, scope gio, type r */ | ||
| 661 | typedef struct { | ||
| 662 | unsigned int data : 32; | ||
| 663 | } reg_gio_r_pwm_in_cnt; | ||
| 664 | #define REG_RD_ADDR_gio_r_pwm_in_cnt 240 | ||
| 665 | |||
| 666 | |||
| 667 | /* Constants */ | ||
| 668 | enum { | ||
| 669 | regk_gio_anyedge = 0x00000007, | ||
| 670 | regk_gio_f100k = 0x00000000, | ||
| 671 | regk_gio_f1562 = 0x00000000, | ||
| 672 | regk_gio_f195 = 0x00000003, | ||
| 673 | regk_gio_f1m = 0x00000002, | ||
| 674 | regk_gio_f390 = 0x00000002, | ||
| 675 | regk_gio_f400k = 0x00000001, | ||
| 676 | regk_gio_f5m = 0x00000003, | ||
| 677 | regk_gio_f781 = 0x00000001, | ||
| 678 | regk_gio_hi = 0x00000001, | ||
| 679 | regk_gio_in = 0x00000000, | ||
| 680 | regk_gio_intr_pa0 = 0x00000000, | ||
| 681 | regk_gio_intr_pa1 = 0x00000000, | ||
| 682 | regk_gio_intr_pa10 = 0x00000001, | ||
| 683 | regk_gio_intr_pa11 = 0x00000001, | ||
| 684 | regk_gio_intr_pa12 = 0x00000001, | ||
| 685 | regk_gio_intr_pa13 = 0x00000001, | ||
| 686 | regk_gio_intr_pa14 = 0x00000001, | ||
| 687 | regk_gio_intr_pa15 = 0x00000001, | ||
| 688 | regk_gio_intr_pa16 = 0x00000002, | ||
| 689 | regk_gio_intr_pa17 = 0x00000002, | ||
| 690 | regk_gio_intr_pa18 = 0x00000002, | ||
| 691 | regk_gio_intr_pa19 = 0x00000002, | ||
| 692 | regk_gio_intr_pa2 = 0x00000000, | ||
| 693 | regk_gio_intr_pa20 = 0x00000002, | ||
| 694 | regk_gio_intr_pa21 = 0x00000002, | ||
| 695 | regk_gio_intr_pa22 = 0x00000002, | ||
| 696 | regk_gio_intr_pa23 = 0x00000002, | ||
| 697 | regk_gio_intr_pa24 = 0x00000003, | ||
| 698 | regk_gio_intr_pa25 = 0x00000003, | ||
| 699 | regk_gio_intr_pa26 = 0x00000003, | ||
| 700 | regk_gio_intr_pa27 = 0x00000003, | ||
| 701 | regk_gio_intr_pa28 = 0x00000003, | ||
| 702 | regk_gio_intr_pa29 = 0x00000003, | ||
| 703 | regk_gio_intr_pa3 = 0x00000000, | ||
| 704 | regk_gio_intr_pa30 = 0x00000003, | ||
| 705 | regk_gio_intr_pa31 = 0x00000003, | ||
| 706 | regk_gio_intr_pa4 = 0x00000000, | ||
| 707 | regk_gio_intr_pa5 = 0x00000000, | ||
| 708 | regk_gio_intr_pa6 = 0x00000000, | ||
| 709 | regk_gio_intr_pa7 = 0x00000000, | ||
| 710 | regk_gio_intr_pa8 = 0x00000001, | ||
| 711 | regk_gio_intr_pa9 = 0x00000001, | ||
| 712 | regk_gio_intr_pb0 = 0x00000004, | ||
| 713 | regk_gio_intr_pb1 = 0x00000004, | ||
| 714 | regk_gio_intr_pb10 = 0x00000005, | ||
| 715 | regk_gio_intr_pb11 = 0x00000005, | ||
| 716 | regk_gio_intr_pb12 = 0x00000005, | ||
| 717 | regk_gio_intr_pb13 = 0x00000005, | ||
| 718 | regk_gio_intr_pb14 = 0x00000005, | ||
| 719 | regk_gio_intr_pb15 = 0x00000005, | ||
| 720 | regk_gio_intr_pb16 = 0x00000006, | ||
| 721 | regk_gio_intr_pb17 = 0x00000006, | ||
| 722 | regk_gio_intr_pb18 = 0x00000006, | ||
| 723 | regk_gio_intr_pb19 = 0x00000006, | ||
| 724 | regk_gio_intr_pb2 = 0x00000004, | ||
| 725 | regk_gio_intr_pb20 = 0x00000006, | ||
| 726 | regk_gio_intr_pb21 = 0x00000006, | ||
| 727 | regk_gio_intr_pb22 = 0x00000006, | ||
| 728 | regk_gio_intr_pb23 = 0x00000006, | ||
| 729 | regk_gio_intr_pb24 = 0x00000007, | ||
| 730 | regk_gio_intr_pb25 = 0x00000007, | ||
| 731 | regk_gio_intr_pb26 = 0x00000007, | ||
| 732 | regk_gio_intr_pb27 = 0x00000007, | ||
| 733 | regk_gio_intr_pb28 = 0x00000007, | ||
| 734 | regk_gio_intr_pb29 = 0x00000007, | ||
| 735 | regk_gio_intr_pb3 = 0x00000004, | ||
| 736 | regk_gio_intr_pb30 = 0x00000007, | ||
| 737 | regk_gio_intr_pb31 = 0x00000007, | ||
| 738 | regk_gio_intr_pb4 = 0x00000004, | ||
| 739 | regk_gio_intr_pb5 = 0x00000004, | ||
| 740 | regk_gio_intr_pb6 = 0x00000004, | ||
| 741 | regk_gio_intr_pb7 = 0x00000004, | ||
| 742 | regk_gio_intr_pb8 = 0x00000005, | ||
| 743 | regk_gio_intr_pb9 = 0x00000005, | ||
| 744 | regk_gio_intr_pc0 = 0x00000008, | ||
| 745 | regk_gio_intr_pc1 = 0x00000008, | ||
| 746 | regk_gio_intr_pc10 = 0x00000009, | ||
| 747 | regk_gio_intr_pc11 = 0x00000009, | ||
| 748 | regk_gio_intr_pc12 = 0x00000009, | ||
| 749 | regk_gio_intr_pc13 = 0x00000009, | ||
| 750 | regk_gio_intr_pc14 = 0x00000009, | ||
| 751 | regk_gio_intr_pc15 = 0x00000009, | ||
| 752 | regk_gio_intr_pc2 = 0x00000008, | ||
| 753 | regk_gio_intr_pc3 = 0x00000008, | ||
| 754 | regk_gio_intr_pc4 = 0x00000008, | ||
| 755 | regk_gio_intr_pc5 = 0x00000008, | ||
| 756 | regk_gio_intr_pc6 = 0x00000008, | ||
| 757 | regk_gio_intr_pc7 = 0x00000008, | ||
| 758 | regk_gio_intr_pc8 = 0x00000009, | ||
| 759 | regk_gio_intr_pc9 = 0x00000009, | ||
| 760 | regk_gio_intr_pd0 = 0x0000000c, | ||
| 761 | regk_gio_intr_pd1 = 0x0000000c, | ||
| 762 | regk_gio_intr_pd10 = 0x0000000d, | ||
| 763 | regk_gio_intr_pd11 = 0x0000000d, | ||
| 764 | regk_gio_intr_pd12 = 0x0000000d, | ||
| 765 | regk_gio_intr_pd13 = 0x0000000d, | ||
| 766 | regk_gio_intr_pd14 = 0x0000000d, | ||
| 767 | regk_gio_intr_pd15 = 0x0000000d, | ||
| 768 | regk_gio_intr_pd16 = 0x0000000e, | ||
| 769 | regk_gio_intr_pd17 = 0x0000000e, | ||
| 770 | regk_gio_intr_pd18 = 0x0000000e, | ||
| 771 | regk_gio_intr_pd19 = 0x0000000e, | ||
| 772 | regk_gio_intr_pd2 = 0x0000000c, | ||
| 773 | regk_gio_intr_pd20 = 0x0000000e, | ||
| 774 | regk_gio_intr_pd21 = 0x0000000e, | ||
| 775 | regk_gio_intr_pd22 = 0x0000000e, | ||
| 776 | regk_gio_intr_pd23 = 0x0000000e, | ||
| 777 | regk_gio_intr_pd24 = 0x0000000f, | ||
| 778 | regk_gio_intr_pd25 = 0x0000000f, | ||
| 779 | regk_gio_intr_pd26 = 0x0000000f, | ||
| 780 | regk_gio_intr_pd27 = 0x0000000f, | ||
| 781 | regk_gio_intr_pd28 = 0x0000000f, | ||
| 782 | regk_gio_intr_pd29 = 0x0000000f, | ||
| 783 | regk_gio_intr_pd3 = 0x0000000c, | ||
| 784 | regk_gio_intr_pd30 = 0x0000000f, | ||
| 785 | regk_gio_intr_pd31 = 0x0000000f, | ||
| 786 | regk_gio_intr_pd4 = 0x0000000c, | ||
| 787 | regk_gio_intr_pd5 = 0x0000000c, | ||
| 788 | regk_gio_intr_pd6 = 0x0000000c, | ||
| 789 | regk_gio_intr_pd7 = 0x0000000c, | ||
| 790 | regk_gio_intr_pd8 = 0x0000000d, | ||
| 791 | regk_gio_intr_pd9 = 0x0000000d, | ||
| 792 | regk_gio_lo = 0x00000002, | ||
| 793 | regk_gio_lsb = 0x00000000, | ||
| 794 | regk_gio_msb = 0x00000001, | ||
| 795 | regk_gio_negedge = 0x00000006, | ||
| 796 | regk_gio_no = 0x00000000, | ||
| 797 | regk_gio_no_switch = 0x0000003f, | ||
| 798 | regk_gio_none = 0x00000007, | ||
| 799 | regk_gio_off = 0x00000000, | ||
| 800 | regk_gio_opendrain = 0x00000000, | ||
| 801 | regk_gio_out = 0x00000001, | ||
| 802 | regk_gio_posedge = 0x00000005, | ||
| 803 | regk_gio_pwm_hfp = 0x00000002, | ||
| 804 | regk_gio_pwm_pa0 = 0x00000001, | ||
| 805 | regk_gio_pwm_pa19 = 0x00000004, | ||
| 806 | regk_gio_pwm_pa6 = 0x00000002, | ||
| 807 | regk_gio_pwm_pa7 = 0x00000003, | ||
| 808 | regk_gio_pwm_pb26 = 0x00000005, | ||
| 809 | regk_gio_pwm_pd23 = 0x00000006, | ||
| 810 | regk_gio_pwm_pd31 = 0x00000007, | ||
| 811 | regk_gio_pwm_std = 0x00000001, | ||
| 812 | regk_gio_pwm_var = 0x00000003, | ||
| 813 | regk_gio_rw_i2c0_cfg_default = 0x00000020, | ||
| 814 | regk_gio_rw_i2c0_ctrl_default = 0x00010000, | ||
| 815 | regk_gio_rw_i2c0_start_default = 0x00000000, | ||
| 816 | regk_gio_rw_i2c1_cfg_default = 0x00000aa0, | ||
| 817 | regk_gio_rw_i2c1_ctrl_default = 0x00010000, | ||
| 818 | regk_gio_rw_i2c1_start_default = 0x00000000, | ||
| 819 | regk_gio_rw_intr_cfg_default = 0x00000000, | ||
| 820 | regk_gio_rw_intr_mask_default = 0x00000000, | ||
| 821 | regk_gio_rw_pa_oe_default = 0x00000000, | ||
| 822 | regk_gio_rw_pb_oe_default = 0x00000000, | ||
| 823 | regk_gio_rw_pc_oe_default = 0x00000000, | ||
| 824 | regk_gio_rw_ppwm_data_default = 0x00000000, | ||
| 825 | regk_gio_rw_pwm0_ctrl_default = 0x00000000, | ||
| 826 | regk_gio_rw_pwm1_ctrl_default = 0x00000000, | ||
| 827 | regk_gio_rw_pwm2_ctrl_default = 0x00000000, | ||
| 828 | regk_gio_rw_pwm_in_cfg_default = 0x00000000, | ||
| 829 | regk_gio_sda0 = 0x00000000, | ||
| 830 | regk_gio_sda1 = 0x00000001, | ||
| 831 | regk_gio_sda2 = 0x00000002, | ||
| 832 | regk_gio_sda3 = 0x00000003, | ||
| 833 | regk_gio_sen = 0x00000000, | ||
| 834 | regk_gio_set = 0x00000003, | ||
| 835 | regk_gio_yes = 0x00000001 | ||
| 836 | }; | ||
| 837 | #endif /* __gio_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h new file mode 100644 index 000000000000..bea699aa480e --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr | ||
| 2 | from intr_vect.r */ | ||
| 3 | |||
| 4 | #ifndef _INTR_VECT_R | ||
| 5 | #define _INTR_VECT_R | ||
| 6 | #define TIMER0_INTR_VECT 0x31 | ||
| 7 | #define TIMER1_INTR_VECT 0x32 | ||
| 8 | #define DMA0_INTR_VECT 0x33 | ||
| 9 | #define DMA1_INTR_VECT 0x34 | ||
| 10 | #define DMA2_INTR_VECT 0x35 | ||
| 11 | #define DMA3_INTR_VECT 0x36 | ||
| 12 | #define DMA4_INTR_VECT 0x37 | ||
| 13 | #define DMA5_INTR_VECT 0x38 | ||
| 14 | #define DMA6_INTR_VECT 0x39 | ||
| 15 | #define DMA7_INTR_VECT 0x3a | ||
| 16 | #define DMA9_INTR_VECT 0x3b | ||
| 17 | #define DMA11_INTR_VECT 0x3c | ||
| 18 | #define GIO_INTR_VECT 0x3d | ||
| 19 | #define IOP0_INTR_VECT 0x3e | ||
| 20 | #define IOP1_INTR_VECT 0x3f | ||
| 21 | #define SER0_INTR_VECT 0x40 | ||
| 22 | #define SER1_INTR_VECT 0x41 | ||
| 23 | #define SER2_INTR_VECT 0x42 | ||
| 24 | #define SER3_INTR_VECT 0x43 | ||
| 25 | #define SER4_INTR_VECT 0x44 | ||
| 26 | #define SSER_INTR_VECT 0x45 | ||
| 27 | #define STRDMA0_INTR_VECT 0x46 | ||
| 28 | #define STRDMA1_INTR_VECT 0x47 | ||
| 29 | #define STRDMA2_INTR_VECT 0x48 | ||
| 30 | #define STRDMA3_INTR_VECT 0x49 | ||
| 31 | #define STRDMA5_INTR_VECT 0x4a | ||
| 32 | #define VIN_INTR_VECT 0x4b | ||
| 33 | #define VOUT_INTR_VECT 0x4c | ||
| 34 | #define JPEG_INTR_VECT 0x4d | ||
| 35 | #define H264_INTR_VECT 0x4e | ||
| 36 | #define HISTO_INTR_VECT 0x4f | ||
| 37 | #define CCD_INTR_VECT 0x50 | ||
| 38 | #define ETH_INTR_VECT 0x51 | ||
| 39 | #define MEMARB_BAR_INTR_VECT 0x52 | ||
| 40 | #define MEMARB_FOO_INTR_VECT 0x53 | ||
| 41 | #define PIO_INTR_VECT 0x54 | ||
| 42 | #define SCLR_INTR_VECT 0x55 | ||
| 43 | #define SCLR_FIFO_INTR_VECT 0x56 | ||
| 44 | #define IPI_INTR_VECT 0x57 | ||
| 45 | #define NBR_INTR_VECT 0x58 | ||
| 46 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h new file mode 100644 index 000000000000..b820f6347c74 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h | |||
| @@ -0,0 +1,341 @@ | |||
| 1 | #ifndef __intr_vect_defs_h | ||
| 2 | #define __intr_vect_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: intr_vect.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope intr_vect */ | ||
| 83 | |||
| 84 | |||
| 85 | #define STRIDE_intr_vect_rw_mask 4 | ||
| 86 | /* Register rw_mask0, scope intr_vect, type rw */ | ||
| 87 | typedef struct { | ||
| 88 | unsigned int timer0 : 1; | ||
| 89 | unsigned int timer1 : 1; | ||
| 90 | unsigned int dma0 : 1; | ||
| 91 | unsigned int dma1 : 1; | ||
| 92 | unsigned int dma2 : 1; | ||
| 93 | unsigned int dma3 : 1; | ||
| 94 | unsigned int dma4 : 1; | ||
| 95 | unsigned int dma5 : 1; | ||
| 96 | unsigned int dma6 : 1; | ||
| 97 | unsigned int dma7 : 1; | ||
| 98 | unsigned int dma9 : 1; | ||
| 99 | unsigned int dma11 : 1; | ||
| 100 | unsigned int gio : 1; | ||
| 101 | unsigned int iop0 : 1; | ||
| 102 | unsigned int iop1 : 1; | ||
| 103 | unsigned int ser0 : 1; | ||
| 104 | unsigned int ser1 : 1; | ||
| 105 | unsigned int ser2 : 1; | ||
| 106 | unsigned int ser3 : 1; | ||
| 107 | unsigned int ser4 : 1; | ||
| 108 | unsigned int sser : 1; | ||
| 109 | unsigned int strdma0 : 1; | ||
| 110 | unsigned int strdma1 : 1; | ||
| 111 | unsigned int strdma2 : 1; | ||
| 112 | unsigned int strdma3 : 1; | ||
| 113 | unsigned int strdma5 : 1; | ||
| 114 | unsigned int vin : 1; | ||
| 115 | unsigned int vout : 1; | ||
| 116 | unsigned int jpeg : 1; | ||
| 117 | unsigned int h264 : 1; | ||
| 118 | unsigned int histo : 1; | ||
| 119 | unsigned int ccd : 1; | ||
| 120 | } reg_intr_vect_rw_mask0; | ||
| 121 | #define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0 | ||
| 122 | #define REG_RD_ADDR_intr_vect_rw_mask 0 | ||
| 123 | #define REG_WR_ADDR_intr_vect_rw_mask 0 | ||
| 124 | #define REG_RD_ADDR_intr_vect_rw_mask0 0 | ||
| 125 | #define REG_WR_ADDR_intr_vect_rw_mask0 0 | ||
| 126 | |||
| 127 | #define STRIDE_intr_vect_r_vect 4 | ||
| 128 | /* Register r_vect0, scope intr_vect, type r */ | ||
| 129 | typedef struct { | ||
| 130 | unsigned int timer0 : 1; | ||
| 131 | unsigned int timer1 : 1; | ||
| 132 | unsigned int dma0 : 1; | ||
| 133 | unsigned int dma1 : 1; | ||
| 134 | unsigned int dma2 : 1; | ||
| 135 | unsigned int dma3 : 1; | ||
| 136 | unsigned int dma4 : 1; | ||
| 137 | unsigned int dma5 : 1; | ||
| 138 | unsigned int dma6 : 1; | ||
| 139 | unsigned int dma7 : 1; | ||
| 140 | unsigned int dma9 : 1; | ||
| 141 | unsigned int dma11 : 1; | ||
| 142 | unsigned int gio : 1; | ||
| 143 | unsigned int iop0 : 1; | ||
| 144 | unsigned int iop1 : 1; | ||
| 145 | unsigned int ser0 : 1; | ||
| 146 | unsigned int ser1 : 1; | ||
| 147 | unsigned int ser2 : 1; | ||
| 148 | unsigned int ser3 : 1; | ||
| 149 | unsigned int ser4 : 1; | ||
| 150 | unsigned int sser : 1; | ||
| 151 | unsigned int strdma0 : 1; | ||
| 152 | unsigned int strdma1 : 1; | ||
| 153 | unsigned int strdma2 : 1; | ||
| 154 | unsigned int strdma3 : 1; | ||
| 155 | unsigned int strdma5 : 1; | ||
| 156 | unsigned int vin : 1; | ||
| 157 | unsigned int vout : 1; | ||
| 158 | unsigned int jpeg : 1; | ||
| 159 | unsigned int h264 : 1; | ||
| 160 | unsigned int histo : 1; | ||
| 161 | unsigned int ccd : 1; | ||
| 162 | } reg_intr_vect_r_vect0; | ||
| 163 | #define reg_intr_vect_r_vect reg_intr_vect_r_vect0 | ||
| 164 | #define REG_RD_ADDR_intr_vect_r_vect 8 | ||
| 165 | #define REG_RD_ADDR_intr_vect_r_vect0 8 | ||
| 166 | |||
| 167 | #define STRIDE_intr_vect_r_masked_vect 4 | ||
| 168 | /* Register r_masked_vect0, scope intr_vect, type r */ | ||
| 169 | typedef struct { | ||
| 170 | unsigned int timer0 : 1; | ||
| 171 | unsigned int timer1 : 1; | ||
| 172 | unsigned int dma0 : 1; | ||
| 173 | unsigned int dma1 : 1; | ||
| 174 | unsigned int dma2 : 1; | ||
| 175 | unsigned int dma3 : 1; | ||
| 176 | unsigned int dma4 : 1; | ||
| 177 | unsigned int dma5 : 1; | ||
| 178 | unsigned int dma6 : 1; | ||
| 179 | unsigned int dma7 : 1; | ||
| 180 | unsigned int dma9 : 1; | ||
| 181 | unsigned int dma11 : 1; | ||
| 182 | unsigned int gio : 1; | ||
| 183 | unsigned int iop0 : 1; | ||
| 184 | unsigned int iop1 : 1; | ||
| 185 | unsigned int ser0 : 1; | ||
| 186 | unsigned int ser1 : 1; | ||
| 187 | unsigned int ser2 : 1; | ||
| 188 | unsigned int ser3 : 1; | ||
| 189 | unsigned int ser4 : 1; | ||
| 190 | unsigned int sser : 1; | ||
| 191 | unsigned int strdma0 : 1; | ||
| 192 | unsigned int strdma1 : 1; | ||
| 193 | unsigned int strdma2 : 1; | ||
| 194 | unsigned int strdma3 : 1; | ||
| 195 | unsigned int strdma5 : 1; | ||
| 196 | unsigned int vin : 1; | ||
| 197 | unsigned int vout : 1; | ||
| 198 | unsigned int jpeg : 1; | ||
| 199 | unsigned int h264 : 1; | ||
| 200 | unsigned int histo : 1; | ||
| 201 | unsigned int ccd : 1; | ||
| 202 | } reg_intr_vect_r_masked_vect0; | ||
| 203 | #define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0 | ||
| 204 | #define REG_RD_ADDR_intr_vect_r_masked_vect0 16 | ||
| 205 | #define REG_RD_ADDR_intr_vect_r_masked_vect 16 | ||
| 206 | |||
| 207 | #define STRIDE_intr_vect_rw_xmask 4 | ||
| 208 | /* Register rw_xmask0, scope intr_vect, type rw */ | ||
| 209 | typedef struct { | ||
| 210 | unsigned int timer0 : 1; | ||
| 211 | unsigned int timer1 : 1; | ||
| 212 | unsigned int dma0 : 1; | ||
| 213 | unsigned int dma1 : 1; | ||
| 214 | unsigned int dma2 : 1; | ||
| 215 | unsigned int dma3 : 1; | ||
| 216 | unsigned int dma4 : 1; | ||
| 217 | unsigned int dma5 : 1; | ||
| 218 | unsigned int dma6 : 1; | ||
| 219 | unsigned int dma7 : 1; | ||
| 220 | unsigned int dma9 : 1; | ||
| 221 | unsigned int dma11 : 1; | ||
| 222 | unsigned int gio : 1; | ||
| 223 | unsigned int iop0 : 1; | ||
| 224 | unsigned int iop1 : 1; | ||
| 225 | unsigned int ser0 : 1; | ||
| 226 | unsigned int ser1 : 1; | ||
| 227 | unsigned int ser2 : 1; | ||
| 228 | unsigned int ser3 : 1; | ||
| 229 | unsigned int ser4 : 1; | ||
| 230 | unsigned int sser : 1; | ||
| 231 | unsigned int strdma0 : 1; | ||
| 232 | unsigned int strdma1 : 1; | ||
| 233 | unsigned int strdma2 : 1; | ||
| 234 | unsigned int strdma3 : 1; | ||
| 235 | unsigned int strdma5 : 1; | ||
| 236 | unsigned int vin : 1; | ||
| 237 | unsigned int vout : 1; | ||
| 238 | unsigned int jpeg : 1; | ||
| 239 | unsigned int h264 : 1; | ||
| 240 | unsigned int histo : 1; | ||
| 241 | unsigned int ccd : 1; | ||
| 242 | } reg_intr_vect_rw_xmask0; | ||
| 243 | #define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0 | ||
| 244 | #define REG_RD_ADDR_intr_vect_rw_xmask0 24 | ||
| 245 | #define REG_WR_ADDR_intr_vect_rw_xmask0 24 | ||
| 246 | #define REG_RD_ADDR_intr_vect_rw_xmask 24 | ||
| 247 | #define REG_WR_ADDR_intr_vect_rw_xmask 24 | ||
| 248 | |||
| 249 | /* Register rw_mask1, scope intr_vect, type rw */ | ||
| 250 | typedef struct { | ||
| 251 | unsigned int eth : 1; | ||
| 252 | unsigned int memarb_bar : 1; | ||
| 253 | unsigned int memarb_foo : 1; | ||
| 254 | unsigned int pio : 1; | ||
| 255 | unsigned int sclr : 1; | ||
| 256 | unsigned int sclr_fifo : 1; | ||
| 257 | unsigned int dummy1 : 26; | ||
| 258 | } reg_intr_vect_rw_mask1; | ||
| 259 | #define REG_RD_ADDR_intr_vect_rw_mask1 4 | ||
| 260 | #define REG_WR_ADDR_intr_vect_rw_mask1 4 | ||
| 261 | |||
| 262 | /* Register r_vect1, scope intr_vect, type r */ | ||
| 263 | typedef struct { | ||
| 264 | unsigned int eth : 1; | ||
| 265 | unsigned int memarb_bar : 1; | ||
| 266 | unsigned int memarb_foo : 1; | ||
| 267 | unsigned int pio : 1; | ||
| 268 | unsigned int sclr : 1; | ||
| 269 | unsigned int sclr_fifo : 1; | ||
| 270 | unsigned int dummy1 : 26; | ||
| 271 | } reg_intr_vect_r_vect1; | ||
| 272 | #define REG_RD_ADDR_intr_vect_r_vect1 12 | ||
| 273 | |||
| 274 | /* Register r_masked_vect1, scope intr_vect, type r */ | ||
| 275 | typedef struct { | ||
| 276 | unsigned int eth : 1; | ||
| 277 | unsigned int memarb_bar : 1; | ||
| 278 | unsigned int memarb_foo : 1; | ||
| 279 | unsigned int pio : 1; | ||
| 280 | unsigned int sclr : 1; | ||
| 281 | unsigned int sclr_fifo : 1; | ||
| 282 | unsigned int dummy1 : 26; | ||
| 283 | } reg_intr_vect_r_masked_vect1; | ||
| 284 | #define REG_RD_ADDR_intr_vect_r_masked_vect1 20 | ||
| 285 | |||
| 286 | /* Register rw_xmask1, scope intr_vect, type rw */ | ||
| 287 | typedef struct { | ||
| 288 | unsigned int eth : 1; | ||
| 289 | unsigned int memarb_bar : 1; | ||
| 290 | unsigned int memarb_foo : 1; | ||
| 291 | unsigned int pio : 1; | ||
| 292 | unsigned int sclr : 1; | ||
| 293 | unsigned int sclr_fifo : 1; | ||
| 294 | unsigned int dummy1 : 26; | ||
| 295 | } reg_intr_vect_rw_xmask1; | ||
| 296 | #define REG_RD_ADDR_intr_vect_rw_xmask1 28 | ||
| 297 | #define REG_WR_ADDR_intr_vect_rw_xmask1 28 | ||
| 298 | |||
| 299 | /* Register rw_xmask_ctrl, scope intr_vect, type rw */ | ||
| 300 | typedef struct { | ||
| 301 | unsigned int en : 1; | ||
| 302 | unsigned int dummy1 : 31; | ||
| 303 | } reg_intr_vect_rw_xmask_ctrl; | ||
| 304 | #define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32 | ||
| 305 | #define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32 | ||
| 306 | |||
| 307 | /* Register r_nmi, scope intr_vect, type r */ | ||
| 308 | typedef struct { | ||
| 309 | unsigned int watchdog0 : 1; | ||
| 310 | unsigned int watchdog1 : 1; | ||
| 311 | unsigned int dummy1 : 30; | ||
| 312 | } reg_intr_vect_r_nmi; | ||
| 313 | #define REG_RD_ADDR_intr_vect_r_nmi 64 | ||
| 314 | |||
| 315 | /* Register r_guru, scope intr_vect, type r */ | ||
| 316 | typedef struct { | ||
| 317 | unsigned int jtag : 1; | ||
| 318 | unsigned int dummy1 : 31; | ||
| 319 | } reg_intr_vect_r_guru; | ||
| 320 | #define REG_RD_ADDR_intr_vect_r_guru 68 | ||
| 321 | |||
| 322 | |||
| 323 | /* Register rw_ipi, scope intr_vect, type rw */ | ||
| 324 | typedef struct | ||
| 325 | { | ||
| 326 | unsigned int vector; | ||
| 327 | } reg_intr_vect_rw_ipi; | ||
| 328 | #define REG_RD_ADDR_intr_vect_rw_ipi 72 | ||
| 329 | #define REG_WR_ADDR_intr_vect_rw_ipi 72 | ||
| 330 | |||
| 331 | /* Constants */ | ||
| 332 | enum { | ||
| 333 | regk_intr_vect_no = 0x00000000, | ||
| 334 | regk_intr_vect_rw_mask0_default = 0x00000000, | ||
| 335 | regk_intr_vect_rw_mask1_default = 0x00000000, | ||
| 336 | regk_intr_vect_rw_xmask0_default = 0x00000000, | ||
| 337 | regk_intr_vect_rw_xmask1_default = 0x00000000, | ||
| 338 | regk_intr_vect_rw_xmask_ctrl_default = 0x00000000, | ||
| 339 | regk_intr_vect_yes = 0x00000001 | ||
| 340 | }; | ||
| 341 | #endif /* __intr_vect_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h new file mode 100644 index 000000000000..d75a74e90458 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* Autogenerated Changes here will be lost! | ||
| 2 | * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg | ||
| 3 | */ | ||
| 4 | #define iop_version 0 | ||
| 5 | #define iop_fifo_in_extra 64 | ||
| 6 | #define iop_fifo_out_extra 128 | ||
| 7 | #define iop_trigger_grp0 192 | ||
| 8 | #define iop_trigger_grp1 256 | ||
| 9 | #define iop_trigger_grp2 320 | ||
| 10 | #define iop_trigger_grp3 384 | ||
| 11 | #define iop_trigger_grp4 448 | ||
| 12 | #define iop_trigger_grp5 512 | ||
| 13 | #define iop_trigger_grp6 576 | ||
| 14 | #define iop_trigger_grp7 640 | ||
| 15 | #define iop_crc_par 768 | ||
| 16 | #define iop_dmc_in 896 | ||
| 17 | #define iop_dmc_out 1024 | ||
| 18 | #define iop_fifo_in 1152 | ||
| 19 | #define iop_fifo_out 1280 | ||
| 20 | #define iop_scrc_in 1408 | ||
| 21 | #define iop_scrc_out 1536 | ||
| 22 | #define iop_timer_grp0 1664 | ||
| 23 | #define iop_timer_grp1 1792 | ||
| 24 | #define iop_sap_in 2048 | ||
| 25 | #define iop_sap_out 2304 | ||
| 26 | #define iop_spu 2560 | ||
| 27 | #define iop_sw_cfg 2816 | ||
| 28 | #define iop_sw_cpu 3072 | ||
| 29 | #define iop_sw_mpu 3328 | ||
| 30 | #define iop_sw_spu 3584 | ||
| 31 | #define iop_mpu 4096 | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h new file mode 100644 index 000000000000..7f90b5a0460d --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h | |||
| @@ -0,0 +1,109 @@ | |||
| 1 | #ifndef __iop_sap_in_defs_asm_h | ||
| 2 | #define __iop_sap_in_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sap_in.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #define STRIDE_iop_sap_in_rw_bus_byte 4 | ||
| 54 | /* Register rw_bus_byte, scope iop_sap_in, type rw */ | ||
| 55 | #define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0 | ||
| 56 | #define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2 | ||
| 57 | #define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2 | ||
| 58 | #define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3 | ||
| 59 | #define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5 | ||
| 60 | #define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2 | ||
| 61 | #define reg_iop_sap_in_rw_bus_byte___delay___lsb 7 | ||
| 62 | #define reg_iop_sap_in_rw_bus_byte___delay___width 2 | ||
| 63 | #define reg_iop_sap_in_rw_bus_byte_offset 0 | ||
| 64 | |||
| 65 | #define STRIDE_iop_sap_in_rw_gio 4 | ||
| 66 | /* Register rw_gio, scope iop_sap_in, type rw */ | ||
| 67 | #define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 | ||
| 68 | #define reg_iop_sap_in_rw_gio___sync_sel___width 2 | ||
| 69 | #define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 | ||
| 70 | #define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 | ||
| 71 | #define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 | ||
| 72 | #define reg_iop_sap_in_rw_gio___sync_edge___width 2 | ||
| 73 | #define reg_iop_sap_in_rw_gio___delay___lsb 7 | ||
| 74 | #define reg_iop_sap_in_rw_gio___delay___width 2 | ||
| 75 | #define reg_iop_sap_in_rw_gio___logic___lsb 9 | ||
| 76 | #define reg_iop_sap_in_rw_gio___logic___width 2 | ||
| 77 | #define reg_iop_sap_in_rw_gio_offset 16 | ||
| 78 | |||
| 79 | |||
| 80 | /* Constants */ | ||
| 81 | #define regk_iop_sap_in_and 0x00000002 | ||
| 82 | #define regk_iop_sap_in_ext_clk200 0x00000003 | ||
| 83 | #define regk_iop_sap_in_gio0 0x00000000 | ||
| 84 | #define regk_iop_sap_in_gio12 0x00000003 | ||
| 85 | #define regk_iop_sap_in_gio16 0x00000004 | ||
| 86 | #define regk_iop_sap_in_gio20 0x00000005 | ||
| 87 | #define regk_iop_sap_in_gio24 0x00000006 | ||
| 88 | #define regk_iop_sap_in_gio28 0x00000007 | ||
| 89 | #define regk_iop_sap_in_gio4 0x00000001 | ||
| 90 | #define regk_iop_sap_in_gio8 0x00000002 | ||
| 91 | #define regk_iop_sap_in_inv 0x00000001 | ||
| 92 | #define regk_iop_sap_in_neg 0x00000002 | ||
| 93 | #define regk_iop_sap_in_no 0x00000000 | ||
| 94 | #define regk_iop_sap_in_no_del_ext_clk200 0x00000002 | ||
| 95 | #define regk_iop_sap_in_none 0x00000000 | ||
| 96 | #define regk_iop_sap_in_one 0x00000001 | ||
| 97 | #define regk_iop_sap_in_or 0x00000003 | ||
| 98 | #define regk_iop_sap_in_pos 0x00000001 | ||
| 99 | #define regk_iop_sap_in_pos_neg 0x00000003 | ||
| 100 | #define regk_iop_sap_in_rw_bus_byte_default 0x00000000 | ||
| 101 | #define regk_iop_sap_in_rw_bus_byte_size 0x00000004 | ||
| 102 | #define regk_iop_sap_in_rw_gio_default 0x00000000 | ||
| 103 | #define regk_iop_sap_in_rw_gio_size 0x00000020 | ||
| 104 | #define regk_iop_sap_in_timer_grp0_tmr3 0x00000000 | ||
| 105 | #define regk_iop_sap_in_timer_grp1_tmr3 0x00000001 | ||
| 106 | #define regk_iop_sap_in_tmr_clk200 0x00000001 | ||
| 107 | #define regk_iop_sap_in_two 0x00000002 | ||
| 108 | #define regk_iop_sap_in_two_clk200 0x00000000 | ||
| 109 | #endif /* __iop_sap_in_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h new file mode 100644 index 000000000000..399bd656406b --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_out_defs_asm.h | |||
| @@ -0,0 +1,276 @@ | |||
| 1 | #ifndef __iop_sap_out_defs_asm_h | ||
| 2 | #define __iop_sap_out_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sap_out.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_gen_gated, scope iop_sap_out, type rw */ | ||
| 54 | #define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 | ||
| 55 | #define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 | ||
| 56 | #define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 | ||
| 57 | #define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 | ||
| 58 | #define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 | ||
| 59 | #define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 | ||
| 60 | #define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 | ||
| 61 | #define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 | ||
| 62 | #define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 | ||
| 63 | #define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 | ||
| 64 | #define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 | ||
| 65 | #define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 | ||
| 66 | #define reg_iop_sap_out_rw_gen_gated_offset 0 | ||
| 67 | |||
| 68 | /* Register rw_bus, scope iop_sap_out, type rw */ | ||
| 69 | #define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 | ||
| 70 | #define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 | ||
| 71 | #define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 | ||
| 72 | #define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 | ||
| 73 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 | ||
| 74 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 | ||
| 75 | #define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 | ||
| 76 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 | ||
| 77 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 | ||
| 78 | #define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 | ||
| 79 | #define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 | ||
| 80 | #define reg_iop_sap_out_rw_bus___byte0_delay___width 1 | ||
| 81 | #define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 | ||
| 82 | #define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 | ||
| 83 | #define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 | ||
| 84 | #define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 | ||
| 85 | #define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 | ||
| 86 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 | ||
| 87 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 | ||
| 88 | #define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 | ||
| 89 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 | ||
| 90 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 | ||
| 91 | #define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 | ||
| 92 | #define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 | ||
| 93 | #define reg_iop_sap_out_rw_bus___byte1_delay___width 1 | ||
| 94 | #define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 | ||
| 95 | #define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 | ||
| 96 | #define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 | ||
| 97 | #define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 | ||
| 98 | #define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 | ||
| 99 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 | ||
| 100 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 | ||
| 101 | #define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 | ||
| 102 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 | ||
| 103 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 | ||
| 104 | #define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 | ||
| 105 | #define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 | ||
| 106 | #define reg_iop_sap_out_rw_bus___byte2_delay___width 1 | ||
| 107 | #define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 | ||
| 108 | #define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 | ||
| 109 | #define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 | ||
| 110 | #define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 | ||
| 111 | #define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 | ||
| 112 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 | ||
| 113 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 | ||
| 114 | #define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 | ||
| 115 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 | ||
| 116 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 | ||
| 117 | #define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 | ||
| 118 | #define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 | ||
| 119 | #define reg_iop_sap_out_rw_bus___byte3_delay___width 1 | ||
| 120 | #define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 | ||
| 121 | #define reg_iop_sap_out_rw_bus_offset 4 | ||
| 122 | |||
| 123 | /* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ | ||
| 124 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 | ||
| 125 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 | ||
| 126 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 | ||
| 127 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 | ||
| 128 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 | ||
| 129 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 | ||
| 130 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 | ||
| 131 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 | ||
| 132 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 | ||
| 133 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 | ||
| 134 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 | ||
| 135 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 | ||
| 136 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 | ||
| 137 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 | ||
| 138 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 | ||
| 139 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 | ||
| 140 | #define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 | ||
| 141 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 | ||
| 142 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 | ||
| 143 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 | ||
| 144 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 | ||
| 145 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 | ||
| 146 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 | ||
| 147 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 | ||
| 148 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 | ||
| 149 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 | ||
| 150 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 | ||
| 151 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 | ||
| 152 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 | ||
| 153 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 | ||
| 154 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 | ||
| 155 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 | ||
| 156 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 | ||
| 157 | #define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 | ||
| 158 | #define reg_iop_sap_out_rw_bus_lo_oe_offset 8 | ||
| 159 | |||
| 160 | /* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ | ||
| 161 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 | ||
| 162 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 | ||
| 163 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 | ||
| 164 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 | ||
| 165 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 | ||
| 166 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 | ||
| 167 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 | ||
| 168 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 | ||
| 169 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 | ||
| 170 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 | ||
| 171 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 | ||
| 172 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 | ||
| 173 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 | ||
| 174 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 | ||
| 175 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 | ||
| 176 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 | ||
| 177 | #define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 | ||
| 178 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 | ||
| 179 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 | ||
| 180 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 | ||
| 181 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 | ||
| 182 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 | ||
| 183 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 | ||
| 184 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 | ||
| 185 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 | ||
| 186 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 | ||
| 187 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 | ||
| 188 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 | ||
| 189 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 | ||
| 190 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 | ||
| 191 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 | ||
| 192 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 | ||
| 193 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 | ||
| 194 | #define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 | ||
| 195 | #define reg_iop_sap_out_rw_bus_hi_oe_offset 12 | ||
| 196 | |||
| 197 | #define STRIDE_iop_sap_out_rw_gio 4 | ||
| 198 | /* Register rw_gio, scope iop_sap_out, type rw */ | ||
| 199 | #define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 | ||
| 200 | #define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 | ||
| 201 | #define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 | ||
| 202 | #define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 | ||
| 203 | #define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 | ||
| 204 | #define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 | ||
| 205 | #define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 | ||
| 206 | #define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 | ||
| 207 | #define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 | ||
| 208 | #define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 | ||
| 209 | #define reg_iop_sap_out_rw_gio___out_delay___lsb 7 | ||
| 210 | #define reg_iop_sap_out_rw_gio___out_delay___width 1 | ||
| 211 | #define reg_iop_sap_out_rw_gio___out_delay___bit 7 | ||
| 212 | #define reg_iop_sap_out_rw_gio___out_logic___lsb 8 | ||
| 213 | #define reg_iop_sap_out_rw_gio___out_logic___width 2 | ||
| 214 | #define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 | ||
| 215 | #define reg_iop_sap_out_rw_gio___out_logic_src___width 2 | ||
| 216 | #define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 | ||
| 217 | #define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 | ||
| 218 | #define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 | ||
| 219 | #define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 | ||
| 220 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 | ||
| 221 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 | ||
| 222 | #define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 | ||
| 223 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 | ||
| 224 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 | ||
| 225 | #define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 | ||
| 226 | #define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 | ||
| 227 | #define reg_iop_sap_out_rw_gio___oe_delay___width 1 | ||
| 228 | #define reg_iop_sap_out_rw_gio___oe_delay___bit 19 | ||
| 229 | #define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 | ||
| 230 | #define reg_iop_sap_out_rw_gio___oe_logic___width 2 | ||
| 231 | #define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 | ||
| 232 | #define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 | ||
| 233 | #define reg_iop_sap_out_rw_gio_offset 16 | ||
| 234 | |||
| 235 | |||
| 236 | /* Constants */ | ||
| 237 | #define regk_iop_sap_out_always 0x00000001 | ||
| 238 | #define regk_iop_sap_out_and 0x00000002 | ||
| 239 | #define regk_iop_sap_out_clk0 0x00000000 | ||
| 240 | #define regk_iop_sap_out_clk1 0x00000001 | ||
| 241 | #define regk_iop_sap_out_clk12 0x00000004 | ||
| 242 | #define regk_iop_sap_out_clk200 0x00000000 | ||
| 243 | #define regk_iop_sap_out_ext 0x00000002 | ||
| 244 | #define regk_iop_sap_out_gated 0x00000003 | ||
| 245 | #define regk_iop_sap_out_gio0 0x00000000 | ||
| 246 | #define regk_iop_sap_out_gio1 0x00000000 | ||
| 247 | #define regk_iop_sap_out_gio16 0x00000002 | ||
| 248 | #define regk_iop_sap_out_gio17 0x00000002 | ||
| 249 | #define regk_iop_sap_out_gio24 0x00000003 | ||
| 250 | #define regk_iop_sap_out_gio25 0x00000003 | ||
| 251 | #define regk_iop_sap_out_gio8 0x00000001 | ||
| 252 | #define regk_iop_sap_out_gio9 0x00000001 | ||
| 253 | #define regk_iop_sap_out_gio_out10 0x00000005 | ||
| 254 | #define regk_iop_sap_out_gio_out18 0x00000006 | ||
| 255 | #define regk_iop_sap_out_gio_out2 0x00000004 | ||
| 256 | #define regk_iop_sap_out_gio_out26 0x00000007 | ||
| 257 | #define regk_iop_sap_out_inv 0x00000001 | ||
| 258 | #define regk_iop_sap_out_nand 0x00000003 | ||
| 259 | #define regk_iop_sap_out_no 0x00000000 | ||
| 260 | #define regk_iop_sap_out_none 0x00000000 | ||
| 261 | #define regk_iop_sap_out_one 0x00000001 | ||
| 262 | #define regk_iop_sap_out_rw_bus_default 0x00000000 | ||
| 263 | #define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 | ||
| 264 | #define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 | ||
| 265 | #define regk_iop_sap_out_rw_gen_gated_default 0x00000000 | ||
| 266 | #define regk_iop_sap_out_rw_gio_default 0x00000000 | ||
| 267 | #define regk_iop_sap_out_rw_gio_size 0x00000020 | ||
| 268 | #define regk_iop_sap_out_spu_gio6 0x00000002 | ||
| 269 | #define regk_iop_sap_out_spu_gio7 0x00000003 | ||
| 270 | #define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 | ||
| 271 | #define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 | ||
| 272 | #define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 | ||
| 273 | #define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 | ||
| 274 | #define regk_iop_sap_out_tmr200 0x00000001 | ||
| 275 | #define regk_iop_sap_out_yes 0x00000001 | ||
| 276 | #endif /* __iop_sap_out_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h new file mode 100644 index 000000000000..3b3949b51a66 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cfg_defs_asm.h | |||
| @@ -0,0 +1,739 @@ | |||
| 1 | #ifndef __iop_sw_cfg_defs_asm_h | ||
| 2 | #define __iop_sw_cfg_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_cfg.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ | ||
| 54 | #define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 | ||
| 55 | #define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 | ||
| 56 | #define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 | ||
| 57 | |||
| 58 | /* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ | ||
| 59 | #define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 | ||
| 60 | #define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 | ||
| 61 | #define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 | ||
| 62 | |||
| 63 | /* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ | ||
| 64 | #define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 | ||
| 65 | #define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 | ||
| 66 | #define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 | ||
| 67 | |||
| 68 | /* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ | ||
| 69 | #define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 | ||
| 70 | #define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 | ||
| 71 | #define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 | ||
| 72 | |||
| 73 | /* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 74 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 | ||
| 75 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 | ||
| 76 | #define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 | ||
| 77 | |||
| 78 | /* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ | ||
| 79 | #define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 | ||
| 80 | #define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 | ||
| 81 | #define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 | ||
| 82 | |||
| 83 | /* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 84 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 | ||
| 85 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 | ||
| 86 | #define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 | ||
| 87 | |||
| 88 | /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ | ||
| 89 | #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 | ||
| 90 | #define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 | ||
| 91 | #define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 | ||
| 92 | |||
| 93 | /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ | ||
| 94 | #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 | ||
| 95 | #define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 | ||
| 96 | #define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 | ||
| 97 | |||
| 98 | /* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ | ||
| 99 | #define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 | ||
| 100 | #define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 | ||
| 101 | #define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 | ||
| 102 | |||
| 103 | /* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ | ||
| 104 | #define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 | ||
| 105 | #define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 | ||
| 106 | #define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 | ||
| 107 | |||
| 108 | /* Register rw_spu_owner, scope iop_sw_cfg, type rw */ | ||
| 109 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 | ||
| 110 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 | ||
| 111 | #define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 | ||
| 112 | #define reg_iop_sw_cfg_rw_spu_owner_offset 44 | ||
| 113 | |||
| 114 | /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 115 | #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 | ||
| 116 | #define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 | ||
| 117 | #define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 | ||
| 118 | |||
| 119 | /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 120 | #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 | ||
| 121 | #define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 | ||
| 122 | #define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 | ||
| 123 | |||
| 124 | /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 125 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 | ||
| 126 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 | ||
| 127 | #define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 | ||
| 128 | |||
| 129 | /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 130 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 | ||
| 131 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 | ||
| 132 | #define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 | ||
| 133 | |||
| 134 | /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ | ||
| 135 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 | ||
| 136 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 | ||
| 137 | #define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 | ||
| 138 | |||
| 139 | /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ | ||
| 140 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 | ||
| 141 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 | ||
| 142 | #define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 | ||
| 143 | |||
| 144 | /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ | ||
| 145 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 | ||
| 146 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 | ||
| 147 | #define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 | ||
| 148 | |||
| 149 | /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ | ||
| 150 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 | ||
| 151 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 | ||
| 152 | #define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 | ||
| 153 | |||
| 154 | /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ | ||
| 155 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 | ||
| 156 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 | ||
| 157 | #define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 | ||
| 158 | |||
| 159 | /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ | ||
| 160 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 | ||
| 161 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 | ||
| 162 | #define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 | ||
| 163 | |||
| 164 | /* Register rw_bus_mask, scope iop_sw_cfg, type rw */ | ||
| 165 | #define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 | ||
| 166 | #define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 | ||
| 167 | #define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 | ||
| 168 | #define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 | ||
| 169 | #define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 | ||
| 170 | #define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 | ||
| 171 | #define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 | ||
| 172 | #define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 | ||
| 173 | #define reg_iop_sw_cfg_rw_bus_mask_offset 88 | ||
| 174 | |||
| 175 | /* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 176 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 | ||
| 177 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 | ||
| 178 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 | ||
| 179 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 | ||
| 180 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 | ||
| 181 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 | ||
| 182 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 | ||
| 183 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 | ||
| 184 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 | ||
| 185 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 | ||
| 186 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 | ||
| 187 | #define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 | ||
| 188 | #define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 | ||
| 189 | |||
| 190 | /* Register rw_gio_mask, scope iop_sw_cfg, type rw */ | ||
| 191 | #define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 | ||
| 192 | #define reg_iop_sw_cfg_rw_gio_mask___val___width 32 | ||
| 193 | #define reg_iop_sw_cfg_rw_gio_mask_offset 96 | ||
| 194 | |||
| 195 | /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 196 | #define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 | ||
| 197 | #define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 | ||
| 198 | #define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 | ||
| 199 | |||
| 200 | /* Register rw_pinmapping, scope iop_sw_cfg, type rw */ | ||
| 201 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 | ||
| 202 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 | ||
| 203 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 | ||
| 204 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 | ||
| 205 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 | ||
| 206 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 | ||
| 207 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 | ||
| 208 | #define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 | ||
| 209 | #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 | ||
| 210 | #define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 | ||
| 211 | #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 | ||
| 212 | #define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 | ||
| 213 | #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 | ||
| 214 | #define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 | ||
| 215 | #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 | ||
| 216 | #define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 | ||
| 217 | #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 | ||
| 218 | #define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 | ||
| 219 | #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 | ||
| 220 | #define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 | ||
| 221 | #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 | ||
| 222 | #define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 | ||
| 223 | #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 | ||
| 224 | #define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 | ||
| 225 | #define reg_iop_sw_cfg_rw_pinmapping_offset 104 | ||
| 226 | |||
| 227 | /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ | ||
| 228 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 | ||
| 229 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 | ||
| 230 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 | ||
| 231 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 | ||
| 232 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 | ||
| 233 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 | ||
| 234 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 | ||
| 235 | #define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 | ||
| 236 | #define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 | ||
| 237 | |||
| 238 | /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 239 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 | ||
| 240 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 | ||
| 241 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 | ||
| 242 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 | ||
| 243 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 | ||
| 244 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 | ||
| 245 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 | ||
| 246 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 | ||
| 247 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 | ||
| 248 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 | ||
| 249 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 | ||
| 250 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 | ||
| 251 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 | ||
| 252 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 | ||
| 253 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 | ||
| 254 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 | ||
| 255 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 | ||
| 256 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 | ||
| 257 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 | ||
| 258 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 | ||
| 259 | #define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 | ||
| 260 | |||
| 261 | /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 262 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 | ||
| 263 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 | ||
| 264 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 | ||
| 265 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 | ||
| 266 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 | ||
| 267 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 | ||
| 268 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 | ||
| 269 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 | ||
| 270 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 | ||
| 271 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 | ||
| 272 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 | ||
| 273 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 | ||
| 274 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 | ||
| 275 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 | ||
| 276 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 | ||
| 277 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 | ||
| 278 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 | ||
| 279 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 | ||
| 280 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 | ||
| 281 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 | ||
| 282 | #define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 | ||
| 283 | |||
| 284 | /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ | ||
| 285 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 | ||
| 286 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 | ||
| 287 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 | ||
| 288 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 | ||
| 289 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 | ||
| 290 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 | ||
| 291 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 | ||
| 292 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 | ||
| 293 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 | ||
| 294 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 | ||
| 295 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 | ||
| 296 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 | ||
| 297 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 | ||
| 298 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 | ||
| 299 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 | ||
| 300 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 | ||
| 301 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 | ||
| 302 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 | ||
| 303 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 | ||
| 304 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 | ||
| 305 | #define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 | ||
| 306 | |||
| 307 | /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ | ||
| 308 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 | ||
| 309 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 | ||
| 310 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 | ||
| 311 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 | ||
| 312 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 | ||
| 313 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 | ||
| 314 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 | ||
| 315 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 | ||
| 316 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 | ||
| 317 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 | ||
| 318 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 | ||
| 319 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 | ||
| 320 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 | ||
| 321 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 | ||
| 322 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 | ||
| 323 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 | ||
| 324 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 | ||
| 325 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 | ||
| 326 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 | ||
| 327 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 | ||
| 328 | #define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 | ||
| 329 | |||
| 330 | /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ | ||
| 331 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 | ||
| 332 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 | ||
| 333 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 | ||
| 334 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 | ||
| 335 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 | ||
| 336 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 | ||
| 337 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 | ||
| 338 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 | ||
| 339 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 | ||
| 340 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 | ||
| 341 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 | ||
| 342 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 | ||
| 343 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 | ||
| 344 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 | ||
| 345 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 | ||
| 346 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 | ||
| 347 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 | ||
| 348 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 | ||
| 349 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 | ||
| 350 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 | ||
| 351 | #define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 | ||
| 352 | |||
| 353 | /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ | ||
| 354 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 | ||
| 355 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 | ||
| 356 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 | ||
| 357 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 | ||
| 358 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 | ||
| 359 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 | ||
| 360 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 | ||
| 361 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 | ||
| 362 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 | ||
| 363 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 | ||
| 364 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 | ||
| 365 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 | ||
| 366 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 | ||
| 367 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 | ||
| 368 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 | ||
| 369 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 | ||
| 370 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 | ||
| 371 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 | ||
| 372 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 | ||
| 373 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 | ||
| 374 | #define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 | ||
| 375 | |||
| 376 | /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ | ||
| 377 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 | ||
| 378 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 | ||
| 379 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 | ||
| 380 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 | ||
| 381 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 | ||
| 382 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 | ||
| 383 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 | ||
| 384 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 | ||
| 385 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 | ||
| 386 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 | ||
| 387 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 | ||
| 388 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 | ||
| 389 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 | ||
| 390 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 | ||
| 391 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 | ||
| 392 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 | ||
| 393 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 | ||
| 394 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 | ||
| 395 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 | ||
| 396 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 | ||
| 397 | #define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 | ||
| 398 | |||
| 399 | /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ | ||
| 400 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 | ||
| 401 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 | ||
| 402 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 | ||
| 403 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 | ||
| 404 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 | ||
| 405 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 | ||
| 406 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 | ||
| 407 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 | ||
| 408 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 | ||
| 409 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 | ||
| 410 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 | ||
| 411 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 | ||
| 412 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 | ||
| 413 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 | ||
| 414 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 | ||
| 415 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 | ||
| 416 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 | ||
| 417 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 | ||
| 418 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 | ||
| 419 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 | ||
| 420 | #define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 | ||
| 421 | |||
| 422 | /* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ | ||
| 423 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 | ||
| 424 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 | ||
| 425 | #define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 | ||
| 426 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 | ||
| 427 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 | ||
| 428 | #define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 | ||
| 429 | #define reg_iop_sw_cfg_rw_spu_cfg_offset 144 | ||
| 430 | |||
| 431 | /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 432 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 | ||
| 433 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 | ||
| 434 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 | ||
| 435 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 | ||
| 436 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 | ||
| 437 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 | ||
| 438 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 | ||
| 439 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 | ||
| 440 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 | ||
| 441 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 | ||
| 442 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 | ||
| 443 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 | ||
| 444 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 | ||
| 445 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 | ||
| 446 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 | ||
| 447 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 | ||
| 448 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 | ||
| 449 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 | ||
| 450 | #define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 | ||
| 451 | |||
| 452 | /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 453 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 | ||
| 454 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 | ||
| 455 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 | ||
| 456 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 | ||
| 457 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 | ||
| 458 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 | ||
| 459 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 | ||
| 460 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 | ||
| 461 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 | ||
| 462 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 | ||
| 463 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 | ||
| 464 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 | ||
| 465 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 | ||
| 466 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 | ||
| 467 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 | ||
| 468 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 | ||
| 469 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 | ||
| 470 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 | ||
| 471 | #define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 | ||
| 472 | |||
| 473 | /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ | ||
| 474 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 | ||
| 475 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 | ||
| 476 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 | ||
| 477 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 | ||
| 478 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 | ||
| 479 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 | ||
| 480 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 | ||
| 481 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 | ||
| 482 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 | ||
| 483 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 | ||
| 484 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 | ||
| 485 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 | ||
| 486 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 | ||
| 487 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 | ||
| 488 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 | ||
| 489 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 | ||
| 490 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 | ||
| 491 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 | ||
| 492 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 | ||
| 493 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 | ||
| 494 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 | ||
| 495 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 | ||
| 496 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 | ||
| 497 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 | ||
| 498 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 | ||
| 499 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 | ||
| 500 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 | ||
| 501 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 | ||
| 502 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 | ||
| 503 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 | ||
| 504 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 | ||
| 505 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 | ||
| 506 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 | ||
| 507 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 | ||
| 508 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 | ||
| 509 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 | ||
| 510 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 | ||
| 511 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 | ||
| 512 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 | ||
| 513 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 | ||
| 514 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 | ||
| 515 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 | ||
| 516 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 | ||
| 517 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 | ||
| 518 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 | ||
| 519 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 | ||
| 520 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 | ||
| 521 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 | ||
| 522 | #define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 | ||
| 523 | |||
| 524 | /* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ | ||
| 525 | #define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 | ||
| 526 | #define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 | ||
| 527 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 | ||
| 528 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 | ||
| 529 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 | ||
| 530 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 | ||
| 531 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 | ||
| 532 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 | ||
| 533 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 | ||
| 534 | #define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 | ||
| 535 | #define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 | ||
| 536 | |||
| 537 | /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ | ||
| 538 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 | ||
| 539 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 | ||
| 540 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 | ||
| 541 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 | ||
| 542 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 | ||
| 543 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 | ||
| 544 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 | ||
| 545 | #define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 | ||
| 546 | #define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 | ||
| 547 | |||
| 548 | |||
| 549 | /* Constants */ | ||
| 550 | #define regk_iop_sw_cfg_a 0x00000001 | ||
| 551 | #define regk_iop_sw_cfg_b 0x00000002 | ||
| 552 | #define regk_iop_sw_cfg_bus 0x00000000 | ||
| 553 | #define regk_iop_sw_cfg_bus_rot16 0x00000002 | ||
| 554 | #define regk_iop_sw_cfg_bus_rot24 0x00000003 | ||
| 555 | #define regk_iop_sw_cfg_bus_rot8 0x00000001 | ||
| 556 | #define regk_iop_sw_cfg_clk12 0x00000000 | ||
| 557 | #define regk_iop_sw_cfg_cpu 0x00000000 | ||
| 558 | #define regk_iop_sw_cfg_gated_clk0 0x0000000e | ||
| 559 | #define regk_iop_sw_cfg_gated_clk1 0x0000000f | ||
| 560 | #define regk_iop_sw_cfg_gio0 0x00000004 | ||
| 561 | #define regk_iop_sw_cfg_gio1 0x00000001 | ||
| 562 | #define regk_iop_sw_cfg_gio2 0x00000005 | ||
| 563 | #define regk_iop_sw_cfg_gio3 0x00000002 | ||
| 564 | #define regk_iop_sw_cfg_gio4 0x00000006 | ||
| 565 | #define regk_iop_sw_cfg_gio5 0x00000003 | ||
| 566 | #define regk_iop_sw_cfg_gio6 0x00000007 | ||
| 567 | #define regk_iop_sw_cfg_gio7 0x00000004 | ||
| 568 | #define regk_iop_sw_cfg_gio_in18 0x00000002 | ||
| 569 | #define regk_iop_sw_cfg_gio_in19 0x00000003 | ||
| 570 | #define regk_iop_sw_cfg_gio_in20 0x00000004 | ||
| 571 | #define regk_iop_sw_cfg_gio_in21 0x00000005 | ||
| 572 | #define regk_iop_sw_cfg_gio_in26 0x00000006 | ||
| 573 | #define regk_iop_sw_cfg_gio_in27 0x00000007 | ||
| 574 | #define regk_iop_sw_cfg_gio_in4 0x00000000 | ||
| 575 | #define regk_iop_sw_cfg_gio_in5 0x00000001 | ||
| 576 | #define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 | ||
| 577 | #define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 | ||
| 578 | #define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 | ||
| 579 | #define regk_iop_sw_cfg_mpu 0x00000001 | ||
| 580 | #define regk_iop_sw_cfg_none 0x00000000 | ||
| 581 | #define regk_iop_sw_cfg_pdp_out 0x00000001 | ||
| 582 | #define regk_iop_sw_cfg_pdp_out_hi 0x00000001 | ||
| 583 | #define regk_iop_sw_cfg_pdp_out_lo 0x00000000 | ||
| 584 | #define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 | ||
| 585 | #define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 | ||
| 586 | #define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 | ||
| 587 | #define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 | ||
| 588 | #define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 | ||
| 589 | #define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 | ||
| 590 | #define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 | ||
| 591 | #define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 | ||
| 592 | #define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 | ||
| 593 | #define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 | ||
| 594 | #define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 | ||
| 595 | #define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 | ||
| 596 | #define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 | ||
| 597 | #define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 | ||
| 598 | #define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 | ||
| 599 | #define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 | ||
| 600 | #define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 | ||
| 601 | #define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 | ||
| 602 | #define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 | ||
| 603 | #define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 | ||
| 604 | #define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 | ||
| 605 | #define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 | ||
| 606 | #define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 | ||
| 607 | #define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 | ||
| 608 | #define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 | ||
| 609 | #define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 | ||
| 610 | #define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 | ||
| 611 | #define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 | ||
| 612 | #define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 | ||
| 613 | #define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 | ||
| 614 | #define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 | ||
| 615 | #define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 | ||
| 616 | #define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 | ||
| 617 | #define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 | ||
| 618 | #define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 | ||
| 619 | #define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 | ||
| 620 | #define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 | ||
| 621 | #define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 | ||
| 622 | #define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 | ||
| 623 | #define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 | ||
| 624 | #define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 | ||
| 625 | #define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 | ||
| 626 | #define regk_iop_sw_cfg_sdp_out 0x00000004 | ||
| 627 | #define regk_iop_sw_cfg_size16 0x00000002 | ||
| 628 | #define regk_iop_sw_cfg_size24 0x00000003 | ||
| 629 | #define regk_iop_sw_cfg_size32 0x00000004 | ||
| 630 | #define regk_iop_sw_cfg_size8 0x00000001 | ||
| 631 | #define regk_iop_sw_cfg_spu 0x00000002 | ||
| 632 | #define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 | ||
| 633 | #define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 | ||
| 634 | #define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 | ||
| 635 | #define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 | ||
| 636 | #define regk_iop_sw_cfg_spu_g0 0x00000007 | ||
| 637 | #define regk_iop_sw_cfg_spu_g1 0x00000007 | ||
| 638 | #define regk_iop_sw_cfg_spu_g2 0x00000007 | ||
| 639 | #define regk_iop_sw_cfg_spu_g3 0x00000007 | ||
| 640 | #define regk_iop_sw_cfg_spu_g4 0x00000007 | ||
| 641 | #define regk_iop_sw_cfg_spu_g5 0x00000007 | ||
| 642 | #define regk_iop_sw_cfg_spu_g6 0x00000007 | ||
| 643 | #define regk_iop_sw_cfg_spu_g7 0x00000007 | ||
| 644 | #define regk_iop_sw_cfg_spu_gio0 0x00000000 | ||
| 645 | #define regk_iop_sw_cfg_spu_gio1 0x00000001 | ||
| 646 | #define regk_iop_sw_cfg_spu_gio5 0x00000005 | ||
| 647 | #define regk_iop_sw_cfg_spu_gio6 0x00000006 | ||
| 648 | #define regk_iop_sw_cfg_spu_gio7 0x00000007 | ||
| 649 | #define regk_iop_sw_cfg_spu_gio_out0 0x00000008 | ||
| 650 | #define regk_iop_sw_cfg_spu_gio_out1 0x00000009 | ||
| 651 | #define regk_iop_sw_cfg_spu_gio_out2 0x0000000a | ||
| 652 | #define regk_iop_sw_cfg_spu_gio_out3 0x0000000b | ||
| 653 | #define regk_iop_sw_cfg_spu_gio_out4 0x0000000c | ||
| 654 | #define regk_iop_sw_cfg_spu_gio_out5 0x0000000d | ||
| 655 | #define regk_iop_sw_cfg_spu_gio_out6 0x0000000e | ||
| 656 | #define regk_iop_sw_cfg_spu_gio_out7 0x0000000f | ||
| 657 | #define regk_iop_sw_cfg_spu_gioout0 0x00000000 | ||
| 658 | #define regk_iop_sw_cfg_spu_gioout1 0x00000000 | ||
| 659 | #define regk_iop_sw_cfg_spu_gioout10 0x00000007 | ||
| 660 | #define regk_iop_sw_cfg_spu_gioout11 0x00000007 | ||
| 661 | #define regk_iop_sw_cfg_spu_gioout12 0x00000007 | ||
| 662 | #define regk_iop_sw_cfg_spu_gioout13 0x00000007 | ||
| 663 | #define regk_iop_sw_cfg_spu_gioout14 0x00000007 | ||
| 664 | #define regk_iop_sw_cfg_spu_gioout15 0x00000007 | ||
| 665 | #define regk_iop_sw_cfg_spu_gioout16 0x00000007 | ||
| 666 | #define regk_iop_sw_cfg_spu_gioout17 0x00000007 | ||
| 667 | #define regk_iop_sw_cfg_spu_gioout18 0x00000007 | ||
| 668 | #define regk_iop_sw_cfg_spu_gioout19 0x00000007 | ||
| 669 | #define regk_iop_sw_cfg_spu_gioout2 0x00000001 | ||
| 670 | #define regk_iop_sw_cfg_spu_gioout20 0x00000007 | ||
| 671 | #define regk_iop_sw_cfg_spu_gioout21 0x00000007 | ||
| 672 | #define regk_iop_sw_cfg_spu_gioout22 0x00000007 | ||
| 673 | #define regk_iop_sw_cfg_spu_gioout23 0x00000007 | ||
| 674 | #define regk_iop_sw_cfg_spu_gioout24 0x00000007 | ||
| 675 | #define regk_iop_sw_cfg_spu_gioout25 0x00000007 | ||
| 676 | #define regk_iop_sw_cfg_spu_gioout26 0x00000007 | ||
| 677 | #define regk_iop_sw_cfg_spu_gioout27 0x00000007 | ||
| 678 | #define regk_iop_sw_cfg_spu_gioout28 0x00000007 | ||
| 679 | #define regk_iop_sw_cfg_spu_gioout29 0x00000007 | ||
| 680 | #define regk_iop_sw_cfg_spu_gioout3 0x00000001 | ||
| 681 | #define regk_iop_sw_cfg_spu_gioout30 0x00000007 | ||
| 682 | #define regk_iop_sw_cfg_spu_gioout31 0x00000007 | ||
| 683 | #define regk_iop_sw_cfg_spu_gioout4 0x00000002 | ||
| 684 | #define regk_iop_sw_cfg_spu_gioout5 0x00000002 | ||
| 685 | #define regk_iop_sw_cfg_spu_gioout6 0x00000003 | ||
| 686 | #define regk_iop_sw_cfg_spu_gioout7 0x00000003 | ||
| 687 | #define regk_iop_sw_cfg_spu_gioout8 0x00000007 | ||
| 688 | #define regk_iop_sw_cfg_spu_gioout9 0x00000007 | ||
| 689 | #define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 | ||
| 690 | #define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 | ||
| 691 | #define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 | ||
| 692 | #define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 | ||
| 693 | #define regk_iop_sw_cfg_timer_grp0 0x00000000 | ||
| 694 | #define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 | ||
| 695 | #define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 | ||
| 696 | #define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 | ||
| 697 | #define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 | ||
| 698 | #define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 | ||
| 699 | #define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 | ||
| 700 | #define regk_iop_sw_cfg_timer_grp1 0x00000000 | ||
| 701 | #define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 | ||
| 702 | #define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 | ||
| 703 | #define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 | ||
| 704 | #define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 | ||
| 705 | #define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 | ||
| 706 | #define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 | ||
| 707 | #define regk_iop_sw_cfg_trig0_0 0x00000000 | ||
| 708 | #define regk_iop_sw_cfg_trig0_1 0x00000000 | ||
| 709 | #define regk_iop_sw_cfg_trig0_2 0x00000000 | ||
| 710 | #define regk_iop_sw_cfg_trig0_3 0x00000000 | ||
| 711 | #define regk_iop_sw_cfg_trig1_0 0x00000000 | ||
| 712 | #define regk_iop_sw_cfg_trig1_1 0x00000000 | ||
| 713 | #define regk_iop_sw_cfg_trig1_2 0x00000000 | ||
| 714 | #define regk_iop_sw_cfg_trig1_3 0x00000000 | ||
| 715 | #define regk_iop_sw_cfg_trig2_0 0x00000001 | ||
| 716 | #define regk_iop_sw_cfg_trig2_1 0x00000001 | ||
| 717 | #define regk_iop_sw_cfg_trig2_2 0x00000001 | ||
| 718 | #define regk_iop_sw_cfg_trig2_3 0x00000001 | ||
| 719 | #define regk_iop_sw_cfg_trig3_0 0x00000001 | ||
| 720 | #define regk_iop_sw_cfg_trig3_1 0x00000001 | ||
| 721 | #define regk_iop_sw_cfg_trig3_2 0x00000001 | ||
| 722 | #define regk_iop_sw_cfg_trig3_3 0x00000001 | ||
| 723 | #define regk_iop_sw_cfg_trig4_0 0x00000002 | ||
| 724 | #define regk_iop_sw_cfg_trig4_1 0x00000002 | ||
| 725 | #define regk_iop_sw_cfg_trig4_2 0x00000002 | ||
| 726 | #define regk_iop_sw_cfg_trig4_3 0x00000002 | ||
| 727 | #define regk_iop_sw_cfg_trig5_0 0x00000002 | ||
| 728 | #define regk_iop_sw_cfg_trig5_1 0x00000002 | ||
| 729 | #define regk_iop_sw_cfg_trig5_2 0x00000002 | ||
| 730 | #define regk_iop_sw_cfg_trig5_3 0x00000002 | ||
| 731 | #define regk_iop_sw_cfg_trig6_0 0x00000003 | ||
| 732 | #define regk_iop_sw_cfg_trig6_1 0x00000003 | ||
| 733 | #define regk_iop_sw_cfg_trig6_2 0x00000003 | ||
| 734 | #define regk_iop_sw_cfg_trig6_3 0x00000003 | ||
| 735 | #define regk_iop_sw_cfg_trig7_0 0x00000003 | ||
| 736 | #define regk_iop_sw_cfg_trig7_1 0x00000003 | ||
| 737 | #define regk_iop_sw_cfg_trig7_2 0x00000003 | ||
| 738 | #define regk_iop_sw_cfg_trig7_3 0x00000003 | ||
| 739 | #endif /* __iop_sw_cfg_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h new file mode 100644 index 000000000000..3f4fe1b31815 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_cpu_defs_asm.h | |||
| @@ -0,0 +1,950 @@ | |||
| 1 | #ifndef __iop_sw_cpu_defs_asm_h | ||
| 2 | #define __iop_sw_cpu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_cpu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register r_mpu_trace, scope iop_sw_cpu, type r */ | ||
| 54 | #define reg_iop_sw_cpu_r_mpu_trace_offset 0 | ||
| 55 | |||
| 56 | /* Register r_spu_trace, scope iop_sw_cpu, type r */ | ||
| 57 | #define reg_iop_sw_cpu_r_spu_trace_offset 4 | ||
| 58 | |||
| 59 | /* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ | ||
| 60 | #define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 | ||
| 61 | |||
| 62 | /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ | ||
| 63 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 | ||
| 64 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 | ||
| 65 | #define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 | ||
| 66 | #define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 | ||
| 67 | #define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 | ||
| 68 | #define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 | ||
| 69 | #define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 | ||
| 70 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 | ||
| 71 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 | ||
| 72 | #define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 | ||
| 73 | #define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 | ||
| 74 | |||
| 75 | /* Register rw_mc_data, scope iop_sw_cpu, type rw */ | ||
| 76 | #define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 | ||
| 77 | #define reg_iop_sw_cpu_rw_mc_data___val___width 32 | ||
| 78 | #define reg_iop_sw_cpu_rw_mc_data_offset 16 | ||
| 79 | |||
| 80 | /* Register rw_mc_addr, scope iop_sw_cpu, type rw */ | ||
| 81 | #define reg_iop_sw_cpu_rw_mc_addr_offset 20 | ||
| 82 | |||
| 83 | /* Register rs_mc_data, scope iop_sw_cpu, type rs */ | ||
| 84 | #define reg_iop_sw_cpu_rs_mc_data_offset 24 | ||
| 85 | |||
| 86 | /* Register r_mc_data, scope iop_sw_cpu, type r */ | ||
| 87 | #define reg_iop_sw_cpu_r_mc_data_offset 28 | ||
| 88 | |||
| 89 | /* Register r_mc_stat, scope iop_sw_cpu, type r */ | ||
| 90 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 | ||
| 91 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 | ||
| 92 | #define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 | ||
| 93 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 | ||
| 94 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 | ||
| 95 | #define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 | ||
| 96 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 | ||
| 97 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 | ||
| 98 | #define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 | ||
| 99 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 | ||
| 100 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 | ||
| 101 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 | ||
| 102 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 | ||
| 103 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 | ||
| 104 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 | ||
| 105 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 | ||
| 106 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 | ||
| 107 | #define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 | ||
| 108 | #define reg_iop_sw_cpu_r_mc_stat_offset 32 | ||
| 109 | |||
| 110 | /* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 111 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 | ||
| 112 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 | ||
| 113 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 | ||
| 114 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 | ||
| 115 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 | ||
| 116 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 | ||
| 117 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 | ||
| 118 | #define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 | ||
| 119 | #define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 | ||
| 120 | |||
| 121 | /* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ | ||
| 122 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 | ||
| 123 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 | ||
| 124 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 | ||
| 125 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 | ||
| 126 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 | ||
| 127 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 | ||
| 128 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 | ||
| 129 | #define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 | ||
| 130 | #define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 | ||
| 131 | |||
| 132 | /* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 133 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 | ||
| 134 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 | ||
| 135 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 | ||
| 136 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 | ||
| 137 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 | ||
| 138 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 | ||
| 139 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 | ||
| 140 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 | ||
| 141 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 | ||
| 142 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 | ||
| 143 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 | ||
| 144 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 | ||
| 145 | #define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 | ||
| 146 | |||
| 147 | /* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 148 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 | ||
| 149 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 | ||
| 150 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 | ||
| 151 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 | ||
| 152 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 | ||
| 153 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 | ||
| 154 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 | ||
| 155 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 | ||
| 156 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 | ||
| 157 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 | ||
| 158 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 | ||
| 159 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 | ||
| 160 | #define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 | ||
| 161 | |||
| 162 | /* Register r_bus_in, scope iop_sw_cpu, type r */ | ||
| 163 | #define reg_iop_sw_cpu_r_bus_in_offset 52 | ||
| 164 | |||
| 165 | /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 166 | #define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 | ||
| 167 | #define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 | ||
| 168 | #define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 | ||
| 169 | |||
| 170 | /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ | ||
| 171 | #define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 | ||
| 172 | #define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 | ||
| 173 | #define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 | ||
| 174 | |||
| 175 | /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 176 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 | ||
| 177 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 | ||
| 178 | #define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 | ||
| 179 | |||
| 180 | /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 181 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 | ||
| 182 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 | ||
| 183 | #define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 | ||
| 184 | |||
| 185 | /* Register r_gio_in, scope iop_sw_cpu, type r */ | ||
| 186 | #define reg_iop_sw_cpu_r_gio_in_offset 72 | ||
| 187 | |||
| 188 | /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ | ||
| 189 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 | ||
| 190 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 | ||
| 191 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 | ||
| 192 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 | ||
| 193 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 | ||
| 194 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 | ||
| 195 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 | ||
| 196 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 | ||
| 197 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 | ||
| 198 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 | ||
| 199 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 | ||
| 200 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 | ||
| 201 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 | ||
| 202 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 | ||
| 203 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 | ||
| 204 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 | ||
| 205 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 | ||
| 206 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 | ||
| 207 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 | ||
| 208 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 | ||
| 209 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 | ||
| 210 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 | ||
| 211 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 | ||
| 212 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 | ||
| 213 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 | ||
| 214 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 | ||
| 215 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 | ||
| 216 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 | ||
| 217 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 | ||
| 218 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 | ||
| 219 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 | ||
| 220 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 | ||
| 221 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 | ||
| 222 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 | ||
| 223 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 | ||
| 224 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 | ||
| 225 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 | ||
| 226 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 | ||
| 227 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 | ||
| 228 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 | ||
| 229 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 | ||
| 230 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 | ||
| 231 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 | ||
| 232 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 | ||
| 233 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 | ||
| 234 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 | ||
| 235 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 | ||
| 236 | #define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 | ||
| 237 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 | ||
| 238 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 | ||
| 239 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 | ||
| 240 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 | ||
| 241 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 | ||
| 242 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 | ||
| 243 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 | ||
| 244 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 | ||
| 245 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 | ||
| 246 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 | ||
| 247 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 | ||
| 248 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 | ||
| 249 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 | ||
| 250 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 | ||
| 251 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 | ||
| 252 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 | ||
| 253 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 | ||
| 254 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 | ||
| 255 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 | ||
| 256 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 | ||
| 257 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 | ||
| 258 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 | ||
| 259 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 | ||
| 260 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 | ||
| 261 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 | ||
| 262 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 | ||
| 263 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 | ||
| 264 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 | ||
| 265 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 | ||
| 266 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 | ||
| 267 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 | ||
| 268 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 | ||
| 269 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 | ||
| 270 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 | ||
| 271 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 | ||
| 272 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 | ||
| 273 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 | ||
| 274 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 | ||
| 275 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 | ||
| 276 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 | ||
| 277 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 | ||
| 278 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 | ||
| 279 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 | ||
| 280 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 | ||
| 281 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 | ||
| 282 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 | ||
| 283 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 | ||
| 284 | #define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 | ||
| 285 | #define reg_iop_sw_cpu_rw_intr0_mask_offset 76 | ||
| 286 | |||
| 287 | /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ | ||
| 288 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 | ||
| 289 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 | ||
| 290 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 | ||
| 291 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 | ||
| 292 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 | ||
| 293 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 | ||
| 294 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 | ||
| 295 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 | ||
| 296 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 | ||
| 297 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 | ||
| 298 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 | ||
| 299 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 | ||
| 300 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 | ||
| 301 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 | ||
| 302 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 | ||
| 303 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 | ||
| 304 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 | ||
| 305 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 | ||
| 306 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 | ||
| 307 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 | ||
| 308 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 | ||
| 309 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 | ||
| 310 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 | ||
| 311 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 | ||
| 312 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 | ||
| 313 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 | ||
| 314 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 | ||
| 315 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 | ||
| 316 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 | ||
| 317 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 | ||
| 318 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 | ||
| 319 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 | ||
| 320 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 | ||
| 321 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 | ||
| 322 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 | ||
| 323 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 | ||
| 324 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 | ||
| 325 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 | ||
| 326 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 | ||
| 327 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 | ||
| 328 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 | ||
| 329 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 | ||
| 330 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 | ||
| 331 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 | ||
| 332 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 | ||
| 333 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 | ||
| 334 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 | ||
| 335 | #define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 | ||
| 336 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 | ||
| 337 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 | ||
| 338 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 | ||
| 339 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 | ||
| 340 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 | ||
| 341 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 | ||
| 342 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 | ||
| 343 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 | ||
| 344 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 | ||
| 345 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 | ||
| 346 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 | ||
| 347 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 | ||
| 348 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 | ||
| 349 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 | ||
| 350 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 | ||
| 351 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 | ||
| 352 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 | ||
| 353 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 | ||
| 354 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 | ||
| 355 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 | ||
| 356 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 | ||
| 357 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 | ||
| 358 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 | ||
| 359 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 | ||
| 360 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 | ||
| 361 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 | ||
| 362 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 | ||
| 363 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 | ||
| 364 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 | ||
| 365 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 | ||
| 366 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 | ||
| 367 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 | ||
| 368 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 | ||
| 369 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 | ||
| 370 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 | ||
| 371 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 | ||
| 372 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 | ||
| 373 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 | ||
| 374 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 | ||
| 375 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 | ||
| 376 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 | ||
| 377 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 | ||
| 378 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 | ||
| 379 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 | ||
| 380 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 | ||
| 381 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 | ||
| 382 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 | ||
| 383 | #define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 | ||
| 384 | #define reg_iop_sw_cpu_rw_ack_intr0_offset 80 | ||
| 385 | |||
| 386 | /* Register r_intr0, scope iop_sw_cpu, type r */ | ||
| 387 | #define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 | ||
| 388 | #define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 | ||
| 389 | #define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 | ||
| 390 | #define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 | ||
| 391 | #define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 | ||
| 392 | #define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 | ||
| 393 | #define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 | ||
| 394 | #define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 | ||
| 395 | #define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 | ||
| 396 | #define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 | ||
| 397 | #define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 | ||
| 398 | #define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 | ||
| 399 | #define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 | ||
| 400 | #define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 | ||
| 401 | #define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 | ||
| 402 | #define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 | ||
| 403 | #define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 | ||
| 404 | #define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 | ||
| 405 | #define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 | ||
| 406 | #define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 | ||
| 407 | #define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 | ||
| 408 | #define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 | ||
| 409 | #define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 | ||
| 410 | #define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 | ||
| 411 | #define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 | ||
| 412 | #define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 | ||
| 413 | #define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 | ||
| 414 | #define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 | ||
| 415 | #define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 | ||
| 416 | #define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 | ||
| 417 | #define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 | ||
| 418 | #define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 | ||
| 419 | #define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 | ||
| 420 | #define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 | ||
| 421 | #define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 | ||
| 422 | #define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 | ||
| 423 | #define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 | ||
| 424 | #define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 | ||
| 425 | #define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 | ||
| 426 | #define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 | ||
| 427 | #define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 | ||
| 428 | #define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 | ||
| 429 | #define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 | ||
| 430 | #define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 | ||
| 431 | #define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 | ||
| 432 | #define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 | ||
| 433 | #define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 | ||
| 434 | #define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 | ||
| 435 | #define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 | ||
| 436 | #define reg_iop_sw_cpu_r_intr0___spu_0___width 1 | ||
| 437 | #define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 | ||
| 438 | #define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 | ||
| 439 | #define reg_iop_sw_cpu_r_intr0___spu_1___width 1 | ||
| 440 | #define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 | ||
| 441 | #define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 | ||
| 442 | #define reg_iop_sw_cpu_r_intr0___spu_2___width 1 | ||
| 443 | #define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 | ||
| 444 | #define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 | ||
| 445 | #define reg_iop_sw_cpu_r_intr0___spu_3___width 1 | ||
| 446 | #define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 | ||
| 447 | #define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 | ||
| 448 | #define reg_iop_sw_cpu_r_intr0___spu_4___width 1 | ||
| 449 | #define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 | ||
| 450 | #define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 | ||
| 451 | #define reg_iop_sw_cpu_r_intr0___spu_5___width 1 | ||
| 452 | #define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 | ||
| 453 | #define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 | ||
| 454 | #define reg_iop_sw_cpu_r_intr0___spu_6___width 1 | ||
| 455 | #define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 | ||
| 456 | #define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 | ||
| 457 | #define reg_iop_sw_cpu_r_intr0___spu_7___width 1 | ||
| 458 | #define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 | ||
| 459 | #define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 | ||
| 460 | #define reg_iop_sw_cpu_r_intr0___spu_8___width 1 | ||
| 461 | #define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 | ||
| 462 | #define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 | ||
| 463 | #define reg_iop_sw_cpu_r_intr0___spu_9___width 1 | ||
| 464 | #define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 | ||
| 465 | #define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 | ||
| 466 | #define reg_iop_sw_cpu_r_intr0___spu_10___width 1 | ||
| 467 | #define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 | ||
| 468 | #define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 | ||
| 469 | #define reg_iop_sw_cpu_r_intr0___spu_11___width 1 | ||
| 470 | #define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 | ||
| 471 | #define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 | ||
| 472 | #define reg_iop_sw_cpu_r_intr0___spu_12___width 1 | ||
| 473 | #define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 | ||
| 474 | #define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 | ||
| 475 | #define reg_iop_sw_cpu_r_intr0___spu_13___width 1 | ||
| 476 | #define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 | ||
| 477 | #define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 | ||
| 478 | #define reg_iop_sw_cpu_r_intr0___spu_14___width 1 | ||
| 479 | #define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 | ||
| 480 | #define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 | ||
| 481 | #define reg_iop_sw_cpu_r_intr0___spu_15___width 1 | ||
| 482 | #define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 | ||
| 483 | #define reg_iop_sw_cpu_r_intr0_offset 84 | ||
| 484 | |||
| 485 | /* Register r_masked_intr0, scope iop_sw_cpu, type r */ | ||
| 486 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 | ||
| 487 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 | ||
| 488 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 | ||
| 489 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 | ||
| 490 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 | ||
| 491 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 | ||
| 492 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 | ||
| 493 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 | ||
| 494 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 | ||
| 495 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 | ||
| 496 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 | ||
| 497 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 | ||
| 498 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 | ||
| 499 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 | ||
| 500 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 | ||
| 501 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 | ||
| 502 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 | ||
| 503 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 | ||
| 504 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 | ||
| 505 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 | ||
| 506 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 | ||
| 507 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 | ||
| 508 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 | ||
| 509 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 | ||
| 510 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 | ||
| 511 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 | ||
| 512 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 | ||
| 513 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 | ||
| 514 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 | ||
| 515 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 | ||
| 516 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 | ||
| 517 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 | ||
| 518 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 | ||
| 519 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 | ||
| 520 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 | ||
| 521 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 | ||
| 522 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 | ||
| 523 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 | ||
| 524 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 | ||
| 525 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 | ||
| 526 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 | ||
| 527 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 | ||
| 528 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 | ||
| 529 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 | ||
| 530 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 | ||
| 531 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 | ||
| 532 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 | ||
| 533 | #define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 | ||
| 534 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 | ||
| 535 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 | ||
| 536 | #define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 | ||
| 537 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 | ||
| 538 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 | ||
| 539 | #define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 | ||
| 540 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 | ||
| 541 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 | ||
| 542 | #define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 | ||
| 543 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 | ||
| 544 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 | ||
| 545 | #define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 | ||
| 546 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 | ||
| 547 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 | ||
| 548 | #define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 | ||
| 549 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 | ||
| 550 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 | ||
| 551 | #define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 | ||
| 552 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 | ||
| 553 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 | ||
| 554 | #define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 | ||
| 555 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 | ||
| 556 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 | ||
| 557 | #define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 | ||
| 558 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 | ||
| 559 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 | ||
| 560 | #define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 | ||
| 561 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 | ||
| 562 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 | ||
| 563 | #define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 | ||
| 564 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 | ||
| 565 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 | ||
| 566 | #define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 | ||
| 567 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 | ||
| 568 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 | ||
| 569 | #define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 | ||
| 570 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 | ||
| 571 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 | ||
| 572 | #define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 | ||
| 573 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 | ||
| 574 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 | ||
| 575 | #define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 | ||
| 576 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 | ||
| 577 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 | ||
| 578 | #define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 | ||
| 579 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 | ||
| 580 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 | ||
| 581 | #define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 | ||
| 582 | #define reg_iop_sw_cpu_r_masked_intr0_offset 88 | ||
| 583 | |||
| 584 | /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ | ||
| 585 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 | ||
| 586 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 | ||
| 587 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 | ||
| 588 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 | ||
| 589 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 | ||
| 590 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 | ||
| 591 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 | ||
| 592 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 | ||
| 593 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 | ||
| 594 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 | ||
| 595 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 | ||
| 596 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 | ||
| 597 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 | ||
| 598 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 | ||
| 599 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 | ||
| 600 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 | ||
| 601 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 | ||
| 602 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 | ||
| 603 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 | ||
| 604 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 | ||
| 605 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 | ||
| 606 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 | ||
| 607 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 | ||
| 608 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 | ||
| 609 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 | ||
| 610 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 | ||
| 611 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 | ||
| 612 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 | ||
| 613 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 | ||
| 614 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 | ||
| 615 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 | ||
| 616 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 | ||
| 617 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 | ||
| 618 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 | ||
| 619 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 | ||
| 620 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 | ||
| 621 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 | ||
| 622 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 | ||
| 623 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 | ||
| 624 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 | ||
| 625 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 | ||
| 626 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 | ||
| 627 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 | ||
| 628 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 | ||
| 629 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 | ||
| 630 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 | ||
| 631 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 | ||
| 632 | #define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 | ||
| 633 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 | ||
| 634 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 | ||
| 635 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 | ||
| 636 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 | ||
| 637 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 | ||
| 638 | #define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 | ||
| 639 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 | ||
| 640 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 | ||
| 641 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 | ||
| 642 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 | ||
| 643 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 | ||
| 644 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 | ||
| 645 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 | ||
| 646 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 | ||
| 647 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 | ||
| 648 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 | ||
| 649 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 | ||
| 650 | #define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 | ||
| 651 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 | ||
| 652 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 | ||
| 653 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 | ||
| 654 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 | ||
| 655 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 | ||
| 656 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 | ||
| 657 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 | ||
| 658 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 | ||
| 659 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 | ||
| 660 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 | ||
| 661 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 | ||
| 662 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 | ||
| 663 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 | ||
| 664 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 | ||
| 665 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 | ||
| 666 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 | ||
| 667 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 | ||
| 668 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 | ||
| 669 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 | ||
| 670 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 | ||
| 671 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 | ||
| 672 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 | ||
| 673 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 | ||
| 674 | #define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 | ||
| 675 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 | ||
| 676 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 | ||
| 677 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 | ||
| 678 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 | ||
| 679 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 | ||
| 680 | #define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 | ||
| 681 | #define reg_iop_sw_cpu_rw_intr1_mask_offset 92 | ||
| 682 | |||
| 683 | /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ | ||
| 684 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 | ||
| 685 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 | ||
| 686 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 | ||
| 687 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 | ||
| 688 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 | ||
| 689 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 | ||
| 690 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 | ||
| 691 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 | ||
| 692 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 | ||
| 693 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 | ||
| 694 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 | ||
| 695 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 | ||
| 696 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 | ||
| 697 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 | ||
| 698 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 | ||
| 699 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 | ||
| 700 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 | ||
| 701 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 | ||
| 702 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 | ||
| 703 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 | ||
| 704 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 | ||
| 705 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 | ||
| 706 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 | ||
| 707 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 | ||
| 708 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 | ||
| 709 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 | ||
| 710 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 | ||
| 711 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 | ||
| 712 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 | ||
| 713 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 | ||
| 714 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 | ||
| 715 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 | ||
| 716 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 | ||
| 717 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 | ||
| 718 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 | ||
| 719 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 | ||
| 720 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 | ||
| 721 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 | ||
| 722 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 | ||
| 723 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 | ||
| 724 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 | ||
| 725 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 | ||
| 726 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 | ||
| 727 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 | ||
| 728 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 | ||
| 729 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 | ||
| 730 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 | ||
| 731 | #define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 | ||
| 732 | #define reg_iop_sw_cpu_rw_ack_intr1_offset 96 | ||
| 733 | |||
| 734 | /* Register r_intr1, scope iop_sw_cpu, type r */ | ||
| 735 | #define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 | ||
| 736 | #define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 | ||
| 737 | #define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 | ||
| 738 | #define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 | ||
| 739 | #define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 | ||
| 740 | #define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 | ||
| 741 | #define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 | ||
| 742 | #define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 | ||
| 743 | #define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 | ||
| 744 | #define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 | ||
| 745 | #define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 | ||
| 746 | #define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 | ||
| 747 | #define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 | ||
| 748 | #define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 | ||
| 749 | #define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 | ||
| 750 | #define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 | ||
| 751 | #define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 | ||
| 752 | #define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 | ||
| 753 | #define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 | ||
| 754 | #define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 | ||
| 755 | #define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 | ||
| 756 | #define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 | ||
| 757 | #define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 | ||
| 758 | #define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 | ||
| 759 | #define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 | ||
| 760 | #define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 | ||
| 761 | #define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 | ||
| 762 | #define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 | ||
| 763 | #define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 | ||
| 764 | #define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 | ||
| 765 | #define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 | ||
| 766 | #define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 | ||
| 767 | #define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 | ||
| 768 | #define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 | ||
| 769 | #define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 | ||
| 770 | #define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 | ||
| 771 | #define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 | ||
| 772 | #define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 | ||
| 773 | #define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 | ||
| 774 | #define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 | ||
| 775 | #define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 | ||
| 776 | #define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 | ||
| 777 | #define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 | ||
| 778 | #define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 | ||
| 779 | #define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 | ||
| 780 | #define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 | ||
| 781 | #define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 | ||
| 782 | #define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 | ||
| 783 | #define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 | ||
| 784 | #define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 | ||
| 785 | #define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 | ||
| 786 | #define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 | ||
| 787 | #define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 | ||
| 788 | #define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 | ||
| 789 | #define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 | ||
| 790 | #define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 | ||
| 791 | #define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 | ||
| 792 | #define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 | ||
| 793 | #define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 | ||
| 794 | #define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 | ||
| 795 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 | ||
| 796 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 | ||
| 797 | #define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 | ||
| 798 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 | ||
| 799 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 | ||
| 800 | #define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 | ||
| 801 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 | ||
| 802 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 | ||
| 803 | #define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 | ||
| 804 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 | ||
| 805 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 | ||
| 806 | #define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 | ||
| 807 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 | ||
| 808 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 | ||
| 809 | #define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 | ||
| 810 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 | ||
| 811 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 | ||
| 812 | #define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 | ||
| 813 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 | ||
| 814 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 | ||
| 815 | #define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 | ||
| 816 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 | ||
| 817 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 | ||
| 818 | #define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 | ||
| 819 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 | ||
| 820 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 | ||
| 821 | #define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 | ||
| 822 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 | ||
| 823 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 | ||
| 824 | #define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 | ||
| 825 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 | ||
| 826 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 | ||
| 827 | #define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 | ||
| 828 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 | ||
| 829 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 | ||
| 830 | #define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 | ||
| 831 | #define reg_iop_sw_cpu_r_intr1_offset 100 | ||
| 832 | |||
| 833 | /* Register r_masked_intr1, scope iop_sw_cpu, type r */ | ||
| 834 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 | ||
| 835 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 | ||
| 836 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 | ||
| 837 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 | ||
| 838 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 | ||
| 839 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 | ||
| 840 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 | ||
| 841 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 | ||
| 842 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 | ||
| 843 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 | ||
| 844 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 | ||
| 845 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 | ||
| 846 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 | ||
| 847 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 | ||
| 848 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 | ||
| 849 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 | ||
| 850 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 | ||
| 851 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 | ||
| 852 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 | ||
| 853 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 | ||
| 854 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 | ||
| 855 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 | ||
| 856 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 | ||
| 857 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 | ||
| 858 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 | ||
| 859 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 | ||
| 860 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 | ||
| 861 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 | ||
| 862 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 | ||
| 863 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 | ||
| 864 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 | ||
| 865 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 | ||
| 866 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 | ||
| 867 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 | ||
| 868 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 | ||
| 869 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 | ||
| 870 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 | ||
| 871 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 | ||
| 872 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 | ||
| 873 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 | ||
| 874 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 | ||
| 875 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 | ||
| 876 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 | ||
| 877 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 | ||
| 878 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 | ||
| 879 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 | ||
| 880 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 | ||
| 881 | #define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 | ||
| 882 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 | ||
| 883 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 | ||
| 884 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 | ||
| 885 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 | ||
| 886 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 | ||
| 887 | #define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 | ||
| 888 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 | ||
| 889 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 | ||
| 890 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 | ||
| 891 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 | ||
| 892 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 | ||
| 893 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 | ||
| 894 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 | ||
| 895 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 | ||
| 896 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 | ||
| 897 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 | ||
| 898 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 | ||
| 899 | #define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 | ||
| 900 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 | ||
| 901 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 | ||
| 902 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 | ||
| 903 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 | ||
| 904 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 | ||
| 905 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 | ||
| 906 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 | ||
| 907 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 | ||
| 908 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 | ||
| 909 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 | ||
| 910 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 | ||
| 911 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 | ||
| 912 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 | ||
| 913 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 | ||
| 914 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 | ||
| 915 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 | ||
| 916 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 | ||
| 917 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 | ||
| 918 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 | ||
| 919 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 | ||
| 920 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 | ||
| 921 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 | ||
| 922 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 | ||
| 923 | #define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 | ||
| 924 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 | ||
| 925 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 | ||
| 926 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 | ||
| 927 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 | ||
| 928 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 | ||
| 929 | #define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 | ||
| 930 | #define reg_iop_sw_cpu_r_masked_intr1_offset 104 | ||
| 931 | |||
| 932 | |||
| 933 | /* Constants */ | ||
| 934 | #define regk_iop_sw_cpu_copy 0x00000000 | ||
| 935 | #define regk_iop_sw_cpu_no 0x00000000 | ||
| 936 | #define regk_iop_sw_cpu_rd 0x00000002 | ||
| 937 | #define regk_iop_sw_cpu_reg_copy 0x00000001 | ||
| 938 | #define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 | ||
| 939 | #define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 | ||
| 940 | #define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 | ||
| 941 | #define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 | ||
| 942 | #define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 | ||
| 943 | #define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 | ||
| 944 | #define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 | ||
| 945 | #define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 | ||
| 946 | #define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 | ||
| 947 | #define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 | ||
| 948 | #define regk_iop_sw_cpu_wr 0x00000003 | ||
| 949 | #define regk_iop_sw_cpu_yes 0x00000001 | ||
| 950 | #endif /* __iop_sw_cpu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h new file mode 100644 index 000000000000..ffcc83b22d21 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_mpu_defs_asm.h | |||
| @@ -0,0 +1,1086 @@ | |||
| 1 | #ifndef __iop_sw_mpu_defs_asm_h | ||
| 2 | #define __iop_sw_mpu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_mpu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ | ||
| 54 | #define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 | ||
| 55 | #define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 | ||
| 56 | #define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 | ||
| 57 | |||
| 58 | /* Register r_spu_trace, scope iop_sw_mpu, type r */ | ||
| 59 | #define reg_iop_sw_mpu_r_spu_trace_offset 4 | ||
| 60 | |||
| 61 | /* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ | ||
| 62 | #define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 | ||
| 63 | |||
| 64 | /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ | ||
| 65 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 | ||
| 66 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 | ||
| 67 | #define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 | ||
| 68 | #define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 | ||
| 69 | #define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 | ||
| 70 | #define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 | ||
| 71 | #define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 | ||
| 72 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 | ||
| 73 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 | ||
| 74 | #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 | ||
| 75 | #define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 | ||
| 76 | |||
| 77 | /* Register rw_mc_data, scope iop_sw_mpu, type rw */ | ||
| 78 | #define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 | ||
| 79 | #define reg_iop_sw_mpu_rw_mc_data___val___width 32 | ||
| 80 | #define reg_iop_sw_mpu_rw_mc_data_offset 16 | ||
| 81 | |||
| 82 | /* Register rw_mc_addr, scope iop_sw_mpu, type rw */ | ||
| 83 | #define reg_iop_sw_mpu_rw_mc_addr_offset 20 | ||
| 84 | |||
| 85 | /* Register rs_mc_data, scope iop_sw_mpu, type rs */ | ||
| 86 | #define reg_iop_sw_mpu_rs_mc_data_offset 24 | ||
| 87 | |||
| 88 | /* Register r_mc_data, scope iop_sw_mpu, type r */ | ||
| 89 | #define reg_iop_sw_mpu_r_mc_data_offset 28 | ||
| 90 | |||
| 91 | /* Register r_mc_stat, scope iop_sw_mpu, type r */ | ||
| 92 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 | ||
| 93 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 | ||
| 94 | #define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 | ||
| 95 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 | ||
| 96 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 | ||
| 97 | #define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 | ||
| 98 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 | ||
| 99 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 | ||
| 100 | #define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 | ||
| 101 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 | ||
| 102 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 | ||
| 103 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 | ||
| 104 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 | ||
| 105 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 | ||
| 106 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 | ||
| 107 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 | ||
| 108 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 | ||
| 109 | #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 | ||
| 110 | #define reg_iop_sw_mpu_r_mc_stat_offset 32 | ||
| 111 | |||
| 112 | /* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 113 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 | ||
| 114 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 | ||
| 115 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 | ||
| 116 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 | ||
| 117 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 | ||
| 118 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 | ||
| 119 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 | ||
| 120 | #define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 | ||
| 121 | #define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 | ||
| 122 | |||
| 123 | /* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ | ||
| 124 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 | ||
| 125 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 | ||
| 126 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 | ||
| 127 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 | ||
| 128 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 | ||
| 129 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 | ||
| 130 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 | ||
| 131 | #define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 | ||
| 132 | #define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 | ||
| 133 | |||
| 134 | /* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 135 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 | ||
| 136 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 | ||
| 137 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 | ||
| 138 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 | ||
| 139 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 | ||
| 140 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 | ||
| 141 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 | ||
| 142 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 | ||
| 143 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 | ||
| 144 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 | ||
| 145 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 | ||
| 146 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 | ||
| 147 | #define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 | ||
| 148 | |||
| 149 | /* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 150 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 | ||
| 151 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 | ||
| 152 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 | ||
| 153 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 | ||
| 154 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 | ||
| 155 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 | ||
| 156 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 | ||
| 157 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 | ||
| 158 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 | ||
| 159 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 | ||
| 160 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 | ||
| 161 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 | ||
| 162 | #define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 | ||
| 163 | |||
| 164 | /* Register r_bus_in, scope iop_sw_mpu, type r */ | ||
| 165 | #define reg_iop_sw_mpu_r_bus_in_offset 52 | ||
| 166 | |||
| 167 | /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 168 | #define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 | ||
| 169 | #define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 | ||
| 170 | #define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 | ||
| 171 | |||
| 172 | /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ | ||
| 173 | #define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 | ||
| 174 | #define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 | ||
| 175 | #define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 | ||
| 176 | |||
| 177 | /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 178 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 | ||
| 179 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 | ||
| 180 | #define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 | ||
| 181 | |||
| 182 | /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 183 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 | ||
| 184 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 | ||
| 185 | #define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 | ||
| 186 | |||
| 187 | /* Register r_gio_in, scope iop_sw_mpu, type r */ | ||
| 188 | #define reg_iop_sw_mpu_r_gio_in_offset 72 | ||
| 189 | |||
| 190 | /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ | ||
| 191 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 | ||
| 192 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 | ||
| 193 | #define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 | ||
| 194 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 | ||
| 195 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 | ||
| 196 | #define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 | ||
| 197 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 | ||
| 198 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 | ||
| 199 | #define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 | ||
| 200 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 | ||
| 201 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 | ||
| 202 | #define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 | ||
| 203 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 | ||
| 204 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 | ||
| 205 | #define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 | ||
| 206 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 | ||
| 207 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 | ||
| 208 | #define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 | ||
| 209 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 | ||
| 210 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 | ||
| 211 | #define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 | ||
| 212 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 | ||
| 213 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 | ||
| 214 | #define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 | ||
| 215 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 | ||
| 216 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 | ||
| 217 | #define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 | ||
| 218 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 | ||
| 219 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 | ||
| 220 | #define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 | ||
| 221 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 | ||
| 222 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 | ||
| 223 | #define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 | ||
| 224 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 | ||
| 225 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 | ||
| 226 | #define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 | ||
| 227 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 | ||
| 228 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 | ||
| 229 | #define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 | ||
| 230 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 | ||
| 231 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 | ||
| 232 | #define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 | ||
| 233 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 | ||
| 234 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 | ||
| 235 | #define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 | ||
| 236 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 | ||
| 237 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 | ||
| 238 | #define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 | ||
| 239 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 | ||
| 240 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 | ||
| 241 | #define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 | ||
| 242 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 | ||
| 243 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 | ||
| 244 | #define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 | ||
| 245 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 | ||
| 246 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 | ||
| 247 | #define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 | ||
| 248 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 | ||
| 249 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 | ||
| 250 | #define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 | ||
| 251 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 | ||
| 252 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 | ||
| 253 | #define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 | ||
| 254 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 | ||
| 255 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 | ||
| 256 | #define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 | ||
| 257 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 | ||
| 258 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 | ||
| 259 | #define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 | ||
| 260 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 | ||
| 261 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 | ||
| 262 | #define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 | ||
| 263 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 | ||
| 264 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 | ||
| 265 | #define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 | ||
| 266 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 | ||
| 267 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 | ||
| 268 | #define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 | ||
| 269 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 | ||
| 270 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 | ||
| 271 | #define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 | ||
| 272 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 | ||
| 273 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 | ||
| 274 | #define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 | ||
| 275 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 | ||
| 276 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 | ||
| 277 | #define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 | ||
| 278 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 | ||
| 279 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 | ||
| 280 | #define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 | ||
| 281 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 | ||
| 282 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 | ||
| 283 | #define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 | ||
| 284 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 | ||
| 285 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 | ||
| 286 | #define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 | ||
| 287 | #define reg_iop_sw_mpu_rw_cpu_intr_offset 76 | ||
| 288 | |||
| 289 | /* Register r_cpu_intr, scope iop_sw_mpu, type r */ | ||
| 290 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 | ||
| 291 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 | ||
| 292 | #define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 | ||
| 293 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 | ||
| 294 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 | ||
| 295 | #define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 | ||
| 296 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 | ||
| 297 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 | ||
| 298 | #define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 | ||
| 299 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 | ||
| 300 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 | ||
| 301 | #define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 | ||
| 302 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 | ||
| 303 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 | ||
| 304 | #define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 | ||
| 305 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 | ||
| 306 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 | ||
| 307 | #define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 | ||
| 308 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 | ||
| 309 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 | ||
| 310 | #define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 | ||
| 311 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 | ||
| 312 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 | ||
| 313 | #define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 | ||
| 314 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 | ||
| 315 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 | ||
| 316 | #define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 | ||
| 317 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 | ||
| 318 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 | ||
| 319 | #define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 | ||
| 320 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 | ||
| 321 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 | ||
| 322 | #define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 | ||
| 323 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 | ||
| 324 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 | ||
| 325 | #define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 | ||
| 326 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 | ||
| 327 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 | ||
| 328 | #define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 | ||
| 329 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 | ||
| 330 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 | ||
| 331 | #define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 | ||
| 332 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 | ||
| 333 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 | ||
| 334 | #define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 | ||
| 335 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 | ||
| 336 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 | ||
| 337 | #define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 | ||
| 338 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 | ||
| 339 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 | ||
| 340 | #define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 | ||
| 341 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 | ||
| 342 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 | ||
| 343 | #define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 | ||
| 344 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 | ||
| 345 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 | ||
| 346 | #define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 | ||
| 347 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 | ||
| 348 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 | ||
| 349 | #define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 | ||
| 350 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 | ||
| 351 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 | ||
| 352 | #define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 | ||
| 353 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 | ||
| 354 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 | ||
| 355 | #define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 | ||
| 356 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 | ||
| 357 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 | ||
| 358 | #define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 | ||
| 359 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 | ||
| 360 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 | ||
| 361 | #define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 | ||
| 362 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 | ||
| 363 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 | ||
| 364 | #define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 | ||
| 365 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 | ||
| 366 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 | ||
| 367 | #define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 | ||
| 368 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 | ||
| 369 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 | ||
| 370 | #define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 | ||
| 371 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 | ||
| 372 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 | ||
| 373 | #define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 | ||
| 374 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 | ||
| 375 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 | ||
| 376 | #define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 | ||
| 377 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 | ||
| 378 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 | ||
| 379 | #define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 | ||
| 380 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 | ||
| 381 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 | ||
| 382 | #define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 | ||
| 383 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 | ||
| 384 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 | ||
| 385 | #define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 | ||
| 386 | #define reg_iop_sw_mpu_r_cpu_intr_offset 80 | ||
| 387 | |||
| 388 | /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ | ||
| 389 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 | ||
| 390 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 | ||
| 391 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 | ||
| 392 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 | ||
| 393 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 | ||
| 394 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 | ||
| 395 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 | ||
| 396 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 | ||
| 397 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 | ||
| 398 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 | ||
| 399 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 | ||
| 400 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 | ||
| 401 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 | ||
| 402 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 | ||
| 403 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 | ||
| 404 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 | ||
| 405 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 | ||
| 406 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 | ||
| 407 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 | ||
| 408 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 | ||
| 409 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 | ||
| 410 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 | ||
| 411 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 | ||
| 412 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 | ||
| 413 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 | ||
| 414 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 | ||
| 415 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 | ||
| 416 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 | ||
| 417 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 | ||
| 418 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 | ||
| 419 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 | ||
| 420 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 | ||
| 421 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 | ||
| 422 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 | ||
| 423 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 | ||
| 424 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 | ||
| 425 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 | ||
| 426 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 | ||
| 427 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 | ||
| 428 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 | ||
| 429 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 | ||
| 430 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 | ||
| 431 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 | ||
| 432 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 | ||
| 433 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 | ||
| 434 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 | ||
| 435 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 | ||
| 436 | #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 | ||
| 437 | #define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 | ||
| 438 | |||
| 439 | /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ | ||
| 440 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 | ||
| 441 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 | ||
| 442 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 | ||
| 443 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 | ||
| 444 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 | ||
| 445 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 | ||
| 446 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 | ||
| 447 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 | ||
| 448 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 | ||
| 449 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 | ||
| 450 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 | ||
| 451 | #define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 | ||
| 452 | #define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 | ||
| 453 | |||
| 454 | /* Register r_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 455 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 | ||
| 456 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 | ||
| 457 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 | ||
| 458 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 | ||
| 459 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 | ||
| 460 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 | ||
| 461 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 | ||
| 462 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 | ||
| 463 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 | ||
| 464 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 | ||
| 465 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 | ||
| 466 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 | ||
| 467 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 | ||
| 468 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 | ||
| 469 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 | ||
| 470 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 | ||
| 471 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 | ||
| 472 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 | ||
| 473 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 | ||
| 474 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 | ||
| 475 | #define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 | ||
| 476 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 | ||
| 477 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 | ||
| 478 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 | ||
| 479 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 | ||
| 480 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 | ||
| 481 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 | ||
| 482 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 | ||
| 483 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 | ||
| 484 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 | ||
| 485 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 | ||
| 486 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 | ||
| 487 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 | ||
| 488 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 | ||
| 489 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 | ||
| 490 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 | ||
| 491 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 | ||
| 492 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 | ||
| 493 | #define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 | ||
| 494 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 | ||
| 495 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 | ||
| 496 | #define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 | ||
| 497 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 | ||
| 498 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 | ||
| 499 | #define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 | ||
| 500 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 | ||
| 501 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 | ||
| 502 | #define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 | ||
| 503 | #define reg_iop_sw_mpu_r_intr_grp0_offset 92 | ||
| 504 | |||
| 505 | /* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 506 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 | ||
| 507 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 | ||
| 508 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 | ||
| 509 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 | ||
| 510 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 | ||
| 511 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 | ||
| 512 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 | ||
| 513 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 | ||
| 514 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 | ||
| 515 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 | ||
| 516 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 | ||
| 517 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 | ||
| 518 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 | ||
| 519 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 | ||
| 520 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 | ||
| 521 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 | ||
| 522 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 | ||
| 523 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 | ||
| 524 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 | ||
| 525 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 | ||
| 526 | #define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 | ||
| 527 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 | ||
| 528 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 | ||
| 529 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 | ||
| 530 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 | ||
| 531 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 | ||
| 532 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 | ||
| 533 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 | ||
| 534 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 | ||
| 535 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 | ||
| 536 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 | ||
| 537 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 | ||
| 538 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 | ||
| 539 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 | ||
| 540 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 | ||
| 541 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 | ||
| 542 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 | ||
| 543 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 | ||
| 544 | #define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 | ||
| 545 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 | ||
| 546 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 | ||
| 547 | #define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 | ||
| 548 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 | ||
| 549 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 | ||
| 550 | #define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 | ||
| 551 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 | ||
| 552 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 | ||
| 553 | #define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 | ||
| 554 | #define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 | ||
| 555 | |||
| 556 | /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ | ||
| 557 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 | ||
| 558 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 | ||
| 559 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 | ||
| 560 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 | ||
| 561 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 | ||
| 562 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 | ||
| 563 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 | ||
| 564 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 | ||
| 565 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 | ||
| 566 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 | ||
| 567 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 | ||
| 568 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 | ||
| 569 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 | ||
| 570 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 | ||
| 571 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 | ||
| 572 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 | ||
| 573 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 | ||
| 574 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 | ||
| 575 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 | ||
| 576 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 | ||
| 577 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 | ||
| 578 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 | ||
| 579 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 | ||
| 580 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 | ||
| 581 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 | ||
| 582 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 | ||
| 583 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 | ||
| 584 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 | ||
| 585 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 | ||
| 586 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 | ||
| 587 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 | ||
| 588 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 | ||
| 589 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 | ||
| 590 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 | ||
| 591 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 | ||
| 592 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 | ||
| 593 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 | ||
| 594 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 | ||
| 595 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 | ||
| 596 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 | ||
| 597 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 | ||
| 598 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 | ||
| 599 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 | ||
| 600 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 | ||
| 601 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 | ||
| 602 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 | ||
| 603 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 | ||
| 604 | #define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 | ||
| 605 | #define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 | ||
| 606 | |||
| 607 | /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ | ||
| 608 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 | ||
| 609 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 | ||
| 610 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 | ||
| 611 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 | ||
| 612 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 | ||
| 613 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 | ||
| 614 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 | ||
| 615 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 | ||
| 616 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 | ||
| 617 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 | ||
| 618 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 | ||
| 619 | #define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 | ||
| 620 | #define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 | ||
| 621 | |||
| 622 | /* Register r_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 623 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 | ||
| 624 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 | ||
| 625 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 | ||
| 626 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 | ||
| 627 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 | ||
| 628 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 | ||
| 629 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 | ||
| 630 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 | ||
| 631 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 | ||
| 632 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 | ||
| 633 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 | ||
| 634 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 | ||
| 635 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 | ||
| 636 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 | ||
| 637 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 | ||
| 638 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 | ||
| 639 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 | ||
| 640 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 | ||
| 641 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 | ||
| 642 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 | ||
| 643 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 | ||
| 644 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 | ||
| 645 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 | ||
| 646 | #define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 | ||
| 647 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 | ||
| 648 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 | ||
| 649 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 | ||
| 650 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 | ||
| 651 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 | ||
| 652 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 | ||
| 653 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 | ||
| 654 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 | ||
| 655 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 | ||
| 656 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 | ||
| 657 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 | ||
| 658 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 | ||
| 659 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 | ||
| 660 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 | ||
| 661 | #define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 | ||
| 662 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 | ||
| 663 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 | ||
| 664 | #define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 | ||
| 665 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 | ||
| 666 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 | ||
| 667 | #define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 | ||
| 668 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 | ||
| 669 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 | ||
| 670 | #define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 | ||
| 671 | #define reg_iop_sw_mpu_r_intr_grp1_offset 108 | ||
| 672 | |||
| 673 | /* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 674 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 | ||
| 675 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 | ||
| 676 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 | ||
| 677 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 | ||
| 678 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 | ||
| 679 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 | ||
| 680 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 | ||
| 681 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 | ||
| 682 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 | ||
| 683 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 | ||
| 684 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 | ||
| 685 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 | ||
| 686 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 | ||
| 687 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 | ||
| 688 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 | ||
| 689 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 | ||
| 690 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 | ||
| 691 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 | ||
| 692 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 | ||
| 693 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 | ||
| 694 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 | ||
| 695 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 | ||
| 696 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 | ||
| 697 | #define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 | ||
| 698 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 | ||
| 699 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 | ||
| 700 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 | ||
| 701 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 | ||
| 702 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 | ||
| 703 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 | ||
| 704 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 | ||
| 705 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 | ||
| 706 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 | ||
| 707 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 | ||
| 708 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 | ||
| 709 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 | ||
| 710 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 | ||
| 711 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 | ||
| 712 | #define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 | ||
| 713 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 | ||
| 714 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 | ||
| 715 | #define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 | ||
| 716 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 | ||
| 717 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 | ||
| 718 | #define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 | ||
| 719 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 | ||
| 720 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 | ||
| 721 | #define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 | ||
| 722 | #define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 | ||
| 723 | |||
| 724 | /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ | ||
| 725 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 | ||
| 726 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 | ||
| 727 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 | ||
| 728 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 | ||
| 729 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 | ||
| 730 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 | ||
| 731 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 | ||
| 732 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 | ||
| 733 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 | ||
| 734 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 | ||
| 735 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 | ||
| 736 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 | ||
| 737 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 | ||
| 738 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 | ||
| 739 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 | ||
| 740 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 | ||
| 741 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 | ||
| 742 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 | ||
| 743 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 | ||
| 744 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 | ||
| 745 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 | ||
| 746 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 | ||
| 747 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 | ||
| 748 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 | ||
| 749 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 | ||
| 750 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 | ||
| 751 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 | ||
| 752 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 | ||
| 753 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 | ||
| 754 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 | ||
| 755 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 | ||
| 756 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 | ||
| 757 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 | ||
| 758 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 | ||
| 759 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 | ||
| 760 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 | ||
| 761 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 | ||
| 762 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 | ||
| 763 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 | ||
| 764 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 | ||
| 765 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 | ||
| 766 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 | ||
| 767 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 | ||
| 768 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 | ||
| 769 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 | ||
| 770 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 | ||
| 771 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 | ||
| 772 | #define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 | ||
| 773 | #define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 | ||
| 774 | |||
| 775 | /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ | ||
| 776 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 | ||
| 777 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 | ||
| 778 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 | ||
| 779 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 | ||
| 780 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 | ||
| 781 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 | ||
| 782 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 | ||
| 783 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 | ||
| 784 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 | ||
| 785 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 | ||
| 786 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 | ||
| 787 | #define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 | ||
| 788 | #define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 | ||
| 789 | |||
| 790 | /* Register r_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 791 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 | ||
| 792 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 | ||
| 793 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 | ||
| 794 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 | ||
| 795 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 | ||
| 796 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 | ||
| 797 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 | ||
| 798 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 | ||
| 799 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 | ||
| 800 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 | ||
| 801 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 | ||
| 802 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 | ||
| 803 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 | ||
| 804 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 | ||
| 805 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 | ||
| 806 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 | ||
| 807 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 | ||
| 808 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 | ||
| 809 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 | ||
| 810 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 | ||
| 811 | #define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 | ||
| 812 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 | ||
| 813 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 | ||
| 814 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 | ||
| 815 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 | ||
| 816 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 | ||
| 817 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 | ||
| 818 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 | ||
| 819 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 | ||
| 820 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 | ||
| 821 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 | ||
| 822 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 | ||
| 823 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 | ||
| 824 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 | ||
| 825 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 | ||
| 826 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 | ||
| 827 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 | ||
| 828 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 | ||
| 829 | #define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 | ||
| 830 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 | ||
| 831 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 | ||
| 832 | #define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 | ||
| 833 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 | ||
| 834 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 | ||
| 835 | #define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 | ||
| 836 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 | ||
| 837 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 | ||
| 838 | #define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 | ||
| 839 | #define reg_iop_sw_mpu_r_intr_grp2_offset 124 | ||
| 840 | |||
| 841 | /* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 842 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 | ||
| 843 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 | ||
| 844 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 | ||
| 845 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 | ||
| 846 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 | ||
| 847 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 | ||
| 848 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 | ||
| 849 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 | ||
| 850 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 | ||
| 851 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 | ||
| 852 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 | ||
| 853 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 | ||
| 854 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 | ||
| 855 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 | ||
| 856 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 | ||
| 857 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 | ||
| 858 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 | ||
| 859 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 | ||
| 860 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 | ||
| 861 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 | ||
| 862 | #define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 | ||
| 863 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 | ||
| 864 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 | ||
| 865 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 | ||
| 866 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 | ||
| 867 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 | ||
| 868 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 | ||
| 869 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 | ||
| 870 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 | ||
| 871 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 | ||
| 872 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 | ||
| 873 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 | ||
| 874 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 | ||
| 875 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 | ||
| 876 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 | ||
| 877 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 | ||
| 878 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 | ||
| 879 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 | ||
| 880 | #define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 | ||
| 881 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 | ||
| 882 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 | ||
| 883 | #define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 | ||
| 884 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 | ||
| 885 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 | ||
| 886 | #define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 | ||
| 887 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 | ||
| 888 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 | ||
| 889 | #define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 | ||
| 890 | #define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 | ||
| 891 | |||
| 892 | /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ | ||
| 893 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 | ||
| 894 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 | ||
| 895 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 | ||
| 896 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 | ||
| 897 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 | ||
| 898 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 | ||
| 899 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 | ||
| 900 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 | ||
| 901 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 | ||
| 902 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 | ||
| 903 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 | ||
| 904 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 | ||
| 905 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 | ||
| 906 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 | ||
| 907 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 | ||
| 908 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 | ||
| 909 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 | ||
| 910 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 | ||
| 911 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 | ||
| 912 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 | ||
| 913 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 | ||
| 914 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 | ||
| 915 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 | ||
| 916 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 | ||
| 917 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 | ||
| 918 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 | ||
| 919 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 | ||
| 920 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 | ||
| 921 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 | ||
| 922 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 | ||
| 923 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 | ||
| 924 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 | ||
| 925 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 | ||
| 926 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 | ||
| 927 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 | ||
| 928 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 | ||
| 929 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 | ||
| 930 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 | ||
| 931 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 | ||
| 932 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 | ||
| 933 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 | ||
| 934 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 | ||
| 935 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 | ||
| 936 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 | ||
| 937 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 | ||
| 938 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 | ||
| 939 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 | ||
| 940 | #define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 | ||
| 941 | #define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 | ||
| 942 | |||
| 943 | /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ | ||
| 944 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 | ||
| 945 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 | ||
| 946 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 | ||
| 947 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 | ||
| 948 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 | ||
| 949 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 | ||
| 950 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 | ||
| 951 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 | ||
| 952 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 | ||
| 953 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 | ||
| 954 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 | ||
| 955 | #define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 | ||
| 956 | #define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 | ||
| 957 | |||
| 958 | /* Register r_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 959 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 | ||
| 960 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 | ||
| 961 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 | ||
| 962 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 | ||
| 963 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 | ||
| 964 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 | ||
| 965 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 | ||
| 966 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 | ||
| 967 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 | ||
| 968 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 | ||
| 969 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 | ||
| 970 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 | ||
| 971 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 | ||
| 972 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 | ||
| 973 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 | ||
| 974 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 | ||
| 975 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 | ||
| 976 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 | ||
| 977 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 | ||
| 978 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 | ||
| 979 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 | ||
| 980 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 | ||
| 981 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 | ||
| 982 | #define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 | ||
| 983 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 | ||
| 984 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 | ||
| 985 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 | ||
| 986 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 | ||
| 987 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 | ||
| 988 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 | ||
| 989 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 | ||
| 990 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 | ||
| 991 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 | ||
| 992 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 | ||
| 993 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 | ||
| 994 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 | ||
| 995 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 | ||
| 996 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 | ||
| 997 | #define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 | ||
| 998 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 | ||
| 999 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 | ||
| 1000 | #define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 | ||
| 1001 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 | ||
| 1002 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 | ||
| 1003 | #define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 | ||
| 1004 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 | ||
| 1005 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 | ||
| 1006 | #define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 | ||
| 1007 | #define reg_iop_sw_mpu_r_intr_grp3_offset 140 | ||
| 1008 | |||
| 1009 | /* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 1010 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 | ||
| 1011 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 | ||
| 1012 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 | ||
| 1013 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 | ||
| 1014 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 | ||
| 1015 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 | ||
| 1016 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 | ||
| 1017 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 | ||
| 1018 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 | ||
| 1019 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 | ||
| 1020 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 | ||
| 1021 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 | ||
| 1022 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 | ||
| 1023 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 | ||
| 1024 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 | ||
| 1025 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 | ||
| 1026 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 | ||
| 1027 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 | ||
| 1028 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 | ||
| 1029 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 | ||
| 1030 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 | ||
| 1031 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 | ||
| 1032 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 | ||
| 1033 | #define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 | ||
| 1034 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 | ||
| 1035 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 | ||
| 1036 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 | ||
| 1037 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 | ||
| 1038 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 | ||
| 1039 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 | ||
| 1040 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 | ||
| 1041 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 | ||
| 1042 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 | ||
| 1043 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 | ||
| 1044 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 | ||
| 1045 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 | ||
| 1046 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 | ||
| 1047 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 | ||
| 1048 | #define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 | ||
| 1049 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 | ||
| 1050 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 | ||
| 1051 | #define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 | ||
| 1052 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 | ||
| 1053 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 | ||
| 1054 | #define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 | ||
| 1055 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 | ||
| 1056 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 | ||
| 1057 | #define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 | ||
| 1058 | #define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 | ||
| 1059 | |||
| 1060 | |||
| 1061 | /* Constants */ | ||
| 1062 | #define regk_iop_sw_mpu_copy 0x00000000 | ||
| 1063 | #define regk_iop_sw_mpu_cpu 0x00000000 | ||
| 1064 | #define regk_iop_sw_mpu_mpu 0x00000001 | ||
| 1065 | #define regk_iop_sw_mpu_no 0x00000000 | ||
| 1066 | #define regk_iop_sw_mpu_nop 0x00000000 | ||
| 1067 | #define regk_iop_sw_mpu_rd 0x00000002 | ||
| 1068 | #define regk_iop_sw_mpu_reg_copy 0x00000001 | ||
| 1069 | #define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 | ||
| 1070 | #define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 | ||
| 1071 | #define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 | ||
| 1072 | #define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 | ||
| 1073 | #define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 | ||
| 1074 | #define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 | ||
| 1075 | #define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 | ||
| 1076 | #define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 | ||
| 1077 | #define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 | ||
| 1078 | #define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 | ||
| 1079 | #define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 | ||
| 1080 | #define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 | ||
| 1081 | #define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 | ||
| 1082 | #define regk_iop_sw_mpu_set 0x00000001 | ||
| 1083 | #define regk_iop_sw_mpu_spu 0x00000002 | ||
| 1084 | #define regk_iop_sw_mpu_wr 0x00000003 | ||
| 1085 | #define regk_iop_sw_mpu_yes 0x00000001 | ||
| 1086 | #endif /* __iop_sw_mpu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h new file mode 100644 index 000000000000..67a745338087 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sw_spu_defs_asm.h | |||
| @@ -0,0 +1,523 @@ | |||
| 1 | #ifndef __iop_sw_spu_defs_asm_h | ||
| 2 | #define __iop_sw_spu_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_spu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register r_mpu_trace, scope iop_sw_spu, type r */ | ||
| 54 | #define reg_iop_sw_spu_r_mpu_trace_offset 0 | ||
| 55 | |||
| 56 | /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ | ||
| 57 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 | ||
| 58 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 | ||
| 59 | #define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 | ||
| 60 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 | ||
| 61 | #define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 | ||
| 62 | #define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 | ||
| 63 | #define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 | ||
| 64 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 | ||
| 65 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 | ||
| 66 | #define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 | ||
| 67 | #define reg_iop_sw_spu_rw_mc_ctrl_offset 4 | ||
| 68 | |||
| 69 | /* Register rw_mc_data, scope iop_sw_spu, type rw */ | ||
| 70 | #define reg_iop_sw_spu_rw_mc_data___val___lsb 0 | ||
| 71 | #define reg_iop_sw_spu_rw_mc_data___val___width 32 | ||
| 72 | #define reg_iop_sw_spu_rw_mc_data_offset 8 | ||
| 73 | |||
| 74 | /* Register rw_mc_addr, scope iop_sw_spu, type rw */ | ||
| 75 | #define reg_iop_sw_spu_rw_mc_addr_offset 12 | ||
| 76 | |||
| 77 | /* Register rs_mc_data, scope iop_sw_spu, type rs */ | ||
| 78 | #define reg_iop_sw_spu_rs_mc_data_offset 16 | ||
| 79 | |||
| 80 | /* Register r_mc_data, scope iop_sw_spu, type r */ | ||
| 81 | #define reg_iop_sw_spu_r_mc_data_offset 20 | ||
| 82 | |||
| 83 | /* Register r_mc_stat, scope iop_sw_spu, type r */ | ||
| 84 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 | ||
| 85 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 | ||
| 86 | #define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 | ||
| 87 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 | ||
| 88 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 | ||
| 89 | #define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 | ||
| 90 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 | ||
| 91 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 | ||
| 92 | #define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 | ||
| 93 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 | ||
| 94 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 | ||
| 95 | #define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 | ||
| 96 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 | ||
| 97 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 | ||
| 98 | #define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 | ||
| 99 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 | ||
| 100 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 | ||
| 101 | #define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 | ||
| 102 | #define reg_iop_sw_spu_r_mc_stat_offset 24 | ||
| 103 | |||
| 104 | /* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ | ||
| 105 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 | ||
| 106 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 | ||
| 107 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 | ||
| 108 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 | ||
| 109 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 | ||
| 110 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 | ||
| 111 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 | ||
| 112 | #define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 | ||
| 113 | #define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 | ||
| 114 | |||
| 115 | /* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ | ||
| 116 | #define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 | ||
| 117 | #define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 | ||
| 118 | #define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 | ||
| 119 | #define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 | ||
| 120 | #define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 | ||
| 121 | #define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 | ||
| 122 | #define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 | ||
| 123 | #define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 | ||
| 124 | #define reg_iop_sw_spu_rw_bus_set_mask_offset 32 | ||
| 125 | |||
| 126 | /* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 127 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 | ||
| 128 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 | ||
| 129 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 | ||
| 130 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 | ||
| 131 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 | ||
| 132 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 | ||
| 133 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 | ||
| 134 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 | ||
| 135 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 | ||
| 136 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 | ||
| 137 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 | ||
| 138 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 | ||
| 139 | #define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 | ||
| 140 | |||
| 141 | /* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 142 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 | ||
| 143 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 | ||
| 144 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 | ||
| 145 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 | ||
| 146 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 | ||
| 147 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 | ||
| 148 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 | ||
| 149 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 | ||
| 150 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 | ||
| 151 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 | ||
| 152 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 | ||
| 153 | #define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 | ||
| 154 | #define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 | ||
| 155 | |||
| 156 | /* Register r_bus_in, scope iop_sw_spu, type r */ | ||
| 157 | #define reg_iop_sw_spu_r_bus_in_offset 44 | ||
| 158 | |||
| 159 | /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ | ||
| 160 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 | ||
| 161 | #define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 | ||
| 162 | #define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 | ||
| 163 | |||
| 164 | /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ | ||
| 165 | #define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 | ||
| 166 | #define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 | ||
| 167 | #define reg_iop_sw_spu_rw_gio_set_mask_offset 52 | ||
| 168 | |||
| 169 | /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 170 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 | ||
| 171 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 | ||
| 172 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 | ||
| 173 | |||
| 174 | /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 175 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 | ||
| 176 | #define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 | ||
| 177 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 | ||
| 178 | |||
| 179 | /* Register r_gio_in, scope iop_sw_spu, type r */ | ||
| 180 | #define reg_iop_sw_spu_r_gio_in_offset 64 | ||
| 181 | |||
| 182 | /* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 183 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 | ||
| 184 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 | ||
| 185 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 | ||
| 186 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 | ||
| 187 | #define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 | ||
| 188 | |||
| 189 | /* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 190 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 | ||
| 191 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 | ||
| 192 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 | ||
| 193 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 | ||
| 194 | #define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 | ||
| 195 | |||
| 196 | /* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 197 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 | ||
| 198 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 | ||
| 199 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 | ||
| 200 | #define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 | ||
| 201 | #define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 | ||
| 202 | |||
| 203 | /* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 204 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 | ||
| 205 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 | ||
| 206 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 | ||
| 207 | #define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 | ||
| 208 | #define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 | ||
| 209 | |||
| 210 | /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 211 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 | ||
| 212 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 | ||
| 213 | #define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 | ||
| 214 | |||
| 215 | /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 216 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 | ||
| 217 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 | ||
| 218 | #define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 | ||
| 219 | |||
| 220 | /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 221 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 | ||
| 222 | #define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 | ||
| 223 | #define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 | ||
| 224 | |||
| 225 | /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 226 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 | ||
| 227 | #define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 | ||
| 228 | #define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 | ||
| 229 | |||
| 230 | /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 231 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 | ||
| 232 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 | ||
| 233 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 | ||
| 234 | |||
| 235 | /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 236 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 | ||
| 237 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 | ||
| 238 | #define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 | ||
| 239 | |||
| 240 | /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 241 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 | ||
| 242 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 | ||
| 243 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 | ||
| 244 | |||
| 245 | /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 246 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 | ||
| 247 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 | ||
| 248 | #define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 | ||
| 249 | |||
| 250 | /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ | ||
| 251 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 | ||
| 252 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 | ||
| 253 | #define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 | ||
| 254 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 | ||
| 255 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 | ||
| 256 | #define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 | ||
| 257 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 | ||
| 258 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 | ||
| 259 | #define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 | ||
| 260 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 | ||
| 261 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 | ||
| 262 | #define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 | ||
| 263 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 | ||
| 264 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 | ||
| 265 | #define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 | ||
| 266 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 | ||
| 267 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 | ||
| 268 | #define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 | ||
| 269 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 | ||
| 270 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 | ||
| 271 | #define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 | ||
| 272 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 | ||
| 273 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 | ||
| 274 | #define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 | ||
| 275 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 | ||
| 276 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 | ||
| 277 | #define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 | ||
| 278 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 | ||
| 279 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 | ||
| 280 | #define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 | ||
| 281 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 | ||
| 282 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 | ||
| 283 | #define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 | ||
| 284 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 | ||
| 285 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 | ||
| 286 | #define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 | ||
| 287 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 | ||
| 288 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 | ||
| 289 | #define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 | ||
| 290 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 | ||
| 291 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 | ||
| 292 | #define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 | ||
| 293 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 | ||
| 294 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 | ||
| 295 | #define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 | ||
| 296 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 | ||
| 297 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 | ||
| 298 | #define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 | ||
| 299 | #define reg_iop_sw_spu_rw_cpu_intr_offset 116 | ||
| 300 | |||
| 301 | /* Register r_cpu_intr, scope iop_sw_spu, type r */ | ||
| 302 | #define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 | ||
| 303 | #define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 | ||
| 304 | #define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 | ||
| 305 | #define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 | ||
| 306 | #define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 | ||
| 307 | #define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 | ||
| 308 | #define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 | ||
| 309 | #define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 | ||
| 310 | #define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 | ||
| 311 | #define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 | ||
| 312 | #define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 | ||
| 313 | #define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 | ||
| 314 | #define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 | ||
| 315 | #define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 | ||
| 316 | #define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 | ||
| 317 | #define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 | ||
| 318 | #define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 | ||
| 319 | #define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 | ||
| 320 | #define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 | ||
| 321 | #define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 | ||
| 322 | #define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 | ||
| 323 | #define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 | ||
| 324 | #define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 | ||
| 325 | #define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 | ||
| 326 | #define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 | ||
| 327 | #define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 | ||
| 328 | #define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 | ||
| 329 | #define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 | ||
| 330 | #define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 | ||
| 331 | #define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 | ||
| 332 | #define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 | ||
| 333 | #define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 | ||
| 334 | #define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 | ||
| 335 | #define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 | ||
| 336 | #define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 | ||
| 337 | #define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 | ||
| 338 | #define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 | ||
| 339 | #define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 | ||
| 340 | #define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 | ||
| 341 | #define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 | ||
| 342 | #define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 | ||
| 343 | #define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 | ||
| 344 | #define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 | ||
| 345 | #define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 | ||
| 346 | #define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 | ||
| 347 | #define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 | ||
| 348 | #define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 | ||
| 349 | #define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 | ||
| 350 | #define reg_iop_sw_spu_r_cpu_intr_offset 120 | ||
| 351 | |||
| 352 | /* Register r_hw_intr, scope iop_sw_spu, type r */ | ||
| 353 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 | ||
| 354 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 | ||
| 355 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 | ||
| 356 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 | ||
| 357 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 | ||
| 358 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 | ||
| 359 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 | ||
| 360 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 | ||
| 361 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 | ||
| 362 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 | ||
| 363 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 | ||
| 364 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 | ||
| 365 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 | ||
| 366 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 | ||
| 367 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 | ||
| 368 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 | ||
| 369 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 | ||
| 370 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 | ||
| 371 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 | ||
| 372 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 | ||
| 373 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 | ||
| 374 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 | ||
| 375 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 | ||
| 376 | #define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 | ||
| 377 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 | ||
| 378 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 | ||
| 379 | #define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 | ||
| 380 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 | ||
| 381 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 | ||
| 382 | #define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 | ||
| 383 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 | ||
| 384 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 | ||
| 385 | #define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 | ||
| 386 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 | ||
| 387 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 | ||
| 388 | #define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 | ||
| 389 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 | ||
| 390 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 | ||
| 391 | #define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 | ||
| 392 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 | ||
| 393 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 | ||
| 394 | #define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 | ||
| 395 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 | ||
| 396 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 | ||
| 397 | #define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 | ||
| 398 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 | ||
| 399 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 | ||
| 400 | #define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 | ||
| 401 | #define reg_iop_sw_spu_r_hw_intr_offset 124 | ||
| 402 | |||
| 403 | /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ | ||
| 404 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 | ||
| 405 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 | ||
| 406 | #define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 | ||
| 407 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 | ||
| 408 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 | ||
| 409 | #define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 | ||
| 410 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 | ||
| 411 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 | ||
| 412 | #define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 | ||
| 413 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 | ||
| 414 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 | ||
| 415 | #define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 | ||
| 416 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 | ||
| 417 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 | ||
| 418 | #define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 | ||
| 419 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 | ||
| 420 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 | ||
| 421 | #define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 | ||
| 422 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 | ||
| 423 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 | ||
| 424 | #define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 | ||
| 425 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 | ||
| 426 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 | ||
| 427 | #define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 | ||
| 428 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 | ||
| 429 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 | ||
| 430 | #define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 | ||
| 431 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 | ||
| 432 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 | ||
| 433 | #define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 | ||
| 434 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 | ||
| 435 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 | ||
| 436 | #define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 | ||
| 437 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 | ||
| 438 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 | ||
| 439 | #define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 | ||
| 440 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 | ||
| 441 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 | ||
| 442 | #define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 | ||
| 443 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 | ||
| 444 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 | ||
| 445 | #define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 | ||
| 446 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 | ||
| 447 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 | ||
| 448 | #define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 | ||
| 449 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 | ||
| 450 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 | ||
| 451 | #define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 | ||
| 452 | #define reg_iop_sw_spu_rw_mpu_intr_offset 128 | ||
| 453 | |||
| 454 | /* Register r_mpu_intr, scope iop_sw_spu, type r */ | ||
| 455 | #define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 | ||
| 456 | #define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 | ||
| 457 | #define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 | ||
| 458 | #define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 | ||
| 459 | #define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 | ||
| 460 | #define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 | ||
| 461 | #define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 | ||
| 462 | #define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 | ||
| 463 | #define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 | ||
| 464 | #define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 | ||
| 465 | #define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 | ||
| 466 | #define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 | ||
| 467 | #define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 | ||
| 468 | #define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 | ||
| 469 | #define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 | ||
| 470 | #define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 | ||
| 471 | #define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 | ||
| 472 | #define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 | ||
| 473 | #define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 | ||
| 474 | #define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 | ||
| 475 | #define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 | ||
| 476 | #define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 | ||
| 477 | #define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 | ||
| 478 | #define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 | ||
| 479 | #define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 | ||
| 480 | #define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 | ||
| 481 | #define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 | ||
| 482 | #define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 | ||
| 483 | #define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 | ||
| 484 | #define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 | ||
| 485 | #define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 | ||
| 486 | #define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 | ||
| 487 | #define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 | ||
| 488 | #define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 | ||
| 489 | #define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 | ||
| 490 | #define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 | ||
| 491 | #define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 | ||
| 492 | #define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 | ||
| 493 | #define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 | ||
| 494 | #define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 | ||
| 495 | #define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 | ||
| 496 | #define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 | ||
| 497 | #define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 | ||
| 498 | #define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 | ||
| 499 | #define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 | ||
| 500 | #define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 | ||
| 501 | #define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 | ||
| 502 | #define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 | ||
| 503 | #define reg_iop_sw_spu_r_mpu_intr_offset 132 | ||
| 504 | |||
| 505 | |||
| 506 | /* Constants */ | ||
| 507 | #define regk_iop_sw_spu_copy 0x00000000 | ||
| 508 | #define regk_iop_sw_spu_no 0x00000000 | ||
| 509 | #define regk_iop_sw_spu_nop 0x00000000 | ||
| 510 | #define regk_iop_sw_spu_rd 0x00000002 | ||
| 511 | #define regk_iop_sw_spu_reg_copy 0x00000001 | ||
| 512 | #define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 | ||
| 513 | #define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 | ||
| 514 | #define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 | ||
| 515 | #define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 | ||
| 516 | #define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 | ||
| 517 | #define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 | ||
| 518 | #define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 | ||
| 519 | #define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 | ||
| 520 | #define regk_iop_sw_spu_set 0x00000001 | ||
| 521 | #define regk_iop_sw_spu_wr 0x00000003 | ||
| 522 | #define regk_iop_sw_spu_yes 0x00000001 | ||
| 523 | #endif /* __iop_sw_spu_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h new file mode 100644 index 000000000000..4ad671202af0 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_version_defs_asm.h | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | #ifndef __iop_version_defs_asm_h | ||
| 2 | #define __iop_version_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_version.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef REG_FIELD | ||
| 15 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_STATE | ||
| 21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 23 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_MASK | ||
| 27 | #define REG_MASK( scope, reg, field ) \ | ||
| 28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 30 | #endif | ||
| 31 | |||
| 32 | #ifndef REG_LSB | ||
| 33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_BIT | ||
| 37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_ADDR | ||
| 41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_ADDR_VECT | ||
| 46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 48 | STRIDE_##scope##_##reg ) | ||
| 49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 50 | ((inst) + offs + (index) * stride) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* Register r_version, scope iop_version, type r */ | ||
| 54 | #define reg_iop_version_r_version___nr___lsb 0 | ||
| 55 | #define reg_iop_version_r_version___nr___width 8 | ||
| 56 | #define reg_iop_version_r_version_offset 0 | ||
| 57 | |||
| 58 | |||
| 59 | /* Constants */ | ||
| 60 | #define regk_iop_version_v2_0 0x00000002 | ||
| 61 | #endif /* __iop_version_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h new file mode 100644 index 000000000000..af3196c60a46 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_reg_space.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* Autogenerated Changes here will be lost! | ||
| 2 | * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg | ||
| 3 | */ | ||
| 4 | #define regi_iop_version (regi_iop + 0) | ||
| 5 | #define regi_iop_fifo_in_extra (regi_iop + 64) | ||
| 6 | #define regi_iop_fifo_out_extra (regi_iop + 128) | ||
| 7 | #define regi_iop_trigger_grp0 (regi_iop + 192) | ||
| 8 | #define regi_iop_trigger_grp1 (regi_iop + 256) | ||
| 9 | #define regi_iop_trigger_grp2 (regi_iop + 320) | ||
| 10 | #define regi_iop_trigger_grp3 (regi_iop + 384) | ||
| 11 | #define regi_iop_trigger_grp4 (regi_iop + 448) | ||
| 12 | #define regi_iop_trigger_grp5 (regi_iop + 512) | ||
| 13 | #define regi_iop_trigger_grp6 (regi_iop + 576) | ||
| 14 | #define regi_iop_trigger_grp7 (regi_iop + 640) | ||
| 15 | #define regi_iop_crc_par (regi_iop + 768) | ||
| 16 | #define regi_iop_dmc_in (regi_iop + 896) | ||
| 17 | #define regi_iop_dmc_out (regi_iop + 1024) | ||
| 18 | #define regi_iop_fifo_in (regi_iop + 1152) | ||
| 19 | #define regi_iop_fifo_out (regi_iop + 1280) | ||
| 20 | #define regi_iop_scrc_in (regi_iop + 1408) | ||
| 21 | #define regi_iop_scrc_out (regi_iop + 1536) | ||
| 22 | #define regi_iop_timer_grp0 (regi_iop + 1664) | ||
| 23 | #define regi_iop_timer_grp1 (regi_iop + 1792) | ||
| 24 | #define regi_iop_sap_in (regi_iop + 2048) | ||
| 25 | #define regi_iop_sap_out (regi_iop + 2304) | ||
| 26 | #define regi_iop_spu (regi_iop + 2560) | ||
| 27 | #define regi_iop_sw_cfg (regi_iop + 2816) | ||
| 28 | #define regi_iop_sw_cpu (regi_iop + 3072) | ||
| 29 | #define regi_iop_sw_mpu (regi_iop + 3328) | ||
| 30 | #define regi_iop_sw_spu (regi_iop + 3584) | ||
| 31 | #define regi_iop_mpu (regi_iop + 4096) | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h new file mode 100644 index 000000000000..51dde016c03a --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_in_defs.h | |||
| @@ -0,0 +1,141 @@ | |||
| 1 | #ifndef __iop_sap_in_defs_h | ||
| 2 | #define __iop_sap_in_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sap_in.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sap_in */ | ||
| 83 | |||
| 84 | #define STRIDE_iop_sap_in_rw_bus_byte 4 | ||
| 85 | /* Register rw_bus_byte, scope iop_sap_in, type rw */ | ||
| 86 | typedef struct { | ||
| 87 | unsigned int sync_sel : 2; | ||
| 88 | unsigned int sync_ext_src : 3; | ||
| 89 | unsigned int sync_edge : 2; | ||
| 90 | unsigned int delay : 2; | ||
| 91 | unsigned int dummy1 : 23; | ||
| 92 | } reg_iop_sap_in_rw_bus_byte; | ||
| 93 | #define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0 | ||
| 94 | #define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0 | ||
| 95 | |||
| 96 | #define STRIDE_iop_sap_in_rw_gio 4 | ||
| 97 | /* Register rw_gio, scope iop_sap_in, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int sync_sel : 2; | ||
| 100 | unsigned int sync_ext_src : 3; | ||
| 101 | unsigned int sync_edge : 2; | ||
| 102 | unsigned int delay : 2; | ||
| 103 | unsigned int logic : 2; | ||
| 104 | unsigned int dummy1 : 21; | ||
| 105 | } reg_iop_sap_in_rw_gio; | ||
| 106 | #define REG_RD_ADDR_iop_sap_in_rw_gio 16 | ||
| 107 | #define REG_WR_ADDR_iop_sap_in_rw_gio 16 | ||
| 108 | |||
| 109 | |||
| 110 | /* Constants */ | ||
| 111 | enum { | ||
| 112 | regk_iop_sap_in_and = 0x00000002, | ||
| 113 | regk_iop_sap_in_ext_clk200 = 0x00000003, | ||
| 114 | regk_iop_sap_in_gio0 = 0x00000000, | ||
| 115 | regk_iop_sap_in_gio12 = 0x00000003, | ||
| 116 | regk_iop_sap_in_gio16 = 0x00000004, | ||
| 117 | regk_iop_sap_in_gio20 = 0x00000005, | ||
| 118 | regk_iop_sap_in_gio24 = 0x00000006, | ||
| 119 | regk_iop_sap_in_gio28 = 0x00000007, | ||
| 120 | regk_iop_sap_in_gio4 = 0x00000001, | ||
| 121 | regk_iop_sap_in_gio8 = 0x00000002, | ||
| 122 | regk_iop_sap_in_inv = 0x00000001, | ||
| 123 | regk_iop_sap_in_neg = 0x00000002, | ||
| 124 | regk_iop_sap_in_no = 0x00000000, | ||
| 125 | regk_iop_sap_in_no_del_ext_clk200 = 0x00000002, | ||
| 126 | regk_iop_sap_in_none = 0x00000000, | ||
| 127 | regk_iop_sap_in_one = 0x00000001, | ||
| 128 | regk_iop_sap_in_or = 0x00000003, | ||
| 129 | regk_iop_sap_in_pos = 0x00000001, | ||
| 130 | regk_iop_sap_in_pos_neg = 0x00000003, | ||
| 131 | regk_iop_sap_in_rw_bus_byte_default = 0x00000000, | ||
| 132 | regk_iop_sap_in_rw_bus_byte_size = 0x00000004, | ||
| 133 | regk_iop_sap_in_rw_gio_default = 0x00000000, | ||
| 134 | regk_iop_sap_in_rw_gio_size = 0x00000020, | ||
| 135 | regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000, | ||
| 136 | regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001, | ||
| 137 | regk_iop_sap_in_tmr_clk200 = 0x00000001, | ||
| 138 | regk_iop_sap_in_two = 0x00000002, | ||
| 139 | regk_iop_sap_in_two_clk200 = 0x00000000 | ||
| 140 | }; | ||
| 141 | #endif /* __iop_sap_in_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h new file mode 100644 index 000000000000..5af88baa2ac1 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sap_out_defs.h | |||
| @@ -0,0 +1,231 @@ | |||
| 1 | #ifndef __iop_sap_out_defs_h | ||
| 2 | #define __iop_sap_out_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sap_out.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sap_out */ | ||
| 83 | |||
| 84 | /* Register rw_gen_gated, scope iop_sap_out, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int clk0_src : 2; | ||
| 87 | unsigned int clk0_gate_src : 2; | ||
| 88 | unsigned int clk0_force_src : 3; | ||
| 89 | unsigned int clk1_src : 2; | ||
| 90 | unsigned int clk1_gate_src : 2; | ||
| 91 | unsigned int clk1_force_src : 3; | ||
| 92 | unsigned int dummy1 : 18; | ||
| 93 | } reg_iop_sap_out_rw_gen_gated; | ||
| 94 | #define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 | ||
| 95 | #define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 | ||
| 96 | |||
| 97 | /* Register rw_bus, scope iop_sap_out, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int byte0_clk_sel : 2; | ||
| 100 | unsigned int byte0_clk_ext : 2; | ||
| 101 | unsigned int byte0_gated_clk : 1; | ||
| 102 | unsigned int byte0_clk_inv : 1; | ||
| 103 | unsigned int byte0_delay : 1; | ||
| 104 | unsigned int byte1_clk_sel : 2; | ||
| 105 | unsigned int byte1_clk_ext : 2; | ||
| 106 | unsigned int byte1_gated_clk : 1; | ||
| 107 | unsigned int byte1_clk_inv : 1; | ||
| 108 | unsigned int byte1_delay : 1; | ||
| 109 | unsigned int byte2_clk_sel : 2; | ||
| 110 | unsigned int byte2_clk_ext : 2; | ||
| 111 | unsigned int byte2_gated_clk : 1; | ||
| 112 | unsigned int byte2_clk_inv : 1; | ||
| 113 | unsigned int byte2_delay : 1; | ||
| 114 | unsigned int byte3_clk_sel : 2; | ||
| 115 | unsigned int byte3_clk_ext : 2; | ||
| 116 | unsigned int byte3_gated_clk : 1; | ||
| 117 | unsigned int byte3_clk_inv : 1; | ||
| 118 | unsigned int byte3_delay : 1; | ||
| 119 | unsigned int dummy1 : 4; | ||
| 120 | } reg_iop_sap_out_rw_bus; | ||
| 121 | #define REG_RD_ADDR_iop_sap_out_rw_bus 4 | ||
| 122 | #define REG_WR_ADDR_iop_sap_out_rw_bus 4 | ||
| 123 | |||
| 124 | /* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ | ||
| 125 | typedef struct { | ||
| 126 | unsigned int byte0_clk_sel : 2; | ||
| 127 | unsigned int byte0_clk_ext : 2; | ||
| 128 | unsigned int byte0_gated_clk : 1; | ||
| 129 | unsigned int byte0_clk_inv : 1; | ||
| 130 | unsigned int byte0_delay : 1; | ||
| 131 | unsigned int byte0_logic : 2; | ||
| 132 | unsigned int byte0_logic_src : 2; | ||
| 133 | unsigned int byte1_clk_sel : 2; | ||
| 134 | unsigned int byte1_clk_ext : 2; | ||
| 135 | unsigned int byte1_gated_clk : 1; | ||
| 136 | unsigned int byte1_clk_inv : 1; | ||
| 137 | unsigned int byte1_delay : 1; | ||
| 138 | unsigned int byte1_logic : 2; | ||
| 139 | unsigned int byte1_logic_src : 2; | ||
| 140 | unsigned int dummy1 : 10; | ||
| 141 | } reg_iop_sap_out_rw_bus_lo_oe; | ||
| 142 | #define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 | ||
| 143 | #define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 | ||
| 144 | |||
| 145 | /* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ | ||
| 146 | typedef struct { | ||
| 147 | unsigned int byte2_clk_sel : 2; | ||
| 148 | unsigned int byte2_clk_ext : 2; | ||
| 149 | unsigned int byte2_gated_clk : 1; | ||
| 150 | unsigned int byte2_clk_inv : 1; | ||
| 151 | unsigned int byte2_delay : 1; | ||
| 152 | unsigned int byte2_logic : 2; | ||
| 153 | unsigned int byte2_logic_src : 2; | ||
| 154 | unsigned int byte3_clk_sel : 2; | ||
| 155 | unsigned int byte3_clk_ext : 2; | ||
| 156 | unsigned int byte3_gated_clk : 1; | ||
| 157 | unsigned int byte3_clk_inv : 1; | ||
| 158 | unsigned int byte3_delay : 1; | ||
| 159 | unsigned int byte3_logic : 2; | ||
| 160 | unsigned int byte3_logic_src : 2; | ||
| 161 | unsigned int dummy1 : 10; | ||
| 162 | } reg_iop_sap_out_rw_bus_hi_oe; | ||
| 163 | #define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 | ||
| 164 | #define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 | ||
| 165 | |||
| 166 | #define STRIDE_iop_sap_out_rw_gio 4 | ||
| 167 | /* Register rw_gio, scope iop_sap_out, type rw */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int out_clk_sel : 3; | ||
| 170 | unsigned int out_clk_ext : 2; | ||
| 171 | unsigned int out_gated_clk : 1; | ||
| 172 | unsigned int out_clk_inv : 1; | ||
| 173 | unsigned int out_delay : 1; | ||
| 174 | unsigned int out_logic : 2; | ||
| 175 | unsigned int out_logic_src : 2; | ||
| 176 | unsigned int oe_clk_sel : 3; | ||
| 177 | unsigned int oe_clk_ext : 2; | ||
| 178 | unsigned int oe_gated_clk : 1; | ||
| 179 | unsigned int oe_clk_inv : 1; | ||
| 180 | unsigned int oe_delay : 1; | ||
| 181 | unsigned int oe_logic : 2; | ||
| 182 | unsigned int oe_logic_src : 2; | ||
| 183 | unsigned int dummy1 : 8; | ||
| 184 | } reg_iop_sap_out_rw_gio; | ||
| 185 | #define REG_RD_ADDR_iop_sap_out_rw_gio 16 | ||
| 186 | #define REG_WR_ADDR_iop_sap_out_rw_gio 16 | ||
| 187 | |||
| 188 | |||
| 189 | /* Constants */ | ||
| 190 | enum { | ||
| 191 | regk_iop_sap_out_always = 0x00000001, | ||
| 192 | regk_iop_sap_out_and = 0x00000002, | ||
| 193 | regk_iop_sap_out_clk0 = 0x00000000, | ||
| 194 | regk_iop_sap_out_clk1 = 0x00000001, | ||
| 195 | regk_iop_sap_out_clk12 = 0x00000004, | ||
| 196 | regk_iop_sap_out_clk200 = 0x00000000, | ||
| 197 | regk_iop_sap_out_ext = 0x00000002, | ||
| 198 | regk_iop_sap_out_gated = 0x00000003, | ||
| 199 | regk_iop_sap_out_gio0 = 0x00000000, | ||
| 200 | regk_iop_sap_out_gio1 = 0x00000000, | ||
| 201 | regk_iop_sap_out_gio16 = 0x00000002, | ||
| 202 | regk_iop_sap_out_gio17 = 0x00000002, | ||
| 203 | regk_iop_sap_out_gio24 = 0x00000003, | ||
| 204 | regk_iop_sap_out_gio25 = 0x00000003, | ||
| 205 | regk_iop_sap_out_gio8 = 0x00000001, | ||
| 206 | regk_iop_sap_out_gio9 = 0x00000001, | ||
| 207 | regk_iop_sap_out_gio_out10 = 0x00000005, | ||
| 208 | regk_iop_sap_out_gio_out18 = 0x00000006, | ||
| 209 | regk_iop_sap_out_gio_out2 = 0x00000004, | ||
| 210 | regk_iop_sap_out_gio_out26 = 0x00000007, | ||
| 211 | regk_iop_sap_out_inv = 0x00000001, | ||
| 212 | regk_iop_sap_out_nand = 0x00000003, | ||
| 213 | regk_iop_sap_out_no = 0x00000000, | ||
| 214 | regk_iop_sap_out_none = 0x00000000, | ||
| 215 | regk_iop_sap_out_one = 0x00000001, | ||
| 216 | regk_iop_sap_out_rw_bus_default = 0x00000000, | ||
| 217 | regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, | ||
| 218 | regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, | ||
| 219 | regk_iop_sap_out_rw_gen_gated_default = 0x00000000, | ||
| 220 | regk_iop_sap_out_rw_gio_default = 0x00000000, | ||
| 221 | regk_iop_sap_out_rw_gio_size = 0x00000020, | ||
| 222 | regk_iop_sap_out_spu_gio6 = 0x00000002, | ||
| 223 | regk_iop_sap_out_spu_gio7 = 0x00000003, | ||
| 224 | regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, | ||
| 225 | regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, | ||
| 226 | regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, | ||
| 227 | regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, | ||
| 228 | regk_iop_sap_out_tmr200 = 0x00000001, | ||
| 229 | regk_iop_sap_out_yes = 0x00000001 | ||
| 230 | }; | ||
| 231 | #endif /* __iop_sap_out_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h new file mode 100644 index 000000000000..98ac95275a1c --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cfg_defs.h | |||
| @@ -0,0 +1,725 @@ | |||
| 1 | #ifndef __iop_sw_cfg_defs_h | ||
| 2 | #define __iop_sw_cfg_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_cfg.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sw_cfg */ | ||
| 83 | |||
| 84 | /* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int cfg : 2; | ||
| 87 | unsigned int dummy1 : 30; | ||
| 88 | } reg_iop_sw_cfg_rw_crc_par_owner; | ||
| 89 | #define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 | ||
| 90 | #define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 | ||
| 91 | |||
| 92 | /* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ | ||
| 93 | typedef struct { | ||
| 94 | unsigned int cfg : 2; | ||
| 95 | unsigned int dummy1 : 30; | ||
| 96 | } reg_iop_sw_cfg_rw_dmc_in_owner; | ||
| 97 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 | ||
| 98 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 | ||
| 99 | |||
| 100 | /* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ | ||
| 101 | typedef struct { | ||
| 102 | unsigned int cfg : 2; | ||
| 103 | unsigned int dummy1 : 30; | ||
| 104 | } reg_iop_sw_cfg_rw_dmc_out_owner; | ||
| 105 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 | ||
| 106 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 | ||
| 107 | |||
| 108 | /* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ | ||
| 109 | typedef struct { | ||
| 110 | unsigned int cfg : 2; | ||
| 111 | unsigned int dummy1 : 30; | ||
| 112 | } reg_iop_sw_cfg_rw_fifo_in_owner; | ||
| 113 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 | ||
| 114 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 | ||
| 115 | |||
| 116 | /* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 117 | typedef struct { | ||
| 118 | unsigned int cfg : 2; | ||
| 119 | unsigned int dummy1 : 30; | ||
| 120 | } reg_iop_sw_cfg_rw_fifo_in_extra_owner; | ||
| 121 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 | ||
| 122 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 | ||
| 123 | |||
| 124 | /* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ | ||
| 125 | typedef struct { | ||
| 126 | unsigned int cfg : 2; | ||
| 127 | unsigned int dummy1 : 30; | ||
| 128 | } reg_iop_sw_cfg_rw_fifo_out_owner; | ||
| 129 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 | ||
| 130 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 | ||
| 131 | |||
| 132 | /* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ | ||
| 133 | typedef struct { | ||
| 134 | unsigned int cfg : 2; | ||
| 135 | unsigned int dummy1 : 30; | ||
| 136 | } reg_iop_sw_cfg_rw_fifo_out_extra_owner; | ||
| 137 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 | ||
| 138 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 | ||
| 139 | |||
| 140 | /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ | ||
| 141 | typedef struct { | ||
| 142 | unsigned int cfg : 2; | ||
| 143 | unsigned int dummy1 : 30; | ||
| 144 | } reg_iop_sw_cfg_rw_sap_in_owner; | ||
| 145 | #define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 | ||
| 146 | #define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 | ||
| 147 | |||
| 148 | /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ | ||
| 149 | typedef struct { | ||
| 150 | unsigned int cfg : 2; | ||
| 151 | unsigned int dummy1 : 30; | ||
| 152 | } reg_iop_sw_cfg_rw_sap_out_owner; | ||
| 153 | #define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 | ||
| 154 | #define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 | ||
| 155 | |||
| 156 | /* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ | ||
| 157 | typedef struct { | ||
| 158 | unsigned int cfg : 2; | ||
| 159 | unsigned int dummy1 : 30; | ||
| 160 | } reg_iop_sw_cfg_rw_scrc_in_owner; | ||
| 161 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 | ||
| 162 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 | ||
| 163 | |||
| 164 | /* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ | ||
| 165 | typedef struct { | ||
| 166 | unsigned int cfg : 2; | ||
| 167 | unsigned int dummy1 : 30; | ||
| 168 | } reg_iop_sw_cfg_rw_scrc_out_owner; | ||
| 169 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 | ||
| 170 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 | ||
| 171 | |||
| 172 | /* Register rw_spu_owner, scope iop_sw_cfg, type rw */ | ||
| 173 | typedef struct { | ||
| 174 | unsigned int cfg : 1; | ||
| 175 | unsigned int dummy1 : 31; | ||
| 176 | } reg_iop_sw_cfg_rw_spu_owner; | ||
| 177 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 | ||
| 178 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 | ||
| 179 | |||
| 180 | /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 181 | typedef struct { | ||
| 182 | unsigned int cfg : 2; | ||
| 183 | unsigned int dummy1 : 30; | ||
| 184 | } reg_iop_sw_cfg_rw_timer_grp0_owner; | ||
| 185 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 | ||
| 186 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 | ||
| 187 | |||
| 188 | /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 189 | typedef struct { | ||
| 190 | unsigned int cfg : 2; | ||
| 191 | unsigned int dummy1 : 30; | ||
| 192 | } reg_iop_sw_cfg_rw_timer_grp1_owner; | ||
| 193 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 | ||
| 194 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 | ||
| 195 | |||
| 196 | /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int cfg : 2; | ||
| 199 | unsigned int dummy1 : 30; | ||
| 200 | } reg_iop_sw_cfg_rw_trigger_grp0_owner; | ||
| 201 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 | ||
| 202 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 | ||
| 203 | |||
| 204 | /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ | ||
| 205 | typedef struct { | ||
| 206 | unsigned int cfg : 2; | ||
| 207 | unsigned int dummy1 : 30; | ||
| 208 | } reg_iop_sw_cfg_rw_trigger_grp1_owner; | ||
| 209 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 | ||
| 210 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 | ||
| 211 | |||
| 212 | /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ | ||
| 213 | typedef struct { | ||
| 214 | unsigned int cfg : 2; | ||
| 215 | unsigned int dummy1 : 30; | ||
| 216 | } reg_iop_sw_cfg_rw_trigger_grp2_owner; | ||
| 217 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 | ||
| 218 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 | ||
| 219 | |||
| 220 | /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ | ||
| 221 | typedef struct { | ||
| 222 | unsigned int cfg : 2; | ||
| 223 | unsigned int dummy1 : 30; | ||
| 224 | } reg_iop_sw_cfg_rw_trigger_grp3_owner; | ||
| 225 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 | ||
| 226 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 | ||
| 227 | |||
| 228 | /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ | ||
| 229 | typedef struct { | ||
| 230 | unsigned int cfg : 2; | ||
| 231 | unsigned int dummy1 : 30; | ||
| 232 | } reg_iop_sw_cfg_rw_trigger_grp4_owner; | ||
| 233 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 | ||
| 234 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 | ||
| 235 | |||
| 236 | /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int cfg : 2; | ||
| 239 | unsigned int dummy1 : 30; | ||
| 240 | } reg_iop_sw_cfg_rw_trigger_grp5_owner; | ||
| 241 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 | ||
| 242 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 | ||
| 243 | |||
| 244 | /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ | ||
| 245 | typedef struct { | ||
| 246 | unsigned int cfg : 2; | ||
| 247 | unsigned int dummy1 : 30; | ||
| 248 | } reg_iop_sw_cfg_rw_trigger_grp6_owner; | ||
| 249 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 | ||
| 250 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 | ||
| 251 | |||
| 252 | /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ | ||
| 253 | typedef struct { | ||
| 254 | unsigned int cfg : 2; | ||
| 255 | unsigned int dummy1 : 30; | ||
| 256 | } reg_iop_sw_cfg_rw_trigger_grp7_owner; | ||
| 257 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 | ||
| 258 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 | ||
| 259 | |||
| 260 | /* Register rw_bus_mask, scope iop_sw_cfg, type rw */ | ||
| 261 | typedef struct { | ||
| 262 | unsigned int byte0 : 8; | ||
| 263 | unsigned int byte1 : 8; | ||
| 264 | unsigned int byte2 : 8; | ||
| 265 | unsigned int byte3 : 8; | ||
| 266 | } reg_iop_sw_cfg_rw_bus_mask; | ||
| 267 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 | ||
| 268 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 | ||
| 269 | |||
| 270 | /* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 271 | typedef struct { | ||
| 272 | unsigned int byte0 : 1; | ||
| 273 | unsigned int byte1 : 1; | ||
| 274 | unsigned int byte2 : 1; | ||
| 275 | unsigned int byte3 : 1; | ||
| 276 | unsigned int dummy1 : 28; | ||
| 277 | } reg_iop_sw_cfg_rw_bus_oe_mask; | ||
| 278 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 | ||
| 279 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 | ||
| 280 | |||
| 281 | /* Register rw_gio_mask, scope iop_sw_cfg, type rw */ | ||
| 282 | typedef struct { | ||
| 283 | unsigned int val : 32; | ||
| 284 | } reg_iop_sw_cfg_rw_gio_mask; | ||
| 285 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 | ||
| 286 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 | ||
| 287 | |||
| 288 | /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ | ||
| 289 | typedef struct { | ||
| 290 | unsigned int val : 32; | ||
| 291 | } reg_iop_sw_cfg_rw_gio_oe_mask; | ||
| 292 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 | ||
| 293 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 | ||
| 294 | |||
| 295 | /* Register rw_pinmapping, scope iop_sw_cfg, type rw */ | ||
| 296 | typedef struct { | ||
| 297 | unsigned int bus_byte0 : 2; | ||
| 298 | unsigned int bus_byte1 : 2; | ||
| 299 | unsigned int bus_byte2 : 2; | ||
| 300 | unsigned int bus_byte3 : 2; | ||
| 301 | unsigned int gio3_0 : 2; | ||
| 302 | unsigned int gio7_4 : 2; | ||
| 303 | unsigned int gio11_8 : 2; | ||
| 304 | unsigned int gio15_12 : 2; | ||
| 305 | unsigned int gio19_16 : 2; | ||
| 306 | unsigned int gio23_20 : 2; | ||
| 307 | unsigned int gio27_24 : 2; | ||
| 308 | unsigned int gio31_28 : 2; | ||
| 309 | unsigned int dummy1 : 8; | ||
| 310 | } reg_iop_sw_cfg_rw_pinmapping; | ||
| 311 | #define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 | ||
| 312 | #define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 | ||
| 313 | |||
| 314 | /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ | ||
| 315 | typedef struct { | ||
| 316 | unsigned int bus_lo : 2; | ||
| 317 | unsigned int bus_hi : 2; | ||
| 318 | unsigned int bus_lo_oe : 2; | ||
| 319 | unsigned int bus_hi_oe : 2; | ||
| 320 | unsigned int dummy1 : 24; | ||
| 321 | } reg_iop_sw_cfg_rw_bus_out_cfg; | ||
| 322 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 | ||
| 323 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 | ||
| 324 | |||
| 325 | /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 326 | typedef struct { | ||
| 327 | unsigned int gio0 : 3; | ||
| 328 | unsigned int gio0_oe : 1; | ||
| 329 | unsigned int gio1 : 3; | ||
| 330 | unsigned int gio1_oe : 1; | ||
| 331 | unsigned int gio2 : 3; | ||
| 332 | unsigned int gio2_oe : 1; | ||
| 333 | unsigned int gio3 : 3; | ||
| 334 | unsigned int gio3_oe : 1; | ||
| 335 | unsigned int dummy1 : 16; | ||
| 336 | } reg_iop_sw_cfg_rw_gio_out_grp0_cfg; | ||
| 337 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 | ||
| 338 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 | ||
| 339 | |||
| 340 | /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 341 | typedef struct { | ||
| 342 | unsigned int gio4 : 3; | ||
| 343 | unsigned int gio4_oe : 1; | ||
| 344 | unsigned int gio5 : 3; | ||
| 345 | unsigned int gio5_oe : 1; | ||
| 346 | unsigned int gio6 : 3; | ||
| 347 | unsigned int gio6_oe : 1; | ||
| 348 | unsigned int gio7 : 3; | ||
| 349 | unsigned int gio7_oe : 1; | ||
| 350 | unsigned int dummy1 : 16; | ||
| 351 | } reg_iop_sw_cfg_rw_gio_out_grp1_cfg; | ||
| 352 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 | ||
| 353 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 | ||
| 354 | |||
| 355 | /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ | ||
| 356 | typedef struct { | ||
| 357 | unsigned int gio8 : 3; | ||
| 358 | unsigned int gio8_oe : 1; | ||
| 359 | unsigned int gio9 : 3; | ||
| 360 | unsigned int gio9_oe : 1; | ||
| 361 | unsigned int gio10 : 3; | ||
| 362 | unsigned int gio10_oe : 1; | ||
| 363 | unsigned int gio11 : 3; | ||
| 364 | unsigned int gio11_oe : 1; | ||
| 365 | unsigned int dummy1 : 16; | ||
| 366 | } reg_iop_sw_cfg_rw_gio_out_grp2_cfg; | ||
| 367 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 | ||
| 368 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 | ||
| 369 | |||
| 370 | /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ | ||
| 371 | typedef struct { | ||
| 372 | unsigned int gio12 : 3; | ||
| 373 | unsigned int gio12_oe : 1; | ||
| 374 | unsigned int gio13 : 3; | ||
| 375 | unsigned int gio13_oe : 1; | ||
| 376 | unsigned int gio14 : 3; | ||
| 377 | unsigned int gio14_oe : 1; | ||
| 378 | unsigned int gio15 : 3; | ||
| 379 | unsigned int gio15_oe : 1; | ||
| 380 | unsigned int dummy1 : 16; | ||
| 381 | } reg_iop_sw_cfg_rw_gio_out_grp3_cfg; | ||
| 382 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 | ||
| 383 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 | ||
| 384 | |||
| 385 | /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ | ||
| 386 | typedef struct { | ||
| 387 | unsigned int gio16 : 3; | ||
| 388 | unsigned int gio16_oe : 1; | ||
| 389 | unsigned int gio17 : 3; | ||
| 390 | unsigned int gio17_oe : 1; | ||
| 391 | unsigned int gio18 : 3; | ||
| 392 | unsigned int gio18_oe : 1; | ||
| 393 | unsigned int gio19 : 3; | ||
| 394 | unsigned int gio19_oe : 1; | ||
| 395 | unsigned int dummy1 : 16; | ||
| 396 | } reg_iop_sw_cfg_rw_gio_out_grp4_cfg; | ||
| 397 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 | ||
| 398 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 | ||
| 399 | |||
| 400 | /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ | ||
| 401 | typedef struct { | ||
| 402 | unsigned int gio20 : 3; | ||
| 403 | unsigned int gio20_oe : 1; | ||
| 404 | unsigned int gio21 : 3; | ||
| 405 | unsigned int gio21_oe : 1; | ||
| 406 | unsigned int gio22 : 3; | ||
| 407 | unsigned int gio22_oe : 1; | ||
| 408 | unsigned int gio23 : 3; | ||
| 409 | unsigned int gio23_oe : 1; | ||
| 410 | unsigned int dummy1 : 16; | ||
| 411 | } reg_iop_sw_cfg_rw_gio_out_grp5_cfg; | ||
| 412 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 | ||
| 413 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 | ||
| 414 | |||
| 415 | /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ | ||
| 416 | typedef struct { | ||
| 417 | unsigned int gio24 : 3; | ||
| 418 | unsigned int gio24_oe : 1; | ||
| 419 | unsigned int gio25 : 3; | ||
| 420 | unsigned int gio25_oe : 1; | ||
| 421 | unsigned int gio26 : 3; | ||
| 422 | unsigned int gio26_oe : 1; | ||
| 423 | unsigned int gio27 : 3; | ||
| 424 | unsigned int gio27_oe : 1; | ||
| 425 | unsigned int dummy1 : 16; | ||
| 426 | } reg_iop_sw_cfg_rw_gio_out_grp6_cfg; | ||
| 427 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 | ||
| 428 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 | ||
| 429 | |||
| 430 | /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ | ||
| 431 | typedef struct { | ||
| 432 | unsigned int gio28 : 3; | ||
| 433 | unsigned int gio28_oe : 1; | ||
| 434 | unsigned int gio29 : 3; | ||
| 435 | unsigned int gio29_oe : 1; | ||
| 436 | unsigned int gio30 : 3; | ||
| 437 | unsigned int gio30_oe : 1; | ||
| 438 | unsigned int gio31 : 3; | ||
| 439 | unsigned int gio31_oe : 1; | ||
| 440 | unsigned int dummy1 : 16; | ||
| 441 | } reg_iop_sw_cfg_rw_gio_out_grp7_cfg; | ||
| 442 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 | ||
| 443 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 | ||
| 444 | |||
| 445 | /* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ | ||
| 446 | typedef struct { | ||
| 447 | unsigned int bus0_in : 1; | ||
| 448 | unsigned int bus1_in : 1; | ||
| 449 | unsigned int dummy1 : 30; | ||
| 450 | } reg_iop_sw_cfg_rw_spu_cfg; | ||
| 451 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 | ||
| 452 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 | ||
| 453 | |||
| 454 | /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ | ||
| 455 | typedef struct { | ||
| 456 | unsigned int ext_clk : 3; | ||
| 457 | unsigned int tmr0_en : 2; | ||
| 458 | unsigned int tmr1_en : 2; | ||
| 459 | unsigned int tmr2_en : 2; | ||
| 460 | unsigned int tmr3_en : 2; | ||
| 461 | unsigned int tmr0_dis : 2; | ||
| 462 | unsigned int tmr1_dis : 2; | ||
| 463 | unsigned int tmr2_dis : 2; | ||
| 464 | unsigned int tmr3_dis : 2; | ||
| 465 | unsigned int dummy1 : 13; | ||
| 466 | } reg_iop_sw_cfg_rw_timer_grp0_cfg; | ||
| 467 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 | ||
| 468 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 | ||
| 469 | |||
| 470 | /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ | ||
| 471 | typedef struct { | ||
| 472 | unsigned int ext_clk : 3; | ||
| 473 | unsigned int tmr0_en : 2; | ||
| 474 | unsigned int tmr1_en : 2; | ||
| 475 | unsigned int tmr2_en : 2; | ||
| 476 | unsigned int tmr3_en : 2; | ||
| 477 | unsigned int tmr0_dis : 2; | ||
| 478 | unsigned int tmr1_dis : 2; | ||
| 479 | unsigned int tmr2_dis : 2; | ||
| 480 | unsigned int tmr3_dis : 2; | ||
| 481 | unsigned int dummy1 : 13; | ||
| 482 | } reg_iop_sw_cfg_rw_timer_grp1_cfg; | ||
| 483 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 | ||
| 484 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 | ||
| 485 | |||
| 486 | /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ | ||
| 487 | typedef struct { | ||
| 488 | unsigned int grp0_dis : 1; | ||
| 489 | unsigned int grp0_en : 1; | ||
| 490 | unsigned int grp1_dis : 1; | ||
| 491 | unsigned int grp1_en : 1; | ||
| 492 | unsigned int grp2_dis : 1; | ||
| 493 | unsigned int grp2_en : 1; | ||
| 494 | unsigned int grp3_dis : 1; | ||
| 495 | unsigned int grp3_en : 1; | ||
| 496 | unsigned int grp4_dis : 1; | ||
| 497 | unsigned int grp4_en : 1; | ||
| 498 | unsigned int grp5_dis : 1; | ||
| 499 | unsigned int grp5_en : 1; | ||
| 500 | unsigned int grp6_dis : 1; | ||
| 501 | unsigned int grp6_en : 1; | ||
| 502 | unsigned int grp7_dis : 1; | ||
| 503 | unsigned int grp7_en : 1; | ||
| 504 | unsigned int dummy1 : 16; | ||
| 505 | } reg_iop_sw_cfg_rw_trigger_grps_cfg; | ||
| 506 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 | ||
| 507 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 | ||
| 508 | |||
| 509 | /* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ | ||
| 510 | typedef struct { | ||
| 511 | unsigned int out_strb : 4; | ||
| 512 | unsigned int in_src : 2; | ||
| 513 | unsigned int in_size : 3; | ||
| 514 | unsigned int in_last : 2; | ||
| 515 | unsigned int in_strb : 4; | ||
| 516 | unsigned int dummy1 : 17; | ||
| 517 | } reg_iop_sw_cfg_rw_pdp_cfg; | ||
| 518 | #define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 | ||
| 519 | #define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 | ||
| 520 | |||
| 521 | /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ | ||
| 522 | typedef struct { | ||
| 523 | unsigned int sdp_out_strb : 3; | ||
| 524 | unsigned int sdp_in_data : 3; | ||
| 525 | unsigned int sdp_in_last : 2; | ||
| 526 | unsigned int sdp_in_strb : 3; | ||
| 527 | unsigned int dummy1 : 21; | ||
| 528 | } reg_iop_sw_cfg_rw_sdp_cfg; | ||
| 529 | #define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 | ||
| 530 | #define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 | ||
| 531 | |||
| 532 | |||
| 533 | /* Constants */ | ||
| 534 | enum { | ||
| 535 | regk_iop_sw_cfg_a = 0x00000001, | ||
| 536 | regk_iop_sw_cfg_b = 0x00000002, | ||
| 537 | regk_iop_sw_cfg_bus = 0x00000000, | ||
| 538 | regk_iop_sw_cfg_bus_rot16 = 0x00000002, | ||
| 539 | regk_iop_sw_cfg_bus_rot24 = 0x00000003, | ||
| 540 | regk_iop_sw_cfg_bus_rot8 = 0x00000001, | ||
| 541 | regk_iop_sw_cfg_clk12 = 0x00000000, | ||
| 542 | regk_iop_sw_cfg_cpu = 0x00000000, | ||
| 543 | regk_iop_sw_cfg_gated_clk0 = 0x0000000e, | ||
| 544 | regk_iop_sw_cfg_gated_clk1 = 0x0000000f, | ||
| 545 | regk_iop_sw_cfg_gio0 = 0x00000004, | ||
| 546 | regk_iop_sw_cfg_gio1 = 0x00000001, | ||
| 547 | regk_iop_sw_cfg_gio2 = 0x00000005, | ||
| 548 | regk_iop_sw_cfg_gio3 = 0x00000002, | ||
| 549 | regk_iop_sw_cfg_gio4 = 0x00000006, | ||
| 550 | regk_iop_sw_cfg_gio5 = 0x00000003, | ||
| 551 | regk_iop_sw_cfg_gio6 = 0x00000007, | ||
| 552 | regk_iop_sw_cfg_gio7 = 0x00000004, | ||
| 553 | regk_iop_sw_cfg_gio_in18 = 0x00000002, | ||
| 554 | regk_iop_sw_cfg_gio_in19 = 0x00000003, | ||
| 555 | regk_iop_sw_cfg_gio_in20 = 0x00000004, | ||
| 556 | regk_iop_sw_cfg_gio_in21 = 0x00000005, | ||
| 557 | regk_iop_sw_cfg_gio_in26 = 0x00000006, | ||
| 558 | regk_iop_sw_cfg_gio_in27 = 0x00000007, | ||
| 559 | regk_iop_sw_cfg_gio_in4 = 0x00000000, | ||
| 560 | regk_iop_sw_cfg_gio_in5 = 0x00000001, | ||
| 561 | regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, | ||
| 562 | regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, | ||
| 563 | regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, | ||
| 564 | regk_iop_sw_cfg_mpu = 0x00000001, | ||
| 565 | regk_iop_sw_cfg_none = 0x00000000, | ||
| 566 | regk_iop_sw_cfg_pdp_out = 0x00000001, | ||
| 567 | regk_iop_sw_cfg_pdp_out_hi = 0x00000001, | ||
| 568 | regk_iop_sw_cfg_pdp_out_lo = 0x00000000, | ||
| 569 | regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, | ||
| 570 | regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, | ||
| 571 | regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, | ||
| 572 | regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, | ||
| 573 | regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, | ||
| 574 | regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, | ||
| 575 | regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, | ||
| 576 | regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, | ||
| 577 | regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, | ||
| 578 | regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, | ||
| 579 | regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, | ||
| 580 | regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, | ||
| 581 | regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, | ||
| 582 | regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, | ||
| 583 | regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, | ||
| 584 | regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, | ||
| 585 | regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, | ||
| 586 | regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, | ||
| 587 | regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, | ||
| 588 | regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, | ||
| 589 | regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, | ||
| 590 | regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, | ||
| 591 | regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, | ||
| 592 | regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, | ||
| 593 | regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, | ||
| 594 | regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, | ||
| 595 | regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, | ||
| 596 | regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, | ||
| 597 | regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, | ||
| 598 | regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, | ||
| 599 | regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, | ||
| 600 | regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, | ||
| 601 | regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, | ||
| 602 | regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, | ||
| 603 | regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, | ||
| 604 | regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, | ||
| 605 | regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, | ||
| 606 | regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, | ||
| 607 | regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, | ||
| 608 | regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, | ||
| 609 | regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, | ||
| 610 | regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, | ||
| 611 | regk_iop_sw_cfg_sdp_out = 0x00000004, | ||
| 612 | regk_iop_sw_cfg_size16 = 0x00000002, | ||
| 613 | regk_iop_sw_cfg_size24 = 0x00000003, | ||
| 614 | regk_iop_sw_cfg_size32 = 0x00000004, | ||
| 615 | regk_iop_sw_cfg_size8 = 0x00000001, | ||
| 616 | regk_iop_sw_cfg_spu = 0x00000002, | ||
| 617 | regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, | ||
| 618 | regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, | ||
| 619 | regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, | ||
| 620 | regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, | ||
| 621 | regk_iop_sw_cfg_spu_g0 = 0x00000007, | ||
| 622 | regk_iop_sw_cfg_spu_g1 = 0x00000007, | ||
| 623 | regk_iop_sw_cfg_spu_g2 = 0x00000007, | ||
| 624 | regk_iop_sw_cfg_spu_g3 = 0x00000007, | ||
| 625 | regk_iop_sw_cfg_spu_g4 = 0x00000007, | ||
| 626 | regk_iop_sw_cfg_spu_g5 = 0x00000007, | ||
| 627 | regk_iop_sw_cfg_spu_g6 = 0x00000007, | ||
| 628 | regk_iop_sw_cfg_spu_g7 = 0x00000007, | ||
| 629 | regk_iop_sw_cfg_spu_gio0 = 0x00000000, | ||
| 630 | regk_iop_sw_cfg_spu_gio1 = 0x00000001, | ||
| 631 | regk_iop_sw_cfg_spu_gio5 = 0x00000005, | ||
| 632 | regk_iop_sw_cfg_spu_gio6 = 0x00000006, | ||
| 633 | regk_iop_sw_cfg_spu_gio7 = 0x00000007, | ||
| 634 | regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, | ||
| 635 | regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, | ||
| 636 | regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, | ||
| 637 | regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, | ||
| 638 | regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, | ||
| 639 | regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, | ||
| 640 | regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, | ||
| 641 | regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, | ||
| 642 | regk_iop_sw_cfg_spu_gioout0 = 0x00000000, | ||
| 643 | regk_iop_sw_cfg_spu_gioout1 = 0x00000000, | ||
| 644 | regk_iop_sw_cfg_spu_gioout10 = 0x00000007, | ||
| 645 | regk_iop_sw_cfg_spu_gioout11 = 0x00000007, | ||
| 646 | regk_iop_sw_cfg_spu_gioout12 = 0x00000007, | ||
| 647 | regk_iop_sw_cfg_spu_gioout13 = 0x00000007, | ||
| 648 | regk_iop_sw_cfg_spu_gioout14 = 0x00000007, | ||
| 649 | regk_iop_sw_cfg_spu_gioout15 = 0x00000007, | ||
| 650 | regk_iop_sw_cfg_spu_gioout16 = 0x00000007, | ||
| 651 | regk_iop_sw_cfg_spu_gioout17 = 0x00000007, | ||
| 652 | regk_iop_sw_cfg_spu_gioout18 = 0x00000007, | ||
| 653 | regk_iop_sw_cfg_spu_gioout19 = 0x00000007, | ||
| 654 | regk_iop_sw_cfg_spu_gioout2 = 0x00000001, | ||
| 655 | regk_iop_sw_cfg_spu_gioout20 = 0x00000007, | ||
| 656 | regk_iop_sw_cfg_spu_gioout21 = 0x00000007, | ||
| 657 | regk_iop_sw_cfg_spu_gioout22 = 0x00000007, | ||
| 658 | regk_iop_sw_cfg_spu_gioout23 = 0x00000007, | ||
| 659 | regk_iop_sw_cfg_spu_gioout24 = 0x00000007, | ||
| 660 | regk_iop_sw_cfg_spu_gioout25 = 0x00000007, | ||
| 661 | regk_iop_sw_cfg_spu_gioout26 = 0x00000007, | ||
| 662 | regk_iop_sw_cfg_spu_gioout27 = 0x00000007, | ||
| 663 | regk_iop_sw_cfg_spu_gioout28 = 0x00000007, | ||
| 664 | regk_iop_sw_cfg_spu_gioout29 = 0x00000007, | ||
| 665 | regk_iop_sw_cfg_spu_gioout3 = 0x00000001, | ||
| 666 | regk_iop_sw_cfg_spu_gioout30 = 0x00000007, | ||
| 667 | regk_iop_sw_cfg_spu_gioout31 = 0x00000007, | ||
| 668 | regk_iop_sw_cfg_spu_gioout4 = 0x00000002, | ||
| 669 | regk_iop_sw_cfg_spu_gioout5 = 0x00000002, | ||
| 670 | regk_iop_sw_cfg_spu_gioout6 = 0x00000003, | ||
| 671 | regk_iop_sw_cfg_spu_gioout7 = 0x00000003, | ||
| 672 | regk_iop_sw_cfg_spu_gioout8 = 0x00000007, | ||
| 673 | regk_iop_sw_cfg_spu_gioout9 = 0x00000007, | ||
| 674 | regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, | ||
| 675 | regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, | ||
| 676 | regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, | ||
| 677 | regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, | ||
| 678 | regk_iop_sw_cfg_timer_grp0 = 0x00000000, | ||
| 679 | regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, | ||
| 680 | regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, | ||
| 681 | regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, | ||
| 682 | regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, | ||
| 683 | regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, | ||
| 684 | regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, | ||
| 685 | regk_iop_sw_cfg_timer_grp1 = 0x00000000, | ||
| 686 | regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, | ||
| 687 | regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, | ||
| 688 | regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, | ||
| 689 | regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, | ||
| 690 | regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, | ||
| 691 | regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, | ||
| 692 | regk_iop_sw_cfg_trig0_0 = 0x00000000, | ||
| 693 | regk_iop_sw_cfg_trig0_1 = 0x00000000, | ||
| 694 | regk_iop_sw_cfg_trig0_2 = 0x00000000, | ||
| 695 | regk_iop_sw_cfg_trig0_3 = 0x00000000, | ||
| 696 | regk_iop_sw_cfg_trig1_0 = 0x00000000, | ||
| 697 | regk_iop_sw_cfg_trig1_1 = 0x00000000, | ||
| 698 | regk_iop_sw_cfg_trig1_2 = 0x00000000, | ||
| 699 | regk_iop_sw_cfg_trig1_3 = 0x00000000, | ||
| 700 | regk_iop_sw_cfg_trig2_0 = 0x00000001, | ||
| 701 | regk_iop_sw_cfg_trig2_1 = 0x00000001, | ||
| 702 | regk_iop_sw_cfg_trig2_2 = 0x00000001, | ||
| 703 | regk_iop_sw_cfg_trig2_3 = 0x00000001, | ||
| 704 | regk_iop_sw_cfg_trig3_0 = 0x00000001, | ||
| 705 | regk_iop_sw_cfg_trig3_1 = 0x00000001, | ||
| 706 | regk_iop_sw_cfg_trig3_2 = 0x00000001, | ||
| 707 | regk_iop_sw_cfg_trig3_3 = 0x00000001, | ||
| 708 | regk_iop_sw_cfg_trig4_0 = 0x00000002, | ||
| 709 | regk_iop_sw_cfg_trig4_1 = 0x00000002, | ||
| 710 | regk_iop_sw_cfg_trig4_2 = 0x00000002, | ||
| 711 | regk_iop_sw_cfg_trig4_3 = 0x00000002, | ||
| 712 | regk_iop_sw_cfg_trig5_0 = 0x00000002, | ||
| 713 | regk_iop_sw_cfg_trig5_1 = 0x00000002, | ||
| 714 | regk_iop_sw_cfg_trig5_2 = 0x00000002, | ||
| 715 | regk_iop_sw_cfg_trig5_3 = 0x00000002, | ||
| 716 | regk_iop_sw_cfg_trig6_0 = 0x00000003, | ||
| 717 | regk_iop_sw_cfg_trig6_1 = 0x00000003, | ||
| 718 | regk_iop_sw_cfg_trig6_2 = 0x00000003, | ||
| 719 | regk_iop_sw_cfg_trig6_3 = 0x00000003, | ||
| 720 | regk_iop_sw_cfg_trig7_0 = 0x00000003, | ||
| 721 | regk_iop_sw_cfg_trig7_1 = 0x00000003, | ||
| 722 | regk_iop_sw_cfg_trig7_2 = 0x00000003, | ||
| 723 | regk_iop_sw_cfg_trig7_3 = 0x00000003 | ||
| 724 | }; | ||
| 725 | #endif /* __iop_sw_cfg_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h new file mode 100644 index 000000000000..a16f556370eb --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_cpu_defs.h | |||
| @@ -0,0 +1,522 @@ | |||
| 1 | #ifndef __iop_sw_cpu_defs_h | ||
| 2 | #define __iop_sw_cpu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_cpu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sw_cpu */ | ||
| 83 | |||
| 84 | /* Register r_mpu_trace, scope iop_sw_cpu, type r */ | ||
| 85 | typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; | ||
| 86 | #define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 | ||
| 87 | |||
| 88 | /* Register r_spu_trace, scope iop_sw_cpu, type r */ | ||
| 89 | typedef unsigned int reg_iop_sw_cpu_r_spu_trace; | ||
| 90 | #define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 | ||
| 91 | |||
| 92 | /* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ | ||
| 93 | typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; | ||
| 94 | #define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 | ||
| 95 | |||
| 96 | /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ | ||
| 97 | typedef struct { | ||
| 98 | unsigned int keep_owner : 1; | ||
| 99 | unsigned int cmd : 2; | ||
| 100 | unsigned int size : 3; | ||
| 101 | unsigned int wr_spu_mem : 1; | ||
| 102 | unsigned int dummy1 : 25; | ||
| 103 | } reg_iop_sw_cpu_rw_mc_ctrl; | ||
| 104 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 | ||
| 105 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 | ||
| 106 | |||
| 107 | /* Register rw_mc_data, scope iop_sw_cpu, type rw */ | ||
| 108 | typedef struct { | ||
| 109 | unsigned int val : 32; | ||
| 110 | } reg_iop_sw_cpu_rw_mc_data; | ||
| 111 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 | ||
| 112 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 | ||
| 113 | |||
| 114 | /* Register rw_mc_addr, scope iop_sw_cpu, type rw */ | ||
| 115 | typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; | ||
| 116 | #define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 | ||
| 117 | #define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 | ||
| 118 | |||
| 119 | /* Register rs_mc_data, scope iop_sw_cpu, type rs */ | ||
| 120 | typedef unsigned int reg_iop_sw_cpu_rs_mc_data; | ||
| 121 | #define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 | ||
| 122 | |||
| 123 | /* Register r_mc_data, scope iop_sw_cpu, type r */ | ||
| 124 | typedef unsigned int reg_iop_sw_cpu_r_mc_data; | ||
| 125 | #define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 | ||
| 126 | |||
| 127 | /* Register r_mc_stat, scope iop_sw_cpu, type r */ | ||
| 128 | typedef struct { | ||
| 129 | unsigned int busy_cpu : 1; | ||
| 130 | unsigned int busy_mpu : 1; | ||
| 131 | unsigned int busy_spu : 1; | ||
| 132 | unsigned int owned_by_cpu : 1; | ||
| 133 | unsigned int owned_by_mpu : 1; | ||
| 134 | unsigned int owned_by_spu : 1; | ||
| 135 | unsigned int dummy1 : 26; | ||
| 136 | } reg_iop_sw_cpu_r_mc_stat; | ||
| 137 | #define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 | ||
| 138 | |||
| 139 | /* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 140 | typedef struct { | ||
| 141 | unsigned int byte0 : 8; | ||
| 142 | unsigned int byte1 : 8; | ||
| 143 | unsigned int byte2 : 8; | ||
| 144 | unsigned int byte3 : 8; | ||
| 145 | } reg_iop_sw_cpu_rw_bus_clr_mask; | ||
| 146 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 | ||
| 147 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 | ||
| 148 | |||
| 149 | /* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ | ||
| 150 | typedef struct { | ||
| 151 | unsigned int byte0 : 8; | ||
| 152 | unsigned int byte1 : 8; | ||
| 153 | unsigned int byte2 : 8; | ||
| 154 | unsigned int byte3 : 8; | ||
| 155 | } reg_iop_sw_cpu_rw_bus_set_mask; | ||
| 156 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 | ||
| 157 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 | ||
| 158 | |||
| 159 | /* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 160 | typedef struct { | ||
| 161 | unsigned int byte0 : 1; | ||
| 162 | unsigned int byte1 : 1; | ||
| 163 | unsigned int byte2 : 1; | ||
| 164 | unsigned int byte3 : 1; | ||
| 165 | unsigned int dummy1 : 28; | ||
| 166 | } reg_iop_sw_cpu_rw_bus_oe_clr_mask; | ||
| 167 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 | ||
| 168 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 | ||
| 169 | |||
| 170 | /* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 171 | typedef struct { | ||
| 172 | unsigned int byte0 : 1; | ||
| 173 | unsigned int byte1 : 1; | ||
| 174 | unsigned int byte2 : 1; | ||
| 175 | unsigned int byte3 : 1; | ||
| 176 | unsigned int dummy1 : 28; | ||
| 177 | } reg_iop_sw_cpu_rw_bus_oe_set_mask; | ||
| 178 | #define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 | ||
| 179 | #define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 | ||
| 180 | |||
| 181 | /* Register r_bus_in, scope iop_sw_cpu, type r */ | ||
| 182 | typedef unsigned int reg_iop_sw_cpu_r_bus_in; | ||
| 183 | #define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 | ||
| 184 | |||
| 185 | /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 186 | typedef struct { | ||
| 187 | unsigned int val : 32; | ||
| 188 | } reg_iop_sw_cpu_rw_gio_clr_mask; | ||
| 189 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 | ||
| 190 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 | ||
| 191 | |||
| 192 | /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ | ||
| 193 | typedef struct { | ||
| 194 | unsigned int val : 32; | ||
| 195 | } reg_iop_sw_cpu_rw_gio_set_mask; | ||
| 196 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 | ||
| 197 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 | ||
| 198 | |||
| 199 | /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ | ||
| 200 | typedef struct { | ||
| 201 | unsigned int val : 32; | ||
| 202 | } reg_iop_sw_cpu_rw_gio_oe_clr_mask; | ||
| 203 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 | ||
| 204 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 | ||
| 205 | |||
| 206 | /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ | ||
| 207 | typedef struct { | ||
| 208 | unsigned int val : 32; | ||
| 209 | } reg_iop_sw_cpu_rw_gio_oe_set_mask; | ||
| 210 | #define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 | ||
| 211 | #define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 | ||
| 212 | |||
| 213 | /* Register r_gio_in, scope iop_sw_cpu, type r */ | ||
| 214 | typedef unsigned int reg_iop_sw_cpu_r_gio_in; | ||
| 215 | #define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 | ||
| 216 | |||
| 217 | /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int mpu_0 : 1; | ||
| 220 | unsigned int mpu_1 : 1; | ||
| 221 | unsigned int mpu_2 : 1; | ||
| 222 | unsigned int mpu_3 : 1; | ||
| 223 | unsigned int mpu_4 : 1; | ||
| 224 | unsigned int mpu_5 : 1; | ||
| 225 | unsigned int mpu_6 : 1; | ||
| 226 | unsigned int mpu_7 : 1; | ||
| 227 | unsigned int mpu_8 : 1; | ||
| 228 | unsigned int mpu_9 : 1; | ||
| 229 | unsigned int mpu_10 : 1; | ||
| 230 | unsigned int mpu_11 : 1; | ||
| 231 | unsigned int mpu_12 : 1; | ||
| 232 | unsigned int mpu_13 : 1; | ||
| 233 | unsigned int mpu_14 : 1; | ||
| 234 | unsigned int mpu_15 : 1; | ||
| 235 | unsigned int spu_0 : 1; | ||
| 236 | unsigned int spu_1 : 1; | ||
| 237 | unsigned int spu_2 : 1; | ||
| 238 | unsigned int spu_3 : 1; | ||
| 239 | unsigned int spu_4 : 1; | ||
| 240 | unsigned int spu_5 : 1; | ||
| 241 | unsigned int spu_6 : 1; | ||
| 242 | unsigned int spu_7 : 1; | ||
| 243 | unsigned int spu_8 : 1; | ||
| 244 | unsigned int spu_9 : 1; | ||
| 245 | unsigned int spu_10 : 1; | ||
| 246 | unsigned int spu_11 : 1; | ||
| 247 | unsigned int spu_12 : 1; | ||
| 248 | unsigned int spu_13 : 1; | ||
| 249 | unsigned int spu_14 : 1; | ||
| 250 | unsigned int spu_15 : 1; | ||
| 251 | } reg_iop_sw_cpu_rw_intr0_mask; | ||
| 252 | #define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 | ||
| 253 | #define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 | ||
| 254 | |||
| 255 | /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ | ||
| 256 | typedef struct { | ||
| 257 | unsigned int mpu_0 : 1; | ||
| 258 | unsigned int mpu_1 : 1; | ||
| 259 | unsigned int mpu_2 : 1; | ||
| 260 | unsigned int mpu_3 : 1; | ||
| 261 | unsigned int mpu_4 : 1; | ||
| 262 | unsigned int mpu_5 : 1; | ||
| 263 | unsigned int mpu_6 : 1; | ||
| 264 | unsigned int mpu_7 : 1; | ||
| 265 | unsigned int mpu_8 : 1; | ||
| 266 | unsigned int mpu_9 : 1; | ||
| 267 | unsigned int mpu_10 : 1; | ||
| 268 | unsigned int mpu_11 : 1; | ||
| 269 | unsigned int mpu_12 : 1; | ||
| 270 | unsigned int mpu_13 : 1; | ||
| 271 | unsigned int mpu_14 : 1; | ||
| 272 | unsigned int mpu_15 : 1; | ||
| 273 | unsigned int spu_0 : 1; | ||
| 274 | unsigned int spu_1 : 1; | ||
| 275 | unsigned int spu_2 : 1; | ||
| 276 | unsigned int spu_3 : 1; | ||
| 277 | unsigned int spu_4 : 1; | ||
| 278 | unsigned int spu_5 : 1; | ||
| 279 | unsigned int spu_6 : 1; | ||
| 280 | unsigned int spu_7 : 1; | ||
| 281 | unsigned int spu_8 : 1; | ||
| 282 | unsigned int spu_9 : 1; | ||
| 283 | unsigned int spu_10 : 1; | ||
| 284 | unsigned int spu_11 : 1; | ||
| 285 | unsigned int spu_12 : 1; | ||
| 286 | unsigned int spu_13 : 1; | ||
| 287 | unsigned int spu_14 : 1; | ||
| 288 | unsigned int spu_15 : 1; | ||
| 289 | } reg_iop_sw_cpu_rw_ack_intr0; | ||
| 290 | #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 | ||
| 291 | #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 | ||
| 292 | |||
| 293 | /* Register r_intr0, scope iop_sw_cpu, type r */ | ||
| 294 | typedef struct { | ||
| 295 | unsigned int mpu_0 : 1; | ||
| 296 | unsigned int mpu_1 : 1; | ||
| 297 | unsigned int mpu_2 : 1; | ||
| 298 | unsigned int mpu_3 : 1; | ||
| 299 | unsigned int mpu_4 : 1; | ||
| 300 | unsigned int mpu_5 : 1; | ||
| 301 | unsigned int mpu_6 : 1; | ||
| 302 | unsigned int mpu_7 : 1; | ||
| 303 | unsigned int mpu_8 : 1; | ||
| 304 | unsigned int mpu_9 : 1; | ||
| 305 | unsigned int mpu_10 : 1; | ||
| 306 | unsigned int mpu_11 : 1; | ||
| 307 | unsigned int mpu_12 : 1; | ||
| 308 | unsigned int mpu_13 : 1; | ||
| 309 | unsigned int mpu_14 : 1; | ||
| 310 | unsigned int mpu_15 : 1; | ||
| 311 | unsigned int spu_0 : 1; | ||
| 312 | unsigned int spu_1 : 1; | ||
| 313 | unsigned int spu_2 : 1; | ||
| 314 | unsigned int spu_3 : 1; | ||
| 315 | unsigned int spu_4 : 1; | ||
| 316 | unsigned int spu_5 : 1; | ||
| 317 | unsigned int spu_6 : 1; | ||
| 318 | unsigned int spu_7 : 1; | ||
| 319 | unsigned int spu_8 : 1; | ||
| 320 | unsigned int spu_9 : 1; | ||
| 321 | unsigned int spu_10 : 1; | ||
| 322 | unsigned int spu_11 : 1; | ||
| 323 | unsigned int spu_12 : 1; | ||
| 324 | unsigned int spu_13 : 1; | ||
| 325 | unsigned int spu_14 : 1; | ||
| 326 | unsigned int spu_15 : 1; | ||
| 327 | } reg_iop_sw_cpu_r_intr0; | ||
| 328 | #define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 | ||
| 329 | |||
| 330 | /* Register r_masked_intr0, scope iop_sw_cpu, type r */ | ||
| 331 | typedef struct { | ||
| 332 | unsigned int mpu_0 : 1; | ||
| 333 | unsigned int mpu_1 : 1; | ||
| 334 | unsigned int mpu_2 : 1; | ||
| 335 | unsigned int mpu_3 : 1; | ||
| 336 | unsigned int mpu_4 : 1; | ||
| 337 | unsigned int mpu_5 : 1; | ||
| 338 | unsigned int mpu_6 : 1; | ||
| 339 | unsigned int mpu_7 : 1; | ||
| 340 | unsigned int mpu_8 : 1; | ||
| 341 | unsigned int mpu_9 : 1; | ||
| 342 | unsigned int mpu_10 : 1; | ||
| 343 | unsigned int mpu_11 : 1; | ||
| 344 | unsigned int mpu_12 : 1; | ||
| 345 | unsigned int mpu_13 : 1; | ||
| 346 | unsigned int mpu_14 : 1; | ||
| 347 | unsigned int mpu_15 : 1; | ||
| 348 | unsigned int spu_0 : 1; | ||
| 349 | unsigned int spu_1 : 1; | ||
| 350 | unsigned int spu_2 : 1; | ||
| 351 | unsigned int spu_3 : 1; | ||
| 352 | unsigned int spu_4 : 1; | ||
| 353 | unsigned int spu_5 : 1; | ||
| 354 | unsigned int spu_6 : 1; | ||
| 355 | unsigned int spu_7 : 1; | ||
| 356 | unsigned int spu_8 : 1; | ||
| 357 | unsigned int spu_9 : 1; | ||
| 358 | unsigned int spu_10 : 1; | ||
| 359 | unsigned int spu_11 : 1; | ||
| 360 | unsigned int spu_12 : 1; | ||
| 361 | unsigned int spu_13 : 1; | ||
| 362 | unsigned int spu_14 : 1; | ||
| 363 | unsigned int spu_15 : 1; | ||
| 364 | } reg_iop_sw_cpu_r_masked_intr0; | ||
| 365 | #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 | ||
| 366 | |||
| 367 | /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ | ||
| 368 | typedef struct { | ||
| 369 | unsigned int mpu_16 : 1; | ||
| 370 | unsigned int mpu_17 : 1; | ||
| 371 | unsigned int mpu_18 : 1; | ||
| 372 | unsigned int mpu_19 : 1; | ||
| 373 | unsigned int mpu_20 : 1; | ||
| 374 | unsigned int mpu_21 : 1; | ||
| 375 | unsigned int mpu_22 : 1; | ||
| 376 | unsigned int mpu_23 : 1; | ||
| 377 | unsigned int mpu_24 : 1; | ||
| 378 | unsigned int mpu_25 : 1; | ||
| 379 | unsigned int mpu_26 : 1; | ||
| 380 | unsigned int mpu_27 : 1; | ||
| 381 | unsigned int mpu_28 : 1; | ||
| 382 | unsigned int mpu_29 : 1; | ||
| 383 | unsigned int mpu_30 : 1; | ||
| 384 | unsigned int mpu_31 : 1; | ||
| 385 | unsigned int dmc_in : 1; | ||
| 386 | unsigned int dmc_out : 1; | ||
| 387 | unsigned int fifo_in : 1; | ||
| 388 | unsigned int fifo_out : 1; | ||
| 389 | unsigned int fifo_in_extra : 1; | ||
| 390 | unsigned int fifo_out_extra : 1; | ||
| 391 | unsigned int trigger_grp0 : 1; | ||
| 392 | unsigned int trigger_grp1 : 1; | ||
| 393 | unsigned int trigger_grp2 : 1; | ||
| 394 | unsigned int trigger_grp3 : 1; | ||
| 395 | unsigned int trigger_grp4 : 1; | ||
| 396 | unsigned int trigger_grp5 : 1; | ||
| 397 | unsigned int trigger_grp6 : 1; | ||
| 398 | unsigned int trigger_grp7 : 1; | ||
| 399 | unsigned int timer_grp0 : 1; | ||
| 400 | unsigned int timer_grp1 : 1; | ||
| 401 | } reg_iop_sw_cpu_rw_intr1_mask; | ||
| 402 | #define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 | ||
| 403 | #define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 | ||
| 404 | |||
| 405 | /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ | ||
| 406 | typedef struct { | ||
| 407 | unsigned int mpu_16 : 1; | ||
| 408 | unsigned int mpu_17 : 1; | ||
| 409 | unsigned int mpu_18 : 1; | ||
| 410 | unsigned int mpu_19 : 1; | ||
| 411 | unsigned int mpu_20 : 1; | ||
| 412 | unsigned int mpu_21 : 1; | ||
| 413 | unsigned int mpu_22 : 1; | ||
| 414 | unsigned int mpu_23 : 1; | ||
| 415 | unsigned int mpu_24 : 1; | ||
| 416 | unsigned int mpu_25 : 1; | ||
| 417 | unsigned int mpu_26 : 1; | ||
| 418 | unsigned int mpu_27 : 1; | ||
| 419 | unsigned int mpu_28 : 1; | ||
| 420 | unsigned int mpu_29 : 1; | ||
| 421 | unsigned int mpu_30 : 1; | ||
| 422 | unsigned int mpu_31 : 1; | ||
| 423 | unsigned int dummy1 : 16; | ||
| 424 | } reg_iop_sw_cpu_rw_ack_intr1; | ||
| 425 | #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 | ||
| 426 | #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 | ||
| 427 | |||
| 428 | /* Register r_intr1, scope iop_sw_cpu, type r */ | ||
| 429 | typedef struct { | ||
| 430 | unsigned int mpu_16 : 1; | ||
| 431 | unsigned int mpu_17 : 1; | ||
| 432 | unsigned int mpu_18 : 1; | ||
| 433 | unsigned int mpu_19 : 1; | ||
| 434 | unsigned int mpu_20 : 1; | ||
| 435 | unsigned int mpu_21 : 1; | ||
| 436 | unsigned int mpu_22 : 1; | ||
| 437 | unsigned int mpu_23 : 1; | ||
| 438 | unsigned int mpu_24 : 1; | ||
| 439 | unsigned int mpu_25 : 1; | ||
| 440 | unsigned int mpu_26 : 1; | ||
| 441 | unsigned int mpu_27 : 1; | ||
| 442 | unsigned int mpu_28 : 1; | ||
| 443 | unsigned int mpu_29 : 1; | ||
| 444 | unsigned int mpu_30 : 1; | ||
| 445 | unsigned int mpu_31 : 1; | ||
| 446 | unsigned int dmc_in : 1; | ||
| 447 | unsigned int dmc_out : 1; | ||
| 448 | unsigned int fifo_in : 1; | ||
| 449 | unsigned int fifo_out : 1; | ||
| 450 | unsigned int fifo_in_extra : 1; | ||
| 451 | unsigned int fifo_out_extra : 1; | ||
| 452 | unsigned int trigger_grp0 : 1; | ||
| 453 | unsigned int trigger_grp1 : 1; | ||
| 454 | unsigned int trigger_grp2 : 1; | ||
| 455 | unsigned int trigger_grp3 : 1; | ||
| 456 | unsigned int trigger_grp4 : 1; | ||
| 457 | unsigned int trigger_grp5 : 1; | ||
| 458 | unsigned int trigger_grp6 : 1; | ||
| 459 | unsigned int trigger_grp7 : 1; | ||
| 460 | unsigned int timer_grp0 : 1; | ||
| 461 | unsigned int timer_grp1 : 1; | ||
| 462 | } reg_iop_sw_cpu_r_intr1; | ||
| 463 | #define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 | ||
| 464 | |||
| 465 | /* Register r_masked_intr1, scope iop_sw_cpu, type r */ | ||
| 466 | typedef struct { | ||
| 467 | unsigned int mpu_16 : 1; | ||
| 468 | unsigned int mpu_17 : 1; | ||
| 469 | unsigned int mpu_18 : 1; | ||
| 470 | unsigned int mpu_19 : 1; | ||
| 471 | unsigned int mpu_20 : 1; | ||
| 472 | unsigned int mpu_21 : 1; | ||
| 473 | unsigned int mpu_22 : 1; | ||
| 474 | unsigned int mpu_23 : 1; | ||
| 475 | unsigned int mpu_24 : 1; | ||
| 476 | unsigned int mpu_25 : 1; | ||
| 477 | unsigned int mpu_26 : 1; | ||
| 478 | unsigned int mpu_27 : 1; | ||
| 479 | unsigned int mpu_28 : 1; | ||
| 480 | unsigned int mpu_29 : 1; | ||
| 481 | unsigned int mpu_30 : 1; | ||
| 482 | unsigned int mpu_31 : 1; | ||
| 483 | unsigned int dmc_in : 1; | ||
| 484 | unsigned int dmc_out : 1; | ||
| 485 | unsigned int fifo_in : 1; | ||
| 486 | unsigned int fifo_out : 1; | ||
| 487 | unsigned int fifo_in_extra : 1; | ||
| 488 | unsigned int fifo_out_extra : 1; | ||
| 489 | unsigned int trigger_grp0 : 1; | ||
| 490 | unsigned int trigger_grp1 : 1; | ||
| 491 | unsigned int trigger_grp2 : 1; | ||
| 492 | unsigned int trigger_grp3 : 1; | ||
| 493 | unsigned int trigger_grp4 : 1; | ||
| 494 | unsigned int trigger_grp5 : 1; | ||
| 495 | unsigned int trigger_grp6 : 1; | ||
| 496 | unsigned int trigger_grp7 : 1; | ||
| 497 | unsigned int timer_grp0 : 1; | ||
| 498 | unsigned int timer_grp1 : 1; | ||
| 499 | } reg_iop_sw_cpu_r_masked_intr1; | ||
| 500 | #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 | ||
| 501 | |||
| 502 | |||
| 503 | /* Constants */ | ||
| 504 | enum { | ||
| 505 | regk_iop_sw_cpu_copy = 0x00000000, | ||
| 506 | regk_iop_sw_cpu_no = 0x00000000, | ||
| 507 | regk_iop_sw_cpu_rd = 0x00000002, | ||
| 508 | regk_iop_sw_cpu_reg_copy = 0x00000001, | ||
| 509 | regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, | ||
| 510 | regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, | ||
| 511 | regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, | ||
| 512 | regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, | ||
| 513 | regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, | ||
| 514 | regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
| 515 | regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, | ||
| 516 | regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, | ||
| 517 | regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, | ||
| 518 | regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, | ||
| 519 | regk_iop_sw_cpu_wr = 0x00000003, | ||
| 520 | regk_iop_sw_cpu_yes = 0x00000001 | ||
| 521 | }; | ||
| 522 | #endif /* __iop_sw_cpu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h new file mode 100644 index 000000000000..a2e4e1a33e57 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_mpu_defs.h | |||
| @@ -0,0 +1,648 @@ | |||
| 1 | #ifndef __iop_sw_mpu_defs_h | ||
| 2 | #define __iop_sw_mpu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_mpu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sw_mpu */ | ||
| 83 | |||
| 84 | /* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int cfg : 2; | ||
| 87 | unsigned int dummy1 : 30; | ||
| 88 | } reg_iop_sw_mpu_rw_sw_cfg_owner; | ||
| 89 | #define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 | ||
| 90 | #define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 | ||
| 91 | |||
| 92 | /* Register r_spu_trace, scope iop_sw_mpu, type r */ | ||
| 93 | typedef unsigned int reg_iop_sw_mpu_r_spu_trace; | ||
| 94 | #define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4 | ||
| 95 | |||
| 96 | /* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ | ||
| 97 | typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace; | ||
| 98 | #define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8 | ||
| 99 | |||
| 100 | /* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ | ||
| 101 | typedef struct { | ||
| 102 | unsigned int keep_owner : 1; | ||
| 103 | unsigned int cmd : 2; | ||
| 104 | unsigned int size : 3; | ||
| 105 | unsigned int wr_spu_mem : 1; | ||
| 106 | unsigned int dummy1 : 25; | ||
| 107 | } reg_iop_sw_mpu_rw_mc_ctrl; | ||
| 108 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12 | ||
| 109 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12 | ||
| 110 | |||
| 111 | /* Register rw_mc_data, scope iop_sw_mpu, type rw */ | ||
| 112 | typedef struct { | ||
| 113 | unsigned int val : 32; | ||
| 114 | } reg_iop_sw_mpu_rw_mc_data; | ||
| 115 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16 | ||
| 116 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16 | ||
| 117 | |||
| 118 | /* Register rw_mc_addr, scope iop_sw_mpu, type rw */ | ||
| 119 | typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; | ||
| 120 | #define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20 | ||
| 121 | #define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20 | ||
| 122 | |||
| 123 | /* Register rs_mc_data, scope iop_sw_mpu, type rs */ | ||
| 124 | typedef unsigned int reg_iop_sw_mpu_rs_mc_data; | ||
| 125 | #define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24 | ||
| 126 | |||
| 127 | /* Register r_mc_data, scope iop_sw_mpu, type r */ | ||
| 128 | typedef unsigned int reg_iop_sw_mpu_r_mc_data; | ||
| 129 | #define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28 | ||
| 130 | |||
| 131 | /* Register r_mc_stat, scope iop_sw_mpu, type r */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int busy_cpu : 1; | ||
| 134 | unsigned int busy_mpu : 1; | ||
| 135 | unsigned int busy_spu : 1; | ||
| 136 | unsigned int owned_by_cpu : 1; | ||
| 137 | unsigned int owned_by_mpu : 1; | ||
| 138 | unsigned int owned_by_spu : 1; | ||
| 139 | unsigned int dummy1 : 26; | ||
| 140 | } reg_iop_sw_mpu_r_mc_stat; | ||
| 141 | #define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32 | ||
| 142 | |||
| 143 | /* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 144 | typedef struct { | ||
| 145 | unsigned int byte0 : 8; | ||
| 146 | unsigned int byte1 : 8; | ||
| 147 | unsigned int byte2 : 8; | ||
| 148 | unsigned int byte3 : 8; | ||
| 149 | } reg_iop_sw_mpu_rw_bus_clr_mask; | ||
| 150 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 | ||
| 151 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 | ||
| 152 | |||
| 153 | /* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int byte0 : 8; | ||
| 156 | unsigned int byte1 : 8; | ||
| 157 | unsigned int byte2 : 8; | ||
| 158 | unsigned int byte3 : 8; | ||
| 159 | } reg_iop_sw_mpu_rw_bus_set_mask; | ||
| 160 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40 | ||
| 161 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40 | ||
| 162 | |||
| 163 | /* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 164 | typedef struct { | ||
| 165 | unsigned int byte0 : 1; | ||
| 166 | unsigned int byte1 : 1; | ||
| 167 | unsigned int byte2 : 1; | ||
| 168 | unsigned int byte3 : 1; | ||
| 169 | unsigned int dummy1 : 28; | ||
| 170 | } reg_iop_sw_mpu_rw_bus_oe_clr_mask; | ||
| 171 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 | ||
| 172 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 | ||
| 173 | |||
| 174 | /* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 175 | typedef struct { | ||
| 176 | unsigned int byte0 : 1; | ||
| 177 | unsigned int byte1 : 1; | ||
| 178 | unsigned int byte2 : 1; | ||
| 179 | unsigned int byte3 : 1; | ||
| 180 | unsigned int dummy1 : 28; | ||
| 181 | } reg_iop_sw_mpu_rw_bus_oe_set_mask; | ||
| 182 | #define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 | ||
| 183 | #define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 | ||
| 184 | |||
| 185 | /* Register r_bus_in, scope iop_sw_mpu, type r */ | ||
| 186 | typedef unsigned int reg_iop_sw_mpu_r_bus_in; | ||
| 187 | #define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52 | ||
| 188 | |||
| 189 | /* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 190 | typedef struct { | ||
| 191 | unsigned int val : 32; | ||
| 192 | } reg_iop_sw_mpu_rw_gio_clr_mask; | ||
| 193 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 | ||
| 194 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 | ||
| 195 | |||
| 196 | /* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int val : 32; | ||
| 199 | } reg_iop_sw_mpu_rw_gio_set_mask; | ||
| 200 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60 | ||
| 201 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60 | ||
| 202 | |||
| 203 | /* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ | ||
| 204 | typedef struct { | ||
| 205 | unsigned int val : 32; | ||
| 206 | } reg_iop_sw_mpu_rw_gio_oe_clr_mask; | ||
| 207 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 | ||
| 208 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 | ||
| 209 | |||
| 210 | /* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ | ||
| 211 | typedef struct { | ||
| 212 | unsigned int val : 32; | ||
| 213 | } reg_iop_sw_mpu_rw_gio_oe_set_mask; | ||
| 214 | #define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 | ||
| 215 | #define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 | ||
| 216 | |||
| 217 | /* Register r_gio_in, scope iop_sw_mpu, type r */ | ||
| 218 | typedef unsigned int reg_iop_sw_mpu_r_gio_in; | ||
| 219 | #define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72 | ||
| 220 | |||
| 221 | /* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ | ||
| 222 | typedef struct { | ||
| 223 | unsigned int intr0 : 1; | ||
| 224 | unsigned int intr1 : 1; | ||
| 225 | unsigned int intr2 : 1; | ||
| 226 | unsigned int intr3 : 1; | ||
| 227 | unsigned int intr4 : 1; | ||
| 228 | unsigned int intr5 : 1; | ||
| 229 | unsigned int intr6 : 1; | ||
| 230 | unsigned int intr7 : 1; | ||
| 231 | unsigned int intr8 : 1; | ||
| 232 | unsigned int intr9 : 1; | ||
| 233 | unsigned int intr10 : 1; | ||
| 234 | unsigned int intr11 : 1; | ||
| 235 | unsigned int intr12 : 1; | ||
| 236 | unsigned int intr13 : 1; | ||
| 237 | unsigned int intr14 : 1; | ||
| 238 | unsigned int intr15 : 1; | ||
| 239 | unsigned int intr16 : 1; | ||
| 240 | unsigned int intr17 : 1; | ||
| 241 | unsigned int intr18 : 1; | ||
| 242 | unsigned int intr19 : 1; | ||
| 243 | unsigned int intr20 : 1; | ||
| 244 | unsigned int intr21 : 1; | ||
| 245 | unsigned int intr22 : 1; | ||
| 246 | unsigned int intr23 : 1; | ||
| 247 | unsigned int intr24 : 1; | ||
| 248 | unsigned int intr25 : 1; | ||
| 249 | unsigned int intr26 : 1; | ||
| 250 | unsigned int intr27 : 1; | ||
| 251 | unsigned int intr28 : 1; | ||
| 252 | unsigned int intr29 : 1; | ||
| 253 | unsigned int intr30 : 1; | ||
| 254 | unsigned int intr31 : 1; | ||
| 255 | } reg_iop_sw_mpu_rw_cpu_intr; | ||
| 256 | #define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76 | ||
| 257 | #define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76 | ||
| 258 | |||
| 259 | /* Register r_cpu_intr, scope iop_sw_mpu, type r */ | ||
| 260 | typedef struct { | ||
| 261 | unsigned int intr0 : 1; | ||
| 262 | unsigned int intr1 : 1; | ||
| 263 | unsigned int intr2 : 1; | ||
| 264 | unsigned int intr3 : 1; | ||
| 265 | unsigned int intr4 : 1; | ||
| 266 | unsigned int intr5 : 1; | ||
| 267 | unsigned int intr6 : 1; | ||
| 268 | unsigned int intr7 : 1; | ||
| 269 | unsigned int intr8 : 1; | ||
| 270 | unsigned int intr9 : 1; | ||
| 271 | unsigned int intr10 : 1; | ||
| 272 | unsigned int intr11 : 1; | ||
| 273 | unsigned int intr12 : 1; | ||
| 274 | unsigned int intr13 : 1; | ||
| 275 | unsigned int intr14 : 1; | ||
| 276 | unsigned int intr15 : 1; | ||
| 277 | unsigned int intr16 : 1; | ||
| 278 | unsigned int intr17 : 1; | ||
| 279 | unsigned int intr18 : 1; | ||
| 280 | unsigned int intr19 : 1; | ||
| 281 | unsigned int intr20 : 1; | ||
| 282 | unsigned int intr21 : 1; | ||
| 283 | unsigned int intr22 : 1; | ||
| 284 | unsigned int intr23 : 1; | ||
| 285 | unsigned int intr24 : 1; | ||
| 286 | unsigned int intr25 : 1; | ||
| 287 | unsigned int intr26 : 1; | ||
| 288 | unsigned int intr27 : 1; | ||
| 289 | unsigned int intr28 : 1; | ||
| 290 | unsigned int intr29 : 1; | ||
| 291 | unsigned int intr30 : 1; | ||
| 292 | unsigned int intr31 : 1; | ||
| 293 | } reg_iop_sw_mpu_r_cpu_intr; | ||
| 294 | #define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80 | ||
| 295 | |||
| 296 | /* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ | ||
| 297 | typedef struct { | ||
| 298 | unsigned int spu_intr0 : 1; | ||
| 299 | unsigned int trigger_grp0 : 1; | ||
| 300 | unsigned int timer_grp0 : 1; | ||
| 301 | unsigned int fifo_out : 1; | ||
| 302 | unsigned int spu_intr1 : 1; | ||
| 303 | unsigned int trigger_grp1 : 1; | ||
| 304 | unsigned int timer_grp1 : 1; | ||
| 305 | unsigned int fifo_in : 1; | ||
| 306 | unsigned int spu_intr2 : 1; | ||
| 307 | unsigned int trigger_grp2 : 1; | ||
| 308 | unsigned int fifo_out_extra : 1; | ||
| 309 | unsigned int dmc_out : 1; | ||
| 310 | unsigned int spu_intr3 : 1; | ||
| 311 | unsigned int trigger_grp3 : 1; | ||
| 312 | unsigned int fifo_in_extra : 1; | ||
| 313 | unsigned int dmc_in : 1; | ||
| 314 | unsigned int dummy1 : 16; | ||
| 315 | } reg_iop_sw_mpu_rw_intr_grp0_mask; | ||
| 316 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 | ||
| 317 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 | ||
| 318 | |||
| 319 | /* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ | ||
| 320 | typedef struct { | ||
| 321 | unsigned int spu_intr0 : 1; | ||
| 322 | unsigned int dummy1 : 3; | ||
| 323 | unsigned int spu_intr1 : 1; | ||
| 324 | unsigned int dummy2 : 3; | ||
| 325 | unsigned int spu_intr2 : 1; | ||
| 326 | unsigned int dummy3 : 3; | ||
| 327 | unsigned int spu_intr3 : 1; | ||
| 328 | unsigned int dummy4 : 19; | ||
| 329 | } reg_iop_sw_mpu_rw_ack_intr_grp0; | ||
| 330 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 | ||
| 331 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 | ||
| 332 | |||
| 333 | /* Register r_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 334 | typedef struct { | ||
| 335 | unsigned int spu_intr0 : 1; | ||
| 336 | unsigned int trigger_grp0 : 1; | ||
| 337 | unsigned int timer_grp0 : 1; | ||
| 338 | unsigned int fifo_out : 1; | ||
| 339 | unsigned int spu_intr1 : 1; | ||
| 340 | unsigned int trigger_grp1 : 1; | ||
| 341 | unsigned int timer_grp1 : 1; | ||
| 342 | unsigned int fifo_in : 1; | ||
| 343 | unsigned int spu_intr2 : 1; | ||
| 344 | unsigned int trigger_grp2 : 1; | ||
| 345 | unsigned int fifo_out_extra : 1; | ||
| 346 | unsigned int dmc_out : 1; | ||
| 347 | unsigned int spu_intr3 : 1; | ||
| 348 | unsigned int trigger_grp3 : 1; | ||
| 349 | unsigned int fifo_in_extra : 1; | ||
| 350 | unsigned int dmc_in : 1; | ||
| 351 | unsigned int dummy1 : 16; | ||
| 352 | } reg_iop_sw_mpu_r_intr_grp0; | ||
| 353 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92 | ||
| 354 | |||
| 355 | /* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ | ||
| 356 | typedef struct { | ||
| 357 | unsigned int spu_intr0 : 1; | ||
| 358 | unsigned int trigger_grp0 : 1; | ||
| 359 | unsigned int timer_grp0 : 1; | ||
| 360 | unsigned int fifo_out : 1; | ||
| 361 | unsigned int spu_intr1 : 1; | ||
| 362 | unsigned int trigger_grp1 : 1; | ||
| 363 | unsigned int timer_grp1 : 1; | ||
| 364 | unsigned int fifo_in : 1; | ||
| 365 | unsigned int spu_intr2 : 1; | ||
| 366 | unsigned int trigger_grp2 : 1; | ||
| 367 | unsigned int fifo_out_extra : 1; | ||
| 368 | unsigned int dmc_out : 1; | ||
| 369 | unsigned int spu_intr3 : 1; | ||
| 370 | unsigned int trigger_grp3 : 1; | ||
| 371 | unsigned int fifo_in_extra : 1; | ||
| 372 | unsigned int dmc_in : 1; | ||
| 373 | unsigned int dummy1 : 16; | ||
| 374 | } reg_iop_sw_mpu_r_masked_intr_grp0; | ||
| 375 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96 | ||
| 376 | |||
| 377 | /* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ | ||
| 378 | typedef struct { | ||
| 379 | unsigned int spu_intr4 : 1; | ||
| 380 | unsigned int trigger_grp4 : 1; | ||
| 381 | unsigned int fifo_out_extra : 1; | ||
| 382 | unsigned int dmc_out : 1; | ||
| 383 | unsigned int spu_intr5 : 1; | ||
| 384 | unsigned int trigger_grp5 : 1; | ||
| 385 | unsigned int fifo_in_extra : 1; | ||
| 386 | unsigned int dmc_in : 1; | ||
| 387 | unsigned int spu_intr6 : 1; | ||
| 388 | unsigned int trigger_grp6 : 1; | ||
| 389 | unsigned int timer_grp0 : 1; | ||
| 390 | unsigned int fifo_out : 1; | ||
| 391 | unsigned int spu_intr7 : 1; | ||
| 392 | unsigned int trigger_grp7 : 1; | ||
| 393 | unsigned int timer_grp1 : 1; | ||
| 394 | unsigned int fifo_in : 1; | ||
| 395 | unsigned int dummy1 : 16; | ||
| 396 | } reg_iop_sw_mpu_rw_intr_grp1_mask; | ||
| 397 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 | ||
| 398 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 | ||
| 399 | |||
| 400 | /* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ | ||
| 401 | typedef struct { | ||
| 402 | unsigned int spu_intr4 : 1; | ||
| 403 | unsigned int dummy1 : 3; | ||
| 404 | unsigned int spu_intr5 : 1; | ||
| 405 | unsigned int dummy2 : 3; | ||
| 406 | unsigned int spu_intr6 : 1; | ||
| 407 | unsigned int dummy3 : 3; | ||
| 408 | unsigned int spu_intr7 : 1; | ||
| 409 | unsigned int dummy4 : 19; | ||
| 410 | } reg_iop_sw_mpu_rw_ack_intr_grp1; | ||
| 411 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 | ||
| 412 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 | ||
| 413 | |||
| 414 | /* Register r_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 415 | typedef struct { | ||
| 416 | unsigned int spu_intr4 : 1; | ||
| 417 | unsigned int trigger_grp4 : 1; | ||
| 418 | unsigned int fifo_out_extra : 1; | ||
| 419 | unsigned int dmc_out : 1; | ||
| 420 | unsigned int spu_intr5 : 1; | ||
| 421 | unsigned int trigger_grp5 : 1; | ||
| 422 | unsigned int fifo_in_extra : 1; | ||
| 423 | unsigned int dmc_in : 1; | ||
| 424 | unsigned int spu_intr6 : 1; | ||
| 425 | unsigned int trigger_grp6 : 1; | ||
| 426 | unsigned int timer_grp0 : 1; | ||
| 427 | unsigned int fifo_out : 1; | ||
| 428 | unsigned int spu_intr7 : 1; | ||
| 429 | unsigned int trigger_grp7 : 1; | ||
| 430 | unsigned int timer_grp1 : 1; | ||
| 431 | unsigned int fifo_in : 1; | ||
| 432 | unsigned int dummy1 : 16; | ||
| 433 | } reg_iop_sw_mpu_r_intr_grp1; | ||
| 434 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108 | ||
| 435 | |||
| 436 | /* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ | ||
| 437 | typedef struct { | ||
| 438 | unsigned int spu_intr4 : 1; | ||
| 439 | unsigned int trigger_grp4 : 1; | ||
| 440 | unsigned int fifo_out_extra : 1; | ||
| 441 | unsigned int dmc_out : 1; | ||
| 442 | unsigned int spu_intr5 : 1; | ||
| 443 | unsigned int trigger_grp5 : 1; | ||
| 444 | unsigned int fifo_in_extra : 1; | ||
| 445 | unsigned int dmc_in : 1; | ||
| 446 | unsigned int spu_intr6 : 1; | ||
| 447 | unsigned int trigger_grp6 : 1; | ||
| 448 | unsigned int timer_grp0 : 1; | ||
| 449 | unsigned int fifo_out : 1; | ||
| 450 | unsigned int spu_intr7 : 1; | ||
| 451 | unsigned int trigger_grp7 : 1; | ||
| 452 | unsigned int timer_grp1 : 1; | ||
| 453 | unsigned int fifo_in : 1; | ||
| 454 | unsigned int dummy1 : 16; | ||
| 455 | } reg_iop_sw_mpu_r_masked_intr_grp1; | ||
| 456 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112 | ||
| 457 | |||
| 458 | /* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ | ||
| 459 | typedef struct { | ||
| 460 | unsigned int spu_intr8 : 1; | ||
| 461 | unsigned int trigger_grp0 : 1; | ||
| 462 | unsigned int timer_grp0 : 1; | ||
| 463 | unsigned int fifo_out : 1; | ||
| 464 | unsigned int spu_intr9 : 1; | ||
| 465 | unsigned int trigger_grp1 : 1; | ||
| 466 | unsigned int timer_grp1 : 1; | ||
| 467 | unsigned int fifo_in : 1; | ||
| 468 | unsigned int spu_intr10 : 1; | ||
| 469 | unsigned int trigger_grp2 : 1; | ||
| 470 | unsigned int fifo_out_extra : 1; | ||
| 471 | unsigned int dmc_out : 1; | ||
| 472 | unsigned int spu_intr11 : 1; | ||
| 473 | unsigned int trigger_grp3 : 1; | ||
| 474 | unsigned int fifo_in_extra : 1; | ||
| 475 | unsigned int dmc_in : 1; | ||
| 476 | unsigned int dummy1 : 16; | ||
| 477 | } reg_iop_sw_mpu_rw_intr_grp2_mask; | ||
| 478 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 | ||
| 479 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 | ||
| 480 | |||
| 481 | /* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ | ||
| 482 | typedef struct { | ||
| 483 | unsigned int spu_intr8 : 1; | ||
| 484 | unsigned int dummy1 : 3; | ||
| 485 | unsigned int spu_intr9 : 1; | ||
| 486 | unsigned int dummy2 : 3; | ||
| 487 | unsigned int spu_intr10 : 1; | ||
| 488 | unsigned int dummy3 : 3; | ||
| 489 | unsigned int spu_intr11 : 1; | ||
| 490 | unsigned int dummy4 : 19; | ||
| 491 | } reg_iop_sw_mpu_rw_ack_intr_grp2; | ||
| 492 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 | ||
| 493 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 | ||
| 494 | |||
| 495 | /* Register r_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 496 | typedef struct { | ||
| 497 | unsigned int spu_intr8 : 1; | ||
| 498 | unsigned int trigger_grp0 : 1; | ||
| 499 | unsigned int timer_grp0 : 1; | ||
| 500 | unsigned int fifo_out : 1; | ||
| 501 | unsigned int spu_intr9 : 1; | ||
| 502 | unsigned int trigger_grp1 : 1; | ||
| 503 | unsigned int timer_grp1 : 1; | ||
| 504 | unsigned int fifo_in : 1; | ||
| 505 | unsigned int spu_intr10 : 1; | ||
| 506 | unsigned int trigger_grp2 : 1; | ||
| 507 | unsigned int fifo_out_extra : 1; | ||
| 508 | unsigned int dmc_out : 1; | ||
| 509 | unsigned int spu_intr11 : 1; | ||
| 510 | unsigned int trigger_grp3 : 1; | ||
| 511 | unsigned int fifo_in_extra : 1; | ||
| 512 | unsigned int dmc_in : 1; | ||
| 513 | unsigned int dummy1 : 16; | ||
| 514 | } reg_iop_sw_mpu_r_intr_grp2; | ||
| 515 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124 | ||
| 516 | |||
| 517 | /* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ | ||
| 518 | typedef struct { | ||
| 519 | unsigned int spu_intr8 : 1; | ||
| 520 | unsigned int trigger_grp0 : 1; | ||
| 521 | unsigned int timer_grp0 : 1; | ||
| 522 | unsigned int fifo_out : 1; | ||
| 523 | unsigned int spu_intr9 : 1; | ||
| 524 | unsigned int trigger_grp1 : 1; | ||
| 525 | unsigned int timer_grp1 : 1; | ||
| 526 | unsigned int fifo_in : 1; | ||
| 527 | unsigned int spu_intr10 : 1; | ||
| 528 | unsigned int trigger_grp2 : 1; | ||
| 529 | unsigned int fifo_out_extra : 1; | ||
| 530 | unsigned int dmc_out : 1; | ||
| 531 | unsigned int spu_intr11 : 1; | ||
| 532 | unsigned int trigger_grp3 : 1; | ||
| 533 | unsigned int fifo_in_extra : 1; | ||
| 534 | unsigned int dmc_in : 1; | ||
| 535 | unsigned int dummy1 : 16; | ||
| 536 | } reg_iop_sw_mpu_r_masked_intr_grp2; | ||
| 537 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128 | ||
| 538 | |||
| 539 | /* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ | ||
| 540 | typedef struct { | ||
| 541 | unsigned int spu_intr12 : 1; | ||
| 542 | unsigned int trigger_grp4 : 1; | ||
| 543 | unsigned int fifo_out_extra : 1; | ||
| 544 | unsigned int dmc_out : 1; | ||
| 545 | unsigned int spu_intr13 : 1; | ||
| 546 | unsigned int trigger_grp5 : 1; | ||
| 547 | unsigned int fifo_in_extra : 1; | ||
| 548 | unsigned int dmc_in : 1; | ||
| 549 | unsigned int spu_intr14 : 1; | ||
| 550 | unsigned int trigger_grp6 : 1; | ||
| 551 | unsigned int timer_grp0 : 1; | ||
| 552 | unsigned int fifo_out : 1; | ||
| 553 | unsigned int spu_intr15 : 1; | ||
| 554 | unsigned int trigger_grp7 : 1; | ||
| 555 | unsigned int timer_grp1 : 1; | ||
| 556 | unsigned int fifo_in : 1; | ||
| 557 | unsigned int dummy1 : 16; | ||
| 558 | } reg_iop_sw_mpu_rw_intr_grp3_mask; | ||
| 559 | #define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 | ||
| 560 | #define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 | ||
| 561 | |||
| 562 | /* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ | ||
| 563 | typedef struct { | ||
| 564 | unsigned int spu_intr12 : 1; | ||
| 565 | unsigned int dummy1 : 3; | ||
| 566 | unsigned int spu_intr13 : 1; | ||
| 567 | unsigned int dummy2 : 3; | ||
| 568 | unsigned int spu_intr14 : 1; | ||
| 569 | unsigned int dummy3 : 3; | ||
| 570 | unsigned int spu_intr15 : 1; | ||
| 571 | unsigned int dummy4 : 19; | ||
| 572 | } reg_iop_sw_mpu_rw_ack_intr_grp3; | ||
| 573 | #define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 | ||
| 574 | #define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 | ||
| 575 | |||
| 576 | /* Register r_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 577 | typedef struct { | ||
| 578 | unsigned int spu_intr12 : 1; | ||
| 579 | unsigned int trigger_grp4 : 1; | ||
| 580 | unsigned int fifo_out_extra : 1; | ||
| 581 | unsigned int dmc_out : 1; | ||
| 582 | unsigned int spu_intr13 : 1; | ||
| 583 | unsigned int trigger_grp5 : 1; | ||
| 584 | unsigned int fifo_in_extra : 1; | ||
| 585 | unsigned int dmc_in : 1; | ||
| 586 | unsigned int spu_intr14 : 1; | ||
| 587 | unsigned int trigger_grp6 : 1; | ||
| 588 | unsigned int timer_grp0 : 1; | ||
| 589 | unsigned int fifo_out : 1; | ||
| 590 | unsigned int spu_intr15 : 1; | ||
| 591 | unsigned int trigger_grp7 : 1; | ||
| 592 | unsigned int timer_grp1 : 1; | ||
| 593 | unsigned int fifo_in : 1; | ||
| 594 | unsigned int dummy1 : 16; | ||
| 595 | } reg_iop_sw_mpu_r_intr_grp3; | ||
| 596 | #define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140 | ||
| 597 | |||
| 598 | /* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ | ||
| 599 | typedef struct { | ||
| 600 | unsigned int spu_intr12 : 1; | ||
| 601 | unsigned int trigger_grp4 : 1; | ||
| 602 | unsigned int fifo_out_extra : 1; | ||
| 603 | unsigned int dmc_out : 1; | ||
| 604 | unsigned int spu_intr13 : 1; | ||
| 605 | unsigned int trigger_grp5 : 1; | ||
| 606 | unsigned int fifo_in_extra : 1; | ||
| 607 | unsigned int dmc_in : 1; | ||
| 608 | unsigned int spu_intr14 : 1; | ||
| 609 | unsigned int trigger_grp6 : 1; | ||
| 610 | unsigned int timer_grp0 : 1; | ||
| 611 | unsigned int fifo_out : 1; | ||
| 612 | unsigned int spu_intr15 : 1; | ||
| 613 | unsigned int trigger_grp7 : 1; | ||
| 614 | unsigned int timer_grp1 : 1; | ||
| 615 | unsigned int fifo_in : 1; | ||
| 616 | unsigned int dummy1 : 16; | ||
| 617 | } reg_iop_sw_mpu_r_masked_intr_grp3; | ||
| 618 | #define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144 | ||
| 619 | |||
| 620 | |||
| 621 | /* Constants */ | ||
| 622 | enum { | ||
| 623 | regk_iop_sw_mpu_copy = 0x00000000, | ||
| 624 | regk_iop_sw_mpu_cpu = 0x00000000, | ||
| 625 | regk_iop_sw_mpu_mpu = 0x00000001, | ||
| 626 | regk_iop_sw_mpu_no = 0x00000000, | ||
| 627 | regk_iop_sw_mpu_nop = 0x00000000, | ||
| 628 | regk_iop_sw_mpu_rd = 0x00000002, | ||
| 629 | regk_iop_sw_mpu_reg_copy = 0x00000001, | ||
| 630 | regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000, | ||
| 631 | regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, | ||
| 632 | regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, | ||
| 633 | regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, | ||
| 634 | regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, | ||
| 635 | regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
| 636 | regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, | ||
| 637 | regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, | ||
| 638 | regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, | ||
| 639 | regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, | ||
| 640 | regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, | ||
| 641 | regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, | ||
| 642 | regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, | ||
| 643 | regk_iop_sw_mpu_set = 0x00000001, | ||
| 644 | regk_iop_sw_mpu_spu = 0x00000002, | ||
| 645 | regk_iop_sw_mpu_wr = 0x00000003, | ||
| 646 | regk_iop_sw_mpu_yes = 0x00000001 | ||
| 647 | }; | ||
| 648 | #endif /* __iop_sw_mpu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h new file mode 100644 index 000000000000..c8560b865a1a --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_sw_spu_defs.h | |||
| @@ -0,0 +1,441 @@ | |||
| 1 | #ifndef __iop_sw_spu_defs_h | ||
| 2 | #define __iop_sw_spu_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_sw_spu.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_sw_spu */ | ||
| 83 | |||
| 84 | /* Register r_mpu_trace, scope iop_sw_spu, type r */ | ||
| 85 | typedef unsigned int reg_iop_sw_spu_r_mpu_trace; | ||
| 86 | #define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 | ||
| 87 | |||
| 88 | /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ | ||
| 89 | typedef struct { | ||
| 90 | unsigned int keep_owner : 1; | ||
| 91 | unsigned int cmd : 2; | ||
| 92 | unsigned int size : 3; | ||
| 93 | unsigned int wr_spu_mem : 1; | ||
| 94 | unsigned int dummy1 : 25; | ||
| 95 | } reg_iop_sw_spu_rw_mc_ctrl; | ||
| 96 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 | ||
| 97 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 | ||
| 98 | |||
| 99 | /* Register rw_mc_data, scope iop_sw_spu, type rw */ | ||
| 100 | typedef struct { | ||
| 101 | unsigned int val : 32; | ||
| 102 | } reg_iop_sw_spu_rw_mc_data; | ||
| 103 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 | ||
| 104 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 | ||
| 105 | |||
| 106 | /* Register rw_mc_addr, scope iop_sw_spu, type rw */ | ||
| 107 | typedef unsigned int reg_iop_sw_spu_rw_mc_addr; | ||
| 108 | #define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 | ||
| 109 | #define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 | ||
| 110 | |||
| 111 | /* Register rs_mc_data, scope iop_sw_spu, type rs */ | ||
| 112 | typedef unsigned int reg_iop_sw_spu_rs_mc_data; | ||
| 113 | #define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 | ||
| 114 | |||
| 115 | /* Register r_mc_data, scope iop_sw_spu, type r */ | ||
| 116 | typedef unsigned int reg_iop_sw_spu_r_mc_data; | ||
| 117 | #define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 | ||
| 118 | |||
| 119 | /* Register r_mc_stat, scope iop_sw_spu, type r */ | ||
| 120 | typedef struct { | ||
| 121 | unsigned int busy_cpu : 1; | ||
| 122 | unsigned int busy_mpu : 1; | ||
| 123 | unsigned int busy_spu : 1; | ||
| 124 | unsigned int owned_by_cpu : 1; | ||
| 125 | unsigned int owned_by_mpu : 1; | ||
| 126 | unsigned int owned_by_spu : 1; | ||
| 127 | unsigned int dummy1 : 26; | ||
| 128 | } reg_iop_sw_spu_r_mc_stat; | ||
| 129 | #define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 | ||
| 130 | |||
| 131 | /* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int byte0 : 8; | ||
| 134 | unsigned int byte1 : 8; | ||
| 135 | unsigned int byte2 : 8; | ||
| 136 | unsigned int byte3 : 8; | ||
| 137 | } reg_iop_sw_spu_rw_bus_clr_mask; | ||
| 138 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 | ||
| 139 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 | ||
| 140 | |||
| 141 | /* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ | ||
| 142 | typedef struct { | ||
| 143 | unsigned int byte0 : 8; | ||
| 144 | unsigned int byte1 : 8; | ||
| 145 | unsigned int byte2 : 8; | ||
| 146 | unsigned int byte3 : 8; | ||
| 147 | } reg_iop_sw_spu_rw_bus_set_mask; | ||
| 148 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 | ||
| 149 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 | ||
| 150 | |||
| 151 | /* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 152 | typedef struct { | ||
| 153 | unsigned int byte0 : 1; | ||
| 154 | unsigned int byte1 : 1; | ||
| 155 | unsigned int byte2 : 1; | ||
| 156 | unsigned int byte3 : 1; | ||
| 157 | unsigned int dummy1 : 28; | ||
| 158 | } reg_iop_sw_spu_rw_bus_oe_clr_mask; | ||
| 159 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 | ||
| 160 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 | ||
| 161 | |||
| 162 | /* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int byte0 : 1; | ||
| 165 | unsigned int byte1 : 1; | ||
| 166 | unsigned int byte2 : 1; | ||
| 167 | unsigned int byte3 : 1; | ||
| 168 | unsigned int dummy1 : 28; | ||
| 169 | } reg_iop_sw_spu_rw_bus_oe_set_mask; | ||
| 170 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 | ||
| 171 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 | ||
| 172 | |||
| 173 | /* Register r_bus_in, scope iop_sw_spu, type r */ | ||
| 174 | typedef unsigned int reg_iop_sw_spu_r_bus_in; | ||
| 175 | #define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 | ||
| 176 | |||
| 177 | /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int val : 32; | ||
| 180 | } reg_iop_sw_spu_rw_gio_clr_mask; | ||
| 181 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 | ||
| 182 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 | ||
| 183 | |||
| 184 | /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ | ||
| 185 | typedef struct { | ||
| 186 | unsigned int val : 32; | ||
| 187 | } reg_iop_sw_spu_rw_gio_set_mask; | ||
| 188 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 | ||
| 189 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 | ||
| 190 | |||
| 191 | /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int val : 32; | ||
| 194 | } reg_iop_sw_spu_rw_gio_oe_clr_mask; | ||
| 195 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 | ||
| 196 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 | ||
| 197 | |||
| 198 | /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ | ||
| 199 | typedef struct { | ||
| 200 | unsigned int val : 32; | ||
| 201 | } reg_iop_sw_spu_rw_gio_oe_set_mask; | ||
| 202 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 | ||
| 203 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 | ||
| 204 | |||
| 205 | /* Register r_gio_in, scope iop_sw_spu, type r */ | ||
| 206 | typedef unsigned int reg_iop_sw_spu_r_gio_in; | ||
| 207 | #define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 | ||
| 208 | |||
| 209 | /* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 210 | typedef struct { | ||
| 211 | unsigned int byte0 : 8; | ||
| 212 | unsigned int byte1 : 8; | ||
| 213 | unsigned int dummy1 : 16; | ||
| 214 | } reg_iop_sw_spu_rw_bus_clr_mask_lo; | ||
| 215 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 | ||
| 216 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 | ||
| 217 | |||
| 218 | /* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 219 | typedef struct { | ||
| 220 | unsigned int byte2 : 8; | ||
| 221 | unsigned int byte3 : 8; | ||
| 222 | unsigned int dummy1 : 16; | ||
| 223 | } reg_iop_sw_spu_rw_bus_clr_mask_hi; | ||
| 224 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 | ||
| 225 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 | ||
| 226 | |||
| 227 | /* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 228 | typedef struct { | ||
| 229 | unsigned int byte0 : 8; | ||
| 230 | unsigned int byte1 : 8; | ||
| 231 | unsigned int dummy1 : 16; | ||
| 232 | } reg_iop_sw_spu_rw_bus_set_mask_lo; | ||
| 233 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 | ||
| 234 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 | ||
| 235 | |||
| 236 | /* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int byte2 : 8; | ||
| 239 | unsigned int byte3 : 8; | ||
| 240 | unsigned int dummy1 : 16; | ||
| 241 | } reg_iop_sw_spu_rw_bus_set_mask_hi; | ||
| 242 | #define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 | ||
| 243 | #define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 | ||
| 244 | |||
| 245 | /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 246 | typedef struct { | ||
| 247 | unsigned int val : 16; | ||
| 248 | unsigned int dummy1 : 16; | ||
| 249 | } reg_iop_sw_spu_rw_gio_clr_mask_lo; | ||
| 250 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 | ||
| 251 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 | ||
| 252 | |||
| 253 | /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 254 | typedef struct { | ||
| 255 | unsigned int val : 16; | ||
| 256 | unsigned int dummy1 : 16; | ||
| 257 | } reg_iop_sw_spu_rw_gio_clr_mask_hi; | ||
| 258 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 | ||
| 259 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 | ||
| 260 | |||
| 261 | /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 262 | typedef struct { | ||
| 263 | unsigned int val : 16; | ||
| 264 | unsigned int dummy1 : 16; | ||
| 265 | } reg_iop_sw_spu_rw_gio_set_mask_lo; | ||
| 266 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 | ||
| 267 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 | ||
| 268 | |||
| 269 | /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 270 | typedef struct { | ||
| 271 | unsigned int val : 16; | ||
| 272 | unsigned int dummy1 : 16; | ||
| 273 | } reg_iop_sw_spu_rw_gio_set_mask_hi; | ||
| 274 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 | ||
| 275 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 | ||
| 276 | |||
| 277 | /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ | ||
| 278 | typedef struct { | ||
| 279 | unsigned int val : 16; | ||
| 280 | unsigned int dummy1 : 16; | ||
| 281 | } reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; | ||
| 282 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 | ||
| 283 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 | ||
| 284 | |||
| 285 | /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ | ||
| 286 | typedef struct { | ||
| 287 | unsigned int val : 16; | ||
| 288 | unsigned int dummy1 : 16; | ||
| 289 | } reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; | ||
| 290 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 | ||
| 291 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 | ||
| 292 | |||
| 293 | /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ | ||
| 294 | typedef struct { | ||
| 295 | unsigned int val : 16; | ||
| 296 | unsigned int dummy1 : 16; | ||
| 297 | } reg_iop_sw_spu_rw_gio_oe_set_mask_lo; | ||
| 298 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 | ||
| 299 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 | ||
| 300 | |||
| 301 | /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ | ||
| 302 | typedef struct { | ||
| 303 | unsigned int val : 16; | ||
| 304 | unsigned int dummy1 : 16; | ||
| 305 | } reg_iop_sw_spu_rw_gio_oe_set_mask_hi; | ||
| 306 | #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 | ||
| 307 | #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 | ||
| 308 | |||
| 309 | /* Register rw_cpu_intr, scope iop_sw_spu, type rw */ | ||
| 310 | typedef struct { | ||
| 311 | unsigned int intr0 : 1; | ||
| 312 | unsigned int intr1 : 1; | ||
| 313 | unsigned int intr2 : 1; | ||
| 314 | unsigned int intr3 : 1; | ||
| 315 | unsigned int intr4 : 1; | ||
| 316 | unsigned int intr5 : 1; | ||
| 317 | unsigned int intr6 : 1; | ||
| 318 | unsigned int intr7 : 1; | ||
| 319 | unsigned int intr8 : 1; | ||
| 320 | unsigned int intr9 : 1; | ||
| 321 | unsigned int intr10 : 1; | ||
| 322 | unsigned int intr11 : 1; | ||
| 323 | unsigned int intr12 : 1; | ||
| 324 | unsigned int intr13 : 1; | ||
| 325 | unsigned int intr14 : 1; | ||
| 326 | unsigned int intr15 : 1; | ||
| 327 | unsigned int dummy1 : 16; | ||
| 328 | } reg_iop_sw_spu_rw_cpu_intr; | ||
| 329 | #define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 | ||
| 330 | #define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 | ||
| 331 | |||
| 332 | /* Register r_cpu_intr, scope iop_sw_spu, type r */ | ||
| 333 | typedef struct { | ||
| 334 | unsigned int intr0 : 1; | ||
| 335 | unsigned int intr1 : 1; | ||
| 336 | unsigned int intr2 : 1; | ||
| 337 | unsigned int intr3 : 1; | ||
| 338 | unsigned int intr4 : 1; | ||
| 339 | unsigned int intr5 : 1; | ||
| 340 | unsigned int intr6 : 1; | ||
| 341 | unsigned int intr7 : 1; | ||
| 342 | unsigned int intr8 : 1; | ||
| 343 | unsigned int intr9 : 1; | ||
| 344 | unsigned int intr10 : 1; | ||
| 345 | unsigned int intr11 : 1; | ||
| 346 | unsigned int intr12 : 1; | ||
| 347 | unsigned int intr13 : 1; | ||
| 348 | unsigned int intr14 : 1; | ||
| 349 | unsigned int intr15 : 1; | ||
| 350 | unsigned int dummy1 : 16; | ||
| 351 | } reg_iop_sw_spu_r_cpu_intr; | ||
| 352 | #define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 | ||
| 353 | |||
| 354 | /* Register r_hw_intr, scope iop_sw_spu, type r */ | ||
| 355 | typedef struct { | ||
| 356 | unsigned int trigger_grp0 : 1; | ||
| 357 | unsigned int trigger_grp1 : 1; | ||
| 358 | unsigned int trigger_grp2 : 1; | ||
| 359 | unsigned int trigger_grp3 : 1; | ||
| 360 | unsigned int trigger_grp4 : 1; | ||
| 361 | unsigned int trigger_grp5 : 1; | ||
| 362 | unsigned int trigger_grp6 : 1; | ||
| 363 | unsigned int trigger_grp7 : 1; | ||
| 364 | unsigned int timer_grp0 : 1; | ||
| 365 | unsigned int timer_grp1 : 1; | ||
| 366 | unsigned int fifo_out : 1; | ||
| 367 | unsigned int fifo_out_extra : 1; | ||
| 368 | unsigned int fifo_in : 1; | ||
| 369 | unsigned int fifo_in_extra : 1; | ||
| 370 | unsigned int dmc_out : 1; | ||
| 371 | unsigned int dmc_in : 1; | ||
| 372 | unsigned int dummy1 : 16; | ||
| 373 | } reg_iop_sw_spu_r_hw_intr; | ||
| 374 | #define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 | ||
| 375 | |||
| 376 | /* Register rw_mpu_intr, scope iop_sw_spu, type rw */ | ||
| 377 | typedef struct { | ||
| 378 | unsigned int intr0 : 1; | ||
| 379 | unsigned int intr1 : 1; | ||
| 380 | unsigned int intr2 : 1; | ||
| 381 | unsigned int intr3 : 1; | ||
| 382 | unsigned int intr4 : 1; | ||
| 383 | unsigned int intr5 : 1; | ||
| 384 | unsigned int intr6 : 1; | ||
| 385 | unsigned int intr7 : 1; | ||
| 386 | unsigned int intr8 : 1; | ||
| 387 | unsigned int intr9 : 1; | ||
| 388 | unsigned int intr10 : 1; | ||
| 389 | unsigned int intr11 : 1; | ||
| 390 | unsigned int intr12 : 1; | ||
| 391 | unsigned int intr13 : 1; | ||
| 392 | unsigned int intr14 : 1; | ||
| 393 | unsigned int intr15 : 1; | ||
| 394 | unsigned int dummy1 : 16; | ||
| 395 | } reg_iop_sw_spu_rw_mpu_intr; | ||
| 396 | #define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 | ||
| 397 | #define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 | ||
| 398 | |||
| 399 | /* Register r_mpu_intr, scope iop_sw_spu, type r */ | ||
| 400 | typedef struct { | ||
| 401 | unsigned int intr0 : 1; | ||
| 402 | unsigned int intr1 : 1; | ||
| 403 | unsigned int intr2 : 1; | ||
| 404 | unsigned int intr3 : 1; | ||
| 405 | unsigned int intr4 : 1; | ||
| 406 | unsigned int intr5 : 1; | ||
| 407 | unsigned int intr6 : 1; | ||
| 408 | unsigned int intr7 : 1; | ||
| 409 | unsigned int intr8 : 1; | ||
| 410 | unsigned int intr9 : 1; | ||
| 411 | unsigned int intr10 : 1; | ||
| 412 | unsigned int intr11 : 1; | ||
| 413 | unsigned int intr12 : 1; | ||
| 414 | unsigned int intr13 : 1; | ||
| 415 | unsigned int intr14 : 1; | ||
| 416 | unsigned int intr15 : 1; | ||
| 417 | unsigned int dummy1 : 16; | ||
| 418 | } reg_iop_sw_spu_r_mpu_intr; | ||
| 419 | #define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 | ||
| 420 | |||
| 421 | |||
| 422 | /* Constants */ | ||
| 423 | enum { | ||
| 424 | regk_iop_sw_spu_copy = 0x00000000, | ||
| 425 | regk_iop_sw_spu_no = 0x00000000, | ||
| 426 | regk_iop_sw_spu_nop = 0x00000000, | ||
| 427 | regk_iop_sw_spu_rd = 0x00000002, | ||
| 428 | regk_iop_sw_spu_reg_copy = 0x00000001, | ||
| 429 | regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, | ||
| 430 | regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, | ||
| 431 | regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, | ||
| 432 | regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, | ||
| 433 | regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, | ||
| 434 | regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, | ||
| 435 | regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, | ||
| 436 | regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, | ||
| 437 | regk_iop_sw_spu_set = 0x00000001, | ||
| 438 | regk_iop_sw_spu_wr = 0x00000003, | ||
| 439 | regk_iop_sw_spu_yes = 0x00000001 | ||
| 440 | }; | ||
| 441 | #endif /* __iop_sw_spu_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h new file mode 100644 index 000000000000..20de425e652b --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/iop/iop_version_defs.h | |||
| @@ -0,0 +1,96 @@ | |||
| 1 | #ifndef __iop_version_defs_h | ||
| 2 | #define __iop_version_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: iop_version.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope iop_version */ | ||
| 83 | |||
| 84 | /* Register r_version, scope iop_version, type r */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int nr : 8; | ||
| 87 | unsigned int dummy1 : 24; | ||
| 88 | } reg_iop_version_r_version; | ||
| 89 | #define REG_RD_ADDR_iop_version_r_version 0 | ||
| 90 | |||
| 91 | |||
| 92 | /* Constants */ | ||
| 93 | enum { | ||
| 94 | regk_iop_version_v2_0 = 0x00000002 | ||
| 95 | }; | ||
| 96 | #endif /* __iop_version_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h new file mode 100644 index 000000000000..243ac3c882cb --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/l2cache_defs.h | |||
| @@ -0,0 +1,142 @@ | |||
| 1 | #ifndef __l2cache_defs_h | ||
| 2 | #define __l2cache_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: l2cache.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope l2cache */ | ||
| 83 | |||
| 84 | /* Register rw_cfg, scope l2cache, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int en : 1; | ||
| 87 | unsigned int dummy1 : 31; | ||
| 88 | } reg_l2cache_rw_cfg; | ||
| 89 | #define REG_RD_ADDR_l2cache_rw_cfg 0 | ||
| 90 | #define REG_WR_ADDR_l2cache_rw_cfg 0 | ||
| 91 | |||
| 92 | /* Register rw_ctrl, scope l2cache, type rw */ | ||
| 93 | typedef struct { | ||
| 94 | unsigned int dummy1 : 7; | ||
| 95 | unsigned int cbase : 9; | ||
| 96 | unsigned int dummy2 : 4; | ||
| 97 | unsigned int csize : 10; | ||
| 98 | unsigned int dummy3 : 2; | ||
| 99 | } reg_l2cache_rw_ctrl; | ||
| 100 | #define REG_RD_ADDR_l2cache_rw_ctrl 4 | ||
| 101 | #define REG_WR_ADDR_l2cache_rw_ctrl 4 | ||
| 102 | |||
| 103 | /* Register rw_idxop, scope l2cache, type rw */ | ||
| 104 | typedef struct { | ||
| 105 | unsigned int idx : 10; | ||
| 106 | unsigned int dummy1 : 14; | ||
| 107 | unsigned int way : 3; | ||
| 108 | unsigned int dummy2 : 2; | ||
| 109 | unsigned int cmd : 3; | ||
| 110 | } reg_l2cache_rw_idxop; | ||
| 111 | #define REG_RD_ADDR_l2cache_rw_idxop 8 | ||
| 112 | #define REG_WR_ADDR_l2cache_rw_idxop 8 | ||
| 113 | |||
| 114 | /* Register rw_addrop_addr, scope l2cache, type rw */ | ||
| 115 | typedef struct { | ||
| 116 | unsigned int addr : 32; | ||
| 117 | } reg_l2cache_rw_addrop_addr; | ||
| 118 | #define REG_RD_ADDR_l2cache_rw_addrop_addr 12 | ||
| 119 | #define REG_WR_ADDR_l2cache_rw_addrop_addr 12 | ||
| 120 | |||
| 121 | /* Register rw_addrop_ctrl, scope l2cache, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int size : 16; | ||
| 124 | unsigned int dummy1 : 13; | ||
| 125 | unsigned int cmd : 3; | ||
| 126 | } reg_l2cache_rw_addrop_ctrl; | ||
| 127 | #define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16 | ||
| 128 | #define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16 | ||
| 129 | |||
| 130 | |||
| 131 | /* Constants */ | ||
| 132 | enum { | ||
| 133 | regk_l2cache_flush = 0x00000001, | ||
| 134 | regk_l2cache_no = 0x00000000, | ||
| 135 | regk_l2cache_rw_addrop_addr_default = 0x00000000, | ||
| 136 | regk_l2cache_rw_addrop_ctrl_default = 0x00000000, | ||
| 137 | regk_l2cache_rw_cfg_default = 0x00000000, | ||
| 138 | regk_l2cache_rw_ctrl_default = 0x00000000, | ||
| 139 | regk_l2cache_rw_idxop_default = 0x00000000, | ||
| 140 | regk_l2cache_yes = 0x00000001 | ||
| 141 | }; | ||
| 142 | #endif /* __l2cache_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h new file mode 100644 index 000000000000..c0e7628cbf7d --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_bar_defs.h | |||
| @@ -0,0 +1,482 @@ | |||
| 1 | #ifndef __marb_bar_defs_h | ||
| 2 | #define __marb_bar_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: marb_bar.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope marb_bar */ | ||
| 83 | |||
| 84 | #define STRIDE_marb_bar_rw_ddr2_slots 4 | ||
| 85 | /* Register rw_ddr2_slots, scope marb_bar, type rw */ | ||
| 86 | typedef struct { | ||
| 87 | unsigned int owner : 4; | ||
| 88 | unsigned int dummy1 : 28; | ||
| 89 | } reg_marb_bar_rw_ddr2_slots; | ||
| 90 | #define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0 | ||
| 91 | #define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0 | ||
| 92 | |||
| 93 | /* Register rw_h264_rd_burst, scope marb_bar, type rw */ | ||
| 94 | typedef struct { | ||
| 95 | unsigned int ddr2_bsize : 2; | ||
| 96 | unsigned int dummy1 : 30; | ||
| 97 | } reg_marb_bar_rw_h264_rd_burst; | ||
| 98 | #define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256 | ||
| 99 | #define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256 | ||
| 100 | |||
| 101 | /* Register rw_h264_wr_burst, scope marb_bar, type rw */ | ||
| 102 | typedef struct { | ||
| 103 | unsigned int ddr2_bsize : 2; | ||
| 104 | unsigned int dummy1 : 30; | ||
| 105 | } reg_marb_bar_rw_h264_wr_burst; | ||
| 106 | #define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260 | ||
| 107 | #define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260 | ||
| 108 | |||
| 109 | /* Register rw_ccd_burst, scope marb_bar, type rw */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned int ddr2_bsize : 2; | ||
| 112 | unsigned int dummy1 : 30; | ||
| 113 | } reg_marb_bar_rw_ccd_burst; | ||
| 114 | #define REG_RD_ADDR_marb_bar_rw_ccd_burst 264 | ||
| 115 | #define REG_WR_ADDR_marb_bar_rw_ccd_burst 264 | ||
| 116 | |||
| 117 | /* Register rw_vin_wr_burst, scope marb_bar, type rw */ | ||
| 118 | typedef struct { | ||
| 119 | unsigned int ddr2_bsize : 2; | ||
| 120 | unsigned int dummy1 : 30; | ||
| 121 | } reg_marb_bar_rw_vin_wr_burst; | ||
| 122 | #define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268 | ||
| 123 | #define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268 | ||
| 124 | |||
| 125 | /* Register rw_vin_rd_burst, scope marb_bar, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int ddr2_bsize : 2; | ||
| 128 | unsigned int dummy1 : 30; | ||
| 129 | } reg_marb_bar_rw_vin_rd_burst; | ||
| 130 | #define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272 | ||
| 131 | #define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272 | ||
| 132 | |||
| 133 | /* Register rw_sclr_rd_burst, scope marb_bar, type rw */ | ||
| 134 | typedef struct { | ||
| 135 | unsigned int ddr2_bsize : 2; | ||
| 136 | unsigned int dummy1 : 30; | ||
| 137 | } reg_marb_bar_rw_sclr_rd_burst; | ||
| 138 | #define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276 | ||
| 139 | #define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276 | ||
| 140 | |||
| 141 | /* Register rw_vout_burst, scope marb_bar, type rw */ | ||
| 142 | typedef struct { | ||
| 143 | unsigned int ddr2_bsize : 2; | ||
| 144 | unsigned int dummy1 : 30; | ||
| 145 | } reg_marb_bar_rw_vout_burst; | ||
| 146 | #define REG_RD_ADDR_marb_bar_rw_vout_burst 280 | ||
| 147 | #define REG_WR_ADDR_marb_bar_rw_vout_burst 280 | ||
| 148 | |||
| 149 | /* Register rw_sclr_fifo_burst, scope marb_bar, type rw */ | ||
| 150 | typedef struct { | ||
| 151 | unsigned int ddr2_bsize : 2; | ||
| 152 | unsigned int dummy1 : 30; | ||
| 153 | } reg_marb_bar_rw_sclr_fifo_burst; | ||
| 154 | #define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284 | ||
| 155 | #define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284 | ||
| 156 | |||
| 157 | /* Register rw_l2cache_burst, scope marb_bar, type rw */ | ||
| 158 | typedef struct { | ||
| 159 | unsigned int ddr2_bsize : 2; | ||
| 160 | unsigned int dummy1 : 30; | ||
| 161 | } reg_marb_bar_rw_l2cache_burst; | ||
| 162 | #define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288 | ||
| 163 | #define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288 | ||
| 164 | |||
| 165 | /* Register rw_intr_mask, scope marb_bar, type rw */ | ||
| 166 | typedef struct { | ||
| 167 | unsigned int bp0 : 1; | ||
| 168 | unsigned int bp1 : 1; | ||
| 169 | unsigned int bp2 : 1; | ||
| 170 | unsigned int bp3 : 1; | ||
| 171 | unsigned int dummy1 : 28; | ||
| 172 | } reg_marb_bar_rw_intr_mask; | ||
| 173 | #define REG_RD_ADDR_marb_bar_rw_intr_mask 292 | ||
| 174 | #define REG_WR_ADDR_marb_bar_rw_intr_mask 292 | ||
| 175 | |||
| 176 | /* Register rw_ack_intr, scope marb_bar, type rw */ | ||
| 177 | typedef struct { | ||
| 178 | unsigned int bp0 : 1; | ||
| 179 | unsigned int bp1 : 1; | ||
| 180 | unsigned int bp2 : 1; | ||
| 181 | unsigned int bp3 : 1; | ||
| 182 | unsigned int dummy1 : 28; | ||
| 183 | } reg_marb_bar_rw_ack_intr; | ||
| 184 | #define REG_RD_ADDR_marb_bar_rw_ack_intr 296 | ||
| 185 | #define REG_WR_ADDR_marb_bar_rw_ack_intr 296 | ||
| 186 | |||
| 187 | /* Register r_intr, scope marb_bar, type r */ | ||
| 188 | typedef struct { | ||
| 189 | unsigned int bp0 : 1; | ||
| 190 | unsigned int bp1 : 1; | ||
| 191 | unsigned int bp2 : 1; | ||
| 192 | unsigned int bp3 : 1; | ||
| 193 | unsigned int dummy1 : 28; | ||
| 194 | } reg_marb_bar_r_intr; | ||
| 195 | #define REG_RD_ADDR_marb_bar_r_intr 300 | ||
| 196 | |||
| 197 | /* Register r_masked_intr, scope marb_bar, type r */ | ||
| 198 | typedef struct { | ||
| 199 | unsigned int bp0 : 1; | ||
| 200 | unsigned int bp1 : 1; | ||
| 201 | unsigned int bp2 : 1; | ||
| 202 | unsigned int bp3 : 1; | ||
| 203 | unsigned int dummy1 : 28; | ||
| 204 | } reg_marb_bar_r_masked_intr; | ||
| 205 | #define REG_RD_ADDR_marb_bar_r_masked_intr 304 | ||
| 206 | |||
| 207 | /* Register rw_stop_mask, scope marb_bar, type rw */ | ||
| 208 | typedef struct { | ||
| 209 | unsigned int h264_rd : 1; | ||
| 210 | unsigned int h264_wr : 1; | ||
| 211 | unsigned int ccd : 1; | ||
| 212 | unsigned int vin_wr : 1; | ||
| 213 | unsigned int vin_rd : 1; | ||
| 214 | unsigned int sclr_rd : 1; | ||
| 215 | unsigned int vout : 1; | ||
| 216 | unsigned int sclr_fifo : 1; | ||
| 217 | unsigned int l2cache : 1; | ||
| 218 | unsigned int dummy1 : 23; | ||
| 219 | } reg_marb_bar_rw_stop_mask; | ||
| 220 | #define REG_RD_ADDR_marb_bar_rw_stop_mask 308 | ||
| 221 | #define REG_WR_ADDR_marb_bar_rw_stop_mask 308 | ||
| 222 | |||
| 223 | /* Register r_stopped, scope marb_bar, type r */ | ||
| 224 | typedef struct { | ||
| 225 | unsigned int h264_rd : 1; | ||
| 226 | unsigned int h264_wr : 1; | ||
| 227 | unsigned int ccd : 1; | ||
| 228 | unsigned int vin_wr : 1; | ||
| 229 | unsigned int vin_rd : 1; | ||
| 230 | unsigned int sclr_rd : 1; | ||
| 231 | unsigned int vout : 1; | ||
| 232 | unsigned int sclr_fifo : 1; | ||
| 233 | unsigned int l2cache : 1; | ||
| 234 | unsigned int dummy1 : 23; | ||
| 235 | } reg_marb_bar_r_stopped; | ||
| 236 | #define REG_RD_ADDR_marb_bar_r_stopped 312 | ||
| 237 | |||
| 238 | /* Register rw_no_snoop, scope marb_bar, type rw */ | ||
| 239 | typedef struct { | ||
| 240 | unsigned int h264_rd : 1; | ||
| 241 | unsigned int h264_wr : 1; | ||
| 242 | unsigned int ccd : 1; | ||
| 243 | unsigned int vin_wr : 1; | ||
| 244 | unsigned int vin_rd : 1; | ||
| 245 | unsigned int sclr_rd : 1; | ||
| 246 | unsigned int vout : 1; | ||
| 247 | unsigned int sclr_fifo : 1; | ||
| 248 | unsigned int l2cache : 1; | ||
| 249 | unsigned int dummy1 : 23; | ||
| 250 | } reg_marb_bar_rw_no_snoop; | ||
| 251 | #define REG_RD_ADDR_marb_bar_rw_no_snoop 576 | ||
| 252 | #define REG_WR_ADDR_marb_bar_rw_no_snoop 576 | ||
| 253 | |||
| 254 | |||
| 255 | /* Constants */ | ||
| 256 | enum { | ||
| 257 | regk_marb_bar_ccd = 0x00000002, | ||
| 258 | regk_marb_bar_h264_rd = 0x00000000, | ||
| 259 | regk_marb_bar_h264_wr = 0x00000001, | ||
| 260 | regk_marb_bar_l2cache = 0x00000008, | ||
| 261 | regk_marb_bar_no = 0x00000000, | ||
| 262 | regk_marb_bar_r_stopped_default = 0x00000000, | ||
| 263 | regk_marb_bar_rw_ccd_burst_default = 0x00000000, | ||
| 264 | regk_marb_bar_rw_ddr2_slots_default = 0x00000000, | ||
| 265 | regk_marb_bar_rw_ddr2_slots_size = 0x00000040, | ||
| 266 | regk_marb_bar_rw_h264_rd_burst_default = 0x00000000, | ||
| 267 | regk_marb_bar_rw_h264_wr_burst_default = 0x00000000, | ||
| 268 | regk_marb_bar_rw_intr_mask_default = 0x00000000, | ||
| 269 | regk_marb_bar_rw_l2cache_burst_default = 0x00000000, | ||
| 270 | regk_marb_bar_rw_no_snoop_default = 0x00000000, | ||
| 271 | regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000, | ||
| 272 | regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000, | ||
| 273 | regk_marb_bar_rw_stop_mask_default = 0x00000000, | ||
| 274 | regk_marb_bar_rw_vin_rd_burst_default = 0x00000000, | ||
| 275 | regk_marb_bar_rw_vin_wr_burst_default = 0x00000000, | ||
| 276 | regk_marb_bar_rw_vout_burst_default = 0x00000000, | ||
| 277 | regk_marb_bar_sclr_fifo = 0x00000007, | ||
| 278 | regk_marb_bar_sclr_rd = 0x00000005, | ||
| 279 | regk_marb_bar_vin_rd = 0x00000004, | ||
| 280 | regk_marb_bar_vin_wr = 0x00000003, | ||
| 281 | regk_marb_bar_vout = 0x00000006, | ||
| 282 | regk_marb_bar_yes = 0x00000001 | ||
| 283 | }; | ||
| 284 | #endif /* __marb_bar_defs_h */ | ||
| 285 | #ifndef __marb_bar_bp_defs_h | ||
| 286 | #define __marb_bar_bp_defs_h | ||
| 287 | |||
| 288 | /* | ||
| 289 | * This file is autogenerated from | ||
| 290 | * file: marb_bar.r | ||
| 291 | * | ||
| 292 | * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r | ||
| 293 | * Any changes here will be lost. | ||
| 294 | * | ||
| 295 | * -*- buffer-read-only: t -*- | ||
| 296 | */ | ||
| 297 | /* Main access macros */ | ||
| 298 | #ifndef REG_RD | ||
| 299 | #define REG_RD( scope, inst, reg ) \ | ||
| 300 | REG_READ( reg_##scope##_##reg, \ | ||
| 301 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 302 | #endif | ||
| 303 | |||
| 304 | #ifndef REG_WR | ||
| 305 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 306 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 307 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 308 | #endif | ||
| 309 | |||
| 310 | #ifndef REG_RD_VECT | ||
| 311 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 312 | REG_READ( reg_##scope##_##reg, \ | ||
| 313 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 314 | (index) * STRIDE_##scope##_##reg ) | ||
| 315 | #endif | ||
| 316 | |||
| 317 | #ifndef REG_WR_VECT | ||
| 318 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 319 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 320 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 321 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 322 | #endif | ||
| 323 | |||
| 324 | #ifndef REG_RD_INT | ||
| 325 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 326 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 327 | #endif | ||
| 328 | |||
| 329 | #ifndef REG_WR_INT | ||
| 330 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 331 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 332 | #endif | ||
| 333 | |||
| 334 | #ifndef REG_RD_INT_VECT | ||
| 335 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 336 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 337 | (index) * STRIDE_##scope##_##reg ) | ||
| 338 | #endif | ||
| 339 | |||
| 340 | #ifndef REG_WR_INT_VECT | ||
| 341 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 342 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 343 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 344 | #endif | ||
| 345 | |||
| 346 | #ifndef REG_TYPE_CONV | ||
| 347 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 348 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 349 | #endif | ||
| 350 | |||
| 351 | #ifndef reg_page_size | ||
| 352 | #define reg_page_size 8192 | ||
| 353 | #endif | ||
| 354 | |||
| 355 | #ifndef REG_ADDR | ||
| 356 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 357 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 358 | #endif | ||
| 359 | |||
| 360 | #ifndef REG_ADDR_VECT | ||
| 361 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 362 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 363 | (index) * STRIDE_##scope##_##reg ) | ||
| 364 | #endif | ||
| 365 | |||
| 366 | /* C-code for register scope marb_bar_bp */ | ||
| 367 | |||
| 368 | /* Register rw_first_addr, scope marb_bar_bp, type rw */ | ||
| 369 | typedef unsigned int reg_marb_bar_bp_rw_first_addr; | ||
| 370 | #define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0 | ||
| 371 | #define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0 | ||
| 372 | |||
| 373 | /* Register rw_last_addr, scope marb_bar_bp, type rw */ | ||
| 374 | typedef unsigned int reg_marb_bar_bp_rw_last_addr; | ||
| 375 | #define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4 | ||
| 376 | #define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4 | ||
| 377 | |||
| 378 | /* Register rw_op, scope marb_bar_bp, type rw */ | ||
| 379 | typedef struct { | ||
| 380 | unsigned int rd : 1; | ||
| 381 | unsigned int wr : 1; | ||
| 382 | unsigned int rd_excl : 1; | ||
| 383 | unsigned int pri_wr : 1; | ||
| 384 | unsigned int us_rd : 1; | ||
| 385 | unsigned int us_wr : 1; | ||
| 386 | unsigned int us_rd_excl : 1; | ||
| 387 | unsigned int us_pri_wr : 1; | ||
| 388 | unsigned int dummy1 : 24; | ||
| 389 | } reg_marb_bar_bp_rw_op; | ||
| 390 | #define REG_RD_ADDR_marb_bar_bp_rw_op 8 | ||
| 391 | #define REG_WR_ADDR_marb_bar_bp_rw_op 8 | ||
| 392 | |||
| 393 | /* Register rw_clients, scope marb_bar_bp, type rw */ | ||
| 394 | typedef struct { | ||
| 395 | unsigned int h264_rd : 1; | ||
| 396 | unsigned int h264_wr : 1; | ||
| 397 | unsigned int ccd : 1; | ||
| 398 | unsigned int vin_wr : 1; | ||
| 399 | unsigned int vin_rd : 1; | ||
| 400 | unsigned int sclr_rd : 1; | ||
| 401 | unsigned int vout : 1; | ||
| 402 | unsigned int sclr_fifo : 1; | ||
| 403 | unsigned int l2cache : 1; | ||
| 404 | unsigned int dummy1 : 23; | ||
| 405 | } reg_marb_bar_bp_rw_clients; | ||
| 406 | #define REG_RD_ADDR_marb_bar_bp_rw_clients 12 | ||
| 407 | #define REG_WR_ADDR_marb_bar_bp_rw_clients 12 | ||
| 408 | |||
| 409 | /* Register rw_options, scope marb_bar_bp, type rw */ | ||
| 410 | typedef struct { | ||
| 411 | unsigned int wrap : 1; | ||
| 412 | unsigned int dummy1 : 31; | ||
| 413 | } reg_marb_bar_bp_rw_options; | ||
| 414 | #define REG_RD_ADDR_marb_bar_bp_rw_options 16 | ||
| 415 | #define REG_WR_ADDR_marb_bar_bp_rw_options 16 | ||
| 416 | |||
| 417 | /* Register r_brk_addr, scope marb_bar_bp, type r */ | ||
| 418 | typedef unsigned int reg_marb_bar_bp_r_brk_addr; | ||
| 419 | #define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20 | ||
| 420 | |||
| 421 | /* Register r_brk_op, scope marb_bar_bp, type r */ | ||
| 422 | typedef struct { | ||
| 423 | unsigned int rd : 1; | ||
| 424 | unsigned int wr : 1; | ||
| 425 | unsigned int rd_excl : 1; | ||
| 426 | unsigned int pri_wr : 1; | ||
| 427 | unsigned int us_rd : 1; | ||
| 428 | unsigned int us_wr : 1; | ||
| 429 | unsigned int us_rd_excl : 1; | ||
| 430 | unsigned int us_pri_wr : 1; | ||
| 431 | unsigned int dummy1 : 24; | ||
| 432 | } reg_marb_bar_bp_r_brk_op; | ||
| 433 | #define REG_RD_ADDR_marb_bar_bp_r_brk_op 24 | ||
| 434 | |||
| 435 | /* Register r_brk_clients, scope marb_bar_bp, type r */ | ||
| 436 | typedef struct { | ||
| 437 | unsigned int h264_rd : 1; | ||
| 438 | unsigned int h264_wr : 1; | ||
| 439 | unsigned int ccd : 1; | ||
| 440 | unsigned int vin_wr : 1; | ||
| 441 | unsigned int vin_rd : 1; | ||
| 442 | unsigned int sclr_rd : 1; | ||
| 443 | unsigned int vout : 1; | ||
| 444 | unsigned int sclr_fifo : 1; | ||
| 445 | unsigned int l2cache : 1; | ||
| 446 | unsigned int dummy1 : 23; | ||
| 447 | } reg_marb_bar_bp_r_brk_clients; | ||
| 448 | #define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28 | ||
| 449 | |||
| 450 | /* Register r_brk_first_client, scope marb_bar_bp, type r */ | ||
| 451 | typedef struct { | ||
| 452 | unsigned int h264_rd : 1; | ||
| 453 | unsigned int h264_wr : 1; | ||
| 454 | unsigned int ccd : 1; | ||
| 455 | unsigned int vin_wr : 1; | ||
| 456 | unsigned int vin_rd : 1; | ||
| 457 | unsigned int sclr_rd : 1; | ||
| 458 | unsigned int vout : 1; | ||
| 459 | unsigned int sclr_fifo : 1; | ||
| 460 | unsigned int l2cache : 1; | ||
| 461 | unsigned int dummy1 : 23; | ||
| 462 | } reg_marb_bar_bp_r_brk_first_client; | ||
| 463 | #define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32 | ||
| 464 | |||
| 465 | /* Register r_brk_size, scope marb_bar_bp, type r */ | ||
| 466 | typedef unsigned int reg_marb_bar_bp_r_brk_size; | ||
| 467 | #define REG_RD_ADDR_marb_bar_bp_r_brk_size 36 | ||
| 468 | |||
| 469 | /* Register rw_ack, scope marb_bar_bp, type rw */ | ||
| 470 | typedef unsigned int reg_marb_bar_bp_rw_ack; | ||
| 471 | #define REG_RD_ADDR_marb_bar_bp_rw_ack 40 | ||
| 472 | #define REG_WR_ADDR_marb_bar_bp_rw_ack 40 | ||
| 473 | |||
| 474 | |||
| 475 | /* Constants */ | ||
| 476 | enum { | ||
| 477 | regk_marb_bar_bp_no = 0x00000000, | ||
| 478 | regk_marb_bar_bp_rw_op_default = 0x00000000, | ||
| 479 | regk_marb_bar_bp_rw_options_default = 0x00000000, | ||
| 480 | regk_marb_bar_bp_yes = 0x00000001 | ||
| 481 | }; | ||
| 482 | #endif /* __marb_bar_bp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h new file mode 100644 index 000000000000..2baa833f109a --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/marb_foo_defs.h | |||
| @@ -0,0 +1,626 @@ | |||
| 1 | #ifndef __marb_foo_defs_h | ||
| 2 | #define __marb_foo_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: marb_foo.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope marb_foo */ | ||
| 83 | |||
| 84 | #define STRIDE_marb_foo_rw_intm_slots 4 | ||
| 85 | /* Register rw_intm_slots, scope marb_foo, type rw */ | ||
| 86 | typedef struct { | ||
| 87 | unsigned int owner : 4; | ||
| 88 | unsigned int dummy1 : 28; | ||
| 89 | } reg_marb_foo_rw_intm_slots; | ||
| 90 | #define REG_RD_ADDR_marb_foo_rw_intm_slots 0 | ||
| 91 | #define REG_WR_ADDR_marb_foo_rw_intm_slots 0 | ||
| 92 | |||
| 93 | #define STRIDE_marb_foo_rw_l2_slots 4 | ||
| 94 | /* Register rw_l2_slots, scope marb_foo, type rw */ | ||
| 95 | typedef struct { | ||
| 96 | unsigned int owner : 4; | ||
| 97 | unsigned int dummy1 : 28; | ||
| 98 | } reg_marb_foo_rw_l2_slots; | ||
| 99 | #define REG_RD_ADDR_marb_foo_rw_l2_slots 256 | ||
| 100 | #define REG_WR_ADDR_marb_foo_rw_l2_slots 256 | ||
| 101 | |||
| 102 | #define STRIDE_marb_foo_rw_regs_slots 4 | ||
| 103 | /* Register rw_regs_slots, scope marb_foo, type rw */ | ||
| 104 | typedef struct { | ||
| 105 | unsigned int owner : 4; | ||
| 106 | unsigned int dummy1 : 28; | ||
| 107 | } reg_marb_foo_rw_regs_slots; | ||
| 108 | #define REG_RD_ADDR_marb_foo_rw_regs_slots 512 | ||
| 109 | #define REG_WR_ADDR_marb_foo_rw_regs_slots 512 | ||
| 110 | |||
| 111 | /* Register rw_sclr_burst, scope marb_foo, type rw */ | ||
| 112 | typedef struct { | ||
| 113 | unsigned int intm_bsize : 2; | ||
| 114 | unsigned int l2_bsize : 2; | ||
| 115 | unsigned int dummy1 : 28; | ||
| 116 | } reg_marb_foo_rw_sclr_burst; | ||
| 117 | #define REG_RD_ADDR_marb_foo_rw_sclr_burst 528 | ||
| 118 | #define REG_WR_ADDR_marb_foo_rw_sclr_burst 528 | ||
| 119 | |||
| 120 | /* Register rw_dma0_burst, scope marb_foo, type rw */ | ||
| 121 | typedef struct { | ||
| 122 | unsigned int intm_bsize : 2; | ||
| 123 | unsigned int l2_bsize : 2; | ||
| 124 | unsigned int dummy1 : 28; | ||
| 125 | } reg_marb_foo_rw_dma0_burst; | ||
| 126 | #define REG_RD_ADDR_marb_foo_rw_dma0_burst 532 | ||
| 127 | #define REG_WR_ADDR_marb_foo_rw_dma0_burst 532 | ||
| 128 | |||
| 129 | /* Register rw_dma1_burst, scope marb_foo, type rw */ | ||
| 130 | typedef struct { | ||
| 131 | unsigned int intm_bsize : 2; | ||
| 132 | unsigned int l2_bsize : 2; | ||
| 133 | unsigned int dummy1 : 28; | ||
| 134 | } reg_marb_foo_rw_dma1_burst; | ||
| 135 | #define REG_RD_ADDR_marb_foo_rw_dma1_burst 536 | ||
| 136 | #define REG_WR_ADDR_marb_foo_rw_dma1_burst 536 | ||
| 137 | |||
| 138 | /* Register rw_dma2_burst, scope marb_foo, type rw */ | ||
| 139 | typedef struct { | ||
| 140 | unsigned int intm_bsize : 2; | ||
| 141 | unsigned int l2_bsize : 2; | ||
| 142 | unsigned int dummy1 : 28; | ||
| 143 | } reg_marb_foo_rw_dma2_burst; | ||
| 144 | #define REG_RD_ADDR_marb_foo_rw_dma2_burst 540 | ||
| 145 | #define REG_WR_ADDR_marb_foo_rw_dma2_burst 540 | ||
| 146 | |||
| 147 | /* Register rw_dma3_burst, scope marb_foo, type rw */ | ||
| 148 | typedef struct { | ||
| 149 | unsigned int intm_bsize : 2; | ||
| 150 | unsigned int l2_bsize : 2; | ||
| 151 | unsigned int dummy1 : 28; | ||
| 152 | } reg_marb_foo_rw_dma3_burst; | ||
| 153 | #define REG_RD_ADDR_marb_foo_rw_dma3_burst 544 | ||
| 154 | #define REG_WR_ADDR_marb_foo_rw_dma3_burst 544 | ||
| 155 | |||
| 156 | /* Register rw_dma4_burst, scope marb_foo, type rw */ | ||
| 157 | typedef struct { | ||
| 158 | unsigned int intm_bsize : 2; | ||
| 159 | unsigned int l2_bsize : 2; | ||
| 160 | unsigned int dummy1 : 28; | ||
| 161 | } reg_marb_foo_rw_dma4_burst; | ||
| 162 | #define REG_RD_ADDR_marb_foo_rw_dma4_burst 548 | ||
| 163 | #define REG_WR_ADDR_marb_foo_rw_dma4_burst 548 | ||
| 164 | |||
| 165 | /* Register rw_dma5_burst, scope marb_foo, type rw */ | ||
| 166 | typedef struct { | ||
| 167 | unsigned int intm_bsize : 2; | ||
| 168 | unsigned int l2_bsize : 2; | ||
| 169 | unsigned int dummy1 : 28; | ||
| 170 | } reg_marb_foo_rw_dma5_burst; | ||
| 171 | #define REG_RD_ADDR_marb_foo_rw_dma5_burst 552 | ||
| 172 | #define REG_WR_ADDR_marb_foo_rw_dma5_burst 552 | ||
| 173 | |||
| 174 | /* Register rw_dma6_burst, scope marb_foo, type rw */ | ||
| 175 | typedef struct { | ||
| 176 | unsigned int intm_bsize : 2; | ||
| 177 | unsigned int l2_bsize : 2; | ||
| 178 | unsigned int dummy1 : 28; | ||
| 179 | } reg_marb_foo_rw_dma6_burst; | ||
| 180 | #define REG_RD_ADDR_marb_foo_rw_dma6_burst 556 | ||
| 181 | #define REG_WR_ADDR_marb_foo_rw_dma6_burst 556 | ||
| 182 | |||
| 183 | /* Register rw_dma7_burst, scope marb_foo, type rw */ | ||
| 184 | typedef struct { | ||
| 185 | unsigned int intm_bsize : 2; | ||
| 186 | unsigned int l2_bsize : 2; | ||
| 187 | unsigned int dummy1 : 28; | ||
| 188 | } reg_marb_foo_rw_dma7_burst; | ||
| 189 | #define REG_RD_ADDR_marb_foo_rw_dma7_burst 560 | ||
| 190 | #define REG_WR_ADDR_marb_foo_rw_dma7_burst 560 | ||
| 191 | |||
| 192 | /* Register rw_dma9_burst, scope marb_foo, type rw */ | ||
| 193 | typedef struct { | ||
| 194 | unsigned int intm_bsize : 2; | ||
| 195 | unsigned int l2_bsize : 2; | ||
| 196 | unsigned int dummy1 : 28; | ||
| 197 | } reg_marb_foo_rw_dma9_burst; | ||
| 198 | #define REG_RD_ADDR_marb_foo_rw_dma9_burst 564 | ||
| 199 | #define REG_WR_ADDR_marb_foo_rw_dma9_burst 564 | ||
| 200 | |||
| 201 | /* Register rw_dma11_burst, scope marb_foo, type rw */ | ||
| 202 | typedef struct { | ||
| 203 | unsigned int intm_bsize : 2; | ||
| 204 | unsigned int l2_bsize : 2; | ||
| 205 | unsigned int dummy1 : 28; | ||
| 206 | } reg_marb_foo_rw_dma11_burst; | ||
| 207 | #define REG_RD_ADDR_marb_foo_rw_dma11_burst 568 | ||
| 208 | #define REG_WR_ADDR_marb_foo_rw_dma11_burst 568 | ||
| 209 | |||
| 210 | /* Register rw_cpui_burst, scope marb_foo, type rw */ | ||
| 211 | typedef struct { | ||
| 212 | unsigned int intm_bsize : 2; | ||
| 213 | unsigned int l2_bsize : 2; | ||
| 214 | unsigned int dummy1 : 28; | ||
| 215 | } reg_marb_foo_rw_cpui_burst; | ||
| 216 | #define REG_RD_ADDR_marb_foo_rw_cpui_burst 572 | ||
| 217 | #define REG_WR_ADDR_marb_foo_rw_cpui_burst 572 | ||
| 218 | |||
| 219 | /* Register rw_cpud_burst, scope marb_foo, type rw */ | ||
| 220 | typedef struct { | ||
| 221 | unsigned int intm_bsize : 2; | ||
| 222 | unsigned int l2_bsize : 2; | ||
| 223 | unsigned int dummy1 : 28; | ||
| 224 | } reg_marb_foo_rw_cpud_burst; | ||
| 225 | #define REG_RD_ADDR_marb_foo_rw_cpud_burst 576 | ||
| 226 | #define REG_WR_ADDR_marb_foo_rw_cpud_burst 576 | ||
| 227 | |||
| 228 | /* Register rw_iop_burst, scope marb_foo, type rw */ | ||
| 229 | typedef struct { | ||
| 230 | unsigned int intm_bsize : 2; | ||
| 231 | unsigned int l2_bsize : 2; | ||
| 232 | unsigned int dummy1 : 28; | ||
| 233 | } reg_marb_foo_rw_iop_burst; | ||
| 234 | #define REG_RD_ADDR_marb_foo_rw_iop_burst 580 | ||
| 235 | #define REG_WR_ADDR_marb_foo_rw_iop_burst 580 | ||
| 236 | |||
| 237 | /* Register rw_ccdstat_burst, scope marb_foo, type rw */ | ||
| 238 | typedef struct { | ||
| 239 | unsigned int intm_bsize : 2; | ||
| 240 | unsigned int l2_bsize : 2; | ||
| 241 | unsigned int dummy1 : 28; | ||
| 242 | } reg_marb_foo_rw_ccdstat_burst; | ||
| 243 | #define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584 | ||
| 244 | #define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584 | ||
| 245 | |||
| 246 | /* Register rw_intr_mask, scope marb_foo, type rw */ | ||
| 247 | typedef struct { | ||
| 248 | unsigned int bp0 : 1; | ||
| 249 | unsigned int bp1 : 1; | ||
| 250 | unsigned int bp2 : 1; | ||
| 251 | unsigned int bp3 : 1; | ||
| 252 | unsigned int dummy1 : 28; | ||
| 253 | } reg_marb_foo_rw_intr_mask; | ||
| 254 | #define REG_RD_ADDR_marb_foo_rw_intr_mask 588 | ||
| 255 | #define REG_WR_ADDR_marb_foo_rw_intr_mask 588 | ||
| 256 | |||
| 257 | /* Register rw_ack_intr, scope marb_foo, type rw */ | ||
| 258 | typedef struct { | ||
| 259 | unsigned int bp0 : 1; | ||
| 260 | unsigned int bp1 : 1; | ||
| 261 | unsigned int bp2 : 1; | ||
| 262 | unsigned int bp3 : 1; | ||
| 263 | unsigned int dummy1 : 28; | ||
| 264 | } reg_marb_foo_rw_ack_intr; | ||
| 265 | #define REG_RD_ADDR_marb_foo_rw_ack_intr 592 | ||
| 266 | #define REG_WR_ADDR_marb_foo_rw_ack_intr 592 | ||
| 267 | |||
| 268 | /* Register r_intr, scope marb_foo, type r */ | ||
| 269 | typedef struct { | ||
| 270 | unsigned int bp0 : 1; | ||
| 271 | unsigned int bp1 : 1; | ||
| 272 | unsigned int bp2 : 1; | ||
| 273 | unsigned int bp3 : 1; | ||
| 274 | unsigned int dummy1 : 28; | ||
| 275 | } reg_marb_foo_r_intr; | ||
| 276 | #define REG_RD_ADDR_marb_foo_r_intr 596 | ||
| 277 | |||
| 278 | /* Register r_masked_intr, scope marb_foo, type r */ | ||
| 279 | typedef struct { | ||
| 280 | unsigned int bp0 : 1; | ||
| 281 | unsigned int bp1 : 1; | ||
| 282 | unsigned int bp2 : 1; | ||
| 283 | unsigned int bp3 : 1; | ||
| 284 | unsigned int dummy1 : 28; | ||
| 285 | } reg_marb_foo_r_masked_intr; | ||
| 286 | #define REG_RD_ADDR_marb_foo_r_masked_intr 600 | ||
| 287 | |||
| 288 | /* Register rw_stop_mask, scope marb_foo, type rw */ | ||
| 289 | typedef struct { | ||
| 290 | unsigned int sclr : 1; | ||
| 291 | unsigned int dma0 : 1; | ||
| 292 | unsigned int dma1 : 1; | ||
| 293 | unsigned int dma2 : 1; | ||
| 294 | unsigned int dma3 : 1; | ||
| 295 | unsigned int dma4 : 1; | ||
| 296 | unsigned int dma5 : 1; | ||
| 297 | unsigned int dma6 : 1; | ||
| 298 | unsigned int dma7 : 1; | ||
| 299 | unsigned int dma9 : 1; | ||
| 300 | unsigned int dma11 : 1; | ||
| 301 | unsigned int cpui : 1; | ||
| 302 | unsigned int cpud : 1; | ||
| 303 | unsigned int iop : 1; | ||
| 304 | unsigned int ccdstat : 1; | ||
| 305 | unsigned int dummy1 : 17; | ||
| 306 | } reg_marb_foo_rw_stop_mask; | ||
| 307 | #define REG_RD_ADDR_marb_foo_rw_stop_mask 604 | ||
| 308 | #define REG_WR_ADDR_marb_foo_rw_stop_mask 604 | ||
| 309 | |||
| 310 | /* Register r_stopped, scope marb_foo, type r */ | ||
| 311 | typedef struct { | ||
| 312 | unsigned int sclr : 1; | ||
| 313 | unsigned int dma0 : 1; | ||
| 314 | unsigned int dma1 : 1; | ||
| 315 | unsigned int dma2 : 1; | ||
| 316 | unsigned int dma3 : 1; | ||
| 317 | unsigned int dma4 : 1; | ||
| 318 | unsigned int dma5 : 1; | ||
| 319 | unsigned int dma6 : 1; | ||
| 320 | unsigned int dma7 : 1; | ||
| 321 | unsigned int dma9 : 1; | ||
| 322 | unsigned int dma11 : 1; | ||
| 323 | unsigned int cpui : 1; | ||
| 324 | unsigned int cpud : 1; | ||
| 325 | unsigned int iop : 1; | ||
| 326 | unsigned int ccdstat : 1; | ||
| 327 | unsigned int dummy1 : 17; | ||
| 328 | } reg_marb_foo_r_stopped; | ||
| 329 | #define REG_RD_ADDR_marb_foo_r_stopped 608 | ||
| 330 | |||
| 331 | /* Register rw_no_snoop, scope marb_foo, type rw */ | ||
| 332 | typedef struct { | ||
| 333 | unsigned int sclr : 1; | ||
| 334 | unsigned int dma0 : 1; | ||
| 335 | unsigned int dma1 : 1; | ||
| 336 | unsigned int dma2 : 1; | ||
| 337 | unsigned int dma3 : 1; | ||
| 338 | unsigned int dma4 : 1; | ||
| 339 | unsigned int dma5 : 1; | ||
| 340 | unsigned int dma6 : 1; | ||
| 341 | unsigned int dma7 : 1; | ||
| 342 | unsigned int dma9 : 1; | ||
| 343 | unsigned int dma11 : 1; | ||
| 344 | unsigned int cpui : 1; | ||
| 345 | unsigned int cpud : 1; | ||
| 346 | unsigned int iop : 1; | ||
| 347 | unsigned int ccdstat : 1; | ||
| 348 | unsigned int dummy1 : 17; | ||
| 349 | } reg_marb_foo_rw_no_snoop; | ||
| 350 | #define REG_RD_ADDR_marb_foo_rw_no_snoop 896 | ||
| 351 | #define REG_WR_ADDR_marb_foo_rw_no_snoop 896 | ||
| 352 | |||
| 353 | /* Register rw_no_snoop_rq, scope marb_foo, type rw */ | ||
| 354 | typedef struct { | ||
| 355 | unsigned int dummy1 : 11; | ||
| 356 | unsigned int cpui : 1; | ||
| 357 | unsigned int cpud : 1; | ||
| 358 | unsigned int dummy2 : 19; | ||
| 359 | } reg_marb_foo_rw_no_snoop_rq; | ||
| 360 | #define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900 | ||
| 361 | #define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900 | ||
| 362 | |||
| 363 | |||
| 364 | /* Constants */ | ||
| 365 | enum { | ||
| 366 | regk_marb_foo_ccdstat = 0x0000000e, | ||
| 367 | regk_marb_foo_cpud = 0x0000000c, | ||
| 368 | regk_marb_foo_cpui = 0x0000000b, | ||
| 369 | regk_marb_foo_dma0 = 0x00000001, | ||
| 370 | regk_marb_foo_dma1 = 0x00000002, | ||
| 371 | regk_marb_foo_dma11 = 0x0000000a, | ||
| 372 | regk_marb_foo_dma2 = 0x00000003, | ||
| 373 | regk_marb_foo_dma3 = 0x00000004, | ||
| 374 | regk_marb_foo_dma4 = 0x00000005, | ||
| 375 | regk_marb_foo_dma5 = 0x00000006, | ||
| 376 | regk_marb_foo_dma6 = 0x00000007, | ||
| 377 | regk_marb_foo_dma7 = 0x00000008, | ||
| 378 | regk_marb_foo_dma9 = 0x00000009, | ||
| 379 | regk_marb_foo_iop = 0x0000000d, | ||
| 380 | regk_marb_foo_no = 0x00000000, | ||
| 381 | regk_marb_foo_r_stopped_default = 0x00000000, | ||
| 382 | regk_marb_foo_rw_ccdstat_burst_default = 0x00000000, | ||
| 383 | regk_marb_foo_rw_cpud_burst_default = 0x00000000, | ||
| 384 | regk_marb_foo_rw_cpui_burst_default = 0x00000000, | ||
| 385 | regk_marb_foo_rw_dma0_burst_default = 0x00000000, | ||
| 386 | regk_marb_foo_rw_dma11_burst_default = 0x00000000, | ||
| 387 | regk_marb_foo_rw_dma1_burst_default = 0x00000000, | ||
| 388 | regk_marb_foo_rw_dma2_burst_default = 0x00000000, | ||
| 389 | regk_marb_foo_rw_dma3_burst_default = 0x00000000, | ||
| 390 | regk_marb_foo_rw_dma4_burst_default = 0x00000000, | ||
| 391 | regk_marb_foo_rw_dma5_burst_default = 0x00000000, | ||
| 392 | regk_marb_foo_rw_dma6_burst_default = 0x00000000, | ||
| 393 | regk_marb_foo_rw_dma7_burst_default = 0x00000000, | ||
| 394 | regk_marb_foo_rw_dma9_burst_default = 0x00000000, | ||
| 395 | regk_marb_foo_rw_intm_slots_default = 0x00000000, | ||
| 396 | regk_marb_foo_rw_intm_slots_size = 0x00000040, | ||
| 397 | regk_marb_foo_rw_intr_mask_default = 0x00000000, | ||
| 398 | regk_marb_foo_rw_iop_burst_default = 0x00000000, | ||
| 399 | regk_marb_foo_rw_l2_slots_default = 0x00000000, | ||
| 400 | regk_marb_foo_rw_l2_slots_size = 0x00000040, | ||
| 401 | regk_marb_foo_rw_no_snoop_default = 0x00000000, | ||
| 402 | regk_marb_foo_rw_no_snoop_rq_default = 0x00000000, | ||
| 403 | regk_marb_foo_rw_regs_slots_default = 0x00000000, | ||
| 404 | regk_marb_foo_rw_regs_slots_size = 0x00000004, | ||
| 405 | regk_marb_foo_rw_sclr_burst_default = 0x00000000, | ||
| 406 | regk_marb_foo_rw_stop_mask_default = 0x00000000, | ||
| 407 | regk_marb_foo_sclr = 0x00000000, | ||
| 408 | regk_marb_foo_yes = 0x00000001 | ||
| 409 | }; | ||
| 410 | #endif /* __marb_foo_defs_h */ | ||
| 411 | #ifndef __marb_foo_bp_defs_h | ||
| 412 | #define __marb_foo_bp_defs_h | ||
| 413 | |||
| 414 | /* | ||
| 415 | * This file is autogenerated from | ||
| 416 | * file: marb_foo.r | ||
| 417 | * | ||
| 418 | * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r | ||
| 419 | * Any changes here will be lost. | ||
| 420 | * | ||
| 421 | * -*- buffer-read-only: t -*- | ||
| 422 | */ | ||
| 423 | /* Main access macros */ | ||
| 424 | #ifndef REG_RD | ||
| 425 | #define REG_RD( scope, inst, reg ) \ | ||
| 426 | REG_READ( reg_##scope##_##reg, \ | ||
| 427 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 428 | #endif | ||
| 429 | |||
| 430 | #ifndef REG_WR | ||
| 431 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 432 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 433 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 434 | #endif | ||
| 435 | |||
| 436 | #ifndef REG_RD_VECT | ||
| 437 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 438 | REG_READ( reg_##scope##_##reg, \ | ||
| 439 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 440 | (index) * STRIDE_##scope##_##reg ) | ||
| 441 | #endif | ||
| 442 | |||
| 443 | #ifndef REG_WR_VECT | ||
| 444 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 445 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 446 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 447 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 448 | #endif | ||
| 449 | |||
| 450 | #ifndef REG_RD_INT | ||
| 451 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 452 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 453 | #endif | ||
| 454 | |||
| 455 | #ifndef REG_WR_INT | ||
| 456 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 457 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 458 | #endif | ||
| 459 | |||
| 460 | #ifndef REG_RD_INT_VECT | ||
| 461 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 462 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 463 | (index) * STRIDE_##scope##_##reg ) | ||
| 464 | #endif | ||
| 465 | |||
| 466 | #ifndef REG_WR_INT_VECT | ||
| 467 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 468 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 469 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 470 | #endif | ||
| 471 | |||
| 472 | #ifndef REG_TYPE_CONV | ||
| 473 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 474 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 475 | #endif | ||
| 476 | |||
| 477 | #ifndef reg_page_size | ||
| 478 | #define reg_page_size 8192 | ||
| 479 | #endif | ||
| 480 | |||
| 481 | #ifndef REG_ADDR | ||
| 482 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 483 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 484 | #endif | ||
| 485 | |||
| 486 | #ifndef REG_ADDR_VECT | ||
| 487 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 488 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 489 | (index) * STRIDE_##scope##_##reg ) | ||
| 490 | #endif | ||
| 491 | |||
| 492 | /* C-code for register scope marb_foo_bp */ | ||
| 493 | |||
| 494 | /* Register rw_first_addr, scope marb_foo_bp, type rw */ | ||
| 495 | typedef unsigned int reg_marb_foo_bp_rw_first_addr; | ||
| 496 | #define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0 | ||
| 497 | #define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0 | ||
| 498 | |||
| 499 | /* Register rw_last_addr, scope marb_foo_bp, type rw */ | ||
| 500 | typedef unsigned int reg_marb_foo_bp_rw_last_addr; | ||
| 501 | #define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4 | ||
| 502 | #define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4 | ||
| 503 | |||
| 504 | /* Register rw_op, scope marb_foo_bp, type rw */ | ||
| 505 | typedef struct { | ||
| 506 | unsigned int rd : 1; | ||
| 507 | unsigned int wr : 1; | ||
| 508 | unsigned int rd_excl : 1; | ||
| 509 | unsigned int pri_wr : 1; | ||
| 510 | unsigned int us_rd : 1; | ||
| 511 | unsigned int us_wr : 1; | ||
| 512 | unsigned int us_rd_excl : 1; | ||
| 513 | unsigned int us_pri_wr : 1; | ||
| 514 | unsigned int dummy1 : 24; | ||
| 515 | } reg_marb_foo_bp_rw_op; | ||
| 516 | #define REG_RD_ADDR_marb_foo_bp_rw_op 8 | ||
| 517 | #define REG_WR_ADDR_marb_foo_bp_rw_op 8 | ||
| 518 | |||
| 519 | /* Register rw_clients, scope marb_foo_bp, type rw */ | ||
| 520 | typedef struct { | ||
| 521 | unsigned int sclr : 1; | ||
| 522 | unsigned int dma0 : 1; | ||
| 523 | unsigned int dma1 : 1; | ||
| 524 | unsigned int dma2 : 1; | ||
| 525 | unsigned int dma3 : 1; | ||
| 526 | unsigned int dma4 : 1; | ||
| 527 | unsigned int dma5 : 1; | ||
| 528 | unsigned int dma6 : 1; | ||
| 529 | unsigned int dma7 : 1; | ||
| 530 | unsigned int dma9 : 1; | ||
| 531 | unsigned int dma11 : 1; | ||
| 532 | unsigned int cpui : 1; | ||
| 533 | unsigned int cpud : 1; | ||
| 534 | unsigned int iop : 1; | ||
| 535 | unsigned int ccdstat : 1; | ||
| 536 | unsigned int dummy1 : 17; | ||
| 537 | } reg_marb_foo_bp_rw_clients; | ||
| 538 | #define REG_RD_ADDR_marb_foo_bp_rw_clients 12 | ||
| 539 | #define REG_WR_ADDR_marb_foo_bp_rw_clients 12 | ||
| 540 | |||
| 541 | /* Register rw_options, scope marb_foo_bp, type rw */ | ||
| 542 | typedef struct { | ||
| 543 | unsigned int wrap : 1; | ||
| 544 | unsigned int dummy1 : 31; | ||
| 545 | } reg_marb_foo_bp_rw_options; | ||
| 546 | #define REG_RD_ADDR_marb_foo_bp_rw_options 16 | ||
| 547 | #define REG_WR_ADDR_marb_foo_bp_rw_options 16 | ||
| 548 | |||
| 549 | /* Register r_brk_addr, scope marb_foo_bp, type r */ | ||
| 550 | typedef unsigned int reg_marb_foo_bp_r_brk_addr; | ||
| 551 | #define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20 | ||
| 552 | |||
| 553 | /* Register r_brk_op, scope marb_foo_bp, type r */ | ||
| 554 | typedef struct { | ||
| 555 | unsigned int rd : 1; | ||
| 556 | unsigned int wr : 1; | ||
| 557 | unsigned int rd_excl : 1; | ||
| 558 | unsigned int pri_wr : 1; | ||
| 559 | unsigned int us_rd : 1; | ||
| 560 | unsigned int us_wr : 1; | ||
| 561 | unsigned int us_rd_excl : 1; | ||
| 562 | unsigned int us_pri_wr : 1; | ||
| 563 | unsigned int dummy1 : 24; | ||
| 564 | } reg_marb_foo_bp_r_brk_op; | ||
| 565 | #define REG_RD_ADDR_marb_foo_bp_r_brk_op 24 | ||
| 566 | |||
| 567 | /* Register r_brk_clients, scope marb_foo_bp, type r */ | ||
| 568 | typedef struct { | ||
| 569 | unsigned int sclr : 1; | ||
| 570 | unsigned int dma0 : 1; | ||
| 571 | unsigned int dma1 : 1; | ||
| 572 | unsigned int dma2 : 1; | ||
| 573 | unsigned int dma3 : 1; | ||
| 574 | unsigned int dma4 : 1; | ||
| 575 | unsigned int dma5 : 1; | ||
| 576 | unsigned int dma6 : 1; | ||
| 577 | unsigned int dma7 : 1; | ||
| 578 | unsigned int dma9 : 1; | ||
| 579 | unsigned int dma11 : 1; | ||
| 580 | unsigned int cpui : 1; | ||
| 581 | unsigned int cpud : 1; | ||
| 582 | unsigned int iop : 1; | ||
| 583 | unsigned int ccdstat : 1; | ||
| 584 | unsigned int dummy1 : 17; | ||
| 585 | } reg_marb_foo_bp_r_brk_clients; | ||
| 586 | #define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28 | ||
| 587 | |||
| 588 | /* Register r_brk_first_client, scope marb_foo_bp, type r */ | ||
| 589 | typedef struct { | ||
| 590 | unsigned int sclr : 1; | ||
| 591 | unsigned int dma0 : 1; | ||
| 592 | unsigned int dma1 : 1; | ||
| 593 | unsigned int dma2 : 1; | ||
| 594 | unsigned int dma3 : 1; | ||
| 595 | unsigned int dma4 : 1; | ||
| 596 | unsigned int dma5 : 1; | ||
| 597 | unsigned int dma6 : 1; | ||
| 598 | unsigned int dma7 : 1; | ||
| 599 | unsigned int dma9 : 1; | ||
| 600 | unsigned int dma11 : 1; | ||
| 601 | unsigned int cpui : 1; | ||
| 602 | unsigned int cpud : 1; | ||
| 603 | unsigned int iop : 1; | ||
| 604 | unsigned int ccdstat : 1; | ||
| 605 | unsigned int dummy1 : 17; | ||
| 606 | } reg_marb_foo_bp_r_brk_first_client; | ||
| 607 | #define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32 | ||
| 608 | |||
| 609 | /* Register r_brk_size, scope marb_foo_bp, type r */ | ||
| 610 | typedef unsigned int reg_marb_foo_bp_r_brk_size; | ||
| 611 | #define REG_RD_ADDR_marb_foo_bp_r_brk_size 36 | ||
| 612 | |||
| 613 | /* Register rw_ack, scope marb_foo_bp, type rw */ | ||
| 614 | typedef unsigned int reg_marb_foo_bp_rw_ack; | ||
| 615 | #define REG_RD_ADDR_marb_foo_bp_rw_ack 40 | ||
| 616 | #define REG_WR_ADDR_marb_foo_bp_rw_ack 40 | ||
| 617 | |||
| 618 | |||
| 619 | /* Constants */ | ||
| 620 | enum { | ||
| 621 | regk_marb_foo_bp_no = 0x00000000, | ||
| 622 | regk_marb_foo_bp_rw_op_default = 0x00000000, | ||
| 623 | regk_marb_foo_bp_rw_options_default = 0x00000000, | ||
| 624 | regk_marb_foo_bp_yes = 0x00000001 | ||
| 625 | }; | ||
| 626 | #endif /* __marb_foo_bp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h new file mode 100644 index 000000000000..4b96cd2cba8a --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/pinmux_defs.h | |||
| @@ -0,0 +1,312 @@ | |||
| 1 | #ifndef __pinmux_defs_h | ||
| 2 | #define __pinmux_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: pinmux.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope pinmux */ | ||
| 83 | |||
| 84 | /* Register rw_hwprot, scope pinmux, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int eth : 1; | ||
| 87 | unsigned int eth_mdio : 1; | ||
| 88 | unsigned int geth : 1; | ||
| 89 | unsigned int tg : 1; | ||
| 90 | unsigned int tg_clk : 1; | ||
| 91 | unsigned int vout : 1; | ||
| 92 | unsigned int vout_sync : 1; | ||
| 93 | unsigned int ser1 : 1; | ||
| 94 | unsigned int ser2 : 1; | ||
| 95 | unsigned int ser3 : 1; | ||
| 96 | unsigned int ser4 : 1; | ||
| 97 | unsigned int sser : 1; | ||
| 98 | unsigned int pwm0 : 1; | ||
| 99 | unsigned int pwm1 : 1; | ||
| 100 | unsigned int pwm2 : 1; | ||
| 101 | unsigned int timer0 : 1; | ||
| 102 | unsigned int timer1 : 1; | ||
| 103 | unsigned int pio : 1; | ||
| 104 | unsigned int i2c0 : 1; | ||
| 105 | unsigned int i2c1 : 1; | ||
| 106 | unsigned int i2c1_sda1 : 1; | ||
| 107 | unsigned int i2c1_sda2 : 1; | ||
| 108 | unsigned int i2c1_sda3 : 1; | ||
| 109 | unsigned int i2c1_sen : 1; | ||
| 110 | unsigned int dummy1 : 8; | ||
| 111 | } reg_pinmux_rw_hwprot; | ||
| 112 | #define REG_RD_ADDR_pinmux_rw_hwprot 0 | ||
| 113 | #define REG_WR_ADDR_pinmux_rw_hwprot 0 | ||
| 114 | |||
| 115 | /* Register rw_gio_pa, scope pinmux, type rw */ | ||
| 116 | typedef struct { | ||
| 117 | unsigned int pa0 : 1; | ||
| 118 | unsigned int pa1 : 1; | ||
| 119 | unsigned int pa2 : 1; | ||
| 120 | unsigned int pa3 : 1; | ||
| 121 | unsigned int pa4 : 1; | ||
| 122 | unsigned int pa5 : 1; | ||
| 123 | unsigned int pa6 : 1; | ||
| 124 | unsigned int pa7 : 1; | ||
| 125 | unsigned int pa8 : 1; | ||
| 126 | unsigned int pa9 : 1; | ||
| 127 | unsigned int pa10 : 1; | ||
| 128 | unsigned int pa11 : 1; | ||
| 129 | unsigned int pa12 : 1; | ||
| 130 | unsigned int pa13 : 1; | ||
| 131 | unsigned int pa14 : 1; | ||
| 132 | unsigned int pa15 : 1; | ||
| 133 | unsigned int pa16 : 1; | ||
| 134 | unsigned int pa17 : 1; | ||
| 135 | unsigned int pa18 : 1; | ||
| 136 | unsigned int pa19 : 1; | ||
| 137 | unsigned int pa20 : 1; | ||
| 138 | unsigned int pa21 : 1; | ||
| 139 | unsigned int pa22 : 1; | ||
| 140 | unsigned int pa23 : 1; | ||
| 141 | unsigned int pa24 : 1; | ||
| 142 | unsigned int pa25 : 1; | ||
| 143 | unsigned int pa26 : 1; | ||
| 144 | unsigned int pa27 : 1; | ||
| 145 | unsigned int pa28 : 1; | ||
| 146 | unsigned int pa29 : 1; | ||
| 147 | unsigned int pa30 : 1; | ||
| 148 | unsigned int pa31 : 1; | ||
| 149 | } reg_pinmux_rw_gio_pa; | ||
| 150 | #define REG_RD_ADDR_pinmux_rw_gio_pa 4 | ||
| 151 | #define REG_WR_ADDR_pinmux_rw_gio_pa 4 | ||
| 152 | |||
| 153 | /* Register rw_gio_pb, scope pinmux, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int pb0 : 1; | ||
| 156 | unsigned int pb1 : 1; | ||
| 157 | unsigned int pb2 : 1; | ||
| 158 | unsigned int pb3 : 1; | ||
| 159 | unsigned int pb4 : 1; | ||
| 160 | unsigned int pb5 : 1; | ||
| 161 | unsigned int pb6 : 1; | ||
| 162 | unsigned int pb7 : 1; | ||
| 163 | unsigned int pb8 : 1; | ||
| 164 | unsigned int pb9 : 1; | ||
| 165 | unsigned int pb10 : 1; | ||
| 166 | unsigned int pb11 : 1; | ||
| 167 | unsigned int pb12 : 1; | ||
| 168 | unsigned int pb13 : 1; | ||
| 169 | unsigned int pb14 : 1; | ||
| 170 | unsigned int pb15 : 1; | ||
| 171 | unsigned int pb16 : 1; | ||
| 172 | unsigned int pb17 : 1; | ||
| 173 | unsigned int pb18 : 1; | ||
| 174 | unsigned int pb19 : 1; | ||
| 175 | unsigned int pb20 : 1; | ||
| 176 | unsigned int pb21 : 1; | ||
| 177 | unsigned int pb22 : 1; | ||
| 178 | unsigned int pb23 : 1; | ||
| 179 | unsigned int pb24 : 1; | ||
| 180 | unsigned int pb25 : 1; | ||
| 181 | unsigned int pb26 : 1; | ||
| 182 | unsigned int pb27 : 1; | ||
| 183 | unsigned int pb28 : 1; | ||
| 184 | unsigned int pb29 : 1; | ||
| 185 | unsigned int pb30 : 1; | ||
| 186 | unsigned int pb31 : 1; | ||
| 187 | } reg_pinmux_rw_gio_pb; | ||
| 188 | #define REG_RD_ADDR_pinmux_rw_gio_pb 8 | ||
| 189 | #define REG_WR_ADDR_pinmux_rw_gio_pb 8 | ||
| 190 | |||
| 191 | /* Register rw_gio_pc, scope pinmux, type rw */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int pc0 : 1; | ||
| 194 | unsigned int pc1 : 1; | ||
| 195 | unsigned int pc2 : 1; | ||
| 196 | unsigned int pc3 : 1; | ||
| 197 | unsigned int pc4 : 1; | ||
| 198 | unsigned int pc5 : 1; | ||
| 199 | unsigned int pc6 : 1; | ||
| 200 | unsigned int pc7 : 1; | ||
| 201 | unsigned int pc8 : 1; | ||
| 202 | unsigned int pc9 : 1; | ||
| 203 | unsigned int pc10 : 1; | ||
| 204 | unsigned int pc11 : 1; | ||
| 205 | unsigned int pc12 : 1; | ||
| 206 | unsigned int pc13 : 1; | ||
| 207 | unsigned int pc14 : 1; | ||
| 208 | unsigned int pc15 : 1; | ||
| 209 | unsigned int dummy1 : 16; | ||
| 210 | } reg_pinmux_rw_gio_pc; | ||
| 211 | #define REG_RD_ADDR_pinmux_rw_gio_pc 12 | ||
| 212 | #define REG_WR_ADDR_pinmux_rw_gio_pc 12 | ||
| 213 | |||
| 214 | /* Register rw_iop_pa, scope pinmux, type rw */ | ||
| 215 | typedef struct { | ||
| 216 | unsigned int pa0 : 1; | ||
| 217 | unsigned int pa1 : 1; | ||
| 218 | unsigned int pa2 : 1; | ||
| 219 | unsigned int pa3 : 1; | ||
| 220 | unsigned int pa4 : 1; | ||
| 221 | unsigned int pa5 : 1; | ||
| 222 | unsigned int pa6 : 1; | ||
| 223 | unsigned int pa7 : 1; | ||
| 224 | unsigned int pa8 : 1; | ||
| 225 | unsigned int pa9 : 1; | ||
| 226 | unsigned int pa10 : 1; | ||
| 227 | unsigned int pa11 : 1; | ||
| 228 | unsigned int pa12 : 1; | ||
| 229 | unsigned int pa13 : 1; | ||
| 230 | unsigned int pa14 : 1; | ||
| 231 | unsigned int pa15 : 1; | ||
| 232 | unsigned int pa16 : 1; | ||
| 233 | unsigned int pa17 : 1; | ||
| 234 | unsigned int pa18 : 1; | ||
| 235 | unsigned int pa19 : 1; | ||
| 236 | unsigned int pa20 : 1; | ||
| 237 | unsigned int pa21 : 1; | ||
| 238 | unsigned int pa22 : 1; | ||
| 239 | unsigned int pa23 : 1; | ||
| 240 | unsigned int pa24 : 1; | ||
| 241 | unsigned int pa25 : 1; | ||
| 242 | unsigned int pa26 : 1; | ||
| 243 | unsigned int pa27 : 1; | ||
| 244 | unsigned int pa28 : 1; | ||
| 245 | unsigned int pa29 : 1; | ||
| 246 | unsigned int pa30 : 1; | ||
| 247 | unsigned int pa31 : 1; | ||
| 248 | } reg_pinmux_rw_iop_pa; | ||
| 249 | #define REG_RD_ADDR_pinmux_rw_iop_pa 16 | ||
| 250 | #define REG_WR_ADDR_pinmux_rw_iop_pa 16 | ||
| 251 | |||
| 252 | /* Register rw_iop_pb, scope pinmux, type rw */ | ||
| 253 | typedef struct { | ||
| 254 | unsigned int pb0 : 1; | ||
| 255 | unsigned int pb1 : 1; | ||
| 256 | unsigned int pb2 : 1; | ||
| 257 | unsigned int pb3 : 1; | ||
| 258 | unsigned int pb4 : 1; | ||
| 259 | unsigned int pb5 : 1; | ||
| 260 | unsigned int pb6 : 1; | ||
| 261 | unsigned int pb7 : 1; | ||
| 262 | unsigned int dummy1 : 24; | ||
| 263 | } reg_pinmux_rw_iop_pb; | ||
| 264 | #define REG_RD_ADDR_pinmux_rw_iop_pb 20 | ||
| 265 | #define REG_WR_ADDR_pinmux_rw_iop_pb 20 | ||
| 266 | |||
| 267 | /* Register rw_iop_pio, scope pinmux, type rw */ | ||
| 268 | typedef struct { | ||
| 269 | unsigned int d0 : 1; | ||
| 270 | unsigned int d1 : 1; | ||
| 271 | unsigned int d2 : 1; | ||
| 272 | unsigned int d3 : 1; | ||
| 273 | unsigned int d4 : 1; | ||
| 274 | unsigned int d5 : 1; | ||
| 275 | unsigned int d6 : 1; | ||
| 276 | unsigned int d7 : 1; | ||
| 277 | unsigned int rd_n : 1; | ||
| 278 | unsigned int wr_n : 1; | ||
| 279 | unsigned int a0 : 1; | ||
| 280 | unsigned int a1 : 1; | ||
| 281 | unsigned int ce0_n : 1; | ||
| 282 | unsigned int ce1_n : 1; | ||
| 283 | unsigned int ce2_n : 1; | ||
| 284 | unsigned int rdy : 1; | ||
| 285 | unsigned int dummy1 : 16; | ||
| 286 | } reg_pinmux_rw_iop_pio; | ||
| 287 | #define REG_RD_ADDR_pinmux_rw_iop_pio 24 | ||
| 288 | #define REG_WR_ADDR_pinmux_rw_iop_pio 24 | ||
| 289 | |||
| 290 | /* Register rw_iop_usb, scope pinmux, type rw */ | ||
| 291 | typedef struct { | ||
| 292 | unsigned int usb0 : 1; | ||
| 293 | unsigned int dummy1 : 31; | ||
| 294 | } reg_pinmux_rw_iop_usb; | ||
| 295 | #define REG_RD_ADDR_pinmux_rw_iop_usb 28 | ||
| 296 | #define REG_WR_ADDR_pinmux_rw_iop_usb 28 | ||
| 297 | |||
| 298 | |||
| 299 | /* Constants */ | ||
| 300 | enum { | ||
| 301 | regk_pinmux_no = 0x00000000, | ||
| 302 | regk_pinmux_rw_gio_pa_default = 0x00000000, | ||
| 303 | regk_pinmux_rw_gio_pb_default = 0x00000000, | ||
| 304 | regk_pinmux_rw_gio_pc_default = 0x00000000, | ||
| 305 | regk_pinmux_rw_hwprot_default = 0x00000000, | ||
| 306 | regk_pinmux_rw_iop_pa_default = 0x00000000, | ||
| 307 | regk_pinmux_rw_iop_pb_default = 0x00000000, | ||
| 308 | regk_pinmux_rw_iop_pio_default = 0x00000000, | ||
| 309 | regk_pinmux_rw_iop_usb_default = 0x00000001, | ||
| 310 | regk_pinmux_yes = 0x00000001 | ||
| 311 | }; | ||
| 312 | #endif /* __pinmux_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h new file mode 100644 index 000000000000..2d8e4b4cc602 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/pio_defs.h | |||
| @@ -0,0 +1,371 @@ | |||
| 1 | #ifndef __pio_defs_h | ||
| 2 | #define __pio_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: pio.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope pio */ | ||
| 83 | |||
| 84 | /* Register rw_data, scope pio, type rw */ | ||
| 85 | typedef unsigned int reg_pio_rw_data; | ||
| 86 | #define REG_RD_ADDR_pio_rw_data 64 | ||
| 87 | #define REG_WR_ADDR_pio_rw_data 64 | ||
| 88 | |||
| 89 | /* Register rw_io_access0, scope pio, type rw */ | ||
| 90 | typedef struct { | ||
| 91 | unsigned int data : 8; | ||
| 92 | unsigned int dummy1 : 24; | ||
| 93 | } reg_pio_rw_io_access0; | ||
| 94 | #define REG_RD_ADDR_pio_rw_io_access0 0 | ||
| 95 | #define REG_WR_ADDR_pio_rw_io_access0 0 | ||
| 96 | |||
| 97 | /* Register rw_io_access1, scope pio, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int data : 8; | ||
| 100 | unsigned int dummy1 : 24; | ||
| 101 | } reg_pio_rw_io_access1; | ||
| 102 | #define REG_RD_ADDR_pio_rw_io_access1 4 | ||
| 103 | #define REG_WR_ADDR_pio_rw_io_access1 4 | ||
| 104 | |||
| 105 | /* Register rw_io_access2, scope pio, type rw */ | ||
| 106 | typedef struct { | ||
| 107 | unsigned int data : 8; | ||
| 108 | unsigned int dummy1 : 24; | ||
| 109 | } reg_pio_rw_io_access2; | ||
| 110 | #define REG_RD_ADDR_pio_rw_io_access2 8 | ||
| 111 | #define REG_WR_ADDR_pio_rw_io_access2 8 | ||
| 112 | |||
| 113 | /* Register rw_io_access3, scope pio, type rw */ | ||
| 114 | typedef struct { | ||
| 115 | unsigned int data : 8; | ||
| 116 | unsigned int dummy1 : 24; | ||
| 117 | } reg_pio_rw_io_access3; | ||
| 118 | #define REG_RD_ADDR_pio_rw_io_access3 12 | ||
| 119 | #define REG_WR_ADDR_pio_rw_io_access3 12 | ||
| 120 | |||
| 121 | /* Register rw_io_access4, scope pio, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int data : 8; | ||
| 124 | unsigned int dummy1 : 24; | ||
| 125 | } reg_pio_rw_io_access4; | ||
| 126 | #define REG_RD_ADDR_pio_rw_io_access4 16 | ||
| 127 | #define REG_WR_ADDR_pio_rw_io_access4 16 | ||
| 128 | |||
| 129 | /* Register rw_io_access5, scope pio, type rw */ | ||
| 130 | typedef struct { | ||
| 131 | unsigned int data : 8; | ||
| 132 | unsigned int dummy1 : 24; | ||
| 133 | } reg_pio_rw_io_access5; | ||
| 134 | #define REG_RD_ADDR_pio_rw_io_access5 20 | ||
| 135 | #define REG_WR_ADDR_pio_rw_io_access5 20 | ||
| 136 | |||
| 137 | /* Register rw_io_access6, scope pio, type rw */ | ||
| 138 | typedef struct { | ||
| 139 | unsigned int data : 8; | ||
| 140 | unsigned int dummy1 : 24; | ||
| 141 | } reg_pio_rw_io_access6; | ||
| 142 | #define REG_RD_ADDR_pio_rw_io_access6 24 | ||
| 143 | #define REG_WR_ADDR_pio_rw_io_access6 24 | ||
| 144 | |||
| 145 | /* Register rw_io_access7, scope pio, type rw */ | ||
| 146 | typedef struct { | ||
| 147 | unsigned int data : 8; | ||
| 148 | unsigned int dummy1 : 24; | ||
| 149 | } reg_pio_rw_io_access7; | ||
| 150 | #define REG_RD_ADDR_pio_rw_io_access7 28 | ||
| 151 | #define REG_WR_ADDR_pio_rw_io_access7 28 | ||
| 152 | |||
| 153 | /* Register rw_io_access8, scope pio, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int data : 8; | ||
| 156 | unsigned int dummy1 : 24; | ||
| 157 | } reg_pio_rw_io_access8; | ||
| 158 | #define REG_RD_ADDR_pio_rw_io_access8 32 | ||
| 159 | #define REG_WR_ADDR_pio_rw_io_access8 32 | ||
| 160 | |||
| 161 | /* Register rw_io_access9, scope pio, type rw */ | ||
| 162 | typedef struct { | ||
| 163 | unsigned int data : 8; | ||
| 164 | unsigned int dummy1 : 24; | ||
| 165 | } reg_pio_rw_io_access9; | ||
| 166 | #define REG_RD_ADDR_pio_rw_io_access9 36 | ||
| 167 | #define REG_WR_ADDR_pio_rw_io_access9 36 | ||
| 168 | |||
| 169 | /* Register rw_io_access10, scope pio, type rw */ | ||
| 170 | typedef struct { | ||
| 171 | unsigned int data : 8; | ||
| 172 | unsigned int dummy1 : 24; | ||
| 173 | } reg_pio_rw_io_access10; | ||
| 174 | #define REG_RD_ADDR_pio_rw_io_access10 40 | ||
| 175 | #define REG_WR_ADDR_pio_rw_io_access10 40 | ||
| 176 | |||
| 177 | /* Register rw_io_access11, scope pio, type rw */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int data : 8; | ||
| 180 | unsigned int dummy1 : 24; | ||
| 181 | } reg_pio_rw_io_access11; | ||
| 182 | #define REG_RD_ADDR_pio_rw_io_access11 44 | ||
| 183 | #define REG_WR_ADDR_pio_rw_io_access11 44 | ||
| 184 | |||
| 185 | /* Register rw_io_access12, scope pio, type rw */ | ||
| 186 | typedef struct { | ||
| 187 | unsigned int data : 8; | ||
| 188 | unsigned int dummy1 : 24; | ||
| 189 | } reg_pio_rw_io_access12; | ||
| 190 | #define REG_RD_ADDR_pio_rw_io_access12 48 | ||
| 191 | #define REG_WR_ADDR_pio_rw_io_access12 48 | ||
| 192 | |||
| 193 | /* Register rw_io_access13, scope pio, type rw */ | ||
| 194 | typedef struct { | ||
| 195 | unsigned int data : 8; | ||
| 196 | unsigned int dummy1 : 24; | ||
| 197 | } reg_pio_rw_io_access13; | ||
| 198 | #define REG_RD_ADDR_pio_rw_io_access13 52 | ||
| 199 | #define REG_WR_ADDR_pio_rw_io_access13 52 | ||
| 200 | |||
| 201 | /* Register rw_io_access14, scope pio, type rw */ | ||
| 202 | typedef struct { | ||
| 203 | unsigned int data : 8; | ||
| 204 | unsigned int dummy1 : 24; | ||
| 205 | } reg_pio_rw_io_access14; | ||
| 206 | #define REG_RD_ADDR_pio_rw_io_access14 56 | ||
| 207 | #define REG_WR_ADDR_pio_rw_io_access14 56 | ||
| 208 | |||
| 209 | /* Register rw_io_access15, scope pio, type rw */ | ||
| 210 | typedef struct { | ||
| 211 | unsigned int data : 8; | ||
| 212 | unsigned int dummy1 : 24; | ||
| 213 | } reg_pio_rw_io_access15; | ||
| 214 | #define REG_RD_ADDR_pio_rw_io_access15 60 | ||
| 215 | #define REG_WR_ADDR_pio_rw_io_access15 60 | ||
| 216 | |||
| 217 | /* Register rw_ce0_cfg, scope pio, type rw */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int lw : 6; | ||
| 220 | unsigned int ew : 3; | ||
| 221 | unsigned int zw : 3; | ||
| 222 | unsigned int aw : 2; | ||
| 223 | unsigned int mode : 2; | ||
| 224 | unsigned int dummy1 : 16; | ||
| 225 | } reg_pio_rw_ce0_cfg; | ||
| 226 | #define REG_RD_ADDR_pio_rw_ce0_cfg 68 | ||
| 227 | #define REG_WR_ADDR_pio_rw_ce0_cfg 68 | ||
| 228 | |||
| 229 | /* Register rw_ce1_cfg, scope pio, type rw */ | ||
| 230 | typedef struct { | ||
| 231 | unsigned int lw : 6; | ||
| 232 | unsigned int ew : 3; | ||
| 233 | unsigned int zw : 3; | ||
| 234 | unsigned int aw : 2; | ||
| 235 | unsigned int mode : 2; | ||
| 236 | unsigned int dummy1 : 16; | ||
| 237 | } reg_pio_rw_ce1_cfg; | ||
| 238 | #define REG_RD_ADDR_pio_rw_ce1_cfg 72 | ||
| 239 | #define REG_WR_ADDR_pio_rw_ce1_cfg 72 | ||
| 240 | |||
| 241 | /* Register rw_ce2_cfg, scope pio, type rw */ | ||
| 242 | typedef struct { | ||
| 243 | unsigned int lw : 6; | ||
| 244 | unsigned int ew : 3; | ||
| 245 | unsigned int zw : 3; | ||
| 246 | unsigned int aw : 2; | ||
| 247 | unsigned int mode : 2; | ||
| 248 | unsigned int dummy1 : 16; | ||
| 249 | } reg_pio_rw_ce2_cfg; | ||
| 250 | #define REG_RD_ADDR_pio_rw_ce2_cfg 76 | ||
| 251 | #define REG_WR_ADDR_pio_rw_ce2_cfg 76 | ||
| 252 | |||
| 253 | /* Register rw_dout, scope pio, type rw */ | ||
| 254 | typedef struct { | ||
| 255 | unsigned int data : 8; | ||
| 256 | unsigned int rd_n : 1; | ||
| 257 | unsigned int wr_n : 1; | ||
| 258 | unsigned int a0 : 1; | ||
| 259 | unsigned int a1 : 1; | ||
| 260 | unsigned int ce0_n : 1; | ||
| 261 | unsigned int ce1_n : 1; | ||
| 262 | unsigned int ce2_n : 1; | ||
| 263 | unsigned int rdy : 1; | ||
| 264 | unsigned int dummy1 : 16; | ||
| 265 | } reg_pio_rw_dout; | ||
| 266 | #define REG_RD_ADDR_pio_rw_dout 80 | ||
| 267 | #define REG_WR_ADDR_pio_rw_dout 80 | ||
| 268 | |||
| 269 | /* Register rw_oe, scope pio, type rw */ | ||
| 270 | typedef struct { | ||
| 271 | unsigned int data : 8; | ||
| 272 | unsigned int rd_n : 1; | ||
| 273 | unsigned int wr_n : 1; | ||
| 274 | unsigned int a0 : 1; | ||
| 275 | unsigned int a1 : 1; | ||
| 276 | unsigned int ce0_n : 1; | ||
| 277 | unsigned int ce1_n : 1; | ||
| 278 | unsigned int ce2_n : 1; | ||
| 279 | unsigned int rdy : 1; | ||
| 280 | unsigned int dummy1 : 16; | ||
| 281 | } reg_pio_rw_oe; | ||
| 282 | #define REG_RD_ADDR_pio_rw_oe 84 | ||
| 283 | #define REG_WR_ADDR_pio_rw_oe 84 | ||
| 284 | |||
| 285 | /* Register rw_man_ctrl, scope pio, type rw */ | ||
| 286 | typedef struct { | ||
| 287 | unsigned int data : 8; | ||
| 288 | unsigned int rd_n : 1; | ||
| 289 | unsigned int wr_n : 1; | ||
| 290 | unsigned int a0 : 1; | ||
| 291 | unsigned int a1 : 1; | ||
| 292 | unsigned int ce0_n : 1; | ||
| 293 | unsigned int ce1_n : 1; | ||
| 294 | unsigned int ce2_n : 1; | ||
| 295 | unsigned int rdy : 1; | ||
| 296 | unsigned int dummy1 : 16; | ||
| 297 | } reg_pio_rw_man_ctrl; | ||
| 298 | #define REG_RD_ADDR_pio_rw_man_ctrl 88 | ||
| 299 | #define REG_WR_ADDR_pio_rw_man_ctrl 88 | ||
| 300 | |||
| 301 | /* Register r_din, scope pio, type r */ | ||
| 302 | typedef struct { | ||
| 303 | unsigned int data : 8; | ||
| 304 | unsigned int rd_n : 1; | ||
| 305 | unsigned int wr_n : 1; | ||
| 306 | unsigned int a0 : 1; | ||
| 307 | unsigned int a1 : 1; | ||
| 308 | unsigned int ce0_n : 1; | ||
| 309 | unsigned int ce1_n : 1; | ||
| 310 | unsigned int ce2_n : 1; | ||
| 311 | unsigned int rdy : 1; | ||
| 312 | unsigned int dummy1 : 16; | ||
| 313 | } reg_pio_r_din; | ||
| 314 | #define REG_RD_ADDR_pio_r_din 92 | ||
| 315 | |||
| 316 | /* Register r_stat, scope pio, type r */ | ||
| 317 | typedef struct { | ||
| 318 | unsigned int busy : 1; | ||
| 319 | unsigned int dummy1 : 31; | ||
| 320 | } reg_pio_r_stat; | ||
| 321 | #define REG_RD_ADDR_pio_r_stat 96 | ||
| 322 | |||
| 323 | /* Register rw_intr_mask, scope pio, type rw */ | ||
| 324 | typedef struct { | ||
| 325 | unsigned int rdy : 1; | ||
| 326 | unsigned int dummy1 : 31; | ||
| 327 | } reg_pio_rw_intr_mask; | ||
| 328 | #define REG_RD_ADDR_pio_rw_intr_mask 100 | ||
| 329 | #define REG_WR_ADDR_pio_rw_intr_mask 100 | ||
| 330 | |||
| 331 | /* Register rw_ack_intr, scope pio, type rw */ | ||
| 332 | typedef struct { | ||
| 333 | unsigned int rdy : 1; | ||
| 334 | unsigned int dummy1 : 31; | ||
| 335 | } reg_pio_rw_ack_intr; | ||
| 336 | #define REG_RD_ADDR_pio_rw_ack_intr 104 | ||
| 337 | #define REG_WR_ADDR_pio_rw_ack_intr 104 | ||
| 338 | |||
| 339 | /* Register r_intr, scope pio, type r */ | ||
| 340 | typedef struct { | ||
| 341 | unsigned int rdy : 1; | ||
| 342 | unsigned int dummy1 : 31; | ||
| 343 | } reg_pio_r_intr; | ||
| 344 | #define REG_RD_ADDR_pio_r_intr 108 | ||
| 345 | |||
| 346 | /* Register r_masked_intr, scope pio, type r */ | ||
| 347 | typedef struct { | ||
| 348 | unsigned int rdy : 1; | ||
| 349 | unsigned int dummy1 : 31; | ||
| 350 | } reg_pio_r_masked_intr; | ||
| 351 | #define REG_RD_ADDR_pio_r_masked_intr 112 | ||
| 352 | |||
| 353 | |||
| 354 | /* Constants */ | ||
| 355 | enum { | ||
| 356 | regk_pio_a2 = 0x00000003, | ||
| 357 | regk_pio_no = 0x00000000, | ||
| 358 | regk_pio_normal = 0x00000000, | ||
| 359 | regk_pio_rd = 0x00000001, | ||
| 360 | regk_pio_rw_ce0_cfg_default = 0x00000000, | ||
| 361 | regk_pio_rw_ce1_cfg_default = 0x00000000, | ||
| 362 | regk_pio_rw_ce2_cfg_default = 0x00000000, | ||
| 363 | regk_pio_rw_intr_mask_default = 0x00000000, | ||
| 364 | regk_pio_rw_man_ctrl_default = 0x00000000, | ||
| 365 | regk_pio_rw_oe_default = 0x00000000, | ||
| 366 | regk_pio_wr = 0x00000002, | ||
| 367 | regk_pio_wr_ce2 = 0x00000003, | ||
| 368 | regk_pio_yes = 0x00000001, | ||
| 369 | regk_pio_yes_all = 0x000000ff | ||
| 370 | }; | ||
| 371 | #endif /* __pio_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h new file mode 100644 index 000000000000..36e59d6e96b6 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/reg_map.h | |||
| @@ -0,0 +1,103 @@ | |||
| 1 | #ifndef __reg_map_h | ||
| 2 | #define __reg_map_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: reg.rmap | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | typedef enum { | ||
| 14 | regi_ccd = 0xb0000000, | ||
| 15 | regi_ccd_top = 0xb0000000, | ||
| 16 | regi_ccd_dp = 0xb0000400, | ||
| 17 | regi_ccd_stat = 0xb0000800, | ||
| 18 | regi_ccd_tg = 0xb0001000, | ||
| 19 | regi_cfg = 0xb0002000, | ||
| 20 | regi_clkgen = 0xb0004000, | ||
| 21 | regi_ddr2_ctrl = 0xb0006000, | ||
| 22 | regi_dma0 = 0xb0008000, | ||
| 23 | regi_dma1 = 0xb000a000, | ||
| 24 | regi_dma11 = 0xb000c000, | ||
| 25 | regi_dma2 = 0xb000e000, | ||
| 26 | regi_dma3 = 0xb0010000, | ||
| 27 | regi_dma4 = 0xb0012000, | ||
| 28 | regi_dma5 = 0xb0014000, | ||
| 29 | regi_dma6 = 0xb0016000, | ||
| 30 | regi_dma7 = 0xb0018000, | ||
| 31 | regi_dma9 = 0xb001a000, | ||
| 32 | regi_eth = 0xb001c000, | ||
| 33 | regi_gio = 0xb0020000, | ||
| 34 | regi_h264 = 0xb0022000, | ||
| 35 | regi_hist = 0xb0026000, | ||
| 36 | regi_iop = 0xb0028000, | ||
| 37 | regi_iop_version = 0xb0028000, | ||
| 38 | regi_iop_fifo_in_extra = 0xb0028040, | ||
| 39 | regi_iop_fifo_out_extra = 0xb0028080, | ||
| 40 | regi_iop_trigger_grp0 = 0xb00280c0, | ||
| 41 | regi_iop_trigger_grp1 = 0xb0028100, | ||
| 42 | regi_iop_trigger_grp2 = 0xb0028140, | ||
| 43 | regi_iop_trigger_grp3 = 0xb0028180, | ||
| 44 | regi_iop_trigger_grp4 = 0xb00281c0, | ||
| 45 | regi_iop_trigger_grp5 = 0xb0028200, | ||
| 46 | regi_iop_trigger_grp6 = 0xb0028240, | ||
| 47 | regi_iop_trigger_grp7 = 0xb0028280, | ||
| 48 | regi_iop_crc_par = 0xb0028300, | ||
| 49 | regi_iop_dmc_in = 0xb0028380, | ||
| 50 | regi_iop_dmc_out = 0xb0028400, | ||
| 51 | regi_iop_fifo_in = 0xb0028480, | ||
| 52 | regi_iop_fifo_out = 0xb0028500, | ||
| 53 | regi_iop_scrc_in = 0xb0028580, | ||
| 54 | regi_iop_scrc_out = 0xb0028600, | ||
| 55 | regi_iop_timer_grp0 = 0xb0028680, | ||
| 56 | regi_iop_timer_grp1 = 0xb0028700, | ||
| 57 | regi_iop_sap_in = 0xb0028800, | ||
| 58 | regi_iop_sap_out = 0xb0028900, | ||
| 59 | regi_iop_spu = 0xb0028a00, | ||
| 60 | regi_iop_sw_cfg = 0xb0028b00, | ||
| 61 | regi_iop_sw_cpu = 0xb0028c00, | ||
| 62 | regi_iop_sw_mpu = 0xb0028d00, | ||
| 63 | regi_iop_sw_spu = 0xb0028e00, | ||
| 64 | regi_iop_mpu = 0xb0029000, | ||
| 65 | regi_irq = 0xb002a000, | ||
| 66 | regi_irq2 = 0xb006a000, | ||
| 67 | regi_jpeg = 0xb002c000, | ||
| 68 | regi_l2cache = 0xb0030000, | ||
| 69 | regi_marb_bar = 0xb0032000, | ||
| 70 | regi_marb_bar_bp0 = 0xb0032140, | ||
| 71 | regi_marb_bar_bp1 = 0xb0032180, | ||
| 72 | regi_marb_bar_bp2 = 0xb00321c0, | ||
| 73 | regi_marb_bar_bp3 = 0xb0032200, | ||
| 74 | regi_marb_foo = 0xb0034000, | ||
| 75 | regi_marb_foo_bp0 = 0xb0034280, | ||
| 76 | regi_marb_foo_bp1 = 0xb00342c0, | ||
| 77 | regi_marb_foo_bp2 = 0xb0034300, | ||
| 78 | regi_marb_foo_bp3 = 0xb0034340, | ||
| 79 | regi_pinmux = 0xb0038000, | ||
| 80 | regi_pio = 0xb0036000, | ||
| 81 | regi_sclr = 0xb003a000, | ||
| 82 | regi_sclr_fifo = 0xb003c000, | ||
| 83 | regi_ser0 = 0xb003e000, | ||
| 84 | regi_ser1 = 0xb0040000, | ||
| 85 | regi_ser2 = 0xb0042000, | ||
| 86 | regi_ser3 = 0xb0044000, | ||
| 87 | regi_ser4 = 0xb0046000, | ||
| 88 | regi_sser = 0xb0048000, | ||
| 89 | regi_strcop = 0xb004a000, | ||
| 90 | regi_strdma0 = 0xb004e000, | ||
| 91 | regi_strdma1 = 0xb0050000, | ||
| 92 | regi_strdma2 = 0xb0052000, | ||
| 93 | regi_strdma3 = 0xb0054000, | ||
| 94 | regi_strdma5 = 0xb0056000, | ||
| 95 | regi_strmux = 0xb004c000, | ||
| 96 | regi_timer0 = 0xb0058000, | ||
| 97 | regi_timer1 = 0xb005a000, | ||
| 98 | regi_timer2 = 0xb006e000, | ||
| 99 | regi_trace = 0xb005c000, | ||
| 100 | regi_vin = 0xb005e000, | ||
| 101 | regi_vout = 0xb0060000 | ||
| 102 | } reg_scope_instances; | ||
| 103 | #endif /* __reg_map_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h new file mode 100644 index 000000000000..14f718a4ecc3 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/strmux_defs.h | |||
| @@ -0,0 +1,120 @@ | |||
| 1 | #ifndef __strmux_defs_h | ||
| 2 | #define __strmux_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: strmux.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope strmux */ | ||
| 83 | |||
| 84 | /* Register rw_cfg, scope strmux, type rw */ | ||
| 85 | typedef struct { | ||
| 86 | unsigned int dma0 : 2; | ||
| 87 | unsigned int dma1 : 2; | ||
| 88 | unsigned int dma2 : 2; | ||
| 89 | unsigned int dma3 : 2; | ||
| 90 | unsigned int dma4 : 2; | ||
| 91 | unsigned int dma5 : 2; | ||
| 92 | unsigned int dma6 : 2; | ||
| 93 | unsigned int dma7 : 2; | ||
| 94 | unsigned int dummy1 : 2; | ||
| 95 | unsigned int dma9 : 2; | ||
| 96 | unsigned int dummy2 : 2; | ||
| 97 | unsigned int dma11 : 2; | ||
| 98 | unsigned int dummy3 : 8; | ||
| 99 | } reg_strmux_rw_cfg; | ||
| 100 | #define REG_RD_ADDR_strmux_rw_cfg 0 | ||
| 101 | #define REG_WR_ADDR_strmux_rw_cfg 0 | ||
| 102 | |||
| 103 | |||
| 104 | /* Constants */ | ||
| 105 | enum { | ||
| 106 | regk_strmux_eth = 0x00000001, | ||
| 107 | regk_strmux_h264 = 0x00000001, | ||
| 108 | regk_strmux_iop = 0x00000001, | ||
| 109 | regk_strmux_jpeg = 0x00000001, | ||
| 110 | regk_strmux_off = 0x00000000, | ||
| 111 | regk_strmux_rw_cfg_default = 0x00000000, | ||
| 112 | regk_strmux_ser0 = 0x00000002, | ||
| 113 | regk_strmux_ser1 = 0x00000002, | ||
| 114 | regk_strmux_ser2 = 0x00000002, | ||
| 115 | regk_strmux_ser3 = 0x00000002, | ||
| 116 | regk_strmux_ser4 = 0x00000002, | ||
| 117 | regk_strmux_sser = 0x00000001, | ||
| 118 | regk_strmux_strcop = 0x00000001 | ||
| 119 | }; | ||
| 120 | #endif /* __strmux_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h new file mode 100644 index 000000000000..2c33e097d60a --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/hwregs/timer_defs.h | |||
| @@ -0,0 +1,265 @@ | |||
| 1 | #ifndef __timer_defs_h | ||
| 2 | #define __timer_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: timer.r | ||
| 7 | * | ||
| 8 | * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r | ||
| 9 | * Any changes here will be lost. | ||
| 10 | * | ||
| 11 | * -*- buffer-read-only: t -*- | ||
| 12 | */ | ||
| 13 | /* Main access macros */ | ||
| 14 | #ifndef REG_RD | ||
| 15 | #define REG_RD( scope, inst, reg ) \ | ||
| 16 | REG_READ( reg_##scope##_##reg, \ | ||
| 17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef REG_WR | ||
| 21 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 22 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifndef REG_RD_VECT | ||
| 27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 28 | REG_READ( reg_##scope##_##reg, \ | ||
| 29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 30 | (index) * STRIDE_##scope##_##reg ) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | #ifndef REG_WR_VECT | ||
| 34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 35 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 37 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #ifndef REG_RD_INT | ||
| 41 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #ifndef REG_WR_INT | ||
| 46 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #ifndef REG_RD_INT_VECT | ||
| 51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 53 | (index) * STRIDE_##scope##_##reg ) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | #ifndef REG_WR_INT_VECT | ||
| 57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 59 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 60 | #endif | ||
| 61 | |||
| 62 | #ifndef REG_TYPE_CONV | ||
| 63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifndef reg_page_size | ||
| 68 | #define reg_page_size 8192 | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #ifndef REG_ADDR | ||
| 72 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #ifndef REG_ADDR_VECT | ||
| 77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 79 | (index) * STRIDE_##scope##_##reg ) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | /* C-code for register scope timer */ | ||
| 83 | |||
| 84 | /* Register rw_tmr0_div, scope timer, type rw */ | ||
| 85 | typedef unsigned int reg_timer_rw_tmr0_div; | ||
| 86 | #define REG_RD_ADDR_timer_rw_tmr0_div 0 | ||
| 87 | #define REG_WR_ADDR_timer_rw_tmr0_div 0 | ||
| 88 | |||
| 89 | /* Register r_tmr0_data, scope timer, type r */ | ||
| 90 | typedef unsigned int reg_timer_r_tmr0_data; | ||
| 91 | #define REG_RD_ADDR_timer_r_tmr0_data 4 | ||
| 92 | |||
| 93 | /* Register rw_tmr0_ctrl, scope timer, type rw */ | ||
| 94 | typedef struct { | ||
| 95 | unsigned int op : 2; | ||
| 96 | unsigned int freq : 3; | ||
| 97 | unsigned int dummy1 : 27; | ||
| 98 | } reg_timer_rw_tmr0_ctrl; | ||
| 99 | #define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 | ||
| 100 | #define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 | ||
| 101 | |||
| 102 | /* Register rw_tmr1_div, scope timer, type rw */ | ||
| 103 | typedef unsigned int reg_timer_rw_tmr1_div; | ||
| 104 | #define REG_RD_ADDR_timer_rw_tmr1_div 16 | ||
| 105 | #define REG_WR_ADDR_timer_rw_tmr1_div 16 | ||
| 106 | |||
| 107 | /* Register r_tmr1_data, scope timer, type r */ | ||
| 108 | typedef unsigned int reg_timer_r_tmr1_data; | ||
| 109 | #define REG_RD_ADDR_timer_r_tmr1_data 20 | ||
| 110 | |||
| 111 | /* Register rw_tmr1_ctrl, scope timer, type rw */ | ||
| 112 | typedef struct { | ||
| 113 | unsigned int op : 2; | ||
| 114 | unsigned int freq : 3; | ||
| 115 | unsigned int dummy1 : 27; | ||
| 116 | } reg_timer_rw_tmr1_ctrl; | ||
| 117 | #define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 | ||
| 118 | #define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 | ||
| 119 | |||
| 120 | /* Register rs_cnt_data, scope timer, type rs */ | ||
| 121 | typedef struct { | ||
| 122 | unsigned int tmr : 24; | ||
| 123 | unsigned int cnt : 8; | ||
| 124 | } reg_timer_rs_cnt_data; | ||
| 125 | #define REG_RD_ADDR_timer_rs_cnt_data 32 | ||
| 126 | |||
| 127 | /* Register r_cnt_data, scope timer, type r */ | ||
| 128 | typedef struct { | ||
| 129 | unsigned int tmr : 24; | ||
| 130 | unsigned int cnt : 8; | ||
| 131 | } reg_timer_r_cnt_data; | ||
| 132 | #define REG_RD_ADDR_timer_r_cnt_data 36 | ||
| 133 | |||
| 134 | /* Register rw_cnt_cfg, scope timer, type rw */ | ||
| 135 | typedef struct { | ||
| 136 | unsigned int clk : 2; | ||
| 137 | unsigned int dummy1 : 30; | ||
| 138 | } reg_timer_rw_cnt_cfg; | ||
| 139 | #define REG_RD_ADDR_timer_rw_cnt_cfg 40 | ||
| 140 | #define REG_WR_ADDR_timer_rw_cnt_cfg 40 | ||
| 141 | |||
| 142 | /* Register rw_trig, scope timer, type rw */ | ||
| 143 | typedef unsigned int reg_timer_rw_trig; | ||
| 144 | #define REG_RD_ADDR_timer_rw_trig 48 | ||
| 145 | #define REG_WR_ADDR_timer_rw_trig 48 | ||
| 146 | |||
| 147 | /* Register rw_trig_cfg, scope timer, type rw */ | ||
| 148 | typedef struct { | ||
| 149 | unsigned int tmr : 2; | ||
| 150 | unsigned int dummy1 : 30; | ||
| 151 | } reg_timer_rw_trig_cfg; | ||
| 152 | #define REG_RD_ADDR_timer_rw_trig_cfg 52 | ||
| 153 | #define REG_WR_ADDR_timer_rw_trig_cfg 52 | ||
| 154 | |||
| 155 | /* Register r_time, scope timer, type r */ | ||
| 156 | typedef unsigned int reg_timer_r_time; | ||
| 157 | #define REG_RD_ADDR_timer_r_time 56 | ||
| 158 | |||
| 159 | /* Register rw_out, scope timer, type rw */ | ||
| 160 | typedef struct { | ||
| 161 | unsigned int tmr : 2; | ||
| 162 | unsigned int dummy1 : 30; | ||
| 163 | } reg_timer_rw_out; | ||
| 164 | #define REG_RD_ADDR_timer_rw_out 60 | ||
| 165 | #define REG_WR_ADDR_timer_rw_out 60 | ||
| 166 | |||
| 167 | /* Register rw_wd_ctrl, scope timer, type rw */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int cnt : 8; | ||
| 170 | unsigned int cmd : 1; | ||
| 171 | unsigned int key : 7; | ||
| 172 | unsigned int dummy1 : 16; | ||
| 173 | } reg_timer_rw_wd_ctrl; | ||
| 174 | #define REG_RD_ADDR_timer_rw_wd_ctrl 64 | ||
| 175 | #define REG_WR_ADDR_timer_rw_wd_ctrl 64 | ||
| 176 | |||
| 177 | /* Register r_wd_stat, scope timer, type r */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int cnt : 8; | ||
| 180 | unsigned int cmd : 1; | ||
| 181 | unsigned int dummy1 : 23; | ||
| 182 | } reg_timer_r_wd_stat; | ||
| 183 | #define REG_RD_ADDR_timer_r_wd_stat 68 | ||
| 184 | |||
| 185 | /* Register rw_intr_mask, scope timer, type rw */ | ||
| 186 | typedef struct { | ||
| 187 | unsigned int tmr0 : 1; | ||
| 188 | unsigned int tmr1 : 1; | ||
| 189 | unsigned int cnt : 1; | ||
| 190 | unsigned int trig : 1; | ||
| 191 | unsigned int dummy1 : 28; | ||
| 192 | } reg_timer_rw_intr_mask; | ||
| 193 | #define REG_RD_ADDR_timer_rw_intr_mask 72 | ||
| 194 | #define REG_WR_ADDR_timer_rw_intr_mask 72 | ||
| 195 | |||
| 196 | /* Register rw_ack_intr, scope timer, type rw */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int tmr0 : 1; | ||
| 199 | unsigned int tmr1 : 1; | ||
| 200 | unsigned int cnt : 1; | ||
| 201 | unsigned int trig : 1; | ||
| 202 | unsigned int dummy1 : 28; | ||
| 203 | } reg_timer_rw_ack_intr; | ||
| 204 | #define REG_RD_ADDR_timer_rw_ack_intr 76 | ||
| 205 | #define REG_WR_ADDR_timer_rw_ack_intr 76 | ||
| 206 | |||
| 207 | /* Register r_intr, scope timer, type r */ | ||
| 208 | typedef struct { | ||
| 209 | unsigned int tmr0 : 1; | ||
| 210 | unsigned int tmr1 : 1; | ||
| 211 | unsigned int cnt : 1; | ||
| 212 | unsigned int trig : 1; | ||
| 213 | unsigned int dummy1 : 28; | ||
| 214 | } reg_timer_r_intr; | ||
| 215 | #define REG_RD_ADDR_timer_r_intr 80 | ||
| 216 | |||
| 217 | /* Register r_masked_intr, scope timer, type r */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int tmr0 : 1; | ||
| 220 | unsigned int tmr1 : 1; | ||
| 221 | unsigned int cnt : 1; | ||
| 222 | unsigned int trig : 1; | ||
| 223 | unsigned int dummy1 : 28; | ||
| 224 | } reg_timer_r_masked_intr; | ||
| 225 | #define REG_RD_ADDR_timer_r_masked_intr 84 | ||
| 226 | |||
| 227 | /* Register rw_test, scope timer, type rw */ | ||
| 228 | typedef struct { | ||
| 229 | unsigned int dis : 1; | ||
| 230 | unsigned int en : 1; | ||
| 231 | unsigned int dummy1 : 30; | ||
| 232 | } reg_timer_rw_test; | ||
| 233 | #define REG_RD_ADDR_timer_rw_test 88 | ||
| 234 | #define REG_WR_ADDR_timer_rw_test 88 | ||
| 235 | |||
| 236 | |||
| 237 | /* Constants */ | ||
| 238 | enum { | ||
| 239 | regk_timer_ext = 0x00000001, | ||
| 240 | regk_timer_f100 = 0x00000007, | ||
| 241 | regk_timer_f29_493 = 0x00000004, | ||
| 242 | regk_timer_f32 = 0x00000005, | ||
| 243 | regk_timer_f32_768 = 0x00000006, | ||
| 244 | regk_timer_f90 = 0x00000003, | ||
| 245 | regk_timer_hold = 0x00000001, | ||
| 246 | regk_timer_ld = 0x00000000, | ||
| 247 | regk_timer_no = 0x00000000, | ||
| 248 | regk_timer_off = 0x00000000, | ||
| 249 | regk_timer_run = 0x00000002, | ||
| 250 | regk_timer_rw_cnt_cfg_default = 0x00000000, | ||
| 251 | regk_timer_rw_intr_mask_default = 0x00000000, | ||
| 252 | regk_timer_rw_out_default = 0x00000000, | ||
| 253 | regk_timer_rw_test_default = 0x00000000, | ||
| 254 | regk_timer_rw_tmr0_ctrl_default = 0x00000000, | ||
| 255 | regk_timer_rw_tmr1_ctrl_default = 0x00000000, | ||
| 256 | regk_timer_rw_trig_cfg_default = 0x00000000, | ||
| 257 | regk_timer_start = 0x00000001, | ||
| 258 | regk_timer_stop = 0x00000000, | ||
| 259 | regk_timer_time = 0x00000001, | ||
| 260 | regk_timer_tmr0 = 0x00000002, | ||
| 261 | regk_timer_tmr1 = 0x00000003, | ||
| 262 | regk_timer_vclk = 0x00000002, | ||
| 263 | regk_timer_yes = 0x00000001 | ||
| 264 | }; | ||
| 265 | #endif /* __timer_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/memmap.h b/include/asm-cris/arch-v32/mach-a3/memmap.h new file mode 100644 index 000000000000..7e15c9eb4e49 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/memmap.h | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | #ifndef _ASM_ARCH_MEMMAP_H | ||
| 2 | #define _ASM_ARCH_MEMMAP_H | ||
| 3 | |||
| 4 | #define MEM_INTMEM_START (0x38000000) | ||
| 5 | #define MEM_INTMEM_SIZE (0x00018000) | ||
| 6 | #define MEM_DRAM_START (0x40000000) | ||
| 7 | |||
| 8 | #define MEM_NON_CACHEABLE (0x80000000) | ||
| 9 | |||
| 10 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/pinmux.h b/include/asm-cris/arch-v32/mach-a3/pinmux.h new file mode 100644 index 000000000000..db42a7254584 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/pinmux.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_PINMUX_H | ||
| 2 | #define _ASM_CRIS_ARCH_PINMUX_H | ||
| 3 | |||
| 4 | #define PORT_A 0 | ||
| 5 | #define PORT_B 1 | ||
| 6 | #define PORT_C 2 | ||
| 7 | |||
| 8 | enum pin_mode { | ||
| 9 | pinmux_none = 0, | ||
| 10 | pinmux_fixed, | ||
| 11 | pinmux_gpio, | ||
| 12 | pinmux_iop | ||
| 13 | }; | ||
| 14 | |||
| 15 | enum fixed_function { | ||
| 16 | pinmux_eth, | ||
| 17 | pinmux_geth, | ||
| 18 | pinmux_tg_ccd, | ||
| 19 | pinmux_tg_cmos, | ||
| 20 | pinmux_vout, | ||
| 21 | pinmux_ser1, | ||
| 22 | pinmux_ser2, | ||
| 23 | pinmux_ser3, | ||
| 24 | pinmux_ser4, | ||
| 25 | pinmux_sser, | ||
| 26 | pinmux_pio, | ||
| 27 | pinmux_pwm0, | ||
| 28 | pinmux_pwm1, | ||
| 29 | pinmux_pwm2, | ||
| 30 | pinmux_i2c0, | ||
| 31 | pinmux_i2c1, | ||
| 32 | pinmux_i2c1_3wire, | ||
| 33 | pinmux_i2c1_sda1, | ||
| 34 | pinmux_i2c1_sda2, | ||
| 35 | pinmux_i2c1_sda3, | ||
| 36 | }; | ||
| 37 | |||
| 38 | int crisv32_pinmux_init(void); | ||
| 39 | int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); | ||
| 40 | int crisv32_pinmux_alloc_fixed(enum fixed_function function); | ||
| 41 | int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); | ||
| 42 | int crisv32_pinmux_dealloc_fixed(enum fixed_function function); | ||
| 43 | void crisv32_pinmux_dump(void); | ||
| 44 | |||
| 45 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-a3/startup.inc b/include/asm-cris/arch-v32/mach-a3/startup.inc new file mode 100644 index 000000000000..2f23e5e16f4a --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/startup.inc | |||
| @@ -0,0 +1,60 @@ | |||
| 1 | #include <hwregs/asm/reg_map_asm.h> | ||
| 2 | #include <hwregs/asm/gio_defs_asm.h> | ||
| 3 | #include <hwregs/asm/pio_defs_asm.h> | ||
| 4 | #include <hwregs/asm/clkgen_defs_asm.h> | ||
| 5 | #include <hwregs/asm/pinmux_defs_asm.h> | ||
| 6 | |||
| 7 | .macro GIO_INIT | ||
| 8 | move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 | ||
| 9 | move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 | ||
| 10 | move.d $r0, [$r1] | ||
| 11 | |||
| 12 | move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 | ||
| 13 | move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 | ||
| 14 | move.d $r0, [$r1] | ||
| 15 | |||
| 16 | move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 | ||
| 17 | move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 | ||
| 18 | move.d $r0, [$r1] | ||
| 19 | |||
| 20 | move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 | ||
| 21 | move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 | ||
| 22 | move.d $r0, [$r1] | ||
| 23 | |||
| 24 | move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 | ||
| 25 | move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 | ||
| 26 | move.d $r0, [$r1] | ||
| 27 | |||
| 28 | move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 | ||
| 29 | move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 | ||
| 30 | move.d $r0, [$r1] | ||
| 31 | |||
| 32 | move.d 0xFFFFFFFF, $r0 | ||
| 33 | move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1 | ||
| 34 | move.d $r0, [$r1] | ||
| 35 | move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1 | ||
| 36 | move.d $r0, [$r1] | ||
| 37 | move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1 | ||
| 38 | move.d $r0, [$r1] | ||
| 39 | .endm | ||
| 40 | |||
| 41 | .macro START_CLOCKS | ||
| 42 | move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1 | ||
| 43 | move.d [$r1], $r0 | ||
| 44 | or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \ | ||
| 45 | REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \ | ||
| 46 | REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0 | ||
| 47 | move.d $r0, [$r1] | ||
| 48 | .endm | ||
| 49 | |||
| 50 | .macro SETUP_WAIT_STATES | ||
| 51 | move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0 | ||
| 52 | move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1 | ||
| 53 | move.d $r1, [$r0] | ||
| 54 | move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0 | ||
| 55 | move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1 | ||
| 56 | move.d $r1, [$r0] | ||
| 57 | move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0 | ||
| 58 | move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1 | ||
| 59 | move.d $r1, [$r0] | ||
| 60 | .endm | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/arbiter.h b/include/asm-cris/arch-v32/mach-fs/arbiter.h new file mode 100644 index 000000000000..a2e0ec8faa7d --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/arbiter.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_ARBITER_H | ||
| 2 | #define _ASM_CRIS_ARCH_ARBITER_H | ||
| 3 | |||
| 4 | #define EXT_REGION 0 | ||
| 5 | #define INT_REGION 1 | ||
| 6 | |||
| 7 | typedef void (watch_callback)(void); | ||
| 8 | |||
| 9 | enum { | ||
| 10 | arbiter_all_dmas = 0x3ff, | ||
| 11 | arbiter_cpu = 0xc00, | ||
| 12 | arbiter_all_clients = 0x3fff | ||
| 13 | }; | ||
| 14 | |||
| 15 | enum { | ||
| 16 | arbiter_all_read = 0x55, | ||
| 17 | arbiter_all_write = 0xaa, | ||
| 18 | arbiter_all_accesses = 0xff | ||
| 19 | }; | ||
| 20 | |||
| 21 | int crisv32_arbiter_allocate_bandwidth(int client, int region, | ||
| 22 | unsigned long bandwidth); | ||
| 23 | int crisv32_arbiter_watch(unsigned long start, unsigned long size, | ||
| 24 | unsigned long clients, unsigned long accesses, | ||
| 25 | watch_callback * cb); | ||
| 26 | int crisv32_arbiter_unwatch(int id); | ||
| 27 | |||
| 28 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h new file mode 100644 index 000000000000..0a409c92837e --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/bif_core_defs_asm.h | |||
| @@ -0,0 +1,319 @@ | |||
| 1 | #ifndef __bif_core_defs_asm_h | ||
| 2 | #define __bif_core_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_core_regs.r | ||
| 7 | * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:33 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r | ||
| 11 | * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_grp1_cfg, scope bif_core, type rw */ | ||
| 57 | #define reg_bif_core_rw_grp1_cfg___lw___lsb 0 | ||
| 58 | #define reg_bif_core_rw_grp1_cfg___lw___width 6 | ||
| 59 | #define reg_bif_core_rw_grp1_cfg___ew___lsb 6 | ||
| 60 | #define reg_bif_core_rw_grp1_cfg___ew___width 3 | ||
| 61 | #define reg_bif_core_rw_grp1_cfg___zw___lsb 9 | ||
| 62 | #define reg_bif_core_rw_grp1_cfg___zw___width 3 | ||
| 63 | #define reg_bif_core_rw_grp1_cfg___aw___lsb 12 | ||
| 64 | #define reg_bif_core_rw_grp1_cfg___aw___width 2 | ||
| 65 | #define reg_bif_core_rw_grp1_cfg___dw___lsb 14 | ||
| 66 | #define reg_bif_core_rw_grp1_cfg___dw___width 2 | ||
| 67 | #define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 | ||
| 68 | #define reg_bif_core_rw_grp1_cfg___ewb___width 2 | ||
| 69 | #define reg_bif_core_rw_grp1_cfg___bw___lsb 18 | ||
| 70 | #define reg_bif_core_rw_grp1_cfg___bw___width 1 | ||
| 71 | #define reg_bif_core_rw_grp1_cfg___bw___bit 18 | ||
| 72 | #define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 | ||
| 73 | #define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 | ||
| 74 | #define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 | ||
| 75 | #define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 | ||
| 76 | #define reg_bif_core_rw_grp1_cfg___erc_en___width 1 | ||
| 77 | #define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 | ||
| 78 | #define reg_bif_core_rw_grp1_cfg___mode___lsb 21 | ||
| 79 | #define reg_bif_core_rw_grp1_cfg___mode___width 1 | ||
| 80 | #define reg_bif_core_rw_grp1_cfg___mode___bit 21 | ||
| 81 | #define reg_bif_core_rw_grp1_cfg_offset 0 | ||
| 82 | |||
| 83 | /* Register rw_grp2_cfg, scope bif_core, type rw */ | ||
| 84 | #define reg_bif_core_rw_grp2_cfg___lw___lsb 0 | ||
| 85 | #define reg_bif_core_rw_grp2_cfg___lw___width 6 | ||
| 86 | #define reg_bif_core_rw_grp2_cfg___ew___lsb 6 | ||
| 87 | #define reg_bif_core_rw_grp2_cfg___ew___width 3 | ||
| 88 | #define reg_bif_core_rw_grp2_cfg___zw___lsb 9 | ||
| 89 | #define reg_bif_core_rw_grp2_cfg___zw___width 3 | ||
| 90 | #define reg_bif_core_rw_grp2_cfg___aw___lsb 12 | ||
| 91 | #define reg_bif_core_rw_grp2_cfg___aw___width 2 | ||
| 92 | #define reg_bif_core_rw_grp2_cfg___dw___lsb 14 | ||
| 93 | #define reg_bif_core_rw_grp2_cfg___dw___width 2 | ||
| 94 | #define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 | ||
| 95 | #define reg_bif_core_rw_grp2_cfg___ewb___width 2 | ||
| 96 | #define reg_bif_core_rw_grp2_cfg___bw___lsb 18 | ||
| 97 | #define reg_bif_core_rw_grp2_cfg___bw___width 1 | ||
| 98 | #define reg_bif_core_rw_grp2_cfg___bw___bit 18 | ||
| 99 | #define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 | ||
| 100 | #define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 | ||
| 101 | #define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 | ||
| 102 | #define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 | ||
| 103 | #define reg_bif_core_rw_grp2_cfg___erc_en___width 1 | ||
| 104 | #define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 | ||
| 105 | #define reg_bif_core_rw_grp2_cfg___mode___lsb 21 | ||
| 106 | #define reg_bif_core_rw_grp2_cfg___mode___width 1 | ||
| 107 | #define reg_bif_core_rw_grp2_cfg___mode___bit 21 | ||
| 108 | #define reg_bif_core_rw_grp2_cfg_offset 4 | ||
| 109 | |||
| 110 | /* Register rw_grp3_cfg, scope bif_core, type rw */ | ||
| 111 | #define reg_bif_core_rw_grp3_cfg___lw___lsb 0 | ||
| 112 | #define reg_bif_core_rw_grp3_cfg___lw___width 6 | ||
| 113 | #define reg_bif_core_rw_grp3_cfg___ew___lsb 6 | ||
| 114 | #define reg_bif_core_rw_grp3_cfg___ew___width 3 | ||
| 115 | #define reg_bif_core_rw_grp3_cfg___zw___lsb 9 | ||
| 116 | #define reg_bif_core_rw_grp3_cfg___zw___width 3 | ||
| 117 | #define reg_bif_core_rw_grp3_cfg___aw___lsb 12 | ||
| 118 | #define reg_bif_core_rw_grp3_cfg___aw___width 2 | ||
| 119 | #define reg_bif_core_rw_grp3_cfg___dw___lsb 14 | ||
| 120 | #define reg_bif_core_rw_grp3_cfg___dw___width 2 | ||
| 121 | #define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 | ||
| 122 | #define reg_bif_core_rw_grp3_cfg___ewb___width 2 | ||
| 123 | #define reg_bif_core_rw_grp3_cfg___bw___lsb 18 | ||
| 124 | #define reg_bif_core_rw_grp3_cfg___bw___width 1 | ||
| 125 | #define reg_bif_core_rw_grp3_cfg___bw___bit 18 | ||
| 126 | #define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 | ||
| 127 | #define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 | ||
| 128 | #define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 | ||
| 129 | #define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 | ||
| 130 | #define reg_bif_core_rw_grp3_cfg___erc_en___width 1 | ||
| 131 | #define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 | ||
| 132 | #define reg_bif_core_rw_grp3_cfg___mode___lsb 21 | ||
| 133 | #define reg_bif_core_rw_grp3_cfg___mode___width 1 | ||
| 134 | #define reg_bif_core_rw_grp3_cfg___mode___bit 21 | ||
| 135 | #define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 | ||
| 136 | #define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 | ||
| 137 | #define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 | ||
| 138 | #define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 | ||
| 139 | #define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 | ||
| 140 | #define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 | ||
| 141 | #define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 | ||
| 142 | #define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 | ||
| 143 | #define reg_bif_core_rw_grp3_cfg_offset 8 | ||
| 144 | |||
| 145 | /* Register rw_grp4_cfg, scope bif_core, type rw */ | ||
| 146 | #define reg_bif_core_rw_grp4_cfg___lw___lsb 0 | ||
| 147 | #define reg_bif_core_rw_grp4_cfg___lw___width 6 | ||
| 148 | #define reg_bif_core_rw_grp4_cfg___ew___lsb 6 | ||
| 149 | #define reg_bif_core_rw_grp4_cfg___ew___width 3 | ||
| 150 | #define reg_bif_core_rw_grp4_cfg___zw___lsb 9 | ||
| 151 | #define reg_bif_core_rw_grp4_cfg___zw___width 3 | ||
| 152 | #define reg_bif_core_rw_grp4_cfg___aw___lsb 12 | ||
| 153 | #define reg_bif_core_rw_grp4_cfg___aw___width 2 | ||
| 154 | #define reg_bif_core_rw_grp4_cfg___dw___lsb 14 | ||
| 155 | #define reg_bif_core_rw_grp4_cfg___dw___width 2 | ||
| 156 | #define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 | ||
| 157 | #define reg_bif_core_rw_grp4_cfg___ewb___width 2 | ||
| 158 | #define reg_bif_core_rw_grp4_cfg___bw___lsb 18 | ||
| 159 | #define reg_bif_core_rw_grp4_cfg___bw___width 1 | ||
| 160 | #define reg_bif_core_rw_grp4_cfg___bw___bit 18 | ||
| 161 | #define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 | ||
| 162 | #define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 | ||
| 163 | #define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 | ||
| 164 | #define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 | ||
| 165 | #define reg_bif_core_rw_grp4_cfg___erc_en___width 1 | ||
| 166 | #define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 | ||
| 167 | #define reg_bif_core_rw_grp4_cfg___mode___lsb 21 | ||
| 168 | #define reg_bif_core_rw_grp4_cfg___mode___width 1 | ||
| 169 | #define reg_bif_core_rw_grp4_cfg___mode___bit 21 | ||
| 170 | #define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 | ||
| 171 | #define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 | ||
| 172 | #define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 | ||
| 173 | #define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 | ||
| 174 | #define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 | ||
| 175 | #define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 | ||
| 176 | #define reg_bif_core_rw_grp4_cfg_offset 12 | ||
| 177 | |||
| 178 | /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ | ||
| 179 | #define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 | ||
| 180 | #define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 | ||
| 181 | #define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 | ||
| 182 | #define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 | ||
| 183 | #define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 | ||
| 184 | #define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 | ||
| 185 | #define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 | ||
| 186 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 | ||
| 187 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 | ||
| 188 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 | ||
| 189 | #define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 | ||
| 190 | #define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 | ||
| 191 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 | ||
| 192 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 | ||
| 193 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 | ||
| 194 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 | ||
| 195 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 | ||
| 196 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 | ||
| 197 | #define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 | ||
| 198 | #define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 | ||
| 199 | #define reg_bif_core_rw_sdram_cfg_grp0_offset 16 | ||
| 200 | |||
| 201 | /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ | ||
| 202 | #define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 | ||
| 203 | #define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 | ||
| 204 | #define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 | ||
| 205 | #define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 | ||
| 206 | #define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 | ||
| 207 | #define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 | ||
| 208 | #define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 | ||
| 209 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 | ||
| 210 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 | ||
| 211 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 | ||
| 212 | #define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 | ||
| 213 | #define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 | ||
| 214 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 | ||
| 215 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 | ||
| 216 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 | ||
| 217 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 | ||
| 218 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 | ||
| 219 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 | ||
| 220 | #define reg_bif_core_rw_sdram_cfg_grp1_offset 20 | ||
| 221 | |||
| 222 | /* Register rw_sdram_timing, scope bif_core, type rw */ | ||
| 223 | #define reg_bif_core_rw_sdram_timing___cl___lsb 0 | ||
| 224 | #define reg_bif_core_rw_sdram_timing___cl___width 3 | ||
| 225 | #define reg_bif_core_rw_sdram_timing___rcd___lsb 3 | ||
| 226 | #define reg_bif_core_rw_sdram_timing___rcd___width 3 | ||
| 227 | #define reg_bif_core_rw_sdram_timing___rp___lsb 6 | ||
| 228 | #define reg_bif_core_rw_sdram_timing___rp___width 3 | ||
| 229 | #define reg_bif_core_rw_sdram_timing___rc___lsb 9 | ||
| 230 | #define reg_bif_core_rw_sdram_timing___rc___width 2 | ||
| 231 | #define reg_bif_core_rw_sdram_timing___dpl___lsb 11 | ||
| 232 | #define reg_bif_core_rw_sdram_timing___dpl___width 2 | ||
| 233 | #define reg_bif_core_rw_sdram_timing___pde___lsb 13 | ||
| 234 | #define reg_bif_core_rw_sdram_timing___pde___width 1 | ||
| 235 | #define reg_bif_core_rw_sdram_timing___pde___bit 13 | ||
| 236 | #define reg_bif_core_rw_sdram_timing___ref___lsb 14 | ||
| 237 | #define reg_bif_core_rw_sdram_timing___ref___width 2 | ||
| 238 | #define reg_bif_core_rw_sdram_timing___cpd___lsb 16 | ||
| 239 | #define reg_bif_core_rw_sdram_timing___cpd___width 1 | ||
| 240 | #define reg_bif_core_rw_sdram_timing___cpd___bit 16 | ||
| 241 | #define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 | ||
| 242 | #define reg_bif_core_rw_sdram_timing___sdcke___width 1 | ||
| 243 | #define reg_bif_core_rw_sdram_timing___sdcke___bit 17 | ||
| 244 | #define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 | ||
| 245 | #define reg_bif_core_rw_sdram_timing___sdclk___width 1 | ||
| 246 | #define reg_bif_core_rw_sdram_timing___sdclk___bit 18 | ||
| 247 | #define reg_bif_core_rw_sdram_timing_offset 24 | ||
| 248 | |||
| 249 | /* Register rw_sdram_cmd, scope bif_core, type rw */ | ||
| 250 | #define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 | ||
| 251 | #define reg_bif_core_rw_sdram_cmd___cmd___width 3 | ||
| 252 | #define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 | ||
| 253 | #define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 | ||
| 254 | #define reg_bif_core_rw_sdram_cmd_offset 28 | ||
| 255 | |||
| 256 | /* Register rs_sdram_ref_stat, scope bif_core, type rs */ | ||
| 257 | #define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 | ||
| 258 | #define reg_bif_core_rs_sdram_ref_stat___ok___width 1 | ||
| 259 | #define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 | ||
| 260 | #define reg_bif_core_rs_sdram_ref_stat_offset 32 | ||
| 261 | |||
| 262 | /* Register r_sdram_ref_stat, scope bif_core, type r */ | ||
| 263 | #define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 | ||
| 264 | #define reg_bif_core_r_sdram_ref_stat___ok___width 1 | ||
| 265 | #define reg_bif_core_r_sdram_ref_stat___ok___bit 0 | ||
| 266 | #define reg_bif_core_r_sdram_ref_stat_offset 36 | ||
| 267 | |||
| 268 | |||
| 269 | /* Constants */ | ||
| 270 | #define regk_bif_core_bank2 0x00000000 | ||
| 271 | #define regk_bif_core_bank4 0x00000001 | ||
| 272 | #define regk_bif_core_bit10 0x0000000a | ||
| 273 | #define regk_bif_core_bit11 0x0000000b | ||
| 274 | #define regk_bif_core_bit12 0x0000000c | ||
| 275 | #define regk_bif_core_bit13 0x0000000d | ||
| 276 | #define regk_bif_core_bit14 0x0000000e | ||
| 277 | #define regk_bif_core_bit15 0x0000000f | ||
| 278 | #define regk_bif_core_bit16 0x00000010 | ||
| 279 | #define regk_bif_core_bit17 0x00000011 | ||
| 280 | #define regk_bif_core_bit18 0x00000012 | ||
| 281 | #define regk_bif_core_bit19 0x00000013 | ||
| 282 | #define regk_bif_core_bit20 0x00000014 | ||
| 283 | #define regk_bif_core_bit21 0x00000015 | ||
| 284 | #define regk_bif_core_bit22 0x00000016 | ||
| 285 | #define regk_bif_core_bit23 0x00000017 | ||
| 286 | #define regk_bif_core_bit24 0x00000018 | ||
| 287 | #define regk_bif_core_bit25 0x00000019 | ||
| 288 | #define regk_bif_core_bit26 0x0000001a | ||
| 289 | #define regk_bif_core_bit27 0x0000001b | ||
| 290 | #define regk_bif_core_bit28 0x0000001c | ||
| 291 | #define regk_bif_core_bit29 0x0000001d | ||
| 292 | #define regk_bif_core_bit9 0x00000009 | ||
| 293 | #define regk_bif_core_bw16 0x00000001 | ||
| 294 | #define regk_bif_core_bw32 0x00000000 | ||
| 295 | #define regk_bif_core_bwe 0x00000000 | ||
| 296 | #define regk_bif_core_cwe 0x00000001 | ||
| 297 | #define regk_bif_core_e15us 0x00000001 | ||
| 298 | #define regk_bif_core_e7800ns 0x00000002 | ||
| 299 | #define regk_bif_core_grp0 0x00000000 | ||
| 300 | #define regk_bif_core_grp1 0x00000001 | ||
| 301 | #define regk_bif_core_mrs 0x00000003 | ||
| 302 | #define regk_bif_core_no 0x00000000 | ||
| 303 | #define regk_bif_core_none 0x00000000 | ||
| 304 | #define regk_bif_core_nop 0x00000000 | ||
| 305 | #define regk_bif_core_off 0x00000000 | ||
| 306 | #define regk_bif_core_pre 0x00000002 | ||
| 307 | #define regk_bif_core_r_sdram_ref_stat_default 0x00000001 | ||
| 308 | #define regk_bif_core_rd 0x00000002 | ||
| 309 | #define regk_bif_core_ref 0x00000001 | ||
| 310 | #define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 | ||
| 311 | #define regk_bif_core_rw_grp1_cfg_default 0x000006cf | ||
| 312 | #define regk_bif_core_rw_grp2_cfg_default 0x000006cf | ||
| 313 | #define regk_bif_core_rw_grp3_cfg_default 0x000006cf | ||
| 314 | #define regk_bif_core_rw_grp4_cfg_default 0x000006cf | ||
| 315 | #define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 | ||
| 316 | #define regk_bif_core_slf 0x00000004 | ||
| 317 | #define regk_bif_core_wr 0x00000001 | ||
| 318 | #define regk_bif_core_yes 0x00000001 | ||
| 319 | #endif /* __bif_core_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h new file mode 100644 index 000000000000..a9908dfc2937 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/config_defs_asm.h | |||
| @@ -0,0 +1,131 @@ | |||
| 1 | #ifndef __config_defs_asm_h | ||
| 2 | #define __config_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../rtl/config_regs.r | ||
| 7 | * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp | ||
| 8 | * last modfied: Thu Mar 4 12:34:39 2004 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r | ||
| 11 | * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register r_bootsel, scope config, type r */ | ||
| 57 | #define reg_config_r_bootsel___boot_mode___lsb 0 | ||
| 58 | #define reg_config_r_bootsel___boot_mode___width 3 | ||
| 59 | #define reg_config_r_bootsel___full_duplex___lsb 3 | ||
| 60 | #define reg_config_r_bootsel___full_duplex___width 1 | ||
| 61 | #define reg_config_r_bootsel___full_duplex___bit 3 | ||
| 62 | #define reg_config_r_bootsel___user___lsb 4 | ||
| 63 | #define reg_config_r_bootsel___user___width 1 | ||
| 64 | #define reg_config_r_bootsel___user___bit 4 | ||
| 65 | #define reg_config_r_bootsel___pll___lsb 5 | ||
| 66 | #define reg_config_r_bootsel___pll___width 1 | ||
| 67 | #define reg_config_r_bootsel___pll___bit 5 | ||
| 68 | #define reg_config_r_bootsel___flash_bw___lsb 6 | ||
| 69 | #define reg_config_r_bootsel___flash_bw___width 1 | ||
| 70 | #define reg_config_r_bootsel___flash_bw___bit 6 | ||
| 71 | #define reg_config_r_bootsel_offset 0 | ||
| 72 | |||
| 73 | /* Register rw_clk_ctrl, scope config, type rw */ | ||
| 74 | #define reg_config_rw_clk_ctrl___pll___lsb 0 | ||
| 75 | #define reg_config_rw_clk_ctrl___pll___width 1 | ||
| 76 | #define reg_config_rw_clk_ctrl___pll___bit 0 | ||
| 77 | #define reg_config_rw_clk_ctrl___cpu___lsb 1 | ||
| 78 | #define reg_config_rw_clk_ctrl___cpu___width 1 | ||
| 79 | #define reg_config_rw_clk_ctrl___cpu___bit 1 | ||
| 80 | #define reg_config_rw_clk_ctrl___iop___lsb 2 | ||
| 81 | #define reg_config_rw_clk_ctrl___iop___width 1 | ||
| 82 | #define reg_config_rw_clk_ctrl___iop___bit 2 | ||
| 83 | #define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 | ||
| 84 | #define reg_config_rw_clk_ctrl___dma01_eth0___width 1 | ||
| 85 | #define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 | ||
| 86 | #define reg_config_rw_clk_ctrl___dma23___lsb 4 | ||
| 87 | #define reg_config_rw_clk_ctrl___dma23___width 1 | ||
| 88 | #define reg_config_rw_clk_ctrl___dma23___bit 4 | ||
| 89 | #define reg_config_rw_clk_ctrl___dma45___lsb 5 | ||
| 90 | #define reg_config_rw_clk_ctrl___dma45___width 1 | ||
| 91 | #define reg_config_rw_clk_ctrl___dma45___bit 5 | ||
| 92 | #define reg_config_rw_clk_ctrl___dma67___lsb 6 | ||
| 93 | #define reg_config_rw_clk_ctrl___dma67___width 1 | ||
| 94 | #define reg_config_rw_clk_ctrl___dma67___bit 6 | ||
| 95 | #define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 | ||
| 96 | #define reg_config_rw_clk_ctrl___dma89_strcop___width 1 | ||
| 97 | #define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 | ||
| 98 | #define reg_config_rw_clk_ctrl___bif___lsb 8 | ||
| 99 | #define reg_config_rw_clk_ctrl___bif___width 1 | ||
| 100 | #define reg_config_rw_clk_ctrl___bif___bit 8 | ||
| 101 | #define reg_config_rw_clk_ctrl___fix_io___lsb 9 | ||
| 102 | #define reg_config_rw_clk_ctrl___fix_io___width 1 | ||
| 103 | #define reg_config_rw_clk_ctrl___fix_io___bit 9 | ||
| 104 | #define reg_config_rw_clk_ctrl_offset 4 | ||
| 105 | |||
| 106 | /* Register rw_pad_ctrl, scope config, type rw */ | ||
| 107 | #define reg_config_rw_pad_ctrl___usb_susp___lsb 0 | ||
| 108 | #define reg_config_rw_pad_ctrl___usb_susp___width 1 | ||
| 109 | #define reg_config_rw_pad_ctrl___usb_susp___bit 0 | ||
| 110 | #define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 | ||
| 111 | #define reg_config_rw_pad_ctrl___phyrst_n___width 1 | ||
| 112 | #define reg_config_rw_pad_ctrl___phyrst_n___bit 1 | ||
| 113 | #define reg_config_rw_pad_ctrl_offset 8 | ||
| 114 | |||
| 115 | |||
| 116 | /* Constants */ | ||
| 117 | #define regk_config_bw16 0x00000000 | ||
| 118 | #define regk_config_bw32 0x00000001 | ||
| 119 | #define regk_config_master 0x00000005 | ||
| 120 | #define regk_config_nand 0x00000003 | ||
| 121 | #define regk_config_net_rx 0x00000001 | ||
| 122 | #define regk_config_net_tx_rx 0x00000002 | ||
| 123 | #define regk_config_no 0x00000000 | ||
| 124 | #define regk_config_none 0x00000007 | ||
| 125 | #define regk_config_nor 0x00000000 | ||
| 126 | #define regk_config_rw_clk_ctrl_default 0x00000002 | ||
| 127 | #define regk_config_rw_pad_ctrl_default 0x00000000 | ||
| 128 | #define regk_config_ser 0x00000004 | ||
| 129 | #define regk_config_slave 0x00000006 | ||
| 130 | #define regk_config_yes 0x00000001 | ||
| 131 | #endif /* __config_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h new file mode 100644 index 000000000000..be4c63936d90 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/gio_defs_asm.h | |||
| @@ -0,0 +1,276 @@ | |||
| 1 | #ifndef __gio_defs_asm_h | ||
| 2 | #define __gio_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/gio/rtl/gio_regs.r | ||
| 7 | * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:07:47 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r | ||
| 11 | * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_pa_dout, scope gio, type rw */ | ||
| 57 | #define reg_gio_rw_pa_dout___data___lsb 0 | ||
| 58 | #define reg_gio_rw_pa_dout___data___width 8 | ||
| 59 | #define reg_gio_rw_pa_dout_offset 0 | ||
| 60 | |||
| 61 | /* Register r_pa_din, scope gio, type r */ | ||
| 62 | #define reg_gio_r_pa_din___data___lsb 0 | ||
| 63 | #define reg_gio_r_pa_din___data___width 8 | ||
| 64 | #define reg_gio_r_pa_din_offset 4 | ||
| 65 | |||
| 66 | /* Register rw_pa_oe, scope gio, type rw */ | ||
| 67 | #define reg_gio_rw_pa_oe___oe___lsb 0 | ||
| 68 | #define reg_gio_rw_pa_oe___oe___width 8 | ||
| 69 | #define reg_gio_rw_pa_oe_offset 8 | ||
| 70 | |||
| 71 | /* Register rw_intr_cfg, scope gio, type rw */ | ||
| 72 | #define reg_gio_rw_intr_cfg___pa0___lsb 0 | ||
| 73 | #define reg_gio_rw_intr_cfg___pa0___width 3 | ||
| 74 | #define reg_gio_rw_intr_cfg___pa1___lsb 3 | ||
| 75 | #define reg_gio_rw_intr_cfg___pa1___width 3 | ||
| 76 | #define reg_gio_rw_intr_cfg___pa2___lsb 6 | ||
| 77 | #define reg_gio_rw_intr_cfg___pa2___width 3 | ||
| 78 | #define reg_gio_rw_intr_cfg___pa3___lsb 9 | ||
| 79 | #define reg_gio_rw_intr_cfg___pa3___width 3 | ||
| 80 | #define reg_gio_rw_intr_cfg___pa4___lsb 12 | ||
| 81 | #define reg_gio_rw_intr_cfg___pa4___width 3 | ||
| 82 | #define reg_gio_rw_intr_cfg___pa5___lsb 15 | ||
| 83 | #define reg_gio_rw_intr_cfg___pa5___width 3 | ||
| 84 | #define reg_gio_rw_intr_cfg___pa6___lsb 18 | ||
| 85 | #define reg_gio_rw_intr_cfg___pa6___width 3 | ||
| 86 | #define reg_gio_rw_intr_cfg___pa7___lsb 21 | ||
| 87 | #define reg_gio_rw_intr_cfg___pa7___width 3 | ||
| 88 | #define reg_gio_rw_intr_cfg_offset 12 | ||
| 89 | |||
| 90 | /* Register rw_intr_mask, scope gio, type rw */ | ||
| 91 | #define reg_gio_rw_intr_mask___pa0___lsb 0 | ||
| 92 | #define reg_gio_rw_intr_mask___pa0___width 1 | ||
| 93 | #define reg_gio_rw_intr_mask___pa0___bit 0 | ||
| 94 | #define reg_gio_rw_intr_mask___pa1___lsb 1 | ||
| 95 | #define reg_gio_rw_intr_mask___pa1___width 1 | ||
| 96 | #define reg_gio_rw_intr_mask___pa1___bit 1 | ||
| 97 | #define reg_gio_rw_intr_mask___pa2___lsb 2 | ||
| 98 | #define reg_gio_rw_intr_mask___pa2___width 1 | ||
| 99 | #define reg_gio_rw_intr_mask___pa2___bit 2 | ||
| 100 | #define reg_gio_rw_intr_mask___pa3___lsb 3 | ||
| 101 | #define reg_gio_rw_intr_mask___pa3___width 1 | ||
| 102 | #define reg_gio_rw_intr_mask___pa3___bit 3 | ||
| 103 | #define reg_gio_rw_intr_mask___pa4___lsb 4 | ||
| 104 | #define reg_gio_rw_intr_mask___pa4___width 1 | ||
| 105 | #define reg_gio_rw_intr_mask___pa4___bit 4 | ||
| 106 | #define reg_gio_rw_intr_mask___pa5___lsb 5 | ||
| 107 | #define reg_gio_rw_intr_mask___pa5___width 1 | ||
| 108 | #define reg_gio_rw_intr_mask___pa5___bit 5 | ||
| 109 | #define reg_gio_rw_intr_mask___pa6___lsb 6 | ||
| 110 | #define reg_gio_rw_intr_mask___pa6___width 1 | ||
| 111 | #define reg_gio_rw_intr_mask___pa6___bit 6 | ||
| 112 | #define reg_gio_rw_intr_mask___pa7___lsb 7 | ||
| 113 | #define reg_gio_rw_intr_mask___pa7___width 1 | ||
| 114 | #define reg_gio_rw_intr_mask___pa7___bit 7 | ||
| 115 | #define reg_gio_rw_intr_mask_offset 16 | ||
| 116 | |||
| 117 | /* Register rw_ack_intr, scope gio, type rw */ | ||
| 118 | #define reg_gio_rw_ack_intr___pa0___lsb 0 | ||
| 119 | #define reg_gio_rw_ack_intr___pa0___width 1 | ||
| 120 | #define reg_gio_rw_ack_intr___pa0___bit 0 | ||
| 121 | #define reg_gio_rw_ack_intr___pa1___lsb 1 | ||
| 122 | #define reg_gio_rw_ack_intr___pa1___width 1 | ||
| 123 | #define reg_gio_rw_ack_intr___pa1___bit 1 | ||
| 124 | #define reg_gio_rw_ack_intr___pa2___lsb 2 | ||
| 125 | #define reg_gio_rw_ack_intr___pa2___width 1 | ||
| 126 | #define reg_gio_rw_ack_intr___pa2___bit 2 | ||
| 127 | #define reg_gio_rw_ack_intr___pa3___lsb 3 | ||
| 128 | #define reg_gio_rw_ack_intr___pa3___width 1 | ||
| 129 | #define reg_gio_rw_ack_intr___pa3___bit 3 | ||
| 130 | #define reg_gio_rw_ack_intr___pa4___lsb 4 | ||
| 131 | #define reg_gio_rw_ack_intr___pa4___width 1 | ||
| 132 | #define reg_gio_rw_ack_intr___pa4___bit 4 | ||
| 133 | #define reg_gio_rw_ack_intr___pa5___lsb 5 | ||
| 134 | #define reg_gio_rw_ack_intr___pa5___width 1 | ||
| 135 | #define reg_gio_rw_ack_intr___pa5___bit 5 | ||
| 136 | #define reg_gio_rw_ack_intr___pa6___lsb 6 | ||
| 137 | #define reg_gio_rw_ack_intr___pa6___width 1 | ||
| 138 | #define reg_gio_rw_ack_intr___pa6___bit 6 | ||
| 139 | #define reg_gio_rw_ack_intr___pa7___lsb 7 | ||
| 140 | #define reg_gio_rw_ack_intr___pa7___width 1 | ||
| 141 | #define reg_gio_rw_ack_intr___pa7___bit 7 | ||
| 142 | #define reg_gio_rw_ack_intr_offset 20 | ||
| 143 | |||
| 144 | /* Register r_intr, scope gio, type r */ | ||
| 145 | #define reg_gio_r_intr___pa0___lsb 0 | ||
| 146 | #define reg_gio_r_intr___pa0___width 1 | ||
| 147 | #define reg_gio_r_intr___pa0___bit 0 | ||
| 148 | #define reg_gio_r_intr___pa1___lsb 1 | ||
| 149 | #define reg_gio_r_intr___pa1___width 1 | ||
| 150 | #define reg_gio_r_intr___pa1___bit 1 | ||
| 151 | #define reg_gio_r_intr___pa2___lsb 2 | ||
| 152 | #define reg_gio_r_intr___pa2___width 1 | ||
| 153 | #define reg_gio_r_intr___pa2___bit 2 | ||
| 154 | #define reg_gio_r_intr___pa3___lsb 3 | ||
| 155 | #define reg_gio_r_intr___pa3___width 1 | ||
| 156 | #define reg_gio_r_intr___pa3___bit 3 | ||
| 157 | #define reg_gio_r_intr___pa4___lsb 4 | ||
| 158 | #define reg_gio_r_intr___pa4___width 1 | ||
| 159 | #define reg_gio_r_intr___pa4___bit 4 | ||
| 160 | #define reg_gio_r_intr___pa5___lsb 5 | ||
| 161 | #define reg_gio_r_intr___pa5___width 1 | ||
| 162 | #define reg_gio_r_intr___pa5___bit 5 | ||
| 163 | #define reg_gio_r_intr___pa6___lsb 6 | ||
| 164 | #define reg_gio_r_intr___pa6___width 1 | ||
| 165 | #define reg_gio_r_intr___pa6___bit 6 | ||
| 166 | #define reg_gio_r_intr___pa7___lsb 7 | ||
| 167 | #define reg_gio_r_intr___pa7___width 1 | ||
| 168 | #define reg_gio_r_intr___pa7___bit 7 | ||
| 169 | #define reg_gio_r_intr_offset 24 | ||
| 170 | |||
| 171 | /* Register r_masked_intr, scope gio, type r */ | ||
| 172 | #define reg_gio_r_masked_intr___pa0___lsb 0 | ||
| 173 | #define reg_gio_r_masked_intr___pa0___width 1 | ||
| 174 | #define reg_gio_r_masked_intr___pa0___bit 0 | ||
| 175 | #define reg_gio_r_masked_intr___pa1___lsb 1 | ||
| 176 | #define reg_gio_r_masked_intr___pa1___width 1 | ||
| 177 | #define reg_gio_r_masked_intr___pa1___bit 1 | ||
| 178 | #define reg_gio_r_masked_intr___pa2___lsb 2 | ||
| 179 | #define reg_gio_r_masked_intr___pa2___width 1 | ||
| 180 | #define reg_gio_r_masked_intr___pa2___bit 2 | ||
| 181 | #define reg_gio_r_masked_intr___pa3___lsb 3 | ||
| 182 | #define reg_gio_r_masked_intr___pa3___width 1 | ||
| 183 | #define reg_gio_r_masked_intr___pa3___bit 3 | ||
| 184 | #define reg_gio_r_masked_intr___pa4___lsb 4 | ||
| 185 | #define reg_gio_r_masked_intr___pa4___width 1 | ||
| 186 | #define reg_gio_r_masked_intr___pa4___bit 4 | ||
| 187 | #define reg_gio_r_masked_intr___pa5___lsb 5 | ||
| 188 | #define reg_gio_r_masked_intr___pa5___width 1 | ||
| 189 | #define reg_gio_r_masked_intr___pa5___bit 5 | ||
| 190 | #define reg_gio_r_masked_intr___pa6___lsb 6 | ||
| 191 | #define reg_gio_r_masked_intr___pa6___width 1 | ||
| 192 | #define reg_gio_r_masked_intr___pa6___bit 6 | ||
| 193 | #define reg_gio_r_masked_intr___pa7___lsb 7 | ||
| 194 | #define reg_gio_r_masked_intr___pa7___width 1 | ||
| 195 | #define reg_gio_r_masked_intr___pa7___bit 7 | ||
| 196 | #define reg_gio_r_masked_intr_offset 28 | ||
| 197 | |||
| 198 | /* Register rw_pb_dout, scope gio, type rw */ | ||
| 199 | #define reg_gio_rw_pb_dout___data___lsb 0 | ||
| 200 | #define reg_gio_rw_pb_dout___data___width 18 | ||
| 201 | #define reg_gio_rw_pb_dout_offset 32 | ||
| 202 | |||
| 203 | /* Register r_pb_din, scope gio, type r */ | ||
| 204 | #define reg_gio_r_pb_din___data___lsb 0 | ||
| 205 | #define reg_gio_r_pb_din___data___width 18 | ||
| 206 | #define reg_gio_r_pb_din_offset 36 | ||
| 207 | |||
| 208 | /* Register rw_pb_oe, scope gio, type rw */ | ||
| 209 | #define reg_gio_rw_pb_oe___oe___lsb 0 | ||
| 210 | #define reg_gio_rw_pb_oe___oe___width 18 | ||
| 211 | #define reg_gio_rw_pb_oe_offset 40 | ||
| 212 | |||
| 213 | /* Register rw_pc_dout, scope gio, type rw */ | ||
| 214 | #define reg_gio_rw_pc_dout___data___lsb 0 | ||
| 215 | #define reg_gio_rw_pc_dout___data___width 18 | ||
| 216 | #define reg_gio_rw_pc_dout_offset 48 | ||
| 217 | |||
| 218 | /* Register r_pc_din, scope gio, type r */ | ||
| 219 | #define reg_gio_r_pc_din___data___lsb 0 | ||
| 220 | #define reg_gio_r_pc_din___data___width 18 | ||
| 221 | #define reg_gio_r_pc_din_offset 52 | ||
| 222 | |||
| 223 | /* Register rw_pc_oe, scope gio, type rw */ | ||
| 224 | #define reg_gio_rw_pc_oe___oe___lsb 0 | ||
| 225 | #define reg_gio_rw_pc_oe___oe___width 18 | ||
| 226 | #define reg_gio_rw_pc_oe_offset 56 | ||
| 227 | |||
| 228 | /* Register rw_pd_dout, scope gio, type rw */ | ||
| 229 | #define reg_gio_rw_pd_dout___data___lsb 0 | ||
| 230 | #define reg_gio_rw_pd_dout___data___width 18 | ||
| 231 | #define reg_gio_rw_pd_dout_offset 64 | ||
| 232 | |||
| 233 | /* Register r_pd_din, scope gio, type r */ | ||
| 234 | #define reg_gio_r_pd_din___data___lsb 0 | ||
| 235 | #define reg_gio_r_pd_din___data___width 18 | ||
| 236 | #define reg_gio_r_pd_din_offset 68 | ||
| 237 | |||
| 238 | /* Register rw_pd_oe, scope gio, type rw */ | ||
| 239 | #define reg_gio_rw_pd_oe___oe___lsb 0 | ||
| 240 | #define reg_gio_rw_pd_oe___oe___width 18 | ||
| 241 | #define reg_gio_rw_pd_oe_offset 72 | ||
| 242 | |||
| 243 | /* Register rw_pe_dout, scope gio, type rw */ | ||
| 244 | #define reg_gio_rw_pe_dout___data___lsb 0 | ||
| 245 | #define reg_gio_rw_pe_dout___data___width 18 | ||
| 246 | #define reg_gio_rw_pe_dout_offset 80 | ||
| 247 | |||
| 248 | /* Register r_pe_din, scope gio, type r */ | ||
| 249 | #define reg_gio_r_pe_din___data___lsb 0 | ||
| 250 | #define reg_gio_r_pe_din___data___width 18 | ||
| 251 | #define reg_gio_r_pe_din_offset 84 | ||
| 252 | |||
| 253 | /* Register rw_pe_oe, scope gio, type rw */ | ||
| 254 | #define reg_gio_rw_pe_oe___oe___lsb 0 | ||
| 255 | #define reg_gio_rw_pe_oe___oe___width 18 | ||
| 256 | #define reg_gio_rw_pe_oe_offset 88 | ||
| 257 | |||
| 258 | |||
| 259 | /* Constants */ | ||
| 260 | #define regk_gio_anyedge 0x00000007 | ||
| 261 | #define regk_gio_hi 0x00000001 | ||
| 262 | #define regk_gio_lo 0x00000002 | ||
| 263 | #define regk_gio_negedge 0x00000006 | ||
| 264 | #define regk_gio_no 0x00000000 | ||
| 265 | #define regk_gio_off 0x00000000 | ||
| 266 | #define regk_gio_posedge 0x00000005 | ||
| 267 | #define regk_gio_rw_intr_cfg_default 0x00000000 | ||
| 268 | #define regk_gio_rw_intr_mask_default 0x00000000 | ||
| 269 | #define regk_gio_rw_pa_oe_default 0x00000000 | ||
| 270 | #define regk_gio_rw_pb_oe_default 0x00000000 | ||
| 271 | #define regk_gio_rw_pc_oe_default 0x00000000 | ||
| 272 | #define regk_gio_rw_pd_oe_default 0x00000000 | ||
| 273 | #define regk_gio_rw_pe_oe_default 0x00000000 | ||
| 274 | #define regk_gio_set 0x00000003 | ||
| 275 | #define regk_gio_yes 0x00000001 | ||
| 276 | #endif /* __gio_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h new file mode 100644 index 000000000000..30cf5a936b64 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/pinmux_defs_asm.h | |||
| @@ -0,0 +1,632 @@ | |||
| 1 | #ifndef __pinmux_defs_asm_h | ||
| 2 | #define __pinmux_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 7 | * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:11 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 11 | * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_pa, scope pinmux, type rw */ | ||
| 57 | #define reg_pinmux_rw_pa___pa0___lsb 0 | ||
| 58 | #define reg_pinmux_rw_pa___pa0___width 1 | ||
| 59 | #define reg_pinmux_rw_pa___pa0___bit 0 | ||
| 60 | #define reg_pinmux_rw_pa___pa1___lsb 1 | ||
| 61 | #define reg_pinmux_rw_pa___pa1___width 1 | ||
| 62 | #define reg_pinmux_rw_pa___pa1___bit 1 | ||
| 63 | #define reg_pinmux_rw_pa___pa2___lsb 2 | ||
| 64 | #define reg_pinmux_rw_pa___pa2___width 1 | ||
| 65 | #define reg_pinmux_rw_pa___pa2___bit 2 | ||
| 66 | #define reg_pinmux_rw_pa___pa3___lsb 3 | ||
| 67 | #define reg_pinmux_rw_pa___pa3___width 1 | ||
| 68 | #define reg_pinmux_rw_pa___pa3___bit 3 | ||
| 69 | #define reg_pinmux_rw_pa___pa4___lsb 4 | ||
| 70 | #define reg_pinmux_rw_pa___pa4___width 1 | ||
| 71 | #define reg_pinmux_rw_pa___pa4___bit 4 | ||
| 72 | #define reg_pinmux_rw_pa___pa5___lsb 5 | ||
| 73 | #define reg_pinmux_rw_pa___pa5___width 1 | ||
| 74 | #define reg_pinmux_rw_pa___pa5___bit 5 | ||
| 75 | #define reg_pinmux_rw_pa___pa6___lsb 6 | ||
| 76 | #define reg_pinmux_rw_pa___pa6___width 1 | ||
| 77 | #define reg_pinmux_rw_pa___pa6___bit 6 | ||
| 78 | #define reg_pinmux_rw_pa___pa7___lsb 7 | ||
| 79 | #define reg_pinmux_rw_pa___pa7___width 1 | ||
| 80 | #define reg_pinmux_rw_pa___pa7___bit 7 | ||
| 81 | #define reg_pinmux_rw_pa___csp2_n___lsb 8 | ||
| 82 | #define reg_pinmux_rw_pa___csp2_n___width 1 | ||
| 83 | #define reg_pinmux_rw_pa___csp2_n___bit 8 | ||
| 84 | #define reg_pinmux_rw_pa___csp3_n___lsb 9 | ||
| 85 | #define reg_pinmux_rw_pa___csp3_n___width 1 | ||
| 86 | #define reg_pinmux_rw_pa___csp3_n___bit 9 | ||
| 87 | #define reg_pinmux_rw_pa___csp5_n___lsb 10 | ||
| 88 | #define reg_pinmux_rw_pa___csp5_n___width 1 | ||
| 89 | #define reg_pinmux_rw_pa___csp5_n___bit 10 | ||
| 90 | #define reg_pinmux_rw_pa___csp6_n___lsb 11 | ||
| 91 | #define reg_pinmux_rw_pa___csp6_n___width 1 | ||
| 92 | #define reg_pinmux_rw_pa___csp6_n___bit 11 | ||
| 93 | #define reg_pinmux_rw_pa___hsh4___lsb 12 | ||
| 94 | #define reg_pinmux_rw_pa___hsh4___width 1 | ||
| 95 | #define reg_pinmux_rw_pa___hsh4___bit 12 | ||
| 96 | #define reg_pinmux_rw_pa___hsh5___lsb 13 | ||
| 97 | #define reg_pinmux_rw_pa___hsh5___width 1 | ||
| 98 | #define reg_pinmux_rw_pa___hsh5___bit 13 | ||
| 99 | #define reg_pinmux_rw_pa___hsh6___lsb 14 | ||
| 100 | #define reg_pinmux_rw_pa___hsh6___width 1 | ||
| 101 | #define reg_pinmux_rw_pa___hsh6___bit 14 | ||
| 102 | #define reg_pinmux_rw_pa___hsh7___lsb 15 | ||
| 103 | #define reg_pinmux_rw_pa___hsh7___width 1 | ||
| 104 | #define reg_pinmux_rw_pa___hsh7___bit 15 | ||
| 105 | #define reg_pinmux_rw_pa_offset 0 | ||
| 106 | |||
| 107 | /* Register rw_hwprot, scope pinmux, type rw */ | ||
| 108 | #define reg_pinmux_rw_hwprot___ser1___lsb 0 | ||
| 109 | #define reg_pinmux_rw_hwprot___ser1___width 1 | ||
| 110 | #define reg_pinmux_rw_hwprot___ser1___bit 0 | ||
| 111 | #define reg_pinmux_rw_hwprot___ser2___lsb 1 | ||
| 112 | #define reg_pinmux_rw_hwprot___ser2___width 1 | ||
| 113 | #define reg_pinmux_rw_hwprot___ser2___bit 1 | ||
| 114 | #define reg_pinmux_rw_hwprot___ser3___lsb 2 | ||
| 115 | #define reg_pinmux_rw_hwprot___ser3___width 1 | ||
| 116 | #define reg_pinmux_rw_hwprot___ser3___bit 2 | ||
| 117 | #define reg_pinmux_rw_hwprot___sser0___lsb 3 | ||
| 118 | #define reg_pinmux_rw_hwprot___sser0___width 1 | ||
| 119 | #define reg_pinmux_rw_hwprot___sser0___bit 3 | ||
| 120 | #define reg_pinmux_rw_hwprot___sser1___lsb 4 | ||
| 121 | #define reg_pinmux_rw_hwprot___sser1___width 1 | ||
| 122 | #define reg_pinmux_rw_hwprot___sser1___bit 4 | ||
| 123 | #define reg_pinmux_rw_hwprot___ata0___lsb 5 | ||
| 124 | #define reg_pinmux_rw_hwprot___ata0___width 1 | ||
| 125 | #define reg_pinmux_rw_hwprot___ata0___bit 5 | ||
| 126 | #define reg_pinmux_rw_hwprot___ata1___lsb 6 | ||
| 127 | #define reg_pinmux_rw_hwprot___ata1___width 1 | ||
| 128 | #define reg_pinmux_rw_hwprot___ata1___bit 6 | ||
| 129 | #define reg_pinmux_rw_hwprot___ata2___lsb 7 | ||
| 130 | #define reg_pinmux_rw_hwprot___ata2___width 1 | ||
| 131 | #define reg_pinmux_rw_hwprot___ata2___bit 7 | ||
| 132 | #define reg_pinmux_rw_hwprot___ata3___lsb 8 | ||
| 133 | #define reg_pinmux_rw_hwprot___ata3___width 1 | ||
| 134 | #define reg_pinmux_rw_hwprot___ata3___bit 8 | ||
| 135 | #define reg_pinmux_rw_hwprot___ata___lsb 9 | ||
| 136 | #define reg_pinmux_rw_hwprot___ata___width 1 | ||
| 137 | #define reg_pinmux_rw_hwprot___ata___bit 9 | ||
| 138 | #define reg_pinmux_rw_hwprot___eth1___lsb 10 | ||
| 139 | #define reg_pinmux_rw_hwprot___eth1___width 1 | ||
| 140 | #define reg_pinmux_rw_hwprot___eth1___bit 10 | ||
| 141 | #define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 | ||
| 142 | #define reg_pinmux_rw_hwprot___eth1_mgm___width 1 | ||
| 143 | #define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 | ||
| 144 | #define reg_pinmux_rw_hwprot___timer___lsb 12 | ||
| 145 | #define reg_pinmux_rw_hwprot___timer___width 1 | ||
| 146 | #define reg_pinmux_rw_hwprot___timer___bit 12 | ||
| 147 | #define reg_pinmux_rw_hwprot___p21___lsb 13 | ||
| 148 | #define reg_pinmux_rw_hwprot___p21___width 1 | ||
| 149 | #define reg_pinmux_rw_hwprot___p21___bit 13 | ||
| 150 | #define reg_pinmux_rw_hwprot_offset 4 | ||
| 151 | |||
| 152 | /* Register rw_pb_gio, scope pinmux, type rw */ | ||
| 153 | #define reg_pinmux_rw_pb_gio___pb0___lsb 0 | ||
| 154 | #define reg_pinmux_rw_pb_gio___pb0___width 1 | ||
| 155 | #define reg_pinmux_rw_pb_gio___pb0___bit 0 | ||
| 156 | #define reg_pinmux_rw_pb_gio___pb1___lsb 1 | ||
| 157 | #define reg_pinmux_rw_pb_gio___pb1___width 1 | ||
| 158 | #define reg_pinmux_rw_pb_gio___pb1___bit 1 | ||
| 159 | #define reg_pinmux_rw_pb_gio___pb2___lsb 2 | ||
| 160 | #define reg_pinmux_rw_pb_gio___pb2___width 1 | ||
| 161 | #define reg_pinmux_rw_pb_gio___pb2___bit 2 | ||
| 162 | #define reg_pinmux_rw_pb_gio___pb3___lsb 3 | ||
| 163 | #define reg_pinmux_rw_pb_gio___pb3___width 1 | ||
| 164 | #define reg_pinmux_rw_pb_gio___pb3___bit 3 | ||
| 165 | #define reg_pinmux_rw_pb_gio___pb4___lsb 4 | ||
| 166 | #define reg_pinmux_rw_pb_gio___pb4___width 1 | ||
| 167 | #define reg_pinmux_rw_pb_gio___pb4___bit 4 | ||
| 168 | #define reg_pinmux_rw_pb_gio___pb5___lsb 5 | ||
| 169 | #define reg_pinmux_rw_pb_gio___pb5___width 1 | ||
| 170 | #define reg_pinmux_rw_pb_gio___pb5___bit 5 | ||
| 171 | #define reg_pinmux_rw_pb_gio___pb6___lsb 6 | ||
| 172 | #define reg_pinmux_rw_pb_gio___pb6___width 1 | ||
| 173 | #define reg_pinmux_rw_pb_gio___pb6___bit 6 | ||
| 174 | #define reg_pinmux_rw_pb_gio___pb7___lsb 7 | ||
| 175 | #define reg_pinmux_rw_pb_gio___pb7___width 1 | ||
| 176 | #define reg_pinmux_rw_pb_gio___pb7___bit 7 | ||
| 177 | #define reg_pinmux_rw_pb_gio___pb8___lsb 8 | ||
| 178 | #define reg_pinmux_rw_pb_gio___pb8___width 1 | ||
| 179 | #define reg_pinmux_rw_pb_gio___pb8___bit 8 | ||
| 180 | #define reg_pinmux_rw_pb_gio___pb9___lsb 9 | ||
| 181 | #define reg_pinmux_rw_pb_gio___pb9___width 1 | ||
| 182 | #define reg_pinmux_rw_pb_gio___pb9___bit 9 | ||
| 183 | #define reg_pinmux_rw_pb_gio___pb10___lsb 10 | ||
| 184 | #define reg_pinmux_rw_pb_gio___pb10___width 1 | ||
| 185 | #define reg_pinmux_rw_pb_gio___pb10___bit 10 | ||
| 186 | #define reg_pinmux_rw_pb_gio___pb11___lsb 11 | ||
| 187 | #define reg_pinmux_rw_pb_gio___pb11___width 1 | ||
| 188 | #define reg_pinmux_rw_pb_gio___pb11___bit 11 | ||
| 189 | #define reg_pinmux_rw_pb_gio___pb12___lsb 12 | ||
| 190 | #define reg_pinmux_rw_pb_gio___pb12___width 1 | ||
| 191 | #define reg_pinmux_rw_pb_gio___pb12___bit 12 | ||
| 192 | #define reg_pinmux_rw_pb_gio___pb13___lsb 13 | ||
| 193 | #define reg_pinmux_rw_pb_gio___pb13___width 1 | ||
| 194 | #define reg_pinmux_rw_pb_gio___pb13___bit 13 | ||
| 195 | #define reg_pinmux_rw_pb_gio___pb14___lsb 14 | ||
| 196 | #define reg_pinmux_rw_pb_gio___pb14___width 1 | ||
| 197 | #define reg_pinmux_rw_pb_gio___pb14___bit 14 | ||
| 198 | #define reg_pinmux_rw_pb_gio___pb15___lsb 15 | ||
| 199 | #define reg_pinmux_rw_pb_gio___pb15___width 1 | ||
| 200 | #define reg_pinmux_rw_pb_gio___pb15___bit 15 | ||
| 201 | #define reg_pinmux_rw_pb_gio___pb16___lsb 16 | ||
| 202 | #define reg_pinmux_rw_pb_gio___pb16___width 1 | ||
| 203 | #define reg_pinmux_rw_pb_gio___pb16___bit 16 | ||
| 204 | #define reg_pinmux_rw_pb_gio___pb17___lsb 17 | ||
| 205 | #define reg_pinmux_rw_pb_gio___pb17___width 1 | ||
| 206 | #define reg_pinmux_rw_pb_gio___pb17___bit 17 | ||
| 207 | #define reg_pinmux_rw_pb_gio_offset 8 | ||
| 208 | |||
| 209 | /* Register rw_pb_iop, scope pinmux, type rw */ | ||
| 210 | #define reg_pinmux_rw_pb_iop___pb0___lsb 0 | ||
| 211 | #define reg_pinmux_rw_pb_iop___pb0___width 1 | ||
| 212 | #define reg_pinmux_rw_pb_iop___pb0___bit 0 | ||
| 213 | #define reg_pinmux_rw_pb_iop___pb1___lsb 1 | ||
| 214 | #define reg_pinmux_rw_pb_iop___pb1___width 1 | ||
| 215 | #define reg_pinmux_rw_pb_iop___pb1___bit 1 | ||
| 216 | #define reg_pinmux_rw_pb_iop___pb2___lsb 2 | ||
| 217 | #define reg_pinmux_rw_pb_iop___pb2___width 1 | ||
| 218 | #define reg_pinmux_rw_pb_iop___pb2___bit 2 | ||
| 219 | #define reg_pinmux_rw_pb_iop___pb3___lsb 3 | ||
| 220 | #define reg_pinmux_rw_pb_iop___pb3___width 1 | ||
| 221 | #define reg_pinmux_rw_pb_iop___pb3___bit 3 | ||
| 222 | #define reg_pinmux_rw_pb_iop___pb4___lsb 4 | ||
| 223 | #define reg_pinmux_rw_pb_iop___pb4___width 1 | ||
| 224 | #define reg_pinmux_rw_pb_iop___pb4___bit 4 | ||
| 225 | #define reg_pinmux_rw_pb_iop___pb5___lsb 5 | ||
| 226 | #define reg_pinmux_rw_pb_iop___pb5___width 1 | ||
| 227 | #define reg_pinmux_rw_pb_iop___pb5___bit 5 | ||
| 228 | #define reg_pinmux_rw_pb_iop___pb6___lsb 6 | ||
| 229 | #define reg_pinmux_rw_pb_iop___pb6___width 1 | ||
| 230 | #define reg_pinmux_rw_pb_iop___pb6___bit 6 | ||
| 231 | #define reg_pinmux_rw_pb_iop___pb7___lsb 7 | ||
| 232 | #define reg_pinmux_rw_pb_iop___pb7___width 1 | ||
| 233 | #define reg_pinmux_rw_pb_iop___pb7___bit 7 | ||
| 234 | #define reg_pinmux_rw_pb_iop___pb8___lsb 8 | ||
| 235 | #define reg_pinmux_rw_pb_iop___pb8___width 1 | ||
| 236 | #define reg_pinmux_rw_pb_iop___pb8___bit 8 | ||
| 237 | #define reg_pinmux_rw_pb_iop___pb9___lsb 9 | ||
| 238 | #define reg_pinmux_rw_pb_iop___pb9___width 1 | ||
| 239 | #define reg_pinmux_rw_pb_iop___pb9___bit 9 | ||
| 240 | #define reg_pinmux_rw_pb_iop___pb10___lsb 10 | ||
| 241 | #define reg_pinmux_rw_pb_iop___pb10___width 1 | ||
| 242 | #define reg_pinmux_rw_pb_iop___pb10___bit 10 | ||
| 243 | #define reg_pinmux_rw_pb_iop___pb11___lsb 11 | ||
| 244 | #define reg_pinmux_rw_pb_iop___pb11___width 1 | ||
| 245 | #define reg_pinmux_rw_pb_iop___pb11___bit 11 | ||
| 246 | #define reg_pinmux_rw_pb_iop___pb12___lsb 12 | ||
| 247 | #define reg_pinmux_rw_pb_iop___pb12___width 1 | ||
| 248 | #define reg_pinmux_rw_pb_iop___pb12___bit 12 | ||
| 249 | #define reg_pinmux_rw_pb_iop___pb13___lsb 13 | ||
| 250 | #define reg_pinmux_rw_pb_iop___pb13___width 1 | ||
| 251 | #define reg_pinmux_rw_pb_iop___pb13___bit 13 | ||
| 252 | #define reg_pinmux_rw_pb_iop___pb14___lsb 14 | ||
| 253 | #define reg_pinmux_rw_pb_iop___pb14___width 1 | ||
| 254 | #define reg_pinmux_rw_pb_iop___pb14___bit 14 | ||
| 255 | #define reg_pinmux_rw_pb_iop___pb15___lsb 15 | ||
| 256 | #define reg_pinmux_rw_pb_iop___pb15___width 1 | ||
| 257 | #define reg_pinmux_rw_pb_iop___pb15___bit 15 | ||
| 258 | #define reg_pinmux_rw_pb_iop___pb16___lsb 16 | ||
| 259 | #define reg_pinmux_rw_pb_iop___pb16___width 1 | ||
| 260 | #define reg_pinmux_rw_pb_iop___pb16___bit 16 | ||
| 261 | #define reg_pinmux_rw_pb_iop___pb17___lsb 17 | ||
| 262 | #define reg_pinmux_rw_pb_iop___pb17___width 1 | ||
| 263 | #define reg_pinmux_rw_pb_iop___pb17___bit 17 | ||
| 264 | #define reg_pinmux_rw_pb_iop_offset 12 | ||
| 265 | |||
| 266 | /* Register rw_pc_gio, scope pinmux, type rw */ | ||
| 267 | #define reg_pinmux_rw_pc_gio___pc0___lsb 0 | ||
| 268 | #define reg_pinmux_rw_pc_gio___pc0___width 1 | ||
| 269 | #define reg_pinmux_rw_pc_gio___pc0___bit 0 | ||
| 270 | #define reg_pinmux_rw_pc_gio___pc1___lsb 1 | ||
| 271 | #define reg_pinmux_rw_pc_gio___pc1___width 1 | ||
| 272 | #define reg_pinmux_rw_pc_gio___pc1___bit 1 | ||
| 273 | #define reg_pinmux_rw_pc_gio___pc2___lsb 2 | ||
| 274 | #define reg_pinmux_rw_pc_gio___pc2___width 1 | ||
| 275 | #define reg_pinmux_rw_pc_gio___pc2___bit 2 | ||
| 276 | #define reg_pinmux_rw_pc_gio___pc3___lsb 3 | ||
| 277 | #define reg_pinmux_rw_pc_gio___pc3___width 1 | ||
| 278 | #define reg_pinmux_rw_pc_gio___pc3___bit 3 | ||
| 279 | #define reg_pinmux_rw_pc_gio___pc4___lsb 4 | ||
| 280 | #define reg_pinmux_rw_pc_gio___pc4___width 1 | ||
| 281 | #define reg_pinmux_rw_pc_gio___pc4___bit 4 | ||
| 282 | #define reg_pinmux_rw_pc_gio___pc5___lsb 5 | ||
| 283 | #define reg_pinmux_rw_pc_gio___pc5___width 1 | ||
| 284 | #define reg_pinmux_rw_pc_gio___pc5___bit 5 | ||
| 285 | #define reg_pinmux_rw_pc_gio___pc6___lsb 6 | ||
| 286 | #define reg_pinmux_rw_pc_gio___pc6___width 1 | ||
| 287 | #define reg_pinmux_rw_pc_gio___pc6___bit 6 | ||
| 288 | #define reg_pinmux_rw_pc_gio___pc7___lsb 7 | ||
| 289 | #define reg_pinmux_rw_pc_gio___pc7___width 1 | ||
| 290 | #define reg_pinmux_rw_pc_gio___pc7___bit 7 | ||
| 291 | #define reg_pinmux_rw_pc_gio___pc8___lsb 8 | ||
| 292 | #define reg_pinmux_rw_pc_gio___pc8___width 1 | ||
| 293 | #define reg_pinmux_rw_pc_gio___pc8___bit 8 | ||
| 294 | #define reg_pinmux_rw_pc_gio___pc9___lsb 9 | ||
| 295 | #define reg_pinmux_rw_pc_gio___pc9___width 1 | ||
| 296 | #define reg_pinmux_rw_pc_gio___pc9___bit 9 | ||
| 297 | #define reg_pinmux_rw_pc_gio___pc10___lsb 10 | ||
| 298 | #define reg_pinmux_rw_pc_gio___pc10___width 1 | ||
| 299 | #define reg_pinmux_rw_pc_gio___pc10___bit 10 | ||
| 300 | #define reg_pinmux_rw_pc_gio___pc11___lsb 11 | ||
| 301 | #define reg_pinmux_rw_pc_gio___pc11___width 1 | ||
| 302 | #define reg_pinmux_rw_pc_gio___pc11___bit 11 | ||
| 303 | #define reg_pinmux_rw_pc_gio___pc12___lsb 12 | ||
| 304 | #define reg_pinmux_rw_pc_gio___pc12___width 1 | ||
| 305 | #define reg_pinmux_rw_pc_gio___pc12___bit 12 | ||
| 306 | #define reg_pinmux_rw_pc_gio___pc13___lsb 13 | ||
| 307 | #define reg_pinmux_rw_pc_gio___pc13___width 1 | ||
| 308 | #define reg_pinmux_rw_pc_gio___pc13___bit 13 | ||
| 309 | #define reg_pinmux_rw_pc_gio___pc14___lsb 14 | ||
| 310 | #define reg_pinmux_rw_pc_gio___pc14___width 1 | ||
| 311 | #define reg_pinmux_rw_pc_gio___pc14___bit 14 | ||
| 312 | #define reg_pinmux_rw_pc_gio___pc15___lsb 15 | ||
| 313 | #define reg_pinmux_rw_pc_gio___pc15___width 1 | ||
| 314 | #define reg_pinmux_rw_pc_gio___pc15___bit 15 | ||
| 315 | #define reg_pinmux_rw_pc_gio___pc16___lsb 16 | ||
| 316 | #define reg_pinmux_rw_pc_gio___pc16___width 1 | ||
| 317 | #define reg_pinmux_rw_pc_gio___pc16___bit 16 | ||
| 318 | #define reg_pinmux_rw_pc_gio___pc17___lsb 17 | ||
| 319 | #define reg_pinmux_rw_pc_gio___pc17___width 1 | ||
| 320 | #define reg_pinmux_rw_pc_gio___pc17___bit 17 | ||
| 321 | #define reg_pinmux_rw_pc_gio_offset 16 | ||
| 322 | |||
| 323 | /* Register rw_pc_iop, scope pinmux, type rw */ | ||
| 324 | #define reg_pinmux_rw_pc_iop___pc0___lsb 0 | ||
| 325 | #define reg_pinmux_rw_pc_iop___pc0___width 1 | ||
| 326 | #define reg_pinmux_rw_pc_iop___pc0___bit 0 | ||
| 327 | #define reg_pinmux_rw_pc_iop___pc1___lsb 1 | ||
| 328 | #define reg_pinmux_rw_pc_iop___pc1___width 1 | ||
| 329 | #define reg_pinmux_rw_pc_iop___pc1___bit 1 | ||
| 330 | #define reg_pinmux_rw_pc_iop___pc2___lsb 2 | ||
| 331 | #define reg_pinmux_rw_pc_iop___pc2___width 1 | ||
| 332 | #define reg_pinmux_rw_pc_iop___pc2___bit 2 | ||
| 333 | #define reg_pinmux_rw_pc_iop___pc3___lsb 3 | ||
| 334 | #define reg_pinmux_rw_pc_iop___pc3___width 1 | ||
| 335 | #define reg_pinmux_rw_pc_iop___pc3___bit 3 | ||
| 336 | #define reg_pinmux_rw_pc_iop___pc4___lsb 4 | ||
| 337 | #define reg_pinmux_rw_pc_iop___pc4___width 1 | ||
| 338 | #define reg_pinmux_rw_pc_iop___pc4___bit 4 | ||
| 339 | #define reg_pinmux_rw_pc_iop___pc5___lsb 5 | ||
| 340 | #define reg_pinmux_rw_pc_iop___pc5___width 1 | ||
| 341 | #define reg_pinmux_rw_pc_iop___pc5___bit 5 | ||
| 342 | #define reg_pinmux_rw_pc_iop___pc6___lsb 6 | ||
| 343 | #define reg_pinmux_rw_pc_iop___pc6___width 1 | ||
| 344 | #define reg_pinmux_rw_pc_iop___pc6___bit 6 | ||
| 345 | #define reg_pinmux_rw_pc_iop___pc7___lsb 7 | ||
| 346 | #define reg_pinmux_rw_pc_iop___pc7___width 1 | ||
| 347 | #define reg_pinmux_rw_pc_iop___pc7___bit 7 | ||
| 348 | #define reg_pinmux_rw_pc_iop___pc8___lsb 8 | ||
| 349 | #define reg_pinmux_rw_pc_iop___pc8___width 1 | ||
| 350 | #define reg_pinmux_rw_pc_iop___pc8___bit 8 | ||
| 351 | #define reg_pinmux_rw_pc_iop___pc9___lsb 9 | ||
| 352 | #define reg_pinmux_rw_pc_iop___pc9___width 1 | ||
| 353 | #define reg_pinmux_rw_pc_iop___pc9___bit 9 | ||
| 354 | #define reg_pinmux_rw_pc_iop___pc10___lsb 10 | ||
| 355 | #define reg_pinmux_rw_pc_iop___pc10___width 1 | ||
| 356 | #define reg_pinmux_rw_pc_iop___pc10___bit 10 | ||
| 357 | #define reg_pinmux_rw_pc_iop___pc11___lsb 11 | ||
| 358 | #define reg_pinmux_rw_pc_iop___pc11___width 1 | ||
| 359 | #define reg_pinmux_rw_pc_iop___pc11___bit 11 | ||
| 360 | #define reg_pinmux_rw_pc_iop___pc12___lsb 12 | ||
| 361 | #define reg_pinmux_rw_pc_iop___pc12___width 1 | ||
| 362 | #define reg_pinmux_rw_pc_iop___pc12___bit 12 | ||
| 363 | #define reg_pinmux_rw_pc_iop___pc13___lsb 13 | ||
| 364 | #define reg_pinmux_rw_pc_iop___pc13___width 1 | ||
| 365 | #define reg_pinmux_rw_pc_iop___pc13___bit 13 | ||
| 366 | #define reg_pinmux_rw_pc_iop___pc14___lsb 14 | ||
| 367 | #define reg_pinmux_rw_pc_iop___pc14___width 1 | ||
| 368 | #define reg_pinmux_rw_pc_iop___pc14___bit 14 | ||
| 369 | #define reg_pinmux_rw_pc_iop___pc15___lsb 15 | ||
| 370 | #define reg_pinmux_rw_pc_iop___pc15___width 1 | ||
| 371 | #define reg_pinmux_rw_pc_iop___pc15___bit 15 | ||
| 372 | #define reg_pinmux_rw_pc_iop___pc16___lsb 16 | ||
| 373 | #define reg_pinmux_rw_pc_iop___pc16___width 1 | ||
| 374 | #define reg_pinmux_rw_pc_iop___pc16___bit 16 | ||
| 375 | #define reg_pinmux_rw_pc_iop___pc17___lsb 17 | ||
| 376 | #define reg_pinmux_rw_pc_iop___pc17___width 1 | ||
| 377 | #define reg_pinmux_rw_pc_iop___pc17___bit 17 | ||
| 378 | #define reg_pinmux_rw_pc_iop_offset 20 | ||
| 379 | |||
| 380 | /* Register rw_pd_gio, scope pinmux, type rw */ | ||
| 381 | #define reg_pinmux_rw_pd_gio___pd0___lsb 0 | ||
| 382 | #define reg_pinmux_rw_pd_gio___pd0___width 1 | ||
| 383 | #define reg_pinmux_rw_pd_gio___pd0___bit 0 | ||
| 384 | #define reg_pinmux_rw_pd_gio___pd1___lsb 1 | ||
| 385 | #define reg_pinmux_rw_pd_gio___pd1___width 1 | ||
| 386 | #define reg_pinmux_rw_pd_gio___pd1___bit 1 | ||
| 387 | #define reg_pinmux_rw_pd_gio___pd2___lsb 2 | ||
| 388 | #define reg_pinmux_rw_pd_gio___pd2___width 1 | ||
| 389 | #define reg_pinmux_rw_pd_gio___pd2___bit 2 | ||
| 390 | #define reg_pinmux_rw_pd_gio___pd3___lsb 3 | ||
| 391 | #define reg_pinmux_rw_pd_gio___pd3___width 1 | ||
| 392 | #define reg_pinmux_rw_pd_gio___pd3___bit 3 | ||
| 393 | #define reg_pinmux_rw_pd_gio___pd4___lsb 4 | ||
| 394 | #define reg_pinmux_rw_pd_gio___pd4___width 1 | ||
| 395 | #define reg_pinmux_rw_pd_gio___pd4___bit 4 | ||
| 396 | #define reg_pinmux_rw_pd_gio___pd5___lsb 5 | ||
| 397 | #define reg_pinmux_rw_pd_gio___pd5___width 1 | ||
| 398 | #define reg_pinmux_rw_pd_gio___pd5___bit 5 | ||
| 399 | #define reg_pinmux_rw_pd_gio___pd6___lsb 6 | ||
| 400 | #define reg_pinmux_rw_pd_gio___pd6___width 1 | ||
| 401 | #define reg_pinmux_rw_pd_gio___pd6___bit 6 | ||
| 402 | #define reg_pinmux_rw_pd_gio___pd7___lsb 7 | ||
| 403 | #define reg_pinmux_rw_pd_gio___pd7___width 1 | ||
| 404 | #define reg_pinmux_rw_pd_gio___pd7___bit 7 | ||
| 405 | #define reg_pinmux_rw_pd_gio___pd8___lsb 8 | ||
| 406 | #define reg_pinmux_rw_pd_gio___pd8___width 1 | ||
| 407 | #define reg_pinmux_rw_pd_gio___pd8___bit 8 | ||
| 408 | #define reg_pinmux_rw_pd_gio___pd9___lsb 9 | ||
| 409 | #define reg_pinmux_rw_pd_gio___pd9___width 1 | ||
| 410 | #define reg_pinmux_rw_pd_gio___pd9___bit 9 | ||
| 411 | #define reg_pinmux_rw_pd_gio___pd10___lsb 10 | ||
| 412 | #define reg_pinmux_rw_pd_gio___pd10___width 1 | ||
| 413 | #define reg_pinmux_rw_pd_gio___pd10___bit 10 | ||
| 414 | #define reg_pinmux_rw_pd_gio___pd11___lsb 11 | ||
| 415 | #define reg_pinmux_rw_pd_gio___pd11___width 1 | ||
| 416 | #define reg_pinmux_rw_pd_gio___pd11___bit 11 | ||
| 417 | #define reg_pinmux_rw_pd_gio___pd12___lsb 12 | ||
| 418 | #define reg_pinmux_rw_pd_gio___pd12___width 1 | ||
| 419 | #define reg_pinmux_rw_pd_gio___pd12___bit 12 | ||
| 420 | #define reg_pinmux_rw_pd_gio___pd13___lsb 13 | ||
| 421 | #define reg_pinmux_rw_pd_gio___pd13___width 1 | ||
| 422 | #define reg_pinmux_rw_pd_gio___pd13___bit 13 | ||
| 423 | #define reg_pinmux_rw_pd_gio___pd14___lsb 14 | ||
| 424 | #define reg_pinmux_rw_pd_gio___pd14___width 1 | ||
| 425 | #define reg_pinmux_rw_pd_gio___pd14___bit 14 | ||
| 426 | #define reg_pinmux_rw_pd_gio___pd15___lsb 15 | ||
| 427 | #define reg_pinmux_rw_pd_gio___pd15___width 1 | ||
| 428 | #define reg_pinmux_rw_pd_gio___pd15___bit 15 | ||
| 429 | #define reg_pinmux_rw_pd_gio___pd16___lsb 16 | ||
| 430 | #define reg_pinmux_rw_pd_gio___pd16___width 1 | ||
| 431 | #define reg_pinmux_rw_pd_gio___pd16___bit 16 | ||
| 432 | #define reg_pinmux_rw_pd_gio___pd17___lsb 17 | ||
| 433 | #define reg_pinmux_rw_pd_gio___pd17___width 1 | ||
| 434 | #define reg_pinmux_rw_pd_gio___pd17___bit 17 | ||
| 435 | #define reg_pinmux_rw_pd_gio_offset 24 | ||
| 436 | |||
| 437 | /* Register rw_pd_iop, scope pinmux, type rw */ | ||
| 438 | #define reg_pinmux_rw_pd_iop___pd0___lsb 0 | ||
| 439 | #define reg_pinmux_rw_pd_iop___pd0___width 1 | ||
| 440 | #define reg_pinmux_rw_pd_iop___pd0___bit 0 | ||
| 441 | #define reg_pinmux_rw_pd_iop___pd1___lsb 1 | ||
| 442 | #define reg_pinmux_rw_pd_iop___pd1___width 1 | ||
| 443 | #define reg_pinmux_rw_pd_iop___pd1___bit 1 | ||
| 444 | #define reg_pinmux_rw_pd_iop___pd2___lsb 2 | ||
| 445 | #define reg_pinmux_rw_pd_iop___pd2___width 1 | ||
| 446 | #define reg_pinmux_rw_pd_iop___pd2___bit 2 | ||
| 447 | #define reg_pinmux_rw_pd_iop___pd3___lsb 3 | ||
| 448 | #define reg_pinmux_rw_pd_iop___pd3___width 1 | ||
| 449 | #define reg_pinmux_rw_pd_iop___pd3___bit 3 | ||
| 450 | #define reg_pinmux_rw_pd_iop___pd4___lsb 4 | ||
| 451 | #define reg_pinmux_rw_pd_iop___pd4___width 1 | ||
| 452 | #define reg_pinmux_rw_pd_iop___pd4___bit 4 | ||
| 453 | #define reg_pinmux_rw_pd_iop___pd5___lsb 5 | ||
| 454 | #define reg_pinmux_rw_pd_iop___pd5___width 1 | ||
| 455 | #define reg_pinmux_rw_pd_iop___pd5___bit 5 | ||
| 456 | #define reg_pinmux_rw_pd_iop___pd6___lsb 6 | ||
| 457 | #define reg_pinmux_rw_pd_iop___pd6___width 1 | ||
| 458 | #define reg_pinmux_rw_pd_iop___pd6___bit 6 | ||
| 459 | #define reg_pinmux_rw_pd_iop___pd7___lsb 7 | ||
| 460 | #define reg_pinmux_rw_pd_iop___pd7___width 1 | ||
| 461 | #define reg_pinmux_rw_pd_iop___pd7___bit 7 | ||
| 462 | #define reg_pinmux_rw_pd_iop___pd8___lsb 8 | ||
| 463 | #define reg_pinmux_rw_pd_iop___pd8___width 1 | ||
| 464 | #define reg_pinmux_rw_pd_iop___pd8___bit 8 | ||
| 465 | #define reg_pinmux_rw_pd_iop___pd9___lsb 9 | ||
| 466 | #define reg_pinmux_rw_pd_iop___pd9___width 1 | ||
| 467 | #define reg_pinmux_rw_pd_iop___pd9___bit 9 | ||
| 468 | #define reg_pinmux_rw_pd_iop___pd10___lsb 10 | ||
| 469 | #define reg_pinmux_rw_pd_iop___pd10___width 1 | ||
| 470 | #define reg_pinmux_rw_pd_iop___pd10___bit 10 | ||
| 471 | #define reg_pinmux_rw_pd_iop___pd11___lsb 11 | ||
| 472 | #define reg_pinmux_rw_pd_iop___pd11___width 1 | ||
| 473 | #define reg_pinmux_rw_pd_iop___pd11___bit 11 | ||
| 474 | #define reg_pinmux_rw_pd_iop___pd12___lsb 12 | ||
| 475 | #define reg_pinmux_rw_pd_iop___pd12___width 1 | ||
| 476 | #define reg_pinmux_rw_pd_iop___pd12___bit 12 | ||
| 477 | #define reg_pinmux_rw_pd_iop___pd13___lsb 13 | ||
| 478 | #define reg_pinmux_rw_pd_iop___pd13___width 1 | ||
| 479 | #define reg_pinmux_rw_pd_iop___pd13___bit 13 | ||
| 480 | #define reg_pinmux_rw_pd_iop___pd14___lsb 14 | ||
| 481 | #define reg_pinmux_rw_pd_iop___pd14___width 1 | ||
| 482 | #define reg_pinmux_rw_pd_iop___pd14___bit 14 | ||
| 483 | #define reg_pinmux_rw_pd_iop___pd15___lsb 15 | ||
| 484 | #define reg_pinmux_rw_pd_iop___pd15___width 1 | ||
| 485 | #define reg_pinmux_rw_pd_iop___pd15___bit 15 | ||
| 486 | #define reg_pinmux_rw_pd_iop___pd16___lsb 16 | ||
| 487 | #define reg_pinmux_rw_pd_iop___pd16___width 1 | ||
| 488 | #define reg_pinmux_rw_pd_iop___pd16___bit 16 | ||
| 489 | #define reg_pinmux_rw_pd_iop___pd17___lsb 17 | ||
| 490 | #define reg_pinmux_rw_pd_iop___pd17___width 1 | ||
| 491 | #define reg_pinmux_rw_pd_iop___pd17___bit 17 | ||
| 492 | #define reg_pinmux_rw_pd_iop_offset 28 | ||
| 493 | |||
| 494 | /* Register rw_pe_gio, scope pinmux, type rw */ | ||
| 495 | #define reg_pinmux_rw_pe_gio___pe0___lsb 0 | ||
| 496 | #define reg_pinmux_rw_pe_gio___pe0___width 1 | ||
| 497 | #define reg_pinmux_rw_pe_gio___pe0___bit 0 | ||
| 498 | #define reg_pinmux_rw_pe_gio___pe1___lsb 1 | ||
| 499 | #define reg_pinmux_rw_pe_gio___pe1___width 1 | ||
| 500 | #define reg_pinmux_rw_pe_gio___pe1___bit 1 | ||
| 501 | #define reg_pinmux_rw_pe_gio___pe2___lsb 2 | ||
| 502 | #define reg_pinmux_rw_pe_gio___pe2___width 1 | ||
| 503 | #define reg_pinmux_rw_pe_gio___pe2___bit 2 | ||
| 504 | #define reg_pinmux_rw_pe_gio___pe3___lsb 3 | ||
| 505 | #define reg_pinmux_rw_pe_gio___pe3___width 1 | ||
| 506 | #define reg_pinmux_rw_pe_gio___pe3___bit 3 | ||
| 507 | #define reg_pinmux_rw_pe_gio___pe4___lsb 4 | ||
| 508 | #define reg_pinmux_rw_pe_gio___pe4___width 1 | ||
| 509 | #define reg_pinmux_rw_pe_gio___pe4___bit 4 | ||
| 510 | #define reg_pinmux_rw_pe_gio___pe5___lsb 5 | ||
| 511 | #define reg_pinmux_rw_pe_gio___pe5___width 1 | ||
| 512 | #define reg_pinmux_rw_pe_gio___pe5___bit 5 | ||
| 513 | #define reg_pinmux_rw_pe_gio___pe6___lsb 6 | ||
| 514 | #define reg_pinmux_rw_pe_gio___pe6___width 1 | ||
| 515 | #define reg_pinmux_rw_pe_gio___pe6___bit 6 | ||
| 516 | #define reg_pinmux_rw_pe_gio___pe7___lsb 7 | ||
| 517 | #define reg_pinmux_rw_pe_gio___pe7___width 1 | ||
| 518 | #define reg_pinmux_rw_pe_gio___pe7___bit 7 | ||
| 519 | #define reg_pinmux_rw_pe_gio___pe8___lsb 8 | ||
| 520 | #define reg_pinmux_rw_pe_gio___pe8___width 1 | ||
| 521 | #define reg_pinmux_rw_pe_gio___pe8___bit 8 | ||
| 522 | #define reg_pinmux_rw_pe_gio___pe9___lsb 9 | ||
| 523 | #define reg_pinmux_rw_pe_gio___pe9___width 1 | ||
| 524 | #define reg_pinmux_rw_pe_gio___pe9___bit 9 | ||
| 525 | #define reg_pinmux_rw_pe_gio___pe10___lsb 10 | ||
| 526 | #define reg_pinmux_rw_pe_gio___pe10___width 1 | ||
| 527 | #define reg_pinmux_rw_pe_gio___pe10___bit 10 | ||
| 528 | #define reg_pinmux_rw_pe_gio___pe11___lsb 11 | ||
| 529 | #define reg_pinmux_rw_pe_gio___pe11___width 1 | ||
| 530 | #define reg_pinmux_rw_pe_gio___pe11___bit 11 | ||
| 531 | #define reg_pinmux_rw_pe_gio___pe12___lsb 12 | ||
| 532 | #define reg_pinmux_rw_pe_gio___pe12___width 1 | ||
| 533 | #define reg_pinmux_rw_pe_gio___pe12___bit 12 | ||
| 534 | #define reg_pinmux_rw_pe_gio___pe13___lsb 13 | ||
| 535 | #define reg_pinmux_rw_pe_gio___pe13___width 1 | ||
| 536 | #define reg_pinmux_rw_pe_gio___pe13___bit 13 | ||
| 537 | #define reg_pinmux_rw_pe_gio___pe14___lsb 14 | ||
| 538 | #define reg_pinmux_rw_pe_gio___pe14___width 1 | ||
| 539 | #define reg_pinmux_rw_pe_gio___pe14___bit 14 | ||
| 540 | #define reg_pinmux_rw_pe_gio___pe15___lsb 15 | ||
| 541 | #define reg_pinmux_rw_pe_gio___pe15___width 1 | ||
| 542 | #define reg_pinmux_rw_pe_gio___pe15___bit 15 | ||
| 543 | #define reg_pinmux_rw_pe_gio___pe16___lsb 16 | ||
| 544 | #define reg_pinmux_rw_pe_gio___pe16___width 1 | ||
| 545 | #define reg_pinmux_rw_pe_gio___pe16___bit 16 | ||
| 546 | #define reg_pinmux_rw_pe_gio___pe17___lsb 17 | ||
| 547 | #define reg_pinmux_rw_pe_gio___pe17___width 1 | ||
| 548 | #define reg_pinmux_rw_pe_gio___pe17___bit 17 | ||
| 549 | #define reg_pinmux_rw_pe_gio_offset 32 | ||
| 550 | |||
| 551 | /* Register rw_pe_iop, scope pinmux, type rw */ | ||
| 552 | #define reg_pinmux_rw_pe_iop___pe0___lsb 0 | ||
| 553 | #define reg_pinmux_rw_pe_iop___pe0___width 1 | ||
| 554 | #define reg_pinmux_rw_pe_iop___pe0___bit 0 | ||
| 555 | #define reg_pinmux_rw_pe_iop___pe1___lsb 1 | ||
| 556 | #define reg_pinmux_rw_pe_iop___pe1___width 1 | ||
| 557 | #define reg_pinmux_rw_pe_iop___pe1___bit 1 | ||
| 558 | #define reg_pinmux_rw_pe_iop___pe2___lsb 2 | ||
| 559 | #define reg_pinmux_rw_pe_iop___pe2___width 1 | ||
| 560 | #define reg_pinmux_rw_pe_iop___pe2___bit 2 | ||
| 561 | #define reg_pinmux_rw_pe_iop___pe3___lsb 3 | ||
| 562 | #define reg_pinmux_rw_pe_iop___pe3___width 1 | ||
| 563 | #define reg_pinmux_rw_pe_iop___pe3___bit 3 | ||
| 564 | #define reg_pinmux_rw_pe_iop___pe4___lsb 4 | ||
| 565 | #define reg_pinmux_rw_pe_iop___pe4___width 1 | ||
| 566 | #define reg_pinmux_rw_pe_iop___pe4___bit 4 | ||
| 567 | #define reg_pinmux_rw_pe_iop___pe5___lsb 5 | ||
| 568 | #define reg_pinmux_rw_pe_iop___pe5___width 1 | ||
| 569 | #define reg_pinmux_rw_pe_iop___pe5___bit 5 | ||
| 570 | #define reg_pinmux_rw_pe_iop___pe6___lsb 6 | ||
| 571 | #define reg_pinmux_rw_pe_iop___pe6___width 1 | ||
| 572 | #define reg_pinmux_rw_pe_iop___pe6___bit 6 | ||
| 573 | #define reg_pinmux_rw_pe_iop___pe7___lsb 7 | ||
| 574 | #define reg_pinmux_rw_pe_iop___pe7___width 1 | ||
| 575 | #define reg_pinmux_rw_pe_iop___pe7___bit 7 | ||
| 576 | #define reg_pinmux_rw_pe_iop___pe8___lsb 8 | ||
| 577 | #define reg_pinmux_rw_pe_iop___pe8___width 1 | ||
| 578 | #define reg_pinmux_rw_pe_iop___pe8___bit 8 | ||
| 579 | #define reg_pinmux_rw_pe_iop___pe9___lsb 9 | ||
| 580 | #define reg_pinmux_rw_pe_iop___pe9___width 1 | ||
| 581 | #define reg_pinmux_rw_pe_iop___pe9___bit 9 | ||
| 582 | #define reg_pinmux_rw_pe_iop___pe10___lsb 10 | ||
| 583 | #define reg_pinmux_rw_pe_iop___pe10___width 1 | ||
| 584 | #define reg_pinmux_rw_pe_iop___pe10___bit 10 | ||
| 585 | #define reg_pinmux_rw_pe_iop___pe11___lsb 11 | ||
| 586 | #define reg_pinmux_rw_pe_iop___pe11___width 1 | ||
| 587 | #define reg_pinmux_rw_pe_iop___pe11___bit 11 | ||
| 588 | #define reg_pinmux_rw_pe_iop___pe12___lsb 12 | ||
| 589 | #define reg_pinmux_rw_pe_iop___pe12___width 1 | ||
| 590 | #define reg_pinmux_rw_pe_iop___pe12___bit 12 | ||
| 591 | #define reg_pinmux_rw_pe_iop___pe13___lsb 13 | ||
| 592 | #define reg_pinmux_rw_pe_iop___pe13___width 1 | ||
| 593 | #define reg_pinmux_rw_pe_iop___pe13___bit 13 | ||
| 594 | #define reg_pinmux_rw_pe_iop___pe14___lsb 14 | ||
| 595 | #define reg_pinmux_rw_pe_iop___pe14___width 1 | ||
| 596 | #define reg_pinmux_rw_pe_iop___pe14___bit 14 | ||
| 597 | #define reg_pinmux_rw_pe_iop___pe15___lsb 15 | ||
| 598 | #define reg_pinmux_rw_pe_iop___pe15___width 1 | ||
| 599 | #define reg_pinmux_rw_pe_iop___pe15___bit 15 | ||
| 600 | #define reg_pinmux_rw_pe_iop___pe16___lsb 16 | ||
| 601 | #define reg_pinmux_rw_pe_iop___pe16___width 1 | ||
| 602 | #define reg_pinmux_rw_pe_iop___pe16___bit 16 | ||
| 603 | #define reg_pinmux_rw_pe_iop___pe17___lsb 17 | ||
| 604 | #define reg_pinmux_rw_pe_iop___pe17___width 1 | ||
| 605 | #define reg_pinmux_rw_pe_iop___pe17___bit 17 | ||
| 606 | #define reg_pinmux_rw_pe_iop_offset 36 | ||
| 607 | |||
| 608 | /* Register rw_usb_phy, scope pinmux, type rw */ | ||
| 609 | #define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 | ||
| 610 | #define reg_pinmux_rw_usb_phy___en_usb0___width 1 | ||
| 611 | #define reg_pinmux_rw_usb_phy___en_usb0___bit 0 | ||
| 612 | #define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 | ||
| 613 | #define reg_pinmux_rw_usb_phy___en_usb1___width 1 | ||
| 614 | #define reg_pinmux_rw_usb_phy___en_usb1___bit 1 | ||
| 615 | #define reg_pinmux_rw_usb_phy_offset 40 | ||
| 616 | |||
| 617 | |||
| 618 | /* Constants */ | ||
| 619 | #define regk_pinmux_no 0x00000000 | ||
| 620 | #define regk_pinmux_rw_hwprot_default 0x00000000 | ||
| 621 | #define regk_pinmux_rw_pa_default 0x00000000 | ||
| 622 | #define regk_pinmux_rw_pb_gio_default 0x00000000 | ||
| 623 | #define regk_pinmux_rw_pb_iop_default 0x00000000 | ||
| 624 | #define regk_pinmux_rw_pc_gio_default 0x00000000 | ||
| 625 | #define regk_pinmux_rw_pc_iop_default 0x00000000 | ||
| 626 | #define regk_pinmux_rw_pd_gio_default 0x00000000 | ||
| 627 | #define regk_pinmux_rw_pd_iop_default 0x00000000 | ||
| 628 | #define regk_pinmux_rw_pe_gio_default 0x00000000 | ||
| 629 | #define regk_pinmux_rw_pe_iop_default 0x00000000 | ||
| 630 | #define regk_pinmux_rw_usb_phy_default 0x00000000 | ||
| 631 | #define regk_pinmux_yes 0x00000001 | ||
| 632 | #endif /* __pinmux_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h new file mode 100644 index 000000000000..87517aebd2cb --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/reg_map_asm.h | |||
| @@ -0,0 +1,96 @@ | |||
| 1 | #ifndef __reg_map_h | ||
| 2 | #define __reg_map_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../mod/fakereg.rmap | ||
| 7 | * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp | ||
| 8 | * last modified: Wed Feb 11 20:53:25 2004 | ||
| 9 | * file: ../../rtl/global.rmap | ||
| 10 | * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp | ||
| 11 | * last modified: Mon Aug 18 17:08:23 2003 | ||
| 12 | * file: ../../mod/modreg.rmap | ||
| 13 | * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp | ||
| 14 | * last modified: Fri Feb 20 16:40:04 2004 | ||
| 15 | * | ||
| 16 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap | ||
| 17 | * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 18 | * Any changes here will be lost. | ||
| 19 | * | ||
| 20 | * -*- buffer-read-only: t -*- | ||
| 21 | */ | ||
| 22 | #define regi_artpec_mod 0xb7044000 | ||
| 23 | #define regi_ata 0xb0032000 | ||
| 24 | #define regi_ata_mod 0xb7006000 | ||
| 25 | #define regi_barber 0xb701a000 | ||
| 26 | #define regi_bif_core 0xb0014000 | ||
| 27 | #define regi_bif_dma 0xb0016000 | ||
| 28 | #define regi_bif_slave 0xb0018000 | ||
| 29 | #define regi_bif_slave_ext 0xac000000 | ||
| 30 | #define regi_bus_master 0xb703c000 | ||
| 31 | #define regi_config 0xb003c000 | ||
| 32 | #define regi_dma0 0xb0000000 | ||
| 33 | #define regi_dma1 0xb0002000 | ||
| 34 | #define regi_dma2 0xb0004000 | ||
| 35 | #define regi_dma3 0xb0006000 | ||
| 36 | #define regi_dma4 0xb0008000 | ||
| 37 | #define regi_dma5 0xb000a000 | ||
| 38 | #define regi_dma6 0xb000c000 | ||
| 39 | #define regi_dma7 0xb000e000 | ||
| 40 | #define regi_dma8 0xb0010000 | ||
| 41 | #define regi_dma9 0xb0012000 | ||
| 42 | #define regi_eth0 0xb0034000 | ||
| 43 | #define regi_eth1 0xb0036000 | ||
| 44 | #define regi_eth_mod 0xb7004000 | ||
| 45 | #define regi_eth_mod1 0xb701c000 | ||
| 46 | #define regi_eth_strmod 0xb7008000 | ||
| 47 | #define regi_eth_strmod1 0xb7032000 | ||
| 48 | #define regi_ext_dma 0xb703a000 | ||
| 49 | #define regi_ext_mem 0xb7046000 | ||
| 50 | #define regi_gen_io 0xb7016000 | ||
| 51 | #define regi_gio 0xb001a000 | ||
| 52 | #define regi_hook 0xb7000000 | ||
| 53 | #define regi_iop 0xb0020000 | ||
| 54 | #define regi_irq 0xb001c000 | ||
| 55 | #define regi_irq_nmi 0xb701e000 | ||
| 56 | #define regi_marb 0xb003e000 | ||
| 57 | #define regi_marb_bp0 0xb003e240 | ||
| 58 | #define regi_marb_bp1 0xb003e280 | ||
| 59 | #define regi_marb_bp2 0xb003e2c0 | ||
| 60 | #define regi_marb_bp3 0xb003e300 | ||
| 61 | #define regi_nand_mod 0xb7014000 | ||
| 62 | #define regi_p21 0xb002e000 | ||
| 63 | #define regi_p21_mod 0xb7042000 | ||
| 64 | #define regi_pci_mod 0xb7010000 | ||
| 65 | #define regi_pin_test 0xb7018000 | ||
| 66 | #define regi_pinmux 0xb0038000 | ||
| 67 | #define regi_sdram_chk 0xb703e000 | ||
| 68 | #define regi_sdram_mod 0xb7012000 | ||
| 69 | #define regi_ser0 0xb0026000 | ||
| 70 | #define regi_ser1 0xb0028000 | ||
| 71 | #define regi_ser2 0xb002a000 | ||
| 72 | #define regi_ser3 0xb002c000 | ||
| 73 | #define regi_ser_mod0 0xb7020000 | ||
| 74 | #define regi_ser_mod1 0xb7022000 | ||
| 75 | #define regi_ser_mod2 0xb7024000 | ||
| 76 | #define regi_ser_mod3 0xb7026000 | ||
| 77 | #define regi_smif_stat 0xb700e000 | ||
| 78 | #define regi_sser0 0xb0022000 | ||
| 79 | #define regi_sser1 0xb0024000 | ||
| 80 | #define regi_sser_mod0 0xb700a000 | ||
| 81 | #define regi_sser_mod1 0xb700c000 | ||
| 82 | #define regi_strcop 0xb0030000 | ||
| 83 | #define regi_strmux 0xb003a000 | ||
| 84 | #define regi_strmux_tst 0xb7040000 | ||
| 85 | #define regi_tap 0xb7002000 | ||
| 86 | #define regi_timer 0xb001e000 | ||
| 87 | #define regi_timer_mod 0xb7034000 | ||
| 88 | #define regi_trace 0xb0040000 | ||
| 89 | #define regi_usb0 0xb7028000 | ||
| 90 | #define regi_usb1 0xb702a000 | ||
| 91 | #define regi_usb2 0xb702c000 | ||
| 92 | #define regi_usb3 0xb702e000 | ||
| 93 | #define regi_usb_dev 0xb7030000 | ||
| 94 | #define regi_utmi_mod0 0xb7036000 | ||
| 95 | #define regi_utmi_mod1 0xb7038000 | ||
| 96 | #endif /* __reg_map_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h new file mode 100644 index 000000000000..e1197194d5c1 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/asm/timer_defs_asm.h | |||
| @@ -0,0 +1,229 @@ | |||
| 1 | #ifndef __timer_defs_asm_h | ||
| 2 | #define __timer_defs_asm_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/timer/rtl/timer_regs.r | ||
| 7 | * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:53 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r | ||
| 11 | * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef REG_FIELD | ||
| 18 | #define REG_FIELD( scope, reg, field, value ) \ | ||
| 19 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 20 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_STATE | ||
| 24 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | ||
| 25 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | ||
| 26 | #define REG_STATE_X_( k, shift ) (k << shift) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_MASK | ||
| 30 | #define REG_MASK( scope, reg, field ) \ | ||
| 31 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | ||
| 32 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifndef REG_LSB | ||
| 36 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifndef REG_BIT | ||
| 40 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_ADDR | ||
| 44 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | ||
| 45 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_ADDR_VECT | ||
| 49 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 50 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | ||
| 51 | STRIDE_##scope##_##reg ) | ||
| 52 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | ||
| 53 | ((inst) + offs + (index) * stride) | ||
| 54 | #endif | ||
| 55 | |||
| 56 | /* Register rw_tmr0_div, scope timer, type rw */ | ||
| 57 | #define reg_timer_rw_tmr0_div_offset 0 | ||
| 58 | |||
| 59 | /* Register r_tmr0_data, scope timer, type r */ | ||
| 60 | #define reg_timer_r_tmr0_data_offset 4 | ||
| 61 | |||
| 62 | /* Register rw_tmr0_ctrl, scope timer, type rw */ | ||
| 63 | #define reg_timer_rw_tmr0_ctrl___op___lsb 0 | ||
| 64 | #define reg_timer_rw_tmr0_ctrl___op___width 2 | ||
| 65 | #define reg_timer_rw_tmr0_ctrl___freq___lsb 2 | ||
| 66 | #define reg_timer_rw_tmr0_ctrl___freq___width 3 | ||
| 67 | #define reg_timer_rw_tmr0_ctrl_offset 8 | ||
| 68 | |||
| 69 | /* Register rw_tmr1_div, scope timer, type rw */ | ||
| 70 | #define reg_timer_rw_tmr1_div_offset 16 | ||
| 71 | |||
| 72 | /* Register r_tmr1_data, scope timer, type r */ | ||
| 73 | #define reg_timer_r_tmr1_data_offset 20 | ||
| 74 | |||
| 75 | /* Register rw_tmr1_ctrl, scope timer, type rw */ | ||
| 76 | #define reg_timer_rw_tmr1_ctrl___op___lsb 0 | ||
| 77 | #define reg_timer_rw_tmr1_ctrl___op___width 2 | ||
| 78 | #define reg_timer_rw_tmr1_ctrl___freq___lsb 2 | ||
| 79 | #define reg_timer_rw_tmr1_ctrl___freq___width 3 | ||
| 80 | #define reg_timer_rw_tmr1_ctrl_offset 24 | ||
| 81 | |||
| 82 | /* Register rs_cnt_data, scope timer, type rs */ | ||
| 83 | #define reg_timer_rs_cnt_data___tmr___lsb 0 | ||
| 84 | #define reg_timer_rs_cnt_data___tmr___width 24 | ||
| 85 | #define reg_timer_rs_cnt_data___cnt___lsb 24 | ||
| 86 | #define reg_timer_rs_cnt_data___cnt___width 8 | ||
| 87 | #define reg_timer_rs_cnt_data_offset 32 | ||
| 88 | |||
| 89 | /* Register r_cnt_data, scope timer, type r */ | ||
| 90 | #define reg_timer_r_cnt_data___tmr___lsb 0 | ||
| 91 | #define reg_timer_r_cnt_data___tmr___width 24 | ||
| 92 | #define reg_timer_r_cnt_data___cnt___lsb 24 | ||
| 93 | #define reg_timer_r_cnt_data___cnt___width 8 | ||
| 94 | #define reg_timer_r_cnt_data_offset 36 | ||
| 95 | |||
| 96 | /* Register rw_cnt_cfg, scope timer, type rw */ | ||
| 97 | #define reg_timer_rw_cnt_cfg___clk___lsb 0 | ||
| 98 | #define reg_timer_rw_cnt_cfg___clk___width 2 | ||
| 99 | #define reg_timer_rw_cnt_cfg_offset 40 | ||
| 100 | |||
| 101 | /* Register rw_trig, scope timer, type rw */ | ||
| 102 | #define reg_timer_rw_trig_offset 48 | ||
| 103 | |||
| 104 | /* Register rw_trig_cfg, scope timer, type rw */ | ||
| 105 | #define reg_timer_rw_trig_cfg___tmr___lsb 0 | ||
| 106 | #define reg_timer_rw_trig_cfg___tmr___width 2 | ||
| 107 | #define reg_timer_rw_trig_cfg_offset 52 | ||
| 108 | |||
| 109 | /* Register r_time, scope timer, type r */ | ||
| 110 | #define reg_timer_r_time_offset 56 | ||
| 111 | |||
| 112 | /* Register rw_out, scope timer, type rw */ | ||
| 113 | #define reg_timer_rw_out___tmr___lsb 0 | ||
| 114 | #define reg_timer_rw_out___tmr___width 2 | ||
| 115 | #define reg_timer_rw_out_offset 60 | ||
| 116 | |||
| 117 | /* Register rw_wd_ctrl, scope timer, type rw */ | ||
| 118 | #define reg_timer_rw_wd_ctrl___cnt___lsb 0 | ||
| 119 | #define reg_timer_rw_wd_ctrl___cnt___width 8 | ||
| 120 | #define reg_timer_rw_wd_ctrl___cmd___lsb 8 | ||
| 121 | #define reg_timer_rw_wd_ctrl___cmd___width 1 | ||
| 122 | #define reg_timer_rw_wd_ctrl___cmd___bit 8 | ||
| 123 | #define reg_timer_rw_wd_ctrl___key___lsb 9 | ||
| 124 | #define reg_timer_rw_wd_ctrl___key___width 7 | ||
| 125 | #define reg_timer_rw_wd_ctrl_offset 64 | ||
| 126 | |||
| 127 | /* Register r_wd_stat, scope timer, type r */ | ||
| 128 | #define reg_timer_r_wd_stat___cnt___lsb 0 | ||
| 129 | #define reg_timer_r_wd_stat___cnt___width 8 | ||
| 130 | #define reg_timer_r_wd_stat___cmd___lsb 8 | ||
| 131 | #define reg_timer_r_wd_stat___cmd___width 1 | ||
| 132 | #define reg_timer_r_wd_stat___cmd___bit 8 | ||
| 133 | #define reg_timer_r_wd_stat_offset 68 | ||
| 134 | |||
| 135 | /* Register rw_intr_mask, scope timer, type rw */ | ||
| 136 | #define reg_timer_rw_intr_mask___tmr0___lsb 0 | ||
| 137 | #define reg_timer_rw_intr_mask___tmr0___width 1 | ||
| 138 | #define reg_timer_rw_intr_mask___tmr0___bit 0 | ||
| 139 | #define reg_timer_rw_intr_mask___tmr1___lsb 1 | ||
| 140 | #define reg_timer_rw_intr_mask___tmr1___width 1 | ||
| 141 | #define reg_timer_rw_intr_mask___tmr1___bit 1 | ||
| 142 | #define reg_timer_rw_intr_mask___cnt___lsb 2 | ||
| 143 | #define reg_timer_rw_intr_mask___cnt___width 1 | ||
| 144 | #define reg_timer_rw_intr_mask___cnt___bit 2 | ||
| 145 | #define reg_timer_rw_intr_mask___trig___lsb 3 | ||
| 146 | #define reg_timer_rw_intr_mask___trig___width 1 | ||
| 147 | #define reg_timer_rw_intr_mask___trig___bit 3 | ||
| 148 | #define reg_timer_rw_intr_mask_offset 72 | ||
| 149 | |||
| 150 | /* Register rw_ack_intr, scope timer, type rw */ | ||
| 151 | #define reg_timer_rw_ack_intr___tmr0___lsb 0 | ||
| 152 | #define reg_timer_rw_ack_intr___tmr0___width 1 | ||
| 153 | #define reg_timer_rw_ack_intr___tmr0___bit 0 | ||
| 154 | #define reg_timer_rw_ack_intr___tmr1___lsb 1 | ||
| 155 | #define reg_timer_rw_ack_intr___tmr1___width 1 | ||
| 156 | #define reg_timer_rw_ack_intr___tmr1___bit 1 | ||
| 157 | #define reg_timer_rw_ack_intr___cnt___lsb 2 | ||
| 158 | #define reg_timer_rw_ack_intr___cnt___width 1 | ||
| 159 | #define reg_timer_rw_ack_intr___cnt___bit 2 | ||
| 160 | #define reg_timer_rw_ack_intr___trig___lsb 3 | ||
| 161 | #define reg_timer_rw_ack_intr___trig___width 1 | ||
| 162 | #define reg_timer_rw_ack_intr___trig___bit 3 | ||
| 163 | #define reg_timer_rw_ack_intr_offset 76 | ||
| 164 | |||
| 165 | /* Register r_intr, scope timer, type r */ | ||
| 166 | #define reg_timer_r_intr___tmr0___lsb 0 | ||
| 167 | #define reg_timer_r_intr___tmr0___width 1 | ||
| 168 | #define reg_timer_r_intr___tmr0___bit 0 | ||
| 169 | #define reg_timer_r_intr___tmr1___lsb 1 | ||
| 170 | #define reg_timer_r_intr___tmr1___width 1 | ||
| 171 | #define reg_timer_r_intr___tmr1___bit 1 | ||
| 172 | #define reg_timer_r_intr___cnt___lsb 2 | ||
| 173 | #define reg_timer_r_intr___cnt___width 1 | ||
| 174 | #define reg_timer_r_intr___cnt___bit 2 | ||
| 175 | #define reg_timer_r_intr___trig___lsb 3 | ||
| 176 | #define reg_timer_r_intr___trig___width 1 | ||
| 177 | #define reg_timer_r_intr___trig___bit 3 | ||
| 178 | #define reg_timer_r_intr_offset 80 | ||
| 179 | |||
| 180 | /* Register r_masked_intr, scope timer, type r */ | ||
| 181 | #define reg_timer_r_masked_intr___tmr0___lsb 0 | ||
| 182 | #define reg_timer_r_masked_intr___tmr0___width 1 | ||
| 183 | #define reg_timer_r_masked_intr___tmr0___bit 0 | ||
| 184 | #define reg_timer_r_masked_intr___tmr1___lsb 1 | ||
| 185 | #define reg_timer_r_masked_intr___tmr1___width 1 | ||
| 186 | #define reg_timer_r_masked_intr___tmr1___bit 1 | ||
| 187 | #define reg_timer_r_masked_intr___cnt___lsb 2 | ||
| 188 | #define reg_timer_r_masked_intr___cnt___width 1 | ||
| 189 | #define reg_timer_r_masked_intr___cnt___bit 2 | ||
| 190 | #define reg_timer_r_masked_intr___trig___lsb 3 | ||
| 191 | #define reg_timer_r_masked_intr___trig___width 1 | ||
| 192 | #define reg_timer_r_masked_intr___trig___bit 3 | ||
| 193 | #define reg_timer_r_masked_intr_offset 84 | ||
| 194 | |||
| 195 | /* Register rw_test, scope timer, type rw */ | ||
| 196 | #define reg_timer_rw_test___dis___lsb 0 | ||
| 197 | #define reg_timer_rw_test___dis___width 1 | ||
| 198 | #define reg_timer_rw_test___dis___bit 0 | ||
| 199 | #define reg_timer_rw_test___en___lsb 1 | ||
| 200 | #define reg_timer_rw_test___en___width 1 | ||
| 201 | #define reg_timer_rw_test___en___bit 1 | ||
| 202 | #define reg_timer_rw_test_offset 88 | ||
| 203 | |||
| 204 | |||
| 205 | /* Constants */ | ||
| 206 | #define regk_timer_ext 0x00000001 | ||
| 207 | #define regk_timer_f100 0x00000007 | ||
| 208 | #define regk_timer_f29_493 0x00000004 | ||
| 209 | #define regk_timer_f32 0x00000005 | ||
| 210 | #define regk_timer_f32_768 0x00000006 | ||
| 211 | #define regk_timer_hold 0x00000001 | ||
| 212 | #define regk_timer_ld 0x00000000 | ||
| 213 | #define regk_timer_no 0x00000000 | ||
| 214 | #define regk_timer_off 0x00000000 | ||
| 215 | #define regk_timer_run 0x00000002 | ||
| 216 | #define regk_timer_rw_cnt_cfg_default 0x00000000 | ||
| 217 | #define regk_timer_rw_intr_mask_default 0x00000000 | ||
| 218 | #define regk_timer_rw_out_default 0x00000000 | ||
| 219 | #define regk_timer_rw_test_default 0x00000000 | ||
| 220 | #define regk_timer_rw_tmr0_ctrl_default 0x00000000 | ||
| 221 | #define regk_timer_rw_tmr1_ctrl_default 0x00000000 | ||
| 222 | #define regk_timer_rw_trig_cfg_default 0x00000000 | ||
| 223 | #define regk_timer_start 0x00000001 | ||
| 224 | #define regk_timer_stop 0x00000000 | ||
| 225 | #define regk_timer_time 0x00000001 | ||
| 226 | #define regk_timer_tmr0 0x00000002 | ||
| 227 | #define regk_timer_tmr1 0x00000003 | ||
| 228 | #define regk_timer_yes 0x00000001 | ||
| 229 | #endif /* __timer_defs_asm_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h new file mode 100644 index 000000000000..44362a62b47c --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_core_defs.h | |||
| @@ -0,0 +1,284 @@ | |||
| 1 | #ifndef __bif_core_defs_h | ||
| 2 | #define __bif_core_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_core_regs.r | ||
| 7 | * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:33 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r | ||
| 11 | * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope bif_core */ | ||
| 86 | |||
| 87 | /* Register rw_grp1_cfg, scope bif_core, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int lw : 6; | ||
| 90 | unsigned int ew : 3; | ||
| 91 | unsigned int zw : 3; | ||
| 92 | unsigned int aw : 2; | ||
| 93 | unsigned int dw : 2; | ||
| 94 | unsigned int ewb : 2; | ||
| 95 | unsigned int bw : 1; | ||
| 96 | unsigned int wr_extend : 1; | ||
| 97 | unsigned int erc_en : 1; | ||
| 98 | unsigned int mode : 1; | ||
| 99 | unsigned int dummy1 : 10; | ||
| 100 | } reg_bif_core_rw_grp1_cfg; | ||
| 101 | #define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 | ||
| 102 | #define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 | ||
| 103 | |||
| 104 | /* Register rw_grp2_cfg, scope bif_core, type rw */ | ||
| 105 | typedef struct { | ||
| 106 | unsigned int lw : 6; | ||
| 107 | unsigned int ew : 3; | ||
| 108 | unsigned int zw : 3; | ||
| 109 | unsigned int aw : 2; | ||
| 110 | unsigned int dw : 2; | ||
| 111 | unsigned int ewb : 2; | ||
| 112 | unsigned int bw : 1; | ||
| 113 | unsigned int wr_extend : 1; | ||
| 114 | unsigned int erc_en : 1; | ||
| 115 | unsigned int mode : 1; | ||
| 116 | unsigned int dummy1 : 10; | ||
| 117 | } reg_bif_core_rw_grp2_cfg; | ||
| 118 | #define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 | ||
| 119 | #define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 | ||
| 120 | |||
| 121 | /* Register rw_grp3_cfg, scope bif_core, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int lw : 6; | ||
| 124 | unsigned int ew : 3; | ||
| 125 | unsigned int zw : 3; | ||
| 126 | unsigned int aw : 2; | ||
| 127 | unsigned int dw : 2; | ||
| 128 | unsigned int ewb : 2; | ||
| 129 | unsigned int bw : 1; | ||
| 130 | unsigned int wr_extend : 1; | ||
| 131 | unsigned int erc_en : 1; | ||
| 132 | unsigned int mode : 1; | ||
| 133 | unsigned int dummy1 : 2; | ||
| 134 | unsigned int gated_csp0 : 2; | ||
| 135 | unsigned int gated_csp1 : 2; | ||
| 136 | unsigned int gated_csp2 : 2; | ||
| 137 | unsigned int gated_csp3 : 2; | ||
| 138 | } reg_bif_core_rw_grp3_cfg; | ||
| 139 | #define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 | ||
| 140 | #define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 | ||
| 141 | |||
| 142 | /* Register rw_grp4_cfg, scope bif_core, type rw */ | ||
| 143 | typedef struct { | ||
| 144 | unsigned int lw : 6; | ||
| 145 | unsigned int ew : 3; | ||
| 146 | unsigned int zw : 3; | ||
| 147 | unsigned int aw : 2; | ||
| 148 | unsigned int dw : 2; | ||
| 149 | unsigned int ewb : 2; | ||
| 150 | unsigned int bw : 1; | ||
| 151 | unsigned int wr_extend : 1; | ||
| 152 | unsigned int erc_en : 1; | ||
| 153 | unsigned int mode : 1; | ||
| 154 | unsigned int dummy1 : 4; | ||
| 155 | unsigned int gated_csp4 : 2; | ||
| 156 | unsigned int gated_csp5 : 2; | ||
| 157 | unsigned int gated_csp6 : 2; | ||
| 158 | } reg_bif_core_rw_grp4_cfg; | ||
| 159 | #define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 | ||
| 160 | #define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 | ||
| 161 | |||
| 162 | /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int bank_sel : 5; | ||
| 165 | unsigned int ca : 3; | ||
| 166 | unsigned int type : 1; | ||
| 167 | unsigned int bw : 1; | ||
| 168 | unsigned int sh : 3; | ||
| 169 | unsigned int wmm : 1; | ||
| 170 | unsigned int sh16 : 1; | ||
| 171 | unsigned int grp_sel : 5; | ||
| 172 | unsigned int dummy1 : 12; | ||
| 173 | } reg_bif_core_rw_sdram_cfg_grp0; | ||
| 174 | #define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 | ||
| 175 | #define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 | ||
| 176 | |||
| 177 | /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int bank_sel : 5; | ||
| 180 | unsigned int ca : 3; | ||
| 181 | unsigned int type : 1; | ||
| 182 | unsigned int bw : 1; | ||
| 183 | unsigned int sh : 3; | ||
| 184 | unsigned int wmm : 1; | ||
| 185 | unsigned int sh16 : 1; | ||
| 186 | unsigned int dummy1 : 17; | ||
| 187 | } reg_bif_core_rw_sdram_cfg_grp1; | ||
| 188 | #define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 | ||
| 189 | #define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 | ||
| 190 | |||
| 191 | /* Register rw_sdram_timing, scope bif_core, type rw */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int cl : 3; | ||
| 194 | unsigned int rcd : 3; | ||
| 195 | unsigned int rp : 3; | ||
| 196 | unsigned int rc : 2; | ||
| 197 | unsigned int dpl : 2; | ||
| 198 | unsigned int pde : 1; | ||
| 199 | unsigned int ref : 2; | ||
| 200 | unsigned int cpd : 1; | ||
| 201 | unsigned int sdcke : 1; | ||
| 202 | unsigned int sdclk : 1; | ||
| 203 | unsigned int dummy1 : 13; | ||
| 204 | } reg_bif_core_rw_sdram_timing; | ||
| 205 | #define REG_RD_ADDR_bif_core_rw_sdram_timing 24 | ||
| 206 | #define REG_WR_ADDR_bif_core_rw_sdram_timing 24 | ||
| 207 | |||
| 208 | /* Register rw_sdram_cmd, scope bif_core, type rw */ | ||
| 209 | typedef struct { | ||
| 210 | unsigned int cmd : 3; | ||
| 211 | unsigned int mrs_data : 15; | ||
| 212 | unsigned int dummy1 : 14; | ||
| 213 | } reg_bif_core_rw_sdram_cmd; | ||
| 214 | #define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 | ||
| 215 | #define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 | ||
| 216 | |||
| 217 | /* Register rs_sdram_ref_stat, scope bif_core, type rs */ | ||
| 218 | typedef struct { | ||
| 219 | unsigned int ok : 1; | ||
| 220 | unsigned int dummy1 : 31; | ||
| 221 | } reg_bif_core_rs_sdram_ref_stat; | ||
| 222 | #define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 | ||
| 223 | |||
| 224 | /* Register r_sdram_ref_stat, scope bif_core, type r */ | ||
| 225 | typedef struct { | ||
| 226 | unsigned int ok : 1; | ||
| 227 | unsigned int dummy1 : 31; | ||
| 228 | } reg_bif_core_r_sdram_ref_stat; | ||
| 229 | #define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 | ||
| 230 | |||
| 231 | |||
| 232 | /* Constants */ | ||
| 233 | enum { | ||
| 234 | regk_bif_core_bank2 = 0x00000000, | ||
| 235 | regk_bif_core_bank4 = 0x00000001, | ||
| 236 | regk_bif_core_bit10 = 0x0000000a, | ||
| 237 | regk_bif_core_bit11 = 0x0000000b, | ||
| 238 | regk_bif_core_bit12 = 0x0000000c, | ||
| 239 | regk_bif_core_bit13 = 0x0000000d, | ||
| 240 | regk_bif_core_bit14 = 0x0000000e, | ||
| 241 | regk_bif_core_bit15 = 0x0000000f, | ||
| 242 | regk_bif_core_bit16 = 0x00000010, | ||
| 243 | regk_bif_core_bit17 = 0x00000011, | ||
| 244 | regk_bif_core_bit18 = 0x00000012, | ||
| 245 | regk_bif_core_bit19 = 0x00000013, | ||
| 246 | regk_bif_core_bit20 = 0x00000014, | ||
| 247 | regk_bif_core_bit21 = 0x00000015, | ||
| 248 | regk_bif_core_bit22 = 0x00000016, | ||
| 249 | regk_bif_core_bit23 = 0x00000017, | ||
| 250 | regk_bif_core_bit24 = 0x00000018, | ||
| 251 | regk_bif_core_bit25 = 0x00000019, | ||
| 252 | regk_bif_core_bit26 = 0x0000001a, | ||
| 253 | regk_bif_core_bit27 = 0x0000001b, | ||
| 254 | regk_bif_core_bit28 = 0x0000001c, | ||
| 255 | regk_bif_core_bit29 = 0x0000001d, | ||
| 256 | regk_bif_core_bit9 = 0x00000009, | ||
| 257 | regk_bif_core_bw16 = 0x00000001, | ||
| 258 | regk_bif_core_bw32 = 0x00000000, | ||
| 259 | regk_bif_core_bwe = 0x00000000, | ||
| 260 | regk_bif_core_cwe = 0x00000001, | ||
| 261 | regk_bif_core_e15us = 0x00000001, | ||
| 262 | regk_bif_core_e7800ns = 0x00000002, | ||
| 263 | regk_bif_core_grp0 = 0x00000000, | ||
| 264 | regk_bif_core_grp1 = 0x00000001, | ||
| 265 | regk_bif_core_mrs = 0x00000003, | ||
| 266 | regk_bif_core_no = 0x00000000, | ||
| 267 | regk_bif_core_none = 0x00000000, | ||
| 268 | regk_bif_core_nop = 0x00000000, | ||
| 269 | regk_bif_core_off = 0x00000000, | ||
| 270 | regk_bif_core_pre = 0x00000002, | ||
| 271 | regk_bif_core_r_sdram_ref_stat_default = 0x00000001, | ||
| 272 | regk_bif_core_rd = 0x00000002, | ||
| 273 | regk_bif_core_ref = 0x00000001, | ||
| 274 | regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, | ||
| 275 | regk_bif_core_rw_grp1_cfg_default = 0x000006cf, | ||
| 276 | regk_bif_core_rw_grp2_cfg_default = 0x000006cf, | ||
| 277 | regk_bif_core_rw_grp3_cfg_default = 0x000006cf, | ||
| 278 | regk_bif_core_rw_grp4_cfg_default = 0x000006cf, | ||
| 279 | regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, | ||
| 280 | regk_bif_core_slf = 0x00000004, | ||
| 281 | regk_bif_core_wr = 0x00000001, | ||
| 282 | regk_bif_core_yes = 0x00000001 | ||
| 283 | }; | ||
| 284 | #endif /* __bif_core_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h new file mode 100644 index 000000000000..3cb51a09dba7 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_dma_defs.h | |||
| @@ -0,0 +1,473 @@ | |||
| 1 | #ifndef __bif_dma_defs_h | ||
| 2 | #define __bif_dma_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_dma_regs.r | ||
| 7 | * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:33 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r | ||
| 11 | * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope bif_dma */ | ||
| 86 | |||
| 87 | /* Register rw_ch0_ctrl, scope bif_dma, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int bw : 2; | ||
| 90 | unsigned int burst_len : 1; | ||
| 91 | unsigned int cont : 1; | ||
| 92 | unsigned int end_pad : 1; | ||
| 93 | unsigned int cnt : 1; | ||
| 94 | unsigned int dreq_pin : 3; | ||
| 95 | unsigned int dreq_mode : 2; | ||
| 96 | unsigned int tc_in_pin : 3; | ||
| 97 | unsigned int tc_in_mode : 2; | ||
| 98 | unsigned int bus_mode : 2; | ||
| 99 | unsigned int rate_en : 1; | ||
| 100 | unsigned int wr_all : 1; | ||
| 101 | unsigned int dummy1 : 12; | ||
| 102 | } reg_bif_dma_rw_ch0_ctrl; | ||
| 103 | #define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 | ||
| 104 | #define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 | ||
| 105 | |||
| 106 | /* Register rw_ch0_addr, scope bif_dma, type rw */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int addr : 32; | ||
| 109 | } reg_bif_dma_rw_ch0_addr; | ||
| 110 | #define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 | ||
| 111 | #define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 | ||
| 112 | |||
| 113 | /* Register rw_ch0_start, scope bif_dma, type rw */ | ||
| 114 | typedef struct { | ||
| 115 | unsigned int run : 1; | ||
| 116 | unsigned int dummy1 : 31; | ||
| 117 | } reg_bif_dma_rw_ch0_start; | ||
| 118 | #define REG_RD_ADDR_bif_dma_rw_ch0_start 8 | ||
| 119 | #define REG_WR_ADDR_bif_dma_rw_ch0_start 8 | ||
| 120 | |||
| 121 | /* Register rw_ch0_cnt, scope bif_dma, type rw */ | ||
| 122 | typedef struct { | ||
| 123 | unsigned int start_cnt : 16; | ||
| 124 | unsigned int dummy1 : 16; | ||
| 125 | } reg_bif_dma_rw_ch0_cnt; | ||
| 126 | #define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 | ||
| 127 | #define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 | ||
| 128 | |||
| 129 | /* Register r_ch0_stat, scope bif_dma, type r */ | ||
| 130 | typedef struct { | ||
| 131 | unsigned int cnt : 16; | ||
| 132 | unsigned int dummy1 : 15; | ||
| 133 | unsigned int run : 1; | ||
| 134 | } reg_bif_dma_r_ch0_stat; | ||
| 135 | #define REG_RD_ADDR_bif_dma_r_ch0_stat 16 | ||
| 136 | |||
| 137 | /* Register rw_ch1_ctrl, scope bif_dma, type rw */ | ||
| 138 | typedef struct { | ||
| 139 | unsigned int bw : 2; | ||
| 140 | unsigned int burst_len : 1; | ||
| 141 | unsigned int cont : 1; | ||
| 142 | unsigned int end_discard : 1; | ||
| 143 | unsigned int cnt : 1; | ||
| 144 | unsigned int dreq_pin : 3; | ||
| 145 | unsigned int dreq_mode : 2; | ||
| 146 | unsigned int tc_in_pin : 3; | ||
| 147 | unsigned int tc_in_mode : 2; | ||
| 148 | unsigned int bus_mode : 2; | ||
| 149 | unsigned int rate_en : 1; | ||
| 150 | unsigned int dummy1 : 13; | ||
| 151 | } reg_bif_dma_rw_ch1_ctrl; | ||
| 152 | #define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 | ||
| 153 | #define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 | ||
| 154 | |||
| 155 | /* Register rw_ch1_addr, scope bif_dma, type rw */ | ||
| 156 | typedef struct { | ||
| 157 | unsigned int addr : 32; | ||
| 158 | } reg_bif_dma_rw_ch1_addr; | ||
| 159 | #define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 | ||
| 160 | #define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 | ||
| 161 | |||
| 162 | /* Register rw_ch1_start, scope bif_dma, type rw */ | ||
| 163 | typedef struct { | ||
| 164 | unsigned int run : 1; | ||
| 165 | unsigned int dummy1 : 31; | ||
| 166 | } reg_bif_dma_rw_ch1_start; | ||
| 167 | #define REG_RD_ADDR_bif_dma_rw_ch1_start 40 | ||
| 168 | #define REG_WR_ADDR_bif_dma_rw_ch1_start 40 | ||
| 169 | |||
| 170 | /* Register rw_ch1_cnt, scope bif_dma, type rw */ | ||
| 171 | typedef struct { | ||
| 172 | unsigned int start_cnt : 16; | ||
| 173 | unsigned int dummy1 : 16; | ||
| 174 | } reg_bif_dma_rw_ch1_cnt; | ||
| 175 | #define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 | ||
| 176 | #define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 | ||
| 177 | |||
| 178 | /* Register r_ch1_stat, scope bif_dma, type r */ | ||
| 179 | typedef struct { | ||
| 180 | unsigned int cnt : 16; | ||
| 181 | unsigned int dummy1 : 15; | ||
| 182 | unsigned int run : 1; | ||
| 183 | } reg_bif_dma_r_ch1_stat; | ||
| 184 | #define REG_RD_ADDR_bif_dma_r_ch1_stat 48 | ||
| 185 | |||
| 186 | /* Register rw_ch2_ctrl, scope bif_dma, type rw */ | ||
| 187 | typedef struct { | ||
| 188 | unsigned int bw : 2; | ||
| 189 | unsigned int burst_len : 1; | ||
| 190 | unsigned int cont : 1; | ||
| 191 | unsigned int end_pad : 1; | ||
| 192 | unsigned int cnt : 1; | ||
| 193 | unsigned int dreq_pin : 3; | ||
| 194 | unsigned int dreq_mode : 2; | ||
| 195 | unsigned int tc_in_pin : 3; | ||
| 196 | unsigned int tc_in_mode : 2; | ||
| 197 | unsigned int bus_mode : 2; | ||
| 198 | unsigned int rate_en : 1; | ||
| 199 | unsigned int wr_all : 1; | ||
| 200 | unsigned int dummy1 : 12; | ||
| 201 | } reg_bif_dma_rw_ch2_ctrl; | ||
| 202 | #define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 | ||
| 203 | #define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 | ||
| 204 | |||
| 205 | /* Register rw_ch2_addr, scope bif_dma, type rw */ | ||
| 206 | typedef struct { | ||
| 207 | unsigned int addr : 32; | ||
| 208 | } reg_bif_dma_rw_ch2_addr; | ||
| 209 | #define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 | ||
| 210 | #define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 | ||
| 211 | |||
| 212 | /* Register rw_ch2_start, scope bif_dma, type rw */ | ||
| 213 | typedef struct { | ||
| 214 | unsigned int run : 1; | ||
| 215 | unsigned int dummy1 : 31; | ||
| 216 | } reg_bif_dma_rw_ch2_start; | ||
| 217 | #define REG_RD_ADDR_bif_dma_rw_ch2_start 72 | ||
| 218 | #define REG_WR_ADDR_bif_dma_rw_ch2_start 72 | ||
| 219 | |||
| 220 | /* Register rw_ch2_cnt, scope bif_dma, type rw */ | ||
| 221 | typedef struct { | ||
| 222 | unsigned int start_cnt : 16; | ||
| 223 | unsigned int dummy1 : 16; | ||
| 224 | } reg_bif_dma_rw_ch2_cnt; | ||
| 225 | #define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 | ||
| 226 | #define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 | ||
| 227 | |||
| 228 | /* Register r_ch2_stat, scope bif_dma, type r */ | ||
| 229 | typedef struct { | ||
| 230 | unsigned int cnt : 16; | ||
| 231 | unsigned int dummy1 : 15; | ||
| 232 | unsigned int run : 1; | ||
| 233 | } reg_bif_dma_r_ch2_stat; | ||
| 234 | #define REG_RD_ADDR_bif_dma_r_ch2_stat 80 | ||
| 235 | |||
| 236 | /* Register rw_ch3_ctrl, scope bif_dma, type rw */ | ||
| 237 | typedef struct { | ||
| 238 | unsigned int bw : 2; | ||
| 239 | unsigned int burst_len : 1; | ||
| 240 | unsigned int cont : 1; | ||
| 241 | unsigned int end_discard : 1; | ||
| 242 | unsigned int cnt : 1; | ||
| 243 | unsigned int dreq_pin : 3; | ||
| 244 | unsigned int dreq_mode : 2; | ||
| 245 | unsigned int tc_in_pin : 3; | ||
| 246 | unsigned int tc_in_mode : 2; | ||
| 247 | unsigned int bus_mode : 2; | ||
| 248 | unsigned int rate_en : 1; | ||
| 249 | unsigned int dummy1 : 13; | ||
| 250 | } reg_bif_dma_rw_ch3_ctrl; | ||
| 251 | #define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 | ||
| 252 | #define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 | ||
| 253 | |||
| 254 | /* Register rw_ch3_addr, scope bif_dma, type rw */ | ||
| 255 | typedef struct { | ||
| 256 | unsigned int addr : 32; | ||
| 257 | } reg_bif_dma_rw_ch3_addr; | ||
| 258 | #define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 | ||
| 259 | #define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 | ||
| 260 | |||
| 261 | /* Register rw_ch3_start, scope bif_dma, type rw */ | ||
| 262 | typedef struct { | ||
| 263 | unsigned int run : 1; | ||
| 264 | unsigned int dummy1 : 31; | ||
| 265 | } reg_bif_dma_rw_ch3_start; | ||
| 266 | #define REG_RD_ADDR_bif_dma_rw_ch3_start 104 | ||
| 267 | #define REG_WR_ADDR_bif_dma_rw_ch3_start 104 | ||
| 268 | |||
| 269 | /* Register rw_ch3_cnt, scope bif_dma, type rw */ | ||
| 270 | typedef struct { | ||
| 271 | unsigned int start_cnt : 16; | ||
| 272 | unsigned int dummy1 : 16; | ||
| 273 | } reg_bif_dma_rw_ch3_cnt; | ||
| 274 | #define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 | ||
| 275 | #define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 | ||
| 276 | |||
| 277 | /* Register r_ch3_stat, scope bif_dma, type r */ | ||
| 278 | typedef struct { | ||
| 279 | unsigned int cnt : 16; | ||
| 280 | unsigned int dummy1 : 15; | ||
| 281 | unsigned int run : 1; | ||
| 282 | } reg_bif_dma_r_ch3_stat; | ||
| 283 | #define REG_RD_ADDR_bif_dma_r_ch3_stat 112 | ||
| 284 | |||
| 285 | /* Register rw_intr_mask, scope bif_dma, type rw */ | ||
| 286 | typedef struct { | ||
| 287 | unsigned int ext_dma0 : 1; | ||
| 288 | unsigned int ext_dma1 : 1; | ||
| 289 | unsigned int ext_dma2 : 1; | ||
| 290 | unsigned int ext_dma3 : 1; | ||
| 291 | unsigned int dummy1 : 28; | ||
| 292 | } reg_bif_dma_rw_intr_mask; | ||
| 293 | #define REG_RD_ADDR_bif_dma_rw_intr_mask 128 | ||
| 294 | #define REG_WR_ADDR_bif_dma_rw_intr_mask 128 | ||
| 295 | |||
| 296 | /* Register rw_ack_intr, scope bif_dma, type rw */ | ||
| 297 | typedef struct { | ||
| 298 | unsigned int ext_dma0 : 1; | ||
| 299 | unsigned int ext_dma1 : 1; | ||
| 300 | unsigned int ext_dma2 : 1; | ||
| 301 | unsigned int ext_dma3 : 1; | ||
| 302 | unsigned int dummy1 : 28; | ||
| 303 | } reg_bif_dma_rw_ack_intr; | ||
| 304 | #define REG_RD_ADDR_bif_dma_rw_ack_intr 132 | ||
| 305 | #define REG_WR_ADDR_bif_dma_rw_ack_intr 132 | ||
| 306 | |||
| 307 | /* Register r_intr, scope bif_dma, type r */ | ||
| 308 | typedef struct { | ||
| 309 | unsigned int ext_dma0 : 1; | ||
| 310 | unsigned int ext_dma1 : 1; | ||
| 311 | unsigned int ext_dma2 : 1; | ||
| 312 | unsigned int ext_dma3 : 1; | ||
| 313 | unsigned int dummy1 : 28; | ||
| 314 | } reg_bif_dma_r_intr; | ||
| 315 | #define REG_RD_ADDR_bif_dma_r_intr 136 | ||
| 316 | |||
| 317 | /* Register r_masked_intr, scope bif_dma, type r */ | ||
| 318 | typedef struct { | ||
| 319 | unsigned int ext_dma0 : 1; | ||
| 320 | unsigned int ext_dma1 : 1; | ||
| 321 | unsigned int ext_dma2 : 1; | ||
| 322 | unsigned int ext_dma3 : 1; | ||
| 323 | unsigned int dummy1 : 28; | ||
| 324 | } reg_bif_dma_r_masked_intr; | ||
| 325 | #define REG_RD_ADDR_bif_dma_r_masked_intr 140 | ||
| 326 | |||
| 327 | /* Register rw_pin0_cfg, scope bif_dma, type rw */ | ||
| 328 | typedef struct { | ||
| 329 | unsigned int master_ch : 2; | ||
| 330 | unsigned int master_mode : 3; | ||
| 331 | unsigned int slave_ch : 2; | ||
| 332 | unsigned int slave_mode : 3; | ||
| 333 | unsigned int dummy1 : 22; | ||
| 334 | } reg_bif_dma_rw_pin0_cfg; | ||
| 335 | #define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 | ||
| 336 | #define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 | ||
| 337 | |||
| 338 | /* Register rw_pin1_cfg, scope bif_dma, type rw */ | ||
| 339 | typedef struct { | ||
| 340 | unsigned int master_ch : 2; | ||
| 341 | unsigned int master_mode : 3; | ||
| 342 | unsigned int slave_ch : 2; | ||
| 343 | unsigned int slave_mode : 3; | ||
| 344 | unsigned int dummy1 : 22; | ||
| 345 | } reg_bif_dma_rw_pin1_cfg; | ||
| 346 | #define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 | ||
| 347 | #define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 | ||
| 348 | |||
| 349 | /* Register rw_pin2_cfg, scope bif_dma, type rw */ | ||
| 350 | typedef struct { | ||
| 351 | unsigned int master_ch : 2; | ||
| 352 | unsigned int master_mode : 3; | ||
| 353 | unsigned int slave_ch : 2; | ||
| 354 | unsigned int slave_mode : 3; | ||
| 355 | unsigned int dummy1 : 22; | ||
| 356 | } reg_bif_dma_rw_pin2_cfg; | ||
| 357 | #define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 | ||
| 358 | #define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 | ||
| 359 | |||
| 360 | /* Register rw_pin3_cfg, scope bif_dma, type rw */ | ||
| 361 | typedef struct { | ||
| 362 | unsigned int master_ch : 2; | ||
| 363 | unsigned int master_mode : 3; | ||
| 364 | unsigned int slave_ch : 2; | ||
| 365 | unsigned int slave_mode : 3; | ||
| 366 | unsigned int dummy1 : 22; | ||
| 367 | } reg_bif_dma_rw_pin3_cfg; | ||
| 368 | #define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 | ||
| 369 | #define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 | ||
| 370 | |||
| 371 | /* Register rw_pin4_cfg, scope bif_dma, type rw */ | ||
| 372 | typedef struct { | ||
| 373 | unsigned int master_ch : 2; | ||
| 374 | unsigned int master_mode : 3; | ||
| 375 | unsigned int slave_ch : 2; | ||
| 376 | unsigned int slave_mode : 3; | ||
| 377 | unsigned int dummy1 : 22; | ||
| 378 | } reg_bif_dma_rw_pin4_cfg; | ||
| 379 | #define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 | ||
| 380 | #define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 | ||
| 381 | |||
| 382 | /* Register rw_pin5_cfg, scope bif_dma, type rw */ | ||
| 383 | typedef struct { | ||
| 384 | unsigned int master_ch : 2; | ||
| 385 | unsigned int master_mode : 3; | ||
| 386 | unsigned int slave_ch : 2; | ||
| 387 | unsigned int slave_mode : 3; | ||
| 388 | unsigned int dummy1 : 22; | ||
| 389 | } reg_bif_dma_rw_pin5_cfg; | ||
| 390 | #define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 | ||
| 391 | #define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 | ||
| 392 | |||
| 393 | /* Register rw_pin6_cfg, scope bif_dma, type rw */ | ||
| 394 | typedef struct { | ||
| 395 | unsigned int master_ch : 2; | ||
| 396 | unsigned int master_mode : 3; | ||
| 397 | unsigned int slave_ch : 2; | ||
| 398 | unsigned int slave_mode : 3; | ||
| 399 | unsigned int dummy1 : 22; | ||
| 400 | } reg_bif_dma_rw_pin6_cfg; | ||
| 401 | #define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 | ||
| 402 | #define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 | ||
| 403 | |||
| 404 | /* Register rw_pin7_cfg, scope bif_dma, type rw */ | ||
| 405 | typedef struct { | ||
| 406 | unsigned int master_ch : 2; | ||
| 407 | unsigned int master_mode : 3; | ||
| 408 | unsigned int slave_ch : 2; | ||
| 409 | unsigned int slave_mode : 3; | ||
| 410 | unsigned int dummy1 : 22; | ||
| 411 | } reg_bif_dma_rw_pin7_cfg; | ||
| 412 | #define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 | ||
| 413 | #define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 | ||
| 414 | |||
| 415 | /* Register r_pin_stat, scope bif_dma, type r */ | ||
| 416 | typedef struct { | ||
| 417 | unsigned int pin0 : 1; | ||
| 418 | unsigned int pin1 : 1; | ||
| 419 | unsigned int pin2 : 1; | ||
| 420 | unsigned int pin3 : 1; | ||
| 421 | unsigned int pin4 : 1; | ||
| 422 | unsigned int pin5 : 1; | ||
| 423 | unsigned int pin6 : 1; | ||
| 424 | unsigned int pin7 : 1; | ||
| 425 | unsigned int dummy1 : 24; | ||
| 426 | } reg_bif_dma_r_pin_stat; | ||
| 427 | #define REG_RD_ADDR_bif_dma_r_pin_stat 192 | ||
| 428 | |||
| 429 | |||
| 430 | /* Constants */ | ||
| 431 | enum { | ||
| 432 | regk_bif_dma_as_master = 0x00000001, | ||
| 433 | regk_bif_dma_as_slave = 0x00000001, | ||
| 434 | regk_bif_dma_burst1 = 0x00000000, | ||
| 435 | regk_bif_dma_burst8 = 0x00000001, | ||
| 436 | regk_bif_dma_bw16 = 0x00000001, | ||
| 437 | regk_bif_dma_bw32 = 0x00000002, | ||
| 438 | regk_bif_dma_bw8 = 0x00000000, | ||
| 439 | regk_bif_dma_dack = 0x00000006, | ||
| 440 | regk_bif_dma_dack_inv = 0x00000007, | ||
| 441 | regk_bif_dma_force = 0x00000001, | ||
| 442 | regk_bif_dma_hi = 0x00000003, | ||
| 443 | regk_bif_dma_inv = 0x00000003, | ||
| 444 | regk_bif_dma_lo = 0x00000002, | ||
| 445 | regk_bif_dma_master = 0x00000001, | ||
| 446 | regk_bif_dma_no = 0x00000000, | ||
| 447 | regk_bif_dma_norm = 0x00000002, | ||
| 448 | regk_bif_dma_off = 0x00000000, | ||
| 449 | regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, | ||
| 450 | regk_bif_dma_rw_ch0_start_default = 0x00000000, | ||
| 451 | regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, | ||
| 452 | regk_bif_dma_rw_ch1_start_default = 0x00000000, | ||
| 453 | regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, | ||
| 454 | regk_bif_dma_rw_ch2_start_default = 0x00000000, | ||
| 455 | regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, | ||
| 456 | regk_bif_dma_rw_ch3_start_default = 0x00000000, | ||
| 457 | regk_bif_dma_rw_intr_mask_default = 0x00000000, | ||
| 458 | regk_bif_dma_rw_pin0_cfg_default = 0x00000000, | ||
| 459 | regk_bif_dma_rw_pin1_cfg_default = 0x00000000, | ||
| 460 | regk_bif_dma_rw_pin2_cfg_default = 0x00000000, | ||
| 461 | regk_bif_dma_rw_pin3_cfg_default = 0x00000000, | ||
| 462 | regk_bif_dma_rw_pin4_cfg_default = 0x00000000, | ||
| 463 | regk_bif_dma_rw_pin5_cfg_default = 0x00000000, | ||
| 464 | regk_bif_dma_rw_pin6_cfg_default = 0x00000000, | ||
| 465 | regk_bif_dma_rw_pin7_cfg_default = 0x00000000, | ||
| 466 | regk_bif_dma_slave = 0x00000002, | ||
| 467 | regk_bif_dma_sreq = 0x00000006, | ||
| 468 | regk_bif_dma_sreq_inv = 0x00000007, | ||
| 469 | regk_bif_dma_tc = 0x00000004, | ||
| 470 | regk_bif_dma_tc_inv = 0x00000005, | ||
| 471 | regk_bif_dma_yes = 0x00000001 | ||
| 472 | }; | ||
| 473 | #endif /* __bif_dma_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h new file mode 100644 index 000000000000..0c434585a3f9 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/bif_slave_defs.h | |||
| @@ -0,0 +1,249 @@ | |||
| 1 | #ifndef __bif_slave_defs_h | ||
| 2 | #define __bif_slave_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/bif/rtl/bif_slave_regs.r | ||
| 7 | * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:06:34 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r | ||
| 11 | * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope bif_slave */ | ||
| 86 | |||
| 87 | /* Register rw_slave_cfg, scope bif_slave, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int slave_id : 3; | ||
| 90 | unsigned int use_slave_id : 1; | ||
| 91 | unsigned int boot_rdy : 1; | ||
| 92 | unsigned int loopback : 1; | ||
| 93 | unsigned int dis : 1; | ||
| 94 | unsigned int dummy1 : 25; | ||
| 95 | } reg_bif_slave_rw_slave_cfg; | ||
| 96 | #define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 | ||
| 97 | #define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 | ||
| 98 | |||
| 99 | /* Register r_slave_mode, scope bif_slave, type r */ | ||
| 100 | typedef struct { | ||
| 101 | unsigned int ch0_mode : 1; | ||
| 102 | unsigned int ch1_mode : 1; | ||
| 103 | unsigned int ch2_mode : 1; | ||
| 104 | unsigned int ch3_mode : 1; | ||
| 105 | unsigned int dummy1 : 28; | ||
| 106 | } reg_bif_slave_r_slave_mode; | ||
| 107 | #define REG_RD_ADDR_bif_slave_r_slave_mode 4 | ||
| 108 | |||
| 109 | /* Register rw_ch0_cfg, scope bif_slave, type rw */ | ||
| 110 | typedef struct { | ||
| 111 | unsigned int rd_hold : 2; | ||
| 112 | unsigned int access_mode : 1; | ||
| 113 | unsigned int access_ctrl : 1; | ||
| 114 | unsigned int data_cs : 2; | ||
| 115 | unsigned int dummy1 : 26; | ||
| 116 | } reg_bif_slave_rw_ch0_cfg; | ||
| 117 | #define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 | ||
| 118 | #define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 | ||
| 119 | |||
| 120 | /* Register rw_ch1_cfg, scope bif_slave, type rw */ | ||
| 121 | typedef struct { | ||
| 122 | unsigned int rd_hold : 2; | ||
| 123 | unsigned int access_mode : 1; | ||
| 124 | unsigned int access_ctrl : 1; | ||
| 125 | unsigned int data_cs : 2; | ||
| 126 | unsigned int dummy1 : 26; | ||
| 127 | } reg_bif_slave_rw_ch1_cfg; | ||
| 128 | #define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 | ||
| 129 | #define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 | ||
| 130 | |||
| 131 | /* Register rw_ch2_cfg, scope bif_slave, type rw */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int rd_hold : 2; | ||
| 134 | unsigned int access_mode : 1; | ||
| 135 | unsigned int access_ctrl : 1; | ||
| 136 | unsigned int data_cs : 2; | ||
| 137 | unsigned int dummy1 : 26; | ||
| 138 | } reg_bif_slave_rw_ch2_cfg; | ||
| 139 | #define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 | ||
| 140 | #define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 | ||
| 141 | |||
| 142 | /* Register rw_ch3_cfg, scope bif_slave, type rw */ | ||
| 143 | typedef struct { | ||
| 144 | unsigned int rd_hold : 2; | ||
| 145 | unsigned int access_mode : 1; | ||
| 146 | unsigned int access_ctrl : 1; | ||
| 147 | unsigned int data_cs : 2; | ||
| 148 | unsigned int dummy1 : 26; | ||
| 149 | } reg_bif_slave_rw_ch3_cfg; | ||
| 150 | #define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 | ||
| 151 | #define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 | ||
| 152 | |||
| 153 | /* Register rw_arb_cfg, scope bif_slave, type rw */ | ||
| 154 | typedef struct { | ||
| 155 | unsigned int brin_mode : 1; | ||
| 156 | unsigned int brout_mode : 3; | ||
| 157 | unsigned int bg_mode : 3; | ||
| 158 | unsigned int release : 2; | ||
| 159 | unsigned int acquire : 1; | ||
| 160 | unsigned int settle_time : 2; | ||
| 161 | unsigned int dram_ctrl : 1; | ||
| 162 | unsigned int dummy1 : 19; | ||
| 163 | } reg_bif_slave_rw_arb_cfg; | ||
| 164 | #define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 | ||
| 165 | #define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 | ||
| 166 | |||
| 167 | /* Register r_arb_stat, scope bif_slave, type r */ | ||
| 168 | typedef struct { | ||
| 169 | unsigned int init_mode : 1; | ||
| 170 | unsigned int mode : 1; | ||
| 171 | unsigned int brin : 1; | ||
| 172 | unsigned int brout : 1; | ||
| 173 | unsigned int bg : 1; | ||
| 174 | unsigned int dummy1 : 27; | ||
| 175 | } reg_bif_slave_r_arb_stat; | ||
| 176 | #define REG_RD_ADDR_bif_slave_r_arb_stat 36 | ||
| 177 | |||
| 178 | /* Register rw_intr_mask, scope bif_slave, type rw */ | ||
| 179 | typedef struct { | ||
| 180 | unsigned int bus_release : 1; | ||
| 181 | unsigned int bus_acquire : 1; | ||
| 182 | unsigned int dummy1 : 30; | ||
| 183 | } reg_bif_slave_rw_intr_mask; | ||
| 184 | #define REG_RD_ADDR_bif_slave_rw_intr_mask 64 | ||
| 185 | #define REG_WR_ADDR_bif_slave_rw_intr_mask 64 | ||
| 186 | |||
| 187 | /* Register rw_ack_intr, scope bif_slave, type rw */ | ||
| 188 | typedef struct { | ||
| 189 | unsigned int bus_release : 1; | ||
| 190 | unsigned int bus_acquire : 1; | ||
| 191 | unsigned int dummy1 : 30; | ||
| 192 | } reg_bif_slave_rw_ack_intr; | ||
| 193 | #define REG_RD_ADDR_bif_slave_rw_ack_intr 68 | ||
| 194 | #define REG_WR_ADDR_bif_slave_rw_ack_intr 68 | ||
| 195 | |||
| 196 | /* Register r_intr, scope bif_slave, type r */ | ||
| 197 | typedef struct { | ||
| 198 | unsigned int bus_release : 1; | ||
| 199 | unsigned int bus_acquire : 1; | ||
| 200 | unsigned int dummy1 : 30; | ||
| 201 | } reg_bif_slave_r_intr; | ||
| 202 | #define REG_RD_ADDR_bif_slave_r_intr 72 | ||
| 203 | |||
| 204 | /* Register r_masked_intr, scope bif_slave, type r */ | ||
| 205 | typedef struct { | ||
| 206 | unsigned int bus_release : 1; | ||
| 207 | unsigned int bus_acquire : 1; | ||
| 208 | unsigned int dummy1 : 30; | ||
| 209 | } reg_bif_slave_r_masked_intr; | ||
| 210 | #define REG_RD_ADDR_bif_slave_r_masked_intr 76 | ||
| 211 | |||
| 212 | |||
| 213 | /* Constants */ | ||
| 214 | enum { | ||
| 215 | regk_bif_slave_active_hi = 0x00000003, | ||
| 216 | regk_bif_slave_active_lo = 0x00000002, | ||
| 217 | regk_bif_slave_addr = 0x00000000, | ||
| 218 | regk_bif_slave_always = 0x00000001, | ||
| 219 | regk_bif_slave_at_idle = 0x00000002, | ||
| 220 | regk_bif_slave_burst_end = 0x00000003, | ||
| 221 | regk_bif_slave_dma = 0x00000001, | ||
| 222 | regk_bif_slave_hi = 0x00000003, | ||
| 223 | regk_bif_slave_inv = 0x00000001, | ||
| 224 | regk_bif_slave_lo = 0x00000002, | ||
| 225 | regk_bif_slave_local = 0x00000001, | ||
| 226 | regk_bif_slave_master = 0x00000000, | ||
| 227 | regk_bif_slave_mode_reg = 0x00000001, | ||
| 228 | regk_bif_slave_no = 0x00000000, | ||
| 229 | regk_bif_slave_norm = 0x00000000, | ||
| 230 | regk_bif_slave_on_access = 0x00000000, | ||
| 231 | regk_bif_slave_rw_arb_cfg_default = 0x00000000, | ||
| 232 | regk_bif_slave_rw_ch0_cfg_default = 0x00000000, | ||
| 233 | regk_bif_slave_rw_ch1_cfg_default = 0x00000000, | ||
| 234 | regk_bif_slave_rw_ch2_cfg_default = 0x00000000, | ||
| 235 | regk_bif_slave_rw_ch3_cfg_default = 0x00000000, | ||
| 236 | regk_bif_slave_rw_intr_mask_default = 0x00000000, | ||
| 237 | regk_bif_slave_rw_slave_cfg_default = 0x00000000, | ||
| 238 | regk_bif_slave_shared = 0x00000000, | ||
| 239 | regk_bif_slave_slave = 0x00000001, | ||
| 240 | regk_bif_slave_t0ns = 0x00000003, | ||
| 241 | regk_bif_slave_t10ns = 0x00000002, | ||
| 242 | regk_bif_slave_t20ns = 0x00000003, | ||
| 243 | regk_bif_slave_t30ns = 0x00000002, | ||
| 244 | regk_bif_slave_t40ns = 0x00000001, | ||
| 245 | regk_bif_slave_t50ns = 0x00000000, | ||
| 246 | regk_bif_slave_yes = 0x00000001, | ||
| 247 | regk_bif_slave_z = 0x00000004 | ||
| 248 | }; | ||
| 249 | #endif /* __bif_slave_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h new file mode 100644 index 000000000000..abc5f20705f7 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/config_defs.h | |||
| @@ -0,0 +1,142 @@ | |||
| 1 | #ifndef __config_defs_h | ||
| 2 | #define __config_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../rtl/config_regs.r | ||
| 7 | * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp | ||
| 8 | * last modfied: Thu Mar 4 12:34:39 2004 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r | ||
| 11 | * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope config */ | ||
| 86 | |||
| 87 | /* Register r_bootsel, scope config, type r */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int boot_mode : 3; | ||
| 90 | unsigned int full_duplex : 1; | ||
| 91 | unsigned int user : 1; | ||
| 92 | unsigned int pll : 1; | ||
| 93 | unsigned int flash_bw : 1; | ||
| 94 | unsigned int dummy1 : 25; | ||
| 95 | } reg_config_r_bootsel; | ||
| 96 | #define REG_RD_ADDR_config_r_bootsel 0 | ||
| 97 | |||
| 98 | /* Register rw_clk_ctrl, scope config, type rw */ | ||
| 99 | typedef struct { | ||
| 100 | unsigned int pll : 1; | ||
| 101 | unsigned int cpu : 1; | ||
| 102 | unsigned int iop : 1; | ||
| 103 | unsigned int dma01_eth0 : 1; | ||
| 104 | unsigned int dma23 : 1; | ||
| 105 | unsigned int dma45 : 1; | ||
| 106 | unsigned int dma67 : 1; | ||
| 107 | unsigned int dma89_strcop : 1; | ||
| 108 | unsigned int bif : 1; | ||
| 109 | unsigned int fix_io : 1; | ||
| 110 | unsigned int dummy1 : 22; | ||
| 111 | } reg_config_rw_clk_ctrl; | ||
| 112 | #define REG_RD_ADDR_config_rw_clk_ctrl 4 | ||
| 113 | #define REG_WR_ADDR_config_rw_clk_ctrl 4 | ||
| 114 | |||
| 115 | /* Register rw_pad_ctrl, scope config, type rw */ | ||
| 116 | typedef struct { | ||
| 117 | unsigned int usb_susp : 1; | ||
| 118 | unsigned int phyrst_n : 1; | ||
| 119 | unsigned int dummy1 : 30; | ||
| 120 | } reg_config_rw_pad_ctrl; | ||
| 121 | #define REG_RD_ADDR_config_rw_pad_ctrl 8 | ||
| 122 | #define REG_WR_ADDR_config_rw_pad_ctrl 8 | ||
| 123 | |||
| 124 | |||
| 125 | /* Constants */ | ||
| 126 | enum { | ||
| 127 | regk_config_bw16 = 0x00000000, | ||
| 128 | regk_config_bw32 = 0x00000001, | ||
| 129 | regk_config_master = 0x00000005, | ||
| 130 | regk_config_nand = 0x00000003, | ||
| 131 | regk_config_net_rx = 0x00000001, | ||
| 132 | regk_config_net_tx_rx = 0x00000002, | ||
| 133 | regk_config_no = 0x00000000, | ||
| 134 | regk_config_none = 0x00000007, | ||
| 135 | regk_config_nor = 0x00000000, | ||
| 136 | regk_config_rw_clk_ctrl_default = 0x00000002, | ||
| 137 | regk_config_rw_pad_ctrl_default = 0x00000000, | ||
| 138 | regk_config_ser = 0x00000004, | ||
| 139 | regk_config_slave = 0x00000006, | ||
| 140 | regk_config_yes = 0x00000001 | ||
| 141 | }; | ||
| 142 | #endif /* __config_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h new file mode 100644 index 000000000000..26aa3efcf91b --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/gio_defs.h | |||
| @@ -0,0 +1,295 @@ | |||
| 1 | #ifndef __gio_defs_h | ||
| 2 | #define __gio_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/gio/rtl/gio_regs.r | ||
| 7 | * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:07:47 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r | ||
| 11 | * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope gio */ | ||
| 86 | |||
| 87 | /* Register rw_pa_dout, scope gio, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int data : 8; | ||
| 90 | unsigned int dummy1 : 24; | ||
| 91 | } reg_gio_rw_pa_dout; | ||
| 92 | #define REG_RD_ADDR_gio_rw_pa_dout 0 | ||
| 93 | #define REG_WR_ADDR_gio_rw_pa_dout 0 | ||
| 94 | |||
| 95 | /* Register r_pa_din, scope gio, type r */ | ||
| 96 | typedef struct { | ||
| 97 | unsigned int data : 8; | ||
| 98 | unsigned int dummy1 : 24; | ||
| 99 | } reg_gio_r_pa_din; | ||
| 100 | #define REG_RD_ADDR_gio_r_pa_din 4 | ||
| 101 | |||
| 102 | /* Register rw_pa_oe, scope gio, type rw */ | ||
| 103 | typedef struct { | ||
| 104 | unsigned int oe : 8; | ||
| 105 | unsigned int dummy1 : 24; | ||
| 106 | } reg_gio_rw_pa_oe; | ||
| 107 | #define REG_RD_ADDR_gio_rw_pa_oe 8 | ||
| 108 | #define REG_WR_ADDR_gio_rw_pa_oe 8 | ||
| 109 | |||
| 110 | /* Register rw_intr_cfg, scope gio, type rw */ | ||
| 111 | typedef struct { | ||
| 112 | unsigned int pa0 : 3; | ||
| 113 | unsigned int pa1 : 3; | ||
| 114 | unsigned int pa2 : 3; | ||
| 115 | unsigned int pa3 : 3; | ||
| 116 | unsigned int pa4 : 3; | ||
| 117 | unsigned int pa5 : 3; | ||
| 118 | unsigned int pa6 : 3; | ||
| 119 | unsigned int pa7 : 3; | ||
| 120 | unsigned int dummy1 : 8; | ||
| 121 | } reg_gio_rw_intr_cfg; | ||
| 122 | #define REG_RD_ADDR_gio_rw_intr_cfg 12 | ||
| 123 | #define REG_WR_ADDR_gio_rw_intr_cfg 12 | ||
| 124 | |||
| 125 | /* Register rw_intr_mask, scope gio, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int pa0 : 1; | ||
| 128 | unsigned int pa1 : 1; | ||
| 129 | unsigned int pa2 : 1; | ||
| 130 | unsigned int pa3 : 1; | ||
| 131 | unsigned int pa4 : 1; | ||
| 132 | unsigned int pa5 : 1; | ||
| 133 | unsigned int pa6 : 1; | ||
| 134 | unsigned int pa7 : 1; | ||
| 135 | unsigned int dummy1 : 24; | ||
| 136 | } reg_gio_rw_intr_mask; | ||
| 137 | #define REG_RD_ADDR_gio_rw_intr_mask 16 | ||
| 138 | #define REG_WR_ADDR_gio_rw_intr_mask 16 | ||
| 139 | |||
| 140 | /* Register rw_ack_intr, scope gio, type rw */ | ||
| 141 | typedef struct { | ||
| 142 | unsigned int pa0 : 1; | ||
| 143 | unsigned int pa1 : 1; | ||
| 144 | unsigned int pa2 : 1; | ||
| 145 | unsigned int pa3 : 1; | ||
| 146 | unsigned int pa4 : 1; | ||
| 147 | unsigned int pa5 : 1; | ||
| 148 | unsigned int pa6 : 1; | ||
| 149 | unsigned int pa7 : 1; | ||
| 150 | unsigned int dummy1 : 24; | ||
| 151 | } reg_gio_rw_ack_intr; | ||
| 152 | #define REG_RD_ADDR_gio_rw_ack_intr 20 | ||
| 153 | #define REG_WR_ADDR_gio_rw_ack_intr 20 | ||
| 154 | |||
| 155 | /* Register r_intr, scope gio, type r */ | ||
| 156 | typedef struct { | ||
| 157 | unsigned int pa0 : 1; | ||
| 158 | unsigned int pa1 : 1; | ||
| 159 | unsigned int pa2 : 1; | ||
| 160 | unsigned int pa3 : 1; | ||
| 161 | unsigned int pa4 : 1; | ||
| 162 | unsigned int pa5 : 1; | ||
| 163 | unsigned int pa6 : 1; | ||
| 164 | unsigned int pa7 : 1; | ||
| 165 | unsigned int dummy1 : 24; | ||
| 166 | } reg_gio_r_intr; | ||
| 167 | #define REG_RD_ADDR_gio_r_intr 24 | ||
| 168 | |||
| 169 | /* Register r_masked_intr, scope gio, type r */ | ||
| 170 | typedef struct { | ||
| 171 | unsigned int pa0 : 1; | ||
| 172 | unsigned int pa1 : 1; | ||
| 173 | unsigned int pa2 : 1; | ||
| 174 | unsigned int pa3 : 1; | ||
| 175 | unsigned int pa4 : 1; | ||
| 176 | unsigned int pa5 : 1; | ||
| 177 | unsigned int pa6 : 1; | ||
| 178 | unsigned int pa7 : 1; | ||
| 179 | unsigned int dummy1 : 24; | ||
| 180 | } reg_gio_r_masked_intr; | ||
| 181 | #define REG_RD_ADDR_gio_r_masked_intr 28 | ||
| 182 | |||
| 183 | /* Register rw_pb_dout, scope gio, type rw */ | ||
| 184 | typedef struct { | ||
| 185 | unsigned int data : 18; | ||
| 186 | unsigned int dummy1 : 14; | ||
| 187 | } reg_gio_rw_pb_dout; | ||
| 188 | #define REG_RD_ADDR_gio_rw_pb_dout 32 | ||
| 189 | #define REG_WR_ADDR_gio_rw_pb_dout 32 | ||
| 190 | |||
| 191 | /* Register r_pb_din, scope gio, type r */ | ||
| 192 | typedef struct { | ||
| 193 | unsigned int data : 18; | ||
| 194 | unsigned int dummy1 : 14; | ||
| 195 | } reg_gio_r_pb_din; | ||
| 196 | #define REG_RD_ADDR_gio_r_pb_din 36 | ||
| 197 | |||
| 198 | /* Register rw_pb_oe, scope gio, type rw */ | ||
| 199 | typedef struct { | ||
| 200 | unsigned int oe : 18; | ||
| 201 | unsigned int dummy1 : 14; | ||
| 202 | } reg_gio_rw_pb_oe; | ||
| 203 | #define REG_RD_ADDR_gio_rw_pb_oe 40 | ||
| 204 | #define REG_WR_ADDR_gio_rw_pb_oe 40 | ||
| 205 | |||
| 206 | /* Register rw_pc_dout, scope gio, type rw */ | ||
| 207 | typedef struct { | ||
| 208 | unsigned int data : 18; | ||
| 209 | unsigned int dummy1 : 14; | ||
| 210 | } reg_gio_rw_pc_dout; | ||
| 211 | #define REG_RD_ADDR_gio_rw_pc_dout 48 | ||
| 212 | #define REG_WR_ADDR_gio_rw_pc_dout 48 | ||
| 213 | |||
| 214 | /* Register r_pc_din, scope gio, type r */ | ||
| 215 | typedef struct { | ||
| 216 | unsigned int data : 18; | ||
| 217 | unsigned int dummy1 : 14; | ||
| 218 | } reg_gio_r_pc_din; | ||
| 219 | #define REG_RD_ADDR_gio_r_pc_din 52 | ||
| 220 | |||
| 221 | /* Register rw_pc_oe, scope gio, type rw */ | ||
| 222 | typedef struct { | ||
| 223 | unsigned int oe : 18; | ||
| 224 | unsigned int dummy1 : 14; | ||
| 225 | } reg_gio_rw_pc_oe; | ||
| 226 | #define REG_RD_ADDR_gio_rw_pc_oe 56 | ||
| 227 | #define REG_WR_ADDR_gio_rw_pc_oe 56 | ||
| 228 | |||
| 229 | /* Register rw_pd_dout, scope gio, type rw */ | ||
| 230 | typedef struct { | ||
| 231 | unsigned int data : 18; | ||
| 232 | unsigned int dummy1 : 14; | ||
| 233 | } reg_gio_rw_pd_dout; | ||
| 234 | #define REG_RD_ADDR_gio_rw_pd_dout 64 | ||
| 235 | #define REG_WR_ADDR_gio_rw_pd_dout 64 | ||
| 236 | |||
| 237 | /* Register r_pd_din, scope gio, type r */ | ||
| 238 | typedef struct { | ||
| 239 | unsigned int data : 18; | ||
| 240 | unsigned int dummy1 : 14; | ||
| 241 | } reg_gio_r_pd_din; | ||
| 242 | #define REG_RD_ADDR_gio_r_pd_din 68 | ||
| 243 | |||
| 244 | /* Register rw_pd_oe, scope gio, type rw */ | ||
| 245 | typedef struct { | ||
| 246 | unsigned int oe : 18; | ||
| 247 | unsigned int dummy1 : 14; | ||
| 248 | } reg_gio_rw_pd_oe; | ||
| 249 | #define REG_RD_ADDR_gio_rw_pd_oe 72 | ||
| 250 | #define REG_WR_ADDR_gio_rw_pd_oe 72 | ||
| 251 | |||
| 252 | /* Register rw_pe_dout, scope gio, type rw */ | ||
| 253 | typedef struct { | ||
| 254 | unsigned int data : 18; | ||
| 255 | unsigned int dummy1 : 14; | ||
| 256 | } reg_gio_rw_pe_dout; | ||
| 257 | #define REG_RD_ADDR_gio_rw_pe_dout 80 | ||
| 258 | #define REG_WR_ADDR_gio_rw_pe_dout 80 | ||
| 259 | |||
| 260 | /* Register r_pe_din, scope gio, type r */ | ||
| 261 | typedef struct { | ||
| 262 | unsigned int data : 18; | ||
| 263 | unsigned int dummy1 : 14; | ||
| 264 | } reg_gio_r_pe_din; | ||
| 265 | #define REG_RD_ADDR_gio_r_pe_din 84 | ||
| 266 | |||
| 267 | /* Register rw_pe_oe, scope gio, type rw */ | ||
| 268 | typedef struct { | ||
| 269 | unsigned int oe : 18; | ||
| 270 | unsigned int dummy1 : 14; | ||
| 271 | } reg_gio_rw_pe_oe; | ||
| 272 | #define REG_RD_ADDR_gio_rw_pe_oe 88 | ||
| 273 | #define REG_WR_ADDR_gio_rw_pe_oe 88 | ||
| 274 | |||
| 275 | |||
| 276 | /* Constants */ | ||
| 277 | enum { | ||
| 278 | regk_gio_anyedge = 0x00000007, | ||
| 279 | regk_gio_hi = 0x00000001, | ||
| 280 | regk_gio_lo = 0x00000002, | ||
| 281 | regk_gio_negedge = 0x00000006, | ||
| 282 | regk_gio_no = 0x00000000, | ||
| 283 | regk_gio_off = 0x00000000, | ||
| 284 | regk_gio_posedge = 0x00000005, | ||
| 285 | regk_gio_rw_intr_cfg_default = 0x00000000, | ||
| 286 | regk_gio_rw_intr_mask_default = 0x00000000, | ||
| 287 | regk_gio_rw_pa_oe_default = 0x00000000, | ||
| 288 | regk_gio_rw_pb_oe_default = 0x00000000, | ||
| 289 | regk_gio_rw_pc_oe_default = 0x00000000, | ||
| 290 | regk_gio_rw_pd_oe_default = 0x00000000, | ||
| 291 | regk_gio_rw_pe_oe_default = 0x00000000, | ||
| 292 | regk_gio_set = 0x00000003, | ||
| 293 | regk_gio_yes = 0x00000001 | ||
| 294 | }; | ||
| 295 | #endif /* __gio_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h new file mode 100644 index 000000000000..bacc2a895c21 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version | ||
| 2 | from ../../inst/intr_vect/rtl/guinness/ivmask.config.r | ||
| 3 | version . */ | ||
| 4 | |||
| 5 | #ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R | ||
| 6 | #define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R | ||
| 7 | #define MEMARB_INTR_VECT 0x31 | ||
| 8 | #define GEN_IO_INTR_VECT 0x32 | ||
| 9 | #define GIO_INTR_VECT GEN_IO_INTR_VECT | ||
| 10 | #define IOP0_INTR_VECT 0x33 | ||
| 11 | #define IOP1_INTR_VECT 0x34 | ||
| 12 | #define IOP2_INTR_VECT 0x35 | ||
| 13 | #define IOP3_INTR_VECT 0x36 | ||
| 14 | #define DMA0_INTR_VECT 0x37 | ||
| 15 | #define DMA1_INTR_VECT 0x38 | ||
| 16 | #define DMA2_INTR_VECT 0x39 | ||
| 17 | #define DMA3_INTR_VECT 0x3a | ||
| 18 | #define DMA4_INTR_VECT 0x3b | ||
| 19 | #define DMA5_INTR_VECT 0x3c | ||
| 20 | #define DMA6_INTR_VECT 0x3d | ||
| 21 | #define DMA7_INTR_VECT 0x3e | ||
| 22 | #define DMA8_INTR_VECT 0x3f | ||
| 23 | #define DMA9_INTR_VECT 0x40 | ||
| 24 | #define ATA_INTR_VECT 0x41 | ||
| 25 | #define SSER0_INTR_VECT 0x42 | ||
| 26 | #define SSER1_INTR_VECT 0x43 | ||
| 27 | #define SER0_INTR_VECT 0x44 | ||
| 28 | #define SER1_INTR_VECT 0x45 | ||
| 29 | #define SER2_INTR_VECT 0x46 | ||
| 30 | #define SER3_INTR_VECT 0x47 | ||
| 31 | #define P21_INTR_VECT 0x48 | ||
| 32 | #define ETH0_INTR_VECT 0x49 | ||
| 33 | #define ETH1_INTR_VECT 0x4a | ||
| 34 | #define TIMER_INTR_VECT 0x4b | ||
| 35 | #define TIMER0_INTR_VECT TIMER_INTR_VECT | ||
| 36 | #define BIF_ARB_INTR_VECT 0x4c | ||
| 37 | #define BIF_DMA_INTR_VECT 0x4d | ||
| 38 | #define EXT_INTR_VECT 0x4e | ||
| 39 | #define IPI_INTR_VECT 0x4f | ||
| 40 | #define NBR_INTR_VECT 0x50 | ||
| 41 | #endif | ||
diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h index 535aaf1b4b52..aa65128ae1aa 100644 --- a/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/intr_vect_defs.h | |||
| @@ -4,11 +4,11 @@ | |||
| 4 | /* | 4 | /* |
| 5 | * This file is autogenerated from | 5 | * This file is autogenerated from |
| 6 | * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r | 6 | * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r |
| 7 | * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp | 7 | * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp |
| 8 | * last modfied: Mon Apr 11 16:08:03 2005 | 8 | * last modfied: Mon Apr 11 16:08:03 2005 |
| 9 | * | 9 | * |
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r | 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r |
| 11 | * id: $Id: intr_vect_defs.h,v 1.8 2005/04/24 18:30:58 starvik Exp $ | 11 | * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ |
| 12 | * Any changes here will be lost. | 12 | * Any changes here will be lost. |
| 13 | * | 13 | * |
| 14 | * -*- buffer-read-only: t -*- | 14 | * -*- buffer-read-only: t -*- |
| @@ -84,6 +84,7 @@ | |||
| 84 | 84 | ||
| 85 | /* C-code for register scope intr_vect */ | 85 | /* C-code for register scope intr_vect */ |
| 86 | 86 | ||
| 87 | #define STRIDE_intr_vect_rw_mask 0 | ||
| 87 | /* Register rw_mask, scope intr_vect, type rw */ | 88 | /* Register rw_mask, scope intr_vect, type rw */ |
| 88 | typedef struct { | 89 | typedef struct { |
| 89 | unsigned int memarb : 1; | 90 | unsigned int memarb : 1; |
| @@ -112,7 +113,7 @@ typedef struct { | |||
| 112 | unsigned int p21 : 1; | 113 | unsigned int p21 : 1; |
| 113 | unsigned int eth0 : 1; | 114 | unsigned int eth0 : 1; |
| 114 | unsigned int eth1 : 1; | 115 | unsigned int eth1 : 1; |
| 115 | unsigned int timer : 1; | 116 | unsigned int timer0 : 1; |
| 116 | unsigned int bif_arb : 1; | 117 | unsigned int bif_arb : 1; |
| 117 | unsigned int bif_dma : 1; | 118 | unsigned int bif_dma : 1; |
| 118 | unsigned int ext : 1; | 119 | unsigned int ext : 1; |
| @@ -121,6 +122,7 @@ typedef struct { | |||
| 121 | #define REG_RD_ADDR_intr_vect_rw_mask 0 | 122 | #define REG_RD_ADDR_intr_vect_rw_mask 0 |
| 122 | #define REG_WR_ADDR_intr_vect_rw_mask 0 | 123 | #define REG_WR_ADDR_intr_vect_rw_mask 0 |
| 123 | 124 | ||
| 125 | #define STRIDE_intr_vect_r_vect 0 | ||
| 124 | /* Register r_vect, scope intr_vect, type r */ | 126 | /* Register r_vect, scope intr_vect, type r */ |
| 125 | typedef struct { | 127 | typedef struct { |
| 126 | unsigned int memarb : 1; | 128 | unsigned int memarb : 1; |
| @@ -157,6 +159,7 @@ typedef struct { | |||
| 157 | } reg_intr_vect_r_vect; | 159 | } reg_intr_vect_r_vect; |
| 158 | #define REG_RD_ADDR_intr_vect_r_vect 4 | 160 | #define REG_RD_ADDR_intr_vect_r_vect 4 |
| 159 | 161 | ||
| 162 | #define STRIDE_intr_vect_r_masked_vect 0 | ||
| 160 | /* Register r_masked_vect, scope intr_vect, type r */ | 163 | /* Register r_masked_vect, scope intr_vect, type r */ |
| 161 | typedef struct { | 164 | typedef struct { |
| 162 | unsigned int memarb : 1; | 165 | unsigned int memarb : 1; |
| @@ -209,7 +212,7 @@ typedef struct { | |||
| 209 | #define REG_RD_ADDR_intr_vect_r_guru 16 | 212 | #define REG_RD_ADDR_intr_vect_r_guru 16 |
| 210 | 213 | ||
| 211 | /* Register rw_ipi, scope intr_vect, type rw */ | 214 | /* Register rw_ipi, scope intr_vect, type rw */ |
| 212 | typedef struct | 215 | typedef struct |
| 213 | { | 216 | { |
| 214 | unsigned int vector; | 217 | unsigned int vector; |
| 215 | } reg_intr_vect_rw_ipi; | 218 | } reg_intr_vect_rw_ipi; |
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h new file mode 100644 index 000000000000..dcaaec4620ba --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_bp_defs.h | |||
| @@ -0,0 +1,205 @@ | |||
| 1 | #ifndef __marb_bp_defs_h | ||
| 2 | #define __marb_bp_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Fri Nov 7 15:36:04 2003 | ||
| 9 | * | ||
| 10 | * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 11 | * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | /* C-code for register scope marb_bp */ | ||
| 75 | |||
| 76 | /* Register rw_first_addr, scope marb_bp, type rw */ | ||
| 77 | typedef unsigned int reg_marb_bp_rw_first_addr; | ||
| 78 | #define REG_RD_ADDR_marb_bp_rw_first_addr 0 | ||
| 79 | #define REG_WR_ADDR_marb_bp_rw_first_addr 0 | ||
| 80 | |||
| 81 | /* Register rw_last_addr, scope marb_bp, type rw */ | ||
| 82 | typedef unsigned int reg_marb_bp_rw_last_addr; | ||
| 83 | #define REG_RD_ADDR_marb_bp_rw_last_addr 4 | ||
| 84 | #define REG_WR_ADDR_marb_bp_rw_last_addr 4 | ||
| 85 | |||
| 86 | /* Register rw_op, scope marb_bp, type rw */ | ||
| 87 | typedef struct { | ||
| 88 | unsigned int read : 1; | ||
| 89 | unsigned int write : 1; | ||
| 90 | unsigned int read_excl : 1; | ||
| 91 | unsigned int pri_write : 1; | ||
| 92 | unsigned int us_read : 1; | ||
| 93 | unsigned int us_write : 1; | ||
| 94 | unsigned int us_read_excl : 1; | ||
| 95 | unsigned int us_pri_write : 1; | ||
| 96 | unsigned int dummy1 : 24; | ||
| 97 | } reg_marb_bp_rw_op; | ||
| 98 | #define REG_RD_ADDR_marb_bp_rw_op 8 | ||
| 99 | #define REG_WR_ADDR_marb_bp_rw_op 8 | ||
| 100 | |||
| 101 | /* Register rw_clients, scope marb_bp, type rw */ | ||
| 102 | typedef struct { | ||
| 103 | unsigned int dma0 : 1; | ||
| 104 | unsigned int dma1 : 1; | ||
| 105 | unsigned int dma2 : 1; | ||
| 106 | unsigned int dma3 : 1; | ||
| 107 | unsigned int dma4 : 1; | ||
| 108 | unsigned int dma5 : 1; | ||
| 109 | unsigned int dma6 : 1; | ||
| 110 | unsigned int dma7 : 1; | ||
| 111 | unsigned int dma8 : 1; | ||
| 112 | unsigned int dma9 : 1; | ||
| 113 | unsigned int cpui : 1; | ||
| 114 | unsigned int cpud : 1; | ||
| 115 | unsigned int iop : 1; | ||
| 116 | unsigned int slave : 1; | ||
| 117 | unsigned int dummy1 : 18; | ||
| 118 | } reg_marb_bp_rw_clients; | ||
| 119 | #define REG_RD_ADDR_marb_bp_rw_clients 12 | ||
| 120 | #define REG_WR_ADDR_marb_bp_rw_clients 12 | ||
| 121 | |||
| 122 | /* Register rw_options, scope marb_bp, type rw */ | ||
| 123 | typedef struct { | ||
| 124 | unsigned int wrap : 1; | ||
| 125 | unsigned int dummy1 : 31; | ||
| 126 | } reg_marb_bp_rw_options; | ||
| 127 | #define REG_RD_ADDR_marb_bp_rw_options 16 | ||
| 128 | #define REG_WR_ADDR_marb_bp_rw_options 16 | ||
| 129 | |||
| 130 | /* Register r_break_addr, scope marb_bp, type r */ | ||
| 131 | typedef unsigned int reg_marb_bp_r_break_addr; | ||
| 132 | #define REG_RD_ADDR_marb_bp_r_break_addr 20 | ||
| 133 | |||
| 134 | /* Register r_break_op, scope marb_bp, type r */ | ||
| 135 | typedef struct { | ||
| 136 | unsigned int read : 1; | ||
| 137 | unsigned int write : 1; | ||
| 138 | unsigned int read_excl : 1; | ||
| 139 | unsigned int pri_write : 1; | ||
| 140 | unsigned int us_read : 1; | ||
| 141 | unsigned int us_write : 1; | ||
| 142 | unsigned int us_read_excl : 1; | ||
| 143 | unsigned int us_pri_write : 1; | ||
| 144 | unsigned int dummy1 : 24; | ||
| 145 | } reg_marb_bp_r_break_op; | ||
| 146 | #define REG_RD_ADDR_marb_bp_r_break_op 24 | ||
| 147 | |||
| 148 | /* Register r_break_clients, scope marb_bp, type r */ | ||
| 149 | typedef struct { | ||
| 150 | unsigned int dma0 : 1; | ||
| 151 | unsigned int dma1 : 1; | ||
| 152 | unsigned int dma2 : 1; | ||
| 153 | unsigned int dma3 : 1; | ||
| 154 | unsigned int dma4 : 1; | ||
| 155 | unsigned int dma5 : 1; | ||
| 156 | unsigned int dma6 : 1; | ||
| 157 | unsigned int dma7 : 1; | ||
| 158 | unsigned int dma8 : 1; | ||
| 159 | unsigned int dma9 : 1; | ||
| 160 | unsigned int cpui : 1; | ||
| 161 | unsigned int cpud : 1; | ||
| 162 | unsigned int iop : 1; | ||
| 163 | unsigned int slave : 1; | ||
| 164 | unsigned int dummy1 : 18; | ||
| 165 | } reg_marb_bp_r_break_clients; | ||
| 166 | #define REG_RD_ADDR_marb_bp_r_break_clients 28 | ||
| 167 | |||
| 168 | /* Register r_break_first_client, scope marb_bp, type r */ | ||
| 169 | typedef struct { | ||
| 170 | unsigned int dma0 : 1; | ||
| 171 | unsigned int dma1 : 1; | ||
| 172 | unsigned int dma2 : 1; | ||
| 173 | unsigned int dma3 : 1; | ||
| 174 | unsigned int dma4 : 1; | ||
| 175 | unsigned int dma5 : 1; | ||
| 176 | unsigned int dma6 : 1; | ||
| 177 | unsigned int dma7 : 1; | ||
| 178 | unsigned int dma8 : 1; | ||
| 179 | unsigned int dma9 : 1; | ||
| 180 | unsigned int cpui : 1; | ||
| 181 | unsigned int cpud : 1; | ||
| 182 | unsigned int iop : 1; | ||
| 183 | unsigned int slave : 1; | ||
| 184 | unsigned int dummy1 : 18; | ||
| 185 | } reg_marb_bp_r_break_first_client; | ||
| 186 | #define REG_RD_ADDR_marb_bp_r_break_first_client 32 | ||
| 187 | |||
| 188 | /* Register r_break_size, scope marb_bp, type r */ | ||
| 189 | typedef unsigned int reg_marb_bp_r_break_size; | ||
| 190 | #define REG_RD_ADDR_marb_bp_r_break_size 36 | ||
| 191 | |||
| 192 | /* Register rw_ack, scope marb_bp, type rw */ | ||
| 193 | typedef unsigned int reg_marb_bp_rw_ack; | ||
| 194 | #define REG_RD_ADDR_marb_bp_rw_ack 40 | ||
| 195 | #define REG_WR_ADDR_marb_bp_rw_ack 40 | ||
| 196 | |||
| 197 | |||
| 198 | /* Constants */ | ||
| 199 | enum { | ||
| 200 | regk_marb_bp_no = 0x00000000, | ||
| 201 | regk_marb_bp_rw_op_default = 0x00000000, | ||
| 202 | regk_marb_bp_rw_options_default = 0x00000000, | ||
| 203 | regk_marb_bp_yes = 0x00000001 | ||
| 204 | }; | ||
| 205 | #endif /* __marb_bp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h new file mode 100644 index 000000000000..254da0854986 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/marb_defs.h | |||
| @@ -0,0 +1,475 @@ | |||
| 1 | #ifndef __marb_defs_h | ||
| 2 | #define __marb_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 7 | * id: <not found> | ||
| 8 | * last modfied: Mon Apr 11 16:12:16 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 11 | * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope marb */ | ||
| 86 | |||
| 87 | #define STRIDE_marb_rw_int_slots 4 | ||
| 88 | /* Register rw_int_slots, scope marb, type rw */ | ||
| 89 | typedef struct { | ||
| 90 | unsigned int owner : 4; | ||
| 91 | unsigned int dummy1 : 28; | ||
| 92 | } reg_marb_rw_int_slots; | ||
| 93 | #define REG_RD_ADDR_marb_rw_int_slots 0 | ||
| 94 | #define REG_WR_ADDR_marb_rw_int_slots 0 | ||
| 95 | |||
| 96 | #define STRIDE_marb_rw_ext_slots 4 | ||
| 97 | /* Register rw_ext_slots, scope marb, type rw */ | ||
| 98 | typedef struct { | ||
| 99 | unsigned int owner : 4; | ||
| 100 | unsigned int dummy1 : 28; | ||
| 101 | } reg_marb_rw_ext_slots; | ||
| 102 | #define REG_RD_ADDR_marb_rw_ext_slots 256 | ||
| 103 | #define REG_WR_ADDR_marb_rw_ext_slots 256 | ||
| 104 | |||
| 105 | #define STRIDE_marb_rw_regs_slots 4 | ||
| 106 | /* Register rw_regs_slots, scope marb, type rw */ | ||
| 107 | typedef struct { | ||
| 108 | unsigned int owner : 4; | ||
| 109 | unsigned int dummy1 : 28; | ||
| 110 | } reg_marb_rw_regs_slots; | ||
| 111 | #define REG_RD_ADDR_marb_rw_regs_slots 512 | ||
| 112 | #define REG_WR_ADDR_marb_rw_regs_slots 512 | ||
| 113 | |||
| 114 | /* Register rw_intr_mask, scope marb, type rw */ | ||
| 115 | typedef struct { | ||
| 116 | unsigned int bp0 : 1; | ||
| 117 | unsigned int bp1 : 1; | ||
| 118 | unsigned int bp2 : 1; | ||
| 119 | unsigned int bp3 : 1; | ||
| 120 | unsigned int dummy1 : 28; | ||
| 121 | } reg_marb_rw_intr_mask; | ||
| 122 | #define REG_RD_ADDR_marb_rw_intr_mask 528 | ||
| 123 | #define REG_WR_ADDR_marb_rw_intr_mask 528 | ||
| 124 | |||
| 125 | /* Register rw_ack_intr, scope marb, type rw */ | ||
| 126 | typedef struct { | ||
| 127 | unsigned int bp0 : 1; | ||
| 128 | unsigned int bp1 : 1; | ||
| 129 | unsigned int bp2 : 1; | ||
| 130 | unsigned int bp3 : 1; | ||
| 131 | unsigned int dummy1 : 28; | ||
| 132 | } reg_marb_rw_ack_intr; | ||
| 133 | #define REG_RD_ADDR_marb_rw_ack_intr 532 | ||
| 134 | #define REG_WR_ADDR_marb_rw_ack_intr 532 | ||
| 135 | |||
| 136 | /* Register r_intr, scope marb, type r */ | ||
| 137 | typedef struct { | ||
| 138 | unsigned int bp0 : 1; | ||
| 139 | unsigned int bp1 : 1; | ||
| 140 | unsigned int bp2 : 1; | ||
| 141 | unsigned int bp3 : 1; | ||
| 142 | unsigned int dummy1 : 28; | ||
| 143 | } reg_marb_r_intr; | ||
| 144 | #define REG_RD_ADDR_marb_r_intr 536 | ||
| 145 | |||
| 146 | /* Register r_masked_intr, scope marb, type r */ | ||
| 147 | typedef struct { | ||
| 148 | unsigned int bp0 : 1; | ||
| 149 | unsigned int bp1 : 1; | ||
| 150 | unsigned int bp2 : 1; | ||
| 151 | unsigned int bp3 : 1; | ||
| 152 | unsigned int dummy1 : 28; | ||
| 153 | } reg_marb_r_masked_intr; | ||
| 154 | #define REG_RD_ADDR_marb_r_masked_intr 540 | ||
| 155 | |||
| 156 | /* Register rw_stop_mask, scope marb, type rw */ | ||
| 157 | typedef struct { | ||
| 158 | unsigned int dma0 : 1; | ||
| 159 | unsigned int dma1 : 1; | ||
| 160 | unsigned int dma2 : 1; | ||
| 161 | unsigned int dma3 : 1; | ||
| 162 | unsigned int dma4 : 1; | ||
| 163 | unsigned int dma5 : 1; | ||
| 164 | unsigned int dma6 : 1; | ||
| 165 | unsigned int dma7 : 1; | ||
| 166 | unsigned int dma8 : 1; | ||
| 167 | unsigned int dma9 : 1; | ||
| 168 | unsigned int cpui : 1; | ||
| 169 | unsigned int cpud : 1; | ||
| 170 | unsigned int iop : 1; | ||
| 171 | unsigned int slave : 1; | ||
| 172 | unsigned int dummy1 : 18; | ||
| 173 | } reg_marb_rw_stop_mask; | ||
| 174 | #define REG_RD_ADDR_marb_rw_stop_mask 544 | ||
| 175 | #define REG_WR_ADDR_marb_rw_stop_mask 544 | ||
| 176 | |||
| 177 | /* Register r_stopped, scope marb, type r */ | ||
| 178 | typedef struct { | ||
| 179 | unsigned int dma0 : 1; | ||
| 180 | unsigned int dma1 : 1; | ||
| 181 | unsigned int dma2 : 1; | ||
| 182 | unsigned int dma3 : 1; | ||
| 183 | unsigned int dma4 : 1; | ||
| 184 | unsigned int dma5 : 1; | ||
| 185 | unsigned int dma6 : 1; | ||
| 186 | unsigned int dma7 : 1; | ||
| 187 | unsigned int dma8 : 1; | ||
| 188 | unsigned int dma9 : 1; | ||
| 189 | unsigned int cpui : 1; | ||
| 190 | unsigned int cpud : 1; | ||
| 191 | unsigned int iop : 1; | ||
| 192 | unsigned int slave : 1; | ||
| 193 | unsigned int dummy1 : 18; | ||
| 194 | } reg_marb_r_stopped; | ||
| 195 | #define REG_RD_ADDR_marb_r_stopped 548 | ||
| 196 | |||
| 197 | /* Register rw_no_snoop, scope marb, type rw */ | ||
| 198 | typedef struct { | ||
| 199 | unsigned int dma0 : 1; | ||
| 200 | unsigned int dma1 : 1; | ||
| 201 | unsigned int dma2 : 1; | ||
| 202 | unsigned int dma3 : 1; | ||
| 203 | unsigned int dma4 : 1; | ||
| 204 | unsigned int dma5 : 1; | ||
| 205 | unsigned int dma6 : 1; | ||
| 206 | unsigned int dma7 : 1; | ||
| 207 | unsigned int dma8 : 1; | ||
| 208 | unsigned int dma9 : 1; | ||
| 209 | unsigned int cpui : 1; | ||
| 210 | unsigned int cpud : 1; | ||
| 211 | unsigned int iop : 1; | ||
| 212 | unsigned int slave : 1; | ||
| 213 | unsigned int dummy1 : 18; | ||
| 214 | } reg_marb_rw_no_snoop; | ||
| 215 | #define REG_RD_ADDR_marb_rw_no_snoop 832 | ||
| 216 | #define REG_WR_ADDR_marb_rw_no_snoop 832 | ||
| 217 | |||
| 218 | /* Register rw_no_snoop_rq, scope marb, type rw */ | ||
| 219 | typedef struct { | ||
| 220 | unsigned int dummy1 : 10; | ||
| 221 | unsigned int cpui : 1; | ||
| 222 | unsigned int cpud : 1; | ||
| 223 | unsigned int dummy2 : 20; | ||
| 224 | } reg_marb_rw_no_snoop_rq; | ||
| 225 | #define REG_RD_ADDR_marb_rw_no_snoop_rq 836 | ||
| 226 | #define REG_WR_ADDR_marb_rw_no_snoop_rq 836 | ||
| 227 | |||
| 228 | |||
| 229 | /* Constants */ | ||
| 230 | enum { | ||
| 231 | regk_marb_cpud = 0x0000000b, | ||
| 232 | regk_marb_cpui = 0x0000000a, | ||
| 233 | regk_marb_dma0 = 0x00000000, | ||
| 234 | regk_marb_dma1 = 0x00000001, | ||
| 235 | regk_marb_dma2 = 0x00000002, | ||
| 236 | regk_marb_dma3 = 0x00000003, | ||
| 237 | regk_marb_dma4 = 0x00000004, | ||
| 238 | regk_marb_dma5 = 0x00000005, | ||
| 239 | regk_marb_dma6 = 0x00000006, | ||
| 240 | regk_marb_dma7 = 0x00000007, | ||
| 241 | regk_marb_dma8 = 0x00000008, | ||
| 242 | regk_marb_dma9 = 0x00000009, | ||
| 243 | regk_marb_iop = 0x0000000c, | ||
| 244 | regk_marb_no = 0x00000000, | ||
| 245 | regk_marb_r_stopped_default = 0x00000000, | ||
| 246 | regk_marb_rw_ext_slots_default = 0x00000000, | ||
| 247 | regk_marb_rw_ext_slots_size = 0x00000040, | ||
| 248 | regk_marb_rw_int_slots_default = 0x00000000, | ||
| 249 | regk_marb_rw_int_slots_size = 0x00000040, | ||
| 250 | regk_marb_rw_intr_mask_default = 0x00000000, | ||
| 251 | regk_marb_rw_no_snoop_default = 0x00000000, | ||
| 252 | regk_marb_rw_no_snoop_rq_default = 0x00000000, | ||
| 253 | regk_marb_rw_regs_slots_default = 0x00000000, | ||
| 254 | regk_marb_rw_regs_slots_size = 0x00000004, | ||
| 255 | regk_marb_rw_stop_mask_default = 0x00000000, | ||
| 256 | regk_marb_slave = 0x0000000d, | ||
| 257 | regk_marb_yes = 0x00000001 | ||
| 258 | }; | ||
| 259 | #endif /* __marb_defs_h */ | ||
| 260 | #ifndef __marb_bp_defs_h | ||
| 261 | #define __marb_bp_defs_h | ||
| 262 | |||
| 263 | /* | ||
| 264 | * This file is autogenerated from | ||
| 265 | * file: ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 266 | * id: <not found> | ||
| 267 | * last modfied: Mon Apr 11 16:12:16 2005 | ||
| 268 | * | ||
| 269 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r | ||
| 270 | * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 271 | * Any changes here will be lost. | ||
| 272 | * | ||
| 273 | * -*- buffer-read-only: t -*- | ||
| 274 | */ | ||
| 275 | /* Main access macros */ | ||
| 276 | #ifndef REG_RD | ||
| 277 | #define REG_RD( scope, inst, reg ) \ | ||
| 278 | REG_READ( reg_##scope##_##reg, \ | ||
| 279 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 280 | #endif | ||
| 281 | |||
| 282 | #ifndef REG_WR | ||
| 283 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 284 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 285 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 286 | #endif | ||
| 287 | |||
| 288 | #ifndef REG_RD_VECT | ||
| 289 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 290 | REG_READ( reg_##scope##_##reg, \ | ||
| 291 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 292 | (index) * STRIDE_##scope##_##reg ) | ||
| 293 | #endif | ||
| 294 | |||
| 295 | #ifndef REG_WR_VECT | ||
| 296 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 297 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 298 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 299 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 300 | #endif | ||
| 301 | |||
| 302 | #ifndef REG_RD_INT | ||
| 303 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 304 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 305 | #endif | ||
| 306 | |||
| 307 | #ifndef REG_WR_INT | ||
| 308 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 309 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 310 | #endif | ||
| 311 | |||
| 312 | #ifndef REG_RD_INT_VECT | ||
| 313 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 314 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 315 | (index) * STRIDE_##scope##_##reg ) | ||
| 316 | #endif | ||
| 317 | |||
| 318 | #ifndef REG_WR_INT_VECT | ||
| 319 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 320 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 321 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 322 | #endif | ||
| 323 | |||
| 324 | #ifndef REG_TYPE_CONV | ||
| 325 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 326 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 327 | #endif | ||
| 328 | |||
| 329 | #ifndef reg_page_size | ||
| 330 | #define reg_page_size 8192 | ||
| 331 | #endif | ||
| 332 | |||
| 333 | #ifndef REG_ADDR | ||
| 334 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 335 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 336 | #endif | ||
| 337 | |||
| 338 | #ifndef REG_ADDR_VECT | ||
| 339 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 340 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 341 | (index) * STRIDE_##scope##_##reg ) | ||
| 342 | #endif | ||
| 343 | |||
| 344 | /* C-code for register scope marb_bp */ | ||
| 345 | |||
| 346 | /* Register rw_first_addr, scope marb_bp, type rw */ | ||
| 347 | typedef unsigned int reg_marb_bp_rw_first_addr; | ||
| 348 | #define REG_RD_ADDR_marb_bp_rw_first_addr 0 | ||
| 349 | #define REG_WR_ADDR_marb_bp_rw_first_addr 0 | ||
| 350 | |||
| 351 | /* Register rw_last_addr, scope marb_bp, type rw */ | ||
| 352 | typedef unsigned int reg_marb_bp_rw_last_addr; | ||
| 353 | #define REG_RD_ADDR_marb_bp_rw_last_addr 4 | ||
| 354 | #define REG_WR_ADDR_marb_bp_rw_last_addr 4 | ||
| 355 | |||
| 356 | /* Register rw_op, scope marb_bp, type rw */ | ||
| 357 | typedef struct { | ||
| 358 | unsigned int rd : 1; | ||
| 359 | unsigned int wr : 1; | ||
| 360 | unsigned int rd_excl : 1; | ||
| 361 | unsigned int pri_wr : 1; | ||
| 362 | unsigned int us_rd : 1; | ||
| 363 | unsigned int us_wr : 1; | ||
| 364 | unsigned int us_rd_excl : 1; | ||
| 365 | unsigned int us_pri_wr : 1; | ||
| 366 | unsigned int dummy1 : 24; | ||
| 367 | } reg_marb_bp_rw_op; | ||
| 368 | #define REG_RD_ADDR_marb_bp_rw_op 8 | ||
| 369 | #define REG_WR_ADDR_marb_bp_rw_op 8 | ||
| 370 | |||
| 371 | /* Register rw_clients, scope marb_bp, type rw */ | ||
| 372 | typedef struct { | ||
| 373 | unsigned int dma0 : 1; | ||
| 374 | unsigned int dma1 : 1; | ||
| 375 | unsigned int dma2 : 1; | ||
| 376 | unsigned int dma3 : 1; | ||
| 377 | unsigned int dma4 : 1; | ||
| 378 | unsigned int dma5 : 1; | ||
| 379 | unsigned int dma6 : 1; | ||
| 380 | unsigned int dma7 : 1; | ||
| 381 | unsigned int dma8 : 1; | ||
| 382 | unsigned int dma9 : 1; | ||
| 383 | unsigned int cpui : 1; | ||
| 384 | unsigned int cpud : 1; | ||
| 385 | unsigned int iop : 1; | ||
| 386 | unsigned int slave : 1; | ||
| 387 | unsigned int dummy1 : 18; | ||
| 388 | } reg_marb_bp_rw_clients; | ||
| 389 | #define REG_RD_ADDR_marb_bp_rw_clients 12 | ||
| 390 | #define REG_WR_ADDR_marb_bp_rw_clients 12 | ||
| 391 | |||
| 392 | /* Register rw_options, scope marb_bp, type rw */ | ||
| 393 | typedef struct { | ||
| 394 | unsigned int wrap : 1; | ||
| 395 | unsigned int dummy1 : 31; | ||
| 396 | } reg_marb_bp_rw_options; | ||
| 397 | #define REG_RD_ADDR_marb_bp_rw_options 16 | ||
| 398 | #define REG_WR_ADDR_marb_bp_rw_options 16 | ||
| 399 | |||
| 400 | /* Register r_brk_addr, scope marb_bp, type r */ | ||
| 401 | typedef unsigned int reg_marb_bp_r_brk_addr; | ||
| 402 | #define REG_RD_ADDR_marb_bp_r_brk_addr 20 | ||
| 403 | |||
| 404 | /* Register r_brk_op, scope marb_bp, type r */ | ||
| 405 | typedef struct { | ||
| 406 | unsigned int rd : 1; | ||
| 407 | unsigned int wr : 1; | ||
| 408 | unsigned int rd_excl : 1; | ||
| 409 | unsigned int pri_wr : 1; | ||
| 410 | unsigned int us_rd : 1; | ||
| 411 | unsigned int us_wr : 1; | ||
| 412 | unsigned int us_rd_excl : 1; | ||
| 413 | unsigned int us_pri_wr : 1; | ||
| 414 | unsigned int dummy1 : 24; | ||
| 415 | } reg_marb_bp_r_brk_op; | ||
| 416 | #define REG_RD_ADDR_marb_bp_r_brk_op 24 | ||
| 417 | |||
| 418 | /* Register r_brk_clients, scope marb_bp, type r */ | ||
| 419 | typedef struct { | ||
| 420 | unsigned int dma0 : 1; | ||
| 421 | unsigned int dma1 : 1; | ||
| 422 | unsigned int dma2 : 1; | ||
| 423 | unsigned int dma3 : 1; | ||
| 424 | unsigned int dma4 : 1; | ||
| 425 | unsigned int dma5 : 1; | ||
| 426 | unsigned int dma6 : 1; | ||
| 427 | unsigned int dma7 : 1; | ||
| 428 | unsigned int dma8 : 1; | ||
| 429 | unsigned int dma9 : 1; | ||
| 430 | unsigned int cpui : 1; | ||
| 431 | unsigned int cpud : 1; | ||
| 432 | unsigned int iop : 1; | ||
| 433 | unsigned int slave : 1; | ||
| 434 | unsigned int dummy1 : 18; | ||
| 435 | } reg_marb_bp_r_brk_clients; | ||
| 436 | #define REG_RD_ADDR_marb_bp_r_brk_clients 28 | ||
| 437 | |||
| 438 | /* Register r_brk_first_client, scope marb_bp, type r */ | ||
| 439 | typedef struct { | ||
| 440 | unsigned int dma0 : 1; | ||
| 441 | unsigned int dma1 : 1; | ||
| 442 | unsigned int dma2 : 1; | ||
| 443 | unsigned int dma3 : 1; | ||
| 444 | unsigned int dma4 : 1; | ||
| 445 | unsigned int dma5 : 1; | ||
| 446 | unsigned int dma6 : 1; | ||
| 447 | unsigned int dma7 : 1; | ||
| 448 | unsigned int dma8 : 1; | ||
| 449 | unsigned int dma9 : 1; | ||
| 450 | unsigned int cpui : 1; | ||
| 451 | unsigned int cpud : 1; | ||
| 452 | unsigned int iop : 1; | ||
| 453 | unsigned int slave : 1; | ||
| 454 | unsigned int dummy1 : 18; | ||
| 455 | } reg_marb_bp_r_brk_first_client; | ||
| 456 | #define REG_RD_ADDR_marb_bp_r_brk_first_client 32 | ||
| 457 | |||
| 458 | /* Register r_brk_size, scope marb_bp, type r */ | ||
| 459 | typedef unsigned int reg_marb_bp_r_brk_size; | ||
| 460 | #define REG_RD_ADDR_marb_bp_r_brk_size 36 | ||
| 461 | |||
| 462 | /* Register rw_ack, scope marb_bp, type rw */ | ||
| 463 | typedef unsigned int reg_marb_bp_rw_ack; | ||
| 464 | #define REG_RD_ADDR_marb_bp_rw_ack 40 | ||
| 465 | #define REG_WR_ADDR_marb_bp_rw_ack 40 | ||
| 466 | |||
| 467 | |||
| 468 | /* Constants */ | ||
| 469 | enum { | ||
| 470 | regk_marb_bp_no = 0x00000000, | ||
| 471 | regk_marb_bp_rw_op_default = 0x00000000, | ||
| 472 | regk_marb_bp_rw_options_default = 0x00000000, | ||
| 473 | regk_marb_bp_yes = 0x00000001 | ||
| 474 | }; | ||
| 475 | #endif /* __marb_bp_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h new file mode 100644 index 000000000000..751eab5f191c --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/pinmux_defs.h | |||
| @@ -0,0 +1,357 @@ | |||
| 1 | #ifndef __pinmux_defs_h | ||
| 2 | #define __pinmux_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 7 | * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:11 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r | ||
| 11 | * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope pinmux */ | ||
| 86 | |||
| 87 | /* Register rw_pa, scope pinmux, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int pa0 : 1; | ||
| 90 | unsigned int pa1 : 1; | ||
| 91 | unsigned int pa2 : 1; | ||
| 92 | unsigned int pa3 : 1; | ||
| 93 | unsigned int pa4 : 1; | ||
| 94 | unsigned int pa5 : 1; | ||
| 95 | unsigned int pa6 : 1; | ||
| 96 | unsigned int pa7 : 1; | ||
| 97 | unsigned int csp2_n : 1; | ||
| 98 | unsigned int csp3_n : 1; | ||
| 99 | unsigned int csp5_n : 1; | ||
| 100 | unsigned int csp6_n : 1; | ||
| 101 | unsigned int hsh4 : 1; | ||
| 102 | unsigned int hsh5 : 1; | ||
| 103 | unsigned int hsh6 : 1; | ||
| 104 | unsigned int hsh7 : 1; | ||
| 105 | unsigned int dummy1 : 16; | ||
| 106 | } reg_pinmux_rw_pa; | ||
| 107 | #define REG_RD_ADDR_pinmux_rw_pa 0 | ||
| 108 | #define REG_WR_ADDR_pinmux_rw_pa 0 | ||
| 109 | |||
| 110 | /* Register rw_hwprot, scope pinmux, type rw */ | ||
| 111 | typedef struct { | ||
| 112 | unsigned int ser1 : 1; | ||
| 113 | unsigned int ser2 : 1; | ||
| 114 | unsigned int ser3 : 1; | ||
| 115 | unsigned int sser0 : 1; | ||
| 116 | unsigned int sser1 : 1; | ||
| 117 | unsigned int ata0 : 1; | ||
| 118 | unsigned int ata1 : 1; | ||
| 119 | unsigned int ata2 : 1; | ||
| 120 | unsigned int ata3 : 1; | ||
| 121 | unsigned int ata : 1; | ||
| 122 | unsigned int eth1 : 1; | ||
| 123 | unsigned int eth1_mgm : 1; | ||
| 124 | unsigned int timer : 1; | ||
| 125 | unsigned int p21 : 1; | ||
| 126 | unsigned int dummy1 : 18; | ||
| 127 | } reg_pinmux_rw_hwprot; | ||
| 128 | #define REG_RD_ADDR_pinmux_rw_hwprot 4 | ||
| 129 | #define REG_WR_ADDR_pinmux_rw_hwprot 4 | ||
| 130 | |||
| 131 | /* Register rw_pb_gio, scope pinmux, type rw */ | ||
| 132 | typedef struct { | ||
| 133 | unsigned int pb0 : 1; | ||
| 134 | unsigned int pb1 : 1; | ||
| 135 | unsigned int pb2 : 1; | ||
| 136 | unsigned int pb3 : 1; | ||
| 137 | unsigned int pb4 : 1; | ||
| 138 | unsigned int pb5 : 1; | ||
| 139 | unsigned int pb6 : 1; | ||
| 140 | unsigned int pb7 : 1; | ||
| 141 | unsigned int pb8 : 1; | ||
| 142 | unsigned int pb9 : 1; | ||
| 143 | unsigned int pb10 : 1; | ||
| 144 | unsigned int pb11 : 1; | ||
| 145 | unsigned int pb12 : 1; | ||
| 146 | unsigned int pb13 : 1; | ||
| 147 | unsigned int pb14 : 1; | ||
| 148 | unsigned int pb15 : 1; | ||
| 149 | unsigned int pb16 : 1; | ||
| 150 | unsigned int pb17 : 1; | ||
| 151 | unsigned int dummy1 : 14; | ||
| 152 | } reg_pinmux_rw_pb_gio; | ||
| 153 | #define REG_RD_ADDR_pinmux_rw_pb_gio 8 | ||
| 154 | #define REG_WR_ADDR_pinmux_rw_pb_gio 8 | ||
| 155 | |||
| 156 | /* Register rw_pb_iop, scope pinmux, type rw */ | ||
| 157 | typedef struct { | ||
| 158 | unsigned int pb0 : 1; | ||
| 159 | unsigned int pb1 : 1; | ||
| 160 | unsigned int pb2 : 1; | ||
| 161 | unsigned int pb3 : 1; | ||
| 162 | unsigned int pb4 : 1; | ||
| 163 | unsigned int pb5 : 1; | ||
| 164 | unsigned int pb6 : 1; | ||
| 165 | unsigned int pb7 : 1; | ||
| 166 | unsigned int pb8 : 1; | ||
| 167 | unsigned int pb9 : 1; | ||
| 168 | unsigned int pb10 : 1; | ||
| 169 | unsigned int pb11 : 1; | ||
| 170 | unsigned int pb12 : 1; | ||
| 171 | unsigned int pb13 : 1; | ||
| 172 | unsigned int pb14 : 1; | ||
| 173 | unsigned int pb15 : 1; | ||
| 174 | unsigned int pb16 : 1; | ||
| 175 | unsigned int pb17 : 1; | ||
| 176 | unsigned int dummy1 : 14; | ||
| 177 | } reg_pinmux_rw_pb_iop; | ||
| 178 | #define REG_RD_ADDR_pinmux_rw_pb_iop 12 | ||
| 179 | #define REG_WR_ADDR_pinmux_rw_pb_iop 12 | ||
| 180 | |||
| 181 | /* Register rw_pc_gio, scope pinmux, type rw */ | ||
| 182 | typedef struct { | ||
| 183 | unsigned int pc0 : 1; | ||
| 184 | unsigned int pc1 : 1; | ||
| 185 | unsigned int pc2 : 1; | ||
| 186 | unsigned int pc3 : 1; | ||
| 187 | unsigned int pc4 : 1; | ||
| 188 | unsigned int pc5 : 1; | ||
| 189 | unsigned int pc6 : 1; | ||
| 190 | unsigned int pc7 : 1; | ||
| 191 | unsigned int pc8 : 1; | ||
| 192 | unsigned int pc9 : 1; | ||
| 193 | unsigned int pc10 : 1; | ||
| 194 | unsigned int pc11 : 1; | ||
| 195 | unsigned int pc12 : 1; | ||
| 196 | unsigned int pc13 : 1; | ||
| 197 | unsigned int pc14 : 1; | ||
| 198 | unsigned int pc15 : 1; | ||
| 199 | unsigned int pc16 : 1; | ||
| 200 | unsigned int pc17 : 1; | ||
| 201 | unsigned int dummy1 : 14; | ||
| 202 | } reg_pinmux_rw_pc_gio; | ||
| 203 | #define REG_RD_ADDR_pinmux_rw_pc_gio 16 | ||
| 204 | #define REG_WR_ADDR_pinmux_rw_pc_gio 16 | ||
| 205 | |||
| 206 | /* Register rw_pc_iop, scope pinmux, type rw */ | ||
| 207 | typedef struct { | ||
| 208 | unsigned int pc0 : 1; | ||
| 209 | unsigned int pc1 : 1; | ||
| 210 | unsigned int pc2 : 1; | ||
| 211 | unsigned int pc3 : 1; | ||
| 212 | unsigned int pc4 : 1; | ||
| 213 | unsigned int pc5 : 1; | ||
| 214 | unsigned int pc6 : 1; | ||
| 215 | unsigned int pc7 : 1; | ||
| 216 | unsigned int pc8 : 1; | ||
| 217 | unsigned int pc9 : 1; | ||
| 218 | unsigned int pc10 : 1; | ||
| 219 | unsigned int pc11 : 1; | ||
| 220 | unsigned int pc12 : 1; | ||
| 221 | unsigned int pc13 : 1; | ||
| 222 | unsigned int pc14 : 1; | ||
| 223 | unsigned int pc15 : 1; | ||
| 224 | unsigned int pc16 : 1; | ||
| 225 | unsigned int pc17 : 1; | ||
| 226 | unsigned int dummy1 : 14; | ||
| 227 | } reg_pinmux_rw_pc_iop; | ||
| 228 | #define REG_RD_ADDR_pinmux_rw_pc_iop 20 | ||
| 229 | #define REG_WR_ADDR_pinmux_rw_pc_iop 20 | ||
| 230 | |||
| 231 | /* Register rw_pd_gio, scope pinmux, type rw */ | ||
| 232 | typedef struct { | ||
| 233 | unsigned int pd0 : 1; | ||
| 234 | unsigned int pd1 : 1; | ||
| 235 | unsigned int pd2 : 1; | ||
| 236 | unsigned int pd3 : 1; | ||
| 237 | unsigned int pd4 : 1; | ||
| 238 | unsigned int pd5 : 1; | ||
| 239 | unsigned int pd6 : 1; | ||
| 240 | unsigned int pd7 : 1; | ||
| 241 | unsigned int pd8 : 1; | ||
| 242 | unsigned int pd9 : 1; | ||
| 243 | unsigned int pd10 : 1; | ||
| 244 | unsigned int pd11 : 1; | ||
| 245 | unsigned int pd12 : 1; | ||
| 246 | unsigned int pd13 : 1; | ||
| 247 | unsigned int pd14 : 1; | ||
| 248 | unsigned int pd15 : 1; | ||
| 249 | unsigned int pd16 : 1; | ||
| 250 | unsigned int pd17 : 1; | ||
| 251 | unsigned int dummy1 : 14; | ||
| 252 | } reg_pinmux_rw_pd_gio; | ||
| 253 | #define REG_RD_ADDR_pinmux_rw_pd_gio 24 | ||
| 254 | #define REG_WR_ADDR_pinmux_rw_pd_gio 24 | ||
| 255 | |||
| 256 | /* Register rw_pd_iop, scope pinmux, type rw */ | ||
| 257 | typedef struct { | ||
| 258 | unsigned int pd0 : 1; | ||
| 259 | unsigned int pd1 : 1; | ||
| 260 | unsigned int pd2 : 1; | ||
| 261 | unsigned int pd3 : 1; | ||
| 262 | unsigned int pd4 : 1; | ||
| 263 | unsigned int pd5 : 1; | ||
| 264 | unsigned int pd6 : 1; | ||
| 265 | unsigned int pd7 : 1; | ||
| 266 | unsigned int pd8 : 1; | ||
| 267 | unsigned int pd9 : 1; | ||
| 268 | unsigned int pd10 : 1; | ||
| 269 | unsigned int pd11 : 1; | ||
| 270 | unsigned int pd12 : 1; | ||
| 271 | unsigned int pd13 : 1; | ||
| 272 | unsigned int pd14 : 1; | ||
| 273 | unsigned int pd15 : 1; | ||
| 274 | unsigned int pd16 : 1; | ||
| 275 | unsigned int pd17 : 1; | ||
| 276 | unsigned int dummy1 : 14; | ||
| 277 | } reg_pinmux_rw_pd_iop; | ||
| 278 | #define REG_RD_ADDR_pinmux_rw_pd_iop 28 | ||
| 279 | #define REG_WR_ADDR_pinmux_rw_pd_iop 28 | ||
| 280 | |||
| 281 | /* Register rw_pe_gio, scope pinmux, type rw */ | ||
| 282 | typedef struct { | ||
| 283 | unsigned int pe0 : 1; | ||
| 284 | unsigned int pe1 : 1; | ||
| 285 | unsigned int pe2 : 1; | ||
| 286 | unsigned int pe3 : 1; | ||
| 287 | unsigned int pe4 : 1; | ||
| 288 | unsigned int pe5 : 1; | ||
| 289 | unsigned int pe6 : 1; | ||
| 290 | unsigned int pe7 : 1; | ||
| 291 | unsigned int pe8 : 1; | ||
| 292 | unsigned int pe9 : 1; | ||
| 293 | unsigned int pe10 : 1; | ||
| 294 | unsigned int pe11 : 1; | ||
| 295 | unsigned int pe12 : 1; | ||
| 296 | unsigned int pe13 : 1; | ||
| 297 | unsigned int pe14 : 1; | ||
| 298 | unsigned int pe15 : 1; | ||
| 299 | unsigned int pe16 : 1; | ||
| 300 | unsigned int pe17 : 1; | ||
| 301 | unsigned int dummy1 : 14; | ||
| 302 | } reg_pinmux_rw_pe_gio; | ||
| 303 | #define REG_RD_ADDR_pinmux_rw_pe_gio 32 | ||
| 304 | #define REG_WR_ADDR_pinmux_rw_pe_gio 32 | ||
| 305 | |||
| 306 | /* Register rw_pe_iop, scope pinmux, type rw */ | ||
| 307 | typedef struct { | ||
| 308 | unsigned int pe0 : 1; | ||
| 309 | unsigned int pe1 : 1; | ||
| 310 | unsigned int pe2 : 1; | ||
| 311 | unsigned int pe3 : 1; | ||
| 312 | unsigned int pe4 : 1; | ||
| 313 | unsigned int pe5 : 1; | ||
| 314 | unsigned int pe6 : 1; | ||
| 315 | unsigned int pe7 : 1; | ||
| 316 | unsigned int pe8 : 1; | ||
| 317 | unsigned int pe9 : 1; | ||
| 318 | unsigned int pe10 : 1; | ||
| 319 | unsigned int pe11 : 1; | ||
| 320 | unsigned int pe12 : 1; | ||
| 321 | unsigned int pe13 : 1; | ||
| 322 | unsigned int pe14 : 1; | ||
| 323 | unsigned int pe15 : 1; | ||
| 324 | unsigned int pe16 : 1; | ||
| 325 | unsigned int pe17 : 1; | ||
| 326 | unsigned int dummy1 : 14; | ||
| 327 | } reg_pinmux_rw_pe_iop; | ||
| 328 | #define REG_RD_ADDR_pinmux_rw_pe_iop 36 | ||
| 329 | #define REG_WR_ADDR_pinmux_rw_pe_iop 36 | ||
| 330 | |||
| 331 | /* Register rw_usb_phy, scope pinmux, type rw */ | ||
| 332 | typedef struct { | ||
| 333 | unsigned int en_usb0 : 1; | ||
| 334 | unsigned int en_usb1 : 1; | ||
| 335 | unsigned int dummy1 : 30; | ||
| 336 | } reg_pinmux_rw_usb_phy; | ||
| 337 | #define REG_RD_ADDR_pinmux_rw_usb_phy 40 | ||
| 338 | #define REG_WR_ADDR_pinmux_rw_usb_phy 40 | ||
| 339 | |||
| 340 | |||
| 341 | /* Constants */ | ||
| 342 | enum { | ||
| 343 | regk_pinmux_no = 0x00000000, | ||
| 344 | regk_pinmux_rw_hwprot_default = 0x00000000, | ||
| 345 | regk_pinmux_rw_pa_default = 0x00000000, | ||
| 346 | regk_pinmux_rw_pb_gio_default = 0x00000000, | ||
| 347 | regk_pinmux_rw_pb_iop_default = 0x00000000, | ||
| 348 | regk_pinmux_rw_pc_gio_default = 0x00000000, | ||
| 349 | regk_pinmux_rw_pc_iop_default = 0x00000000, | ||
| 350 | regk_pinmux_rw_pd_gio_default = 0x00000000, | ||
| 351 | regk_pinmux_rw_pd_iop_default = 0x00000000, | ||
| 352 | regk_pinmux_rw_pe_gio_default = 0x00000000, | ||
| 353 | regk_pinmux_rw_pe_iop_default = 0x00000000, | ||
| 354 | regk_pinmux_rw_usb_phy_default = 0x00000000, | ||
| 355 | regk_pinmux_yes = 0x00000001 | ||
| 356 | }; | ||
| 357 | #endif /* __pinmux_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/reg_map.h b/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h index e31502838ec6..4146973a58b3 100644 --- a/include/asm-cris/arch-v32/hwregs/reg_map.h +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/reg_map.h | |||
| @@ -4,17 +4,17 @@ | |||
| 4 | /* | 4 | /* |
| 5 | * This file is autogenerated from | 5 | * This file is autogenerated from |
| 6 | * file: ../../mod/fakereg.rmap | 6 | * file: ../../mod/fakereg.rmap |
| 7 | * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp | 7 | * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp |
| 8 | * last modified: Wed Feb 11 20:53:25 2004 | 8 | * last modified: Wed Feb 11 20:53:25 2004 |
| 9 | * file: ../../rtl/global.rmap | 9 | * file: ../../rtl/global.rmap |
| 10 | * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp | 10 | * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp |
| 11 | * last modified: Mon Aug 18 17:08:23 2003 | 11 | * last modified: Mon Aug 18 17:08:23 2003 |
| 12 | * file: ../../mod/modreg.rmap | 12 | * file: ../../mod/modreg.rmap |
| 13 | * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp | 13 | * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp |
| 14 | * last modified: Fri Feb 20 16:40:04 2004 | 14 | * last modified: Fri Feb 20 16:40:04 2004 |
| 15 | * | 15 | * |
| 16 | * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap | 16 | * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap |
| 17 | * id: $Id: reg_map.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ | 17 | * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ |
| 18 | * Any changes here will be lost. | 18 | * Any changes here will be lost. |
| 19 | * | 19 | * |
| 20 | * -*- buffer-read-only: t -*- | 20 | * -*- buffer-read-only: t -*- |
| @@ -97,6 +97,7 @@ typedef enum { | |||
| 97 | regi_strcop = 0xb0030000, | 97 | regi_strcop = 0xb0030000, |
| 98 | regi_strmux = 0xb003a000, | 98 | regi_strmux = 0xb003a000, |
| 99 | regi_timer = 0xb001e000, | 99 | regi_timer = 0xb001e000, |
| 100 | regi_timer0 = 0xb001e000, | ||
| 100 | regi_timer2 = 0xb005e000, | 101 | regi_timer2 = 0xb005e000, |
| 101 | regi_trace = 0xb0040000, | 102 | regi_trace = 0xb0040000, |
| 102 | } reg_scope_instances; | 103 | } reg_scope_instances; |
diff --git a/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h new file mode 100644 index 000000000000..cbfaa867829e --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/strmux_defs.h | |||
| @@ -0,0 +1,127 @@ | |||
| 1 | #ifndef __strmux_defs_h | ||
| 2 | #define __strmux_defs_h | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is autogenerated from | ||
| 6 | * file: ../../inst/strmux/rtl/guinness/strmux_regs.r | ||
| 7 | * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp | ||
| 8 | * last modfied: Mon Apr 11 16:09:43 2005 | ||
| 9 | * | ||
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r | ||
| 11 | * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | ||
| 12 | * Any changes here will be lost. | ||
| 13 | * | ||
| 14 | * -*- buffer-read-only: t -*- | ||
| 15 | */ | ||
| 16 | /* Main access macros */ | ||
| 17 | #ifndef REG_RD | ||
| 18 | #define REG_RD( scope, inst, reg ) \ | ||
| 19 | REG_READ( reg_##scope##_##reg, \ | ||
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef REG_WR | ||
| 24 | #define REG_WR( scope, inst, reg, val ) \ | ||
| 25 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifndef REG_RD_VECT | ||
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ | ||
| 31 | REG_READ( reg_##scope##_##reg, \ | ||
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 33 | (index) * STRIDE_##scope##_##reg ) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #ifndef REG_WR_VECT | ||
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | ||
| 38 | REG_WRITE( reg_##scope##_##reg, \ | ||
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #ifndef REG_RD_INT | ||
| 44 | #define REG_RD_INT( scope, inst, reg ) \ | ||
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #ifndef REG_WR_INT | ||
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ | ||
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef REG_RD_INT_VECT | ||
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | ||
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 56 | (index) * STRIDE_##scope##_##reg ) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifndef REG_WR_INT_VECT | ||
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | ||
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | ||
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #ifndef REG_TYPE_CONV | ||
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ | ||
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #ifndef reg_page_size | ||
| 71 | #define reg_page_size 8192 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef REG_ADDR | ||
| 75 | #define REG_ADDR( scope, inst, reg ) \ | ||
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifndef REG_ADDR_VECT | ||
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | ||
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | ||
| 82 | (index) * STRIDE_##scope##_##reg ) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | /* C-code for register scope strmux */ | ||
| 86 | |||
| 87 | /* Register rw_cfg, scope strmux, type rw */ | ||
| 88 | typedef struct { | ||
| 89 | unsigned int dma0 : 3; | ||
| 90 | unsigned int dma1 : 3; | ||
| 91 | unsigned int dma2 : 3; | ||
| 92 | unsigned int dma3 : 3; | ||
| 93 | unsigned int dma4 : 3; | ||
| 94 | unsigned int dma5 : 3; | ||
| 95 | unsigned int dma6 : 3; | ||
| 96 | unsigned int dma7 : 3; | ||
| 97 | unsigned int dma8 : 3; | ||
| 98 | unsigned int dma9 : 3; | ||
| 99 | unsigned int dummy1 : 2; | ||
| 100 | } reg_strmux_rw_cfg; | ||
| 101 | #define REG_RD_ADDR_strmux_rw_cfg 0 | ||
| 102 | #define REG_WR_ADDR_strmux_rw_cfg 0 | ||
| 103 | |||
| 104 | |||
| 105 | /* Constants */ | ||
| 106 | enum { | ||
| 107 | regk_strmux_ata = 0x00000003, | ||
| 108 | regk_strmux_eth0 = 0x00000001, | ||
| 109 | regk_strmux_eth1 = 0x00000004, | ||
| 110 | regk_strmux_ext0 = 0x00000001, | ||
| 111 | regk_strmux_ext1 = 0x00000001, | ||
| 112 | regk_strmux_ext2 = 0x00000001, | ||
| 113 | regk_strmux_ext3 = 0x00000001, | ||
| 114 | regk_strmux_iop0 = 0x00000002, | ||
| 115 | regk_strmux_iop1 = 0x00000001, | ||
| 116 | regk_strmux_off = 0x00000000, | ||
| 117 | regk_strmux_p21 = 0x00000004, | ||
| 118 | regk_strmux_rw_cfg_default = 0x00000000, | ||
| 119 | regk_strmux_ser0 = 0x00000002, | ||
| 120 | regk_strmux_ser1 = 0x00000002, | ||
| 121 | regk_strmux_ser2 = 0x00000004, | ||
| 122 | regk_strmux_ser3 = 0x00000003, | ||
| 123 | regk_strmux_sser0 = 0x00000003, | ||
| 124 | regk_strmux_sser1 = 0x00000003, | ||
| 125 | regk_strmux_strcop = 0x00000002 | ||
| 126 | }; | ||
| 127 | #endif /* __strmux_defs_h */ | ||
diff --git a/include/asm-cris/arch-v32/hwregs/timer_defs.h b/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h index 20c8c89ec076..76bcc591921d 100644 --- a/include/asm-cris/arch-v32/hwregs/timer_defs.h +++ b/include/asm-cris/arch-v32/mach-fs/hwregs/timer_defs.h | |||
| @@ -4,11 +4,11 @@ | |||
| 4 | /* | 4 | /* |
| 5 | * This file is autogenerated from | 5 | * This file is autogenerated from |
| 6 | * file: ../../inst/timer/rtl/timer_regs.r | 6 | * file: ../../inst/timer/rtl/timer_regs.r |
| 7 | * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp | 7 | * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp |
| 8 | * last modfied: Mon Apr 11 16:09:53 2005 | 8 | * last modfied: Mon Apr 11 16:09:53 2005 |
| 9 | * | 9 | * |
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r | 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r |
| 11 | * id: $Id: timer_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ | 11 | * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ |
| 12 | * Any changes here will be lost. | 12 | * Any changes here will be lost. |
| 13 | * | 13 | * |
| 14 | * -*- buffer-read-only: t -*- | 14 | * -*- buffer-read-only: t -*- |
diff --git a/include/asm-cris/arch-v32/mach-fs/pinmux.h b/include/asm-cris/arch-v32/mach-fs/pinmux.h new file mode 100644 index 000000000000..c2b3036779df --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/pinmux.h | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_PINMUX_H | ||
| 2 | #define _ASM_CRIS_ARCH_PINMUX_H | ||
| 3 | |||
| 4 | #define PORT_B 0 | ||
| 5 | #define PORT_C 1 | ||
| 6 | #define PORT_D 2 | ||
| 7 | #define PORT_E 3 | ||
| 8 | |||
| 9 | enum pin_mode { | ||
| 10 | pinmux_none = 0, | ||
| 11 | pinmux_fixed, | ||
| 12 | pinmux_gpio, | ||
| 13 | pinmux_iop | ||
| 14 | }; | ||
| 15 | |||
| 16 | enum fixed_function { | ||
| 17 | pinmux_ser1, | ||
| 18 | pinmux_ser2, | ||
| 19 | pinmux_ser3, | ||
| 20 | pinmux_sser0, | ||
| 21 | pinmux_sser1, | ||
| 22 | pinmux_ata0, | ||
| 23 | pinmux_ata1, | ||
| 24 | pinmux_ata2, | ||
| 25 | pinmux_ata3, | ||
| 26 | pinmux_ata, | ||
| 27 | pinmux_eth1, | ||
| 28 | pinmux_timer | ||
| 29 | }; | ||
| 30 | |||
| 31 | int crisv32_pinmux_init(void); | ||
| 32 | int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); | ||
| 33 | int crisv32_pinmux_alloc_fixed(enum fixed_function function); | ||
| 34 | int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); | ||
| 35 | int crisv32_pinmux_dealloc_fixed(enum fixed_function function); | ||
| 36 | void crisv32_pinmux_dump(void); | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-cris/arch-v32/mach-fs/startup.inc b/include/asm-cris/arch-v32/mach-fs/startup.inc new file mode 100644 index 000000000000..4a10ccbd6cc1 --- /dev/null +++ b/include/asm-cris/arch-v32/mach-fs/startup.inc | |||
| @@ -0,0 +1,77 @@ | |||
| 1 | #include <hwregs/asm/reg_map_asm.h> | ||
| 2 | #include <hwregs/asm/bif_core_defs_asm.h> | ||
| 3 | #include <hwregs/asm/gio_defs_asm.h> | ||
| 4 | #include <hwregs/asm/config_defs_asm.h> | ||
| 5 | |||
| 6 | .macro GIO_INIT | ||
| 7 | move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 | ||
| 8 | move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 | ||
| 9 | move.d $r0, [$r1] | ||
| 10 | |||
| 11 | move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 | ||
| 12 | move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 | ||
| 13 | move.d $r0, [$r1] | ||
| 14 | |||
| 15 | move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 | ||
| 16 | move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 | ||
| 17 | move.d $r0, [$r1] | ||
| 18 | |||
| 19 | move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 | ||
| 20 | move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 | ||
| 21 | move.d $r0, [$r1] | ||
| 22 | |||
| 23 | move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 | ||
| 24 | move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 | ||
| 25 | move.d $r0, [$r1] | ||
| 26 | |||
| 27 | move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 | ||
| 28 | move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 | ||
| 29 | move.d $r0, [$r1] | ||
| 30 | |||
| 31 | move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0 | ||
| 32 | move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1 | ||
| 33 | move.d $r0, [$r1] | ||
| 34 | |||
| 35 | move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0 | ||
| 36 | move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1 | ||
| 37 | move.d $r0, [$r1] | ||
| 38 | |||
| 39 | move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0 | ||
| 40 | move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1 | ||
| 41 | move.d $r0, [$r1] | ||
| 42 | |||
| 43 | move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0 | ||
| 44 | move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1 | ||
| 45 | move.d $r0, [$r1] | ||
| 46 | .endm | ||
| 47 | |||
| 48 | .macro START_CLOCKS | ||
| 49 | move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 | ||
| 50 | move.d [$r1], $r0 | ||
| 51 | or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ | ||
| 52 | REG_STATE(config, rw_clk_ctrl, bif, yes) | \ | ||
| 53 | REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 | ||
| 54 | move.d $r0, [$r1] | ||
| 55 | .endm | ||
| 56 | |||
| 57 | .macro SETUP_WAIT_STATES | ||
| 58 | ;; Set up waitstates etc | ||
| 59 | move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 | ||
| 60 | move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 | ||
| 61 | move.d $r1, [$r0] | ||
| 62 | move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 | ||
| 63 | move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 | ||
| 64 | move.d $r1, [$r0] | ||
| 65 | move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 | ||
| 66 | move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 | ||
| 67 | move.d $r1, [$r0] | ||
| 68 | move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 | ||
| 69 | move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 | ||
| 70 | move.d $r1, [$r0] | ||
| 71 | #ifdef CONFIG_ETRAX_VCS_SIM | ||
| 72 | ;; Set up minimal flash waitstates | ||
| 73 | move.d 0, $r10 | ||
| 74 | move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11 | ||
| 75 | move.d $r10, [$r11] | ||
| 76 | #endif | ||
| 77 | .endm | ||
diff --git a/include/asm-cris/arch-v32/offset.h b/include/asm-cris/arch-v32/offset.h index 597419b033f9..4442c4bd52f4 100644 --- a/include/asm-cris/arch-v32/offset.h +++ b/include/asm-cris/arch-v32/offset.h | |||
| @@ -27,7 +27,7 @@ | |||
| 27 | #define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ | 27 | #define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ |
| 28 | #define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ | 28 | #define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ |
| 29 | 29 | ||
| 30 | #define TASK_pid 149 /* offsetof(struct task_struct, pid) */ | 30 | #define TASK_pid 151 /* offsetof(struct task_struct, pid) */ |
| 31 | 31 | ||
| 32 | #define LCLONE_VM 256 /* CLONE_VM */ | 32 | #define LCLONE_VM 256 /* CLONE_VM */ |
| 33 | #define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ | 33 | #define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ |
diff --git a/include/asm-cris/arch-v32/page.h b/include/asm-cris/arch-v32/page.h index fa454fe12425..20f1b4806bfe 100644 --- a/include/asm-cris/arch-v32/page.h +++ b/include/asm-cris/arch-v32/page.h | |||
| @@ -7,11 +7,11 @@ | |||
| 7 | #define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ | 7 | #define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ |
| 8 | 8 | ||
| 9 | /* | 9 | /* |
| 10 | * Macros to convert between physical and virtual addresses. By stripiing a | 10 | * Macros to convert between physical and virtual addresses. By stripping a |
| 11 | * selected bit it's possible to convert between KSEG_x and 0x40000000 where the | 11 | * selected bit it's possible to convert between KSEG_x and 0x40000000 where the |
| 12 | * DRAM really resides. DRAM is virtually at 0xc. | 12 | * DRAM really resides. DRAM is virtually at 0xc. |
| 13 | */ | 13 | */ |
| 14 | #ifndef CONFIG_ETRAXFS_SIM | 14 | #ifndef CONFIG_ETRAX_VCS_SIM |
| 15 | #define __pa(x) ((unsigned long)(x) & 0x7fffffff) | 15 | #define __pa(x) ((unsigned long)(x) & 0x7fffffff) |
| 16 | #define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) | 16 | #define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) |
| 17 | #else | 17 | #else |
diff --git a/include/asm-cris/arch-v32/pinmux.h b/include/asm-cris/arch-v32/pinmux.h index a66dc9970919..bb09bce42e7a 100644 --- a/include/asm-cris/arch-v32/pinmux.h +++ b/include/asm-cris/arch-v32/pinmux.h | |||
| @@ -34,6 +34,7 @@ int crisv32_pinmux_init(void); | |||
| 34 | int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); | 34 | int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); |
| 35 | int crisv32_pinmux_alloc_fixed(enum fixed_function function); | 35 | int crisv32_pinmux_alloc_fixed(enum fixed_function function); |
| 36 | int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); | 36 | int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); |
| 37 | int crisv32_pinmux_dealloc_fixed(enum fixed_function function); | ||
| 37 | void crisv32_pinmux_dump(void); | 38 | void crisv32_pinmux_dump(void); |
| 38 | 39 | ||
| 39 | #endif | 40 | #endif |
diff --git a/include/asm-cris/arch-v32/processor.h b/include/asm-cris/arch-v32/processor.h index 5553b0cd02bf..f80b47790ca6 100644 --- a/include/asm-cris/arch-v32/processor.h +++ b/include/asm-cris/arch-v32/processor.h | |||
| @@ -23,7 +23,7 @@ struct thread_struct { | |||
| 23 | * User-space process size. This is hardcoded into a few places, so don't | 23 | * User-space process size. This is hardcoded into a few places, so don't |
| 24 | * changed it unless everything's clear! | 24 | * changed it unless everything's clear! |
| 25 | */ | 25 | */ |
| 26 | #ifndef CONFIG_ETRAXFS_SIM | 26 | #ifndef CONFIG_ETRAX_VCS_SIM |
| 27 | #define TASK_SIZE (0xB0000000UL) | 27 | #define TASK_SIZE (0xB0000000UL) |
| 28 | #else | 28 | #else |
| 29 | #define TASK_SIZE (0xA0000000UL) | 29 | #define TASK_SIZE (0xA0000000UL) |
diff --git a/include/asm-cris/arch-v32/spinlock.h b/include/asm-cris/arch-v32/spinlock.h index 5f43df0a5fb4..0d5709b983a1 100644 --- a/include/asm-cris/arch-v32/spinlock.h +++ b/include/asm-cris/arch-v32/spinlock.h | |||
| @@ -1,40 +1,47 @@ | |||
| 1 | #ifndef __ASM_ARCH_SPINLOCK_H | 1 | #ifndef __ASM_ARCH_SPINLOCK_H |
| 2 | #define __ASM_ARCH_SPINLOCK_H | 2 | #define __ASM_ARCH_SPINLOCK_H |
| 3 | 3 | ||
| 4 | #include <asm/system.h> | 4 | #include <linux/spinlock_types.h> |
| 5 | 5 | ||
| 6 | #define RW_LOCK_BIAS 0x01000000 | 6 | #define RW_LOCK_BIAS 0x01000000 |
| 7 | #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } | ||
| 8 | #define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0) | ||
| 9 | |||
| 10 | #define spin_is_locked(x) (*(volatile signed char *)(&(x)->lock) <= 0) | ||
| 11 | #define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) | ||
| 12 | 7 | ||
| 13 | extern void cris_spin_unlock(void *l, int val); | 8 | extern void cris_spin_unlock(void *l, int val); |
| 14 | extern void cris_spin_lock(void *l); | 9 | extern void cris_spin_lock(void *l); |
| 15 | extern int cris_spin_trylock(void* l); | 10 | extern int cris_spin_trylock(void *l); |
| 16 | 11 | ||
| 17 | static inline void _raw_spin_unlock(spinlock_t *lock) | 12 | static inline int __raw_spin_is_locked(raw_spinlock_t *x) |
| 13 | { | ||
| 14 | return *(volatile signed char *)(&(x)->slock) <= 0; | ||
| 15 | } | ||
| 16 | |||
| 17 | static inline void __raw_spin_unlock(raw_spinlock_t *lock) | ||
| 18 | { | 18 | { |
| 19 | __asm__ volatile ("move.d %1,%0" \ | 19 | __asm__ volatile ("move.d %1,%0" \ |
| 20 | : "=m" (lock->lock) \ | 20 | : "=m" (lock->slock) \ |
| 21 | : "r" (1) \ | 21 | : "r" (1) \ |
| 22 | : "memory"); | 22 | : "memory"); |
| 23 | } | 23 | } |
| 24 | 24 | ||
| 25 | static inline int _raw_spin_trylock(spinlock_t *lock) | 25 | static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock) |
| 26 | { | ||
| 27 | while (__raw_spin_is_locked(lock)) | ||
| 28 | cpu_relax(); | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline int __raw_spin_trylock(raw_spinlock_t *lock) | ||
| 26 | { | 32 | { |
| 27 | return cris_spin_trylock((void*)&lock->lock); | 33 | return cris_spin_trylock((void *)&lock->slock); |
| 28 | } | 34 | } |
| 29 | 35 | ||
| 30 | static inline void _raw_spin_lock(spinlock_t *lock) | 36 | static inline void __raw_spin_lock(raw_spinlock_t *lock) |
| 31 | { | 37 | { |
| 32 | cris_spin_lock((void*)&lock->lock); | 38 | cris_spin_lock((void *)&lock->slock); |
| 33 | } | 39 | } |
| 34 | 40 | ||
| 35 | static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags) | 41 | static inline void |
| 42 | __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags) | ||
| 36 | { | 43 | { |
| 37 | _raw_spin_lock(lock); | 44 | __raw_spin_lock(lock); |
| 38 | } | 45 | } |
| 39 | 46 | ||
| 40 | /* | 47 | /* |
| @@ -46,120 +53,75 @@ static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags) | |||
| 46 | * can "mix" irq-safe locks - any writer needs to get a | 53 | * can "mix" irq-safe locks - any writer needs to get a |
| 47 | * irq-safe write-lock, but readers can get non-irqsafe | 54 | * irq-safe write-lock, but readers can get non-irqsafe |
| 48 | * read-locks. | 55 | * read-locks. |
| 56 | * | ||
| 49 | */ | 57 | */ |
| 50 | typedef struct { | ||
| 51 | spinlock_t lock; | ||
| 52 | volatile int counter; | ||
| 53 | #ifdef CONFIG_PREEMPT | ||
| 54 | unsigned int break_lock; | ||
| 55 | #endif | ||
| 56 | } rwlock_t; | ||
| 57 | |||
| 58 | #define RW_LOCK_UNLOCKED (rwlock_t) { {1}, 0 } | ||
| 59 | |||
| 60 | #define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while (0) | ||
| 61 | |||
| 62 | /** | ||
| 63 | * read_can_lock - would read_trylock() succeed? | ||
| 64 | * @lock: the rwlock in question. | ||
| 65 | */ | ||
| 66 | #define read_can_lock(x) ((int)(x)->counter >= 0) | ||
| 67 | |||
| 68 | /** | ||
| 69 | * write_can_lock - would write_trylock() succeed? | ||
| 70 | * @lock: the rwlock in question. | ||
| 71 | */ | ||
| 72 | #define write_can_lock(x) ((x)->counter == 0) | ||
| 73 | |||
| 74 | #define _raw_read_trylock(lock) generic_raw_read_trylock(lock) | ||
| 75 | 58 | ||
| 76 | /* read_lock, read_unlock are pretty straightforward. Of course it somehow | 59 | static inline int __raw_read_can_lock(raw_rwlock_t *x) |
| 77 | * sucks we end up saving/restoring flags twice for read_lock_irqsave aso. */ | ||
| 78 | |||
| 79 | static __inline__ void _raw_read_lock(rwlock_t *rw) | ||
| 80 | { | 60 | { |
| 81 | unsigned long flags; | 61 | return (int)(x)->lock > 0; |
| 82 | local_irq_save(flags); | ||
| 83 | _raw_spin_lock(&rw->lock); | ||
| 84 | |||
| 85 | rw->counter++; | ||
| 86 | |||
| 87 | _raw_spin_unlock(&rw->lock); | ||
| 88 | local_irq_restore(flags); | ||
| 89 | } | 62 | } |
| 90 | 63 | ||
| 91 | static __inline__ void _raw_read_unlock(rwlock_t *rw) | 64 | static inline int __raw_write_can_lock(raw_rwlock_t *x) |
| 92 | { | 65 | { |
| 93 | unsigned long flags; | 66 | return (x)->lock == RW_LOCK_BIAS; |
| 94 | local_irq_save(flags); | ||
| 95 | _raw_spin_lock(&rw->lock); | ||
| 96 | |||
| 97 | rw->counter--; | ||
| 98 | |||
| 99 | _raw_spin_unlock(&rw->lock); | ||
| 100 | local_irq_restore(flags); | ||
| 101 | } | 67 | } |
| 102 | 68 | ||
| 103 | /* write_lock is less trivial. We optimistically grab the lock and check | 69 | static inline void __raw_read_lock(raw_rwlock_t *rw) |
| 104 | * if we surprised any readers. If so we release the lock and wait till | ||
| 105 | * they're all gone before trying again | ||
| 106 | * | ||
| 107 | * Also note that we don't use the _irqsave / _irqrestore suffixes here. | ||
| 108 | * If we're called with interrupts enabled and we've got readers (or other | ||
| 109 | * writers) in interrupt handlers someone fucked up and we'd dead-lock | ||
| 110 | * sooner or later anyway. prumpf */ | ||
| 111 | |||
| 112 | static __inline__ void _raw_write_lock(rwlock_t *rw) | ||
| 113 | { | 70 | { |
| 114 | retry: | 71 | __raw_spin_lock(&rw->slock); |
| 115 | _raw_spin_lock(&rw->lock); | 72 | while (rw->lock == 0); |
| 116 | 73 | rw->lock--; | |
| 117 | if(rw->counter != 0) { | 74 | __raw_spin_unlock(&rw->slock); |
| 118 | /* this basically never happens */ | ||
| 119 | _raw_spin_unlock(&rw->lock); | ||
| 120 | |||
| 121 | while(rw->counter != 0); | ||
| 122 | |||
| 123 | goto retry; | ||
| 124 | } | ||
| 125 | |||
| 126 | /* got it. now leave without unlocking */ | ||
| 127 | rw->counter = -1; /* remember we are locked */ | ||
| 128 | } | 75 | } |
| 129 | 76 | ||
| 130 | /* write_unlock is absolutely trivial - we don't have to wait for anything */ | 77 | static inline void __raw_write_lock(raw_rwlock_t *rw) |
| 131 | |||
| 132 | static __inline__ void _raw_write_unlock(rwlock_t *rw) | ||
| 133 | { | 78 | { |
| 134 | rw->counter = 0; | 79 | __raw_spin_lock(&rw->slock); |
| 135 | _raw_spin_unlock(&rw->lock); | 80 | while (rw->lock != RW_LOCK_BIAS); |
| 81 | rw->lock == 0; | ||
| 82 | __raw_spin_unlock(&rw->slock); | ||
| 136 | } | 83 | } |
| 137 | 84 | ||
| 138 | static __inline__ int _raw_write_trylock(rwlock_t *rw) | 85 | static inline void __raw_read_unlock(raw_rwlock_t *rw) |
| 139 | { | 86 | { |
| 140 | _raw_spin_lock(&rw->lock); | 87 | __raw_spin_lock(&rw->slock); |
| 141 | if (rw->counter != 0) { | 88 | rw->lock++; |
| 142 | /* this basically never happens */ | 89 | __raw_spin_unlock(&rw->slock); |
| 143 | _raw_spin_unlock(&rw->lock); | 90 | } |
| 144 | |||
| 145 | return 0; | ||
| 146 | } | ||
| 147 | 91 | ||
| 148 | /* got it. now leave without unlocking */ | 92 | static inline void __raw_write_unlock(raw_rwlock_t *rw) |
| 149 | rw->counter = -1; /* remember we are locked */ | 93 | { |
| 150 | return 1; | 94 | __raw_spin_lock(&rw->slock); |
| 95 | while (rw->lock != RW_LOCK_BIAS); | ||
| 96 | rw->lock == RW_LOCK_BIAS; | ||
| 97 | __raw_spin_unlock(&rw->slock); | ||
| 151 | } | 98 | } |
| 152 | 99 | ||
| 153 | static __inline__ int is_read_locked(rwlock_t *rw) | 100 | static inline int __raw_read_trylock(raw_rwlock_t *rw) |
| 154 | { | 101 | { |
| 155 | return rw->counter > 0; | 102 | int ret = 0; |
| 103 | __raw_spin_lock(&rw->slock); | ||
| 104 | if (rw->lock != 0) { | ||
| 105 | rw->lock--; | ||
| 106 | ret = 1; | ||
| 107 | } | ||
| 108 | __raw_spin_unlock(&rw->slock); | ||
| 109 | return ret; | ||
| 156 | } | 110 | } |
| 157 | 111 | ||
| 158 | static __inline__ int is_write_locked(rwlock_t *rw) | 112 | static inline int __raw_write_trylock(raw_rwlock_t *rw) |
| 159 | { | 113 | { |
| 160 | return rw->counter < 0; | 114 | int ret = 0; |
| 115 | __raw_spin_lock(&rw->slock); | ||
| 116 | if (rw->lock == RW_LOCK_BIAS) { | ||
| 117 | rw->lock == 0; | ||
| 118 | ret = 1; | ||
| 119 | } | ||
| 120 | __raw_spin_unlock(&rw->slock); | ||
| 121 | return 1; | ||
| 161 | } | 122 | } |
| 162 | 123 | ||
| 124 | |||
| 163 | #define _raw_spin_relax(lock) cpu_relax() | 125 | #define _raw_spin_relax(lock) cpu_relax() |
| 164 | #define _raw_read_relax(lock) cpu_relax() | 126 | #define _raw_read_relax(lock) cpu_relax() |
| 165 | #define _raw_write_relax(lock) cpu_relax() | 127 | #define _raw_write_relax(lock) cpu_relax() |
diff --git a/include/asm-cris/arch-v32/system.h b/include/asm-cris/arch-v32/system.h index d20e2d6d64a3..6ca90f1f110a 100644 --- a/include/asm-cris/arch-v32/system.h +++ b/include/asm-cris/arch-v32/system.h | |||
| @@ -66,13 +66,4 @@ struct __xchg_dummy { unsigned long a[100]; }; | |||
| 66 | #define local_irq_save(x) \ | 66 | #define local_irq_save(x) \ |
| 67 | __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory"); | 67 | __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory"); |
| 68 | 68 | ||
| 69 | #ifdef CONFIG_SMP | ||
| 70 | typedef struct { | ||
| 71 | volatile unsigned int lock __attribute__ ((aligned(4))); | ||
| 72 | #ifdef CONFIG_PREEMPT | ||
| 73 | unsigned int break_lock; | ||
| 74 | #endif | ||
| 75 | } spinlock_t; | ||
| 76 | #endif | ||
| 77 | |||
| 78 | #endif /* _ASM_CRIS_ARCH_SYSTEM_H */ | 69 | #endif /* _ASM_CRIS_ARCH_SYSTEM_H */ |
diff --git a/include/asm-cris/arch-v32/timex.h b/include/asm-cris/arch-v32/timex.h index 5a4aa285d5fd..2591d3c5ed9d 100644 --- a/include/asm-cris/arch-v32/timex.h +++ b/include/asm-cris/arch-v32/timex.h | |||
| @@ -1,9 +1,9 @@ | |||
| 1 | #ifndef _ASM_CRIS_ARCH_TIMEX_H | 1 | #ifndef _ASM_CRIS_ARCH_TIMEX_H |
| 2 | #define _ASM_CRIS_ARCH_TIMEX_H | 2 | #define _ASM_CRIS_ARCH_TIMEX_H |
| 3 | 3 | ||
| 4 | #include <asm/arch/hwregs/reg_map.h> | 4 | #include <hwregs/reg_map.h> |
| 5 | #include <asm/arch/hwregs/reg_rdwr.h> | 5 | #include <hwregs/reg_rdwr.h> |
| 6 | #include <asm/arch/hwregs/timer_defs.h> | 6 | #include <hwregs/timer_defs.h> |
| 7 | 7 | ||
| 8 | /* | 8 | /* |
| 9 | * The clock runs at 100MHz, we divide it by 1000000. If you change anything | 9 | * The clock runs at 100MHz, we divide it by 1000000. If you change anything |
| @@ -18,7 +18,7 @@ | |||
| 18 | 18 | ||
| 19 | /* Convert the value in step of 10 ns to 1us without overflow: */ | 19 | /* Convert the value in step of 10 ns to 1us without overflow: */ |
| 20 | #define GET_JIFFIES_USEC() \ | 20 | #define GET_JIFFIES_USEC() \ |
| 21 | ( (TIMER0_DIV - REG_RD(timer, regi_timer, r_tmr0_data)) /100 ) | 21 | ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100) |
| 22 | 22 | ||
| 23 | extern unsigned long get_ns_in_jiffie(void); | 23 | extern unsigned long get_ns_in_jiffie(void); |
| 24 | 24 | ||
diff --git a/include/asm-cris/arch-v32/unistd.h b/include/asm-cris/arch-v32/unistd.h index 5d369d4439d9..0051114c63c7 100644 --- a/include/asm-cris/arch-v32/unistd.h +++ b/include/asm-cris/arch-v32/unistd.h | |||
| @@ -16,7 +16,8 @@ type name(void) \ | |||
| 16 | ".endif\n\t" \ | 16 | ".endif\n\t" \ |
| 17 | "break 13" \ | 17 | "break 13" \ |
| 18 | : "=r" (__a) \ | 18 | : "=r" (__a) \ |
| 19 | : "r" (__n_)); \ | 19 | : "r" (__n_) \ |
| 20 | : "memory"); \ | ||
| 20 | if (__a >= 0) \ | 21 | if (__a >= 0) \ |
| 21 | return (type) __a; \ | 22 | return (type) __a; \ |
| 22 | errno = -__a; \ | 23 | errno = -__a; \ |
| @@ -33,7 +34,8 @@ type name(type1 arg1) \ | |||
| 33 | ".endif\n\t" \ | 34 | ".endif\n\t" \ |
| 34 | "break 13" \ | 35 | "break 13" \ |
| 35 | : "=r" (__a) \ | 36 | : "=r" (__a) \ |
| 36 | : "r" (__n_), "0" (__a)); \ | 37 | : "r" (__n_), "0" (__a) \ |
| 38 | : "memory"); \ | ||
| 37 | if (__a >= 0) \ | 39 | if (__a >= 0) \ |
| 38 | return (type) __a; \ | 40 | return (type) __a; \ |
| 39 | errno = -__a; \ | 41 | errno = -__a; \ |
| @@ -51,7 +53,8 @@ type name(type1 arg1,type2 arg2) \ | |||
| 51 | ".endif\n\t" \ | 53 | ".endif\n\t" \ |
| 52 | "break 13" \ | 54 | "break 13" \ |
| 53 | : "=r" (__a) \ | 55 | : "=r" (__a) \ |
| 54 | : "r" (__n_), "0" (__a), "r" (__b)); \ | 56 | : "r" (__n_), "0" (__a), "r" (__b) \ |
| 57 | : "memory"); \ | ||
| 55 | if (__a >= 0) \ | 58 | if (__a >= 0) \ |
| 56 | return (type) __a; \ | 59 | return (type) __a; \ |
| 57 | errno = -__a; \ | 60 | errno = -__a; \ |
| @@ -70,7 +73,8 @@ type name(type1 arg1,type2 arg2,type3 arg3) \ | |||
| 70 | ".endif\n\t" \ | 73 | ".endif\n\t" \ |
| 71 | "break 13" \ | 74 | "break 13" \ |
| 72 | : "=r" (__a) \ | 75 | : "=r" (__a) \ |
| 73 | : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ | 76 | : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \ |
| 77 | : "memory"); \ | ||
| 74 | if (__a >= 0) \ | 78 | if (__a >= 0) \ |
| 75 | return (type) __a; \ | 79 | return (type) __a; \ |
| 76 | errno = -__a; \ | 80 | errno = -__a; \ |
| @@ -91,7 +95,8 @@ type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ | |||
| 91 | "break 13" \ | 95 | "break 13" \ |
| 92 | : "=r" (__a) \ | 96 | : "=r" (__a) \ |
| 93 | : "r" (__n_), "0" (__a), "r" (__b), \ | 97 | : "r" (__n_), "0" (__a), "r" (__b), \ |
| 94 | "r" (__c), "r" (__d)); \ | 98 | "r" (__c), "r" (__d)\ |
| 99 | : "memory"); \ | ||
| 95 | if (__a >= 0) \ | 100 | if (__a >= 0) \ |
| 96 | return (type) __a; \ | 101 | return (type) __a; \ |
| 97 | errno = -__a; \ | 102 | errno = -__a; \ |
| @@ -114,7 +119,8 @@ type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ | |||
| 114 | "break 13" \ | 119 | "break 13" \ |
| 115 | : "=r" (__a) \ | 120 | : "=r" (__a) \ |
| 116 | : "r" (__n_), "0" (__a), "r" (__b), \ | 121 | : "r" (__n_), "0" (__a), "r" (__b), \ |
| 117 | "r" (__c), "r" (__d), "h" (__e)); \ | 122 | "r" (__c), "r" (__d), "h" (__e) \ |
| 123 | : "memory"); \ | ||
| 118 | if (__a >= 0) \ | 124 | if (__a >= 0) \ |
| 119 | return (type) __a; \ | 125 | return (type) __a; \ |
| 120 | errno = -__a; \ | 126 | errno = -__a; \ |
| @@ -138,7 +144,8 @@ type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ | |||
| 138 | "break 13" \ | 144 | "break 13" \ |
| 139 | : "=r" (__a) \ | 145 | : "=r" (__a) \ |
| 140 | : "r" (__n_), "0" (__a), "r" (__b), \ | 146 | : "r" (__n_), "0" (__a), "r" (__b), \ |
| 141 | "r" (__c), "r" (__d), "h" (__e), "x" (__f)); \ | 147 | "r" (__c), "r" (__d), "h" (__e), "x" (__f) \ |
| 148 | : "memory"); \ | ||
| 142 | if (__a >= 0) \ | 149 | if (__a >= 0) \ |
| 143 | return (type) __a; \ | 150 | return (type) __a; \ |
| 144 | errno = -__a; \ | 151 | errno = -__a; \ |
diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h index 2949a945876a..5fc87768774a 100644 --- a/include/asm-cris/atomic.h +++ b/include/asm-cris/atomic.h | |||
| @@ -91,7 +91,7 @@ static inline int atomic_inc_return(volatile atomic_t *v) | |||
| 91 | unsigned long flags; | 91 | unsigned long flags; |
| 92 | int retval; | 92 | int retval; |
| 93 | cris_atomic_save(v, flags); | 93 | cris_atomic_save(v, flags); |
| 94 | retval = (v->counter)++; | 94 | retval = ++(v->counter); |
| 95 | cris_atomic_restore(v, flags); | 95 | cris_atomic_restore(v, flags); |
| 96 | return retval; | 96 | return retval; |
| 97 | } | 97 | } |
| @@ -101,7 +101,7 @@ static inline int atomic_dec_return(volatile atomic_t *v) | |||
| 101 | unsigned long flags; | 101 | unsigned long flags; |
| 102 | int retval; | 102 | int retval; |
| 103 | cris_atomic_save(v, flags); | 103 | cris_atomic_save(v, flags); |
| 104 | retval = (v->counter)--; | 104 | retval = --(v->counter); |
| 105 | cris_atomic_restore(v, flags); | 105 | cris_atomic_restore(v, flags); |
| 106 | return retval; | 106 | return retval; |
| 107 | } | 107 | } |
diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h index 7a8d3114e682..015ca5445ddd 100644 --- a/include/asm-cris/axisflashmap.h +++ b/include/asm-cris/axisflashmap.h | |||
| @@ -10,23 +10,23 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #define PARTITION_TABLE_OFFSET 10 | 12 | #define PARTITION_TABLE_OFFSET 10 |
| 13 | #define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ | 13 | #define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ |
| 14 | 14 | ||
| 15 | /* The partitiontable_head is located at offset +10: */ | 15 | /* The partitiontable_head is located at offset +10: */ |
| 16 | struct partitiontable_head { | 16 | struct partitiontable_head { |
| 17 | __u16 magic; /* PARTITION_TABLE_MAGIC */ | 17 | __u16 magic; /* PARTITION_TABLE_MAGIC */ |
| 18 | __u16 size; /* Length of ptable block (not header) */ | 18 | __u16 size; /* Length of ptable block (entries + end marker) */ |
| 19 | __u32 checksum; /* simple longword sum */ | 19 | __u32 checksum; /* simple longword sum, over entries + end marker */ |
| 20 | }; | 20 | }; |
| 21 | 21 | ||
| 22 | /* And followed by partition table entries */ | 22 | /* And followed by partition table entries */ |
| 23 | struct partitiontable_entry { | 23 | struct partitiontable_entry { |
| 24 | __u32 offset; /* Offset is relative to the sector the ptable is in */ | 24 | __u32 offset; /* relative to the sector the ptable is in */ |
| 25 | __u32 size; | 25 | __u32 size; /* in bytes */ |
| 26 | __u32 checksum; /* simple longword sum */ | 26 | __u32 checksum; /* simple longword sum */ |
| 27 | __u16 type; | 27 | __u16 type; /* see type codes below */ |
| 28 | __u16 flags; /* bit 0: ro/rw = 1/0 */ | 28 | __u16 flags; /* bit 0: ro/rw = 1/0 */ |
| 29 | __u32 future0; /* 16 bytes reserved for future use */ | 29 | __u32 future0; /* 16 bytes reserved for future use */ |
| 30 | __u32 future1; | 30 | __u32 future1; |
| 31 | __u32 future2; | 31 | __u32 future2; |
| 32 | __u32 future3; | 32 | __u32 future3; |
| @@ -35,12 +35,27 @@ struct partitiontable_entry { | |||
| 35 | #define PARTITIONTABLE_END_MARKER 0xFFFFFFFF | 35 | #define PARTITIONTABLE_END_MARKER 0xFFFFFFFF |
| 36 | #define PARTITIONTABLE_END_MARKER_SIZE 4 | 36 | #define PARTITIONTABLE_END_MARKER_SIZE 4 |
| 37 | 37 | ||
| 38 | /*#define PARTITION_TYPE_RESCUE 0x0000?*/ /* Not used, maybe it should? */ | 38 | #define PARTITIONTABLE_END_PAD 10 |
| 39 | |||
| 40 | /* Complete structure for whole partition table */ | ||
| 41 | /* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting | ||
| 42 | * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER. | ||
| 43 | */ | ||
| 44 | struct partitiontable { | ||
| 45 | __u8 skip[PARTITION_TABLE_OFFSET]; | ||
| 46 | struct partitiontable_head head; | ||
| 47 | struct partitiontable_entry entries[]; | ||
| 48 | }; | ||
| 49 | |||
| 39 | #define PARTITION_TYPE_PARAM 0x0001 | 50 | #define PARTITION_TYPE_PARAM 0x0001 |
| 40 | #define PARTITION_TYPE_KERNEL 0x0002 | 51 | #define PARTITION_TYPE_KERNEL 0x0002 |
| 41 | #define PARTITION_TYPE_JFFS 0x0003 | 52 | #define PARTITION_TYPE_JFFS 0x0003 |
| 53 | #define PARTITION_TYPE_JFFS2 0x0000 | ||
| 54 | |||
| 55 | #define PARTITION_FLAGS_READONLY_MASK 0x0001 | ||
| 56 | #define PARTITION_FLAGS_READONLY 0x0001 | ||
| 42 | 57 | ||
| 43 | /* The master mtd for the entire flash. */ | 58 | /* The master mtd for the entire flash. */ |
| 44 | extern struct mtd_info* axisflash_mtd; | 59 | extern struct mtd_info *axisflash_mtd; |
| 45 | 60 | ||
| 46 | #endif | 61 | #endif |
diff --git a/include/asm-cris/bug.h b/include/asm-cris/bug.h index 8dd6b23c15d6..fee12d4ae683 100644 --- a/include/asm-cris/bug.h +++ b/include/asm-cris/bug.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | #ifndef _CRIS_BUG_H | 1 | #ifndef _CRIS_BUG_H |
| 2 | #define _CRIS_BUG_H | 2 | #define _CRIS_BUG_H |
| 3 | #include <asm-generic/bug.h> | 3 | #include <asm/arch/bug.h> |
| 4 | #endif | 4 | #endif |
diff --git a/include/asm-cris/delay.h b/include/asm-cris/delay.h index d3a397803719..123e19aef49d 100644 --- a/include/asm-cris/delay.h +++ b/include/asm-cris/delay.h | |||
| @@ -13,10 +13,13 @@ | |||
| 13 | 13 | ||
| 14 | extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */ | 14 | extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */ |
| 15 | 15 | ||
| 16 | /* May be defined by arch/delay.h. */ | ||
| 17 | #ifndef udelay | ||
| 16 | static inline void udelay(unsigned long usecs) | 18 | static inline void udelay(unsigned long usecs) |
| 17 | { | 19 | { |
| 18 | __delay(usecs * loops_per_usec); | 20 | __delay(usecs * loops_per_usec); |
| 19 | } | 21 | } |
| 22 | #endif | ||
| 20 | 23 | ||
| 21 | #endif /* defined(_CRIS_DELAY_H) */ | 24 | #endif /* defined(_CRIS_DELAY_H) */ |
| 22 | 25 | ||
diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h index 662cea70152d..edc8d1bfaae2 100644 --- a/include/asm-cris/dma-mapping.h +++ b/include/asm-cris/dma-mapping.h | |||
| @@ -164,16 +164,5 @@ dma_cache_sync(struct device *dev, void *vaddr, size_t size, | |||
| 164 | { | 164 | { |
| 165 | } | 165 | } |
| 166 | 166 | ||
| 167 | #define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY | ||
| 168 | extern int | ||
| 169 | dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, | ||
| 170 | dma_addr_t device_addr, size_t size, int flags); | ||
| 171 | |||
| 172 | extern void | ||
| 173 | dma_release_declared_memory(struct device *dev); | ||
| 174 | |||
| 175 | extern void * | ||
| 176 | dma_mark_declared_memory_occupied(struct device *dev, | ||
| 177 | dma_addr_t device_addr, size_t size); | ||
| 178 | 167 | ||
| 179 | #endif | 168 | #endif |
diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h index 5d0028dba7c6..38f1c8e1770c 100644 --- a/include/asm-cris/etraxgpio.h +++ b/include/asm-cris/etraxgpio.h | |||
| @@ -1,25 +1,34 @@ | |||
| 1 | /* $Id: etraxgpio.h,v 1.8 2002/06/17 15:53:07 johana Exp $ */ | ||
| 2 | /* | 1 | /* |
| 3 | * The following devices are accessable using this driver using | 2 | * The following devices are accessable using this driver using |
| 4 | * GPIO_MAJOR (120) and a couple of minor numbers: | 3 | * GPIO_MAJOR (120) and a couple of minor numbers. |
| 5 | * For ETRAX 100LX (ARCH_V10): | 4 | * |
| 5 | * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): | ||
| 6 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | 6 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction |
| 7 | * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction | 7 | * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction |
| 8 | * /dev/leds minor 2, Access to leds depending on kernelconfig | 8 | * /dev/leds minor 2, Access to leds depending on kernelconfig |
| 9 | * /dev/gpiog minor 3 | 9 | * /dev/gpiog minor 3 |
| 10 | g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG | 10 | * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG |
| 11 | g1-g7 and g25-g31 is both input and outputs but on different pins | 11 | * g1-g7 and g25-g31 is both input and outputs but on different pins |
| 12 | Also note that some bits change pins depending on what interfaces | 12 | * Also note that some bits change pins depending on what interfaces |
| 13 | are enabled. | 13 | * are enabled. |
| 14 | * | 14 | * |
| 15 | * For ETRAX FS (CONFIG_ETRAXFS): | ||
| 16 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | ||
| 17 | * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction | ||
| 18 | * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction | ||
| 19 | * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction | ||
| 20 | * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction | ||
| 21 | * /dev/leds minor 2, Access to leds depending on kernelconfig | ||
| 15 | * | 22 | * |
| 16 | * For ETRAX FS (ARCH_V32): | 23 | * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): |
| 17 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction | 24 | * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction |
| 18 | * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction | 25 | * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction |
| 19 | * /dev/gpioc minor 2, 18 bit GPIO, each bit can change direction | 26 | * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction |
| 20 | * /dev/gpiod minor 3, 18 bit GPIO, each bit can change direction | 27 | * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction |
| 21 | * /dev/gpioe minor 4, 18 bit GPIO, each bit can change direction | 28 | * /dev/leds minor 2, Access to leds depending on kernelconfig |
| 22 | * /dev/leds minor 5, Access to leds depending on kernelconfig | 29 | * /dev/pwm0 minor 16, PWM channel 0 on PA30 |
| 30 | * /dev/pwm1 minor 17, PWM channel 1 on PA31 | ||
| 31 | * /dev/pwm2 minor 18, PWM channel 2 on PB26 | ||
| 23 | * | 32 | * |
| 24 | */ | 33 | */ |
| 25 | #ifndef _ASM_ETRAXGPIO_H | 34 | #ifndef _ASM_ETRAXGPIO_H |
| @@ -34,7 +43,8 @@ | |||
| 34 | #define GPIO_MINOR_G 3 | 43 | #define GPIO_MINOR_G 3 |
| 35 | #define GPIO_MINOR_LAST 3 | 44 | #define GPIO_MINOR_LAST 3 |
| 36 | #endif | 45 | #endif |
| 37 | #ifdef CONFIG_ETRAX_ARCH_V32 | 46 | |
| 47 | #ifdef CONFIG_ETRAXFS | ||
| 38 | #define ETRAXGPIO_IOCTYPE 43 | 48 | #define ETRAXGPIO_IOCTYPE 43 |
| 39 | #define GPIO_MINOR_A 0 | 49 | #define GPIO_MINOR_A 0 |
| 40 | #define GPIO_MINOR_B 1 | 50 | #define GPIO_MINOR_B 1 |
| @@ -42,8 +52,32 @@ | |||
| 42 | #define GPIO_MINOR_C 3 | 52 | #define GPIO_MINOR_C 3 |
| 43 | #define GPIO_MINOR_D 4 | 53 | #define GPIO_MINOR_D 4 |
| 44 | #define GPIO_MINOR_E 5 | 54 | #define GPIO_MINOR_E 5 |
| 55 | #ifdef CONFIG_ETRAX_VIRTUAL_GPIO | ||
| 56 | #define GPIO_MINOR_V 6 | ||
| 57 | #define GPIO_MINOR_LAST 6 | ||
| 58 | #else | ||
| 45 | #define GPIO_MINOR_LAST 5 | 59 | #define GPIO_MINOR_LAST 5 |
| 46 | #endif | 60 | #endif |
| 61 | #endif | ||
| 62 | |||
| 63 | #ifdef CONFIG_CRIS_MACH_ARTPEC3 | ||
| 64 | #define ETRAXGPIO_IOCTYPE 43 | ||
| 65 | #define GPIO_MINOR_A 0 | ||
| 66 | #define GPIO_MINOR_B 1 | ||
| 67 | #define GPIO_MINOR_LEDS 2 | ||
| 68 | #define GPIO_MINOR_C 3 | ||
| 69 | #define GPIO_MINOR_D 4 | ||
| 70 | #ifdef CONFIG_ETRAX_VIRTUAL_GPIO | ||
| 71 | #define GPIO_MINOR_V 6 | ||
| 72 | #define GPIO_MINOR_LAST 6 | ||
| 73 | #else | ||
| 74 | #define GPIO_MINOR_LAST 4 | ||
| 75 | #endif | ||
| 76 | #define GPIO_MINOR_PWM0 16 | ||
| 77 | #define GPIO_MINOR_PWM1 17 | ||
| 78 | #define GPIO_MINOR_PWM2 18 | ||
| 79 | #define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2 | ||
| 80 | #endif | ||
| 47 | 81 | ||
| 48 | /* supported ioctl _IOC_NR's */ | 82 | /* supported ioctl _IOC_NR's */ |
| 49 | 83 | ||
| @@ -63,7 +97,7 @@ | |||
| 63 | 97 | ||
| 64 | /* GPIO direction ioctl's */ | 98 | /* GPIO direction ioctl's */ |
| 65 | #define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ | 99 | #define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ |
| 66 | #define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, | 100 | #define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, |
| 67 | returns mask with current inputs (obsolete) */ | 101 | returns mask with current inputs (obsolete) */ |
| 68 | #define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, | 102 | #define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, |
| 69 | returns mask with current outputs (obsolete)*/ | 103 | returns mask with current outputs (obsolete)*/ |
| @@ -77,13 +111,13 @@ | |||
| 77 | #define IO_GET_PWR_BT 0xE | 111 | #define IO_GET_PWR_BT 0xE |
| 78 | 112 | ||
| 79 | /* Bit toggling in driver settings */ | 113 | /* Bit toggling in driver settings */ |
| 80 | /* bit set in low byte0 is CLK mask (0x00FF), | 114 | /* bit set in low byte0 is CLK mask (0x00FF), |
| 81 | bit set in byte1 is DATA mask (0xFF00) | 115 | bit set in byte1 is DATA mask (0xFF00) |
| 82 | msb, data_mask[7:0] , clk_mask[7:0] | 116 | msb, data_mask[7:0] , clk_mask[7:0] |
| 83 | */ | 117 | */ |
| 84 | #define IO_CFG_WRITE_MODE 0xF | 118 | #define IO_CFG_WRITE_MODE 0xF |
| 85 | #define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ | 119 | #define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ |
| 86 | ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) | 120 | ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) |
| 87 | 121 | ||
| 88 | /* The following 4 ioctl's take a pointer as argument and handles | 122 | /* The following 4 ioctl's take a pointer as argument and handles |
| 89 | * 32 bit ports (port G) properly. | 123 | * 32 bit ports (port G) properly. |
| @@ -98,6 +132,48 @@ | |||
| 98 | * *arg updated with current output pins. | 132 | * *arg updated with current output pins. |
| 99 | */ | 133 | */ |
| 100 | 134 | ||
| 135 | /* The following ioctl's are applicable to the PWM channels only */ | ||
| 136 | |||
| 137 | #define IO_PWM_SET_MODE 0x20 | ||
| 138 | |||
| 139 | enum io_pwm_mode { | ||
| 140 | PWM_OFF = 0, /* disabled, deallocated */ | ||
| 141 | PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ | ||
| 142 | PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ | ||
| 143 | PWM_VARFREQ = 3 /* individually configurable high/low periods */ | ||
| 144 | }; | ||
| 145 | |||
| 146 | struct io_pwm_set_mode { | ||
| 147 | enum io_pwm_mode mode; | ||
| 148 | }; | ||
| 149 | |||
| 150 | /* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns | ||
| 151 | * from 10ns (value = 0) to 81920ns (value = 8191) | ||
| 152 | * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to | ||
| 153 | * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty | ||
| 154 | * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) | ||
| 155 | */ | ||
| 156 | #define IO_PWM_SET_PERIOD 0x21 | ||
| 157 | |||
| 158 | struct io_pwm_set_period { | ||
| 159 | unsigned int lo; /* 0..8191 */ | ||
| 160 | unsigned int hi; /* 0..8191 */ | ||
| 161 | }; | ||
| 162 | |||
| 163 | /* Only for modes PWM_STANDARD and PWM_FAST. | ||
| 164 | * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from | ||
| 165 | * 0 (value = 0) to 255/256 (value = 255). | ||
| 166 | * For PWM_FAST, set duty cycle of PWM output signal from | ||
| 167 | * 0% (value = 0) to 100% (value = 255). Output signal in this mode | ||
| 168 | * is a 10ns pulse surrounded by a high or low level depending on duty | ||
| 169 | * cycle (except for 0% and 100% which result in a constant output). | ||
| 170 | * Resulting output frequency varies from 50 MHz at 50% duty cycle, | ||
| 171 | * down to 390 kHz at min/max duty cycle. | ||
| 172 | */ | ||
| 173 | #define IO_PWM_SET_DUTY 0x22 | ||
| 101 | 174 | ||
| 175 | struct io_pwm_set_duty { | ||
| 176 | int duty; /* 0..255 */ | ||
| 177 | }; | ||
| 102 | 178 | ||
| 103 | #endif | 179 | #endif |
diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h index d196dd6b2df3..b87ce63f531f 100644 --- a/include/asm-cris/io.h +++ b/include/asm-cris/io.h | |||
| @@ -122,8 +122,8 @@ static inline void writel(unsigned int b, volatile void __iomem *addr) | |||
| 122 | #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | 122 | #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) |
| 123 | 123 | ||
| 124 | 124 | ||
| 125 | /* The following is junk needed for the arch-independent code but which | 125 | /* I/O port access. Normally there is no I/O space on CRIS but when |
| 126 | * we never use in the CRIS port | 126 | * Cardbus/PCI is enabled the request is passed through the bridge. |
| 127 | */ | 127 | */ |
| 128 | 128 | ||
| 129 | #define IO_SPACE_LIMIT 0xffff | 129 | #define IO_SPACE_LIMIT 0xffff |
diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h index 3b0156c46311..c45bb1ef397c 100644 --- a/include/asm-cris/page.h +++ b/include/asm-cris/page.h | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | typedef struct { unsigned long pte; } pte_t; | 26 | typedef struct { unsigned long pte; } pte_t; |
| 27 | typedef struct { unsigned long pgd; } pgd_t; | 27 | typedef struct { unsigned long pgd; } pgd_t; |
| 28 | typedef struct { unsigned long pgprot; } pgprot_t; | 28 | typedef struct { unsigned long pgprot; } pgprot_t; |
| 29 | typedef struct page *pgtable_t; | ||
| 29 | #endif | 30 | #endif |
| 30 | 31 | ||
| 31 | #define pte_val(x) ((x).pte) | 32 | #define pte_val(x) ((x).pte) |
diff --git a/include/asm-cris/param.h b/include/asm-cris/param.h index b24972639832..0e47994e40be 100644 --- a/include/asm-cris/param.h +++ b/include/asm-cris/param.h | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | 3 | ||
| 4 | /* Currently we assume that HZ=100 is good for CRIS. */ | 4 | /* Currently we assume that HZ=100 is good for CRIS. */ |
| 5 | #ifdef __KERNEL__ | 5 | #ifdef __KERNEL__ |
| 6 | # define HZ 100 /* Internal kernel timer frequency */ | 6 | # define HZ CONFIG_HZ /* Internal kernel timer frequency */ |
| 7 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ | 7 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ |
| 8 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | 8 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ |
| 9 | #endif | 9 | #endif |
diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h index 8ddd66f81773..a1ba761d0573 100644 --- a/include/asm-cris/pgalloc.h +++ b/include/asm-cris/pgalloc.h | |||
| @@ -6,6 +6,7 @@ | |||
| 6 | 6 | ||
| 7 | #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) | 7 | #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) |
| 8 | #define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte)) | 8 | #define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte)) |
| 9 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 9 | 10 | ||
| 10 | /* | 11 | /* |
| 11 | * Allocate and free page tables. | 12 | * Allocate and free page tables. |
| @@ -27,10 +28,11 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long ad | |||
| 27 | return pte; | 28 | return pte; |
| 28 | } | 29 | } |
| 29 | 30 | ||
| 30 | static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) | 31 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) |
| 31 | { | 32 | { |
| 32 | struct page *pte; | 33 | struct page *pte; |
| 33 | pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); | 34 | pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); |
| 35 | pgtable_page_ctor(pte); | ||
| 34 | return pte; | 36 | return pte; |
| 35 | } | 37 | } |
| 36 | 38 | ||
| @@ -39,13 +41,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 39 | free_page((unsigned long)pte); | 41 | free_page((unsigned long)pte); |
| 40 | } | 42 | } |
| 41 | 43 | ||
| 42 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 44 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 43 | { | 45 | { |
| 46 | pgtable_page_dtor(pte); | ||
| 44 | __free_page(pte); | 47 | __free_page(pte); |
| 45 | } | 48 | } |
| 46 | 49 | ||
| 47 | 50 | #define __pte_free_tlb(tlb,pte) \ | |
| 48 | #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) | 51 | do { \ |
| 52 | pgtable_page_dtor(pte); \ | ||
| 53 | tlb_remove_page((tlb), pte); \ | ||
| 54 | } while (0) | ||
| 49 | 55 | ||
| 50 | #define check_pgt_cache() do { } while (0) | 56 | #define check_pgt_cache() do { } while (0) |
| 51 | 57 | ||
diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h index 417f71116215..a2607575681b 100644 --- a/include/asm-cris/pgtable.h +++ b/include/asm-cris/pgtable.h | |||
| @@ -249,7 +249,7 @@ static inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) | |||
| 249 | #define pte_unmap(pte) do { } while (0) | 249 | #define pte_unmap(pte) do { } while (0) |
| 250 | #define pte_unmap_nested(pte) do { } while (0) | 250 | #define pte_unmap_nested(pte) do { } while (0) |
| 251 | #define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT) | 251 | #define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT) |
| 252 | #define pfn_pte(pfn, prot) __pte((__pa((pfn) << PAGE_SHIFT)) | pgprot_val(prot)) | 252 | #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) |
| 253 | 253 | ||
| 254 | #define pte_ERROR(e) \ | 254 | #define pte_ERROR(e) \ |
| 255 | printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) | 255 | printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) |
diff --git a/include/asm-cris/posix_types.h b/include/asm-cris/posix_types.h index 3a5e4c43eae7..ce3fb25a460b 100644 --- a/include/asm-cris/posix_types.h +++ b/include/asm-cris/posix_types.h | |||
| @@ -44,11 +44,7 @@ typedef long long __kernel_loff_t; | |||
| 44 | #endif | 44 | #endif |
| 45 | 45 | ||
| 46 | typedef struct { | 46 | typedef struct { |
| 47 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 48 | int val[2]; | 47 | int val[2]; |
| 49 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 50 | int __val[2]; | ||
| 51 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 52 | } __kernel_fsid_t; | 48 | } __kernel_fsid_t; |
| 53 | 49 | ||
| 54 | #ifdef __KERNEL__ | 50 | #ifdef __KERNEL__ |
diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h index 568da1deceb9..cdc0c1dce6be 100644 --- a/include/asm-cris/processor.h +++ b/include/asm-cris/processor.h | |||
| @@ -17,6 +17,9 @@ | |||
| 17 | 17 | ||
| 18 | struct task_struct; | 18 | struct task_struct; |
| 19 | 19 | ||
| 20 | #define STACK_TOP TASK_SIZE | ||
| 21 | #define STACK_TOP_MAX STACK_TOP | ||
| 22 | |||
| 20 | /* This decides where the kernel will search for a free chunk of vm | 23 | /* This decides where the kernel will search for a free chunk of vm |
| 21 | * space during mmap's. | 24 | * space during mmap's. |
| 22 | */ | 25 | */ |
diff --git a/include/asm-cris/rtc.h b/include/asm-cris/rtc.h index cb4bf9217fee..17d3019529e1 100644 --- a/include/asm-cris/rtc.h +++ b/include/asm-cris/rtc.h | |||
| @@ -1,10 +1,7 @@ | |||
| 1 | /* $Id: rtc.h,v 1.7 2002/11/04 07:32:09 starvik Exp $ */ | ||
| 2 | 1 | ||
| 3 | #ifndef __RTC_H__ | 2 | #ifndef __RTC_H__ |
| 4 | #define __RTC_H__ | 3 | #define __RTC_H__ |
| 5 | 4 | ||
| 6 | |||
| 7 | |||
| 8 | #ifdef CONFIG_ETRAX_DS1302 | 5 | #ifdef CONFIG_ETRAX_DS1302 |
| 9 | /* Dallas DS1302 clock/calendar register numbers. */ | 6 | /* Dallas DS1302 clock/calendar register numbers. */ |
| 10 | # define RTC_SECONDS 0 | 7 | # define RTC_SECONDS 0 |
| @@ -17,17 +14,17 @@ | |||
| 17 | # define RTC_CONTROL 7 | 14 | # define RTC_CONTROL 7 |
| 18 | 15 | ||
| 19 | /* Bits in CONTROL register. */ | 16 | /* Bits in CONTROL register. */ |
| 20 | # define RTC_CONTROL_WRITEPROTECT 0x80 | 17 | # define RTC_CONTROL_WRITEPROTECT 0x80 |
| 21 | # define RTC_TRICKLECHARGER 8 | 18 | # define RTC_TRICKLECHARGER 8 |
| 22 | 19 | ||
| 23 | /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */ | 20 | /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */ |
| 24 | # define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */ | 21 | # define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */ |
| 25 | # define RTC_TCR_1DIOD 0x04 /* xxxx01xx */ | 22 | # define RTC_TCR_1DIOD 0x04 /* xxxx01xx */ |
| 26 | # define RTC_TCR_2DIOD 0x08 /* xxxx10xx */ | 23 | # define RTC_TCR_2DIOD 0x08 /* xxxx10xx */ |
| 27 | # define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */ | 24 | # define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */ |
| 28 | # define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */ | 25 | # define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */ |
| 29 | # define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */ | 26 | # define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */ |
| 30 | # define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */ | 27 | # define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */ |
| 31 | 28 | ||
| 32 | #elif defined(CONFIG_ETRAX_PCF8563) | 29 | #elif defined(CONFIG_ETRAX_PCF8563) |
| 33 | /* I2C bus slave registers. */ | 30 | /* I2C bus slave registers. */ |
| @@ -79,7 +76,7 @@ extern int pcf8563_init(void); | |||
| 79 | 76 | ||
| 80 | /* | 77 | /* |
| 81 | * The struct used to pass data via the following ioctl. Similar to the | 78 | * The struct used to pass data via the following ioctl. Similar to the |
| 82 | * struct tm in <time.h>, but it needs to be here so that the kernel | 79 | * struct tm in <time.h>, but it needs to be here so that the kernel |
| 83 | * source is self contained, allowing cross-compiles, etc. etc. | 80 | * source is self contained, allowing cross-compiles, etc. etc. |
| 84 | */ | 81 | */ |
| 85 | struct rtc_time { | 82 | struct rtc_time { |
| @@ -96,11 +93,15 @@ struct rtc_time { | |||
| 96 | 93 | ||
| 97 | /* ioctl() calls that are permitted to the /dev/rtc interface. */ | 94 | /* ioctl() calls that are permitted to the /dev/rtc interface. */ |
| 98 | #define RTC_MAGIC 'p' | 95 | #define RTC_MAGIC 'p' |
| 99 | #define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) /* Read RTC time. */ | 96 | /* Read RTC time. */ |
| 100 | #define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) /* Set RTC time. */ | 97 | #define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) |
| 101 | #define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int) | 98 | /* Set RTC time. */ |
| 102 | #define RTC_VLOW_RD _IOR(RTC_MAGIC, 0x11, int) /* Voltage Low detector */ | 99 | #define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) |
| 103 | #define RTC_VLOW_SET _IO(RTC_MAGIC, 0x12) /* Clear voltage low information */ | 100 | #define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int) |
| 104 | #define RTC_MAX_IOCTL 0x12 | 101 | /* Voltage low detector */ |
| 102 | #define RTC_VL_READ _IOR(RTC_MAGIC, 0x13, int) | ||
| 103 | /* Clear voltage low information */ | ||
| 104 | #define RTC_VL_CLR _IO(RTC_MAGIC, 0x14) | ||
| 105 | #define RTC_MAX_IOCTL 0x14 | ||
| 105 | 106 | ||
| 106 | #endif /* __RTC_H__ */ | 107 | #endif /* __RTC_H__ */ |
diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h index dca5ef1d8c97..dba33aba3e95 100644 --- a/include/asm-cris/smp.h +++ b/include/asm-cris/smp.h | |||
| @@ -4,8 +4,8 @@ | |||
| 4 | #include <linux/cpumask.h> | 4 | #include <linux/cpumask.h> |
| 5 | 5 | ||
| 6 | extern cpumask_t phys_cpu_present_map; | 6 | extern cpumask_t phys_cpu_present_map; |
| 7 | #define cpu_possible_map phys_cpu_present_map | 7 | extern cpumask_t cpu_possible_map; |
| 8 | 8 | ||
| 9 | #define __smp_processor_id() (current_thread_info()->cpu) | 9 | #define raw_smp_processor_id() (current_thread_info()->cpu) |
| 10 | 10 | ||
| 11 | #endif | 11 | #endif |
diff --git a/include/asm-cris/sync_serial.h b/include/asm-cris/sync_serial.h index f930b6e00663..d87c24df2b38 100644 --- a/include/asm-cris/sync_serial.h +++ b/include/asm-cris/sync_serial.h | |||
| @@ -67,6 +67,7 @@ | |||
| 67 | /* Values for SSP_FRAME_SYNC */ | 67 | /* Values for SSP_FRAME_SYNC */ |
| 68 | #define NORMAL_SYNC 1 | 68 | #define NORMAL_SYNC 1 |
| 69 | #define EARLY_SYNC 2 | 69 | #define EARLY_SYNC 2 |
| 70 | #define SECOND_WORD_SYNC 0x40000 | ||
| 70 | 71 | ||
| 71 | #define BIT_SYNC 4 | 72 | #define BIT_SYNC 4 |
| 72 | #define WORD_SYNC 8 | 73 | #define WORD_SYNC 8 |
diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h index bd57a7949170..007cb16a6b5b 100644 --- a/include/asm-cris/unistd.h +++ b/include/asm-cris/unistd.h | |||
| @@ -326,9 +326,11 @@ | |||
| 326 | #define __NR_epoll_pwait 319 | 326 | #define __NR_epoll_pwait 319 |
| 327 | #define __NR_utimensat 320 | 327 | #define __NR_utimensat 320 |
| 328 | #define __NR_signalfd 321 | 328 | #define __NR_signalfd 321 |
| 329 | #define __NR_timerfd 322 | 329 | #define __NR_timerfd_create 322 |
| 330 | #define __NR_eventfd 323 | 330 | #define __NR_eventfd 323 |
| 331 | #define __NR_fallocate 324 | 331 | #define __NR_fallocate 324 |
| 332 | #define __NR_timerfd_settime 315 | ||
| 333 | #define __NR_timerfd_gettime 316 | ||
| 332 | 334 | ||
| 333 | #ifdef __KERNEL__ | 335 | #ifdef __KERNEL__ |
| 334 | 336 | ||
diff --git a/include/asm-frv/a.out.h b/include/asm-frv/a.out.h deleted file mode 100644 index dd3b7e5754c9..000000000000 --- a/include/asm-frv/a.out.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * FRV doesn't do AOUT format. This header file should be removed as | ||
| 3 | * soon as fs/exec.c and fs/proc/kcore.c and the archs that require | ||
| 4 | * them to include linux/a.out.h are fixed. | ||
| 5 | */ | ||
diff --git a/include/asm-frv/atomic.h b/include/asm-frv/atomic.h index 6ec494a5bc5a..46d696b331e7 100644 --- a/include/asm-frv/atomic.h +++ b/include/asm-frv/atomic.h | |||
| @@ -125,87 +125,6 @@ static inline void atomic_dec(atomic_t *v) | |||
| 125 | #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) | 125 | #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) |
| 126 | #define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) | 126 | #define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) |
| 127 | 127 | ||
| 128 | #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS | ||
| 129 | static inline | ||
| 130 | unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v) | ||
| 131 | { | ||
| 132 | unsigned long old, tmp; | ||
| 133 | |||
| 134 | asm volatile( | ||
| 135 | "0: \n" | ||
| 136 | " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ | ||
| 137 | " ckeq icc3,cc7 \n" | ||
| 138 | " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ | ||
| 139 | " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ | ||
| 140 | " and%I3 %1,%3,%2 \n" | ||
| 141 | " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ | ||
| 142 | " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ | ||
| 143 | " beq icc3,#0,0b \n" | ||
| 144 | : "+U"(*v), "=&r"(old), "=r"(tmp) | ||
| 145 | : "NPr"(~mask) | ||
| 146 | : "memory", "cc7", "cc3", "icc3" | ||
| 147 | ); | ||
| 148 | |||
| 149 | return old; | ||
| 150 | } | ||
| 151 | |||
| 152 | static inline | ||
| 153 | unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v) | ||
| 154 | { | ||
| 155 | unsigned long old, tmp; | ||
| 156 | |||
| 157 | asm volatile( | ||
| 158 | "0: \n" | ||
| 159 | " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ | ||
| 160 | " ckeq icc3,cc7 \n" | ||
| 161 | " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ | ||
| 162 | " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ | ||
| 163 | " or%I3 %1,%3,%2 \n" | ||
| 164 | " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ | ||
| 165 | " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ | ||
| 166 | " beq icc3,#0,0b \n" | ||
| 167 | : "+U"(*v), "=&r"(old), "=r"(tmp) | ||
| 168 | : "NPr"(mask) | ||
| 169 | : "memory", "cc7", "cc3", "icc3" | ||
| 170 | ); | ||
| 171 | |||
| 172 | return old; | ||
| 173 | } | ||
| 174 | |||
| 175 | static inline | ||
| 176 | unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v) | ||
| 177 | { | ||
| 178 | unsigned long old, tmp; | ||
| 179 | |||
| 180 | asm volatile( | ||
| 181 | "0: \n" | ||
| 182 | " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ | ||
| 183 | " ckeq icc3,cc7 \n" | ||
| 184 | " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ | ||
| 185 | " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ | ||
| 186 | " xor%I3 %1,%3,%2 \n" | ||
| 187 | " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ | ||
| 188 | " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ | ||
| 189 | " beq icc3,#0,0b \n" | ||
| 190 | : "+U"(*v), "=&r"(old), "=r"(tmp) | ||
| 191 | : "NPr"(mask) | ||
| 192 | : "memory", "cc7", "cc3", "icc3" | ||
| 193 | ); | ||
| 194 | |||
| 195 | return old; | ||
| 196 | } | ||
| 197 | |||
| 198 | #else | ||
| 199 | |||
| 200 | extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v); | ||
| 201 | extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v); | ||
| 202 | extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v); | ||
| 203 | |||
| 204 | #endif | ||
| 205 | |||
| 206 | #define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v)) | ||
| 207 | #define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v)) | ||
| 208 | |||
| 209 | /*****************************************************************************/ | 128 | /*****************************************************************************/ |
| 210 | /* | 129 | /* |
| 211 | * exchange value with memory | 130 | * exchange value with memory |
diff --git a/include/asm-frv/bitops.h b/include/asm-frv/bitops.h index 5f86b876b298..39456ba0ec17 100644 --- a/include/asm-frv/bitops.h +++ b/include/asm-frv/bitops.h | |||
| @@ -16,8 +16,6 @@ | |||
| 16 | 16 | ||
| 17 | #include <linux/compiler.h> | 17 | #include <linux/compiler.h> |
| 18 | #include <asm/byteorder.h> | 18 | #include <asm/byteorder.h> |
| 19 | #include <asm/system.h> | ||
| 20 | #include <asm/atomic.h> | ||
| 21 | 19 | ||
| 22 | #ifdef __KERNEL__ | 20 | #ifdef __KERNEL__ |
| 23 | 21 | ||
| @@ -33,6 +31,87 @@ | |||
| 33 | #define smp_mb__before_clear_bit() barrier() | 31 | #define smp_mb__before_clear_bit() barrier() |
| 34 | #define smp_mb__after_clear_bit() barrier() | 32 | #define smp_mb__after_clear_bit() barrier() |
| 35 | 33 | ||
| 34 | #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS | ||
| 35 | static inline | ||
| 36 | unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v) | ||
| 37 | { | ||
| 38 | unsigned long old, tmp; | ||
| 39 | |||
| 40 | asm volatile( | ||
| 41 | "0: \n" | ||
| 42 | " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ | ||
| 43 | " ckeq icc3,cc7 \n" | ||
| 44 | " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ | ||
| 45 | " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ | ||
| 46 | " and%I3 %1,%3,%2 \n" | ||
| 47 | " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ | ||
| 48 | " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ | ||
| 49 | " beq icc3,#0,0b \n" | ||
| 50 | : "+U"(*v), "=&r"(old), "=r"(tmp) | ||
| 51 | : "NPr"(~mask) | ||
| 52 | : "memory", "cc7", "cc3", "icc3" | ||
| 53 | ); | ||
| 54 | |||
| 55 | return old; | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline | ||
| 59 | unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v) | ||
| 60 | { | ||
| 61 | unsigned long old, tmp; | ||
| 62 | |||
| 63 | asm volatile( | ||
| 64 | "0: \n" | ||
| 65 | " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ | ||
| 66 | " ckeq icc3,cc7 \n" | ||
| 67 | " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ | ||
| 68 | " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ | ||
| 69 | " or%I3 %1,%3,%2 \n" | ||
| 70 | " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ | ||
| 71 | " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ | ||
| 72 | " beq icc3,#0,0b \n" | ||
| 73 | : "+U"(*v), "=&r"(old), "=r"(tmp) | ||
| 74 | : "NPr"(mask) | ||
| 75 | : "memory", "cc7", "cc3", "icc3" | ||
| 76 | ); | ||
| 77 | |||
| 78 | return old; | ||
| 79 | } | ||
| 80 | |||
| 81 | static inline | ||
| 82 | unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v) | ||
| 83 | { | ||
| 84 | unsigned long old, tmp; | ||
| 85 | |||
| 86 | asm volatile( | ||
| 87 | "0: \n" | ||
| 88 | " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */ | ||
| 89 | " ckeq icc3,cc7 \n" | ||
| 90 | " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */ | ||
| 91 | " orcr cc7,cc7,cc3 \n" /* set CC3 to true */ | ||
| 92 | " xor%I3 %1,%3,%2 \n" | ||
| 93 | " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */ | ||
| 94 | " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */ | ||
| 95 | " beq icc3,#0,0b \n" | ||
| 96 | : "+U"(*v), "=&r"(old), "=r"(tmp) | ||
| 97 | : "NPr"(mask) | ||
| 98 | : "memory", "cc7", "cc3", "icc3" | ||
| 99 | ); | ||
| 100 | |||
| 101 | return old; | ||
| 102 | } | ||
| 103 | |||
| 104 | #else | ||
| 105 | |||
| 106 | extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v); | ||
| 107 | extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v); | ||
| 108 | extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v); | ||
| 109 | |||
| 110 | #endif | ||
| 111 | |||
| 112 | #define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v)) | ||
| 113 | #define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v)) | ||
| 114 | |||
| 36 | static inline int test_and_clear_bit(int nr, volatile void *addr) | 115 | static inline int test_and_clear_bit(int nr, volatile void *addr) |
| 37 | { | 116 | { |
| 38 | volatile unsigned long *ptr = addr; | 117 | volatile unsigned long *ptr = addr; |
diff --git a/include/asm-frv/page.h b/include/asm-frv/page.h index cacc045700de..c2c1e89e747d 100644 --- a/include/asm-frv/page.h +++ b/include/asm-frv/page.h | |||
| @@ -25,6 +25,7 @@ typedef struct { unsigned long ste[64];} pmd_t; | |||
| 25 | typedef struct { pmd_t pue[1]; } pud_t; | 25 | typedef struct { pmd_t pue[1]; } pud_t; |
| 26 | typedef struct { pud_t pge[1]; } pgd_t; | 26 | typedef struct { pud_t pge[1]; } pgd_t; |
| 27 | typedef struct { unsigned long pgprot; } pgprot_t; | 27 | typedef struct { unsigned long pgprot; } pgprot_t; |
| 28 | typedef struct page *pgtable_t; | ||
| 28 | 29 | ||
| 29 | #define pte_val(x) ((x).pte) | 30 | #define pte_val(x) ((x).pte) |
| 30 | #define pmd_val(x) ((x).ste[0]) | 31 | #define pmd_val(x) ((x).ste[0]) |
diff --git a/include/asm-frv/param.h b/include/asm-frv/param.h index 365653b1726c..6859dd503ed3 100644 --- a/include/asm-frv/param.h +++ b/include/asm-frv/param.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | #define _ASM_PARAM_H | 2 | #define _ASM_PARAM_H |
| 3 | 3 | ||
| 4 | #ifdef __KERNEL__ | 4 | #ifdef __KERNEL__ |
| 5 | #define HZ 1000 /* Internal kernel timer frequency */ | 5 | #define HZ CONFIG_HZ /* Internal kernel timer frequency */ |
| 6 | #define USER_HZ 100 /* .. some user interfaces are in "ticks" */ | 6 | #define USER_HZ 100 /* .. some user interfaces are in "ticks" */ |
| 7 | #define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | 7 | #define CLOCKS_PER_SEC (USER_HZ) /* like times() */ |
| 8 | #endif | 8 | #endif |
diff --git a/include/asm-frv/pgalloc.h b/include/asm-frv/pgalloc.h index e89620ef08ca..971e6addb009 100644 --- a/include/asm-frv/pgalloc.h +++ b/include/asm-frv/pgalloc.h | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | do { \ | 25 | do { \ |
| 26 | __set_pmd((PMD), page_to_pfn(PAGE) << PAGE_SHIFT | _PAGE_TABLE); \ | 26 | __set_pmd((PMD), page_to_pfn(PAGE) << PAGE_SHIFT | _PAGE_TABLE); \ |
| 27 | } while(0) | 27 | } while(0) |
| 28 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 28 | 29 | ||
| 29 | /* | 30 | /* |
| 30 | * Allocate and free page tables. | 31 | * Allocate and free page tables. |
| @@ -35,19 +36,24 @@ extern void pgd_free(struct mm_struct *mm, pgd_t *); | |||
| 35 | 36 | ||
| 36 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); | 37 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); |
| 37 | 38 | ||
| 38 | extern struct page *pte_alloc_one(struct mm_struct *, unsigned long); | 39 | extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long); |
| 39 | 40 | ||
| 40 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | 41 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) |
| 41 | { | 42 | { |
| 42 | free_page((unsigned long)pte); | 43 | free_page((unsigned long)pte); |
| 43 | } | 44 | } |
| 44 | 45 | ||
| 45 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 46 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 46 | { | 47 | { |
| 48 | pgtable_page_dtor(pte); | ||
| 47 | __free_page(pte); | 49 | __free_page(pte); |
| 48 | } | 50 | } |
| 49 | 51 | ||
| 50 | #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) | 52 | #define __pte_free_tlb(tlb,pte) \ |
| 53 | do { \ | ||
| 54 | pgtable_page_dtor(pte); \ | ||
| 55 | tlb_remove_page((tlb),(pte)); \ | ||
| 56 | } while (0) | ||
| 51 | 57 | ||
| 52 | /* | 58 | /* |
| 53 | * allocating and freeing a pmd is trivial: the 1-entry pmd is | 59 | * allocating and freeing a pmd is trivial: the 1-entry pmd is |
diff --git a/include/asm-frv/posix_types.h b/include/asm-frv/posix_types.h index 73c2ba8d76b4..a9f1f5be0632 100644 --- a/include/asm-frv/posix_types.h +++ b/include/asm-frv/posix_types.h | |||
| @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; | |||
| 39 | #endif | 39 | #endif |
| 40 | 40 | ||
| 41 | typedef struct { | 41 | typedef struct { |
| 42 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 43 | int val[2]; | 42 | int val[2]; |
| 44 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 45 | int __val[2]; | ||
| 46 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 47 | } __kernel_fsid_t; | 43 | } __kernel_fsid_t; |
| 48 | 44 | ||
| 49 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 45 | #if defined(__KERNEL__) |
| 50 | 46 | ||
| 51 | #undef __FD_SET | 47 | #undef __FD_SET |
| 52 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) | 48 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) |
| @@ -60,7 +56,7 @@ typedef struct { | |||
| 60 | #undef __FD_ZERO | 56 | #undef __FD_ZERO |
| 61 | #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) | 57 | #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) |
| 62 | 58 | ||
| 63 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 59 | #endif /* defined(__KERNEL__) */ |
| 64 | 60 | ||
| 65 | #endif | 61 | #endif |
| 66 | 62 | ||
diff --git a/include/asm-frv/system.h b/include/asm-frv/system.h index 59be5443a68f..b400cea81487 100644 --- a/include/asm-frv/system.h +++ b/include/asm-frv/system.h | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | 14 | ||
| 15 | #include <linux/types.h> | 15 | #include <linux/types.h> |
| 16 | #include <linux/linkage.h> | 16 | #include <linux/linkage.h> |
| 17 | #include <linux/kernel.h> | ||
| 17 | 18 | ||
| 18 | struct thread_struct; | 19 | struct thread_struct; |
| 19 | 20 | ||
| @@ -276,7 +277,7 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr, | |||
| 276 | { | 277 | { |
| 277 | switch (size) { | 278 | switch (size) { |
| 278 | case 4: | 279 | case 4: |
| 279 | return cmpxchg(ptr, old, new); | 280 | return cmpxchg((unsigned long *)ptr, old, new); |
| 280 | default: | 281 | default: |
| 281 | return __cmpxchg_local_generic(ptr, old, new, size); | 282 | return __cmpxchg_local_generic(ptr, old, new, size); |
| 282 | } | 283 | } |
diff --git a/include/asm-generic/Kbuild.asm b/include/asm-generic/Kbuild.asm index 57ba60635959..fd9dcfd91c39 100644 --- a/include/asm-generic/Kbuild.asm +++ b/include/asm-generic/Kbuild.asm | |||
| @@ -1,4 +1,6 @@ | |||
| 1 | ifeq ($(wildcard include/asm-$(SRCARCH)/a.out.h),include/asm-$(SRCARCH)/a.out.h) | ||
| 1 | unifdef-y += a.out.h | 2 | unifdef-y += a.out.h |
| 3 | endif | ||
| 2 | unifdef-y += auxvec.h | 4 | unifdef-y += auxvec.h |
| 3 | unifdef-y += byteorder.h | 5 | unifdef-y += byteorder.h |
| 4 | unifdef-y += errno.h | 6 | unifdef-y += errno.h |
diff --git a/include/asm-generic/iomap.h b/include/asm-generic/iomap.h index cde592fca441..67dc84cd1343 100644 --- a/include/asm-generic/iomap.h +++ b/include/asm-generic/iomap.h | |||
| @@ -25,17 +25,17 @@ | |||
| 25 | * in the low address range. Architectures for which this is not | 25 | * in the low address range. Architectures for which this is not |
| 26 | * true can't use this generic implementation. | 26 | * true can't use this generic implementation. |
| 27 | */ | 27 | */ |
| 28 | extern unsigned int fastcall ioread8(void __iomem *); | 28 | extern unsigned int ioread8(void __iomem *); |
| 29 | extern unsigned int fastcall ioread16(void __iomem *); | 29 | extern unsigned int ioread16(void __iomem *); |
| 30 | extern unsigned int fastcall ioread16be(void __iomem *); | 30 | extern unsigned int ioread16be(void __iomem *); |
| 31 | extern unsigned int fastcall ioread32(void __iomem *); | 31 | extern unsigned int ioread32(void __iomem *); |
| 32 | extern unsigned int fastcall ioread32be(void __iomem *); | 32 | extern unsigned int ioread32be(void __iomem *); |
| 33 | 33 | ||
| 34 | extern void fastcall iowrite8(u8, void __iomem *); | 34 | extern void iowrite8(u8, void __iomem *); |
| 35 | extern void fastcall iowrite16(u16, void __iomem *); | 35 | extern void iowrite16(u16, void __iomem *); |
| 36 | extern void fastcall iowrite16be(u16, void __iomem *); | 36 | extern void iowrite16be(u16, void __iomem *); |
| 37 | extern void fastcall iowrite32(u32, void __iomem *); | 37 | extern void iowrite32(u32, void __iomem *); |
| 38 | extern void fastcall iowrite32be(u32, void __iomem *); | 38 | extern void iowrite32be(u32, void __iomem *); |
| 39 | 39 | ||
| 40 | /* | 40 | /* |
| 41 | * "string" versions of the above. Note that they | 41 | * "string" versions of the above. Note that they |
| @@ -48,13 +48,13 @@ extern void fastcall iowrite32be(u32, void __iomem *); | |||
| 48 | * memory across multiple ports, use "memcpy_toio()" | 48 | * memory across multiple ports, use "memcpy_toio()" |
| 49 | * and friends. | 49 | * and friends. |
| 50 | */ | 50 | */ |
| 51 | extern void fastcall ioread8_rep(void __iomem *port, void *buf, unsigned long count); | 51 | extern void ioread8_rep(void __iomem *port, void *buf, unsigned long count); |
| 52 | extern void fastcall ioread16_rep(void __iomem *port, void *buf, unsigned long count); | 52 | extern void ioread16_rep(void __iomem *port, void *buf, unsigned long count); |
| 53 | extern void fastcall ioread32_rep(void __iomem *port, void *buf, unsigned long count); | 53 | extern void ioread32_rep(void __iomem *port, void *buf, unsigned long count); |
| 54 | 54 | ||
| 55 | extern void fastcall iowrite8_rep(void __iomem *port, const void *buf, unsigned long count); | 55 | extern void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count); |
| 56 | extern void fastcall iowrite16_rep(void __iomem *port, const void *buf, unsigned long count); | 56 | extern void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count); |
| 57 | extern void fastcall iowrite32_rep(void __iomem *port, const void *buf, unsigned long count); | 57 | extern void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count); |
| 58 | 58 | ||
| 59 | /* Create a virtual mapping cookie for an IO port range */ | 59 | /* Create a virtual mapping cookie for an IO port range */ |
| 60 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | 60 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); |
diff --git a/include/asm-generic/mutex-dec.h b/include/asm-generic/mutex-dec.h index 0134151656af..ed108be6743f 100644 --- a/include/asm-generic/mutex-dec.h +++ b/include/asm-generic/mutex-dec.h | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | * 1 even when the "1" assertion wasn't true. | 18 | * 1 even when the "1" assertion wasn't true. |
| 19 | */ | 19 | */ |
| 20 | static inline void | 20 | static inline void |
| 21 | __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | 21 | __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *)) |
| 22 | { | 22 | { |
| 23 | if (unlikely(atomic_dec_return(count) < 0)) | 23 | if (unlikely(atomic_dec_return(count) < 0)) |
| 24 | fail_fn(count); | 24 | fail_fn(count); |
| @@ -37,7 +37,7 @@ __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | |||
| 37 | * or anything the slow path function returns. | 37 | * or anything the slow path function returns. |
| 38 | */ | 38 | */ |
| 39 | static inline int | 39 | static inline int |
| 40 | __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *)) | 40 | __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) |
| 41 | { | 41 | { |
| 42 | if (unlikely(atomic_dec_return(count) < 0)) | 42 | if (unlikely(atomic_dec_return(count) < 0)) |
| 43 | return fail_fn(count); | 43 | return fail_fn(count); |
| @@ -61,7 +61,7 @@ __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t * | |||
| 61 | * to return 0 otherwise. | 61 | * to return 0 otherwise. |
| 62 | */ | 62 | */ |
| 63 | static inline void | 63 | static inline void |
| 64 | __mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | 64 | __mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *)) |
| 65 | { | 65 | { |
| 66 | smp_mb(); | 66 | smp_mb(); |
| 67 | if (unlikely(atomic_inc_return(count) <= 0)) | 67 | if (unlikely(atomic_inc_return(count) <= 0)) |
diff --git a/include/asm-generic/mutex-xchg.h b/include/asm-generic/mutex-xchg.h index 6a7e8c141b53..7b9cd2cbfebe 100644 --- a/include/asm-generic/mutex-xchg.h +++ b/include/asm-generic/mutex-xchg.h | |||
| @@ -23,7 +23,7 @@ | |||
| 23 | * even when the "1" assertion wasn't true. | 23 | * even when the "1" assertion wasn't true. |
| 24 | */ | 24 | */ |
| 25 | static inline void | 25 | static inline void |
| 26 | __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | 26 | __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *)) |
| 27 | { | 27 | { |
| 28 | if (unlikely(atomic_xchg(count, 0) != 1)) | 28 | if (unlikely(atomic_xchg(count, 0) != 1)) |
| 29 | fail_fn(count); | 29 | fail_fn(count); |
| @@ -42,7 +42,7 @@ __mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | |||
| 42 | * or anything the slow path function returns | 42 | * or anything the slow path function returns |
| 43 | */ | 43 | */ |
| 44 | static inline int | 44 | static inline int |
| 45 | __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *)) | 45 | __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *)) |
| 46 | { | 46 | { |
| 47 | if (unlikely(atomic_xchg(count, 0) != 1)) | 47 | if (unlikely(atomic_xchg(count, 0) != 1)) |
| 48 | return fail_fn(count); | 48 | return fail_fn(count); |
| @@ -65,7 +65,7 @@ __mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t * | |||
| 65 | * to return 0 otherwise. | 65 | * to return 0 otherwise. |
| 66 | */ | 66 | */ |
| 67 | static inline void | 67 | static inline void |
| 68 | __mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *)) | 68 | __mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *)) |
| 69 | { | 69 | { |
| 70 | smp_mb(); | 70 | smp_mb(); |
| 71 | if (unlikely(atomic_xchg(count, 1) != 0)) | 71 | if (unlikely(atomic_xchg(count, 1) != 0)) |
diff --git a/include/asm-generic/termios.h b/include/asm-generic/termios.h index 33dca30a3c45..7d39ecc92d94 100644 --- a/include/asm-generic/termios.h +++ b/include/asm-generic/termios.h | |||
| @@ -61,8 +61,14 @@ static inline int kernel_termios_to_user_termio(struct termio __user *termio, | |||
| 61 | return 0; | 61 | return 0; |
| 62 | } | 62 | } |
| 63 | 63 | ||
| 64 | #ifndef user_termios_to_kernel_termios | ||
| 64 | #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) | 65 | #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) |
| 66 | #endif | ||
| 67 | |||
| 68 | #ifndef kernel_termios_to_user_termios | ||
| 65 | #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) | 69 | #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) |
| 70 | #endif | ||
| 71 | |||
| 66 | #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) | 72 | #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) |
| 67 | #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) | 73 | #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) |
| 68 | 74 | ||
diff --git a/include/asm-h8300/a.out.h b/include/asm-h8300/a.out.h index aa5d22778235..ded780f0a492 100644 --- a/include/asm-h8300/a.out.h +++ b/include/asm-h8300/a.out.h | |||
| @@ -17,11 +17,4 @@ struct exec | |||
| 17 | #define N_DRSIZE(a) ((a).a_drsize) | 17 | #define N_DRSIZE(a) ((a).a_drsize) |
| 18 | #define N_SYMSIZE(a) ((a).a_syms) | 18 | #define N_SYMSIZE(a) ((a).a_syms) |
| 19 | 19 | ||
| 20 | #ifdef __KERNEL__ | ||
| 21 | |||
| 22 | #define STACK_TOP TASK_SIZE | ||
| 23 | #define STACK_TOP_MAX STACK_TOP | ||
| 24 | |||
| 25 | #endif | ||
| 26 | |||
| 27 | #endif /* __H8300_A_OUT_H__ */ | 20 | #endif /* __H8300_A_OUT_H__ */ |
diff --git a/include/asm-h8300/param.h b/include/asm-h8300/param.h index c25806ed1fb3..04f64f100379 100644 --- a/include/asm-h8300/param.h +++ b/include/asm-h8300/param.h | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | 3 | ||
| 4 | 4 | ||
| 5 | #ifndef HZ | 5 | #ifndef HZ |
| 6 | #define HZ 100 | 6 | #define HZ CONFIG_HZ |
| 7 | #endif | 7 | #endif |
| 8 | 8 | ||
| 9 | #ifdef __KERNEL__ | 9 | #ifdef __KERNEL__ |
diff --git a/include/asm-h8300/posix_types.h b/include/asm-h8300/posix_types.h index 7de94b1fd0e5..5c553927fc53 100644 --- a/include/asm-h8300/posix_types.h +++ b/include/asm-h8300/posix_types.h | |||
| @@ -38,14 +38,10 @@ typedef long long __kernel_loff_t; | |||
| 38 | #endif | 38 | #endif |
| 39 | 39 | ||
| 40 | typedef struct { | 40 | typedef struct { |
| 41 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 42 | int val[2]; | 41 | int val[2]; |
| 43 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 44 | int __val[2]; | ||
| 45 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 46 | } __kernel_fsid_t; | 42 | } __kernel_fsid_t; |
| 47 | 43 | ||
| 48 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 44 | #if defined(__KERNEL__) |
| 49 | 45 | ||
| 50 | #undef __FD_SET | 46 | #undef __FD_SET |
| 51 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) | 47 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) |
| @@ -59,6 +55,6 @@ typedef struct { | |||
| 59 | #undef __FD_ZERO | 55 | #undef __FD_ZERO |
| 60 | #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) | 56 | #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) |
| 61 | 57 | ||
| 62 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 58 | #endif /* defined(__KERNEL__) */ |
| 63 | 59 | ||
| 64 | #endif | 60 | #endif |
diff --git a/include/asm-h8300/processor.h b/include/asm-h8300/processor.h index 49fc886a6232..69e8a34eb6d5 100644 --- a/include/asm-h8300/processor.h +++ b/include/asm-h8300/processor.h | |||
| @@ -39,6 +39,11 @@ static inline void wrusp(unsigned long usp) { | |||
| 39 | */ | 39 | */ |
| 40 | #define TASK_SIZE (0xFFFFFFFFUL) | 40 | #define TASK_SIZE (0xFFFFFFFFUL) |
| 41 | 41 | ||
| 42 | #ifdef __KERNEL__ | ||
| 43 | #define STACK_TOP TASK_SIZE | ||
| 44 | #define STACK_TOP_MAX STACK_TOP | ||
| 45 | #endif | ||
| 46 | |||
| 42 | /* | 47 | /* |
| 43 | * This decides where the kernel will search for a free chunk of vm | 48 | * This decides where the kernel will search for a free chunk of vm |
| 44 | * space during mmap's. We won't be using it | 49 | * space during mmap's. We won't be using it |
diff --git a/include/asm-ia64/a.out.h b/include/asm-ia64/a.out.h index 7293ac1df3ab..193dcfb67596 100644 --- a/include/asm-ia64/a.out.h +++ b/include/asm-ia64/a.out.h | |||
| @@ -29,7 +29,4 @@ struct exec { | |||
| 29 | #define N_SYMSIZE(x) 0 | 29 | #define N_SYMSIZE(x) 0 |
| 30 | #define N_TXTOFF(x) 0 | 30 | #define N_TXTOFF(x) 0 |
| 31 | 31 | ||
| 32 | #ifdef __KERNEL__ | ||
| 33 | #include <asm/ustack.h> | ||
| 34 | #endif | ||
| 35 | #endif /* _ASM_IA64_A_OUT_H */ | 32 | #endif /* _ASM_IA64_A_OUT_H */ |
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h index 8a8aa3fd7cd4..4999a6c63775 100644 --- a/include/asm-ia64/page.h +++ b/include/asm-ia64/page.h | |||
| @@ -185,6 +185,7 @@ get_order (unsigned long size) | |||
| 185 | #endif | 185 | #endif |
| 186 | typedef struct { unsigned long pgd; } pgd_t; | 186 | typedef struct { unsigned long pgd; } pgd_t; |
| 187 | typedef struct { unsigned long pgprot; } pgprot_t; | 187 | typedef struct { unsigned long pgprot; } pgprot_t; |
| 188 | typedef struct page *pgtable_t; | ||
| 188 | 189 | ||
| 189 | # define pte_val(x) ((x).pte) | 190 | # define pte_val(x) ((x).pte) |
| 190 | # define pmd_val(x) ((x).pmd) | 191 | # define pmd_val(x) ((x).pmd) |
| @@ -206,6 +207,7 @@ get_order (unsigned long size) | |||
| 206 | typedef unsigned long pmd_t; | 207 | typedef unsigned long pmd_t; |
| 207 | typedef unsigned long pgd_t; | 208 | typedef unsigned long pgd_t; |
| 208 | typedef unsigned long pgprot_t; | 209 | typedef unsigned long pgprot_t; |
| 210 | typedef struct page *pgtable_t; | ||
| 209 | # endif | 211 | # endif |
| 210 | 212 | ||
| 211 | # define pte_val(x) (x) | 213 | # define pte_val(x) (x) |
diff --git a/include/asm-ia64/pgalloc.h b/include/asm-ia64/pgalloc.h index 556d988123ac..b9ac1a6fc216 100644 --- a/include/asm-ia64/pgalloc.h +++ b/include/asm-ia64/pgalloc.h | |||
| @@ -70,10 +70,11 @@ static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd) | |||
| 70 | #define __pmd_free_tlb(tlb, pmd) pmd_free((tlb)->mm, pmd) | 70 | #define __pmd_free_tlb(tlb, pmd) pmd_free((tlb)->mm, pmd) |
| 71 | 71 | ||
| 72 | static inline void | 72 | static inline void |
| 73 | pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, struct page *pte) | 73 | pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, pgtable_t pte) |
| 74 | { | 74 | { |
| 75 | pmd_val(*pmd_entry) = page_to_phys(pte); | 75 | pmd_val(*pmd_entry) = page_to_phys(pte); |
| 76 | } | 76 | } |
| 77 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 77 | 78 | ||
| 78 | static inline void | 79 | static inline void |
| 79 | pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte) | 80 | pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte) |
| @@ -81,11 +82,17 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte) | |||
| 81 | pmd_val(*pmd_entry) = __pa(pte); | 82 | pmd_val(*pmd_entry) = __pa(pte); |
| 82 | } | 83 | } |
| 83 | 84 | ||
| 84 | static inline struct page *pte_alloc_one(struct mm_struct *mm, | 85 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr) |
| 85 | unsigned long addr) | ||
| 86 | { | 86 | { |
| 87 | void *pg = quicklist_alloc(0, GFP_KERNEL, NULL); | 87 | struct page *page; |
| 88 | return pg ? virt_to_page(pg) : NULL; | 88 | void *pg; |
| 89 | |||
| 90 | pg = quicklist_alloc(0, GFP_KERNEL, NULL); | ||
| 91 | if (!pg) | ||
| 92 | return NULL; | ||
| 93 | page = virt_to_page(pg); | ||
| 94 | pgtable_page_ctor(page); | ||
| 95 | return page; | ||
| 89 | } | 96 | } |
| 90 | 97 | ||
| 91 | static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, | 98 | static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, |
| @@ -94,8 +101,9 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, | |||
| 94 | return quicklist_alloc(0, GFP_KERNEL, NULL); | 101 | return quicklist_alloc(0, GFP_KERNEL, NULL); |
| 95 | } | 102 | } |
| 96 | 103 | ||
| 97 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 104 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 98 | { | 105 | { |
| 106 | pgtable_page_dtor(pte); | ||
| 99 | quicklist_free_page(0, NULL, pte); | 107 | quicklist_free_page(0, NULL, pte); |
| 100 | } | 108 | } |
| 101 | 109 | ||
diff --git a/include/asm-ia64/ptrace.h b/include/asm-ia64/ptrace.h index f4ef87a36236..0bdce7dde1b0 100644 --- a/include/asm-ia64/ptrace.h +++ b/include/asm-ia64/ptrace.h | |||
| @@ -292,6 +292,7 @@ struct switch_stack { | |||
| 292 | unsigned long, long); | 292 | unsigned long, long); |
| 293 | extern void ia64_flush_fph (struct task_struct *); | 293 | extern void ia64_flush_fph (struct task_struct *); |
| 294 | extern void ia64_sync_fph (struct task_struct *); | 294 | extern void ia64_sync_fph (struct task_struct *); |
| 295 | extern void ia64_sync_krbs(void); | ||
| 295 | extern long ia64_sync_user_rbs (struct task_struct *, struct switch_stack *, | 296 | extern long ia64_sync_user_rbs (struct task_struct *, struct switch_stack *, |
| 296 | unsigned long, unsigned long); | 297 | unsigned long, unsigned long); |
| 297 | 298 | ||
| @@ -303,6 +304,16 @@ struct switch_stack { | |||
| 303 | extern void ia64_increment_ip (struct pt_regs *pt); | 304 | extern void ia64_increment_ip (struct pt_regs *pt); |
| 304 | extern void ia64_decrement_ip (struct pt_regs *pt); | 305 | extern void ia64_decrement_ip (struct pt_regs *pt); |
| 305 | 306 | ||
| 307 | extern void ia64_ptrace_stop(void); | ||
| 308 | #define arch_ptrace_stop(code, info) \ | ||
| 309 | ia64_ptrace_stop() | ||
| 310 | #define arch_ptrace_stop_needed(code, info) \ | ||
| 311 | (!test_thread_flag(TIF_RESTORE_RSE)) | ||
| 312 | |||
| 313 | extern void ptrace_attach_sync_user_rbs (struct task_struct *); | ||
| 314 | #define arch_ptrace_attach(child) \ | ||
| 315 | ptrace_attach_sync_user_rbs(child) | ||
| 316 | |||
| 306 | #endif /* !__KERNEL__ */ | 317 | #endif /* !__KERNEL__ */ |
| 307 | 318 | ||
| 308 | /* pt_all_user_regs is used for PTRACE_GETREGS PTRACE_SETREGS */ | 319 | /* pt_all_user_regs is used for PTRACE_GETREGS PTRACE_SETREGS */ |
diff --git a/include/asm-ia64/thread_info.h b/include/asm-ia64/thread_info.h index d16031e72efa..93d83cbe0c8c 100644 --- a/include/asm-ia64/thread_info.h +++ b/include/asm-ia64/thread_info.h | |||
| @@ -71,6 +71,9 @@ struct thread_info { | |||
| 71 | #define alloc_task_struct() ((struct task_struct *)__get_free_pages(GFP_KERNEL | __GFP_COMP, KERNEL_STACK_SIZE_ORDER)) | 71 | #define alloc_task_struct() ((struct task_struct *)__get_free_pages(GFP_KERNEL | __GFP_COMP, KERNEL_STACK_SIZE_ORDER)) |
| 72 | #define free_task_struct(tsk) free_pages((unsigned long) (tsk), KERNEL_STACK_SIZE_ORDER) | 72 | #define free_task_struct(tsk) free_pages((unsigned long) (tsk), KERNEL_STACK_SIZE_ORDER) |
| 73 | 73 | ||
| 74 | #define tsk_set_notify_resume(tsk) \ | ||
| 75 | set_ti_thread_flag(task_thread_info(tsk), TIF_NOTIFY_RESUME) | ||
| 76 | extern void tsk_clear_notify_resume(struct task_struct *tsk); | ||
| 74 | #endif /* !__ASSEMBLY */ | 77 | #endif /* !__ASSEMBLY */ |
| 75 | 78 | ||
| 76 | /* | 79 | /* |
| @@ -85,28 +88,30 @@ struct thread_info { | |||
| 85 | #define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */ | 88 | #define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */ |
| 86 | #define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ | 89 | #define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ |
| 87 | #define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ | 90 | #define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ |
| 88 | #define TIF_PERFMON_WORK 6 /* work for pfm_handle_work() */ | 91 | #define TIF_NOTIFY_RESUME 6 /* resumption notification requested */ |
| 89 | #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ | 92 | #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ |
| 90 | #define TIF_MEMDIE 17 | 93 | #define TIF_MEMDIE 17 |
| 91 | #define TIF_MCA_INIT 18 /* this task is processing MCA or INIT */ | 94 | #define TIF_MCA_INIT 18 /* this task is processing MCA or INIT */ |
| 92 | #define TIF_DB_DISABLED 19 /* debug trap disabled for fsyscall */ | 95 | #define TIF_DB_DISABLED 19 /* debug trap disabled for fsyscall */ |
| 93 | #define TIF_FREEZE 20 /* is freezing for suspend */ | 96 | #define TIF_FREEZE 20 /* is freezing for suspend */ |
| 97 | #define TIF_RESTORE_RSE 21 /* user RBS is newer than kernel RBS */ | ||
| 94 | 98 | ||
| 95 | #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) | 99 | #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) |
| 96 | #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) | 100 | #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) |
| 97 | #define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) | 101 | #define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) |
| 98 | #define _TIF_SYSCALL_TRACEAUDIT (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP) | 102 | #define _TIF_SYSCALL_TRACEAUDIT (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP) |
| 99 | #define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) | 103 | #define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) |
| 100 | #define _TIF_PERFMON_WORK (1 << TIF_PERFMON_WORK) | 104 | #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) |
| 101 | #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) | 105 | #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) |
| 102 | #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) | 106 | #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) |
| 103 | #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) | 107 | #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) |
| 104 | #define _TIF_MCA_INIT (1 << TIF_MCA_INIT) | 108 | #define _TIF_MCA_INIT (1 << TIF_MCA_INIT) |
| 105 | #define _TIF_DB_DISABLED (1 << TIF_DB_DISABLED) | 109 | #define _TIF_DB_DISABLED (1 << TIF_DB_DISABLED) |
| 106 | #define _TIF_FREEZE (1 << TIF_FREEZE) | 110 | #define _TIF_FREEZE (1 << TIF_FREEZE) |
| 111 | #define _TIF_RESTORE_RSE (1 << TIF_RESTORE_RSE) | ||
| 107 | 112 | ||
| 108 | /* "work to do on user-return" bits */ | 113 | /* "work to do on user-return" bits */ |
| 109 | #define TIF_ALLWORK_MASK (_TIF_SIGPENDING|_TIF_PERFMON_WORK|_TIF_SYSCALL_AUDIT|\ | 114 | #define TIF_ALLWORK_MASK (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME|_TIF_SYSCALL_AUDIT|\ |
| 110 | _TIF_NEED_RESCHED| _TIF_SYSCALL_TRACE|\ | 115 | _TIF_NEED_RESCHED| _TIF_SYSCALL_TRACE|\ |
| 111 | _TIF_RESTORE_SIGMASK) | 116 | _TIF_RESTORE_SIGMASK) |
| 112 | /* like TIF_ALLWORK_BITS but sans TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT */ | 117 | /* like TIF_ALLWORK_BITS but sans TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT */ |
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h index 315f8de950a2..e60314716122 100644 --- a/include/asm-ia64/unistd.h +++ b/include/asm-ia64/unistd.h | |||
| @@ -299,11 +299,14 @@ | |||
| 299 | #define __NR_signalfd 1307 | 299 | #define __NR_signalfd 1307 |
| 300 | #define __NR_timerfd 1308 | 300 | #define __NR_timerfd 1308 |
| 301 | #define __NR_eventfd 1309 | 301 | #define __NR_eventfd 1309 |
| 302 | #define __NR_timerfd_create 1310 | ||
| 303 | #define __NR_timerfd_settime 1311 | ||
| 304 | #define __NR_timerfd_gettime 1312 | ||
| 302 | 305 | ||
| 303 | #ifdef __KERNEL__ | 306 | #ifdef __KERNEL__ |
| 304 | 307 | ||
| 305 | 308 | ||
| 306 | #define NR_syscalls 286 /* length of syscall table */ | 309 | #define NR_syscalls 289 /* length of syscall table */ |
| 307 | 310 | ||
| 308 | /* | 311 | /* |
| 309 | * The following defines stop scripts/checksyscalls.sh from complaining about | 312 | * The following defines stop scripts/checksyscalls.sh from complaining about |
diff --git a/include/asm-m32r/a.out.h b/include/asm-m32r/a.out.h index 6a1b5d42f328..ab150f5c1666 100644 --- a/include/asm-m32r/a.out.h +++ b/include/asm-m32r/a.out.h | |||
| @@ -17,11 +17,4 @@ struct exec | |||
| 17 | #define N_DRSIZE(a) ((a).a_drsize) | 17 | #define N_DRSIZE(a) ((a).a_drsize) |
| 18 | #define N_SYMSIZE(a) ((a).a_syms) | 18 | #define N_SYMSIZE(a) ((a).a_syms) |
| 19 | 19 | ||
| 20 | #ifdef __KERNEL__ | ||
| 21 | |||
| 22 | #define STACK_TOP TASK_SIZE | ||
| 23 | #define STACK_TOP_MAX STACK_TOP | ||
| 24 | |||
| 25 | #endif | ||
| 26 | |||
| 27 | #endif /* _ASM_M32R_A_OUT_H */ | 20 | #endif /* _ASM_M32R_A_OUT_H */ |
diff --git a/include/asm-m32r/page.h b/include/asm-m32r/page.h index 05d43bbbf940..8a677f3fca68 100644 --- a/include/asm-m32r/page.h +++ b/include/asm-m32r/page.h | |||
| @@ -28,6 +28,7 @@ typedef struct { unsigned long pgd; } pgd_t; | |||
| 28 | #define PTE_MASK PAGE_MASK | 28 | #define PTE_MASK PAGE_MASK |
| 29 | 29 | ||
| 30 | typedef struct { unsigned long pgprot; } pgprot_t; | 30 | typedef struct { unsigned long pgprot; } pgprot_t; |
| 31 | typedef struct page *pgtable_t; | ||
| 31 | 32 | ||
| 32 | #define pmd_val(x) ((x).pmd) | 33 | #define pmd_val(x) ((x).pmd) |
| 33 | #define pgd_val(x) ((x).pgd) | 34 | #define pgd_val(x) ((x).pgd) |
diff --git a/include/asm-m32r/param.h b/include/asm-m32r/param.h index 3e14026e39cd..94c770196048 100644 --- a/include/asm-m32r/param.h +++ b/include/asm-m32r/param.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | #define _ASM_M32R_PARAM_H | 2 | #define _ASM_M32R_PARAM_H |
| 3 | 3 | ||
| 4 | #ifdef __KERNEL__ | 4 | #ifdef __KERNEL__ |
| 5 | # define HZ 100 /* Internal kernel timer frequency */ | 5 | # define HZ CONFIG_HZ /* Internal kernel timer frequency */ |
| 6 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ | 6 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ |
| 7 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | 7 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ |
| 8 | #endif | 8 | #endif |
diff --git a/include/asm-m32r/pgalloc.h b/include/asm-m32r/pgalloc.h index e5921adfad1b..f11a2b909cdb 100644 --- a/include/asm-m32r/pgalloc.h +++ b/include/asm-m32r/pgalloc.h | |||
| @@ -9,10 +9,11 @@ | |||
| 9 | set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))) | 9 | set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))) |
| 10 | 10 | ||
| 11 | static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd, | 11 | static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd, |
| 12 | struct page *pte) | 12 | pgtable_t pte) |
| 13 | { | 13 | { |
| 14 | set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte))); | 14 | set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte))); |
| 15 | } | 15 | } |
| 16 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 16 | 17 | ||
| 17 | /* | 18 | /* |
| 18 | * Allocate and free page tables. | 19 | * Allocate and free page tables. |
| @@ -37,12 +38,12 @@ static __inline__ pte_t *pte_alloc_one_kernel(struct mm_struct *mm, | |||
| 37 | return pte; | 38 | return pte; |
| 38 | } | 39 | } |
| 39 | 40 | ||
| 40 | static __inline__ struct page *pte_alloc_one(struct mm_struct *mm, | 41 | static __inline__ pgtable_t pte_alloc_one(struct mm_struct *mm, |
| 41 | unsigned long address) | 42 | unsigned long address) |
| 42 | { | 43 | { |
| 43 | struct page *pte = alloc_page(GFP_KERNEL|__GFP_ZERO); | 44 | struct page *pte = alloc_page(GFP_KERNEL|__GFP_ZERO); |
| 44 | 45 | ||
| 45 | 46 | pgtable_page_ctor(pte); | |
| 46 | return pte; | 47 | return pte; |
| 47 | } | 48 | } |
| 48 | 49 | ||
| @@ -51,8 +52,9 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 51 | free_page((unsigned long)pte); | 52 | free_page((unsigned long)pte); |
| 52 | } | 53 | } |
| 53 | 54 | ||
| 54 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 55 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 55 | { | 56 | { |
| 57 | pgtable_page_dtor(pte); | ||
| 56 | __free_page(pte); | 58 | __free_page(pte); |
| 57 | } | 59 | } |
| 58 | 60 | ||
diff --git a/include/asm-m32r/posix_types.h b/include/asm-m32r/posix_types.h index 1caac65d208f..b309c5858637 100644 --- a/include/asm-m32r/posix_types.h +++ b/include/asm-m32r/posix_types.h | |||
| @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; | |||
| 39 | #endif | 39 | #endif |
| 40 | 40 | ||
| 41 | typedef struct { | 41 | typedef struct { |
| 42 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 43 | int val[2]; | 42 | int val[2]; |
| 44 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 45 | int __val[2]; | ||
| 46 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 47 | } __kernel_fsid_t; | 43 | } __kernel_fsid_t; |
| 48 | 44 | ||
| 49 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 45 | #if defined(__KERNEL__) |
| 50 | 46 | ||
| 51 | #undef __FD_SET | 47 | #undef __FD_SET |
| 52 | static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) | 48 | static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) |
| @@ -117,6 +113,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *__p) | |||
| 117 | } | 113 | } |
| 118 | } | 114 | } |
| 119 | 115 | ||
| 120 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 116 | #endif /* defined(__KERNEL__) */ |
| 121 | 117 | ||
| 122 | #endif /* _ASM_M32R_POSIX_TYPES_H */ | 118 | #endif /* _ASM_M32R_POSIX_TYPES_H */ |
diff --git a/include/asm-m32r/processor.h b/include/asm-m32r/processor.h index 32755bf136de..1a997fc148a2 100644 --- a/include/asm-m32r/processor.h +++ b/include/asm-m32r/processor.h | |||
| @@ -60,6 +60,11 @@ extern struct cpuinfo_m32r cpu_data[]; | |||
| 60 | #define TASK_SIZE (0x00400000UL) | 60 | #define TASK_SIZE (0x00400000UL) |
| 61 | #endif | 61 | #endif |
| 62 | 62 | ||
| 63 | #ifdef __KERNEL__ | ||
| 64 | #define STACK_TOP TASK_SIZE | ||
| 65 | #define STACK_TOP_MAX STACK_TOP | ||
| 66 | #endif | ||
| 67 | |||
| 63 | /* This decides where the kernel will search for a free chunk of vm | 68 | /* This decides where the kernel will search for a free chunk of vm |
| 64 | * space during mmap's. | 69 | * space during mmap's. |
| 65 | */ | 70 | */ |
diff --git a/include/asm-m68k/a.out-core.h b/include/asm-m68k/a.out-core.h new file mode 100644 index 000000000000..f6bfc1d63ff6 --- /dev/null +++ b/include/asm-m68k/a.out-core.h | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | /* a.out coredump register dumper | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_A_OUT_CORE_H | ||
| 13 | #define _ASM_A_OUT_CORE_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #include <linux/user.h> | ||
| 18 | #include <linux/elfcore.h> | ||
| 19 | |||
| 20 | /* | ||
| 21 | * fill in the user structure for an a.out core dump | ||
| 22 | */ | ||
| 23 | static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) | ||
| 24 | { | ||
| 25 | struct switch_stack *sw; | ||
| 26 | |||
| 27 | /* changed the size calculations - should hopefully work better. lbt */ | ||
| 28 | dump->magic = CMAGIC; | ||
| 29 | dump->start_code = 0; | ||
| 30 | dump->start_stack = rdusp() & ~(PAGE_SIZE - 1); | ||
| 31 | dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT; | ||
| 32 | dump->u_dsize = ((unsigned long) (current->mm->brk + | ||
| 33 | (PAGE_SIZE-1))) >> PAGE_SHIFT; | ||
| 34 | dump->u_dsize -= dump->u_tsize; | ||
| 35 | dump->u_ssize = 0; | ||
| 36 | |||
| 37 | if (dump->start_stack < TASK_SIZE) | ||
| 38 | dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT; | ||
| 39 | |||
| 40 | dump->u_ar0 = offsetof(struct user, regs); | ||
| 41 | sw = ((struct switch_stack *)regs) - 1; | ||
| 42 | dump->regs.d1 = regs->d1; | ||
| 43 | dump->regs.d2 = regs->d2; | ||
| 44 | dump->regs.d3 = regs->d3; | ||
| 45 | dump->regs.d4 = regs->d4; | ||
| 46 | dump->regs.d5 = regs->d5; | ||
| 47 | dump->regs.d6 = sw->d6; | ||
| 48 | dump->regs.d7 = sw->d7; | ||
| 49 | dump->regs.a0 = regs->a0; | ||
| 50 | dump->regs.a1 = regs->a1; | ||
| 51 | dump->regs.a2 = regs->a2; | ||
| 52 | dump->regs.a3 = sw->a3; | ||
| 53 | dump->regs.a4 = sw->a4; | ||
| 54 | dump->regs.a5 = sw->a5; | ||
| 55 | dump->regs.a6 = sw->a6; | ||
| 56 | dump->regs.d0 = regs->d0; | ||
| 57 | dump->regs.orig_d0 = regs->orig_d0; | ||
| 58 | dump->regs.stkadj = regs->stkadj; | ||
| 59 | dump->regs.sr = regs->sr; | ||
| 60 | dump->regs.pc = regs->pc; | ||
| 61 | dump->regs.fmtvec = (regs->format << 12) | regs->vector; | ||
| 62 | /* dump floating point stuff */ | ||
| 63 | dump->u_fpvalid = dump_fpu (regs, &dump->m68kfp); | ||
| 64 | } | ||
| 65 | |||
| 66 | #endif /* __KERNEL__ */ | ||
| 67 | #endif /* _ASM_A_OUT_CORE_H */ | ||
diff --git a/include/asm-m68k/a.out.h b/include/asm-m68k/a.out.h index 6fc86a221a94..3885fe43432a 100644 --- a/include/asm-m68k/a.out.h +++ b/include/asm-m68k/a.out.h | |||
| @@ -17,11 +17,4 @@ struct exec | |||
| 17 | #define N_DRSIZE(a) ((a).a_drsize) | 17 | #define N_DRSIZE(a) ((a).a_drsize) |
| 18 | #define N_SYMSIZE(a) ((a).a_syms) | 18 | #define N_SYMSIZE(a) ((a).a_syms) |
| 19 | 19 | ||
| 20 | #ifdef __KERNEL__ | ||
| 21 | |||
| 22 | #define STACK_TOP TASK_SIZE | ||
| 23 | #define STACK_TOP_MAX STACK_TOP | ||
| 24 | |||
| 25 | #endif | ||
| 26 | |||
| 27 | #endif /* __M68K_A_OUT_H__ */ | 20 | #endif /* __M68K_A_OUT_H__ */ |
diff --git a/include/asm-m68k/motorola_pgalloc.h b/include/asm-m68k/motorola_pgalloc.h index 500ec9b8b189..d08bf6261df8 100644 --- a/include/asm-m68k/motorola_pgalloc.h +++ b/include/asm-m68k/motorola_pgalloc.h | |||
| @@ -7,7 +7,6 @@ | |||
| 7 | extern pmd_t *get_pointer_table(void); | 7 | extern pmd_t *get_pointer_table(void); |
| 8 | extern int free_pointer_table(pmd_t *); | 8 | extern int free_pointer_table(pmd_t *); |
| 9 | 9 | ||
| 10 | |||
| 11 | static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) | 10 | static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) |
| 12 | { | 11 | { |
| 13 | pte_t *pte; | 12 | pte_t *pte; |
| @@ -28,7 +27,7 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 28 | free_page((unsigned long) pte); | 27 | free_page((unsigned long) pte); |
| 29 | } | 28 | } |
| 30 | 29 | ||
| 31 | static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) | 30 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) |
| 32 | { | 31 | { |
| 33 | struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); | 32 | struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); |
| 34 | pte_t *pte; | 33 | pte_t *pte; |
| @@ -43,19 +42,21 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long add | |||
| 43 | nocache_page(pte); | 42 | nocache_page(pte); |
| 44 | } | 43 | } |
| 45 | kunmap(pte); | 44 | kunmap(pte); |
| 46 | 45 | pgtable_page_ctor(page); | |
| 47 | return page; | 46 | return page; |
| 48 | } | 47 | } |
| 49 | 48 | ||
| 50 | static inline void pte_free(struct mm_struct *mm, struct page *page) | 49 | static inline void pte_free(struct mm_struct *mm, pgtable_t page) |
| 51 | { | 50 | { |
| 51 | pgtable_page_dtor(page); | ||
| 52 | cache_page(kmap(page)); | 52 | cache_page(kmap(page)); |
| 53 | kunmap(page); | 53 | kunmap(page); |
| 54 | __free_page(page); | 54 | __free_page(page); |
| 55 | } | 55 | } |
| 56 | 56 | ||
| 57 | static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *page) | 57 | static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t page) |
| 58 | { | 58 | { |
| 59 | pgtable_page_dtor(page); | ||
| 59 | cache_page(kmap(page)); | 60 | cache_page(kmap(page)); |
| 60 | kunmap(page); | 61 | kunmap(page); |
| 61 | __free_page(page); | 62 | __free_page(page); |
| @@ -94,10 +95,11 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t * | |||
| 94 | pmd_set(pmd, pte); | 95 | pmd_set(pmd, pte); |
| 95 | } | 96 | } |
| 96 | 97 | ||
| 97 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page) | 98 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page) |
| 98 | { | 99 | { |
| 99 | pmd_set(pmd, page_address(page)); | 100 | pmd_set(pmd, page_address(page)); |
| 100 | } | 101 | } |
| 102 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 101 | 103 | ||
| 102 | static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmd) | 104 | static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmd) |
| 103 | { | 105 | { |
diff --git a/include/asm-m68k/page.h b/include/asm-m68k/page.h index 3f29e2a03a43..880c2cbff8a6 100644 --- a/include/asm-m68k/page.h +++ b/include/asm-m68k/page.h | |||
| @@ -91,6 +91,7 @@ typedef struct { unsigned long pte; } pte_t; | |||
| 91 | typedef struct { unsigned long pmd[16]; } pmd_t; | 91 | typedef struct { unsigned long pmd[16]; } pmd_t; |
| 92 | typedef struct { unsigned long pgd; } pgd_t; | 92 | typedef struct { unsigned long pgd; } pgd_t; |
| 93 | typedef struct { unsigned long pgprot; } pgprot_t; | 93 | typedef struct { unsigned long pgprot; } pgprot_t; |
| 94 | typedef struct page *pgtable_t; | ||
| 94 | 95 | ||
| 95 | #define pte_val(x) ((x).pte) | 96 | #define pte_val(x) ((x).pte) |
| 96 | #define pmd_val(x) ((&x)->pmd[0]) | 97 | #define pmd_val(x) ((&x)->pmd[0]) |
diff --git a/include/asm-m68k/param.h b/include/asm-m68k/param.h index 60f409d81658..536a27888358 100644 --- a/include/asm-m68k/param.h +++ b/include/asm-m68k/param.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | #define _M68K_PARAM_H | 2 | #define _M68K_PARAM_H |
| 3 | 3 | ||
| 4 | #ifdef __KERNEL__ | 4 | #ifdef __KERNEL__ |
| 5 | # define HZ 100 /* Internal kernel timer frequency */ | 5 | # define HZ CONFIG_HZ /* Internal kernel timer frequency */ |
| 6 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ | 6 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ |
| 7 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | 7 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ |
| 8 | #endif | 8 | #endif |
diff --git a/include/asm-m68k/posix_types.h b/include/asm-m68k/posix_types.h index fa166ee30286..63cdcc142d93 100644 --- a/include/asm-m68k/posix_types.h +++ b/include/asm-m68k/posix_types.h | |||
| @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; | |||
| 39 | #endif | 39 | #endif |
| 40 | 40 | ||
| 41 | typedef struct { | 41 | typedef struct { |
| 42 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 43 | int val[2]; | 42 | int val[2]; |
| 44 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 45 | int __val[2]; | ||
| 46 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 47 | } __kernel_fsid_t; | 43 | } __kernel_fsid_t; |
| 48 | 44 | ||
| 49 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 45 | #if defined(__KERNEL__) |
| 50 | 46 | ||
| 51 | #undef __FD_SET | 47 | #undef __FD_SET |
| 52 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) | 48 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) |
| @@ -60,6 +56,6 @@ typedef struct { | |||
| 60 | #undef __FD_ZERO | 56 | #undef __FD_ZERO |
| 61 | #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) | 57 | #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) |
| 62 | 58 | ||
| 63 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 59 | #endif /* defined(__KERNEL__) */ |
| 64 | 60 | ||
| 65 | #endif | 61 | #endif |
diff --git a/include/asm-m68k/processor.h b/include/asm-m68k/processor.h index 4453ec379c5d..1f61ef53f0e0 100644 --- a/include/asm-m68k/processor.h +++ b/include/asm-m68k/processor.h | |||
| @@ -41,6 +41,11 @@ static inline void wrusp(unsigned long usp) | |||
| 41 | #define TASK_SIZE (0x0E000000UL) | 41 | #define TASK_SIZE (0x0E000000UL) |
| 42 | #endif | 42 | #endif |
| 43 | 43 | ||
| 44 | #ifdef __KERNEL__ | ||
| 45 | #define STACK_TOP TASK_SIZE | ||
| 46 | #define STACK_TOP_MAX STACK_TOP | ||
| 47 | #endif | ||
| 48 | |||
| 44 | /* This decides where the kernel will search for a free chunk of vm | 49 | /* This decides where the kernel will search for a free chunk of vm |
| 45 | * space during mmap's. | 50 | * space during mmap's. |
| 46 | */ | 51 | */ |
diff --git a/include/asm-m68k/sun3_pgalloc.h b/include/asm-m68k/sun3_pgalloc.h index a5a91e72714b..d4c83f143816 100644 --- a/include/asm-m68k/sun3_pgalloc.h +++ b/include/asm-m68k/sun3_pgalloc.h | |||
| @@ -26,12 +26,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 26 | free_page((unsigned long) pte); | 26 | free_page((unsigned long) pte); |
| 27 | } | 27 | } |
| 28 | 28 | ||
| 29 | static inline void pte_free(struct mm_struct *mm, struct page *page) | 29 | static inline void pte_free(struct mm_struct *mm, pgtable_t page) |
| 30 | { | 30 | { |
| 31 | pgtable_page_dtor(page); | ||
| 31 | __free_page(page); | 32 | __free_page(page); |
| 32 | } | 33 | } |
| 33 | 34 | ||
| 34 | #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) | 35 | #define __pte_free_tlb(tlb,pte) \ |
| 36 | do { \ | ||
| 37 | pgtable_page_dtor(pte); \ | ||
| 38 | tlb_remove_page((tlb), pte); \ | ||
| 39 | } while (0) | ||
| 35 | 40 | ||
| 36 | static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, | 41 | static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, |
| 37 | unsigned long address) | 42 | unsigned long address) |
| @@ -45,8 +50,8 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, | |||
| 45 | return (pte_t *) (page); | 50 | return (pte_t *) (page); |
| 46 | } | 51 | } |
| 47 | 52 | ||
| 48 | static inline struct page *pte_alloc_one(struct mm_struct *mm, | 53 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, |
| 49 | unsigned long address) | 54 | unsigned long address) |
| 50 | { | 55 | { |
| 51 | struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0); | 56 | struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0); |
| 52 | 57 | ||
| @@ -54,6 +59,7 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, | |||
| 54 | return NULL; | 59 | return NULL; |
| 55 | 60 | ||
| 56 | clear_highpage(page); | 61 | clear_highpage(page); |
| 62 | pgtable_page_ctor(page); | ||
| 57 | return page; | 63 | return page; |
| 58 | 64 | ||
| 59 | } | 65 | } |
| @@ -63,10 +69,11 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t * | |||
| 63 | pmd_val(*pmd) = __pa((unsigned long)pte); | 69 | pmd_val(*pmd) = __pa((unsigned long)pte); |
| 64 | } | 70 | } |
| 65 | 71 | ||
| 66 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page) | 72 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page) |
| 67 | { | 73 | { |
| 68 | pmd_val(*pmd) = __pa((unsigned long)page_address(page)); | 74 | pmd_val(*pmd) = __pa((unsigned long)page_address(page)); |
| 69 | } | 75 | } |
| 76 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 70 | 77 | ||
| 71 | /* | 78 | /* |
| 72 | * allocating and freeing a pmd is trivial: the 1-entry pmd is | 79 | * allocating and freeing a pmd is trivial: the 1-entry pmd is |
diff --git a/include/asm-m68knommu/param.h b/include/asm-m68knommu/param.h index 4c9904d6512e..96c451018324 100644 --- a/include/asm-m68knommu/param.h +++ b/include/asm-m68knommu/param.h | |||
| @@ -1,13 +1,7 @@ | |||
| 1 | #ifndef _M68KNOMMU_PARAM_H | 1 | #ifndef _M68KNOMMU_PARAM_H |
| 2 | #define _M68KNOMMU_PARAM_H | 2 | #define _M68KNOMMU_PARAM_H |
| 3 | 3 | ||
| 4 | 4 | #define HZ CONFIG_HZ | |
| 5 | #if defined(CONFIG_CLEOPATRA) | ||
| 6 | #define HZ 1000 | ||
| 7 | #endif | ||
| 8 | #ifndef HZ | ||
| 9 | #define HZ 100 | ||
| 10 | #endif | ||
| 11 | 5 | ||
| 12 | #ifdef __KERNEL__ | 6 | #ifdef __KERNEL__ |
| 13 | #define USER_HZ HZ | 7 | #define USER_HZ HZ |
diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h index bf55a5b34bef..cad8371422ab 100644 --- a/include/asm-mips/a.out.h +++ b/include/asm-mips/a.out.h | |||
| @@ -32,17 +32,4 @@ struct exec | |||
| 32 | #define N_DRSIZE(a) ((a).a_drsize) | 32 | #define N_DRSIZE(a) ((a).a_drsize) |
| 33 | #define N_SYMSIZE(a) ((a).a_syms) | 33 | #define N_SYMSIZE(a) ((a).a_syms) |
| 34 | 34 | ||
| 35 | #ifdef __KERNEL__ | ||
| 36 | |||
| 37 | #ifdef CONFIG_32BIT | ||
| 38 | #define STACK_TOP TASK_SIZE | ||
| 39 | #endif | ||
| 40 | #ifdef CONFIG_64BIT | ||
| 41 | #define STACK_TOP \ | ||
| 42 | (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) | ||
| 43 | #endif | ||
| 44 | #define STACK_TOP_MAX TASK_SIZE | ||
| 45 | |||
| 46 | #endif | ||
| 47 | |||
| 48 | #endif /* _ASM_A_OUT_H */ | 35 | #endif /* _ASM_A_OUT_H */ |
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 635aa44d2290..8735aa0b8963 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h | |||
| @@ -90,6 +90,7 @@ typedef struct { unsigned long pte; } pte_t; | |||
| 90 | #define pte_val(x) ((x).pte) | 90 | #define pte_val(x) ((x).pte) |
| 91 | #define __pte(x) ((pte_t) { (x) } ) | 91 | #define __pte(x) ((pte_t) { (x) } ) |
| 92 | #endif | 92 | #endif |
| 93 | typedef struct page *pgtable_t; | ||
| 93 | 94 | ||
| 94 | /* | 95 | /* |
| 95 | * For 3-level pagetables we defines these ourselves, for 2-level the | 96 | * For 3-level pagetables we defines these ourselves, for 2-level the |
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index c4efeced8396..1275831dda29 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h | |||
| @@ -20,10 +20,11 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, | |||
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, | 22 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, |
| 23 | struct page *pte) | 23 | pgtable_t pte) |
| 24 | { | 24 | { |
| 25 | set_pmd(pmd, __pmd((unsigned long)page_address(pte))); | 25 | set_pmd(pmd, __pmd((unsigned long)page_address(pte))); |
| 26 | } | 26 | } |
| 27 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 27 | 28 | ||
| 28 | /* | 29 | /* |
| 29 | * Initialize a new pmd table with invalid pointers. | 30 | * Initialize a new pmd table with invalid pointers. |
| @@ -79,9 +80,10 @@ static inline struct page *pte_alloc_one(struct mm_struct *mm, | |||
| 79 | struct page *pte; | 80 | struct page *pte; |
| 80 | 81 | ||
| 81 | pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER); | 82 | pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER); |
| 82 | if (pte) | 83 | if (pte) { |
| 83 | clear_highpage(pte); | 84 | clear_highpage(pte); |
| 84 | 85 | pgtable_page_ctor(pte); | |
| 86 | } | ||
| 85 | return pte; | 87 | return pte; |
| 86 | } | 88 | } |
| 87 | 89 | ||
| @@ -90,12 +92,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 90 | free_pages((unsigned long)pte, PTE_ORDER); | 92 | free_pages((unsigned long)pte, PTE_ORDER); |
| 91 | } | 93 | } |
| 92 | 94 | ||
| 93 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 95 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 94 | { | 96 | { |
| 97 | pgtable_page_dtor(pte); | ||
| 95 | __free_pages(pte, PTE_ORDER); | 98 | __free_pages(pte, PTE_ORDER); |
| 96 | } | 99 | } |
| 97 | 100 | ||
| 98 | #define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte)) | 101 | #define __pte_free_tlb(tlb,pte) \ |
| 102 | do { \ | ||
| 103 | pgtable_page_dtor(pte); \ | ||
| 104 | tlb_remove_page((tlb), pte); \ | ||
| 105 | } while (0) | ||
| 99 | 106 | ||
| 100 | #ifdef CONFIG_32BIT | 107 | #ifdef CONFIG_32BIT |
| 101 | 108 | ||
diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h index c2e8a0070daf..c200102c8586 100644 --- a/include/asm-mips/posix_types.h +++ b/include/asm-mips/posix_types.h | |||
| @@ -69,7 +69,7 @@ typedef struct { | |||
| 69 | #endif | 69 | #endif |
| 70 | } __kernel_fsid_t; | 70 | } __kernel_fsid_t; |
| 71 | 71 | ||
| 72 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 72 | #if defined(__KERNEL__) |
| 73 | 73 | ||
| 74 | #undef __FD_SET | 74 | #undef __FD_SET |
| 75 | static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) | 75 | static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) |
| @@ -139,6 +139,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *__p) | |||
| 139 | } | 139 | } |
| 140 | } | 140 | } |
| 141 | 141 | ||
| 142 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 142 | #endif /* defined(__KERNEL__) */ |
| 143 | 143 | ||
| 144 | #endif /* _ASM_POSIX_TYPES_H */ | 144 | #endif /* _ASM_POSIX_TYPES_H */ |
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 36f42de59409..58cbac5a64e4 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h | |||
| @@ -39,6 +39,7 @@ extern unsigned int vced_count, vcei_count; | |||
| 39 | * so don't change it unless you know what you are doing. | 39 | * so don't change it unless you know what you are doing. |
| 40 | */ | 40 | */ |
| 41 | #define TASK_SIZE 0x7fff8000UL | 41 | #define TASK_SIZE 0x7fff8000UL |
| 42 | #define STACK_TOP TASK_SIZE | ||
| 42 | 43 | ||
| 43 | /* | 44 | /* |
| 44 | * This decides where the kernel will search for a free chunk of vm | 45 | * This decides where the kernel will search for a free chunk of vm |
| @@ -57,6 +58,8 @@ extern unsigned int vced_count, vcei_count; | |||
| 57 | */ | 58 | */ |
| 58 | #define TASK_SIZE32 0x7fff8000UL | 59 | #define TASK_SIZE32 0x7fff8000UL |
| 59 | #define TASK_SIZE 0x10000000000UL | 60 | #define TASK_SIZE 0x10000000000UL |
| 61 | #define STACK_TOP \ | ||
| 62 | (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) | ||
| 60 | 63 | ||
| 61 | /* | 64 | /* |
| 62 | * This decides where the kernel will search for a free chunk of vm | 65 | * This decides where the kernel will search for a free chunk of vm |
| @@ -69,6 +72,10 @@ extern unsigned int vced_count, vcei_count; | |||
| 69 | (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) | 72 | (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) |
| 70 | #endif | 73 | #endif |
| 71 | 74 | ||
| 75 | #ifdef __KERNEL__ | ||
| 76 | #define STACK_TOP_MAX TASK_SIZE | ||
| 77 | #endif | ||
| 78 | |||
| 72 | #define NUM_FPU_REGS 32 | 79 | #define NUM_FPU_REGS 32 |
| 73 | 80 | ||
| 74 | typedef __u64 fpureg_t; | 81 | typedef __u64 fpureg_t; |
diff --git a/include/asm-mn10300/.gitignore b/include/asm-mn10300/.gitignore new file mode 100644 index 000000000000..0f87ba790e26 --- /dev/null +++ b/include/asm-mn10300/.gitignore | |||
| @@ -0,0 +1,2 @@ | |||
| 1 | proc | ||
| 2 | unit | ||
diff --git a/include/asm-mn10300/Kbuild b/include/asm-mn10300/Kbuild new file mode 100644 index 000000000000..79384c537dc6 --- /dev/null +++ b/include/asm-mn10300/Kbuild | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | include include/asm-generic/Kbuild.asm | ||
| 2 | |||
| 3 | unifdef-y += termios.h | ||
| 4 | unifdef-y += ptrace.h | ||
| 5 | unifdef-y += page.h | ||
diff --git a/include/asm-mn10300/atomic.h b/include/asm-mn10300/atomic.h new file mode 100644 index 000000000000..27c9690b9574 --- /dev/null +++ b/include/asm-mn10300/atomic.h | |||
| @@ -0,0 +1,166 @@ | |||
| 1 | /* MN10300 Atomic counter operations | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_ATOMIC_H | ||
| 12 | #define _ASM_ATOMIC_H | ||
| 13 | |||
| 14 | #ifdef CONFIG_SMP | ||
| 15 | #error not SMP safe | ||
| 16 | #endif | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Atomic operations that C can't guarantee us. Useful for | ||
| 20 | * resource counting etc.. | ||
| 21 | */ | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Make sure gcc doesn't try to be clever and move things around | ||
| 25 | * on us. We need to use _exactly_ the address the user gave us, | ||
| 26 | * not some alias that contains the same information. | ||
| 27 | */ | ||
| 28 | typedef struct { | ||
| 29 | int counter; | ||
| 30 | } atomic_t; | ||
| 31 | |||
| 32 | #define ATOMIC_INIT(i) { (i) } | ||
| 33 | |||
| 34 | #ifdef __KERNEL__ | ||
| 35 | |||
| 36 | /** | ||
| 37 | * atomic_read - read atomic variable | ||
| 38 | * @v: pointer of type atomic_t | ||
| 39 | * | ||
| 40 | * Atomically reads the value of @v. Note that the guaranteed | ||
| 41 | * useful range of an atomic_t is only 24 bits. | ||
| 42 | */ | ||
| 43 | #define atomic_read(v) ((v)->counter) | ||
| 44 | |||
| 45 | /** | ||
| 46 | * atomic_set - set atomic variable | ||
| 47 | * @v: pointer of type atomic_t | ||
| 48 | * @i: required value | ||
| 49 | * | ||
| 50 | * Atomically sets the value of @v to @i. Note that the guaranteed | ||
| 51 | * useful range of an atomic_t is only 24 bits. | ||
| 52 | */ | ||
| 53 | #define atomic_set(v, i) (((v)->counter) = (i)) | ||
| 54 | |||
| 55 | #include <asm/system.h> | ||
| 56 | |||
| 57 | /** | ||
| 58 | * atomic_add_return - add integer to atomic variable | ||
| 59 | * @i: integer value to add | ||
| 60 | * @v: pointer of type atomic_t | ||
| 61 | * | ||
| 62 | * Atomically adds @i to @v and returns the result | ||
| 63 | * Note that the guaranteed useful range of an atomic_t is only 24 bits. | ||
| 64 | */ | ||
| 65 | static inline int atomic_add_return(int i, atomic_t *v) | ||
| 66 | { | ||
| 67 | unsigned long flags; | ||
| 68 | int temp; | ||
| 69 | |||
| 70 | local_irq_save(flags); | ||
| 71 | temp = v->counter; | ||
| 72 | temp += i; | ||
| 73 | v->counter = temp; | ||
| 74 | local_irq_restore(flags); | ||
| 75 | |||
| 76 | return temp; | ||
| 77 | } | ||
| 78 | |||
| 79 | /** | ||
| 80 | * atomic_sub_return - subtract integer from atomic variable | ||
| 81 | * @i: integer value to subtract | ||
| 82 | * @v: pointer of type atomic_t | ||
| 83 | * | ||
| 84 | * Atomically subtracts @i from @v and returns the result | ||
| 85 | * Note that the guaranteed useful range of an atomic_t is only 24 bits. | ||
| 86 | */ | ||
| 87 | static inline int atomic_sub_return(int i, atomic_t *v) | ||
| 88 | { | ||
| 89 | unsigned long flags; | ||
| 90 | int temp; | ||
| 91 | |||
| 92 | local_irq_save(flags); | ||
| 93 | temp = v->counter; | ||
| 94 | temp -= i; | ||
| 95 | v->counter = temp; | ||
| 96 | local_irq_restore(flags); | ||
| 97 | |||
| 98 | return temp; | ||
| 99 | } | ||
| 100 | |||
| 101 | static inline int atomic_add_negative(int i, atomic_t *v) | ||
| 102 | { | ||
| 103 | return atomic_add_return(i, v) < 0; | ||
| 104 | } | ||
| 105 | |||
| 106 | static inline void atomic_add(int i, atomic_t *v) | ||
| 107 | { | ||
| 108 | atomic_add_return(i, v); | ||
| 109 | } | ||
| 110 | |||
| 111 | static inline void atomic_sub(int i, atomic_t *v) | ||
| 112 | { | ||
| 113 | atomic_sub_return(i, v); | ||
| 114 | } | ||
| 115 | |||
| 116 | static inline void atomic_inc(atomic_t *v) | ||
| 117 | { | ||
| 118 | atomic_add_return(1, v); | ||
| 119 | } | ||
| 120 | |||
| 121 | static inline void atomic_dec(atomic_t *v) | ||
| 122 | { | ||
| 123 | atomic_sub_return(1, v); | ||
| 124 | } | ||
| 125 | |||
| 126 | #define atomic_dec_return(v) atomic_sub_return(1, (v)) | ||
| 127 | #define atomic_inc_return(v) atomic_add_return(1, (v)) | ||
| 128 | |||
| 129 | #define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0) | ||
| 130 | #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) | ||
| 131 | #define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) | ||
| 132 | |||
| 133 | #define atomic_add_unless(v, a, u) \ | ||
| 134 | ({ \ | ||
| 135 | int c, old; \ | ||
| 136 | c = atomic_read(v); \ | ||
| 137 | while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \ | ||
| 138 | c = old; \ | ||
| 139 | c != (u); \ | ||
| 140 | }) | ||
| 141 | |||
| 142 | #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) | ||
| 143 | |||
| 144 | static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) | ||
| 145 | { | ||
| 146 | unsigned long flags; | ||
| 147 | |||
| 148 | mask = ~mask; | ||
| 149 | local_irq_save(flags); | ||
| 150 | *addr &= mask; | ||
| 151 | local_irq_restore(flags); | ||
| 152 | } | ||
| 153 | |||
| 154 | #define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v))) | ||
| 155 | #define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new))) | ||
| 156 | |||
| 157 | /* Atomic operations are already serializing on MN10300??? */ | ||
| 158 | #define smp_mb__before_atomic_dec() barrier() | ||
| 159 | #define smp_mb__after_atomic_dec() barrier() | ||
| 160 | #define smp_mb__before_atomic_inc() barrier() | ||
| 161 | #define smp_mb__after_atomic_inc() barrier() | ||
| 162 | |||
| 163 | #include <asm-generic/atomic.h> | ||
| 164 | |||
| 165 | #endif /* __KERNEL__ */ | ||
| 166 | #endif /* _ASM_ATOMIC_H */ | ||
diff --git a/include/asm-mn10300/auxvec.h b/include/asm-mn10300/auxvec.h new file mode 100644 index 000000000000..4fdb60b2ae39 --- /dev/null +++ b/include/asm-mn10300/auxvec.h | |||
| @@ -0,0 +1,4 @@ | |||
| 1 | #ifndef _ASM_AUXVEC_H | ||
| 2 | #define _ASM_AUXVEC_H | ||
| 3 | |||
| 4 | #endif | ||
diff --git a/include/asm-mn10300/bitops.h b/include/asm-mn10300/bitops.h new file mode 100644 index 000000000000..cc6d40c05cf3 --- /dev/null +++ b/include/asm-mn10300/bitops.h | |||
| @@ -0,0 +1,229 @@ | |||
| 1 | /* MN10300 bit operations | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | * | ||
| 11 | * These have to be done with inline assembly: that way the bit-setting | ||
| 12 | * is guaranteed to be atomic. All bit operations return 0 if the bit | ||
| 13 | * was cleared before the operation and != 0 if it was not. | ||
| 14 | * | ||
| 15 | * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). | ||
| 16 | */ | ||
| 17 | #ifndef __ASM_BITOPS_H | ||
| 18 | #define __ASM_BITOPS_H | ||
| 19 | |||
| 20 | #include <asm/cpu-regs.h> | ||
| 21 | |||
| 22 | #define smp_mb__before_clear_bit() barrier() | ||
| 23 | #define smp_mb__after_clear_bit() barrier() | ||
| 24 | |||
| 25 | /* | ||
| 26 | * set bit | ||
| 27 | */ | ||
| 28 | #define __set_bit(nr, addr) \ | ||
| 29 | ({ \ | ||
| 30 | volatile unsigned char *_a = (unsigned char *)(addr); \ | ||
| 31 | const unsigned shift = (nr) & 7; \ | ||
| 32 | _a += (nr) >> 3; \ | ||
| 33 | \ | ||
| 34 | asm volatile("bset %2,(%1) # set_bit reg" \ | ||
| 35 | : "=m"(*_a) \ | ||
| 36 | : "a"(_a), "d"(1 << shift), "m"(*_a) \ | ||
| 37 | : "memory", "cc"); \ | ||
| 38 | }) | ||
| 39 | |||
| 40 | #define set_bit(nr, addr) __set_bit((nr), (addr)) | ||
| 41 | |||
| 42 | /* | ||
| 43 | * clear bit | ||
| 44 | */ | ||
| 45 | #define ___clear_bit(nr, addr) \ | ||
| 46 | ({ \ | ||
| 47 | volatile unsigned char *_a = (unsigned char *)(addr); \ | ||
| 48 | const unsigned shift = (nr) & 7; \ | ||
| 49 | _a += (nr) >> 3; \ | ||
| 50 | \ | ||
| 51 | asm volatile("bclr %2,(%1) # clear_bit reg" \ | ||
| 52 | : "=m"(*_a) \ | ||
| 53 | : "a"(_a), "d"(1 << shift), "m"(*_a) \ | ||
| 54 | : "memory", "cc"); \ | ||
| 55 | }) | ||
| 56 | |||
| 57 | #define clear_bit(nr, addr) ___clear_bit((nr), (addr)) | ||
| 58 | |||
| 59 | |||
| 60 | static inline void __clear_bit(int nr, volatile void *addr) | ||
| 61 | { | ||
| 62 | unsigned int *a = (unsigned int *) addr; | ||
| 63 | int mask; | ||
| 64 | |||
| 65 | a += nr >> 5; | ||
| 66 | mask = 1 << (nr & 0x1f); | ||
| 67 | *a &= ~mask; | ||
| 68 | } | ||
| 69 | |||
| 70 | /* | ||
| 71 | * test bit | ||
| 72 | */ | ||
| 73 | static inline int test_bit(int nr, const volatile void *addr) | ||
| 74 | { | ||
| 75 | return 1UL & (((const unsigned int *) addr)[nr >> 5] >> (nr & 31)); | ||
| 76 | } | ||
| 77 | |||
| 78 | /* | ||
| 79 | * change bit | ||
| 80 | */ | ||
| 81 | static inline void __change_bit(int nr, volatile void *addr) | ||
| 82 | { | ||
| 83 | int mask; | ||
| 84 | unsigned int *a = (unsigned int *) addr; | ||
| 85 | |||
| 86 | a += nr >> 5; | ||
| 87 | mask = 1 << (nr & 0x1f); | ||
| 88 | *a ^= mask; | ||
| 89 | } | ||
| 90 | |||
| 91 | extern void change_bit(int nr, volatile void *addr); | ||
| 92 | |||
| 93 | /* | ||
| 94 | * test and set bit | ||
| 95 | */ | ||
| 96 | #define __test_and_set_bit(nr,addr) \ | ||
| 97 | ({ \ | ||
| 98 | volatile unsigned char *_a = (unsigned char *)(addr); \ | ||
| 99 | const unsigned shift = (nr) & 7; \ | ||
| 100 | unsigned epsw; \ | ||
| 101 | _a += (nr) >> 3; \ | ||
| 102 | \ | ||
| 103 | asm volatile("bset %3,(%2) # test_set_bit reg\n" \ | ||
| 104 | "mov epsw,%1" \ | ||
| 105 | : "=m"(*_a), "=d"(epsw) \ | ||
| 106 | : "a"(_a), "d"(1 << shift), "m"(*_a) \ | ||
| 107 | : "memory", "cc"); \ | ||
| 108 | \ | ||
| 109 | !(epsw & EPSW_FLAG_Z); \ | ||
| 110 | }) | ||
| 111 | |||
| 112 | #define test_and_set_bit(nr, addr) __test_and_set_bit((nr), (addr)) | ||
| 113 | |||
| 114 | /* | ||
| 115 | * test and clear bit | ||
| 116 | */ | ||
| 117 | #define __test_and_clear_bit(nr, addr) \ | ||
| 118 | ({ \ | ||
| 119 | volatile unsigned char *_a = (unsigned char *)(addr); \ | ||
| 120 | const unsigned shift = (nr) & 7; \ | ||
| 121 | unsigned epsw; \ | ||
| 122 | _a += (nr) >> 3; \ | ||
| 123 | \ | ||
| 124 | asm volatile("bclr %3,(%2) # test_clear_bit reg\n" \ | ||
| 125 | "mov epsw,%1" \ | ||
| 126 | : "=m"(*_a), "=d"(epsw) \ | ||
| 127 | : "a"(_a), "d"(1 << shift), "m"(*_a) \ | ||
| 128 | : "memory", "cc"); \ | ||
| 129 | \ | ||
| 130 | !(epsw & EPSW_FLAG_Z); \ | ||
| 131 | }) | ||
| 132 | |||
| 133 | #define test_and_clear_bit(nr, addr) __test_and_clear_bit((nr), (addr)) | ||
| 134 | |||
| 135 | /* | ||
| 136 | * test and change bit | ||
| 137 | */ | ||
| 138 | static inline int __test_and_change_bit(int nr, volatile void *addr) | ||
| 139 | { | ||
| 140 | int mask, retval; | ||
| 141 | unsigned int *a = (unsigned int *)addr; | ||
| 142 | |||
| 143 | a += nr >> 5; | ||
| 144 | mask = 1 << (nr & 0x1f); | ||
| 145 | retval = (mask & *a) != 0; | ||
| 146 | *a ^= mask; | ||
| 147 | |||
| 148 | return retval; | ||
| 149 | } | ||
| 150 | |||
| 151 | extern int test_and_change_bit(int nr, volatile void *addr); | ||
| 152 | |||
| 153 | #include <asm-generic/bitops/lock.h> | ||
| 154 | |||
| 155 | #ifdef __KERNEL__ | ||
| 156 | |||
| 157 | /** | ||
| 158 | * __ffs - find first bit set | ||
| 159 | * @x: the word to search | ||
| 160 | * | ||
| 161 | * - return 31..0 to indicate bit 31..0 most least significant bit set | ||
| 162 | * - if no bits are set in x, the result is undefined | ||
| 163 | */ | ||
| 164 | static inline __attribute__((const)) | ||
| 165 | unsigned long __ffs(unsigned long x) | ||
| 166 | { | ||
| 167 | int bit; | ||
| 168 | asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(x & -x)); | ||
| 169 | return bit; | ||
| 170 | } | ||
| 171 | |||
| 172 | /* | ||
| 173 | * special slimline version of fls() for calculating ilog2_u32() | ||
| 174 | * - note: no protection against n == 0 | ||
| 175 | */ | ||
| 176 | static inline __attribute__((const)) | ||
| 177 | int __ilog2_u32(u32 n) | ||
| 178 | { | ||
| 179 | int bit; | ||
| 180 | asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(n)); | ||
| 181 | return bit; | ||
| 182 | } | ||
| 183 | |||
| 184 | /** | ||
| 185 | * fls - find last bit set | ||
| 186 | * @x: the word to search | ||
| 187 | * | ||
| 188 | * This is defined the same way as ffs: | ||
| 189 | * - return 32..1 to indicate bit 31..0 most significant bit set | ||
| 190 | * - return 0 to indicate no bits set | ||
| 191 | */ | ||
| 192 | static inline __attribute__((const)) | ||
| 193 | int fls(int x) | ||
| 194 | { | ||
| 195 | return (x != 0) ? __ilog2_u32(x) + 1 : 0; | ||
| 196 | } | ||
| 197 | |||
| 198 | /** | ||
| 199 | * ffs - find first bit set | ||
| 200 | * @x: the word to search | ||
| 201 | * | ||
| 202 | * - return 32..1 to indicate bit 31..0 most least significant bit set | ||
| 203 | * - return 0 to indicate no bits set | ||
| 204 | */ | ||
| 205 | static inline __attribute__((const)) | ||
| 206 | int ffs(int x) | ||
| 207 | { | ||
| 208 | /* Note: (x & -x) gives us a mask that is the least significant | ||
| 209 | * (rightmost) 1-bit of the value in x. | ||
| 210 | */ | ||
| 211 | return fls(x & -x); | ||
| 212 | } | ||
| 213 | |||
| 214 | #include <asm-generic/bitops/ffz.h> | ||
| 215 | #include <asm-generic/bitops/fls64.h> | ||
| 216 | #include <asm-generic/bitops/find.h> | ||
| 217 | #include <asm-generic/bitops/sched.h> | ||
| 218 | #include <asm-generic/bitops/hweight.h> | ||
| 219 | |||
| 220 | #define ext2_set_bit_atomic(lock, nr, addr) \ | ||
| 221 | test_and_set_bit((nr) ^ 0x18, (addr)) | ||
| 222 | #define ext2_clear_bit_atomic(lock, nr, addr) \ | ||
| 223 | test_and_clear_bit((nr) ^ 0x18, (addr)) | ||
| 224 | |||
| 225 | #include <asm-generic/bitops/ext2-non-atomic.h> | ||
| 226 | #include <asm-generic/bitops/minix-le.h> | ||
| 227 | |||
| 228 | #endif /* __KERNEL__ */ | ||
| 229 | #endif /* __ASM_BITOPS_H */ | ||
diff --git a/include/asm-mn10300/bug.h b/include/asm-mn10300/bug.h new file mode 100644 index 000000000000..4fcf3384e259 --- /dev/null +++ b/include/asm-mn10300/bug.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* MN10300 Kernel bug reporting | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_BUG_H | ||
| 12 | #define _ASM_BUG_H | ||
| 13 | |||
| 14 | /* | ||
| 15 | * Tell the user there is some problem. | ||
| 16 | */ | ||
| 17 | #define _debug_bug_trap() \ | ||
| 18 | do { \ | ||
| 19 | asm volatile( \ | ||
| 20 | " syscall 15 \n" \ | ||
| 21 | "0: \n" \ | ||
| 22 | " .section __bug_table,\"a\" \n" \ | ||
| 23 | " .long 0b,%0,%1 \n" \ | ||
| 24 | " .previous \n" \ | ||
| 25 | : \ | ||
| 26 | : "i"(__FILE__), "i"(__LINE__) \ | ||
| 27 | ); \ | ||
| 28 | } while (0) | ||
| 29 | |||
| 30 | #define BUG() _debug_bug_trap() | ||
| 31 | |||
| 32 | #define HAVE_ARCH_BUG | ||
| 33 | #include <asm-generic/bug.h> | ||
| 34 | |||
| 35 | #endif /* _ASM_BUG_H */ | ||
diff --git a/include/asm-mn10300/bugs.h b/include/asm-mn10300/bugs.h new file mode 100644 index 000000000000..31c8bc592b47 --- /dev/null +++ b/include/asm-mn10300/bugs.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | /* MN10300 Checks for architecture-dependent bugs | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_BUGS_H | ||
| 12 | #define _ASM_BUGS_H | ||
| 13 | |||
| 14 | #include <asm/processor.h> | ||
| 15 | |||
| 16 | static inline void __init check_bugs(void) | ||
| 17 | { | ||
| 18 | } | ||
| 19 | |||
| 20 | #endif /* _ASM_BUGS_H */ | ||
diff --git a/include/asm-mn10300/busctl-regs.h b/include/asm-mn10300/busctl-regs.h new file mode 100644 index 000000000000..1632aef73401 --- /dev/null +++ b/include/asm-mn10300/busctl-regs.h | |||
| @@ -0,0 +1,151 @@ | |||
| 1 | /* AM33v2 on-board bus controller registers | ||
| 2 | * | ||
| 3 | * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_BUSCTL_REGS_H | ||
| 13 | #define _ASM_BUSCTL_REGS_H | ||
| 14 | |||
| 15 | #include <asm/cpu-regs.h> | ||
| 16 | |||
| 17 | #ifdef __KERNEL__ | ||
| 18 | |||
| 19 | /* bus controller registers */ | ||
| 20 | #define BCCR __SYSREG(0xc0002000, u32) /* bus controller control reg */ | ||
| 21 | #define BCCR_B0AD 0x00000003 /* block 0 (80000000-83ffffff) bus allocation */ | ||
| 22 | #define BCCR_B1AD 0x0000000c /* block 1 (84000000-87ffffff) bus allocation */ | ||
| 23 | #define BCCR_B2AD 0x00000030 /* block 2 (88000000-8bffffff) bus allocation */ | ||
| 24 | #define BCCR_B3AD 0x000000c0 /* block 3 (8c000000-8fffffff) bus allocation */ | ||
| 25 | #define BCCR_B4AD 0x00000300 /* block 4 (90000000-93ffffff) bus allocation */ | ||
| 26 | #define BCCR_B5AD 0x00000c00 /* block 5 (94000000-97ffffff) bus allocation */ | ||
| 27 | #define BCCR_B6AD 0x00003000 /* block 6 (98000000-9bffffff) bus allocation */ | ||
| 28 | #define BCCR_B7AD 0x0000c000 /* block 7 (9c000000-9fffffff) bus allocation */ | ||
| 29 | #define BCCR_BxAD_EXBUS 0x0 /* - direct to system bus controller */ | ||
| 30 | #define BCCR_BxAD_OPEXBUS 0x1 /* - direct to memory bus controller */ | ||
| 31 | #define BCCR_BxAD_OCMBUS 0x2 /* - direct to on chip memory */ | ||
| 32 | #define BCCR_API 0x00070000 /* bus arbitration priority */ | ||
| 33 | #define BCCR_API_DMACICD 0x00000000 /* - DMA > CI > CD */ | ||
| 34 | #define BCCR_API_DMACDCI 0x00010000 /* - DMA > CD > CI */ | ||
| 35 | #define BCCR_API_CICDDMA 0x00020000 /* - CI > CD > DMA */ | ||
| 36 | #define BCCR_API_CDCIDMA 0x00030000 /* - CD > CI > DMA */ | ||
| 37 | #define BCCR_API_ROUNDROBIN 0x00040000 /* - round robin */ | ||
| 38 | #define BCCR_BEPRI_DMACICD 0x00c00000 /* bus error address priority */ | ||
| 39 | #define BCCR_BEPRI_DMACDCI 0x00000000 /* - DMA > CI > CD */ | ||
| 40 | #define BCCR_BEPRI_CICDDMA 0x00400000 /* - DMA > CD > CI */ | ||
| 41 | #define BCCR_BEPRI_CDCIDMA 0x00800000 /* - CI > CD > DMA */ | ||
| 42 | #define BCCR_BEPRI 0x00c00000 /* - CD > CI > DMA */ | ||
| 43 | #define BCCR_TMON 0x03000000 /* timeout value settings */ | ||
| 44 | #define BCCR_TMON_16IOCLK 0x00000000 /* - 16 IOCLK cycles */ | ||
| 45 | #define BCCR_TMON_256IOCLK 0x01000000 /* - 256 IOCLK cycles */ | ||
| 46 | #define BCCR_TMON_4096IOCLK 0x02000000 /* - 4096 IOCLK cycles */ | ||
| 47 | #define BCCR_TMON_65536IOCLK 0x03000000 /* - 65536 IOCLK cycles */ | ||
| 48 | #define BCCR_TMOE 0x10000000 /* timeout detection enable */ | ||
| 49 | |||
| 50 | #define BCBERR __SYSREG(0xc0002010, u32) /* bus error source reg */ | ||
| 51 | #define BCBERR_BESB 0x0000001f /* erroneous access destination space */ | ||
| 52 | #define BCBERR_BESB_MON 0x00000001 /* - monitor space */ | ||
| 53 | #define BCBERR_BESB_IO 0x00000002 /* - IO bus */ | ||
| 54 | #define BCBERR_BESB_EX 0x00000004 /* - EX bus */ | ||
| 55 | #define BCBERR_BESB_OPEX 0x00000008 /* - OpEX bus */ | ||
| 56 | #define BCBERR_BESB_OCM 0x00000010 /* - on chip memory */ | ||
| 57 | #define BCBERR_BERW 0x00000100 /* type of access */ | ||
| 58 | #define BCBERR_BERW_WRITE 0x00000000 /* - write */ | ||
| 59 | #define BCBERR_BERW_READ 0x00000100 /* - read */ | ||
| 60 | #define BCBERR_BESD 0x00000200 /* error detector */ | ||
| 61 | #define BCBERR_BESD_BCU 0x00000000 /* - BCU detected error */ | ||
| 62 | #define BCBERR_BESD_SLAVE_BUS 0x00000200 /* - slave bus detected error */ | ||
| 63 | #define BCBERR_BEBST 0x00000400 /* type of access */ | ||
| 64 | #define BCBERR_BEBST_SINGLE 0x00000000 /* - single */ | ||
| 65 | #define BCBERR_BEBST_BURST 0x00000400 /* - burst */ | ||
| 66 | #define BCBERR_BEME 0x00000800 /* multiple bus error flag */ | ||
| 67 | #define BCBERR_BEMR 0x00007000 /* master bus that caused the error */ | ||
| 68 | #define BCBERR_BEMR_NOERROR 0x00000000 /* - no error */ | ||
| 69 | #define BCBERR_BEMR_CI 0x00001000 /* - CPU instruction fetch bus caused error */ | ||
| 70 | #define BCBERR_BEMR_CD 0x00002000 /* - CPU data bus caused error */ | ||
| 71 | #define BCBERR_BEMR_DMA 0x00004000 /* - DMA bus caused error */ | ||
| 72 | |||
| 73 | #define BCBEAR __SYSREGC(0xc0002020, u32) /* bus error address reg */ | ||
| 74 | |||
| 75 | /* system bus controller registers */ | ||
| 76 | #define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32) /* SBC base addr regs */ | ||
| 77 | #define SBBASE_BE 0x00000001 /* bank enable */ | ||
| 78 | #define SBBASE_BAM 0x0000fffe /* bank address mask [31:17] */ | ||
| 79 | #define SBBASE_BBA 0xfffe0000 /* bank base address [31:17] */ | ||
| 80 | |||
| 81 | #define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32) /* SBC bank ctrl0 regs */ | ||
| 82 | #define SBCNTRL0_WEH 0x00000f00 /* write enable hold */ | ||
| 83 | #define SBCNTRL0_REH 0x0000f000 /* read enable hold */ | ||
| 84 | #define SBCNTRL0_RWH 0x000f0000 /* SRW signal hold */ | ||
| 85 | #define SBCNTRL0_CSH 0x00f00000 /* chip select hold */ | ||
| 86 | #define SBCNTRL0_DAH 0x0f000000 /* data hold */ | ||
| 87 | #define SBCNTRL0_ADH 0xf0000000 /* address hold */ | ||
| 88 | |||
| 89 | #define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32) /* SBC bank ctrl1 regs */ | ||
| 90 | #define SBCNTRL1_WED 0x00000f00 /* write enable delay */ | ||
| 91 | #define SBCNTRL1_RED 0x0000f000 /* read enable delay */ | ||
| 92 | #define SBCNTRL1_RWD 0x000f0000 /* SRW signal delay */ | ||
| 93 | #define SBCNTRL1_ASW 0x00f00000 /* address strobe width */ | ||
| 94 | #define SBCNTRL1_CSD 0x0f000000 /* chip select delay */ | ||
| 95 | #define SBCNTRL1_ASD 0xf0000000 /* address strobe delay */ | ||
| 96 | |||
| 97 | #define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32) /* SBC bank ctrl2 regs */ | ||
| 98 | #define SBCNTRL2_WC 0x000000ff /* wait count */ | ||
| 99 | #define SBCNTRL2_BWC 0x00000f00 /* burst wait count */ | ||
| 100 | #define SBCNTRL2_WM 0x01000000 /* wait mode setting */ | ||
| 101 | #define SBCNTRL2_WM_FIXEDWAIT 0x00000000 /* - fixed wait access */ | ||
| 102 | #define SBCNTRL2_WM_HANDSHAKE 0x01000000 /* - handshake access */ | ||
| 103 | #define SBCNTRL2_BM 0x02000000 /* bus synchronisation mode */ | ||
| 104 | #define SBCNTRL2_BM_SYNC 0x00000000 /* - synchronous mode */ | ||
| 105 | #define SBCNTRL2_BM_ASYNC 0x02000000 /* - asynchronous mode */ | ||
| 106 | #define SBCNTRL2_BW 0x04000000 /* bus width */ | ||
| 107 | #define SBCNTRL2_BW_32 0x00000000 /* - 32 bits */ | ||
| 108 | #define SBCNTRL2_BW_16 0x04000000 /* - 16 bits */ | ||
| 109 | #define SBCNTRL2_RWINV 0x08000000 /* R/W signal invert polarity */ | ||
| 110 | #define SBCNTRL2_RWINV_NORM 0x00000000 /* - normal (read high) */ | ||
| 111 | #define SBCNTRL2_RWINV_INV 0x08000000 /* - inverted (read low) */ | ||
| 112 | #define SBCNTRL2_BT 0x70000000 /* bus type setting */ | ||
| 113 | #define SBCNTRL2_BT_SRAM 0x00000000 /* - SRAM interface */ | ||
| 114 | #define SBCNTRL2_BT_ADMUX 0x00000000 /* - addr/data multiplexed interface */ | ||
| 115 | #define SBCNTRL2_BT_BROM 0x00000000 /* - burst ROM interface */ | ||
| 116 | #define SBCNTRL2_BTSE 0x80000000 /* burst enable */ | ||
| 117 | |||
| 118 | /* memory bus controller */ | ||
| 119 | #define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32) /* MBC base addr regs */ | ||
| 120 | #define SDBASE_CE 0x00000001 /* chip enable */ | ||
| 121 | #define SDBASE_CBAM 0x0000fff0 /* chip base address mask [31:20] */ | ||
| 122 | #define SDBASE_CBAM_SHIFT 16 | ||
| 123 | #define SDBASE_CBA 0xfff00000 /* chip base address [31:20] */ | ||
| 124 | |||
| 125 | #define SDRAMBUS __SYSREG(0xda000000, u32) /* bus mode control reg */ | ||
| 126 | #define SDRAMBUS_REFEN 0x00000004 /* refresh enable */ | ||
| 127 | #define SDRAMBUS_TRC 0x00000018 /* refresh command delay time */ | ||
| 128 | #define SDRAMBUS_BSTPT 0x00000020 /* burst stop command enable */ | ||
| 129 | #define SDRAMBUS_PONSEQ 0x00000040 /* power on sequence */ | ||
| 130 | #define SDRAMBUS_SELFREQ 0x00000080 /* self-refresh mode request */ | ||
| 131 | #define SDRAMBUS_SELFON 0x00000100 /* self-refresh mode on */ | ||
| 132 | #define SDRAMBUS_SIZE 0x00030000 /* SDRAM size */ | ||
| 133 | #define SDRAMBUS_SIZE_64Mbit 0x00010000 /* 64Mbit SDRAM (x16) */ | ||
| 134 | #define SDRAMBUS_SIZE_128Mbit 0x00020000 /* 128Mbit SDRAM (x16) */ | ||
| 135 | #define SDRAMBUS_SIZE_256Mbit 0x00030000 /* 256Mbit SDRAM (x16) */ | ||
| 136 | #define SDRAMBUS_TRASWAIT 0x000c0000 /* row address precharge command cycle number */ | ||
| 137 | #define SDRAMBUS_REFNUM 0x00300000 /* refresh command number */ | ||
| 138 | #define SDRAMBUS_BSTWAIT 0x00c00000 /* burst stop command cycle */ | ||
| 139 | #define SDRAMBUS_SETWAIT 0x03000000 /* mode register setting command cycle */ | ||
| 140 | #define SDRAMBUS_PREWAIT 0x0c000000 /* precharge command cycle */ | ||
| 141 | #define SDRAMBUS_RASLATE 0x30000000 /* RAS latency */ | ||
| 142 | #define SDRAMBUS_CASLATE 0xc0000000 /* CAS latency */ | ||
| 143 | |||
| 144 | #define SDREFCNT __SYSREG(0xda000004, u32) /* refresh period reg */ | ||
| 145 | #define SDREFCNT_PERI 0x00000fff /* refresh period */ | ||
| 146 | |||
| 147 | #define SDSHDW __SYSREG(0xda000010, u32) /* test reg */ | ||
| 148 | |||
| 149 | #endif /* __KERNEL__ */ | ||
| 150 | |||
| 151 | #endif /* _ASM_BUSCTL_REGS_H */ | ||
diff --git a/include/asm-mn10300/byteorder.h b/include/asm-mn10300/byteorder.h new file mode 100644 index 000000000000..3c993cc625f8 --- /dev/null +++ b/include/asm-mn10300/byteorder.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /* MN10300 Byte-order primitive construction | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_BYTEORDER_H | ||
| 12 | #define _ASM_BYTEORDER_H | ||
| 13 | |||
| 14 | #include <asm/types.h> | ||
| 15 | |||
| 16 | #ifdef __GNUC__ | ||
| 17 | |||
| 18 | static inline __attribute__((const)) | ||
| 19 | __u32 ___arch__swab32(__u32 x) | ||
| 20 | { | ||
| 21 | __u32 ret; | ||
| 22 | asm("swap %1,%0" : "=r" (ret) : "r" (x)); | ||
| 23 | return ret; | ||
| 24 | } | ||
| 25 | |||
| 26 | static inline __attribute__((const)) | ||
| 27 | __u16 ___arch__swab16(__u16 x) | ||
| 28 | { | ||
| 29 | __u16 ret; | ||
| 30 | asm("swaph %1,%0" : "=r" (ret) : "r" (x)); | ||
| 31 | return ret; | ||
| 32 | } | ||
| 33 | |||
| 34 | #define __arch__swab32(x) ___arch__swab32(x) | ||
| 35 | #define __arch__swab16(x) ___arch__swab16(x) | ||
| 36 | |||
| 37 | #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) | ||
| 38 | # define __BYTEORDER_HAS_U64__ | ||
| 39 | # define __SWAB_64_THRU_32__ | ||
| 40 | #endif | ||
| 41 | |||
| 42 | #endif /* __GNUC__ */ | ||
| 43 | |||
| 44 | #include <linux/byteorder/little_endian.h> | ||
| 45 | |||
| 46 | #endif /* _ASM_BYTEORDER_H */ | ||
diff --git a/include/asm-mn10300/cache.h b/include/asm-mn10300/cache.h new file mode 100644 index 000000000000..9e01122208a9 --- /dev/null +++ b/include/asm-mn10300/cache.h | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* MN10300 cache management registers | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_CACHE_H | ||
| 13 | #define _ASM_CACHE_H | ||
| 14 | |||
| 15 | #include <asm/cpu-regs.h> | ||
| 16 | #include <asm/proc/cache.h> | ||
| 17 | |||
| 18 | #ifndef __ASSEMBLY__ | ||
| 19 | #define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES) | ||
| 20 | #else | ||
| 21 | #define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES | ||
| 22 | #endif | ||
| 23 | |||
| 24 | /* data cache purge registers | ||
| 25 | * - read from the register to unconditionally purge that cache line | ||
| 26 | * - write address & 0xffffff00 to conditionally purge that cache line | ||
| 27 | * - clear LSB to request invalidation as well | ||
| 28 | */ | ||
| 29 | #define DCACHE_PURGE(WAY, ENTRY) \ | ||
| 30 | __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \ | ||
| 31 | (ENTRY) * L1_CACHE_BYTES, u32) | ||
| 32 | |||
| 33 | #define DCACHE_PURGE_WAY0(ENTRY) \ | ||
| 34 | __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) | ||
| 35 | #define DCACHE_PURGE_WAY1(ENTRY) \ | ||
| 36 | __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) | ||
| 37 | #define DCACHE_PURGE_WAY2(ENTRY) \ | ||
| 38 | __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) | ||
| 39 | #define DCACHE_PURGE_WAY3(ENTRY) \ | ||
| 40 | __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) | ||
| 41 | |||
| 42 | /* instruction cache access registers */ | ||
| 43 | #define ICACHE_DATA(WAY, ENTRY, OFF) \ | ||
| 44 | __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32) | ||
| 45 | #define ICACHE_TAG(WAY, ENTRY) \ | ||
| 46 | __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32) | ||
| 47 | |||
| 48 | /* instruction cache access registers */ | ||
| 49 | #define DCACHE_DATA(WAY, ENTRY, OFF) \ | ||
| 50 | __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32) | ||
| 51 | #define DCACHE_TAG(WAY, ENTRY) \ | ||
| 52 | __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32) | ||
| 53 | |||
| 54 | #endif /* _ASM_CACHE_H */ | ||
diff --git a/include/asm-mn10300/cacheflush.h b/include/asm-mn10300/cacheflush.h new file mode 100644 index 000000000000..2db746a251f8 --- /dev/null +++ b/include/asm-mn10300/cacheflush.h | |||
| @@ -0,0 +1,116 @@ | |||
| 1 | /* MN10300 Cache flushing | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_CACHEFLUSH_H | ||
| 12 | #define _ASM_CACHEFLUSH_H | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | |||
| 16 | /* Keep includes the same across arches. */ | ||
| 17 | #include <linux/mm.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * virtually-indexed cache managment (our cache is physically indexed) | ||
| 21 | */ | ||
| 22 | #define flush_cache_all() do {} while (0) | ||
| 23 | #define flush_cache_mm(mm) do {} while (0) | ||
| 24 | #define flush_cache_dup_mm(mm) do {} while (0) | ||
| 25 | #define flush_cache_range(mm, start, end) do {} while (0) | ||
| 26 | #define flush_cache_page(vma, vmaddr, pfn) do {} while (0) | ||
| 27 | #define flush_cache_vmap(start, end) do {} while (0) | ||
| 28 | #define flush_cache_vunmap(start, end) do {} while (0) | ||
| 29 | #define flush_dcache_page(page) do {} while (0) | ||
| 30 | #define flush_dcache_mmap_lock(mapping) do {} while (0) | ||
| 31 | #define flush_dcache_mmap_unlock(mapping) do {} while (0) | ||
| 32 | |||
| 33 | /* | ||
| 34 | * physically-indexed cache managment | ||
| 35 | */ | ||
| 36 | #ifndef CONFIG_MN10300_CACHE_DISABLED | ||
| 37 | |||
| 38 | extern void flush_icache_range(unsigned long start, unsigned long end); | ||
| 39 | extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg); | ||
| 40 | |||
| 41 | #else | ||
| 42 | |||
| 43 | #define flush_icache_range(start, end) do {} while (0) | ||
| 44 | #define flush_icache_page(vma, pg) do {} while (0) | ||
| 45 | |||
| 46 | #endif | ||
| 47 | |||
| 48 | #define flush_icache_user_range(vma, pg, adr, len) \ | ||
| 49 | flush_icache_range(adr, adr + len) | ||
| 50 | |||
| 51 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | ||
| 52 | do { \ | ||
| 53 | memcpy(dst, src, len); \ | ||
| 54 | flush_icache_page(vma, page); \ | ||
| 55 | } while (0) | ||
| 56 | |||
| 57 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | ||
| 58 | memcpy(dst, src, len) | ||
| 59 | |||
| 60 | /* | ||
| 61 | * primitive routines | ||
| 62 | */ | ||
| 63 | #ifndef CONFIG_MN10300_CACHE_DISABLED | ||
| 64 | extern void mn10300_icache_inv(void); | ||
| 65 | extern void mn10300_dcache_inv(void); | ||
| 66 | extern void mn10300_dcache_inv_page(unsigned start); | ||
| 67 | extern void mn10300_dcache_inv_range(unsigned start, unsigned end); | ||
| 68 | extern void mn10300_dcache_inv_range2(unsigned start, unsigned size); | ||
| 69 | #ifdef CONFIG_MN10300_CACHE_WBACK | ||
| 70 | extern void mn10300_dcache_flush(void); | ||
| 71 | extern void mn10300_dcache_flush_page(unsigned start); | ||
| 72 | extern void mn10300_dcache_flush_range(unsigned start, unsigned end); | ||
| 73 | extern void mn10300_dcache_flush_range2(unsigned start, unsigned size); | ||
| 74 | extern void mn10300_dcache_flush_inv(void); | ||
| 75 | extern void mn10300_dcache_flush_inv_page(unsigned start); | ||
| 76 | extern void mn10300_dcache_flush_inv_range(unsigned start, unsigned end); | ||
| 77 | extern void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size); | ||
| 78 | #else | ||
| 79 | #define mn10300_dcache_flush() do {} while (0) | ||
| 80 | #define mn10300_dcache_flush_page(start) do {} while (0) | ||
| 81 | #define mn10300_dcache_flush_range(start, end) do {} while (0) | ||
| 82 | #define mn10300_dcache_flush_range2(start, size) do {} while (0) | ||
| 83 | #define mn10300_dcache_flush_inv() mn10300_dcache_inv() | ||
| 84 | #define mn10300_dcache_flush_inv_page(start) \ | ||
| 85 | mn10300_dcache_inv_page((start)) | ||
| 86 | #define mn10300_dcache_flush_inv_range(start, end) \ | ||
| 87 | mn10300_dcache_inv_range((start), (end)) | ||
| 88 | #define mn10300_dcache_flush_inv_range2(start, size) \ | ||
| 89 | mn10300_dcache_inv_range2((start), (size)) | ||
| 90 | #endif /* CONFIG_MN10300_CACHE_WBACK */ | ||
| 91 | #else | ||
| 92 | #define mn10300_icache_inv() do {} while (0) | ||
| 93 | #define mn10300_dcache_inv() do {} while (0) | ||
| 94 | #define mn10300_dcache_inv_page(start) do {} while (0) | ||
| 95 | #define mn10300_dcache_inv_range(start, end) do {} while (0) | ||
| 96 | #define mn10300_dcache_inv_range2(start, size) do {} while (0) | ||
| 97 | #define mn10300_dcache_flush() do {} while (0) | ||
| 98 | #define mn10300_dcache_flush_inv_page(start) do {} while (0) | ||
| 99 | #define mn10300_dcache_flush_inv() do {} while (0) | ||
| 100 | #define mn10300_dcache_flush_inv_range(start, end) do {} while (0) | ||
| 101 | #define mn10300_dcache_flush_inv_range2(start, size) do {} while (0) | ||
| 102 | #define mn10300_dcache_flush_page(start) do {} while (0) | ||
| 103 | #define mn10300_dcache_flush_range(start, end) do {} while (0) | ||
| 104 | #define mn10300_dcache_flush_range2(start, size) do {} while (0) | ||
| 105 | #endif /* CONFIG_MN10300_CACHE_DISABLED */ | ||
| 106 | |||
| 107 | /* | ||
| 108 | * internal debugging function | ||
| 109 | */ | ||
| 110 | #ifdef CONFIG_DEBUG_PAGEALLOC | ||
| 111 | extern void kernel_map_pages(struct page *page, int numpages, int enable); | ||
| 112 | #endif | ||
| 113 | |||
| 114 | #endif /* __ASSEMBLY__ */ | ||
| 115 | |||
| 116 | #endif /* _ASM_CACHEFLUSH_H */ | ||
diff --git a/include/asm-mn10300/checksum.h b/include/asm-mn10300/checksum.h new file mode 100644 index 000000000000..9fb2a8d8826a --- /dev/null +++ b/include/asm-mn10300/checksum.h | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | /* MN10300 Optimised checksumming code | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_CHECKSUM_H | ||
| 12 | #define _ASM_CHECKSUM_H | ||
| 13 | |||
| 14 | extern __wsum csum_partial(const void *buff, int len, __wsum sum); | ||
| 15 | extern __wsum csum_partial_copy_nocheck(const void *src, void *dst, | ||
| 16 | int len, __wsum sum); | ||
| 17 | extern __wsum csum_partial_copy_from_user(const void *src, void *dst, | ||
| 18 | int len, __wsum sum, | ||
| 19 | int *err_ptr); | ||
| 20 | extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl); | ||
| 21 | extern __wsum csum_partial(const void *buff, int len, __wsum sum); | ||
| 22 | extern __sum16 ip_compute_csum(const void *buff, int len); | ||
| 23 | |||
| 24 | #define csum_partial_copy_fromuser csum_partial_copy | ||
| 25 | extern __wsum csum_partial_copy(const void *src, void *dst, int len, | ||
| 26 | __wsum sum); | ||
| 27 | |||
| 28 | static inline __sum16 csum_fold(__wsum sum) | ||
| 29 | { | ||
| 30 | asm( | ||
| 31 | " add %1,%0 \n" | ||
| 32 | " addc 0xffff,%0 \n" | ||
| 33 | : "=r" (sum) | ||
| 34 | : "r" (sum << 16), "0" (sum & 0xffff0000) | ||
| 35 | : "cc" | ||
| 36 | ); | ||
| 37 | return (~sum) >> 16; | ||
| 38 | } | ||
| 39 | |||
| 40 | static inline __wsum csum_tcpudp_nofold(unsigned long saddr, | ||
| 41 | unsigned long daddr, | ||
| 42 | unsigned short len, | ||
| 43 | unsigned short proto, | ||
| 44 | __wsum sum) | ||
| 45 | { | ||
| 46 | __wsum tmp; | ||
| 47 | |||
| 48 | tmp = (__wsum) ntohs(len) << 16; | ||
| 49 | tmp += (__wsum) proto << 8; | ||
| 50 | |||
| 51 | asm( | ||
| 52 | " add %1,%0 \n" | ||
| 53 | " addc %2,%0 \n" | ||
| 54 | " addc %3,%0 \n" | ||
| 55 | " addc 0,%0 \n" | ||
| 56 | : "=r" (sum) | ||
| 57 | : "r" (daddr), "r"(saddr), "r"(tmp), "0"(sum) | ||
| 58 | : "cc" | ||
| 59 | ); | ||
| 60 | return sum; | ||
| 61 | } | ||
| 62 | |||
| 63 | /* | ||
| 64 | * computes the checksum of the TCP/UDP pseudo-header | ||
| 65 | * returns a 16-bit checksum, already complemented | ||
| 66 | */ | ||
| 67 | static inline __sum16 csum_tcpudp_magic(unsigned long saddr, | ||
| 68 | unsigned long daddr, | ||
| 69 | unsigned short len, | ||
| 70 | unsigned short proto, | ||
| 71 | __wsum sum) | ||
| 72 | { | ||
| 73 | return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); | ||
| 74 | } | ||
| 75 | |||
| 76 | #undef _HAVE_ARCH_IPV6_CSUM | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Copy and checksum to user | ||
| 80 | */ | ||
| 81 | #define HAVE_CSUM_COPY_USER | ||
| 82 | extern __wsum csum_and_copy_to_user(const void *src, void *dst, int len, | ||
| 83 | __wsum sum, int *err_ptr); | ||
| 84 | |||
| 85 | |||
| 86 | #endif /* _ASM_CHECKSUM_H */ | ||
diff --git a/include/asm-mn10300/cpu-regs.h b/include/asm-mn10300/cpu-regs.h new file mode 100644 index 000000000000..757e9b5388ea --- /dev/null +++ b/include/asm-mn10300/cpu-regs.h | |||
| @@ -0,0 +1,290 @@ | |||
| 1 | /* MN10300 Core system registers | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_CPU_REGS_H | ||
| 12 | #define _ASM_CPU_REGS_H | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | #include <linux/types.h> | ||
| 16 | #endif | ||
| 17 | |||
| 18 | #ifdef CONFIG_MN10300_CPU_AM33V2 | ||
| 19 | /* we tell the compiler to pretend to be AM33 so that it doesn't try and use | ||
| 20 | * the FP regs, but tell the assembler that we're actually allowed AM33v2 | ||
| 21 | * instructions */ | ||
| 22 | #ifndef __ASSEMBLY__ | ||
| 23 | asm(" .am33_2\n"); | ||
| 24 | #else | ||
| 25 | .am33_2 | ||
| 26 | #endif | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #ifdef __KERNEL__ | ||
| 30 | |||
| 31 | #ifndef __ASSEMBLY__ | ||
| 32 | #define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR)) | ||
| 33 | #define __SYSREGC(ADDR, TYPE) (*(const volatile TYPE *)(ADDR)) | ||
| 34 | #else | ||
| 35 | #define __SYSREG(ADDR, TYPE) ADDR | ||
| 36 | #define __SYSREGC(ADDR, TYPE) ADDR | ||
| 37 | #endif | ||
| 38 | |||
| 39 | /* CPU registers */ | ||
| 40 | #define EPSW_FLAG_Z 0x00000001 /* zero flag */ | ||
| 41 | #define EPSW_FLAG_N 0x00000002 /* negative flag */ | ||
| 42 | #define EPSW_FLAG_C 0x00000004 /* carry flag */ | ||
| 43 | #define EPSW_FLAG_V 0x00000008 /* overflow flag */ | ||
| 44 | #define EPSW_IM 0x00000700 /* interrupt mode */ | ||
| 45 | #define EPSW_IM_0 0x00000000 /* interrupt mode 0 */ | ||
| 46 | #define EPSW_IM_1 0x00000100 /* interrupt mode 1 */ | ||
| 47 | #define EPSW_IM_2 0x00000200 /* interrupt mode 2 */ | ||
| 48 | #define EPSW_IM_3 0x00000300 /* interrupt mode 3 */ | ||
| 49 | #define EPSW_IM_4 0x00000400 /* interrupt mode 4 */ | ||
| 50 | #define EPSW_IM_5 0x00000500 /* interrupt mode 5 */ | ||
| 51 | #define EPSW_IM_6 0x00000600 /* interrupt mode 6 */ | ||
| 52 | #define EPSW_IM_7 0x00000700 /* interrupt mode 7 */ | ||
| 53 | #define EPSW_IE 0x00000800 /* interrupt enable */ | ||
| 54 | #define EPSW_S 0x00003000 /* software auxilliary bits */ | ||
| 55 | #define EPSW_T 0x00008000 /* trace enable */ | ||
| 56 | #define EPSW_nSL 0x00010000 /* not supervisor level */ | ||
| 57 | #define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */ | ||
| 58 | #define EPSW_nAR 0x00040000 /* register bank control */ | ||
| 59 | #define EPSW_ML 0x00080000 /* monitor level */ | ||
| 60 | #define EPSW_FE 0x00100000 /* FPU enable */ | ||
| 61 | |||
| 62 | /* FPU registers */ | ||
| 63 | #define FPCR_EF_I 0x00000001 /* inexact result FPU exception flag */ | ||
| 64 | #define FPCR_EF_U 0x00000002 /* underflow FPU exception flag */ | ||
| 65 | #define FPCR_EF_O 0x00000004 /* overflow FPU exception flag */ | ||
| 66 | #define FPCR_EF_Z 0x00000008 /* zero divide FPU exception flag */ | ||
| 67 | #define FPCR_EF_V 0x00000010 /* invalid operand FPU exception flag */ | ||
| 68 | #define FPCR_EE_I 0x00000020 /* inexact result FPU exception enable */ | ||
| 69 | #define FPCR_EE_U 0x00000040 /* underflow FPU exception enable */ | ||
| 70 | #define FPCR_EE_O 0x00000080 /* overflow FPU exception enable */ | ||
| 71 | #define FPCR_EE_Z 0x00000100 /* zero divide FPU exception enable */ | ||
| 72 | #define FPCR_EE_V 0x00000200 /* invalid operand FPU exception enable */ | ||
| 73 | #define FPCR_EC_I 0x00000400 /* inexact result FPU exception cause */ | ||
| 74 | #define FPCR_EC_U 0x00000800 /* underflow FPU exception cause */ | ||
| 75 | #define FPCR_EC_O 0x00001000 /* overflow FPU exception cause */ | ||
| 76 | #define FPCR_EC_Z 0x00002000 /* zero divide FPU exception cause */ | ||
| 77 | #define FPCR_EC_V 0x00004000 /* invalid operand FPU exception cause */ | ||
| 78 | #define FPCR_RM 0x00030000 /* rounding mode */ | ||
| 79 | #define FPCR_RM_NEAREST 0x00000000 /* - round to nearest value */ | ||
| 80 | #define FPCR_FCC_U 0x00040000 /* FPU unordered condition code */ | ||
| 81 | #define FPCR_FCC_E 0x00080000 /* FPU equal condition code */ | ||
| 82 | #define FPCR_FCC_G 0x00100000 /* FPU greater than condition code */ | ||
| 83 | #define FPCR_FCC_L 0x00200000 /* FPU less than condition code */ | ||
| 84 | #define FPCR_INIT 0x00000000 /* no exceptions, rounding to nearest */ | ||
| 85 | |||
| 86 | /* CPU control registers */ | ||
| 87 | #define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */ | ||
| 88 | #define CPUP_DWBD 0x0020 /* write buffer disable flag */ | ||
| 89 | #define CPUP_IPFD 0x0040 /* instruction prefetch disable flag */ | ||
| 90 | #define CPUP_EXM 0x0080 /* exception operation mode */ | ||
| 91 | #define CPUP_EXM_AM33V1 0x0000 /* - AM33 v1 exception mode */ | ||
| 92 | #define CPUP_EXM_AM33V2 0x0080 /* - AM33 v2 exception mode */ | ||
| 93 | |||
| 94 | #define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */ | ||
| 95 | #define CPUM_SLEEP 0x0004 /* set to enter sleep state */ | ||
| 96 | #define CPUM_HALT 0x0008 /* set to enter halt state */ | ||
| 97 | #define CPUM_STOP 0x0010 /* set to enter stop state */ | ||
| 98 | |||
| 99 | #define CPUREV __SYSREGC(0xc0000050, u32) /* CPU revision register */ | ||
| 100 | #define CPUREV_TYPE 0x0000000f /* CPU type */ | ||
| 101 | #define CPUREV_TYPE_S 0 | ||
| 102 | #define CPUREV_TYPE_AM33V1 0x00000000 /* - AM33 V1 core, AM33/1.00 arch */ | ||
| 103 | #define CPUREV_TYPE_AM33V2 0x00000001 /* - AM33 V2 core, AM33/2.00 arch */ | ||
| 104 | #define CPUREV_TYPE_AM34V1 0x00000002 /* - AM34 V1 core, AM33/2.00 arch */ | ||
| 105 | #define CPUREV_REVISION 0x000000f0 /* CPU revision */ | ||
| 106 | #define CPUREV_REVISION_S 4 | ||
| 107 | #define CPUREV_ICWAY 0x00000f00 /* number of instruction cache ways */ | ||
| 108 | #define CPUREV_ICWAY_S 8 | ||
| 109 | #define CPUREV_ICSIZE 0x0000f000 /* instruction cache way size */ | ||
| 110 | #define CPUREV_ICSIZE_S 12 | ||
| 111 | #define CPUREV_DCWAY 0x000f0000 /* number of data cache ways */ | ||
| 112 | #define CPUREV_DCWAY_S 16 | ||
| 113 | #define CPUREV_DCSIZE 0x00f00000 /* data cache way size */ | ||
| 114 | #define CPUREV_DCSIZE_S 20 | ||
| 115 | #define CPUREV_FPUTYPE 0x0f000000 /* FPU core type */ | ||
| 116 | #define CPUREV_FPUTYPE_NONE 0x00000000 /* - no FPU core implemented */ | ||
| 117 | #define CPUREV_OCDCTG 0xf0000000 /* on-chip debug function category */ | ||
| 118 | |||
| 119 | #define DCR __SYSREG(0xc0000030, u16) /* Debug control register */ | ||
| 120 | |||
| 121 | /* interrupt/exception control registers */ | ||
| 122 | #define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */ | ||
| 123 | #define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */ | ||
| 124 | #define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */ | ||
| 125 | #define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */ | ||
| 126 | #define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */ | ||
| 127 | #define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */ | ||
| 128 | #define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */ | ||
| 129 | |||
| 130 | #define TBR __SYSREG(0xc0000024, u32) /* Trap table base */ | ||
| 131 | #define TBR_TB 0xff000000 /* table base address bits 31-24 */ | ||
| 132 | #define TBR_INT_CODE 0x00ffffff /* interrupt code */ | ||
| 133 | |||
| 134 | #define DEAR __SYSREG(0xc0000038, u32) /* Data access exception address */ | ||
| 135 | |||
| 136 | #define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */ | ||
| 137 | #define sISR_IRQICE 0x00000001 /* ICE interrupt */ | ||
| 138 | #define sISR_ISTEP 0x00000002 /* single step interrupt */ | ||
| 139 | #define sISR_MISSA 0x00000004 /* memory access address misalignment fault */ | ||
| 140 | #define sISR_UNIMP 0x00000008 /* unimplemented instruction execution fault */ | ||
| 141 | #define sISR_PIEXE 0x00000010 /* program interrupt */ | ||
| 142 | #define sISR_MEMERR 0x00000020 /* illegal memory access fault */ | ||
| 143 | #define sISR_IBREAK 0x00000040 /* instraction break interrupt */ | ||
| 144 | #define sISR_DBSRL 0x00000080 /* debug serial interrupt */ | ||
| 145 | #define sISR_PERIDB 0x00000100 /* peripheral debug interrupt */ | ||
| 146 | #define sISR_EXUNIMP 0x00000200 /* unimplemented ex-instruction execution fault */ | ||
| 147 | #define sISR_OBREAK 0x00000400 /* operand break interrupt */ | ||
| 148 | #define sISR_PRIV 0x00000800 /* privileged instruction execution fault */ | ||
| 149 | #define sISR_BUSERR 0x00001000 /* bus error fault */ | ||
| 150 | #define sISR_DBLFT 0x00002000 /* double fault */ | ||
| 151 | #define sISR_DBG 0x00008000 /* debug reserved interrupt */ | ||
| 152 | #define sISR_ITMISS 0x00010000 /* instruction TLB miss */ | ||
| 153 | #define sISR_DTMISS 0x00020000 /* data TLB miss */ | ||
| 154 | #define sISR_ITEX 0x00040000 /* instruction TLB access exception */ | ||
| 155 | #define sISR_DTEX 0x00080000 /* data TLB access exception */ | ||
| 156 | #define sISR_ILGIA 0x00100000 /* illegal instruction access exception */ | ||
| 157 | #define sISR_ILGDA 0x00200000 /* illegal data access exception */ | ||
| 158 | #define sISR_IOIA 0x00400000 /* internal I/O space instruction access excep */ | ||
| 159 | #define sISR_PRIVA 0x00800000 /* privileged space instruction access excep */ | ||
| 160 | #define sISR_PRIDA 0x01000000 /* privileged space data access excep */ | ||
| 161 | #define sISR_DISA 0x02000000 /* data space instruction access excep */ | ||
| 162 | #define sISR_SYSC 0x04000000 /* system call instruction excep */ | ||
| 163 | #define sISR_FPUD 0x08000000 /* FPU disabled excep */ | ||
| 164 | #define sISR_FPUUI 0x10000000 /* FPU unimplemented instruction excep */ | ||
| 165 | #define sISR_FPUOP 0x20000000 /* FPU operation excep */ | ||
| 166 | #define sISR_NE 0x80000000 /* multiple synchronous exceptions excep */ | ||
| 167 | |||
| 168 | /* cache control registers */ | ||
| 169 | #define CHCTR __SYSREG(0xc0000070, u16) /* cache control */ | ||
| 170 | #define CHCTR_ICEN 0x0001 /* instruction cache enable */ | ||
| 171 | #define CHCTR_DCEN 0x0002 /* data cache enable */ | ||
| 172 | #define CHCTR_ICBUSY 0x0004 /* instruction cache busy */ | ||
| 173 | #define CHCTR_DCBUSY 0x0008 /* data cache busy */ | ||
| 174 | #define CHCTR_ICINV 0x0010 /* instruction cache invalidate */ | ||
| 175 | #define CHCTR_DCINV 0x0020 /* data cache invalidate */ | ||
| 176 | #define CHCTR_DCWTMD 0x0040 /* data cache writing mode */ | ||
| 177 | #define CHCTR_DCWTMD_WRBACK 0x0000 /* - write back mode */ | ||
| 178 | #define CHCTR_DCWTMD_WRTHROUGH 0x0040 /* - write through mode */ | ||
| 179 | #define CHCTR_DCALMD 0x0080 /* data cache allocation mode */ | ||
| 180 | #define CHCTR_ICWMD 0x0f00 /* instruction cache way mode */ | ||
| 181 | #define CHCTR_DCWMD 0xf000 /* data cache way mode */ | ||
| 182 | |||
| 183 | /* MMU control registers */ | ||
| 184 | #define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */ | ||
| 185 | #define MMUCTR_IRP 0x0000003f /* instruction TLB replace pointer */ | ||
| 186 | #define MMUCTR_ITE 0x00000040 /* instruction TLB enable */ | ||
| 187 | #define MMUCTR_IIV 0x00000080 /* instruction TLB invalidate */ | ||
| 188 | #define MMUCTR_ITL 0x00000700 /* instruction TLB lock pointer */ | ||
| 189 | #define MMUCTR_ITL_NOLOCK 0x00000000 /* - no lock */ | ||
| 190 | #define MMUCTR_ITL_LOCK0 0x00000100 /* - entry 0 locked */ | ||
| 191 | #define MMUCTR_ITL_LOCK0_1 0x00000200 /* - entry 0-1 locked */ | ||
| 192 | #define MMUCTR_ITL_LOCK0_3 0x00000300 /* - entry 0-3 locked */ | ||
| 193 | #define MMUCTR_ITL_LOCK0_7 0x00000400 /* - entry 0-7 locked */ | ||
| 194 | #define MMUCTR_ITL_LOCK0_15 0x00000500 /* - entry 0-15 locked */ | ||
| 195 | #define MMUCTR_CE 0x00008000 /* cacheable bit enable */ | ||
| 196 | #define MMUCTR_DRP 0x003f0000 /* data TLB replace pointer */ | ||
| 197 | #define MMUCTR_DTE 0x00400000 /* data TLB enable */ | ||
| 198 | #define MMUCTR_DIV 0x00800000 /* data TLB invalidate */ | ||
| 199 | #define MMUCTR_DTL 0x07000000 /* data TLB lock pointer */ | ||
| 200 | #define MMUCTR_DTL_NOLOCK 0x00000000 /* - no lock */ | ||
| 201 | #define MMUCTR_DTL_LOCK0 0x01000000 /* - entry 0 locked */ | ||
| 202 | #define MMUCTR_DTL_LOCK0_1 0x02000000 /* - entry 0-1 locked */ | ||
| 203 | #define MMUCTR_DTL_LOCK0_3 0x03000000 /* - entry 0-3 locked */ | ||
| 204 | #define MMUCTR_DTL_LOCK0_7 0x04000000 /* - entry 0-7 locked */ | ||
| 205 | #define MMUCTR_DTL_LOCK0_15 0x05000000 /* - entry 0-15 locked */ | ||
| 206 | |||
| 207 | #define PIDR __SYSREG(0xc0000094, u16) /* PID register */ | ||
| 208 | #define PIDR_PID 0x00ff /* process identifier */ | ||
| 209 | |||
| 210 | #define PTBR __SYSREG(0xc0000098, unsigned long) /* Page table base register */ | ||
| 211 | |||
| 212 | #define IPTEL __SYSREG(0xc00000a0, u32) /* instruction TLB entry */ | ||
| 213 | #define DPTEL __SYSREG(0xc00000b0, u32) /* data TLB entry */ | ||
| 214 | #define xPTEL_V 0x00000001 /* TLB entry valid */ | ||
| 215 | #define xPTEL_UNUSED1 0x00000002 /* unused bit */ | ||
| 216 | #define xPTEL_UNUSED2 0x00000004 /* unused bit */ | ||
| 217 | #define xPTEL_C 0x00000008 /* cached if set */ | ||
| 218 | #define xPTEL_PV 0x00000010 /* page valid */ | ||
| 219 | #define xPTEL_D 0x00000020 /* dirty */ | ||
| 220 | #define xPTEL_PR 0x000001c0 /* page protection */ | ||
| 221 | #define xPTEL_PR_ROK 0x00000000 /* - R/O kernel */ | ||
| 222 | #define xPTEL_PR_RWK 0x00000100 /* - R/W kernel */ | ||
| 223 | #define xPTEL_PR_ROK_ROU 0x00000080 /* - R/O kernel and R/O user */ | ||
| 224 | #define xPTEL_PR_RWK_ROU 0x00000180 /* - R/W kernel and R/O user */ | ||
| 225 | #define xPTEL_PR_RWK_RWU 0x000001c0 /* - R/W kernel and R/W user */ | ||
| 226 | #define xPTEL_G 0x00000200 /* global (use PID if 0) */ | ||
| 227 | #define xPTEL_PS 0x00000c00 /* page size */ | ||
| 228 | #define xPTEL_PS_4Kb 0x00000000 /* - 4Kb page */ | ||
| 229 | #define xPTEL_PS_128Kb 0x00000400 /* - 128Kb page */ | ||
| 230 | #define xPTEL_PS_1Kb 0x00000800 /* - 1Kb page */ | ||
| 231 | #define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */ | ||
| 232 | #define xPTEL_PPN 0xfffff006 /* physical page number */ | ||
| 233 | |||
| 234 | #define xPTEL_V_BIT 0 /* bit numbers corresponding to above masks */ | ||
| 235 | #define xPTEL_UNUSED1_BIT 1 | ||
| 236 | #define xPTEL_UNUSED2_BIT 2 | ||
| 237 | #define xPTEL_C_BIT 3 | ||
| 238 | #define xPTEL_PV_BIT 4 | ||
| 239 | #define xPTEL_D_BIT 5 | ||
| 240 | #define xPTEL_G_BIT 9 | ||
| 241 | |||
| 242 | #define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */ | ||
| 243 | #define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */ | ||
| 244 | #define xPTEU_VPN 0xfffffc00 /* virtual page number */ | ||
| 245 | #define xPTEU_PID 0x000000ff /* process identifier to which applicable */ | ||
| 246 | |||
| 247 | #define IPTEL2 __SYSREG(0xc00000a8, u32) /* instruction TLB entry */ | ||
| 248 | #define DPTEL2 __SYSREG(0xc00000b8, u32) /* data TLB entry */ | ||
| 249 | #define xPTEL2_V 0x00000001 /* TLB entry valid */ | ||
| 250 | #define xPTEL2_C 0x00000002 /* cacheable */ | ||
| 251 | #define xPTEL2_PV 0x00000004 /* page valid */ | ||
| 252 | #define xPTEL2_D 0x00000008 /* dirty */ | ||
| 253 | #define xPTEL2_PR 0x00000070 /* page protection */ | ||
| 254 | #define xPTEL2_PR_ROK 0x00000000 /* - R/O kernel */ | ||
| 255 | #define xPTEL2_PR_RWK 0x00000040 /* - R/W kernel */ | ||
| 256 | #define xPTEL2_PR_ROK_ROU 0x00000020 /* - R/O kernel and R/O user */ | ||
| 257 | #define xPTEL2_PR_RWK_ROU 0x00000060 /* - R/W kernel and R/O user */ | ||
| 258 | #define xPTEL2_PR_RWK_RWU 0x00000070 /* - R/W kernel and R/W user */ | ||
| 259 | #define xPTEL2_G 0x00000080 /* global (use PID if 0) */ | ||
| 260 | #define xPTEL2_PS 0x00000300 /* page size */ | ||
| 261 | #define xPTEL2_PS_4Kb 0x00000000 /* - 4Kb page */ | ||
| 262 | #define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */ | ||
| 263 | #define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */ | ||
| 264 | #define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */ | ||
| 265 | #define xPTEL2_PPN 0xfffffc00 /* physical page number */ | ||
| 266 | |||
| 267 | #define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */ | ||
| 268 | #define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */ | ||
| 269 | #define MMUFCR_DFC __SYSREGC(0xc000009e, u16) /* MMU data exception cause */ | ||
| 270 | #define MMUFCR_xFC_TLBMISS 0x0001 /* TLB miss flag */ | ||
| 271 | #define MMUFCR_xFC_INITWR 0x0002 /* initial write excep flag */ | ||
| 272 | #define MMUFCR_xFC_PGINVAL 0x0004 /* page invalid excep flag */ | ||
| 273 | #define MMUFCR_xFC_PROTVIOL 0x0008 /* protection violation excep flag */ | ||
| 274 | #define MMUFCR_xFC_ACCESS 0x0010 /* access level flag */ | ||
| 275 | #define MMUFCR_xFC_ACCESS_USR 0x0000 /* - user mode */ | ||
| 276 | #define MMUFCR_xFC_ACCESS_SR 0x0010 /* - supervisor mode */ | ||
| 277 | #define MMUFCR_xFC_TYPE 0x0020 /* access type flag */ | ||
| 278 | #define MMUFCR_xFC_TYPE_READ 0x0000 /* - read */ | ||
| 279 | #define MMUFCR_xFC_TYPE_WRITE 0x0020 /* - write */ | ||
| 280 | #define MMUFCR_xFC_PR 0x01c0 /* page protection flag */ | ||
| 281 | #define MMUFCR_xFC_PR_ROK 0x0000 /* - R/O kernel */ | ||
| 282 | #define MMUFCR_xFC_PR_RWK 0x0100 /* - R/W kernel */ | ||
| 283 | #define MMUFCR_xFC_PR_ROK_ROU 0x0080 /* - R/O kernel and R/O user */ | ||
| 284 | #define MMUFCR_xFC_PR_RWK_ROU 0x0180 /* - R/W kernel and R/O user */ | ||
| 285 | #define MMUFCR_xFC_PR_RWK_RWU 0x01c0 /* - R/W kernel and R/W user */ | ||
| 286 | #define MMUFCR_xFC_ILLADDR 0x0200 /* illegal address excep flag */ | ||
| 287 | |||
| 288 | #endif /* __KERNEL__ */ | ||
| 289 | |||
| 290 | #endif /* _ASM_CPU_REGS_H */ | ||
diff --git a/include/asm-mn10300/cputime.h b/include/asm-mn10300/cputime.h new file mode 100644 index 000000000000..6d68ad7e0ea3 --- /dev/null +++ b/include/asm-mn10300/cputime.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/cputime.h> | |||
diff --git a/include/asm-mn10300/current.h b/include/asm-mn10300/current.h new file mode 100644 index 000000000000..ca6027d83743 --- /dev/null +++ b/include/asm-mn10300/current.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* MN10300 Current task structure accessor | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_CURRENT_H | ||
| 12 | #define _ASM_CURRENT_H | ||
| 13 | |||
| 14 | #include <linux/thread_info.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * dedicate E2 to keeping the current task pointer | ||
| 18 | */ | ||
| 19 | #ifdef CONFIG_MN10300_CURRENT_IN_E2 | ||
| 20 | |||
| 21 | register struct task_struct *const current asm("e2") __attribute__((used)); | ||
| 22 | |||
| 23 | #define get_current() current | ||
| 24 | |||
| 25 | extern struct task_struct *__current; | ||
| 26 | |||
| 27 | #else | ||
| 28 | static inline __attribute__((const)) | ||
| 29 | struct task_struct *get_current(void) | ||
| 30 | { | ||
| 31 | return current_thread_info()->task; | ||
| 32 | } | ||
| 33 | |||
| 34 | #define current get_current() | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #endif /* _ASM_CURRENT_H */ | ||
diff --git a/include/asm-mn10300/delay.h b/include/asm-mn10300/delay.h new file mode 100644 index 000000000000..34517b359399 --- /dev/null +++ b/include/asm-mn10300/delay.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* MN10300 Uninterruptible delay routines | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_DELAY_H | ||
| 12 | #define _ASM_DELAY_H | ||
| 13 | |||
| 14 | extern void __udelay(unsigned long usecs); | ||
| 15 | extern void __delay(unsigned long loops); | ||
| 16 | |||
| 17 | #define udelay(n) __udelay(n) | ||
| 18 | |||
| 19 | #endif /* _ASM_DELAY_H */ | ||
diff --git a/include/asm-mn10300/device.h b/include/asm-mn10300/device.h new file mode 100644 index 000000000000..f0a4c256403b --- /dev/null +++ b/include/asm-mn10300/device.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/device.h> | |||
diff --git a/include/asm-mn10300/div64.h b/include/asm-mn10300/div64.h new file mode 100644 index 000000000000..bf9c515a998c --- /dev/null +++ b/include/asm-mn10300/div64.h | |||
| @@ -0,0 +1,103 @@ | |||
| 1 | /* MN10300 64-bit division | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_DIV64 | ||
| 12 | #define _ASM_DIV64 | ||
| 13 | |||
| 14 | #include <linux/types.h> | ||
| 15 | |||
| 16 | extern void ____unhandled_size_in_do_div___(void); | ||
| 17 | |||
| 18 | /* | ||
| 19 | * divide n by base, leaving the result in n and returning the remainder | ||
| 20 | * - we can do this quite efficiently on the MN10300 by cascading the divides | ||
| 21 | * through the MDR register | ||
| 22 | */ | ||
| 23 | #define do_div(n, base) \ | ||
| 24 | ({ \ | ||
| 25 | unsigned __rem = 0; \ | ||
| 26 | if (sizeof(n) <= 4) { \ | ||
| 27 | asm("mov %1,mdr \n" \ | ||
| 28 | "divu %2,%0 \n" \ | ||
| 29 | "mov mdr,%1 \n" \ | ||
| 30 | : "+r"(n), "=d"(__rem) \ | ||
| 31 | : "r"(base), "1"(__rem) \ | ||
| 32 | : "cc" \ | ||
| 33 | ); \ | ||
| 34 | } else if (sizeof(n) <= 8) { \ | ||
| 35 | union { \ | ||
| 36 | unsigned long long l; \ | ||
| 37 | u32 w[2]; \ | ||
| 38 | } __quot; \ | ||
| 39 | __quot.l = n; \ | ||
| 40 | asm("mov %0,mdr \n" /* MDR = 0 */ \ | ||
| 41 | "divu %3,%1 \n" \ | ||
| 42 | /* __quot.MSL = __div.MSL / base, */ \ | ||
| 43 | /* MDR = MDR:__div.MSL % base */ \ | ||
| 44 | "divu %3,%2 \n" \ | ||
| 45 | /* __quot.LSL = MDR:__div.LSL / base, */ \ | ||
| 46 | /* MDR = MDR:__div.LSL % base */ \ | ||
| 47 | "mov mdr,%0 \n" \ | ||
| 48 | : "=d"(__rem), "=r"(__quot.w[1]), "=r"(__quot.w[0]) \ | ||
| 49 | : "r"(base), "0"(__rem), "1"(__quot.w[1]), \ | ||
| 50 | "2"(__quot.w[0]) \ | ||
| 51 | : "cc" \ | ||
| 52 | ); \ | ||
| 53 | n = __quot.l; \ | ||
| 54 | } else { \ | ||
| 55 | ____unhandled_size_in_do_div___(); \ | ||
| 56 | } \ | ||
| 57 | __rem; \ | ||
| 58 | }) | ||
| 59 | |||
| 60 | /* | ||
| 61 | * do an unsigned 32-bit multiply and divide with intermediate 64-bit product | ||
| 62 | * so as not to lose accuracy | ||
| 63 | * - we use the MDR register to hold the MSW of the product | ||
| 64 | */ | ||
| 65 | static inline __attribute__((const)) | ||
| 66 | unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div) | ||
| 67 | { | ||
| 68 | unsigned result; | ||
| 69 | |||
| 70 | asm("mulu %2,%0 \n" /* MDR:val = val*mult */ | ||
| 71 | "divu %3,%0 \n" /* val = MDR:val/div; | ||
| 72 | * MDR = MDR:val%div */ | ||
| 73 | : "=r"(result) | ||
| 74 | : "0"(val), "ir"(mult), "r"(div) | ||
| 75 | ); | ||
| 76 | |||
| 77 | return result; | ||
| 78 | } | ||
| 79 | |||
| 80 | /* | ||
| 81 | * do a signed 32-bit multiply and divide with intermediate 64-bit product so | ||
| 82 | * as not to lose accuracy | ||
| 83 | * - we use the MDR register to hold the MSW of the product | ||
| 84 | */ | ||
| 85 | static inline __attribute__((const)) | ||
| 86 | signed __muldiv64s(signed val, signed mult, signed div) | ||
| 87 | { | ||
| 88 | signed result; | ||
| 89 | |||
| 90 | asm("mul %2,%0 \n" /* MDR:val = val*mult */ | ||
| 91 | "div %3,%0 \n" /* val = MDR:val/div; | ||
| 92 | * MDR = MDR:val%div */ | ||
| 93 | : "=r"(result) | ||
| 94 | : "0"(val), "ir"(mult), "r"(div) | ||
| 95 | ); | ||
| 96 | |||
| 97 | return result; | ||
| 98 | } | ||
| 99 | |||
| 100 | extern __attribute__((const)) | ||
| 101 | uint64_t div64_64(uint64_t dividend, uint64_t divisor); | ||
| 102 | |||
| 103 | #endif /* _ASM_DIV64 */ | ||
diff --git a/include/asm-mn10300/dma-mapping.h b/include/asm-mn10300/dma-mapping.h new file mode 100644 index 000000000000..7c882fca9ec8 --- /dev/null +++ b/include/asm-mn10300/dma-mapping.h | |||
| @@ -0,0 +1,234 @@ | |||
| 1 | /* DMA mapping routines for the MN10300 arch | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_DMA_MAPPING_H | ||
| 12 | #define _ASM_DMA_MAPPING_H | ||
| 13 | |||
| 14 | #include <linux/mm.h> | ||
| 15 | #include <linux/scatterlist.h> | ||
| 16 | |||
| 17 | #include <asm/cache.h> | ||
| 18 | #include <asm/io.h> | ||
| 19 | |||
| 20 | extern void *dma_alloc_coherent(struct device *dev, size_t size, | ||
| 21 | dma_addr_t *dma_handle, int flag); | ||
| 22 | |||
| 23 | extern void dma_free_coherent(struct device *dev, size_t size, | ||
| 24 | void *vaddr, dma_addr_t dma_handle); | ||
| 25 | |||
| 26 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent((d), (s), (h), (f)) | ||
| 27 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent((d), (s), (v), (h)) | ||
| 28 | |||
| 29 | /* | ||
| 30 | * Map a single buffer of the indicated size for DMA in streaming mode. The | ||
| 31 | * 32-bit bus address to use is returned. | ||
| 32 | * | ||
| 33 | * Once the device is given the dma address, the device owns this memory until | ||
| 34 | * either pci_unmap_single or pci_dma_sync_single is performed. | ||
| 35 | */ | ||
| 36 | static inline | ||
| 37 | dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, | ||
| 38 | enum dma_data_direction direction) | ||
| 39 | { | ||
| 40 | BUG_ON(direction == DMA_NONE); | ||
| 41 | mn10300_dcache_flush_inv(); | ||
| 42 | return virt_to_bus(ptr); | ||
| 43 | } | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | ||
| 47 | * match what was provided for in a previous pci_map_single call. All other | ||
| 48 | * usages are undefined. | ||
| 49 | * | ||
| 50 | * After this call, reads by the cpu to the buffer are guarenteed to see | ||
| 51 | * whatever the device wrote there. | ||
| 52 | */ | ||
| 53 | static inline | ||
| 54 | void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, | ||
| 55 | enum dma_data_direction direction) | ||
| 56 | { | ||
| 57 | BUG_ON(direction == DMA_NONE); | ||
| 58 | } | ||
| 59 | |||
| 60 | /* | ||
| 61 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | ||
| 62 | * This is the scather-gather version of the above pci_map_single interface. | ||
| 63 | * Here the scatter gather list elements are each tagged with the appropriate | ||
| 64 | * dma address and length. They are obtained via sg_dma_{address,length}(SG). | ||
| 65 | * | ||
| 66 | * NOTE: An implementation may be able to use a smaller number of DMA | ||
| 67 | * address/length pairs than there are SG table elements. (for example | ||
| 68 | * via virtual mapping capabilities) The routine returns the number of | ||
| 69 | * addr/length pairs actually used, at most nents. | ||
| 70 | * | ||
| 71 | * Device ownership issues as mentioned above for pci_map_single are the same | ||
| 72 | * here. | ||
| 73 | */ | ||
| 74 | static inline | ||
| 75 | int dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents, | ||
| 76 | enum dma_data_direction direction) | ||
| 77 | { | ||
| 78 | struct scatterlist *sg; | ||
| 79 | int i; | ||
| 80 | |||
| 81 | BUG_ON(!valid_dma_direction(direction)); | ||
| 82 | WARN_ON(nents == 0 || sglist[0].length == 0); | ||
| 83 | |||
| 84 | for_each_sg(sglist, sg, nents, i) { | ||
| 85 | BUG_ON(!sg_page(sg)); | ||
| 86 | |||
| 87 | sg->dma_address = sg_phys(sg); | ||
| 88 | } | ||
| 89 | |||
| 90 | mn10300_dcache_flush_inv(); | ||
| 91 | return nents; | ||
| 92 | } | ||
| 93 | |||
| 94 | /* | ||
| 95 | * Unmap a set of streaming mode DMA translations. | ||
| 96 | * Again, cpu read rules concerning calls here are the same as for | ||
| 97 | * pci_unmap_single() above. | ||
| 98 | */ | ||
| 99 | static inline | ||
| 100 | void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, | ||
| 101 | enum dma_data_direction direction) | ||
| 102 | { | ||
| 103 | BUG_ON(!valid_dma_direction(direction)); | ||
| 104 | } | ||
| 105 | |||
| 106 | /* | ||
| 107 | * pci_{map,unmap}_single_page maps a kernel page to a dma_addr_t. identical | ||
| 108 | * to pci_map_single, but takes a struct page instead of a virtual address | ||
| 109 | */ | ||
| 110 | static inline | ||
| 111 | dma_addr_t dma_map_page(struct device *dev, struct page *page, | ||
| 112 | unsigned long offset, size_t size, | ||
| 113 | enum dma_data_direction direction) | ||
| 114 | { | ||
| 115 | BUG_ON(direction == DMA_NONE); | ||
| 116 | return page_to_bus(page) + offset; | ||
| 117 | } | ||
| 118 | |||
| 119 | static inline | ||
| 120 | void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, | ||
| 121 | enum dma_data_direction direction) | ||
| 122 | { | ||
| 123 | BUG_ON(direction == DMA_NONE); | ||
| 124 | } | ||
| 125 | |||
| 126 | /* | ||
| 127 | * Make physical memory consistent for a single streaming mode DMA translation | ||
| 128 | * after a transfer. | ||
| 129 | * | ||
| 130 | * If you perform a pci_map_single() but wish to interrogate the buffer using | ||
| 131 | * the cpu, yet do not wish to teardown the PCI dma mapping, you must call this | ||
| 132 | * function before doing so. At the next point you give the PCI dma address | ||
| 133 | * back to the card, the device again owns the buffer. | ||
| 134 | */ | ||
| 135 | static inline | ||
| 136 | void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, | ||
| 137 | size_t size, enum dma_data_direction direction) | ||
| 138 | { | ||
| 139 | } | ||
| 140 | |||
| 141 | static inline | ||
| 142 | void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, | ||
| 143 | size_t size, enum dma_data_direction direction) | ||
| 144 | { | ||
| 145 | mn10300_dcache_flush_inv(); | ||
| 146 | } | ||
| 147 | |||
| 148 | static inline | ||
| 149 | void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, | ||
| 150 | unsigned long offset, size_t size, | ||
| 151 | enum dma_data_direction direction) | ||
| 152 | { | ||
| 153 | } | ||
| 154 | |||
| 155 | static inline void | ||
| 156 | dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, | ||
| 157 | unsigned long offset, size_t size, | ||
| 158 | enum dma_data_direction direction) | ||
| 159 | { | ||
| 160 | mn10300_dcache_flush_inv(); | ||
| 161 | } | ||
| 162 | |||
| 163 | |||
| 164 | /* | ||
| 165 | * Make physical memory consistent for a set of streaming mode DMA translations | ||
| 166 | * after a transfer. | ||
| 167 | * | ||
| 168 | * The same as pci_dma_sync_single but for a scatter-gather list, same rules | ||
| 169 | * and usage. | ||
| 170 | */ | ||
| 171 | static inline | ||
| 172 | void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | ||
| 173 | int nelems, enum dma_data_direction direction) | ||
| 174 | { | ||
| 175 | } | ||
| 176 | |||
| 177 | static inline | ||
| 178 | void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | ||
| 179 | int nelems, enum dma_data_direction direction) | ||
| 180 | { | ||
| 181 | mn10300_dcache_flush_inv(); | ||
| 182 | } | ||
| 183 | |||
| 184 | static inline | ||
| 185 | int dma_mapping_error(dma_addr_t dma_addr) | ||
| 186 | { | ||
| 187 | return 0; | ||
| 188 | } | ||
| 189 | |||
| 190 | /* | ||
| 191 | * Return whether the given PCI device DMA address mask can be supported | ||
| 192 | * properly. For example, if your device can only drive the low 24-bits during | ||
| 193 | * PCI bus mastering, then you would pass 0x00ffffff as the mask to this | ||
| 194 | * function. | ||
| 195 | */ | ||
| 196 | static inline | ||
| 197 | int dma_supported(struct device *dev, u64 mask) | ||
| 198 | { | ||
| 199 | /* | ||
| 200 | * we fall back to GFP_DMA when the mask isn't all 1s, so we can't | ||
| 201 | * guarantee allocations that must be within a tighter range than | ||
| 202 | * GFP_DMA | ||
| 203 | */ | ||
| 204 | if (mask < 0x00ffffff) | ||
| 205 | return 0; | ||
| 206 | return 1; | ||
| 207 | } | ||
| 208 | |||
| 209 | static inline | ||
| 210 | int dma_set_mask(struct device *dev, u64 mask) | ||
| 211 | { | ||
| 212 | if (!dev->dma_mask || !dma_supported(dev, mask)) | ||
| 213 | return -EIO; | ||
| 214 | |||
| 215 | *dev->dma_mask = mask; | ||
| 216 | return 0; | ||
| 217 | } | ||
| 218 | |||
| 219 | static inline | ||
| 220 | int dma_get_cache_alignment(void) | ||
| 221 | { | ||
| 222 | return 1 << L1_CACHE_SHIFT; | ||
| 223 | } | ||
| 224 | |||
| 225 | #define dma_is_consistent(d) (1) | ||
| 226 | |||
| 227 | static inline | ||
| 228 | void dma_cache_sync(void *vaddr, size_t size, | ||
| 229 | enum dma_data_direction direction) | ||
| 230 | { | ||
| 231 | mn10300_dcache_flush_inv(); | ||
| 232 | } | ||
| 233 | |||
| 234 | #endif | ||
diff --git a/include/asm-mn10300/dma.h b/include/asm-mn10300/dma.h new file mode 100644 index 000000000000..098df2e617ab --- /dev/null +++ b/include/asm-mn10300/dma.h | |||
| @@ -0,0 +1,118 @@ | |||
| 1 | /* MN10300 ISA DMA handlers and definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_DMA_H | ||
| 12 | #define _ASM_DMA_H | ||
| 13 | |||
| 14 | #include <asm/system.h> | ||
| 15 | #include <linux/spinlock.h> | ||
| 16 | #include <asm/io.h> | ||
| 17 | #include <linux/delay.h> | ||
| 18 | |||
| 19 | #undef MAX_DMA_CHANNELS /* switch off linux/kernel/dma.c */ | ||
| 20 | #define MAX_DMA_ADDRESS 0xbfffffff | ||
| 21 | |||
| 22 | extern spinlock_t dma_spin_lock; | ||
| 23 | |||
| 24 | static inline unsigned long claim_dma_lock(void) | ||
| 25 | { | ||
| 26 | unsigned long flags; | ||
| 27 | spin_lock_irqsave(&dma_spin_lock, flags); | ||
| 28 | return flags; | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline void release_dma_lock(unsigned long flags) | ||
| 32 | { | ||
| 33 | spin_unlock_irqrestore(&dma_spin_lock, flags); | ||
| 34 | } | ||
| 35 | |||
| 36 | /* enable/disable a specific DMA channel */ | ||
| 37 | static inline void enable_dma(unsigned int dmanr) | ||
| 38 | { | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline void disable_dma(unsigned int dmanr) | ||
| 42 | { | ||
| 43 | } | ||
| 44 | |||
| 45 | /* Clear the 'DMA Pointer Flip Flop'. | ||
| 46 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. | ||
| 47 | * Use this once to initialize the FF to a known state. | ||
| 48 | * After that, keep track of it. :-) | ||
| 49 | * --- In order to do that, the DMA routines below should --- | ||
| 50 | * --- only be used while holding the DMA lock ! --- | ||
| 51 | */ | ||
| 52 | static inline void clear_dma_ff(unsigned int dmanr) | ||
| 53 | { | ||
| 54 | } | ||
| 55 | |||
| 56 | /* set mode (above) for a specific DMA channel */ | ||
| 57 | static inline void set_dma_mode(unsigned int dmanr, char mode) | ||
| 58 | { | ||
| 59 | } | ||
| 60 | |||
| 61 | /* Set only the page register bits of the transfer address. | ||
| 62 | * This is used for successive transfers when we know the contents of | ||
| 63 | * the lower 16 bits of the DMA current address register, but a 64k boundary | ||
| 64 | * may have been crossed. | ||
| 65 | */ | ||
| 66 | static inline void set_dma_page(unsigned int dmanr, char pagenr) | ||
| 67 | { | ||
| 68 | } | ||
| 69 | |||
| 70 | |||
| 71 | /* Set transfer address & page bits for specific DMA channel. | ||
| 72 | * Assumes dma flipflop is clear. | ||
| 73 | */ | ||
| 74 | static inline void set_dma_addr(unsigned int dmanr, unsigned int a) | ||
| 75 | { | ||
| 76 | } | ||
| 77 | |||
| 78 | |||
| 79 | /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for | ||
| 80 | * a specific DMA channel. | ||
| 81 | * You must ensure the parameters are valid. | ||
| 82 | * NOTE: from a manual: "the number of transfers is one more | ||
| 83 | * than the initial word count"! This is taken into account. | ||
| 84 | * Assumes dma flip-flop is clear. | ||
| 85 | * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. | ||
| 86 | */ | ||
| 87 | static inline void set_dma_count(unsigned int dmanr, unsigned int count) | ||
| 88 | { | ||
| 89 | } | ||
| 90 | |||
| 91 | |||
| 92 | /* Get DMA residue count. After a DMA transfer, this | ||
| 93 | * should return zero. Reading this while a DMA transfer is | ||
| 94 | * still in progress will return unpredictable results. | ||
| 95 | * If called before the channel has been used, it may return 1. | ||
| 96 | * Otherwise, it returns the number of _bytes_ left to transfer. | ||
| 97 | * | ||
| 98 | * Assumes DMA flip-flop is clear. | ||
| 99 | */ | ||
| 100 | static inline int get_dma_residue(unsigned int dmanr) | ||
| 101 | { | ||
| 102 | return 0; | ||
| 103 | } | ||
| 104 | |||
| 105 | |||
| 106 | /* These are in kernel/dma.c: */ | ||
| 107 | extern int request_dma(unsigned int dmanr, const char *device_id); | ||
| 108 | extern void free_dma(unsigned int dmanr); | ||
| 109 | |||
| 110 | /* From PCI */ | ||
| 111 | |||
| 112 | #ifdef CONFIG_PCI | ||
| 113 | extern int isa_dma_bridge_buggy; | ||
| 114 | #else | ||
| 115 | #define isa_dma_bridge_buggy (0) | ||
| 116 | #endif | ||
| 117 | |||
| 118 | #endif /* _ASM_DMA_H */ | ||
diff --git a/include/asm-mn10300/dmactl-regs.h b/include/asm-mn10300/dmactl-regs.h new file mode 100644 index 000000000000..58a199da0f4a --- /dev/null +++ b/include/asm-mn10300/dmactl-regs.h | |||
| @@ -0,0 +1,101 @@ | |||
| 1 | /* MN10300 on-board DMA controller registers | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_DMACTL_REGS_H | ||
| 12 | #define _ASM_DMACTL_REGS_H | ||
| 13 | |||
| 14 | #include <asm/cpu-regs.h> | ||
| 15 | |||
| 16 | #ifdef __KERNEL__ | ||
| 17 | |||
| 18 | /* DMA registers */ | ||
| 19 | #define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */ | ||
| 20 | #define DMxCTR_BG 0x0000001f /* transfer request source */ | ||
| 21 | #define DMxCTR_BG_SOFT 0x00000000 /* - software source */ | ||
| 22 | #define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */ | ||
| 23 | #define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */ | ||
| 24 | #define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */ | ||
| 25 | #define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */ | ||
| 26 | #define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */ | ||
| 27 | #define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */ | ||
| 28 | #define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */ | ||
| 29 | #define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */ | ||
| 30 | #define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */ | ||
| 31 | #define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */ | ||
| 32 | #define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */ | ||
| 33 | #define DMxCTR_BG_AFE 0x0000000d /* - analogue front-end interrupt source */ | ||
| 34 | #define DMxCTR_BG_ADC 0x0000000e /* - A/D conversion end interrupt source */ | ||
| 35 | #define DMxCTR_BG_IRDA 0x0000000f /* - IrDA interrupt source */ | ||
| 36 | #define DMxCTR_BG_RTC 0x00000010 /* - RTC interrupt source */ | ||
| 37 | #define DMxCTR_BG_XIRQ0 0x00000011 /* - XIRQ0 pin interrupt source */ | ||
| 38 | #define DMxCTR_BG_XIRQ1 0x00000012 /* - XIRQ1 pin interrupt source */ | ||
| 39 | #define DMxCTR_BG_XDMR0 0x00000013 /* - external request 0 source (XDMR0 pin) */ | ||
| 40 | #define DMxCTR_BG_XDMR1 0x00000014 /* - external request 1 source (XDMR1 pin) */ | ||
| 41 | #define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */ | ||
| 42 | #define DMxCTR_SAM_INCR 0x00000000 /* - increment */ | ||
| 43 | #define DMxCTR_SAM_DECR 0x00000020 /* - decrement */ | ||
| 44 | #define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */ | ||
| 45 | #define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */ | ||
| 46 | #define DMxCTR_DAM_INCR 0x00000000 /* - increment */ | ||
| 47 | #define DMxCTR_DAM_DECR 0x00000100 /* - decrement */ | ||
| 48 | #define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */ | ||
| 49 | #define DMxCTR_TM 0x00001800 /* DMA transfer mode */ | ||
| 50 | #define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */ | ||
| 51 | #define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */ | ||
| 52 | #define DMxCTR_UT 0x00006000 /* DMA transfer unit */ | ||
| 53 | #define DMxCTR_UT_1 0x00000000 /* - 1 byte */ | ||
| 54 | #define DMxCTR_UT_2 0x00002000 /* - 2 byte */ | ||
| 55 | #define DMxCTR_UT_4 0x00004000 /* - 4 byte */ | ||
| 56 | #define DMxCTR_UT_16 0x00006000 /* - 16 byte */ | ||
| 57 | #define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */ | ||
| 58 | #define DMxCTR_RQM 0x00060000 /* external request input source mode */ | ||
| 59 | #define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */ | ||
| 60 | #define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */ | ||
| 61 | #define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */ | ||
| 62 | #define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */ | ||
| 63 | #define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */ | ||
| 64 | #define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */ | ||
| 65 | |||
| 66 | #define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */ | ||
| 67 | |||
| 68 | #define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */ | ||
| 69 | |||
| 70 | #define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */ | ||
| 71 | #define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */ | ||
| 72 | |||
| 73 | #define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent | ||
| 74 | * size reg */ | ||
| 75 | #define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */ | ||
| 76 | |||
| 77 | #define DM0IRQ 16 /* DMA channel 0 complete IRQ */ | ||
| 78 | #define DM1IRQ 17 /* DMA channel 1 complete IRQ */ | ||
| 79 | #define DM2IRQ 18 /* DMA channel 2 complete IRQ */ | ||
| 80 | #define DM3IRQ 19 /* DMA channel 3 complete IRQ */ | ||
| 81 | |||
| 82 | #define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */ | ||
| 83 | #define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */ | ||
| 84 | #define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */ | ||
| 85 | #define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */ | ||
| 86 | |||
| 87 | #ifndef __ASSEMBLY__ | ||
| 88 | |||
| 89 | struct mn10300_dmactl_regs { | ||
| 90 | u32 ctr; | ||
| 91 | const void *src; | ||
| 92 | void *dst; | ||
| 93 | u32 siz; | ||
| 94 | u32 cyc; | ||
| 95 | } __attribute__((aligned(0x100))); | ||
| 96 | |||
| 97 | #endif /* __ASSEMBLY__ */ | ||
| 98 | |||
| 99 | #endif /* __KERNEL__ */ | ||
| 100 | |||
| 101 | #endif /* _ASM_DMACTL_REGS_H */ | ||
diff --git a/include/asm-mn10300/elf.h b/include/asm-mn10300/elf.h new file mode 100644 index 000000000000..256a70466ca4 --- /dev/null +++ b/include/asm-mn10300/elf.h | |||
| @@ -0,0 +1,147 @@ | |||
| 1 | /* MN10300 ELF constant and register definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * Written by David Howells (dhowells@redhat.com) | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #ifndef _ASM_ELF_H | ||
| 13 | #define _ASM_ELF_H | ||
| 14 | |||
| 15 | #include <linux/utsname.h> | ||
| 16 | #include <asm/ptrace.h> | ||
| 17 | #include <asm/user.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * AM33 relocations | ||
| 21 | */ | ||
| 22 | #define R_MN10300_NONE 0 /* No reloc. */ | ||
| 23 | #define R_MN10300_32 1 /* Direct 32 bit. */ | ||
| 24 | #define R_MN10300_16 2 /* Direct 16 bit. */ | ||
| 25 | #define R_MN10300_8 3 /* Direct 8 bit. */ | ||
| 26 | #define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ | ||
| 27 | #define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ | ||
| 28 | #define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ | ||
| 29 | #define R_MN10300_24 9 /* Direct 24 bit. */ | ||
| 30 | #define R_MN10300_RELATIVE 23 /* Adjust by program base. */ | ||
| 31 | |||
| 32 | /* | ||
| 33 | * ELF register definitions.. | ||
| 34 | */ | ||
| 35 | typedef unsigned long elf_greg_t; | ||
| 36 | |||
| 37 | #define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) | ||
| 38 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | ||
| 39 | |||
| 40 | #define ELF_NFPREG 32 | ||
| 41 | typedef float elf_fpreg_t; | ||
| 42 | |||
| 43 | typedef struct { | ||
| 44 | elf_fpreg_t fpregs[ELF_NFPREG]; | ||
| 45 | u_int32_t fpcr; | ||
| 46 | } elf_fpregset_t; | ||
| 47 | |||
| 48 | extern int dump_fpu(struct pt_regs *, elf_fpregset_t *); | ||
| 49 | |||
| 50 | /* | ||
| 51 | * This is used to ensure we don't load something for the wrong architecture | ||
| 52 | */ | ||
| 53 | #define elf_check_arch(x) \ | ||
| 54 | (((x)->e_machine == EM_CYGNUS_MN10300) || \ | ||
| 55 | ((x)->e_machine == EM_MN10300)) | ||
| 56 | |||
| 57 | /* | ||
| 58 | * These are used to set parameters in the core dumps. | ||
| 59 | */ | ||
| 60 | #define ELF_CLASS ELFCLASS32 | ||
| 61 | #define ELF_DATA ELFDATA2LSB | ||
| 62 | #define ELF_ARCH EM_MN10300 | ||
| 63 | |||
| 64 | /* | ||
| 65 | * ELF process initialiser | ||
| 66 | */ | ||
| 67 | #define ELF_PLAT_INIT(_r, load_addr) \ | ||
| 68 | do { \ | ||
| 69 | struct pt_regs *_ur = current->thread.uregs; \ | ||
| 70 | _ur->a3 = 0; _ur->a2 = 0; _ur->d3 = 0; _ur->d2 = 0; \ | ||
| 71 | _ur->mcvf = 0; _ur->mcrl = 0; _ur->mcrh = 0; _ur->mdrq = 0; \ | ||
| 72 | _ur->e1 = 0; _ur->e0 = 0; _ur->e7 = 0; _ur->e6 = 0; \ | ||
| 73 | _ur->e5 = 0; _ur->e4 = 0; _ur->e3 = 0; _ur->e2 = 0; \ | ||
| 74 | _ur->lar = 0; _ur->lir = 0; _ur->mdr = 0; \ | ||
| 75 | _ur->a1 = 0; _ur->a0 = 0; _ur->d1 = 0; _ur->d0 = 0; \ | ||
| 76 | } while (0) | ||
| 77 | |||
| 78 | #define USE_ELF_CORE_DUMP | ||
| 79 | #define ELF_EXEC_PAGESIZE 4096 | ||
| 80 | |||
| 81 | /* | ||
| 82 | * This is the location that an ET_DYN program is loaded if exec'ed. Typical | ||
| 83 | * use of this is to invoke "./ld.so someprog" to test out a new version of | ||
| 84 | * the loader. We need to make sure that it is out of the way of the program | ||
| 85 | * that it will "exec", and that there is sufficient room for the brk. | ||
| 86 | * - must clear the VMALLOC area | ||
| 87 | */ | ||
| 88 | #define ELF_ET_DYN_BASE 0x04000000 | ||
| 89 | |||
| 90 | /* | ||
| 91 | * regs is struct pt_regs, pr_reg is elf_gregset_t (which is | ||
| 92 | * now struct user_regs, they are different) | ||
| 93 | * - ELF_CORE_COPY_REGS has been guessed, and may be wrong | ||
| 94 | */ | ||
| 95 | #define ELF_CORE_COPY_REGS(pr_reg, regs) \ | ||
| 96 | do { \ | ||
| 97 | pr_reg[0] = regs->a3; \ | ||
| 98 | pr_reg[1] = regs->a2; \ | ||
| 99 | pr_reg[2] = regs->d3; \ | ||
| 100 | pr_reg[3] = regs->d2; \ | ||
| 101 | pr_reg[4] = regs->mcvf; \ | ||
| 102 | pr_reg[5] = regs->mcrl; \ | ||
| 103 | pr_reg[6] = regs->mcrh; \ | ||
| 104 | pr_reg[7] = regs->mdrq; \ | ||
| 105 | pr_reg[8] = regs->e1; \ | ||
| 106 | pr_reg[9] = regs->e0; \ | ||
| 107 | pr_reg[10] = regs->e7; \ | ||
| 108 | pr_reg[11] = regs->e6; \ | ||
| 109 | pr_reg[12] = regs->e5; \ | ||
| 110 | pr_reg[13] = regs->e4; \ | ||
| 111 | pr_reg[14] = regs->e3; \ | ||
| 112 | pr_reg[15] = regs->e2; \ | ||
| 113 | pr_reg[16] = regs->sp; \ | ||
| 114 | pr_reg[17] = regs->lar; \ | ||
| 115 | pr_reg[18] = regs->lir; \ | ||
| 116 | pr_reg[19] = regs->mdr; \ | ||
| 117 | pr_reg[20] = regs->a1; \ | ||
| 118 | pr_reg[21] = regs->a0; \ | ||
| 119 | pr_reg[22] = regs->d1; \ | ||
| 120 | pr_reg[23] = regs->d0; \ | ||
| 121 | pr_reg[24] = regs->orig_d0; \ | ||
| 122 | pr_reg[25] = regs->epsw; \ | ||
| 123 | pr_reg[26] = regs->pc; \ | ||
| 124 | } while (0); | ||
| 125 | |||
| 126 | /* | ||
| 127 | * This yields a mask that user programs can use to figure out what | ||
| 128 | * instruction set this CPU supports. This could be done in user space, | ||
| 129 | * but it's not easy, and we've already done it here. | ||
| 130 | */ | ||
| 131 | #define ELF_HWCAP (0) | ||
| 132 | |||
| 133 | /* | ||
| 134 | * This yields a string that ld.so will use to load implementation | ||
| 135 | * specific libraries for optimization. This is more specific in | ||
| 136 | * intent than poking at uname or /proc/cpuinfo. | ||
| 137 | * | ||
| 138 | * For the moment, we have only optimizations for the Intel generations, | ||
| 139 | * but that could change... | ||
| 140 | */ | ||
| 141 | #define ELF_PLATFORM (NULL) | ||
| 142 | |||
| 143 | #ifdef __KERNEL__ | ||
| 144 | #define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX) | ||
| 145 | #endif | ||
| 146 | |||
| 147 | #endif /* _ASM_ELF_H */ | ||
diff --git a/include/asm-mn10300/emergency-restart.h b/include/asm-mn10300/emergency-restart.h new file mode 100644 index 000000000000..3711bd9d50bd --- /dev/null +++ b/include/asm-mn10300/emergency-restart.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/emergency-restart.h> | |||
diff --git a/include/asm-mn10300/errno.h b/include/asm-mn10300/errno.h new file mode 100644 index 000000000000..4c82b503d92f --- /dev/null +++ b/include/asm-mn10300/errno.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/errno.h> | |||
diff --git a/include/asm-mn10300/exceptions.h b/include/asm-mn10300/exceptions.h new file mode 100644 index 000000000000..fa16466ef3f9 --- /dev/null +++ b/include/asm-mn10300/exceptions.h | |||
| @@ -0,0 +1,121 @@ | |||
| 1 | /* MN10300 Microcontroller core exceptions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_EXCEPTIONS_H | ||
| 12 | #define _ASM_EXCEPTIONS_H | ||
| 13 | |||
| 14 | #include <linux/linkage.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * define the breakpoint instruction opcode to use | ||
| 18 | * - note that the JTAG unit steals 0xFF, so we want to avoid that if we can | ||
| 19 | * (can use 0xF7) | ||
| 20 | */ | ||
| 21 | #define GDBSTUB_BKPT 0xFF | ||
| 22 | |||
| 23 | #ifndef __ASSEMBLY__ | ||
| 24 | |||
| 25 | /* | ||
| 26 | * enumeration of exception codes (as extracted from TBR MSW) | ||
| 27 | */ | ||
| 28 | enum exception_code { | ||
| 29 | EXCEP_RESET = 0x000000, /* reset */ | ||
| 30 | |||
| 31 | /* MMU exceptions */ | ||
| 32 | EXCEP_ITLBMISS = 0x000100, /* instruction TLB miss */ | ||
| 33 | EXCEP_DTLBMISS = 0x000108, /* data TLB miss */ | ||
| 34 | EXCEP_IAERROR = 0x000110, /* instruction address */ | ||
| 35 | EXCEP_DAERROR = 0x000118, /* data address */ | ||
| 36 | |||
| 37 | /* system exceptions */ | ||
| 38 | EXCEP_TRAP = 0x000128, /* program interrupt (PI instruction) */ | ||
| 39 | EXCEP_ISTEP = 0x000130, /* single step */ | ||
| 40 | EXCEP_IBREAK = 0x000150, /* instruction breakpoint */ | ||
| 41 | EXCEP_OBREAK = 0x000158, /* operand breakpoint */ | ||
| 42 | EXCEP_PRIVINS = 0x000160, /* privileged instruction execution */ | ||
| 43 | EXCEP_UNIMPINS = 0x000168, /* unimplemented instruction execution */ | ||
| 44 | EXCEP_UNIMPEXINS = 0x000170, /* unimplemented extended instruction execution */ | ||
| 45 | EXCEP_MEMERR = 0x000178, /* illegal memory access */ | ||
| 46 | EXCEP_MISALIGN = 0x000180, /* misalignment */ | ||
| 47 | EXCEP_BUSERROR = 0x000188, /* bus error */ | ||
| 48 | EXCEP_ILLINSACC = 0x000190, /* illegal instruction access */ | ||
| 49 | EXCEP_ILLDATACC = 0x000198, /* illegal data access */ | ||
| 50 | EXCEP_IOINSACC = 0x0001a0, /* I/O space instruction access */ | ||
| 51 | EXCEP_PRIVINSACC = 0x0001a8, /* privileged space instruction access */ | ||
| 52 | EXCEP_PRIVDATACC = 0x0001b0, /* privileged space data access */ | ||
| 53 | EXCEP_DATINSACC = 0x0001b8, /* data space instruction access */ | ||
| 54 | EXCEP_DOUBLE_FAULT = 0x000200, /* double fault */ | ||
| 55 | |||
| 56 | /* FPU exceptions */ | ||
| 57 | EXCEP_FPU_DISABLED = 0x0001c0, /* FPU disabled */ | ||
| 58 | EXCEP_FPU_UNIMPINS = 0x0001c8, /* FPU unimplemented operation */ | ||
| 59 | EXCEP_FPU_OPERATION = 0x0001d0, /* FPU operation */ | ||
| 60 | |||
| 61 | /* interrupts */ | ||
| 62 | EXCEP_WDT = 0x000240, /* watchdog timer overflow */ | ||
| 63 | EXCEP_NMI = 0x000248, /* non-maskable interrupt */ | ||
| 64 | EXCEP_IRQ_LEVEL0 = 0x000280, /* level 0 maskable interrupt */ | ||
| 65 | EXCEP_IRQ_LEVEL1 = 0x000288, /* level 1 maskable interrupt */ | ||
| 66 | EXCEP_IRQ_LEVEL2 = 0x000290, /* level 2 maskable interrupt */ | ||
| 67 | EXCEP_IRQ_LEVEL3 = 0x000298, /* level 3 maskable interrupt */ | ||
| 68 | EXCEP_IRQ_LEVEL4 = 0x0002a0, /* level 4 maskable interrupt */ | ||
| 69 | EXCEP_IRQ_LEVEL5 = 0x0002a8, /* level 5 maskable interrupt */ | ||
| 70 | EXCEP_IRQ_LEVEL6 = 0x0002b0, /* level 6 maskable interrupt */ | ||
| 71 | |||
| 72 | /* system calls */ | ||
| 73 | EXCEP_SYSCALL0 = 0x000300, /* system call 0 */ | ||
| 74 | EXCEP_SYSCALL1 = 0x000308, /* system call 1 */ | ||
| 75 | EXCEP_SYSCALL2 = 0x000310, /* system call 2 */ | ||
| 76 | EXCEP_SYSCALL3 = 0x000318, /* system call 3 */ | ||
| 77 | EXCEP_SYSCALL4 = 0x000320, /* system call 4 */ | ||
| 78 | EXCEP_SYSCALL5 = 0x000328, /* system call 5 */ | ||
| 79 | EXCEP_SYSCALL6 = 0x000330, /* system call 6 */ | ||
| 80 | EXCEP_SYSCALL7 = 0x000338, /* system call 7 */ | ||
| 81 | EXCEP_SYSCALL8 = 0x000340, /* system call 8 */ | ||
| 82 | EXCEP_SYSCALL9 = 0x000348, /* system call 9 */ | ||
| 83 | EXCEP_SYSCALL10 = 0x000350, /* system call 10 */ | ||
| 84 | EXCEP_SYSCALL11 = 0x000358, /* system call 11 */ | ||
| 85 | EXCEP_SYSCALL12 = 0x000360, /* system call 12 */ | ||
| 86 | EXCEP_SYSCALL13 = 0x000368, /* system call 13 */ | ||
| 87 | EXCEP_SYSCALL14 = 0x000370, /* system call 14 */ | ||
| 88 | EXCEP_SYSCALL15 = 0x000378, /* system call 15 */ | ||
| 89 | }; | ||
| 90 | |||
| 91 | extern void __set_intr_stub(enum exception_code code, void *handler); | ||
| 92 | extern void set_intr_stub(enum exception_code code, void *handler); | ||
| 93 | extern void set_jtag_stub(enum exception_code code, void *handler); | ||
| 94 | |||
| 95 | struct pt_regs; | ||
| 96 | |||
| 97 | extern asmlinkage void __common_exception(void); | ||
| 98 | extern asmlinkage void itlb_miss(void); | ||
| 99 | extern asmlinkage void dtlb_miss(void); | ||
| 100 | extern asmlinkage void itlb_aerror(void); | ||
| 101 | extern asmlinkage void dtlb_aerror(void); | ||
| 102 | extern asmlinkage void raw_bus_error(void); | ||
| 103 | extern asmlinkage void double_fault(void); | ||
| 104 | extern asmlinkage int system_call(struct pt_regs *); | ||
| 105 | extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code); | ||
| 106 | extern asmlinkage void nmi(struct pt_regs *, enum exception_code); | ||
| 107 | extern asmlinkage void uninitialised_exception(struct pt_regs *, | ||
| 108 | enum exception_code); | ||
| 109 | extern asmlinkage void irq_handler(void); | ||
| 110 | extern asmlinkage void profile_handler(void); | ||
| 111 | extern asmlinkage void nmi_handler(void); | ||
| 112 | extern asmlinkage void misalignment(struct pt_regs *, enum exception_code); | ||
| 113 | |||
| 114 | extern void die(const char *, struct pt_regs *, enum exception_code) | ||
| 115 | ATTRIB_NORET; | ||
| 116 | |||
| 117 | extern int die_if_no_fixup(const char *, struct pt_regs *, enum exception_code); | ||
| 118 | |||
| 119 | #endif /* __ASSEMBLY__ */ | ||
| 120 | |||
| 121 | #endif /* _ASM_EXCEPTIONS_H */ | ||
diff --git a/include/asm-mn10300/fb.h b/include/asm-mn10300/fb.h new file mode 100644 index 000000000000..697b24a91e1a --- /dev/null +++ b/include/asm-mn10300/fb.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* MN10300 Frame buffer stuff | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_FB_H | ||
| 12 | #define _ASM_FB_H | ||
| 13 | |||
| 14 | #include <linux/fb.h> | ||
| 15 | |||
| 16 | #define fb_pgprotect(...) do {} while (0) | ||
| 17 | |||
| 18 | static inline int fb_is_primary_device(struct fb_info *info) | ||
| 19 | { | ||
| 20 | return 0; | ||
| 21 | } | ||
| 22 | |||
| 23 | #endif /* _ASM_FB_H */ | ||
diff --git a/include/asm-mn10300/fcntl.h b/include/asm-mn10300/fcntl.h new file mode 100644 index 000000000000..46ab12db5739 --- /dev/null +++ b/include/asm-mn10300/fcntl.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/fcntl.h> | |||
diff --git a/include/asm-mn10300/fpu.h b/include/asm-mn10300/fpu.h new file mode 100644 index 000000000000..64a2b83a7a6a --- /dev/null +++ b/include/asm-mn10300/fpu.h | |||
| @@ -0,0 +1,85 @@ | |||
| 1 | /* MN10300 FPU definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * Derived from include/asm-i386/i387.h: Copyright (C) 1994 Linus Torvalds | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #ifndef _ASM_FPU_H | ||
| 13 | #define _ASM_FPU_H | ||
| 14 | |||
| 15 | #include <asm/processor.h> | ||
| 16 | #include <asm/sigcontext.h> | ||
| 17 | #include <asm/user.h> | ||
| 18 | |||
| 19 | #ifdef __KERNEL__ | ||
| 20 | |||
| 21 | /* the task that owns the FPU state */ | ||
| 22 | extern struct task_struct *fpu_state_owner; | ||
| 23 | |||
| 24 | #define set_using_fpu(tsk) \ | ||
| 25 | do { \ | ||
| 26 | (tsk)->thread.fpu_flags |= THREAD_USING_FPU; \ | ||
| 27 | } while (0) | ||
| 28 | |||
| 29 | #define clear_using_fpu(tsk) \ | ||
| 30 | do { \ | ||
| 31 | (tsk)->thread.fpu_flags &= ~THREAD_USING_FPU; \ | ||
| 32 | } while (0) | ||
| 33 | |||
| 34 | #define is_using_fpu(tsk) ((tsk)->thread.fpu_flags & THREAD_USING_FPU) | ||
| 35 | |||
| 36 | #define unlazy_fpu(tsk) \ | ||
| 37 | do { \ | ||
| 38 | preempt_disable(); \ | ||
| 39 | if (fpu_state_owner == (tsk)) \ | ||
| 40 | fpu_save(&tsk->thread.fpu_state); \ | ||
| 41 | preempt_enable(); \ | ||
| 42 | } while (0) | ||
| 43 | |||
| 44 | #define exit_fpu() \ | ||
| 45 | do { \ | ||
| 46 | struct task_struct *__tsk = current; \ | ||
| 47 | preempt_disable(); \ | ||
| 48 | if (fpu_state_owner == __tsk) \ | ||
| 49 | fpu_state_owner = NULL; \ | ||
| 50 | preempt_enable(); \ | ||
| 51 | } while (0) | ||
| 52 | |||
| 53 | #define flush_fpu() \ | ||
| 54 | do { \ | ||
| 55 | struct task_struct *__tsk = current; \ | ||
| 56 | preempt_disable(); \ | ||
| 57 | if (fpu_state_owner == __tsk) { \ | ||
| 58 | fpu_state_owner = NULL; \ | ||
| 59 | __tsk->thread.uregs->epsw &= ~EPSW_FE; \ | ||
| 60 | } \ | ||
| 61 | preempt_enable(); \ | ||
| 62 | clear_using_fpu(__tsk); \ | ||
| 63 | } while (0) | ||
| 64 | |||
| 65 | extern asmlinkage void fpu_init_state(void); | ||
| 66 | extern asmlinkage void fpu_kill_state(struct task_struct *); | ||
| 67 | extern asmlinkage void fpu_disabled(struct pt_regs *, enum exception_code); | ||
| 68 | extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code); | ||
| 69 | |||
| 70 | #ifdef CONFIG_FPU | ||
| 71 | extern asmlinkage void fpu_save(struct fpu_state_struct *); | ||
| 72 | extern asmlinkage void fpu_restore(struct fpu_state_struct *); | ||
| 73 | #else | ||
| 74 | #define fpu_save(a) | ||
| 75 | #define fpu_restore(a) | ||
| 76 | #endif /* CONFIG_FPU */ | ||
| 77 | |||
| 78 | /* | ||
| 79 | * signal frame handlers | ||
| 80 | */ | ||
| 81 | extern int fpu_setup_sigcontext(struct fpucontext *buf); | ||
| 82 | extern int fpu_restore_sigcontext(struct fpucontext *buf); | ||
| 83 | |||
| 84 | #endif /* __KERNEL__ */ | ||
| 85 | #endif /* _ASM_FPU_H */ | ||
diff --git a/include/asm-mn10300/frame.inc b/include/asm-mn10300/frame.inc new file mode 100644 index 000000000000..5b1949bdf039 --- /dev/null +++ b/include/asm-mn10300/frame.inc | |||
| @@ -0,0 +1,91 @@ | |||
| 1 | /* MN10300 Microcontroller core system register definitions -*- asm -*- | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_FRAME_INC | ||
| 12 | #define _ASM_FRAME_INC | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | #error not for use in C files | ||
| 16 | #endif | ||
| 17 | |||
| 18 | #ifndef __ASM_OFFSETS_H__ | ||
| 19 | #include <asm/asm-offsets.h> | ||
| 20 | #endif | ||
| 21 | |||
| 22 | #define pi break | ||
| 23 | |||
| 24 | #define fp a3 | ||
| 25 | |||
| 26 | ############################################################################### | ||
| 27 | # | ||
| 28 | # build a stack frame from the registers | ||
| 29 | # - the caller has subtracted 4 from SP before coming here | ||
| 30 | # | ||
| 31 | ############################################################################### | ||
| 32 | .macro SAVE_ALL | ||
| 33 | add -4,sp # next exception frame ptr save area | ||
| 34 | movm [other],(sp) | ||
| 35 | mov usp,a1 | ||
| 36 | mov a1,(sp) # USP in MOVM[other] dummy slot | ||
| 37 | movm [d2,d3,a2,a3,exreg0,exreg1,exother],(sp) | ||
| 38 | mov sp,fp # FRAME pointer in A3 | ||
| 39 | add -12,sp # allow for calls to be made | ||
| 40 | mov (__frame),a1 | ||
| 41 | mov a1,(REG_NEXT,fp) | ||
| 42 | mov fp,(__frame) | ||
| 43 | |||
| 44 | and ~EPSW_FE,epsw # disable the FPU inside the kernel | ||
| 45 | |||
| 46 | # we may be holding current in E2 | ||
| 47 | #ifdef CONFIG_MN10300_CURRENT_IN_E2 | ||
| 48 | mov (__current),e2 | ||
| 49 | #endif | ||
| 50 | .endm | ||
| 51 | |||
| 52 | ############################################################################### | ||
| 53 | # | ||
| 54 | # restore the registers from a stack frame | ||
| 55 | # | ||
| 56 | ############################################################################### | ||
| 57 | .macro RESTORE_ALL | ||
| 58 | # peel back the stack to the calling frame | ||
| 59 | # - this permits execve() to discard extra frames due to kernel syscalls | ||
| 60 | mov (__frame),fp | ||
| 61 | mov fp,sp | ||
| 62 | mov (REG_NEXT,fp),d0 # userspace has regs->next == 0 | ||
| 63 | mov d0,(__frame) | ||
| 64 | |||
| 65 | #ifndef CONFIG_MN10300_USING_JTAG | ||
| 66 | mov (REG_EPSW,fp),d0 | ||
| 67 | btst EPSW_T,d0 | ||
| 68 | beq 99f | ||
| 69 | |||
| 70 | or EPSW_NMID,epsw | ||
| 71 | movhu (DCR),d1 | ||
| 72 | or 0x0001, d1 | ||
| 73 | movhu d1,(DCR) | ||
| 74 | |||
| 75 | 99: | ||
| 76 | #endif | ||
| 77 | movm (sp),[d2,d3,a2,a3,exreg0,exreg1,exother] | ||
| 78 | |||
| 79 | # must restore usp even if returning to kernel space, | ||
| 80 | # when CONFIG_PREEMPT is enabled. | ||
| 81 | mov (sp),a1 # USP in MOVM[other] dummy slot | ||
| 82 | mov a1,usp | ||
| 83 | |||
| 84 | movm (sp),[other] | ||
| 85 | add 8,sp | ||
| 86 | rti | ||
| 87 | |||
| 88 | .endm | ||
| 89 | |||
| 90 | |||
| 91 | #endif /* _ASM_FRAME_INC */ | ||
diff --git a/include/asm-mn10300/futex.h b/include/asm-mn10300/futex.h new file mode 100644 index 000000000000..0b745828f42b --- /dev/null +++ b/include/asm-mn10300/futex.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/futex.h> | |||
diff --git a/include/asm-mn10300/gdb-stub.h b/include/asm-mn10300/gdb-stub.h new file mode 100644 index 000000000000..e5a6368559af --- /dev/null +++ b/include/asm-mn10300/gdb-stub.h | |||
| @@ -0,0 +1,183 @@ | |||
| 1 | /* MN10300 Kernel GDB stub definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * - Derived from asm-mips/gdb-stub.h (c) 1995 Andreas Busse | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #ifndef _ASM_GDB_STUB_H | ||
| 13 | #define _ASM_GDB_STUB_H | ||
| 14 | |||
| 15 | #include <asm/exceptions.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * register ID numbers in GDB remote protocol | ||
| 19 | */ | ||
| 20 | |||
| 21 | #define GDB_REGID_PC 9 | ||
| 22 | #define GDB_REGID_FP 7 | ||
| 23 | #define GDB_REGID_SP 8 | ||
| 24 | |||
| 25 | /* | ||
| 26 | * virtual stack layout for the GDB exception handler | ||
| 27 | */ | ||
| 28 | #define NUMREGS 64 | ||
| 29 | |||
| 30 | #define GDB_FR_D0 (0 * 4) | ||
| 31 | #define GDB_FR_D1 (1 * 4) | ||
| 32 | #define GDB_FR_D2 (2 * 4) | ||
| 33 | #define GDB_FR_D3 (3 * 4) | ||
| 34 | #define GDB_FR_A0 (4 * 4) | ||
| 35 | #define GDB_FR_A1 (5 * 4) | ||
| 36 | #define GDB_FR_A2 (6 * 4) | ||
| 37 | #define GDB_FR_A3 (7 * 4) | ||
| 38 | |||
| 39 | #define GDB_FR_SP (8 * 4) | ||
| 40 | #define GDB_FR_PC (9 * 4) | ||
| 41 | #define GDB_FR_MDR (10 * 4) | ||
| 42 | #define GDB_FR_EPSW (11 * 4) | ||
| 43 | #define GDB_FR_LIR (12 * 4) | ||
| 44 | #define GDB_FR_LAR (13 * 4) | ||
| 45 | #define GDB_FR_MDRQ (14 * 4) | ||
| 46 | |||
| 47 | #define GDB_FR_E0 (15 * 4) | ||
| 48 | #define GDB_FR_E1 (16 * 4) | ||
| 49 | #define GDB_FR_E2 (17 * 4) | ||
| 50 | #define GDB_FR_E3 (18 * 4) | ||
| 51 | #define GDB_FR_E4 (19 * 4) | ||
| 52 | #define GDB_FR_E5 (20 * 4) | ||
| 53 | #define GDB_FR_E6 (21 * 4) | ||
| 54 | #define GDB_FR_E7 (22 * 4) | ||
| 55 | |||
| 56 | #define GDB_FR_SSP (23 * 4) | ||
| 57 | #define GDB_FR_MSP (24 * 4) | ||
| 58 | #define GDB_FR_USP (25 * 4) | ||
| 59 | #define GDB_FR_MCRH (26 * 4) | ||
| 60 | #define GDB_FR_MCRL (27 * 4) | ||
| 61 | #define GDB_FR_MCVF (28 * 4) | ||
| 62 | |||
| 63 | #define GDB_FR_FPCR (29 * 4) | ||
| 64 | #define GDB_FR_DUMMY0 (30 * 4) | ||
| 65 | #define GDB_FR_DUMMY1 (31 * 4) | ||
| 66 | |||
| 67 | #define GDB_FR_FS0 (32 * 4) | ||
| 68 | |||
| 69 | #define GDB_FR_SIZE (NUMREGS * 4) | ||
| 70 | |||
| 71 | #ifndef __ASSEMBLY__ | ||
| 72 | |||
| 73 | /* | ||
| 74 | * This is the same as above, but for the high-level | ||
| 75 | * part of the GDB stub. | ||
| 76 | */ | ||
| 77 | |||
| 78 | struct gdb_regs { | ||
| 79 | /* saved main processor registers */ | ||
| 80 | u32 d0, d1, d2, d3, a0, a1, a2, a3; | ||
| 81 | u32 sp, pc, mdr, epsw, lir, lar, mdrq; | ||
| 82 | u32 e0, e1, e2, e3, e4, e5, e6, e7; | ||
| 83 | u32 ssp, msp, usp, mcrh, mcrl, mcvf; | ||
| 84 | |||
| 85 | /* saved floating point registers */ | ||
| 86 | u32 fpcr, _dummy0, _dummy1; | ||
| 87 | u32 fs0, fs1, fs2, fs3, fs4, fs5, fs6, fs7; | ||
| 88 | u32 fs8, fs9, fs10, fs11, fs12, fs13, fs14, fs15; | ||
| 89 | u32 fs16, fs17, fs18, fs19, fs20, fs21, fs22, fs23; | ||
| 90 | u32 fs24, fs25, fs26, fs27, fs28, fs29, fs30, fs31; | ||
| 91 | }; | ||
| 92 | |||
| 93 | /* | ||
| 94 | * Prototypes | ||
| 95 | */ | ||
| 96 | extern void show_registers_only(struct pt_regs *regs); | ||
| 97 | |||
| 98 | extern asmlinkage void gdbstub_init(void); | ||
| 99 | extern asmlinkage void gdbstub_exit(int status); | ||
| 100 | extern asmlinkage void gdbstub_io_init(void); | ||
| 101 | extern asmlinkage void gdbstub_io_set_baud(unsigned baud); | ||
| 102 | extern asmlinkage int gdbstub_io_rx_char(unsigned char *_ch, int nonblock); | ||
| 103 | extern asmlinkage void gdbstub_io_tx_char(unsigned char ch); | ||
| 104 | extern asmlinkage void gdbstub_io_tx_flush(void); | ||
| 105 | |||
| 106 | extern asmlinkage void gdbstub_io_rx_handler(void); | ||
| 107 | extern asmlinkage void gdbstub_rx_irq(struct pt_regs *, enum exception_code); | ||
| 108 | extern asmlinkage int gdbstub_intercept(struct pt_regs *, enum exception_code); | ||
| 109 | extern asmlinkage void gdbstub_exception(struct pt_regs *, enum exception_code); | ||
| 110 | extern asmlinkage void __gdbstub_bug_trap(void); | ||
| 111 | extern asmlinkage void __gdbstub_pause(void); | ||
| 112 | extern asmlinkage void start_kernel(void); | ||
| 113 | |||
| 114 | #ifndef CONFIG_MN10300_CACHE_DISABLED | ||
| 115 | extern asmlinkage void gdbstub_purge_cache(void); | ||
| 116 | #else | ||
| 117 | #define gdbstub_purge_cache() do {} while (0) | ||
| 118 | #endif | ||
| 119 | |||
| 120 | /* Used to prevent crashes in memory access */ | ||
| 121 | extern asmlinkage int gdbstub_read_byte(const u8 *, u8 *); | ||
| 122 | extern asmlinkage int gdbstub_read_word(const u8 *, u8 *); | ||
| 123 | extern asmlinkage int gdbstub_read_dword(const u8 *, u8 *); | ||
| 124 | extern asmlinkage int gdbstub_write_byte(u32, u8 *); | ||
| 125 | extern asmlinkage int gdbstub_write_word(u32, u8 *); | ||
| 126 | extern asmlinkage int gdbstub_write_dword(u32, u8 *); | ||
| 127 | |||
| 128 | extern asmlinkage void gdbstub_read_byte_guard(void); | ||
| 129 | extern asmlinkage void gdbstub_read_byte_cont(void); | ||
| 130 | extern asmlinkage void gdbstub_read_word_guard(void); | ||
| 131 | extern asmlinkage void gdbstub_read_word_cont(void); | ||
| 132 | extern asmlinkage void gdbstub_read_dword_guard(void); | ||
| 133 | extern asmlinkage void gdbstub_read_dword_cont(void); | ||
| 134 | extern asmlinkage void gdbstub_write_byte_guard(void); | ||
| 135 | extern asmlinkage void gdbstub_write_byte_cont(void); | ||
| 136 | extern asmlinkage void gdbstub_write_word_guard(void); | ||
| 137 | extern asmlinkage void gdbstub_write_word_cont(void); | ||
| 138 | extern asmlinkage void gdbstub_write_dword_guard(void); | ||
| 139 | extern asmlinkage void gdbstub_write_dword_cont(void); | ||
| 140 | |||
| 141 | extern u8 gdbstub_rx_buffer[PAGE_SIZE]; | ||
| 142 | extern u32 gdbstub_rx_inp; | ||
| 143 | extern u32 gdbstub_rx_outp; | ||
| 144 | extern u8 gdbstub_rx_overflow; | ||
| 145 | extern u8 gdbstub_busy; | ||
| 146 | extern u8 gdbstub_rx_unget; | ||
| 147 | |||
| 148 | #ifdef CONFIG_GDBSTUB_DEBUGGING | ||
| 149 | extern void gdbstub_printk(const char *fmt, ...) | ||
| 150 | __attribute__((format(printf, 1, 2))); | ||
| 151 | #else | ||
| 152 | static inline __attribute__((format(printf, 1, 2))) | ||
| 153 | void gdbstub_printk(const char *fmt, ...) | ||
| 154 | { | ||
| 155 | } | ||
| 156 | #endif | ||
| 157 | |||
| 158 | #ifdef CONFIG_GDBSTUB_DEBUG_ENTRY | ||
| 159 | #define gdbstub_entry(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) | ||
| 160 | #else | ||
| 161 | #define gdbstub_entry(FMT, ...) ({ 0; }) | ||
| 162 | #endif | ||
| 163 | |||
| 164 | #ifdef CONFIG_GDBSTUB_DEBUG_PROTOCOL | ||
| 165 | #define gdbstub_proto(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) | ||
| 166 | #else | ||
| 167 | #define gdbstub_proto(FMT, ...) ({ 0; }) | ||
| 168 | #endif | ||
| 169 | |||
| 170 | #ifdef CONFIG_GDBSTUB_DEBUG_IO | ||
| 171 | #define gdbstub_io(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) | ||
| 172 | #else | ||
| 173 | #define gdbstub_io(FMT, ...) ({ 0; }) | ||
| 174 | #endif | ||
| 175 | |||
| 176 | #ifdef CONFIG_GDBSTUB_DEBUG_BREAKPOINT | ||
| 177 | #define gdbstub_bkpt(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__) | ||
| 178 | #else | ||
| 179 | #define gdbstub_bkpt(FMT, ...) ({ 0; }) | ||
| 180 | #endif | ||
| 181 | |||
| 182 | #endif /* !__ASSEMBLY__ */ | ||
| 183 | #endif /* _ASM_GDB_STUB_H */ | ||
diff --git a/include/asm-mn10300/hardirq.h b/include/asm-mn10300/hardirq.h new file mode 100644 index 000000000000..54d950117674 --- /dev/null +++ b/include/asm-mn10300/hardirq.h | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* MN10300 Hardware IRQ statistics and management | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * Modified by David Howells (dhowells@redhat.com) | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #ifndef _ASM_HARDIRQ_H | ||
| 13 | #define _ASM_HARDIRQ_H | ||
| 14 | |||
| 15 | #include <linux/threads.h> | ||
| 16 | #include <linux/irq.h> | ||
| 17 | #include <asm/exceptions.h> | ||
| 18 | |||
| 19 | /* assembly code in softirq.h is sensitive to the offsets of these fields */ | ||
| 20 | typedef struct { | ||
| 21 | unsigned int __softirq_pending; | ||
| 22 | unsigned long idle_timestamp; | ||
| 23 | unsigned int __nmi_count; /* arch dependent */ | ||
| 24 | unsigned int __irq_count; /* arch dependent */ | ||
| 25 | } ____cacheline_aligned irq_cpustat_t; | ||
| 26 | |||
| 27 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | ||
| 28 | |||
| 29 | extern void ack_bad_irq(int irq); | ||
| 30 | |||
| 31 | /* | ||
| 32 | * manipulate stubs in the MN10300 CPU Trap/Interrupt Vector table | ||
| 33 | * - these should jump to __common_exception in entry.S unless there's a good | ||
| 34 | * reason to do otherwise (see trap_preinit() in traps.c) | ||
| 35 | */ | ||
| 36 | typedef void (*intr_stub_fnx)(struct pt_regs *regs, | ||
| 37 | enum exception_code intcode); | ||
| 38 | |||
| 39 | /* | ||
| 40 | * manipulate pointers in the Exception table (see entry.S) | ||
| 41 | * - these are indexed by decoding the lower 24 bits of the TBR register | ||
| 42 | * - note that the MN103E010 doesn't always trap through the correct vector, | ||
| 43 | * but does always set the TBR correctly | ||
| 44 | */ | ||
| 45 | extern asmlinkage void set_excp_vector(enum exception_code code, | ||
| 46 | intr_stub_fnx handler); | ||
| 47 | |||
| 48 | #endif /* _ASM_HARDIRQ_H */ | ||
diff --git a/include/asm-mn10300/highmem.h b/include/asm-mn10300/highmem.h new file mode 100644 index 000000000000..383c0c42982e --- /dev/null +++ b/include/asm-mn10300/highmem.h | |||
| @@ -0,0 +1,114 @@ | |||
| 1 | /* MN10300 Virtual kernel memory mappings for high memory | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * - Derived from include/asm-i386/highmem.h | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #ifndef _ASM_HIGHMEM_H | ||
| 13 | #define _ASM_HIGHMEM_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/interrupt.h> | ||
| 19 | #include <asm/kmap_types.h> | ||
| 20 | #include <asm/pgtable.h> | ||
| 21 | |||
| 22 | /* undef for production */ | ||
| 23 | #undef HIGHMEM_DEBUG | ||
| 24 | |||
| 25 | /* declarations for highmem.c */ | ||
| 26 | extern unsigned long highstart_pfn, highend_pfn; | ||
| 27 | |||
| 28 | extern pte_t *kmap_pte; | ||
| 29 | extern pgprot_t kmap_prot; | ||
| 30 | extern pte_t *pkmap_page_table; | ||
| 31 | |||
| 32 | extern void __init kmap_init(void); | ||
| 33 | |||
| 34 | /* | ||
| 35 | * Right now we initialize only a single pte table. It can be extended | ||
| 36 | * easily, subsequent pte tables have to be allocated in one physical | ||
| 37 | * chunk of RAM. | ||
| 38 | */ | ||
| 39 | #define PKMAP_BASE 0xfe000000UL | ||
| 40 | #define LAST_PKMAP 1024 | ||
| 41 | #define LAST_PKMAP_MASK (LAST_PKMAP - 1) | ||
| 42 | #define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT) | ||
| 43 | #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) | ||
| 44 | |||
| 45 | extern unsigned long __fastcall kmap_high(struct page *page); | ||
| 46 | extern void __fastcall kunmap_high(struct page *page); | ||
| 47 | |||
| 48 | static inline unsigned long kmap(struct page *page) | ||
| 49 | { | ||
| 50 | if (in_interrupt()) | ||
| 51 | BUG(); | ||
| 52 | if (page < highmem_start_page) | ||
| 53 | return page_address(page); | ||
| 54 | return kmap_high(page); | ||
| 55 | } | ||
| 56 | |||
| 57 | static inline void kunmap(struct page *page) | ||
| 58 | { | ||
| 59 | if (in_interrupt()) | ||
| 60 | BUG(); | ||
| 61 | if (page < highmem_start_page) | ||
| 62 | return; | ||
| 63 | kunmap_high(page); | ||
| 64 | } | ||
| 65 | |||
| 66 | /* | ||
| 67 | * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap | ||
| 68 | * gives a more generic (and caching) interface. But kmap_atomic can | ||
| 69 | * be used in IRQ contexts, so in some (very limited) cases we need | ||
| 70 | * it. | ||
| 71 | */ | ||
| 72 | static inline unsigned long kmap_atomic(struct page *page, enum km_type type) | ||
| 73 | { | ||
| 74 | enum fixed_addresses idx; | ||
| 75 | unsigned long vaddr; | ||
| 76 | |||
| 77 | if (page < highmem_start_page) | ||
| 78 | return page_address(page); | ||
| 79 | |||
| 80 | idx = type + KM_TYPE_NR * smp_processor_id(); | ||
| 81 | vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 82 | #if HIGHMEM_DEBUG | ||
| 83 | if (!pte_none(*(kmap_pte - idx))) | ||
| 84 | BUG(); | ||
| 85 | #endif | ||
| 86 | set_pte(kmap_pte - idx, mk_pte(page, kmap_prot)); | ||
| 87 | __flush_tlb_one(vaddr); | ||
| 88 | |||
| 89 | return vaddr; | ||
| 90 | } | ||
| 91 | |||
| 92 | static inline void kunmap_atomic(unsigned long vaddr, enum km_type type) | ||
| 93 | { | ||
| 94 | #if HIGHMEM_DEBUG | ||
| 95 | enum fixed_addresses idx = type + KM_TYPE_NR * smp_processor_id(); | ||
| 96 | |||
| 97 | if (vaddr < FIXADDR_START) /* FIXME */ | ||
| 98 | return; | ||
| 99 | |||
| 100 | if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)) | ||
| 101 | BUG(); | ||
| 102 | |||
| 103 | /* | ||
| 104 | * force other mappings to Oops if they'll try to access | ||
| 105 | * this pte without first remap it | ||
| 106 | */ | ||
| 107 | pte_clear(kmap_pte - idx); | ||
| 108 | __flush_tlb_one(vaddr); | ||
| 109 | #endif | ||
| 110 | } | ||
| 111 | |||
| 112 | #endif /* __KERNEL__ */ | ||
| 113 | |||
| 114 | #endif /* _ASM_HIGHMEM_H */ | ||
diff --git a/include/asm-mn10300/hw_irq.h b/include/asm-mn10300/hw_irq.h new file mode 100644 index 000000000000..70619901098e --- /dev/null +++ b/include/asm-mn10300/hw_irq.h | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | /* MN10300 Hardware interrupt definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_HW_IRQ_H | ||
| 12 | #define _ASM_HW_IRQ_H | ||
| 13 | |||
| 14 | #endif /* _ASM_HW_IRQ_H */ | ||
diff --git a/include/asm-mn10300/ide.h b/include/asm-mn10300/ide.h new file mode 100644 index 000000000000..dc235121ec42 --- /dev/null +++ b/include/asm-mn10300/ide.h | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /* MN10300 Arch-specific IDE code | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * - Derived from include/asm-i386/ide.h | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef _ASM_IDE_H | ||
| 14 | #define _ASM_IDE_H | ||
| 15 | |||
| 16 | #ifdef __KERNEL__ | ||
| 17 | |||
| 18 | #include <asm/intctl-regs.h> | ||
| 19 | |||
| 20 | #undef SUPPORT_SLOW_DATA_PORTS | ||
| 21 | #define SUPPORT_SLOW_DATA_PORTS 0 | ||
| 22 | |||
| 23 | #undef SUPPORT_VLB_SYNC | ||
| 24 | #define SUPPORT_VLB_SYNC 0 | ||
| 25 | |||
| 26 | #ifndef MAX_HWIFS | ||
| 27 | #define MAX_HWIFS 8 | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* | ||
| 31 | * some bits needed for parts of the IDE subsystem to compile | ||
| 32 | */ | ||
| 33 | #define __ide_mm_insw(port, addr, n) \ | ||
| 34 | insw((unsigned long) (port), (addr), (n)) | ||
| 35 | #define __ide_mm_insl(port, addr, n) \ | ||
| 36 | insl((unsigned long) (port), (addr), (n)) | ||
| 37 | #define __ide_mm_outsw(port, addr, n) \ | ||
| 38 | outsw((unsigned long) (port), (addr), (n)) | ||
| 39 | #define __ide_mm_outsl(port, addr, n) \ | ||
| 40 | outsl((unsigned long) (port), (addr), (n)) | ||
| 41 | |||
| 42 | #endif /* __KERNEL__ */ | ||
| 43 | #endif /* _ASM_IDE_H */ | ||
diff --git a/include/asm-mn10300/intctl-regs.h b/include/asm-mn10300/intctl-regs.h new file mode 100644 index 000000000000..ba544c796c5a --- /dev/null +++ b/include/asm-mn10300/intctl-regs.h | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | /* MN10300 On-board interrupt controller registers | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_INTCTL_REGS_H | ||
| 12 | #define _ASM_INTCTL_REGS_H | ||
| 13 | |||
| 14 | #include <asm/cpu-regs.h> | ||
| 15 | |||
| 16 | #ifdef __KERNEL__ | ||
| 17 | |||
| 18 | /* interrupt controller registers */ | ||
| 19 | #define GxICR(X) __SYSREG(0xd4000000 + (X) * 4, u16) /* group irq ctrl regs */ | ||
| 20 | |||
| 21 | #define IAGR __SYSREG(0xd4000100, u16) /* intr acceptance group reg */ | ||
| 22 | #define IAGR_GN 0x00fc /* group number register | ||
| 23 | * (documentation _has_ to be wrong) | ||
| 24 | */ | ||
| 25 | |||
| 26 | #define EXTMD __SYSREG(0xd4000200, u16) /* external pin intr spec reg */ | ||
| 27 | #define GET_XIRQ_TRIGGER(X) ((EXTMD >> ((X) * 2)) & 3) | ||
| 28 | |||
| 29 | #define SET_XIRQ_TRIGGER(X,Y) \ | ||
| 30 | do { \ | ||
| 31 | u16 x = EXTMD; \ | ||
| 32 | x &= ~(3 << ((X) * 2)); \ | ||
| 33 | x |= ((Y) & 3) << ((X) * 2); \ | ||
| 34 | EXTMD = x; \ | ||
| 35 | } while (0) | ||
| 36 | |||
| 37 | #define XIRQ_TRIGGER_LOWLEVEL 0 | ||
| 38 | #define XIRQ_TRIGGER_HILEVEL 1 | ||
| 39 | #define XIRQ_TRIGGER_NEGEDGE 2 | ||
| 40 | #define XIRQ_TRIGGER_POSEDGE 3 | ||
| 41 | |||
| 42 | /* non-maskable interrupt control */ | ||
| 43 | #define NMIIRQ 0 | ||
| 44 | #define NMICR GxICR(NMIIRQ) /* NMI control register */ | ||
| 45 | #define NMICR_NMIF 0x0001 /* NMI pin interrupt flag */ | ||
| 46 | #define NMICR_WDIF 0x0002 /* watchdog timer overflow flag */ | ||
| 47 | #define NMICR_ABUSERR 0x0008 /* async bus error flag */ | ||
| 48 | |||
| 49 | /* maskable interrupt control */ | ||
| 50 | #define GxICR_DETECT 0x0001 /* interrupt detect flag */ | ||
| 51 | #define GxICR_REQUEST 0x0010 /* interrupt request flag */ | ||
| 52 | #define GxICR_ENABLE 0x0100 /* interrupt enable flag */ | ||
| 53 | #define GxICR_LEVEL 0x7000 /* interrupt priority level */ | ||
| 54 | #define GxICR_LEVEL_0 0x0000 /* - level 0 */ | ||
| 55 | #define GxICR_LEVEL_1 0x1000 /* - level 1 */ | ||
| 56 | #define GxICR_LEVEL_2 0x2000 /* - level 2 */ | ||
| 57 | #define GxICR_LEVEL_3 0x3000 /* - level 3 */ | ||
| 58 | #define GxICR_LEVEL_4 0x4000 /* - level 4 */ | ||
| 59 | #define GxICR_LEVEL_5 0x5000 /* - level 5 */ | ||
| 60 | #define GxICR_LEVEL_6 0x6000 /* - level 6 */ | ||
| 61 | #define GxICR_LEVEL_SHIFT 12 | ||
| 62 | |||
| 63 | #ifndef __ASSEMBLY__ | ||
| 64 | extern void set_intr_level(int irq, u16 level); | ||
| 65 | extern void set_intr_postackable(int irq); | ||
| 66 | #endif | ||
| 67 | |||
| 68 | /* external interrupts */ | ||
| 69 | #define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */ | ||
| 70 | |||
| 71 | #endif /* __KERNEL__ */ | ||
| 72 | |||
| 73 | #endif /* _ASM_INTCTL_REGS_H */ | ||
diff --git a/include/asm-mn10300/io.h b/include/asm-mn10300/io.h new file mode 100644 index 000000000000..b8b6dc878250 --- /dev/null +++ b/include/asm-mn10300/io.h | |||
| @@ -0,0 +1,299 @@ | |||
| 1 | /* MN10300 I/O port emulation and memory-mapped I/O | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_IO_H | ||
| 12 | #define _ASM_IO_H | ||
| 13 | |||
| 14 | #include <asm/page.h> /* I/O is all done through memory accesses */ | ||
| 15 | #include <asm/cpu-regs.h> | ||
| 16 | #include <asm/cacheflush.h> | ||
| 17 | |||
| 18 | #define mmiowb() do {} while (0) | ||
| 19 | |||
| 20 | /*****************************************************************************/ | ||
| 21 | /* | ||
| 22 | * readX/writeX() are used to access memory mapped devices. On some | ||
| 23 | * architectures the memory mapped IO stuff needs to be accessed | ||
| 24 | * differently. On the x86 architecture, we just read/write the | ||
| 25 | * memory location directly. | ||
| 26 | */ | ||
| 27 | static inline u8 readb(const volatile void __iomem *addr) | ||
| 28 | { | ||
| 29 | return *(const volatile u8 *) addr; | ||
| 30 | } | ||
| 31 | |||
| 32 | static inline u16 readw(const volatile void __iomem *addr) | ||
| 33 | { | ||
| 34 | return *(const volatile u16 *) addr; | ||
| 35 | } | ||
| 36 | |||
| 37 | static inline u32 readl(const volatile void __iomem *addr) | ||
| 38 | { | ||
| 39 | return *(const volatile u32 *) addr; | ||
| 40 | } | ||
| 41 | |||
| 42 | #define __raw_readb readb | ||
| 43 | #define __raw_readw readw | ||
| 44 | #define __raw_readl readl | ||
| 45 | |||
| 46 | #define readb_relaxed readb | ||
| 47 | #define readw_relaxed readw | ||
| 48 | #define readl_relaxed readl | ||
| 49 | |||
| 50 | static inline void writeb(u8 b, volatile void __iomem *addr) | ||
| 51 | { | ||
| 52 | *(volatile u8 *) addr = b; | ||
| 53 | } | ||
| 54 | |||
| 55 | static inline void writew(u16 b, volatile void __iomem *addr) | ||
| 56 | { | ||
| 57 | *(volatile u16 *) addr = b; | ||
| 58 | } | ||
| 59 | |||
| 60 | static inline void writel(u32 b, volatile void __iomem *addr) | ||
| 61 | { | ||
| 62 | *(volatile u32 *) addr = b; | ||
| 63 | } | ||
| 64 | |||
| 65 | #define __raw_writeb writeb | ||
| 66 | #define __raw_writew writew | ||
| 67 | #define __raw_writel writel | ||
| 68 | |||
| 69 | /*****************************************************************************/ | ||
| 70 | /* | ||
| 71 | * traditional input/output functions | ||
| 72 | */ | ||
| 73 | static inline u8 inb_local(unsigned long addr) | ||
| 74 | { | ||
| 75 | return readb((volatile void __iomem *) addr); | ||
| 76 | } | ||
| 77 | |||
| 78 | static inline void outb_local(u8 b, unsigned long addr) | ||
| 79 | { | ||
| 80 | return writeb(b, (volatile void __iomem *) addr); | ||
| 81 | } | ||
| 82 | |||
| 83 | static inline u8 inb(unsigned long addr) | ||
| 84 | { | ||
| 85 | return readb((volatile void __iomem *) addr); | ||
| 86 | } | ||
| 87 | |||
| 88 | static inline u16 inw(unsigned long addr) | ||
| 89 | { | ||
| 90 | return readw((volatile void __iomem *) addr); | ||
| 91 | } | ||
| 92 | |||
| 93 | static inline u32 inl(unsigned long addr) | ||
| 94 | { | ||
| 95 | return readl((volatile void __iomem *) addr); | ||
| 96 | } | ||
| 97 | |||
| 98 | static inline void outb(u8 b, unsigned long addr) | ||
| 99 | { | ||
| 100 | return writeb(b, (volatile void __iomem *) addr); | ||
| 101 | } | ||
| 102 | |||
| 103 | static inline void outw(u16 b, unsigned long addr) | ||
| 104 | { | ||
| 105 | return writew(b, (volatile void __iomem *) addr); | ||
| 106 | } | ||
| 107 | |||
| 108 | static inline void outl(u32 b, unsigned long addr) | ||
| 109 | { | ||
| 110 | return writel(b, (volatile void __iomem *) addr); | ||
| 111 | } | ||
| 112 | |||
| 113 | #define inb_p(addr) inb(addr) | ||
| 114 | #define inw_p(addr) inw(addr) | ||
| 115 | #define inl_p(addr) inl(addr) | ||
| 116 | #define outb_p(x, addr) outb((x), (addr)) | ||
| 117 | #define outw_p(x, addr) outw((x), (addr)) | ||
| 118 | #define outl_p(x, addr) outl((x), (addr)) | ||
| 119 | |||
| 120 | static inline void insb(unsigned long addr, void *buffer, int count) | ||
| 121 | { | ||
| 122 | if (count) { | ||
| 123 | u8 *buf = buffer; | ||
| 124 | do { | ||
| 125 | u8 x = inb(addr); | ||
| 126 | *buf++ = x; | ||
| 127 | } while (--count); | ||
| 128 | } | ||
| 129 | } | ||
| 130 | |||
| 131 | static inline void insw(unsigned long addr, void *buffer, int count) | ||
| 132 | { | ||
| 133 | if (count) { | ||
| 134 | u16 *buf = buffer; | ||
| 135 | do { | ||
| 136 | u16 x = inw(addr); | ||
| 137 | *buf++ = x; | ||
| 138 | } while (--count); | ||
| 139 | } | ||
| 140 | } | ||
| 141 | |||
| 142 | static inline void insl(unsigned long addr, void *buffer, int count) | ||
| 143 | { | ||
| 144 | if (count) { | ||
| 145 | u32 *buf = buffer; | ||
| 146 | do { | ||
| 147 | u32 x = inl(addr); | ||
| 148 | *buf++ = x; | ||
| 149 | } while (--count); | ||
| 150 | } | ||
| 151 | } | ||
| 152 | |||
| 153 | static inline void outsb(unsigned long addr, const void *buffer, int count) | ||
| 154 | { | ||
| 155 | if (count) { | ||
| 156 | const u8 *buf = buffer; | ||
| 157 | do { | ||
| 158 | outb(*buf++, addr); | ||
| 159 | } while (--count); | ||
| 160 | } | ||
| 161 | } | ||
| 162 | |||
| 163 | static inline void outsw(unsigned long addr, const void *buffer, int count) | ||
| 164 | { | ||
| 165 | if (count) { | ||
| 166 | const u16 *buf = buffer; | ||
| 167 | do { | ||
| 168 | outw(*buf++, addr); | ||
| 169 | } while (--count); | ||
| 170 | } | ||
| 171 | } | ||
| 172 | |||
| 173 | extern void __outsl(unsigned long addr, const void *buffer, int count); | ||
| 174 | static inline void outsl(unsigned long addr, const void *buffer, int count) | ||
| 175 | { | ||
| 176 | if ((unsigned long) buffer & 0x3) | ||
| 177 | return __outsl(addr, buffer, count); | ||
| 178 | |||
| 179 | if (count) { | ||
| 180 | const u32 *buf = buffer; | ||
| 181 | do { | ||
| 182 | outl(*buf++, addr); | ||
| 183 | } while (--count); | ||
| 184 | } | ||
| 185 | } | ||
| 186 | |||
| 187 | #define ioread8(addr) readb(addr) | ||
| 188 | #define ioread16(addr) readw(addr) | ||
| 189 | #define ioread32(addr) readl(addr) | ||
| 190 | |||
| 191 | #define iowrite8(v, addr) writeb((v), (addr)) | ||
| 192 | #define iowrite16(v, addr) writew((v), (addr)) | ||
| 193 | #define iowrite32(v, addr) writel((v), (addr)) | ||
| 194 | |||
| 195 | #define ioread8_rep(p, dst, count) \ | ||
| 196 | insb((unsigned long) (p), (dst), (count)) | ||
| 197 | #define ioread16_rep(p, dst, count) \ | ||
| 198 | insw((unsigned long) (p), (dst), (count)) | ||
| 199 | #define ioread32_rep(p, dst, count) \ | ||
| 200 | insl((unsigned long) (p), (dst), (count)) | ||
| 201 | |||
| 202 | #define iowrite8_rep(p, src, count) \ | ||
| 203 | outsb((unsigned long) (p), (src), (count)) | ||
| 204 | #define iowrite16_rep(p, src, count) \ | ||
| 205 | outsw((unsigned long) (p), (src), (count)) | ||
| 206 | #define iowrite32_rep(p, src, count) \ | ||
| 207 | outsl((unsigned long) (p), (src), (count)) | ||
| 208 | |||
| 209 | |||
| 210 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 211 | |||
| 212 | #ifdef __KERNEL__ | ||
| 213 | |||
| 214 | #include <linux/vmalloc.h> | ||
| 215 | #define __io_virt(x) ((void *) (x)) | ||
| 216 | |||
| 217 | /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ | ||
| 218 | struct pci_dev; | ||
| 219 | extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); | ||
| 220 | static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) | ||
| 221 | { | ||
| 222 | } | ||
| 223 | |||
| 224 | /* | ||
| 225 | * Change virtual addresses to physical addresses and vv. | ||
| 226 | * These are pretty trivial | ||
| 227 | */ | ||
| 228 | static inline unsigned long virt_to_phys(volatile void *address) | ||
| 229 | { | ||
| 230 | return __pa(address); | ||
| 231 | } | ||
| 232 | |||
| 233 | static inline void *phys_to_virt(unsigned long address) | ||
| 234 | { | ||
| 235 | return __va(address); | ||
| 236 | } | ||
| 237 | |||
| 238 | /* | ||
| 239 | * Change "struct page" to physical address. | ||
| 240 | */ | ||
| 241 | static inline void *__ioremap(unsigned long offset, unsigned long size, | ||
| 242 | unsigned long flags) | ||
| 243 | { | ||
| 244 | return (void *) offset; | ||
| 245 | } | ||
| 246 | |||
| 247 | static inline void *ioremap(unsigned long offset, unsigned long size) | ||
| 248 | { | ||
| 249 | return (void *) offset; | ||
| 250 | } | ||
| 251 | |||
| 252 | /* | ||
| 253 | * This one maps high address device memory and turns off caching for that | ||
| 254 | * area. it's useful if some control registers are in such an area and write | ||
| 255 | * combining or read caching is not desirable: | ||
| 256 | */ | ||
| 257 | static inline void *ioremap_nocache(unsigned long offset, unsigned long size) | ||
| 258 | { | ||
| 259 | return (void *) (offset | 0x20000000); | ||
| 260 | } | ||
| 261 | |||
| 262 | static inline void iounmap(void *addr) | ||
| 263 | { | ||
| 264 | } | ||
| 265 | |||
| 266 | static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) | ||
| 267 | { | ||
| 268 | return (void __iomem *) port; | ||
| 269 | } | ||
| 270 | |||
| 271 | static inline void ioport_unmap(void __iomem *p) | ||
| 272 | { | ||
| 273 | } | ||
| 274 | |||
| 275 | #define xlate_dev_kmem_ptr(p) ((void *) (p)) | ||
| 276 | #define xlate_dev_mem_ptr(p) ((void *) (p)) | ||
| 277 | |||
| 278 | /* | ||
| 279 | * PCI bus iomem addresses must be in the region 0x80000000-0x9fffffff | ||
| 280 | */ | ||
| 281 | static inline unsigned long virt_to_bus(volatile void *address) | ||
| 282 | { | ||
| 283 | return ((unsigned long) address) & ~0x20000000; | ||
| 284 | } | ||
| 285 | |||
| 286 | static inline void *bus_to_virt(unsigned long address) | ||
| 287 | { | ||
| 288 | return (void *) address; | ||
| 289 | } | ||
| 290 | |||
| 291 | #define page_to_bus page_to_phys | ||
| 292 | |||
| 293 | #define memset_io(a, b, c) memset(__io_virt(a), (b), (c)) | ||
| 294 | #define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c)) | ||
| 295 | #define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c)) | ||
| 296 | |||
| 297 | #endif /* __KERNEL__ */ | ||
| 298 | |||
| 299 | #endif /* _ASM_IO_H */ | ||
diff --git a/include/asm-mn10300/ioctl.h b/include/asm-mn10300/ioctl.h new file mode 100644 index 000000000000..b279fe06dfe5 --- /dev/null +++ b/include/asm-mn10300/ioctl.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/ioctl.h> | |||
diff --git a/include/asm-mn10300/ioctls.h b/include/asm-mn10300/ioctls.h new file mode 100644 index 000000000000..dcbfb452974f --- /dev/null +++ b/include/asm-mn10300/ioctls.h | |||
| @@ -0,0 +1,88 @@ | |||
| 1 | #ifndef _ASM_IOCTLS_H | ||
| 2 | #define _ASM_IOCTLS_H | ||
| 3 | |||
| 4 | #include <asm/ioctl.h> | ||
| 5 | |||
| 6 | /* 0x54 is just a magic number to make these relatively unique ('T') */ | ||
| 7 | |||
| 8 | #define TCGETS 0x5401 | ||
| 9 | #define TCSETS 0x5402 | ||
| 10 | #define TCSETSW 0x5403 | ||
| 11 | #define TCSETSF 0x5404 | ||
| 12 | #define TCGETA 0x5405 | ||
| 13 | #define TCSETA 0x5406 | ||
| 14 | #define TCSETAW 0x5407 | ||
| 15 | #define TCSETAF 0x5408 | ||
| 16 | #define TCSBRK 0x5409 | ||
| 17 | #define TCXONC 0x540A | ||
| 18 | #define TCFLSH 0x540B | ||
| 19 | #define TIOCEXCL 0x540C | ||
| 20 | #define TIOCNXCL 0x540D | ||
| 21 | #define TIOCSCTTY 0x540E | ||
| 22 | #define TIOCGPGRP 0x540F | ||
| 23 | #define TIOCSPGRP 0x5410 | ||
| 24 | #define TIOCOUTQ 0x5411 | ||
| 25 | #define TIOCSTI 0x5412 | ||
| 26 | #define TIOCGWINSZ 0x5413 | ||
| 27 | #define TIOCSWINSZ 0x5414 | ||
| 28 | #define TIOCMGET 0x5415 | ||
| 29 | #define TIOCMBIS 0x5416 | ||
| 30 | #define TIOCMBIC 0x5417 | ||
| 31 | #define TIOCMSET 0x5418 | ||
| 32 | #define TIOCGSOFTCAR 0x5419 | ||
| 33 | #define TIOCSSOFTCAR 0x541A | ||
| 34 | #define FIONREAD 0x541B | ||
| 35 | #define TIOCINQ FIONREAD | ||
| 36 | #define TIOCLINUX 0x541C | ||
| 37 | #define TIOCCONS 0x541D | ||
| 38 | #define TIOCGSERIAL 0x541E | ||
| 39 | #define TIOCSSERIAL 0x541F | ||
| 40 | #define TIOCPKT 0x5420 | ||
| 41 | #define FIONBIO 0x5421 | ||
| 42 | #define TIOCNOTTY 0x5422 | ||
| 43 | #define TIOCSETD 0x5423 | ||
| 44 | #define TIOCGETD 0x5424 | ||
| 45 | #define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ | ||
| 46 | /* #define TIOCTTYGSTRUCT 0x5426 - Former debugging-only ioctl */ | ||
| 47 | #define TIOCSBRK 0x5427 /* BSD compatibility */ | ||
| 48 | #define TIOCCBRK 0x5428 /* BSD compatibility */ | ||
| 49 | #define TIOCGSID 0x5429 /* Return the session ID of FD */ | ||
| 50 | #define TCGETS2 _IOR('T', 0x2A, struct termios2) | ||
| 51 | #define TCSETS2 _IOW('T', 0x2B, struct termios2) | ||
| 52 | #define TCSETSW2 _IOW('T', 0x2C, struct termios2) | ||
| 53 | #define TCSETSF2 _IOW('T', 0x2D, struct termios2) | ||
| 54 | #define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number | ||
| 55 | * (of pty-mux device) */ | ||
| 56 | #define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ | ||
| 57 | |||
| 58 | #define FIONCLEX 0x5450 | ||
| 59 | #define FIOCLEX 0x5451 | ||
| 60 | #define FIOASYNC 0x5452 | ||
| 61 | #define TIOCSERCONFIG 0x5453 | ||
| 62 | #define TIOCSERGWILD 0x5454 | ||
| 63 | #define TIOCSERSWILD 0x5455 | ||
| 64 | #define TIOCGLCKTRMIOS 0x5456 | ||
| 65 | #define TIOCSLCKTRMIOS 0x5457 | ||
| 66 | #define TIOCSERGSTRUCT 0x5458 /* For debugging only */ | ||
| 67 | #define TIOCSERGETLSR 0x5459 /* Get line status register */ | ||
| 68 | #define TIOCSERGETMULTI 0x545A /* Get multiport config */ | ||
| 69 | #define TIOCSERSETMULTI 0x545B /* Set multiport config */ | ||
| 70 | |||
| 71 | #define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ | ||
| 72 | #define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ | ||
| 73 | #define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */ | ||
| 74 | #define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */ | ||
| 75 | #define FIOQSIZE 0x5460 | ||
| 76 | |||
| 77 | /* Used for packet mode */ | ||
| 78 | #define TIOCPKT_DATA 0 | ||
| 79 | #define TIOCPKT_FLUSHREAD 1 | ||
| 80 | #define TIOCPKT_FLUSHWRITE 2 | ||
| 81 | #define TIOCPKT_STOP 4 | ||
| 82 | #define TIOCPKT_START 8 | ||
| 83 | #define TIOCPKT_NOSTOP 16 | ||
| 84 | #define TIOCPKT_DOSTOP 32 | ||
| 85 | |||
| 86 | #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ | ||
| 87 | |||
| 88 | #endif /* _ASM_IOCTLS_H */ | ||
diff --git a/include/asm-mn10300/ipc.h b/include/asm-mn10300/ipc.h new file mode 100644 index 000000000000..a46e3d9c2a3f --- /dev/null +++ b/include/asm-mn10300/ipc.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/ipc.h> | |||
diff --git a/include/asm-mn10300/ipcbuf.h b/include/asm-mn10300/ipcbuf.h new file mode 100644 index 000000000000..efbbef8d1c69 --- /dev/null +++ b/include/asm-mn10300/ipcbuf.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | #ifndef _ASM_IPCBUF_H_ | ||
| 2 | #define _ASM_IPCBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The ipc64_perm structure for MN10300 architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 32-bit mode_t and seq | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct ipc64_perm | ||
| 15 | { | ||
| 16 | __kernel_key_t key; | ||
| 17 | __kernel_uid32_t uid; | ||
| 18 | __kernel_gid32_t gid; | ||
| 19 | __kernel_uid32_t cuid; | ||
| 20 | __kernel_gid32_t cgid; | ||
| 21 | __kernel_mode_t mode; | ||
| 22 | unsigned short __pad1; | ||
| 23 | unsigned short seq; | ||
| 24 | unsigned short __pad2; | ||
| 25 | unsigned long __unused1; | ||
| 26 | unsigned long __unused2; | ||
| 27 | }; | ||
| 28 | |||
| 29 | #endif /* _ASM_IPCBUF_H */ | ||
diff --git a/include/asm-mn10300/irq.h b/include/asm-mn10300/irq.h new file mode 100644 index 000000000000..53b380116901 --- /dev/null +++ b/include/asm-mn10300/irq.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* MN10300 Hardware interrupt definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * Modified by David Howells (dhowells@redhat.com) | ||
| 6 | * - Derived from include/asm-i386/irq.h: | ||
| 7 | * - (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public Licence | ||
| 11 | * as published by the Free Software Foundation; either version | ||
| 12 | * 2 of the Licence, or (at your option) any later version. | ||
| 13 | */ | ||
| 14 | #ifndef _ASM_IRQ_H | ||
| 15 | #define _ASM_IRQ_H | ||
| 16 | |||
| 17 | #include <asm/intctl-regs.h> | ||
| 18 | #include <asm/reset-regs.h> | ||
| 19 | #include <asm/proc/irq.h> | ||
| 20 | |||
| 21 | /* this number is used when no interrupt has been assigned */ | ||
| 22 | #define NO_IRQ INT_MAX | ||
| 23 | |||
| 24 | /* hardware irq numbers */ | ||
| 25 | #define NR_IRQS GxICR_NUM_IRQS | ||
| 26 | |||
| 27 | /* external hardware irq numbers */ | ||
| 28 | #define NR_XIRQS GxICR_NUM_XIRQS | ||
| 29 | |||
| 30 | #define irq_canonicalize(IRQ) (IRQ) | ||
| 31 | |||
| 32 | #endif /* _ASM_IRQ_H */ | ||
diff --git a/include/asm-mn10300/irq_regs.h b/include/asm-mn10300/irq_regs.h new file mode 100644 index 000000000000..a848cd232eb4 --- /dev/null +++ b/include/asm-mn10300/irq_regs.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* MN10300 IRQ registers pointer definition | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_IRQ_REGS_H | ||
| 12 | #define _ASM_IRQ_REGS_H | ||
| 13 | |||
| 14 | /* | ||
| 15 | * Per-cpu current frame pointer - the location of the last exception frame on | ||
| 16 | * the stack | ||
| 17 | */ | ||
| 18 | #define ARCH_HAS_OWN_IRQ_REGS | ||
| 19 | |||
| 20 | #ifndef __ASSEMBLY__ | ||
| 21 | #define get_irq_regs() (__frame) | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #endif /* _ASM_IRQ_REGS_H */ | ||
diff --git a/include/asm-mn10300/kdebug.h b/include/asm-mn10300/kdebug.h new file mode 100644 index 000000000000..0f47e112190c --- /dev/null +++ b/include/asm-mn10300/kdebug.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* MN10300 In-kernel death knells | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_KDEBUG_H | ||
| 13 | #define _ASM_KDEBUG_H | ||
| 14 | |||
| 15 | /* Grossly misnamed. */ | ||
| 16 | enum die_val { | ||
| 17 | DIE_OOPS = 1, | ||
| 18 | DIE_BREAKPOINT, | ||
| 19 | DIE_GPF, | ||
| 20 | }; | ||
| 21 | |||
| 22 | #endif /* _ASM_KDEBUG_H */ | ||
diff --git a/include/asm-mn10300/kmap_types.h b/include/asm-mn10300/kmap_types.h new file mode 100644 index 000000000000..3398f9f35603 --- /dev/null +++ b/include/asm-mn10300/kmap_types.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* MN10300 kmap_atomic() slot IDs | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_KMAP_TYPES_H | ||
| 12 | #define _ASM_KMAP_TYPES_H | ||
| 13 | |||
| 14 | enum km_type { | ||
| 15 | KM_BOUNCE_READ, | ||
| 16 | KM_SKB_SUNRPC_DATA, | ||
| 17 | KM_SKB_DATA_SOFTIRQ, | ||
| 18 | KM_USER0, | ||
| 19 | KM_USER1, | ||
| 20 | KM_BIO_SRC_IRQ, | ||
| 21 | KM_BIO_DST_IRQ, | ||
| 22 | KM_PTE0, | ||
| 23 | KM_PTE1, | ||
| 24 | KM_IRQ0, | ||
| 25 | KM_IRQ1, | ||
| 26 | KM_SOFTIRQ0, | ||
| 27 | KM_SOFTIRQ1, | ||
| 28 | KM_TYPE_NR | ||
| 29 | }; | ||
| 30 | |||
| 31 | #endif /* _ASM_KMAP_TYPES_H */ | ||
diff --git a/include/asm-mn10300/kprobes.h b/include/asm-mn10300/kprobes.h new file mode 100644 index 000000000000..c800b590183a --- /dev/null +++ b/include/asm-mn10300/kprobes.h | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* MN10300 Kernel Probes support | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by Mark Salter (msalter@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public Licence as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the Licence, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public Licence for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public Licence | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 19 | * | ||
| 20 | */ | ||
| 21 | #ifndef _ASM_KPROBES_H | ||
| 22 | #define _ASM_KPROBES_H | ||
| 23 | |||
| 24 | #include <linux/types.h> | ||
| 25 | #include <linux/ptrace.h> | ||
| 26 | |||
| 27 | struct kprobe; | ||
| 28 | |||
| 29 | typedef unsigned char kprobe_opcode_t; | ||
| 30 | #define BREAKPOINT_INSTRUCTION 0xff | ||
| 31 | #define MAX_INSN_SIZE 8 | ||
| 32 | #define MAX_STACK_SIZE 128 | ||
| 33 | |||
| 34 | /* Architecture specific copy of original instruction */ | ||
| 35 | struct arch_specific_insn { | ||
| 36 | /* copy of original instruction | ||
| 37 | */ | ||
| 38 | kprobe_opcode_t insn[MAX_INSN_SIZE]; | ||
| 39 | }; | ||
| 40 | |||
| 41 | extern const int kretprobe_blacklist_size; | ||
| 42 | |||
| 43 | extern int kprobe_exceptions_notify(struct notifier_block *self, | ||
| 44 | unsigned long val, void *data); | ||
| 45 | |||
| 46 | #define flush_insn_slot(p) do {} while (0) | ||
| 47 | |||
| 48 | extern void arch_remove_kprobe(struct kprobe *p); | ||
| 49 | |||
| 50 | #endif /* _ASM_KPROBES_H */ | ||
diff --git a/include/asm-mn10300/linkage.h b/include/asm-mn10300/linkage.h new file mode 100644 index 000000000000..29a32e467523 --- /dev/null +++ b/include/asm-mn10300/linkage.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* MN10300 Linkage and calling-convention overrides | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_LINKAGE_H | ||
| 12 | #define _ASM_LINKAGE_H | ||
| 13 | |||
| 14 | /* don't override anything */ | ||
| 15 | #define asmlinkage | ||
| 16 | #define FASTCALL(x) x | ||
| 17 | #define fastcall | ||
| 18 | |||
| 19 | #define __ALIGN .align 4,0xcb | ||
| 20 | #define __ALIGN_STR ".align 4,0xcb" | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/include/asm-mn10300/local.h b/include/asm-mn10300/local.h new file mode 100644 index 000000000000..c11c530f74d0 --- /dev/null +++ b/include/asm-mn10300/local.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/local.h> | |||
diff --git a/include/asm-mn10300/mc146818rtc.h b/include/asm-mn10300/mc146818rtc.h new file mode 100644 index 000000000000..df6bc6e0e8c6 --- /dev/null +++ b/include/asm-mn10300/mc146818rtc.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm/rtc-regs.h> | |||
diff --git a/include/asm-mn10300/mman.h b/include/asm-mn10300/mman.h new file mode 100644 index 000000000000..b7986b65addf --- /dev/null +++ b/include/asm-mn10300/mman.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | /* MN10300 Constants for mmap and co. | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * - Derived from asm-x86/mman.h | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #ifndef _ASM_MMAN_H | ||
| 13 | #define _ASM_MMAN_H | ||
| 14 | |||
| 15 | #include <asm-generic/mman.h> | ||
| 16 | |||
| 17 | #define MAP_GROWSDOWN 0x0100 /* stack-like segment */ | ||
| 18 | #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ | ||
| 19 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | ||
| 20 | #define MAP_LOCKED 0x2000 /* pages are locked */ | ||
| 21 | #define MAP_NORESERVE 0x4000 /* don't check for reservations */ | ||
| 22 | #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ | ||
| 23 | #define MAP_NONBLOCK 0x10000 /* do not block on IO */ | ||
| 24 | |||
| 25 | #define MCL_CURRENT 1 /* lock all current mappings */ | ||
| 26 | #define MCL_FUTURE 2 /* lock all future mappings */ | ||
| 27 | |||
| 28 | #endif /* _ASM_MMAN_H */ | ||
diff --git a/include/asm-mn10300/mmu.h b/include/asm-mn10300/mmu.h new file mode 100644 index 000000000000..2d2d097e7309 --- /dev/null +++ b/include/asm-mn10300/mmu.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* MN10300 Memory management context | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * - Derived from include/asm-frv/mmu.h | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _ASM_MMU_H | ||
| 9 | #define _ASM_MMU_H | ||
| 10 | |||
| 11 | /* | ||
| 12 | * MMU context | ||
| 13 | */ | ||
| 14 | typedef struct { | ||
| 15 | unsigned long tlbpid[NR_CPUS]; /* TLB PID for this process on | ||
| 16 | * each CPU */ | ||
| 17 | } mm_context_t; | ||
| 18 | |||
| 19 | #endif /* _ASM_MMU_H */ | ||
diff --git a/include/asm-mn10300/mmu_context.h b/include/asm-mn10300/mmu_context.h new file mode 100644 index 000000000000..a9e2e34f69b0 --- /dev/null +++ b/include/asm-mn10300/mmu_context.h | |||
| @@ -0,0 +1,138 @@ | |||
| 1 | /* MN10300 MMU context management | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Modified by David Howells (dhowells@redhat.com) | ||
| 5 | * - Derived from include/asm-m32r/mmu_context.h | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | * | ||
| 12 | * | ||
| 13 | * This implements an algorithm to provide TLB PID mappings to provide | ||
| 14 | * selective access to the TLB for processes, thus reducing the number of TLB | ||
| 15 | * flushes required. | ||
| 16 | * | ||
| 17 | * Note, however, that the M32R algorithm is technically broken as it does not | ||
| 18 | * handle version wrap-around, and could, theoretically, have a problem with a | ||
| 19 | * very long lived program that sleeps long enough for the version number to | ||
| 20 | * wrap all the way around so that its TLB mappings appear valid once again. | ||
| 21 | */ | ||
| 22 | #ifndef _ASM_MMU_CONTEXT_H | ||
| 23 | #define _ASM_MMU_CONTEXT_H | ||
| 24 | |||
| 25 | #include <asm/atomic.h> | ||
| 26 | #include <asm/pgalloc.h> | ||
| 27 | #include <asm/tlbflush.h> | ||
| 28 | #include <asm-generic/mm_hooks.h> | ||
| 29 | |||
| 30 | #define MMU_CONTEXT_TLBPID_MASK 0x000000ffUL | ||
| 31 | #define MMU_CONTEXT_VERSION_MASK 0xffffff00UL | ||
| 32 | #define MMU_CONTEXT_FIRST_VERSION 0x00000100UL | ||
| 33 | #define MMU_NO_CONTEXT 0x00000000UL | ||
| 34 | |||
| 35 | extern unsigned long mmu_context_cache[NR_CPUS]; | ||
| 36 | #define mm_context(mm) (mm->context.tlbpid[smp_processor_id()]) | ||
| 37 | |||
| 38 | #define enter_lazy_tlb(mm, tsk) do {} while (0) | ||
| 39 | |||
| 40 | #ifdef CONFIG_SMP | ||
| 41 | #define cpu_ran_vm(cpu, task) \ | ||
| 42 | cpu_set((cpu), (task)->cpu_vm_mask) | ||
| 43 | #define cpu_maybe_ran_vm(cpu, task) \ | ||
| 44 | cpu_test_and_set((cpu), (task)->cpu_vm_mask) | ||
| 45 | #else | ||
| 46 | #define cpu_ran_vm(cpu, task) do {} while (0) | ||
| 47 | #define cpu_maybe_ran_vm(cpu, task) true | ||
| 48 | #endif /* CONFIG_SMP */ | ||
| 49 | |||
| 50 | /* | ||
| 51 | * allocate an MMU context | ||
| 52 | */ | ||
| 53 | static inline unsigned long allocate_mmu_context(struct mm_struct *mm) | ||
| 54 | { | ||
| 55 | unsigned long *pmc = &mmu_context_cache[smp_processor_id()]; | ||
| 56 | unsigned long mc = ++(*pmc); | ||
| 57 | |||
| 58 | if (!(mc & MMU_CONTEXT_TLBPID_MASK)) { | ||
| 59 | /* we exhausted the TLB PIDs of this version on this CPU, so we | ||
| 60 | * flush this CPU's TLB in its entirety and start new cycle */ | ||
| 61 | flush_tlb_all(); | ||
| 62 | |||
| 63 | /* fix the TLB version if needed (we avoid version #0 so as to | ||
| 64 | * distingush MMU_NO_CONTEXT) */ | ||
| 65 | if (!mc) | ||
| 66 | *pmc = mc = MMU_CONTEXT_FIRST_VERSION; | ||
| 67 | } | ||
| 68 | mm_context(mm) = mc; | ||
| 69 | return mc; | ||
| 70 | } | ||
| 71 | |||
| 72 | /* | ||
| 73 | * get an MMU context if one is needed | ||
| 74 | */ | ||
| 75 | static inline unsigned long get_mmu_context(struct mm_struct *mm) | ||
| 76 | { | ||
| 77 | unsigned long mc = MMU_NO_CONTEXT, cache; | ||
| 78 | |||
| 79 | if (mm) { | ||
| 80 | cache = mmu_context_cache[smp_processor_id()]; | ||
| 81 | mc = mm_context(mm); | ||
| 82 | |||
| 83 | /* if we have an old version of the context, replace it */ | ||
| 84 | if ((mc ^ cache) & MMU_CONTEXT_VERSION_MASK) | ||
| 85 | mc = allocate_mmu_context(mm); | ||
| 86 | } | ||
| 87 | return mc; | ||
| 88 | } | ||
| 89 | |||
| 90 | /* | ||
| 91 | * initialise the context related info for a new mm_struct instance | ||
| 92 | */ | ||
| 93 | static inline int init_new_context(struct task_struct *tsk, | ||
| 94 | struct mm_struct *mm) | ||
| 95 | { | ||
| 96 | int num_cpus = NR_CPUS, i; | ||
| 97 | |||
| 98 | for (i = 0; i < num_cpus; i++) | ||
| 99 | mm->context.tlbpid[i] = MMU_NO_CONTEXT; | ||
| 100 | return 0; | ||
| 101 | } | ||
| 102 | |||
| 103 | /* | ||
| 104 | * destroy context related info for an mm_struct that is about to be put to | ||
| 105 | * rest | ||
| 106 | */ | ||
| 107 | #define destroy_context(mm) do { } while (0) | ||
| 108 | |||
| 109 | /* | ||
| 110 | * after we have set current->mm to a new value, this activates the context for | ||
| 111 | * the new mm so we see the new mappings. | ||
| 112 | */ | ||
| 113 | static inline void activate_context(struct mm_struct *mm, int cpu) | ||
| 114 | { | ||
| 115 | PIDR = get_mmu_context(mm) & MMU_CONTEXT_TLBPID_MASK; | ||
| 116 | } | ||
| 117 | |||
| 118 | /* | ||
| 119 | * change between virtual memory sets | ||
| 120 | */ | ||
| 121 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | ||
| 122 | struct task_struct *tsk) | ||
| 123 | { | ||
| 124 | int cpu = smp_processor_id(); | ||
| 125 | |||
| 126 | if (prev != next) { | ||
| 127 | cpu_ran_vm(cpu, next); | ||
| 128 | activate_context(next, cpu); | ||
| 129 | PTBR = (unsigned long) next->pgd; | ||
| 130 | } else if (!cpu_maybe_ran_vm(cpu, next)) { | ||
| 131 | activate_context(next, cpu); | ||
| 132 | } | ||
| 133 | } | ||
| 134 | |||
| 135 | #define deactivate_mm(tsk, mm) do {} while (0) | ||
| 136 | #define activate_mm(prev, next) switch_mm((prev), (next), NULL) | ||
| 137 | |||
| 138 | #endif /* _ASM_MMU_CONTEXT_H */ | ||
diff --git a/include/asm-mn10300/module.h b/include/asm-mn10300/module.h new file mode 100644 index 000000000000..5d7057d01494 --- /dev/null +++ b/include/asm-mn10300/module.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | /* MN10300 Arch-specific module definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by Mark Salter (msalter@redhat.com) | ||
| 5 | * Derived from include/asm-i386/module.h | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #ifndef _ASM_MODULE_H | ||
| 13 | #define _ASM_MODULE_H | ||
| 14 | |||
| 15 | struct mod_arch_specific { | ||
| 16 | }; | ||
| 17 | |||
| 18 | #define Elf_Shdr Elf32_Shdr | ||
| 19 | #define Elf_Sym Elf32_Sym | ||
| 20 | #define Elf_Ehdr Elf32_Ehdr | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Include the MN10300 architecture version. | ||
| 24 | */ | ||
| 25 | #define MODULE_ARCH_VERMAGIC __stringify(PROCESSOR_MODEL_NAME) " " | ||
| 26 | |||
| 27 | #endif /* _ASM_MODULE_H */ | ||
diff --git a/include/asm-mn10300/msgbuf.h b/include/asm-mn10300/msgbuf.h new file mode 100644 index 000000000000..8b602450cc4a --- /dev/null +++ b/include/asm-mn10300/msgbuf.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | #ifndef _ASM_MSGBUF_H | ||
| 2 | #define _ASM_MSGBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The msqid64_ds structure for MN10300 architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct msqid64_ds { | ||
| 15 | struct ipc64_perm msg_perm; | ||
| 16 | __kernel_time_t msg_stime; /* last msgsnd time */ | ||
| 17 | unsigned long __unused1; | ||
| 18 | __kernel_time_t msg_rtime; /* last msgrcv time */ | ||
| 19 | unsigned long __unused2; | ||
| 20 | __kernel_time_t msg_ctime; /* last change time */ | ||
| 21 | unsigned long __unused3; | ||
| 22 | unsigned long msg_cbytes; /* current number of bytes on queue */ | ||
| 23 | unsigned long msg_qnum; /* number of messages in queue */ | ||
| 24 | unsigned long msg_qbytes; /* max number of bytes on queue */ | ||
| 25 | __kernel_pid_t msg_lspid; /* pid of last msgsnd */ | ||
| 26 | __kernel_pid_t msg_lrpid; /* last receive pid */ | ||
| 27 | unsigned long __unused4; | ||
| 28 | unsigned long __unused5; | ||
| 29 | }; | ||
| 30 | |||
| 31 | #endif /* _ASM_MSGBUF_H */ | ||
diff --git a/include/asm-mn10300/mutex.h b/include/asm-mn10300/mutex.h new file mode 100644 index 000000000000..84f5490c6fb4 --- /dev/null +++ b/include/asm-mn10300/mutex.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | /* MN10300 Mutex fastpath | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | * | ||
| 11 | * | ||
| 12 | * TODO: implement optimized primitives instead, or leave the generic | ||
| 13 | * implementation in place, or pick the atomic_xchg() based generic | ||
| 14 | * implementation. (see asm-generic/mutex-xchg.h for details) | ||
| 15 | */ | ||
| 16 | #include <asm-generic/mutex-null.h> | ||
diff --git a/include/asm-mn10300/namei.h b/include/asm-mn10300/namei.h new file mode 100644 index 000000000000..bd9ce94aeb65 --- /dev/null +++ b/include/asm-mn10300/namei.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* Emulation stuff | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_NAMEI_H | ||
| 13 | #define _ASM_NAMEI_H | ||
| 14 | |||
| 15 | /* This dummy routine maybe changed to something useful | ||
| 16 | * for /usr/gnemul/ emulation stuff. | ||
| 17 | * Look at asm-sparc/namei.h for details. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define __emul_prefix() NULL | ||
| 21 | |||
| 22 | #endif /* _ASM_NAMEI_H */ | ||
diff --git a/include/asm-mn10300/nmi.h b/include/asm-mn10300/nmi.h new file mode 100644 index 000000000000..f3671cbbc117 --- /dev/null +++ b/include/asm-mn10300/nmi.h | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | /* MN10300 NMI handling | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_NMI_H | ||
| 12 | #define _ASM_NMI_H | ||
| 13 | |||
| 14 | #endif /* _ASM_NMI_H */ | ||
diff --git a/include/asm-mn10300/page.h b/include/asm-mn10300/page.h new file mode 100644 index 000000000000..124971b9fb9b --- /dev/null +++ b/include/asm-mn10300/page.h | |||
| @@ -0,0 +1,131 @@ | |||
| 1 | /* MN10300 Page table definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_PAGE_H | ||
| 12 | #define _ASM_PAGE_H | ||
| 13 | |||
| 14 | /* PAGE_SHIFT determines the page size */ | ||
| 15 | #define PAGE_SHIFT 12 | ||
| 16 | |||
| 17 | #ifndef __ASSEMBLY__ | ||
| 18 | #define PAGE_SIZE (1UL << PAGE_SHIFT) | ||
| 19 | #define PAGE_MASK (~(PAGE_SIZE - 1)) | ||
| 20 | #else | ||
| 21 | #define PAGE_SIZE +(1 << PAGE_SHIFT) /* unary plus marks an | ||
| 22 | * immediate val not an addr */ | ||
| 23 | #define PAGE_MASK +(~(PAGE_SIZE - 1)) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifdef __KERNEL__ | ||
| 27 | #ifndef __ASSEMBLY__ | ||
| 28 | |||
| 29 | #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) | ||
| 30 | #define copy_page(to, from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) | ||
| 31 | |||
| 32 | #define clear_user_page(addr, vaddr, page) clear_page(addr) | ||
| 33 | #define copy_user_page(vto, vfrom, vaddr, to) copy_page(vto, vfrom) | ||
| 34 | |||
| 35 | /* | ||
| 36 | * These are used to make use of C type-checking.. | ||
| 37 | */ | ||
| 38 | typedef struct { unsigned long pte; } pte_t; | ||
| 39 | typedef struct { unsigned long pgd; } pgd_t; | ||
| 40 | typedef struct { unsigned long pgprot; } pgprot_t; | ||
| 41 | typedef struct page *pgtable_t; | ||
| 42 | |||
| 43 | #define PTE_MASK PAGE_MASK | ||
| 44 | #define HPAGE_SHIFT 22 | ||
| 45 | |||
| 46 | #ifdef CONFIG_HUGETLB_PAGE | ||
| 47 | #define HPAGE_SIZE ((1UL) << HPAGE_SHIFT) | ||
| 48 | #define HPAGE_MASK (~(HPAGE_SIZE - 1)) | ||
| 49 | #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) | ||
| 50 | #endif | ||
| 51 | |||
| 52 | #define pte_val(x) ((x).pte) | ||
| 53 | #define pgd_val(x) ((x).pgd) | ||
| 54 | #define pgprot_val(x) ((x).pgprot) | ||
| 55 | |||
| 56 | #define __pte(x) ((pte_t) { (x) }) | ||
| 57 | #define __pgd(x) ((pgd_t) { (x) }) | ||
| 58 | #define __pgprot(x) ((pgprot_t) { (x) }) | ||
| 59 | |||
| 60 | #include <asm-generic/pgtable-nopmd.h> | ||
| 61 | |||
| 62 | #endif /* !__ASSEMBLY__ */ | ||
| 63 | |||
| 64 | /* to align the pointer to the (next) page boundary */ | ||
| 65 | #define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) | ||
| 66 | |||
| 67 | /* | ||
| 68 | * This handles the memory map.. We could make this a config | ||
| 69 | * option, but too many people screw it up, and too few need | ||
| 70 | * it. | ||
| 71 | * | ||
| 72 | * A __PAGE_OFFSET of 0xC0000000 means that the kernel has | ||
| 73 | * a virtual address space of one gigabyte, which limits the | ||
| 74 | * amount of physical memory you can use to about 950MB. | ||
| 75 | */ | ||
| 76 | |||
| 77 | #ifndef __ASSEMBLY__ | ||
| 78 | |||
| 79 | /* Pure 2^n version of get_order */ | ||
| 80 | static inline int get_order(unsigned long size) __attribute__((const)); | ||
| 81 | static inline int get_order(unsigned long size) | ||
| 82 | { | ||
| 83 | int order; | ||
| 84 | |||
| 85 | size = (size - 1) >> (PAGE_SHIFT - 1); | ||
| 86 | order = -1; | ||
| 87 | do { | ||
| 88 | size >>= 1; | ||
| 89 | order++; | ||
| 90 | } while (size); | ||
| 91 | return order; | ||
| 92 | } | ||
| 93 | |||
| 94 | #endif /* __ASSEMBLY__ */ | ||
| 95 | |||
| 96 | #include <asm/page_offset.h> | ||
| 97 | |||
| 98 | #define __PAGE_OFFSET (PAGE_OFFSET_RAW) | ||
| 99 | #define PAGE_OFFSET ((unsigned long) __PAGE_OFFSET) | ||
| 100 | |||
| 101 | /* | ||
| 102 | * main RAM and kernel working space are coincident at 0x90000000, but to make | ||
| 103 | * life more interesting, there's also an uncached virtual shadow at 0xb0000000 | ||
| 104 | * - these mappings are fixed in the MMU | ||
| 105 | */ | ||
| 106 | #define __pfn_disp (CONFIG_KERNEL_RAM_BASE_ADDRESS >> PAGE_SHIFT) | ||
| 107 | |||
| 108 | #define __pa(x) ((unsigned long)(x)) | ||
| 109 | #define __va(x) ((void *)(unsigned long)(x)) | ||
| 110 | #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) | ||
| 111 | #define pfn_to_page(pfn) (mem_map + ((pfn) - __pfn_disp)) | ||
| 112 | #define page_to_pfn(page) ((unsigned long)((page) - mem_map) + __pfn_disp) | ||
| 113 | |||
| 114 | #define pfn_valid(pfn) \ | ||
| 115 | ({ \ | ||
| 116 | unsigned long __pfn = (pfn) - __pfn_disp; \ | ||
| 117 | __pfn < max_mapnr; \ | ||
| 118 | }) | ||
| 119 | |||
| 120 | #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) | ||
| 121 | #define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) | ||
| 122 | #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) | ||
| 123 | |||
| 124 | #define VM_DATA_DEFAULT_FLAGS \ | ||
| 125 | (VM_READ | VM_WRITE | \ | ||
| 126 | ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \ | ||
| 127 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | ||
| 128 | |||
| 129 | #endif /* __KERNEL__ */ | ||
| 130 | |||
| 131 | #endif /* _ASM_PAGE_H */ | ||
diff --git a/include/asm-mn10300/page_offset.h b/include/asm-mn10300/page_offset.h new file mode 100644 index 000000000000..8eb5b16ad86b --- /dev/null +++ b/include/asm-mn10300/page_offset.h | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | /* MN10300 Kernel base address | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | */ | ||
| 6 | #ifndef _ASM_PAGE_OFFSET_H | ||
| 7 | #define _ASM_PAGE_OFFSET_H | ||
| 8 | |||
| 9 | #define PAGE_OFFSET_RAW CONFIG_KERNEL_RAM_BASE_ADDRESS | ||
| 10 | |||
| 11 | #endif | ||
diff --git a/include/asm-mn10300/param.h b/include/asm-mn10300/param.h new file mode 100644 index 000000000000..54b883ec3906 --- /dev/null +++ b/include/asm-mn10300/param.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* MN10300 Kernel parameters | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_PARAM_H | ||
| 12 | #define _ASM_PARAM_H | ||
| 13 | |||
| 14 | #ifdef __KERNEL__ | ||
| 15 | #define HZ 1000 /* Internal kernel timer frequency */ | ||
| 16 | #define USER_HZ 100 /* .. some user interfaces are in | ||
| 17 | * "ticks" */ | ||
| 18 | #define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #ifndef HZ | ||
| 22 | #define HZ 100 | ||
| 23 | #endif | ||
| 24 | |||
| 25 | #define EXEC_PAGESIZE 4096 | ||
| 26 | |||
| 27 | #ifndef NOGROUP | ||
| 28 | #define NOGROUP (-1) | ||
| 29 | #endif | ||
| 30 | |||
| 31 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | ||
| 32 | #define COMMAND_LINE_SIZE 256 | ||
| 33 | |||
| 34 | #endif /* _ASM_PARAM_H */ | ||
diff --git a/include/asm-mn10300/pci.h b/include/asm-mn10300/pci.h new file mode 100644 index 000000000000..205192c52bb5 --- /dev/null +++ b/include/asm-mn10300/pci.h | |||
| @@ -0,0 +1,133 @@ | |||
| 1 | /* MN10300 PCI definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_PCI_H | ||
| 12 | #define _ASM_PCI_H | ||
| 13 | |||
| 14 | #ifdef __KERNEL__ | ||
| 15 | #include <linux/mm.h> /* for struct page */ | ||
| 16 | |||
| 17 | #if 0 | ||
| 18 | #define __pcbdebug(FMT, ADDR, ...) \ | ||
| 19 | printk(KERN_DEBUG "PCIBRIDGE[%08x]: "FMT"\n", \ | ||
| 20 | (u32)(ADDR), ##__VA_ARGS__) | ||
| 21 | |||
| 22 | #define __pcidebug(FMT, BUS, DEVFN, WHERE,...) \ | ||
| 23 | do { \ | ||
| 24 | printk(KERN_DEBUG "PCI[%02x:%02x.%x + %02x]: "FMT"\n", \ | ||
| 25 | (BUS)->number, \ | ||
| 26 | PCI_SLOT(DEVFN), \ | ||
| 27 | PCI_FUNC(DEVFN), \ | ||
| 28 | (u32)(WHERE), ##__VA_ARGS__); \ | ||
| 29 | } while (0) | ||
| 30 | |||
| 31 | #else | ||
| 32 | #define __pcbdebug(FMT, ADDR, ...) do {} while (0) | ||
| 33 | #define __pcidebug(FMT, BUS, DEVFN, WHERE, ...) do {} while (0) | ||
| 34 | #endif | ||
| 35 | |||
| 36 | /* Can be used to override the logic in pci_scan_bus for skipping | ||
| 37 | * already-configured bus numbers - to be used for buggy BIOSes or | ||
| 38 | * architectures with incomplete PCI setup by the loader */ | ||
| 39 | |||
| 40 | #ifdef CONFIG_PCI | ||
| 41 | #define pcibios_assign_all_busses() 1 | ||
| 42 | extern void unit_pci_init(void); | ||
| 43 | #else | ||
| 44 | #define pcibios_assign_all_busses() 0 | ||
| 45 | #endif | ||
| 46 | |||
| 47 | extern unsigned long pci_mem_start; | ||
| 48 | #define PCIBIOS_MIN_IO 0xBE000004 | ||
| 49 | #define PCIBIOS_MIN_MEM 0xB8000000 | ||
| 50 | |||
| 51 | void pcibios_set_master(struct pci_dev *dev); | ||
| 52 | void pcibios_penalize_isa_irq(int irq); | ||
| 53 | |||
| 54 | /* Dynamic DMA mapping stuff. | ||
| 55 | * i386 has everything mapped statically. | ||
| 56 | */ | ||
| 57 | |||
| 58 | #include <linux/types.h> | ||
| 59 | #include <linux/slab.h> | ||
| 60 | #include <asm/scatterlist.h> | ||
| 61 | #include <linux/string.h> | ||
| 62 | #include <linux/mm.h> | ||
| 63 | #include <asm/io.h> | ||
| 64 | |||
| 65 | struct pci_dev; | ||
| 66 | |||
| 67 | /* The PCI address space does equal the physical memory | ||
| 68 | * address space. The networking and block device layers use | ||
| 69 | * this boolean for bounce buffer decisions. | ||
| 70 | */ | ||
| 71 | #define PCI_DMA_BUS_IS_PHYS (1) | ||
| 72 | |||
| 73 | |||
| 74 | /* This is always fine. */ | ||
| 75 | #define pci_dac_dma_supported(pci_dev, mask) (0) | ||
| 76 | |||
| 77 | /* | ||
| 78 | * These macros should be used after a pci_map_sg call has been done | ||
| 79 | * to get bus addresses of each of the SG entries and their lengths. | ||
| 80 | * You should only work with the number of sg entries pci_map_sg | ||
| 81 | * returns. | ||
| 82 | */ | ||
| 83 | #define sg_dma_address(sg) ((sg)->dma_address) | ||
| 84 | #define sg_dma_len(sg) ((sg)->length) | ||
| 85 | |||
| 86 | /* Return the index of the PCI controller for device. */ | ||
| 87 | static inline int pci_controller_num(struct pci_dev *dev) | ||
| 88 | { | ||
| 89 | return 0; | ||
| 90 | } | ||
| 91 | |||
| 92 | #define HAVE_PCI_MMAP | ||
| 93 | extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | ||
| 94 | enum pci_mmap_state mmap_state, | ||
| 95 | int write_combine); | ||
| 96 | |||
| 97 | #endif /* __KERNEL__ */ | ||
| 98 | |||
| 99 | /* implement the pci_ DMA API in terms of the generic device dma_ one */ | ||
| 100 | #include <asm-generic/pci-dma-compat.h> | ||
| 101 | |||
| 102 | /** | ||
| 103 | * pcibios_resource_to_bus - convert resource to PCI bus address | ||
| 104 | * @dev: device which owns this resource | ||
| 105 | * @region: converted bus-centric region (start,end) | ||
| 106 | * @res: resource to convert | ||
| 107 | * | ||
| 108 | * Convert a resource to a PCI device bus address or bus window. | ||
| 109 | */ | ||
| 110 | extern void pcibios_resource_to_bus(struct pci_dev *dev, | ||
| 111 | struct pci_bus_region *region, | ||
| 112 | struct resource *res); | ||
| 113 | |||
| 114 | extern void pcibios_bus_to_resource(struct pci_dev *dev, | ||
| 115 | struct resource *res, | ||
| 116 | struct pci_bus_region *region); | ||
| 117 | |||
| 118 | static inline struct resource * | ||
| 119 | pcibios_select_root(struct pci_dev *pdev, struct resource *res) | ||
| 120 | { | ||
| 121 | struct resource *root = NULL; | ||
| 122 | |||
| 123 | if (res->flags & IORESOURCE_IO) | ||
| 124 | root = &ioport_resource; | ||
| 125 | if (res->flags & IORESOURCE_MEM) | ||
| 126 | root = &iomem_resource; | ||
| 127 | |||
| 128 | return root; | ||
| 129 | } | ||
| 130 | |||
| 131 | #define pcibios_scan_all_fns(a, b) 0 | ||
| 132 | |||
| 133 | #endif /* _ASM_PCI_H */ | ||
diff --git a/include/asm-mn10300/percpu.h b/include/asm-mn10300/percpu.h new file mode 100644 index 000000000000..06a959d67234 --- /dev/null +++ b/include/asm-mn10300/percpu.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/percpu.h> | |||
diff --git a/include/asm-mn10300/pgalloc.h b/include/asm-mn10300/pgalloc.h new file mode 100644 index 000000000000..ec057e1bd4cf --- /dev/null +++ b/include/asm-mn10300/pgalloc.h | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /* MN10300 Page and page table/directory allocation | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_PGALLOC_H | ||
| 12 | #define _ASM_PGALLOC_H | ||
| 13 | |||
| 14 | #include <asm/processor.h> | ||
| 15 | #include <asm/page.h> | ||
| 16 | #include <linux/threads.h> | ||
| 17 | #include <linux/mm.h> /* for struct page */ | ||
| 18 | |||
| 19 | struct mm_struct; | ||
| 20 | struct page; | ||
| 21 | |||
| 22 | /* attach a page table to a PMD entry */ | ||
| 23 | #define pmd_populate_kernel(mm, pmd, pte) \ | ||
| 24 | set_pmd(pmd, __pmd(__pa(pte) | _PAGE_TABLE)) | ||
| 25 | |||
| 26 | static inline | ||
| 27 | void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte) | ||
| 28 | { | ||
| 29 | set_pmd(pmd, __pmd((page_to_pfn(pte) << PAGE_SHIFT) | _PAGE_TABLE)); | ||
| 30 | } | ||
| 31 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 32 | |||
| 33 | /* | ||
| 34 | * Allocate and free page tables. | ||
| 35 | */ | ||
| 36 | |||
| 37 | extern pgd_t *pgd_alloc(struct mm_struct *); | ||
| 38 | extern void pgd_free(struct mm_struct *, pgd_t *); | ||
| 39 | |||
| 40 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); | ||
| 41 | extern struct page *pte_alloc_one(struct mm_struct *, unsigned long); | ||
| 42 | |||
| 43 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | ||
| 44 | { | ||
| 45 | free_page((unsigned long) pte); | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | ||
| 49 | { | ||
| 50 | __free_page(pte); | ||
| 51 | } | ||
| 52 | |||
| 53 | |||
| 54 | #define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte)) | ||
| 55 | |||
| 56 | #endif /* _ASM_PGALLOC_H */ | ||
diff --git a/include/asm-mn10300/pgtable.h b/include/asm-mn10300/pgtable.h new file mode 100644 index 000000000000..375c4941deda --- /dev/null +++ b/include/asm-mn10300/pgtable.h | |||
| @@ -0,0 +1,489 @@ | |||
| 1 | /* MN10300 Page table manipulators and constants | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | * | ||
| 11 | * | ||
| 12 | * The Linux memory management assumes a three-level page table setup. On | ||
| 13 | * the i386, we use that, but "fold" the mid level into the top-level page | ||
| 14 | * table, so that we physically have the same two-level page table as the | ||
| 15 | * i386 mmu expects. | ||
| 16 | * | ||
| 17 | * This file contains the functions and defines necessary to modify and use | ||
| 18 | * the i386 page table tree for the purposes of the MN10300 TLB handler | ||
| 19 | * functions. | ||
| 20 | */ | ||
| 21 | #ifndef _ASM_PGTABLE_H | ||
| 22 | #define _ASM_PGTABLE_H | ||
| 23 | |||
| 24 | #include <asm/cpu-regs.h> | ||
| 25 | |||
| 26 | #ifndef __ASSEMBLY__ | ||
| 27 | #include <asm/processor.h> | ||
| 28 | #include <asm/cache.h> | ||
| 29 | #include <linux/threads.h> | ||
| 30 | |||
| 31 | #include <asm/bitops.h> | ||
| 32 | |||
| 33 | #include <linux/slab.h> | ||
| 34 | #include <linux/list.h> | ||
| 35 | #include <linux/spinlock.h> | ||
| 36 | |||
| 37 | /* | ||
| 38 | * ZERO_PAGE is a global shared page that is always zero: used | ||
| 39 | * for zero-mapped memory areas etc.. | ||
| 40 | */ | ||
| 41 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | ||
| 42 | extern unsigned long empty_zero_page[1024]; | ||
| 43 | extern spinlock_t pgd_lock; | ||
| 44 | extern struct page *pgd_list; | ||
| 45 | |||
| 46 | extern void pmd_ctor(void *, struct kmem_cache *, unsigned long); | ||
| 47 | extern void pgtable_cache_init(void); | ||
| 48 | extern void paging_init(void); | ||
| 49 | |||
| 50 | #endif /* !__ASSEMBLY__ */ | ||
| 51 | |||
| 52 | /* | ||
| 53 | * The Linux mn10300 paging architecture only implements both the traditional | ||
| 54 | * 2-level page tables | ||
| 55 | */ | ||
| 56 | #define PGDIR_SHIFT 22 | ||
| 57 | #define PTRS_PER_PGD 1024 | ||
| 58 | #define PTRS_PER_PUD 1 /* we don't really have any PUD physically */ | ||
| 59 | #define PTRS_PER_PMD 1 /* we don't really have any PMD physically */ | ||
| 60 | #define PTRS_PER_PTE 1024 | ||
| 61 | |||
| 62 | #define PGD_SIZE PAGE_SIZE | ||
| 63 | #define PMD_SIZE (1UL << PMD_SHIFT) | ||
| 64 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
| 65 | #define PGDIR_MASK (~(PGDIR_SIZE - 1)) | ||
| 66 | |||
| 67 | #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) | ||
| 68 | #define FIRST_USER_ADDRESS 0 | ||
| 69 | |||
| 70 | #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) | ||
| 71 | #define KERNEL_PGD_PTRS (PTRS_PER_PGD - USER_PGD_PTRS) | ||
| 72 | |||
| 73 | #define TWOLEVEL_PGDIR_SHIFT 22 | ||
| 74 | #define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT) | ||
| 75 | #define BOOT_KERNEL_PGD_PTRS (1024 - BOOT_USER_PGD_PTRS) | ||
| 76 | |||
| 77 | #ifndef __ASSEMBLY__ | ||
| 78 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | ||
| 79 | #endif | ||
| 80 | |||
| 81 | /* | ||
| 82 | * Unfortunately, due to the way the MMU works on the MN10300, the vmalloc VM | ||
| 83 | * area has to be in the lower half of the virtual address range (the upper | ||
| 84 | * half is not translated through the TLB). | ||
| 85 | * | ||
| 86 | * So in this case, the vmalloc area goes at the bottom of the address map | ||
| 87 | * (leaving a hole at the very bottom to catch addressing errors), and | ||
| 88 | * userspace starts immediately above. | ||
| 89 | * | ||
| 90 | * The vmalloc() routines also leaves a hole of 4kB between each vmalloced | ||
| 91 | * area to catch addressing errors. | ||
| 92 | */ | ||
| 93 | #define VMALLOC_OFFSET (8 * 1024 * 1024) | ||
| 94 | #define VMALLOC_START (0x70000000) | ||
| 95 | #define VMALLOC_END (0x7C000000) | ||
| 96 | |||
| 97 | #ifndef __ASSEMBLY__ | ||
| 98 | extern pte_t kernel_vmalloc_ptes[(VMALLOC_END - VMALLOC_START) / PAGE_SIZE]; | ||
| 99 | #endif | ||
| 100 | |||
| 101 | /* IPTEL/DPTEL bit assignments */ | ||
| 102 | #define _PAGE_BIT_VALID xPTEL_V_BIT | ||
| 103 | #define _PAGE_BIT_ACCESSED xPTEL_UNUSED1_BIT /* mustn't be loaded into IPTEL/DPTEL */ | ||
| 104 | #define _PAGE_BIT_NX xPTEL_UNUSED2_BIT /* mustn't be loaded into IPTEL/DPTEL */ | ||
| 105 | #define _PAGE_BIT_CACHE xPTEL_C_BIT | ||
| 106 | #define _PAGE_BIT_PRESENT xPTEL_PV_BIT | ||
| 107 | #define _PAGE_BIT_DIRTY xPTEL_D_BIT | ||
| 108 | #define _PAGE_BIT_GLOBAL xPTEL_G_BIT | ||
| 109 | |||
| 110 | #define _PAGE_VALID xPTEL_V | ||
| 111 | #define _PAGE_ACCESSED xPTEL_UNUSED1 | ||
| 112 | #define _PAGE_NX xPTEL_UNUSED2 /* no-execute bit */ | ||
| 113 | #define _PAGE_CACHE xPTEL_C | ||
| 114 | #define _PAGE_PRESENT xPTEL_PV | ||
| 115 | #define _PAGE_DIRTY xPTEL_D | ||
| 116 | #define _PAGE_PROT xPTEL_PR | ||
| 117 | #define _PAGE_PROT_RKNU xPTEL_PR_ROK | ||
| 118 | #define _PAGE_PROT_WKNU xPTEL_PR_RWK | ||
| 119 | #define _PAGE_PROT_RKRU xPTEL_PR_ROK_ROU | ||
| 120 | #define _PAGE_PROT_WKRU xPTEL_PR_RWK_ROU | ||
| 121 | #define _PAGE_PROT_WKWU xPTEL_PR_RWK_RWU | ||
| 122 | #define _PAGE_GLOBAL xPTEL_G | ||
| 123 | #define _PAGE_PSE xPTEL_PS_4Mb /* 4MB page */ | ||
| 124 | |||
| 125 | #define _PAGE_FILE xPTEL_UNUSED1_BIT /* set:pagecache unset:swap */ | ||
| 126 | |||
| 127 | #define __PAGE_PROT_UWAUX 0x040 | ||
| 128 | #define __PAGE_PROT_USER 0x080 | ||
| 129 | #define __PAGE_PROT_WRITE 0x100 | ||
| 130 | |||
| 131 | #define _PAGE_PRESENTV (_PAGE_PRESENT|_PAGE_VALID) | ||
| 132 | #define _PAGE_PROTNONE 0x000 /* If not present */ | ||
| 133 | |||
| 134 | #ifndef __ASSEMBLY__ | ||
| 135 | |||
| 136 | #define VMALLOC_VMADDR(x) ((unsigned long)(x)) | ||
| 137 | |||
| 138 | #define _PAGE_TABLE (_PAGE_PRESENTV | _PAGE_PROT_WKNU | _PAGE_ACCESSED | _PAGE_DIRTY) | ||
| 139 | #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) | ||
| 140 | |||
| 141 | #define __PAGE_NONE (_PAGE_PRESENTV | _PAGE_PROT_RKNU | _PAGE_ACCESSED | _PAGE_CACHE) | ||
| 142 | #define __PAGE_SHARED (_PAGE_PRESENTV | _PAGE_PROT_WKWU | _PAGE_ACCESSED | _PAGE_CACHE) | ||
| 143 | #define __PAGE_COPY (_PAGE_PRESENTV | _PAGE_PROT_RKRU | _PAGE_ACCESSED | _PAGE_CACHE) | ||
| 144 | #define __PAGE_READONLY (_PAGE_PRESENTV | _PAGE_PROT_RKRU | _PAGE_ACCESSED | _PAGE_CACHE) | ||
| 145 | |||
| 146 | #define PAGE_NONE __pgprot(__PAGE_NONE | _PAGE_NX) | ||
| 147 | #define PAGE_SHARED_NOEXEC __pgprot(__PAGE_SHARED | _PAGE_NX) | ||
| 148 | #define PAGE_COPY_NOEXEC __pgprot(__PAGE_COPY | _PAGE_NX) | ||
| 149 | #define PAGE_READONLY_NOEXEC __pgprot(__PAGE_READONLY | _PAGE_NX) | ||
| 150 | #define PAGE_SHARED_EXEC __pgprot(__PAGE_SHARED) | ||
| 151 | #define PAGE_COPY_EXEC __pgprot(__PAGE_COPY) | ||
| 152 | #define PAGE_READONLY_EXEC __pgprot(__PAGE_READONLY) | ||
| 153 | #define PAGE_COPY PAGE_COPY_NOEXEC | ||
| 154 | #define PAGE_READONLY PAGE_READONLY_NOEXEC | ||
| 155 | #define PAGE_SHARED PAGE_SHARED_EXEC | ||
| 156 | |||
| 157 | #define __PAGE_KERNEL_BASE (_PAGE_PRESENTV | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL) | ||
| 158 | |||
| 159 | #define __PAGE_KERNEL (__PAGE_KERNEL_BASE | _PAGE_PROT_WKNU | _PAGE_CACHE | _PAGE_NX) | ||
| 160 | #define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL_BASE | _PAGE_PROT_WKNU | _PAGE_NX) | ||
| 161 | #define __PAGE_KERNEL_EXEC (__PAGE_KERNEL & ~_PAGE_NX) | ||
| 162 | #define __PAGE_KERNEL_RO (__PAGE_KERNEL_BASE | _PAGE_PROT_RKNU | _PAGE_CACHE | _PAGE_NX) | ||
| 163 | #define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE) | ||
| 164 | #define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE) | ||
| 165 | |||
| 166 | #define PAGE_KERNEL __pgprot(__PAGE_KERNEL) | ||
| 167 | #define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO) | ||
| 168 | #define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC) | ||
| 169 | #define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE) | ||
| 170 | #define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE) | ||
| 171 | #define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC) | ||
| 172 | |||
| 173 | /* | ||
| 174 | * Whilst the MN10300 can do page protection for execute (given separate data | ||
| 175 | * and insn TLBs), we are not supporting it at the moment. Write permission, | ||
| 176 | * however, always implies read permission (but not execute permission). | ||
| 177 | */ | ||
| 178 | #define __P000 PAGE_NONE | ||
| 179 | #define __P001 PAGE_READONLY_NOEXEC | ||
| 180 | #define __P010 PAGE_COPY_NOEXEC | ||
| 181 | #define __P011 PAGE_COPY_NOEXEC | ||
| 182 | #define __P100 PAGE_READONLY_EXEC | ||
| 183 | #define __P101 PAGE_READONLY_EXEC | ||
| 184 | #define __P110 PAGE_COPY_EXEC | ||
| 185 | #define __P111 PAGE_COPY_EXEC | ||
| 186 | |||
| 187 | #define __S000 PAGE_NONE | ||
| 188 | #define __S001 PAGE_READONLY_NOEXEC | ||
| 189 | #define __S010 PAGE_SHARED_NOEXEC | ||
| 190 | #define __S011 PAGE_SHARED_NOEXEC | ||
| 191 | #define __S100 PAGE_READONLY_EXEC | ||
| 192 | #define __S101 PAGE_READONLY_EXEC | ||
| 193 | #define __S110 PAGE_SHARED_EXEC | ||
| 194 | #define __S111 PAGE_SHARED_EXEC | ||
| 195 | |||
| 196 | /* | ||
| 197 | * Define this to warn about kernel memory accesses that are | ||
| 198 | * done without a 'verify_area(VERIFY_WRITE,..)' | ||
| 199 | */ | ||
| 200 | #undef TEST_VERIFY_AREA | ||
| 201 | |||
| 202 | #define pte_present(x) (pte_val(x) & _PAGE_VALID) | ||
| 203 | #define pte_clear(mm, addr, xp) \ | ||
| 204 | do { \ | ||
| 205 | set_pte_at((mm), (addr), (xp), __pte(0)); \ | ||
| 206 | } while (0) | ||
| 207 | |||
| 208 | #define pmd_none(x) (!pmd_val(x)) | ||
| 209 | #define pmd_present(x) (!pmd_none(x)) | ||
| 210 | #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) | ||
| 211 | #define pmd_bad(x) 0 | ||
| 212 | |||
| 213 | |||
| 214 | #define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT)) | ||
| 215 | |||
| 216 | #ifndef __ASSEMBLY__ | ||
| 217 | |||
| 218 | /* | ||
| 219 | * The following only work if pte_present() is true. | ||
| 220 | * Undefined behaviour if not.. | ||
| 221 | */ | ||
| 222 | static inline int pte_user(pte_t pte) { return pte_val(pte) & __PAGE_PROT_USER; } | ||
| 223 | static inline int pte_read(pte_t pte) { return pte_val(pte) & __PAGE_PROT_USER; } | ||
| 224 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } | ||
| 225 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } | ||
| 226 | static inline int pte_write(pte_t pte) { return pte_val(pte) & __PAGE_PROT_WRITE; } | ||
| 227 | |||
| 228 | /* | ||
| 229 | * The following only works if pte_present() is not true. | ||
| 230 | */ | ||
| 231 | static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } | ||
| 232 | |||
| 233 | static inline pte_t pte_rdprotect(pte_t pte) | ||
| 234 | { | ||
| 235 | pte_val(pte) &= ~(__PAGE_PROT_USER|__PAGE_PROT_UWAUX); return pte; | ||
| 236 | } | ||
| 237 | static inline pte_t pte_exprotect(pte_t pte) | ||
| 238 | { | ||
| 239 | pte_val(pte) |= _PAGE_NX; return pte; | ||
| 240 | } | ||
| 241 | |||
| 242 | static inline pte_t pte_wrprotect(pte_t pte) | ||
| 243 | { | ||
| 244 | pte_val(pte) &= ~(__PAGE_PROT_WRITE|__PAGE_PROT_UWAUX); return pte; | ||
| 245 | } | ||
| 246 | |||
| 247 | static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } | ||
| 248 | static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } | ||
| 249 | static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } | ||
| 250 | static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } | ||
| 251 | static inline pte_t pte_mkexec(pte_t pte) { pte_val(pte) &= ~_PAGE_NX; return pte; } | ||
| 252 | |||
| 253 | static inline pte_t pte_mkread(pte_t pte) | ||
| 254 | { | ||
| 255 | pte_val(pte) |= __PAGE_PROT_USER; | ||
| 256 | if (pte_write(pte)) | ||
| 257 | pte_val(pte) |= __PAGE_PROT_UWAUX; | ||
| 258 | return pte; | ||
| 259 | } | ||
| 260 | static inline pte_t pte_mkwrite(pte_t pte) | ||
| 261 | { | ||
| 262 | pte_val(pte) |= __PAGE_PROT_WRITE; | ||
| 263 | if (pte_val(pte) & __PAGE_PROT_USER) | ||
| 264 | pte_val(pte) |= __PAGE_PROT_UWAUX; | ||
| 265 | return pte; | ||
| 266 | } | ||
| 267 | |||
| 268 | #define pte_ERROR(e) \ | ||
| 269 | printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \ | ||
| 270 | __FILE__, __LINE__, pte_val(e)) | ||
| 271 | #define pgd_ERROR(e) \ | ||
| 272 | printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ | ||
| 273 | __FILE__, __LINE__, pgd_val(e)) | ||
| 274 | |||
| 275 | /* | ||
| 276 | * The "pgd_xxx()" functions here are trivial for a folded two-level | ||
| 277 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | ||
| 278 | * into the pgd entry) | ||
| 279 | */ | ||
| 280 | #define pgd_clear(xp) do { } while (0) | ||
| 281 | |||
| 282 | /* | ||
| 283 | * Certain architectures need to do special things when PTEs | ||
| 284 | * within a page table are directly modified. Thus, the following | ||
| 285 | * hook is made available. | ||
| 286 | */ | ||
| 287 | #define set_pte(pteptr, pteval) (*(pteptr) = pteval) | ||
| 288 | #define set_pte_at(mm, addr, ptep, pteval) set_pte((ptep), (pteval)) | ||
| 289 | #define set_pte_atomic(pteptr, pteval) set_pte((pteptr), (pteval)) | ||
| 290 | |||
| 291 | /* | ||
| 292 | * (pmds are folded into pgds so this doesn't get actually called, | ||
| 293 | * but the define is needed for a generic inline function.) | ||
| 294 | */ | ||
| 295 | #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) | ||
| 296 | |||
| 297 | #define ptep_get_and_clear(mm, addr, ptep) \ | ||
| 298 | __pte(xchg(&(ptep)->pte, 0)) | ||
| 299 | #define pte_same(a, b) (pte_val(a) == pte_val(b)) | ||
| 300 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | ||
| 301 | #define pte_none(x) (!pte_val(x)) | ||
| 302 | #define pte_pfn(x) ((unsigned long) (pte_val(x) >> PAGE_SHIFT)) | ||
| 303 | #define __pfn_addr(pfn) ((pfn) << PAGE_SHIFT) | ||
| 304 | #define pfn_pte(pfn, prot) __pte(__pfn_addr(pfn) | pgprot_val(prot)) | ||
| 305 | #define pfn_pmd(pfn, prot) __pmd(__pfn_addr(pfn) | pgprot_val(prot)) | ||
| 306 | |||
| 307 | /* | ||
| 308 | * All present user pages are user-executable: | ||
| 309 | */ | ||
| 310 | static inline int pte_exec(pte_t pte) | ||
| 311 | { | ||
| 312 | return pte_user(pte); | ||
| 313 | } | ||
| 314 | |||
| 315 | /* | ||
| 316 | * All present pages are kernel-executable: | ||
| 317 | */ | ||
| 318 | static inline int pte_exec_kernel(pte_t pte) | ||
| 319 | { | ||
| 320 | return 1; | ||
| 321 | } | ||
| 322 | |||
| 323 | /* | ||
| 324 | * Bits 0 and 1 are taken, split up the 29 bits of offset | ||
| 325 | * into this range: | ||
| 326 | */ | ||
| 327 | #define PTE_FILE_MAX_BITS 29 | ||
| 328 | |||
| 329 | #define pte_to_pgoff(pte) (pte_val(pte) >> 2) | ||
| 330 | #define pgoff_to_pte(off) __pte((off) << 2 | _PAGE_FILE) | ||
| 331 | |||
| 332 | /* Encode and de-code a swap entry */ | ||
| 333 | #define __swp_type(x) (((x).val >> 2) & 0x3f) | ||
| 334 | #define __swp_offset(x) ((x).val >> 8) | ||
| 335 | #define __swp_entry(type, offset) \ | ||
| 336 | ((swp_entry_t) { ((type) << 2) | ((offset) << 8) }) | ||
| 337 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | ||
| 338 | #define __swp_entry_to_pte(x) __pte((x).val) | ||
| 339 | |||
| 340 | static inline | ||
| 341 | int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr, | ||
| 342 | pte_t *ptep) | ||
| 343 | { | ||
| 344 | if (!pte_dirty(*ptep)) | ||
| 345 | return 0; | ||
| 346 | return test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte); | ||
| 347 | } | ||
| 348 | |||
| 349 | static inline | ||
| 350 | int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, | ||
| 351 | pte_t *ptep) | ||
| 352 | { | ||
| 353 | if (!pte_young(*ptep)) | ||
| 354 | return 0; | ||
| 355 | return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte); | ||
| 356 | } | ||
| 357 | |||
| 358 | static inline | ||
| 359 | void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) | ||
| 360 | { | ||
| 361 | pte_val(*ptep) &= ~(__PAGE_PROT_WRITE|__PAGE_PROT_UWAUX); | ||
| 362 | } | ||
| 363 | |||
| 364 | static inline void ptep_mkdirty(pte_t *ptep) | ||
| 365 | { | ||
| 366 | set_bit(_PAGE_BIT_DIRTY, &ptep->pte); | ||
| 367 | } | ||
| 368 | |||
| 369 | /* | ||
| 370 | * Macro to mark a page protection value as "uncacheable". On processors which | ||
| 371 | * do not support it, this is a no-op. | ||
| 372 | */ | ||
| 373 | #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_CACHE) | ||
| 374 | |||
| 375 | |||
| 376 | /* | ||
| 377 | * Conversion functions: convert a page and protection to a page entry, | ||
| 378 | * and a page entry and page directory to the page they refer to. | ||
| 379 | */ | ||
| 380 | |||
| 381 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | ||
| 382 | #define mk_pte_huge(entry) \ | ||
| 383 | ((entry).pte |= _PAGE_PRESENT | _PAGE_PSE | _PAGE_VALID) | ||
| 384 | |||
| 385 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | ||
| 386 | { | ||
| 387 | pte_val(pte) &= _PAGE_CHG_MASK; | ||
| 388 | pte_val(pte) |= pgprot_val(newprot); | ||
| 389 | return pte; | ||
| 390 | } | ||
| 391 | |||
| 392 | #define page_pte(page) page_pte_prot((page), __pgprot(0)) | ||
| 393 | |||
| 394 | #define pmd_page_kernel(pmd) \ | ||
| 395 | ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) | ||
| 396 | |||
| 397 | #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) | ||
| 398 | |||
| 399 | #define pmd_large(pmd) \ | ||
| 400 | ((pmd_val(pmd) & (_PAGE_PSE | _PAGE_PRESENT)) == \ | ||
| 401 | (_PAGE_PSE | _PAGE_PRESENT)) | ||
| 402 | |||
| 403 | /* | ||
| 404 | * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD] | ||
| 405 | * | ||
| 406 | * this macro returns the index of the entry in the pgd page which would | ||
| 407 | * control the given virtual address | ||
| 408 | */ | ||
| 409 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) | ||
| 410 | |||
| 411 | /* | ||
| 412 | * pgd_offset() returns a (pgd_t *) | ||
| 413 | * pgd_index() is used get the offset into the pgd page's array of pgd_t's; | ||
| 414 | */ | ||
| 415 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | ||
| 416 | |||
| 417 | /* | ||
| 418 | * a shortcut which implies the use of the kernel's pgd, instead | ||
| 419 | * of a process's | ||
| 420 | */ | ||
| 421 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | ||
| 422 | |||
| 423 | /* | ||
| 424 | * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD] | ||
| 425 | * | ||
| 426 | * this macro returns the index of the entry in the pmd page which would | ||
| 427 | * control the given virtual address | ||
| 428 | */ | ||
| 429 | #define pmd_index(address) \ | ||
| 430 | (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) | ||
| 431 | |||
| 432 | /* | ||
| 433 | * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE] | ||
| 434 | * | ||
| 435 | * this macro returns the index of the entry in the pte page which would | ||
| 436 | * control the given virtual address | ||
| 437 | */ | ||
| 438 | #define pte_index(address) \ | ||
| 439 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | ||
| 440 | |||
| 441 | #define pte_offset_kernel(dir, address) \ | ||
| 442 | ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address)) | ||
| 443 | |||
| 444 | /* | ||
| 445 | * Make a given kernel text page executable/non-executable. | ||
| 446 | * Returns the previous executability setting of that page (which | ||
| 447 | * is used to restore the previous state). Used by the SMP bootup code. | ||
| 448 | * NOTE: this is an __init function for security reasons. | ||
| 449 | */ | ||
| 450 | static inline int set_kernel_exec(unsigned long vaddr, int enable) | ||
| 451 | { | ||
| 452 | return 0; | ||
| 453 | } | ||
| 454 | |||
| 455 | #define pte_offset_map(dir, address) \ | ||
| 456 | ((pte_t *) page_address(pmd_page(*(dir))) + pte_index(address)) | ||
| 457 | #define pte_offset_map_nested(dir, address) pte_offset_map(dir, address) | ||
| 458 | #define pte_unmap(pte) do {} while (0) | ||
| 459 | #define pte_unmap_nested(pte) do {} while (0) | ||
| 460 | |||
| 461 | /* | ||
| 462 | * The MN10300 has external MMU info in the form of a TLB: this is adapted from | ||
| 463 | * the kernel page tables containing the necessary information by tlb-mn10300.S | ||
| 464 | */ | ||
| 465 | extern void update_mmu_cache(struct vm_area_struct *vma, | ||
| 466 | unsigned long address, pte_t pte); | ||
| 467 | |||
| 468 | #endif /* !__ASSEMBLY__ */ | ||
| 469 | |||
| 470 | #define kern_addr_valid(addr) (1) | ||
| 471 | |||
| 472 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ | ||
| 473 | remap_pfn_range((vma), (vaddr), (pfn), (size), (prot)) | ||
| 474 | |||
| 475 | #define MK_IOSPACE_PFN(space, pfn) (pfn) | ||
| 476 | #define GET_IOSPACE(pfn) 0 | ||
| 477 | #define GET_PFN(pfn) (pfn) | ||
| 478 | |||
| 479 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | ||
| 480 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY | ||
| 481 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | ||
| 482 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | ||
| 483 | #define __HAVE_ARCH_PTEP_MKDIRTY | ||
| 484 | #define __HAVE_ARCH_PTE_SAME | ||
| 485 | #include <asm-generic/pgtable.h> | ||
| 486 | |||
| 487 | #endif /* !__ASSEMBLY__ */ | ||
| 488 | |||
| 489 | #endif /* _ASM_PGTABLE_H */ | ||
diff --git a/include/asm-mn10300/pio-regs.h b/include/asm-mn10300/pio-regs.h new file mode 100644 index 000000000000..96bc8182d0ba --- /dev/null +++ b/include/asm-mn10300/pio-regs.h | |||
| @@ -0,0 +1,233 @@ | |||
| 1 | /* MN10300 On-board I/O port module registers | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_PIO_REGS_H | ||
| 12 | #define _ASM_PIO_REGS_H | ||
| 13 | |||
| 14 | #include <asm/cpu-regs.h> | ||
| 15 | #include <asm/intctl-regs.h> | ||
| 16 | |||
| 17 | #ifdef __KERNEL__ | ||
| 18 | |||
| 19 | /* I/O port 0 */ | ||
| 20 | #define P0MD __SYSREG(0xdb000000, u16) /* mode reg */ | ||
| 21 | #define P0MD_0 0x0003 /* mask */ | ||
| 22 | #define P0MD_0_IN 0x0000 /* input mode */ | ||
| 23 | #define P0MD_0_OUT 0x0001 /* output mode */ | ||
| 24 | #define P0MD_0_TM0IO 0x0002 /* timer 0 I/O mode */ | ||
| 25 | #define P0MD_0_EYECLK 0x0003 /* test signal output (clock) */ | ||
| 26 | #define P0MD_1 0x000c | ||
| 27 | #define P0MD_1_IN 0x0000 | ||
| 28 | #define P0MD_1_OUT 0x0004 | ||
| 29 | #define P0MD_1_TM1IO 0x0008 /* timer 1 I/O mode */ | ||
| 30 | #define P0MD_1_EYED 0x000c /* test signal output (data) */ | ||
| 31 | #define P0MD_2 0x0030 | ||
| 32 | #define P0MD_2_IN 0x0000 | ||
| 33 | #define P0MD_2_OUT 0x0010 | ||
| 34 | #define P0MD_2_TM2IO 0x0020 /* timer 2 I/O mode */ | ||
| 35 | #define P0MD_3 0x00c0 | ||
| 36 | #define P0MD_3_IN 0x0000 | ||
| 37 | #define P0MD_3_OUT 0x0040 | ||
| 38 | #define P0MD_3_TM3IO 0x0080 /* timer 3 I/O mode */ | ||
| 39 | #define P0MD_4 0x0300 | ||
| 40 | #define P0MD_4_IN 0x0000 | ||
| 41 | #define P0MD_4_OUT 0x0100 | ||
| 42 | #define P0MD_4_TM4IO 0x0200 /* timer 4 I/O mode */ | ||
| 43 | #define P0MD_4_XCTS 0x0300 /* XCTS input for serial port 2 */ | ||
| 44 | #define P0MD_5 0x0c00 | ||
| 45 | #define P0MD_5_IN 0x0000 | ||
| 46 | #define P0MD_5_OUT 0x0400 | ||
| 47 | #define P0MD_5_TM5IO 0x0800 /* timer 5 I/O mode */ | ||
| 48 | #define P0MD_6 0x3000 | ||
| 49 | #define P0MD_6_IN 0x0000 | ||
| 50 | #define P0MD_6_OUT 0x1000 | ||
| 51 | #define P0MD_6_TM6IOA 0x2000 /* timer 6 I/O mode A */ | ||
| 52 | #define P0MD_7 0xc000 | ||
| 53 | #define P0MD_7_IN 0x0000 | ||
| 54 | #define P0MD_7_OUT 0x4000 | ||
| 55 | #define P0MD_7_TM6IOB 0x8000 /* timer 6 I/O mode B */ | ||
| 56 | |||
| 57 | #define P0IN __SYSREG(0xdb000004, u8) /* in reg */ | ||
| 58 | #define P0OUT __SYSREG(0xdb000008, u8) /* out reg */ | ||
| 59 | |||
| 60 | #define P0TMIO __SYSREG(0xdb00000c, u8) /* TM pin I/O control reg */ | ||
| 61 | #define P0TMIO_TM0_IN 0x00 | ||
| 62 | #define P0TMIO_TM0_OUT 0x01 | ||
| 63 | #define P0TMIO_TM1_IN 0x00 | ||
| 64 | #define P0TMIO_TM1_OUT 0x02 | ||
| 65 | #define P0TMIO_TM2_IN 0x00 | ||
| 66 | #define P0TMIO_TM2_OUT 0x04 | ||
| 67 | #define P0TMIO_TM3_IN 0x00 | ||
| 68 | #define P0TMIO_TM3_OUT 0x08 | ||
| 69 | #define P0TMIO_TM4_IN 0x00 | ||
| 70 | #define P0TMIO_TM4_OUT 0x10 | ||
| 71 | #define P0TMIO_TM5_IN 0x00 | ||
| 72 | #define P0TMIO_TM5_OUT 0x20 | ||
| 73 | #define P0TMIO_TM6A_IN 0x00 | ||
| 74 | #define P0TMIO_TM6A_OUT 0x40 | ||
| 75 | #define P0TMIO_TM6B_IN 0x00 | ||
| 76 | #define P0TMIO_TM6B_OUT 0x80 | ||
| 77 | |||
| 78 | /* I/O port 1 */ | ||
| 79 | #define P1MD __SYSREG(0xdb000100, u16) /* mode reg */ | ||
| 80 | #define P1MD_0 0x0003 /* mask */ | ||
| 81 | #define P1MD_0_IN 0x0000 /* input mode */ | ||
| 82 | #define P1MD_0_OUT 0x0001 /* output mode */ | ||
| 83 | #define P1MD_0_TM7IO 0x0002 /* timer 7 I/O mode */ | ||
| 84 | #define P1MD_0_ADTRG 0x0003 /* A/D converter trigger mode */ | ||
| 85 | #define P1MD_1 0x000c | ||
| 86 | #define P1MD_1_IN 0x0000 | ||
| 87 | #define P1MD_1_OUT 0x0004 | ||
| 88 | #define P1MD_1_TM8IO 0x0008 /* timer 8 I/O mode */ | ||
| 89 | #define P1MD_1_XDMR0 0x000c /* DMA request input 0 mode */ | ||
| 90 | #define P1MD_2 0x0030 | ||
| 91 | #define P1MD_2_IN 0x0000 | ||
| 92 | #define P1MD_2_OUT 0x0010 | ||
| 93 | #define P1MD_2_TM9IO 0x0020 /* timer 9 I/O mode */ | ||
| 94 | #define P1MD_2_XDMR1 0x0030 /* DMA request input 1 mode */ | ||
| 95 | #define P1MD_3 0x00c0 | ||
| 96 | #define P1MD_3_IN 0x0000 | ||
| 97 | #define P1MD_3_OUT 0x0040 | ||
| 98 | #define P1MD_3_TM10IO 0x0080 /* timer 10 I/O mode */ | ||
| 99 | #define P1MD_3_FRQS0 0x00c0 /* CPU clock multiplier setting input 0 mode */ | ||
| 100 | #define P1MD_4 0x0300 | ||
| 101 | #define P1MD_4_IN 0x0000 | ||
| 102 | #define P1MD_4_OUT 0x0100 | ||
| 103 | #define P1MD_4_TM11IO 0x0200 /* timer 11 I/O mode */ | ||
| 104 | #define P1MD_4_FRQS1 0x0300 /* CPU clock multiplier setting input 1 mode */ | ||
| 105 | |||
| 106 | #define P1IN __SYSREG(0xdb000104, u8) /* in reg */ | ||
| 107 | #define P1OUT __SYSREG(0xdb000108, u8) /* out reg */ | ||
| 108 | #define P1TMIO __SYSREG(0xdb00010c, u8) /* TM pin I/O control reg */ | ||
| 109 | #define P1TMIO_TM11_IN 0x00 | ||
| 110 | #define P1TMIO_TM11_OUT 0x01 | ||
| 111 | #define P1TMIO_TM10_IN 0x00 | ||
| 112 | #define P1TMIO_TM10_OUT 0x02 | ||
| 113 | #define P1TMIO_TM9_IN 0x00 | ||
| 114 | #define P1TMIO_TM9_OUT 0x04 | ||
| 115 | #define P1TMIO_TM8_IN 0x00 | ||
| 116 | #define P1TMIO_TM8_OUT 0x08 | ||
| 117 | #define P1TMIO_TM7_IN 0x00 | ||
| 118 | #define P1TMIO_TM7_OUT 0x10 | ||
| 119 | |||
| 120 | /* I/O port 2 */ | ||
| 121 | #define P2MD __SYSREG(0xdb000200, u16) /* mode reg */ | ||
| 122 | #define P2MD_0 0x0003 /* mask */ | ||
| 123 | #define P2MD_0_IN 0x0000 /* input mode */ | ||
| 124 | #define P2MD_0_OUT 0x0001 /* output mode */ | ||
| 125 | #define P2MD_0_BOOTBW 0x0003 /* boot bus width selector mode */ | ||
| 126 | #define P2MD_1 0x000c | ||
| 127 | #define P2MD_1_IN 0x0000 | ||
| 128 | #define P2MD_1_OUT 0x0004 | ||
| 129 | #define P2MD_1_BOOTSEL 0x000c /* boot device selector mode */ | ||
| 130 | #define P2MD_2 0x0030 | ||
| 131 | #define P2MD_2_IN 0x0000 | ||
| 132 | #define P2MD_2_OUT 0x0010 | ||
| 133 | #define P2MD_3 0x00c0 | ||
| 134 | #define P2MD_3_IN 0x0000 | ||
| 135 | #define P2MD_3_OUT 0x0040 | ||
| 136 | #define P2MD_3_CKIO 0x00c0 /* mode */ | ||
| 137 | #define P2MD_4 0x0300 | ||
| 138 | #define P2MD_4_IN 0x0000 | ||
| 139 | #define P2MD_4_OUT 0x0100 | ||
| 140 | #define P2MD_4_CMOD 0x0300 /* mode */ | ||
| 141 | |||
| 142 | #define P2IN __SYSREG(0xdb000204, u8) /* in reg */ | ||
| 143 | #define P2OUT __SYSREG(0xdb000208, u8) /* out reg */ | ||
| 144 | #define P2TMIO __SYSREG(0xdb00020c, u8) /* TM pin I/O control reg */ | ||
| 145 | |||
| 146 | /* I/O port 3 */ | ||
| 147 | #define P3MD __SYSREG(0xdb000300, u16) /* mode reg */ | ||
| 148 | #define P3MD_0 0x0003 /* mask */ | ||
| 149 | #define P3MD_0_IN 0x0000 /* input mode */ | ||
| 150 | #define P3MD_0_OUT 0x0001 /* output mode */ | ||
| 151 | #define P3MD_0_AFRXD 0x0002 /* AFR interface mode */ | ||
| 152 | #define P3MD_1 0x000c | ||
| 153 | #define P3MD_1_IN 0x0000 | ||
| 154 | #define P3MD_1_OUT 0x0004 | ||
| 155 | #define P3MD_1_AFTXD 0x0008 /* AFR interface mode */ | ||
| 156 | #define P3MD_2 0x0030 | ||
| 157 | #define P3MD_2_IN 0x0000 | ||
| 158 | #define P3MD_2_OUT 0x0010 | ||
| 159 | #define P3MD_2_AFSCLK 0x0020 /* AFR interface mode */ | ||
| 160 | #define P3MD_3 0x00c0 | ||
| 161 | #define P3MD_3_IN 0x0000 | ||
| 162 | #define P3MD_3_OUT 0x0040 | ||
| 163 | #define P3MD_3_AFFS 0x0080 /* AFR interface mode */ | ||
| 164 | #define P3MD_4 0x0300 | ||
| 165 | #define P3MD_4_IN 0x0000 | ||
| 166 | #define P3MD_4_OUT 0x0100 | ||
| 167 | #define P3MD_4_AFEHC 0x0200 /* AFR interface mode */ | ||
| 168 | |||
| 169 | #define P3IN __SYSREG(0xdb000304, u8) /* in reg */ | ||
| 170 | #define P3OUT __SYSREG(0xdb000308, u8) /* out reg */ | ||
| 171 | |||
| 172 | /* I/O port 4 */ | ||
| 173 | #define P4MD __SYSREG(0xdb000400, u16) /* mode reg */ | ||
| 174 | #define P4MD_0 0x0003 /* mask */ | ||
| 175 | #define P4MD_0_IN 0x0000 /* input mode */ | ||
| 176 | #define P4MD_0_OUT 0x0001 /* output mode */ | ||
| 177 | #define P4MD_0_SCL0 0x0002 /* I2C/serial mode */ | ||
| 178 | #define P4MD_1 0x000c | ||
| 179 | #define P4MD_1_IN 0x0000 | ||
| 180 | #define P4MD_1_OUT 0x0004 | ||
| 181 | #define P4MD_1_SDA0 0x0008 | ||
| 182 | #define P4MD_2 0x0030 | ||
| 183 | #define P4MD_2_IN 0x0000 | ||
| 184 | #define P4MD_2_OUT 0x0010 | ||
| 185 | #define P4MD_2_SCL1 0x0020 | ||
| 186 | #define P4MD_3 0x00c0 | ||
| 187 | #define P4MD_3_IN 0x0000 | ||
| 188 | #define P4MD_3_OUT 0x0040 | ||
| 189 | #define P4MD_3_SDA1 0x0080 | ||
| 190 | #define P4MD_4 0x0300 | ||
| 191 | #define P4MD_4_IN 0x0000 | ||
| 192 | #define P4MD_4_OUT 0x0100 | ||
| 193 | #define P4MD_4_SBO0 0x0200 | ||
| 194 | #define P4MD_5 0x0c00 | ||
| 195 | #define P4MD_5_IN 0x0000 | ||
| 196 | #define P4MD_5_OUT 0x0400 | ||
| 197 | #define P4MD_5_SBO1 0x0800 | ||
| 198 | #define P4MD_6 0x3000 | ||
| 199 | #define P4MD_6_IN 0x0000 | ||
| 200 | #define P4MD_6_OUT 0x1000 | ||
| 201 | #define P4MD_6_SBT0 0x2000 | ||
| 202 | #define P4MD_7 0xc000 | ||
| 203 | #define P4MD_7_IN 0x0000 | ||
| 204 | #define P4MD_7_OUT 0x4000 | ||
| 205 | #define P4MD_7_SBT1 0x8000 | ||
| 206 | |||
| 207 | #define P4IN __SYSREG(0xdb000404, u8) /* in reg */ | ||
| 208 | #define P4OUT __SYSREG(0xdb000408, u8) /* out reg */ | ||
| 209 | |||
| 210 | /* I/O port 5 */ | ||
| 211 | #define P5MD __SYSREG(0xdb000500, u16) /* mode reg */ | ||
| 212 | #define P5MD_0 0x0003 /* mask */ | ||
| 213 | #define P5MD_0_IN 0x0000 /* input mode */ | ||
| 214 | #define P5MD_0_OUT 0x0001 /* output mode */ | ||
| 215 | #define P5MD_0_IRTXD 0x0002 /* IrDA mode */ | ||
| 216 | #define P5MD_0_SOUT 0x0004 /* serial mode */ | ||
| 217 | #define P5MD_1 0x000c | ||
| 218 | #define P5MD_1_IN 0x0000 | ||
| 219 | #define P5MD_1_OUT 0x0004 | ||
| 220 | #define P5MD_1_IRRXDS 0x0008 /* IrDA mode */ | ||
| 221 | #define P5MD_1_SIN 0x000c /* serial mode */ | ||
| 222 | #define P5MD_2 0x0030 | ||
| 223 | #define P5MD_2_IN 0x0000 | ||
| 224 | #define P5MD_2_OUT 0x0010 | ||
| 225 | #define P5MD_2_IRRXDF 0x0020 /* IrDA mode */ | ||
| 226 | |||
| 227 | #define P5IN __SYSREG(0xdb000504, u8) /* in reg */ | ||
| 228 | #define P5OUT __SYSREG(0xdb000508, u8) /* out reg */ | ||
| 229 | |||
| 230 | |||
| 231 | #endif /* __KERNEL__ */ | ||
| 232 | |||
| 233 | #endif /* _ASM_PIO_REGS_H */ | ||
diff --git a/include/asm-mn10300/poll.h b/include/asm-mn10300/poll.h new file mode 100644 index 000000000000..c98509d3149e --- /dev/null +++ b/include/asm-mn10300/poll.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/poll.h> | |||
diff --git a/include/asm-mn10300/posix_types.h b/include/asm-mn10300/posix_types.h new file mode 100644 index 000000000000..077567c37798 --- /dev/null +++ b/include/asm-mn10300/posix_types.h | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | /* MN10300 POSIX types | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_POSIX_TYPES_H | ||
| 12 | #define _ASM_POSIX_TYPES_H | ||
| 13 | |||
| 14 | /* | ||
| 15 | * This file is generally used by user-level software, so you need to | ||
| 16 | * be a little careful about namespace pollution etc. Also, we cannot | ||
| 17 | * assume GCC is being used. | ||
| 18 | */ | ||
| 19 | |||
| 20 | typedef unsigned long __kernel_ino_t; | ||
| 21 | typedef unsigned short __kernel_mode_t; | ||
| 22 | typedef unsigned short __kernel_nlink_t; | ||
| 23 | typedef long __kernel_off_t; | ||
| 24 | typedef int __kernel_pid_t; | ||
| 25 | typedef unsigned short __kernel_ipc_pid_t; | ||
| 26 | typedef unsigned short __kernel_uid_t; | ||
| 27 | typedef unsigned short __kernel_gid_t; | ||
| 28 | typedef unsigned long __kernel_size_t; | ||
| 29 | typedef long __kernel_ssize_t; | ||
| 30 | typedef int __kernel_ptrdiff_t; | ||
| 31 | typedef long __kernel_time_t; | ||
| 32 | typedef long __kernel_suseconds_t; | ||
| 33 | typedef long __kernel_clock_t; | ||
| 34 | typedef int __kernel_timer_t; | ||
| 35 | typedef int __kernel_clockid_t; | ||
| 36 | typedef int __kernel_daddr_t; | ||
| 37 | typedef char * __kernel_caddr_t; | ||
| 38 | typedef unsigned short __kernel_uid16_t; | ||
| 39 | typedef unsigned short __kernel_gid16_t; | ||
| 40 | typedef unsigned int __kernel_uid32_t; | ||
| 41 | typedef unsigned int __kernel_gid32_t; | ||
| 42 | |||
| 43 | typedef unsigned short __kernel_old_uid_t; | ||
| 44 | typedef unsigned short __kernel_old_gid_t; | ||
| 45 | typedef unsigned short __kernel_old_dev_t; | ||
| 46 | |||
| 47 | #ifdef __GNUC__ | ||
| 48 | typedef long long __kernel_loff_t; | ||
| 49 | #endif | ||
| 50 | |||
| 51 | typedef struct { | ||
| 52 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 53 | int val[2]; | ||
| 54 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 55 | int __val[2]; | ||
| 56 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 57 | } __kernel_fsid_t; | ||
| 58 | |||
| 59 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | ||
| 60 | |||
| 61 | #undef __FD_SET | ||
| 62 | static inline void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) | ||
| 63 | { | ||
| 64 | unsigned long __tmp = __fd / __NFDBITS; | ||
| 65 | unsigned long __rem = __fd % __NFDBITS; | ||
| 66 | __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); | ||
| 67 | } | ||
| 68 | |||
| 69 | #undef __FD_CLR | ||
| 70 | static inline void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) | ||
| 71 | { | ||
| 72 | unsigned long __tmp = __fd / __NFDBITS; | ||
| 73 | unsigned long __rem = __fd % __NFDBITS; | ||
| 74 | __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); | ||
| 75 | } | ||
| 76 | |||
| 77 | |||
| 78 | #undef __FD_ISSET | ||
| 79 | static inline int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) | ||
| 80 | { | ||
| 81 | unsigned long __tmp = __fd / __NFDBITS; | ||
| 82 | unsigned long __rem = __fd % __NFDBITS; | ||
| 83 | return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; | ||
| 84 | } | ||
| 85 | |||
| 86 | /* | ||
| 87 | * This will unroll the loop for the normal constant case (8 ints, | ||
| 88 | * for a 256-bit fd_set) | ||
| 89 | */ | ||
| 90 | #undef __FD_ZERO | ||
| 91 | static inline void __FD_ZERO(__kernel_fd_set *__p) | ||
| 92 | { | ||
| 93 | unsigned long *__tmp = __p->fds_bits; | ||
| 94 | int __i; | ||
| 95 | |||
| 96 | if (__builtin_constant_p(__FDSET_LONGS)) { | ||
| 97 | switch (__FDSET_LONGS) { | ||
| 98 | case 16: | ||
| 99 | __tmp[ 0] = 0; __tmp[ 1] = 0; | ||
| 100 | __tmp[ 2] = 0; __tmp[ 3] = 0; | ||
| 101 | __tmp[ 4] = 0; __tmp[ 5] = 0; | ||
| 102 | __tmp[ 6] = 0; __tmp[ 7] = 0; | ||
| 103 | __tmp[ 8] = 0; __tmp[ 9] = 0; | ||
| 104 | __tmp[10] = 0; __tmp[11] = 0; | ||
| 105 | __tmp[12] = 0; __tmp[13] = 0; | ||
| 106 | __tmp[14] = 0; __tmp[15] = 0; | ||
| 107 | return; | ||
| 108 | |||
| 109 | case 8: | ||
| 110 | __tmp[ 0] = 0; __tmp[ 1] = 0; | ||
| 111 | __tmp[ 2] = 0; __tmp[ 3] = 0; | ||
| 112 | __tmp[ 4] = 0; __tmp[ 5] = 0; | ||
| 113 | __tmp[ 6] = 0; __tmp[ 7] = 0; | ||
| 114 | return; | ||
| 115 | |||
| 116 | case 4: | ||
| 117 | __tmp[ 0] = 0; __tmp[ 1] = 0; | ||
| 118 | __tmp[ 2] = 0; __tmp[ 3] = 0; | ||
| 119 | return; | ||
| 120 | } | ||
| 121 | } | ||
| 122 | __i = __FDSET_LONGS; | ||
| 123 | while (__i) { | ||
| 124 | __i--; | ||
| 125 | *__tmp = 0; | ||
| 126 | __tmp++; | ||
| 127 | } | ||
| 128 | } | ||
| 129 | |||
| 130 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | ||
| 131 | |||
| 132 | #endif /* _ASM_POSIX_TYPES_H */ | ||
diff --git a/include/asm-mn10300/proc-mn103e010/cache.h b/include/asm-mn10300/proc-mn103e010/cache.h new file mode 100644 index 000000000000..bdc1f9a59b4c --- /dev/null +++ b/include/asm-mn10300/proc-mn103e010/cache.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /* MN103E010 Cache specification | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_PROC_CACHE_H | ||
| 12 | #define _ASM_PROC_CACHE_H | ||
| 13 | |||
| 14 | /* L1 cache */ | ||
| 15 | |||
| 16 | #define L1_CACHE_NWAYS 4 /* number of ways in caches */ | ||
| 17 | #define L1_CACHE_NENTRIES 256 /* number of entries in each way */ | ||
| 18 | #define L1_CACHE_BYTES 16 /* bytes per entry */ | ||
| 19 | #define L1_CACHE_SHIFT 4 /* shift for bytes per entry */ | ||
| 20 | #define L1_CACHE_WAYDISP 0x1000 /* displacement of one way from the next */ | ||
| 21 | |||
| 22 | #define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */ | ||
| 23 | #define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ | ||
| 24 | #define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */ | ||
| 25 | #define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ | ||
| 26 | |||
| 27 | /* | ||
| 28 | * specification of the interval between interrupt checking intervals whilst | ||
| 29 | * managing the cache with the interrupts disabled | ||
| 30 | */ | ||
| 31 | #define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4 | ||
| 32 | |||
| 33 | #endif /* _ASM_PROC_CACHE_H */ | ||
diff --git a/include/asm-mn10300/proc-mn103e010/clock.h b/include/asm-mn10300/proc-mn103e010/clock.h new file mode 100644 index 000000000000..caf998350633 --- /dev/null +++ b/include/asm-mn10300/proc-mn103e010/clock.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* MN103E010-specific clocks | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_PROC_CLOCK_H | ||
| 12 | #define _ASM_PROC_CLOCK_H | ||
| 13 | |||
| 14 | #include <asm/unit/clock.h> | ||
| 15 | |||
| 16 | #define MN10300_WDCLK MN10300_IOCLK | ||
| 17 | |||
| 18 | #endif /* _ASM_PROC_CLOCK_H */ | ||
diff --git a/include/asm-mn10300/proc-mn103e010/irq.h b/include/asm-mn10300/proc-mn103e010/irq.h new file mode 100644 index 000000000000..aa6ee8f98b1b --- /dev/null +++ b/include/asm-mn10300/proc-mn103e010/irq.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* MN103E010 On-board interrupt controller numbers | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_PROC_IRQ_H | ||
| 13 | #define _ASM_PROC_IRQ_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #define GxICR_NUM_IRQS 42 | ||
| 18 | |||
| 19 | #define GxICR_NUM_XIRQS 8 | ||
| 20 | |||
| 21 | #define XIRQ0 34 | ||
| 22 | #define XIRQ1 35 | ||
| 23 | #define XIRQ2 36 | ||
| 24 | #define XIRQ3 37 | ||
| 25 | #define XIRQ4 38 | ||
| 26 | #define XIRQ5 39 | ||
| 27 | #define XIRQ6 40 | ||
| 28 | #define XIRQ7 41 | ||
| 29 | |||
| 30 | #define XIRQ2IRQ(num) (XIRQ0 + num) | ||
| 31 | |||
| 32 | #endif /* __KERNEL__ */ | ||
| 33 | |||
| 34 | #endif /* _ASM_PROC_IRQ_H */ | ||
diff --git a/include/asm-mn10300/proc-mn103e010/proc.h b/include/asm-mn10300/proc-mn103e010/proc.h new file mode 100644 index 000000000000..22a2b93f70b7 --- /dev/null +++ b/include/asm-mn10300/proc-mn103e010/proc.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* MN103E010 Processor description | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_PROC_PROC_H | ||
| 13 | #define _ASM_PROC_PROC_H | ||
| 14 | |||
| 15 | #define PROCESSOR_VENDOR_NAME "Matsushita" | ||
| 16 | #define PROCESSOR_MODEL_NAME "mn103e010" | ||
| 17 | |||
| 18 | #endif /* _ASM_PROC_PROC_H */ | ||
diff --git a/include/asm-mn10300/processor.h b/include/asm-mn10300/processor.h new file mode 100644 index 000000000000..f1b081f53468 --- /dev/null +++ b/include/asm-mn10300/processor.h | |||
| @@ -0,0 +1,186 @@ | |||
| 1 | /* MN10300 Processor specifics | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * Written by David Howells (dhowells@redhat.com) | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef _ASM_PROCESSOR_H | ||
| 14 | #define _ASM_PROCESSOR_H | ||
| 15 | |||
| 16 | #include <asm/page.h> | ||
| 17 | #include <asm/ptrace.h> | ||
| 18 | #include <asm/cpu-regs.h> | ||
| 19 | #include <linux/threads.h> | ||
| 20 | |||
| 21 | /* Forward declaration, a strange C thing */ | ||
| 22 | struct task_struct; | ||
| 23 | struct mm_struct; | ||
| 24 | |||
| 25 | /* | ||
| 26 | * Default implementation of macro that returns current | ||
| 27 | * instruction pointer ("program counter"). | ||
| 28 | */ | ||
| 29 | #define current_text_addr() \ | ||
| 30 | ({ \ | ||
| 31 | void *__pc; \ | ||
| 32 | asm("mov pc,%0" : "=a"(__pc)); \ | ||
| 33 | __pc; \ | ||
| 34 | }) | ||
| 35 | |||
| 36 | extern void show_registers(struct pt_regs *regs); | ||
| 37 | |||
| 38 | /* | ||
| 39 | * CPU type and hardware bug flags. Kept separately for each CPU. | ||
| 40 | * Members of this structure are referenced in head.S, so think twice | ||
| 41 | * before touching them. [mj] | ||
| 42 | */ | ||
| 43 | |||
| 44 | struct mn10300_cpuinfo { | ||
| 45 | int type; | ||
| 46 | unsigned long loops_per_sec; | ||
| 47 | char hard_math; | ||
| 48 | unsigned long *pgd_quick; | ||
| 49 | unsigned long *pte_quick; | ||
| 50 | unsigned long pgtable_cache_sz; | ||
| 51 | }; | ||
| 52 | |||
| 53 | extern struct mn10300_cpuinfo boot_cpu_data; | ||
| 54 | |||
| 55 | #define cpu_data &boot_cpu_data | ||
| 56 | #define current_cpu_data boot_cpu_data | ||
| 57 | |||
| 58 | extern void identify_cpu(struct mn10300_cpuinfo *); | ||
| 59 | extern void print_cpu_info(struct mn10300_cpuinfo *); | ||
| 60 | extern void dodgy_tsc(void); | ||
| 61 | #define cpu_relax() do {} while (0) | ||
| 62 | |||
| 63 | /* | ||
| 64 | * User space process size: 1.75GB (default). | ||
| 65 | */ | ||
| 66 | #define TASK_SIZE 0x70000000 | ||
| 67 | |||
| 68 | /* | ||
| 69 | * Where to put the userspace stack by default | ||
| 70 | */ | ||
| 71 | #define STACK_TOP 0x70000000 | ||
| 72 | #define STACK_TOP_MAX STACK_TOP | ||
| 73 | |||
| 74 | /* This decides where the kernel will search for a free chunk of vm | ||
| 75 | * space during mmap's. | ||
| 76 | */ | ||
| 77 | #define TASK_UNMAPPED_BASE 0x30000000 | ||
| 78 | |||
| 79 | typedef struct { | ||
| 80 | unsigned long seg; | ||
| 81 | } mm_segment_t; | ||
| 82 | |||
| 83 | struct fpu_state_struct { | ||
| 84 | unsigned long fs[32]; /* fpu registers */ | ||
| 85 | unsigned long fpcr; /* fpu control register */ | ||
| 86 | }; | ||
| 87 | |||
| 88 | struct thread_struct { | ||
| 89 | struct pt_regs *uregs; /* userspace register frame */ | ||
| 90 | unsigned long pc; /* kernel PC */ | ||
| 91 | unsigned long sp; /* kernel SP */ | ||
| 92 | unsigned long a3; /* kernel FP */ | ||
| 93 | unsigned long wchan; | ||
| 94 | unsigned long usp; | ||
| 95 | struct pt_regs *__frame; | ||
| 96 | unsigned long fpu_flags; | ||
| 97 | #define THREAD_USING_FPU 0x00000001 /* T if this task is using the FPU */ | ||
| 98 | struct fpu_state_struct fpu_state; | ||
| 99 | }; | ||
| 100 | |||
| 101 | #define INIT_THREAD \ | ||
| 102 | { \ | ||
| 103 | .uregs = init_uregs, \ | ||
| 104 | .pc = 0, \ | ||
| 105 | .sp = 0, \ | ||
| 106 | .a3 = 0, \ | ||
| 107 | .wchan = 0, \ | ||
| 108 | .__frame = NULL, \ | ||
| 109 | } | ||
| 110 | |||
| 111 | #define INIT_MMAP \ | ||
| 112 | { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, \ | ||
| 113 | NULL, NULL } | ||
| 114 | |||
| 115 | /* | ||
| 116 | * do necessary setup to start up a newly executed thread | ||
| 117 | * - need to discard the frame stacked by the kernel thread invoking the execve | ||
| 118 | * syscall (see RESTORE_ALL macro) | ||
| 119 | */ | ||
| 120 | #define start_thread(regs, new_pc, new_sp) do { \ | ||
| 121 | set_fs(USER_DS); \ | ||
| 122 | __frame = current->thread.uregs; \ | ||
| 123 | __frame->epsw = EPSW_nSL | EPSW_IE | EPSW_IM; \ | ||
| 124 | __frame->pc = new_pc; \ | ||
| 125 | __frame->sp = new_sp; \ | ||
| 126 | } while (0) | ||
| 127 | |||
| 128 | /* Free all resources held by a thread. */ | ||
| 129 | extern void release_thread(struct task_struct *); | ||
| 130 | |||
| 131 | /* Prepare to copy thread state - unlazy all lazy status */ | ||
| 132 | extern void prepare_to_copy(struct task_struct *tsk); | ||
| 133 | |||
| 134 | /* | ||
| 135 | * create a kernel thread without removing it from tasklists | ||
| 136 | */ | ||
| 137 | extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); | ||
| 138 | |||
| 139 | /* | ||
| 140 | * Return saved PC of a blocked thread. | ||
| 141 | */ | ||
| 142 | extern unsigned long thread_saved_pc(struct task_struct *tsk); | ||
| 143 | |||
| 144 | unsigned long get_wchan(struct task_struct *p); | ||
| 145 | |||
| 146 | #define task_pt_regs(task) \ | ||
| 147 | ({ \ | ||
| 148 | struct pt_regs *__regs__; \ | ||
| 149 | __regs__ = (struct pt_regs *) (KSTK_TOP(task_stack_page(task)) - 8); \ | ||
| 150 | __regs__ - 1; \ | ||
| 151 | }) | ||
| 152 | |||
| 153 | #define KSTK_EIP(task) (task_pt_regs(task)->pc) | ||
| 154 | #define KSTK_ESP(task) (task_pt_regs(task)->sp) | ||
| 155 | |||
| 156 | #define KSTK_TOP(info) \ | ||
| 157 | ({ \ | ||
| 158 | (unsigned long)(info) + THREAD_SIZE; \ | ||
| 159 | }) | ||
| 160 | |||
| 161 | #define ARCH_HAS_PREFETCH | ||
| 162 | #define ARCH_HAS_PREFETCHW | ||
| 163 | |||
| 164 | static inline void prefetch(const void *x) | ||
| 165 | { | ||
| 166 | #ifndef CONFIG_MN10300_CACHE_DISABLED | ||
| 167 | #ifdef CONFIG_MN10300_PROC_MN103E010 | ||
| 168 | asm volatile ("nop; nop; dcpf (%0)" : : "r"(x)); | ||
| 169 | #else | ||
| 170 | asm volatile ("dcpf (%0)" : : "r"(x)); | ||
| 171 | #endif | ||
| 172 | #endif | ||
| 173 | } | ||
| 174 | |||
| 175 | static inline void prefetchw(const void *x) | ||
| 176 | { | ||
| 177 | #ifndef CONFIG_MN10300_CACHE_DISABLED | ||
| 178 | #ifdef CONFIG_MN10300_PROC_MN103E010 | ||
| 179 | asm volatile ("nop; nop; dcpf (%0)" : : "r"(x)); | ||
| 180 | #else | ||
| 181 | asm volatile ("dcpf (%0)" : : "r"(x)); | ||
| 182 | #endif | ||
| 183 | #endif | ||
| 184 | } | ||
| 185 | |||
| 186 | #endif /* _ASM_PROCESSOR_H */ | ||
diff --git a/include/asm-mn10300/ptrace.h b/include/asm-mn10300/ptrace.h new file mode 100644 index 000000000000..b3684689fcce --- /dev/null +++ b/include/asm-mn10300/ptrace.h | |||
| @@ -0,0 +1,99 @@ | |||
| 1 | /* MN10300 Exception frame layout and ptrace constants | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_PTRACE_H | ||
| 12 | #define _ASM_PTRACE_H | ||
| 13 | |||
| 14 | #define PT_A3 0 | ||
| 15 | #define PT_A2 1 | ||
| 16 | #define PT_D3 2 | ||
| 17 | #define PT_D2 3 | ||
| 18 | #define PT_MCVF 4 | ||
| 19 | #define PT_MCRL 5 | ||
| 20 | #define PT_MCRH 6 | ||
| 21 | #define PT_MDRQ 7 | ||
| 22 | #define PT_E1 8 | ||
| 23 | #define PT_E0 9 | ||
| 24 | #define PT_E7 10 | ||
| 25 | #define PT_E6 11 | ||
| 26 | #define PT_E5 12 | ||
| 27 | #define PT_E4 13 | ||
| 28 | #define PT_E3 14 | ||
| 29 | #define PT_E2 15 | ||
| 30 | #define PT_SP 16 | ||
| 31 | #define PT_LAR 17 | ||
| 32 | #define PT_LIR 18 | ||
| 33 | #define PT_MDR 19 | ||
| 34 | #define PT_A1 20 | ||
| 35 | #define PT_A0 21 | ||
| 36 | #define PT_D1 22 | ||
| 37 | #define PT_D0 23 | ||
| 38 | #define PT_ORIG_D0 24 | ||
| 39 | #define PT_EPSW 25 | ||
| 40 | #define PT_PC 26 | ||
| 41 | #define NR_PTREGS 27 | ||
| 42 | |||
| 43 | #ifndef __ASSEMBLY__ | ||
| 44 | /* | ||
| 45 | * This defines the way registers are stored in the event of an exception | ||
| 46 | * - the strange order is due to the MOVM instruction | ||
| 47 | */ | ||
| 48 | struct pt_regs { | ||
| 49 | unsigned long a3; /* syscall arg 3 */ | ||
| 50 | unsigned long a2; /* syscall arg 4 */ | ||
| 51 | unsigned long d3; /* syscall arg 5 */ | ||
| 52 | unsigned long d2; /* syscall arg 6 */ | ||
| 53 | unsigned long mcvf; | ||
| 54 | unsigned long mcrl; | ||
| 55 | unsigned long mcrh; | ||
| 56 | unsigned long mdrq; | ||
| 57 | unsigned long e1; | ||
| 58 | unsigned long e0; | ||
| 59 | unsigned long e7; | ||
| 60 | unsigned long e6; | ||
| 61 | unsigned long e5; | ||
| 62 | unsigned long e4; | ||
| 63 | unsigned long e3; | ||
| 64 | unsigned long e2; | ||
| 65 | unsigned long sp; | ||
| 66 | unsigned long lar; | ||
| 67 | unsigned long lir; | ||
| 68 | unsigned long mdr; | ||
| 69 | unsigned long a1; | ||
| 70 | unsigned long a0; /* syscall arg 1 */ | ||
| 71 | unsigned long d1; /* syscall arg 2 */ | ||
| 72 | unsigned long d0; /* syscall ret */ | ||
| 73 | struct pt_regs *next; /* next frame pointer */ | ||
| 74 | unsigned long orig_d0; /* syscall number */ | ||
| 75 | unsigned long epsw; | ||
| 76 | unsigned long pc; | ||
| 77 | }; | ||
| 78 | #endif | ||
| 79 | |||
| 80 | extern struct pt_regs *__frame; /* current frame pointer */ | ||
| 81 | |||
| 82 | /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ | ||
| 83 | #define PTRACE_GETREGS 12 | ||
| 84 | #define PTRACE_SETREGS 13 | ||
| 85 | #define PTRACE_GETFPREGS 14 | ||
| 86 | #define PTRACE_SETFPREGS 15 | ||
| 87 | |||
| 88 | /* options set using PTRACE_SETOPTIONS */ | ||
| 89 | #define PTRACE_O_TRACESYSGOOD 0x00000001 | ||
| 90 | |||
| 91 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) | ||
| 92 | #define user_mode(regs) (((regs)->epsw & EPSW_nSL) == EPSW_nSL) | ||
| 93 | #define instruction_pointer(regs) ((regs)->pc) | ||
| 94 | extern void show_regs(struct pt_regs *); | ||
| 95 | #endif | ||
| 96 | |||
| 97 | #define profile_pc(regs) ((regs)->pc) | ||
| 98 | |||
| 99 | #endif /* _ASM_PTRACE_H */ | ||
diff --git a/include/asm-mn10300/reset-regs.h b/include/asm-mn10300/reset-regs.h new file mode 100644 index 000000000000..174523d50132 --- /dev/null +++ b/include/asm-mn10300/reset-regs.h | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /* MN10300 Reset controller and watchdog timer definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_RESET_REGS_H | ||
| 13 | #define _ASM_RESET_REGS_H | ||
| 14 | |||
| 15 | #include <asm/cpu-regs.h> | ||
| 16 | #include <asm/exceptions.h> | ||
| 17 | |||
| 18 | #ifdef __KERNEL__ | ||
| 19 | |||
| 20 | #ifdef CONFIG_MN10300_WD_TIMER | ||
| 21 | #define ARCH_HAS_NMI_WATCHDOG /* See include/linux/nmi.h */ | ||
| 22 | #endif | ||
| 23 | |||
| 24 | /* | ||
| 25 | * watchdog timer registers | ||
| 26 | */ | ||
| 27 | #define WDBC __SYSREGC(0xc0001000, u8) /* watchdog binary counter reg */ | ||
| 28 | |||
| 29 | #define WDCTR __SYSREG(0xc0001002, u8) /* watchdog timer control reg */ | ||
| 30 | #define WDCTR_WDCK 0x07 /* clock source selection */ | ||
| 31 | #define WDCTR_WDCK_256th 0x00 /* - OSCI/256 */ | ||
| 32 | #define WDCTR_WDCK_1024th 0x01 /* - OSCI/1024 */ | ||
| 33 | #define WDCTR_WDCK_2048th 0x02 /* - OSCI/2048 */ | ||
| 34 | #define WDCTR_WDCK_16384th 0x03 /* - OSCI/16384 */ | ||
| 35 | #define WDCTR_WDCK_65536th 0x04 /* - OSCI/65536 */ | ||
| 36 | #define WDCTR_WDRST 0x40 /* binary counter reset */ | ||
| 37 | #define WDCTR_WDCNE 0x80 /* watchdog timer enable */ | ||
| 38 | |||
| 39 | #define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */ | ||
| 40 | #define RSTCTR_CHIPRST 0x01 /* chip reset */ | ||
| 41 | #define RSTCTR_DBFRST 0x02 /* double fault reset flag */ | ||
| 42 | #define RSTCTR_WDTRST 0x04 /* watchdog timer reset flag */ | ||
| 43 | #define RSTCTR_WDREN 0x08 /* watchdog timer reset enable */ | ||
| 44 | |||
| 45 | #ifndef __ASSEMBLY__ | ||
| 46 | |||
| 47 | static inline void mn10300_proc_hard_reset(void) | ||
| 48 | { | ||
| 49 | RSTCTR &= ~RSTCTR_CHIPRST; | ||
| 50 | RSTCTR |= RSTCTR_CHIPRST; | ||
| 51 | } | ||
| 52 | |||
| 53 | extern unsigned int watchdog_alert_counter; | ||
| 54 | |||
| 55 | extern void watchdog_go(void); | ||
| 56 | extern asmlinkage void watchdog_handler(void); | ||
| 57 | extern asmlinkage | ||
| 58 | void watchdog_interrupt(struct pt_regs *, enum exception_code); | ||
| 59 | |||
| 60 | #endif | ||
| 61 | |||
| 62 | #endif /* __KERNEL__ */ | ||
| 63 | |||
| 64 | #endif /* _ASM_RESET_REGS_H */ | ||
diff --git a/include/asm-mn10300/resource.h b/include/asm-mn10300/resource.h new file mode 100644 index 000000000000..04bc4db8921b --- /dev/null +++ b/include/asm-mn10300/resource.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/resource.h> | |||
diff --git a/include/asm-mn10300/rtc-regs.h b/include/asm-mn10300/rtc-regs.h new file mode 100644 index 000000000000..c42deefaec11 --- /dev/null +++ b/include/asm-mn10300/rtc-regs.h | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | /* MN10300 on-chip Real-Time Clock registers | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_RTC_REGS_H | ||
| 12 | #define _ASM_RTC_REGS_H | ||
| 13 | |||
| 14 | #include <asm/intctl-regs.h> | ||
| 15 | |||
| 16 | #ifdef __KERNEL__ | ||
| 17 | |||
| 18 | #define RTSCR __SYSREG(0xd8600000, u8) /* RTC seconds count reg */ | ||
| 19 | #define RTSAR __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */ | ||
| 20 | #define RTMCR __SYSREG(0xd8600002, u8) /* RTC minutes count reg */ | ||
| 21 | #define RTMAR __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */ | ||
| 22 | #define RTHCR __SYSREG(0xd8600004, u8) /* RTC hours count reg */ | ||
| 23 | #define RTHAR __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */ | ||
| 24 | #define RTDWCR __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */ | ||
| 25 | #define RTDMCR __SYSREG(0xd8600007, u8) /* RTC days count reg */ | ||
| 26 | #define RTMTCR __SYSREG(0xd8600008, u8) /* RTC months count reg */ | ||
| 27 | #define RTYCR __SYSREG(0xd8600009, u8) /* RTC years count reg */ | ||
| 28 | |||
| 29 | #define RTCRA __SYSREG(0xd860000a, u8)/* RTC control reg A */ | ||
| 30 | #define RTCRA_RS 0x0f /* periodic timer interrupt cycle setting */ | ||
| 31 | #define RTCRA_RS_NONE 0x00 /* - off */ | ||
| 32 | #define RTCRA_RS_3_90625ms 0x01 /* - 3.90625ms (1/256s) */ | ||
| 33 | #define RTCRA_RS_7_8125ms 0x02 /* - 7.8125ms (1/128s) */ | ||
| 34 | #define RTCRA_RS_122_070us 0x03 /* - 122.070us (1/8192s) */ | ||
| 35 | #define RTCRA_RS_244_141us 0x04 /* - 244.141us (1/4096s) */ | ||
| 36 | #define RTCRA_RS_488_281us 0x05 /* - 488.281us (1/2048s) */ | ||
| 37 | #define RTCRA_RS_976_5625us 0x06 /* - 976.5625us (1/1024s) */ | ||
| 38 | #define RTCRA_RS_1_953125ms 0x07 /* - 1.953125ms (1/512s) */ | ||
| 39 | #define RTCRA_RS_3_90624ms 0x08 /* - 3.90624ms (1/256s) */ | ||
| 40 | #define RTCRA_RS_7_8125ms_b 0x09 /* - 7.8125ms (1/128s) */ | ||
| 41 | #define RTCRA_RS_15_625ms 0x0a /* - 15.625ms (1/64s) */ | ||
| 42 | #define RTCRA_RS_31_25ms 0x0b /* - 31.25ms (1/32s) */ | ||
| 43 | #define RTCRA_RS_62_5ms 0x0c /* - 62.5ms (1/16s) */ | ||
| 44 | #define RTCRA_RS_125ms 0x0d /* - 125ms (1/8s) */ | ||
| 45 | #define RTCRA_RS_250ms 0x0e /* - 250ms (1/4s) */ | ||
| 46 | #define RTCRA_RS_500ms 0x0f /* - 500ms (1/2s) */ | ||
| 47 | #define RTCRA_DVR 0x40 /* divider reset */ | ||
| 48 | #define RTCRA_UIP 0x80 /* clock update flag */ | ||
| 49 | |||
| 50 | #define RTCRB __SYSREG(0xd860000b, u8) /* RTC control reg B */ | ||
| 51 | #define RTCRB_DSE 0x01 /* daylight savings time enable */ | ||
| 52 | #define RTCRB_TM 0x02 /* time format */ | ||
| 53 | #define RTCRB_TM_12HR 0x00 /* - 12 hour format */ | ||
| 54 | #define RTCRB_TM_24HR 0x02 /* - 24 hour format */ | ||
| 55 | #define RTCRB_DM 0x04 /* numeric value format */ | ||
| 56 | #define RTCRB_DM_BCD 0x00 /* - BCD */ | ||
| 57 | #define RTCRB_DM_BINARY 0x04 /* - binary */ | ||
| 58 | #define RTCRB_UIE 0x10 /* update interrupt disable */ | ||
| 59 | #define RTCRB_AIE 0x20 /* alarm interrupt disable */ | ||
| 60 | #define RTCRB_PIE 0x40 /* periodic interrupt disable */ | ||
| 61 | #define RTCRB_SET 0x80 /* clock update enable */ | ||
| 62 | |||
| 63 | #define RTSRC __SYSREG(0xd860000c, u8) /* RTC status reg C */ | ||
| 64 | #define RTSRC_UF 0x10 /* update end interrupt flag */ | ||
| 65 | #define RTSRC_AF 0x20 /* alarm interrupt flag */ | ||
| 66 | #define RTSRC_PF 0x40 /* periodic interrupt flag */ | ||
| 67 | #define RTSRC_IRQF 0x80 /* interrupt flag */ | ||
| 68 | |||
| 69 | #define RTIRQ 32 | ||
| 70 | #define RTICR GxICR(RTIRQ) | ||
| 71 | |||
| 72 | /* | ||
| 73 | * MC146818 RTC compatibility defs for the MN10300 on-chip RTC | ||
| 74 | */ | ||
| 75 | #define RTC_PORT(x) 0xd8600000 | ||
| 76 | #define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ | ||
| 77 | |||
| 78 | #define CMOS_READ(addr) __SYSREG(0xd8600000 + (addr), u8) | ||
| 79 | #define CMOS_WRITE(val, addr) \ | ||
| 80 | do { __SYSREG(0xd8600000 + (addr), u8) = val; } while (0) | ||
| 81 | |||
| 82 | #define RTC_IRQ RTIRQ | ||
| 83 | |||
| 84 | #endif /* __KERNEL__ */ | ||
| 85 | |||
| 86 | #endif /* _ASM_RTC_REGS_H */ | ||
diff --git a/include/asm-mn10300/rtc.h b/include/asm-mn10300/rtc.h new file mode 100644 index 000000000000..c295194cc703 --- /dev/null +++ b/include/asm-mn10300/rtc.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* MN10300 Real time clock definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_RTC_H | ||
| 12 | #define _ASM_RTC_H | ||
| 13 | |||
| 14 | #ifdef CONFIG_MN10300_RTC | ||
| 15 | |||
| 16 | #include <linux/init.h> | ||
| 17 | |||
| 18 | extern void check_rtc_time(void); | ||
| 19 | extern void __init calibrate_clock(void); | ||
| 20 | extern unsigned long __init get_initial_rtc_time(void); | ||
| 21 | |||
| 22 | #else /* !CONFIG_MN10300_RTC */ | ||
| 23 | |||
| 24 | static inline void check_rtc_time(void) | ||
| 25 | { | ||
| 26 | } | ||
| 27 | |||
| 28 | static inline void calibrate_clock(void) | ||
| 29 | { | ||
| 30 | } | ||
| 31 | |||
| 32 | static inline unsigned long get_initial_rtc_time(void) | ||
| 33 | { | ||
| 34 | return 0; | ||
| 35 | } | ||
| 36 | |||
| 37 | #endif /* !CONFIG_MN10300_RTC */ | ||
| 38 | |||
| 39 | #include <asm-generic/rtc.h> | ||
| 40 | |||
| 41 | #endif /* _ASM_RTC_H */ | ||
diff --git a/include/asm-mn10300/scatterlist.h b/include/asm-mn10300/scatterlist.h new file mode 100644 index 000000000000..e29d91dbcf2b --- /dev/null +++ b/include/asm-mn10300/scatterlist.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /* MN10300 Scatterlist definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_SCATTERLIST_H | ||
| 12 | #define _ASM_SCATTERLIST_H | ||
| 13 | |||
| 14 | #include <asm/types.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Drivers must set either ->address or (preferred) page and ->offset | ||
| 18 | * to indicate where data must be transferred to/from. | ||
| 19 | * | ||
| 20 | * Using page is recommended since it handles highmem data as well as | ||
| 21 | * low mem. ->address is restricted to data which has a virtual mapping, and | ||
| 22 | * it will go away in the future. Updating to page can be automated very | ||
| 23 | * easily -- something like | ||
| 24 | * | ||
| 25 | * sg->address = some_ptr; | ||
| 26 | * | ||
| 27 | * can be rewritten as | ||
| 28 | * | ||
| 29 | * sg_set_page(virt_to_page(some_ptr)); | ||
| 30 | * sg->offset = (unsigned long) some_ptr & ~PAGE_MASK; | ||
| 31 | * | ||
| 32 | * and that's it. There's no excuse for not highmem enabling YOUR driver. /jens | ||
| 33 | */ | ||
| 34 | struct scatterlist { | ||
| 35 | #ifdef CONFIG_DEBUG_SG | ||
| 36 | unsigned long sg_magic; | ||
| 37 | #endif | ||
| 38 | unsigned long page_link; | ||
| 39 | unsigned int offset; /* for highmem, page offset */ | ||
| 40 | dma_addr_t dma_address; | ||
| 41 | unsigned int length; | ||
| 42 | }; | ||
| 43 | |||
| 44 | #define ISA_DMA_THRESHOLD (0x00ffffff) | ||
| 45 | |||
| 46 | #endif /* _ASM_SCATTERLIST_H */ | ||
diff --git a/include/asm-mn10300/sections.h b/include/asm-mn10300/sections.h new file mode 100644 index 000000000000..2b8c5160388f --- /dev/null +++ b/include/asm-mn10300/sections.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/sections.h> | |||
diff --git a/include/asm-mn10300/semaphore.h b/include/asm-mn10300/semaphore.h new file mode 100644 index 000000000000..5a9e1ad0b253 --- /dev/null +++ b/include/asm-mn10300/semaphore.h | |||
| @@ -0,0 +1,169 @@ | |||
| 1 | /* MN10300 Semaphores | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_SEMAPHORE_H | ||
| 12 | #define _ASM_SEMAPHORE_H | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | |||
| 16 | #include <linux/linkage.h> | ||
| 17 | #include <linux/wait.h> | ||
| 18 | #include <linux/spinlock.h> | ||
| 19 | #include <linux/rwsem.h> | ||
| 20 | |||
| 21 | #define SEMAPHORE_DEBUG 0 | ||
| 22 | |||
| 23 | /* | ||
| 24 | * the semaphore definition | ||
| 25 | * - if count is >0 then there are tokens available on the semaphore for down | ||
| 26 | * to collect | ||
| 27 | * - if count is <=0 then there are no spare tokens, and anyone that wants one | ||
| 28 | * must wait | ||
| 29 | * - if wait_list is not empty, then there are processes waiting for the | ||
| 30 | * semaphore | ||
| 31 | */ | ||
| 32 | struct semaphore { | ||
| 33 | atomic_t count; /* it's not really atomic, it's | ||
| 34 | * just that certain modules | ||
| 35 | * expect to be able to access | ||
| 36 | * it directly */ | ||
| 37 | spinlock_t wait_lock; | ||
| 38 | struct list_head wait_list; | ||
| 39 | #if SEMAPHORE_DEBUG | ||
| 40 | unsigned __magic; | ||
| 41 | #endif | ||
| 42 | }; | ||
| 43 | |||
| 44 | #if SEMAPHORE_DEBUG | ||
| 45 | # define __SEM_DEBUG_INIT(name) , (long)&(name).__magic | ||
| 46 | #else | ||
| 47 | # define __SEM_DEBUG_INIT(name) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | |||
| 51 | #define __SEMAPHORE_INITIALIZER(name, init_count) \ | ||
| 52 | { \ | ||
| 53 | .count = ATOMIC_INIT(init_count), \ | ||
| 54 | .wait_lock = __SPIN_LOCK_UNLOCKED((name).wait_lock), \ | ||
| 55 | .wait_list = LIST_HEAD_INIT((name).wait_list) \ | ||
| 56 | __SEM_DEBUG_INIT(name) \ | ||
| 57 | } | ||
| 58 | |||
| 59 | #define __DECLARE_SEMAPHORE_GENERIC(name,count) \ | ||
| 60 | struct semaphore name = __SEMAPHORE_INITIALIZER(name, count) | ||
| 61 | |||
| 62 | #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) | ||
| 63 | #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0) | ||
| 64 | |||
| 65 | static inline void sema_init(struct semaphore *sem, int val) | ||
| 66 | { | ||
| 67 | *sem = (struct semaphore) __SEMAPHORE_INITIALIZER(*sem, val); | ||
| 68 | } | ||
| 69 | |||
| 70 | static inline void init_MUTEX(struct semaphore *sem) | ||
| 71 | { | ||
| 72 | sema_init(sem, 1); | ||
| 73 | } | ||
| 74 | |||
| 75 | static inline void init_MUTEX_LOCKED(struct semaphore *sem) | ||
| 76 | { | ||
| 77 | sema_init(sem, 0); | ||
| 78 | } | ||
| 79 | |||
| 80 | extern void __down(struct semaphore *sem, unsigned long flags); | ||
| 81 | extern int __down_interruptible(struct semaphore *sem, unsigned long flags); | ||
| 82 | extern void __up(struct semaphore *sem); | ||
| 83 | |||
| 84 | static inline void down(struct semaphore *sem) | ||
| 85 | { | ||
| 86 | unsigned long flags; | ||
| 87 | int count; | ||
| 88 | |||
| 89 | #if SEMAPHORE_DEBUG | ||
| 90 | CHECK_MAGIC(sem->__magic); | ||
| 91 | #endif | ||
| 92 | |||
| 93 | spin_lock_irqsave(&sem->wait_lock, flags); | ||
| 94 | count = atomic_read(&sem->count); | ||
| 95 | if (likely(count > 0)) { | ||
| 96 | atomic_set(&sem->count, count - 1); | ||
| 97 | spin_unlock_irqrestore(&sem->wait_lock, flags); | ||
| 98 | } else { | ||
| 99 | __down(sem, flags); | ||
| 100 | } | ||
| 101 | } | ||
| 102 | |||
| 103 | static inline int down_interruptible(struct semaphore *sem) | ||
| 104 | { | ||
| 105 | unsigned long flags; | ||
| 106 | int count, ret = 0; | ||
| 107 | |||
| 108 | #if SEMAPHORE_DEBUG | ||
| 109 | CHECK_MAGIC(sem->__magic); | ||
| 110 | #endif | ||
| 111 | |||
| 112 | spin_lock_irqsave(&sem->wait_lock, flags); | ||
| 113 | count = atomic_read(&sem->count); | ||
| 114 | if (likely(count > 0)) { | ||
| 115 | atomic_set(&sem->count, count - 1); | ||
| 116 | spin_unlock_irqrestore(&sem->wait_lock, flags); | ||
| 117 | } else { | ||
| 118 | ret = __down_interruptible(sem, flags); | ||
| 119 | } | ||
| 120 | return ret; | ||
| 121 | } | ||
| 122 | |||
| 123 | /* | ||
| 124 | * non-blockingly attempt to down() a semaphore. | ||
| 125 | * - returns zero if we acquired it | ||
| 126 | */ | ||
| 127 | static inline int down_trylock(struct semaphore *sem) | ||
| 128 | { | ||
| 129 | unsigned long flags; | ||
| 130 | int count, success = 0; | ||
| 131 | |||
| 132 | #if SEMAPHORE_DEBUG | ||
| 133 | CHECK_MAGIC(sem->__magic); | ||
| 134 | #endif | ||
| 135 | |||
| 136 | spin_lock_irqsave(&sem->wait_lock, flags); | ||
| 137 | count = atomic_read(&sem->count); | ||
| 138 | if (likely(count > 0)) { | ||
| 139 | atomic_set(&sem->count, count - 1); | ||
| 140 | success = 1; | ||
| 141 | } | ||
| 142 | spin_unlock_irqrestore(&sem->wait_lock, flags); | ||
| 143 | return !success; | ||
| 144 | } | ||
| 145 | |||
| 146 | static inline void up(struct semaphore *sem) | ||
| 147 | { | ||
| 148 | unsigned long flags; | ||
| 149 | |||
| 150 | #if SEMAPHORE_DEBUG | ||
| 151 | CHECK_MAGIC(sem->__magic); | ||
| 152 | #endif | ||
| 153 | |||
| 154 | spin_lock_irqsave(&sem->wait_lock, flags); | ||
| 155 | if (!list_empty(&sem->wait_list)) | ||
| 156 | __up(sem); | ||
| 157 | else | ||
| 158 | atomic_set(&sem->count, atomic_read(&sem->count) + 1); | ||
| 159 | spin_unlock_irqrestore(&sem->wait_lock, flags); | ||
| 160 | } | ||
| 161 | |||
| 162 | static inline int sem_getcount(struct semaphore *sem) | ||
| 163 | { | ||
| 164 | return atomic_read(&sem->count); | ||
| 165 | } | ||
| 166 | |||
| 167 | #endif /* __ASSEMBLY__ */ | ||
| 168 | |||
| 169 | #endif | ||
diff --git a/include/asm-mn10300/sembuf.h b/include/asm-mn10300/sembuf.h new file mode 100644 index 000000000000..301f3f9d8aa9 --- /dev/null +++ b/include/asm-mn10300/sembuf.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | #ifndef _ASM_SEMBUF_H | ||
| 2 | #define _ASM_SEMBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The semid64_ds structure for MN10300 architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct semid64_ds { | ||
| 15 | struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ | ||
| 16 | __kernel_time_t sem_otime; /* last semop time */ | ||
| 17 | unsigned long __unused1; | ||
| 18 | __kernel_time_t sem_ctime; /* last change time */ | ||
| 19 | unsigned long __unused2; | ||
| 20 | unsigned long sem_nsems; /* no. of semaphores in array */ | ||
| 21 | unsigned long __unused3; | ||
| 22 | unsigned long __unused4; | ||
| 23 | }; | ||
| 24 | |||
| 25 | #endif /* _ASM_SEMBUF_H */ | ||
diff --git a/include/asm-mn10300/serial-regs.h b/include/asm-mn10300/serial-regs.h new file mode 100644 index 000000000000..6498469e93ac --- /dev/null +++ b/include/asm-mn10300/serial-regs.h | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /* MN10300 on-board serial port module registers | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_SERIAL_REGS_H | ||
| 13 | #define _ASM_SERIAL_REGS_H | ||
| 14 | |||
| 15 | #include <asm/cpu-regs.h> | ||
| 16 | #include <asm/intctl-regs.h> | ||
| 17 | |||
| 18 | #ifdef __KERNEL__ | ||
| 19 | |||
| 20 | /* serial port 0 */ | ||
| 21 | #define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */ | ||
| 22 | #define SC01CTR_CK 0x0007 /* clock source select */ | ||
| 23 | #define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */ | ||
| 24 | #define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */ | ||
| 25 | #define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */ | ||
| 26 | #define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */ | ||
| 27 | #define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */ | ||
| 28 | #define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */ | ||
| 29 | #define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 0 only) */ | ||
| 30 | #define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 2 underflow (serial port 1 only) */ | ||
| 31 | #define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */ | ||
| 32 | #define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */ | ||
| 33 | #define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */ | ||
| 34 | #define SC01CTR_CK_EXTERN 0x0007 /* - external closk */ | ||
| 35 | #define SC01CTR_STB 0x0008 /* stop bit select */ | ||
| 36 | #define SC01CTR_STB_1BIT 0x0000 /* - 1 stop bit */ | ||
| 37 | #define SC01CTR_STB_2BIT 0x0008 /* - 2 stop bits */ | ||
| 38 | #define SC01CTR_PB 0x0070 /* parity bit select */ | ||
| 39 | #define SC01CTR_PB_NONE 0x0000 /* - no parity */ | ||
| 40 | #define SC01CTR_PB_FIXED0 0x0040 /* - fixed at 0 */ | ||
| 41 | #define SC01CTR_PB_FIXED1 0x0050 /* - fixed at 1 */ | ||
| 42 | #define SC01CTR_PB_EVEN 0x0060 /* - even parity */ | ||
| 43 | #define SC01CTR_PB_ODD 0x0070 /* - odd parity */ | ||
| 44 | #define SC01CTR_CLN 0x0080 /* character length */ | ||
| 45 | #define SC01CTR_CLN_7BIT 0x0000 /* - 7 bit chars */ | ||
| 46 | #define SC01CTR_CLN_8BIT 0x0080 /* - 8 bit chars */ | ||
| 47 | #define SC01CTR_TOE 0x0100 /* T input output enable */ | ||
| 48 | #define SC01CTR_OD 0x0200 /* bit order select */ | ||
| 49 | #define SC01CTR_OD_LSBFIRST 0x0000 /* - LSB first */ | ||
| 50 | #define SC01CTR_OD_MSBFIRST 0x0200 /* - MSB first */ | ||
| 51 | #define SC01CTR_MD 0x0c00 /* mode select */ | ||
| 52 | #define SC01CTR_MD_STST_SYNC 0x0000 /* - start-stop synchronous */ | ||
| 53 | #define SC01CTR_MD_CLOCK_SYNC1 0x0400 /* - clock synchronous 1 */ | ||
| 54 | #define SC01CTR_MD_I2C 0x0800 /* - I2C mode */ | ||
| 55 | #define SC01CTR_MD_CLOCK_SYNC2 0x0c00 /* - clock synchronous 2 */ | ||
| 56 | #define SC01CTR_IIC 0x1000 /* I2C mode select */ | ||
| 57 | #define SC01CTR_BKE 0x2000 /* break transmit enable */ | ||
| 58 | #define SC01CTR_RXE 0x4000 /* receive enable */ | ||
| 59 | #define SC01CTR_TXE 0x8000 /* transmit enable */ | ||
| 60 | |||
| 61 | #define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */ | ||
| 62 | #define SC01ICR_DMD 0x80 /* output data mode */ | ||
| 63 | #define SC01ICR_TD 0x20 /* transmit DMA trigger cause */ | ||
| 64 | #define SC01ICR_TI 0x10 /* transmit interrupt cause */ | ||
| 65 | #define SC01ICR_RES 0x04 /* receive error select */ | ||
| 66 | #define SC01ICR_RI 0x01 /* receive interrupt cause */ | ||
| 67 | |||
| 68 | #define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */ | ||
| 69 | #define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */ | ||
| 70 | |||
| 71 | #define SC0STR __SYSREG(0xd400200c, u16) /* status reg */ | ||
| 72 | #define SC01STR_OEF 0x0001 /* overrun error found */ | ||
| 73 | #define SC01STR_PEF 0x0002 /* parity error found */ | ||
| 74 | #define SC01STR_FEF 0x0004 /* framing error found */ | ||
| 75 | #define SC01STR_RBF 0x0010 /* receive buffer status */ | ||
| 76 | #define SC01STR_TBF 0x0020 /* transmit buffer status */ | ||
| 77 | #define SC01STR_RXF 0x0040 /* receive status */ | ||
| 78 | #define SC01STR_TXF 0x0080 /* transmit status */ | ||
| 79 | #define SC01STR_STF 0x0100 /* I2C start sequence found */ | ||
| 80 | #define SC01STR_SPF 0x0200 /* I2C stop sequence found */ | ||
| 81 | |||
| 82 | #define SC0RXIRQ 20 /* timer 0 Receive IRQ */ | ||
| 83 | #define SC0TXIRQ 21 /* timer 0 Transmit IRQ */ | ||
| 84 | |||
| 85 | #define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */ | ||
| 86 | #define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */ | ||
| 87 | |||
| 88 | /* serial port 1 */ | ||
| 89 | #define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */ | ||
| 90 | #define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */ | ||
| 91 | #define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */ | ||
| 92 | #define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */ | ||
| 93 | #define SC1STR __SYSREG(0xd400201c, u16) /* status reg */ | ||
| 94 | |||
| 95 | #define SC1RXIRQ 22 /* timer 1 Receive IRQ */ | ||
| 96 | #define SC1TXIRQ 23 /* timer 1 Transmit IRQ */ | ||
| 97 | |||
| 98 | #define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */ | ||
| 99 | #define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */ | ||
| 100 | |||
| 101 | /* serial port 2 */ | ||
| 102 | #define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */ | ||
| 103 | #define SC2CTR_CK 0x0003 /* clock source select */ | ||
| 104 | #define SC2CTR_CK_TM10UFLOW 0x0000 /* - timer 10 underflow */ | ||
| 105 | #define SC2CTR_CK_TM2UFLOW 0x0001 /* - timer 2 underflow */ | ||
| 106 | #define SC2CTR_CK_EXTERN 0x0002 /* - external closk */ | ||
| 107 | #define SC2CTR_CK_TM3UFLOW 0x0003 /* - timer 3 underflow */ | ||
| 108 | #define SC2CTR_STB 0x0008 /* stop bit select */ | ||
| 109 | #define SC2CTR_STB_1BIT 0x0000 /* - 1 stop bit */ | ||
| 110 | #define SC2CTR_STB_2BIT 0x0008 /* - 2 stop bits */ | ||
| 111 | #define SC2CTR_PB 0x0070 /* parity bit select */ | ||
| 112 | #define SC2CTR_PB_NONE 0x0000 /* - no parity */ | ||
| 113 | #define SC2CTR_PB_FIXED0 0x0040 /* - fixed at 0 */ | ||
| 114 | #define SC2CTR_PB_FIXED1 0x0050 /* - fixed at 1 */ | ||
| 115 | #define SC2CTR_PB_EVEN 0x0060 /* - even parity */ | ||
| 116 | #define SC2CTR_PB_ODD 0x0070 /* - odd parity */ | ||
| 117 | #define SC2CTR_CLN 0x0080 /* character length */ | ||
| 118 | #define SC2CTR_CLN_7BIT 0x0000 /* - 7 bit chars */ | ||
| 119 | #define SC2CTR_CLN_8BIT 0x0080 /* - 8 bit chars */ | ||
| 120 | #define SC2CTR_TWE 0x0100 /* transmit wait enable (enable XCTS control) */ | ||
| 121 | #define SC2CTR_OD 0x0200 /* bit order select */ | ||
| 122 | #define SC2CTR_OD_LSBFIRST 0x0000 /* - LSB first */ | ||
| 123 | #define SC2CTR_OD_MSBFIRST 0x0200 /* - MSB first */ | ||
| 124 | #define SC2CTR_TWS 0x1000 /* transmit wait select */ | ||
| 125 | #define SC2CTR_TWS_XCTS_HIGH 0x0000 /* - interrupt TX when XCTS high */ | ||
| 126 | #define SC2CTR_TWS_XCTS_LOW 0x1000 /* - interrupt TX when XCTS low */ | ||
| 127 | #define SC2CTR_BKE 0x2000 /* break transmit enable */ | ||
| 128 | #define SC2CTR_RXE 0x4000 /* receive enable */ | ||
| 129 | #define SC2CTR_TXE 0x8000 /* transmit enable */ | ||
| 130 | |||
| 131 | #define SC2ICR __SYSREG(0xd4002024, u8) /* interrupt control reg */ | ||
| 132 | #define SC2ICR_TD 0x20 /* transmit DMA trigger cause */ | ||
| 133 | #define SC2ICR_TI 0x10 /* transmit interrupt cause */ | ||
| 134 | #define SC2ICR_RES 0x04 /* receive error select */ | ||
| 135 | #define SC2ICR_RI 0x01 /* receive interrupt cause */ | ||
| 136 | |||
| 137 | #define SC2TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */ | ||
| 138 | #define SC2RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */ | ||
| 139 | #define SC2STR __SYSREG(0xd400201c, u8) /* status reg */ | ||
| 140 | #define SC2STR_OEF 0x0001 /* overrun error found */ | ||
| 141 | #define SC2STR_PEF 0x0002 /* parity error found */ | ||
| 142 | #define SC2STR_FEF 0x0004 /* framing error found */ | ||
| 143 | #define SC2STR_CTS 0x0008 /* XCTS input pin status (0 means high) */ | ||
| 144 | #define SC2STR_RBF 0x0010 /* receive buffer status */ | ||
| 145 | #define SC2STR_TBF 0x0020 /* transmit buffer status */ | ||
| 146 | #define SC2STR_RXF 0x0040 /* receive status */ | ||
| 147 | #define SC2STR_TXF 0x0080 /* transmit status */ | ||
| 148 | |||
| 149 | #define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */ | ||
| 150 | |||
| 151 | #define SC2RXIRQ 24 /* serial 2 Receive IRQ */ | ||
| 152 | #define SC2TXIRQ 25 /* serial 2 Transmit IRQ */ | ||
| 153 | |||
| 154 | #define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */ | ||
| 155 | #define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */ | ||
| 156 | |||
| 157 | |||
| 158 | #endif /* __KERNEL__ */ | ||
| 159 | |||
| 160 | #endif /* _ASM_SERIAL_REGS_H */ | ||
diff --git a/include/asm-mn10300/serial.h b/include/asm-mn10300/serial.h new file mode 100644 index 000000000000..99785a9deadb --- /dev/null +++ b/include/asm-mn10300/serial.h | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | /* Standard UART definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * The ASB2305 has an 18.432 MHz clock the UART | ||
| 14 | */ | ||
| 15 | #define BASE_BAUD (18432000 / 16) | ||
| 16 | |||
| 17 | /* Standard COM flags (except for COM4, because of the 8514 problem) */ | ||
| 18 | #ifdef CONFIG_SERIAL_DETECT_IRQ | ||
| 19 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) | ||
| 20 | #define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) | ||
| 21 | #else | ||
| 22 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) | ||
| 23 | #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifdef CONFIG_SERIAL_MANY_PORTS | ||
| 27 | #define FOURPORT_FLAGS ASYNC_FOURPORT | ||
| 28 | #define ACCENT_FLAGS 0 | ||
| 29 | #define BOCA_FLAGS 0 | ||
| 30 | #define HUB6_FLAGS 0 | ||
| 31 | #define RS_TABLE_SIZE 64 | ||
| 32 | #else | ||
| 33 | #define RS_TABLE_SIZE | ||
| 34 | #endif | ||
| 35 | |||
| 36 | #include <asm/unit/serial.h> | ||
diff --git a/include/asm-mn10300/setup.h b/include/asm-mn10300/setup.h new file mode 100644 index 000000000000..08356c832283 --- /dev/null +++ b/include/asm-mn10300/setup.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* MN10300 Setup declarations | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_SETUP_H | ||
| 12 | #define _ASM_SETUP_H | ||
| 13 | |||
| 14 | extern void __init unit_setup(void); | ||
| 15 | extern void __init unit_init_IRQ(void); | ||
| 16 | |||
| 17 | #endif /* _ASM_SETUP_H */ | ||
diff --git a/include/asm-mn10300/shmbuf.h b/include/asm-mn10300/shmbuf.h new file mode 100644 index 000000000000..8f300cc35d6c --- /dev/null +++ b/include/asm-mn10300/shmbuf.h | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | #ifndef _ASM_SHMBUF_H | ||
| 2 | #define _ASM_SHMBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The shmid64_ds structure for MN10300 architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct shmid64_ds { | ||
| 15 | struct ipc64_perm shm_perm; /* operation perms */ | ||
| 16 | size_t shm_segsz; /* size of segment (bytes) */ | ||
| 17 | __kernel_time_t shm_atime; /* last attach time */ | ||
| 18 | unsigned long __unused1; | ||
| 19 | __kernel_time_t shm_dtime; /* last detach time */ | ||
| 20 | unsigned long __unused2; | ||
| 21 | __kernel_time_t shm_ctime; /* last change time */ | ||
| 22 | unsigned long __unused3; | ||
| 23 | __kernel_pid_t shm_cpid; /* pid of creator */ | ||
| 24 | __kernel_pid_t shm_lpid; /* pid of last operator */ | ||
| 25 | unsigned long shm_nattch; /* no. of current attaches */ | ||
| 26 | unsigned long __unused4; | ||
| 27 | unsigned long __unused5; | ||
| 28 | }; | ||
| 29 | |||
| 30 | struct shminfo64 { | ||
| 31 | unsigned long shmmax; | ||
| 32 | unsigned long shmmin; | ||
| 33 | unsigned long shmmni; | ||
| 34 | unsigned long shmseg; | ||
| 35 | unsigned long shmall; | ||
| 36 | unsigned long __unused1; | ||
| 37 | unsigned long __unused2; | ||
| 38 | unsigned long __unused3; | ||
| 39 | unsigned long __unused4; | ||
| 40 | }; | ||
| 41 | |||
| 42 | #endif /* _ASM_SHMBUF_H */ | ||
diff --git a/include/asm-mn10300/shmparam.h b/include/asm-mn10300/shmparam.h new file mode 100644 index 000000000000..ab666ed1a070 --- /dev/null +++ b/include/asm-mn10300/shmparam.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _ASM_SHMPARAM_H | ||
| 2 | #define _ASM_SHMPARAM_H | ||
| 3 | |||
| 4 | #define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ | ||
| 5 | |||
| 6 | #endif /* _ASM_SHMPARAM_H */ | ||
diff --git a/include/asm-mn10300/sigcontext.h b/include/asm-mn10300/sigcontext.h new file mode 100644 index 000000000000..4de3afff4ad7 --- /dev/null +++ b/include/asm-mn10300/sigcontext.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | /* MN10300 Userspace signal context | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_SIGCONTEXT_H | ||
| 12 | #define _ASM_SIGCONTEXT_H | ||
| 13 | |||
| 14 | struct fpucontext { | ||
| 15 | /* Regular FPU environment */ | ||
| 16 | unsigned long fs[32]; /* fpu registers */ | ||
| 17 | unsigned long fpcr; /* fpu control register */ | ||
| 18 | }; | ||
| 19 | |||
| 20 | struct sigcontext { | ||
| 21 | unsigned long d0; | ||
| 22 | unsigned long d1; | ||
| 23 | unsigned long d2; | ||
| 24 | unsigned long d3; | ||
| 25 | unsigned long a0; | ||
| 26 | unsigned long a1; | ||
| 27 | unsigned long a2; | ||
| 28 | unsigned long a3; | ||
| 29 | unsigned long e0; | ||
| 30 | unsigned long e1; | ||
| 31 | unsigned long e2; | ||
| 32 | unsigned long e3; | ||
| 33 | unsigned long e4; | ||
| 34 | unsigned long e5; | ||
| 35 | unsigned long e6; | ||
| 36 | unsigned long e7; | ||
| 37 | unsigned long lar; | ||
| 38 | unsigned long lir; | ||
| 39 | unsigned long mdr; | ||
| 40 | unsigned long mcvf; | ||
| 41 | unsigned long mcrl; | ||
| 42 | unsigned long mcrh; | ||
| 43 | unsigned long mdrq; | ||
| 44 | unsigned long sp; | ||
| 45 | unsigned long epsw; | ||
| 46 | unsigned long pc; | ||
| 47 | struct fpucontext *fpucontext; | ||
| 48 | unsigned long oldmask; | ||
| 49 | }; | ||
| 50 | |||
| 51 | |||
| 52 | #endif /* _ASM_SIGCONTEXT_H */ | ||
diff --git a/include/asm-mn10300/siginfo.h b/include/asm-mn10300/siginfo.h new file mode 100644 index 000000000000..0815d29d82e5 --- /dev/null +++ b/include/asm-mn10300/siginfo.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/siginfo.h> | |||
diff --git a/include/asm-mn10300/signal.h b/include/asm-mn10300/signal.h new file mode 100644 index 000000000000..e98817cec5f7 --- /dev/null +++ b/include/asm-mn10300/signal.h | |||
| @@ -0,0 +1,171 @@ | |||
| 1 | /* MN10300 Signal definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_SIGNAL_H | ||
| 12 | #define _ASM_SIGNAL_H | ||
| 13 | |||
| 14 | #include <linux/types.h> | ||
| 15 | |||
| 16 | /* Avoid too many header ordering problems. */ | ||
| 17 | struct siginfo; | ||
| 18 | |||
| 19 | #ifdef __KERNEL__ | ||
| 20 | /* Most things should be clean enough to redefine this at will, if care | ||
| 21 | is taken to make libc match. */ | ||
| 22 | |||
| 23 | #define _NSIG 64 | ||
| 24 | #define _NSIG_BPW 32 | ||
| 25 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
| 26 | |||
| 27 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
| 28 | |||
| 29 | typedef struct { | ||
| 30 | unsigned long sig[_NSIG_WORDS]; | ||
| 31 | } sigset_t; | ||
| 32 | |||
| 33 | #else | ||
| 34 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 35 | |||
| 36 | #define NSIG 32 | ||
| 37 | typedef unsigned long sigset_t; | ||
| 38 | |||
| 39 | #endif /* __KERNEL__ */ | ||
| 40 | |||
| 41 | #define SIGHUP 1 | ||
| 42 | #define SIGINT 2 | ||
| 43 | #define SIGQUIT 3 | ||
| 44 | #define SIGILL 4 | ||
| 45 | #define SIGTRAP 5 | ||
| 46 | #define SIGABRT 6 | ||
| 47 | #define SIGIOT 6 | ||
| 48 | #define SIGBUS 7 | ||
| 49 | #define SIGFPE 8 | ||
| 50 | #define SIGKILL 9 | ||
| 51 | #define SIGUSR1 10 | ||
| 52 | #define SIGSEGV 11 | ||
| 53 | #define SIGUSR2 12 | ||
| 54 | #define SIGPIPE 13 | ||
| 55 | #define SIGALRM 14 | ||
| 56 | #define SIGTERM 15 | ||
| 57 | #define SIGSTKFLT 16 | ||
| 58 | #define SIGCHLD 17 | ||
| 59 | #define SIGCONT 18 | ||
| 60 | #define SIGSTOP 19 | ||
| 61 | #define SIGTSTP 20 | ||
| 62 | #define SIGTTIN 21 | ||
| 63 | #define SIGTTOU 22 | ||
| 64 | #define SIGURG 23 | ||
| 65 | #define SIGXCPU 24 | ||
| 66 | #define SIGXFSZ 25 | ||
| 67 | #define SIGVTALRM 26 | ||
| 68 | #define SIGPROF 27 | ||
| 69 | #define SIGWINCH 28 | ||
| 70 | #define SIGIO 29 | ||
| 71 | #define SIGPOLL SIGIO | ||
| 72 | /* | ||
| 73 | #define SIGLOST 29 | ||
| 74 | */ | ||
| 75 | #define SIGPWR 30 | ||
| 76 | #define SIGSYS 31 | ||
| 77 | #define SIGUNUSED 31 | ||
| 78 | |||
| 79 | /* These should not be considered constants from userland. */ | ||
| 80 | #define SIGRTMIN 32 | ||
| 81 | #define SIGRTMAX (_NSIG-1) | ||
| 82 | |||
| 83 | /* | ||
| 84 | * SA_FLAGS values: | ||
| 85 | * | ||
| 86 | * SA_ONSTACK indicates that a registered stack_t will be used. | ||
| 87 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
| 88 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
| 89 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
| 90 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
| 91 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
| 92 | * | ||
| 93 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
| 94 | * Unix names RESETHAND and NODEFER respectively. | ||
| 95 | */ | ||
| 96 | #define SA_NOCLDSTOP 0x00000001U | ||
| 97 | #define SA_NOCLDWAIT 0x00000002U | ||
| 98 | #define SA_SIGINFO 0x00000004U | ||
| 99 | #define SA_ONSTACK 0x08000000U | ||
| 100 | #define SA_RESTART 0x10000000U | ||
| 101 | #define SA_NODEFER 0x40000000U | ||
| 102 | #define SA_RESETHAND 0x80000000U | ||
| 103 | |||
| 104 | #define SA_NOMASK SA_NODEFER | ||
| 105 | #define SA_ONESHOT SA_RESETHAND | ||
| 106 | |||
| 107 | #define SA_RESTORER 0x04000000 | ||
| 108 | |||
| 109 | /* | ||
| 110 | * sigaltstack controls | ||
| 111 | */ | ||
| 112 | #define SS_ONSTACK 1 | ||
| 113 | #define SS_DISABLE 2 | ||
| 114 | |||
| 115 | #define MINSIGSTKSZ 2048 | ||
| 116 | #define SIGSTKSZ 8192 | ||
| 117 | |||
| 118 | #include <asm-generic/signal.h> | ||
| 119 | |||
| 120 | #ifdef __KERNEL__ | ||
| 121 | struct old_sigaction { | ||
| 122 | __sighandler_t sa_handler; | ||
| 123 | old_sigset_t sa_mask; | ||
| 124 | unsigned long sa_flags; | ||
| 125 | __sigrestore_t sa_restorer; | ||
| 126 | }; | ||
| 127 | |||
| 128 | struct sigaction { | ||
| 129 | __sighandler_t sa_handler; | ||
| 130 | unsigned long sa_flags; | ||
| 131 | __sigrestore_t sa_restorer; | ||
| 132 | sigset_t sa_mask; /* mask last for extensibility */ | ||
| 133 | }; | ||
| 134 | |||
| 135 | struct k_sigaction { | ||
| 136 | struct sigaction sa; | ||
| 137 | }; | ||
| 138 | #else | ||
| 139 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 140 | |||
| 141 | struct sigaction { | ||
| 142 | union { | ||
| 143 | __sighandler_t _sa_handler; | ||
| 144 | void (*_sa_sigaction)(int, struct siginfo *, void *); | ||
| 145 | } _u; | ||
| 146 | sigset_t sa_mask; | ||
| 147 | unsigned long sa_flags; | ||
| 148 | void (*sa_restorer)(void); | ||
| 149 | }; | ||
| 150 | |||
| 151 | #define sa_handler _u._sa_handler | ||
| 152 | #define sa_sigaction _u._sa_sigaction | ||
| 153 | |||
| 154 | #endif /* __KERNEL__ */ | ||
| 155 | |||
| 156 | typedef struct sigaltstack { | ||
| 157 | void __user *ss_sp; | ||
| 158 | int ss_flags; | ||
| 159 | size_t ss_size; | ||
| 160 | } stack_t; | ||
| 161 | |||
| 162 | #ifdef __KERNEL__ | ||
| 163 | #include <asm/sigcontext.h> | ||
| 164 | |||
| 165 | |||
| 166 | struct pt_regs; | ||
| 167 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) | ||
| 168 | |||
| 169 | #endif /* __KERNEL__ */ | ||
| 170 | |||
| 171 | #endif /* _ASM_SIGNAL_H */ | ||
diff --git a/include/asm-mn10300/smp.h b/include/asm-mn10300/smp.h new file mode 100644 index 000000000000..4eb8c61b7dab --- /dev/null +++ b/include/asm-mn10300/smp.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* MN10300 SMP support | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_SMP_H | ||
| 12 | #define _ASM_SMP_H | ||
| 13 | |||
| 14 | #ifdef CONFIG_SMP | ||
| 15 | #error SMP not yet supported for MN10300 | ||
| 16 | #endif | ||
| 17 | |||
| 18 | #endif | ||
diff --git a/include/asm-mn10300/socket.h b/include/asm-mn10300/socket.h new file mode 100644 index 000000000000..99ca648b94c5 --- /dev/null +++ b/include/asm-mn10300/socket.h | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | #ifndef _ASM_SOCKET_H | ||
| 2 | #define _ASM_SOCKET_H | ||
| 3 | |||
| 4 | #include <asm/sockios.h> | ||
| 5 | |||
| 6 | /* For setsockopt(2) */ | ||
| 7 | #define SOL_SOCKET 1 | ||
| 8 | |||
| 9 | #define SO_DEBUG 1 | ||
| 10 | #define SO_REUSEADDR 2 | ||
| 11 | #define SO_TYPE 3 | ||
| 12 | #define SO_ERROR 4 | ||
| 13 | #define SO_DONTROUTE 5 | ||
| 14 | #define SO_BROADCAST 6 | ||
| 15 | #define SO_SNDBUF 7 | ||
| 16 | #define SO_RCVBUF 8 | ||
| 17 | #define SO_SNDBUFFORCE 32 | ||
| 18 | #define SO_RCVBUFFORCE 33 | ||
| 19 | #define SO_KEEPALIVE 9 | ||
| 20 | #define SO_OOBINLINE 10 | ||
| 21 | #define SO_NO_CHECK 11 | ||
| 22 | #define SO_PRIORITY 12 | ||
| 23 | #define SO_LINGER 13 | ||
| 24 | #define SO_BSDCOMPAT 14 | ||
| 25 | /* To add :#define SO_REUSEPORT 15 */ | ||
| 26 | #define SO_PASSCRED 16 | ||
| 27 | #define SO_PEERCRED 17 | ||
| 28 | #define SO_RCVLOWAT 18 | ||
| 29 | #define SO_SNDLOWAT 19 | ||
| 30 | #define SO_RCVTIMEO 20 | ||
| 31 | #define SO_SNDTIMEO 21 | ||
| 32 | |||
| 33 | /* Security levels - as per NRL IPv6 - don't actually do anything */ | ||
| 34 | #define SO_SECURITY_AUTHENTICATION 22 | ||
| 35 | #define SO_SECURITY_ENCRYPTION_TRANSPORT 23 | ||
| 36 | #define SO_SECURITY_ENCRYPTION_NETWORK 24 | ||
| 37 | |||
| 38 | #define SO_BINDTODEVICE 25 | ||
| 39 | |||
| 40 | /* Socket filtering */ | ||
| 41 | #define SO_ATTACH_FILTER 26 | ||
| 42 | #define SO_DETACH_FILTER 27 | ||
| 43 | |||
| 44 | #define SO_PEERNAME 28 | ||
| 45 | #define SO_TIMESTAMP 29 | ||
| 46 | #define SCM_TIMESTAMP SO_TIMESTAMP | ||
| 47 | |||
| 48 | #define SO_ACCEPTCONN 30 | ||
| 49 | |||
| 50 | #define SO_PEERSEC 31 | ||
| 51 | #define SO_PASSSEC 34 | ||
| 52 | #define SO_TIMESTAMPNS 35 | ||
| 53 | #define SCM_TIMESTAMPNS SO_TIMESTAMPNS | ||
| 54 | |||
| 55 | #endif /* _ASM_SOCKET_H */ | ||
diff --git a/include/asm-mn10300/sockios.h b/include/asm-mn10300/sockios.h new file mode 100644 index 000000000000..b03043a1c564 --- /dev/null +++ b/include/asm-mn10300/sockios.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #ifndef _ASM_SOCKIOS_H | ||
| 2 | #define _ASM_SOCKIOS_H | ||
| 3 | |||
| 4 | /* Socket-level I/O control calls. */ | ||
| 5 | #define FIOSETOWN 0x8901 | ||
| 6 | #define SIOCSPGRP 0x8902 | ||
| 7 | #define FIOGETOWN 0x8903 | ||
| 8 | #define SIOCGPGRP 0x8904 | ||
| 9 | #define SIOCATMARK 0x8905 | ||
| 10 | #define SIOCGSTAMP 0x8906 /* Get stamp */ | ||
| 11 | #define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ | ||
| 12 | |||
| 13 | #endif /* _ASM_SOCKIOS_H */ | ||
diff --git a/include/asm-mn10300/spinlock.h b/include/asm-mn10300/spinlock.h new file mode 100644 index 000000000000..4bf9c8b169e0 --- /dev/null +++ b/include/asm-mn10300/spinlock.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | /* MN10300 spinlock support | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_SPINLOCK_H | ||
| 12 | #define _ASM_SPINLOCK_H | ||
| 13 | |||
| 14 | #error SMP spinlocks not implemented for MN10300 | ||
| 15 | |||
| 16 | #endif /* _ASM_SPINLOCK_H */ | ||
diff --git a/include/asm-mn10300/stat.h b/include/asm-mn10300/stat.h new file mode 100644 index 000000000000..63ff8371cf2c --- /dev/null +++ b/include/asm-mn10300/stat.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | #ifndef _ASM_STAT_H | ||
| 2 | #define _ASM_STAT_H | ||
| 3 | |||
| 4 | struct __old_kernel_stat { | ||
| 5 | unsigned short st_dev; | ||
| 6 | unsigned short st_ino; | ||
| 7 | unsigned short st_mode; | ||
| 8 | unsigned short st_nlink; | ||
| 9 | unsigned short st_uid; | ||
| 10 | unsigned short st_gid; | ||
| 11 | unsigned short st_rdev; | ||
| 12 | unsigned long st_size; | ||
| 13 | unsigned long st_atime; | ||
| 14 | unsigned long st_mtime; | ||
| 15 | unsigned long st_ctime; | ||
| 16 | }; | ||
| 17 | |||
| 18 | struct stat { | ||
| 19 | unsigned long st_dev; | ||
| 20 | unsigned long st_ino; | ||
| 21 | unsigned short st_mode; | ||
| 22 | unsigned short st_nlink; | ||
| 23 | unsigned short st_uid; | ||
| 24 | unsigned short st_gid; | ||
| 25 | unsigned long st_rdev; | ||
| 26 | unsigned long st_size; | ||
| 27 | unsigned long st_blksize; | ||
| 28 | unsigned long st_blocks; | ||
| 29 | unsigned long st_atime; | ||
| 30 | unsigned long st_atime_nsec; | ||
| 31 | unsigned long st_mtime; | ||
| 32 | unsigned long st_mtime_nsec; | ||
| 33 | unsigned long st_ctime; | ||
| 34 | unsigned long st_ctime_nsec; | ||
| 35 | unsigned long __unused4; | ||
| 36 | unsigned long __unused5; | ||
| 37 | }; | ||
| 38 | |||
| 39 | /* This matches struct stat64 in glibc2.1, hence the absolutely | ||
| 40 | * insane amounts of padding around dev_t's. | ||
| 41 | */ | ||
| 42 | struct stat64 { | ||
| 43 | unsigned long long st_dev; | ||
| 44 | unsigned char __pad0[4]; | ||
| 45 | |||
| 46 | #define STAT64_HAS_BROKEN_ST_INO 1 | ||
| 47 | unsigned long __st_ino; | ||
| 48 | |||
| 49 | unsigned int st_mode; | ||
| 50 | unsigned int st_nlink; | ||
| 51 | |||
| 52 | unsigned long st_uid; | ||
| 53 | unsigned long st_gid; | ||
| 54 | |||
| 55 | unsigned long long st_rdev; | ||
| 56 | unsigned char __pad3[4]; | ||
| 57 | |||
| 58 | long long st_size; | ||
| 59 | unsigned long st_blksize; | ||
| 60 | |||
| 61 | unsigned long st_blocks; /* Number 512-byte blocks allocated. */ | ||
| 62 | unsigned long __pad4; /* future possible st_blocks high bits */ | ||
| 63 | |||
| 64 | unsigned long st_atime; | ||
| 65 | unsigned long st_atime_nsec; | ||
| 66 | |||
| 67 | unsigned long st_mtime; | ||
| 68 | unsigned int st_mtime_nsec; | ||
| 69 | |||
| 70 | unsigned long st_ctime; | ||
| 71 | unsigned long st_ctime_nsec; | ||
| 72 | |||
| 73 | unsigned long long st_ino; | ||
| 74 | }; | ||
| 75 | |||
| 76 | #define STAT_HAVE_NSEC 1 | ||
| 77 | |||
| 78 | #endif /* _ASM_STAT_H */ | ||
diff --git a/include/asm-mn10300/statfs.h b/include/asm-mn10300/statfs.h new file mode 100644 index 000000000000..0b91fe198c20 --- /dev/null +++ b/include/asm-mn10300/statfs.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/statfs.h> | |||
diff --git a/include/asm-mn10300/string.h b/include/asm-mn10300/string.h new file mode 100644 index 000000000000..47dbd4346c32 --- /dev/null +++ b/include/asm-mn10300/string.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* MN10300 Optimised string functions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * Modified by David Howells (dhowells@redhat.com) | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public Licence | ||
| 9 | * as published by the Free Software Foundation; either version | ||
| 10 | * 2 of the Licence, or (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #ifndef _ASM_STRING_H | ||
| 13 | #define _ASM_STRING_H | ||
| 14 | |||
| 15 | #define __HAVE_ARCH_MEMSET | ||
| 16 | #define __HAVE_ARCH_MEMCPY | ||
| 17 | #define __HAVE_ARCH_MEMMOVE | ||
| 18 | |||
| 19 | extern void *memset(void *dest, int ch, size_t count); | ||
| 20 | extern void *memcpy(void *dest, const void *src, size_t count); | ||
| 21 | extern void *memmove(void *dest, const void *src, size_t count); | ||
| 22 | |||
| 23 | |||
| 24 | extern void __struct_cpy_bug(void); | ||
| 25 | #define struct_cpy(x, y) \ | ||
| 26 | ({ \ | ||
| 27 | if (sizeof(*(x)) != sizeof(*(y))) \ | ||
| 28 | __struct_cpy_bug; \ | ||
| 29 | memcpy(x, y, sizeof(*(x))); \ | ||
| 30 | }) | ||
| 31 | |||
| 32 | #endif /* _ASM_STRING_H */ | ||
diff --git a/include/asm-mn10300/system.h b/include/asm-mn10300/system.h new file mode 100644 index 000000000000..8214fb7e7fe4 --- /dev/null +++ b/include/asm-mn10300/system.h | |||
| @@ -0,0 +1,237 @@ | |||
| 1 | /* MN10300 System definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_SYSTEM_H | ||
| 12 | #define _ASM_SYSTEM_H | ||
| 13 | |||
| 14 | #include <asm/cpu-regs.h> | ||
| 15 | |||
| 16 | #ifdef __KERNEL__ | ||
| 17 | #ifndef __ASSEMBLY__ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | |||
| 21 | struct task_struct; | ||
| 22 | struct thread_struct; | ||
| 23 | |||
| 24 | extern asmlinkage | ||
| 25 | struct task_struct *__switch_to(struct thread_struct *prev, | ||
| 26 | struct thread_struct *next, | ||
| 27 | struct task_struct *prev_task); | ||
| 28 | |||
| 29 | /* context switching is now performed out-of-line in switch_to.S */ | ||
| 30 | #define switch_to(prev, next, last) \ | ||
| 31 | do { \ | ||
| 32 | current->thread.wchan = (u_long) __builtin_return_address(0); \ | ||
| 33 | (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \ | ||
| 34 | mb(); \ | ||
| 35 | current->thread.wchan = 0; \ | ||
| 36 | } while (0) | ||
| 37 | |||
| 38 | #define arch_align_stack(x) (x) | ||
| 39 | |||
| 40 | #define nop() asm volatile ("nop") | ||
| 41 | |||
| 42 | #endif /* !__ASSEMBLY__ */ | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Force strict CPU ordering. | ||
| 46 | * And yes, this is required on UP too when we're talking | ||
| 47 | * to devices. | ||
| 48 | * | ||
| 49 | * For now, "wmb()" doesn't actually do anything, as all | ||
| 50 | * Intel CPU's follow what Intel calls a *Processor Order*, | ||
| 51 | * in which all writes are seen in the program order even | ||
| 52 | * outside the CPU. | ||
| 53 | * | ||
| 54 | * I expect future Intel CPU's to have a weaker ordering, | ||
| 55 | * but I'd also expect them to finally get their act together | ||
| 56 | * and add some real memory barriers if so. | ||
| 57 | * | ||
| 58 | * Some non intel clones support out of order store. wmb() ceases to be a | ||
| 59 | * nop for these. | ||
| 60 | */ | ||
| 61 | |||
| 62 | #define mb() asm volatile ("": : :"memory") | ||
| 63 | #define rmb() mb() | ||
| 64 | #define wmb() asm volatile ("": : :"memory") | ||
| 65 | |||
| 66 | #ifdef CONFIG_SMP | ||
| 67 | #define smp_mb() mb() | ||
| 68 | #define smp_rmb() rmb() | ||
| 69 | #define smp_wmb() wmb() | ||
| 70 | #else | ||
| 71 | #define smp_mb() barrier() | ||
| 72 | #define smp_rmb() barrier() | ||
| 73 | #define smp_wmb() barrier() | ||
| 74 | #endif | ||
| 75 | |||
| 76 | #define set_mb(var, value) do { var = value; mb(); } while (0) | ||
| 77 | #define set_wmb(var, value) do { var = value; wmb(); } while (0) | ||
| 78 | |||
| 79 | #define read_barrier_depends() do {} while (0) | ||
| 80 | #define smp_read_barrier_depends() do {} while (0) | ||
| 81 | |||
| 82 | /*****************************************************************************/ | ||
| 83 | /* | ||
| 84 | * interrupt control | ||
| 85 | * - "disabled": run in IM1/2 | ||
| 86 | * - level 0 - GDB stub | ||
| 87 | * - level 1 - virtual serial DMA (if present) | ||
| 88 | * - level 5 - normal interrupt priority | ||
| 89 | * - level 6 - timer interrupt | ||
| 90 | * - "enabled": run in IM7 | ||
| 91 | */ | ||
| 92 | #ifdef CONFIG_MN10300_TTYSM | ||
| 93 | #define MN10300_CLI_LEVEL EPSW_IM_2 | ||
| 94 | #else | ||
| 95 | #define MN10300_CLI_LEVEL EPSW_IM_1 | ||
| 96 | #endif | ||
| 97 | |||
| 98 | #define local_save_flags(x) \ | ||
| 99 | do { \ | ||
| 100 | typecheck(unsigned long, x); \ | ||
| 101 | asm volatile( \ | ||
| 102 | " mov epsw,%0 \n" \ | ||
| 103 | : "=d"(x) \ | ||
| 104 | ); \ | ||
| 105 | } while (0) | ||
| 106 | |||
| 107 | #define local_irq_disable() \ | ||
| 108 | do { \ | ||
| 109 | asm volatile( \ | ||
| 110 | " and %0,epsw \n" \ | ||
| 111 | " or %1,epsw \n" \ | ||
| 112 | " nop \n" \ | ||
| 113 | " nop \n" \ | ||
| 114 | " nop \n" \ | ||
| 115 | : \ | ||
| 116 | : "i"(~EPSW_IM), "i"(EPSW_IE | MN10300_CLI_LEVEL) \ | ||
| 117 | ); \ | ||
| 118 | } while (0) | ||
| 119 | |||
| 120 | #define local_irq_save(x) \ | ||
| 121 | do { \ | ||
| 122 | local_save_flags(x); \ | ||
| 123 | local_irq_disable(); \ | ||
| 124 | } while (0) | ||
| 125 | |||
| 126 | /* | ||
| 127 | * we make sure local_irq_enable() doesn't cause priority inversion | ||
| 128 | */ | ||
| 129 | #ifndef __ASSEMBLY__ | ||
| 130 | |||
| 131 | extern unsigned long __mn10300_irq_enabled_epsw; | ||
| 132 | |||
| 133 | #endif | ||
| 134 | |||
| 135 | #define local_irq_enable() \ | ||
| 136 | do { \ | ||
| 137 | unsigned long tmp; \ | ||
| 138 | \ | ||
| 139 | asm volatile( \ | ||
| 140 | " mov epsw,%0 \n" \ | ||
| 141 | " and %1,%0 \n" \ | ||
| 142 | " or %2,%0 \n" \ | ||
| 143 | " mov %0,epsw \n" \ | ||
| 144 | : "=&d"(tmp) \ | ||
| 145 | : "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw) \ | ||
| 146 | ); \ | ||
| 147 | } while (0) | ||
| 148 | |||
| 149 | #define local_irq_restore(x) \ | ||
| 150 | do { \ | ||
| 151 | typecheck(unsigned long, x); \ | ||
| 152 | asm volatile( \ | ||
| 153 | " mov %0,epsw \n" \ | ||
| 154 | " nop \n" \ | ||
| 155 | " nop \n" \ | ||
| 156 | " nop \n" \ | ||
| 157 | : \ | ||
| 158 | : "d"(x) \ | ||
| 159 | : "memory", "cc" \ | ||
| 160 | ); \ | ||
| 161 | } while (0) | ||
| 162 | |||
| 163 | #define irqs_disabled() \ | ||
| 164 | ({ \ | ||
| 165 | unsigned long flags; \ | ||
| 166 | local_save_flags(flags); \ | ||
| 167 | (flags & EPSW_IM) <= MN10300_CLI_LEVEL; \ | ||
| 168 | }) | ||
| 169 | |||
| 170 | /* hook to save power by halting the CPU | ||
| 171 | * - called from the idle loop | ||
| 172 | * - must reenable interrupts (which takes three instruction cycles to complete) | ||
| 173 | */ | ||
| 174 | #define safe_halt() \ | ||
| 175 | do { \ | ||
| 176 | asm volatile(" or %0,epsw \n" \ | ||
| 177 | " nop \n" \ | ||
| 178 | " nop \n" \ | ||
| 179 | " bset %2,(%1) \n" \ | ||
| 180 | : \ | ||
| 181 | : "i"(EPSW_IE|EPSW_IM), "n"(&CPUM), "i"(CPUM_SLEEP)\ | ||
| 182 | : "cc" \ | ||
| 183 | ); \ | ||
| 184 | } while (0) | ||
| 185 | |||
| 186 | #define STI or EPSW_IE|EPSW_IM,epsw | ||
| 187 | #define CLI and ~EPSW_IM,epsw; or EPSW_IE|MN10300_CLI_LEVEL,epsw; nop; nop; nop | ||
| 188 | |||
| 189 | /*****************************************************************************/ | ||
| 190 | /* | ||
| 191 | * MN10300 doesn't actually have an exchange instruction | ||
| 192 | */ | ||
| 193 | #ifndef __ASSEMBLY__ | ||
| 194 | |||
| 195 | struct __xchg_dummy { unsigned long a[100]; }; | ||
| 196 | #define __xg(x) ((struct __xchg_dummy *)(x)) | ||
| 197 | |||
| 198 | static inline | ||
| 199 | unsigned long __xchg(volatile unsigned long *m, unsigned long val) | ||
| 200 | { | ||
| 201 | unsigned long retval; | ||
| 202 | unsigned long flags; | ||
| 203 | |||
| 204 | local_irq_save(flags); | ||
| 205 | retval = *m; | ||
| 206 | *m = val; | ||
| 207 | local_irq_restore(flags); | ||
| 208 | return retval; | ||
| 209 | } | ||
| 210 | |||
| 211 | #define xchg(ptr, v) \ | ||
| 212 | ((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \ | ||
| 213 | (unsigned long)(v))) | ||
| 214 | |||
| 215 | static inline unsigned long __cmpxchg(volatile unsigned long *m, | ||
| 216 | unsigned long old, unsigned long new) | ||
| 217 | { | ||
| 218 | unsigned long retval; | ||
| 219 | unsigned long flags; | ||
| 220 | |||
| 221 | local_irq_save(flags); | ||
| 222 | retval = *m; | ||
| 223 | if (retval == old) | ||
| 224 | *m = new; | ||
| 225 | local_irq_restore(flags); | ||
| 226 | return retval; | ||
| 227 | } | ||
| 228 | |||
| 229 | #define cmpxchg(ptr, o, n) \ | ||
| 230 | ((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \ | ||
| 231 | (unsigned long)(o), \ | ||
| 232 | (unsigned long)(n))) | ||
| 233 | |||
| 234 | #endif /* !__ASSEMBLY__ */ | ||
| 235 | |||
| 236 | #endif /* __KERNEL__ */ | ||
| 237 | #endif /* _ASM_SYSTEM_H */ | ||
diff --git a/include/asm-mn10300/termbits.h b/include/asm-mn10300/termbits.h new file mode 100644 index 000000000000..eb2b0dc1f696 --- /dev/null +++ b/include/asm-mn10300/termbits.h | |||
| @@ -0,0 +1,200 @@ | |||
| 1 | #ifndef _ASM_TERMBITS_H | ||
| 2 | #define _ASM_TERMBITS_H | ||
| 3 | |||
| 4 | #include <linux/posix_types.h> | ||
| 5 | |||
| 6 | typedef unsigned char cc_t; | ||
| 7 | typedef unsigned int speed_t; | ||
| 8 | typedef unsigned int tcflag_t; | ||
| 9 | |||
| 10 | #define NCCS 19 | ||
| 11 | struct termios { | ||
| 12 | tcflag_t c_iflag; /* input mode flags */ | ||
| 13 | tcflag_t c_oflag; /* output mode flags */ | ||
| 14 | tcflag_t c_cflag; /* control mode flags */ | ||
| 15 | tcflag_t c_lflag; /* local mode flags */ | ||
| 16 | cc_t c_line; /* line discipline */ | ||
| 17 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 18 | }; | ||
| 19 | |||
| 20 | struct termios2 { | ||
| 21 | tcflag_t c_iflag; /* input mode flags */ | ||
| 22 | tcflag_t c_oflag; /* output mode flags */ | ||
| 23 | tcflag_t c_cflag; /* control mode flags */ | ||
| 24 | tcflag_t c_lflag; /* local mode flags */ | ||
| 25 | cc_t c_line; /* line discipline */ | ||
| 26 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 27 | speed_t c_ispeed; /* input speed */ | ||
| 28 | speed_t c_ospeed; /* output speed */ | ||
| 29 | }; | ||
| 30 | |||
| 31 | struct ktermios { | ||
| 32 | tcflag_t c_iflag; /* input mode flags */ | ||
| 33 | tcflag_t c_oflag; /* output mode flags */ | ||
| 34 | tcflag_t c_cflag; /* control mode flags */ | ||
| 35 | tcflag_t c_lflag; /* local mode flags */ | ||
| 36 | cc_t c_line; /* line discipline */ | ||
| 37 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 38 | speed_t c_ispeed; /* input speed */ | ||
| 39 | speed_t c_ospeed; /* output speed */ | ||
| 40 | }; | ||
| 41 | |||
| 42 | /* c_cc characters */ | ||
| 43 | #define VINTR 0 | ||
| 44 | #define VQUIT 1 | ||
| 45 | #define VERASE 2 | ||
| 46 | #define VKILL 3 | ||
| 47 | #define VEOF 4 | ||
| 48 | #define VTIME 5 | ||
| 49 | #define VMIN 6 | ||
| 50 | #define VSWTC 7 | ||
| 51 | #define VSTART 8 | ||
| 52 | #define VSTOP 9 | ||
| 53 | #define VSUSP 10 | ||
| 54 | #define VEOL 11 | ||
| 55 | #define VREPRINT 12 | ||
| 56 | #define VDISCARD 13 | ||
| 57 | #define VWERASE 14 | ||
| 58 | #define VLNEXT 15 | ||
| 59 | #define VEOL2 16 | ||
| 60 | |||
| 61 | |||
| 62 | /* c_iflag bits */ | ||
| 63 | #define IGNBRK 0000001 | ||
| 64 | #define BRKINT 0000002 | ||
| 65 | #define IGNPAR 0000004 | ||
| 66 | #define PARMRK 0000010 | ||
| 67 | #define INPCK 0000020 | ||
| 68 | #define ISTRIP 0000040 | ||
| 69 | #define INLCR 0000100 | ||
| 70 | #define IGNCR 0000200 | ||
| 71 | #define ICRNL 0000400 | ||
| 72 | #define IUCLC 0001000 | ||
| 73 | #define IXON 0002000 | ||
| 74 | #define IXANY 0004000 | ||
| 75 | #define IXOFF 0010000 | ||
| 76 | #define IMAXBEL 0020000 | ||
| 77 | #define IUTF8 0040000 | ||
| 78 | |||
| 79 | /* c_oflag bits */ | ||
| 80 | #define OPOST 0000001 | ||
| 81 | #define OLCUC 0000002 | ||
| 82 | #define ONLCR 0000004 | ||
| 83 | #define OCRNL 0000010 | ||
| 84 | #define ONOCR 0000020 | ||
| 85 | #define ONLRET 0000040 | ||
| 86 | #define OFILL 0000100 | ||
| 87 | #define OFDEL 0000200 | ||
| 88 | #define NLDLY 0000400 | ||
| 89 | #define NL0 0000000 | ||
| 90 | #define NL1 0000400 | ||
| 91 | #define CRDLY 0003000 | ||
| 92 | #define CR0 0000000 | ||
| 93 | #define CR1 0001000 | ||
| 94 | #define CR2 0002000 | ||
| 95 | #define CR3 0003000 | ||
| 96 | #define TABDLY 0014000 | ||
| 97 | #define TAB0 0000000 | ||
| 98 | #define TAB1 0004000 | ||
| 99 | #define TAB2 0010000 | ||
| 100 | #define TAB3 0014000 | ||
| 101 | #define XTABS 0014000 | ||
| 102 | #define BSDLY 0020000 | ||
| 103 | #define BS0 0000000 | ||
| 104 | #define BS1 0020000 | ||
| 105 | #define VTDLY 0040000 | ||
| 106 | #define VT0 0000000 | ||
| 107 | #define VT1 0040000 | ||
| 108 | #define FFDLY 0100000 | ||
| 109 | #define FF0 0000000 | ||
| 110 | #define FF1 0100000 | ||
| 111 | |||
| 112 | /* c_cflag bit meaning */ | ||
| 113 | #define CBAUD 0010017 | ||
| 114 | #define B0 0000000 /* hang up */ | ||
| 115 | #define B50 0000001 | ||
| 116 | #define B75 0000002 | ||
| 117 | #define B110 0000003 | ||
| 118 | #define B134 0000004 | ||
| 119 | #define B150 0000005 | ||
| 120 | #define B200 0000006 | ||
| 121 | #define B300 0000007 | ||
| 122 | #define B600 0000010 | ||
| 123 | #define B1200 0000011 | ||
| 124 | #define B1800 0000012 | ||
| 125 | #define B2400 0000013 | ||
| 126 | #define B4800 0000014 | ||
| 127 | #define B9600 0000015 | ||
| 128 | #define B19200 0000016 | ||
| 129 | #define B38400 0000017 | ||
| 130 | #define EXTA B19200 | ||
| 131 | #define EXTB B38400 | ||
| 132 | #define CSIZE 0000060 | ||
| 133 | #define CS5 0000000 | ||
| 134 | #define CS6 0000020 | ||
| 135 | #define CS7 0000040 | ||
| 136 | #define CS8 0000060 | ||
| 137 | #define CSTOPB 0000100 | ||
| 138 | #define CREAD 0000200 | ||
| 139 | #define PARENB 0000400 | ||
| 140 | #define PARODD 0001000 | ||
| 141 | #define HUPCL 0002000 | ||
| 142 | #define CLOCAL 0004000 | ||
| 143 | #define CBAUDEX 0010000 | ||
| 144 | #define BOTHER 0010000 | ||
| 145 | #define B57600 0010001 | ||
| 146 | #define B115200 0010002 | ||
| 147 | #define B230400 0010003 | ||
| 148 | #define B460800 0010004 | ||
| 149 | #define B500000 0010005 | ||
| 150 | #define B576000 0010006 | ||
| 151 | #define B921600 0010007 | ||
| 152 | #define B1000000 0010010 | ||
| 153 | #define B1152000 0010011 | ||
| 154 | #define B1500000 0010012 | ||
| 155 | #define B2000000 0010013 | ||
| 156 | #define B2500000 0010014 | ||
| 157 | #define B3000000 0010015 | ||
| 158 | #define B3500000 0010016 | ||
| 159 | #define B4000000 0010017 | ||
| 160 | #define CIBAUD 002003600000 /* input baud rate (not used) */ | ||
| 161 | #define CTVB 004000000000 /* VisioBraille Terminal flow control */ | ||
| 162 | #define CMSPAR 010000000000 /* mark or space (stick) parity */ | ||
| 163 | #define CRTSCTS 020000000000 /* flow control */ | ||
| 164 | |||
| 165 | #define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ | ||
| 166 | |||
| 167 | /* c_lflag bits */ | ||
| 168 | #define ISIG 0000001 | ||
| 169 | #define ICANON 0000002 | ||
| 170 | #define XCASE 0000004 | ||
| 171 | #define ECHO 0000010 | ||
| 172 | #define ECHOE 0000020 | ||
| 173 | #define ECHOK 0000040 | ||
| 174 | #define ECHONL 0000100 | ||
| 175 | #define NOFLSH 0000200 | ||
| 176 | #define TOSTOP 0000400 | ||
| 177 | #define ECHOCTL 0001000 | ||
| 178 | #define ECHOPRT 0002000 | ||
| 179 | #define ECHOKE 0004000 | ||
| 180 | #define FLUSHO 0010000 | ||
| 181 | #define PENDIN 0040000 | ||
| 182 | #define IEXTEN 0100000 | ||
| 183 | |||
| 184 | /* tcflow() and TCXONC use these */ | ||
| 185 | #define TCOOFF 0 | ||
| 186 | #define TCOON 1 | ||
| 187 | #define TCIOFF 2 | ||
| 188 | #define TCION 3 | ||
| 189 | |||
| 190 | /* tcflush() and TCFLSH use these */ | ||
| 191 | #define TCIFLUSH 0 | ||
| 192 | #define TCOFLUSH 1 | ||
| 193 | #define TCIOFLUSH 2 | ||
| 194 | |||
| 195 | /* tcsetattr uses these */ | ||
| 196 | #define TCSANOW 0 | ||
| 197 | #define TCSADRAIN 1 | ||
| 198 | #define TCSAFLUSH 2 | ||
| 199 | |||
| 200 | #endif /* _ASM_TERMBITS_H */ | ||
diff --git a/include/asm-mn10300/termios.h b/include/asm-mn10300/termios.h new file mode 100644 index 000000000000..dd7cf617e118 --- /dev/null +++ b/include/asm-mn10300/termios.h | |||
| @@ -0,0 +1,92 @@ | |||
| 1 | #ifndef _ASM_TERMIOS_H | ||
| 2 | #define _ASM_TERMIOS_H | ||
| 3 | |||
| 4 | #include <asm/termbits.h> | ||
| 5 | #include <asm/ioctls.h> | ||
| 6 | |||
| 7 | struct winsize { | ||
| 8 | unsigned short ws_row; | ||
| 9 | unsigned short ws_col; | ||
| 10 | unsigned short ws_xpixel; | ||
| 11 | unsigned short ws_ypixel; | ||
| 12 | }; | ||
| 13 | |||
| 14 | #define NCC 8 | ||
| 15 | struct termio { | ||
| 16 | unsigned short c_iflag; /* input mode flags */ | ||
| 17 | unsigned short c_oflag; /* output mode flags */ | ||
| 18 | unsigned short c_cflag; /* control mode flags */ | ||
| 19 | unsigned short c_lflag; /* local mode flags */ | ||
| 20 | unsigned char c_line; /* line discipline */ | ||
| 21 | unsigned char c_cc[NCC]; /* control characters */ | ||
| 22 | }; | ||
| 23 | |||
| 24 | #ifdef __KERNEL__ | ||
| 25 | /* intr=^C quit=^| erase=del kill=^U | ||
| 26 | eof=^D vtime=\0 vmin=\1 sxtc=\0 | ||
| 27 | start=^Q stop=^S susp=^Z eol=\0 | ||
| 28 | reprint=^R discard=^U werase=^W lnext=^V | ||
| 29 | eol2=\0 | ||
| 30 | */ | ||
| 31 | #define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" | ||
| 32 | #endif | ||
| 33 | |||
| 34 | /* modem lines */ | ||
| 35 | #define TIOCM_LE 0x001 | ||
| 36 | #define TIOCM_DTR 0x002 | ||
| 37 | #define TIOCM_RTS 0x004 | ||
| 38 | #define TIOCM_ST 0x008 | ||
| 39 | #define TIOCM_SR 0x010 | ||
| 40 | #define TIOCM_CTS 0x020 | ||
| 41 | #define TIOCM_CAR 0x040 | ||
| 42 | #define TIOCM_RNG 0x080 | ||
| 43 | #define TIOCM_DSR 0x100 | ||
| 44 | #define TIOCM_CD TIOCM_CAR | ||
| 45 | #define TIOCM_RI TIOCM_RNG | ||
| 46 | #define TIOCM_OUT1 0x2000 | ||
| 47 | #define TIOCM_OUT2 0x4000 | ||
| 48 | #define TIOCM_LOOP 0x8000 | ||
| 49 | |||
| 50 | #define TIOCM_MODEM_BITS TIOCM_OUT2 /* IRDA support */ | ||
| 51 | |||
| 52 | /* | ||
| 53 | * Translate a "termio" structure into a "termios". Ugh. | ||
| 54 | */ | ||
| 55 | #define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ | ||
| 56 | unsigned short __tmp; \ | ||
| 57 | get_user(__tmp, &(termio)->x); \ | ||
| 58 | *(unsigned short *) &(termios)->x = __tmp; \ | ||
| 59 | } | ||
| 60 | |||
| 61 | #define user_termio_to_kernel_termios(termios, termio) \ | ||
| 62 | ({ \ | ||
| 63 | SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ | ||
| 64 | SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ | ||
| 65 | SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ | ||
| 66 | SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ | ||
| 67 | copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ | ||
| 68 | }) | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Translate a "termios" structure into a "termio". Ugh. | ||
| 72 | */ | ||
| 73 | #define kernel_termios_to_user_termio(termio, termios) \ | ||
| 74 | ({ \ | ||
| 75 | put_user((termios)->c_iflag, &(termio)->c_iflag); \ | ||
| 76 | put_user((termios)->c_oflag, &(termio)->c_oflag); \ | ||
| 77 | put_user((termios)->c_cflag, &(termio)->c_cflag); \ | ||
| 78 | put_user((termios)->c_lflag, &(termio)->c_lflag); \ | ||
| 79 | put_user((termios)->c_line, &(termio)->c_line); \ | ||
| 80 | copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ | ||
| 81 | }) | ||
| 82 | |||
| 83 | #define user_termios_to_kernel_termios(k, u) \ | ||
| 84 | copy_from_user(k, u, sizeof(struct termios2)) | ||
| 85 | #define kernel_termios_to_user_termios(u, k) \ | ||
| 86 | copy_to_user(u, k, sizeof(struct termios2)) | ||
| 87 | #define user_termios_to_kernel_termios_1(k, u) \ | ||
| 88 | copy_from_user(k, u, sizeof(struct termios)) | ||
| 89 | #define kernel_termios_to_user_termios_1(u, k) \ | ||
| 90 | copy_to_user(u, k, sizeof(struct termios)) | ||
| 91 | |||
| 92 | #endif /* _ASM_TERMIOS_H */ | ||
diff --git a/include/asm-mn10300/thread_info.h b/include/asm-mn10300/thread_info.h new file mode 100644 index 000000000000..e397e7192785 --- /dev/null +++ b/include/asm-mn10300/thread_info.h | |||
| @@ -0,0 +1,168 @@ | |||
| 1 | /* MN10300 Low-level thread information | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_THREAD_INFO_H | ||
| 13 | #define _ASM_THREAD_INFO_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #include <asm/page.h> | ||
| 18 | |||
| 19 | #ifndef __ASSEMBLY__ | ||
| 20 | #include <asm/processor.h> | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #define PREEMPT_ACTIVE 0x10000000 | ||
| 24 | |||
| 25 | #ifdef CONFIG_4KSTACKS | ||
| 26 | #define THREAD_SIZE (4096) | ||
| 27 | #else | ||
| 28 | #define THREAD_SIZE (8192) | ||
| 29 | #endif | ||
| 30 | |||
| 31 | #define STACK_WARN (THREAD_SIZE / 8) | ||
| 32 | |||
| 33 | /* | ||
| 34 | * low level task data that entry.S needs immediate access to | ||
| 35 | * - this struct should fit entirely inside of one cache line | ||
| 36 | * - this struct shares the supervisor stack pages | ||
| 37 | * - if the contents of this structure are changed, the assembly constants | ||
| 38 | * must also be changed | ||
| 39 | */ | ||
| 40 | #ifndef __ASSEMBLY__ | ||
| 41 | |||
| 42 | struct thread_info { | ||
| 43 | struct task_struct *task; /* main task structure */ | ||
| 44 | struct exec_domain *exec_domain; /* execution domain */ | ||
| 45 | unsigned long flags; /* low level flags */ | ||
| 46 | __u32 cpu; /* current CPU */ | ||
| 47 | __s32 preempt_count; /* 0 => preemptable, <0 => BUG */ | ||
| 48 | |||
| 49 | mm_segment_t addr_limit; /* thread address space: | ||
| 50 | 0-0xBFFFFFFF for user-thead | ||
| 51 | 0-0xFFFFFFFF for kernel-thread | ||
| 52 | */ | ||
| 53 | struct restart_block restart_block; | ||
| 54 | |||
| 55 | __u8 supervisor_stack[0]; | ||
| 56 | }; | ||
| 57 | |||
| 58 | #else /* !__ASSEMBLY__ */ | ||
| 59 | |||
| 60 | #ifndef __ASM_OFFSETS_H__ | ||
| 61 | #include <asm/asm-offsets.h> | ||
| 62 | #endif | ||
| 63 | |||
| 64 | #endif | ||
| 65 | |||
| 66 | /* | ||
| 67 | * macros/functions for gaining access to the thread information structure | ||
| 68 | * | ||
| 69 | * preempt_count needs to be 1 initially, until the scheduler is functional. | ||
| 70 | */ | ||
| 71 | #ifndef __ASSEMBLY__ | ||
| 72 | |||
| 73 | #define INIT_THREAD_INFO(tsk) \ | ||
| 74 | { \ | ||
| 75 | .task = &tsk, \ | ||
| 76 | .exec_domain = &default_exec_domain, \ | ||
| 77 | .flags = 0, \ | ||
| 78 | .cpu = 0, \ | ||
| 79 | .preempt_count = 1, \ | ||
| 80 | .addr_limit = KERNEL_DS, \ | ||
| 81 | .restart_block = { \ | ||
| 82 | .fn = do_no_restart_syscall, \ | ||
| 83 | }, \ | ||
| 84 | } | ||
| 85 | |||
| 86 | #define init_thread_info (init_thread_union.thread_info) | ||
| 87 | #define init_stack (init_thread_union.stack) | ||
| 88 | #define init_uregs \ | ||
| 89 | ((struct pt_regs *) \ | ||
| 90 | ((unsigned long) init_stack + THREAD_SIZE - sizeof(struct pt_regs))) | ||
| 91 | |||
| 92 | extern struct thread_info *__current_ti; | ||
| 93 | |||
| 94 | /* how to get the thread information struct from C */ | ||
| 95 | static inline __attribute__((const)) | ||
| 96 | struct thread_info *current_thread_info(void) | ||
| 97 | { | ||
| 98 | struct thread_info *ti; | ||
| 99 | asm("mov sp,%0\n" | ||
| 100 | "and %1,%0\n" | ||
| 101 | : "=d" (ti) | ||
| 102 | : "i" (~(THREAD_SIZE - 1)) | ||
| 103 | : "cc"); | ||
| 104 | return ti; | ||
| 105 | } | ||
| 106 | |||
| 107 | /* how to get the current stack pointer from C */ | ||
| 108 | static inline unsigned long current_stack_pointer(void) | ||
| 109 | { | ||
| 110 | unsigned long sp; | ||
| 111 | asm("mov sp,%0; ":"=r" (sp)); | ||
| 112 | return sp; | ||
| 113 | } | ||
| 114 | |||
| 115 | /* thread information allocation */ | ||
| 116 | #ifdef CONFIG_DEBUG_STACK_USAGE | ||
| 117 | #define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL) | ||
| 118 | #else | ||
| 119 | #define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) | ||
| 120 | #endif | ||
| 121 | |||
| 122 | #define free_thread_info(ti) kfree((ti)) | ||
| 123 | #define get_thread_info(ti) get_task_struct((ti)->task) | ||
| 124 | #define put_thread_info(ti) put_task_struct((ti)->task) | ||
| 125 | |||
| 126 | #else /* !__ASSEMBLY__ */ | ||
| 127 | |||
| 128 | #ifndef __VMLINUX_LDS__ | ||
| 129 | /* how to get the thread information struct from ASM */ | ||
| 130 | .macro GET_THREAD_INFO reg | ||
| 131 | mov sp,\reg | ||
| 132 | and -THREAD_SIZE,\reg | ||
| 133 | .endm | ||
| 134 | #endif | ||
| 135 | #endif | ||
| 136 | |||
| 137 | /* | ||
| 138 | * thread information flags | ||
| 139 | * - these are process state flags that various assembly files may need to | ||
| 140 | * access | ||
| 141 | * - pending work-to-be-done flags are in LSW | ||
| 142 | * - other flags in MSW | ||
| 143 | */ | ||
| 144 | #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ | ||
| 145 | #define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ | ||
| 146 | #define TIF_SIGPENDING 2 /* signal pending */ | ||
| 147 | #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ | ||
| 148 | #define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */ | ||
| 149 | #define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ | ||
| 150 | #define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ | ||
| 151 | #define TIF_MEMDIE 17 /* OOM killer killed process */ | ||
| 152 | #define TIF_FREEZE 18 /* freezing for suspend */ | ||
| 153 | |||
| 154 | #define _TIF_SYSCALL_TRACE +(1 << TIF_SYSCALL_TRACE) | ||
| 155 | #define _TIF_NOTIFY_RESUME +(1 << TIF_NOTIFY_RESUME) | ||
| 156 | #define _TIF_SIGPENDING +(1 << TIF_SIGPENDING) | ||
| 157 | #define _TIF_NEED_RESCHED +(1 << TIF_NEED_RESCHED) | ||
| 158 | #define _TIF_SINGLESTEP +(1 << TIF_SINGLESTEP) | ||
| 159 | #define _TIF_RESTORE_SIGMASK +(1 << TIF_RESTORE_SIGMASK) | ||
| 160 | #define _TIF_POLLING_NRFLAG +(1 << TIF_POLLING_NRFLAG) | ||
| 161 | #define _TIF_FREEZE +(1 << TIF_FREEZE) | ||
| 162 | |||
| 163 | #define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ | ||
| 164 | #define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */ | ||
| 165 | |||
| 166 | #endif /* __KERNEL__ */ | ||
| 167 | |||
| 168 | #endif /* _ASM_THREAD_INFO_H */ | ||
diff --git a/include/asm-mn10300/timer-regs.h b/include/asm-mn10300/timer-regs.h new file mode 100644 index 000000000000..1d883b7f94ab --- /dev/null +++ b/include/asm-mn10300/timer-regs.h | |||
| @@ -0,0 +1,293 @@ | |||
| 1 | /* AM33v2 on-board timer module registers | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_TIMER_REGS_H | ||
| 13 | #define _ASM_TIMER_REGS_H | ||
| 14 | |||
| 15 | #include <asm/cpu-regs.h> | ||
| 16 | #include <asm/intctl-regs.h> | ||
| 17 | |||
| 18 | #ifdef __KERNEL__ | ||
| 19 | |||
| 20 | /* timer prescalar control */ | ||
| 21 | #define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */ | ||
| 22 | #define TMPSCNT_ENABLE 0x80 /* timer prescaler enable */ | ||
| 23 | #define TMPSCNT_DISABLE 0x00 /* timer prescaler disable */ | ||
| 24 | |||
| 25 | /* 8 bit timers */ | ||
| 26 | #define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */ | ||
| 27 | #define TM0MD_SRC 0x07 /* timer source */ | ||
| 28 | #define TM0MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 29 | #define TM0MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 30 | #define TM0MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 31 | #define TM0MD_SRC_TM2IO 0x03 /* - TM2IO pin input */ | ||
| 32 | #define TM0MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ | ||
| 33 | #define TM0MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ | ||
| 34 | #define TM0MD_SRC_TM0IO 0x07 /* - TM0IO pin input */ | ||
| 35 | #define TM0MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 36 | #define TM0MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 37 | |||
| 38 | #define TM1MD __SYSREG(0xd4003001, u8) /* timer 1 mode register */ | ||
| 39 | #define TM1MD_SRC 0x07 /* timer source */ | ||
| 40 | #define TM1MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 41 | #define TM1MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 42 | #define TM1MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 43 | #define TM1MD_SRC_TM0CASCADE 0x03 /* - cascade with timer 0 */ | ||
| 44 | #define TM1MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ | ||
| 45 | #define TM1MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ | ||
| 46 | #define TM1MD_SRC_TM1IO 0x07 /* - TM1IO pin input */ | ||
| 47 | #define TM1MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 48 | #define TM1MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 49 | |||
| 50 | #define TM2MD __SYSREG(0xd4003002, u8) /* timer 2 mode register */ | ||
| 51 | #define TM2MD_SRC 0x07 /* timer source */ | ||
| 52 | #define TM2MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 53 | #define TM2MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 54 | #define TM2MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 55 | #define TM2MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 1 */ | ||
| 56 | #define TM2MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ | ||
| 57 | #define TM2MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ | ||
| 58 | #define TM2MD_SRC_TM2IO 0x07 /* - TM2IO pin input */ | ||
| 59 | #define TM2MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 60 | #define TM2MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 61 | |||
| 62 | #define TM3MD __SYSREG(0xd4003003, u8) /* timer 3 mode register */ | ||
| 63 | #define TM3MD_SRC 0x07 /* timer source */ | ||
| 64 | #define TM3MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 65 | #define TM3MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 66 | #define TM3MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 67 | #define TM3MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 2 */ | ||
| 68 | #define TM3MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ | ||
| 69 | #define TM3MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ | ||
| 70 | #define TM3MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ | ||
| 71 | #define TM3MD_SRC_TM3IO 0x07 /* - TM3IO pin input */ | ||
| 72 | #define TM3MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 73 | #define TM3MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 74 | |||
| 75 | #define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */ | ||
| 76 | |||
| 77 | #define TM0BR __SYSREG(0xd4003010, u8) /* timer 0 base register */ | ||
| 78 | #define TM1BR __SYSREG(0xd4003011, u8) /* timer 1 base register */ | ||
| 79 | #define TM2BR __SYSREG(0xd4003012, u8) /* timer 2 base register */ | ||
| 80 | #define TM3BR __SYSREG(0xd4003013, u8) /* timer 3 base register */ | ||
| 81 | #define TM01BR __SYSREG(0xd4003010, u16) /* timer 0:1 base register */ | ||
| 82 | |||
| 83 | #define TM0BC __SYSREGC(0xd4003020, u8) /* timer 0 binary counter */ | ||
| 84 | #define TM1BC __SYSREGC(0xd4003021, u8) /* timer 1 binary counter */ | ||
| 85 | #define TM2BC __SYSREGC(0xd4003022, u8) /* timer 2 binary counter */ | ||
| 86 | #define TM3BC __SYSREGC(0xd4003023, u8) /* timer 3 binary counter */ | ||
| 87 | #define TM01BC __SYSREGC(0xd4003020, u16) /* timer 0:1 binary counter */ | ||
| 88 | |||
| 89 | #define TM0IRQ 2 /* timer 0 IRQ */ | ||
| 90 | #define TM1IRQ 3 /* timer 1 IRQ */ | ||
| 91 | #define TM2IRQ 4 /* timer 2 IRQ */ | ||
| 92 | #define TM3IRQ 5 /* timer 3 IRQ */ | ||
| 93 | |||
| 94 | #define TM0ICR GxICR(TM0IRQ) /* timer 0 uflow intr ctrl reg */ | ||
| 95 | #define TM1ICR GxICR(TM1IRQ) /* timer 1 uflow intr ctrl reg */ | ||
| 96 | #define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */ | ||
| 97 | #define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */ | ||
| 98 | |||
| 99 | /* 16-bit timers 4,5 & 7-11 */ | ||
| 100 | #define TM4MD __SYSREG(0xd4003080, u8) /* timer 4 mode register */ | ||
| 101 | #define TM4MD_SRC 0x07 /* timer source */ | ||
| 102 | #define TM4MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 103 | #define TM4MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 104 | #define TM4MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 105 | #define TM4MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ | ||
| 106 | #define TM4MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ | ||
| 107 | #define TM4MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ | ||
| 108 | #define TM4MD_SRC_TM4IO 0x07 /* - TM4IO pin input */ | ||
| 109 | #define TM4MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 110 | #define TM4MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 111 | |||
| 112 | #define TM5MD __SYSREG(0xd4003082, u8) /* timer 5 mode register */ | ||
| 113 | #define TM5MD_SRC 0x07 /* timer source */ | ||
| 114 | #define TM5MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 115 | #define TM5MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 116 | #define TM5MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 117 | #define TM5MD_SRC_TM4CASCADE 0x03 /* - cascade with timer 4 */ | ||
| 118 | #define TM5MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ | ||
| 119 | #define TM5MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ | ||
| 120 | #define TM5MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ | ||
| 121 | #define TM5MD_SRC_TM5IO 0x07 /* - TM5IO pin input */ | ||
| 122 | #define TM5MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 123 | #define TM5MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 124 | |||
| 125 | #define TM7MD __SYSREG(0xd4003086, u8) /* timer 7 mode register */ | ||
| 126 | #define TM7MD_SRC 0x07 /* timer source */ | ||
| 127 | #define TM7MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 128 | #define TM7MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 129 | #define TM7MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 130 | #define TM7MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ | ||
| 131 | #define TM7MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ | ||
| 132 | #define TM7MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ | ||
| 133 | #define TM7MD_SRC_TM7IO 0x07 /* - TM7IO pin input */ | ||
| 134 | #define TM7MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 135 | #define TM7MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 136 | |||
| 137 | #define TM8MD __SYSREG(0xd4003088, u8) /* timer 8 mode register */ | ||
| 138 | #define TM8MD_SRC 0x07 /* timer source */ | ||
| 139 | #define TM8MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 140 | #define TM8MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 141 | #define TM8MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 142 | #define TM8MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */ | ||
| 143 | #define TM8MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ | ||
| 144 | #define TM8MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ | ||
| 145 | #define TM8MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ | ||
| 146 | #define TM8MD_SRC_TM8IO 0x07 /* - TM8IO pin input */ | ||
| 147 | #define TM8MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 148 | #define TM8MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 149 | |||
| 150 | #define TM9MD __SYSREG(0xd400308a, u8) /* timer 9 mode register */ | ||
| 151 | #define TM9MD_SRC 0x07 /* timer source */ | ||
| 152 | #define TM9MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 153 | #define TM9MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 154 | #define TM9MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 155 | #define TM9MD_SRC_TM8CASCADE 0x03 /* - cascade with timer 8 */ | ||
| 156 | #define TM9MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ | ||
| 157 | #define TM9MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ | ||
| 158 | #define TM9MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ | ||
| 159 | #define TM9MD_SRC_TM9IO 0x07 /* - TM9IO pin input */ | ||
| 160 | #define TM9MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 161 | #define TM9MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 162 | |||
| 163 | #define TM10MD __SYSREG(0xd400308c, u8) /* timer 10 mode register */ | ||
| 164 | #define TM10MD_SRC 0x07 /* timer source */ | ||
| 165 | #define TM10MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 166 | #define TM10MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 167 | #define TM10MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 168 | #define TM10MD_SRC_TM9CASCADE 0x03 /* - cascade with timer 9 */ | ||
| 169 | #define TM10MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ | ||
| 170 | #define TM10MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ | ||
| 171 | #define TM10MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ | ||
| 172 | #define TM10MD_SRC_TM10IO 0x07 /* - TM10IO pin input */ | ||
| 173 | #define TM10MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 174 | #define TM10MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 175 | |||
| 176 | #define TM11MD __SYSREG(0xd400308e, u8) /* timer 11 mode register */ | ||
| 177 | #define TM11MD_SRC 0x07 /* timer source */ | ||
| 178 | #define TM11MD_SRC_IOCLK 0x00 /* - IOCLK */ | ||
| 179 | #define TM11MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */ | ||
| 180 | #define TM11MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */ | ||
| 181 | #define TM11MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */ | ||
| 182 | #define TM11MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */ | ||
| 183 | #define TM11MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */ | ||
| 184 | #define TM11MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */ | ||
| 185 | #define TM11MD_SRC_TM11IO 0x07 /* - TM11IO pin input */ | ||
| 186 | #define TM11MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */ | ||
| 187 | #define TM11MD_COUNT_ENABLE 0x80 /* timer count enable */ | ||
| 188 | |||
| 189 | #define TM4BR __SYSREG(0xd4003090, u16) /* timer 4 base register */ | ||
| 190 | #define TM5BR __SYSREG(0xd4003092, u16) /* timer 5 base register */ | ||
| 191 | #define TM7BR __SYSREG(0xd4003096, u16) /* timer 7 base register */ | ||
| 192 | #define TM8BR __SYSREG(0xd4003098, u16) /* timer 8 base register */ | ||
| 193 | #define TM9BR __SYSREG(0xd400309a, u16) /* timer 9 base register */ | ||
| 194 | #define TM10BR __SYSREG(0xd400309c, u16) /* timer 10 base register */ | ||
| 195 | #define TM11BR __SYSREG(0xd400309e, u16) /* timer 11 base register */ | ||
| 196 | #define TM45BR __SYSREG(0xd4003090, u32) /* timer 4:5 base register */ | ||
| 197 | |||
| 198 | #define TM4BC __SYSREG(0xd40030a0, u16) /* timer 4 binary counter */ | ||
| 199 | #define TM5BC __SYSREG(0xd40030a2, u16) /* timer 5 binary counter */ | ||
| 200 | #define TM45BC __SYSREG(0xd40030a0, u32) /* timer 4:5 binary counter */ | ||
| 201 | |||
| 202 | #define TM7BC __SYSREG(0xd40030a6, u16) /* timer 7 binary counter */ | ||
| 203 | #define TM8BC __SYSREG(0xd40030a8, u16) /* timer 8 binary counter */ | ||
| 204 | #define TM9BC __SYSREG(0xd40030aa, u16) /* timer 9 binary counter */ | ||
| 205 | #define TM10BC __SYSREG(0xd40030ac, u16) /* timer 10 binary counter */ | ||
| 206 | #define TM11BC __SYSREG(0xd40030ae, u16) /* timer 11 binary counter */ | ||
| 207 | |||
| 208 | #define TM4IRQ 6 /* timer 4 IRQ */ | ||
| 209 | #define TM5IRQ 7 /* timer 5 IRQ */ | ||
| 210 | #define TM7IRQ 11 /* timer 7 IRQ */ | ||
| 211 | #define TM8IRQ 12 /* timer 8 IRQ */ | ||
| 212 | #define TM9IRQ 13 /* timer 9 IRQ */ | ||
| 213 | #define TM10IRQ 14 /* timer 10 IRQ */ | ||
| 214 | #define TM11IRQ 15 /* timer 11 IRQ */ | ||
| 215 | |||
| 216 | #define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */ | ||
| 217 | #define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */ | ||
| 218 | #define TM7ICR GxICR(TM7IRQ) /* timer 7 uflow intr ctrl reg */ | ||
| 219 | #define TM8ICR GxICR(TM8IRQ) /* timer 8 uflow intr ctrl reg */ | ||
| 220 | #define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */ | ||
| 221 | #define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */ | ||
| 222 | #define TM11ICR GxICR(TM11IRQ) /* timer 11 uflow intr ctrl reg */ | ||
| 223 | |||
| 224 | /* 16-bit timer 6 */ | ||
| 225 | #define TM6MD __SYSREG(0xd4003084, u16) /* timer6 mode register */ | ||
| 226 | #define TM6MD_SRC 0x0007 /* timer source */ | ||
| 227 | #define TM6MD_SRC_IOCLK 0x0000 /* - IOCLK */ | ||
| 228 | #define TM6MD_SRC_IOCLK_8 0x0001 /* - 1/8 IOCLK */ | ||
| 229 | #define TM6MD_SRC_IOCLK_32 0x0002 /* - 1/32 IOCLK */ | ||
| 230 | #define TM6MD_SRC_TM0UFLOW 0x0004 /* - timer 0 underflow */ | ||
| 231 | #define TM6MD_SRC_TM1UFLOW 0x0005 /* - timer 1 underflow */ | ||
| 232 | #define TM6MD_SRC_TM6IOB_BOTH 0x0006 /* - TM6IOB pin input (both edges) */ | ||
| 233 | #define TM6MD_SRC_TM6IOB_SINGLE 0x0007 /* - TM6IOB pin input (single edge) */ | ||
| 234 | #define TM6MD_CLR_ENABLE 0x0010 /* clear count enable */ | ||
| 235 | #define TM6MD_ONESHOT_ENABLE 0x0040 /* oneshot count */ | ||
| 236 | #define TM6MD_TRIG_ENABLE 0x0080 /* TM6IOB pin trigger enable */ | ||
| 237 | #define TM6MD_PWM 0x3800 /* PWM output mode */ | ||
| 238 | #define TM6MD_PWM_DIS 0x0000 /* - disabled */ | ||
| 239 | #define TM6MD_PWM_10BIT 0x1000 /* - 10 bits mode */ | ||
| 240 | #define TM6MD_PWM_11BIT 0x1800 /* - 11 bits mode */ | ||
| 241 | #define TM6MD_PWM_12BIT 0x3000 /* - 12 bits mode */ | ||
| 242 | #define TM6MD_PWM_14BIT 0x3800 /* - 14 bits mode */ | ||
| 243 | #define TM6MD_INIT_COUNTER 0x4000 /* initialize TMnBC to zero */ | ||
| 244 | #define TM6MD_COUNT_ENABLE 0x8000 /* timer count enable */ | ||
| 245 | |||
| 246 | #define TM6MDA __SYSREG(0xd40030b4, u8) /* timer6 cmp/cap A mode reg */ | ||
| 247 | #define TM6MDA_OUT 0x07 /* output select */ | ||
| 248 | #define TM6MDA_OUT_SETA_RESETB 0x00 /* - set at match A, reset at match B */ | ||
| 249 | #define TM6MDA_OUT_SETA_RESETOV 0x01 /* - set at match A, reset at overflow */ | ||
| 250 | #define TM6MDA_OUT_SETA 0x02 /* - set at match A */ | ||
| 251 | #define TM6MDA_OUT_RESETA 0x03 /* - reset at match A */ | ||
| 252 | #define TM6MDA_OUT_TOGGLE 0x04 /* - toggle on match A */ | ||
| 253 | #define TM6MDA_MODE 0xc0 /* compare A register mode */ | ||
| 254 | #define TM6MDA_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */ | ||
| 255 | #define TM6MDA_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */ | ||
| 256 | #define TM6MDA_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */ | ||
| 257 | #define TM6MDA_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */ | ||
| 258 | #define TM6MDA_EDGE 0x20 /* compare A edge select */ | ||
| 259 | #define TM6MDA_EDGE_FALLING 0x00 /* capture on falling edge */ | ||
| 260 | #define TM6MDA_EDGE_RISING 0x20 /* capture on rising edge */ | ||
| 261 | #define TM6MDA_CAPTURE_ENABLE 0x10 /* capture enable */ | ||
| 262 | |||
| 263 | #define TM6MDB __SYSREG(0xd40030b5, u8) /* timer6 cmp/cap B mode reg */ | ||
| 264 | #define TM6MDB_OUT 0x07 /* output select */ | ||
| 265 | #define TM6MDB_OUT_SETB_RESETA 0x00 /* - set at match B, reset at match A */ | ||
| 266 | #define TM6MDB_OUT_SETB_RESETOV 0x01 /* - set at match B */ | ||
| 267 | #define TM6MDB_OUT_RESETB 0x03 /* - reset at match B */ | ||
| 268 | #define TM6MDB_OUT_TOGGLE 0x04 /* - toggle on match B */ | ||
| 269 | #define TM6MDB_MODE 0xc0 /* compare B register mode */ | ||
| 270 | #define TM6MDB_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */ | ||
| 271 | #define TM6MDB_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */ | ||
| 272 | #define TM6MDB_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */ | ||
| 273 | #define TM6MDB_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */ | ||
| 274 | #define TM6MDB_EDGE 0x20 /* compare B edge select */ | ||
| 275 | #define TM6MDB_EDGE_FALLING 0x00 /* capture on falling edge */ | ||
| 276 | #define TM6MDB_EDGE_RISING 0x20 /* capture on rising edge */ | ||
| 277 | #define TM6MDB_CAPTURE_ENABLE 0x10 /* capture enable */ | ||
| 278 | |||
| 279 | #define TM6CA __SYSREG(0xd40030c4, u16) /* timer6 cmp/capture reg A */ | ||
| 280 | #define TM6CB __SYSREG(0xd40030d4, u16) /* timer6 cmp/capture reg B */ | ||
| 281 | #define TM6BC __SYSREG(0xd40030a4, u16) /* timer6 binary counter */ | ||
| 282 | |||
| 283 | #define TM6IRQ 6 /* timer 6 IRQ */ | ||
| 284 | #define TM6AIRQ 9 /* timer 6A IRQ */ | ||
| 285 | #define TM6BIRQ 10 /* timer 6B IRQ */ | ||
| 286 | |||
| 287 | #define TM6ICR GxICR(TM6IRQ) /* timer 6 uflow intr ctrl reg */ | ||
| 288 | #define TM6AICR GxICR(TM6AIRQ) /* timer 6A intr control reg */ | ||
| 289 | #define TM6BICR GxICR(TM6BIRQ) /* timer 6B intr control reg */ | ||
| 290 | |||
| 291 | #endif /* __KERNEL__ */ | ||
| 292 | |||
| 293 | #endif /* _ASM_TIMER_REGS_H */ | ||
diff --git a/include/asm-mn10300/timex.h b/include/asm-mn10300/timex.h new file mode 100644 index 000000000000..3944277dab67 --- /dev/null +++ b/include/asm-mn10300/timex.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /* MN10300 Architecture time management specifications | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_TIMEX_H | ||
| 12 | #define _ASM_TIMEX_H | ||
| 13 | |||
| 14 | #include <asm/hardirq.h> | ||
| 15 | #include <asm/unit/timex.h> | ||
| 16 | |||
| 17 | #define TICK_SIZE (tick_nsec / 1000) | ||
| 18 | |||
| 19 | #define CLOCK_TICK_RATE 1193180 /* Underlying HZ - this should probably be set | ||
| 20 | * to something appropriate, but what? */ | ||
| 21 | |||
| 22 | extern cycles_t cacheflush_time; | ||
| 23 | |||
| 24 | #ifdef __KERNEL__ | ||
| 25 | |||
| 26 | static inline cycles_t get_cycles(void) | ||
| 27 | { | ||
| 28 | return read_timestamp_counter(); | ||
| 29 | } | ||
| 30 | |||
| 31 | #endif /* __KERNEL__ */ | ||
| 32 | |||
| 33 | #endif /* _ASM_TIMEX_H */ | ||
diff --git a/include/asm-mn10300/tlb.h b/include/asm-mn10300/tlb.h new file mode 100644 index 000000000000..65d232b96613 --- /dev/null +++ b/include/asm-mn10300/tlb.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* MN10300 TLB definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_TLB_H | ||
| 13 | #define _ASM_TLB_H | ||
| 14 | |||
| 15 | #include <asm/tlbflush.h> | ||
| 16 | |||
| 17 | extern void check_pgt_cache(void); | ||
| 18 | |||
| 19 | /* | ||
| 20 | * we don't need any special per-pte or per-vma handling... | ||
| 21 | */ | ||
| 22 | #define tlb_start_vma(tlb, vma) do { } while (0) | ||
| 23 | #define tlb_end_vma(tlb, vma) do { } while (0) | ||
| 24 | #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) | ||
| 25 | |||
| 26 | /* | ||
| 27 | * .. because we flush the whole mm when it fills up | ||
| 28 | */ | ||
| 29 | #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) | ||
| 30 | |||
| 31 | /* for now, just use the generic stuff */ | ||
| 32 | #include <asm-generic/tlb.h> | ||
| 33 | |||
| 34 | #endif /* _ASM_TLB_H */ | ||
diff --git a/include/asm-mn10300/tlbflush.h b/include/asm-mn10300/tlbflush.h new file mode 100644 index 000000000000..e0239865abcb --- /dev/null +++ b/include/asm-mn10300/tlbflush.h | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | /* MN10300 TLB flushing functions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_TLBFLUSH_H | ||
| 12 | #define _ASM_TLBFLUSH_H | ||
| 13 | |||
| 14 | #include <asm/processor.h> | ||
| 15 | |||
| 16 | #define __flush_tlb() \ | ||
| 17 | do { \ | ||
| 18 | int w; \ | ||
| 19 | __asm__ __volatile__ \ | ||
| 20 | (" mov %1,%0 \n" \ | ||
| 21 | " or %2,%0 \n" \ | ||
| 22 | " mov %0,%1 \n" \ | ||
| 23 | : "=d"(w) \ | ||
| 24 | : "m"(MMUCTR), "i"(MMUCTR_IIV|MMUCTR_DIV) \ | ||
| 25 | : "memory" \ | ||
| 26 | ); \ | ||
| 27 | } while (0) | ||
| 28 | |||
| 29 | #define __flush_tlb_all() __flush_tlb() | ||
| 30 | #define __flush_tlb_one(addr) __flush_tlb() | ||
| 31 | |||
| 32 | |||
| 33 | /* | ||
| 34 | * TLB flushing: | ||
| 35 | * | ||
| 36 | * - flush_tlb() flushes the current mm struct TLBs | ||
| 37 | * - flush_tlb_all() flushes all processes TLBs | ||
| 38 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's | ||
| 39 | * - flush_tlb_page(vma, vmaddr) flushes one page | ||
| 40 | * - flush_tlb_range(mm, start, end) flushes a range of pages | ||
| 41 | * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables | ||
| 42 | */ | ||
| 43 | #define flush_tlb_all() \ | ||
| 44 | do { \ | ||
| 45 | preempt_disable(); \ | ||
| 46 | __flush_tlb_all(); \ | ||
| 47 | preempt_enable(); \ | ||
| 48 | } while (0) | ||
| 49 | |||
| 50 | #define flush_tlb_mm(mm) \ | ||
| 51 | do { \ | ||
| 52 | preempt_disable(); \ | ||
| 53 | __flush_tlb_all(); \ | ||
| 54 | preempt_enable(); \ | ||
| 55 | } while (0) | ||
| 56 | |||
| 57 | #define flush_tlb_range(vma, start, end) \ | ||
| 58 | do { \ | ||
| 59 | unsigned long __s __attribute__((unused)) = (start); \ | ||
| 60 | unsigned long __e __attribute__((unused)) = (end); \ | ||
| 61 | preempt_disable(); \ | ||
| 62 | __flush_tlb_all(); \ | ||
| 63 | preempt_enable(); \ | ||
| 64 | } while (0) | ||
| 65 | |||
| 66 | |||
| 67 | #define __flush_tlb_global() flush_tlb_all() | ||
| 68 | #define flush_tlb() flush_tlb_all() | ||
| 69 | #define flush_tlb_kernel_range(start, end) \ | ||
| 70 | do { \ | ||
| 71 | unsigned long __s __attribute__((unused)) = (start); \ | ||
| 72 | unsigned long __e __attribute__((unused)) = (end); \ | ||
| 73 | flush_tlb_all(); \ | ||
| 74 | } while (0) | ||
| 75 | |||
| 76 | extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); | ||
| 77 | |||
| 78 | #define flush_tlb_pgtables(mm, start, end) do {} while (0) | ||
| 79 | |||
| 80 | #endif /* _ASM_TLBFLUSH_H */ | ||
diff --git a/include/asm-mn10300/topology.h b/include/asm-mn10300/topology.h new file mode 100644 index 000000000000..5428f333a02c --- /dev/null +++ b/include/asm-mn10300/topology.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/topology.h> | |||
diff --git a/include/asm-mn10300/types.h b/include/asm-mn10300/types.h new file mode 100644 index 000000000000..d40ea7628bfc --- /dev/null +++ b/include/asm-mn10300/types.h | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | /* MN10300 Basic type definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_TYPES_H | ||
| 12 | #define _ASM_TYPES_H | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | |||
| 16 | typedef unsigned short umode_t; | ||
| 17 | |||
| 18 | /* | ||
| 19 | * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the | ||
| 20 | * header files exported to user space | ||
| 21 | */ | ||
| 22 | |||
| 23 | typedef __signed__ char __s8; | ||
| 24 | typedef unsigned char __u8; | ||
| 25 | |||
| 26 | typedef __signed__ short __s16; | ||
| 27 | typedef unsigned short __u16; | ||
| 28 | |||
| 29 | typedef __signed__ int __s32; | ||
| 30 | typedef unsigned int __u32; | ||
| 31 | |||
| 32 | #if defined(__GNUC__) && !defined(__STRICT_ANSI__) | ||
| 33 | typedef __signed__ long long __s64; | ||
| 34 | typedef unsigned long long __u64; | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #endif /* __ASSEMBLY__ */ | ||
| 38 | |||
| 39 | /* | ||
| 40 | * These aren't exported outside the kernel to avoid name space clashes | ||
| 41 | */ | ||
| 42 | #ifdef __KERNEL__ | ||
| 43 | |||
| 44 | #define BITS_PER_LONG 32 | ||
| 45 | |||
| 46 | #ifndef __ASSEMBLY__ | ||
| 47 | |||
| 48 | typedef signed char s8; | ||
| 49 | typedef unsigned char u8; | ||
| 50 | |||
| 51 | typedef signed short s16; | ||
| 52 | typedef unsigned short u16; | ||
| 53 | |||
| 54 | typedef signed int s32; | ||
| 55 | typedef unsigned int u32; | ||
| 56 | |||
| 57 | typedef signed long long s64; | ||
| 58 | typedef unsigned long long u64; | ||
| 59 | |||
| 60 | /* Dma addresses are 32-bits wide. */ | ||
| 61 | typedef u32 dma_addr_t; | ||
| 62 | |||
| 63 | #endif /* __ASSEMBLY__ */ | ||
| 64 | |||
| 65 | #endif /* __KERNEL__ */ | ||
| 66 | |||
| 67 | #endif /* _ASM_TYPES_H */ | ||
diff --git a/include/asm-mn10300/uaccess.h b/include/asm-mn10300/uaccess.h new file mode 100644 index 000000000000..46b9b647f3c3 --- /dev/null +++ b/include/asm-mn10300/uaccess.h | |||
| @@ -0,0 +1,490 @@ | |||
| 1 | /* MN10300 userspace access functions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_UACCESS_H | ||
| 12 | #define _ASM_UACCESS_H | ||
| 13 | |||
| 14 | /* | ||
| 15 | * User space memory access functions | ||
| 16 | */ | ||
| 17 | #include <linux/sched.h> | ||
| 18 | #include <asm/page.h> | ||
| 19 | #include <asm/pgtable.h> | ||
| 20 | #include <asm/errno.h> | ||
| 21 | |||
| 22 | #define VERIFY_READ 0 | ||
| 23 | #define VERIFY_WRITE 1 | ||
| 24 | |||
| 25 | /* | ||
| 26 | * The fs value determines whether argument validity checking should be | ||
| 27 | * performed or not. If get_fs() == USER_DS, checking is performed, with | ||
| 28 | * get_fs() == KERNEL_DS, checking is bypassed. | ||
| 29 | * | ||
| 30 | * For historical reasons, these macros are grossly misnamed. | ||
| 31 | */ | ||
| 32 | |||
| 33 | #define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) | ||
| 34 | |||
| 35 | #define KERNEL_XDS MAKE_MM_SEG(0xBFFFFFFF) | ||
| 36 | #define KERNEL_DS MAKE_MM_SEG(0x9FFFFFFF) | ||
| 37 | #define USER_DS MAKE_MM_SEG(TASK_SIZE) | ||
| 38 | |||
| 39 | #define get_ds() (KERNEL_DS) | ||
| 40 | #define get_fs() (current_thread_info()->addr_limit) | ||
| 41 | #define set_fs(x) (current_thread_info()->addr_limit = (x)) | ||
| 42 | #define __kernel_ds_p() (current_thread_info()->addr_limit.seg == 0x9FFFFFFF) | ||
| 43 | |||
| 44 | #define segment_eq(a, b) ((a).seg == (b).seg) | ||
| 45 | |||
| 46 | #define __addr_ok(addr) \ | ||
| 47 | ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg)) | ||
| 48 | |||
| 49 | /* | ||
| 50 | * check that a range of addresses falls within the current address limit | ||
| 51 | */ | ||
| 52 | static inline int ___range_ok(unsigned long addr, unsigned int size) | ||
| 53 | { | ||
| 54 | int flag = 1, tmp; | ||
| 55 | |||
| 56 | asm(" add %3,%1 \n" /* set C-flag if addr + size > 4Gb */ | ||
| 57 | " bcs 0f \n" | ||
| 58 | " cmp %4,%1 \n" /* jump if addr+size>limit (error) */ | ||
| 59 | " bhi 0f \n" | ||
| 60 | " clr %0 \n" /* mark okay */ | ||
| 61 | "0: \n" | ||
| 62 | : "=r"(flag), "=&r"(tmp) | ||
| 63 | : "1"(addr), "ir"(size), | ||
| 64 | "r"(current_thread_info()->addr_limit.seg), "0"(flag) | ||
| 65 | : "cc" | ||
| 66 | ); | ||
| 67 | |||
| 68 | return flag; | ||
| 69 | } | ||
| 70 | |||
| 71 | #define __range_ok(addr, size) ___range_ok((unsigned long)(addr), (u32)(size)) | ||
| 72 | |||
| 73 | #define access_ok(type, addr, size) (__range_ok((addr), (size)) == 0) | ||
| 74 | #define __access_ok(addr, size) (__range_ok((addr), (size)) == 0) | ||
| 75 | |||
| 76 | static inline int verify_area(int type, const void *addr, unsigned long size) | ||
| 77 | { | ||
| 78 | return access_ok(type, addr, size) ? 0 : -EFAULT; | ||
| 79 | } | ||
| 80 | |||
| 81 | |||
| 82 | /* | ||
| 83 | * The exception table consists of pairs of addresses: the first is the | ||
| 84 | * address of an instruction that is allowed to fault, and the second is | ||
| 85 | * the address at which the program should continue. No registers are | ||
| 86 | * modified, so it is entirely up to the continuation code to figure out | ||
| 87 | * what to do. | ||
| 88 | * | ||
| 89 | * All the routines below use bits of fixup code that are out of line | ||
| 90 | * with the main instruction path. This means when everything is well, | ||
| 91 | * we don't even have to jump over them. Further, they do not intrude | ||
| 92 | * on our cache or tlb entries. | ||
| 93 | */ | ||
| 94 | |||
| 95 | struct exception_table_entry | ||
| 96 | { | ||
| 97 | unsigned long insn, fixup; | ||
| 98 | }; | ||
| 99 | |||
| 100 | /* Returns 0 if exception not found and fixup otherwise. */ | ||
| 101 | extern int fixup_exception(struct pt_regs *regs); | ||
| 102 | |||
| 103 | #define put_user(x, ptr) __put_user_check((x), (ptr), sizeof(*(ptr))) | ||
| 104 | #define get_user(x, ptr) __get_user_check((x), (ptr), sizeof(*(ptr))) | ||
| 105 | |||
| 106 | /* | ||
| 107 | * The "__xxx" versions do not do address space checking, useful when | ||
| 108 | * doing multiple accesses to the same area (the user has to do the | ||
| 109 | * checks by hand with "access_ok()") | ||
| 110 | */ | ||
| 111 | #define __put_user(x, ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr))) | ||
| 112 | #define __get_user(x, ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr))) | ||
| 113 | |||
| 114 | /* | ||
| 115 | * The "xxx_ret" versions return constant specified in third argument, if | ||
| 116 | * something bad happens. These macros can be optimized for the | ||
| 117 | * case of just returning from the function xxx_ret is used. | ||
| 118 | */ | ||
| 119 | |||
| 120 | #define put_user_ret(x, ptr, ret) \ | ||
| 121 | ({ if (put_user((x), (ptr))) return (ret); }) | ||
| 122 | #define get_user_ret(x, ptr, ret) \ | ||
| 123 | ({ if (get_user((x), (ptr))) return (ret); }) | ||
| 124 | #define __put_user_ret(x, ptr, ret) \ | ||
| 125 | ({ if (__put_user((x), (ptr))) return (ret); }) | ||
| 126 | #define __get_user_ret(x, ptr, ret) \ | ||
| 127 | ({ if (__get_user((x), (ptr))) return (ret); }) | ||
| 128 | |||
| 129 | struct __large_struct { unsigned long buf[100]; }; | ||
| 130 | #define __m(x) (*(struct __large_struct *)(x)) | ||
| 131 | |||
| 132 | #define __get_user_nocheck(x, ptr, size) \ | ||
| 133 | ({ \ | ||
| 134 | __typeof(*(ptr)) __gu_val; \ | ||
| 135 | unsigned long __gu_addr; \ | ||
| 136 | int __gu_err; \ | ||
| 137 | __gu_addr = (unsigned long) (ptr); \ | ||
| 138 | switch (size) { \ | ||
| 139 | case 1: __get_user_asm("bu"); break; \ | ||
| 140 | case 2: __get_user_asm("hu"); break; \ | ||
| 141 | case 4: __get_user_asm("" ); break; \ | ||
| 142 | default: __get_user_unknown(); break; \ | ||
| 143 | } \ | ||
| 144 | x = (__typeof__(*(ptr))) __gu_val; \ | ||
| 145 | __gu_err; \ | ||
| 146 | }) | ||
| 147 | |||
| 148 | #define __get_user_check(x, ptr, size) \ | ||
| 149 | ({ \ | ||
| 150 | __typeof__(*(ptr)) __gu_val; \ | ||
| 151 | unsigned long __gu_addr; \ | ||
| 152 | int __gu_err; \ | ||
| 153 | __gu_addr = (unsigned long) (ptr); \ | ||
| 154 | if (likely(__access_ok(__gu_addr,size))) { \ | ||
| 155 | switch (size) { \ | ||
| 156 | case 1: __get_user_asm("bu"); break; \ | ||
| 157 | case 2: __get_user_asm("hu"); break; \ | ||
| 158 | case 4: __get_user_asm("" ); break; \ | ||
| 159 | default: __get_user_unknown(); break; \ | ||
| 160 | } \ | ||
| 161 | } \ | ||
| 162 | else { \ | ||
| 163 | __gu_err = -EFAULT; \ | ||
| 164 | __gu_val = 0; \ | ||
| 165 | } \ | ||
| 166 | x = (__typeof__(*(ptr))) __gu_val; \ | ||
| 167 | __gu_err; \ | ||
| 168 | }) | ||
| 169 | |||
| 170 | #define __get_user_asm(INSN) \ | ||
| 171 | ({ \ | ||
| 172 | asm volatile( \ | ||
| 173 | "1:\n" \ | ||
| 174 | " mov"INSN" %2,%1\n" \ | ||
| 175 | " mov 0,%0\n" \ | ||
| 176 | "2:\n" \ | ||
| 177 | " .section .fixup,\"ax\"\n" \ | ||
| 178 | "3:\n\t" \ | ||
| 179 | " mov %3,%0\n" \ | ||
| 180 | " jmp 2b\n" \ | ||
| 181 | " .previous\n" \ | ||
| 182 | " .section __ex_table,\"a\"\n" \ | ||
| 183 | " .balign 4\n" \ | ||
| 184 | " .long 1b, 3b\n" \ | ||
| 185 | " .previous" \ | ||
| 186 | : "=&r" (__gu_err), "=&r" (__gu_val) \ | ||
| 187 | : "m" (__m(__gu_addr)), "i" (-EFAULT)); \ | ||
| 188 | }) | ||
| 189 | |||
| 190 | extern int __get_user_unknown(void); | ||
| 191 | |||
| 192 | #define __put_user_nocheck(x, ptr, size) \ | ||
| 193 | ({ \ | ||
| 194 | union { \ | ||
| 195 | __typeof__(*(ptr)) val; \ | ||
| 196 | u32 bits[2]; \ | ||
| 197 | } __pu_val; \ | ||
| 198 | unsigned long __pu_addr; \ | ||
| 199 | int __pu_err; \ | ||
| 200 | __pu_val.val = (x); \ | ||
| 201 | __pu_addr = (unsigned long) (ptr); \ | ||
| 202 | switch (size) { \ | ||
| 203 | case 1: __put_user_asm("bu"); break; \ | ||
| 204 | case 2: __put_user_asm("hu"); break; \ | ||
| 205 | case 4: __put_user_asm("" ); break; \ | ||
| 206 | case 8: __put_user_asm8(); break; \ | ||
| 207 | default: __pu_err = __put_user_unknown(); break; \ | ||
| 208 | } \ | ||
| 209 | __pu_err; \ | ||
| 210 | }) | ||
| 211 | |||
| 212 | #define __put_user_check(x, ptr, size) \ | ||
| 213 | ({ \ | ||
| 214 | union { \ | ||
| 215 | __typeof__(*(ptr)) val; \ | ||
| 216 | u32 bits[2]; \ | ||
| 217 | } __pu_val; \ | ||
| 218 | unsigned long __pu_addr; \ | ||
| 219 | int __pu_err; \ | ||
| 220 | __pu_val.val = (x); \ | ||
| 221 | __pu_addr = (unsigned long) (ptr); \ | ||
| 222 | if (likely(__access_ok(__pu_addr, size))) { \ | ||
| 223 | switch (size) { \ | ||
| 224 | case 1: __put_user_asm("bu"); break; \ | ||
| 225 | case 2: __put_user_asm("hu"); break; \ | ||
| 226 | case 4: __put_user_asm("" ); break; \ | ||
| 227 | case 8: __put_user_asm8(); break; \ | ||
| 228 | default: __pu_err = __put_user_unknown(); break; \ | ||
| 229 | } \ | ||
| 230 | } \ | ||
| 231 | else { \ | ||
| 232 | __pu_err = -EFAULT; \ | ||
| 233 | } \ | ||
| 234 | __pu_err; \ | ||
| 235 | }) | ||
| 236 | |||
| 237 | #define __put_user_asm(INSN) \ | ||
| 238 | ({ \ | ||
| 239 | asm volatile( \ | ||
| 240 | "1:\n" \ | ||
| 241 | " mov"INSN" %1,%2\n" \ | ||
| 242 | " mov 0,%0\n" \ | ||
| 243 | "2:\n" \ | ||
| 244 | " .section .fixup,\"ax\"\n" \ | ||
| 245 | "3:\n" \ | ||
| 246 | " mov %3,%0\n" \ | ||
| 247 | " jmp 2b\n" \ | ||
| 248 | " .previous\n" \ | ||
| 249 | " .section __ex_table,\"a\"\n" \ | ||
| 250 | " .balign 4\n" \ | ||
| 251 | " .long 1b, 3b\n" \ | ||
| 252 | " .previous" \ | ||
| 253 | : "=&r" (__pu_err) \ | ||
| 254 | : "r" (__pu_val.val), "m" (__m(__pu_addr)), \ | ||
| 255 | "i" (-EFAULT) \ | ||
| 256 | ); \ | ||
| 257 | }) | ||
| 258 | |||
| 259 | #define __put_user_asm8() \ | ||
| 260 | ({ \ | ||
| 261 | asm volatile( \ | ||
| 262 | "1: mov %1,%3 \n" \ | ||
| 263 | "2: mov %2,%4 \n" \ | ||
| 264 | " mov 0,%0 \n" \ | ||
| 265 | "3: \n" \ | ||
| 266 | " .section .fixup,\"ax\" \n" \ | ||
| 267 | "4: \n" \ | ||
| 268 | " mov %5,%0 \n" \ | ||
| 269 | " jmp 2b \n" \ | ||
| 270 | " .previous \n" \ | ||
| 271 | " .section __ex_table,\"a\"\n" \ | ||
| 272 | " .balign 4 \n" \ | ||
| 273 | " .long 1b, 4b \n" \ | ||
| 274 | " .long 2b, 4b \n" \ | ||
| 275 | " .previous \n" \ | ||
| 276 | : "=&r" (__pu_err) \ | ||
| 277 | : "r" (__pu_val.bits[0]), "r" (__pu_val.bits[1]), \ | ||
| 278 | "m" (__m(__pu_addr)), "m" (__m(__pu_addr+4)), \ | ||
| 279 | "i" (-EFAULT) \ | ||
| 280 | ); \ | ||
| 281 | }) | ||
| 282 | |||
| 283 | extern int __put_user_unknown(void); | ||
| 284 | |||
| 285 | |||
| 286 | /* | ||
| 287 | * Copy To/From Userspace | ||
| 288 | */ | ||
| 289 | /* Generic arbitrary sized copy. */ | ||
| 290 | #define __copy_user(to, from, size) \ | ||
| 291 | do { \ | ||
| 292 | if (size) { \ | ||
| 293 | void *__to = to; \ | ||
| 294 | const void *__from = from; \ | ||
| 295 | int w; \ | ||
| 296 | asm volatile( \ | ||
| 297 | "0: movbu (%0),%3;\n" \ | ||
| 298 | "1: movbu %3,(%1);\n" \ | ||
| 299 | " inc %0;\n" \ | ||
| 300 | " inc %1;\n" \ | ||
| 301 | " add -1,%2;\n" \ | ||
| 302 | " bne 0b;\n" \ | ||
| 303 | "2:\n" \ | ||
| 304 | " .section .fixup,\"ax\"\n" \ | ||
| 305 | "3: jmp 2b\n" \ | ||
| 306 | " .previous\n" \ | ||
| 307 | " .section __ex_table,\"a\"\n" \ | ||
| 308 | " .balign 4\n" \ | ||
| 309 | " .long 0b,3b\n" \ | ||
| 310 | " .long 1b,3b\n" \ | ||
| 311 | " .previous\n" \ | ||
| 312 | : "=a"(__from), "=a"(__to), "=r"(size), "=&r"(w)\ | ||
| 313 | : "0"(__from), "1"(__to), "2"(size) \ | ||
| 314 | : "memory"); \ | ||
| 315 | } \ | ||
| 316 | } while (0) | ||
| 317 | |||
| 318 | #define __copy_user_zeroing(to, from, size) \ | ||
| 319 | do { \ | ||
| 320 | if (size) { \ | ||
| 321 | void *__to = to; \ | ||
| 322 | const void *__from = from; \ | ||
| 323 | int w; \ | ||
| 324 | asm volatile( \ | ||
| 325 | "0: movbu (%0),%3;\n" \ | ||
| 326 | "1: movbu %3,(%1);\n" \ | ||
| 327 | " inc %0;\n" \ | ||
| 328 | " inc %1;\n" \ | ||
| 329 | " add -1,%2;\n" \ | ||
| 330 | " bne 0b;\n" \ | ||
| 331 | "2:\n" \ | ||
| 332 | " .section .fixup,\"ax\"\n" \ | ||
| 333 | "3:\n" \ | ||
| 334 | " mov %2,%0\n" \ | ||
| 335 | " clr %3\n" \ | ||
| 336 | "4: movbu %3,(%1);\n" \ | ||
| 337 | " inc %1;\n" \ | ||
| 338 | " add -1,%2;\n" \ | ||
| 339 | " bne 4b;\n" \ | ||
| 340 | " mov %0,%2\n" \ | ||
| 341 | " jmp 2b\n" \ | ||
| 342 | " .previous\n" \ | ||
| 343 | " .section __ex_table,\"a\"\n" \ | ||
| 344 | " .balign 4\n" \ | ||
| 345 | " .long 0b,3b\n" \ | ||
| 346 | " .long 1b,3b\n" \ | ||
| 347 | " .previous\n" \ | ||
| 348 | : "=a"(__from), "=a"(__to), "=r"(size), "=&r"(w)\ | ||
| 349 | : "0"(__from), "1"(__to), "2"(size) \ | ||
| 350 | : "memory"); \ | ||
| 351 | } \ | ||
| 352 | } while (0) | ||
| 353 | |||
| 354 | /* We let the __ versions of copy_from/to_user inline, because they're often | ||
| 355 | * used in fast paths and have only a small space overhead. | ||
| 356 | */ | ||
| 357 | static inline | ||
| 358 | unsigned long __generic_copy_from_user_nocheck(void *to, const void *from, | ||
| 359 | unsigned long n) | ||
| 360 | { | ||
| 361 | __copy_user_zeroing(to, from, n); | ||
| 362 | return n; | ||
| 363 | } | ||
| 364 | |||
| 365 | static inline | ||
| 366 | unsigned long __generic_copy_to_user_nocheck(void *to, const void *from, | ||
| 367 | unsigned long n) | ||
| 368 | { | ||
| 369 | __copy_user(to, from, n); | ||
| 370 | return n; | ||
| 371 | } | ||
| 372 | |||
| 373 | |||
| 374 | #if 0 | ||
| 375 | #error don't use - these macros don't increment to & from pointers | ||
| 376 | /* Optimize just a little bit when we know the size of the move. */ | ||
| 377 | #define __constant_copy_user(to, from, size) \ | ||
| 378 | do { \ | ||
| 379 | asm volatile( \ | ||
| 380 | " mov %0,a0;\n" \ | ||
| 381 | "0: movbu (%1),d3;\n" \ | ||
| 382 | "1: movbu d3,(%2);\n" \ | ||
| 383 | " add -1,a0;\n" \ | ||
| 384 | " bne 0b;\n" \ | ||
| 385 | "2:;" \ | ||
| 386 | ".section .fixup,\"ax\"\n" \ | ||
| 387 | "3: jmp 2b\n" \ | ||
| 388 | ".previous\n" \ | ||
| 389 | ".section __ex_table,\"a\"\n" \ | ||
| 390 | " .balign 4\n" \ | ||
| 391 | " .long 0b,3b\n" \ | ||
| 392 | " .long 1b,3b\n" \ | ||
| 393 | ".previous" \ | ||
| 394 | : \ | ||
| 395 | : "d"(size), "d"(to), "d"(from) \ | ||
| 396 | : "d3", "a0"); \ | ||
| 397 | } while (0) | ||
| 398 | |||
| 399 | /* Optimize just a little bit when we know the size of the move. */ | ||
| 400 | #define __constant_copy_user_zeroing(to, from, size) \ | ||
| 401 | do { \ | ||
| 402 | asm volatile( \ | ||
| 403 | " mov %0,a0;\n" \ | ||
| 404 | "0: movbu (%1),d3;\n" \ | ||
| 405 | "1: movbu d3,(%2);\n" \ | ||
| 406 | " add -1,a0;\n" \ | ||
| 407 | " bne 0b;\n" \ | ||
| 408 | "2:;" \ | ||
| 409 | ".section .fixup,\"ax\"\n" \ | ||
| 410 | "3: jmp 2b\n" \ | ||
| 411 | ".previous\n" \ | ||
| 412 | ".section __ex_table,\"a\"\n" \ | ||
| 413 | " .balign 4\n" \ | ||
| 414 | " .long 0b,3b\n" \ | ||
| 415 | " .long 1b,3b\n" \ | ||
| 416 | ".previous" \ | ||
| 417 | : \ | ||
| 418 | : "d"(size), "d"(to), "d"(from) \ | ||
| 419 | : "d3", "a0"); \ | ||
| 420 | } while (0) | ||
| 421 | |||
| 422 | static inline | ||
| 423 | unsigned long __constant_copy_to_user(void *to, const void *from, | ||
| 424 | unsigned long n) | ||
| 425 | { | ||
| 426 | if (access_ok(VERIFY_WRITE, to, n)) | ||
| 427 | __constant_copy_user(to, from, n); | ||
| 428 | return n; | ||
| 429 | } | ||
| 430 | |||
| 431 | static inline | ||
| 432 | unsigned long __constant_copy_from_user(void *to, const void *from, | ||
| 433 | unsigned long n) | ||
| 434 | { | ||
| 435 | if (access_ok(VERIFY_READ, from, n)) | ||
| 436 | __constant_copy_user_zeroing(to, from, n); | ||
| 437 | return n; | ||
| 438 | } | ||
| 439 | |||
| 440 | static inline | ||
| 441 | unsigned long __constant_copy_to_user_nocheck(void *to, const void *from, | ||
| 442 | unsigned long n) | ||
| 443 | { | ||
| 444 | __constant_copy_user(to, from, n); | ||
| 445 | return n; | ||
| 446 | } | ||
| 447 | |||
| 448 | static inline | ||
| 449 | unsigned long __constant_copy_from_user_nocheck(void *to, const void *from, | ||
| 450 | unsigned long n) | ||
| 451 | { | ||
| 452 | __constant_copy_user_zeroing(to, from, n); | ||
| 453 | return n; | ||
| 454 | } | ||
| 455 | #endif | ||
| 456 | |||
| 457 | extern unsigned long __generic_copy_to_user(void __user *, const void *, | ||
| 458 | unsigned long); | ||
| 459 | extern unsigned long __generic_copy_from_user(void *, const void __user *, | ||
| 460 | unsigned long); | ||
| 461 | |||
| 462 | #define __copy_to_user_inatomic(to, from, n) \ | ||
| 463 | __generic_copy_to_user_nocheck((to), (from), (n)) | ||
| 464 | #define __copy_from_user_inatomic(to, from, n) \ | ||
| 465 | __generic_copy_from_user_nocheck((to), (from), (n)) | ||
| 466 | |||
| 467 | #define __copy_to_user(to, from, n) \ | ||
| 468 | ({ \ | ||
| 469 | might_sleep(); \ | ||
| 470 | __copy_to_user_inatomic((to), (from), (n)); \ | ||
| 471 | }) | ||
| 472 | |||
| 473 | #define __copy_from_user(to, from, n) \ | ||
| 474 | ({ \ | ||
| 475 | might_sleep(); \ | ||
| 476 | __copy_from_user_inatomic((to), (from), (n)); \ | ||
| 477 | }) | ||
| 478 | |||
| 479 | |||
| 480 | #define copy_to_user(to, from, n) __generic_copy_to_user((to), (from), (n)) | ||
| 481 | #define copy_from_user(to, from, n) __generic_copy_from_user((to), (from), (n)) | ||
| 482 | |||
| 483 | extern long strncpy_from_user(char *dst, const char __user *src, long count); | ||
| 484 | extern long __strncpy_from_user(char *dst, const char __user *src, long count); | ||
| 485 | extern long strnlen_user(const char __user *str, long n); | ||
| 486 | #define strlen_user(str) strnlen_user(str, ~0UL >> 1) | ||
| 487 | extern unsigned long clear_user(void __user *mem, unsigned long len); | ||
| 488 | extern unsigned long __clear_user(void __user *mem, unsigned long len); | ||
| 489 | |||
| 490 | #endif /* _ASM_UACCESS_H */ | ||
diff --git a/include/asm-mn10300/ucontext.h b/include/asm-mn10300/ucontext.h new file mode 100644 index 000000000000..fcab5c1d8e18 --- /dev/null +++ b/include/asm-mn10300/ucontext.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* MN10300 User context | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_UCONTEXT_H | ||
| 12 | #define _ASM_UCONTEXT_H | ||
| 13 | |||
| 14 | struct ucontext { | ||
| 15 | unsigned long uc_flags; | ||
| 16 | struct ucontext *uc_link; | ||
| 17 | stack_t uc_stack; | ||
| 18 | struct sigcontext uc_mcontext; | ||
| 19 | sigset_t uc_sigmask; /* mask last for extensibility */ | ||
| 20 | }; | ||
| 21 | |||
| 22 | #endif /* _ASM_UCONTEXT_H */ | ||
diff --git a/include/asm-mn10300/unaligned.h b/include/asm-mn10300/unaligned.h new file mode 100644 index 000000000000..cad3afbd035f --- /dev/null +++ b/include/asm-mn10300/unaligned.h | |||
| @@ -0,0 +1,136 @@ | |||
| 1 | /* MN10300 Unaligned memory access handling | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_UNALIGNED_H | ||
| 12 | #define _ASM_UNALIGNED_H | ||
| 13 | |||
| 14 | #include <asm/types.h> | ||
| 15 | |||
| 16 | #if 0 | ||
| 17 | extern int __bug_unaligned_x(void *ptr); | ||
| 18 | |||
| 19 | /* | ||
| 20 | * What is the most efficient way of loading/storing an unaligned value? | ||
| 21 | * | ||
| 22 | * That is the subject of this file. Efficiency here is defined as | ||
| 23 | * minimum code size with minimum register usage for the common cases. | ||
| 24 | * It is currently not believed that long longs are common, so we | ||
| 25 | * trade efficiency for the chars, shorts and longs against the long | ||
| 26 | * longs. | ||
| 27 | * | ||
| 28 | * Current stats with gcc 2.7.2.2 for these functions: | ||
| 29 | * | ||
| 30 | * ptrsize get: code regs put: code regs | ||
| 31 | * 1 1 1 1 2 | ||
| 32 | * 2 3 2 3 2 | ||
| 33 | * 4 7 3 7 3 | ||
| 34 | * 8 20 6 16 6 | ||
| 35 | * | ||
| 36 | * gcc 2.95.1 seems to code differently: | ||
| 37 | * | ||
| 38 | * ptrsize get: code regs put: code regs | ||
| 39 | * 1 1 1 1 2 | ||
| 40 | * 2 3 2 3 2 | ||
| 41 | * 4 7 4 7 4 | ||
| 42 | * 8 19 8 15 6 | ||
| 43 | * | ||
| 44 | * which may or may not be more efficient (depending upon whether | ||
| 45 | * you can afford the extra registers). Hopefully the gcc 2.95 | ||
| 46 | * is inteligent enough to decide if it is better to use the | ||
| 47 | * extra register, but evidence so far seems to suggest otherwise. | ||
| 48 | * | ||
| 49 | * Unfortunately, gcc is not able to optimise the high word | ||
| 50 | * out of long long >> 32, or the low word from long long << 32 | ||
| 51 | */ | ||
| 52 | |||
| 53 | #define __get_unaligned_2(__p) \ | ||
| 54 | (__p[0] | __p[1] << 8) | ||
| 55 | |||
| 56 | #define __get_unaligned_4(__p) \ | ||
| 57 | (__p[0] | __p[1] << 8 | __p[2] << 16 | __p[3] << 24) | ||
| 58 | |||
| 59 | #define get_unaligned(ptr) \ | ||
| 60 | ({ \ | ||
| 61 | unsigned int __v1, __v2; \ | ||
| 62 | __typeof__(*(ptr)) __v; \ | ||
| 63 | __u8 *__p = (__u8 *)(ptr); \ | ||
| 64 | \ | ||
| 65 | switch (sizeof(*(ptr))) { \ | ||
| 66 | case 1: __v = *(ptr); break; \ | ||
| 67 | case 2: __v = __get_unaligned_2(__p); break; \ | ||
| 68 | case 4: __v = __get_unaligned_4(__p); break; \ | ||
| 69 | case 8: \ | ||
| 70 | __v2 = __get_unaligned_4((__p+4)); \ | ||
| 71 | __v1 = __get_unaligned_4(__p); \ | ||
| 72 | __v = ((unsigned long long)__v2 << 32 | __v1); \ | ||
| 73 | break; \ | ||
| 74 | default: __v = __bug_unaligned_x(__p); break; \ | ||
| 75 | } \ | ||
| 76 | __v; \ | ||
| 77 | }) | ||
| 78 | |||
| 79 | |||
| 80 | static inline void __put_unaligned_2(__u32 __v, register __u8 *__p) | ||
| 81 | { | ||
| 82 | *__p++ = __v; | ||
| 83 | *__p++ = __v >> 8; | ||
| 84 | } | ||
| 85 | |||
| 86 | static inline void __put_unaligned_4(__u32 __v, register __u8 *__p) | ||
| 87 | { | ||
| 88 | __put_unaligned_2(__v >> 16, __p + 2); | ||
| 89 | __put_unaligned_2(__v, __p); | ||
| 90 | } | ||
| 91 | |||
| 92 | static inline void __put_unaligned_8(const unsigned long long __v, __u8 *__p) | ||
| 93 | { | ||
| 94 | /* | ||
| 95 | * tradeoff: 8 bytes of stack for all unaligned puts (2 | ||
| 96 | * instructions), or an extra register in the long long | ||
| 97 | * case - go for the extra register. | ||
| 98 | */ | ||
| 99 | __put_unaligned_4(__v >> 32, __p + 4); | ||
| 100 | __put_unaligned_4(__v, __p); | ||
| 101 | } | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Try to store an unaligned value as efficiently as possible. | ||
| 105 | */ | ||
| 106 | #define put_unaligned(val, ptr) \ | ||
| 107 | ({ \ | ||
| 108 | switch (sizeof(*(ptr))) { \ | ||
| 109 | case 1: \ | ||
| 110 | *(ptr) = (val); \ | ||
| 111 | break; \ | ||
| 112 | case 2: \ | ||
| 113 | __put_unaligned_2((val), (__u8 *)(ptr)); \ | ||
| 114 | break; \ | ||
| 115 | case 4: \ | ||
| 116 | __put_unaligned_4((val), (__u8 *)(ptr)); \ | ||
| 117 | break; \ | ||
| 118 | case 8: \ | ||
| 119 | __put_unaligned_8((val), (__u8 *)(ptr)); \ | ||
| 120 | break; \ | ||
| 121 | default: \ | ||
| 122 | __bug_unaligned_x(ptr); \ | ||
| 123 | break; \ | ||
| 124 | } \ | ||
| 125 | (void) 0; \ | ||
| 126 | }) | ||
| 127 | |||
| 128 | |||
| 129 | #else | ||
| 130 | |||
| 131 | #define get_unaligned(ptr) (*(ptr)) | ||
| 132 | #define put_unaligned(val, ptr) ({ *(ptr) = (val); (void) 0; }) | ||
| 133 | |||
| 134 | #endif | ||
| 135 | |||
| 136 | #endif | ||
diff --git a/include/asm-mn10300/unistd.h b/include/asm-mn10300/unistd.h new file mode 100644 index 000000000000..3721aa9e195d --- /dev/null +++ b/include/asm-mn10300/unistd.h | |||
| @@ -0,0 +1,384 @@ | |||
| 1 | /* MN10300 System call number list | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_UNISTD_H | ||
| 12 | #define _ASM_UNISTD_H | ||
| 13 | |||
| 14 | #define __NR_restart_syscall 0 | ||
| 15 | #define __NR_exit 1 | ||
| 16 | #define __NR_fork 2 | ||
| 17 | #define __NR_read 3 | ||
| 18 | #define __NR_write 4 | ||
| 19 | #define __NR_open 5 | ||
| 20 | #define __NR_close 6 | ||
| 21 | #define __NR_waitpid 7 | ||
| 22 | #define __NR_creat 8 | ||
| 23 | #define __NR_link 9 | ||
| 24 | #define __NR_unlink 10 | ||
| 25 | #define __NR_execve 11 | ||
| 26 | #define __NR_chdir 12 | ||
| 27 | #define __NR_time 13 | ||
| 28 | #define __NR_mknod 14 | ||
| 29 | #define __NR_chmod 15 | ||
| 30 | #define __NR_lchown 16 | ||
| 31 | #define __NR_break 17 | ||
| 32 | #define __NR_oldstat 18 | ||
| 33 | #define __NR_lseek 19 | ||
| 34 | #define __NR_getpid 20 | ||
| 35 | #define __NR_mount 21 | ||
| 36 | #define __NR_umount 22 | ||
| 37 | #define __NR_setuid 23 | ||
| 38 | #define __NR_getuid 24 | ||
| 39 | #define __NR_stime 25 | ||
| 40 | #define __NR_ptrace 26 | ||
| 41 | #define __NR_alarm 27 | ||
| 42 | #define __NR_oldfstat 28 | ||
| 43 | #define __NR_pause 29 | ||
| 44 | #define __NR_utime 30 | ||
| 45 | #define __NR_stty 31 | ||
| 46 | #define __NR_gtty 32 | ||
| 47 | #define __NR_access 33 | ||
| 48 | #define __NR_nice 34 | ||
| 49 | #define __NR_ftime 35 | ||
| 50 | #define __NR_sync 36 | ||
| 51 | #define __NR_kill 37 | ||
| 52 | #define __NR_rename 38 | ||
| 53 | #define __NR_mkdir 39 | ||
| 54 | #define __NR_rmdir 40 | ||
| 55 | #define __NR_dup 41 | ||
| 56 | #define __NR_pipe 42 | ||
| 57 | #define __NR_times 43 | ||
| 58 | #define __NR_prof 44 | ||
| 59 | #define __NR_brk 45 | ||
| 60 | #define __NR_setgid 46 | ||
| 61 | #define __NR_getgid 47 | ||
| 62 | #define __NR_signal 48 | ||
| 63 | #define __NR_geteuid 49 | ||
| 64 | #define __NR_getegid 50 | ||
| 65 | #define __NR_acct 51 | ||
| 66 | #define __NR_umount2 52 | ||
| 67 | #define __NR_lock 53 | ||
| 68 | #define __NR_ioctl 54 | ||
| 69 | #define __NR_fcntl 55 | ||
| 70 | #define __NR_mpx 56 | ||
| 71 | #define __NR_setpgid 57 | ||
| 72 | #define __NR_ulimit 58 | ||
| 73 | #define __NR_oldolduname 59 | ||
| 74 | #define __NR_umask 60 | ||
| 75 | #define __NR_chroot 61 | ||
| 76 | #define __NR_ustat 62 | ||
| 77 | #define __NR_dup2 63 | ||
| 78 | #define __NR_getppid 64 | ||
| 79 | #define __NR_getpgrp 65 | ||
| 80 | #define __NR_setsid 66 | ||
| 81 | #define __NR_sigaction 67 | ||
| 82 | #define __NR_sgetmask 68 | ||
| 83 | #define __NR_ssetmask 69 | ||
| 84 | #define __NR_setreuid 70 | ||
| 85 | #define __NR_setregid 71 | ||
| 86 | #define __NR_sigsuspend 72 | ||
| 87 | #define __NR_sigpending 73 | ||
| 88 | #define __NR_sethostname 74 | ||
| 89 | #define __NR_setrlimit 75 | ||
| 90 | #define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */ | ||
| 91 | #define __NR_getrusage 77 | ||
| 92 | #define __NR_gettimeofday 78 | ||
| 93 | #define __NR_settimeofday 79 | ||
| 94 | #define __NR_getgroups 80 | ||
| 95 | #define __NR_setgroups 81 | ||
| 96 | #define __NR_select 82 | ||
| 97 | #define __NR_symlink 83 | ||
| 98 | #define __NR_oldlstat 84 | ||
| 99 | #define __NR_readlink 85 | ||
| 100 | #define __NR_uselib 86 | ||
| 101 | #define __NR_swapon 87 | ||
| 102 | #define __NR_reboot 88 | ||
| 103 | #define __NR_readdir 89 | ||
| 104 | #define __NR_mmap 90 | ||
| 105 | #define __NR_munmap 91 | ||
| 106 | #define __NR_truncate 92 | ||
| 107 | #define __NR_ftruncate 93 | ||
| 108 | #define __NR_fchmod 94 | ||
| 109 | #define __NR_fchown 95 | ||
| 110 | #define __NR_getpriority 96 | ||
| 111 | #define __NR_setpriority 97 | ||
| 112 | #define __NR_profil 98 | ||
| 113 | #define __NR_statfs 99 | ||
| 114 | #define __NR_fstatfs 100 | ||
| 115 | #define __NR_ioperm 101 | ||
| 116 | #define __NR_socketcall 102 | ||
| 117 | #define __NR_syslog 103 | ||
| 118 | #define __NR_setitimer 104 | ||
| 119 | #define __NR_getitimer 105 | ||
| 120 | #define __NR_stat 106 | ||
| 121 | #define __NR_lstat 107 | ||
| 122 | #define __NR_fstat 108 | ||
| 123 | #define __NR_olduname 109 | ||
| 124 | #define __NR_iopl 110 | ||
| 125 | #define __NR_vhangup 111 | ||
| 126 | #define __NR_idle 112 | ||
| 127 | #define __NR_vm86old 113 | ||
| 128 | #define __NR_wait4 114 | ||
| 129 | #define __NR_swapoff 115 | ||
| 130 | #define __NR_sysinfo 116 | ||
| 131 | #define __NR_ipc 117 | ||
| 132 | #define __NR_fsync 118 | ||
| 133 | #define __NR_sigreturn 119 | ||
| 134 | #define __NR_clone 120 | ||
| 135 | #define __NR_setdomainname 121 | ||
| 136 | #define __NR_uname 122 | ||
| 137 | #define __NR_modify_ldt 123 | ||
| 138 | #define __NR_adjtimex 124 | ||
| 139 | #define __NR_mprotect 125 | ||
| 140 | #define __NR_sigprocmask 126 | ||
| 141 | #define __NR_create_module 127 | ||
| 142 | #define __NR_init_module 128 | ||
| 143 | #define __NR_delete_module 129 | ||
| 144 | #define __NR_get_kernel_syms 130 | ||
| 145 | #define __NR_quotactl 131 | ||
| 146 | #define __NR_getpgid 132 | ||
| 147 | #define __NR_fchdir 133 | ||
| 148 | #define __NR_bdflush 134 | ||
| 149 | #define __NR_sysfs 135 | ||
| 150 | #define __NR_personality 136 | ||
| 151 | #define __NR_afs_syscall 137 /* Syscall for Andrew File System */ | ||
| 152 | #define __NR_setfsuid 138 | ||
| 153 | #define __NR_setfsgid 139 | ||
| 154 | #define __NR__llseek 140 | ||
| 155 | #define __NR_getdents 141 | ||
| 156 | #define __NR__newselect 142 | ||
| 157 | #define __NR_flock 143 | ||
| 158 | #define __NR_msync 144 | ||
| 159 | #define __NR_readv 145 | ||
| 160 | #define __NR_writev 146 | ||
| 161 | #define __NR_getsid 147 | ||
| 162 | #define __NR_fdatasync 148 | ||
| 163 | #define __NR__sysctl 149 | ||
| 164 | #define __NR_mlock 150 | ||
| 165 | #define __NR_munlock 151 | ||
| 166 | #define __NR_mlockall 152 | ||
| 167 | #define __NR_munlockall 153 | ||
| 168 | #define __NR_sched_setparam 154 | ||
| 169 | #define __NR_sched_getparam 155 | ||
| 170 | #define __NR_sched_setscheduler 156 | ||
| 171 | #define __NR_sched_getscheduler 157 | ||
| 172 | #define __NR_sched_yield 158 | ||
| 173 | #define __NR_sched_get_priority_max 159 | ||
| 174 | #define __NR_sched_get_priority_min 160 | ||
| 175 | #define __NR_sched_rr_get_interval 161 | ||
| 176 | #define __NR_nanosleep 162 | ||
| 177 | #define __NR_mremap 163 | ||
| 178 | #define __NR_setresuid 164 | ||
| 179 | #define __NR_getresuid 165 | ||
| 180 | #define __NR_vm86 166 | ||
| 181 | #define __NR_query_module 167 | ||
| 182 | #define __NR_poll 168 | ||
| 183 | #define __NR_nfsservctl 169 | ||
| 184 | #define __NR_setresgid 170 | ||
| 185 | #define __NR_getresgid 171 | ||
| 186 | #define __NR_prctl 172 | ||
| 187 | #define __NR_rt_sigreturn 173 | ||
| 188 | #define __NR_rt_sigaction 174 | ||
| 189 | #define __NR_rt_sigprocmask 175 | ||
| 190 | #define __NR_rt_sigpending 176 | ||
| 191 | #define __NR_rt_sigtimedwait 177 | ||
| 192 | #define __NR_rt_sigqueueinfo 178 | ||
| 193 | #define __NR_rt_sigsuspend 179 | ||
| 194 | #define __NR_pread64 180 | ||
| 195 | #define __NR_pwrite64 181 | ||
| 196 | #define __NR_chown 182 | ||
| 197 | #define __NR_getcwd 183 | ||
| 198 | #define __NR_capget 184 | ||
| 199 | #define __NR_capset 185 | ||
| 200 | #define __NR_sigaltstack 186 | ||
| 201 | #define __NR_sendfile 187 | ||
| 202 | #define __NR_getpmsg 188 /* some people actually want streams */ | ||
| 203 | #define __NR_putpmsg 189 /* some people actually want streams */ | ||
| 204 | #define __NR_vfork 190 | ||
| 205 | #define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ | ||
| 206 | #define __NR_mmap2 192 | ||
| 207 | #define __NR_truncate64 193 | ||
| 208 | #define __NR_ftruncate64 194 | ||
| 209 | #define __NR_stat64 195 | ||
| 210 | #define __NR_lstat64 196 | ||
| 211 | #define __NR_fstat64 197 | ||
| 212 | #define __NR_lchown32 198 | ||
| 213 | #define __NR_getuid32 199 | ||
| 214 | #define __NR_getgid32 200 | ||
| 215 | #define __NR_geteuid32 201 | ||
| 216 | #define __NR_getegid32 202 | ||
| 217 | #define __NR_setreuid32 203 | ||
| 218 | #define __NR_setregid32 204 | ||
| 219 | #define __NR_getgroups32 205 | ||
| 220 | #define __NR_setgroups32 206 | ||
| 221 | #define __NR_fchown32 207 | ||
| 222 | #define __NR_setresuid32 208 | ||
| 223 | #define __NR_getresuid32 209 | ||
| 224 | #define __NR_setresgid32 210 | ||
| 225 | #define __NR_getresgid32 211 | ||
| 226 | #define __NR_chown32 212 | ||
| 227 | #define __NR_setuid32 213 | ||
| 228 | #define __NR_setgid32 214 | ||
| 229 | #define __NR_setfsuid32 215 | ||
| 230 | #define __NR_setfsgid32 216 | ||
| 231 | #define __NR_pivot_root 217 | ||
| 232 | #define __NR_mincore 218 | ||
| 233 | #define __NR_madvise 219 | ||
| 234 | #define __NR_madvise1 219 /* delete when C lib stub is removed */ | ||
| 235 | #define __NR_getdents64 220 | ||
| 236 | #define __NR_fcntl64 221 | ||
| 237 | /* 223 is unused */ | ||
| 238 | #define __NR_gettid 224 | ||
| 239 | #define __NR_readahead 225 | ||
| 240 | #define __NR_setxattr 226 | ||
| 241 | #define __NR_lsetxattr 227 | ||
| 242 | #define __NR_fsetxattr 228 | ||
| 243 | #define __NR_getxattr 229 | ||
| 244 | #define __NR_lgetxattr 230 | ||
| 245 | #define __NR_fgetxattr 231 | ||
| 246 | #define __NR_listxattr 232 | ||
| 247 | #define __NR_llistxattr 233 | ||
| 248 | #define __NR_flistxattr 234 | ||
| 249 | #define __NR_removexattr 235 | ||
| 250 | #define __NR_lremovexattr 236 | ||
| 251 | #define __NR_fremovexattr 237 | ||
| 252 | #define __NR_tkill 238 | ||
| 253 | #define __NR_sendfile64 239 | ||
| 254 | #define __NR_futex 240 | ||
| 255 | #define __NR_sched_setaffinity 241 | ||
| 256 | #define __NR_sched_getaffinity 242 | ||
| 257 | #define __NR_set_thread_area 243 | ||
| 258 | #define __NR_get_thread_area 244 | ||
| 259 | #define __NR_io_setup 245 | ||
| 260 | #define __NR_io_destroy 246 | ||
| 261 | #define __NR_io_getevents 247 | ||
| 262 | #define __NR_io_submit 248 | ||
| 263 | #define __NR_io_cancel 249 | ||
| 264 | #define __NR_fadvise64 250 | ||
| 265 | |||
| 266 | #define __NR_exit_group 252 | ||
| 267 | #define __NR_lookup_dcookie 253 | ||
| 268 | #define __NR_epoll_create 254 | ||
| 269 | #define __NR_epoll_ctl 255 | ||
| 270 | #define __NR_epoll_wait 256 | ||
| 271 | #define __NR_remap_file_pages 257 | ||
| 272 | #define __NR_set_tid_address 258 | ||
| 273 | #define __NR_timer_create 259 | ||
| 274 | #define __NR_timer_settime (__NR_timer_create+1) | ||
| 275 | #define __NR_timer_gettime (__NR_timer_create+2) | ||
| 276 | #define __NR_timer_getoverrun (__NR_timer_create+3) | ||
| 277 | #define __NR_timer_delete (__NR_timer_create+4) | ||
| 278 | #define __NR_clock_settime (__NR_timer_create+5) | ||
| 279 | #define __NR_clock_gettime (__NR_timer_create+6) | ||
| 280 | #define __NR_clock_getres (__NR_timer_create+7) | ||
| 281 | #define __NR_clock_nanosleep (__NR_timer_create+8) | ||
| 282 | #define __NR_statfs64 268 | ||
| 283 | #define __NR_fstatfs64 269 | ||
| 284 | #define __NR_tgkill 270 | ||
| 285 | #define __NR_utimes 271 | ||
| 286 | #define __NR_fadvise64_64 272 | ||
| 287 | #define __NR_vserver 273 | ||
| 288 | #define __NR_mbind 274 | ||
| 289 | #define __NR_get_mempolicy 275 | ||
| 290 | #define __NR_set_mempolicy 276 | ||
| 291 | #define __NR_mq_open 277 | ||
| 292 | #define __NR_mq_unlink (__NR_mq_open+1) | ||
| 293 | #define __NR_mq_timedsend (__NR_mq_open+2) | ||
| 294 | #define __NR_mq_timedreceive (__NR_mq_open+3) | ||
| 295 | #define __NR_mq_notify (__NR_mq_open+4) | ||
| 296 | #define __NR_mq_getsetattr (__NR_mq_open+5) | ||
| 297 | #define __NR_kexec_load 283 | ||
| 298 | #define __NR_waitid 284 | ||
| 299 | #define __NR_add_key 286 | ||
| 300 | #define __NR_request_key 287 | ||
| 301 | #define __NR_keyctl 288 | ||
| 302 | #define __NR_cacheflush 289 | ||
| 303 | #define __NR_ioprio_set 290 | ||
| 304 | #define __NR_ioprio_get 291 | ||
| 305 | #define __NR_inotify_init 292 | ||
| 306 | #define __NR_inotify_add_watch 293 | ||
| 307 | #define __NR_inotify_rm_watch 294 | ||
| 308 | #define __NR_migrate_pages 295 | ||
| 309 | #define __NR_openat 296 | ||
| 310 | #define __NR_mkdirat 297 | ||
| 311 | #define __NR_mknodat 298 | ||
| 312 | #define __NR_fchownat 299 | ||
| 313 | #define __NR_futimesat 300 | ||
| 314 | #define __NR_fstatat64 301 | ||
| 315 | #define __NR_unlinkat 302 | ||
| 316 | #define __NR_renameat 303 | ||
| 317 | #define __NR_linkat 304 | ||
| 318 | #define __NR_symlinkat 305 | ||
| 319 | #define __NR_readlinkat 306 | ||
| 320 | #define __NR_fchmodat 307 | ||
| 321 | #define __NR_faccessat 308 | ||
| 322 | #define __NR_pselect6 309 | ||
| 323 | #define __NR_ppoll 310 | ||
| 324 | #define __NR_unshare 311 | ||
| 325 | #define __NR_set_robust_list 312 | ||
| 326 | #define __NR_get_robust_list 313 | ||
| 327 | #define __NR_splice 314 | ||
| 328 | #define __NR_sync_file_range 315 | ||
| 329 | #define __NR_tee 316 | ||
| 330 | #define __NR_vmsplice 317 | ||
| 331 | #define __NR_move_pages 318 | ||
| 332 | #define __NR_getcpu 319 | ||
| 333 | #define __NR_epoll_pwait 320 | ||
| 334 | #define __NR_utimensat 321 | ||
| 335 | #define __NR_signalfd 322 | ||
| 336 | #define __NR_timerfd_create 323 | ||
| 337 | #define __NR_eventfd 324 | ||
| 338 | #define __NR_fallocate 325 | ||
| 339 | #define __NR_timerfd_settime 326 | ||
| 340 | #define __NR_timerfd_gettime 327 | ||
| 341 | |||
| 342 | #ifdef __KERNEL__ | ||
| 343 | |||
| 344 | #define NR_syscalls 326 | ||
| 345 | |||
| 346 | /* | ||
| 347 | * specify the deprecated syscalls we want to support on this arch | ||
| 348 | */ | ||
| 349 | #define __ARCH_WANT_IPC_PARSE_VERSION | ||
| 350 | #define __ARCH_WANT_OLD_READDIR | ||
| 351 | #define __ARCH_WANT_OLD_STAT | ||
| 352 | #define __ARCH_WANT_STAT64 | ||
| 353 | #define __ARCH_WANT_SYS_ALARM | ||
| 354 | #define __ARCH_WANT_SYS_GETHOSTNAME | ||
| 355 | #define __ARCH_WANT_SYS_PAUSE | ||
| 356 | #define __ARCH_WANT_SYS_SGETMASK | ||
| 357 | #define __ARCH_WANT_SYS_SIGNAL | ||
| 358 | #define __ARCH_WANT_SYS_TIME | ||
| 359 | #define __ARCH_WANT_SYS_UTIME | ||
| 360 | #define __ARCH_WANT_SYS_WAITPID | ||
| 361 | #define __ARCH_WANT_SYS_SOCKETCALL | ||
| 362 | #define __ARCH_WANT_SYS_FADVISE64 | ||
| 363 | #define __ARCH_WANT_SYS_GETPGRP | ||
| 364 | #define __ARCH_WANT_SYS_LLSEEK | ||
| 365 | #define __ARCH_WANT_SYS_NICE | ||
| 366 | #define __ARCH_WANT_SYS_OLD_GETRLIMIT | ||
| 367 | #define __ARCH_WANT_SYS_OLDUMOUNT | ||
| 368 | #define __ARCH_WANT_SYS_SIGPENDING | ||
| 369 | #define __ARCH_WANT_SYS_SIGPROCMASK | ||
| 370 | #define __ARCH_WANT_SYS_RT_SIGACTION | ||
| 371 | #define __ARCH_WANT_SYS_RT_SIGSUSPEND | ||
| 372 | |||
| 373 | /* | ||
| 374 | * "Conditional" syscalls | ||
| 375 | * | ||
| 376 | * What we want is __attribute__((weak,alias("sys_ni_syscall"))), | ||
| 377 | * but it doesn't work on all toolchains, so we just do it by hand | ||
| 378 | */ | ||
| 379 | #ifndef cond_syscall | ||
| 380 | #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall"); | ||
| 381 | #endif | ||
| 382 | |||
| 383 | #endif /* __KERNEL__ */ | ||
| 384 | #endif /* _ASM_UNISTD_H */ | ||
diff --git a/include/asm-mn10300/unit-asb2303/clock.h b/include/asm-mn10300/unit-asb2303/clock.h new file mode 100644 index 000000000000..8b450e920af1 --- /dev/null +++ b/include/asm-mn10300/unit-asb2303/clock.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* ASB2303-specific clocks | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_UNIT_CLOCK_H | ||
| 13 | #define _ASM_UNIT_CLOCK_H | ||
| 14 | |||
| 15 | #ifndef __ASSEMBLY__ | ||
| 16 | |||
| 17 | #ifdef CONFIG_MN10300_RTC | ||
| 18 | |||
| 19 | extern unsigned long mn10300_ioclk; /* IOCLK (crystal speed) in HZ */ | ||
| 20 | extern unsigned long mn10300_iobclk; | ||
| 21 | extern unsigned long mn10300_tsc_per_HZ; | ||
| 22 | |||
| 23 | #define MN10300_IOCLK ((unsigned long)mn10300_ioclk) | ||
| 24 | /* If this processors has a another clock, uncomment the below. */ | ||
| 25 | /* #define MN10300_IOBCLK ((unsigned long)mn10300_iobclk) */ | ||
| 26 | |||
| 27 | #else /* !CONFIG_MN10300_RTC */ | ||
| 28 | |||
| 29 | #define MN10300_IOCLK 33333333UL | ||
| 30 | /* #define MN10300_IOBCLK 66666666UL */ | ||
| 31 | |||
| 32 | #endif /* !CONFIG_MN10300_RTC */ | ||
| 33 | |||
| 34 | #define MN10300_JCCLK MN10300_IOCLK | ||
| 35 | #define MN10300_TSCCLK MN10300_IOCLK | ||
| 36 | |||
| 37 | #ifdef CONFIG_MN10300_RTC | ||
| 38 | #define MN10300_TSC_PER_HZ ((unsigned long)mn10300_tsc_per_HZ) | ||
| 39 | #else /* !CONFIG_MN10300_RTC */ | ||
| 40 | #define MN10300_TSC_PER_HZ (MN10300_TSCCLK/HZ) | ||
| 41 | #endif /* !CONFIG_MN10300_RTC */ | ||
| 42 | |||
| 43 | #endif /* !__ASSEMBLY__ */ | ||
| 44 | |||
| 45 | #endif /* _ASM_UNIT_CLOCK_H */ | ||
diff --git a/include/asm-mn10300/unit-asb2303/leds.h b/include/asm-mn10300/unit-asb2303/leds.h new file mode 100644 index 000000000000..3a7543ea7b5c --- /dev/null +++ b/include/asm-mn10300/unit-asb2303/leds.h | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /* ASB2303-specific LEDs | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_UNIT_LEDS_H | ||
| 13 | #define _ASM_UNIT_LEDS_H | ||
| 14 | |||
| 15 | #include <asm/pio-regs.h> | ||
| 16 | #include <asm/cpu-regs.h> | ||
| 17 | #include <asm/exceptions.h> | ||
| 18 | |||
| 19 | #define ASB2303_GPIO0DEF __SYSREG(0xDB000000, u32) | ||
| 20 | #define ASB2303_7SEGLEDS __SYSREG(0xDB000008, u32) | ||
| 21 | |||
| 22 | /* | ||
| 23 | * use the 7-segment LEDs to indicate states | ||
| 24 | */ | ||
| 25 | |||
| 26 | /* flip the 7-segment LEDs between "G" and "-" */ | ||
| 27 | #define mn10300_set_gdbleds(ONOFF) \ | ||
| 28 | do { \ | ||
| 29 | ASB2303_7SEGLEDS = (ONOFF) ? 0x85 : 0x7f; \ | ||
| 30 | } while (0) | ||
| 31 | |||
| 32 | /* indicate double-fault by displaying "d" on the LEDs */ | ||
| 33 | #define mn10300_set_dbfleds \ | ||
| 34 | mov 0x43,d0 ; \ | ||
| 35 | movbu d0,(ASB2303_7SEGLEDS) | ||
| 36 | |||
| 37 | #ifndef __ASSEMBLY__ | ||
| 38 | extern void peripheral_leds_display_exception(enum exception_code code); | ||
| 39 | extern void peripheral_leds_led_chase(void); | ||
| 40 | extern void debug_to_serial(const char *p, int n); | ||
| 41 | #endif /* __ASSEMBLY__ */ | ||
| 42 | |||
| 43 | #endif /* _ASM_UNIT_LEDS_H */ | ||
diff --git a/include/asm-mn10300/unit-asb2303/serial.h b/include/asm-mn10300/unit-asb2303/serial.h new file mode 100644 index 000000000000..0d55cf5896ac --- /dev/null +++ b/include/asm-mn10300/unit-asb2303/serial.h | |||
| @@ -0,0 +1,136 @@ | |||
| 1 | /* ASB2303-specific 8250 serial ports | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_UNIT_SERIAL_H | ||
| 13 | #define _ASM_UNIT_SERIAL_H | ||
| 14 | |||
| 15 | #include <asm/cpu-regs.h> | ||
| 16 | #include <asm/proc/irq.h> | ||
| 17 | #include <linux/serial_reg.h> | ||
| 18 | |||
| 19 | #define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000 | ||
| 20 | #define SERIAL_PORT1_BASE_ADDRESS 0xA6FC0000 | ||
| 21 | |||
| 22 | #define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */ | ||
| 23 | |||
| 24 | /* | ||
| 25 | * dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports | ||
| 26 | */ | ||
| 27 | #ifndef CONFIG_GDBSTUB_ON_TTYSx | ||
| 28 | |||
| 29 | #define SERIAL_PORT_DFNS \ | ||
| 30 | { \ | ||
| 31 | .baud_base = BASE_BAUD, \ | ||
| 32 | .irq = SERIAL_IRQ, \ | ||
| 33 | .flags = STD_COM_FLAGS, \ | ||
| 34 | .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \ | ||
| 35 | .iomem_reg_shift = 2, \ | ||
| 36 | .io_type = SERIAL_IO_MEM, \ | ||
| 37 | }, \ | ||
| 38 | { \ | ||
| 39 | .baud_base = BASE_BAUD, \ | ||
| 40 | .irq = SERIAL_IRQ, \ | ||
| 41 | .flags = STD_COM_FLAGS, \ | ||
| 42 | .iomem_base = (u8 *) SERIAL_PORT1_BASE_ADDRESS, \ | ||
| 43 | .iomem_reg_shift = 2, \ | ||
| 44 | .io_type = SERIAL_IO_MEM, \ | ||
| 45 | }, | ||
| 46 | |||
| 47 | #ifndef __ASSEMBLY__ | ||
| 48 | |||
| 49 | static inline void __debug_to_serial(const char *p, int n) | ||
| 50 | { | ||
| 51 | } | ||
| 52 | |||
| 53 | #endif /* !__ASSEMBLY__ */ | ||
| 54 | |||
| 55 | #else /* CONFIG_GDBSTUB_ON_TTYSx */ | ||
| 56 | |||
| 57 | #define SERIAL_PORT_DFNS /* both stolen by gdb-stub because they share an IRQ */ | ||
| 58 | |||
| 59 | #if defined(CONFIG_GDBSTUB_ON_TTYS0) | ||
| 60 | #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8) | ||
| 61 | #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8) | ||
| 62 | #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8) | ||
| 63 | #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8) | ||
| 64 | #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8) | ||
| 65 | #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8) | ||
| 66 | #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8) | ||
| 67 | #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8) | ||
| 68 | #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8) | ||
| 69 | #define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8) | ||
| 70 | #define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8) | ||
| 71 | #define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8) | ||
| 72 | #define GDBPORT_SERIAL_IRQ SERIAL_IRQ | ||
| 73 | |||
| 74 | #elif defined(CONFIG_GDBSTUB_ON_TTYS1) | ||
| 75 | #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_RX * 4, u8) | ||
| 76 | #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_TX * 4, u8) | ||
| 77 | #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLL * 4, u8) | ||
| 78 | #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLM * 4, u8) | ||
| 79 | #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IER * 4, u8) | ||
| 80 | #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IIR * 4, u8) | ||
| 81 | #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_FCR * 4, u8) | ||
| 82 | #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LCR * 4, u8) | ||
| 83 | #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MCR * 4, u8) | ||
| 84 | #define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LSR * 4, u8) | ||
| 85 | #define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MSR * 4, u8) | ||
| 86 | #define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_SCR * 4, u8) | ||
| 87 | #define GDBPORT_SERIAL_IRQ SERIAL_IRQ | ||
| 88 | #endif | ||
| 89 | |||
| 90 | #ifndef __ASSEMBLY__ | ||
| 91 | |||
| 92 | #define LSR_WAIT_FOR(STATE) \ | ||
| 93 | do { \ | ||
| 94 | while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE)) {} \ | ||
| 95 | } while (0) | ||
| 96 | #define FLOWCTL_WAIT_FOR(LINE) \ | ||
| 97 | do { \ | ||
| 98 | while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE)) {} \ | ||
| 99 | } while (0) | ||
| 100 | #define FLOWCTL_CLEAR(LINE) \ | ||
| 101 | do { \ | ||
| 102 | GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; \ | ||
| 103 | } while (0) | ||
| 104 | #define FLOWCTL_SET(LINE) \ | ||
| 105 | do { \ | ||
| 106 | GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; \ | ||
| 107 | } while (0) | ||
| 108 | #define FLOWCTL_QUERY(LINE) ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; }) | ||
| 109 | |||
| 110 | static inline void __debug_to_serial(const char *p, int n) | ||
| 111 | { | ||
| 112 | char ch; | ||
| 113 | |||
| 114 | FLOWCTL_SET(DTR); | ||
| 115 | |||
| 116 | for (; n > 0; n--) { | ||
| 117 | LSR_WAIT_FOR(THRE); | ||
| 118 | FLOWCTL_WAIT_FOR(CTS); | ||
| 119 | |||
| 120 | ch = *p++; | ||
| 121 | if (ch == 0x0a) { | ||
| 122 | GDBPORT_SERIAL_TX = 0x0d; | ||
| 123 | LSR_WAIT_FOR(THRE); | ||
| 124 | FLOWCTL_WAIT_FOR(CTS); | ||
| 125 | } | ||
| 126 | GDBPORT_SERIAL_TX = ch; | ||
| 127 | } | ||
| 128 | |||
| 129 | FLOWCTL_CLEAR(DTR); | ||
| 130 | } | ||
| 131 | |||
| 132 | #endif /* !__ASSEMBLY__ */ | ||
| 133 | |||
| 134 | #endif /* CONFIG_GDBSTUB_ON_TTYSx */ | ||
| 135 | |||
| 136 | #endif /* _ASM_UNIT_SERIAL_H */ | ||
diff --git a/include/asm-mn10300/unit-asb2303/smc91111.h b/include/asm-mn10300/unit-asb2303/smc91111.h new file mode 100644 index 000000000000..dd456e9c513f --- /dev/null +++ b/include/asm-mn10300/unit-asb2303/smc91111.h | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* Support for the SMC91C111 NIC on an ASB2303 | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_UNIT_SMC91111_H | ||
| 12 | #define _ASM_UNIT_SMC91111_H | ||
| 13 | |||
| 14 | #include <asm/intctl-regs.h> | ||
| 15 | |||
| 16 | #define SMC91111_BASE 0xAA000300UL | ||
| 17 | #define SMC91111_BASE_END 0xAA000400UL | ||
| 18 | #define SMC91111_IRQ XIRQ3 | ||
| 19 | |||
| 20 | #define SMC_CAN_USE_8BIT 0 | ||
| 21 | #define SMC_CAN_USE_16BIT 1 | ||
| 22 | #define SMC_CAN_USE_32BIT 0 | ||
| 23 | #define SMC_NOWAIT 1 | ||
| 24 | #define SMC_IRQ_FLAGS (0) | ||
| 25 | |||
| 26 | #if SMC_CAN_USE_8BIT | ||
| 27 | #define SMC_inb(a, r) inb((unsigned long) ((a) + (r))) | ||
| 28 | #define SMC_outb(v, a, r) outb(v, (unsigned long) ((a) + (r))) | ||
| 29 | #endif | ||
| 30 | |||
| 31 | #if SMC_CAN_USE_16BIT | ||
| 32 | #define SMC_inw(a, r) inw((unsigned long) ((a) + (r))) | ||
| 33 | #define SMC_outw(v, a, r) outw(v, (unsigned long) ((a) + (r))) | ||
| 34 | #define SMC_insw(a, r, p, l) insw((unsigned long) ((a) + (r)), (p), (l)) | ||
| 35 | #define SMC_outsw(a, r, p, l) outsw((unsigned long) ((a) + (r)), (p), (l)) | ||
| 36 | #endif | ||
| 37 | |||
| 38 | #if SMC_CAN_USE_32BIT | ||
| 39 | #define SMC_inl(a, r) inl((unsigned long) ((a) + (r))) | ||
| 40 | #define SMC_outl(v, a, r) outl(v, (unsigned long) ((a) + (r))) | ||
| 41 | #define SMC_insl(a, r, p, l) insl((unsigned long) ((a) + (r)), (p), (l)) | ||
| 42 | #define SMC_outsl(a, r, p, l) outsl((unsigned long) ((a) + (r)), (p), (l)) | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | ||
| 46 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | ||
| 47 | |||
| 48 | #define set_irq_type(irq, type) | ||
| 49 | |||
| 50 | #endif /* _ASM_UNIT_SMC91111_H */ | ||
diff --git a/include/asm-mn10300/unit-asb2303/timex.h b/include/asm-mn10300/unit-asb2303/timex.h new file mode 100644 index 000000000000..7e54b0cfdd03 --- /dev/null +++ b/include/asm-mn10300/unit-asb2303/timex.h | |||
| @@ -0,0 +1,135 @@ | |||
| 1 | /* ASB2303-specific timer specifcations | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_UNIT_TIMEX_H | ||
| 12 | #define _ASM_UNIT_TIMEX_H | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #endif /* __ASSEMBLY__ */ | ||
| 17 | |||
| 18 | #include <asm/timer-regs.h> | ||
| 19 | #include <asm/unit/clock.h> | ||
| 20 | |||
| 21 | /* | ||
| 22 | * jiffies counter specifications | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define TMJCBR_MAX 0xffff | ||
| 26 | #define TMJCBC TM01BC | ||
| 27 | |||
| 28 | #define TMJCMD TM01MD | ||
| 29 | #define TMJCBR TM01BR | ||
| 30 | #define TMJCIRQ TM1IRQ | ||
| 31 | #define TMJCICR TM1ICR | ||
| 32 | #define TMJCICR_LEVEL GxICR_LEVEL_5 | ||
| 33 | |||
| 34 | #ifndef __ASSEMBLY__ | ||
| 35 | |||
| 36 | static inline void startup_jiffies_counter(void) | ||
| 37 | { | ||
| 38 | unsigned rate; | ||
| 39 | u16 md, t16; | ||
| 40 | |||
| 41 | /* use as little prescaling as possible to avoid losing accuracy */ | ||
| 42 | md = TM0MD_SRC_IOCLK; | ||
| 43 | rate = MN10300_JCCLK / HZ; | ||
| 44 | |||
| 45 | if (rate > TMJCBR_MAX) { | ||
| 46 | md = TM0MD_SRC_IOCLK_8; | ||
| 47 | rate = MN10300_JCCLK / 8 / HZ; | ||
| 48 | |||
| 49 | if (rate > TMJCBR_MAX) { | ||
| 50 | md = TM0MD_SRC_IOCLK_32; | ||
| 51 | rate = MN10300_JCCLK / 32 / HZ; | ||
| 52 | |||
| 53 | if (rate > TMJCBR_MAX) | ||
| 54 | BUG(); | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | TMJCBR = rate - 1; | ||
| 59 | t16 = TMJCBR; | ||
| 60 | |||
| 61 | TMJCMD = | ||
| 62 | md | | ||
| 63 | TM1MD_SRC_TM0CASCADE << 8 | | ||
| 64 | TM0MD_INIT_COUNTER | | ||
| 65 | TM1MD_INIT_COUNTER << 8; | ||
| 66 | |||
| 67 | TMJCMD = | ||
| 68 | md | | ||
| 69 | TM1MD_SRC_TM0CASCADE << 8 | | ||
| 70 | TM0MD_COUNT_ENABLE | | ||
| 71 | TM1MD_COUNT_ENABLE << 8; | ||
| 72 | |||
| 73 | t16 = TMJCMD; | ||
| 74 | |||
| 75 | TMJCICR |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST; | ||
| 76 | t16 = TMJCICR; | ||
| 77 | } | ||
| 78 | |||
| 79 | static inline void shutdown_jiffies_counter(void) | ||
| 80 | { | ||
| 81 | } | ||
| 82 | |||
| 83 | #endif /* !__ASSEMBLY__ */ | ||
| 84 | |||
| 85 | |||
| 86 | /* | ||
| 87 | * timestamp counter specifications | ||
| 88 | */ | ||
| 89 | |||
| 90 | #define TMTSCBR_MAX 0xffffffff | ||
| 91 | #define TMTSCBC TM45BC | ||
| 92 | |||
| 93 | #ifndef __ASSEMBLY__ | ||
| 94 | |||
| 95 | static inline void startup_timestamp_counter(void) | ||
| 96 | { | ||
| 97 | /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time | ||
| 98 | * - count down from 4Gig-1 to 0 and wrap at IOCLK rate | ||
| 99 | */ | ||
| 100 | TM45BR = TMTSCBR_MAX; | ||
| 101 | |||
| 102 | TM4MD = TM4MD_SRC_IOCLK; | ||
| 103 | TM4MD |= TM4MD_INIT_COUNTER; | ||
| 104 | TM4MD &= ~TM4MD_INIT_COUNTER; | ||
| 105 | TM4ICR = 0; | ||
| 106 | |||
| 107 | TM5MD = TM5MD_SRC_TM4CASCADE; | ||
| 108 | TM5MD |= TM5MD_INIT_COUNTER; | ||
| 109 | TM5MD &= ~TM5MD_INIT_COUNTER; | ||
| 110 | TM5ICR = 0; | ||
| 111 | |||
| 112 | TM5MD |= TM5MD_COUNT_ENABLE; | ||
| 113 | TM4MD |= TM4MD_COUNT_ENABLE; | ||
| 114 | } | ||
| 115 | |||
| 116 | static inline void shutdown_timestamp_counter(void) | ||
| 117 | { | ||
| 118 | TM4MD = 0; | ||
| 119 | TM5MD = 0; | ||
| 120 | } | ||
| 121 | |||
| 122 | /* | ||
| 123 | * we use a cascaded pair of 16-bit down-counting timers to count I/O | ||
| 124 | * clock cycles for the purposes of time keeping | ||
| 125 | */ | ||
| 126 | typedef unsigned long cycles_t; | ||
| 127 | |||
| 128 | static inline cycles_t read_timestamp_counter(void) | ||
| 129 | { | ||
| 130 | return (cycles_t)TMTSCBC; | ||
| 131 | } | ||
| 132 | |||
| 133 | #endif /* !__ASSEMBLY__ */ | ||
| 134 | |||
| 135 | #endif /* _ASM_UNIT_TIMEX_H */ | ||
diff --git a/include/asm-mn10300/unit-asb2305/clock.h b/include/asm-mn10300/unit-asb2305/clock.h new file mode 100644 index 000000000000..7d514841ffda --- /dev/null +++ b/include/asm-mn10300/unit-asb2305/clock.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* ASB2305-specific clocks | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_UNIT_CLOCK_H | ||
| 13 | #define _ASM_UNIT_CLOCK_H | ||
| 14 | |||
| 15 | #ifndef __ASSEMBLY__ | ||
| 16 | |||
| 17 | #ifdef CONFIG_MN10300_RTC | ||
| 18 | |||
| 19 | extern unsigned long mn10300_ioclk; /* IOCLK (crystal speed) in HZ */ | ||
| 20 | extern unsigned long mn10300_iobclk; | ||
| 21 | extern unsigned long mn10300_tsc_per_HZ; | ||
| 22 | |||
| 23 | #define MN10300_IOCLK ((unsigned long)mn10300_ioclk) | ||
| 24 | /* If this processors has a another clock, uncomment the below. */ | ||
| 25 | /* #define MN10300_IOBCLK ((unsigned long)mn10300_iobclk) */ | ||
| 26 | |||
| 27 | #else /* !CONFIG_MN10300_RTC */ | ||
| 28 | |||
| 29 | #define MN10300_IOCLK 33333333UL | ||
| 30 | /* #define MN10300_IOBCLK 66666666UL */ | ||
| 31 | |||
| 32 | #endif /* !CONFIG_MN10300_RTC */ | ||
| 33 | |||
| 34 | #define MN10300_JCCLK MN10300_IOCLK | ||
| 35 | #define MN10300_TSCCLK MN10300_IOCLK | ||
| 36 | |||
| 37 | #ifdef CONFIG_MN10300_RTC | ||
| 38 | #define MN10300_TSC_PER_HZ ((unsigned long)mn10300_tsc_per_HZ) | ||
| 39 | #else /* !CONFIG_MN10300_RTC */ | ||
| 40 | #define MN10300_TSC_PER_HZ (MN10300_TSCCLK/HZ) | ||
| 41 | #endif /* !CONFIG_MN10300_RTC */ | ||
| 42 | |||
| 43 | #endif /* !__ASSEMBLY__ */ | ||
| 44 | |||
| 45 | #endif /* _ASM_UNIT_CLOCK_H */ | ||
diff --git a/include/asm-mn10300/unit-asb2305/leds.h b/include/asm-mn10300/unit-asb2305/leds.h new file mode 100644 index 000000000000..bc471f617fd1 --- /dev/null +++ b/include/asm-mn10300/unit-asb2305/leds.h | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | /* ASB2305-specific LEDs | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_UNIT_LEDS_H | ||
| 13 | #define _ASM_UNIT_LEDS_H | ||
| 14 | |||
| 15 | #include <asm/pio-regs.h> | ||
| 16 | #include <asm/cpu-regs.h> | ||
| 17 | #include <asm/exceptions.h> | ||
| 18 | |||
| 19 | #define ASB2305_7SEGLEDS __SYSREG(0xA6F90000, u32) | ||
| 20 | |||
| 21 | /* perform a hard reset by driving PIO06 low */ | ||
| 22 | #define mn10300_unit_hard_reset() \ | ||
| 23 | do { \ | ||
| 24 | P0OUT &= 0xbf; \ | ||
| 25 | P0MD = (P0MD & P0MD_6) | P0MD_6_OUT; \ | ||
| 26 | } while (0) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * use the 7-segment LEDs to indicate states | ||
| 30 | */ | ||
| 31 | /* indicate double-fault by displaying "db-f" on the LEDs */ | ||
| 32 | #define mn10300_set_dbfleds \ | ||
| 33 | mov 0x43077f1d,d0 ; \ | ||
| 34 | mov d0,(ASB2305_7SEGLEDS) | ||
| 35 | |||
| 36 | /* flip the 7-segment LEDs between "Gdb-" and "----" */ | ||
| 37 | #define mn10300_set_gdbleds(ONOFF) \ | ||
| 38 | do { \ | ||
| 39 | ASB2305_7SEGLEDS = (ONOFF) ? 0x8543077f : 0x7f7f7f7f; \ | ||
| 40 | } while (0) | ||
| 41 | |||
| 42 | #ifndef __ASSEMBLY__ | ||
| 43 | extern void peripheral_leds_display_exception(enum exception_code); | ||
| 44 | extern void peripheral_leds_led_chase(void); | ||
| 45 | extern void peripheral_leds7x4_display_dec(unsigned int, unsigned int); | ||
| 46 | extern void peripheral_leds7x4_display_hex(unsigned int, unsigned int); | ||
| 47 | extern void peripheral_leds7x4_display_minssecs(unsigned int, unsigned int); | ||
| 48 | extern void peripheral_leds7x4_display_rtc(void); | ||
| 49 | #endif /* __ASSEMBLY__ */ | ||
| 50 | |||
| 51 | #endif /* _ASM_UNIT_LEDS_H */ | ||
diff --git a/include/asm-mn10300/unit-asb2305/serial.h b/include/asm-mn10300/unit-asb2305/serial.h new file mode 100644 index 000000000000..73d31d67bb71 --- /dev/null +++ b/include/asm-mn10300/unit-asb2305/serial.h | |||
| @@ -0,0 +1,120 @@ | |||
| 1 | /* ASB2305-specific 8250 serial ports | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_UNIT_SERIAL_H | ||
| 12 | #define _ASM_UNIT_SERIAL_H | ||
| 13 | |||
| 14 | #include <asm/cpu/cpu-regs.h> | ||
| 15 | #include <asm/proc/irq.h> | ||
| 16 | #include <linux/serial_reg.h> | ||
| 17 | |||
| 18 | #define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000 | ||
| 19 | #define ASB2305_DEBUG_MCR __SYSREG(0xA6FB0000 + UART_MCR * 2, u8) | ||
| 20 | |||
| 21 | #define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */ | ||
| 22 | |||
| 23 | /* | ||
| 24 | * dispose of the /dev/ttyS0 serial port | ||
| 25 | */ | ||
| 26 | #ifndef CONFIG_GDBSTUB_ON_TTYSx | ||
| 27 | |||
| 28 | #define SERIAL_PORT_DFNS \ | ||
| 29 | { \ | ||
| 30 | .baud_base = BASE_BAUD, \ | ||
| 31 | .irq = SERIAL_IRQ, \ | ||
| 32 | .flags = STD_COM_FLAGS, \ | ||
| 33 | .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \ | ||
| 34 | .iomem_reg_shift = 2, \ | ||
| 35 | .io_type = SERIAL_IO_MEM, \ | ||
| 36 | }, | ||
| 37 | |||
| 38 | #ifndef __ASSEMBLY__ | ||
| 39 | |||
| 40 | static inline void __debug_to_serial(const char *p, int n) | ||
| 41 | { | ||
| 42 | } | ||
| 43 | |||
| 44 | #endif /* !__ASSEMBLY__ */ | ||
| 45 | |||
| 46 | #else /* CONFIG_GDBSTUB_ON_TTYSx */ | ||
| 47 | |||
| 48 | #define SERIAL_PORT_DFNS /* stolen by gdb-stub */ | ||
| 49 | |||
| 50 | #if defined(CONFIG_GDBSTUB_ON_TTYS0) | ||
| 51 | #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8) | ||
| 52 | #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8) | ||
| 53 | #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8) | ||
| 54 | #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8) | ||
| 55 | #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8) | ||
| 56 | #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8) | ||
| 57 | #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8) | ||
| 58 | #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8) | ||
| 59 | #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8) | ||
| 60 | #define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8) | ||
| 61 | #define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8) | ||
| 62 | #define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8) | ||
| 63 | #define GDBPORT_SERIAL_IRQ SERIAL_IRQ | ||
| 64 | |||
| 65 | #elif defined(CONFIG_GDBSTUB_ON_TTYS1) | ||
| 66 | #error The ASB2305 doesnt have a /dev/ttyS1 | ||
| 67 | #endif | ||
| 68 | |||
| 69 | #ifndef __ASSEMBLY__ | ||
| 70 | |||
| 71 | #define TTYS0_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8) | ||
| 72 | #define TTYS0_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8) | ||
| 73 | #define TTYS0_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8) | ||
| 74 | #define TTYS0_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8) | ||
| 75 | |||
| 76 | #define LSR_WAIT_FOR(STATE) \ | ||
| 77 | do { \ | ||
| 78 | while (!(TTYS0_LSR & UART_LSR_##STATE)) {} \ | ||
| 79 | } while (0) | ||
| 80 | #define FLOWCTL_WAIT_FOR(LINE) \ | ||
| 81 | do { \ | ||
| 82 | while (!(TTYS0_MSR & UART_MSR_##LINE)) {} \ | ||
| 83 | } while (0) | ||
| 84 | #define FLOWCTL_CLEAR(LINE) \ | ||
| 85 | do { \ | ||
| 86 | TTYS0_MCR &= ~UART_MCR_##LINE; \ | ||
| 87 | } while (0) | ||
| 88 | #define FLOWCTL_SET(LINE) \ | ||
| 89 | do { \ | ||
| 90 | TTYS0_MCR |= UART_MCR_##LINE; \ | ||
| 91 | } while (0) | ||
| 92 | #define FLOWCTL_QUERY(LINE) ({ TTYS0_MSR & UART_MSR_##LINE; }) | ||
| 93 | |||
| 94 | static inline void __debug_to_serial(const char *p, int n) | ||
| 95 | { | ||
| 96 | char ch; | ||
| 97 | |||
| 98 | FLOWCTL_SET(DTR); | ||
| 99 | |||
| 100 | for (; n > 0; n--) { | ||
| 101 | LSR_WAIT_FOR(THRE); | ||
| 102 | FLOWCTL_WAIT_FOR(CTS); | ||
| 103 | |||
| 104 | ch = *p++; | ||
| 105 | if (ch == 0x0a) { | ||
| 106 | TTYS0_TX = 0x0d; | ||
| 107 | LSR_WAIT_FOR(THRE); | ||
| 108 | FLOWCTL_WAIT_FOR(CTS); | ||
| 109 | } | ||
| 110 | TTYS0_TX = ch; | ||
| 111 | } | ||
| 112 | |||
| 113 | FLOWCTL_CLEAR(DTR); | ||
| 114 | } | ||
| 115 | |||
| 116 | #endif /* !__ASSEMBLY__ */ | ||
| 117 | |||
| 118 | #endif /* CONFIG_GDBSTUB_ON_TTYSx */ | ||
| 119 | |||
| 120 | #endif /* _ASM_UNIT_SERIAL_H */ | ||
diff --git a/include/asm-mn10300/unit-asb2305/timex.h b/include/asm-mn10300/unit-asb2305/timex.h new file mode 100644 index 000000000000..10e1bfe34463 --- /dev/null +++ b/include/asm-mn10300/unit-asb2305/timex.h | |||
| @@ -0,0 +1,135 @@ | |||
| 1 | /* ASB2305 timer specifcations | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_UNIT_TIMEX_H | ||
| 12 | #define _ASM_UNIT_TIMEX_H | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #endif /* __ASSEMBLY__ */ | ||
| 17 | |||
| 18 | #include <asm/cpu/timer-regs.h> | ||
| 19 | #include <asm/unit/clock.h> | ||
| 20 | |||
| 21 | /* | ||
| 22 | * jiffies counter specifications | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define TMJCBR_MAX 0xffff | ||
| 26 | #define TMJCBC TM01BC | ||
| 27 | |||
| 28 | #define TMJCMD TM01MD | ||
| 29 | #define TMJCBR TM01BR | ||
| 30 | #define TMJCIRQ TM1IRQ | ||
| 31 | #define TMJCICR TM1ICR | ||
| 32 | #define TMJCICR_LEVEL GxICR_LEVEL_5 | ||
| 33 | |||
| 34 | #ifndef __ASSEMBLY__ | ||
| 35 | |||
| 36 | static inline void startup_jiffies_counter(void) | ||
| 37 | { | ||
| 38 | unsigned rate; | ||
| 39 | u16 md, t16; | ||
| 40 | |||
| 41 | /* use as little prescaling as possible to avoid losing accuracy */ | ||
| 42 | md = TM0MD_SRC_IOCLK; | ||
| 43 | rate = MN10300_JCCLK / HZ; | ||
| 44 | |||
| 45 | if (rate > TMJCBR_MAX) { | ||
| 46 | md = TM0MD_SRC_IOCLK_8; | ||
| 47 | rate = MN10300_JCCLK / 8 / HZ; | ||
| 48 | |||
| 49 | if (rate > TMJCBR_MAX) { | ||
| 50 | md = TM0MD_SRC_IOCLK_32; | ||
| 51 | rate = MN10300_JCCLK / 32 / HZ; | ||
| 52 | |||
| 53 | if (rate > TMJCBR_MAX) | ||
| 54 | BUG(); | ||
| 55 | } | ||
| 56 | } | ||
| 57 | |||
| 58 | TMJCBR = rate - 1; | ||
| 59 | t16 = TMJCBR; | ||
| 60 | |||
| 61 | TMJCMD = | ||
| 62 | md | | ||
| 63 | TM1MD_SRC_TM0CASCADE << 8 | | ||
| 64 | TM0MD_INIT_COUNTER | | ||
| 65 | TM1MD_INIT_COUNTER << 8; | ||
| 66 | |||
| 67 | TMJCMD = | ||
| 68 | md | | ||
| 69 | TM1MD_SRC_TM0CASCADE << 8 | | ||
| 70 | TM0MD_COUNT_ENABLE | | ||
| 71 | TM1MD_COUNT_ENABLE << 8; | ||
| 72 | |||
| 73 | t16 = TMJCMD; | ||
| 74 | |||
| 75 | TMJCICR |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST; | ||
| 76 | t16 = TMJCICR; | ||
| 77 | } | ||
| 78 | |||
| 79 | static inline void shutdown_jiffies_counter(void) | ||
| 80 | { | ||
| 81 | } | ||
| 82 | |||
| 83 | #endif /* !__ASSEMBLY__ */ | ||
| 84 | |||
| 85 | |||
| 86 | /* | ||
| 87 | * timestamp counter specifications | ||
| 88 | */ | ||
| 89 | |||
| 90 | #define TMTSCBR_MAX 0xffffffff | ||
| 91 | #define TMTSCBC TM45BC | ||
| 92 | |||
| 93 | #ifndef __ASSEMBLY__ | ||
| 94 | |||
| 95 | static inline void startup_timestamp_counter(void) | ||
| 96 | { | ||
| 97 | /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time | ||
| 98 | * - count down from 4Gig-1 to 0 and wrap at IOCLK rate | ||
| 99 | */ | ||
| 100 | TM45BR = TMTSCBR_MAX; | ||
| 101 | |||
| 102 | TM4MD = TM4MD_SRC_IOCLK; | ||
| 103 | TM4MD |= TM4MD_INIT_COUNTER; | ||
| 104 | TM4MD &= ~TM4MD_INIT_COUNTER; | ||
| 105 | TM4ICR = 0; | ||
| 106 | |||
| 107 | TM5MD = TM5MD_SRC_TM4CASCADE; | ||
| 108 | TM5MD |= TM5MD_INIT_COUNTER; | ||
| 109 | TM5MD &= ~TM5MD_INIT_COUNTER; | ||
| 110 | TM5ICR = 0; | ||
| 111 | |||
| 112 | TM5MD |= TM5MD_COUNT_ENABLE; | ||
| 113 | TM4MD |= TM4MD_COUNT_ENABLE; | ||
| 114 | } | ||
| 115 | |||
| 116 | static inline void shutdown_timestamp_counter(void) | ||
| 117 | { | ||
| 118 | TM4MD = 0; | ||
| 119 | TM5MD = 0; | ||
| 120 | } | ||
| 121 | |||
| 122 | /* | ||
| 123 | * we use a cascaded pair of 16-bit down-counting timers to count I/O | ||
| 124 | * clock cycles for the purposes of time keeping | ||
| 125 | */ | ||
| 126 | typedef unsigned long cycles_t; | ||
| 127 | |||
| 128 | static inline cycles_t read_timestamp_counter(void) | ||
| 129 | { | ||
| 130 | return (cycles_t) TMTSCBC; | ||
| 131 | } | ||
| 132 | |||
| 133 | #endif /* !__ASSEMBLY__ */ | ||
| 134 | |||
| 135 | #endif /* _ASM_UNIT_TIMEX_H */ | ||
diff --git a/include/asm-mn10300/user.h b/include/asm-mn10300/user.h new file mode 100644 index 000000000000..e1193908b78c --- /dev/null +++ b/include/asm-mn10300/user.h | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /* MN10300 User process data | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd. | ||
| 4 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef _ASM_USER_H | ||
| 12 | #define _ASM_USER_H | ||
| 13 | |||
| 14 | #include <asm/page.h> | ||
| 15 | #include <linux/ptrace.h> | ||
| 16 | |||
| 17 | #ifndef __ASSEMBLY__ | ||
| 18 | /* | ||
| 19 | * When the kernel dumps core, it starts by dumping the user struct - this will | ||
| 20 | * be used by gdb to figure out where the data and stack segments are within | ||
| 21 | * the file, and what virtual addresses to use. | ||
| 22 | */ | ||
| 23 | struct user { | ||
| 24 | /* We start with the registers, to mimic the way that "memory" is | ||
| 25 | * returned from the ptrace(3,...) function. | ||
| 26 | */ | ||
| 27 | struct pt_regs regs; /* Where the registers are actually stored */ | ||
| 28 | |||
| 29 | /* The rest of this junk is to help gdb figure out what goes where */ | ||
| 30 | unsigned long int u_tsize; /* Text segment size (pages). */ | ||
| 31 | unsigned long int u_dsize; /* Data segment size (pages). */ | ||
| 32 | unsigned long int u_ssize; /* Stack segment size (pages). */ | ||
| 33 | unsigned long start_code; /* Starting virtual address of text. */ | ||
| 34 | unsigned long start_stack; /* Starting virtual address of stack area. | ||
| 35 | This is actually the bottom of the stack, | ||
| 36 | the top of the stack is always found in the | ||
| 37 | esp register. */ | ||
| 38 | long int signal; /* Signal that caused the core dump. */ | ||
| 39 | int reserved; /* No longer used */ | ||
| 40 | struct user_pt_regs *u_ar0; /* Used by gdb to help find the values for */ | ||
| 41 | |||
| 42 | /* the registers */ | ||
| 43 | unsigned long magic; /* To uniquely identify a core file */ | ||
| 44 | char u_comm[32]; /* User command that was responsible */ | ||
| 45 | }; | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #define NBPG PAGE_SIZE | ||
| 49 | #define UPAGES 1 | ||
| 50 | #define HOST_TEXT_START_ADDR +(u.start_code) | ||
| 51 | #define HOST_STACK_END_ADDR +(u.start_stack + u.u_ssize * NBPG) | ||
| 52 | |||
| 53 | #endif /* _ASM_USER_H */ | ||
diff --git a/include/asm-mn10300/vga.h b/include/asm-mn10300/vga.h new file mode 100644 index 000000000000..0163e50a3459 --- /dev/null +++ b/include/asm-mn10300/vga.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* MN10300 VGA register definitions | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_VGA_H | ||
| 13 | #define _ASM_VGA_H | ||
| 14 | |||
| 15 | |||
| 16 | |||
| 17 | #endif /* _ASM_VGA_H */ | ||
diff --git a/include/asm-mn10300/xor.h b/include/asm-mn10300/xor.h new file mode 100644 index 000000000000..c82eb12a5b18 --- /dev/null +++ b/include/asm-mn10300/xor.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/xor.h> | |||
diff --git a/include/asm-parisc/a.out.h b/include/asm-parisc/a.out.h index 23e2c90943e5..eb04e34c5bb1 100644 --- a/include/asm-parisc/a.out.h +++ b/include/asm-parisc/a.out.h | |||
| @@ -17,14 +17,4 @@ struct exec | |||
| 17 | #define N_DRSIZE(a) ((a).a_drsize) | 17 | #define N_DRSIZE(a) ((a).a_drsize) |
| 18 | #define N_SYMSIZE(a) ((a).a_syms) | 18 | #define N_SYMSIZE(a) ((a).a_syms) |
| 19 | 19 | ||
| 20 | #ifdef __KERNEL__ | ||
| 21 | |||
| 22 | /* XXX: STACK_TOP actually should be STACK_BOTTOM for parisc. | ||
| 23 | * prumpf */ | ||
| 24 | |||
| 25 | #define STACK_TOP TASK_SIZE | ||
| 26 | #define STACK_TOP_MAX DEFAULT_TASK_SIZE | ||
| 27 | |||
| 28 | #endif | ||
| 29 | |||
| 30 | #endif /* __A_OUT_GNU_H__ */ | 20 | #endif /* __A_OUT_GNU_H__ */ |
diff --git a/include/asm-parisc/page.h b/include/asm-parisc/page.h index b08d9151c71e..27d50b859541 100644 --- a/include/asm-parisc/page.h +++ b/include/asm-parisc/page.h | |||
| @@ -91,6 +91,7 @@ typedef unsigned long pgprot_t; | |||
| 91 | 91 | ||
| 92 | #endif /* STRICT_MM_TYPECHECKS */ | 92 | #endif /* STRICT_MM_TYPECHECKS */ |
| 93 | 93 | ||
| 94 | typedef struct page *pgtable_t; | ||
| 94 | 95 | ||
| 95 | typedef struct __physmem_range { | 96 | typedef struct __physmem_range { |
| 96 | unsigned long start_pfn; | 97 | unsigned long start_pfn; |
diff --git a/include/asm-parisc/pgalloc.h b/include/asm-parisc/pgalloc.h index aab66f1bea14..3996dfc30a3f 100644 --- a/include/asm-parisc/pgalloc.h +++ b/include/asm-parisc/pgalloc.h | |||
| @@ -115,11 +115,14 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) | |||
| 115 | 115 | ||
| 116 | #define pmd_populate(mm, pmd, pte_page) \ | 116 | #define pmd_populate(mm, pmd, pte_page) \ |
| 117 | pmd_populate_kernel(mm, pmd, page_address(pte_page)) | 117 | pmd_populate_kernel(mm, pmd, page_address(pte_page)) |
| 118 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 118 | 119 | ||
| 119 | static inline struct page * | 120 | static inline pgtable_t |
| 120 | pte_alloc_one(struct mm_struct *mm, unsigned long address) | 121 | pte_alloc_one(struct mm_struct *mm, unsigned long address) |
| 121 | { | 122 | { |
| 122 | struct page *page = alloc_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); | 123 | struct page *page = alloc_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); |
| 124 | if (page) | ||
| 125 | pgtable_page_ctor(page); | ||
| 123 | return page; | 126 | return page; |
| 124 | } | 127 | } |
| 125 | 128 | ||
| @@ -135,7 +138,11 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 135 | free_page((unsigned long)pte); | 138 | free_page((unsigned long)pte); |
| 136 | } | 139 | } |
| 137 | 140 | ||
| 138 | #define pte_free(mm, page) pte_free_kernel(page_address(page)) | 141 | static inline void pte_free_kernel(struct mm_struct *mm, struct page *pte) |
| 142 | { | ||
| 143 | pgtable_page_dtor(pte); | ||
| 144 | pte_free_kernel(page_address((pte)); | ||
| 145 | } | ||
| 139 | 146 | ||
| 140 | #define check_pgt_cache() do { } while (0) | 147 | #define check_pgt_cache() do { } while (0) |
| 141 | 148 | ||
diff --git a/include/asm-parisc/posix_types.h b/include/asm-parisc/posix_types.h index b634e3c47fdc..bb725a6630bb 100644 --- a/include/asm-parisc/posix_types.h +++ b/include/asm-parisc/posix_types.h | |||
| @@ -47,18 +47,14 @@ typedef unsigned long long __kernel_ino64_t; | |||
| 47 | typedef unsigned int __kernel_old_dev_t; | 47 | typedef unsigned int __kernel_old_dev_t; |
| 48 | 48 | ||
| 49 | typedef struct { | 49 | typedef struct { |
| 50 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 51 | int val[2]; | 50 | int val[2]; |
| 52 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 53 | int __val[2]; | ||
| 54 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 55 | } __kernel_fsid_t; | 51 | } __kernel_fsid_t; |
| 56 | 52 | ||
| 57 | /* compatibility stuff */ | 53 | /* compatibility stuff */ |
| 58 | typedef __kernel_uid_t __kernel_old_uid_t; | 54 | typedef __kernel_uid_t __kernel_old_uid_t; |
| 59 | typedef __kernel_gid_t __kernel_old_gid_t; | 55 | typedef __kernel_gid_t __kernel_old_gid_t; |
| 60 | 56 | ||
| 61 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 57 | #if defined(__KERNEL__) |
| 62 | 58 | ||
| 63 | #undef __FD_SET | 59 | #undef __FD_SET |
| 64 | static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) | 60 | static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) |
| @@ -128,6 +124,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *__p) | |||
| 128 | } | 124 | } |
| 129 | } | 125 | } |
| 130 | 126 | ||
| 131 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 127 | #endif /* defined(__KERNEL__) */ |
| 132 | 128 | ||
| 133 | #endif | 129 | #endif |
diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h index 3bb06e898fde..3c9d34844c83 100644 --- a/include/asm-parisc/processor.h +++ b/include/asm-parisc/processor.h | |||
| @@ -47,6 +47,16 @@ | |||
| 47 | #define DEFAULT_MAP_BASE DEFAULT_MAP_BASE32 | 47 | #define DEFAULT_MAP_BASE DEFAULT_MAP_BASE32 |
| 48 | #endif | 48 | #endif |
| 49 | 49 | ||
| 50 | #ifdef __KERNEL__ | ||
| 51 | |||
| 52 | /* XXX: STACK_TOP actually should be STACK_BOTTOM for parisc. | ||
| 53 | * prumpf */ | ||
| 54 | |||
| 55 | #define STACK_TOP TASK_SIZE | ||
| 56 | #define STACK_TOP_MAX DEFAULT_TASK_SIZE | ||
| 57 | |||
| 58 | #endif | ||
| 59 | |||
| 50 | #ifndef __ASSEMBLY__ | 60 | #ifndef __ASSEMBLY__ |
| 51 | 61 | ||
| 52 | /* | 62 | /* |
diff --git a/include/asm-powerpc/a.out.h b/include/asm-powerpc/a.out.h index 5c5ea83f9349..89cead6b176e 100644 --- a/include/asm-powerpc/a.out.h +++ b/include/asm-powerpc/a.out.h | |||
| @@ -17,23 +17,4 @@ struct exec | |||
| 17 | #define N_DRSIZE(a) ((a).a_drsize) | 17 | #define N_DRSIZE(a) ((a).a_drsize) |
| 18 | #define N_SYMSIZE(a) ((a).a_syms) | 18 | #define N_SYMSIZE(a) ((a).a_syms) |
| 19 | 19 | ||
| 20 | #ifdef __KERNEL__ | ||
| 21 | #ifdef __powerpc64__ | ||
| 22 | |||
| 23 | #define STACK_TOP_USER64 TASK_SIZE_USER64 | ||
| 24 | #define STACK_TOP_USER32 TASK_SIZE_USER32 | ||
| 25 | |||
| 26 | #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ | ||
| 27 | STACK_TOP_USER32 : STACK_TOP_USER64) | ||
| 28 | |||
| 29 | #define STACK_TOP_MAX STACK_TOP_USER64 | ||
| 30 | |||
| 31 | #else /* __powerpc64__ */ | ||
| 32 | |||
| 33 | #define STACK_TOP TASK_SIZE | ||
| 34 | #define STACK_TOP_MAX STACK_TOP | ||
| 35 | |||
| 36 | #endif /* __powerpc64__ */ | ||
| 37 | #endif /* __KERNEL__ */ | ||
| 38 | |||
| 39 | #endif /* _ASM_POWERPC_A_OUT_H */ | 20 | #endif /* _ASM_POWERPC_A_OUT_H */ |
diff --git a/include/asm-powerpc/page.h b/include/asm-powerpc/page.h index 61e3725bbd37..df47bbb6ea13 100644 --- a/include/asm-powerpc/page.h +++ b/include/asm-powerpc/page.h | |||
| @@ -190,6 +190,8 @@ extern int page_is_ram(unsigned long pfn); | |||
| 190 | 190 | ||
| 191 | struct vm_area_struct; | 191 | struct vm_area_struct; |
| 192 | 192 | ||
| 193 | typedef struct page *pgtable_t; | ||
| 194 | |||
| 193 | #include <asm-generic/memory_model.h> | 195 | #include <asm-generic/memory_model.h> |
| 194 | #endif /* __ASSEMBLY__ */ | 196 | #endif /* __ASSEMBLY__ */ |
| 195 | 197 | ||
diff --git a/include/asm-powerpc/pgalloc-32.h b/include/asm-powerpc/pgalloc-32.h index c162a4c37b39..58c07147b3ea 100644 --- a/include/asm-powerpc/pgalloc-32.h +++ b/include/asm-powerpc/pgalloc-32.h | |||
| @@ -22,17 +22,19 @@ extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); | |||
| 22 | (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT) | 22 | (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT) |
| 23 | #define pmd_populate(mm, pmd, pte) \ | 23 | #define pmd_populate(mm, pmd, pte) \ |
| 24 | (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT) | 24 | (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT) |
| 25 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 25 | #else | 26 | #else |
| 26 | #define pmd_populate_kernel(mm, pmd, pte) \ | 27 | #define pmd_populate_kernel(mm, pmd, pte) \ |
| 27 | (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT) | 28 | (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT) |
| 28 | #define pmd_populate(mm, pmd, pte) \ | 29 | #define pmd_populate(mm, pmd, pte) \ |
| 29 | (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT) | 30 | (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT) |
| 31 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 30 | #endif | 32 | #endif |
| 31 | 33 | ||
| 32 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); | 34 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); |
| 33 | extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr); | 35 | extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr); |
| 34 | extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte); | 36 | extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte); |
| 35 | extern void pte_free(struct mm_struct *mm, struct page *pte); | 37 | extern void pte_free(struct mm_struct *mm, pgtable_t pte); |
| 36 | 38 | ||
| 37 | #define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte)) | 39 | #define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte)) |
| 38 | 40 | ||
diff --git a/include/asm-powerpc/pgalloc-64.h b/include/asm-powerpc/pgalloc-64.h index 5afae8593931..68980990f62a 100644 --- a/include/asm-powerpc/pgalloc-64.h +++ b/include/asm-powerpc/pgalloc-64.h | |||
| @@ -58,6 +58,7 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) | |||
| 58 | #define pmd_populate(mm, pmd, pte_page) \ | 58 | #define pmd_populate(mm, pmd, pte_page) \ |
| 59 | pmd_populate_kernel(mm, pmd, page_address(pte_page)) | 59 | pmd_populate_kernel(mm, pmd, page_address(pte_page)) |
| 60 | #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte)) | 60 | #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte)) |
| 61 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 61 | 62 | ||
| 62 | 63 | ||
| 63 | #else /* CONFIG_PPC_64K_PAGES */ | 64 | #else /* CONFIG_PPC_64K_PAGES */ |
| @@ -72,6 +73,7 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, | |||
| 72 | 73 | ||
| 73 | #define pmd_populate(mm, pmd, pte_page) \ | 74 | #define pmd_populate(mm, pmd, pte_page) \ |
| 74 | pmd_populate_kernel(mm, pmd, page_address(pte_page)) | 75 | pmd_populate_kernel(mm, pmd, page_address(pte_page)) |
| 76 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 75 | 77 | ||
| 76 | #endif /* CONFIG_PPC_64K_PAGES */ | 78 | #endif /* CONFIG_PPC_64K_PAGES */ |
| 77 | 79 | ||
| @@ -92,11 +94,18 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, | |||
| 92 | return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO); | 94 | return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO); |
| 93 | } | 95 | } |
| 94 | 96 | ||
| 95 | static inline struct page *pte_alloc_one(struct mm_struct *mm, | 97 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, |
| 96 | unsigned long address) | 98 | unsigned long address) |
| 97 | { | 99 | { |
| 98 | pte_t *pte = pte_alloc_one_kernel(mm, address); | 100 | struct page *page; |
| 99 | return pte ? virt_to_page(pte) : NULL; | 101 | pte_t *pte; |
| 102 | |||
| 103 | pte = pte_alloc_one_kernel(mm, address); | ||
| 104 | if (!pte) | ||
| 105 | return NULL; | ||
| 106 | page = virt_to_page(pte); | ||
| 107 | pgtable_page_ctor(page); | ||
| 108 | return page; | ||
| 100 | } | 109 | } |
| 101 | 110 | ||
| 102 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | 111 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) |
| @@ -104,8 +113,9 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 104 | free_page((unsigned long)pte); | 113 | free_page((unsigned long)pte); |
| 105 | } | 114 | } |
| 106 | 115 | ||
| 107 | static inline void pte_free(struct mm_struct *mm, struct page *ptepage) | 116 | static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage) |
| 108 | { | 117 | { |
| 118 | pgtable_page_dtor(ptepage); | ||
| 109 | __free_page(ptepage); | 119 | __free_page(ptepage); |
| 110 | } | 120 | } |
| 111 | 121 | ||
| @@ -136,9 +146,12 @@ static inline void pgtable_free(pgtable_free_t pgf) | |||
| 136 | 146 | ||
| 137 | extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf); | 147 | extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf); |
| 138 | 148 | ||
| 139 | #define __pte_free_tlb(tlb, ptepage) \ | 149 | #define __pte_free_tlb(tlb,ptepage) \ |
| 150 | do { \ | ||
| 151 | pgtable_page_dtor(ptepage); \ | ||
| 140 | pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \ | 152 | pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \ |
| 141 | PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1)) | 153 | PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1)); \ |
| 154 | } while (0) | ||
| 142 | #define __pmd_free_tlb(tlb, pmd) \ | 155 | #define __pmd_free_tlb(tlb, pmd) \ |
| 143 | pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \ | 156 | pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \ |
| 144 | PMD_CACHE_NUM, PMD_TABLE_SIZE-1)) | 157 | PMD_CACHE_NUM, PMD_TABLE_SIZE-1)) |
diff --git a/include/asm-powerpc/pmac_feature.h b/include/asm-powerpc/pmac_feature.h index 26bcb0aa164a..877c35a4356e 100644 --- a/include/asm-powerpc/pmac_feature.h +++ b/include/asm-powerpc/pmac_feature.h | |||
| @@ -392,6 +392,14 @@ extern u32 __iomem *uninorth_base; | |||
| 392 | #define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v))) | 392 | #define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v))) |
| 393 | #define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v))) | 393 | #define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v))) |
| 394 | 394 | ||
| 395 | /* Uninorth variant: | ||
| 396 | * | ||
| 397 | * 0 = not uninorth | ||
| 398 | * 1 = U1.x or U2.x | ||
| 399 | * 3 = U3 | ||
| 400 | * 4 = U4 | ||
| 401 | */ | ||
| 402 | extern int pmac_get_uninorth_variant(void); | ||
| 395 | 403 | ||
| 396 | #endif /* __ASM_POWERPC_PMAC_FEATURE_H */ | 404 | #endif /* __ASM_POWERPC_PMAC_FEATURE_H */ |
| 397 | #endif /* __KERNEL__ */ | 405 | #endif /* __KERNEL__ */ |
diff --git a/include/asm-powerpc/posix_types.h b/include/asm-powerpc/posix_types.h index 2f2288f520be..c4e396b540df 100644 --- a/include/asm-powerpc/posix_types.h +++ b/include/asm-powerpc/posix_types.h | |||
| @@ -64,8 +64,7 @@ typedef struct { | |||
| 64 | 64 | ||
| 65 | #else /* __GNUC__ */ | 65 | #else /* __GNUC__ */ |
| 66 | 66 | ||
| 67 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ | 67 | #if defined(__KERNEL__) |
| 68 | || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) | ||
| 69 | /* With GNU C, use inline functions instead so args are evaluated only once: */ | 68 | /* With GNU C, use inline functions instead so args are evaluated only once: */ |
| 70 | 69 | ||
| 71 | #undef __FD_SET | 70 | #undef __FD_SET |
| @@ -124,6 +123,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *p) | |||
| 124 | } | 123 | } |
| 125 | } | 124 | } |
| 126 | 125 | ||
| 127 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 126 | #endif /* defined(__KERNEL__) */ |
| 128 | #endif /* __GNUC__ */ | 127 | #endif /* __GNUC__ */ |
| 129 | #endif /* _ASM_POWERPC_POSIX_TYPES_H */ | 128 | #endif /* _ASM_POWERPC_POSIX_TYPES_H */ |
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h index 1f4765d6546f..fd98ca998b4f 100644 --- a/include/asm-powerpc/processor.h +++ b/include/asm-powerpc/processor.h | |||
| @@ -113,6 +113,25 @@ extern struct task_struct *last_task_used_spe; | |||
| 113 | TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) | 113 | TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) |
| 114 | #endif | 114 | #endif |
| 115 | 115 | ||
| 116 | #ifdef __KERNEL__ | ||
| 117 | #ifdef __powerpc64__ | ||
| 118 | |||
| 119 | #define STACK_TOP_USER64 TASK_SIZE_USER64 | ||
| 120 | #define STACK_TOP_USER32 TASK_SIZE_USER32 | ||
| 121 | |||
| 122 | #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ | ||
| 123 | STACK_TOP_USER32 : STACK_TOP_USER64) | ||
| 124 | |||
| 125 | #define STACK_TOP_MAX STACK_TOP_USER64 | ||
| 126 | |||
| 127 | #else /* __powerpc64__ */ | ||
| 128 | |||
| 129 | #define STACK_TOP TASK_SIZE | ||
| 130 | #define STACK_TOP_MAX STACK_TOP | ||
| 131 | |||
| 132 | #endif /* __powerpc64__ */ | ||
| 133 | #endif /* __KERNEL__ */ | ||
| 134 | |||
| 116 | typedef struct { | 135 | typedef struct { |
| 117 | unsigned long seg; | 136 | unsigned long seg; |
| 118 | } mm_segment_t; | 137 | } mm_segment_t; |
diff --git a/include/asm-ppc/pgalloc.h b/include/asm-ppc/pgalloc.h index 7c39a95829c7..fd4d1d74cfb1 100644 --- a/include/asm-ppc/pgalloc.h +++ b/include/asm-ppc/pgalloc.h | |||
| @@ -23,17 +23,19 @@ extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); | |||
| 23 | (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT) | 23 | (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT) |
| 24 | #define pmd_populate(mm, pmd, pte) \ | 24 | #define pmd_populate(mm, pmd, pte) \ |
| 25 | (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT) | 25 | (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT) |
| 26 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 26 | #else | 27 | #else |
| 27 | #define pmd_populate_kernel(mm, pmd, pte) \ | 28 | #define pmd_populate_kernel(mm, pmd, pte) \ |
| 28 | (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT) | 29 | (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT) |
| 29 | #define pmd_populate(mm, pmd, pte) \ | 30 | #define pmd_populate(mm, pmd, pte) \ |
| 30 | (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT) | 31 | (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT) |
| 32 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 31 | #endif | 33 | #endif |
| 32 | 34 | ||
| 33 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); | 35 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr); |
| 34 | extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr); | 36 | extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr); |
| 35 | extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte); | 37 | extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte); |
| 36 | extern void pte_free(struct mm_struct *mm, struct page *pte); | 38 | extern void pte_free(struct mm_struct *mm, pgtable_t pte); |
| 37 | 39 | ||
| 38 | #define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte)) | 40 | #define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte)) |
| 39 | 41 | ||
diff --git a/include/asm-s390/a.out.h b/include/asm-s390/a.out.h index 46158dcaf517..8d6bd9c2952e 100644 --- a/include/asm-s390/a.out.h +++ b/include/asm-s390/a.out.h | |||
| @@ -29,11 +29,4 @@ struct exec | |||
| 29 | #define N_DRSIZE(a) ((a).a_drsize) | 29 | #define N_DRSIZE(a) ((a).a_drsize) |
| 30 | #define N_SYMSIZE(a) ((a).a_syms) | 30 | #define N_SYMSIZE(a) ((a).a_syms) |
| 31 | 31 | ||
| 32 | #ifdef __KERNEL__ | ||
| 33 | |||
| 34 | #define STACK_TOP TASK_SIZE | ||
| 35 | #define STACK_TOP_MAX DEFAULT_TASK_SIZE | ||
| 36 | |||
| 37 | #endif | ||
| 38 | |||
| 39 | #endif /* __A_OUT_GNU_H__ */ | 32 | #endif /* __A_OUT_GNU_H__ */ |
diff --git a/include/asm-s390/ioctls.h b/include/asm-s390/ioctls.h index 07e19b2dd73f..40e481b1b461 100644 --- a/include/asm-s390/ioctls.h +++ b/include/asm-s390/ioctls.h | |||
| @@ -54,6 +54,10 @@ | |||
| 54 | #define TIOCSBRK 0x5427 /* BSD compatibility */ | 54 | #define TIOCSBRK 0x5427 /* BSD compatibility */ |
| 55 | #define TIOCCBRK 0x5428 /* BSD compatibility */ | 55 | #define TIOCCBRK 0x5428 /* BSD compatibility */ |
| 56 | #define TIOCGSID 0x5429 /* Return the session ID of FD */ | 56 | #define TIOCGSID 0x5429 /* Return the session ID of FD */ |
| 57 | #define TCGETS2 _IOR('T',0x2A, struct termios2) | ||
| 58 | #define TCSETS2 _IOW('T',0x2B, struct termios2) | ||
| 59 | #define TCSETSW2 _IOW('T',0x2C, struct termios2) | ||
| 60 | #define TCSETSF2 _IOW('T',0x2D, struct termios2) | ||
| 57 | #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ | 61 | #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ |
| 58 | #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ | 62 | #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ |
| 59 | 63 | ||
diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h index a55f9d979dfb..7f29a981f48c 100644 --- a/include/asm-s390/page.h +++ b/include/asm-s390/page.h | |||
| @@ -109,6 +109,8 @@ typedef struct { unsigned long pgd; } pgd_t; | |||
| 109 | 109 | ||
| 110 | #endif /* __s390x__ */ | 110 | #endif /* __s390x__ */ |
| 111 | 111 | ||
| 112 | typedef struct page *pgtable_t; | ||
| 113 | |||
| 112 | #define __pte(x) ((pte_t) { (x) } ) | 114 | #define __pte(x) ((pte_t) { (x) } ) |
| 113 | #define __pmd(x) ((pmd_t) { (x) } ) | 115 | #define __pmd(x) ((pmd_t) { (x) } ) |
| 114 | #define __pgd(x) ((pgd_t) { (x) } ) | 116 | #define __pgd(x) ((pgd_t) { (x) } ) |
diff --git a/include/asm-s390/pgalloc.h b/include/asm-s390/pgalloc.h index 6f6619ba8980..900d44807e10 100644 --- a/include/asm-s390/pgalloc.h +++ b/include/asm-s390/pgalloc.h | |||
| @@ -132,7 +132,7 @@ pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) | |||
| 132 | } | 132 | } |
| 133 | 133 | ||
| 134 | static inline void | 134 | static inline void |
| 135 | pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page) | 135 | pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page) |
| 136 | { | 136 | { |
| 137 | pte_t *pte = (pte_t *)page_to_phys(page); | 137 | pte_t *pte = (pte_t *)page_to_phys(page); |
| 138 | pmd_t *shadow_pmd = get_shadow_table(pmd); | 138 | pmd_t *shadow_pmd = get_shadow_table(pmd); |
| @@ -142,6 +142,7 @@ pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page) | |||
| 142 | if (shadow_pmd && shadow_pte) | 142 | if (shadow_pmd && shadow_pte) |
| 143 | pmd_populate_kernel(mm, shadow_pmd, shadow_pte); | 143 | pmd_populate_kernel(mm, shadow_pmd, shadow_pte); |
| 144 | } | 144 | } |
| 145 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 145 | 146 | ||
| 146 | /* | 147 | /* |
| 147 | * page table entry allocation/free routines. | 148 | * page table entry allocation/free routines. |
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h index 4f744609cd11..e8785634cbdb 100644 --- a/include/asm-s390/processor.h +++ b/include/asm-s390/processor.h | |||
| @@ -78,6 +78,13 @@ extern int get_cpu_capability(unsigned int *); | |||
| 78 | 78 | ||
| 79 | #endif /* __s390x__ */ | 79 | #endif /* __s390x__ */ |
| 80 | 80 | ||
| 81 | #ifdef __KERNEL__ | ||
| 82 | |||
| 83 | #define STACK_TOP TASK_SIZE | ||
| 84 | #define STACK_TOP_MAX DEFAULT_TASK_SIZE | ||
| 85 | |||
| 86 | #endif | ||
| 87 | |||
| 81 | #define HAVE_ARCH_PICK_MMAP_LAYOUT | 88 | #define HAVE_ARCH_PICK_MMAP_LAYOUT |
| 82 | 89 | ||
| 83 | typedef struct { | 90 | typedef struct { |
| @@ -161,6 +168,7 @@ struct stack_frame { | |||
| 161 | /* Forward declaration, a strange C thing */ | 168 | /* Forward declaration, a strange C thing */ |
| 162 | struct task_struct; | 169 | struct task_struct; |
| 163 | struct mm_struct; | 170 | struct mm_struct; |
| 171 | struct seq_file; | ||
| 164 | 172 | ||
| 165 | /* Free all resources held by a thread. */ | 173 | /* Free all resources held by a thread. */ |
| 166 | extern void release_thread(struct task_struct *); | 174 | extern void release_thread(struct task_struct *); |
| @@ -177,7 +185,7 @@ extern unsigned long thread_saved_pc(struct task_struct *t); | |||
| 177 | /* | 185 | /* |
| 178 | * Print register of task into buffer. Used in fs/proc/array.c. | 186 | * Print register of task into buffer. Used in fs/proc/array.c. |
| 179 | */ | 187 | */ |
| 180 | extern char *task_show_regs(struct task_struct *task, char *buffer); | 188 | extern void task_show_regs(struct seq_file *m, struct task_struct *task); |
| 181 | 189 | ||
| 182 | extern void show_registers(struct pt_regs *regs); | 190 | extern void show_registers(struct pt_regs *regs); |
| 183 | extern void show_code(struct pt_regs *regs); | 191 | extern void show_code(struct pt_regs *regs); |
diff --git a/include/asm-s390/termbits.h b/include/asm-s390/termbits.h index 811b9a9cdc08..58731853d529 100644 --- a/include/asm-s390/termbits.h +++ b/include/asm-s390/termbits.h | |||
| @@ -148,6 +148,7 @@ struct ktermios { | |||
| 148 | #define HUPCL 0002000 | 148 | #define HUPCL 0002000 |
| 149 | #define CLOCAL 0004000 | 149 | #define CLOCAL 0004000 |
| 150 | #define CBAUDEX 0010000 | 150 | #define CBAUDEX 0010000 |
| 151 | #define BOTHER 0010000 | ||
| 151 | #define B57600 0010001 | 152 | #define B57600 0010001 |
| 152 | #define B115200 0010002 | 153 | #define B115200 0010002 |
| 153 | #define B230400 0010003 | 154 | #define B230400 0010003 |
| @@ -163,10 +164,12 @@ struct ktermios { | |||
| 163 | #define B3000000 0010015 | 164 | #define B3000000 0010015 |
| 164 | #define B3500000 0010016 | 165 | #define B3500000 0010016 |
| 165 | #define B4000000 0010017 | 166 | #define B4000000 0010017 |
| 166 | #define CIBAUD 002003600000 /* input baud rate (not used) */ | 167 | #define CIBAUD 002003600000 /* input baud rate */ |
| 167 | #define CMSPAR 010000000000 /* mark or space (stick) parity */ | 168 | #define CMSPAR 010000000000 /* mark or space (stick) parity */ |
| 168 | #define CRTSCTS 020000000000 /* flow control */ | 169 | #define CRTSCTS 020000000000 /* flow control */ |
| 169 | 170 | ||
| 171 | #define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ | ||
| 172 | |||
| 170 | /* c_lflag bits */ | 173 | /* c_lflag bits */ |
| 171 | #define ISIG 0000001 | 174 | #define ISIG 0000001 |
| 172 | #define ICANON 0000002 | 175 | #define ICANON 0000002 |
diff --git a/include/asm-s390/termios.h b/include/asm-s390/termios.h index a3480e25eb4b..67f66278f533 100644 --- a/include/asm-s390/termios.h +++ b/include/asm-s390/termios.h | |||
| @@ -57,6 +57,9 @@ struct termio { | |||
| 57 | */ | 57 | */ |
| 58 | #define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" | 58 | #define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" |
| 59 | 59 | ||
| 60 | #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) | ||
| 61 | #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) | ||
| 62 | |||
| 60 | #include <asm-generic/termios.h> | 63 | #include <asm-generic/termios.h> |
| 61 | 64 | ||
| 62 | #endif /* __KERNEL__ */ | 65 | #endif /* __KERNEL__ */ |
diff --git a/include/asm-s390/tlb.h b/include/asm-s390/tlb.h index 985de2b88279..3c8177fa9e06 100644 --- a/include/asm-s390/tlb.h +++ b/include/asm-s390/tlb.h | |||
| @@ -95,7 +95,7 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page) | |||
| 95 | * pte_free_tlb frees a pte table and clears the CRSTE for the | 95 | * pte_free_tlb frees a pte table and clears the CRSTE for the |
| 96 | * page table from the tlb. | 96 | * page table from the tlb. |
| 97 | */ | 97 | */ |
| 98 | static inline void pte_free_tlb(struct mmu_gather *tlb, struct page *page) | 98 | static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t page) |
| 99 | { | 99 | { |
| 100 | if (!tlb->fullmm) { | 100 | if (!tlb->fullmm) { |
| 101 | tlb->array[tlb->nr_ptes++] = page; | 101 | tlb->array[tlb->nr_ptes++] = page; |
diff --git a/include/asm-sh/a.out.h b/include/asm-sh/a.out.h index 685d0f6125fa..1f93130e179c 100644 --- a/include/asm-sh/a.out.h +++ b/include/asm-sh/a.out.h | |||
| @@ -17,11 +17,4 @@ struct exec | |||
| 17 | #define N_DRSIZE(a) ((a).a_drsize) | 17 | #define N_DRSIZE(a) ((a).a_drsize) |
| 18 | #define N_SYMSIZE(a) ((a).a_syms) | 18 | #define N_SYMSIZE(a) ((a).a_syms) |
| 19 | 19 | ||
| 20 | #ifdef __KERNEL__ | ||
| 21 | |||
| 22 | #define STACK_TOP TASK_SIZE | ||
| 23 | #define STACK_TOP_MAX STACK_TOP | ||
| 24 | |||
| 25 | #endif | ||
| 26 | |||
| 27 | #endif /* __ASM_SH_A_OUT_H */ | 20 | #endif /* __ASM_SH_A_OUT_H */ |
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h index e0fe02950f52..134562dc8c45 100644 --- a/include/asm-sh/page.h +++ b/include/asm-sh/page.h | |||
| @@ -100,6 +100,8 @@ typedef struct { unsigned long pgd; } pgd_t; | |||
| 100 | #define __pgd(x) ((pgd_t) { (x) } ) | 100 | #define __pgd(x) ((pgd_t) { (x) } ) |
| 101 | #define __pgprot(x) ((pgprot_t) { (x) } ) | 101 | #define __pgprot(x) ((pgprot_t) { (x) } ) |
| 102 | 102 | ||
| 103 | typedef struct page *pgtable_t; | ||
| 104 | |||
| 103 | #endif /* !__ASSEMBLY__ */ | 105 | #endif /* !__ASSEMBLY__ */ |
| 104 | 106 | ||
| 105 | /* | 107 | /* |
diff --git a/include/asm-sh/pgalloc.h b/include/asm-sh/pgalloc.h index 59ca16d77a1d..84dd2db7104c 100644 --- a/include/asm-sh/pgalloc.h +++ b/include/asm-sh/pgalloc.h | |||
| @@ -14,10 +14,11 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, | |||
| 14 | } | 14 | } |
| 15 | 15 | ||
| 16 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, | 16 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, |
| 17 | struct page *pte) | 17 | pgtable_t pte) |
| 18 | { | 18 | { |
| 19 | set_pmd(pmd, __pmd((unsigned long)page_address(pte))); | 19 | set_pmd(pmd, __pmd((unsigned long)page_address(pte))); |
| 20 | } | 20 | } |
| 21 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 21 | 22 | ||
| 22 | static inline void pgd_ctor(void *x) | 23 | static inline void pgd_ctor(void *x) |
| 23 | { | 24 | { |
| @@ -47,11 +48,18 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, | |||
| 47 | return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL); | 48 | return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL); |
| 48 | } | 49 | } |
| 49 | 50 | ||
| 50 | static inline struct page *pte_alloc_one(struct mm_struct *mm, | 51 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, |
| 51 | unsigned long address) | 52 | unsigned long address) |
| 52 | { | 53 | { |
| 53 | void *pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL); | 54 | struct page *page; |
| 54 | return pg ? virt_to_page(pg) : NULL; | 55 | void *pg; |
| 56 | |||
| 57 | pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL); | ||
| 58 | if (!pg) | ||
| 59 | return NULL; | ||
| 60 | page = virt_to_page(pg); | ||
| 61 | pgtable_page_ctor(page); | ||
| 62 | return page; | ||
| 55 | } | 63 | } |
| 56 | 64 | ||
| 57 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | 65 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) |
| @@ -59,12 +67,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 59 | quicklist_free(QUICK_PT, NULL, pte); | 67 | quicklist_free(QUICK_PT, NULL, pte); |
| 60 | } | 68 | } |
| 61 | 69 | ||
| 62 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 70 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 63 | { | 71 | { |
| 72 | pgtable_page_dtor(pte); | ||
| 64 | quicklist_free_page(QUICK_PT, NULL, pte); | 73 | quicklist_free_page(QUICK_PT, NULL, pte); |
| 65 | } | 74 | } |
| 66 | 75 | ||
| 67 | #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) | 76 | #define __pte_free_tlb(tlb,pte) \ |
| 77 | do { \ | ||
| 78 | pgtable_page_dtor(pte); \ | ||
| 79 | tlb_remove_page((tlb), (pte)); \ | ||
| 80 | } while (0) | ||
| 68 | 81 | ||
| 69 | /* | 82 | /* |
| 70 | * allocating and freeing a pmd is trivial: the 1-entry pmd is | 83 | * allocating and freeing a pmd is trivial: the 1-entry pmd is |
diff --git a/include/asm-sh/processor_32.h b/include/asm-sh/processor_32.h index a7edaa1a870c..df2d5b039ef4 100644 --- a/include/asm-sh/processor_32.h +++ b/include/asm-sh/processor_32.h | |||
| @@ -50,6 +50,9 @@ extern struct sh_cpuinfo cpu_data[]; | |||
| 50 | */ | 50 | */ |
| 51 | #define TASK_SIZE 0x7c000000UL | 51 | #define TASK_SIZE 0x7c000000UL |
| 52 | 52 | ||
| 53 | #define STACK_TOP TASK_SIZE | ||
| 54 | #define STACK_TOP_MAX STACK_TOP | ||
| 55 | |||
| 53 | /* This decides where the kernel will search for a free chunk of vm | 56 | /* This decides where the kernel will search for a free chunk of vm |
| 54 | * space during mmap's. | 57 | * space during mmap's. |
| 55 | */ | 58 | */ |
diff --git a/include/asm-sh/processor_64.h b/include/asm-sh/processor_64.h index 99c22b14a85b..eda4bef448e9 100644 --- a/include/asm-sh/processor_64.h +++ b/include/asm-sh/processor_64.h | |||
| @@ -83,6 +83,9 @@ extern struct sh_cpuinfo cpu_data[]; | |||
| 83 | */ | 83 | */ |
| 84 | #define TASK_SIZE 0x7ffff000UL | 84 | #define TASK_SIZE 0x7ffff000UL |
| 85 | 85 | ||
| 86 | #define STACK_TOP TASK_SIZE | ||
| 87 | #define STACK_TOP_MAX STACK_TOP | ||
| 88 | |||
| 86 | /* This decides where the kernel will search for a free chunk of vm | 89 | /* This decides where the kernel will search for a free chunk of vm |
| 87 | * space during mmap's. | 90 | * space during mmap's. |
| 88 | */ | 91 | */ |
diff --git a/include/asm-sparc/a.out-core.h b/include/asm-sparc/a.out-core.h new file mode 100644 index 000000000000..e8fd338ed0b2 --- /dev/null +++ b/include/asm-sparc/a.out-core.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | /* a.out coredump register dumper | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_A_OUT_CORE_H | ||
| 13 | #define _ASM_A_OUT_CORE_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #include <linux/user.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * fill in the user structure for an a.out core dump | ||
| 21 | */ | ||
| 22 | static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) | ||
| 23 | { | ||
| 24 | unsigned long first_stack_page; | ||
| 25 | |||
| 26 | dump->magic = SUNOS_CORE_MAGIC; | ||
| 27 | dump->len = sizeof(struct user); | ||
| 28 | dump->regs.psr = regs->psr; | ||
| 29 | dump->regs.pc = regs->pc; | ||
| 30 | dump->regs.npc = regs->npc; | ||
| 31 | dump->regs.y = regs->y; | ||
| 32 | /* fuck me plenty */ | ||
| 33 | memcpy(&dump->regs.regs[0], ®s->u_regs[1], (sizeof(unsigned long) * 15)); | ||
| 34 | dump->uexec = current->thread.core_exec; | ||
| 35 | dump->u_tsize = (((unsigned long) current->mm->end_code) - | ||
| 36 | ((unsigned long) current->mm->start_code)) & ~(PAGE_SIZE - 1); | ||
| 37 | dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1))); | ||
| 38 | dump->u_dsize -= dump->u_tsize; | ||
| 39 | dump->u_dsize &= ~(PAGE_SIZE - 1); | ||
| 40 | first_stack_page = (regs->u_regs[UREG_FP] & ~(PAGE_SIZE - 1)); | ||
| 41 | dump->u_ssize = (TASK_SIZE - first_stack_page) & ~(PAGE_SIZE - 1); | ||
| 42 | memcpy(&dump->fpu.fpstatus.fregs.regs[0], ¤t->thread.float_regs[0], (sizeof(unsigned long) * 32)); | ||
| 43 | dump->fpu.fpstatus.fsr = current->thread.fsr; | ||
| 44 | dump->fpu.fpstatus.flags = dump->fpu.fpstatus.extra = 0; | ||
| 45 | dump->fpu.fpstatus.fpq_count = current->thread.fpqdepth; | ||
| 46 | memcpy(&dump->fpu.fpstatus.fpq[0], ¤t->thread.fpqueue[0], | ||
| 47 | ((sizeof(unsigned long) * 2) * 16)); | ||
| 48 | dump->sigcode = 0; | ||
| 49 | } | ||
| 50 | |||
| 51 | #endif /* __KERNEL__ */ | ||
| 52 | #endif /* _ASM_A_OUT_CORE_H */ | ||
diff --git a/include/asm-sparc/a.out.h b/include/asm-sparc/a.out.h index 917e04250696..744cfe6c0de8 100644 --- a/include/asm-sparc/a.out.h +++ b/include/asm-sparc/a.out.h | |||
| @@ -87,13 +87,4 @@ struct relocation_info /* used when header.a_machtype == M_SPARC */ | |||
| 87 | 87 | ||
| 88 | #define N_RELOCATION_INFO_DECLARED 1 | 88 | #define N_RELOCATION_INFO_DECLARED 1 |
| 89 | 89 | ||
| 90 | #ifdef __KERNEL__ | ||
| 91 | |||
| 92 | #include <asm/page.h> | ||
| 93 | |||
| 94 | #define STACK_TOP (PAGE_OFFSET - PAGE_SIZE) | ||
| 95 | #define STACK_TOP_MAX STACK_TOP | ||
| 96 | |||
| 97 | #endif /* __KERNEL__ */ | ||
| 98 | |||
| 99 | #endif /* __SPARC_A_OUT_H__ */ | 90 | #endif /* __SPARC_A_OUT_H__ */ |
diff --git a/include/asm-sparc/page.h b/include/asm-sparc/page.h index cbc48c0c4e15..39ccf2da297c 100644 --- a/include/asm-sparc/page.h +++ b/include/asm-sparc/page.h | |||
| @@ -123,6 +123,8 @@ typedef unsigned long iopgprot_t; | |||
| 123 | 123 | ||
| 124 | #endif | 124 | #endif |
| 125 | 125 | ||
| 126 | typedef struct page *pgtable_t; | ||
| 127 | |||
| 126 | extern unsigned long sparc_unmapped_base; | 128 | extern unsigned long sparc_unmapped_base; |
| 127 | 129 | ||
| 128 | BTFIXUPDEF_SETHI(sparc_unmapped_base) | 130 | BTFIXUPDEF_SETHI(sparc_unmapped_base) |
diff --git a/include/asm-sparc/param.h b/include/asm-sparc/param.h index beaf02d364f2..86ba59af9d2c 100644 --- a/include/asm-sparc/param.h +++ b/include/asm-sparc/param.h | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | #define _ASMSPARC_PARAM_H | 3 | #define _ASMSPARC_PARAM_H |
| 4 | 4 | ||
| 5 | #ifdef __KERNEL__ | 5 | #ifdef __KERNEL__ |
| 6 | # define HZ 100 /* Internal kernel timer frequency */ | 6 | # define HZ CONFIG_HZ /* Internal kernel timer frequency */ |
| 7 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ | 7 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ |
| 8 | # define CLOCKS_PER_SEC (USER_HZ) | 8 | # define CLOCKS_PER_SEC (USER_HZ) |
| 9 | #endif | 9 | #endif |
diff --git a/include/asm-sparc/pgalloc.h b/include/asm-sparc/pgalloc.h index b5fbdd36447f..6292cd00e5af 100644 --- a/include/asm-sparc/pgalloc.h +++ b/include/asm-sparc/pgalloc.h | |||
| @@ -50,10 +50,11 @@ BTFIXUPDEF_CALL(void, free_pmd_fast, pmd_t *) | |||
| 50 | 50 | ||
| 51 | BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *) | 51 | BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *) |
| 52 | #define pmd_populate(MM, PMD, PTE) BTFIXUP_CALL(pmd_populate)(PMD, PTE) | 52 | #define pmd_populate(MM, PMD, PTE) BTFIXUP_CALL(pmd_populate)(PMD, PTE) |
| 53 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 53 | BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *) | 54 | BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *) |
| 54 | #define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE) | 55 | #define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE) |
| 55 | 56 | ||
| 56 | BTFIXUPDEF_CALL(struct page *, pte_alloc_one, struct mm_struct *, unsigned long) | 57 | BTFIXUPDEF_CALL(pgtable_t , pte_alloc_one, struct mm_struct *, unsigned long) |
| 57 | #define pte_alloc_one(mm, address) BTFIXUP_CALL(pte_alloc_one)(mm, address) | 58 | #define pte_alloc_one(mm, address) BTFIXUP_CALL(pte_alloc_one)(mm, address) |
| 58 | BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long) | 59 | BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long) |
| 59 | #define pte_alloc_one_kernel(mm, addr) BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr) | 60 | #define pte_alloc_one_kernel(mm, addr) BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr) |
| @@ -61,7 +62,7 @@ BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long | |||
| 61 | BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *) | 62 | BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *) |
| 62 | #define pte_free_kernel(mm, pte) BTFIXUP_CALL(free_pte_fast)(pte) | 63 | #define pte_free_kernel(mm, pte) BTFIXUP_CALL(free_pte_fast)(pte) |
| 63 | 64 | ||
| 64 | BTFIXUPDEF_CALL(void, pte_free, struct page *) | 65 | BTFIXUPDEF_CALL(void, pte_free, pgtable_t ) |
| 65 | #define pte_free(mm, pte) BTFIXUP_CALL(pte_free)(pte) | 66 | #define pte_free(mm, pte) BTFIXUP_CALL(pte_free)(pte) |
| 66 | #define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, pte) | 67 | #define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, pte) |
| 67 | 68 | ||
diff --git a/include/asm-sparc/posix_types.h b/include/asm-sparc/posix_types.h index 62c8fa7b36d4..dcc07eb5e181 100644 --- a/include/asm-sparc/posix_types.h +++ b/include/asm-sparc/posix_types.h | |||
| @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; | |||
| 39 | #endif | 39 | #endif |
| 40 | 40 | ||
| 41 | typedef struct { | 41 | typedef struct { |
| 42 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 43 | int val[2]; | 42 | int val[2]; |
| 44 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 45 | int __val[2]; | ||
| 46 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 47 | } __kernel_fsid_t; | 43 | } __kernel_fsid_t; |
| 48 | 44 | ||
| 49 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 45 | #if defined(__KERNEL__) |
| 50 | 46 | ||
| 51 | #undef __FD_SET | 47 | #undef __FD_SET |
| 52 | static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) | 48 | static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) |
| @@ -117,6 +113,6 @@ static inline void __FD_ZERO(__kernel_fd_set *p) | |||
| 117 | } | 113 | } |
| 118 | } | 114 | } |
| 119 | 115 | ||
| 120 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 116 | #endif /* defined(__KERNEL__) */ |
| 121 | 117 | ||
| 122 | #endif /* !(__ARCH_SPARC_POSIX_TYPES_H) */ | 118 | #endif /* !(__ARCH_SPARC_POSIX_TYPES_H) */ |
diff --git a/include/asm-sparc/processor.h b/include/asm-sparc/processor.h index 6fbb3f0af8d8..40b1e41fdea7 100644 --- a/include/asm-sparc/processor.h +++ b/include/asm-sparc/processor.h | |||
| @@ -33,6 +33,10 @@ | |||
| 33 | * we can make our access_ok test faster | 33 | * we can make our access_ok test faster |
| 34 | */ | 34 | */ |
| 35 | #define TASK_SIZE PAGE_OFFSET | 35 | #define TASK_SIZE PAGE_OFFSET |
| 36 | #ifdef __KERNEL__ | ||
| 37 | #define STACK_TOP (PAGE_OFFSET - PAGE_SIZE) | ||
| 38 | #define STACK_TOP_MAX STACK_TOP | ||
| 39 | #endif /* __KERNEL__ */ | ||
| 36 | 40 | ||
| 37 | struct task_struct; | 41 | struct task_struct; |
| 38 | 42 | ||
diff --git a/include/asm-sparc/uaccess.h b/include/asm-sparc/uaccess.h index 3cf132e1aa25..366b11696ee3 100644 --- a/include/asm-sparc/uaccess.h +++ b/include/asm-sparc/uaccess.h | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #include <linux/string.h> | 13 | #include <linux/string.h> |
| 14 | #include <linux/errno.h> | 14 | #include <linux/errno.h> |
| 15 | #include <asm/vac-ops.h> | 15 | #include <asm/vac-ops.h> |
| 16 | #include <asm/a.out.h> | ||
| 17 | #endif | 16 | #endif |
| 18 | 17 | ||
| 19 | #ifndef __ASSEMBLY__ | 18 | #ifndef __ASSEMBLY__ |
diff --git a/include/asm-sparc64/a.out-core.h b/include/asm-sparc64/a.out-core.h new file mode 100644 index 000000000000..3499b3c425ca --- /dev/null +++ b/include/asm-sparc64/a.out-core.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* a.out coredump register dumper | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_A_OUT_CORE_H | ||
| 13 | #define _ASM_A_OUT_CORE_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #include <linux/user.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * fill in the user structure for an a.out core dump | ||
| 21 | */ | ||
| 22 | static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) | ||
| 23 | { | ||
| 24 | /* Only should be used for SunOS and ancient a.out | ||
| 25 | * SparcLinux binaries... Not worth implementing. | ||
| 26 | */ | ||
| 27 | memset(dump, 0, sizeof(struct user)); | ||
| 28 | } | ||
| 29 | |||
| 30 | #endif /* __KERNEL__ */ | ||
| 31 | #endif /* _ASM_A_OUT_CORE_H */ | ||
diff --git a/include/asm-sparc64/a.out.h b/include/asm-sparc64/a.out.h index 902e07f89a42..53c95bdfc66e 100644 --- a/include/asm-sparc64/a.out.h +++ b/include/asm-sparc64/a.out.h | |||
| @@ -93,18 +93,6 @@ struct relocation_info /* used when header.a_machtype == M_SPARC */ | |||
| 93 | 93 | ||
| 94 | #define N_RELOCATION_INFO_DECLARED 1 | 94 | #define N_RELOCATION_INFO_DECLARED 1 |
| 95 | 95 | ||
| 96 | #ifdef __KERNEL__ | ||
| 97 | |||
| 98 | #define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE) | ||
| 99 | #define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL)) | ||
| 100 | |||
| 101 | #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ | ||
| 102 | STACK_TOP32 : STACK_TOP64) | ||
| 103 | |||
| 104 | #define STACK_TOP_MAX STACK_TOP64 | ||
| 105 | |||
| 106 | #endif | ||
| 107 | |||
| 108 | #endif /* !(__ASSEMBLY__) */ | 96 | #endif /* !(__ASSEMBLY__) */ |
| 109 | 97 | ||
| 110 | #endif /* !(__SPARC64_A_OUT_H__) */ | 98 | #endif /* !(__SPARC64_A_OUT_H__) */ |
diff --git a/include/asm-sparc64/elf.h b/include/asm-sparc64/elf.h index 272a65873f2e..11c8e68d712a 100644 --- a/include/asm-sparc64/elf.h +++ b/include/asm-sparc64/elf.h | |||
| @@ -75,7 +75,6 @@ | |||
| 75 | /* | 75 | /* |
| 76 | * These are used to set parameters in the core dumps. | 76 | * These are used to set parameters in the core dumps. |
| 77 | */ | 77 | */ |
| 78 | #ifndef ELF_ARCH | ||
| 79 | #define ELF_ARCH EM_SPARCV9 | 78 | #define ELF_ARCH EM_SPARCV9 |
| 80 | #define ELF_CLASS ELFCLASS64 | 79 | #define ELF_CLASS ELFCLASS64 |
| 81 | #define ELF_DATA ELFDATA2MSB | 80 | #define ELF_DATA ELFDATA2MSB |
| @@ -100,14 +99,59 @@ typedef struct { | |||
| 100 | unsigned long pr_gsr; | 99 | unsigned long pr_gsr; |
| 101 | unsigned long pr_fprs; | 100 | unsigned long pr_fprs; |
| 102 | } elf_fpregset_t; | 101 | } elf_fpregset_t; |
| 103 | #endif | 102 | |
| 103 | /* Format of 32-bit elf_gregset_t is: | ||
| 104 | * G0 --> G7 | ||
| 105 | * O0 --> O7 | ||
| 106 | * L0 --> L7 | ||
| 107 | * I0 --> I7 | ||
| 108 | * PSR, PC, nPC, Y, WIM, TBR | ||
| 109 | */ | ||
| 110 | typedef unsigned int compat_elf_greg_t; | ||
| 111 | #define COMPAT_ELF_NGREG 38 | ||
| 112 | typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG]; | ||
| 113 | |||
| 114 | typedef struct { | ||
| 115 | union { | ||
| 116 | unsigned int pr_regs[32]; | ||
| 117 | unsigned long pr_dregs[16]; | ||
| 118 | } pr_fr; | ||
| 119 | unsigned int __unused; | ||
| 120 | unsigned int pr_fsr; | ||
| 121 | unsigned char pr_qcnt; | ||
| 122 | unsigned char pr_q_entrysize; | ||
| 123 | unsigned char pr_en; | ||
| 124 | unsigned int pr_q[64]; | ||
| 125 | } compat_elf_fpregset_t; | ||
| 126 | |||
| 127 | /* UltraSparc extensions. Still unused, but will be eventually. */ | ||
| 128 | typedef struct { | ||
| 129 | unsigned int pr_type; | ||
| 130 | unsigned int pr_align; | ||
| 131 | union { | ||
| 132 | struct { | ||
| 133 | union { | ||
| 134 | unsigned int pr_regs[32]; | ||
| 135 | unsigned long pr_dregs[16]; | ||
| 136 | long double pr_qregs[8]; | ||
| 137 | } pr_xfr; | ||
| 138 | } pr_v8p; | ||
| 139 | unsigned int pr_xfsr; | ||
| 140 | unsigned int pr_fprs; | ||
| 141 | unsigned int pr_xg[8]; | ||
| 142 | unsigned int pr_xo[8]; | ||
| 143 | unsigned long pr_tstate; | ||
| 144 | unsigned int pr_filler[8]; | ||
| 145 | } pr_un; | ||
| 146 | } elf_xregset_t; | ||
| 104 | 147 | ||
| 105 | /* | 148 | /* |
| 106 | * This is used to ensure we don't load something for the wrong architecture. | 149 | * This is used to ensure we don't load something for the wrong architecture. |
| 107 | */ | 150 | */ |
| 108 | #ifndef elf_check_arch | 151 | #define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) |
| 109 | #define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) /* Might be EM_SPARCV9 or EM_SPARC */ | 152 | #define compat_elf_check_arch(x) ((x)->e_machine == EM_SPARC || \ |
| 110 | #endif | 153 | (x)->e_machine == EM_SPARC32PLUS) |
| 154 | #define compat_start_thread start_thread32 | ||
| 111 | 155 | ||
| 112 | #define USE_ELF_CORE_DUMP | 156 | #define USE_ELF_CORE_DUMP |
| 113 | #define ELF_EXEC_PAGESIZE PAGE_SIZE | 157 | #define ELF_EXEC_PAGESIZE PAGE_SIZE |
| @@ -117,9 +161,8 @@ typedef struct { | |||
| 117 | the loader. We need to make sure that it is out of the way of the program | 161 | the loader. We need to make sure that it is out of the way of the program |
| 118 | that it will "exec", and that there is sufficient room for the brk. */ | 162 | that it will "exec", and that there is sufficient room for the brk. */ |
| 119 | 163 | ||
| 120 | #ifndef ELF_ET_DYN_BASE | 164 | #define ELF_ET_DYN_BASE 0x0000010000000000UL |
| 121 | #define ELF_ET_DYN_BASE 0x0000010000000000UL | 165 | #define COMPAT_ELF_ET_DYN_BASE 0x0000000070000000UL |
| 122 | #endif | ||
| 123 | 166 | ||
| 124 | 167 | ||
| 125 | /* This yields a mask that user programs can use to figure out what | 168 | /* This yields a mask that user programs can use to figure out what |
diff --git a/include/asm-sparc64/page.h b/include/asm-sparc64/page.h index cdf950e017ee..e93a482aa24a 100644 --- a/include/asm-sparc64/page.h +++ b/include/asm-sparc64/page.h | |||
| @@ -104,6 +104,8 @@ typedef unsigned long pgprot_t; | |||
| 104 | 104 | ||
| 105 | #endif /* (STRICT_MM_TYPECHECKS) */ | 105 | #endif /* (STRICT_MM_TYPECHECKS) */ |
| 106 | 106 | ||
| 107 | typedef struct page *pgtable_t; | ||
| 108 | |||
| 107 | #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \ | 109 | #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \ |
| 108 | (_AC(0x0000000070000000,UL)) : \ | 110 | (_AC(0x0000000070000000,UL)) : \ |
| 109 | (_AC(0xfffff80000000000,UL) + (1UL << 32UL))) | 111 | (_AC(0xfffff80000000000,UL) + (1UL << 32UL))) |
diff --git a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h index b48f73c2274e..3ee2d406373b 100644 --- a/include/asm-sparc64/pgalloc.h +++ b/include/asm-sparc64/pgalloc.h | |||
| @@ -43,11 +43,18 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, | |||
| 43 | return quicklist_alloc(0, GFP_KERNEL, NULL); | 43 | return quicklist_alloc(0, GFP_KERNEL, NULL); |
| 44 | } | 44 | } |
| 45 | 45 | ||
| 46 | static inline struct page *pte_alloc_one(struct mm_struct *mm, | 46 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, |
| 47 | unsigned long address) | 47 | unsigned long address) |
| 48 | { | 48 | { |
| 49 | void *pg = quicklist_alloc(0, GFP_KERNEL, NULL); | 49 | struct page *page; |
| 50 | return pg ? virt_to_page(pg) : NULL; | 50 | void *pg; |
| 51 | |||
| 52 | pg = quicklist_alloc(0, GFP_KERNEL, NULL); | ||
| 53 | if (!pg) | ||
| 54 | return NULL; | ||
| 55 | page = virt_to_page(pg); | ||
| 56 | pgtable_page_ctor(page); | ||
| 57 | return page; | ||
| 51 | } | 58 | } |
| 52 | 59 | ||
| 53 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | 60 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) |
| @@ -55,8 +62,9 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 55 | quicklist_free(0, NULL, pte); | 62 | quicklist_free(0, NULL, pte); |
| 56 | } | 63 | } |
| 57 | 64 | ||
| 58 | static inline void pte_free(struct mm_struct *mm, struct page *ptepage) | 65 | static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage) |
| 59 | { | 66 | { |
| 67 | pgtable_page_dtor(ptepage); | ||
| 60 | quicklist_free_page(0, NULL, ptepage); | 68 | quicklist_free_page(0, NULL, ptepage); |
| 61 | } | 69 | } |
| 62 | 70 | ||
| @@ -64,6 +72,7 @@ static inline void pte_free(struct mm_struct *mm, struct page *ptepage) | |||
| 64 | #define pmd_populate_kernel(MM, PMD, PTE) pmd_set(PMD, PTE) | 72 | #define pmd_populate_kernel(MM, PMD, PTE) pmd_set(PMD, PTE) |
| 65 | #define pmd_populate(MM,PMD,PTE_PAGE) \ | 73 | #define pmd_populate(MM,PMD,PTE_PAGE) \ |
| 66 | pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE)) | 74 | pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE)) |
| 75 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 67 | 76 | ||
| 68 | static inline void check_pgt_cache(void) | 77 | static inline void check_pgt_cache(void) |
| 69 | { | 78 | { |
diff --git a/include/asm-sparc64/posix_types.h b/include/asm-sparc64/posix_types.h index 3426a65ecd35..4eaaa0196636 100644 --- a/include/asm-sparc64/posix_types.h +++ b/include/asm-sparc64/posix_types.h | |||
| @@ -43,14 +43,10 @@ typedef long long __kernel_loff_t; | |||
| 43 | #endif | 43 | #endif |
| 44 | 44 | ||
| 45 | typedef struct { | 45 | typedef struct { |
| 46 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 47 | int val[2]; | 46 | int val[2]; |
| 48 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 49 | int __val[2]; | ||
| 50 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 51 | } __kernel_fsid_t; | 47 | } __kernel_fsid_t; |
| 52 | 48 | ||
| 53 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 49 | #if defined(__KERNEL__) |
| 54 | 50 | ||
| 55 | #undef __FD_SET | 51 | #undef __FD_SET |
| 56 | static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) | 52 | static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp) |
| @@ -121,6 +117,6 @@ static inline void __FD_ZERO(__kernel_fd_set *p) | |||
| 121 | } | 117 | } |
| 122 | } | 118 | } |
| 123 | 119 | ||
| 124 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 120 | #endif /* defined(__KERNEL__) */ |
| 125 | 121 | ||
| 126 | #endif /* !(__ARCH_SPARC64_POSIX_TYPES_H) */ | 122 | #endif /* !(__ARCH_SPARC64_POSIX_TYPES_H) */ |
diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h index 66dd2fa0e319..8da484c19822 100644 --- a/include/asm-sparc64/processor.h +++ b/include/asm-sparc64/processor.h | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | #define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; }) | 14 | #define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; }) |
| 15 | 15 | ||
| 16 | #include <asm/asi.h> | 16 | #include <asm/asi.h> |
| 17 | #include <asm/a.out.h> | ||
| 18 | #include <asm/pstate.h> | 17 | #include <asm/pstate.h> |
| 19 | #include <asm/ptrace.h> | 18 | #include <asm/ptrace.h> |
| 20 | #include <asm/page.h> | 19 | #include <asm/page.h> |
| @@ -36,7 +35,19 @@ | |||
| 36 | #else | 35 | #else |
| 37 | #define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3)) | 36 | #define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3)) |
| 38 | #endif | 37 | #endif |
| 38 | |||
| 39 | #define TASK_SIZE ((unsigned long)-VPTE_SIZE) | 39 | #define TASK_SIZE ((unsigned long)-VPTE_SIZE) |
| 40 | #ifdef __KERNEL__ | ||
| 41 | |||
| 42 | #define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE) | ||
| 43 | #define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL)) | ||
| 44 | |||
| 45 | #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ | ||
| 46 | STACK_TOP32 : STACK_TOP64) | ||
| 47 | |||
| 48 | #define STACK_TOP_MAX STACK_TOP64 | ||
| 49 | |||
| 50 | #endif | ||
| 40 | 51 | ||
| 41 | #ifndef __ASSEMBLY__ | 52 | #ifndef __ASSEMBLY__ |
| 42 | 53 | ||
diff --git a/include/asm-sparc64/ptrace.h b/include/asm-sparc64/ptrace.h index 734a767f0a4e..8617c3a5143b 100644 --- a/include/asm-sparc64/ptrace.h +++ b/include/asm-sparc64/ptrace.h | |||
| @@ -95,6 +95,8 @@ struct sparc_trapf { | |||
| 95 | 95 | ||
| 96 | #ifdef __KERNEL__ | 96 | #ifdef __KERNEL__ |
| 97 | 97 | ||
| 98 | #define __ARCH_WANT_COMPAT_SYS_PTRACE | ||
| 99 | |||
| 98 | #define force_successful_syscall_return() \ | 100 | #define force_successful_syscall_return() \ |
| 99 | do { current_thread_info()->syscall_noerror = 1; \ | 101 | do { current_thread_info()->syscall_noerror = 1; \ |
| 100 | } while (0) | 102 | } while (0) |
diff --git a/include/asm-sparc64/uaccess.h b/include/asm-sparc64/uaccess.h index 93720e7b0289..d8547b87e730 100644 --- a/include/asm-sparc64/uaccess.h +++ b/include/asm-sparc64/uaccess.h | |||
| @@ -10,7 +10,6 @@ | |||
| 10 | #include <linux/compiler.h> | 10 | #include <linux/compiler.h> |
| 11 | #include <linux/sched.h> | 11 | #include <linux/sched.h> |
| 12 | #include <linux/string.h> | 12 | #include <linux/string.h> |
| 13 | #include <asm/a.out.h> | ||
| 14 | #include <asm/asi.h> | 13 | #include <asm/asi.h> |
| 15 | #include <asm/system.h> | 14 | #include <asm/system.h> |
| 16 | #include <asm/spitfire.h> | 15 | #include <asm/spitfire.h> |
diff --git a/include/asm-sparc64/user.h b/include/asm-sparc64/user.h index fce4e857dfc3..02b138943837 100644 --- a/include/asm-sparc64/user.h +++ b/include/asm-sparc64/user.h | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | #ifndef _SPARC64_USER_H | 8 | #ifndef _SPARC64_USER_H |
| 9 | #define _SPARC64_USER_H | 9 | #define _SPARC64_USER_H |
| 10 | 10 | ||
| 11 | #include <asm/a.out.h> | 11 | #include <linux/a.out.h> |
| 12 | struct sunos_regs { | 12 | struct sunos_regs { |
| 13 | unsigned int psr, pc, npc, y; | 13 | unsigned int psr, pc, npc, y; |
| 14 | unsigned int regs[15]; | 14 | unsigned int regs[15]; |
diff --git a/include/asm-um/a.out-core.h b/include/asm-um/a.out-core.h new file mode 100644 index 000000000000..995643b18309 --- /dev/null +++ b/include/asm-um/a.out-core.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | /* a.out coredump register dumper | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __UM_A_OUT_CORE_H | ||
| 13 | #define __UM_A_OUT_CORE_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #include <linux/user.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * fill in the user structure for an a.out core dump | ||
| 21 | */ | ||
| 22 | static inline void aout_dump_thread(struct pt_regs *regs, struct user *u) | ||
| 23 | { | ||
| 24 | } | ||
| 25 | |||
| 26 | #endif /* __KERNEL__ */ | ||
| 27 | #endif /* __UM_A_OUT_CORE_H */ | ||
diff --git a/include/asm-um/a.out.h b/include/asm-um/a.out.h index f42ff14577fa..754181ee8683 100644 --- a/include/asm-um/a.out.h +++ b/include/asm-um/a.out.h | |||
| @@ -8,15 +8,4 @@ | |||
| 8 | 8 | ||
| 9 | #include "asm/arch/a.out.h" | 9 | #include "asm/arch/a.out.h" |
| 10 | 10 | ||
| 11 | #undef STACK_TOP | ||
| 12 | #undef STACK_TOP_MAX | ||
| 13 | |||
| 14 | extern unsigned long stacksizelim; | ||
| 15 | |||
| 16 | #define STACK_ROOM (stacksizelim) | ||
| 17 | |||
| 18 | #define STACK_TOP (TASK_SIZE - 2 * PAGE_SIZE) | ||
| 19 | |||
| 20 | #define STACK_TOP_MAX STACK_TOP | ||
| 21 | |||
| 22 | #endif | 11 | #endif |
diff --git a/include/asm-um/fixmap.h b/include/asm-um/fixmap.h index 89a87c18b927..9d2be52b8655 100644 --- a/include/asm-um/fixmap.h +++ b/include/asm-um/fixmap.h | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | #ifndef __UM_FIXMAP_H | 1 | #ifndef __UM_FIXMAP_H |
| 2 | #define __UM_FIXMAP_H | 2 | #define __UM_FIXMAP_H |
| 3 | 3 | ||
| 4 | #include <asm/processor.h> | ||
| 4 | #include <asm/system.h> | 5 | #include <asm/system.h> |
| 5 | #include <asm/kmap_types.h> | 6 | #include <asm/kmap_types.h> |
| 6 | #include <asm/archparam.h> | 7 | #include <asm/archparam.h> |
| @@ -57,7 +58,7 @@ extern void __set_fixmap (enum fixed_addresses idx, | |||
| 57 | * at the top of mem.. | 58 | * at the top of mem.. |
| 58 | */ | 59 | */ |
| 59 | 60 | ||
| 60 | #define FIXADDR_TOP (CONFIG_TOP_ADDR - 2 * PAGE_SIZE) | 61 | #define FIXADDR_TOP (TASK_SIZE - 2 * PAGE_SIZE) |
| 61 | #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) | 62 | #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) |
| 62 | #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) | 63 | #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) |
| 63 | 64 | ||
diff --git a/include/asm-um/page.h b/include/asm-um/page.h index fe2374d705d1..381f96b1c825 100644 --- a/include/asm-um/page.h +++ b/include/asm-um/page.h | |||
| @@ -79,6 +79,8 @@ typedef unsigned long phys_t; | |||
| 79 | 79 | ||
| 80 | typedef struct { unsigned long pgprot; } pgprot_t; | 80 | typedef struct { unsigned long pgprot; } pgprot_t; |
| 81 | 81 | ||
| 82 | typedef struct page *pgtable_t; | ||
| 83 | |||
| 82 | #define pgd_val(x) ((x).pgd) | 84 | #define pgd_val(x) ((x).pgd) |
| 83 | #define pgprot_val(x) ((x).pgprot) | 85 | #define pgprot_val(x) ((x).pgprot) |
| 84 | 86 | ||
diff --git a/include/asm-um/pgalloc.h b/include/asm-um/pgalloc.h index 4f3e62b02861..9062a6e72241 100644 --- a/include/asm-um/pgalloc.h +++ b/include/asm-um/pgalloc.h | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | set_pmd(pmd, __pmd(_PAGE_TABLE + \ | 18 | set_pmd(pmd, __pmd(_PAGE_TABLE + \ |
| 19 | ((unsigned long long)page_to_pfn(pte) << \ | 19 | ((unsigned long long)page_to_pfn(pte) << \ |
| 20 | (unsigned long long) PAGE_SHIFT))) | 20 | (unsigned long long) PAGE_SHIFT))) |
| 21 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 21 | 22 | ||
| 22 | /* | 23 | /* |
| 23 | * Allocate and free page tables. | 24 | * Allocate and free page tables. |
| @@ -26,19 +27,24 @@ extern pgd_t *pgd_alloc(struct mm_struct *); | |||
| 26 | extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); | 27 | extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); |
| 27 | 28 | ||
| 28 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); | 29 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); |
| 29 | extern struct page *pte_alloc_one(struct mm_struct *, unsigned long); | 30 | extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long); |
| 30 | 31 | ||
| 31 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | 32 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) |
| 32 | { | 33 | { |
| 33 | free_page((unsigned long) pte); | 34 | free_page((unsigned long) pte); |
| 34 | } | 35 | } |
| 35 | 36 | ||
| 36 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 37 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 37 | { | 38 | { |
| 39 | pgtable_page_dtor(pte); | ||
| 38 | __free_page(pte); | 40 | __free_page(pte); |
| 39 | } | 41 | } |
| 40 | 42 | ||
| 41 | #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) | 43 | #define __pte_free_tlb(tlb,pte) \ |
| 44 | do { \ | ||
| 45 | pgtable_page_dtor(pte); \ | ||
| 46 | tlb_remove_page((tlb),(pte)); \ | ||
| 47 | } while (0) | ||
| 42 | 48 | ||
| 43 | #ifdef CONFIG_3_LEVEL_PGTABLES | 49 | #ifdef CONFIG_3_LEVEL_PGTABLES |
| 44 | 50 | ||
diff --git a/include/asm-um/processor-generic.h b/include/asm-um/processor-generic.h index b7d9a16a7451..bed668824b5f 100644 --- a/include/asm-um/processor-generic.h +++ b/include/asm-um/processor-generic.h | |||
| @@ -11,7 +11,6 @@ struct pt_regs; | |||
| 11 | struct task_struct; | 11 | struct task_struct; |
| 12 | 12 | ||
| 13 | #include "asm/ptrace.h" | 13 | #include "asm/ptrace.h" |
| 14 | #include "asm/pgtable.h" | ||
| 15 | #include "registers.h" | 14 | #include "registers.h" |
| 16 | #include "sysdep/archsetjmp.h" | 15 | #include "sysdep/archsetjmp.h" |
| 17 | 16 | ||
| @@ -92,7 +91,18 @@ static inline void mm_copy_segments(struct mm_struct *from_mm, | |||
| 92 | /* | 91 | /* |
| 93 | * User space process size: 3GB (default). | 92 | * User space process size: 3GB (default). |
| 94 | */ | 93 | */ |
| 95 | #define TASK_SIZE (CONFIG_TOP_ADDR & PGDIR_MASK) | 94 | extern unsigned long task_size; |
| 95 | |||
| 96 | #define TASK_SIZE (task_size) | ||
| 97 | |||
| 98 | #undef STACK_TOP | ||
| 99 | #undef STACK_TOP_MAX | ||
| 100 | |||
| 101 | extern unsigned long stacksizelim; | ||
| 102 | |||
| 103 | #define STACK_ROOM (stacksizelim) | ||
| 104 | #define STACK_TOP (TASK_SIZE - 2 * PAGE_SIZE) | ||
| 105 | #define STACK_TOP_MAX STACK_TOP | ||
| 96 | 106 | ||
| 97 | /* This decides where the kernel will search for a free chunk of vm | 107 | /* This decides where the kernel will search for a free chunk of vm |
| 98 | * space during mmap's. | 108 | * space during mmap's. |
diff --git a/include/asm-um/processor-x86_64.h b/include/asm-um/processor-x86_64.h index d946bf2d334a..e50933175e91 100644 --- a/include/asm-um/processor-x86_64.h +++ b/include/asm-um/processor-x86_64.h | |||
| @@ -26,7 +26,7 @@ static inline void rep_nop(void) | |||
| 26 | #define cpu_relax() rep_nop() | 26 | #define cpu_relax() rep_nop() |
| 27 | 27 | ||
| 28 | #define INIT_ARCH_THREAD { .debugregs = { [ 0 ... 7 ] = 0 }, \ | 28 | #define INIT_ARCH_THREAD { .debugregs = { [ 0 ... 7 ] = 0 }, \ |
| 29 | .debugregs_seq = 0, \ | 29 | .debugregs_seq = 0, \ |
| 30 | .fs = 0, \ | 30 | .fs = 0, \ |
| 31 | .faultinfo = { 0, 0, 0 } } | 31 | .faultinfo = { 0, 0, 0 } } |
| 32 | 32 | ||
| @@ -37,6 +37,7 @@ static inline void arch_flush_thread(struct arch_thread *thread) | |||
| 37 | static inline void arch_copy_thread(struct arch_thread *from, | 37 | static inline void arch_copy_thread(struct arch_thread *from, |
| 38 | struct arch_thread *to) | 38 | struct arch_thread *to) |
| 39 | { | 39 | { |
| 40 | to->fs = from->fs; | ||
| 40 | } | 41 | } |
| 41 | 42 | ||
| 42 | #include "asm/arch/user.h" | 43 | #include "asm/arch/user.h" |
diff --git a/include/asm-v850/anna.h b/include/asm-v850/anna.h index 3be77d5ecfce..cd5eaee103b0 100644 --- a/include/asm-v850/anna.h +++ b/include/asm-v850/anna.h | |||
| @@ -134,10 +134,4 @@ extern void anna_uart_pre_configure (unsigned chan, | |||
| 134 | #define V850E_TIMER_D_TMCD_CS_MIN 1 /* min 2^1 divider */ | 134 | #define V850E_TIMER_D_TMCD_CS_MIN 1 /* min 2^1 divider */ |
| 135 | 135 | ||
| 136 | 136 | ||
| 137 | /* For <asm/param.h> */ | ||
| 138 | #ifndef HZ | ||
| 139 | #define HZ 100 | ||
| 140 | #endif | ||
| 141 | |||
| 142 | |||
| 143 | #endif /* __V850_ANNA_H__ */ | 137 | #endif /* __V850_ANNA_H__ */ |
diff --git a/include/asm-v850/as85ep1.h b/include/asm-v850/as85ep1.h index 659bc910ffd7..5a5ca9073d09 100644 --- a/include/asm-v850/as85ep1.h +++ b/include/asm-v850/as85ep1.h | |||
| @@ -149,10 +149,4 @@ extern void as85ep1_uart_pre_configure (unsigned chan, | |||
| 149 | #define V850E_TIMER_D_TMCD_CS_MIN 2 /* min 2^2 divider */ | 149 | #define V850E_TIMER_D_TMCD_CS_MIN 2 /* min 2^2 divider */ |
| 150 | 150 | ||
| 151 | 151 | ||
| 152 | /* For <asm/param.h> */ | ||
| 153 | #ifndef HZ | ||
| 154 | #define HZ 100 | ||
| 155 | #endif | ||
| 156 | |||
| 157 | |||
| 158 | #endif /* __V850_AS85EP1_H__ */ | 152 | #endif /* __V850_AS85EP1_H__ */ |
diff --git a/include/asm-v850/fpga85e2c.h b/include/asm-v850/fpga85e2c.h index d32f04504b13..23aae666c718 100644 --- a/include/asm-v850/fpga85e2c.h +++ b/include/asm-v850/fpga85e2c.h | |||
| @@ -79,10 +79,4 @@ extern char _r0_ram; | |||
| 79 | #endif | 79 | #endif |
| 80 | 80 | ||
| 81 | 81 | ||
| 82 | /* For <asm/param.h> */ | ||
| 83 | #ifndef HZ | ||
| 84 | #define HZ 122 /* actually, 8.192ms ticks =~ 122.07 */ | ||
| 85 | #endif | ||
| 86 | |||
| 87 | |||
| 88 | #endif /* __V850_FPGA85E2C_H__ */ | 82 | #endif /* __V850_FPGA85E2C_H__ */ |
diff --git a/include/asm-v850/param.h b/include/asm-v850/param.h index 3c65bd573782..281832690290 100644 --- a/include/asm-v850/param.h +++ b/include/asm-v850/param.h | |||
| @@ -23,8 +23,7 @@ | |||
| 23 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | 23 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ |
| 24 | 24 | ||
| 25 | #ifdef __KERNEL__ | 25 | #ifdef __KERNEL__ |
| 26 | #include <asm/machdep.h> /* For HZ */ | 26 | # define HZ CONFIG_HZ |
| 27 | |||
| 28 | # define USER_HZ 100 | 27 | # define USER_HZ 100 |
| 29 | # define CLOCKS_PER_SEC USER_HZ | 28 | # define CLOCKS_PER_SEC USER_HZ |
| 30 | #endif | 29 | #endif |
diff --git a/include/asm-v850/posix_types.h b/include/asm-v850/posix_types.h index ccb7297a0edc..7f403b765390 100644 --- a/include/asm-v850/posix_types.h +++ b/include/asm-v850/posix_types.h | |||
| @@ -44,15 +44,11 @@ typedef __kernel_uid_t __kernel_old_uid_t; | |||
| 44 | typedef unsigned int __kernel_old_dev_t; | 44 | typedef unsigned int __kernel_old_dev_t; |
| 45 | 45 | ||
| 46 | typedef struct { | 46 | typedef struct { |
| 47 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 48 | int val[2]; | 47 | int val[2]; |
| 49 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 50 | int __val[2]; | ||
| 51 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 52 | } __kernel_fsid_t; | 48 | } __kernel_fsid_t; |
| 53 | 49 | ||
| 54 | 50 | ||
| 55 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 51 | #if defined(__KERNEL__) |
| 56 | 52 | ||
| 57 | /* We used to include <asm/bitops.h> here, which seems the right thing, but | 53 | /* We used to include <asm/bitops.h> here, which seems the right thing, but |
| 58 | it caused nasty include-file definition order problems. Removing the | 54 | it caused nasty include-file definition order problems. Removing the |
| @@ -71,6 +67,6 @@ typedef struct { | |||
| 71 | #define __FD_ZERO(fd_set) \ | 67 | #define __FD_ZERO(fd_set) \ |
| 72 | memset (fd_set, 0, sizeof (*(fd_set *)fd_set)) | 68 | memset (fd_set, 0, sizeof (*(fd_set *)fd_set)) |
| 73 | 69 | ||
| 74 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 70 | #endif /* defined(__KERNEL__) */ |
| 75 | 71 | ||
| 76 | #endif /* __V850_POSIX_TYPES_H__ */ | 72 | #endif /* __V850_POSIX_TYPES_H__ */ |
diff --git a/include/asm-v850/rte_cb.h b/include/asm-v850/rte_cb.h index e85d261b79bf..db9879f00aa7 100644 --- a/include/asm-v850/rte_cb.h +++ b/include/asm-v850/rte_cb.h | |||
| @@ -69,12 +69,6 @@ | |||
| 69 | #endif /* CONFIG_RTE_MB_A_PCI */ | 69 | #endif /* CONFIG_RTE_MB_A_PCI */ |
| 70 | 70 | ||
| 71 | 71 | ||
| 72 | /* For <asm/param.h> */ | ||
| 73 | #ifndef HZ | ||
| 74 | #define HZ 100 | ||
| 75 | #endif | ||
| 76 | |||
| 77 | |||
| 78 | #ifndef __ASSEMBLY__ | 72 | #ifndef __ASSEMBLY__ |
| 79 | extern void rte_cb_early_init (void); | 73 | extern void rte_cb_early_init (void); |
| 80 | extern void rte_cb_init_irqs (void); | 74 | extern void rte_cb_init_irqs (void); |
diff --git a/include/asm-v850/sim.h b/include/asm-v850/sim.h index 10236abbe9be..026932d476cd 100644 --- a/include/asm-v850/sim.h +++ b/include/asm-v850/sim.h | |||
| @@ -40,11 +40,6 @@ | |||
| 40 | #define R0_RAM_ADDR 0xFFFFF000 | 40 | #define R0_RAM_ADDR 0xFFFFF000 |
| 41 | 41 | ||
| 42 | 42 | ||
| 43 | /* For <asm/param.h> */ | ||
| 44 | #ifndef HZ | ||
| 45 | #define HZ 24 /* Minimum supported frequency. */ | ||
| 46 | #endif | ||
| 47 | |||
| 48 | /* For <asm/irq.h> */ | 43 | /* For <asm/irq.h> */ |
| 49 | #define NUM_CPU_IRQS 6 | 44 | #define NUM_CPU_IRQS 6 |
| 50 | 45 | ||
diff --git a/include/asm-v850/sim85e2.h b/include/asm-v850/sim85e2.h index 17dd4fa318e6..8b4d6974066c 100644 --- a/include/asm-v850/sim85e2.h +++ b/include/asm-v850/sim85e2.h | |||
| @@ -66,10 +66,4 @@ | |||
| 66 | #define R0_RAM_ADDR 0xFFFFE000 | 66 | #define R0_RAM_ADDR 0xFFFFE000 |
| 67 | 67 | ||
| 68 | 68 | ||
| 69 | /* For <asm/param.h> */ | ||
| 70 | #ifndef HZ | ||
| 71 | #define HZ 24 /* Minimum supported frequency. */ | ||
| 72 | #endif | ||
| 73 | |||
| 74 | |||
| 75 | #endif /* __V850_SIM85E2_H__ */ | 69 | #endif /* __V850_SIM85E2_H__ */ |
diff --git a/include/asm-x86/a.out-core.h b/include/asm-x86/a.out-core.h new file mode 100644 index 000000000000..d2b6e11d3e97 --- /dev/null +++ b/include/asm-x86/a.out-core.h | |||
| @@ -0,0 +1,71 @@ | |||
| 1 | /* a.out coredump register dumper | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_A_OUT_CORE_H | ||
| 13 | #define _ASM_A_OUT_CORE_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | #ifdef CONFIG_X86_32 | ||
| 17 | |||
| 18 | #include <linux/user.h> | ||
| 19 | #include <linux/elfcore.h> | ||
| 20 | |||
| 21 | /* | ||
| 22 | * fill in the user structure for an a.out core dump | ||
| 23 | */ | ||
| 24 | static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) | ||
| 25 | { | ||
| 26 | u16 gs; | ||
| 27 | |||
| 28 | /* changed the size calculations - should hopefully work better. lbt */ | ||
| 29 | dump->magic = CMAGIC; | ||
| 30 | dump->start_code = 0; | ||
| 31 | dump->start_stack = regs->sp & ~(PAGE_SIZE - 1); | ||
| 32 | dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT; | ||
| 33 | dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1))) >> PAGE_SHIFT; | ||
| 34 | dump->u_dsize -= dump->u_tsize; | ||
| 35 | dump->u_ssize = 0; | ||
| 36 | dump->u_debugreg[0] = current->thread.debugreg0; | ||
| 37 | dump->u_debugreg[1] = current->thread.debugreg1; | ||
| 38 | dump->u_debugreg[2] = current->thread.debugreg2; | ||
| 39 | dump->u_debugreg[3] = current->thread.debugreg3; | ||
| 40 | dump->u_debugreg[4] = 0; | ||
| 41 | dump->u_debugreg[5] = 0; | ||
| 42 | dump->u_debugreg[6] = current->thread.debugreg6; | ||
| 43 | dump->u_debugreg[7] = current->thread.debugreg7; | ||
| 44 | |||
| 45 | if (dump->start_stack < TASK_SIZE) | ||
| 46 | dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT; | ||
| 47 | |||
| 48 | dump->regs.bx = regs->bx; | ||
| 49 | dump->regs.cx = regs->cx; | ||
| 50 | dump->regs.dx = regs->dx; | ||
| 51 | dump->regs.si = regs->si; | ||
| 52 | dump->regs.di = regs->di; | ||
| 53 | dump->regs.bp = regs->bp; | ||
| 54 | dump->regs.ax = regs->ax; | ||
| 55 | dump->regs.ds = (u16)regs->ds; | ||
| 56 | dump->regs.es = (u16)regs->es; | ||
| 57 | dump->regs.fs = (u16)regs->fs; | ||
| 58 | savesegment(gs,gs); | ||
| 59 | dump->regs.orig_ax = regs->orig_ax; | ||
| 60 | dump->regs.ip = regs->ip; | ||
| 61 | dump->regs.cs = (u16)regs->cs; | ||
| 62 | dump->regs.flags = regs->flags; | ||
| 63 | dump->regs.sp = regs->sp; | ||
| 64 | dump->regs.ss = (u16)regs->ss; | ||
| 65 | |||
| 66 | dump->u_fpvalid = dump_fpu (regs, &dump->i387); | ||
| 67 | } | ||
| 68 | |||
| 69 | #endif /* CONFIG_X86_32 */ | ||
| 70 | #endif /* __KERNEL__ */ | ||
| 71 | #endif /* _ASM_A_OUT_CORE_H */ | ||
diff --git a/include/asm-x86/a.out.h b/include/asm-x86/a.out.h index a62443e38eb8..4684f97a5bbd 100644 --- a/include/asm-x86/a.out.h +++ b/include/asm-x86/a.out.h | |||
| @@ -17,14 +17,4 @@ struct exec | |||
| 17 | #define N_DRSIZE(a) ((a).a_drsize) | 17 | #define N_DRSIZE(a) ((a).a_drsize) |
| 18 | #define N_SYMSIZE(a) ((a).a_syms) | 18 | #define N_SYMSIZE(a) ((a).a_syms) |
| 19 | 19 | ||
| 20 | #ifdef __KERNEL__ | ||
| 21 | # include <linux/thread_info.h> | ||
| 22 | # define STACK_TOP TASK_SIZE | ||
| 23 | # ifdef CONFIG_X86_32 | ||
| 24 | # define STACK_TOP_MAX STACK_TOP | ||
| 25 | # else | ||
| 26 | # define STACK_TOP_MAX TASK_SIZE64 | ||
| 27 | # endif | ||
| 28 | #endif | ||
| 29 | |||
| 30 | #endif /* _ASM_X86_A_OUT_H */ | 20 | #endif /* _ASM_X86_A_OUT_H */ |
diff --git a/include/asm-x86/page_32.h b/include/asm-x86/page_32.h index a6fd10f230d2..984998a30741 100644 --- a/include/asm-x86/page_32.h +++ b/include/asm-x86/page_32.h | |||
| @@ -53,6 +53,10 @@ typedef pte_t boot_pte_t; | |||
| 53 | #endif /* __ASSEMBLY__ */ | 53 | #endif /* __ASSEMBLY__ */ |
| 54 | #endif /* CONFIG_X86_PAE */ | 54 | #endif /* CONFIG_X86_PAE */ |
| 55 | 55 | ||
| 56 | #ifndef __ASSEMBLY__ | ||
| 57 | typedef struct page *pgtable_t; | ||
| 58 | #endif | ||
| 59 | |||
| 56 | #ifdef CONFIG_HUGETLB_PAGE | 60 | #ifdef CONFIG_HUGETLB_PAGE |
| 57 | #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA | 61 | #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA |
| 58 | #endif | 62 | #endif |
diff --git a/include/asm-x86/page_64.h b/include/asm-x86/page_64.h index dcf0c0746075..f7393bc516ef 100644 --- a/include/asm-x86/page_64.h +++ b/include/asm-x86/page_64.h | |||
| @@ -71,6 +71,8 @@ typedef unsigned long pgdval_t; | |||
| 71 | typedef unsigned long pgprotval_t; | 71 | typedef unsigned long pgprotval_t; |
| 72 | typedef unsigned long phys_addr_t; | 72 | typedef unsigned long phys_addr_t; |
| 73 | 73 | ||
| 74 | typedef struct page *pgtable_t; | ||
| 75 | |||
| 74 | typedef struct { pteval_t pte; } pte_t; | 76 | typedef struct { pteval_t pte; } pte_t; |
| 75 | 77 | ||
| 76 | #define vmemmap ((struct page *)VMEMMAP_START) | 78 | #define vmemmap ((struct page *)VMEMMAP_START) |
diff --git a/include/asm-x86/pgalloc_32.h b/include/asm-x86/pgalloc_32.h index bab12718a913..6bea6e5b5ee5 100644 --- a/include/asm-x86/pgalloc_32.h +++ b/include/asm-x86/pgalloc_32.h | |||
| @@ -31,6 +31,7 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *p | |||
| 31 | paravirt_alloc_pt(mm, pfn); | 31 | paravirt_alloc_pt(mm, pfn); |
| 32 | set_pmd(pmd, __pmd(((pteval_t)pfn << PAGE_SHIFT) | _PAGE_TABLE)); | 32 | set_pmd(pmd, __pmd(((pteval_t)pfn << PAGE_SHIFT) | _PAGE_TABLE)); |
| 33 | } | 33 | } |
| 34 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 34 | 35 | ||
| 35 | /* | 36 | /* |
| 36 | * Allocate and free page tables. | 37 | * Allocate and free page tables. |
| @@ -39,15 +40,16 @@ extern pgd_t *pgd_alloc(struct mm_struct *); | |||
| 39 | extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); | 40 | extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); |
| 40 | 41 | ||
| 41 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); | 42 | extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long); |
| 42 | extern struct page *pte_alloc_one(struct mm_struct *, unsigned long); | 43 | extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long); |
| 43 | 44 | ||
| 44 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | 45 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) |
| 45 | { | 46 | { |
| 46 | free_page((unsigned long)pte); | 47 | free_page((unsigned long)pte); |
| 47 | } | 48 | } |
| 48 | 49 | ||
| 49 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 50 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 50 | { | 51 | { |
| 52 | pgtable_page_dtor(pte); | ||
| 51 | __free_page(pte); | 53 | __free_page(pte); |
| 52 | } | 54 | } |
| 53 | 55 | ||
diff --git a/include/asm-x86/pgalloc_64.h b/include/asm-x86/pgalloc_64.h index 4f6220db22b1..8d6722320dcc 100644 --- a/include/asm-x86/pgalloc_64.h +++ b/include/asm-x86/pgalloc_64.h | |||
| @@ -12,6 +12,8 @@ | |||
| 12 | #define pgd_populate(mm, pgd, pud) \ | 12 | #define pgd_populate(mm, pgd, pud) \ |
| 13 | set_pgd(pgd, __pgd(_PAGE_TABLE | __pa(pud))) | 13 | set_pgd(pgd, __pgd(_PAGE_TABLE | __pa(pud))) |
| 14 | 14 | ||
| 15 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 16 | |||
| 15 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte) | 17 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte) |
| 16 | { | 18 | { |
| 17 | set_pmd(pmd, __pmd(_PAGE_TABLE | (page_to_pfn(pte) << PAGE_SHIFT))); | 19 | set_pmd(pmd, __pmd(_PAGE_TABLE | (page_to_pfn(pte) << PAGE_SHIFT))); |
| @@ -91,12 +93,17 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long ad | |||
| 91 | return (pte_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT); | 93 | return (pte_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT); |
| 92 | } | 94 | } |
| 93 | 95 | ||
| 94 | static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) | 96 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) |
| 95 | { | 97 | { |
| 96 | void *p = (void *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT); | 98 | struct page *page; |
| 99 | void *p; | ||
| 100 | |||
| 101 | p = (void *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT); | ||
| 97 | if (!p) | 102 | if (!p) |
| 98 | return NULL; | 103 | return NULL; |
| 99 | return virt_to_page(p); | 104 | page = virt_to_page(p); |
| 105 | pgtable_page_ctor(page); | ||
| 106 | return page; | ||
| 100 | } | 107 | } |
| 101 | 108 | ||
| 102 | /* Should really implement gc for free page table pages. This could be | 109 | /* Should really implement gc for free page table pages. This could be |
| @@ -108,12 +115,17 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 108 | free_page((unsigned long)pte); | 115 | free_page((unsigned long)pte); |
| 109 | } | 116 | } |
| 110 | 117 | ||
| 111 | static inline void pte_free(struct mm_struct *mm, struct page *pte) | 118 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 112 | { | 119 | { |
| 120 | pgtable_page_dtor(pte); | ||
| 113 | __free_page(pte); | 121 | __free_page(pte); |
| 114 | } | 122 | } |
| 115 | 123 | ||
| 116 | #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) | 124 | #define __pte_free_tlb(tlb,pte) \ |
| 125 | do { \ | ||
| 126 | pgtable_page_dtor((pte)); \ | ||
| 127 | tlb_remove_page((tlb), (pte)); \ | ||
| 128 | } while (0) | ||
| 117 | 129 | ||
| 118 | #define __pmd_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x)) | 130 | #define __pmd_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x)) |
| 119 | #define __pud_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x)) | 131 | #define __pud_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x)) |
diff --git a/include/asm-x86/posix_types_32.h b/include/asm-x86/posix_types_32.h index 133e31e7dfde..015e539cdef5 100644 --- a/include/asm-x86/posix_types_32.h +++ b/include/asm-x86/posix_types_32.h | |||
| @@ -39,14 +39,10 @@ typedef long long __kernel_loff_t; | |||
| 39 | #endif | 39 | #endif |
| 40 | 40 | ||
| 41 | typedef struct { | 41 | typedef struct { |
| 42 | #if defined(__KERNEL__) || defined(__USE_ALL) | ||
| 43 | int val[2]; | 42 | int val[2]; |
| 44 | #else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 45 | int __val[2]; | ||
| 46 | #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ | ||
| 47 | } __kernel_fsid_t; | 43 | } __kernel_fsid_t; |
| 48 | 44 | ||
| 49 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) | 45 | #if defined(__KERNEL__) |
| 50 | 46 | ||
| 51 | #undef __FD_SET | 47 | #undef __FD_SET |
| 52 | #define __FD_SET(fd,fdsetp) \ | 48 | #define __FD_SET(fd,fdsetp) \ |
| @@ -77,6 +73,6 @@ do { \ | |||
| 77 | "2" ((__kernel_fd_set *) (fdsetp)) : "memory"); \ | 73 | "2" ((__kernel_fd_set *) (fdsetp)) : "memory"); \ |
| 78 | } while (0) | 74 | } while (0) |
| 79 | 75 | ||
| 80 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 76 | #endif /* defined(__KERNEL__) */ |
| 81 | 77 | ||
| 82 | #endif | 78 | #endif |
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h index ab4d0c2a3f8f..149920dcd341 100644 --- a/include/asm-x86/processor.h +++ b/include/asm-x86/processor.h | |||
| @@ -719,6 +719,8 @@ static inline void prefetchw(const void *x) | |||
| 719 | * User space process size: 3GB (default). | 719 | * User space process size: 3GB (default). |
| 720 | */ | 720 | */ |
| 721 | #define TASK_SIZE (PAGE_OFFSET) | 721 | #define TASK_SIZE (PAGE_OFFSET) |
| 722 | #define STACK_TOP TASK_SIZE | ||
| 723 | #define STACK_TOP_MAX STACK_TOP | ||
| 722 | 724 | ||
| 723 | #define INIT_THREAD { \ | 725 | #define INIT_THREAD { \ |
| 724 | .sp0 = sizeof(init_stack) + (long)&init_stack, \ | 726 | .sp0 = sizeof(init_stack) + (long)&init_stack, \ |
| @@ -802,6 +804,9 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk); | |||
| 802 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ | 804 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ |
| 803 | IA32_PAGE_OFFSET : TASK_SIZE64) | 805 | IA32_PAGE_OFFSET : TASK_SIZE64) |
| 804 | 806 | ||
| 807 | #define STACK_TOP TASK_SIZE | ||
| 808 | #define STACK_TOP_MAX TASK_SIZE64 | ||
| 809 | |||
| 805 | #define INIT_THREAD { \ | 810 | #define INIT_THREAD { \ |
| 806 | .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ | 811 | .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ |
| 807 | } | 812 | } |
diff --git a/include/asm-xtensa/a.out.h b/include/asm-xtensa/a.out.h index 05a2f67c6768..fdf13702924a 100644 --- a/include/asm-xtensa/a.out.h +++ b/include/asm-xtensa/a.out.h | |||
| @@ -14,11 +14,6 @@ | |||
| 14 | #ifndef _XTENSA_A_OUT_H | 14 | #ifndef _XTENSA_A_OUT_H |
| 15 | #define _XTENSA_A_OUT_H | 15 | #define _XTENSA_A_OUT_H |
| 16 | 16 | ||
| 17 | /* Note: the kernel needs the a.out definitions, even if only ELF is used. */ | ||
| 18 | |||
| 19 | #define STACK_TOP TASK_SIZE | ||
| 20 | #define STACK_TOP_MAX STACK_TOP | ||
| 21 | |||
| 22 | struct exec | 17 | struct exec |
| 23 | { | 18 | { |
| 24 | unsigned long a_info; | 19 | unsigned long a_info; |
diff --git a/include/asm-xtensa/page.h b/include/asm-xtensa/page.h index 1adedbf41d01..80a6ae0dd259 100644 --- a/include/asm-xtensa/page.h +++ b/include/asm-xtensa/page.h | |||
| @@ -98,6 +98,7 @@ | |||
| 98 | typedef struct { unsigned long pte; } pte_t; /* page table entry */ | 98 | typedef struct { unsigned long pte; } pte_t; /* page table entry */ |
| 99 | typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */ | 99 | typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */ |
| 100 | typedef struct { unsigned long pgprot; } pgprot_t; | 100 | typedef struct { unsigned long pgprot; } pgprot_t; |
| 101 | typedef struct page *pgtable_t; | ||
| 101 | 102 | ||
| 102 | #define pte_val(x) ((x).pte) | 103 | #define pte_val(x) ((x).pte) |
| 103 | #define pgd_val(x) ((x).pgd) | 104 | #define pgd_val(x) ((x).pgd) |
diff --git a/include/asm-xtensa/param.h b/include/asm-xtensa/param.h index ce3a336cad07..82ad34d92d35 100644 --- a/include/asm-xtensa/param.h +++ b/include/asm-xtensa/param.h | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | #define _XTENSA_PARAM_H | 12 | #define _XTENSA_PARAM_H |
| 13 | 13 | ||
| 14 | #ifdef __KERNEL__ | 14 | #ifdef __KERNEL__ |
| 15 | # define HZ 100 /* internal timer frequency */ | 15 | # define HZ CONFIG_HZ /* internal timer frequency */ |
| 16 | # define USER_HZ 100 /* for user interfaces in "ticks" */ | 16 | # define USER_HZ 100 /* for user interfaces in "ticks" */ |
| 17 | # define CLOCKS_PER_SEC (USER_HZ) /* frequnzy at which times() counts */ | 17 | # define CLOCKS_PER_SEC (USER_HZ) /* frequnzy at which times() counts */ |
| 18 | #endif | 18 | #endif |
diff --git a/include/asm-xtensa/pgalloc.h b/include/asm-xtensa/pgalloc.h index 1d51ba5463f9..8d1544eb461e 100644 --- a/include/asm-xtensa/pgalloc.h +++ b/include/asm-xtensa/pgalloc.h | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | (pmd_val(*(pmdp)) = ((unsigned long)ptep)) | 24 | (pmd_val(*(pmdp)) = ((unsigned long)ptep)) |
| 25 | #define pmd_populate(mm, pmdp, page) \ | 25 | #define pmd_populate(mm, pmdp, page) \ |
| 26 | (pmd_val(*(pmdp)) = ((unsigned long)page_to_virt(page))) | 26 | (pmd_val(*(pmdp)) = ((unsigned long)page_to_virt(page))) |
| 27 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 27 | 28 | ||
| 28 | static inline pgd_t* | 29 | static inline pgd_t* |
| 29 | pgd_alloc(struct mm_struct *mm) | 30 | pgd_alloc(struct mm_struct *mm) |
| @@ -46,10 +47,14 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, | |||
| 46 | return kmem_cache_alloc(pgtable_cache, GFP_KERNEL|__GFP_REPEAT); | 47 | return kmem_cache_alloc(pgtable_cache, GFP_KERNEL|__GFP_REPEAT); |
| 47 | } | 48 | } |
| 48 | 49 | ||
| 49 | static inline struct page *pte_alloc_one(struct mm_struct *mm, | 50 | static inline pte_token_t pte_alloc_one(struct mm_struct *mm, |
| 50 | unsigned long addr) | 51 | unsigned long addr) |
| 51 | { | 52 | { |
| 52 | return virt_to_page(pte_alloc_one_kernel(mm, addr)); | 53 | struct page *page; |
| 54 | |||
| 55 | page = virt_to_page(pte_alloc_one_kernel(mm, addr)); | ||
| 56 | pgtable_page_ctor(page); | ||
| 57 | return page; | ||
| 53 | } | 58 | } |
| 54 | 59 | ||
| 55 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | 60 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) |
| @@ -57,10 +62,12 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |||
| 57 | kmem_cache_free(pgtable_cache, pte); | 62 | kmem_cache_free(pgtable_cache, pte); |
| 58 | } | 63 | } |
| 59 | 64 | ||
| 60 | static inline void pte_free(struct mm_struct *mm, struct page *page) | 65 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| 61 | { | 66 | { |
| 62 | kmem_cache_free(pgtable_cache, page_address(page)); | 67 | pgtable_page_dtor(pte); |
| 68 | kmem_cache_free(pgtable_cache, page_address(pte)); | ||
| 63 | } | 69 | } |
| 70 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 64 | 71 | ||
| 65 | #endif /* __KERNEL__ */ | 72 | #endif /* __KERNEL__ */ |
| 66 | #endif /* _XTENSA_PGALLOC_H */ | 73 | #endif /* _XTENSA_PGALLOC_H */ |
diff --git a/include/asm-xtensa/posix_types.h b/include/asm-xtensa/posix_types.h index 4ad77dda6d5f..43f9dd1126a4 100644 --- a/include/asm-xtensa/posix_types.h +++ b/include/asm-xtensa/posix_types.h | |||
| @@ -64,8 +64,7 @@ typedef struct { | |||
| 64 | 64 | ||
| 65 | #else /* __GNUC__ */ | 65 | #else /* __GNUC__ */ |
| 66 | 66 | ||
| 67 | #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \ | 67 | #if defined(__KERNEL__) |
| 68 | || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0) | ||
| 69 | /* With GNU C, use inline functions instead so args are evaluated only once: */ | 68 | /* With GNU C, use inline functions instead so args are evaluated only once: */ |
| 70 | 69 | ||
| 71 | #undef __FD_SET | 70 | #undef __FD_SET |
| @@ -118,6 +117,6 @@ static __inline__ void __FD_ZERO(__kernel_fd_set *p) | |||
| 118 | } | 117 | } |
| 119 | } | 118 | } |
| 120 | 119 | ||
| 121 | #endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ | 120 | #endif /* defined(__KERNEL__) */ |
| 122 | #endif /* __GNUC__ */ | 121 | #endif /* __GNUC__ */ |
| 123 | #endif /* _XTENSA_POSIX_TYPES_H */ | 122 | #endif /* _XTENSA_POSIX_TYPES_H */ |
diff --git a/include/asm-xtensa/processor.h b/include/asm-xtensa/processor.h index 35145bcd96eb..96408f436624 100644 --- a/include/asm-xtensa/processor.h +++ b/include/asm-xtensa/processor.h | |||
| @@ -34,6 +34,8 @@ | |||
| 34 | */ | 34 | */ |
| 35 | 35 | ||
| 36 | #define TASK_SIZE __XTENSA_UL_CONST(0x40000000) | 36 | #define TASK_SIZE __XTENSA_UL_CONST(0x40000000) |
| 37 | #define STACK_TOP TASK_SIZE | ||
| 38 | #define STACK_TOP_MAX STACK_TOP | ||
| 37 | 39 | ||
| 38 | /* | 40 | /* |
| 39 | * General exception cause assigned to debug exceptions. Debug exceptions go | 41 | * General exception cause assigned to debug exceptions. Debug exceptions go |
diff --git a/include/asm-xtensa/unistd.h b/include/asm-xtensa/unistd.h index 92968aabe34e..c092c8fbb2cf 100644 --- a/include/asm-xtensa/unistd.h +++ b/include/asm-xtensa/unistd.h | |||
| @@ -677,8 +677,8 @@ __SYSCALL(303, sys_ni_syscall, 0) | |||
| 677 | 677 | ||
| 678 | #define __NR_signalfd 304 | 678 | #define __NR_signalfd 304 |
| 679 | __SYSCALL(304, sys_signalfd, 3) | 679 | __SYSCALL(304, sys_signalfd, 3) |
| 680 | #define __NR_timerfd 305 | 680 | /* 305 was __NR_timerfd */ |
| 681 | __SYSCALL(305, sys_timerfd, 4) | 681 | __SYSCALL(305, sys_ni_syscall, 0) |
| 682 | #define __NR_eventfd 306 | 682 | #define __NR_eventfd 306 |
| 683 | __SYSCALL(306, sys_eventfd, 1) | 683 | __SYSCALL(306, sys_eventfd, 1) |
| 684 | 684 | ||
diff --git a/include/linux/Kbuild b/include/linux/Kbuild index 2ebf068ba504..5cae9b5960ea 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild | |||
| @@ -338,7 +338,6 @@ unifdef-y += tty.h | |||
| 338 | unifdef-y += types.h | 338 | unifdef-y += types.h |
| 339 | unifdef-y += udf_fs_i.h | 339 | unifdef-y += udf_fs_i.h |
| 340 | unifdef-y += udp.h | 340 | unifdef-y += udp.h |
| 341 | unifdef-y += ufs_fs.h | ||
| 342 | unifdef-y += uinput.h | 341 | unifdef-y += uinput.h |
| 343 | unifdef-y += uio.h | 342 | unifdef-y += uio.h |
| 344 | unifdef-y += unistd.h | 343 | unifdef-y += unistd.h |
diff --git a/include/linux/a.out.h b/include/linux/a.out.h index 82cd918f2ab7..208f4e8ed304 100644 --- a/include/linux/a.out.h +++ b/include/linux/a.out.h | |||
| @@ -1,6 +1,8 @@ | |||
| 1 | #ifndef __A_OUT_GNU_H__ | 1 | #ifndef __A_OUT_GNU_H__ |
| 2 | #define __A_OUT_GNU_H__ | 2 | #define __A_OUT_GNU_H__ |
| 3 | 3 | ||
| 4 | #ifdef CONFIG_ARCH_SUPPORTS_AOUT | ||
| 5 | |||
| 4 | #define __GNU_EXEC_MACROS__ | 6 | #define __GNU_EXEC_MACROS__ |
| 5 | 7 | ||
| 6 | #ifndef __STRUCT_EXEC_OVERRIDE__ | 8 | #ifndef __STRUCT_EXEC_OVERRIDE__ |
| @@ -9,6 +11,8 @@ | |||
| 9 | 11 | ||
| 10 | #endif /* __STRUCT_EXEC_OVERRIDE__ */ | 12 | #endif /* __STRUCT_EXEC_OVERRIDE__ */ |
| 11 | 13 | ||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | |||
| 12 | /* these go in the N_MACHTYPE field */ | 16 | /* these go in the N_MACHTYPE field */ |
| 13 | enum machine_type { | 17 | enum machine_type { |
| 14 | #if defined (M_OLDSUN2) | 18 | #if defined (M_OLDSUN2) |
| @@ -272,5 +276,11 @@ struct relocation_info | |||
| 272 | }; | 276 | }; |
| 273 | #endif /* no N_RELOCATION_INFO_DECLARED. */ | 277 | #endif /* no N_RELOCATION_INFO_DECLARED. */ |
| 274 | 278 | ||
| 275 | 279 | #endif /*__ASSEMBLY__ */ | |
| 280 | #else /* CONFIG_ARCH_SUPPORTS_AOUT */ | ||
| 281 | #ifndef __ASSEMBLY__ | ||
| 282 | struct exec { | ||
| 283 | }; | ||
| 284 | #endif | ||
| 285 | #endif /* CONFIG_ARCH_SUPPORTS_AOUT */ | ||
| 276 | #endif /* __A_OUT_GNU_H__ */ | 286 | #endif /* __A_OUT_GNU_H__ */ |
diff --git a/include/linux/atmel_pwm.h b/include/linux/atmel_pwm.h new file mode 100644 index 000000000000..ea04abb3db8e --- /dev/null +++ b/include/linux/atmel_pwm.h | |||
| @@ -0,0 +1,70 @@ | |||
| 1 | #ifndef __LINUX_ATMEL_PWM_H | ||
| 2 | #define __LINUX_ATMEL_PWM_H | ||
| 3 | |||
| 4 | /** | ||
| 5 | * struct pwm_channel - driver handle to a PWM channel | ||
| 6 | * @regs: base of this channel's registers | ||
| 7 | * @index: number of this channel (0..31) | ||
| 8 | * @mck: base clock rate, which can be prescaled and maybe subdivided | ||
| 9 | * | ||
| 10 | * Drivers initialize a pwm_channel structure using pwm_channel_alloc(). | ||
| 11 | * Then they configure its clock rate (derived from MCK), alignment, | ||
| 12 | * polarity, and duty cycle by writing directly to the channel registers, | ||
| 13 | * before enabling the channel by calling pwm_channel_enable(). | ||
| 14 | * | ||
| 15 | * After emitting a PWM signal for the desired length of time, drivers | ||
| 16 | * may then pwm_channel_disable() or pwm_channel_free(). Both of these | ||
| 17 | * disable the channel, but when it's freed the IRQ is deconfigured and | ||
| 18 | * the channel must later be re-allocated and reconfigured. | ||
| 19 | * | ||
| 20 | * Note that if the period or duty cycle need to be changed while the | ||
| 21 | * PWM channel is operating, drivers must use the PWM_CUPD double buffer | ||
| 22 | * mechanism, either polling until they change or getting implicitly | ||
| 23 | * notified through a once-per-period interrupt handler. | ||
| 24 | */ | ||
| 25 | struct pwm_channel { | ||
| 26 | void __iomem *regs; | ||
| 27 | unsigned index; | ||
| 28 | unsigned long mck; | ||
| 29 | }; | ||
| 30 | |||
| 31 | extern int pwm_channel_alloc(int index, struct pwm_channel *ch); | ||
| 32 | extern int pwm_channel_free(struct pwm_channel *ch); | ||
| 33 | |||
| 34 | extern int pwm_clk_alloc(unsigned prescale, unsigned div); | ||
| 35 | extern void pwm_clk_free(unsigned clk); | ||
| 36 | |||
| 37 | extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled); | ||
| 38 | |||
| 39 | #define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1) | ||
| 40 | #define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0) | ||
| 41 | |||
| 42 | /* periodic interrupts, mostly for CUPD changes to period or cycle */ | ||
| 43 | extern int pwm_channel_handler(struct pwm_channel *ch, | ||
| 44 | void (*handler)(struct pwm_channel *ch)); | ||
| 45 | |||
| 46 | /* per-channel registers (banked at pwm_channel->regs) */ | ||
| 47 | #define PWM_CMR 0x00 /* mode register */ | ||
| 48 | #define PWM_CPR_CPD (1 << 10) /* set: CUPD modifies period */ | ||
| 49 | #define PWM_CPR_CPOL (1 << 9) /* set: idle high */ | ||
| 50 | #define PWM_CPR_CALG (1 << 8) /* set: center align */ | ||
| 51 | #define PWM_CPR_CPRE (0xf << 0) /* mask: rate is mck/(2^pre) */ | ||
| 52 | #define PWM_CPR_CLKA (0xb << 0) /* rate CLKA */ | ||
| 53 | #define PWM_CPR_CLKB (0xc << 0) /* rate CLKB */ | ||
| 54 | #define PWM_CDTY 0x04 /* duty cycle (max of CPRD) */ | ||
| 55 | #define PWM_CPRD 0x08 /* period (count up from zero) */ | ||
| 56 | #define PWM_CCNT 0x0c /* counter (20 bits?) */ | ||
| 57 | #define PWM_CUPD 0x10 /* update CPRD (or CDTY) next period */ | ||
| 58 | |||
| 59 | static inline void | ||
| 60 | pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val) | ||
| 61 | { | ||
| 62 | __raw_writel(val, pwmc->regs + offset); | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset) | ||
| 66 | { | ||
| 67 | return __raw_readl(pwmc->regs + offset); | ||
| 68 | } | ||
| 69 | |||
| 70 | #endif /* __LINUX_ATMEL_PWM_H */ | ||
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h index 90392a9d7a9c..e1888cc5b8ae 100644 --- a/include/linux/blkdev.h +++ b/include/linux/blkdev.h | |||
| @@ -137,7 +137,9 @@ enum rq_flag_bits { | |||
| 137 | #define BLK_MAX_CDB 16 | 137 | #define BLK_MAX_CDB 16 |
| 138 | 138 | ||
| 139 | /* | 139 | /* |
| 140 | * try to put the fields that are referenced together in the same cacheline | 140 | * try to put the fields that are referenced together in the same cacheline. |
| 141 | * if you modify this structure, be sure to check block/blk-core.c:rq_init() | ||
| 142 | * as well! | ||
| 141 | */ | 143 | */ |
| 142 | struct request { | 144 | struct request { |
| 143 | struct list_head queuelist; | 145 | struct list_head queuelist; |
diff --git a/include/linux/byteorder/generic.h b/include/linux/byteorder/generic.h index 3dc715b02500..d3771551fdd9 100644 --- a/include/linux/byteorder/generic.h +++ b/include/linux/byteorder/generic.h | |||
| @@ -146,6 +146,36 @@ | |||
| 146 | #define htons(x) ___htons(x) | 146 | #define htons(x) ___htons(x) |
| 147 | #define ntohs(x) ___ntohs(x) | 147 | #define ntohs(x) ___ntohs(x) |
| 148 | 148 | ||
| 149 | static inline void le16_add_cpu(__le16 *var, u16 val) | ||
| 150 | { | ||
| 151 | *var = cpu_to_le16(le16_to_cpu(*var) + val); | ||
| 152 | } | ||
| 153 | |||
| 154 | static inline void le32_add_cpu(__le32 *var, u32 val) | ||
| 155 | { | ||
| 156 | *var = cpu_to_le32(le32_to_cpu(*var) + val); | ||
| 157 | } | ||
| 158 | |||
| 159 | static inline void le64_add_cpu(__le64 *var, u64 val) | ||
| 160 | { | ||
| 161 | *var = cpu_to_le64(le64_to_cpu(*var) + val); | ||
| 162 | } | ||
| 163 | |||
| 164 | static inline void be16_add_cpu(__be16 *var, u16 val) | ||
| 165 | { | ||
| 166 | *var = cpu_to_be16(be16_to_cpu(*var) + val); | ||
| 167 | } | ||
| 168 | |||
| 169 | static inline void be32_add_cpu(__be32 *var, u32 val) | ||
| 170 | { | ||
| 171 | *var = cpu_to_be32(be32_to_cpu(*var) + val); | ||
| 172 | } | ||
| 173 | |||
| 174 | static inline void be64_add_cpu(__be64 *var, u64 val) | ||
| 175 | { | ||
| 176 | *var = cpu_to_be64(be64_to_cpu(*var) + val); | ||
| 177 | } | ||
| 178 | |||
| 149 | #endif /* KERNEL */ | 179 | #endif /* KERNEL */ |
| 150 | 180 | ||
| 151 | #endif /* _LINUX_BYTEORDER_GENERIC_H */ | 181 | #endif /* _LINUX_BYTEORDER_GENERIC_H */ |
diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h index ecae585ec3da..f8c9a2752f06 100644 --- a/include/linux/cpuset.h +++ b/include/linux/cpuset.h | |||
| @@ -57,7 +57,9 @@ extern int cpuset_memory_pressure_enabled; | |||
| 57 | extern void __cpuset_memory_pressure_bump(void); | 57 | extern void __cpuset_memory_pressure_bump(void); |
| 58 | 58 | ||
| 59 | extern const struct file_operations proc_cpuset_operations; | 59 | extern const struct file_operations proc_cpuset_operations; |
| 60 | extern char *cpuset_task_status_allowed(struct task_struct *task, char *buffer); | 60 | struct seq_file; |
| 61 | extern void cpuset_task_status_allowed(struct seq_file *m, | ||
| 62 | struct task_struct *task); | ||
| 61 | 63 | ||
| 62 | extern void cpuset_lock(void); | 64 | extern void cpuset_lock(void); |
| 63 | extern void cpuset_unlock(void); | 65 | extern void cpuset_unlock(void); |
| @@ -126,10 +128,9 @@ static inline int cpuset_mems_allowed_intersects(const struct task_struct *tsk1, | |||
| 126 | 128 | ||
| 127 | static inline void cpuset_memory_pressure_bump(void) {} | 129 | static inline void cpuset_memory_pressure_bump(void) {} |
| 128 | 130 | ||
| 129 | static inline char *cpuset_task_status_allowed(struct task_struct *task, | 131 | static inline void cpuset_task_status_allowed(struct seq_file *m, |
| 130 | char *buffer) | 132 | struct task_struct *task) |
| 131 | { | 133 | { |
| 132 | return buffer; | ||
| 133 | } | 134 | } |
| 134 | 135 | ||
| 135 | static inline void cpuset_lock(void) {} | 136 | static inline void cpuset_lock(void) {} |
diff --git a/include/linux/dca.h b/include/linux/dca.h index 83eaecc6f8ab..af61cd1f37e9 100644 --- a/include/linux/dca.h +++ b/include/linux/dca.h | |||
| @@ -11,7 +11,7 @@ void dca_unregister_notify(struct notifier_block *nb); | |||
| 11 | 11 | ||
| 12 | struct dca_provider { | 12 | struct dca_provider { |
| 13 | struct dca_ops *ops; | 13 | struct dca_ops *ops; |
| 14 | struct class_device *cd; | 14 | struct device *cd; |
| 15 | int id; | 15 | int id; |
| 16 | }; | 16 | }; |
| 17 | 17 | ||
diff --git a/include/linux/dmar.h b/include/linux/dmar.h index ffb6439cb5e6..56c73b847551 100644 --- a/include/linux/dmar.h +++ b/include/linux/dmar.h | |||
| @@ -28,7 +28,7 @@ | |||
| 28 | #ifdef CONFIG_DMAR | 28 | #ifdef CONFIG_DMAR |
| 29 | struct intel_iommu; | 29 | struct intel_iommu; |
| 30 | 30 | ||
| 31 | extern char *dmar_get_fault_reason(u8 fault_reason); | 31 | extern const char *dmar_get_fault_reason(u8 fault_reason); |
| 32 | 32 | ||
| 33 | /* Can't use the common MSI interrupt functions | 33 | /* Can't use the common MSI interrupt functions |
| 34 | * since DMAR is not a pci device | 34 | * since DMAR is not a pci device |
diff --git a/include/linux/dmi.h b/include/linux/dmi.h index bbc9992ec374..325acdf5c462 100644 --- a/include/linux/dmi.h +++ b/include/linux/dmi.h | |||
| @@ -35,8 +35,11 @@ enum dmi_device_type { | |||
| 35 | DMI_DEV_TYPE_ETHERNET, | 35 | DMI_DEV_TYPE_ETHERNET, |
| 36 | DMI_DEV_TYPE_TOKENRING, | 36 | DMI_DEV_TYPE_TOKENRING, |
| 37 | DMI_DEV_TYPE_SOUND, | 37 | DMI_DEV_TYPE_SOUND, |
| 38 | DMI_DEV_TYPE_PATA, | ||
| 39 | DMI_DEV_TYPE_SATA, | ||
| 40 | DMI_DEV_TYPE_SAS, | ||
| 38 | DMI_DEV_TYPE_IPMI = -1, | 41 | DMI_DEV_TYPE_IPMI = -1, |
| 39 | DMI_DEV_TYPE_OEM_STRING = -2 | 42 | DMI_DEV_TYPE_OEM_STRING = -2, |
| 40 | }; | 43 | }; |
| 41 | 44 | ||
| 42 | struct dmi_header { | 45 | struct dmi_header { |
diff --git a/include/linux/elf-em.h b/include/linux/elf-em.h index 5834e843a946..18bea78fe47b 100644 --- a/include/linux/elf-em.h +++ b/include/linux/elf-em.h | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | #define EM_V850 87 /* NEC v850 */ | 31 | #define EM_V850 87 /* NEC v850 */ |
| 32 | #define EM_M32R 88 /* Renesas M32R */ | 32 | #define EM_M32R 88 /* Renesas M32R */ |
| 33 | #define EM_H8_300 46 /* Renesas H8/300,300H,H8S */ | 33 | #define EM_H8_300 46 /* Renesas H8/300,300H,H8S */ |
| 34 | #define EM_MN10300 89 /* Panasonic/MEI MN10300, AM33 */ | ||
| 34 | #define EM_BLACKFIN 106 /* ADI Blackfin Processor */ | 35 | #define EM_BLACKFIN 106 /* ADI Blackfin Processor */ |
| 35 | #define EM_FRV 0x5441 /* Fujitsu FR-V */ | 36 | #define EM_FRV 0x5441 /* Fujitsu FR-V */ |
| 36 | #define EM_AVR32 0x18ad /* Atmel AVR32 */ | 37 | #define EM_AVR32 0x18ad /* Atmel AVR32 */ |
| @@ -47,6 +48,8 @@ | |||
| 47 | #define EM_CYGNUS_M32R 0x9041 | 48 | #define EM_CYGNUS_M32R 0x9041 |
| 48 | /* This is the old interim value for S/390 architecture */ | 49 | /* This is the old interim value for S/390 architecture */ |
| 49 | #define EM_S390_OLD 0xA390 | 50 | #define EM_S390_OLD 0xA390 |
| 51 | /* Also Panasonic/MEI MN10300, AM33 */ | ||
| 52 | #define EM_CYGNUS_MN10300 0xbeef | ||
| 50 | 53 | ||
| 51 | 54 | ||
| 52 | #endif /* _LINUX_ELF_EM_H */ | 55 | #endif /* _LINUX_ELF_EM_H */ |
diff --git a/include/linux/fs.h b/include/linux/fs.h index 36b7abefacbe..18cfbf76ec5b 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h | |||
| @@ -1038,6 +1038,12 @@ struct super_block { | |||
| 1038 | * in /proc/mounts will be "type.subtype" | 1038 | * in /proc/mounts will be "type.subtype" |
| 1039 | */ | 1039 | */ |
| 1040 | char *s_subtype; | 1040 | char *s_subtype; |
| 1041 | |||
| 1042 | /* | ||
| 1043 | * Saved mount options for lazy filesystems using | ||
| 1044 | * generic_show_options() | ||
| 1045 | */ | ||
| 1046 | char *s_options; | ||
| 1041 | }; | 1047 | }; |
| 1042 | 1048 | ||
| 1043 | extern struct timespec current_fs_time(struct super_block *sb); | 1049 | extern struct timespec current_fs_time(struct super_block *sb); |
| @@ -1618,7 +1624,6 @@ extern int register_chrdev(unsigned int, const char *, | |||
| 1618 | const struct file_operations *); | 1624 | const struct file_operations *); |
| 1619 | extern void unregister_chrdev(unsigned int, const char *); | 1625 | extern void unregister_chrdev(unsigned int, const char *); |
| 1620 | extern void unregister_chrdev_region(dev_t, unsigned); | 1626 | extern void unregister_chrdev_region(dev_t, unsigned); |
| 1621 | extern int chrdev_open(struct inode *, struct file *); | ||
| 1622 | extern void chrdev_show(struct seq_file *,off_t); | 1627 | extern void chrdev_show(struct seq_file *,off_t); |
| 1623 | 1628 | ||
| 1624 | /* fs/block_dev.c */ | 1629 | /* fs/block_dev.c */ |
| @@ -1807,9 +1812,6 @@ extern ssize_t generic_file_buffered_write(struct kiocb *, const struct iovec *, | |||
| 1807 | unsigned long, loff_t, loff_t *, size_t, ssize_t); | 1812 | unsigned long, loff_t, loff_t *, size_t, ssize_t); |
| 1808 | extern ssize_t do_sync_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos); | 1813 | extern ssize_t do_sync_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos); |
| 1809 | extern ssize_t do_sync_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos); | 1814 | extern ssize_t do_sync_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos); |
| 1810 | extern void do_generic_mapping_read(struct address_space *mapping, | ||
| 1811 | struct file_ra_state *, struct file *, | ||
| 1812 | loff_t *, read_descriptor_t *, read_actor_t); | ||
| 1813 | extern int generic_segment_checks(const struct iovec *iov, | 1815 | extern int generic_segment_checks(const struct iovec *iov, |
| 1814 | unsigned long *nr_segs, size_t *count, int access_flags); | 1816 | unsigned long *nr_segs, size_t *count, int access_flags); |
| 1815 | 1817 | ||
| @@ -1847,18 +1849,6 @@ static inline int xip_truncate_page(struct address_space *mapping, loff_t from) | |||
| 1847 | } | 1849 | } |
| 1848 | #endif | 1850 | #endif |
| 1849 | 1851 | ||
| 1850 | static inline void do_generic_file_read(struct file * filp, loff_t *ppos, | ||
| 1851 | read_descriptor_t * desc, | ||
| 1852 | read_actor_t actor) | ||
| 1853 | { | ||
| 1854 | do_generic_mapping_read(filp->f_mapping, | ||
| 1855 | &filp->f_ra, | ||
| 1856 | filp, | ||
| 1857 | ppos, | ||
| 1858 | desc, | ||
| 1859 | actor); | ||
| 1860 | } | ||
| 1861 | |||
| 1862 | #ifdef CONFIG_BLOCK | 1852 | #ifdef CONFIG_BLOCK |
| 1863 | ssize_t __blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, | 1853 | ssize_t __blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, |
| 1864 | struct block_device *bdev, const struct iovec *iov, loff_t offset, | 1854 | struct block_device *bdev, const struct iovec *iov, loff_t offset, |
| @@ -1985,6 +1975,9 @@ extern int __must_check inode_setattr(struct inode *, struct iattr *); | |||
| 1985 | 1975 | ||
| 1986 | extern void file_update_time(struct file *file); | 1976 | extern void file_update_time(struct file *file); |
| 1987 | 1977 | ||
| 1978 | extern int generic_show_options(struct seq_file *m, struct vfsmount *mnt); | ||
| 1979 | extern void save_mount_options(struct super_block *sb, char *options); | ||
| 1980 | |||
| 1988 | static inline ino_t parent_ino(struct dentry *dentry) | 1981 | static inline ino_t parent_ino(struct dentry *dentry) |
| 1989 | { | 1982 | { |
| 1990 | ino_t res; | 1983 | ino_t res; |
| @@ -2056,7 +2049,7 @@ static int __fops ## _open(struct inode *inode, struct file *file) \ | |||
| 2056 | static struct file_operations __fops = { \ | 2049 | static struct file_operations __fops = { \ |
| 2057 | .owner = THIS_MODULE, \ | 2050 | .owner = THIS_MODULE, \ |
| 2058 | .open = __fops ## _open, \ | 2051 | .open = __fops ## _open, \ |
| 2059 | .release = simple_attr_close, \ | 2052 | .release = simple_attr_release, \ |
| 2060 | .read = simple_attr_read, \ | 2053 | .read = simple_attr_read, \ |
| 2061 | .write = simple_attr_write, \ | 2054 | .write = simple_attr_write, \ |
| 2062 | }; | 2055 | }; |
| @@ -2068,9 +2061,9 @@ __simple_attr_check_format(const char *fmt, ...) | |||
| 2068 | } | 2061 | } |
| 2069 | 2062 | ||
| 2070 | int simple_attr_open(struct inode *inode, struct file *file, | 2063 | int simple_attr_open(struct inode *inode, struct file *file, |
| 2071 | u64 (*get)(void *), void (*set)(void *, u64), | 2064 | int (*get)(void *, u64 *), int (*set)(void *, u64), |
| 2072 | const char *fmt); | 2065 | const char *fmt); |
| 2073 | int simple_attr_close(struct inode *inode, struct file *file); | 2066 | int simple_attr_release(struct inode *inode, struct file *file); |
| 2074 | ssize_t simple_attr_read(struct file *file, char __user *buf, | 2067 | ssize_t simple_attr_read(struct file *file, char __user *buf, |
| 2075 | size_t len, loff_t *ppos); | 2068 | size_t len, loff_t *ppos); |
| 2076 | ssize_t simple_attr_write(struct file *file, const char __user *buf, | 2069 | ssize_t simple_attr_write(struct file *file, const char __user *buf, |
diff --git a/include/linux/genhd.h b/include/linux/genhd.h index 1dbea0ac5693..09a3b18918c7 100644 --- a/include/linux/genhd.h +++ b/include/linux/genhd.h | |||
| @@ -91,16 +91,31 @@ struct partition { | |||
| 91 | __le32 nr_sects; /* nr of sectors in partition */ | 91 | __le32 nr_sects; /* nr of sectors in partition */ |
| 92 | } __attribute__((packed)); | 92 | } __attribute__((packed)); |
| 93 | 93 | ||
| 94 | struct disk_stats { | ||
| 95 | unsigned long sectors[2]; /* READs and WRITEs */ | ||
| 96 | unsigned long ios[2]; | ||
| 97 | unsigned long merges[2]; | ||
| 98 | unsigned long ticks[2]; | ||
| 99 | unsigned long io_ticks; | ||
| 100 | unsigned long time_in_queue; | ||
| 101 | }; | ||
| 102 | |||
| 94 | struct hd_struct { | 103 | struct hd_struct { |
| 95 | sector_t start_sect; | 104 | sector_t start_sect; |
| 96 | sector_t nr_sects; | 105 | sector_t nr_sects; |
| 97 | struct device dev; | 106 | struct device dev; |
| 98 | struct kobject *holder_dir; | 107 | struct kobject *holder_dir; |
| 99 | unsigned ios[2], sectors[2]; /* READs and WRITEs */ | ||
| 100 | int policy, partno; | 108 | int policy, partno; |
| 101 | #ifdef CONFIG_FAIL_MAKE_REQUEST | 109 | #ifdef CONFIG_FAIL_MAKE_REQUEST |
| 102 | int make_it_fail; | 110 | int make_it_fail; |
| 103 | #endif | 111 | #endif |
| 112 | unsigned long stamp; | ||
| 113 | int in_flight; | ||
| 114 | #ifdef CONFIG_SMP | ||
| 115 | struct disk_stats *dkstats; | ||
| 116 | #else | ||
| 117 | struct disk_stats dkstats; | ||
| 118 | #endif | ||
| 104 | }; | 119 | }; |
| 105 | 120 | ||
| 106 | #define GENHD_FL_REMOVABLE 1 | 121 | #define GENHD_FL_REMOVABLE 1 |
| @@ -111,15 +126,7 @@ struct hd_struct { | |||
| 111 | #define GENHD_FL_SUPPRESS_PARTITION_INFO 32 | 126 | #define GENHD_FL_SUPPRESS_PARTITION_INFO 32 |
| 112 | #define GENHD_FL_FAIL 64 | 127 | #define GENHD_FL_FAIL 64 |
| 113 | 128 | ||
| 114 | struct disk_stats { | 129 | |
| 115 | unsigned long sectors[2]; /* READs and WRITEs */ | ||
| 116 | unsigned long ios[2]; | ||
| 117 | unsigned long merges[2]; | ||
| 118 | unsigned long ticks[2]; | ||
| 119 | unsigned long io_ticks; | ||
| 120 | unsigned long time_in_queue; | ||
| 121 | }; | ||
| 122 | |||
| 123 | struct gendisk { | 130 | struct gendisk { |
| 124 | int major; /* major number of driver */ | 131 | int major; /* major number of driver */ |
| 125 | int first_minor; | 132 | int first_minor; |
| @@ -158,6 +165,20 @@ struct gendisk { | |||
| 158 | * The __ variants should only be called in critical sections. The full | 165 | * The __ variants should only be called in critical sections. The full |
| 159 | * variants disable/enable preemption. | 166 | * variants disable/enable preemption. |
| 160 | */ | 167 | */ |
| 168 | static inline struct hd_struct *get_part(struct gendisk *gendiskp, | ||
| 169 | sector_t sector) | ||
| 170 | { | ||
| 171 | struct hd_struct *part; | ||
| 172 | int i; | ||
| 173 | for (i = 0; i < gendiskp->minors - 1; i++) { | ||
| 174 | part = gendiskp->part[i]; | ||
| 175 | if (part && part->start_sect <= sector | ||
| 176 | && sector < part->start_sect + part->nr_sects) | ||
| 177 | return part; | ||
| 178 | } | ||
| 179 | return NULL; | ||
| 180 | } | ||
| 181 | |||
| 161 | #ifdef CONFIG_SMP | 182 | #ifdef CONFIG_SMP |
| 162 | #define __disk_stat_add(gendiskp, field, addnd) \ | 183 | #define __disk_stat_add(gendiskp, field, addnd) \ |
| 163 | (per_cpu_ptr(gendiskp->dkstats, smp_processor_id())->field += addnd) | 184 | (per_cpu_ptr(gendiskp->dkstats, smp_processor_id())->field += addnd) |
| @@ -177,15 +198,62 @@ static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) { | |||
| 177 | memset(per_cpu_ptr(gendiskp->dkstats, i), value, | 198 | memset(per_cpu_ptr(gendiskp->dkstats, i), value, |
| 178 | sizeof (struct disk_stats)); | 199 | sizeof (struct disk_stats)); |
| 179 | } | 200 | } |
| 201 | |||
| 202 | #define __part_stat_add(part, field, addnd) \ | ||
| 203 | (per_cpu_ptr(part->dkstats, smp_processor_id())->field += addnd) | ||
| 204 | |||
| 205 | #define __all_stat_add(gendiskp, field, addnd, sector) \ | ||
| 206 | ({ \ | ||
| 207 | struct hd_struct *part = get_part(gendiskp, sector); \ | ||
| 208 | if (part) \ | ||
| 209 | __part_stat_add(part, field, addnd); \ | ||
| 210 | __disk_stat_add(gendiskp, field, addnd); \ | ||
| 211 | }) | ||
| 212 | |||
| 213 | #define part_stat_read(part, field) \ | ||
| 214 | ({ \ | ||
| 215 | typeof(part->dkstats->field) res = 0; \ | ||
| 216 | int i; \ | ||
| 217 | for_each_possible_cpu(i) \ | ||
| 218 | res += per_cpu_ptr(part->dkstats, i)->field; \ | ||
| 219 | res; \ | ||
| 220 | }) | ||
| 221 | |||
| 222 | static inline void part_stat_set_all(struct hd_struct *part, int value) { | ||
| 223 | int i; | ||
| 224 | for_each_possible_cpu(i) | ||
| 225 | memset(per_cpu_ptr(part->dkstats, i), value, | ||
| 226 | sizeof(struct disk_stats)); | ||
| 227 | } | ||
| 180 | 228 | ||
| 181 | #else | 229 | #else |
| 182 | #define __disk_stat_add(gendiskp, field, addnd) \ | 230 | #define __disk_stat_add(gendiskp, field, addnd) \ |
| 183 | (gendiskp->dkstats.field += addnd) | 231 | (gendiskp->dkstats.field += addnd) |
| 184 | #define disk_stat_read(gendiskp, field) (gendiskp->dkstats.field) | 232 | #define disk_stat_read(gendiskp, field) (gendiskp->dkstats.field) |
| 185 | 233 | ||
| 186 | static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) { | 234 | static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) |
| 235 | { | ||
| 187 | memset(&gendiskp->dkstats, value, sizeof (struct disk_stats)); | 236 | memset(&gendiskp->dkstats, value, sizeof (struct disk_stats)); |
| 188 | } | 237 | } |
| 238 | |||
| 239 | #define __part_stat_add(part, field, addnd) \ | ||
| 240 | (part->dkstats.field += addnd) | ||
| 241 | |||
| 242 | #define __all_stat_add(gendiskp, field, addnd, sector) \ | ||
| 243 | ({ \ | ||
| 244 | struct hd_struct *part = get_part(gendiskp, sector); \ | ||
| 245 | if (part) \ | ||
| 246 | part->dkstats.field += addnd; \ | ||
| 247 | __disk_stat_add(gendiskp, field, addnd); \ | ||
| 248 | }) | ||
| 249 | |||
| 250 | #define part_stat_read(part, field) (part->dkstats.field) | ||
| 251 | |||
| 252 | static inline void part_stat_set_all(struct hd_struct *part, int value) | ||
| 253 | { | ||
| 254 | memset(&part->dkstats, value, sizeof(struct disk_stats)); | ||
| 255 | } | ||
| 256 | |||
| 189 | #endif | 257 | #endif |
| 190 | 258 | ||
| 191 | #define disk_stat_add(gendiskp, field, addnd) \ | 259 | #define disk_stat_add(gendiskp, field, addnd) \ |
| @@ -206,6 +274,45 @@ static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) { | |||
| 206 | #define disk_stat_sub(gendiskp, field, subnd) \ | 274 | #define disk_stat_sub(gendiskp, field, subnd) \ |
| 207 | disk_stat_add(gendiskp, field, -subnd) | 275 | disk_stat_add(gendiskp, field, -subnd) |
| 208 | 276 | ||
| 277 | #define part_stat_add(gendiskp, field, addnd) \ | ||
| 278 | do { \ | ||
| 279 | preempt_disable(); \ | ||
| 280 | __part_stat_add(gendiskp, field, addnd);\ | ||
| 281 | preempt_enable(); \ | ||
| 282 | } while (0) | ||
| 283 | |||
| 284 | #define __part_stat_dec(gendiskp, field) __part_stat_add(gendiskp, field, -1) | ||
| 285 | #define part_stat_dec(gendiskp, field) part_stat_add(gendiskp, field, -1) | ||
| 286 | |||
| 287 | #define __part_stat_inc(gendiskp, field) __part_stat_add(gendiskp, field, 1) | ||
| 288 | #define part_stat_inc(gendiskp, field) part_stat_add(gendiskp, field, 1) | ||
| 289 | |||
| 290 | #define __part_stat_sub(gendiskp, field, subnd) \ | ||
| 291 | __part_stat_add(gendiskp, field, -subnd) | ||
| 292 | #define part_stat_sub(gendiskp, field, subnd) \ | ||
| 293 | part_stat_add(gendiskp, field, -subnd) | ||
| 294 | |||
| 295 | #define all_stat_add(gendiskp, field, addnd, sector) \ | ||
| 296 | do { \ | ||
| 297 | preempt_disable(); \ | ||
| 298 | __all_stat_add(gendiskp, field, addnd, sector); \ | ||
| 299 | preempt_enable(); \ | ||
| 300 | } while (0) | ||
| 301 | |||
| 302 | #define __all_stat_dec(gendiskp, field, sector) \ | ||
| 303 | __all_stat_add(gendiskp, field, -1, sector) | ||
| 304 | #define all_stat_dec(gendiskp, field, sector) \ | ||
| 305 | all_stat_add(gendiskp, field, -1, sector) | ||
| 306 | |||
| 307 | #define __all_stat_inc(gendiskp, field, sector) \ | ||
| 308 | __all_stat_add(gendiskp, field, 1, sector) | ||
| 309 | #define all_stat_inc(gendiskp, field, sector) \ | ||
| 310 | all_stat_add(gendiskp, field, 1, sector) | ||
| 311 | |||
| 312 | #define __all_stat_sub(gendiskp, field, subnd, sector) \ | ||
| 313 | __all_stat_add(gendiskp, field, -subnd, sector) | ||
| 314 | #define all_stat_sub(gendiskp, field, subnd, sector) \ | ||
| 315 | all_stat_add(gendiskp, field, -subnd, sector) | ||
| 209 | 316 | ||
| 210 | /* Inlines to alloc and free disk stats in struct gendisk */ | 317 | /* Inlines to alloc and free disk stats in struct gendisk */ |
| 211 | #ifdef CONFIG_SMP | 318 | #ifdef CONFIG_SMP |
| @@ -221,6 +328,20 @@ static inline void free_disk_stats(struct gendisk *disk) | |||
| 221 | { | 328 | { |
| 222 | free_percpu(disk->dkstats); | 329 | free_percpu(disk->dkstats); |
| 223 | } | 330 | } |
| 331 | |||
| 332 | static inline int init_part_stats(struct hd_struct *part) | ||
| 333 | { | ||
| 334 | part->dkstats = alloc_percpu(struct disk_stats); | ||
| 335 | if (!part->dkstats) | ||
| 336 | return 0; | ||
| 337 | return 1; | ||
| 338 | } | ||
| 339 | |||
| 340 | static inline void free_part_stats(struct hd_struct *part) | ||
| 341 | { | ||
| 342 | free_percpu(part->dkstats); | ||
| 343 | } | ||
| 344 | |||
| 224 | #else /* CONFIG_SMP */ | 345 | #else /* CONFIG_SMP */ |
| 225 | static inline int init_disk_stats(struct gendisk *disk) | 346 | static inline int init_disk_stats(struct gendisk *disk) |
| 226 | { | 347 | { |
| @@ -230,10 +351,20 @@ static inline int init_disk_stats(struct gendisk *disk) | |||
| 230 | static inline void free_disk_stats(struct gendisk *disk) | 351 | static inline void free_disk_stats(struct gendisk *disk) |
| 231 | { | 352 | { |
| 232 | } | 353 | } |
| 354 | |||
| 355 | static inline int init_part_stats(struct hd_struct *part) | ||
| 356 | { | ||
| 357 | return 1; | ||
| 358 | } | ||
| 359 | |||
| 360 | static inline void free_part_stats(struct hd_struct *part) | ||
| 361 | { | ||
| 362 | } | ||
| 233 | #endif /* CONFIG_SMP */ | 363 | #endif /* CONFIG_SMP */ |
| 234 | 364 | ||
| 235 | /* drivers/block/ll_rw_blk.c */ | 365 | /* drivers/block/ll_rw_blk.c */ |
| 236 | extern void disk_round_stats(struct gendisk *disk); | 366 | extern void disk_round_stats(struct gendisk *disk); |
| 367 | extern void part_round_stats(struct hd_struct *part); | ||
| 237 | 368 | ||
| 238 | /* drivers/block/genhd.c */ | 369 | /* drivers/block/genhd.c */ |
| 239 | extern int get_blkdev_list(char *, int); | 370 | extern int get_blkdev_list(char *, int); |
diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h index 203591e23210..600fc3bcf63e 100644 --- a/include/linux/hrtimer.h +++ b/include/linux/hrtimer.h | |||
| @@ -78,7 +78,7 @@ enum hrtimer_cb_mode { | |||
| 78 | * as otherwise the timer could be removed before the softirq code finishes the | 78 | * as otherwise the timer could be removed before the softirq code finishes the |
| 79 | * the handling of the timer. | 79 | * the handling of the timer. |
| 80 | * | 80 | * |
| 81 | * The HRTIMER_STATE_ENQUEUE bit is always or'ed to the current state to | 81 | * The HRTIMER_STATE_ENQUEUED bit is always or'ed to the current state to |
| 82 | * preserve the HRTIMER_STATE_CALLBACK bit in the above scenario. | 82 | * preserve the HRTIMER_STATE_CALLBACK bit in the above scenario. |
| 83 | * | 83 | * |
| 84 | * All state transitions are protected by cpu_base->lock. | 84 | * All state transitions are protected by cpu_base->lock. |
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h index 30d606afcafe..7ca198b379af 100644 --- a/include/linux/hugetlb.h +++ b/include/linux/hugetlb.h | |||
| @@ -17,6 +17,7 @@ static inline int is_vm_hugetlb_page(struct vm_area_struct *vma) | |||
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | int hugetlb_sysctl_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *); | 19 | int hugetlb_sysctl_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *); |
| 20 | int hugetlb_overcommit_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *); | ||
| 20 | int hugetlb_treat_movable_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *); | 21 | int hugetlb_treat_movable_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *); |
| 21 | int copy_hugetlb_page_range(struct mm_struct *, struct mm_struct *, struct vm_area_struct *); | 22 | int copy_hugetlb_page_range(struct mm_struct *, struct mm_struct *, struct vm_area_struct *); |
| 22 | int follow_hugetlb_page(struct mm_struct *, struct vm_area_struct *, struct page **, struct vm_area_struct **, unsigned long *, int *, int, int); | 23 | int follow_hugetlb_page(struct mm_struct *, struct vm_area_struct *, struct page **, struct vm_area_struct **, unsigned long *, int *, int, int); |
diff --git a/include/linux/ipc.h b/include/linux/ipc.h index 408696ea5189..b8826107b518 100644 --- a/include/linux/ipc.h +++ b/include/linux/ipc.h | |||
| @@ -100,58 +100,6 @@ struct kern_ipc_perm | |||
| 100 | void *security; | 100 | void *security; |
| 101 | }; | 101 | }; |
| 102 | 102 | ||
| 103 | struct ipc_ids; | ||
| 104 | struct ipc_namespace { | ||
| 105 | struct kref kref; | ||
| 106 | struct ipc_ids *ids[3]; | ||
| 107 | |||
| 108 | int sem_ctls[4]; | ||
| 109 | int used_sems; | ||
| 110 | |||
| 111 | int msg_ctlmax; | ||
| 112 | int msg_ctlmnb; | ||
| 113 | int msg_ctlmni; | ||
| 114 | atomic_t msg_bytes; | ||
| 115 | atomic_t msg_hdrs; | ||
| 116 | |||
| 117 | size_t shm_ctlmax; | ||
| 118 | size_t shm_ctlall; | ||
| 119 | int shm_ctlmni; | ||
| 120 | int shm_tot; | ||
| 121 | }; | ||
| 122 | |||
| 123 | extern struct ipc_namespace init_ipc_ns; | ||
| 124 | |||
| 125 | #ifdef CONFIG_SYSVIPC | ||
| 126 | #define INIT_IPC_NS(ns) .ns = &init_ipc_ns, | ||
| 127 | extern void free_ipc_ns(struct kref *kref); | ||
| 128 | extern struct ipc_namespace *copy_ipcs(unsigned long flags, | ||
| 129 | struct ipc_namespace *ns); | ||
| 130 | #else | ||
| 131 | #define INIT_IPC_NS(ns) | ||
| 132 | static inline struct ipc_namespace *copy_ipcs(unsigned long flags, | ||
| 133 | struct ipc_namespace *ns) | ||
| 134 | { | ||
| 135 | return ns; | ||
| 136 | } | ||
| 137 | #endif | ||
| 138 | |||
| 139 | static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns) | ||
| 140 | { | ||
| 141 | #ifdef CONFIG_SYSVIPC | ||
| 142 | if (ns) | ||
| 143 | kref_get(&ns->kref); | ||
| 144 | #endif | ||
| 145 | return ns; | ||
| 146 | } | ||
| 147 | |||
| 148 | static inline void put_ipc_ns(struct ipc_namespace *ns) | ||
| 149 | { | ||
| 150 | #ifdef CONFIG_SYSVIPC | ||
| 151 | kref_put(&ns->kref, free_ipc_ns); | ||
| 152 | #endif | ||
| 153 | } | ||
| 154 | |||
| 155 | #endif /* __KERNEL__ */ | 103 | #endif /* __KERNEL__ */ |
| 156 | 104 | ||
| 157 | #endif /* _LINUX_IPC_H */ | 105 | #endif /* _LINUX_IPC_H */ |
diff --git a/include/linux/ipc_namespace.h b/include/linux/ipc_namespace.h new file mode 100644 index 000000000000..e4451d1da753 --- /dev/null +++ b/include/linux/ipc_namespace.h | |||
| @@ -0,0 +1,81 @@ | |||
| 1 | #ifndef __IPC_NAMESPACE_H__ | ||
| 2 | #define __IPC_NAMESPACE_H__ | ||
| 3 | |||
| 4 | #include <linux/err.h> | ||
| 5 | #include <linux/idr.h> | ||
| 6 | #include <linux/rwsem.h> | ||
| 7 | |||
| 8 | struct ipc_ids { | ||
| 9 | int in_use; | ||
| 10 | unsigned short seq; | ||
| 11 | unsigned short seq_max; | ||
| 12 | struct rw_semaphore rw_mutex; | ||
| 13 | struct idr ipcs_idr; | ||
| 14 | }; | ||
| 15 | |||
| 16 | struct ipc_namespace { | ||
| 17 | struct kref kref; | ||
| 18 | struct ipc_ids ids[3]; | ||
| 19 | |||
| 20 | int sem_ctls[4]; | ||
| 21 | int used_sems; | ||
| 22 | |||
| 23 | int msg_ctlmax; | ||
| 24 | int msg_ctlmnb; | ||
| 25 | int msg_ctlmni; | ||
| 26 | atomic_t msg_bytes; | ||
| 27 | atomic_t msg_hdrs; | ||
| 28 | |||
| 29 | size_t shm_ctlmax; | ||
| 30 | size_t shm_ctlall; | ||
| 31 | int shm_ctlmni; | ||
| 32 | int shm_tot; | ||
| 33 | }; | ||
| 34 | |||
| 35 | extern struct ipc_namespace init_ipc_ns; | ||
| 36 | |||
| 37 | #ifdef CONFIG_SYSVIPC | ||
| 38 | #define INIT_IPC_NS(ns) .ns = &init_ipc_ns, | ||
| 39 | #else | ||
| 40 | #define INIT_IPC_NS(ns) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #if defined(CONFIG_SYSVIPC) && defined(CONFIG_IPC_NS) | ||
| 44 | extern void free_ipc_ns(struct kref *kref); | ||
| 45 | extern struct ipc_namespace *copy_ipcs(unsigned long flags, | ||
| 46 | struct ipc_namespace *ns); | ||
| 47 | extern void free_ipcs(struct ipc_namespace *ns, struct ipc_ids *ids, | ||
| 48 | void (*free)(struct ipc_namespace *, | ||
| 49 | struct kern_ipc_perm *)); | ||
| 50 | |||
| 51 | static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns) | ||
| 52 | { | ||
| 53 | if (ns) | ||
| 54 | kref_get(&ns->kref); | ||
| 55 | return ns; | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline void put_ipc_ns(struct ipc_namespace *ns) | ||
| 59 | { | ||
| 60 | kref_put(&ns->kref, free_ipc_ns); | ||
| 61 | } | ||
| 62 | #else | ||
| 63 | static inline struct ipc_namespace *copy_ipcs(unsigned long flags, | ||
| 64 | struct ipc_namespace *ns) | ||
| 65 | { | ||
| 66 | if (flags & CLONE_NEWIPC) | ||
| 67 | return ERR_PTR(-EINVAL); | ||
| 68 | |||
| 69 | return ns; | ||
| 70 | } | ||
| 71 | |||
| 72 | static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns) | ||
| 73 | { | ||
| 74 | return ns; | ||
| 75 | } | ||
| 76 | |||
| 77 | static inline void put_ipc_ns(struct ipc_namespace *ns) | ||
| 78 | { | ||
| 79 | } | ||
| 80 | #endif | ||
| 81 | #endif | ||
diff --git a/include/linux/irq.h b/include/linux/irq.h index 4669be080617..bfd9efb5cb49 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | #include <asm/irq_regs.h> | 25 | #include <asm/irq_regs.h> |
| 26 | 26 | ||
| 27 | struct irq_desc; | 27 | struct irq_desc; |
| 28 | typedef void fastcall (*irq_flow_handler_t)(unsigned int irq, | 28 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
| 29 | struct irq_desc *desc); | 29 | struct irq_desc *desc); |
| 30 | 30 | ||
| 31 | 31 | ||
| @@ -276,19 +276,19 @@ extern int handle_IRQ_event(unsigned int irq, struct irqaction *action); | |||
| 276 | * Built-in IRQ handlers for various IRQ types, | 276 | * Built-in IRQ handlers for various IRQ types, |
| 277 | * callable via desc->chip->handle_irq() | 277 | * callable via desc->chip->handle_irq() |
| 278 | */ | 278 | */ |
| 279 | extern void fastcall handle_level_irq(unsigned int irq, struct irq_desc *desc); | 279 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
| 280 | extern void fastcall handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | 280 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); |
| 281 | extern void fastcall handle_edge_irq(unsigned int irq, struct irq_desc *desc); | 281 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); |
| 282 | extern void fastcall handle_simple_irq(unsigned int irq, struct irq_desc *desc); | 282 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); |
| 283 | extern void fastcall handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | 283 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); |
| 284 | extern void fastcall handle_bad_irq(unsigned int irq, struct irq_desc *desc); | 284 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); |
| 285 | 285 | ||
| 286 | /* | 286 | /* |
| 287 | * Monolithic do_IRQ implementation. | 287 | * Monolithic do_IRQ implementation. |
| 288 | * (is an explicit fastcall, because i386 4KSTACKS calls it from assembly) | 288 | * (is an explicit fastcall, because i386 4KSTACKS calls it from assembly) |
| 289 | */ | 289 | */ |
| 290 | #ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ | 290 | #ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ |
| 291 | extern fastcall unsigned int __do_IRQ(unsigned int irq); | 291 | extern unsigned int __do_IRQ(unsigned int irq); |
| 292 | #endif | 292 | #endif |
| 293 | 293 | ||
| 294 | /* | 294 | /* |
| @@ -367,6 +367,9 @@ set_irq_chained_handler(unsigned int irq, | |||
| 367 | __set_irq_handler(irq, handle, 1, NULL); | 367 | __set_irq_handler(irq, handle, 1, NULL); |
| 368 | } | 368 | } |
| 369 | 369 | ||
| 370 | extern void set_irq_noprobe(unsigned int irq); | ||
| 371 | extern void set_irq_probe(unsigned int irq); | ||
| 372 | |||
| 370 | /* Handle dynamic irq creation and destruction */ | 373 | /* Handle dynamic irq creation and destruction */ |
| 371 | extern int create_irq(void); | 374 | extern int create_irq(void); |
| 372 | extern void destroy_irq(unsigned int irq); | 375 | extern void destroy_irq(unsigned int irq); |
diff --git a/include/linux/jiffies.h b/include/linux/jiffies.h index 7ba9e47bf061..e0b5b684d83f 100644 --- a/include/linux/jiffies.h +++ b/include/linux/jiffies.h | |||
| @@ -42,7 +42,7 @@ | |||
| 42 | /* LATCH is used in the interval timer and ftape setup. */ | 42 | /* LATCH is used in the interval timer and ftape setup. */ |
| 43 | #define LATCH ((CLOCK_TICK_RATE + HZ/2) / HZ) /* For divider */ | 43 | #define LATCH ((CLOCK_TICK_RATE + HZ/2) / HZ) /* For divider */ |
| 44 | 44 | ||
| 45 | /* Suppose we want to devide two numbers NOM and DEN: NOM/DEN, the we can | 45 | /* Suppose we want to devide two numbers NOM and DEN: NOM/DEN, then we can |
| 46 | * improve accuracy by shifting LSH bits, hence calculating: | 46 | * improve accuracy by shifting LSH bits, hence calculating: |
| 47 | * (NOM << LSH) / DEN | 47 | * (NOM << LSH) / DEN |
| 48 | * This however means trouble for large NOM, because (NOM << LSH) may no | 48 | * This however means trouble for large NOM, because (NOM << LSH) may no |
| @@ -160,7 +160,7 @@ extern unsigned long preset_lpj; | |||
| 160 | * We want to do realistic conversions of time so we need to use the same | 160 | * We want to do realistic conversions of time so we need to use the same |
| 161 | * values the update wall clock code uses as the jiffies size. This value | 161 | * values the update wall clock code uses as the jiffies size. This value |
| 162 | * is: TICK_NSEC (which is defined in timex.h). This | 162 | * is: TICK_NSEC (which is defined in timex.h). This |
| 163 | * is a constant and is in nanoseconds. We will used scaled math | 163 | * is a constant and is in nanoseconds. We will use scaled math |
| 164 | * with a set of scales defined here as SEC_JIFFIE_SC, USEC_JIFFIE_SC and | 164 | * with a set of scales defined here as SEC_JIFFIE_SC, USEC_JIFFIE_SC and |
| 165 | * NSEC_JIFFIE_SC. Note that these defines contain nothing but | 165 | * NSEC_JIFFIE_SC. Note that these defines contain nothing but |
| 166 | * constants and so are computed at compile time. SHIFT_HZ (computed in | 166 | * constants and so are computed at compile time. SHIFT_HZ (computed in |
| @@ -204,7 +204,7 @@ extern unsigned long preset_lpj; | |||
| 204 | * operator if the result is a long long AND at least one of the | 204 | * operator if the result is a long long AND at least one of the |
| 205 | * operands is cast to long long (usually just prior to the "*" so as | 205 | * operands is cast to long long (usually just prior to the "*" so as |
| 206 | * not to confuse it into thinking it really has a 64-bit operand, | 206 | * not to confuse it into thinking it really has a 64-bit operand, |
| 207 | * which, buy the way, it can do, but it take more code and at least 2 | 207 | * which, buy the way, it can do, but it takes more code and at least 2 |
| 208 | * mpys). | 208 | * mpys). |
| 209 | 209 | ||
| 210 | * We also need to be aware that one second in nanoseconds is only a | 210 | * We also need to be aware that one second in nanoseconds is only a |
diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 9e01f376840a..2df44e773270 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h | |||
| @@ -133,7 +133,7 @@ NORET_TYPE void panic(const char * fmt, ...) | |||
| 133 | extern void oops_enter(void); | 133 | extern void oops_enter(void); |
| 134 | extern void oops_exit(void); | 134 | extern void oops_exit(void); |
| 135 | extern int oops_may_print(void); | 135 | extern int oops_may_print(void); |
| 136 | fastcall NORET_TYPE void do_exit(long error_code) | 136 | NORET_TYPE void do_exit(long error_code) |
| 137 | ATTRIB_NORET; | 137 | ATTRIB_NORET; |
| 138 | NORET_TYPE void complete_and_exit(struct completion *, long) | 138 | NORET_TYPE void complete_and_exit(struct completion *, long) |
| 139 | ATTRIB_NORET; | 139 | ATTRIB_NORET; |
| @@ -141,6 +141,10 @@ extern unsigned long simple_strtoul(const char *,char **,unsigned int); | |||
| 141 | extern long simple_strtol(const char *,char **,unsigned int); | 141 | extern long simple_strtol(const char *,char **,unsigned int); |
| 142 | extern unsigned long long simple_strtoull(const char *,char **,unsigned int); | 142 | extern unsigned long long simple_strtoull(const char *,char **,unsigned int); |
| 143 | extern long long simple_strtoll(const char *,char **,unsigned int); | 143 | extern long long simple_strtoll(const char *,char **,unsigned int); |
| 144 | extern int strict_strtoul(const char *, unsigned int, unsigned long *); | ||
| 145 | extern int strict_strtol(const char *, unsigned int, long *); | ||
| 146 | extern int strict_strtoull(const char *, unsigned int, unsigned long long *); | ||
| 147 | extern int strict_strtoll(const char *, unsigned int, long long *); | ||
| 144 | extern int sprintf(char * buf, const char * fmt, ...) | 148 | extern int sprintf(char * buf, const char * fmt, ...) |
| 145 | __attribute__ ((format (printf, 2, 3))); | 149 | __attribute__ ((format (printf, 2, 3))); |
| 146 | extern int vsprintf(char *buf, const char *, va_list) | 150 | extern int vsprintf(char *buf, const char *, va_list) |
| @@ -172,8 +176,6 @@ extern int kernel_text_address(unsigned long addr); | |||
| 172 | struct pid; | 176 | struct pid; |
| 173 | extern struct pid *session_of_pgrp(struct pid *pgrp); | 177 | extern struct pid *session_of_pgrp(struct pid *pgrp); |
| 174 | 178 | ||
| 175 | extern void dump_thread(struct pt_regs *regs, struct user *dump); | ||
| 176 | |||
| 177 | #ifdef CONFIG_PRINTK | 179 | #ifdef CONFIG_PRINTK |
| 178 | asmlinkage int vprintk(const char *fmt, va_list args) | 180 | asmlinkage int vprintk(const char *fmt, va_list args) |
| 179 | __attribute__ ((format (printf, 1, 0))); | 181 | __attribute__ ((format (printf, 1, 0))); |
| @@ -182,6 +184,13 @@ asmlinkage int printk(const char * fmt, ...) | |||
| 182 | extern int log_buf_get_len(void); | 184 | extern int log_buf_get_len(void); |
| 183 | extern int log_buf_read(int idx); | 185 | extern int log_buf_read(int idx); |
| 184 | extern int log_buf_copy(char *dest, int idx, int len); | 186 | extern int log_buf_copy(char *dest, int idx, int len); |
| 187 | |||
| 188 | extern int printk_ratelimit_jiffies; | ||
| 189 | extern int printk_ratelimit_burst; | ||
| 190 | extern int printk_ratelimit(void); | ||
| 191 | extern int __printk_ratelimit(int ratelimit_jiffies, int ratelimit_burst); | ||
| 192 | extern bool printk_timed_ratelimit(unsigned long *caller_jiffies, | ||
| 193 | unsigned int interval_msec); | ||
| 185 | #else | 194 | #else |
| 186 | static inline int vprintk(const char *s, va_list args) | 195 | static inline int vprintk(const char *s, va_list args) |
| 187 | __attribute__ ((format (printf, 1, 0))); | 196 | __attribute__ ((format (printf, 1, 0))); |
| @@ -192,6 +201,12 @@ static inline int __cold printk(const char *s, ...) { return 0; } | |||
| 192 | static inline int log_buf_get_len(void) { return 0; } | 201 | static inline int log_buf_get_len(void) { return 0; } |
| 193 | static inline int log_buf_read(int idx) { return 0; } | 202 | static inline int log_buf_read(int idx) { return 0; } |
| 194 | static inline int log_buf_copy(char *dest, int idx, int len) { return 0; } | 203 | static inline int log_buf_copy(char *dest, int idx, int len) { return 0; } |
| 204 | static inline int printk_ratelimit(void) { return 0; } | ||
| 205 | static inline int __printk_ratelimit(int ratelimit_jiffies, \ | ||
| 206 | int ratelimit_burst) { return 0; } | ||
| 207 | static inline bool printk_timed_ratelimit(unsigned long *caller_jiffies, \ | ||
| 208 | unsigned int interval_msec) \ | ||
| 209 | { return false; } | ||
| 195 | #endif | 210 | #endif |
| 196 | 211 | ||
| 197 | extern void __attribute__((format(printf, 1, 2))) | 212 | extern void __attribute__((format(printf, 1, 2))) |
| @@ -199,11 +214,6 @@ extern void __attribute__((format(printf, 1, 2))) | |||
| 199 | 214 | ||
| 200 | unsigned long int_sqrt(unsigned long); | 215 | unsigned long int_sqrt(unsigned long); |
| 201 | 216 | ||
| 202 | extern int printk_ratelimit(void); | ||
| 203 | extern int __printk_ratelimit(int ratelimit_jiffies, int ratelimit_burst); | ||
| 204 | extern bool printk_timed_ratelimit(unsigned long *caller_jiffies, | ||
| 205 | unsigned int interval_msec); | ||
| 206 | |||
| 207 | static inline void console_silent(void) | 217 | static inline void console_silent(void) |
| 208 | { | 218 | { |
| 209 | console_loglevel = 0; | 219 | console_loglevel = 0; |
| @@ -224,6 +234,7 @@ extern int panic_on_unrecovered_nmi; | |||
| 224 | extern int tainted; | 234 | extern int tainted; |
| 225 | extern const char *print_tainted(void); | 235 | extern const char *print_tainted(void); |
| 226 | extern void add_taint(unsigned); | 236 | extern void add_taint(unsigned); |
| 237 | extern int root_mountflags; | ||
| 227 | 238 | ||
| 228 | /* Values used for system_state */ | 239 | /* Values used for system_state */ |
| 229 | extern enum system_states { | 240 | extern enum system_states { |
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index 222815d91c40..6cdf813cd478 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h | |||
| @@ -133,6 +133,11 @@ enum { | |||
| 133 | MLX4_STAT_RATE_OFFSET = 5 | 133 | MLX4_STAT_RATE_OFFSET = 5 |
| 134 | }; | 134 | }; |
| 135 | 135 | ||
| 136 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) | ||
| 137 | { | ||
| 138 | return (major << 32) | (minor << 16) | subminor; | ||
| 139 | } | ||
| 140 | |||
| 136 | struct mlx4_caps { | 141 | struct mlx4_caps { |
| 137 | u64 fw_ver; | 142 | u64 fw_ver; |
| 138 | int num_ports; | 143 | int num_ports; |
| @@ -189,10 +194,8 @@ struct mlx4_buf_list { | |||
| 189 | }; | 194 | }; |
| 190 | 195 | ||
| 191 | struct mlx4_buf { | 196 | struct mlx4_buf { |
| 192 | union { | 197 | struct mlx4_buf_list direct; |
| 193 | struct mlx4_buf_list direct; | 198 | struct mlx4_buf_list *page_list; |
| 194 | struct mlx4_buf_list *page_list; | ||
| 195 | } u; | ||
| 196 | int nbufs; | 199 | int nbufs; |
| 197 | int npages; | 200 | int npages; |
| 198 | int page_shift; | 201 | int page_shift; |
| @@ -308,6 +311,14 @@ struct mlx4_init_port_param { | |||
| 308 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, | 311 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
| 309 | struct mlx4_buf *buf); | 312 | struct mlx4_buf *buf); |
| 310 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); | 313 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); |
| 314 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) | ||
| 315 | { | ||
| 316 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) | ||
| 317 | return buf->direct.buf + offset; | ||
| 318 | else | ||
| 319 | return buf->page_list[offset >> PAGE_SHIFT].buf + | ||
| 320 | (offset & (PAGE_SIZE - 1)); | ||
| 321 | } | ||
| 311 | 322 | ||
| 312 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | 323 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); |
| 313 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | 324 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); |
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h index 3968b943259a..09a2230923f2 100644 --- a/include/linux/mlx4/qp.h +++ b/include/linux/mlx4/qp.h | |||
| @@ -154,7 +154,11 @@ struct mlx4_qp_context { | |||
| 154 | u32 reserved5[10]; | 154 | u32 reserved5[10]; |
| 155 | }; | 155 | }; |
| 156 | 156 | ||
| 157 | /* Which firmware version adds support for NEC (NoErrorCompletion) bit */ | ||
| 158 | #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) | ||
| 159 | |||
| 157 | enum { | 160 | enum { |
| 161 | MLX4_WQE_CTRL_NEC = 1 << 29, | ||
| 158 | MLX4_WQE_CTRL_FENCE = 1 << 6, | 162 | MLX4_WQE_CTRL_FENCE = 1 << 6, |
| 159 | MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, | 163 | MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, |
| 160 | MLX4_WQE_CTRL_SOLICITED = 1 << 1, | 164 | MLX4_WQE_CTRL_SOLICITED = 1 << 1, |
diff --git a/include/linux/mm.h b/include/linux/mm.h index 89d7c691b93a..e8abb3814209 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h | |||
| @@ -894,6 +894,18 @@ static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long a | |||
| 894 | #define pte_lockptr(mm, pmd) ({(void)(pmd); &(mm)->page_table_lock;}) | 894 | #define pte_lockptr(mm, pmd) ({(void)(pmd); &(mm)->page_table_lock;}) |
| 895 | #endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */ | 895 | #endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */ |
| 896 | 896 | ||
| 897 | static inline void pgtable_page_ctor(struct page *page) | ||
| 898 | { | ||
| 899 | pte_lock_init(page); | ||
| 900 | inc_zone_page_state(page, NR_PAGETABLE); | ||
| 901 | } | ||
| 902 | |||
| 903 | static inline void pgtable_page_dtor(struct page *page) | ||
| 904 | { | ||
| 905 | pte_lock_deinit(page); | ||
| 906 | dec_zone_page_state(page, NR_PAGETABLE); | ||
| 907 | } | ||
| 908 | |||
| 897 | #define pte_offset_map_lock(mm, pmd, address, ptlp) \ | 909 | #define pte_offset_map_lock(mm, pmd, address, ptlp) \ |
| 898 | ({ \ | 910 | ({ \ |
| 899 | spinlock_t *__ptl = pte_lockptr(mm, pmd); \ | 911 | spinlock_t *__ptl = pte_lockptr(mm, pmd); \ |
| @@ -1136,7 +1148,7 @@ struct page *follow_page(struct vm_area_struct *, unsigned long address, | |||
| 1136 | #define FOLL_GET 0x04 /* do get_page on page */ | 1148 | #define FOLL_GET 0x04 /* do get_page on page */ |
| 1137 | #define FOLL_ANON 0x08 /* give ZERO_PAGE if no pgtable */ | 1149 | #define FOLL_ANON 0x08 /* give ZERO_PAGE if no pgtable */ |
| 1138 | 1150 | ||
| 1139 | typedef int (*pte_fn_t)(pte_t *pte, struct page *pmd_page, unsigned long addr, | 1151 | typedef int (*pte_fn_t)(pte_t *pte, pgtable_t token, unsigned long addr, |
| 1140 | void *data); | 1152 | void *data); |
| 1141 | extern int apply_to_page_range(struct mm_struct *mm, unsigned long address, | 1153 | extern int apply_to_page_range(struct mm_struct *mm, unsigned long address, |
| 1142 | unsigned long size, pte_fn_t fn, void *data); | 1154 | unsigned long size, pte_fn_t fn, void *data); |
diff --git a/include/linux/module.h b/include/linux/module.h index ac481e2094fd..ac28e8761e84 100644 --- a/include/linux/module.h +++ b/include/linux/module.h | |||
| @@ -449,7 +449,7 @@ static inline void __module_get(struct module *module) | |||
| 449 | /* For kallsyms to ask for address resolution. namebuf should be at | 449 | /* For kallsyms to ask for address resolution. namebuf should be at |
| 450 | * least KSYM_NAME_LEN long: a pointer to namebuf is returned if | 450 | * least KSYM_NAME_LEN long: a pointer to namebuf is returned if |
| 451 | * found, otherwise NULL. */ | 451 | * found, otherwise NULL. */ |
| 452 | char *module_address_lookup(unsigned long addr, | 452 | const char *module_address_lookup(unsigned long addr, |
| 453 | unsigned long *symbolsize, | 453 | unsigned long *symbolsize, |
| 454 | unsigned long *offset, | 454 | unsigned long *offset, |
| 455 | char **modname, | 455 | char **modname, |
| @@ -519,7 +519,7 @@ static inline void module_put(struct module *module) | |||
| 519 | #define module_name(mod) "kernel" | 519 | #define module_name(mod) "kernel" |
| 520 | 520 | ||
| 521 | /* For kallsyms to ask for address resolution. NULL means not found. */ | 521 | /* For kallsyms to ask for address resolution. NULL means not found. */ |
| 522 | static inline char *module_address_lookup(unsigned long addr, | 522 | static inline const char *module_address_lookup(unsigned long addr, |
| 523 | unsigned long *symbolsize, | 523 | unsigned long *symbolsize, |
| 524 | unsigned long *offset, | 524 | unsigned long *offset, |
| 525 | char **modname, | 525 | char **modname, |
diff --git a/include/linux/mutex.h b/include/linux/mutex.h index 05c590352dd7..bc6da10ceee0 100644 --- a/include/linux/mutex.h +++ b/include/linux/mutex.h | |||
| @@ -112,7 +112,7 @@ extern void __mutex_init(struct mutex *lock, const char *name, | |||
| 112 | * | 112 | * |
| 113 | * Returns 1 if the mutex is locked, 0 if unlocked. | 113 | * Returns 1 if the mutex is locked, 0 if unlocked. |
| 114 | */ | 114 | */ |
| 115 | static inline int fastcall mutex_is_locked(struct mutex *lock) | 115 | static inline int mutex_is_locked(struct mutex *lock) |
| 116 | { | 116 | { |
| 117 | return atomic_read(&lock->count) != 1; | 117 | return atomic_read(&lock->count) != 1; |
| 118 | } | 118 | } |
| @@ -132,9 +132,9 @@ extern int __must_check mutex_lock_killable_nested(struct mutex *lock, | |||
| 132 | #define mutex_lock_interruptible(lock) mutex_lock_interruptible_nested(lock, 0) | 132 | #define mutex_lock_interruptible(lock) mutex_lock_interruptible_nested(lock, 0) |
| 133 | #define mutex_lock_killable(lock) mutex_lock_killable_nested(lock, 0) | 133 | #define mutex_lock_killable(lock) mutex_lock_killable_nested(lock, 0) |
| 134 | #else | 134 | #else |
| 135 | extern void fastcall mutex_lock(struct mutex *lock); | 135 | extern void mutex_lock(struct mutex *lock); |
| 136 | extern int __must_check fastcall mutex_lock_interruptible(struct mutex *lock); | 136 | extern int __must_check mutex_lock_interruptible(struct mutex *lock); |
| 137 | extern int __must_check fastcall mutex_lock_killable(struct mutex *lock); | 137 | extern int __must_check mutex_lock_killable(struct mutex *lock); |
| 138 | 138 | ||
| 139 | # define mutex_lock_nested(lock, subclass) mutex_lock(lock) | 139 | # define mutex_lock_nested(lock, subclass) mutex_lock(lock) |
| 140 | # define mutex_lock_interruptible_nested(lock, subclass) mutex_lock_interruptible(lock) | 140 | # define mutex_lock_interruptible_nested(lock, subclass) mutex_lock_interruptible(lock) |
| @@ -145,7 +145,7 @@ extern int __must_check fastcall mutex_lock_killable(struct mutex *lock); | |||
| 145 | * NOTE: mutex_trylock() follows the spin_trylock() convention, | 145 | * NOTE: mutex_trylock() follows the spin_trylock() convention, |
| 146 | * not the down_trylock() convention! | 146 | * not the down_trylock() convention! |
| 147 | */ | 147 | */ |
| 148 | extern int fastcall mutex_trylock(struct mutex *lock); | 148 | extern int mutex_trylock(struct mutex *lock); |
| 149 | extern void fastcall mutex_unlock(struct mutex *lock); | 149 | extern void mutex_unlock(struct mutex *lock); |
| 150 | 150 | ||
| 151 | #endif | 151 | #endif |
diff --git a/include/linux/nbd.h b/include/linux/nbd.h index cc2b47240a8f..986572081e19 100644 --- a/include/linux/nbd.h +++ b/include/linux/nbd.h | |||
| @@ -35,7 +35,6 @@ enum { | |||
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | #define nbd_cmd(req) ((req)->cmd[0]) | 37 | #define nbd_cmd(req) ((req)->cmd[0]) |
| 38 | #define MAX_NBD 128 | ||
| 39 | 38 | ||
| 40 | /* userspace doesn't need the nbd_device structure */ | 39 | /* userspace doesn't need the nbd_device structure */ |
| 41 | #ifdef __KERNEL__ | 40 | #ifdef __KERNEL__ |
diff --git a/include/linux/pfkeyv2.h b/include/linux/pfkeyv2.h index 6db69ff5d83e..700725ddcaae 100644 --- a/include/linux/pfkeyv2.h +++ b/include/linux/pfkeyv2.h | |||
| @@ -298,6 +298,7 @@ struct sadb_x_sec_ctx { | |||
| 298 | #define SADB_X_EALG_BLOWFISHCBC 7 | 298 | #define SADB_X_EALG_BLOWFISHCBC 7 |
| 299 | #define SADB_EALG_NULL 11 | 299 | #define SADB_EALG_NULL 11 |
| 300 | #define SADB_X_EALG_AESCBC 12 | 300 | #define SADB_X_EALG_AESCBC 12 |
| 301 | #define SADB_X_EALG_AESCTR 13 | ||
| 301 | #define SADB_X_EALG_AES_CCM_ICV8 14 | 302 | #define SADB_X_EALG_AES_CCM_ICV8 14 |
| 302 | #define SADB_X_EALG_AES_CCM_ICV12 15 | 303 | #define SADB_X_EALG_AES_CCM_ICV12 15 |
| 303 | #define SADB_X_EALG_AES_CCM_ICV16 16 | 304 | #define SADB_X_EALG_AES_CCM_ICV16 16 |
diff --git a/include/linux/pid.h b/include/linux/pid.h index e29a900a8499..f84d532b5d23 100644 --- a/include/linux/pid.h +++ b/include/linux/pid.h | |||
| @@ -118,18 +118,17 @@ extern struct pid *find_pid(int nr); | |||
| 118 | */ | 118 | */ |
| 119 | extern struct pid *find_get_pid(int nr); | 119 | extern struct pid *find_get_pid(int nr); |
| 120 | extern struct pid *find_ge_pid(int nr, struct pid_namespace *); | 120 | extern struct pid *find_ge_pid(int nr, struct pid_namespace *); |
| 121 | int next_pidmap(struct pid_namespace *pid_ns, int last); | ||
| 121 | 122 | ||
| 122 | extern struct pid *alloc_pid(struct pid_namespace *ns); | 123 | extern struct pid *alloc_pid(struct pid_namespace *ns); |
| 123 | extern void FASTCALL(free_pid(struct pid *pid)); | 124 | extern void FASTCALL(free_pid(struct pid *pid)); |
| 124 | extern void zap_pid_ns_processes(struct pid_namespace *pid_ns); | ||
| 125 | 125 | ||
| 126 | /* | 126 | /* |
| 127 | * the helpers to get the pid's id seen from different namespaces | 127 | * the helpers to get the pid's id seen from different namespaces |
| 128 | * | 128 | * |
| 129 | * pid_nr() : global id, i.e. the id seen from the init namespace; | 129 | * pid_nr() : global id, i.e. the id seen from the init namespace; |
| 130 | * pid_vnr() : virtual id, i.e. the id seen from the namespace this pid | 130 | * pid_vnr() : virtual id, i.e. the id seen from the pid namespace of |
| 131 | * belongs to. this only makes sence when called in the | 131 | * current. |
| 132 | * context of the task that belongs to the same namespace; | ||
| 133 | * pid_nr_ns() : id seen from the ns specified. | 132 | * pid_nr_ns() : id seen from the ns specified. |
| 134 | * | 133 | * |
| 135 | * see also task_xid_nr() etc in include/linux/sched.h | 134 | * see also task_xid_nr() etc in include/linux/sched.h |
| @@ -144,14 +143,7 @@ static inline pid_t pid_nr(struct pid *pid) | |||
| 144 | } | 143 | } |
| 145 | 144 | ||
| 146 | pid_t pid_nr_ns(struct pid *pid, struct pid_namespace *ns); | 145 | pid_t pid_nr_ns(struct pid *pid, struct pid_namespace *ns); |
| 147 | 146 | pid_t pid_vnr(struct pid *pid); | |
| 148 | static inline pid_t pid_vnr(struct pid *pid) | ||
| 149 | { | ||
| 150 | pid_t nr = 0; | ||
| 151 | if (pid) | ||
| 152 | nr = pid->numbers[pid->level].nr; | ||
| 153 | return nr; | ||
| 154 | } | ||
| 155 | 147 | ||
| 156 | #define do_each_pid_task(pid, type, task) \ | 148 | #define do_each_pid_task(pid, type, task) \ |
| 157 | do { \ | 149 | do { \ |
| @@ -160,7 +152,13 @@ static inline pid_t pid_vnr(struct pid *pid) | |||
| 160 | hlist_for_each_entry_rcu((task), pos___, \ | 152 | hlist_for_each_entry_rcu((task), pos___, \ |
| 161 | &pid->tasks[type], pids[type].node) { | 153 | &pid->tasks[type], pids[type].node) { |
| 162 | 154 | ||
| 155 | /* | ||
| 156 | * Both old and new leaders may be attached to | ||
| 157 | * the same pid in the middle of de_thread(). | ||
| 158 | */ | ||
| 163 | #define while_each_pid_task(pid, type, task) \ | 159 | #define while_each_pid_task(pid, type, task) \ |
| 160 | if (type == PIDTYPE_PID) \ | ||
| 161 | break; \ | ||
| 164 | } \ | 162 | } \ |
| 165 | } while (0) | 163 | } while (0) |
| 166 | 164 | ||
diff --git a/include/linux/pid_namespace.h b/include/linux/pid_namespace.h index 1689e28483e4..fcd61fa2c833 100644 --- a/include/linux/pid_namespace.h +++ b/include/linux/pid_namespace.h | |||
| @@ -39,6 +39,7 @@ static inline struct pid_namespace *get_pid_ns(struct pid_namespace *ns) | |||
| 39 | 39 | ||
| 40 | extern struct pid_namespace *copy_pid_ns(unsigned long flags, struct pid_namespace *ns); | 40 | extern struct pid_namespace *copy_pid_ns(unsigned long flags, struct pid_namespace *ns); |
| 41 | extern void free_pid_ns(struct kref *kref); | 41 | extern void free_pid_ns(struct kref *kref); |
| 42 | extern void zap_pid_ns_processes(struct pid_namespace *pid_ns); | ||
| 42 | 43 | ||
| 43 | static inline void put_pid_ns(struct pid_namespace *ns) | 44 | static inline void put_pid_ns(struct pid_namespace *ns) |
| 44 | { | 45 | { |
| @@ -66,6 +67,11 @@ static inline void put_pid_ns(struct pid_namespace *ns) | |||
| 66 | { | 67 | { |
| 67 | } | 68 | } |
| 68 | 69 | ||
| 70 | |||
| 71 | static inline void zap_pid_ns_processes(struct pid_namespace *ns) | ||
| 72 | { | ||
| 73 | BUG(); | ||
| 74 | } | ||
| 69 | #endif /* CONFIG_PID_NS */ | 75 | #endif /* CONFIG_PID_NS */ |
| 70 | 76 | ||
| 71 | static inline struct pid_namespace *task_active_pid_ns(struct task_struct *tsk) | 77 | static inline struct pid_namespace *task_active_pid_ns(struct task_struct *tsk) |
diff --git a/include/linux/preempt.h b/include/linux/preempt.h index 484988ed301e..23f0c54175cd 100644 --- a/include/linux/preempt.h +++ b/include/linux/preempt.h | |||
| @@ -11,8 +11,8 @@ | |||
| 11 | #include <linux/list.h> | 11 | #include <linux/list.h> |
| 12 | 12 | ||
| 13 | #ifdef CONFIG_DEBUG_PREEMPT | 13 | #ifdef CONFIG_DEBUG_PREEMPT |
| 14 | extern void fastcall add_preempt_count(int val); | 14 | extern void add_preempt_count(int val); |
| 15 | extern void fastcall sub_preempt_count(int val); | 15 | extern void sub_preempt_count(int val); |
| 16 | #else | 16 | #else |
| 17 | # define add_preempt_count(val) do { preempt_count() += (val); } while (0) | 17 | # define add_preempt_count(val) do { preempt_count() += (val); } while (0) |
| 18 | # define sub_preempt_count(val) do { preempt_count() -= (val); } while (0) | 18 | # define sub_preempt_count(val) do { preempt_count() -= (val); } while (0) |
diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h index e43551516831..d6a4f69bdc92 100644 --- a/include/linux/proc_fs.h +++ b/include/linux/proc_fs.h | |||
| @@ -118,13 +118,17 @@ struct dentry *proc_pid_lookup(struct inode *dir, struct dentry * dentry, struct | |||
| 118 | int proc_pid_readdir(struct file * filp, void * dirent, filldir_t filldir); | 118 | int proc_pid_readdir(struct file * filp, void * dirent, filldir_t filldir); |
| 119 | unsigned long task_vsize(struct mm_struct *); | 119 | unsigned long task_vsize(struct mm_struct *); |
| 120 | int task_statm(struct mm_struct *, int *, int *, int *, int *); | 120 | int task_statm(struct mm_struct *, int *, int *, int *, int *); |
| 121 | char *task_mem(struct mm_struct *, char *); | 121 | void task_mem(struct seq_file *, struct mm_struct *); |
| 122 | void clear_refs_smap(struct mm_struct *mm); | ||
| 122 | 123 | ||
| 123 | struct proc_dir_entry *de_get(struct proc_dir_entry *de); | 124 | struct proc_dir_entry *de_get(struct proc_dir_entry *de); |
| 124 | void de_put(struct proc_dir_entry *de); | 125 | void de_put(struct proc_dir_entry *de); |
| 125 | 126 | ||
| 126 | extern struct proc_dir_entry *create_proc_entry(const char *name, mode_t mode, | 127 | extern struct proc_dir_entry *create_proc_entry(const char *name, mode_t mode, |
| 127 | struct proc_dir_entry *parent); | 128 | struct proc_dir_entry *parent); |
| 129 | struct proc_dir_entry *proc_create(const char *name, mode_t mode, | ||
| 130 | struct proc_dir_entry *parent, | ||
| 131 | const struct file_operations *proc_fops); | ||
| 128 | extern void remove_proc_entry(const char *name, struct proc_dir_entry *parent); | 132 | extern void remove_proc_entry(const char *name, struct proc_dir_entry *parent); |
| 129 | 133 | ||
| 130 | extern struct vfsmount *proc_mnt; | 134 | extern struct vfsmount *proc_mnt; |
| @@ -219,7 +223,12 @@ static inline void proc_flush_task(struct task_struct *task) | |||
| 219 | 223 | ||
| 220 | static inline struct proc_dir_entry *create_proc_entry(const char *name, | 224 | static inline struct proc_dir_entry *create_proc_entry(const char *name, |
| 221 | mode_t mode, struct proc_dir_entry *parent) { return NULL; } | 225 | mode_t mode, struct proc_dir_entry *parent) { return NULL; } |
| 222 | 226 | static inline struct proc_dir_entry *proc_create(const char *name, | |
| 227 | mode_t mode, struct proc_dir_entry *parent, | ||
| 228 | const struct file_operations *proc_fops) | ||
| 229 | { | ||
| 230 | return NULL; | ||
| 231 | } | ||
| 223 | #define remove_proc_entry(name, parent) do {} while (0) | 232 | #define remove_proc_entry(name, parent) do {} while (0) |
| 224 | 233 | ||
| 225 | static inline struct proc_dir_entry *proc_symlink(const char *name, | 234 | static inline struct proc_dir_entry *proc_symlink(const char *name, |
| @@ -262,6 +271,9 @@ extern void kclist_add(struct kcore_list *, void *, size_t); | |||
| 262 | union proc_op { | 271 | union proc_op { |
| 263 | int (*proc_get_link)(struct inode *, struct dentry **, struct vfsmount **); | 272 | int (*proc_get_link)(struct inode *, struct dentry **, struct vfsmount **); |
| 264 | int (*proc_read)(struct task_struct *task, char *page); | 273 | int (*proc_read)(struct task_struct *task, char *page); |
| 274 | int (*proc_show)(struct seq_file *m, | ||
| 275 | struct pid_namespace *ns, struct pid *pid, | ||
| 276 | struct task_struct *task); | ||
| 265 | }; | 277 | }; |
| 266 | 278 | ||
| 267 | struct proc_inode { | 279 | struct proc_inode { |
diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h index 6ab80714a916..ebe0c17039cf 100644 --- a/include/linux/ptrace.h +++ b/include/linux/ptrace.h | |||
| @@ -67,7 +67,6 @@ | |||
| 67 | #define PT_TRACE_EXEC 0x00000080 | 67 | #define PT_TRACE_EXEC 0x00000080 |
| 68 | #define PT_TRACE_VFORK_DONE 0x00000100 | 68 | #define PT_TRACE_VFORK_DONE 0x00000100 |
| 69 | #define PT_TRACE_EXIT 0x00000200 | 69 | #define PT_TRACE_EXIT 0x00000200 |
| 70 | #define PT_ATTACHED 0x00000400 /* parent != real_parent */ | ||
| 71 | 70 | ||
| 72 | #define PT_TRACE_MASK 0x000003f4 | 71 | #define PT_TRACE_MASK 0x000003f4 |
| 73 | 72 | ||
diff --git a/include/linux/rcupreempt.h b/include/linux/rcupreempt.h index ece8eb3e4151..60c2a033b19e 100644 --- a/include/linux/rcupreempt.h +++ b/include/linux/rcupreempt.h | |||
| @@ -46,8 +46,8 @@ | |||
| 46 | #define rcu_bh_qsctr_inc(cpu) | 46 | #define rcu_bh_qsctr_inc(cpu) |
| 47 | #define call_rcu_bh(head, rcu) call_rcu(head, rcu) | 47 | #define call_rcu_bh(head, rcu) call_rcu(head, rcu) |
| 48 | 48 | ||
| 49 | extern void __rcu_read_lock(void); | 49 | extern void __rcu_read_lock(void) __acquires(RCU); |
| 50 | extern void __rcu_read_unlock(void); | 50 | extern void __rcu_read_unlock(void) __releases(RCU); |
| 51 | extern int rcu_pending(int cpu); | 51 | extern int rcu_pending(int cpu); |
| 52 | extern int rcu_needs_cpu(int cpu); | 52 | extern int rcu_needs_cpu(int cpu); |
| 53 | 53 | ||
diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h index 422eab4958a6..8e7eff2cd0ab 100644 --- a/include/linux/reiserfs_fs.h +++ b/include/linux/reiserfs_fs.h | |||
| @@ -287,7 +287,7 @@ static inline struct reiserfs_sb_info *REISERFS_SB(const struct super_block *sb) | |||
| 287 | 287 | ||
| 288 | /* Don't trust REISERFS_SB(sb)->s_bmap_nr, it's a u16 | 288 | /* Don't trust REISERFS_SB(sb)->s_bmap_nr, it's a u16 |
| 289 | * which overflows on large file systems. */ | 289 | * which overflows on large file systems. */ |
| 290 | static inline u32 reiserfs_bmap_count(struct super_block *sb) | 290 | static inline __u32 reiserfs_bmap_count(struct super_block *sb) |
| 291 | { | 291 | { |
| 292 | return (SB_BLOCK_COUNT(sb) - 1) / (sb->s_blocksize * 8) + 1; | 292 | return (SB_BLOCK_COUNT(sb) - 1) / (sb->s_blocksize * 8) + 1; |
| 293 | } | 293 | } |
diff --git a/include/linux/sched.h b/include/linux/sched.h index 8a4812c1c038..00e144117326 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h | |||
| @@ -460,7 +460,7 @@ struct signal_struct { | |||
| 460 | 460 | ||
| 461 | /* ITIMER_REAL timer for the process */ | 461 | /* ITIMER_REAL timer for the process */ |
| 462 | struct hrtimer real_timer; | 462 | struct hrtimer real_timer; |
| 463 | struct task_struct *tsk; | 463 | struct pid *leader_pid; |
| 464 | ktime_t it_real_incr; | 464 | ktime_t it_real_incr; |
| 465 | 465 | ||
| 466 | /* ITIMER_PROF and ITIMER_VIRTUAL timers for the process */ | 466 | /* ITIMER_PROF and ITIMER_VIRTUAL timers for the process */ |
| @@ -1332,9 +1332,8 @@ struct pid_namespace; | |||
| 1332 | * from various namespaces | 1332 | * from various namespaces |
| 1333 | * | 1333 | * |
| 1334 | * task_xid_nr() : global id, i.e. the id seen from the init namespace; | 1334 | * task_xid_nr() : global id, i.e. the id seen from the init namespace; |
| 1335 | * task_xid_vnr() : virtual id, i.e. the id seen from the namespace the task | 1335 | * task_xid_vnr() : virtual id, i.e. the id seen from the pid namespace of |
| 1336 | * belongs to. this only makes sence when called in the | 1336 | * current. |
| 1337 | * context of the task that belongs to the same namespace; | ||
| 1338 | * task_xid_nr_ns() : id seen from the ns specified; | 1337 | * task_xid_nr_ns() : id seen from the ns specified; |
| 1339 | * | 1338 | * |
| 1340 | * set_task_vxid() : assigns a virtual id to a task; | 1339 | * set_task_vxid() : assigns a virtual id to a task; |
| @@ -1632,7 +1631,7 @@ extern struct task_struct *find_task_by_vpid(pid_t nr); | |||
| 1632 | extern struct task_struct *find_task_by_pid_ns(pid_t nr, | 1631 | extern struct task_struct *find_task_by_pid_ns(pid_t nr, |
| 1633 | struct pid_namespace *ns); | 1632 | struct pid_namespace *ns); |
| 1634 | 1633 | ||
| 1635 | extern void __set_special_pids(pid_t session, pid_t pgrp); | 1634 | extern void __set_special_pids(struct pid *pid); |
| 1636 | 1635 | ||
| 1637 | /* per-UID process charging. */ | 1636 | /* per-UID process charging. */ |
| 1638 | extern struct user_struct * alloc_uid(struct user_namespace *, uid_t); | 1637 | extern struct user_struct * alloc_uid(struct user_namespace *, uid_t); |
| @@ -1687,11 +1686,9 @@ extern void block_all_signals(int (*notifier)(void *priv), void *priv, | |||
| 1687 | extern void unblock_all_signals(void); | 1686 | extern void unblock_all_signals(void); |
| 1688 | extern void release_task(struct task_struct * p); | 1687 | extern void release_task(struct task_struct * p); |
| 1689 | extern int send_sig_info(int, struct siginfo *, struct task_struct *); | 1688 | extern int send_sig_info(int, struct siginfo *, struct task_struct *); |
| 1690 | extern int send_group_sig_info(int, struct siginfo *, struct task_struct *); | ||
| 1691 | extern int force_sigsegv(int, struct task_struct *); | 1689 | extern int force_sigsegv(int, struct task_struct *); |
| 1692 | extern int force_sig_info(int, struct siginfo *, struct task_struct *); | 1690 | extern int force_sig_info(int, struct siginfo *, struct task_struct *); |
| 1693 | extern int __kill_pgrp_info(int sig, struct siginfo *info, struct pid *pgrp); | 1691 | extern int __kill_pgrp_info(int sig, struct siginfo *info, struct pid *pgrp); |
| 1694 | extern int kill_pgrp_info(int sig, struct siginfo *info, struct pid *pgrp); | ||
| 1695 | extern int kill_pid_info(int sig, struct siginfo *info, struct pid *pid); | 1692 | extern int kill_pid_info(int sig, struct siginfo *info, struct pid *pid); |
| 1696 | extern int kill_pid_info_as_uid(int, struct siginfo *, struct pid *, uid_t, uid_t, u32); | 1693 | extern int kill_pid_info_as_uid(int, struct siginfo *, struct pid *, uid_t, uid_t, u32); |
| 1697 | extern int kill_pgrp(struct pid *pid, int sig, int priv); | 1694 | extern int kill_pgrp(struct pid *pid, int sig, int priv); |
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 9963f81fea9a..1a0b6cf83ff1 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h | |||
| @@ -150,6 +150,10 @@ | |||
| 150 | #define PORT_MCF 78 | 150 | #define PORT_MCF 78 |
| 151 | 151 | ||
| 152 | 152 | ||
| 153 | /* MN10300 on-chip UART numbers */ | ||
| 154 | #define PORT_MN10300 80 | ||
| 155 | #define PORT_MN10300_CTS 81 | ||
| 156 | |||
| 153 | #ifdef __KERNEL__ | 157 | #ifdef __KERNEL__ |
| 154 | 158 | ||
| 155 | #include <linux/compiler.h> | 159 | #include <linux/compiler.h> |
diff --git a/include/linux/shmem_fs.h b/include/linux/shmem_fs.h index f3c51899117f..8d5fb36ea047 100644 --- a/include/linux/shmem_fs.h +++ b/include/linux/shmem_fs.h | |||
| @@ -30,9 +30,12 @@ struct shmem_sb_info { | |||
| 30 | unsigned long free_blocks; /* How many are left for allocation */ | 30 | unsigned long free_blocks; /* How many are left for allocation */ |
| 31 | unsigned long max_inodes; /* How many inodes are allowed */ | 31 | unsigned long max_inodes; /* How many inodes are allowed */ |
| 32 | unsigned long free_inodes; /* How many are left for allocation */ | 32 | unsigned long free_inodes; /* How many are left for allocation */ |
| 33 | spinlock_t stat_lock; /* Serialize shmem_sb_info changes */ | ||
| 34 | uid_t uid; /* Mount uid for root directory */ | ||
| 35 | gid_t gid; /* Mount gid for root directory */ | ||
| 36 | mode_t mode; /* Mount mode for root directory */ | ||
| 33 | int policy; /* Default NUMA memory alloc policy */ | 37 | int policy; /* Default NUMA memory alloc policy */ |
| 34 | nodemask_t policy_nodes; /* nodemask for preferred and bind */ | 38 | nodemask_t policy_nodes; /* nodemask for preferred and bind */ |
| 35 | spinlock_t stat_lock; | ||
| 36 | }; | 39 | }; |
| 37 | 40 | ||
| 38 | static inline struct shmem_inode_info *SHMEM_I(struct inode *inode) | 41 | static inline struct shmem_inode_info *SHMEM_I(struct inode *inode) |
diff --git a/include/linux/signal.h b/include/linux/signal.h index 7e095147656c..42d2e0a948f4 100644 --- a/include/linux/signal.h +++ b/include/linux/signal.h | |||
| @@ -241,6 +241,7 @@ extern int show_unhandled_signals; | |||
| 241 | 241 | ||
| 242 | struct pt_regs; | 242 | struct pt_regs; |
| 243 | extern int get_signal_to_deliver(siginfo_t *info, struct k_sigaction *return_ka, struct pt_regs *regs, void *cookie); | 243 | extern int get_signal_to_deliver(siginfo_t *info, struct k_sigaction *return_ka, struct pt_regs *regs, void *cookie); |
| 244 | extern void exit_signals(struct task_struct *tsk); | ||
| 244 | 245 | ||
| 245 | extern struct kmem_cache *sighand_cachep; | 246 | extern struct kmem_cache *sighand_cachep; |
| 246 | 247 | ||
diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h index 124449733c55..576a5f77d3bd 100644 --- a/include/linux/spinlock.h +++ b/include/linux/spinlock.h | |||
| @@ -71,7 +71,7 @@ | |||
| 71 | #define LOCK_SECTION_END \ | 71 | #define LOCK_SECTION_END \ |
| 72 | ".previous\n\t" | 72 | ".previous\n\t" |
| 73 | 73 | ||
| 74 | #define __lockfunc fastcall __attribute__((section(".spinlock.text"))) | 74 | #define __lockfunc __attribute__((section(".spinlock.text"))) |
| 75 | 75 | ||
| 76 | /* | 76 | /* |
| 77 | * Pull the raw_spinlock_t and raw_rwlock_t definitions: | 77 | * Pull the raw_spinlock_t and raw_rwlock_t definitions: |
diff --git a/include/linux/time.h b/include/linux/time.h index ceaab9fff155..2091a19f1655 100644 --- a/include/linux/time.h +++ b/include/linux/time.h | |||
| @@ -120,7 +120,7 @@ extern void getboottime(struct timespec *ts); | |||
| 120 | extern void monotonic_to_bootbased(struct timespec *ts); | 120 | extern void monotonic_to_bootbased(struct timespec *ts); |
| 121 | 121 | ||
| 122 | extern struct timespec timespec_trunc(struct timespec t, unsigned gran); | 122 | extern struct timespec timespec_trunc(struct timespec t, unsigned gran); |
| 123 | extern int timekeeping_is_continuous(void); | 123 | extern int timekeeping_valid_for_hres(void); |
| 124 | extern void update_wall_time(void); | 124 | extern void update_wall_time(void); |
| 125 | extern void update_xtime_cache(u64 nsec); | 125 | extern void update_xtime_cache(u64 nsec); |
| 126 | 126 | ||
diff --git a/include/linux/timer.h b/include/linux/timer.h index de0e71359ede..979fefdeb862 100644 --- a/include/linux/timer.h +++ b/include/linux/timer.h | |||
| @@ -35,8 +35,8 @@ extern struct tvec_base boot_tvec_bases; | |||
| 35 | struct timer_list _name = \ | 35 | struct timer_list _name = \ |
| 36 | TIMER_INITIALIZER(_function, _expires, _data) | 36 | TIMER_INITIALIZER(_function, _expires, _data) |
| 37 | 37 | ||
| 38 | void fastcall init_timer(struct timer_list * timer); | 38 | void init_timer(struct timer_list *timer); |
| 39 | void fastcall init_timer_deferrable(struct timer_list *timer); | 39 | void init_timer_deferrable(struct timer_list *timer); |
| 40 | 40 | ||
| 41 | static inline void setup_timer(struct timer_list * timer, | 41 | static inline void setup_timer(struct timer_list * timer, |
| 42 | void (*function)(unsigned long), | 42 | void (*function)(unsigned long), |
| @@ -124,8 +124,6 @@ static inline void timer_stats_timer_clear_start_info(struct timer_list *timer) | |||
| 124 | } | 124 | } |
| 125 | #endif | 125 | #endif |
| 126 | 126 | ||
| 127 | extern void delayed_work_timer_fn(unsigned long __data); | ||
| 128 | |||
| 129 | /** | 127 | /** |
| 130 | * add_timer - start a timer | 128 | * add_timer - start a timer |
| 131 | * @timer: the timer to be added | 129 | * @timer: the timer to be added |
diff --git a/include/linux/types.h b/include/linux/types.h index b94c0e4efe24..9dc2346627b4 100644 --- a/include/linux/types.h +++ b/include/linux/types.h | |||
| @@ -53,7 +53,7 @@ typedef __kernel_uid_t uid_t; | |||
| 53 | typedef __kernel_gid_t gid_t; | 53 | typedef __kernel_gid_t gid_t; |
| 54 | #endif /* __KERNEL__ */ | 54 | #endif /* __KERNEL__ */ |
| 55 | 55 | ||
| 56 | #if defined(__GNUC__) && !defined(__STRICT_ANSI__) | 56 | #if defined(__GNUC__) |
| 57 | typedef __kernel_loff_t loff_t; | 57 | typedef __kernel_loff_t loff_t; |
| 58 | #endif | 58 | #endif |
| 59 | 59 | ||
| @@ -119,7 +119,7 @@ typedef __u8 uint8_t; | |||
| 119 | typedef __u16 uint16_t; | 119 | typedef __u16 uint16_t; |
| 120 | typedef __u32 uint32_t; | 120 | typedef __u32 uint32_t; |
| 121 | 121 | ||
| 122 | #if defined(__GNUC__) && !defined(__STRICT_ANSI__) | 122 | #if defined(__GNUC__) |
| 123 | typedef __u64 uint64_t; | 123 | typedef __u64 uint64_t; |
| 124 | typedef __u64 u_int64_t; | 124 | typedef __u64 u_int64_t; |
| 125 | typedef __s64 int64_t; | 125 | typedef __s64 int64_t; |
| @@ -181,7 +181,7 @@ typedef __u16 __bitwise __le16; | |||
| 181 | typedef __u16 __bitwise __be16; | 181 | typedef __u16 __bitwise __be16; |
| 182 | typedef __u32 __bitwise __le32; | 182 | typedef __u32 __bitwise __le32; |
| 183 | typedef __u32 __bitwise __be32; | 183 | typedef __u32 __bitwise __be32; |
| 184 | #if defined(__GNUC__) && !defined(__STRICT_ANSI__) | 184 | #if defined(__GNUC__) |
| 185 | typedef __u64 __bitwise __le64; | 185 | typedef __u64 __bitwise __le64; |
| 186 | typedef __u64 __bitwise __be64; | 186 | typedef __u64 __bitwise __be64; |
| 187 | #endif | 187 | #endif |
diff --git a/include/linux/udf_fs.h b/include/linux/udf_fs.h index 36c684e1b110..aa88654eb76b 100644 --- a/include/linux/udf_fs.h +++ b/include/linux/udf_fs.h | |||
| @@ -32,18 +32,15 @@ | |||
| 32 | #define UDF_PREALLOCATE | 32 | #define UDF_PREALLOCATE |
| 33 | #define UDF_DEFAULT_PREALLOC_BLOCKS 8 | 33 | #define UDF_DEFAULT_PREALLOC_BLOCKS 8 |
| 34 | 34 | ||
| 35 | #define UDFFS_DATE "2004/29/09" | ||
| 36 | #define UDFFS_VERSION "0.9.8.1" | ||
| 37 | |||
| 38 | #undef UDFFS_DEBUG | 35 | #undef UDFFS_DEBUG |
| 39 | 36 | ||
| 40 | #ifdef UDFFS_DEBUG | 37 | #ifdef UDFFS_DEBUG |
| 41 | #define udf_debug(f, a...) \ | 38 | #define udf_debug(f, a...) \ |
| 42 | { \ | 39 | do { \ |
| 43 | printk (KERN_DEBUG "UDF-fs DEBUG %s:%d:%s: ", \ | 40 | printk (KERN_DEBUG "UDF-fs DEBUG %s:%d:%s: ", \ |
| 44 | __FILE__, __LINE__, __FUNCTION__); \ | 41 | __FILE__, __LINE__, __FUNCTION__); \ |
| 45 | printk (f, ##a); \ | 42 | printk (f, ##a); \ |
| 46 | } | 43 | } while (0) |
| 47 | #else | 44 | #else |
| 48 | #define udf_debug(f, a...) /**/ | 45 | #define udf_debug(f, a...) /**/ |
| 49 | #endif | 46 | #endif |
diff --git a/include/linux/udf_fs_sb.h b/include/linux/udf_fs_sb.h index 80ae9ef940dc..9bc47352b6b4 100644 --- a/include/linux/udf_fs_sb.h +++ b/include/linux/udf_fs_sb.h | |||
| @@ -75,7 +75,7 @@ struct udf_part_map | |||
| 75 | struct udf_sb_info | 75 | struct udf_sb_info |
| 76 | { | 76 | { |
| 77 | struct udf_part_map *s_partmaps; | 77 | struct udf_part_map *s_partmaps; |
| 78 | __u8 s_volident[32]; | 78 | __u8 s_volume_ident[32]; |
| 79 | 79 | ||
| 80 | /* Overall info */ | 80 | /* Overall info */ |
| 81 | __u16 s_partitions; | 81 | __u16 s_partitions; |
| @@ -84,9 +84,9 @@ struct udf_sb_info | |||
| 84 | /* Sector headers */ | 84 | /* Sector headers */ |
| 85 | __s32 s_session; | 85 | __s32 s_session; |
| 86 | __u32 s_anchor[4]; | 86 | __u32 s_anchor[4]; |
| 87 | __u32 s_lastblock; | 87 | __u32 s_last_block; |
| 88 | 88 | ||
| 89 | struct buffer_head *s_lvidbh; | 89 | struct buffer_head *s_lvid_bh; |
| 90 | 90 | ||
| 91 | /* Default permissions */ | 91 | /* Default permissions */ |
| 92 | mode_t s_umask; | 92 | mode_t s_umask; |
| @@ -94,10 +94,10 @@ struct udf_sb_info | |||
| 94 | uid_t s_uid; | 94 | uid_t s_uid; |
| 95 | 95 | ||
| 96 | /* Root Info */ | 96 | /* Root Info */ |
| 97 | struct timespec s_recordtime; | 97 | struct timespec s_record_time; |
| 98 | 98 | ||
| 99 | /* Fileset Info */ | 99 | /* Fileset Info */ |
| 100 | __u16 s_serialnum; | 100 | __u16 s_serial_number; |
| 101 | 101 | ||
| 102 | /* highest UDF revision we have recorded to this media */ | 102 | /* highest UDF revision we have recorded to this media */ |
| 103 | __u16 s_udfrev; | 103 | __u16 s_udfrev; |
| @@ -109,7 +109,7 @@ struct udf_sb_info | |||
| 109 | struct nls_table *s_nls_map; | 109 | struct nls_table *s_nls_map; |
| 110 | 110 | ||
| 111 | /* VAT inode */ | 111 | /* VAT inode */ |
| 112 | struct inode *s_vat; | 112 | struct inode *s_vat_inode; |
| 113 | 113 | ||
| 114 | struct mutex s_alloc_mutex; | 114 | struct mutex s_alloc_mutex; |
| 115 | }; | 115 | }; |
diff --git a/include/linux/ufs_fs.h b/include/linux/ufs_fs.h deleted file mode 100644 index 10b854d3561f..000000000000 --- a/include/linux/ufs_fs.h +++ /dev/null | |||
| @@ -1,953 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/linux/ufs_fs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1996 | ||
| 5 | * Adrian Rodriguez (adrian@franklins-tower.rutgers.edu) | ||
| 6 | * Laboratory for Computer Science Research Computing Facility | ||
| 7 | * Rutgers, The State University of New Jersey | ||
| 8 | * | ||
| 9 | * Clean swab support by Fare <fare@tunes.org> | ||
| 10 | * just hope no one is using NNUUXXI on __?64 structure elements | ||
| 11 | * 64-bit clean thanks to Maciej W. Rozycki <macro@ds2.pg.gda.pl> | ||
| 12 | * | ||
| 13 | * 4.4BSD (FreeBSD) support added on February 1st 1998 by | ||
| 14 | * Niels Kristian Bech Jensen <nkbj@image.dk> partially based | ||
| 15 | * on code by Martin von Loewis <martin@mira.isdn.cs.tu-berlin.de>. | ||
| 16 | * | ||
| 17 | * NeXTstep support added on February 5th 1998 by | ||
| 18 | * Niels Kristian Bech Jensen <nkbj@image.dk>. | ||
| 19 | * | ||
| 20 | * Write support by Daniel Pirkl <daniel.pirkl@email.cz> | ||
| 21 | * | ||
| 22 | * HP/UX hfs filesystem support added by | ||
| 23 | * Martin K. Petersen <mkp@mkp.net>, August 1999 | ||
| 24 | * | ||
| 25 | * UFS2 (of FreeBSD 5.x) support added by | ||
| 26 | * Niraj Kumar <niraj17@iitbombay.org> , Jan 2004 | ||
| 27 | * | ||
| 28 | */ | ||
| 29 | |||
| 30 | #ifndef __LINUX_UFS_FS_H | ||
| 31 | #define __LINUX_UFS_FS_H | ||
| 32 | |||
| 33 | #include <linux/types.h> | ||
| 34 | #include <linux/kernel.h> | ||
| 35 | #include <linux/stat.h> | ||
| 36 | #include <linux/fs.h> | ||
| 37 | |||
| 38 | #ifndef __KERNEL__ | ||
| 39 | typedef __u64 __fs64; | ||
| 40 | typedef __u32 __fs32; | ||
| 41 | typedef __u16 __fs16; | ||
| 42 | #else | ||
| 43 | #include <asm/div64.h> | ||
| 44 | typedef __u64 __bitwise __fs64; | ||
| 45 | typedef __u32 __bitwise __fs32; | ||
| 46 | typedef __u16 __bitwise __fs16; | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #define UFS_BBLOCK 0 | ||
| 50 | #define UFS_BBSIZE 8192 | ||
| 51 | #define UFS_SBLOCK 8192 | ||
| 52 | #define UFS_SBSIZE 8192 | ||
| 53 | |||
| 54 | #define UFS_SECTOR_SIZE 512 | ||
| 55 | #define UFS_SECTOR_BITS 9 | ||
| 56 | #define UFS_MAGIC 0x00011954 | ||
| 57 | #define UFS2_MAGIC 0x19540119 | ||
| 58 | #define UFS_CIGAM 0x54190100 /* byteswapped MAGIC */ | ||
| 59 | |||
| 60 | /* Copied from FreeBSD */ | ||
| 61 | /* | ||
| 62 | * Each disk drive contains some number of filesystems. | ||
| 63 | * A filesystem consists of a number of cylinder groups. | ||
| 64 | * Each cylinder group has inodes and data. | ||
| 65 | * | ||
| 66 | * A filesystem is described by its super-block, which in turn | ||
| 67 | * describes the cylinder groups. The super-block is critical | ||
| 68 | * data and is replicated in each cylinder group to protect against | ||
| 69 | * catastrophic loss. This is done at `newfs' time and the critical | ||
| 70 | * super-block data does not change, so the copies need not be | ||
| 71 | * referenced further unless disaster strikes. | ||
| 72 | * | ||
| 73 | * For filesystem fs, the offsets of the various blocks of interest | ||
| 74 | * are given in the super block as: | ||
| 75 | * [fs->fs_sblkno] Super-block | ||
| 76 | * [fs->fs_cblkno] Cylinder group block | ||
| 77 | * [fs->fs_iblkno] Inode blocks | ||
| 78 | * [fs->fs_dblkno] Data blocks | ||
| 79 | * The beginning of cylinder group cg in fs, is given by | ||
| 80 | * the ``cgbase(fs, cg)'' macro. | ||
| 81 | * | ||
| 82 | * Depending on the architecture and the media, the superblock may | ||
| 83 | * reside in any one of four places. For tiny media where every block | ||
| 84 | * counts, it is placed at the very front of the partition. Historically, | ||
| 85 | * UFS1 placed it 8K from the front to leave room for the disk label and | ||
| 86 | * a small bootstrap. For UFS2 it got moved to 64K from the front to leave | ||
| 87 | * room for the disk label and a bigger bootstrap, and for really piggy | ||
| 88 | * systems we check at 256K from the front if the first three fail. In | ||
| 89 | * all cases the size of the superblock will be SBLOCKSIZE. All values are | ||
| 90 | * given in byte-offset form, so they do not imply a sector size. The | ||
| 91 | * SBLOCKSEARCH specifies the order in which the locations should be searched. | ||
| 92 | */ | ||
| 93 | #define SBLOCK_FLOPPY 0 | ||
| 94 | #define SBLOCK_UFS1 8192 | ||
| 95 | #define SBLOCK_UFS2 65536 | ||
| 96 | #define SBLOCK_PIGGY 262144 | ||
| 97 | #define SBLOCKSIZE 8192 | ||
| 98 | #define SBLOCKSEARCH \ | ||
| 99 | { SBLOCK_UFS2, SBLOCK_UFS1, SBLOCK_FLOPPY, SBLOCK_PIGGY, -1 } | ||
| 100 | |||
| 101 | |||
| 102 | /* HP specific MAGIC values */ | ||
| 103 | |||
| 104 | #define UFS_MAGIC_LFN 0x00095014 /* fs supports filenames > 14 chars */ | ||
| 105 | #define UFS_CIGAM_LFN 0x14500900 /* srahc 41 < semanelif stroppus sf */ | ||
| 106 | |||
| 107 | #define UFS_MAGIC_SEC 0x00612195 /* B1 security fs */ | ||
| 108 | #define UFS_CIGAM_SEC 0x95216100 | ||
| 109 | |||
| 110 | #define UFS_MAGIC_FEA 0x00195612 /* fs_featurebits supported */ | ||
| 111 | #define UFS_CIGAM_FEA 0x12561900 | ||
| 112 | |||
| 113 | #define UFS_MAGIC_4GB 0x05231994 /* fs > 4 GB && fs_featurebits */ | ||
| 114 | #define UFS_CIGAM_4GB 0x94192305 | ||
| 115 | |||
| 116 | /* Seems somebody at HP goofed here. B1 and lfs are both 0x2 !?! */ | ||
| 117 | #define UFS_FSF_LFN 0x00000001 /* long file names */ | ||
| 118 | #define UFS_FSF_B1 0x00000002 /* B1 security */ | ||
| 119 | #define UFS_FSF_LFS 0x00000002 /* large files */ | ||
| 120 | #define UFS_FSF_LUID 0x00000004 /* large UIDs */ | ||
| 121 | |||
| 122 | /* End of HP stuff */ | ||
| 123 | |||
| 124 | |||
| 125 | #define UFS_BSIZE 8192 | ||
| 126 | #define UFS_MINBSIZE 4096 | ||
| 127 | #define UFS_FSIZE 1024 | ||
| 128 | #define UFS_MAXFRAG (UFS_BSIZE / UFS_FSIZE) | ||
| 129 | |||
| 130 | #define UFS_NDADDR 12 | ||
| 131 | #define UFS_NINDIR 3 | ||
| 132 | |||
| 133 | #define UFS_IND_BLOCK (UFS_NDADDR + 0) | ||
| 134 | #define UFS_DIND_BLOCK (UFS_NDADDR + 1) | ||
| 135 | #define UFS_TIND_BLOCK (UFS_NDADDR + 2) | ||
| 136 | |||
| 137 | #define UFS_NDIR_FRAGMENT (UFS_NDADDR << uspi->s_fpbshift) | ||
| 138 | #define UFS_IND_FRAGMENT (UFS_IND_BLOCK << uspi->s_fpbshift) | ||
| 139 | #define UFS_DIND_FRAGMENT (UFS_DIND_BLOCK << uspi->s_fpbshift) | ||
| 140 | #define UFS_TIND_FRAGMENT (UFS_TIND_BLOCK << uspi->s_fpbshift) | ||
| 141 | |||
| 142 | #define UFS_ROOTINO 2 | ||
| 143 | #define UFS_FIRST_INO (UFS_ROOTINO + 1) | ||
| 144 | |||
| 145 | #define UFS_USEEFT ((__u16)65535) | ||
| 146 | |||
| 147 | #define UFS_FSOK 0x7c269d38 | ||
| 148 | #define UFS_FSACTIVE ((__s8)0x00) | ||
| 149 | #define UFS_FSCLEAN ((__s8)0x01) | ||
| 150 | #define UFS_FSSTABLE ((__s8)0x02) | ||
| 151 | #define UFS_FSOSF1 ((__s8)0x03) /* is this correct for DEC OSF/1? */ | ||
| 152 | #define UFS_FSBAD ((__s8)0xff) | ||
| 153 | |||
| 154 | /* From here to next blank line, s_flags for ufs_sb_info */ | ||
| 155 | /* directory entry encoding */ | ||
| 156 | #define UFS_DE_MASK 0x00000010 /* mask for the following */ | ||
| 157 | #define UFS_DE_OLD 0x00000000 | ||
| 158 | #define UFS_DE_44BSD 0x00000010 | ||
| 159 | /* uid encoding */ | ||
| 160 | #define UFS_UID_MASK 0x00000060 /* mask for the following */ | ||
| 161 | #define UFS_UID_OLD 0x00000000 | ||
| 162 | #define UFS_UID_44BSD 0x00000020 | ||
| 163 | #define UFS_UID_EFT 0x00000040 | ||
| 164 | /* superblock state encoding */ | ||
| 165 | #define UFS_ST_MASK 0x00000700 /* mask for the following */ | ||
| 166 | #define UFS_ST_OLD 0x00000000 | ||
| 167 | #define UFS_ST_44BSD 0x00000100 | ||
| 168 | #define UFS_ST_SUN 0x00000200 /* Solaris */ | ||
| 169 | #define UFS_ST_SUNOS 0x00000300 | ||
| 170 | #define UFS_ST_SUNx86 0x00000400 /* Solaris x86 */ | ||
| 171 | /*cylinder group encoding */ | ||
| 172 | #define UFS_CG_MASK 0x00003000 /* mask for the following */ | ||
| 173 | #define UFS_CG_OLD 0x00000000 | ||
| 174 | #define UFS_CG_44BSD 0x00002000 | ||
| 175 | #define UFS_CG_SUN 0x00001000 | ||
| 176 | /* filesystem type encoding */ | ||
| 177 | #define UFS_TYPE_MASK 0x00010000 /* mask for the following */ | ||
| 178 | #define UFS_TYPE_UFS1 0x00000000 | ||
| 179 | #define UFS_TYPE_UFS2 0x00010000 | ||
| 180 | |||
| 181 | |||
| 182 | /* fs_inodefmt options */ | ||
| 183 | #define UFS_42INODEFMT -1 | ||
| 184 | #define UFS_44INODEFMT 2 | ||
| 185 | |||
| 186 | /* | ||
| 187 | * MINFREE gives the minimum acceptable percentage of file system | ||
| 188 | * blocks which may be free. If the freelist drops below this level | ||
| 189 | * only the superuser may continue to allocate blocks. This may | ||
| 190 | * be set to 0 if no reserve of free blocks is deemed necessary, | ||
| 191 | * however throughput drops by fifty percent if the file system | ||
| 192 | * is run at between 95% and 100% full; thus the minimum default | ||
| 193 | * value of fs_minfree is 5%. However, to get good clustering | ||
| 194 | * performance, 10% is a better choice. hence we use 10% as our | ||
| 195 | * default value. With 10% free space, fragmentation is not a | ||
| 196 | * problem, so we choose to optimize for time. | ||
| 197 | */ | ||
| 198 | #define UFS_MINFREE 5 | ||
| 199 | #define UFS_DEFAULTOPT UFS_OPTTIME | ||
| 200 | |||
| 201 | /* | ||
| 202 | * Turn file system block numbers into disk block addresses. | ||
| 203 | * This maps file system blocks to device size blocks. | ||
| 204 | */ | ||
| 205 | #define ufs_fsbtodb(uspi, b) ((b) << (uspi)->s_fsbtodb) | ||
| 206 | #define ufs_dbtofsb(uspi, b) ((b) >> (uspi)->s_fsbtodb) | ||
| 207 | |||
| 208 | /* | ||
| 209 | * Cylinder group macros to locate things in cylinder groups. | ||
| 210 | * They calc file system addresses of cylinder group data structures. | ||
| 211 | */ | ||
| 212 | #define ufs_cgbase(c) (uspi->s_fpg * (c)) | ||
| 213 | #define ufs_cgstart(c) ((uspi)->fs_magic == UFS2_MAGIC ? ufs_cgbase(c) : \ | ||
| 214 | (ufs_cgbase(c) + uspi->s_cgoffset * ((c) & ~uspi->s_cgmask))) | ||
| 215 | #define ufs_cgsblock(c) (ufs_cgstart(c) + uspi->s_sblkno) /* super blk */ | ||
| 216 | #define ufs_cgcmin(c) (ufs_cgstart(c) + uspi->s_cblkno) /* cg block */ | ||
| 217 | #define ufs_cgimin(c) (ufs_cgstart(c) + uspi->s_iblkno) /* inode blk */ | ||
| 218 | #define ufs_cgdmin(c) (ufs_cgstart(c) + uspi->s_dblkno) /* 1st data */ | ||
| 219 | |||
| 220 | /* | ||
| 221 | * Macros for handling inode numbers: | ||
| 222 | * inode number to file system block offset. | ||
| 223 | * inode number to cylinder group number. | ||
| 224 | * inode number to file system block address. | ||
| 225 | */ | ||
| 226 | #define ufs_inotocg(x) ((x) / uspi->s_ipg) | ||
| 227 | #define ufs_inotocgoff(x) ((x) % uspi->s_ipg) | ||
| 228 | #define ufs_inotofsba(x) (((u64)ufs_cgimin(ufs_inotocg(x))) + ufs_inotocgoff(x) / uspi->s_inopf) | ||
| 229 | #define ufs_inotofsbo(x) ((x) % uspi->s_inopf) | ||
| 230 | |||
| 231 | /* | ||
| 232 | * Compute the cylinder and rotational position of a cyl block addr. | ||
| 233 | */ | ||
| 234 | #define ufs_cbtocylno(bno) \ | ||
| 235 | ((bno) * uspi->s_nspf / uspi->s_spc) | ||
| 236 | #define ufs_cbtorpos(bno) \ | ||
| 237 | ((((bno) * uspi->s_nspf % uspi->s_spc / uspi->s_nsect \ | ||
| 238 | * uspi->s_trackskew + (bno) * uspi->s_nspf % uspi->s_spc \ | ||
| 239 | % uspi->s_nsect * uspi->s_interleave) % uspi->s_nsect \ | ||
| 240 | * uspi->s_nrpos) / uspi->s_npsect) | ||
| 241 | |||
| 242 | /* | ||
| 243 | * The following macros optimize certain frequently calculated | ||
| 244 | * quantities by using shifts and masks in place of divisions | ||
| 245 | * modulos and multiplications. | ||
| 246 | */ | ||
| 247 | #define ufs_blkoff(loc) ((loc) & uspi->s_qbmask) | ||
| 248 | #define ufs_fragoff(loc) ((loc) & uspi->s_qfmask) | ||
| 249 | #define ufs_lblktosize(blk) ((blk) << uspi->s_bshift) | ||
| 250 | #define ufs_lblkno(loc) ((loc) >> uspi->s_bshift) | ||
| 251 | #define ufs_numfrags(loc) ((loc) >> uspi->s_fshift) | ||
| 252 | #define ufs_blkroundup(size) (((size) + uspi->s_qbmask) & uspi->s_bmask) | ||
| 253 | #define ufs_fragroundup(size) (((size) + uspi->s_qfmask) & uspi->s_fmask) | ||
| 254 | #define ufs_fragstoblks(frags) ((frags) >> uspi->s_fpbshift) | ||
| 255 | #define ufs_blkstofrags(blks) ((blks) << uspi->s_fpbshift) | ||
| 256 | #define ufs_fragnum(fsb) ((fsb) & uspi->s_fpbmask) | ||
| 257 | #define ufs_blknum(fsb) ((fsb) & ~uspi->s_fpbmask) | ||
| 258 | |||
| 259 | #define UFS_MAXNAMLEN 255 | ||
| 260 | #define UFS_MAXMNTLEN 512 | ||
| 261 | #define UFS2_MAXMNTLEN 468 | ||
| 262 | #define UFS2_MAXVOLLEN 32 | ||
| 263 | #define UFS_MAXCSBUFS 31 | ||
| 264 | #define UFS_LINK_MAX 32000 | ||
| 265 | /* | ||
| 266 | #define UFS2_NOCSPTRS ((128 / sizeof(void *)) - 4) | ||
| 267 | */ | ||
| 268 | #define UFS2_NOCSPTRS 28 | ||
| 269 | |||
| 270 | /* | ||
| 271 | * UFS_DIR_PAD defines the directory entries boundaries | ||
| 272 | * (must be a multiple of 4) | ||
| 273 | */ | ||
| 274 | #define UFS_DIR_PAD 4 | ||
| 275 | #define UFS_DIR_ROUND (UFS_DIR_PAD - 1) | ||
| 276 | #define UFS_DIR_REC_LEN(name_len) (((name_len) + 1 + 8 + UFS_DIR_ROUND) & ~UFS_DIR_ROUND) | ||
| 277 | |||
| 278 | struct ufs_timeval { | ||
| 279 | __fs32 tv_sec; | ||
| 280 | __fs32 tv_usec; | ||
| 281 | }; | ||
| 282 | |||
| 283 | struct ufs_dir_entry { | ||
| 284 | __fs32 d_ino; /* inode number of this entry */ | ||
| 285 | __fs16 d_reclen; /* length of this entry */ | ||
| 286 | union { | ||
| 287 | __fs16 d_namlen; /* actual length of d_name */ | ||
| 288 | struct { | ||
| 289 | __u8 d_type; /* file type */ | ||
| 290 | __u8 d_namlen; /* length of string in d_name */ | ||
| 291 | } d_44; | ||
| 292 | } d_u; | ||
| 293 | __u8 d_name[UFS_MAXNAMLEN + 1]; /* file name */ | ||
| 294 | }; | ||
| 295 | |||
| 296 | struct ufs_csum { | ||
| 297 | __fs32 cs_ndir; /* number of directories */ | ||
| 298 | __fs32 cs_nbfree; /* number of free blocks */ | ||
| 299 | __fs32 cs_nifree; /* number of free inodes */ | ||
| 300 | __fs32 cs_nffree; /* number of free frags */ | ||
| 301 | }; | ||
| 302 | struct ufs2_csum_total { | ||
| 303 | __fs64 cs_ndir; /* number of directories */ | ||
| 304 | __fs64 cs_nbfree; /* number of free blocks */ | ||
| 305 | __fs64 cs_nifree; /* number of free inodes */ | ||
| 306 | __fs64 cs_nffree; /* number of free frags */ | ||
| 307 | __fs64 cs_numclusters; /* number of free clusters */ | ||
| 308 | __fs64 cs_spare[3]; /* future expansion */ | ||
| 309 | }; | ||
| 310 | |||
| 311 | struct ufs_csum_core { | ||
| 312 | __u64 cs_ndir; /* number of directories */ | ||
| 313 | __u64 cs_nbfree; /* number of free blocks */ | ||
| 314 | __u64 cs_nifree; /* number of free inodes */ | ||
| 315 | __u64 cs_nffree; /* number of free frags */ | ||
| 316 | __u64 cs_numclusters; /* number of free clusters */ | ||
| 317 | }; | ||
| 318 | |||
| 319 | /* | ||
| 320 | * File system flags | ||
| 321 | */ | ||
| 322 | #define UFS_UNCLEAN 0x01 /* file system not clean at mount (unused) */ | ||
| 323 | #define UFS_DOSOFTDEP 0x02 /* file system using soft dependencies */ | ||
| 324 | #define UFS_NEEDSFSCK 0x04 /* needs sync fsck (FreeBSD compat, unused) */ | ||
| 325 | #define UFS_INDEXDIRS 0x08 /* kernel supports indexed directories */ | ||
| 326 | #define UFS_ACLS 0x10 /* file system has ACLs enabled */ | ||
| 327 | #define UFS_MULTILABEL 0x20 /* file system is MAC multi-label */ | ||
| 328 | #define UFS_FLAGS_UPDATED 0x80 /* flags have been moved to new location */ | ||
| 329 | |||
| 330 | #if 0 | ||
| 331 | /* | ||
| 332 | * This is the actual superblock, as it is laid out on the disk. | ||
| 333 | * Do NOT use this structure, because of sizeof(ufs_super_block) > 512 and | ||
| 334 | * it may occupy several blocks, use | ||
| 335 | * struct ufs_super_block_(first,second,third) instead. | ||
| 336 | */ | ||
| 337 | struct ufs_super_block { | ||
| 338 | union { | ||
| 339 | struct { | ||
| 340 | __fs32 fs_link; /* UNUSED */ | ||
| 341 | } fs_42; | ||
| 342 | struct { | ||
| 343 | __fs32 fs_state; /* file system state flag */ | ||
| 344 | } fs_sun; | ||
| 345 | } fs_u0; | ||
| 346 | __fs32 fs_rlink; /* UNUSED */ | ||
| 347 | __fs32 fs_sblkno; /* addr of super-block in filesys */ | ||
| 348 | __fs32 fs_cblkno; /* offset of cyl-block in filesys */ | ||
| 349 | __fs32 fs_iblkno; /* offset of inode-blocks in filesys */ | ||
| 350 | __fs32 fs_dblkno; /* offset of first data after cg */ | ||
| 351 | __fs32 fs_cgoffset; /* cylinder group offset in cylinder */ | ||
| 352 | __fs32 fs_cgmask; /* used to calc mod fs_ntrak */ | ||
| 353 | __fs32 fs_time; /* last time written -- time_t */ | ||
| 354 | __fs32 fs_size; /* number of blocks in fs */ | ||
| 355 | __fs32 fs_dsize; /* number of data blocks in fs */ | ||
| 356 | __fs32 fs_ncg; /* number of cylinder groups */ | ||
| 357 | __fs32 fs_bsize; /* size of basic blocks in fs */ | ||
| 358 | __fs32 fs_fsize; /* size of frag blocks in fs */ | ||
| 359 | __fs32 fs_frag; /* number of frags in a block in fs */ | ||
| 360 | /* these are configuration parameters */ | ||
| 361 | __fs32 fs_minfree; /* minimum percentage of free blocks */ | ||
| 362 | __fs32 fs_rotdelay; /* num of ms for optimal next block */ | ||
| 363 | __fs32 fs_rps; /* disk revolutions per second */ | ||
| 364 | /* these fields can be computed from the others */ | ||
| 365 | __fs32 fs_bmask; /* ``blkoff'' calc of blk offsets */ | ||
| 366 | __fs32 fs_fmask; /* ``fragoff'' calc of frag offsets */ | ||
| 367 | __fs32 fs_bshift; /* ``lblkno'' calc of logical blkno */ | ||
| 368 | __fs32 fs_fshift; /* ``numfrags'' calc number of frags */ | ||
| 369 | /* these are configuration parameters */ | ||
| 370 | __fs32 fs_maxcontig; /* max number of contiguous blks */ | ||
| 371 | __fs32 fs_maxbpg; /* max number of blks per cyl group */ | ||
| 372 | /* these fields can be computed from the others */ | ||
| 373 | __fs32 fs_fragshift; /* block to frag shift */ | ||
| 374 | __fs32 fs_fsbtodb; /* fsbtodb and dbtofsb shift constant */ | ||
| 375 | __fs32 fs_sbsize; /* actual size of super block */ | ||
| 376 | __fs32 fs_csmask; /* csum block offset */ | ||
| 377 | __fs32 fs_csshift; /* csum block number */ | ||
| 378 | __fs32 fs_nindir; /* value of NINDIR */ | ||
| 379 | __fs32 fs_inopb; /* value of INOPB */ | ||
| 380 | __fs32 fs_nspf; /* value of NSPF */ | ||
| 381 | /* yet another configuration parameter */ | ||
| 382 | __fs32 fs_optim; /* optimization preference, see below */ | ||
| 383 | /* these fields are derived from the hardware */ | ||
| 384 | union { | ||
| 385 | struct { | ||
| 386 | __fs32 fs_npsect; /* # sectors/track including spares */ | ||
| 387 | } fs_sun; | ||
| 388 | struct { | ||
| 389 | __fs32 fs_state; /* file system state time stamp */ | ||
| 390 | } fs_sunx86; | ||
| 391 | } fs_u1; | ||
| 392 | __fs32 fs_interleave; /* hardware sector interleave */ | ||
| 393 | __fs32 fs_trackskew; /* sector 0 skew, per track */ | ||
| 394 | /* a unique id for this filesystem (currently unused and unmaintained) */ | ||
| 395 | /* In 4.3 Tahoe this space is used by fs_headswitch and fs_trkseek */ | ||
| 396 | /* Neither of those fields is used in the Tahoe code right now but */ | ||
| 397 | /* there could be problems if they are. */ | ||
| 398 | __fs32 fs_id[2]; /* file system id */ | ||
| 399 | /* sizes determined by number of cylinder groups and their sizes */ | ||
| 400 | __fs32 fs_csaddr; /* blk addr of cyl grp summary area */ | ||
| 401 | __fs32 fs_cssize; /* size of cyl grp summary area */ | ||
| 402 | __fs32 fs_cgsize; /* cylinder group size */ | ||
| 403 | /* these fields are derived from the hardware */ | ||
| 404 | __fs32 fs_ntrak; /* tracks per cylinder */ | ||
| 405 | __fs32 fs_nsect; /* sectors per track */ | ||
| 406 | __fs32 fs_spc; /* sectors per cylinder */ | ||
| 407 | /* this comes from the disk driver partitioning */ | ||
| 408 | __fs32 fs_ncyl; /* cylinders in file system */ | ||
| 409 | /* these fields can be computed from the others */ | ||
| 410 | __fs32 fs_cpg; /* cylinders per group */ | ||
| 411 | __fs32 fs_ipg; /* inodes per cylinder group */ | ||
| 412 | __fs32 fs_fpg; /* blocks per group * fs_frag */ | ||
| 413 | /* this data must be re-computed after crashes */ | ||
| 414 | struct ufs_csum fs_cstotal; /* cylinder summary information */ | ||
| 415 | /* these fields are cleared at mount time */ | ||
| 416 | __s8 fs_fmod; /* super block modified flag */ | ||
| 417 | __s8 fs_clean; /* file system is clean flag */ | ||
| 418 | __s8 fs_ronly; /* mounted read-only flag */ | ||
| 419 | __s8 fs_flags; | ||
| 420 | union { | ||
| 421 | struct { | ||
| 422 | __s8 fs_fsmnt[UFS_MAXMNTLEN];/* name mounted on */ | ||
| 423 | __fs32 fs_cgrotor; /* last cg searched */ | ||
| 424 | __fs32 fs_csp[UFS_MAXCSBUFS];/*list of fs_cs info buffers */ | ||
| 425 | __fs32 fs_maxcluster; | ||
| 426 | __fs32 fs_cpc; /* cyl per cycle in postbl */ | ||
| 427 | __fs16 fs_opostbl[16][8]; /* old rotation block list head */ | ||
| 428 | } fs_u1; | ||
| 429 | struct { | ||
| 430 | __s8 fs_fsmnt[UFS2_MAXMNTLEN]; /* name mounted on */ | ||
| 431 | __u8 fs_volname[UFS2_MAXVOLLEN]; /* volume name */ | ||
| 432 | __fs64 fs_swuid; /* system-wide uid */ | ||
| 433 | __fs32 fs_pad; /* due to alignment of fs_swuid */ | ||
| 434 | __fs32 fs_cgrotor; /* last cg searched */ | ||
| 435 | __fs32 fs_ocsp[UFS2_NOCSPTRS]; /*list of fs_cs info buffers */ | ||
| 436 | __fs32 fs_contigdirs;/*# of contiguously allocated dirs */ | ||
| 437 | __fs32 fs_csp; /* cg summary info buffer for fs_cs */ | ||
| 438 | __fs32 fs_maxcluster; | ||
| 439 | __fs32 fs_active;/* used by snapshots to track fs */ | ||
| 440 | __fs32 fs_old_cpc; /* cyl per cycle in postbl */ | ||
| 441 | __fs32 fs_maxbsize;/*maximum blocking factor permitted */ | ||
| 442 | __fs64 fs_sparecon64[17];/*old rotation block list head */ | ||
| 443 | __fs64 fs_sblockloc; /* byte offset of standard superblock */ | ||
| 444 | struct ufs2_csum_total fs_cstotal;/*cylinder summary information*/ | ||
| 445 | struct ufs_timeval fs_time; /* last time written */ | ||
| 446 | __fs64 fs_size; /* number of blocks in fs */ | ||
| 447 | __fs64 fs_dsize; /* number of data blocks in fs */ | ||
| 448 | __fs64 fs_csaddr; /* blk addr of cyl grp summary area */ | ||
| 449 | __fs64 fs_pendingblocks;/* blocks in process of being freed */ | ||
| 450 | __fs32 fs_pendinginodes;/*inodes in process of being freed */ | ||
| 451 | } fs_u2; | ||
| 452 | } fs_u11; | ||
| 453 | union { | ||
| 454 | struct { | ||
| 455 | __fs32 fs_sparecon[53];/* reserved for future constants */ | ||
| 456 | __fs32 fs_reclaim; | ||
| 457 | __fs32 fs_sparecon2[1]; | ||
| 458 | __fs32 fs_state; /* file system state time stamp */ | ||
| 459 | __fs32 fs_qbmask[2]; /* ~usb_bmask */ | ||
| 460 | __fs32 fs_qfmask[2]; /* ~usb_fmask */ | ||
| 461 | } fs_sun; | ||
| 462 | struct { | ||
| 463 | __fs32 fs_sparecon[53];/* reserved for future constants */ | ||
| 464 | __fs32 fs_reclaim; | ||
| 465 | __fs32 fs_sparecon2[1]; | ||
| 466 | __fs32 fs_npsect; /* # sectors/track including spares */ | ||
| 467 | __fs32 fs_qbmask[2]; /* ~usb_bmask */ | ||
| 468 | __fs32 fs_qfmask[2]; /* ~usb_fmask */ | ||
| 469 | } fs_sunx86; | ||
| 470 | struct { | ||
| 471 | __fs32 fs_sparecon[50];/* reserved for future constants */ | ||
| 472 | __fs32 fs_contigsumsize;/* size of cluster summary array */ | ||
| 473 | __fs32 fs_maxsymlinklen;/* max length of an internal symlink */ | ||
| 474 | __fs32 fs_inodefmt; /* format of on-disk inodes */ | ||
| 475 | __fs32 fs_maxfilesize[2]; /* max representable file size */ | ||
| 476 | __fs32 fs_qbmask[2]; /* ~usb_bmask */ | ||
| 477 | __fs32 fs_qfmask[2]; /* ~usb_fmask */ | ||
| 478 | __fs32 fs_state; /* file system state time stamp */ | ||
| 479 | } fs_44; | ||
| 480 | } fs_u2; | ||
| 481 | __fs32 fs_postblformat; /* format of positional layout tables */ | ||
| 482 | __fs32 fs_nrpos; /* number of rotational positions */ | ||
| 483 | __fs32 fs_postbloff; /* (__s16) rotation block list head */ | ||
| 484 | __fs32 fs_rotbloff; /* (__u8) blocks for each rotation */ | ||
| 485 | __fs32 fs_magic; /* magic number */ | ||
| 486 | __u8 fs_space[1]; /* list of blocks for each rotation */ | ||
| 487 | }; | ||
| 488 | #endif/*struct ufs_super_block*/ | ||
| 489 | |||
| 490 | /* | ||
| 491 | * Preference for optimization. | ||
| 492 | */ | ||
| 493 | #define UFS_OPTTIME 0 /* minimize allocation time */ | ||
| 494 | #define UFS_OPTSPACE 1 /* minimize disk fragmentation */ | ||
| 495 | |||
| 496 | /* | ||
| 497 | * Rotational layout table format types | ||
| 498 | */ | ||
| 499 | #define UFS_42POSTBLFMT -1 /* 4.2BSD rotational table format */ | ||
| 500 | #define UFS_DYNAMICPOSTBLFMT 1 /* dynamic rotational table format */ | ||
| 501 | |||
| 502 | /* | ||
| 503 | * Convert cylinder group to base address of its global summary info. | ||
| 504 | */ | ||
| 505 | #define fs_cs(indx) s_csp[(indx)] | ||
| 506 | |||
| 507 | /* | ||
| 508 | * Cylinder group block for a file system. | ||
| 509 | * | ||
| 510 | * Writable fields in the cylinder group are protected by the associated | ||
| 511 | * super block lock fs->fs_lock. | ||
| 512 | */ | ||
| 513 | #define CG_MAGIC 0x090255 | ||
| 514 | #define ufs_cg_chkmagic(sb, ucg) \ | ||
| 515 | (fs32_to_cpu((sb), (ucg)->cg_magic) == CG_MAGIC) | ||
| 516 | /* | ||
| 517 | * Macros for access to old cylinder group array structures | ||
| 518 | */ | ||
| 519 | #define ufs_ocg_blktot(sb, ucg) fs32_to_cpu((sb), ((struct ufs_old_cylinder_group *)(ucg))->cg_btot) | ||
| 520 | #define ufs_ocg_blks(sb, ucg, cylno) fs32_to_cpu((sb), ((struct ufs_old_cylinder_group *)(ucg))->cg_b[cylno]) | ||
| 521 | #define ufs_ocg_inosused(sb, ucg) fs32_to_cpu((sb), ((struct ufs_old_cylinder_group *)(ucg))->cg_iused) | ||
| 522 | #define ufs_ocg_blksfree(sb, ucg) fs32_to_cpu((sb), ((struct ufs_old_cylinder_group *)(ucg))->cg_free) | ||
| 523 | #define ufs_ocg_chkmagic(sb, ucg) \ | ||
| 524 | (fs32_to_cpu((sb), ((struct ufs_old_cylinder_group *)(ucg))->cg_magic) == CG_MAGIC) | ||
| 525 | |||
| 526 | /* | ||
| 527 | * size of this structure is 172 B | ||
| 528 | */ | ||
| 529 | struct ufs_cylinder_group { | ||
| 530 | __fs32 cg_link; /* linked list of cyl groups */ | ||
| 531 | __fs32 cg_magic; /* magic number */ | ||
| 532 | __fs32 cg_time; /* time last written */ | ||
| 533 | __fs32 cg_cgx; /* we are the cgx'th cylinder group */ | ||
| 534 | __fs16 cg_ncyl; /* number of cyl's this cg */ | ||
| 535 | __fs16 cg_niblk; /* number of inode blocks this cg */ | ||
| 536 | __fs32 cg_ndblk; /* number of data blocks this cg */ | ||
| 537 | struct ufs_csum cg_cs; /* cylinder summary information */ | ||
| 538 | __fs32 cg_rotor; /* position of last used block */ | ||
| 539 | __fs32 cg_frotor; /* position of last used frag */ | ||
| 540 | __fs32 cg_irotor; /* position of last used inode */ | ||
| 541 | __fs32 cg_frsum[UFS_MAXFRAG]; /* counts of available frags */ | ||
| 542 | __fs32 cg_btotoff; /* (__u32) block totals per cylinder */ | ||
| 543 | __fs32 cg_boff; /* (short) free block positions */ | ||
| 544 | __fs32 cg_iusedoff; /* (char) used inode map */ | ||
| 545 | __fs32 cg_freeoff; /* (u_char) free block map */ | ||
| 546 | __fs32 cg_nextfreeoff; /* (u_char) next available space */ | ||
| 547 | union { | ||
| 548 | struct { | ||
| 549 | __fs32 cg_clustersumoff; /* (u_int32) counts of avail clusters */ | ||
| 550 | __fs32 cg_clusteroff; /* (u_int8) free cluster map */ | ||
| 551 | __fs32 cg_nclusterblks; /* number of clusters this cg */ | ||
| 552 | __fs32 cg_sparecon[13]; /* reserved for future use */ | ||
| 553 | } cg_44; | ||
| 554 | struct { | ||
| 555 | __fs32 cg_clustersumoff;/* (u_int32) counts of avail clusters */ | ||
| 556 | __fs32 cg_clusteroff; /* (u_int8) free cluster map */ | ||
| 557 | __fs32 cg_nclusterblks;/* number of clusters this cg */ | ||
| 558 | __fs32 cg_niblk; /* number of inode blocks this cg */ | ||
| 559 | __fs32 cg_initediblk; /* last initialized inode */ | ||
| 560 | __fs32 cg_sparecon32[3];/* reserved for future use */ | ||
| 561 | __fs64 cg_time; /* time last written */ | ||
| 562 | __fs64 cg_sparecon[3]; /* reserved for future use */ | ||
| 563 | } cg_u2; | ||
| 564 | __fs32 cg_sparecon[16]; /* reserved for future use */ | ||
| 565 | } cg_u; | ||
| 566 | __u8 cg_space[1]; /* space for cylinder group maps */ | ||
| 567 | /* actually longer */ | ||
| 568 | }; | ||
| 569 | |||
| 570 | /* Historic Cylinder group info */ | ||
| 571 | struct ufs_old_cylinder_group { | ||
| 572 | __fs32 cg_link; /* linked list of cyl groups */ | ||
| 573 | __fs32 cg_rlink; /* for incore cyl groups */ | ||
| 574 | __fs32 cg_time; /* time last written */ | ||
| 575 | __fs32 cg_cgx; /* we are the cgx'th cylinder group */ | ||
| 576 | __fs16 cg_ncyl; /* number of cyl's this cg */ | ||
| 577 | __fs16 cg_niblk; /* number of inode blocks this cg */ | ||
| 578 | __fs32 cg_ndblk; /* number of data blocks this cg */ | ||
| 579 | struct ufs_csum cg_cs; /* cylinder summary information */ | ||
| 580 | __fs32 cg_rotor; /* position of last used block */ | ||
| 581 | __fs32 cg_frotor; /* position of last used frag */ | ||
| 582 | __fs32 cg_irotor; /* position of last used inode */ | ||
| 583 | __fs32 cg_frsum[8]; /* counts of available frags */ | ||
| 584 | __fs32 cg_btot[32]; /* block totals per cylinder */ | ||
| 585 | __fs16 cg_b[32][8]; /* positions of free blocks */ | ||
| 586 | __u8 cg_iused[256]; /* used inode map */ | ||
| 587 | __fs32 cg_magic; /* magic number */ | ||
| 588 | __u8 cg_free[1]; /* free block map */ | ||
| 589 | /* actually longer */ | ||
| 590 | }; | ||
| 591 | |||
| 592 | /* | ||
| 593 | * structure of an on-disk inode | ||
| 594 | */ | ||
| 595 | struct ufs_inode { | ||
| 596 | __fs16 ui_mode; /* 0x0 */ | ||
| 597 | __fs16 ui_nlink; /* 0x2 */ | ||
| 598 | union { | ||
| 599 | struct { | ||
| 600 | __fs16 ui_suid; /* 0x4 */ | ||
| 601 | __fs16 ui_sgid; /* 0x6 */ | ||
| 602 | } oldids; | ||
| 603 | __fs32 ui_inumber; /* 0x4 lsf: inode number */ | ||
| 604 | __fs32 ui_author; /* 0x4 GNU HURD: author */ | ||
| 605 | } ui_u1; | ||
| 606 | __fs64 ui_size; /* 0x8 */ | ||
| 607 | struct ufs_timeval ui_atime; /* 0x10 access */ | ||
| 608 | struct ufs_timeval ui_mtime; /* 0x18 modification */ | ||
| 609 | struct ufs_timeval ui_ctime; /* 0x20 creation */ | ||
| 610 | union { | ||
| 611 | struct { | ||
| 612 | __fs32 ui_db[UFS_NDADDR];/* 0x28 data blocks */ | ||
| 613 | __fs32 ui_ib[UFS_NINDIR];/* 0x58 indirect blocks */ | ||
| 614 | } ui_addr; | ||
| 615 | __u8 ui_symlink[4*(UFS_NDADDR+UFS_NINDIR)];/* 0x28 fast symlink */ | ||
| 616 | } ui_u2; | ||
| 617 | __fs32 ui_flags; /* 0x64 immutable, append-only... */ | ||
| 618 | __fs32 ui_blocks; /* 0x68 blocks in use */ | ||
| 619 | __fs32 ui_gen; /* 0x6c like ext2 i_version, for NFS support */ | ||
| 620 | union { | ||
| 621 | struct { | ||
| 622 | __fs32 ui_shadow; /* 0x70 shadow inode with security data */ | ||
| 623 | __fs32 ui_uid; /* 0x74 long EFT version of uid */ | ||
| 624 | __fs32 ui_gid; /* 0x78 long EFT version of gid */ | ||
| 625 | __fs32 ui_oeftflag; /* 0x7c reserved */ | ||
| 626 | } ui_sun; | ||
| 627 | struct { | ||
| 628 | __fs32 ui_uid; /* 0x70 File owner */ | ||
| 629 | __fs32 ui_gid; /* 0x74 File group */ | ||
| 630 | __fs32 ui_spare[2]; /* 0x78 reserved */ | ||
| 631 | } ui_44; | ||
| 632 | struct { | ||
| 633 | __fs32 ui_uid; /* 0x70 */ | ||
| 634 | __fs32 ui_gid; /* 0x74 */ | ||
| 635 | __fs16 ui_modeh; /* 0x78 mode high bits */ | ||
| 636 | __fs16 ui_spare; /* 0x7A unused */ | ||
| 637 | __fs32 ui_trans; /* 0x7c filesystem translator */ | ||
| 638 | } ui_hurd; | ||
| 639 | } ui_u3; | ||
| 640 | }; | ||
| 641 | |||
| 642 | #define UFS_NXADDR 2 /* External addresses in inode. */ | ||
| 643 | struct ufs2_inode { | ||
| 644 | __fs16 ui_mode; /* 0: IFMT, permissions; see below. */ | ||
| 645 | __fs16 ui_nlink; /* 2: File link count. */ | ||
| 646 | __fs32 ui_uid; /* 4: File owner. */ | ||
| 647 | __fs32 ui_gid; /* 8: File group. */ | ||
| 648 | __fs32 ui_blksize; /* 12: Inode blocksize. */ | ||
| 649 | __fs64 ui_size; /* 16: File byte count. */ | ||
| 650 | __fs64 ui_blocks; /* 24: Bytes actually held. */ | ||
| 651 | __fs64 ui_atime; /* 32: Last access time. */ | ||
| 652 | __fs64 ui_mtime; /* 40: Last modified time. */ | ||
| 653 | __fs64 ui_ctime; /* 48: Last inode change time. */ | ||
| 654 | __fs64 ui_birthtime; /* 56: Inode creation time. */ | ||
| 655 | __fs32 ui_mtimensec; /* 64: Last modified time. */ | ||
| 656 | __fs32 ui_atimensec; /* 68: Last access time. */ | ||
| 657 | __fs32 ui_ctimensec; /* 72: Last inode change time. */ | ||
| 658 | __fs32 ui_birthnsec; /* 76: Inode creation time. */ | ||
| 659 | __fs32 ui_gen; /* 80: Generation number. */ | ||
| 660 | __fs32 ui_kernflags; /* 84: Kernel flags. */ | ||
| 661 | __fs32 ui_flags; /* 88: Status flags (chflags). */ | ||
| 662 | __fs32 ui_extsize; /* 92: External attributes block. */ | ||
| 663 | __fs64 ui_extb[UFS_NXADDR];/* 96: External attributes block. */ | ||
| 664 | union { | ||
| 665 | struct { | ||
| 666 | __fs64 ui_db[UFS_NDADDR]; /* 112: Direct disk blocks. */ | ||
| 667 | __fs64 ui_ib[UFS_NINDIR];/* 208: Indirect disk blocks.*/ | ||
| 668 | } ui_addr; | ||
| 669 | __u8 ui_symlink[2*4*(UFS_NDADDR+UFS_NINDIR)];/* 0x28 fast symlink */ | ||
| 670 | } ui_u2; | ||
| 671 | __fs64 ui_spare[3]; /* 232: Reserved; currently unused */ | ||
| 672 | }; | ||
| 673 | |||
| 674 | |||
| 675 | /* FreeBSD has these in sys/stat.h */ | ||
| 676 | /* ui_flags that can be set by a file owner */ | ||
| 677 | #define UFS_UF_SETTABLE 0x0000ffff | ||
| 678 | #define UFS_UF_NODUMP 0x00000001 /* do not dump */ | ||
| 679 | #define UFS_UF_IMMUTABLE 0x00000002 /* immutable (can't "change") */ | ||
| 680 | #define UFS_UF_APPEND 0x00000004 /* append-only */ | ||
| 681 | #define UFS_UF_OPAQUE 0x00000008 /* directory is opaque (unionfs) */ | ||
| 682 | #define UFS_UF_NOUNLINK 0x00000010 /* can't be removed or renamed */ | ||
| 683 | /* ui_flags that only root can set */ | ||
| 684 | #define UFS_SF_SETTABLE 0xffff0000 | ||
| 685 | #define UFS_SF_ARCHIVED 0x00010000 /* archived */ | ||
| 686 | #define UFS_SF_IMMUTABLE 0x00020000 /* immutable (can't "change") */ | ||
| 687 | #define UFS_SF_APPEND 0x00040000 /* append-only */ | ||
| 688 | #define UFS_SF_NOUNLINK 0x00100000 /* can't be removed or renamed */ | ||
| 689 | |||
| 690 | /* | ||
| 691 | * This structure is used for reading disk structures larger | ||
| 692 | * than the size of fragment. | ||
| 693 | */ | ||
| 694 | struct ufs_buffer_head { | ||
| 695 | __u64 fragment; /* first fragment */ | ||
| 696 | __u64 count; /* number of fragments */ | ||
| 697 | struct buffer_head * bh[UFS_MAXFRAG]; /* buffers */ | ||
| 698 | }; | ||
| 699 | |||
| 700 | struct ufs_cg_private_info { | ||
| 701 | struct ufs_buffer_head c_ubh; | ||
| 702 | __u32 c_cgx; /* number of cylidner group */ | ||
| 703 | __u16 c_ncyl; /* number of cyl's this cg */ | ||
| 704 | __u16 c_niblk; /* number of inode blocks this cg */ | ||
| 705 | __u32 c_ndblk; /* number of data blocks this cg */ | ||
| 706 | __u32 c_rotor; /* position of last used block */ | ||
| 707 | __u32 c_frotor; /* position of last used frag */ | ||
| 708 | __u32 c_irotor; /* position of last used inode */ | ||
| 709 | __u32 c_btotoff; /* (__u32) block totals per cylinder */ | ||
| 710 | __u32 c_boff; /* (short) free block positions */ | ||
| 711 | __u32 c_iusedoff; /* (char) used inode map */ | ||
| 712 | __u32 c_freeoff; /* (u_char) free block map */ | ||
| 713 | __u32 c_nextfreeoff; /* (u_char) next available space */ | ||
| 714 | __u32 c_clustersumoff;/* (u_int32) counts of avail clusters */ | ||
| 715 | __u32 c_clusteroff; /* (u_int8) free cluster map */ | ||
| 716 | __u32 c_nclusterblks; /* number of clusters this cg */ | ||
| 717 | }; | ||
| 718 | |||
| 719 | |||
| 720 | struct ufs_sb_private_info { | ||
| 721 | struct ufs_buffer_head s_ubh; /* buffer containing super block */ | ||
| 722 | struct ufs_csum_core cs_total; | ||
| 723 | __u32 s_sblkno; /* offset of super-blocks in filesys */ | ||
| 724 | __u32 s_cblkno; /* offset of cg-block in filesys */ | ||
| 725 | __u32 s_iblkno; /* offset of inode-blocks in filesys */ | ||
| 726 | __u32 s_dblkno; /* offset of first data after cg */ | ||
| 727 | __u32 s_cgoffset; /* cylinder group offset in cylinder */ | ||
| 728 | __u32 s_cgmask; /* used to calc mod fs_ntrak */ | ||
| 729 | __u32 s_size; /* number of blocks (fragments) in fs */ | ||
| 730 | __u32 s_dsize; /* number of data blocks in fs */ | ||
| 731 | __u64 s_u2_size; /* ufs2: number of blocks (fragments) in fs */ | ||
| 732 | __u64 s_u2_dsize; /*ufs2: number of data blocks in fs */ | ||
| 733 | __u32 s_ncg; /* number of cylinder groups */ | ||
| 734 | __u32 s_bsize; /* size of basic blocks */ | ||
| 735 | __u32 s_fsize; /* size of fragments */ | ||
| 736 | __u32 s_fpb; /* fragments per block */ | ||
| 737 | __u32 s_minfree; /* minimum percentage of free blocks */ | ||
| 738 | __u32 s_bmask; /* `blkoff'' calc of blk offsets */ | ||
| 739 | __u32 s_fmask; /* s_fsize mask */ | ||
| 740 | __u32 s_bshift; /* `lblkno'' calc of logical blkno */ | ||
| 741 | __u32 s_fshift; /* s_fsize shift */ | ||
| 742 | __u32 s_fpbshift; /* fragments per block shift */ | ||
| 743 | __u32 s_fsbtodb; /* fsbtodb and dbtofsb shift constant */ | ||
| 744 | __u32 s_sbsize; /* actual size of super block */ | ||
| 745 | __u32 s_csmask; /* csum block offset */ | ||
| 746 | __u32 s_csshift; /* csum block number */ | ||
| 747 | __u32 s_nindir; /* value of NINDIR */ | ||
| 748 | __u32 s_inopb; /* value of INOPB */ | ||
| 749 | __u32 s_nspf; /* value of NSPF */ | ||
| 750 | __u32 s_npsect; /* # sectors/track including spares */ | ||
| 751 | __u32 s_interleave; /* hardware sector interleave */ | ||
| 752 | __u32 s_trackskew; /* sector 0 skew, per track */ | ||
| 753 | __u64 s_csaddr; /* blk addr of cyl grp summary area */ | ||
| 754 | __u32 s_cssize; /* size of cyl grp summary area */ | ||
| 755 | __u32 s_cgsize; /* cylinder group size */ | ||
| 756 | __u32 s_ntrak; /* tracks per cylinder */ | ||
| 757 | __u32 s_nsect; /* sectors per track */ | ||
| 758 | __u32 s_spc; /* sectors per cylinder */ | ||
| 759 | __u32 s_ipg; /* inodes per cylinder group */ | ||
| 760 | __u32 s_fpg; /* fragments per group */ | ||
| 761 | __u32 s_cpc; /* cyl per cycle in postbl */ | ||
| 762 | __s32 s_contigsumsize;/* size of cluster summary array, 44bsd */ | ||
| 763 | __s64 s_qbmask; /* ~usb_bmask */ | ||
| 764 | __s64 s_qfmask; /* ~usb_fmask */ | ||
| 765 | __s32 s_postblformat; /* format of positional layout tables */ | ||
| 766 | __s32 s_nrpos; /* number of rotational positions */ | ||
| 767 | __s32 s_postbloff; /* (__s16) rotation block list head */ | ||
| 768 | __s32 s_rotbloff; /* (__u8) blocks for each rotation */ | ||
| 769 | |||
| 770 | __u32 s_fpbmask; /* fragments per block mask */ | ||
| 771 | __u32 s_apb; /* address per block */ | ||
| 772 | __u32 s_2apb; /* address per block^2 */ | ||
| 773 | __u32 s_3apb; /* address per block^3 */ | ||
| 774 | __u32 s_apbmask; /* address per block mask */ | ||
| 775 | __u32 s_apbshift; /* address per block shift */ | ||
| 776 | __u32 s_2apbshift; /* address per block shift * 2 */ | ||
| 777 | __u32 s_3apbshift; /* address per block shift * 3 */ | ||
| 778 | __u32 s_nspfshift; /* number of sector per fragment shift */ | ||
| 779 | __u32 s_nspb; /* number of sector per block */ | ||
| 780 | __u32 s_inopf; /* inodes per fragment */ | ||
| 781 | __u32 s_sbbase; /* offset of NeXTstep superblock */ | ||
| 782 | __u32 s_bpf; /* bits per fragment */ | ||
| 783 | __u32 s_bpfshift; /* bits per fragment shift*/ | ||
| 784 | __u32 s_bpfmask; /* bits per fragment mask */ | ||
| 785 | |||
| 786 | __u32 s_maxsymlinklen;/* upper limit on fast symlinks' size */ | ||
| 787 | __s32 fs_magic; /* filesystem magic */ | ||
| 788 | unsigned int s_dirblksize; | ||
| 789 | }; | ||
| 790 | |||
| 791 | /* | ||
| 792 | * Sizes of this structures are: | ||
| 793 | * ufs_super_block_first 512 | ||
| 794 | * ufs_super_block_second 512 | ||
| 795 | * ufs_super_block_third 356 | ||
| 796 | */ | ||
| 797 | struct ufs_super_block_first { | ||
| 798 | union { | ||
| 799 | struct { | ||
| 800 | __fs32 fs_link; /* UNUSED */ | ||
| 801 | } fs_42; | ||
| 802 | struct { | ||
| 803 | __fs32 fs_state; /* file system state flag */ | ||
| 804 | } fs_sun; | ||
| 805 | } fs_u0; | ||
| 806 | __fs32 fs_rlink; | ||
| 807 | __fs32 fs_sblkno; | ||
| 808 | __fs32 fs_cblkno; | ||
| 809 | __fs32 fs_iblkno; | ||
| 810 | __fs32 fs_dblkno; | ||
| 811 | __fs32 fs_cgoffset; | ||
| 812 | __fs32 fs_cgmask; | ||
| 813 | __fs32 fs_time; | ||
| 814 | __fs32 fs_size; | ||
| 815 | __fs32 fs_dsize; | ||
| 816 | __fs32 fs_ncg; | ||
| 817 | __fs32 fs_bsize; | ||
| 818 | __fs32 fs_fsize; | ||
| 819 | __fs32 fs_frag; | ||
| 820 | __fs32 fs_minfree; | ||
| 821 | __fs32 fs_rotdelay; | ||
| 822 | __fs32 fs_rps; | ||
| 823 | __fs32 fs_bmask; | ||
| 824 | __fs32 fs_fmask; | ||
| 825 | __fs32 fs_bshift; | ||
| 826 | __fs32 fs_fshift; | ||
| 827 | __fs32 fs_maxcontig; | ||
| 828 | __fs32 fs_maxbpg; | ||
| 829 | __fs32 fs_fragshift; | ||
| 830 | __fs32 fs_fsbtodb; | ||
| 831 | __fs32 fs_sbsize; | ||
| 832 | __fs32 fs_csmask; | ||
| 833 | __fs32 fs_csshift; | ||
| 834 | __fs32 fs_nindir; | ||
| 835 | __fs32 fs_inopb; | ||
| 836 | __fs32 fs_nspf; | ||
| 837 | __fs32 fs_optim; | ||
| 838 | union { | ||
| 839 | struct { | ||
| 840 | __fs32 fs_npsect; | ||
| 841 | } fs_sun; | ||
| 842 | struct { | ||
| 843 | __fs32 fs_state; | ||
| 844 | } fs_sunx86; | ||
| 845 | } fs_u1; | ||
| 846 | __fs32 fs_interleave; | ||
| 847 | __fs32 fs_trackskew; | ||
| 848 | __fs32 fs_id[2]; | ||
| 849 | __fs32 fs_csaddr; | ||
| 850 | __fs32 fs_cssize; | ||
| 851 | __fs32 fs_cgsize; | ||
| 852 | __fs32 fs_ntrak; | ||
| 853 | __fs32 fs_nsect; | ||
| 854 | __fs32 fs_spc; | ||
| 855 | __fs32 fs_ncyl; | ||
| 856 | __fs32 fs_cpg; | ||
| 857 | __fs32 fs_ipg; | ||
| 858 | __fs32 fs_fpg; | ||
| 859 | struct ufs_csum fs_cstotal; | ||
| 860 | __s8 fs_fmod; | ||
| 861 | __s8 fs_clean; | ||
| 862 | __s8 fs_ronly; | ||
| 863 | __s8 fs_flags; | ||
| 864 | __s8 fs_fsmnt[UFS_MAXMNTLEN - 212]; | ||
| 865 | |||
| 866 | }; | ||
| 867 | |||
| 868 | struct ufs_super_block_second { | ||
| 869 | union { | ||
| 870 | struct { | ||
| 871 | __s8 fs_fsmnt[212]; | ||
| 872 | __fs32 fs_cgrotor; | ||
| 873 | __fs32 fs_csp[UFS_MAXCSBUFS]; | ||
| 874 | __fs32 fs_maxcluster; | ||
| 875 | __fs32 fs_cpc; | ||
| 876 | __fs16 fs_opostbl[82]; | ||
| 877 | } fs_u1; | ||
| 878 | struct { | ||
| 879 | __s8 fs_fsmnt[UFS2_MAXMNTLEN - UFS_MAXMNTLEN + 212]; | ||
| 880 | __u8 fs_volname[UFS2_MAXVOLLEN]; | ||
| 881 | __fs64 fs_swuid; | ||
| 882 | __fs32 fs_pad; | ||
| 883 | __fs32 fs_cgrotor; | ||
| 884 | __fs32 fs_ocsp[UFS2_NOCSPTRS]; | ||
| 885 | __fs32 fs_contigdirs; | ||
| 886 | __fs32 fs_csp; | ||
| 887 | __fs32 fs_maxcluster; | ||
| 888 | __fs32 fs_active; | ||
| 889 | __fs32 fs_old_cpc; | ||
| 890 | __fs32 fs_maxbsize; | ||
| 891 | __fs64 fs_sparecon64[17]; | ||
| 892 | __fs64 fs_sblockloc; | ||
| 893 | __fs64 cs_ndir; | ||
| 894 | __fs64 cs_nbfree; | ||
| 895 | } fs_u2; | ||
| 896 | } fs_un; | ||
| 897 | }; | ||
| 898 | |||
| 899 | struct ufs_super_block_third { | ||
| 900 | union { | ||
| 901 | struct { | ||
| 902 | __fs16 fs_opostbl[46]; | ||
| 903 | } fs_u1; | ||
| 904 | struct { | ||
| 905 | __fs64 cs_nifree; /* number of free inodes */ | ||
| 906 | __fs64 cs_nffree; /* number of free frags */ | ||
| 907 | __fs64 cs_numclusters; /* number of free clusters */ | ||
| 908 | __fs64 cs_spare[3]; /* future expansion */ | ||
| 909 | struct ufs_timeval fs_time; /* last time written */ | ||
| 910 | __fs64 fs_size; /* number of blocks in fs */ | ||
| 911 | __fs64 fs_dsize; /* number of data blocks in fs */ | ||
| 912 | __fs64 fs_csaddr; /* blk addr of cyl grp summary area */ | ||
| 913 | __fs64 fs_pendingblocks;/* blocks in process of being freed */ | ||
| 914 | __fs32 fs_pendinginodes;/*inodes in process of being freed */ | ||
| 915 | } __attribute__ ((packed)) fs_u2; | ||
| 916 | } fs_un1; | ||
| 917 | union { | ||
| 918 | struct { | ||
| 919 | __fs32 fs_sparecon[53];/* reserved for future constants */ | ||
| 920 | __fs32 fs_reclaim; | ||
| 921 | __fs32 fs_sparecon2[1]; | ||
| 922 | __fs32 fs_state; /* file system state time stamp */ | ||
| 923 | __fs32 fs_qbmask[2]; /* ~usb_bmask */ | ||
| 924 | __fs32 fs_qfmask[2]; /* ~usb_fmask */ | ||
| 925 | } fs_sun; | ||
| 926 | struct { | ||
| 927 | __fs32 fs_sparecon[53];/* reserved for future constants */ | ||
| 928 | __fs32 fs_reclaim; | ||
| 929 | __fs32 fs_sparecon2[1]; | ||
| 930 | __fs32 fs_npsect; /* # sectors/track including spares */ | ||
| 931 | __fs32 fs_qbmask[2]; /* ~usb_bmask */ | ||
| 932 | __fs32 fs_qfmask[2]; /* ~usb_fmask */ | ||
| 933 | } fs_sunx86; | ||
| 934 | struct { | ||
| 935 | __fs32 fs_sparecon[50];/* reserved for future constants */ | ||
| 936 | __fs32 fs_contigsumsize;/* size of cluster summary array */ | ||
| 937 | __fs32 fs_maxsymlinklen;/* max length of an internal symlink */ | ||
| 938 | __fs32 fs_inodefmt; /* format of on-disk inodes */ | ||
| 939 | __fs32 fs_maxfilesize[2]; /* max representable file size */ | ||
| 940 | __fs32 fs_qbmask[2]; /* ~usb_bmask */ | ||
| 941 | __fs32 fs_qfmask[2]; /* ~usb_fmask */ | ||
| 942 | __fs32 fs_state; /* file system state time stamp */ | ||
| 943 | } fs_44; | ||
| 944 | } fs_un2; | ||
| 945 | __fs32 fs_postblformat; | ||
| 946 | __fs32 fs_nrpos; | ||
| 947 | __fs32 fs_postbloff; | ||
| 948 | __fs32 fs_rotbloff; | ||
| 949 | __fs32 fs_magic; | ||
| 950 | __u8 fs_space[1]; | ||
| 951 | }; | ||
| 952 | |||
| 953 | #endif /* __LINUX_UFS_FS_H */ | ||
diff --git a/include/linux/utsname.h b/include/linux/utsname.h index 923db99175f2..11232676bfff 100644 --- a/include/linux/utsname.h +++ b/include/linux/utsname.h | |||
| @@ -35,6 +35,7 @@ struct new_utsname { | |||
| 35 | #include <linux/sched.h> | 35 | #include <linux/sched.h> |
| 36 | #include <linux/kref.h> | 36 | #include <linux/kref.h> |
| 37 | #include <linux/nsproxy.h> | 37 | #include <linux/nsproxy.h> |
| 38 | #include <linux/err.h> | ||
| 38 | #include <asm/atomic.h> | 39 | #include <asm/atomic.h> |
| 39 | 40 | ||
| 40 | struct uts_namespace { | 41 | struct uts_namespace { |
| @@ -43,6 +44,7 @@ struct uts_namespace { | |||
| 43 | }; | 44 | }; |
| 44 | extern struct uts_namespace init_uts_ns; | 45 | extern struct uts_namespace init_uts_ns; |
| 45 | 46 | ||
| 47 | #ifdef CONFIG_UTS_NS | ||
| 46 | static inline void get_uts_ns(struct uts_namespace *ns) | 48 | static inline void get_uts_ns(struct uts_namespace *ns) |
| 47 | { | 49 | { |
| 48 | kref_get(&ns->kref); | 50 | kref_get(&ns->kref); |
| @@ -56,6 +58,25 @@ static inline void put_uts_ns(struct uts_namespace *ns) | |||
| 56 | { | 58 | { |
| 57 | kref_put(&ns->kref, free_uts_ns); | 59 | kref_put(&ns->kref, free_uts_ns); |
| 58 | } | 60 | } |
| 61 | #else | ||
| 62 | static inline void get_uts_ns(struct uts_namespace *ns) | ||
| 63 | { | ||
| 64 | } | ||
| 65 | |||
| 66 | static inline void put_uts_ns(struct uts_namespace *ns) | ||
| 67 | { | ||
| 68 | } | ||
| 69 | |||
| 70 | static inline struct uts_namespace *copy_utsname(unsigned long flags, | ||
| 71 | struct uts_namespace *ns) | ||
| 72 | { | ||
| 73 | if (flags & CLONE_NEWUTS) | ||
| 74 | return ERR_PTR(-EINVAL); | ||
| 75 | |||
| 76 | return ns; | ||
| 77 | } | ||
| 78 | #endif | ||
| 79 | |||
| 59 | static inline struct new_utsname *utsname(void) | 80 | static inline struct new_utsname *utsname(void) |
| 60 | { | 81 | { |
| 61 | return ¤t->nsproxy->uts_ns->name; | 82 | return ¤t->nsproxy->uts_ns->name; |
diff --git a/include/net/ip6_fib.h b/include/net/ip6_fib.h index d8d85b13364d..953d6040ff50 100644 --- a/include/net/ip6_fib.h +++ b/include/net/ip6_fib.h | |||
| @@ -150,19 +150,6 @@ struct rt6_statistics { | |||
| 150 | * | 150 | * |
| 151 | */ | 151 | */ |
| 152 | 152 | ||
| 153 | #define RTPRI_FIREWALL 8 /* Firewall control information */ | ||
| 154 | #define RTPRI_FLOW 16 /* Flow based forwarding rules */ | ||
| 155 | #define RTPRI_KERN_CTL 32 /* Kernel control routes */ | ||
| 156 | |||
| 157 | #define RTPRI_USER_MIN 256 /* Mimimum user priority */ | ||
| 158 | #define RTPRI_USER_MAX 1024 /* Maximum user priority */ | ||
| 159 | |||
| 160 | #define RTPRI_KERN_DFLT 4096 /* Kernel default routes */ | ||
| 161 | |||
| 162 | #define MAX_FLOW_BACKTRACE 32 | ||
| 163 | |||
| 164 | |||
| 165 | typedef void (*f_pnode)(struct fib6_node *fn, void *); | ||
| 166 | 153 | ||
| 167 | struct fib6_table { | 154 | struct fib6_table { |
| 168 | struct hlist_node tb6_hlist; | 155 | struct hlist_node tb6_hlist; |
diff --git a/include/net/ip6_route.h b/include/net/ip6_route.h index faac0eee1ef3..f99e4f0f568f 100644 --- a/include/net/ip6_route.h +++ b/include/net/ip6_route.h | |||
| @@ -1,11 +1,9 @@ | |||
| 1 | #ifndef _NET_IP6_ROUTE_H | 1 | #ifndef _NET_IP6_ROUTE_H |
| 2 | #define _NET_IP6_ROUTE_H | 2 | #define _NET_IP6_ROUTE_H |
| 3 | 3 | ||
| 4 | #define IP6_RT_PRIO_FW 16 | ||
| 5 | #define IP6_RT_PRIO_USER 1024 | 4 | #define IP6_RT_PRIO_USER 1024 |
| 6 | #define IP6_RT_PRIO_ADDRCONF 256 | 5 | #define IP6_RT_PRIO_ADDRCONF 256 |
| 7 | #define IP6_RT_PRIO_KERN 512 | 6 | #define IP6_RT_PRIO_KERN 512 |
| 8 | #define IP6_RT_FLOW_MASK 0x00ff | ||
| 9 | 7 | ||
| 10 | struct route_info { | 8 | struct route_info { |
| 11 | __u8 type; | 9 | __u8 type; |
diff --git a/include/net/netfilter/nf_conntrack_extend.h b/include/net/netfilter/nf_conntrack_extend.h index 73b5711faf32..49aac6323fbe 100644 --- a/include/net/netfilter/nf_conntrack_extend.h +++ b/include/net/netfilter/nf_conntrack_extend.h | |||
| @@ -67,7 +67,7 @@ struct nf_ct_ext_type | |||
| 67 | void (*destroy)(struct nf_conn *ct); | 67 | void (*destroy)(struct nf_conn *ct); |
| 68 | /* Called when realloacted (can be NULL). | 68 | /* Called when realloacted (can be NULL). |
| 69 | Contents has already been moved. */ | 69 | Contents has already been moved. */ |
| 70 | void (*move)(struct nf_conn *ct, void *old); | 70 | void (*move)(void *new, void *old); |
| 71 | 71 | ||
| 72 | enum nf_ct_ext_id id; | 72 | enum nf_ct_ext_id id; |
| 73 | 73 | ||
diff --git a/include/net/tipc/tipc_msg.h b/include/net/tipc/tipc_msg.h index fb42eb7a86a5..2e159a812f83 100644 --- a/include/net/tipc/tipc_msg.h +++ b/include/net/tipc/tipc_msg.h | |||
| @@ -130,11 +130,6 @@ static inline u32 msg_type(struct tipc_msg *m) | |||
| 130 | return msg_bits(m, 1, 29, 0x7); | 130 | return msg_bits(m, 1, 29, 0x7); |
| 131 | } | 131 | } |
| 132 | 132 | ||
| 133 | static inline u32 msg_direct(struct tipc_msg *m) | ||
| 134 | { | ||
| 135 | return (msg_type(m) == TIPC_DIRECT_MSG); | ||
| 136 | } | ||
| 137 | |||
| 138 | static inline u32 msg_named(struct tipc_msg *m) | 133 | static inline u32 msg_named(struct tipc_msg *m) |
| 139 | { | 134 | { |
| 140 | return (msg_type(m) == TIPC_NAMED_MSG); | 135 | return (msg_type(m) == TIPC_NAMED_MSG); |
| @@ -207,17 +202,6 @@ static inline u32 msg_nameupper(struct tipc_msg *m) | |||
| 207 | return msg_word(m, 10); | 202 | return msg_word(m, 10); |
| 208 | } | 203 | } |
| 209 | 204 | ||
| 210 | static inline char *msg_options(struct tipc_msg *m, u32 *len) | ||
| 211 | { | ||
| 212 | u32 pos = msg_bits(m, 1, 16, 0x7); | ||
| 213 | |||
| 214 | if (!pos) | ||
| 215 | return 0; | ||
| 216 | pos = (pos * 4) + 28; | ||
| 217 | *len = msg_hdr_sz(m) - pos; | ||
| 218 | return (char *)&m->hdr[pos/4]; | ||
| 219 | } | ||
| 220 | |||
| 221 | #endif | 205 | #endif |
| 222 | 206 | ||
| 223 | #endif | 207 | #endif |
diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h index cfbd38fe2998..701e7b40560a 100644 --- a/include/rdma/ib_verbs.h +++ b/include/rdma/ib_verbs.h | |||
| @@ -95,7 +95,15 @@ enum ib_device_cap_flags { | |||
| 95 | IB_DEVICE_N_NOTIFY_CQ = (1<<14), | 95 | IB_DEVICE_N_NOTIFY_CQ = (1<<14), |
| 96 | IB_DEVICE_ZERO_STAG = (1<<15), | 96 | IB_DEVICE_ZERO_STAG = (1<<15), |
| 97 | IB_DEVICE_SEND_W_INV = (1<<16), | 97 | IB_DEVICE_SEND_W_INV = (1<<16), |
| 98 | IB_DEVICE_MEM_WINDOW = (1<<17) | 98 | IB_DEVICE_MEM_WINDOW = (1<<17), |
| 99 | /* | ||
| 100 | * Devices should set IB_DEVICE_UD_IP_SUM if they support | ||
| 101 | * insertion of UDP and TCP checksum on outgoing UD IPoIB | ||
| 102 | * messages and can verify the validity of checksum for | ||
| 103 | * incoming messages. Setting this flag implies that the | ||
| 104 | * IPoIB driver may set NETIF_F_IP_CSUM for datagram mode. | ||
| 105 | */ | ||
| 106 | IB_DEVICE_UD_IP_CSUM = (1<<18), | ||
| 99 | }; | 107 | }; |
| 100 | 108 | ||
| 101 | enum ib_atomic_cap { | 109 | enum ib_atomic_cap { |
| @@ -431,6 +439,7 @@ struct ib_wc { | |||
| 431 | u8 sl; | 439 | u8 sl; |
| 432 | u8 dlid_path_bits; | 440 | u8 dlid_path_bits; |
| 433 | u8 port_num; /* valid only for DR SMPs on switches */ | 441 | u8 port_num; /* valid only for DR SMPs on switches */ |
| 442 | int csum_ok; | ||
| 434 | }; | 443 | }; |
| 435 | 444 | ||
| 436 | enum ib_cq_notify_flags { | 445 | enum ib_cq_notify_flags { |
| @@ -615,7 +624,8 @@ enum ib_send_flags { | |||
| 615 | IB_SEND_FENCE = 1, | 624 | IB_SEND_FENCE = 1, |
| 616 | IB_SEND_SIGNALED = (1<<1), | 625 | IB_SEND_SIGNALED = (1<<1), |
| 617 | IB_SEND_SOLICITED = (1<<2), | 626 | IB_SEND_SOLICITED = (1<<2), |
| 618 | IB_SEND_INLINE = (1<<3) | 627 | IB_SEND_INLINE = (1<<3), |
| 628 | IB_SEND_IP_CSUM = (1<<4) | ||
| 619 | }; | 629 | }; |
| 620 | 630 | ||
| 621 | struct ib_sge { | 631 | struct ib_sge { |
| @@ -890,8 +900,6 @@ struct ib_device { | |||
| 890 | int *pkey_tbl_len; | 900 | int *pkey_tbl_len; |
| 891 | int *gid_tbl_len; | 901 | int *gid_tbl_len; |
| 892 | 902 | ||
| 893 | u32 flags; | ||
| 894 | |||
| 895 | int num_comp_vectors; | 903 | int num_comp_vectors; |
| 896 | 904 | ||
| 897 | struct iw_cm_verbs *iwcm; | 905 | struct iw_cm_verbs *iwcm; |