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-rw-r--r--include/asm-sh/bugs.h2
-rw-r--r--include/asm-sh/cpu-sh4/freq.h2
-rw-r--r--include/asm-sh/cpu-sh4/timer.h57
-rw-r--r--include/asm-sh/processor.h2
4 files changed, 37 insertions, 26 deletions
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index efc8fd3e1fad..aeee8da9c54f 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -35,7 +35,7 @@ static void __init check_bugs(void)
35 case CPU_SH7750 ... CPU_SH4_501: 35 case CPU_SH7750 ... CPU_SH4_501:
36 *p++ = '4'; 36 *p++ = '4';
37 break; 37 break;
38 case CPU_SH7770 ... CPU_SH7785: 38 case CPU_SH7770 ... CPU_SHX3:
39 *p++ = '4'; 39 *p++ = '4';
40 *p++ = 'a'; 40 *p++ = 'a';
41 break; 41 break;
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
index 39f41fcd509d..026025b51cea 100644
--- a/include/asm-sh/cpu-sh4/freq.h
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -22,6 +22,8 @@
22#define FRQCR0 0xffc80000 22#define FRQCR0 0xffc80000
23#define FRQCR1 0xffc80004 23#define FRQCR1 0xffc80004
24#define FRQMR1 0xffc80014 24#define FRQMR1 0xffc80014
25#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
26#define FRQCR 0xffc00014
25#else 27#else
26#define FRQCR 0xffc00000 28#define FRQCR 0xffc00000
27#define FRQCR_PSTBY 0x0200 29#define FRQCR_PSTBY 0x0200
diff --git a/include/asm-sh/cpu-sh4/timer.h b/include/asm-sh/cpu-sh4/timer.h
index 8a4af126c890..d1e796b96888 100644
--- a/include/asm-sh/cpu-sh4/timer.h
+++ b/include/asm-sh/cpu-sh4/timer.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * include/asm-sh/cpu-sh4/timer.h 2 * include/asm-sh/cpu-sh4/timer.h
3 * 3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc. 4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -16,36 +16,45 @@
16 * SH7750S/SH7750R 16 * SH7750S/SH7750R
17 * SH7751/SH7751R 17 * SH7751/SH7751R
18 * SH7760 18 * SH7760
19 * SH-X3
19 * --------------------------------------------------------------------------- 20 * ---------------------------------------------------------------------------
20 */ 21 */
21 22#ifdef CONFIG_CPU_SUBTYPE_SHX3
22#if !defined(CONFIG_CPU_SUBTYPE_SH7760) 23#define TMU_012_BASE 0xffc10000
23#define TMU_TOCR 0xffd80000 /* Byte access */ 24#define TMU_345_BASE 0xffc20000
25#else
26#define TMU_012_BASE 0xffd80000
27#define TMU_345_BASE 0xfe100000
24#endif 28#endif
25#define TMU_TSTR 0xffd80004 /* Byte access */
26 29
27#define TMU0_TCOR 0xffd80008 /* Long access */ 30#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
28#define TMU0_TCNT 0xffd8000c /* Long access */
29#define TMU0_TCR 0xffd80010 /* Word access */
30 31
31#define TMU1_TCOR 0xffd80014 /* Long access */ 32#define TMU_012_TSTR (TMU_012_BASE + 0x04)
32#define TMU1_TCNT 0xffd80018 /* Long access */ 33#define TMU_345_TSTR (TMU_345_BASE + 0x04)
33#define TMU1_TCR 0xffd8001c /* Word access */
34 34
35#define TMU2_TCOR 0xffd80020 /* Long access */ 35#define TMU0_TCOR (TMU_012_BASE + 0x08)
36#define TMU2_TCNT 0xffd80024 /* Long access */ 36#define TMU0_TCNT (TMU_012_BASE + 0x0c)
37#define TMU2_TCR 0xffd80028 /* Word access */ 37#define TMU0_TCR (TMU_012_BASE + 0x10)
38#define TMU2_TCPR 0xffd8002c /* Long access */
39 38
40#if !defined(CONFIG_CPU_SUBTYPE_SH7760) 39#define TMU1_TCOR (TMU_012_BASE + 0x14)
41#define TMU3_TCOR 0xfe100008 /* Long access */ 40#define TMU1_TCNT (TMU_012_BASE + 0x18)
42#define TMU3_TCNT 0xfe10000c /* Long access */ 41#define TMU1_TCR (TMU_012_BASE + 0x1c)
43#define TMU3_TCR 0xfe100010 /* Word access */
44 42
45#define TMU4_TCOR 0xfe100014 /* Long access */ 43#define TMU2_TCOR (TMU_012_BASE + 0x20)
46#define TMU4_TCNT 0xfe100018 /* Long access */ 44#define TMU2_TCNT (TMU_012_BASE + 0x24)
47#define TMU4_TCR 0xfe10001c /* Word access */ 45#define TMU2_TCR (TMU_012_BASE + 0x28)
48#endif 46#define TMU2_TCPR (TMU_012_BASE + 0x2c)
49 47
50#endif /* __ASM_CPU_SH4_TIMER_H */ 48#define TMU3_TCOR (TMU_345_BASE + 0x08)
49#define TMU3_TCNT (TMU_345_BASE + 0x0c)
50#define TMU3_TCR (TMU_345_BASE + 0x10)
51 51
52#define TMU4_TCOR (TMU_345_BASE + 0x14)
53#define TMU4_TCNT (TMU_345_BASE + 0x18)
54#define TMU4_TCR (TMU_345_BASE + 0x1c)
55
56#define TMU5_TCOR (TMU_345_BASE + 0x20)
57#define TMU5_TCNT (TMU_345_BASE + 0x24)
58#define TMU5_TCR (TMU_345_BASE + 0x28)
59
60#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 1a20db096196..2252e75daa26 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -52,7 +52,7 @@ enum cpu_type {
52 CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501, 52 CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
53 53
54 /* SH-4A types */ 54 /* SH-4A types */
55 CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, 55 CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
56 56
57 /* SH4AL-DSP types */ 57 /* SH4AL-DSP types */
58 CPU_SH73180, CPU_SH7343, CPU_SH7722, 58 CPU_SH73180, CPU_SH7343, CPU_SH7722,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 10:57:55 -0500