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-rw-r--r--include/asm-alpha/cache.h1
-rw-r--r--include/asm-arm/cache.h5
-rw-r--r--include/asm-cris/arch-v10/cache.h1
-rw-r--r--include/asm-cris/arch-v32/cache.h1
-rw-r--r--include/asm-cris/dma-mapping.h2
-rw-r--r--include/asm-generic/dma-mapping.h2
-rw-r--r--include/asm-i386/cache.h2
-rw-r--r--include/asm-i386/dma-mapping.h2
-rw-r--r--include/asm-ia64/cache.h2
-rw-r--r--include/asm-m32r/cache.h2
-rw-r--r--include/asm-m68k/cache.h2
-rw-r--r--include/asm-mips/cache.h1
-rw-r--r--include/asm-parisc/cache.h1
-rw-r--r--include/asm-powerpc/cache.h1
-rw-r--r--include/asm-powerpc/dma-mapping.h2
-rw-r--r--include/asm-s390/cache.h1
-rw-r--r--include/asm-sh/cache.h2
-rw-r--r--include/asm-sh64/cache.h2
-rw-r--r--include/asm-sparc/cache.h1
-rw-r--r--include/asm-sparc64/cache.h1
-rw-r--r--include/asm-um/cache.h3
-rw-r--r--include/asm-v850/cache.h2
-rw-r--r--include/asm-x86_64/cache.h1
23 files changed, 4 insertions, 36 deletions
diff --git a/include/asm-alpha/cache.h b/include/asm-alpha/cache.h
index e69b29501a5f..e6d4d1695e25 100644
--- a/include/asm-alpha/cache.h
+++ b/include/asm-alpha/cache.h
@@ -20,6 +20,5 @@
20 20
21#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) 21#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
22#define SMP_CACHE_BYTES L1_CACHE_BYTES 22#define SMP_CACHE_BYTES L1_CACHE_BYTES
23#define L1_CACHE_SHIFT_MAX L1_CACHE_SHIFT
24 23
25#endif 24#endif
diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h
index 8d161f7c87ff..31332c8ac04e 100644
--- a/include/asm-arm/cache.h
+++ b/include/asm-arm/cache.h
@@ -7,9 +7,4 @@
7#define L1_CACHE_SHIFT 5 7#define L1_CACHE_SHIFT 5
8#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 8#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
9 9
10/*
11 * largest L1 which this arch supports
12 */
13#define L1_CACHE_SHIFT_MAX 5
14
15#endif 10#endif
diff --git a/include/asm-cris/arch-v10/cache.h b/include/asm-cris/arch-v10/cache.h
index 1d1d1ba65b1a..aea27184d2d2 100644
--- a/include/asm-cris/arch-v10/cache.h
+++ b/include/asm-cris/arch-v10/cache.h
@@ -4,6 +4,5 @@
4/* Etrax 100LX have 32-byte cache-lines. */ 4/* Etrax 100LX have 32-byte cache-lines. */
5#define L1_CACHE_BYTES 32 5#define L1_CACHE_BYTES 32
6#define L1_CACHE_SHIFT 5 6#define L1_CACHE_SHIFT 5
7#define L1_CACHE_SHIFT_MAX 5
8 7
9#endif /* _ASM_ARCH_CACHE_H */ 8#endif /* _ASM_ARCH_CACHE_H */
diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h
index 4fed8d62ccc8..80b236b15319 100644
--- a/include/asm-cris/arch-v32/cache.h
+++ b/include/asm-cris/arch-v32/cache.h
@@ -4,6 +4,5 @@
4/* A cache-line is 32 bytes. */ 4/* A cache-line is 32 bytes. */
5#define L1_CACHE_BYTES 32 5#define L1_CACHE_BYTES 32
6#define L1_CACHE_SHIFT 5 6#define L1_CACHE_SHIFT 5
7#define L1_CACHE_SHIFT_MAX 5
8 7
9#endif /* _ASM_CRIS_ARCH_CACHE_H */ 8#endif /* _ASM_CRIS_ARCH_CACHE_H */
diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h
index 8eff51349ae7..cbf1a98f0129 100644
--- a/include/asm-cris/dma-mapping.h
+++ b/include/asm-cris/dma-mapping.h
@@ -153,7 +153,7 @@ dma_set_mask(struct device *dev, u64 mask)
153static inline int 153static inline int
154dma_get_cache_alignment(void) 154dma_get_cache_alignment(void)
155{ 155{
156 return (1 << L1_CACHE_SHIFT_MAX); 156 return (1 << INTERNODE_CACHE_SHIFT);
157} 157}
158 158
159#define dma_is_consistent(d) (1) 159#define dma_is_consistent(d) (1)
diff --git a/include/asm-generic/dma-mapping.h b/include/asm-generic/dma-mapping.h
index 747d790295f3..1b356207712c 100644
--- a/include/asm-generic/dma-mapping.h
+++ b/include/asm-generic/dma-mapping.h
@@ -274,7 +274,7 @@ dma_get_cache_alignment(void)
274{ 274{
275 /* no easy way to get cache size on all processors, so return 275 /* no easy way to get cache size on all processors, so return
276 * the maximum possible, to be safe */ 276 * the maximum possible, to be safe */
277 return (1 << L1_CACHE_SHIFT_MAX); 277 return (1 << INTERNODE_CACHE_SHIFT);
278} 278}
279 279
280static inline void 280static inline void
diff --git a/include/asm-i386/cache.h b/include/asm-i386/cache.h
index 849788710feb..615911e5bd24 100644
--- a/include/asm-i386/cache.h
+++ b/include/asm-i386/cache.h
@@ -10,6 +10,4 @@
10#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) 10#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
11#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 11#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
12 12
13#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
14
15#endif 13#endif
diff --git a/include/asm-i386/dma-mapping.h b/include/asm-i386/dma-mapping.h
index e56c335f8ef9..6c37a9ab8d60 100644
--- a/include/asm-i386/dma-mapping.h
+++ b/include/asm-i386/dma-mapping.h
@@ -150,7 +150,7 @@ dma_get_cache_alignment(void)
150{ 150{
151 /* no easy way to get cache size on all x86, so return the 151 /* no easy way to get cache size on all x86, so return the
152 * maximum possible, to be safe */ 152 * maximum possible, to be safe */
153 return (1 << L1_CACHE_SHIFT_MAX); 153 return (1 << INTERNODE_CACHE_SHIFT);
154} 154}
155 155
156#define dma_is_consistent(d) (1) 156#define dma_is_consistent(d) (1)
diff --git a/include/asm-ia64/cache.h b/include/asm-ia64/cache.h
index 666d8f175cb3..40dd25195d65 100644
--- a/include/asm-ia64/cache.h
+++ b/include/asm-ia64/cache.h
@@ -12,8 +12,6 @@
12#define L1_CACHE_SHIFT CONFIG_IA64_L1_CACHE_SHIFT 12#define L1_CACHE_SHIFT CONFIG_IA64_L1_CACHE_SHIFT
13#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 13#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
14 14
15#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
16
17#ifdef CONFIG_SMP 15#ifdef CONFIG_SMP
18# define SMP_CACHE_SHIFT L1_CACHE_SHIFT 16# define SMP_CACHE_SHIFT L1_CACHE_SHIFT
19# define SMP_CACHE_BYTES L1_CACHE_BYTES 17# define SMP_CACHE_BYTES L1_CACHE_BYTES
diff --git a/include/asm-m32r/cache.h b/include/asm-m32r/cache.h
index 724820596980..9c2b2d9998bc 100644
--- a/include/asm-m32r/cache.h
+++ b/include/asm-m32r/cache.h
@@ -7,6 +7,4 @@
7#define L1_CACHE_SHIFT 4 7#define L1_CACHE_SHIFT 4
8#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 8#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
9 9
10#define L1_CACHE_SHIFT_MAX 4
11
12#endif /* _ASM_M32R_CACHE_H */ 10#endif /* _ASM_M32R_CACHE_H */
diff --git a/include/asm-m68k/cache.h b/include/asm-m68k/cache.h
index 6161fd3d8600..fed3fd30de7e 100644
--- a/include/asm-m68k/cache.h
+++ b/include/asm-m68k/cache.h
@@ -8,6 +8,4 @@
8#define L1_CACHE_SHIFT 4 8#define L1_CACHE_SHIFT 4
9#define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT) 9#define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT)
10 10
11#define L1_CACHE_SHIFT_MAX 4 /* largest L1 which this arch supports */
12
13#endif 11#endif
diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h
index 1a5d1a669db3..55e19f2ff0e0 100644
--- a/include/asm-mips/cache.h
+++ b/include/asm-mips/cache.h
@@ -15,7 +15,6 @@
15#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT 15#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
16#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 16#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
17 17
18#define L1_CACHE_SHIFT_MAX 6
19#define SMP_CACHE_SHIFT L1_CACHE_SHIFT 18#define SMP_CACHE_SHIFT L1_CACHE_SHIFT
20#define SMP_CACHE_BYTES L1_CACHE_BYTES 19#define SMP_CACHE_BYTES L1_CACHE_BYTES
21 20
diff --git a/include/asm-parisc/cache.h b/include/asm-parisc/cache.h
index 5da72e38bdde..38d201b5652d 100644
--- a/include/asm-parisc/cache.h
+++ b/include/asm-parisc/cache.h
@@ -28,7 +28,6 @@
28#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) 28#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
29 29
30#define SMP_CACHE_BYTES L1_CACHE_BYTES 30#define SMP_CACHE_BYTES L1_CACHE_BYTES
31#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
32 31
33extern void flush_data_cache_local(void); /* flushes local data-cache only */ 32extern void flush_data_cache_local(void); /* flushes local data-cache only */
34extern void flush_instruction_cache_local(void); /* flushes local code-cache only */ 33extern void flush_instruction_cache_local(void); /* flushes local code-cache only */
diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
index 26ce502e76e8..6379c2df5c40 100644
--- a/include/asm-powerpc/cache.h
+++ b/include/asm-powerpc/cache.h
@@ -19,7 +19,6 @@
19#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 19#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
20 20
21#define SMP_CACHE_BYTES L1_CACHE_BYTES 21#define SMP_CACHE_BYTES L1_CACHE_BYTES
22#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
23 22
24#if defined(__powerpc64__) && !defined(__ASSEMBLY__) 23#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
25struct ppc64_caches { 24struct ppc64_caches {
diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
index 59a80163f75f..a96e5742ca32 100644
--- a/include/asm-powerpc/dma-mapping.h
+++ b/include/asm-powerpc/dma-mapping.h
@@ -229,7 +229,7 @@ static inline int dma_get_cache_alignment(void)
229#ifdef CONFIG_PPC64 229#ifdef CONFIG_PPC64
230 /* no easy way to get cache size on all processors, so return 230 /* no easy way to get cache size on all processors, so return
231 * the maximum possible, to be safe */ 231 * the maximum possible, to be safe */
232 return (1 << L1_CACHE_SHIFT_MAX); 232 return (1 << INTERNODE_CACHE_SHIFT);
233#else 233#else
234 /* 234 /*
235 * Each processor family will define its own L1_CACHE_SHIFT, 235 * Each processor family will define its own L1_CACHE_SHIFT,
diff --git a/include/asm-s390/cache.h b/include/asm-s390/cache.h
index 29845378b206..e20cdd9074db 100644
--- a/include/asm-s390/cache.h
+++ b/include/asm-s390/cache.h
@@ -13,7 +13,6 @@
13 13
14#define L1_CACHE_BYTES 256 14#define L1_CACHE_BYTES 256
15#define L1_CACHE_SHIFT 8 15#define L1_CACHE_SHIFT 8
16#define L1_CACHE_SHIFT_MAX 8 /* largest L1 which this arch supports */
17 16
18#define ARCH_KMALLOC_MINALIGN 8 17#define ARCH_KMALLOC_MINALIGN 8
19 18
diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
index 9b4dd6d8212e..656fdfe9e8b4 100644
--- a/include/asm-sh/cache.h
+++ b/include/asm-sh/cache.h
@@ -22,8 +22,6 @@
22 22
23#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) 23#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
24 24
25#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
26
27struct cache_info { 25struct cache_info {
28 unsigned int ways; 26 unsigned int ways;
29 unsigned int sets; 27 unsigned int sets;
diff --git a/include/asm-sh64/cache.h b/include/asm-sh64/cache.h
index f54e85e8a470..a4f36f0036e1 100644
--- a/include/asm-sh64/cache.h
+++ b/include/asm-sh64/cache.h
@@ -20,8 +20,6 @@
20#define L1_CACHE_ALIGN_MASK (~(L1_CACHE_BYTES - 1)) 20#define L1_CACHE_ALIGN_MASK (~(L1_CACHE_BYTES - 1))
21#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES - 1)) & L1_CACHE_ALIGN_MASK) 21#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES - 1)) & L1_CACHE_ALIGN_MASK)
22#define L1_CACHE_SIZE_BYTES (L1_CACHE_BYTES << 10) 22#define L1_CACHE_SIZE_BYTES (L1_CACHE_BYTES << 10)
23/* Largest L1 which this arch supports */
24#define L1_CACHE_SHIFT_MAX 5
25 23
26#ifdef MODULE 24#ifdef MODULE
27#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) 25#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h
index a10522cb21b7..cb971e88aea4 100644
--- a/include/asm-sparc/cache.h
+++ b/include/asm-sparc/cache.h
@@ -13,7 +13,6 @@
13#define L1_CACHE_SHIFT 5 13#define L1_CACHE_SHIFT 5
14#define L1_CACHE_BYTES 32 14#define L1_CACHE_BYTES 32
15#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))) 15#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
16#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
17 16
18#define SMP_CACHE_BYTES 32 17#define SMP_CACHE_BYTES 32
19 18
diff --git a/include/asm-sparc64/cache.h b/include/asm-sparc64/cache.h
index ade5ec3bfd5a..f7d35a2ae9b8 100644
--- a/include/asm-sparc64/cache.h
+++ b/include/asm-sparc64/cache.h
@@ -9,7 +9,6 @@
9#define L1_CACHE_BYTES 32 /* Two 16-byte sub-blocks per line. */ 9#define L1_CACHE_BYTES 32 /* Two 16-byte sub-blocks per line. */
10 10
11#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) 11#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
12#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
13 12
14#define SMP_CACHE_BYTES_SHIFT 6 13#define SMP_CACHE_BYTES_SHIFT 6
15#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */ 14#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */
diff --git a/include/asm-um/cache.h b/include/asm-um/cache.h
index a10602a5b2d6..3d0587075521 100644
--- a/include/asm-um/cache.h
+++ b/include/asm-um/cache.h
@@ -13,9 +13,6 @@
13# define L1_CACHE_SHIFT 5 13# define L1_CACHE_SHIFT 5
14#endif 14#endif
15 15
16/* XXX: this is valid for x86 and x86_64. */
17#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
18
19#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 16#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
20 17
21#endif 18#endif
diff --git a/include/asm-v850/cache.h b/include/asm-v850/cache.h
index cbf9096e8517..8832c7ea3242 100644
--- a/include/asm-v850/cache.h
+++ b/include/asm-v850/cache.h
@@ -23,6 +23,4 @@
23#define L1_CACHE_SHIFT 4 23#define L1_CACHE_SHIFT 4
24#endif 24#endif
25 25
26#define L1_CACHE_SHIFT_MAX L1_CACHE_SHIFT
27
28#endif /* __V850_CACHE_H__ */ 26#endif /* __V850_CACHE_H__ */
diff --git a/include/asm-x86_64/cache.h b/include/asm-x86_64/cache.h
index 33e53424128b..b4a2401de77b 100644
--- a/include/asm-x86_64/cache.h
+++ b/include/asm-x86_64/cache.h
@@ -9,6 +9,5 @@
9/* L1 cache line size */ 9/* L1 cache line size */
10#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) 10#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
11#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 11#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
12#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
13 12
14#endif 13#endif