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-rw-r--r--include/asm-blackfin/mach-bf533/anomaly.h12
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h14
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h54
-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h18
4 files changed, 67 insertions, 31 deletions
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index f36ff5af1b91..98209d40abba 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -7,9 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List 10 * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
11 * - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List
12 * - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List
13 */ 11 */
14 12
15#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -17,7 +15,7 @@
17 15
18/* We do not support 0.1 or 0.2 silicon - sorry */ 16/* We do not support 0.1 or 0.2 silicon - sorry */
19#if __SILICON_REVISION__ < 3 17#if __SILICON_REVISION__ < 3
20# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2 18# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
21#endif 19#endif
22 20
23#if defined(__ADSPBF531__) 21#if defined(__ADSPBF531__)
@@ -251,6 +249,12 @@
251#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) 249#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
252/* Internal Voltage Regulator may not start up */ 250/* Internal Voltage Regulator may not start up */
253#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) 251#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
252/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
253#define ANOMALY_05000357 (1)
254/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
255#define ANOMALY_05000366 (1)
256/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
257#define ANOMALY_05000371 (1)
254 258
255/* Anomalies that don't exist on this proc */ 259/* Anomalies that don't exist on this proc */
256#define ANOMALY_05000266 (0) 260#define ANOMALY_05000266 (0)
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 2b66ecf489f7..746a794b3119 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,9 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List 10 * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
11 * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
12 * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
13 */ 11 */
14 12
15#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -17,7 +15,7 @@
17 15
18/* We do not support 0.1 silicon - sorry */ 16/* We do not support 0.1 silicon - sorry */
19#if __SILICON_REVISION__ < 2 17#if __SILICON_REVISION__ < 2
20# error Kernel will not work on BF537 silicon version 0.0 or 0.1 18# error will not work on BF537 silicon version 0.0 or 0.1
21#endif 19#endif
22 20
23#if defined(__ADSPBF534__) 21#if defined(__ADSPBF534__)
@@ -44,6 +42,8 @@
44#define ANOMALY_05000122 (1) 42#define ANOMALY_05000122 (1)
45/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ 43/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
46#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) 44#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
45/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
46#define ANOMALY_05000167 (1)
47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */ 47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
48#define ANOMALY_05000180 (1) 48#define ANOMALY_05000180 (1)
49/* Instruction Cache Is Not Functional */ 49/* Instruction Cache Is Not Functional */
@@ -130,6 +130,12 @@
130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) 130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ 131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
132#define ANOMALY_05000322 (1) 132#define ANOMALY_05000322 (1)
133/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
134#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
135/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
136#define ANOMALY_05000357 (1)
137/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
138#define ANOMALY_05000359 (1)
133 139
134/* Anomalies that don't exist on this proc */ 140/* Anomalies that don't exist on this proc */
135#define ANOMALY_05000125 (0) 141#define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index c5b63759cdee..850dc12eb7f2 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List 10 * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -26,47 +26,59 @@
26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 26/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
27#define ANOMALY_05000272 (1) 27#define ANOMALY_05000272 (1)
28/* False Hardware Error Exception when ISR context is not restored */ 28/* False Hardware Error Exception when ISR context is not restored */
29#define ANOMALY_05000281 (1) 29#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 30/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
31#define ANOMALY_05000304 (1) 31#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 32/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
33#define ANOMALY_05000310 (1) 33#define ANOMALY_05000310 (1)
34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 34/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
35#define ANOMALY_05000312 (1) 35#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
36/* TWI Slave Boot Mode Is Not Functional */ 36/* TWI Slave Boot Mode Is Not Functional */
37#define ANOMALY_05000324 (1) 37#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
38/* External FIFO Boot Mode Is Not Functional */ 38/* External FIFO Boot Mode Is Not Functional */
39#define ANOMALY_05000325 (1) 39#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ 40/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
41#define ANOMALY_05000327 (1) 41#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
42/* Incorrect Access of OTP_STATUS During otp_write() Function */ 42/* Incorrect Access of OTP_STATUS During otp_write() Function */
43#define ANOMALY_05000328 (1) 43#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
44/* Synchronous Burst Flash Boot Mode Is Not Functional */ 44/* Synchronous Burst Flash Boot Mode Is Not Functional */
45#define ANOMALY_05000329 (1) 45#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
46/* Host DMA Boot Mode Is Not Functional */ 46/* Host DMA Boot Mode Is Not Functional */
47#define ANOMALY_05000330 (1) 47#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ 48/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
49#define ANOMALY_05000334 (1) 49#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
50/* Inadequate Rotary Debounce Logic Duration */ 50/* Inadequate Rotary Debounce Logic Duration */
51#define ANOMALY_05000335 (1) 51#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
52/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ 52/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
53#define ANOMALY_05000336 (1) 53#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
54/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 54/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
55#define ANOMALY_05000337 (1) 55#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ 56/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
57#define ANOMALY_05000338 (1) 57#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ 58/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
59#define ANOMALY_05000340 (1) 59#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ 60/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
61#define ANOMALY_05000344 (1) 61#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
62/* USB Calibration Value Is Not Intialized */ 62/* USB Calibration Value Is Not Intialized */
63#define ANOMALY_05000346 (1) 63#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ 64/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
65#define ANOMALY_05000347 (1) 65#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
66/* Data Lost when Core Reads SDH Data FIFO */ 66/* Data Lost when Core Reads SDH Data FIFO */
67#define ANOMALY_05000349 (1) 67#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
68/* PLL Status Register Is Inaccurate */ 68/* PLL Status Register Is Inaccurate */
69#define ANOMALY_05000351 (1) 69#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
70/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
71#define ANOMALY_05000357 (1)
72/* External Memory Read Access Hangs Core With PLL Bypass */
73#define ANOMALY_05000360 (1)
74/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
75#define ANOMALY_05000365 (1)
76/* Addressing Conflict between Boot ROM and Asynchronous Memory */
77#define ANOMALY_05000369 (1)
78/* Mobile DDR Operation Not Functional */
79#define ANOMALY_05000377 (1)
80/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
81#define ANOMALY_05000378 (1)
70 82
71/* Anomalies that don't exist on this proc */ 83/* Anomalies that don't exist on this proc */
72#define ANOMALY_05000125 (0) 84#define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index bed956456884..0c1d46193939 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List 10 * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -15,7 +15,7 @@
15 15
16/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ 16/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 17#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
18# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 18# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
19#endif 19#endif
20 20
21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ 21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
@@ -208,6 +208,8 @@
208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) 208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ 209/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) 210#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
211/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
212#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
211/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 213/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
212#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) 214#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
213/* False Hardware Error Exception When ISR Context Is Not Restored */ 215/* False Hardware Error Exception When ISR Context Is Not Restored */
@@ -246,6 +248,18 @@
246#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) 248#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
247/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ 249/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
248#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) 250#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
251/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
252#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
253/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
254#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
255/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
256#define ANOMALY_05000357 (1)
257/* Conflicting Column Address Widths Causes SDRAM Errors */
258#define ANOMALY_05000362 (1)
259/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
260#define ANOMALY_05000366 (1)
261/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
262#define ANOMALY_05000371 (1)
249 263
250/* Anomalies that don't exist on this proc */ 264/* Anomalies that don't exist on this proc */
251#define ANOMALY_05000158 (0) 265#define ANOMALY_05000158 (0)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 12:05:51 -0500