aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/asmmacro.h4
-rw-r--r--include/asm-mips/mipsregs.h3
-rw-r--r--include/asm-mips/stackframe.h16
3 files changed, 12 insertions, 11 deletions
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
index 2c42f6b00a49..92e62ef711ed 100644
--- a/include/asm-mips/asmmacro.h
+++ b/include/asm-mips/asmmacro.h
@@ -26,14 +26,14 @@
26 ori \reg, \reg, TCSTATUS_IXMT 26 ori \reg, \reg, TCSTATUS_IXMT
27 xori \reg, \reg, TCSTATUS_IXMT 27 xori \reg, \reg, TCSTATUS_IXMT
28 mtc0 \reg, CP0_TCSTATUS 28 mtc0 \reg, CP0_TCSTATUS
29 ehb 29 _ehb
30 .endm 30 .endm
31 31
32 .macro local_irq_disable reg=t0 32 .macro local_irq_disable reg=t0
33 mfc0 \reg, CP0_TCSTATUS 33 mfc0 \reg, CP0_TCSTATUS
34 ori \reg, \reg, TCSTATUS_IXMT 34 ori \reg, \reg, TCSTATUS_IXMT
35 mtc0 \reg, CP0_TCSTATUS 35 mtc0 \reg, CP0_TCSTATUS
36 ehb 36 _ehb
37 .endm 37 .endm
38#else 38#else
39 .macro local_irq_enable reg=t0 39 .macro local_irq_enable reg=t0
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 673977901ed3..9192d76c133d 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -1459,7 +1459,8 @@ static inline void __emt(unsigned int previous)
1459static inline void __ehb(void) 1459static inline void __ehb(void)
1460{ 1460{
1461 __asm__ __volatile__( 1461 __asm__ __volatile__(
1462 " ehb \n"); 1462 " .set mips32r2 \n"
1463 " ehb \n" " .set mips0 \n");
1463} 1464}
1464 1465
1465/* 1466/*
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 513aa5133830..158a4cd12e46 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -304,7 +304,7 @@
304 mfc0 v0, CP0_TCSTATUS 304 mfc0 v0, CP0_TCSTATUS
305 ori v0, TCSTATUS_IXMT 305 ori v0, TCSTATUS_IXMT
306 mtc0 v0, CP0_TCSTATUS 306 mtc0 v0, CP0_TCSTATUS
307 ehb 307 _ehb
308 DMT 5 # dmt a1 308 DMT 5 # dmt a1
309 jal mips_ihb 309 jal mips_ihb
310#endif /* CONFIG_MIPS_MT_SMTC */ 310#endif /* CONFIG_MIPS_MT_SMTC */
@@ -325,14 +325,14 @@
325 * restore TCStatus.IXMT. 325 * restore TCStatus.IXMT.
326 */ 326 */
327 LONG_L v1, PT_TCSTATUS(sp) 327 LONG_L v1, PT_TCSTATUS(sp)
328 ehb 328 _ehb
329 mfc0 v0, CP0_TCSTATUS 329 mfc0 v0, CP0_TCSTATUS
330 andi v1, TCSTATUS_IXMT 330 andi v1, TCSTATUS_IXMT
331 /* We know that TCStatua.IXMT should be set from above */ 331 /* We know that TCStatua.IXMT should be set from above */
332 xori v0, v0, TCSTATUS_IXMT 332 xori v0, v0, TCSTATUS_IXMT
333 or v0, v0, v1 333 or v0, v0, v1
334 mtc0 v0, CP0_TCSTATUS 334 mtc0 v0, CP0_TCSTATUS
335 ehb 335 _ehb
336 andi a1, a1, VPECONTROL_TE 336 andi a1, a1, VPECONTROL_TE
337 beqz a1, 1f 337 beqz a1, 1f
338 emt 338 emt
@@ -411,7 +411,7 @@
411 /* Clear TKSU, leave IXMT */ 411 /* Clear TKSU, leave IXMT */
412 xori t0, 0x00001800 412 xori t0, 0x00001800
413 mtc0 t0, CP0_TCSTATUS 413 mtc0 t0, CP0_TCSTATUS
414 ehb 414 _ehb
415 /* We need to leave the global IE bit set, but clear EXL...*/ 415 /* We need to leave the global IE bit set, but clear EXL...*/
416 mfc0 t0, CP0_STATUS 416 mfc0 t0, CP0_STATUS
417 ori t0, ST0_EXL | ST0_ERL 417 ori t0, ST0_EXL | ST0_ERL
@@ -438,7 +438,7 @@
438 * and enable interrupts only for the 438 * and enable interrupts only for the
439 * current TC, using the TCStatus register. 439 * current TC, using the TCStatus register.
440 */ 440 */
441 ehb 441 _ehb
442 mfc0 t0,CP0_TCSTATUS 442 mfc0 t0,CP0_TCSTATUS
443 /* Fortunately CU 0 is in the same place in both registers */ 443 /* Fortunately CU 0 is in the same place in both registers */
444 /* Set TCU0, TKSU (for later inversion) and IXMT */ 444 /* Set TCU0, TKSU (for later inversion) and IXMT */
@@ -447,7 +447,7 @@
447 /* Clear TKSU *and* IXMT */ 447 /* Clear TKSU *and* IXMT */
448 xori t0, 0x00001c00 448 xori t0, 0x00001c00
449 mtc0 t0, CP0_TCSTATUS 449 mtc0 t0, CP0_TCSTATUS
450 ehb 450 _ehb
451 /* We need to leave the global IE bit set, but clear EXL...*/ 451 /* We need to leave the global IE bit set, but clear EXL...*/
452 mfc0 t0, CP0_STATUS 452 mfc0 t0, CP0_STATUS
453 ori t0, ST0_EXL 453 ori t0, ST0_EXL
@@ -479,7 +479,7 @@
479 andi v1, v0, TCSTATUS_IXMT 479 andi v1, v0, TCSTATUS_IXMT
480 ori v0, TCSTATUS_IXMT 480 ori v0, TCSTATUS_IXMT
481 mtc0 v0, CP0_TCSTATUS 481 mtc0 v0, CP0_TCSTATUS
482 ehb 482 _ehb
483 DMT 2 # dmt v0 483 DMT 2 # dmt v0
484 /* 484 /*
485 * We don't know a priori if ra is "live" 485 * We don't know a priori if ra is "live"
@@ -495,7 +495,7 @@
495 xori t0, 0x1e 495 xori t0, 0x1e
496 mtc0 t0, CP0_STATUS 496 mtc0 t0, CP0_STATUS
497#ifdef CONFIG_MIPS_MT_SMTC 497#ifdef CONFIG_MIPS_MT_SMTC
498 ehb 498 _ehb
499 andi v0, v0, VPECONTROL_TE 499 andi v0, v0, VPECONTROL_TE
500 beqz v0, 2f 500 beqz v0, 2f
501 nop /* delay slot */ 501 nop /* delay slot */