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-rw-r--r--include/asm-x86/pci.h90
-rw-r--r--include/asm-x86/pci_32.h58
-rw-r--r--include/asm-x86/pci_64.h56
-rw-r--r--include/linux/pci.h7
-rw-r--r--include/linux/pci_ids.h3
-rw-r--r--include/linux/pci_regs.h8
6 files changed, 104 insertions, 118 deletions
diff --git a/include/asm-x86/pci.h b/include/asm-x86/pci.h
index a8cac8c2cde7..e88361966347 100644
--- a/include/asm-x86/pci.h
+++ b/include/asm-x86/pci.h
@@ -1,5 +1,95 @@
1#ifndef __x86_PCI_H
2#define __x86_PCI_H
3
4#include <linux/mm.h> /* for struct page */
5#include <linux/types.h>
6#include <linux/slab.h>
7#include <linux/string.h>
8#include <asm/scatterlist.h>
9#include <asm/io.h>
10
11
12#ifdef __KERNEL__
13
14struct pci_sysdata {
15 int domain; /* PCI domain */
16 int node; /* NUMA node */
17#ifdef CONFIG_X86_64
18 void* iommu; /* IOMMU private data */
19#endif
20};
21
22/* scan a bus after allocating a pci_sysdata for it */
23extern struct pci_bus *pci_scan_bus_with_sysdata(int busno);
24
25static inline int pci_domain_nr(struct pci_bus *bus)
26{
27 struct pci_sysdata *sd = bus->sysdata;
28 return sd->domain;
29}
30
31static inline int pci_proc_domain(struct pci_bus *bus)
32{
33 return pci_domain_nr(bus);
34}
35
36
37/* Can be used to override the logic in pci_scan_bus for skipping
38 already-configured bus numbers - to be used for buggy BIOSes
39 or architectures with incomplete PCI setup by the loader */
40
41#ifdef CONFIG_PCI
42extern unsigned int pcibios_assign_all_busses(void);
43#else
44#define pcibios_assign_all_busses() 0
45#endif
46#define pcibios_scan_all_fns(a, b) 0
47
48extern unsigned long pci_mem_start;
49#define PCIBIOS_MIN_IO 0x1000
50#define PCIBIOS_MIN_MEM (pci_mem_start)
51
52#define PCIBIOS_MIN_CARDBUS_IO 0x4000
53
54void pcibios_config_init(void);
55struct pci_bus * pcibios_scan_root(int bus);
56
57void pcibios_set_master(struct pci_dev *dev);
58void pcibios_penalize_isa_irq(int irq, int active);
59struct irq_routing_table *pcibios_get_irq_routing_table(void);
60int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
61
62
63#define HAVE_PCI_MMAP
64extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
65 enum pci_mmap_state mmap_state, int write_combine);
66
67
68#ifdef CONFIG_PCI
69static inline void pci_dma_burst_advice(struct pci_dev *pdev,
70 enum pci_dma_burst_strategy *strat,
71 unsigned long *strategy_parameter)
72{
73 *strat = PCI_DMA_BURST_INFINITY;
74 *strategy_parameter = ~0UL;
75}
76#endif
77
78
79#endif /* __KERNEL__ */
80
1#ifdef CONFIG_X86_32 81#ifdef CONFIG_X86_32
2# include "pci_32.h" 82# include "pci_32.h"
3#else 83#else
4# include "pci_64.h" 84# include "pci_64.h"
5#endif 85#endif
86
87/* implement the pci_ DMA API in terms of the generic device dma_ one */
88#include <asm-generic/pci-dma-compat.h>
89
90/* generic pci stuff */
91#include <asm-generic/pci.h>
92
93
94
95#endif
diff --git a/include/asm-x86/pci_32.h b/include/asm-x86/pci_32.h
index 4fcacc711385..8c4c3a0368e2 100644
--- a/include/asm-x86/pci_32.h
+++ b/include/asm-x86/pci_32.h
@@ -4,50 +4,11 @@
4 4
5#ifdef __KERNEL__ 5#ifdef __KERNEL__
6 6
7struct pci_sysdata {
8 int node; /* NUMA node */
9};
10
11/* scan a bus after allocating a pci_sysdata for it */
12extern struct pci_bus *pci_scan_bus_with_sysdata(int busno);
13
14#include <linux/mm.h> /* for struct page */
15
16/* Can be used to override the logic in pci_scan_bus for skipping
17 already-configured bus numbers - to be used for buggy BIOSes
18 or architectures with incomplete PCI setup by the loader */
19
20#ifdef CONFIG_PCI
21extern unsigned int pcibios_assign_all_busses(void);
22#else
23#define pcibios_assign_all_busses() 0
24#endif
25#define pcibios_scan_all_fns(a, b) 0
26
27extern unsigned long pci_mem_start;
28#define PCIBIOS_MIN_IO 0x1000
29#define PCIBIOS_MIN_MEM (pci_mem_start)
30
31#define PCIBIOS_MIN_CARDBUS_IO 0x4000
32
33void pcibios_config_init(void);
34struct pci_bus * pcibios_scan_root(int bus);
35
36void pcibios_set_master(struct pci_dev *dev);
37void pcibios_penalize_isa_irq(int irq, int active);
38struct irq_routing_table *pcibios_get_irq_routing_table(void);
39int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
40 7
41/* Dynamic DMA mapping stuff. 8/* Dynamic DMA mapping stuff.
42 * i386 has everything mapped statically. 9 * i386 has everything mapped statically.
43 */ 10 */
44 11
45#include <linux/types.h>
46#include <linux/slab.h>
47#include <asm/scatterlist.h>
48#include <linux/string.h>
49#include <asm/io.h>
50
51struct pci_dev; 12struct pci_dev;
52 13
53/* The PCI address space does equal the physical memory 14/* The PCI address space does equal the physical memory
@@ -64,27 +25,8 @@ struct pci_dev;
64#define pci_unmap_len(PTR, LEN_NAME) (0) 25#define pci_unmap_len(PTR, LEN_NAME) (0)
65#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) 26#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
66 27
67#define HAVE_PCI_MMAP
68extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
69 enum pci_mmap_state mmap_state, int write_combine);
70
71
72#ifdef CONFIG_PCI
73static inline void pci_dma_burst_advice(struct pci_dev *pdev,
74 enum pci_dma_burst_strategy *strat,
75 unsigned long *strategy_parameter)
76{
77 *strat = PCI_DMA_BURST_INFINITY;
78 *strategy_parameter = ~0UL;
79}
80#endif
81 28
82#endif /* __KERNEL__ */ 29#endif /* __KERNEL__ */
83 30
84/* implement the pci_ DMA API in terms of the generic device dma_ one */
85#include <asm-generic/pci-dma-compat.h>
86
87/* generic pci stuff */
88#include <asm-generic/pci.h>
89 31
90#endif /* __i386_PCI_H */ 32#endif /* __i386_PCI_H */
diff --git a/include/asm-x86/pci_64.h b/include/asm-x86/pci_64.h
index 5da8cb0c0599..9baa46d9f594 100644
--- a/include/asm-x86/pci_64.h
+++ b/include/asm-x86/pci_64.h
@@ -1,16 +1,9 @@
1#ifndef __x8664_PCI_H 1#ifndef __x8664_PCI_H
2#define __x8664_PCI_H 2#define __x8664_PCI_H
3 3
4#include <asm/io.h>
5 4
6#ifdef __KERNEL__ 5#ifdef __KERNEL__
7 6
8struct pci_sysdata {
9 int node; /* NUMA node */
10 void* iommu; /* IOMMU private data */
11};
12
13extern struct pci_bus *pci_scan_bus_with_sysdata(int busno);
14 7
15#ifdef CONFIG_CALGARY_IOMMU 8#ifdef CONFIG_CALGARY_IOMMU
16static inline void* pci_iommu(struct pci_bus *bus) 9static inline void* pci_iommu(struct pci_bus *bus)
@@ -26,40 +19,11 @@ static inline void set_pci_iommu(struct pci_bus *bus, void *val)
26} 19}
27#endif /* CONFIG_CALGARY_IOMMU */ 20#endif /* CONFIG_CALGARY_IOMMU */
28 21
29#include <linux/mm.h> /* for struct page */
30
31/* Can be used to override the logic in pci_scan_bus for skipping
32 already-configured bus numbers - to be used for buggy BIOSes
33 or architectures with incomplete PCI setup by the loader */
34
35#ifdef CONFIG_PCI
36extern unsigned int pcibios_assign_all_busses(void);
37#else
38#define pcibios_assign_all_busses() 0
39#endif
40#define pcibios_scan_all_fns(a, b) 0
41
42extern unsigned long pci_mem_start;
43#define PCIBIOS_MIN_IO 0x1000
44#define PCIBIOS_MIN_MEM (pci_mem_start)
45
46#define PCIBIOS_MIN_CARDBUS_IO 0x4000
47 22
48void pcibios_config_init(void);
49struct pci_bus * pcibios_scan_root(int bus);
50extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value); 23extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value);
51extern int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value); 24extern int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value);
52 25
53void pcibios_set_master(struct pci_dev *dev);
54void pcibios_penalize_isa_irq(int irq, int active);
55struct irq_routing_table *pcibios_get_irq_routing_table(void);
56int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
57 26
58#include <linux/types.h>
59#include <linux/slab.h>
60#include <asm/scatterlist.h>
61#include <linux/string.h>
62#include <asm/page.h>
63 27
64extern void pci_iommu_alloc(void); 28extern void pci_iommu_alloc(void);
65extern int iommu_setup(char *opt); 29extern int iommu_setup(char *opt);
@@ -100,27 +64,7 @@ extern int iommu_setup(char *opt);
100 64
101#endif 65#endif
102 66
103#include <asm-generic/pci-dma-compat.h>
104
105#ifdef CONFIG_PCI
106static inline void pci_dma_burst_advice(struct pci_dev *pdev,
107 enum pci_dma_burst_strategy *strat,
108 unsigned long *strategy_parameter)
109{
110 *strat = PCI_DMA_BURST_INFINITY;
111 *strategy_parameter = ~0UL;
112}
113#endif
114
115#define HAVE_PCI_MMAP
116extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
117 enum pci_mmap_state mmap_state, int write_combine);
118
119#endif /* __KERNEL__ */ 67#endif /* __KERNEL__ */
120 68
121/* generic pci stuff */
122#ifdef CONFIG_PCI
123#include <asm-generic/pci.h>
124#endif
125 69
126#endif /* __x8664_PCI_H */ 70#endif /* __x8664_PCI_H */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 038a0dc7273a..768b93359f90 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -685,13 +685,16 @@ extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
685 * a PCI domain is defined to be a set of PCI busses which share 685 * a PCI domain is defined to be a set of PCI busses which share
686 * configuration space. 686 * configuration space.
687 */ 687 */
688#ifndef CONFIG_PCI_DOMAINS 688#ifdef CONFIG_PCI_DOMAINS
689extern int pci_domains_supported;
690#else
691enum { pci_domains_supported = 0 };
689static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 692static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
690static inline int pci_proc_domain(struct pci_bus *bus) 693static inline int pci_proc_domain(struct pci_bus *bus)
691{ 694{
692 return 0; 695 return 0;
693} 696}
694#endif 697#endif /* CONFIG_PCI_DOMAINS */
695 698
696#else /* CONFIG_PCI is not enabled */ 699#else /* CONFIG_PCI is not enabled */
697 700
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 584741bb73b3..87439ad94685 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -829,6 +829,9 @@
829#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a 829#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a
830#define PCI_DEVICE_ID_UMC_UM8886A 0x886a 830#define PCI_DEVICE_ID_UMC_UM8886A 0x886a
831 831
832#define PCI_VENDOR_ID_PICOPOWER 0x1066
833#define PCI_DEVICE_ID_PICOPOWER_PT86C523 0x0002
834#define PCI_DEVICE_ID_PICOPOWER_PT86C523BBP 0x8002
832 835
833#define PCI_VENDOR_ID_MYLEX 0x1069 836#define PCI_VENDOR_ID_MYLEX 0x1069
834#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 837#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 423d592c55d5..c1914a8b94a9 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -147,7 +147,7 @@
147#define PCI_BRIDGE_CONTROL 0x3e 147#define PCI_BRIDGE_CONTROL 0x3e
148#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 148#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
149#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 149#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
150#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 150#define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */
151#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 151#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
152#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 152#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
153#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 153#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
@@ -202,8 +202,12 @@
202#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 202#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
203#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 203#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
204#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 204#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
205#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ 205#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
206#define PCI_CAP_ID_DBG 0x0A /* Debug port */
207#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
206#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 208#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
209#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
210#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
207#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 211#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
208#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 212#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
209#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 213#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-29 20:42:11 -0400