147 files changed, 27925 insertions, 745 deletions

diff --git a/include/acpi/acpi_numa.h b/include/acpi/acpi_numa.h
index f9d2bde9a7bb..b62cd36ff324 100644
--- a/include/acpi/acpi_numa.h
+++ b/include/acpi/acpi_numa.h
@@ -11,11 +11,8 @@
 #define MAX_PXM_DOMAINS (256)   /* Old pxm spec is defined 8 bit */
 #endif
 
-extern int __cpuinitdata pxm_to_node_map[MAX_PXM_DOMAINS];
-extern int __cpuinitdata node_to_pxm_map[MAX_NUMNODES];
-
-extern int __cpuinit pxm_to_node(int);
-extern int __cpuinit node_to_pxm(int);
+extern int pxm_to_node(int);
+extern int node_to_pxm(int);
 extern int __cpuinit acpi_map_pxm_to_node(int);
 extern void __cpuinit acpi_unmap_pxm_to_node(int);
 
diff --git a/include/asm-alpha/bitops.h b/include/asm-alpha/bitops.h
index 4b6ef7f21b93..3a0cbeb03fa1 100644
--- a/include/asm-alpha/bitops.h
+++ b/include/asm-alpha/bitops.h
@@ -313,32 +313,29 @@ static inline int ffs(int word)
  * fls: find last bit set.
  */
 #if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
-static inline int fls(int word)
+static inline int fls64(unsigned long word)
 {
-        return 64 - __kernel_ctlz(word & 0xffffffff);
+        return 64 - __kernel_ctlz(word);
 }
 #else
-#include <asm-generic/bitops/fls.h>
-#endif
-#include <asm-generic/bitops/fls64.h>
+extern const unsigned char __flsm1_tab[256];
 
-/* Compute powers of two for the given integer.  */
-static inline long floor_log2(unsigned long word)
+static inline int fls64(unsigned long x)
 {
-#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
-        return 63 - __kernel_ctlz(word);
-#else
-        long bit;
-        for (bit = -1; word ; bit++)
-                word >>= 1;
-        return bit;
-#endif
+        unsigned long t, a, r;
+
+        t = __kernel_cmpbge (x, 0x0101010101010101);
+        a = __flsm1_tab[t];
+        t = __kernel_extbl (x, a);
+        r = a*8 + __flsm1_tab[t] + (x != 0);
+
+        return r;
 }
+#endif
 
-static inline long ceil_log2(unsigned long word)
+static inline int fls(int x)
 {
-        long bit = floor_log2(word);
-        return bit + (word > (1UL << bit));
+        return fls64((unsigned int) x);
 }
 
 /*
@@ -353,9 +350,20 @@ static inline unsigned long hweight64(unsigned long w)
         return __kernel_ctpop(w);
 }
 
-#define hweight32(x)    (unsigned int) hweight64((x) & 0xfffffffful)
-#define hweight16(x)    (unsigned int) hweight64((x) & 0xfffful)
-#define hweight8(x)     (unsigned int) hweight64((x) & 0xfful)
+static inline unsigned int hweight32(unsigned int w)
+{
+        return hweight64(w);
+}
+
+static inline unsigned int hweight16(unsigned int w)
+{
+        return hweight64(w & 0xffff);
+}
+
+static inline unsigned int hweight8(unsigned int w)
+{
+        return hweight64(w & 0xff);
+}
 #else
 #include <asm-generic/bitops/hweight.h>
 #endif
diff --git a/include/asm-alpha/thread_info.h b/include/asm-alpha/thread_info.h
index f4defc2bd3fb..48a22e3e6f32 100644
--- a/include/asm-alpha/thread_info.h
+++ b/include/asm-alpha/thread_info.h
@@ -76,12 +76,14 @@ register struct thread_info *__current_thread_info __asm__("$8");
 #define TIF_UAC_NOFIX           7
 #define TIF_UAC_SIGBUS          8
 #define TIF_MEMDIE              9
+#define TIF_RESTORE_SIGMASK     10      /* restore signal mask in do_signal */
 
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
 
 /* Work to do on interrupt/exception return.  */
 #define _TIF_WORK_MASK          (_TIF_NOTIFY_RESUME     \
diff --git a/include/asm-alpha/unistd.h b/include/asm-alpha/unistd.h
index e58a427012dd..29bf2fdc91c0 100644
--- a/include/asm-alpha/unistd.h
+++ b/include/asm-alpha/unistd.h
@@ -233,6 +233,20 @@
 #define __NR_osf_memcntl        260     /* not implemented */
 #define __NR_osf_fdatasync      261     /* not implemented */
 
+/*
+ * Ignore legacy syscalls that we don't use.
+ */
+#define __IGNORE_alarm
+#define __IGNORE_creat
+#define __IGNORE_getegid
+#define __IGNORE_geteuid
+#define __IGNORE_getgid
+#define __IGNORE_getpid
+#define __IGNORE_getppid
+#define __IGNORE_getuid
+#define __IGNORE_pause
+#define __IGNORE_time
+#define __IGNORE_utime
 
 /*
  * Linux-specific system calls begin at 300
@@ -387,10 +401,42 @@
 #define __NR_inotify_init               444
 #define __NR_inotify_add_watch          445
 #define __NR_inotify_rm_watch           446
+#define __NR_fdatasync                  447
+#define __NR_kexec_load                 448
+#define __NR_migrate_pages              449
+#define __NR_openat                     450
+#define __NR_mkdirat                    451
+#define __NR_mknodat                    452
+#define __NR_fchownat                   453
+#define __NR_futimesat                  454
+#define __NR_fstatat64                  455
+#define __NR_unlinkat                   456
+#define __NR_renameat                   457
+#define __NR_linkat                     458
+#define __NR_symlinkat                  459
+#define __NR_readlinkat                 460
+#define __NR_fchmodat                   461
+#define __NR_faccessat                  462
+#define __NR_pselect6                   463
+#define __NR_ppoll                      464
+#define __NR_unshare                    465
+#define __NR_set_robust_list            466
+#define __NR_get_robust_list            467
+#define __NR_splice                     468
+#define __NR_sync_file_range            469
+#define __NR_tee                        470
+#define __NR_vmsplice                   471
+#define __NR_move_pages                 472
+#define __NR_getcpu                     473
+#define __NR_epoll_pwait                474
+#define __NR_utimensat                  475
+#define __NR_signalfd                   476
+#define __NR_timerfd                    477
+#define __NR_eventfd                    478
 
 #ifdef __KERNEL__
 
-#define NR_SYSCALLS                     447
+#define NR_SYSCALLS                     479
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/include/asm-arm/arch-at91/at91_adc.h b/include/asm-arm/arch-at91/at91_adc.h
index 1ed66eaaf83a..6d71ea2637b1 100644
--- a/include/asm-arm/arch-at91/at91_adc.h
+++ b/include/asm-arm/arch-at91/at91_adc.h
@@ -55,7 +55,7 @@
 #define AT91_ADC_IDR            0x28            /* Interrupt Disable Register */
 #define AT91_ADC_IMR            0x2C            /* Interrupt Mask Register */
 
-#define AT91_ADC_CHR(n)         (0x30 + ((n) * 4)       /* Channel Data Register N */
+#define AT91_ADC_CHR(n)         (0x30 + ((n) * 4))      /* Channel Data Register N */
 #define         AT91_ADC_DATA           (0x3ff)
 
 #endif
diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h
deleted file mode 100644
index ab2c79bb9505..000000000000
--- a/include/asm-arm/arch-integrator/smp.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef ASMARM_ARCH_SMP_H
-#define ASMARM_ARCH_SMP_H
-
-
-#include <asm/hardware.h>
-#include <asm/io.h>
-
-#define hard_smp_processor_id()                         \
-        ({                                              \
-                unsigned int cpunum;                    \
-                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
-                        : "=r" (cpunum));               \
-                cpunum &= 0x0F;                         \
-        })
-
-extern void secondary_scan_irqs(void);
-
-#endif
diff --git a/include/asm-arm/arch-ixp4xx/nas100d.h b/include/asm-arm/arch-ixp4xx/nas100d.h
index 84467a5190d0..131e0a1d0df3 100644
--- a/include/asm-arm/arch-ixp4xx/nas100d.h
+++ b/include/asm-arm/arch-ixp4xx/nas100d.h
@@ -10,7 +10,7 @@
  * based on ixdp425.h:
  *      Copyright 2004 (c) MontaVista, Software, Inc.
  *
- * This file is licensed under  the terms of the GNU General Public
+ * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
@@ -36,31 +36,11 @@
 #define NAS100D_PCI_INTD_PIN    8
 #define NAS100D_PCI_INTE_PIN    7
 
-/* GPIO */
-
-#define NAS100D_GPIO0           0
-#define NAS100D_GPIO1           1
-#define NAS100D_GPIO2           2
-#define NAS100D_GPIO3           3
-#define NAS100D_GPIO4           4
-#define NAS100D_GPIO5           5
-#define NAS100D_GPIO6           6
-#define NAS100D_GPIO7           7
-#define NAS100D_GPIO8           8
-#define NAS100D_GPIO9           9
-#define NAS100D_GPIO10          10
-#define NAS100D_GPIO11          11
-#define NAS100D_GPIO12          12
-#define NAS100D_GPIO13          13
-#define NAS100D_GPIO14          14
-#define NAS100D_GPIO15          15
-
-
 /* Buttons */
 
-#define NAS100D_PB_GPIO         NAS100D_GPIO14
-#define NAS100D_RB_GPIO         NAS100D_GPIO4
-#define NAS100D_PO_GPIO         NAS100D_GPIO12   /* power off */
+#define NAS100D_PB_GPIO         14
+#define NAS100D_RB_GPIO         4
+#define NAS100D_PO_GPIO         12   /* power off */
 
 #define NAS100D_PB_IRQ          IRQ_IXP4XX_GPIO14
 #define NAS100D_RB_IRQ          IRQ_IXP4XX_GPIO4
diff --git a/include/asm-arm/arch-ixp4xx/nslu2.h b/include/asm-arm/arch-ixp4xx/nslu2.h
index 6b437f7c9955..850fdc5b45da 100644
--- a/include/asm-arm/arch-ixp4xx/nslu2.h
+++ b/include/asm-arm/arch-ixp4xx/nslu2.h
@@ -9,7 +9,7 @@
  * based on ixdp425.h:
  *      Copyright 2004 (c) MontaVista, Software, Inc.
  *
- * This file is licensed under  the terms of the GNU General Public
+ * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
@@ -34,36 +34,14 @@
 #define NSLU2_PCI_INTC_PIN      9
 #define NSLU2_PCI_INTD_PIN      8
 
-
 /* NSLU2 Timer */
 #define NSLU2_FREQ 66000000
-#define NSLU2_CLOCK_TICK_RATE (((NSLU2_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
-#define NSLU2_CLOCK_TICKS_PER_USEC ((NSLU2_CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
-
-/* GPIO */
-
-#define NSLU2_GPIO0             0
-#define NSLU2_GPIO1             1
-#define NSLU2_GPIO2             2
-#define NSLU2_GPIO3             3
-#define NSLU2_GPIO4             4
-#define NSLU2_GPIO5             5
-#define NSLU2_GPIO6             6
-#define NSLU2_GPIO7             7
-#define NSLU2_GPIO8             8
-#define NSLU2_GPIO9             9
-#define NSLU2_GPIO10            10
-#define NSLU2_GPIO11            11
-#define NSLU2_GPIO12            12
-#define NSLU2_GPIO13            13
-#define NSLU2_GPIO14            14
-#define NSLU2_GPIO15            15
 
 /* Buttons */
 
-#define NSLU2_PB_GPIO           NSLU2_GPIO5
-#define NSLU2_PO_GPIO           NSLU2_GPIO8     /* power off */
-#define NSLU2_RB_GPIO           NSLU2_GPIO12
+#define NSLU2_PB_GPIO           5
+#define NSLU2_PO_GPIO           8       /* power off */
+#define NSLU2_RB_GPIO           12
 
 #define NSLU2_PB_IRQ            IRQ_IXP4XX_GPIO5
 #define NSLU2_RB_IRQ            IRQ_IXP4XX_GPIO12
@@ -79,16 +57,16 @@
 
 /* LEDs */
 
-#define NSLU2_LED_RED           NSLU2_GPIO0
-#define NSLU2_LED_GRN           NSLU2_GPIO1
+#define NSLU2_LED_RED_GPIO      0
+#define NSLU2_LED_GRN_GPIO      1
 
-#define NSLU2_LED_RED_BM        (1L << NSLU2_LED_RED)
-#define NSLU2_LED_GRN_BM        (1L << NSLU2_LED_GRN)
+#define NSLU2_LED_RED_BM        (1L << NSLU2_LED_RED_GPIO)
+#define NSLU2_LED_GRN_BM        (1L << NSLU2_LED_GRN_GPIO)
 
-#define NSLU2_LED_DISK1         NSLU2_GPIO3
-#define NSLU2_LED_DISK2         NSLU2_GPIO2
+#define NSLU2_LED_DISK1_GPIO    3
+#define NSLU2_LED_DISK2_GPIO    2
 
-#define NSLU2_LED_DISK1_BM      (1L << NSLU2_GPIO2)
-#define NSLU2_LED_DISK2_BM      (1L << NSLU2_GPIO3)
+#define NSLU2_LED_DISK1_BM      (1L << NSLU2_LED_DISK1_GPIO)
+#define NSLU2_LED_DISK2_BM      (1L << NSLU2_LED_DISK2_GPIO)
 
 
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index ab194e5f6653..2a44d3d67980 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -113,6 +113,7 @@ extern unsigned long ixp4xx_timer_freq;
 extern void ixp4xx_map_io(void);
 extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
+extern void ixp4xx_timer_init(void);
 extern struct sys_timer ixp4xx_timer;
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
index c79cb1819913..3b49cd1c345c 100644
--- a/include/asm-arm/arch-s3c2410/irqs.h
+++ b/include/asm-arm/arch-s3c2410/irqs.h
@@ -124,7 +124,7 @@
 #define IRQ_S3C2443_DMA         S3C2410_IRQ(17)         /* IRQ_DMA1 */
 #define IRQ_S3C2443_UART3       S3C2410_IRQ(18)         /* IRQ_DMA2 */
 #define IRQ_S3C2443_CFCON       S3C2410_IRQ(19)         /* IRQ_DMA3 */
-#define IRQ_S3C2443_SDI1        S3C2410_IRQ(20)         /* IRQ_SDI */
+#define IRQ_S3C2443_HSMMC       S3C2410_IRQ(20)         /* IRQ_SDI */
 #define IRQ_S3C2443_NAND        S3C2410_IRQ(24)         /* reserved */
 
 #define IRQ_S3C2443_LCD1        S3C2410_IRQSUB(14)
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 4505aefbad17..19e77f038042 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -153,6 +153,10 @@
 #define S3C2440_PA_AC97    (0x5B000000)
 #define S3C2440_SZ_AC97    SZ_1M
 
+/* S3C2443 High-speed SD/MMC */
+#define S3C2443_PA_HSMMC   (0x4A800000)
+#define S3C2443_SZ_HSMMC   (256)
+
 /* ISA style IO, for each machine to sort out mappings for, if it
  * implements it. We reserve two 16M regions for ISA.
  */
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h
index 02131a5a1d3a..0362332faaf0 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpioj.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpioj.h
@@ -98,5 +98,9 @@
 #define S3C2440_GPJ12_OUTP      (0x01 << 24)
 #define S3C2440_GPJ12_CAMRESET  (0x02 << 24)
 
+#define S3C2443_GPJ13           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13)
+#define S3C2443_GPJ14           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14)
+#define S3C2443_GPJ15           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15)
+
 #endif  /* __ASM_ARCH_REGS_GPIOJ_H */
 
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412.h b/include/asm-arm/arch-s3c2410/regs-s3c2412.h
new file mode 100644
index 000000000000..8ca6a3bc8555
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-s3c2412.h
@@ -0,0 +1,21 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-s3c2412.h
+ *
+ * Copyright 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2412 specific register definitions
+*/
+
+#ifndef __ASM_ARCH_REGS_S3C2412_H
+#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
+
+#define S3C2412_SWRST           (S3C24XX_VA_CLKPWR + 0x30)
+#define S3C2412_SWRST_RESET     (0x533C2412)
+
+#endif  /* __ASM_ARCH_REGS_S3C2412_H */
+
diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/arch-s3c2410/regs-spi.h
index 3552280d1e8f..4a499a138256 100644
--- a/include/asm-arm/arch-s3c2410/regs-spi.h
+++ b/include/asm-arm/arch-s3c2410/regs-spi.h
@@ -12,6 +12,8 @@
 #ifndef __ASM_ARCH_REGS_SPI_H
 #define __ASM_ARCH_REGS_SPI_H
 
+#define S3C2410_SPI1    (0x20)
+#define S3C2412_SPI1    (0x100)
 
 #define S3C2410_SPCON   (0x00)
 
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 8261ff9e7955..1d3caa42a386 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -259,9 +259,11 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 #define BIOVEC_MERGEABLE(vec1, vec2)    \
         ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
 
+#ifdef CONFIG_MMU
 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 extern int valid_phys_addr_range(unsigned long addr, size_t size);
 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+#endif
 
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
diff --git a/include/asm-arm/ioctls.h b/include/asm-arm/ioctls.h
index bb9a7aa10c12..a91d8a1523cf 100644
--- a/include/asm-arm/ioctls.h
+++ b/include/asm-arm/ioctls.h
@@ -46,6 +46,10 @@
 #define TIOCSBRK        0x5427  /* BSD compatibility */
 #define TIOCCBRK        0x5428  /* BSD compatibility */
 #define TIOCGSID        0x5429  /* Return the session ID of FD */
+#define TCGETS2         _IOR('T',0x2A, struct termios2)
+#define TCSETS2         _IOW('T',0x2B, struct termios2)
+#define TCSETSW2        _IOW('T',0x2C, struct termios2)
+#define TCSETSF2        _IOW('T',0x2D, struct termios2)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
 
diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h
index fd2f9bf4dcc6..c59fad18e73b 100644
--- a/include/asm-arm/mach/arch.h
+++ b/include/asm-arm/mach/arch.h
@@ -49,7 +49,7 @@ struct machine_desc {
  */
 #define MACHINE_START(_type,_name)                      \
 static const struct machine_desc __mach_desc_##_type    \
- __attribute_used__                                     \
+ __used                                                 \
  __attribute__((__section__(".arch.info.init"))) = {    \
         .nr             = MACH_TYPE_##_type,            \
         .name           = _name,
diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h
index fe2a23b5627b..53099d4ee421 100644
--- a/include/asm-arm/mmu.h
+++ b/include/asm-arm/mmu.h
@@ -4,13 +4,13 @@
 #ifdef CONFIG_MMU
 
 typedef struct {
-#if __LINUX_ARM_ARCH__ >= 6
+#ifdef CONFIG_CPU_HAS_ASID
         unsigned int id;
 #endif
         unsigned int kvm_seq;
 } mm_context_t;
 
-#if __LINUX_ARM_ARCH__ >= 6
+#ifdef CONFIG_CPU_HAS_ASID
 #define ASID(mm)        ((mm)->context.id & 255)
 #else
 #define ASID(mm)        (0)
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index 4981ad419198..6913d02ca5d6 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -20,7 +20,7 @@
 
 void __check_kvm_seq(struct mm_struct *mm);
 
-#if __LINUX_ARM_ARCH__ >= 6
+#ifdef CONFIG_CPU_HAS_ASID
 
 /*
  * On ARMv6, we have the following structure in the Context ID:
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
index dddf485fc067..f9d6f0317bc1 100644
--- a/include/asm-arm/plat-s3c24xx/devs.h
+++ b/include/asm-arm/plat-s3c24xx/devs.h
@@ -29,6 +29,7 @@ extern struct platform_device s3c_device_iis;
 extern struct platform_device s3c_device_rtc;
 extern struct platform_device s3c_device_adc;
 extern struct platform_device s3c_device_sdi;
+extern struct platform_device s3c_device_hsmmc;
 
 extern struct platform_device s3c_device_spi0;
 extern struct platform_device s3c_device_spi1;
diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h
index e5407392afca..7bbf105463f1 100644
--- a/include/asm-arm/setup.h
+++ b/include/asm-arm/setup.h
@@ -185,7 +185,7 @@ struct tagtable {
 
 #ifdef __KERNEL__
 
-#define __tag __attribute_used__ __attribute__((__section__(".taglist.init")))
+#define __tag __used __attribute__((__section__(".taglist.init")))
 #define __tagtable(tag, fn) \
 static struct tagtable __tagtable_##fn __tag = { tag, fn }
 
@@ -218,7 +218,7 @@ struct early_params {
 };
 
 #define __early_param(name,fn)                                  \
-static struct early_params __early_##fn __attribute_used__      \
+static struct early_params __early_##fn __used                  \
 __attribute__((__section__(".early_param.init"))) = { name, fn }
 
 #endif  /*  __KERNEL__  */
diff --git a/include/asm-arm/termbits.h b/include/asm-arm/termbits.h
index a3f4fe1742d0..f784d11f40b5 100644
--- a/include/asm-arm/termbits.h
+++ b/include/asm-arm/termbits.h
@@ -15,6 +15,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 struct ktermios {
         tcflag_t c_iflag;               /* input mode flags */
         tcflag_t c_oflag;               /* output mode flags */
@@ -128,6 +139,7 @@ struct ktermios {
 #define HUPCL   0002000
 #define CLOCAL  0004000
 #define CBAUDEX 0010000
+#define    BOTHER 0010000
 #define    B57600 0010001
 #define   B115200 0010002
 #define   B230400 0010003
@@ -143,10 +155,12 @@ struct ktermios {
 #define  B3000000 0010015
 #define  B3500000 0010016
 #define  B4000000 0010017
-#define CIBAUD    002003600000  /* input baud rate (not used) */
+#define CIBAUD    002003600000          /* input baud rate */
 #define CMSPAR    010000000000          /* mark or space (stick) parity */
 #define CRTSCTS   020000000000          /* flow control */
 
+#define IBSHIFT    16
+
 /* c_lflag bits */
 #define ISIG    0000001
 #define ICANON  0000002
diff --git a/include/asm-arm/termios.h b/include/asm-arm/termios.h
index 329c324c4040..293e3f1bc3f2 100644
--- a/include/asm-arm/termios.h
+++ b/include/asm-arm/termios.h
@@ -82,8 +82,10 @@ struct termio {
         copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
 })
 
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
 
 #endif  /* __KERNEL__ */
 
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 08c6991dc9c9..71be4fded7e2 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -138,12 +138,27 @@
 # define v6wbi_always_flags     (-1UL)
 #endif
 
+#ifdef CONFIG_CPU_TLB_V7
+# define v7wbi_possible_flags   v6wbi_tlb_flags
+# define v7wbi_always_flags     v6wbi_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB v7wbi
+# endif
+#else
+# define v7wbi_possible_flags   0
+# define v7wbi_always_flags     (-1UL)
+#endif
+
 #ifndef _TLB
 #error Unknown TLB model
 #endif
 
 #ifndef __ASSEMBLY__
 
+#include <linux/sched.h>
+
 struct cpu_tlb_fns {
         void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
         void (*flush_kern_range)(unsigned long, unsigned long);
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index c025ab47e4b9..250d7f145aca 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -373,6 +373,10 @@
 #define __NR_getcpu                     (__NR_SYSCALL_BASE+345)
                                         /* 346 for epoll_pwait */
 #define __NR_kexec_load                 (__NR_SYSCALL_BASE+347)
+#define __NR_utimensat                  (__NR_SYSCALL_BASE+348)
+#define __NR_signalfd                   (__NR_SYSCALL_BASE+349)
+#define __NR_timerfd                    (__NR_SYSCALL_BASE+350)
+#define __NR_eventfd                    (__NR_SYSCALL_BASE+351)
 
 /*
  * The following SWIs are ARM private.
@@ -433,5 +437,11 @@
  */
 #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
 
+/*
+ * Unimplemented (or alternatively implemented) syscalls
+ */
+#define __IGNORE_sync_file_range        1
+#define __IGNORE_fadvise64_64           1
+
 #endif /* __KERNEL__ */
 #endif /* __ASM_ARM_UNISTD_H */
diff --git a/include/asm-arm26/setup.h b/include/asm-arm26/setup.h
index 10fd07c76662..e82562306475 100644
--- a/include/asm-arm26/setup.h
+++ b/include/asm-arm26/setup.h
@@ -173,7 +173,7 @@ struct tagtable {
         int (*parse)(const struct tag *);
 };
 
-#define __tag __attribute_used__ __attribute__((__section__(".taglist")))
+#define __tag __used __attribute__((__section__(".taglist")))
 #define __tagtable(tag, fn) \
 static struct tagtable __tagtable_##fn __tag = { tag, fn }
 
diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h
index 1a7b07d436ff..9fd2e32f84b8 100644
--- a/include/asm-avr32/arch-at32ap/board.h
+++ b/include/asm-avr32/arch-at32ap/board.h
@@ -30,11 +30,9 @@ struct spi_board_info;
 struct platform_device *
 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
 
-struct lcdc_platform_data {
-        unsigned long fbmem_start;
-        unsigned long fbmem_size;
-};
+struct atmel_lcdfb_info;
 struct platform_device *
-at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data);
+at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
+                     unsigned long fbmem_start, unsigned long fbmem_len);
 
 #endif /* __ASM_ARCH_BOARD_H */
diff --git a/include/asm-avr32/kdebug.h b/include/asm-avr32/kdebug.h
index de419278fc39..7f54e2b15d13 100644
--- a/include/asm-avr32/kdebug.h
+++ b/include/asm-avr32/kdebug.h
@@ -5,13 +5,22 @@
 
 /* Grossly misnamed. */
 enum die_val {
-        DIE_FAULT,
         DIE_BREAKPOINT,
         DIE_SSTEP,
-        DIE_PAGE_FAULT,
 };
 
-int register_page_fault_notifier(struct notifier_block *nb);
-int unregister_page_fault_notifier(struct notifier_block *nb);
+/*
+ * These are only here because kprobes.c wants them to implement a
+ * blatant layering violation.  Will hopefully go away soon once all
+ * architectures are updated.
+ */
+static inline int register_page_fault_notifier(struct notifier_block *nb)
+{
+        return 0;
+}
+static inline int unregister_page_fault_notifier(struct notifier_block *nb)
+{
+        return 0;
+}
 
 #endif /* __ASM_AVR32_KDEBUG_H */
diff --git a/include/asm-avr32/kprobes.h b/include/asm-avr32/kprobes.h
index 09a5cbe2f896..190a6377c809 100644
--- a/include/asm-avr32/kprobes.h
+++ b/include/asm-avr32/kprobes.h
@@ -26,6 +26,7 @@ struct arch_specific_insn {
         kprobe_opcode_t insn[MAX_INSN_SIZE];
 };
 
+extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
 extern int kprobe_exceptions_notify(struct notifier_block *self,
                                     unsigned long val, void *data);
 
diff --git a/include/asm-avr32/unistd.h b/include/asm-avr32/unistd.h
index 2418cce624cc..3b4e35b55c82 100644
--- a/include/asm-avr32/unistd.h
+++ b/include/asm-avr32/unistd.h
@@ -296,9 +296,12 @@
 #define __NR_shmctl             277
 
 #define __NR_utimensat          278
+#define __NR_signalfd           279
+#define __NR_timerfd            280
+#define __NR_eventfd            281
 
 #ifdef __KERNEL__
-#define NR_syscalls             279
+#define NR_syscalls             282
 
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index e37f81609fc3..57f37ccdcdf1 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -104,6 +104,7 @@ extern unsigned long dpdt_swapcount_table[];
 
 extern unsigned long table_start, table_end;
 
+extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
 extern struct file_operations dpmc_fops;
 extern char _start;
 extern unsigned long _ramstart, _ramend, _rambase;
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index d16fe3cd6135..aa0d5503e232 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -148,10 +148,6 @@
 
 #ifdef BF537_FAMILY
 #define MAX_BLACKFIN_GPIOS 48
-#define PORT_F 0
-#define PORT_G 1
-#define PORT_H 2
-#define PORT_J 3
 
 #define GPIO_PF0        0
 #define GPIO_PF1        1
@@ -202,13 +198,17 @@
 #define GPIO_PH14       46
 #define GPIO_PH15       47
 
+#define PORT_F GPIO_PF0
+#define PORT_G GPIO_PG0
+#define PORT_H GPIO_PH0
+
 #endif
 
 #ifdef BF561_FAMILY
 #define MAX_BLACKFIN_GPIOS 48
-#define PORT_FIO0 0
-#define PORT_FIO1 1
-#define PORT_FIO2 2
+#define PORT_FIO0 GPIO_0
+#define PORT_FIO1 GPIO_16
+#define PORT_FIO2 GPIO_32
 #endif
 
 #ifndef __ASSEMBLY__
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index 7e6995e80d97..eac8bcaf64c2 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -115,13 +115,21 @@ static inline unsigned int readl(void __iomem *addr)
 
 #ifndef __ASSEMBLY__
 
-extern void outsb(void __iomem *port, const void *addr, unsigned long count);
-extern void outsw(void __iomem *port, const void *addr, unsigned long count);
-extern void outsl(void __iomem *port, const void *addr, unsigned long count);
+extern void outsb(void __iomem *port, const void *addr, unsigned short count);
+extern void outsw(void __iomem *port, const void *addr, unsigned short count);
+extern void outsl(void __iomem *port, const void *addr, unsigned short count);
 
-extern void insb(const void __iomem *port, void *addr, unsigned long count);
-extern void insw(const void __iomem *port, void *addr, unsigned long count);
-extern void insl(const void __iomem *port, void *addr, unsigned long count);
+extern void insb(const void __iomem *port, void *addr, unsigned short count);
+extern void insw(const void __iomem *port, void *addr, unsigned short count);
+extern void insl(const void __iomem *port, void *addr, unsigned short count);
+
+extern void dma_outsb(void __iomem *port, const void *addr, unsigned short count);
+extern void dma_outsw(void __iomem *port, const void *addr, unsigned short count);
+extern void dma_outsl(void __iomem *port, const void *addr, unsigned short count);
+
+extern void dma_insb(const void __iomem *port, void *addr, unsigned short count);
+extern void dma_insw(const void __iomem *port, void *addr, unsigned short count);
+extern void dma_insl(const void __iomem *port, void *addr, unsigned short count);
 
 /*
  * Map some physical address range into the kernel address space.
diff --git a/include/asm-blackfin/mach-bf527/cdefBF522.h b/include/asm-blackfin/mach-bf527/cdefBF522.h
new file mode 100644
index 000000000000..52c06494b886
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF522.h
@@ -0,0 +1,46 @@
+/*
+ * File:         include/asm-blackfin/mach-bf527/cdefbf522.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  system mmr register map
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF522_H
+#define _CDEF_BF522_H
+
+/* include all Core registers and bit definitions */
+#include "defBF522.h"
+
+/* include core specific register pointer definitions */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
+
+/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include "cdefBF52x_base.h"
+
+#endif /* _CDEF_BF522_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF525.h b/include/asm-blackfin/mach-bf527/cdefBF525.h
new file mode 100644
index 000000000000..2cc67e4b4d86
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF525.h
@@ -0,0 +1,461 @@
+/*
+ * File:         include/asm-blackfin/mach-bf527/cdefbf525.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  system mmr register map
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF525_H
+#define _CDEF_BF525_H
+
+/* include all Core registers and bit definitions */
+#include "defBF525.h"
+
+/* include core specific register pointer definitions */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
+
+/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include "cdefBF52x_base.h"
+
+/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
+
+/* USB Control Registers */
+
+#define bfin_read_USB_FADDR()                   bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)               bfin_write16(USB_FADDR, val)
+#define bfin_read_USB_POWER()                   bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)               bfin_write16(USB_POWER, val)
+#define bfin_read_USB_INTRTX()                  bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)              bfin_write16(USB_INTRTX, val)
+#define bfin_read_USB_INTRRX()                  bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)              bfin_write16(USB_INTRRX, val)
+#define bfin_read_USB_INTRTXE()                 bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)             bfin_write16(USB_INTRTXE, val)
+#define bfin_read_USB_INTRRXE()                 bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)             bfin_write16(USB_INTRRXE, val)
+#define bfin_read_USB_INTRUSB()                 bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)             bfin_write16(USB_INTRUSB, val)
+#define bfin_read_USB_INTRUSBE()                bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)            bfin_write16(USB_INTRUSBE, val)
+#define bfin_read_USB_FRAME()                   bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)               bfin_write16(USB_FRAME, val)
+#define bfin_read_USB_INDEX()                   bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)               bfin_write16(USB_INDEX, val)
+#define bfin_read_USB_TESTMODE()                bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)            bfin_write16(USB_TESTMODE, val)
+#define bfin_read_USB_GLOBINTR()                bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)            bfin_write16(USB_GLOBINTR, val)
+#define bfin_read_USB_GLOBAL_CTL()              bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
+
+/* USB Packet Control Registers */
+
+#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
+#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
+#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
+#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
+#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
+#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
+#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
+#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
+#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
+#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
+#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
+#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
+#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
+
+/* USB Endpoint FIFO Registers */
+
+#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
+#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
+#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
+#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
+#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
+#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
+#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
+#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
+
+/* USB OTG Control Registers */
+
+#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
+#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
+
+/* USB Phy Control Registers */
+
+#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
+#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
+#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
+#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
+#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
+
+#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
+
+#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
+#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
+
+/* USB Endpoint 0 Control Registers */
+
+#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
+#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
+#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
+
+/* USB Endpoint 1 Control Registers */
+
+#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
+#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
+#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
+
+/* USB Endpoint 2 Control Registers */
+
+#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
+#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
+#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
+
+/* USB Endpoint 3 Control Registers */
+
+#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
+#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
+#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
+
+/* USB Endpoint 4 Control Registers */
+
+#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
+#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
+#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
+
+/* USB Endpoint 5 Control Registers */
+
+#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
+#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
+#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
+
+/* USB Endpoint 6 Control Registers */
+
+#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
+#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
+#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
+
+/* USB Endpoint 7 Control Registers */
+
+#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
+#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
+#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
+
+#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
+
+/* USB Channel 0 Config Registers */
+
+#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
+#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
+#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
+#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
+#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
+#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
+#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
+#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
+#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
+#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
+
+/* USB Channel 1 Config Registers */
+
+#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
+#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
+#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
+#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
+#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
+#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
+#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
+#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
+#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
+#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
+
+/* USB Channel 2 Config Registers */
+
+#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
+#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
+#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
+#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
+#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
+#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
+#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
+#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
+#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
+#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
+
+/* USB Channel 3 Config Registers */
+
+#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
+#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
+#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
+#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
+#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
+#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
+#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
+#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
+#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
+#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
+
+/* USB Channel 4 Config Registers */
+
+#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
+#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
+#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
+#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
+#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
+#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
+#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
+#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
+#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
+#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
+
+/* USB Channel 5 Config Registers */
+
+#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
+#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
+#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
+#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
+#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
+#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
+#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
+#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
+#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
+#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
+
+/* USB Channel 6 Config Registers */
+
+#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
+#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
+#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
+#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
+#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
+#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
+#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
+#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
+#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
+#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
+
+/* USB Channel 7 Config Registers */
+
+#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
+#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
+#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
+#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
+#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
+#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
+#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
+#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
+#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
+#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
+
+#endif /* _CDEF_BF525_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF527.h b/include/asm-blackfin/mach-bf527/cdefBF527.h
new file mode 100644
index 000000000000..5bd1a8601743
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF527.h
@@ -0,0 +1,626 @@
+/*
+ * File:         include/asm-blackfin/mach-bf527/cdefbf527.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  system mmr register map
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF527_H
+#define _CDEF_BF527_H
+
+/* include all Core registers and bit definitions */
+#include "defBF527.h"
+
+/* include core specific register pointer definitions */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
+
+/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include "cdefBF52x_base.h"
+
+/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
+
+/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
+
+#define bfin_read_EMAC_OPMODE()                 bfin_read32(EMAC_OPMODE)
+#define bfin_write_EMAC_OPMODE(val)             bfin_write32(EMAC_OPMODE, val)
+#define bfin_read_EMAC_ADDRLO()                 bfin_read32(EMAC_ADDRLO)
+#define bfin_write_EMAC_ADDRLO(val)             bfin_write32(EMAC_ADDRLO, val)
+#define bfin_read_EMAC_ADDRHI()                 bfin_read32(EMAC_ADDRHI)
+#define bfin_write_EMAC_ADDRHI(val)             bfin_write32(EMAC_ADDRHI, val)
+#define bfin_read_EMAC_HASHLO()                 bfin_read32(EMAC_HASHLO)
+#define bfin_write_EMAC_HASHLO(val)             bfin_write32(EMAC_HASHLO, val)
+#define bfin_read_EMAC_HASHHI()                 bfin_read32(EMAC_HASHHI)
+#define bfin_write_EMAC_HASHHI(val)             bfin_write32(EMAC_HASHHI, val)
+#define bfin_read_EMAC_STAADD()                 bfin_read32(EMAC_STAADD)
+#define bfin_write_EMAC_STAADD(val)             bfin_write32(EMAC_STAADD, val)
+#define bfin_read_EMAC_STADAT()                 bfin_read32(EMAC_STADAT)
+#define bfin_write_EMAC_STADAT(val)             bfin_write32(EMAC_STADAT, val)
+#define bfin_read_EMAC_FLC()                    bfin_read32(EMAC_FLC)
+#define bfin_write_EMAC_FLC(val)                bfin_write32(EMAC_FLC, val)
+#define bfin_read_EMAC_VLAN1()                  bfin_read32(EMAC_VLAN1)
+#define bfin_write_EMAC_VLAN1(val)              bfin_write32(EMAC_VLAN1, val)
+#define bfin_read_EMAC_VLAN2()                  bfin_read32(EMAC_VLAN2)
+#define bfin_write_EMAC_VLAN2(val)              bfin_write32(EMAC_VLAN2, val)
+#define bfin_read_EMAC_WKUP_CTL()               bfin_read32(EMAC_WKUP_CTL)
+#define bfin_write_EMAC_WKUP_CTL(val)           bfin_write32(EMAC_WKUP_CTL, val)
+#define bfin_read_EMAC_WKUP_FFMSK0()            bfin_read32(EMAC_WKUP_FFMSK0)
+#define bfin_write_EMAC_WKUP_FFMSK0(val)        bfin_write32(EMAC_WKUP_FFMSK0, val)
+#define bfin_read_EMAC_WKUP_FFMSK1()            bfin_read32(EMAC_WKUP_FFMSK1)
+#define bfin_write_EMAC_WKUP_FFMSK1(val)        bfin_write32(EMAC_WKUP_FFMSK1, val)
+#define bfin_read_EMAC_WKUP_FFMSK2()            bfin_read32(EMAC_WKUP_FFMSK2)
+#define bfin_write_EMAC_WKUP_FFMSK2(val)        bfin_write32(EMAC_WKUP_FFMSK2, val)
+#define bfin_read_EMAC_WKUP_FFMSK3()            bfin_read32(EMAC_WKUP_FFMSK3)
+#define bfin_write_EMAC_WKUP_FFMSK3(val)        bfin_write32(EMAC_WKUP_FFMSK3, val)
+#define bfin_read_EMAC_WKUP_FFCMD()             bfin_read32(EMAC_WKUP_FFCMD)
+#define bfin_write_EMAC_WKUP_FFCMD(val)         bfin_write32(EMAC_WKUP_FFCMD, val)
+#define bfin_read_EMAC_WKUP_FFOFF()             bfin_read32(EMAC_WKUP_FFOFF)
+#define bfin_write_EMAC_WKUP_FFOFF(val)         bfin_write32(EMAC_WKUP_FFOFF, val)
+#define bfin_read_EMAC_WKUP_FFCRC0()            bfin_read32(EMAC_WKUP_FFCRC0)
+#define bfin_write_EMAC_WKUP_FFCRC0(val)        bfin_write32(EMAC_WKUP_FFCRC0, val)
+#define bfin_read_EMAC_WKUP_FFCRC1()            bfin_read32(EMAC_WKUP_FFCRC1)
+#define bfin_write_EMAC_WKUP_FFCRC1(val)        bfin_write32(EMAC_WKUP_FFCRC1, val)
+
+#define bfin_read_EMAC_SYSCTL()                 bfin_read32(EMAC_SYSCTL)
+#define bfin_write_EMAC_SYSCTL(val)             bfin_write32(EMAC_SYSCTL, val)
+#define bfin_read_EMAC_SYSTAT()                 bfin_read32(EMAC_SYSTAT)
+#define bfin_write_EMAC_SYSTAT(val)             bfin_write32(EMAC_SYSTAT, val)
+#define bfin_read_EMAC_RX_STAT()                bfin_read32(EMAC_RX_STAT)
+#define bfin_write_EMAC_RX_STAT(val)            bfin_write32(EMAC_RX_STAT, val)
+#define bfin_read_EMAC_RX_STKY()                bfin_read32(EMAC_RX_STKY)
+#define bfin_write_EMAC_RX_STKY(val)            bfin_write32(EMAC_RX_STKY, val)
+#define bfin_read_EMAC_RX_IRQE()                bfin_read32(EMAC_RX_IRQE)
+#define bfin_write_EMAC_RX_IRQE(val)            bfin_write32(EMAC_RX_IRQE, val)
+#define bfin_read_EMAC_TX_STAT()                bfin_read32(EMAC_TX_STAT)
+#define bfin_write_EMAC_TX_STAT(val)            bfin_write32(EMAC_TX_STAT, val)
+#define bfin_read_EMAC_TX_STKY()                bfin_read32(EMAC_TX_STKY)
+#define bfin_write_EMAC_TX_STKY(val)            bfin_write32(EMAC_TX_STKY, val)
+#define bfin_read_EMAC_TX_IRQE()                bfin_read32(EMAC_TX_IRQE)
+#define bfin_write_EMAC_TX_IRQE(val)            bfin_write32(EMAC_TX_IRQE, val)
+
+#define bfin_read_EMAC_MMC_CTL()                bfin_read32(EMAC_MMC_CTL)
+#define bfin_write_EMAC_MMC_CTL(val)            bfin_write32(EMAC_MMC_CTL, val)
+#define bfin_read_EMAC_MMC_RIRQS()              bfin_read32(EMAC_MMC_RIRQS)
+#define bfin_write_EMAC_MMC_RIRQS(val)          bfin_write32(EMAC_MMC_RIRQS, val)
+#define bfin_read_EMAC_MMC_RIRQE()              bfin_read32(EMAC_MMC_RIRQE)
+#define bfin_write_EMAC_MMC_RIRQE(val)          bfin_write32(EMAC_MMC_RIRQE, val)
+#define bfin_read_EMAC_MMC_TIRQS()              bfin_read32(EMAC_MMC_TIRQS)
+#define bfin_write_EMAC_MMC_TIRQS(val)          bfin_write32(EMAC_MMC_TIRQS, val)
+#define bfin_read_EMAC_MMC_TIRQE()              bfin_read32(EMAC_MMC_TIRQE)
+#define bfin_write_EMAC_MMC_TIRQE(val)          bfin_write32(EMAC_MMC_TIRQE, val)
+
+#define bfin_read_EMAC_RXC_OK()                 bfin_read32(EMAC_RXC_OK)
+#define bfin_write_EMAC_RXC_OK(val)             bfin_write32(EMAC_RXC_OK, val)
+#define bfin_read_EMAC_RXC_FCS()                bfin_read32(EMAC_RXC_FCS)
+#define bfin_write_EMAC_RXC_FCS(val)            bfin_write32(EMAC_RXC_FCS, val)
+#define bfin_read_EMAC_RXC_ALIGN()              bfin_read32(EMAC_RXC_ALIGN)
+#define bfin_write_EMAC_RXC_ALIGN(val)          bfin_write32(EMAC_RXC_ALIGN, val)
+#define bfin_read_EMAC_RXC_OCTET()              bfin_read32(EMAC_RXC_OCTET)
+#define bfin_write_EMAC_RXC_OCTET(val)          bfin_write32(EMAC_RXC_OCTET, val)
+#define bfin_read_EMAC_RXC_DMAOVF()             bfin_read32(EMAC_RXC_DMAOVF)
+#define bfin_write_EMAC_RXC_DMAOVF(val)         bfin_write32(EMAC_RXC_DMAOVF, val)
+#define bfin_read_EMAC_RXC_UNICST()             bfin_read32(EMAC_RXC_UNICST)
+#define bfin_write_EMAC_RXC_UNICST(val)         bfin_write32(EMAC_RXC_UNICST, val)
+#define bfin_read_EMAC_RXC_MULTI()              bfin_read32(EMAC_RXC_MULTI)
+#define bfin_write_EMAC_RXC_MULTI(val)          bfin_write32(EMAC_RXC_MULTI, val)
+#define bfin_read_EMAC_RXC_BROAD()              bfin_read32(EMAC_RXC_BROAD)
+#define bfin_write_EMAC_RXC_BROAD(val)          bfin_write32(EMAC_RXC_BROAD, val)
+#define bfin_read_EMAC_RXC_LNERRI()             bfin_read32(EMAC_RXC_LNERRI)
+#define bfin_write_EMAC_RXC_LNERRI(val)         bfin_write32(EMAC_RXC_LNERRI, val)
+#define bfin_read_EMAC_RXC_LNERRO()             bfin_read32(EMAC_RXC_LNERRO)
+#define bfin_write_EMAC_RXC_LNERRO(val)         bfin_write32(EMAC_RXC_LNERRO, val)
+#define bfin_read_EMAC_RXC_LONG()               bfin_read32(EMAC_RXC_LONG)
+#define bfin_write_EMAC_RXC_LONG(val)           bfin_write32(EMAC_RXC_LONG, val)
+#define bfin_read_EMAC_RXC_MACCTL()             bfin_read32(EMAC_RXC_MACCTL)
+#define bfin_write_EMAC_RXC_MACCTL(val)         bfin_write32(EMAC_RXC_MACCTL, val)
+#define bfin_read_EMAC_RXC_OPCODE()             bfin_read32(EMAC_RXC_OPCODE)
+#define bfin_write_EMAC_RXC_OPCODE(val)         bfin_write32(EMAC_RXC_OPCODE, val)
+#define bfin_read_EMAC_RXC_PAUSE()              bfin_read32(EMAC_RXC_PAUSE)
+#define bfin_write_EMAC_RXC_PAUSE(val)          bfin_write32(EMAC_RXC_PAUSE, val)
+#define bfin_read_EMAC_RXC_ALLFRM()             bfin_read32(EMAC_RXC_ALLFRM)
+#define bfin_write_EMAC_RXC_ALLFRM(val)         bfin_write32(EMAC_RXC_ALLFRM, val)
+#define bfin_read_EMAC_RXC_ALLOCT()             bfin_read32(EMAC_RXC_ALLOCT)
+#define bfin_write_EMAC_RXC_ALLOCT(val)         bfin_write32(EMAC_RXC_ALLOCT, val)
+#define bfin_read_EMAC_RXC_TYPED()              bfin_read32(EMAC_RXC_TYPED)
+#define bfin_write_EMAC_RXC_TYPED(val)          bfin_write32(EMAC_RXC_TYPED, val)
+#define bfin_read_EMAC_RXC_SHORT()              bfin_read32(EMAC_RXC_SHORT)
+#define bfin_write_EMAC_RXC_SHORT(val)          bfin_write32(EMAC_RXC_SHORT, val)
+#define bfin_read_EMAC_RXC_EQ64()               bfin_read32(EMAC_RXC_EQ64)
+#define bfin_write_EMAC_RXC_EQ64(val)           bfin_write32(EMAC_RXC_EQ64, val)
+#define bfin_read_EMAC_RXC_LT128()              bfin_read32(EMAC_RXC_LT128)
+#define bfin_write_EMAC_RXC_LT128(val)          bfin_write32(EMAC_RXC_LT128, val)
+#define bfin_read_EMAC_RXC_LT256()              bfin_read32(EMAC_RXC_LT256)
+#define bfin_write_EMAC_RXC_LT256(val)          bfin_write32(EMAC_RXC_LT256, val)
+#define bfin_read_EMAC_RXC_LT512()              bfin_read32(EMAC_RXC_LT512)
+#define bfin_write_EMAC_RXC_LT512(val)          bfin_write32(EMAC_RXC_LT512, val)
+#define bfin_read_EMAC_RXC_LT1024()             bfin_read32(EMAC_RXC_LT1024)
+#define bfin_write_EMAC_RXC_LT1024(val)         bfin_write32(EMAC_RXC_LT1024, val)
+#define bfin_read_EMAC_RXC_GE1024()             bfin_read32(EMAC_RXC_GE1024)
+#define bfin_write_EMAC_RXC_GE1024(val)         bfin_write32(EMAC_RXC_GE1024, val)
+
+#define bfin_read_EMAC_TXC_OK()                 bfin_read32(EMAC_TXC_OK)
+#define bfin_write_EMAC_TXC_OK(val)             bfin_write32(EMAC_TXC_OK, val)
+#define bfin_read_EMAC_TXC_1COL()               bfin_read32(EMAC_TXC_1COL)
+#define bfin_write_EMAC_TXC_1COL(val)           bfin_write32(EMAC_TXC_1COL, val)
+#define bfin_read_EMAC_TXC_GT1COL()             bfin_read32(EMAC_TXC_GT1COL)
+#define bfin_write_EMAC_TXC_GT1COL(val)         bfin_write32(EMAC_TXC_GT1COL, val)
+#define bfin_read_EMAC_TXC_OCTET()              bfin_read32(EMAC_TXC_OCTET)
+#define bfin_write_EMAC_TXC_OCTET(val)          bfin_write32(EMAC_TXC_OCTET, val)
+#define bfin_read_EMAC_TXC_DEFER()              bfin_read32(EMAC_TXC_DEFER)
+#define bfin_write_EMAC_TXC_DEFER(val)          bfin_write32(EMAC_TXC_DEFER, val)
+#define bfin_read_EMAC_TXC_LATECL()             bfin_read32(EMAC_TXC_LATECL)
+#define bfin_write_EMAC_TXC_LATECL(val)         bfin_write32(EMAC_TXC_LATECL, val)
+#define bfin_read_EMAC_TXC_XS_COL()             bfin_read32(EMAC_TXC_XS_COL)
+#define bfin_write_EMAC_TXC_XS_COL(val)         bfin_write32(EMAC_TXC_XS_COL, val)
+#define bfin_read_EMAC_TXC_DMAUND()             bfin_read32(EMAC_TXC_DMAUND)
+#define bfin_write_EMAC_TXC_DMAUND(val)         bfin_write32(EMAC_TXC_DMAUND, val)
+#define bfin_read_EMAC_TXC_CRSERR()             bfin_read32(EMAC_TXC_CRSERR)
+#define bfin_write_EMAC_TXC_CRSERR(val)         bfin_write32(EMAC_TXC_CRSERR, val)
+#define bfin_read_EMAC_TXC_UNICST()             bfin_read32(EMAC_TXC_UNICST)
+#define bfin_write_EMAC_TXC_UNICST(val)         bfin_write32(EMAC_TXC_UNICST, val)
+#define bfin_read_EMAC_TXC_MULTI()              bfin_read32(EMAC_TXC_MULTI)
+#define bfin_write_EMAC_TXC_MULTI(val)          bfin_write32(EMAC_TXC_MULTI, val)
+#define bfin_read_EMAC_TXC_BROAD()              bfin_read32(EMAC_TXC_BROAD)
+#define bfin_write_EMAC_TXC_BROAD(val)          bfin_write32(EMAC_TXC_BROAD, val)
+#define bfin_read_EMAC_TXC_XS_DFR()             bfin_read32(EMAC_TXC_XS_DFR)
+#define bfin_write_EMAC_TXC_XS_DFR(val)         bfin_write32(EMAC_TXC_XS_DFR, val)
+#define bfin_read_EMAC_TXC_MACCTL()             bfin_read32(EMAC_TXC_MACCTL)
+#define bfin_write_EMAC_TXC_MACCTL(val)         bfin_write32(EMAC_TXC_MACCTL, val)
+#define bfin_read_EMAC_TXC_ALLFRM()             bfin_read32(EMAC_TXC_ALLFRM)
+#define bfin_write_EMAC_TXC_ALLFRM(val)         bfin_write32(EMAC_TXC_ALLFRM, val)
+#define bfin_read_EMAC_TXC_ALLOCT()             bfin_read32(EMAC_TXC_ALLOCT)
+#define bfin_write_EMAC_TXC_ALLOCT(val)         bfin_write32(EMAC_TXC_ALLOCT, val)
+#define bfin_read_EMAC_TXC_EQ64()               bfin_read32(EMAC_TXC_EQ64)
+#define bfin_write_EMAC_TXC_EQ64(val)           bfin_write32(EMAC_TXC_EQ64, val)
+#define bfin_read_EMAC_TXC_LT128()              bfin_read32(EMAC_TXC_LT128)
+#define bfin_write_EMAC_TXC_LT128(val)          bfin_write32(EMAC_TXC_LT128, val)
+#define bfin_read_EMAC_TXC_LT256()              bfin_read32(EMAC_TXC_LT256)
+#define bfin_write_EMAC_TXC_LT256(val)          bfin_write32(EMAC_TXC_LT256, val)
+#define bfin_read_EMAC_TXC_LT512()              bfin_read32(EMAC_TXC_LT512)
+#define bfin_write_EMAC_TXC_LT512(val)          bfin_write32(EMAC_TXC_LT512, val)
+#define bfin_read_EMAC_TXC_LT1024()             bfin_read32(EMAC_TXC_LT1024)
+#define bfin_write_EMAC_TXC_LT1024(val)         bfin_write32(EMAC_TXC_LT1024, val)
+#define bfin_read_EMAC_TXC_GE1024()             bfin_read32(EMAC_TXC_GE1024)
+#define bfin_write_EMAC_TXC_GE1024(val)         bfin_write32(EMAC_TXC_GE1024, val)
+#define bfin_read_EMAC_TXC_ABORT()              bfin_read32(EMAC_TXC_ABORT)
+#define bfin_write_EMAC_TXC_ABORT(val)          bfin_write32(EMAC_TXC_ABORT, val)
+
+/* USB Control Registers */
+
+#define bfin_read_USB_FADDR()                   bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)               bfin_write16(USB_FADDR, val)
+#define bfin_read_USB_POWER()                   bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)               bfin_write16(USB_POWER, val)
+#define bfin_read_USB_INTRTX()                  bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)              bfin_write16(USB_INTRTX, val)
+#define bfin_read_USB_INTRRX()                  bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)              bfin_write16(USB_INTRRX, val)
+#define bfin_read_USB_INTRTXE()                 bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)             bfin_write16(USB_INTRTXE, val)
+#define bfin_read_USB_INTRRXE()                 bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)             bfin_write16(USB_INTRRXE, val)
+#define bfin_read_USB_INTRUSB()                 bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)             bfin_write16(USB_INTRUSB, val)
+#define bfin_read_USB_INTRUSBE()                bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)            bfin_write16(USB_INTRUSBE, val)
+#define bfin_read_USB_FRAME()                   bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)               bfin_write16(USB_FRAME, val)
+#define bfin_read_USB_INDEX()                   bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)               bfin_write16(USB_INDEX, val)
+#define bfin_read_USB_TESTMODE()                bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)            bfin_write16(USB_TESTMODE, val)
+#define bfin_read_USB_GLOBINTR()                bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)            bfin_write16(USB_GLOBINTR, val)
+#define bfin_read_USB_GLOBAL_CTL()              bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
+
+/* USB Packet Control Registers */
+
+#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
+#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
+#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
+#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
+#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
+#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
+#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
+#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
+#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
+#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
+#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
+#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
+#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
+
+/* USB Endpoint FIFO Registers */
+
+#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
+#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
+#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
+#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
+#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
+#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
+#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
+#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
+
+/* USB OTG Control Registers */
+
+#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
+#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
+
+/* USB Phy Control Registers */
+
+#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
+#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
+#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
+#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
+#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
+
+#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
+
+#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
+#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
+
+/* USB Endpoint 0 Control Registers */
+
+#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
+#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
+#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
+
+/* USB Endpoint 1 Control Registers */
+
+#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
+#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
+#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
+
+/* USB Endpoint 2 Control Registers */
+
+#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
+#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
+#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
+
+/* USB Endpoint 3 Control Registers */
+
+#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
+#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
+#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
+
+/* USB Endpoint 4 Control Registers */
+
+#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
+#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
+#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
+
+/* USB Endpoint 5 Control Registers */
+
+#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
+#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
+#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
+
+/* USB Endpoint 6 Control Registers */
+
+#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
+#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
+#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
+
+/* USB Endpoint 7 Control Registers */
+
+#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
+#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
+#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
+
+#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
+
+/* USB Channel 0 Config Registers */
+
+#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
+#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
+#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
+#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
+#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
+#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
+#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
+#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
+#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
+#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
+
+/* USB Channel 1 Config Registers */
+
+#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
+#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
+#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
+#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
+#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
+#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
+#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
+#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
+#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
+#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
+
+/* USB Channel 2 Config Registers */
+
+#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
+#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
+#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
+#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
+#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
+#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
+#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
+#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
+#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
+#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
+
+/* USB Channel 3 Config Registers */
+
+#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
+#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
+#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
+#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
+#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
+#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
+#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
+#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
+#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
+#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
+
+/* USB Channel 4 Config Registers */
+
+#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
+#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
+#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
+#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
+#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
+#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
+#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
+#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
+#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
+#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
+
+/* USB Channel 5 Config Registers */
+
+#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
+#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
+#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
+#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
+#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
+#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
+#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
+#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
+#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
+#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
+
+/* USB Channel 6 Config Registers */
+
+#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
+#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
+#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
+#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
+#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
+#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
+#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
+#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
+#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
+#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
+
+/* USB Channel 7 Config Registers */
+
+#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
+#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
+#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
+#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
+#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
+#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
+#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
+#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
+#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
+#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
+
+#endif /* _CDEF_BF527_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
new file mode 100644
index 000000000000..5f801a0ef797
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -0,0 +1,1187 @@
+/*
+ * File:         include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF52X_H
+
+#include "defBF52x_base.h"
+
+/* ==== begin from cdefBF534.h ==== */
+
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)                 bfin_write16(PLL_CTL, val)
+#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)                  bfin_write16(VR_CTL, val)
+#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID()                      bfin_read16(CHIPID)
+#define bfin_write_CHIPID(val)                  bfin_write16(CHIPID, val)
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define bfin_read_SWRST()                       bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
+#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
+
+#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
+#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
+/* legacy register name (below) provided for backwards code compatibility */
+#define bfin_read_SIC_IMASK()                   bfin_read32(SIC_IMASK)
+#define bfin_write_SIC_IMASK(val)               bfin_write32(SIC_IMASK, val)
+
+#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
+
+#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
+/* legacy register name (below) provided for backwards code compatibility */
+#define bfin_read_SIC_ISR()                     bfin_read32(SIC_ISR)
+#define bfin_write_SIC_ISR(val)                 bfin_write32(SIC_ISR, val)
+
+#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
+/* legacy register name (below) provided for backwards code compatibility */
+#define bfin_read_SIC_IWR()                     bfin_read32(SIC_IWR)
+#define bfin_write_SIC_IWR(val)                 bfin_write32(SIC_IWR, val)
+
+/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
+
+#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
+#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
+#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
+
+/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
+#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
+#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
+#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
+#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
+#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
+#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
+#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
+
+
+/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
+#define bfin_read_SPI_CTL()                     bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)                 bfin_write16(SPI_CTL, val)
+#define bfin_read_SPI_FLG()                     bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)                 bfin_write16(SPI_FLG, val)
+#define bfin_read_SPI_STAT()                    bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)                bfin_write16(SPI_STAT, val)
+#define bfin_read_SPI_TDBR()                    bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)                bfin_write16(SPI_TDBR, val)
+#define bfin_read_SPI_RDBR()                    bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)                bfin_write16(SPI_RDBR, val)
+#define bfin_read_SPI_BAUD()                    bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)                bfin_write16(SPI_BAUD, val)
+#define bfin_read_SPI_SHADOW()                  bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)              bfin_write16(SPI_SHADOW, val)
+
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
+
+#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
+
+#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
+
+#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
+
+#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
+
+#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
+
+#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
+
+#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
+
+#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
+#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
+#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
+#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
+#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
+#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
+#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
+#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
+#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
+#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
+#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
+
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
+#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX32)
+#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX32, val)
+#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX32)
+#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX32, val)
+#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX16)
+#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX16, val)
+#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX16)
+#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX16, val)
+#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
+
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
+#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX32)
+#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX32, val)
+#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX32)
+#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX32, val)
+#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX16)
+#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX16, val)
+#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX16)
+#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX16, val)
+#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
+#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
+
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define bfin_read_DMA_TC_PER()                  bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)              bfin_write16(DMA_TC_PER, val)
+#define bfin_read_DMA_TC_CNT()                  bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)              bfin_write16(DMA_TC_CNT, val)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define bfin_read_DMA_TCPER()                   bfin_read16(DMA_TCPER)
+#define bfin_write_DMA_TCPER(val)               bfin_write16(DMA_TCPER, val)
+#define bfin_read_DMA_TCCNT()                   bfin_read16(DMA_TCCNT)
+#define bfin_write_DMA_TCCNT(val)               bfin_write16(DMA_TCCNT, val)
+
+/* DMA Controller                                                                                                                                       */
+#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
+#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
+#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
+#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
+#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
+#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
+#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
+#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
+#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
+#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
+#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
+#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
+#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
+#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
+#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
+#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
+#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
+#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
+#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
+#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
+#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
+#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
+#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
+#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
+#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
+#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
+#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
+#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
+#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
+#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
+#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
+#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
+#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
+#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
+#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
+#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
+#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
+#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define bfin_read_TWI_CLKDIV()                  bfin_read16(TWI_CLKDIV)
+#define bfin_write_TWI_CLKDIV(val)              bfin_write16(TWI_CLKDIV, val)
+#define bfin_read_TWI_CONTROL()                 bfin_read16(TWI_CONTROL)
+#define bfin_write_TWI_CONTROL(val)             bfin_write16(TWI_CONTROL, val)
+#define bfin_read_TWI_SLAVE_CTL()               bfin_read16(TWI_SLAVE_CTL)
+#define bfin_write_TWI_SLAVE_CTL(val)           bfin_write16(TWI_SLAVE_CTL, val)
+#define bfin_read_TWI_SLAVE_STAT()              bfin_read16(TWI_SLAVE_STAT)
+#define bfin_write_TWI_SLAVE_STAT(val)          bfin_write16(TWI_SLAVE_STAT, val)
+#define bfin_read_TWI_SLAVE_ADDR()              bfin_read16(TWI_SLAVE_ADDR)
+#define bfin_write_TWI_SLAVE_ADDR(val)          bfin_write16(TWI_SLAVE_ADDR, val)
+#define bfin_read_TWI_MASTER_CTL()              bfin_read16(TWI_MASTER_CTL)
+#define bfin_write_TWI_MASTER_CTL(val)          bfin_write16(TWI_MASTER_CTL, val)
+#define bfin_read_TWI_MASTER_STAT()             bfin_read16(TWI_MASTER_STAT)
+#define bfin_write_TWI_MASTER_STAT(val)         bfin_write16(TWI_MASTER_STAT, val)
+#define bfin_read_TWI_MASTER_ADDR()             bfin_read16(TWI_MASTER_ADDR)
+#define bfin_write_TWI_MASTER_ADDR(val)         bfin_write16(TWI_MASTER_ADDR, val)
+#define bfin_read_TWI_INT_STAT()                bfin_read16(TWI_INT_STAT)
+#define bfin_write_TWI_INT_STAT(val)            bfin_write16(TWI_INT_STAT, val)
+#define bfin_read_TWI_INT_MASK()                bfin_read16(TWI_INT_MASK)
+#define bfin_write_TWI_INT_MASK(val)            bfin_write16(TWI_INT_MASK, val)
+#define bfin_read_TWI_FIFO_CTL()                bfin_read16(TWI_FIFO_CTL)
+#define bfin_write_TWI_FIFO_CTL(val)            bfin_write16(TWI_FIFO_CTL, val)
+#define bfin_read_TWI_FIFO_STAT()               bfin_read16(TWI_FIFO_STAT)
+#define bfin_write_TWI_FIFO_STAT(val)           bfin_write16(TWI_FIFO_STAT, val)
+#define bfin_read_TWI_XMT_DATA8()               bfin_read16(TWI_XMT_DATA8)
+#define bfin_write_TWI_XMT_DATA8(val)           bfin_write16(TWI_XMT_DATA8, val)
+#define bfin_read_TWI_XMT_DATA16()              bfin_read16(TWI_XMT_DATA16)
+#define bfin_write_TWI_XMT_DATA16(val)          bfin_write16(TWI_XMT_DATA16, val)
+#define bfin_read_TWI_RCV_DATA8()               bfin_read16(TWI_RCV_DATA8)
+#define bfin_write_TWI_RCV_DATA8(val)           bfin_write16(TWI_RCV_DATA8, val)
+#define bfin_read_TWI_RCV_DATA16()              bfin_read16(TWI_RCV_DATA16)
+#define bfin_write_TWI_RCV_DATA16(val)          bfin_write16(TWI_RCV_DATA16, val)
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
+#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
+#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
+#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
+#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
+#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
+#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
+#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
+#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
+#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
+#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
+#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
+#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
+#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
+#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
+#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
+#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
+#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
+#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
+#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
+#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
+#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
+#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
+#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
+#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
+#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
+#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
+#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
+#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
+#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
+#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
+#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
+#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
+#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
+#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
+#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
+#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
+#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
+#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
+#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
+
+/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
+#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
+#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
+#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
+#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
+#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
+#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
+
+#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
+
+/* ==== end from cdefBF534.h ==== */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+
+#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
+#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
+#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
+
+#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
+#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
+#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
+#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
+#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
+#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
+#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
+#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
+#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
+#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
+#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
+#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
+#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
+#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
+#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
+#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
+#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
+#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
+#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
+#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
+#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
+#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
+#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
+
+/* HOST Port Registers */
+
+#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
+#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
+#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
+
+/* Counter Registers */
+
+#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
+#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
+#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
+#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
+#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
+#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
+#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
+#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
+
+/* OTP/FUSE Registers */
+
+#define bfin_read_OTP_CONTROL()                 bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)             bfin_write16(OTP_CONTROL, val)
+#define bfin_read_OTP_BEN()                     bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)                 bfin_write16(OTP_BEN, val)
+#define bfin_read_OTP_STATUS()                  bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)              bfin_write16(OTP_STATUS, val)
+#define bfin_read_OTP_TIMING()                  bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)              bfin_write32(OTP_TIMING, val)
+
+/* Security Registers */
+
+#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
+#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
+#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define bfin_read_OTP_DATA0()                   bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)               bfin_write32(OTP_DATA0, val)
+#define bfin_read_OTP_DATA1()                   bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)               bfin_write32(OTP_DATA1, val)
+#define bfin_read_OTP_DATA2()                   bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)               bfin_write32(OTP_DATA2, val)
+#define bfin_read_OTP_DATA3()                   bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)               bfin_write32(OTP_DATA3, val)
+
+/* NFC Registers */
+
+#define bfin_read_NFC_CTL()                     bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)                 bfin_write16(NFC_CTL, val)
+#define bfin_read_NFC_STAT()                    bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)                bfin_write16(NFC_STAT, val)
+#define bfin_read_NFC_IRQSTAT()                 bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)             bfin_write16(NFC_IRQSTAT, val)
+#define bfin_read_NFC_IRQMASK()                 bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)             bfin_write16(NFC_IRQMASK, val)
+#define bfin_read_NFC_ECC0()                    bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)                bfin_write16(NFC_ECC0, val)
+#define bfin_read_NFC_ECC1()                    bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)                bfin_write16(NFC_ECC1, val)
+#define bfin_read_NFC_ECC2()                    bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)                bfin_write16(NFC_ECC2, val)
+#define bfin_read_NFC_ECC3()                    bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)                bfin_write16(NFC_ECC3, val)
+#define bfin_read_NFC_COUNT()                   bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)               bfin_write16(NFC_COUNT, val)
+#define bfin_read_NFC_RST()                     bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)                 bfin_write16(NFC_RST, val)
+#define bfin_read_NFC_PGCTL()                   bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)               bfin_write16(NFC_PGCTL, val)
+#define bfin_read_NFC_READ()                    bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)                bfin_write16(NFC_READ, val)
+#define bfin_read_NFC_ADDR()                    bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)                bfin_write16(NFC_ADDR, val)
+#define bfin_read_NFC_CMD()                     bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)                 bfin_write16(NFC_CMD, val)
+#define bfin_read_NFC_DATA_WR()                 bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)             bfin_write16(NFC_DATA_WR, val)
+#define bfin_read_NFC_DATA_RD()                 bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)             bfin_write16(NFC_DATA_RD, val)
+
+#endif /* _CDEF_BF52X_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF522.h b/include/asm-blackfin/mach-bf527/defBF522.h
new file mode 100644
index 000000000000..9671d8f2c5ef
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF522.h
@@ -0,0 +1,42 @@
+/*
+ * File:         include/asm-blackfin/mach-bf527/defBF522.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF522_H
+#define _DEF_BF522_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
+
+/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include "defBF52x_base.h"
+
+#endif /* _DEF_BF522_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF525.h b/include/asm-blackfin/mach-bf527/defBF525.h
new file mode 100644
index 000000000000..6a375a084acc
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF525.h
@@ -0,0 +1,713 @@
+/*
+ * File:         include/asm-blackfin/mach-bf527/defBF525.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF525_H
+#define _DEF_BF525_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
+
+/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include "defBF52x_base.h"
+
+/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
+
+/* USB Control Registers */
+
+#define                        USB_FADDR  0xffc03800   /* Function address register */
+#define                        USB_POWER  0xffc03804   /* Power management register */
+#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
+#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
+#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
+#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
+#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
+#define                        USB_FRAME  0xffc03820   /* USB frame number */
+#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
+#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
+#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
+#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
+#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
+#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
+#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
+#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
+#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
+#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
+#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
+#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
+#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
+#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
+#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
+#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
+#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
+#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
+#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
+
+#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
+
+#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
+#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
+#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
+#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
+#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
+#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
+#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
+#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
+
+/* USB Endpoint 1 Control Registers */
+
+#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
+#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
+#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
+#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
+#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
+#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
+#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+
+/* USB Endpoint 2 Control Registers */
+
+#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
+#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
+#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
+#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
+#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
+#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
+#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
+
+/* USB Endpoint 3 Control Registers */
+
+#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
+#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
+#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
+#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
+#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
+#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
+#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+
+/* USB Endpoint 4 Control Registers */
+
+#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
+#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
+#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
+#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
+#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
+#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
+#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
+
+/* USB Endpoint 5 Control Registers */
+
+#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
+#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
+#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
+#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
+#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
+#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
+#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
+
+/* USB Endpoint 6 Control Registers */
+
+#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
+#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
+#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
+#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
+#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
+#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
+#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
+
+/* USB Endpoint 7 Control Registers */
+
+#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
+#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
+#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
+#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
+#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
+#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
+#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
+
+#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
+#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
+#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
+#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
+#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
+#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
+#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
+#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
+#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Bit masks for USB_FADDR */
+
+#define          FUNCTION_ADDRESS  0x7f       /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
+#define          nENABLE_SUSPENDM  0x0       
+#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
+#define             nSUSPEND_MODE  0x0       
+#define               RESUME_MODE  0x4        /* DMA Mode */
+#define              nRESUME_MODE  0x0       
+#define                     RESET  0x8        /* Reset indicator */
+#define                    nRESET  0x0       
+#define                   HS_MODE  0x10       /* High Speed mode indicator */
+#define                  nHS_MODE  0x0       
+#define                 HS_ENABLE  0x20       /* high Speed Enable */
+#define                nHS_ENABLE  0x0       
+#define                 SOFT_CONN  0x40       /* Soft connect */
+#define                nSOFT_CONN  0x0       
+#define                ISO_UPDATE  0x80       /* Isochronous update */
+#define               nISO_UPDATE  0x0       
+
+/* Bit masks for USB_INTRTX */
+
+#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
+#define                   nEP0_TX  0x0       
+#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
+#define                   nEP1_TX  0x0       
+#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
+#define                   nEP2_TX  0x0       
+#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
+#define                   nEP3_TX  0x0       
+#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
+#define                   nEP4_TX  0x0       
+#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
+#define                   nEP5_TX  0x0       
+#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
+#define                   nEP6_TX  0x0       
+#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
+#define                   nEP7_TX  0x0       
+
+/* Bit masks for USB_INTRRX */
+
+#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
+#define                   nEP1_RX  0x0       
+#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
+#define                   nEP2_RX  0x0       
+#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
+#define                   nEP3_RX  0x0       
+#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
+#define                   nEP4_RX  0x0       
+#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
+#define                   nEP5_RX  0x0       
+#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
+#define                   nEP6_RX  0x0       
+#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
+#define                   nEP7_RX  0x0       
+
+/* Bit masks for USB_INTRTXE */
+
+#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
+#define                 nEP0_TX_E  0x0       
+#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
+#define                 nEP1_TX_E  0x0       
+#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
+#define                 nEP2_TX_E  0x0       
+#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
+#define                 nEP3_TX_E  0x0       
+#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
+#define                 nEP4_TX_E  0x0       
+#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
+#define                 nEP5_TX_E  0x0       
+#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
+#define                 nEP6_TX_E  0x0       
+#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
+#define                 nEP7_TX_E  0x0       
+
+/* Bit masks for USB_INTRRXE */
+
+#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
+#define                 nEP1_RX_E  0x0       
+#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
+#define                 nEP2_RX_E  0x0       
+#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
+#define                 nEP3_RX_E  0x0       
+#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
+#define                 nEP4_RX_E  0x0       
+#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
+#define                 nEP5_RX_E  0x0       
+#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
+#define                 nEP6_RX_E  0x0       
+#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
+#define                 nEP7_RX_E  0x0       
+
+/* Bit masks for USB_INTRUSB */
+
+#define                 SUSPEND_B  0x1        /* Suspend indicator */
+#define                nSUSPEND_B  0x0       
+#define                  RESUME_B  0x2        /* Resume indicator */
+#define                 nRESUME_B  0x0       
+#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
+#define         nRESET_OR_BABLE_B  0x0       
+#define                     SOF_B  0x8        /* Start of frame */
+#define                    nSOF_B  0x0       
+#define                    CONN_B  0x10       /* Connection indicator */
+#define                   nCONN_B  0x0       
+#define                  DISCON_B  0x20       /* Disconnect indicator */
+#define                 nDISCON_B  0x0       
+#define             SESSION_REQ_B  0x40       /* Session Request */
+#define            nSESSION_REQ_B  0x0       
+#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
+#define             nVBUS_ERROR_B  0x0       
+
+/* Bit masks for USB_INTRUSBE */
+
+#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
+#define               nSUSPEND_BE  0x0       
+#define                 RESUME_BE  0x2        /* Resume indicator int enable */
+#define                nRESUME_BE  0x0       
+#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
+#define        nRESET_OR_BABLE_BE  0x0       
+#define                    SOF_BE  0x8        /* Start of frame int enable */
+#define                   nSOF_BE  0x0       
+#define                   CONN_BE  0x10       /* Connection indicator int enable */
+#define                  nCONN_BE  0x0       
+#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
+#define                nDISCON_BE  0x0       
+#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
+#define           nSESSION_REQ_BE  0x0       
+#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
+#define            nVBUS_ERROR_BE  0x0       
+
+/* Bit masks for USB_FRAME */
+
+#define              FRAME_NUMBER  0x7ff      /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define                GLOBAL_ENA  0x1        /* enables USB module */
+#define               nGLOBAL_ENA  0x0       
+#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
+#define               nEP1_TX_ENA  0x0       
+#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
+#define               nEP2_TX_ENA  0x0       
+#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
+#define               nEP3_TX_ENA  0x0       
+#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
+#define               nEP4_TX_ENA  0x0       
+#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
+#define               nEP5_TX_ENA  0x0       
+#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
+#define               nEP6_TX_ENA  0x0       
+#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
+#define               nEP7_TX_ENA  0x0       
+#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
+#define               nEP1_RX_ENA  0x0       
+#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
+#define               nEP2_RX_ENA  0x0       
+#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
+#define               nEP3_RX_ENA  0x0       
+#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
+#define               nEP4_RX_ENA  0x0       
+#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
+#define               nEP5_RX_ENA  0x0       
+#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
+#define               nEP6_RX_ENA  0x0       
+#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
+#define               nEP7_RX_ENA  0x0       
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define                   SESSION  0x1        /* session indicator */
+#define                  nSESSION  0x0       
+#define                  HOST_REQ  0x2        /* Host negotiation request */
+#define                 nHOST_REQ  0x0       
+#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
+#define                nHOST_MODE  0x0       
+#define                     VBUS0  0x8        /* Vbus level indicator[0] */
+#define                    nVBUS0  0x0       
+#define                     VBUS1  0x10       /* Vbus level indicator[1] */
+#define                    nVBUS1  0x0       
+#define                     LSDEV  0x20       /* Low-speed indicator */
+#define                    nLSDEV  0x0       
+#define                     FSDEV  0x40       /* Full or High-speed indicator */
+#define                    nFSDEV  0x0       
+#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
+#define                 nB_DEVICE  0x0       
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
+#define            nDRIVE_VBUS_ON  0x0       
+#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
+#define           nDRIVE_VBUS_OFF  0x0       
+#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
+#define          nCHRG_VBUS_START  0x0       
+#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
+#define            nCHRG_VBUS_END  0x0       
+#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
+#define       nDISCHRG_VBUS_START  0x0       
+#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
+#define         nDISCHRG_VBUS_END  0x0       
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
+#define        nDRIVE_VBUS_ON_ENA  0x0       
+#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
+#define       nDRIVE_VBUS_OFF_ENA  0x0       
+#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
+#define      nCHRG_VBUS_START_ENA  0x0       
+#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
+#define        nCHRG_VBUS_END_ENA  0x0       
+#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
+#define   nDISCHRG_VBUS_START_ENA  0x0       
+#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
+#define     nDISCHRG_VBUS_END_ENA  0x0       
+
+/* Bit masks for USB_CSR0 */
+
+#define                  RXPKTRDY  0x1        /* data packet receive indicator */
+#define                 nRXPKTRDY  0x0       
+#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
+#define                 nTXPKTRDY  0x0       
+#define                STALL_SENT  0x4        /* STALL handshake sent */
+#define               nSTALL_SENT  0x0       
+#define                   DATAEND  0x8        /* Data end indicator */
+#define                  nDATAEND  0x0       
+#define                  SETUPEND  0x10       /* Setup end */
+#define                 nSETUPEND  0x0       
+#define                 SENDSTALL  0x20       /* Send STALL handshake */
+#define                nSENDSTALL  0x0       
+#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
+#define        nSERVICED_RXPKTRDY  0x0       
+#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
+#define        nSERVICED_SETUPEND  0x0       
+#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
+#define                nFLUSHFIFO  0x0       
+#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
+#define         nSTALL_RECEIVED_H  0x0       
+#define                SETUPPKT_H  0x8        /* send Setup token host mode */
+#define               nSETUPPKT_H  0x0       
+#define                   ERROR_H  0x10       /* timeout error indicator host mode */
+#define                  nERROR_H  0x0       
+#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
+#define                 nREQPKT_H  0x0       
+#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
+#define              nSTATUSPKT_H  0x0       
+#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
+#define            nNAK_TIMEOUT_H  0x0       
+
+/* Bit masks for USB_COUNT0 */
+
+#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
+#define               nTXPKTRDY_T  0x0       
+#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
+#define         nFIFO_NOT_EMPTY_T  0x0       
+#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
+#define               nUNDERRUN_T  0x0       
+#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
+#define              nFLUSHFIFO_T  0x0       
+#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
+#define             nSTALL_SEND_T  0x0       
+#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
+#define             nSTALL_SENT_T  0x0       
+#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
+#define       nCLEAR_DATATOGGLE_T  0x0       
+#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
+#define               nINCOMPTX_T  0x0       
+#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
+#define             nDMAREQMODE_T  0x0       
+#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
+#define       nFORCE_DATATOGGLE_T  0x0       
+#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
+#define             nDMAREQ_ENA_T  0x0       
+#define                     ISO_T  0x4000     /* enable Isochronous transfers */
+#define                    nISO_T  0x0       
+#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
+#define                nAUTOSET_T  0x0       
+#define                  ERROR_TH  0x4        /* error condition host mode */
+#define                 nERROR_TH  0x0       
+#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
+#define        nSTALL_RECEIVED_TH  0x0       
+#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
+#define           nNAK_TIMEOUT_TH  0x0       
+
+/* Bit masks for USB_TXCOUNT */
+
+#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
+#define               nRXPKTRDY_R  0x0       
+#define               FIFO_FULL_R  0x2        /* FIFO not empty */
+#define              nFIFO_FULL_R  0x0       
+#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
+#define                nOVERRUN_R  0x0       
+#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
+#define              nDATAERROR_R  0x0       
+#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
+#define              nFLUSHFIFO_R  0x0       
+#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
+#define             nSTALL_SEND_R  0x0       
+#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
+#define             nSTALL_SENT_R  0x0       
+#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
+#define       nCLEAR_DATATOGGLE_R  0x0       
+#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
+#define               nINCOMPRX_R  0x0       
+#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
+#define             nDMAREQMODE_R  0x0       
+#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
+#define                nDISNYET_R  0x0       
+#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
+#define             nDMAREQ_ENA_R  0x0       
+#define                     ISO_R  0x4000     /* enable Isochronous transfers */
+#define                    nISO_R  0x0       
+#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
+#define              nAUTOCLEAR_R  0x0       
+#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
+#define                 nERROR_RH  0x0       
+#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
+#define                nREQPKT_RH  0x0       
+#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
+#define        nSTALL_RECEIVED_RH  0x0       
+#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
+#define              nINCOMPRX_RH  0x0       
+#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
+#define            nDMAREQMODE_RH  0x0       
+#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
+#define               nAUTOREQ_RH  0x0       
+
+/* Bit masks for USB_RXCOUNT */
+
+#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define            TARGET_EP_NO_T  0xf        /* EP number */
+#define                PROTOCOL_T  0xc        /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define            TARGET_EP_NO_R  0xf        /* EP number */
+#define                PROTOCOL_R  0xc        /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
+#define                 nDMA0_INT  0x0       
+#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
+#define                 nDMA1_INT  0x0       
+#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
+#define                 nDMA2_INT  0x0       
+#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
+#define                 nDMA3_INT  0x0       
+#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
+#define                 nDMA4_INT  0x0       
+#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
+#define                 nDMA5_INT  0x0       
+#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
+#define                 nDMA6_INT  0x0       
+#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
+#define                 nDMA7_INT  0x0       
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define                   DMA_ENA  0x1        /* DMA enable */
+#define                  nDMA_ENA  0x0       
+#define                 DIRECTION  0x2        /* direction of DMA transfer */
+#define                nDIRECTION  0x0       
+#define                      MODE  0x4        /* DMA Bus error */
+#define                     nMODE  0x0       
+#define                   INT_ENA  0x8        /* Interrupt enable */
+#define                  nINT_ENA  0x0       
+#define                     EPNUM  0xf0       /* EP number */
+#define                  BUSERROR  0x100      /* DMA Bus error */
+#define                 nBUSERROR  0x0       
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+#endif /* _DEF_BF525_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF527.h b/include/asm-blackfin/mach-bf527/defBF527.h
new file mode 100644
index 000000000000..2be3293f9e26
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF527.h
@@ -0,0 +1,1089 @@
+/*
+ * File:         include/asm-blackfin/mach-bf527/defBF527.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF527_H
+#define _DEF_BF527_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
+
+/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <defBF52x_base.h>
+
+/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
+/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
+
+#define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
+#define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
+#define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
+#define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
+#define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
+#define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
+#define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
+#define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
+#define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
+#define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
+#define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
+#define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
+#define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
+#define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
+#define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
+#define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
+#define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
+#define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
+#define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
+
+#define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
+#define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
+#define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
+#define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
+#define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
+#define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
+#define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
+#define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
+
+#define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
+#define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
+#define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
+#define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
+#define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
+
+#define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
+#define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
+#define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
+#define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
+#define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
+#define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
+#define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
+#define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
+#define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
+#define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
+#define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
+#define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
+#define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
+#define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
+#define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
+#define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
+#define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
+#define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
+#define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
+#define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
+#define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
+#define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
+#define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
+#define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
+
+#define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
+#define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
+#define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
+#define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
+#define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
+#define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
+#define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
+#define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
+#define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
+#define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
+#define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
+#define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
+#define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
+#define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
+#define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
+#define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
+#define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
+#define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
+#define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
+#define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
+#define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
+#define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
+#define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
+
+/* Listing for IEEE-Supported Count Registers */
+
+#define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
+#define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
+#define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
+#define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
+#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
+#define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
+#define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
+#define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
+#define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
+#define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
+#define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
+#define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
+#define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
+#define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
+#define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
+#define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
+#define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
+#define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
+#define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
+#define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
+#define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
+#define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
+#define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
+#define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
+
+#define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
+#define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
+#define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
+#define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
+#define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
+#define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
+#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
+#define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
+#define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
+#define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
+#define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
+#define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
+#define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
+#define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
+#define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
+#define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
+#define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
+#define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
+#define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
+#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
+#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
+#define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+
+/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
+
+/* EMAC_OPMODE Masks */
+
+#define RE                 0x00000001     /* Receiver Enable                                    */
+#define ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
+#define HU                 0x00000010     /* Hash Filter Unicast Address                        */
+#define HM                 0x00000020     /* Hash Filter Multicast Address                      */
+#define PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
+#define PR                 0x00000080     /* Promiscuous Mode Enable                            */
+#define IFE                0x00000100     /* Inverse Filtering Enable                           */
+#define DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
+#define PBF                0x00000400     /* Pass Bad Frames Enable                             */
+#define PSF                0x00000800     /* Pass Short Frames Enable                           */
+#define RAF                0x00001000     /* Receive-All Mode                                   */
+#define TE                 0x00010000     /* Transmitter Enable                                 */
+#define DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
+#define DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
+#define DC                 0x00080000     /* Deferral Check                                     */
+#define BOLMT              0x00300000     /* Back-Off Limit                                     */
+#define BOLMT_10           0x00000000     /*            10-bit range                            */
+#define BOLMT_8            0x00100000     /*            8-bit range                             */
+#define BOLMT_4            0x00200000     /*            4-bit range                             */
+#define BOLMT_1            0x00300000     /*            1-bit range                             */
+#define DRTY               0x00400000     /* Disable TX Retry On Collision                      */
+#define LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
+#define RMII               0x01000000     /* RMII/MII* Mode                                     */
+#define RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
+#define FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
+#define LB                 0x08000000     /* Internal Loopback Enable                           */
+#define DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
+
+/* EMAC_STAADD Masks */
+
+#define STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
+#define STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
+#define STADISPRE          0x00000004     /* Disable Preamble Generation                        */
+#define STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
+#define REGAD              0x000007C0     /* STA Register Address                               */
+#define PHYAD              0x0000F800     /* PHY Device Address                                 */
+
+#define SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
+#define SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
+
+/* EMAC_STADAT Mask */
+
+#define STADATA            0x0000FFFF     /* Station Management Data                            */
+
+/* EMAC_FLC Masks */
+
+#define FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
+#define FLCE               0x00000002     /* Flow Control Enable                                */
+#define PCF                0x00000004     /* Pass Control Frames                                */
+#define BKPRSEN            0x00000008     /* Enable Backpressure                                */
+#define FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
+
+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
+
+/* EMAC_WKUP_CTL Masks */
+
+#define CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
+#define MPKE               0x00000002    /* Magic Packet Enable                                 */
+#define RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
+#define GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
+#define MPKS               0x00000020    /* Magic Packet Received Status                        */
+#define RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
+
+/* EMAC_WKUP_FFCMD Masks */
+
+#define WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
+#define WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
+#define WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
+#define WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
+#define WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
+#define WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
+#define WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
+#define WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
+
+/* EMAC_WKUP_FFOFF Masks */
+
+#define WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
+#define WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
+#define WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
+#define WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
+
+#define SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
+#define SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
+/* Set ALL Offsets */
+#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+
+#define WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
+#define WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
+
+#define SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
+#define SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+
+#define WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
+#define WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
+
+#define SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
+#define SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
+
+/* EMAC_SYSCTL Masks */
+
+#define PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
+#define RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
+#define RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
+#define MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
+
+#define SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
+
+/* EMAC_SYSTAT Masks */
+
+#define PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
+#define MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
+#define RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
+#define TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
+#define WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
+#define RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
+#define TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
+#define STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+
+#define RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
+#define RX_COMP           0x00001000    /* RX Frame Complete                                      */
+#define RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
+#define RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
+#define RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
+#define RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
+#define RX_LEN            0x00020000    /* RX Frame Length Error                                  */
+#define RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
+#define RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
+#define RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
+#define RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
+#define RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
+#define RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
+#define RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
+#define RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
+#define RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
+#define RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
+#define RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
+#define RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
+#define RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
+#define RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
+
+/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
+
+#define TX_COMP           0x00000001    /* TX Frame Complete                                      */
+#define TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
+#define TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
+#define TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
+#define TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
+#define TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
+#define TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
+#define TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
+#define TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
+#define TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
+#define TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
+#define TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
+#define TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
+#define TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
+#define TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
+
+/* EMAC_MMC_CTL Masks */
+#define RSTC              0x00000001    /* Reset All Counters                                     */
+#define CROLL             0x00000002    /* Counter Roll-Over Enable                               */
+#define CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
+#define MMCE              0x00000008    /* Enable MMC Counter Operation                           */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
+#define RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
+#define RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
+#define RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
+#define RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
+#define RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
+#define RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
+#define RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
+#define RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
+#define RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
+#define RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
+#define RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
+#define RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
+#define RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
+#define RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
+#define RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
+#define RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
+#define RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
+#define RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
+#define RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
+#define RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
+#define RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
+#define RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
+#define RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
+
+#define TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
+#define TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
+#define TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
+#define TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
+#define TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
+#define TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
+#define TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
+#define TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
+#define TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
+#define TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
+#define TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
+#define TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
+#define TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
+#define TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
+#define TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
+#define TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
+#define TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
+#define TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
+#define TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
+#define TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
+#define TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
+#define TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
+#define TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
+
+/* USB Control Registers */
+
+#define                        USB_FADDR  0xffc03800   /* Function address register */
+#define                        USB_POWER  0xffc03804   /* Power management register */
+#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
+#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
+#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
+#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
+#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
+#define                        USB_FRAME  0xffc03820   /* USB frame number */
+#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
+#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
+#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
+#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
+#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
+#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
+#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
+#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
+#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
+#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
+#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
+#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
+#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
+#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
+#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
+#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
+#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
+#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
+#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
+
+#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
+
+#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
+#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
+#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
+#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
+#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
+#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
+#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
+#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
+
+/* USB Endpoint 1 Control Registers */
+
+#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
+#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
+#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
+#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
+#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
+#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
+#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+
+/* USB Endpoint 2 Control Registers */
+
+#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
+#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
+#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
+#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
+#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
+#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
+#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
+
+/* USB Endpoint 3 Control Registers */
+
+#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
+#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
+#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
+#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
+#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
+#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
+#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+
+/* USB Endpoint 4 Control Registers */
+
+#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
+#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
+#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
+#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
+#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
+#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
+#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
+
+/* USB Endpoint 5 Control Registers */
+
+#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
+#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
+#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
+#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
+#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
+#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
+#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
+
+/* USB Endpoint 6 Control Registers */
+
+#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
+#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
+#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
+#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
+#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
+#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
+#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
+
+/* USB Endpoint 7 Control Registers */
+
+#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
+#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
+#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
+#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
+#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
+#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
+#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
+
+#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
+#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
+#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
+#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
+#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
+#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
+#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
+#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
+#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Bit masks for USB_FADDR */
+
+#define          FUNCTION_ADDRESS  0x7f       /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
+#define          nENABLE_SUSPENDM  0x0       
+#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
+#define             nSUSPEND_MODE  0x0       
+#define               RESUME_MODE  0x4        /* DMA Mode */
+#define              nRESUME_MODE  0x0       
+#define                     RESET  0x8        /* Reset indicator */
+#define                    nRESET  0x0       
+#define                   HS_MODE  0x10       /* High Speed mode indicator */
+#define                  nHS_MODE  0x0       
+#define                 HS_ENABLE  0x20       /* high Speed Enable */
+#define                nHS_ENABLE  0x0       
+#define                 SOFT_CONN  0x40       /* Soft connect */
+#define                nSOFT_CONN  0x0       
+#define                ISO_UPDATE  0x80       /* Isochronous update */
+#define               nISO_UPDATE  0x0       
+
+/* Bit masks for USB_INTRTX */
+
+#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
+#define                   nEP0_TX  0x0       
+#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
+#define                   nEP1_TX  0x0       
+#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
+#define                   nEP2_TX  0x0       
+#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
+#define                   nEP3_TX  0x0       
+#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
+#define                   nEP4_TX  0x0       
+#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
+#define                   nEP5_TX  0x0       
+#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
+#define                   nEP6_TX  0x0       
+#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
+#define                   nEP7_TX  0x0       
+
+/* Bit masks for USB_INTRRX */
+
+#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
+#define                   nEP1_RX  0x0       
+#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
+#define                   nEP2_RX  0x0       
+#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
+#define                   nEP3_RX  0x0       
+#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
+#define                   nEP4_RX  0x0       
+#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
+#define                   nEP5_RX  0x0       
+#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
+#define                   nEP6_RX  0x0       
+#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
+#define                   nEP7_RX  0x0       
+
+/* Bit masks for USB_INTRTXE */
+
+#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
+#define                 nEP0_TX_E  0x0       
+#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
+#define                 nEP1_TX_E  0x0       
+#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
+#define                 nEP2_TX_E  0x0       
+#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
+#define                 nEP3_TX_E  0x0       
+#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
+#define                 nEP4_TX_E  0x0       
+#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
+#define                 nEP5_TX_E  0x0       
+#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
+#define                 nEP6_TX_E  0x0       
+#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
+#define                 nEP7_TX_E  0x0       
+
+/* Bit masks for USB_INTRRXE */
+
+#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
+#define                 nEP1_RX_E  0x0       
+#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
+#define                 nEP2_RX_E  0x0       
+#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
+#define                 nEP3_RX_E  0x0       
+#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
+#define                 nEP4_RX_E  0x0       
+#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
+#define                 nEP5_RX_E  0x0       
+#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
+#define                 nEP6_RX_E  0x0       
+#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
+#define                 nEP7_RX_E  0x0       
+
+/* Bit masks for USB_INTRUSB */
+
+#define                 SUSPEND_B  0x1        /* Suspend indicator */
+#define                nSUSPEND_B  0x0       
+#define                  RESUME_B  0x2        /* Resume indicator */
+#define                 nRESUME_B  0x0       
+#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
+#define         nRESET_OR_BABLE_B  0x0       
+#define                     SOF_B  0x8        /* Start of frame */
+#define                    nSOF_B  0x0       
+#define                    CONN_B  0x10       /* Connection indicator */
+#define                   nCONN_B  0x0       
+#define                  DISCON_B  0x20       /* Disconnect indicator */
+#define                 nDISCON_B  0x0       
+#define             SESSION_REQ_B  0x40       /* Session Request */
+#define            nSESSION_REQ_B  0x0       
+#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
+#define             nVBUS_ERROR_B  0x0       
+
+/* Bit masks for USB_INTRUSBE */
+
+#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
+#define               nSUSPEND_BE  0x0       
+#define                 RESUME_BE  0x2        /* Resume indicator int enable */
+#define                nRESUME_BE  0x0       
+#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
+#define        nRESET_OR_BABLE_BE  0x0       
+#define                    SOF_BE  0x8        /* Start of frame int enable */
+#define                   nSOF_BE  0x0       
+#define                   CONN_BE  0x10       /* Connection indicator int enable */
+#define                  nCONN_BE  0x0       
+#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
+#define                nDISCON_BE  0x0       
+#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
+#define           nSESSION_REQ_BE  0x0       
+#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
+#define            nVBUS_ERROR_BE  0x0       
+
+/* Bit masks for USB_FRAME */
+
+#define              FRAME_NUMBER  0x7ff      /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define                GLOBAL_ENA  0x1        /* enables USB module */
+#define               nGLOBAL_ENA  0x0       
+#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
+#define               nEP1_TX_ENA  0x0       
+#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
+#define               nEP2_TX_ENA  0x0       
+#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
+#define               nEP3_TX_ENA  0x0       
+#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
+#define               nEP4_TX_ENA  0x0       
+#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
+#define               nEP5_TX_ENA  0x0       
+#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
+#define               nEP6_TX_ENA  0x0       
+#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
+#define               nEP7_TX_ENA  0x0       
+#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
+#define               nEP1_RX_ENA  0x0       
+#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
+#define               nEP2_RX_ENA  0x0       
+#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
+#define               nEP3_RX_ENA  0x0       
+#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
+#define               nEP4_RX_ENA  0x0       
+#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
+#define               nEP5_RX_ENA  0x0       
+#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
+#define               nEP6_RX_ENA  0x0       
+#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
+#define               nEP7_RX_ENA  0x0       
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define                   SESSION  0x1        /* session indicator */
+#define                  nSESSION  0x0       
+#define                  HOST_REQ  0x2        /* Host negotiation request */
+#define                 nHOST_REQ  0x0       
+#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
+#define                nHOST_MODE  0x0       
+#define                     VBUS0  0x8        /* Vbus level indicator[0] */
+#define                    nVBUS0  0x0       
+#define                     VBUS1  0x10       /* Vbus level indicator[1] */
+#define                    nVBUS1  0x0       
+#define                     LSDEV  0x20       /* Low-speed indicator */
+#define                    nLSDEV  0x0       
+#define                     FSDEV  0x40       /* Full or High-speed indicator */
+#define                    nFSDEV  0x0       
+#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
+#define                 nB_DEVICE  0x0       
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
+#define            nDRIVE_VBUS_ON  0x0       
+#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
+#define           nDRIVE_VBUS_OFF  0x0       
+#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
+#define          nCHRG_VBUS_START  0x0       
+#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
+#define            nCHRG_VBUS_END  0x0       
+#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
+#define       nDISCHRG_VBUS_START  0x0       
+#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
+#define         nDISCHRG_VBUS_END  0x0       
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
+#define        nDRIVE_VBUS_ON_ENA  0x0       
+#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
+#define       nDRIVE_VBUS_OFF_ENA  0x0       
+#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
+#define      nCHRG_VBUS_START_ENA  0x0       
+#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
+#define        nCHRG_VBUS_END_ENA  0x0       
+#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
+#define   nDISCHRG_VBUS_START_ENA  0x0       
+#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
+#define     nDISCHRG_VBUS_END_ENA  0x0       
+
+/* Bit masks for USB_CSR0 */
+
+#define                  RXPKTRDY  0x1        /* data packet receive indicator */
+#define                 nRXPKTRDY  0x0       
+#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
+#define                 nTXPKTRDY  0x0       
+#define                STALL_SENT  0x4        /* STALL handshake sent */
+#define               nSTALL_SENT  0x0       
+#define                   DATAEND  0x8        /* Data end indicator */
+#define                  nDATAEND  0x0       
+#define                  SETUPEND  0x10       /* Setup end */
+#define                 nSETUPEND  0x0       
+#define                 SENDSTALL  0x20       /* Send STALL handshake */
+#define                nSENDSTALL  0x0       
+#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
+#define        nSERVICED_RXPKTRDY  0x0       
+#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
+#define        nSERVICED_SETUPEND  0x0       
+#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
+#define                nFLUSHFIFO  0x0       
+#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
+#define         nSTALL_RECEIVED_H  0x0       
+#define                SETUPPKT_H  0x8        /* send Setup token host mode */
+#define               nSETUPPKT_H  0x0       
+#define                   ERROR_H  0x10       /* timeout error indicator host mode */
+#define                  nERROR_H  0x0       
+#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
+#define                 nREQPKT_H  0x0       
+#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
+#define              nSTATUSPKT_H  0x0       
+#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
+#define            nNAK_TIMEOUT_H  0x0       
+
+/* Bit masks for USB_COUNT0 */
+
+#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
+#define               nTXPKTRDY_T  0x0       
+#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
+#define         nFIFO_NOT_EMPTY_T  0x0       
+#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
+#define               nUNDERRUN_T  0x0       
+#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
+#define              nFLUSHFIFO_T  0x0       
+#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
+#define             nSTALL_SEND_T  0x0       
+#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
+#define             nSTALL_SENT_T  0x0       
+#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
+#define       nCLEAR_DATATOGGLE_T  0x0       
+#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
+#define               nINCOMPTX_T  0x0       
+#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
+#define             nDMAREQMODE_T  0x0       
+#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
+#define       nFORCE_DATATOGGLE_T  0x0       
+#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
+#define             nDMAREQ_ENA_T  0x0       
+#define                     ISO_T  0x4000     /* enable Isochronous transfers */
+#define                    nISO_T  0x0       
+#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
+#define                nAUTOSET_T  0x0       
+#define                  ERROR_TH  0x4        /* error condition host mode */
+#define                 nERROR_TH  0x0       
+#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
+#define        nSTALL_RECEIVED_TH  0x0       
+#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
+#define           nNAK_TIMEOUT_TH  0x0       
+
+/* Bit masks for USB_TXCOUNT */
+
+#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
+#define               nRXPKTRDY_R  0x0       
+#define               FIFO_FULL_R  0x2        /* FIFO not empty */
+#define              nFIFO_FULL_R  0x0       
+#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
+#define                nOVERRUN_R  0x0       
+#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
+#define              nDATAERROR_R  0x0       
+#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
+#define              nFLUSHFIFO_R  0x0       
+#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
+#define             nSTALL_SEND_R  0x0       
+#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
+#define             nSTALL_SENT_R  0x0       
+#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
+#define       nCLEAR_DATATOGGLE_R  0x0       
+#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
+#define               nINCOMPRX_R  0x0       
+#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
+#define             nDMAREQMODE_R  0x0       
+#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
+#define                nDISNYET_R  0x0       
+#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
+#define             nDMAREQ_ENA_R  0x0       
+#define                     ISO_R  0x4000     /* enable Isochronous transfers */
+#define                    nISO_R  0x0       
+#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
+#define              nAUTOCLEAR_R  0x0       
+#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
+#define                 nERROR_RH  0x0       
+#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
+#define                nREQPKT_RH  0x0       
+#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
+#define        nSTALL_RECEIVED_RH  0x0       
+#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
+#define              nINCOMPRX_RH  0x0       
+#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
+#define            nDMAREQMODE_RH  0x0       
+#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
+#define               nAUTOREQ_RH  0x0       
+
+/* Bit masks for USB_RXCOUNT */
+
+#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define            TARGET_EP_NO_T  0xf        /* EP number */
+#define                PROTOCOL_T  0xc        /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define            TARGET_EP_NO_R  0xf        /* EP number */
+#define                PROTOCOL_R  0xc        /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
+#define                 nDMA0_INT  0x0       
+#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
+#define                 nDMA1_INT  0x0       
+#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
+#define                 nDMA2_INT  0x0       
+#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
+#define                 nDMA3_INT  0x0       
+#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
+#define                 nDMA4_INT  0x0       
+#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
+#define                 nDMA5_INT  0x0       
+#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
+#define                 nDMA6_INT  0x0       
+#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
+#define                 nDMA7_INT  0x0       
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define                   DMA_ENA  0x1        /* DMA enable */
+#define                  nDMA_ENA  0x0       
+#define                 DIRECTION  0x2        /* direction of DMA transfer */
+#define                nDIRECTION  0x0       
+#define                      MODE  0x4        /* DMA Bus error */
+#define                     nMODE  0x0       
+#define                   INT_ENA  0x8        /* Interrupt enable */
+#define                  nINT_ENA  0x0       
+#define                     EPNUM  0xf0       /* EP number */
+#define                  BUSERROR  0x100      /* DMA Bus error */
+#define                 nBUSERROR  0x0       
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+#endif /* _DEF_BF527_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
new file mode 100644
index 000000000000..0b2fb5036ed0
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h
@@ -0,0 +1,2009 @@
+/*
+ * File:         include/asm-blackfin/mach-bf527/defBF52x_base.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF52X_H
+#define _DEF_BF52X_H
+
+
+/* ************************************************************** */
+/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
+/* ************************************************************** */
+
+/* ==== begin from defBF534.h ==== */
+
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
+#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
+#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
+#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
+#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
+#define CHIPID        0xFFC00014  /* Device ID Register */
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
+#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
+#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
+
+#define SIC_IMASK                       0xFFC0010C      /* Interrupt Mask Register                                      */
+#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
+#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
+#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
+#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
+#define SIC_ISR                         0xFFC00120      /* Interrupt Status Register                            */
+#define SIC_IWR                         0xFFC00124      /* Interrupt Wakeup Register                            */
+
+/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
+#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
+#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
+#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
+#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
+#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
+#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
+
+
+/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
+#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
+#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
+#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
+#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
+#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
+#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
+#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
+#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
+#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
+#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
+#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
+#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
+#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
+#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
+#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
+#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
+#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
+#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
+#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
+#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
+
+
+/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
+#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
+#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
+#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
+#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
+#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
+#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
+#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
+
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
+#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
+#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
+#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
+
+#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
+#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
+#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
+#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
+
+#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
+#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
+#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
+#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
+
+#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
+#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
+#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
+#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
+
+#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
+#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
+#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
+#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
+
+#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
+#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
+#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
+#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
+
+#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
+#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
+#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
+#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
+
+#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
+#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
+#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
+#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */   
+
+#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
+#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
+#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
+#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
+#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
+#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
+#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
+#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
+#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
+#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
+#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
+#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
+#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
+#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
+#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
+#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
+#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
+#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
+
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
+#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
+#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
+#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
+#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
+#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
+#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
+#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
+#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
+#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
+#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
+#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
+#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
+#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
+#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
+#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
+#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
+#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
+#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
+
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
+#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
+#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
+#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
+#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
+#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
+#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
+#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
+#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
+#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
+#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
+#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
+#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
+#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
+#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
+#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
+#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
+#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
+#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
+#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
+#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
+#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
+#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
+#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
+#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
+#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
+
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
+#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
+#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
+#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
+#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
+#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
+#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
+#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
+#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
+#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
+#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
+#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
+#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
+#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
+
+#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
+#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
+#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
+#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
+#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
+#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
+#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
+#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
+#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
+#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
+#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
+#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
+#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
+
+#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
+#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
+#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
+#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
+#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
+#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
+#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
+#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
+#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
+#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
+#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
+#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
+#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
+
+#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
+#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
+#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
+#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
+#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
+#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
+#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
+#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
+#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
+#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
+#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
+#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
+#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
+
+#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
+#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
+#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
+#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
+#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
+#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
+#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
+#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
+#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
+#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
+#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
+#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
+#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
+
+#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
+#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
+#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
+#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
+#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
+#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
+#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
+#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
+#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
+#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
+#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
+#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
+#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
+
+#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
+#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
+#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
+#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
+#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
+#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
+#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
+#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
+#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
+#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
+#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
+#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
+#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
+
+#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
+#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
+#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
+#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
+#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
+#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
+#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
+#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
+#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
+#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
+#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
+#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
+#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
+
+#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
+#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
+#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
+#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
+#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
+#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
+#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
+#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
+#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
+#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
+#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
+#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
+#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
+
+#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
+#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
+#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
+#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
+#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
+#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
+#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
+#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
+#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
+#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
+#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
+#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
+#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
+
+#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
+#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
+#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
+#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
+#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
+#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
+#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
+#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
+#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
+#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
+#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
+#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
+#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
+
+#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
+#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
+#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
+#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
+#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
+#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
+#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
+#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
+#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
+#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
+#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
+#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
+#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
+
+#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
+#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
+#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
+#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
+#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
+#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
+#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
+#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
+#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
+#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
+#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
+#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
+#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
+
+#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
+#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
+#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
+#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
+#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
+#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
+#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
+#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
+#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
+#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
+#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
+#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
+#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
+
+#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
+#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
+#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
+#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
+#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
+#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
+#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
+#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
+#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
+#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
+#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
+#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
+#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
+
+#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
+#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
+#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
+#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
+#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
+#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
+#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
+#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
+#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
+#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
+#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
+#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
+#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
+#define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI_SLAVE_STAT          0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI_SLAVE_ADDR          0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI_MASTER_CTL          0xFFC01414      /* Master Mode Control Register                         */
+#define TWI_MASTER_STAT         0xFFC01418      /* Master Mode Status Register                          */
+#define TWI_MASTER_ADDR         0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI_INT_STAT            0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI_INT_MASK            0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI_FIFO_CTL            0xFFC01428      /* FIFO Control Register                                        */
+#define TWI_FIFO_STAT           0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI_XMT_DATA8           0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI_XMT_DATA16          0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI_RCV_DATA8           0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI_RCV_DATA16          0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
+#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
+#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
+#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
+#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
+#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
+#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
+#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
+#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
+#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
+#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
+#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
+#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
+#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
+#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
+#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
+#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
+#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
+#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
+#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
+#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
+#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
+#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
+#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
+#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
+#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
+#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
+#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
+#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
+#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
+#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
+#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
+#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
+#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
+#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
+#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
+#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
+#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
+#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
+#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
+#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
+#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
+
+
+/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
+#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
+#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
+#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
+#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
+#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
+#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
+#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
+#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshhold Register         */
+#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
+#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
+#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
+
+#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
+#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
+#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
+#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshhold Register         */
+#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
+#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
+#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+#define PORTF_MUX               0xFFC03210      /* Port F mux control */
+#define PORTG_MUX               0xFFC03214      /* Port G mux control */
+#define PORTH_MUX               0xFFC03218      /* Port H mux control */
+#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
+#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
+#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
+#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
+#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
+#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
+#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
+#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
+#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
+#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
+#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
+#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
+
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+/*
+** ********************* PLL AND RESET MASKS ****************************************/
+/* PLL_CTL Masks                                                                                                                                        */
+#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
+#define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
+#define STOPCK                  0x0008  /* Core Clock Off                                                                       */
+#define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
+#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
+#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
+#define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
+#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
+/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
+#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
+
+/* PLL_DIV Masks                                                                                                                */
+#define SSEL                    0x000F  /* System Select                                                */
+#define CSEL                    0x0030  /* Core Select                                                  */
+#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
+#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
+#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
+#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
+/* PLL_DIV Macros                                                                                                               */
+#define SET_SSEL(x)             ((x)&0xF)               /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
+
+/* VR_CTL Masks                                                                                                                                 */
+#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
+#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
+#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
+#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
+
+#define GAIN                    0x000C  /* Voltage Level Gain   */
+#define GAIN_5                  0x0000  /*              GAIN = 5                */
+#define GAIN_10                 0x0004  /*              GAIN = 10               */
+#define GAIN_20                 0x0008  /*              GAIN = 20               */
+#define GAIN_50                 0x000C  /*              GAIN = 50               */
+
+#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
+#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
+#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
+#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
+#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
+#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
+#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
+#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
+#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
+#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
+#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
+
+#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
+#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate                     */
+#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
+#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
+#define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
+#define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
+
+/* PLL_STAT Masks                                                                                                                                       */
+#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
+#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
+#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
+#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* SWRST Masks                                                                                                                                          */
+#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
+#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
+#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
+#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
+#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
+
+/* SYSCR Masks                                                                                                                                                          */
+#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
+#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
+
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
+#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
+
+#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
+#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
+#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */ 
+#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */ 
+#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */ 
+#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
+#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
+
+#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
+#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
+#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
+#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */ 
+#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
+#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
+#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
+#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
+
+#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
+#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
+#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
+#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
+#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
+#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
+#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
+#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
+#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
+#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
+
+#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
+#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
+#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
+#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
+#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
+#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
+#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
+#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
+#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
+#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
+
+/* SIC_IAR0 Macros                                                                                                                      */
+#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
+#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
+#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
+#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
+#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
+#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
+#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
+#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
+
+/* SIC_IAR1 Macros                                                                                                                      */
+#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
+#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
+#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
+#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
+#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
+#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
+#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
+#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
+
+/* SIC_IAR2 Macros                                                                                                                      */
+#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
+#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
+#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
+#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
+#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
+#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
+#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
+#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
+
+/* SIC_IAR3 Macros                                                                                                                      */
+#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
+#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
+#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
+#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
+#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
+#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
+#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
+#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
+
+
+/* SIC_IMASK Masks                                                                                                                                              */
+#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
+#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
+#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
+#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
+
+/* SIC_IWR Masks                                                                                                                                                */
+#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
+#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
+#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
+#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
+
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+
+#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#define WDEV_RESET 0x0000 /* generate reset event on roll over */
+#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
+#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
+#define WDEV_NONE 0x0006 /* no event on roll over */
+#define WDEN 0x0FF0 /* enable watchdog */
+#define WDDIS 0x0AD0 /* disable watchdog */
+#define WDRO 0x8000 /* watchdog rolled over latch */ 
+
+/* depreciated WDOG_CTL Register Masks for legacy code */
+
+
+#define ICTL WDEV
+#define ENABLE_RESET WDEV_RESET
+#define WDOG_RESET WDEV_RESET
+#define ENABLE_NMI WDEV_NMI
+#define WDOG_NMI WDEV_NMI
+#define ENABLE_GPI WDEV_GPI
+#define WDOG_GPI WDEV_GPI
+#define DISABLE_EVT WDEV_NONE
+#define WDOG_NONE WDEV_NONE
+
+#define TMR_EN WDEN
+#define TMR_DIS WDDIS
+#define TRO WDRO
+#define ICTL_P0 0x01
+ #define ICTL_P1 0x02
+#define TRO_P 0x0F
+
+
+
+/* ***************  REAL TIME CLOCK MASKS  **************************/
+/* RTC_STAT and RTC_ALARM Masks                                                                         */
+#define RTC_SEC                         0x0000003F      /* Real-Time Clock Seconds      */
+#define RTC_MIN                         0x00000FC0      /* Real-Time Clock Minutes      */
+#define RTC_HR                          0x0001F000      /* Real-Time Clock Hours        */
+#define RTC_DAY                         0xFFFE0000      /* Real-Time Clock Days         */
+
+/* RTC_ALARM Macro                      z=day           y=hr    x=min   w=sec           */
+#define SET_ALARM(z,y,x,w)      ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+
+/* RTC_ICTL and RTC_ISTAT Masks                                                                                                                                         */
+#define STOPWATCH                       0x0001          /* Stopwatch Interrupt Enable                                                           */
+#define ALARM                           0x0002          /* Alarm Interrupt Enable                                                                       */
+#define SECOND                          0x0004          /* Seconds (1 Hz) Interrupt Enable                                                      */
+#define MINUTE                          0x0008          /* Minutes Interrupt Enable                                                                     */
+#define HOUR                            0x0010          /* Hours Interrupt Enable                                                                       */
+#define DAY                                     0x0020          /* 24 Hours (Days) Interrupt Enable                                                     */
+#define DAY_ALARM                       0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable       */
+#define WRITE_PENDING           0x4000          /* Write Pending Status                                                                         */
+#define WRITE_COMPLETE          0x8000          /* Write Complete Interrupt Enable                                                      */
+
+/* RTC_FAST / RTC_PREN Mask                                                                                             */
+#define PREN                            0x0001  /* Enable Prescaler, RTC Runs @1 Hz     */
+
+
+/* ************** UART CONTROLLER MASKS *************************/
+/* UARTx_LCR Masks                                                                                              */
+#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
+#define STB                     0x04                            /* Stop Bits                    */
+#define PEN                     0x08                            /* Parity Enable                */
+#define EPS                     0x10                            /* Even Parity Select   */
+#define STP                     0x20                            /* Stick Parity                 */
+#define SB                      0x40                            /* Set Break                    */
+#define DLAB            0x80                            /* Divisor Latch Access */
+
+/* UARTx_MCR Mask                                                                               */
+#define LOOP_ENA        0x10    /* Loopback Mode Enable */
+#define LOOP_ENA_P      0x04
+
+/* UARTx_LSR Masks                                                                              */
+#define DR                      0x01    /* Data Ready                           */
+#define OE                      0x02    /* Overrun Error                        */
+#define PE                      0x04    /* Parity Error                         */
+#define FE                      0x08    /* Framing Error                        */
+#define BI                      0x10    /* Break Interrupt                      */
+#define THRE            0x20    /* THR Empty                            */
+#define TEMT            0x40    /* TSR and UART_THR Empty       */
+
+/* UARTx_IER Masks                                                                                                                      */
+#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt         */
+#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt       */
+#define ELSI            0x04            /* Enable RX Status Interrupt                           */
+
+/* UARTx_IIR Masks                                                                                                              */
+#define NINT            0x01            /* Pending Interrupt                                    */
+#define IIR_TX_READY    0x02            /* UART_THR empty                               */
+#define IIR_RX_READY    0x04            /* Receive data ready                           */
+#define IIR_LINE_CHANGE 0x06            /* Receive line status                          */ 
+#define IIR_STATUS      0x06            /* Highest Priority Pending Interrupt   */
+
+/* UARTx_GCTL Masks                                                                                                     */
+#define UCEN            0x01            /* Enable UARTx Clocks                          */
+#define IREN            0x02            /* Enable IrDA Mode                                     */
+#define TPOLC           0x04            /* IrDA TX Polarity Change                      */
+#define RPOLC           0x08            /* IrDA RX Polarity Change                      */
+#define FPE                     0x10            /* Force Parity Error On Transmit       */
+#define FFE                     0x20            /* Force Framing Error On Transmit      */
+
+
+/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
+/* SPI_CTL Masks                                                                                                                                        */
+#define TIMOD           0x0003          /* Transfer Initiate Mode                                                       */
+#define RDBR_CORE       0x0000          /*              RDBR Read Initiates, IRQ When RDBR Full         */
+#define TDBR_CORE       0x0001          /*              TDBR Write Initiates, IRQ When TDBR Empty       */
+#define RDBR_DMA        0x0002          /*              DMA Read, DMA Until FIFO Empty                          */
+#define TDBR_DMA        0x0003          /*              DMA Write, DMA Until FIFO Full                          */
+#define SZ                      0x0004          /* Send Zero (When TDBR Empty, Send Zero/Last*)         */
+#define GM                      0x0008          /* Get More (When RDBR Full, Overwrite/Discard*)        */
+#define PSSE            0x0010          /* Slave-Select Input Enable                                            */
+#define EMISO           0x0020          /* Enable MISO As Output                                                        */
+#define SIZE            0x0100          /* Size of Words (16/8* Bits)                                           */
+#define LSBF            0x0200          /* LSB First                                                                            */
+#define CPHA            0x0400          /* Clock Phase                                                                          */
+#define CPOL            0x0800          /* Clock Polarity                                                                       */
+#define MSTR            0x1000          /* Master/Slave*                                                                        */
+#define WOM                     0x2000          /* Write Open Drain Master                                                      */
+#define SPE                     0x4000          /* SPI Enable                                                                           */
+
+/* SPI_FLG Masks                                                                                                                                        */
+#define FLS1            0x0002          /* Enables SPI_FLOUT1 as SPI Slave-Select Output        */
+#define FLS2            0x0004          /* Enables SPI_FLOUT2 as SPI Slave-Select Output        */
+#define FLS3            0x0008          /* Enables SPI_FLOUT3 as SPI Slave-Select Output        */
+#define FLS4            0x0010          /* Enables SPI_FLOUT4 as SPI Slave-Select Output        */
+#define FLS5            0x0020          /* Enables SPI_FLOUT5 as SPI Slave-Select Output        */
+#define FLS6            0x0040          /* Enables SPI_FLOUT6 as SPI Slave-Select Output        */
+#define FLS7            0x0080          /* Enables SPI_FLOUT7 as SPI Slave-Select Output        */
+#define FLG1            0xFDFF          /* Activates SPI_FLOUT1                                                         */
+#define FLG2            0xFBFF          /* Activates SPI_FLOUT2                                                         */
+#define FLG3            0xF7FF          /* Activates SPI_FLOUT3                                                         */
+#define FLG4            0xEFFF          /* Activates SPI_FLOUT4                                                         */
+#define FLG5            0xDFFF          /* Activates SPI_FLOUT5                                                         */
+#define FLG6            0xBFFF          /* Activates SPI_FLOUT6                                                         */
+#define FLG7            0x7FFF          /* Activates SPI_FLOUT7                                                         */
+
+/* SPI_STAT Masks                                                                                                                                                               */
+#define SPIF            0x0001          /* SPI Finished (Single-Word Transfer Complete)                                 */
+#define MODF            0x0002          /* Mode Fault Error (Another Device Tried To Become Master)             */
+#define TXE                     0x0004          /* Transmission Error (Data Sent With No New Data In TDBR)              */
+#define TXS                     0x0008          /* SPI_TDBR Data Buffer Status (Full/Empty*)                                    */
+#define RBSY            0x0010          /* Receive Error (Data Received With RDBR Full)                                 */
+#define RXS                     0x0020          /* SPI_RDBR Data Buffer Status (Full/Empty*)                                    */
+#define TXCOL           0x0040          /* Transmit Collision Error (Corrupt Data May Have Been Sent)   */
+
+
+/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
+/* TIMER_ENABLE Masks                                                                                                   */
+#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
+#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
+#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
+#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
+#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
+#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
+#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
+#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
+
+/* TIMER_DISABLE Masks                                                                                                  */
+#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
+#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
+#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
+#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
+#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
+#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
+#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
+#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
+
+/* TIMER_STATUS Masks                                                                                                   */
+#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
+#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
+#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
+#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
+#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
+#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
+#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
+#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
+#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
+#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
+#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
+#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
+#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
+#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
+#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
+#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
+#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
+#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
+#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
+#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
+#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
+#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
+#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
+#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks                                                                                                  */
+#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
+#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
+#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
+#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
+#define PERIOD_CNT              0x0008  /* Period Count                                                 */
+#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
+#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
+#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
+#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
+#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
+#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
+#define ERR_TYP                 0xC000  /* Error Type                                                   */
+
+
+/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
+/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
+/* Port F Masks                                                                                                                 */
+#define PF0             0x0001
+#define PF1             0x0002
+#define PF2             0x0004
+#define PF3             0x0008
+#define PF4             0x0010
+#define PF5             0x0020
+#define PF6             0x0040
+#define PF7             0x0080
+#define PF8             0x0100
+#define PF9             0x0200
+#define PF10    0x0400
+#define PF11    0x0800
+#define PF12    0x1000
+#define PF13    0x2000
+#define PF14    0x4000
+#define PF15    0x8000
+
+/* Port G Masks                                                                                                                 */
+#define PG0             0x0001
+#define PG1             0x0002
+#define PG2             0x0004
+#define PG3             0x0008
+#define PG4             0x0010
+#define PG5             0x0020
+#define PG6             0x0040
+#define PG7             0x0080
+#define PG8             0x0100
+#define PG9             0x0200
+#define PG10    0x0400
+#define PG11    0x0800
+#define PG12    0x1000
+#define PG13    0x2000
+#define PG14    0x4000
+#define PG15    0x8000
+
+/* Port H Masks                                                                                                                 */
+#define PH0             0x0001
+#define PH1             0x0002
+#define PH2             0x0004
+#define PH3             0x0008
+#define PH4             0x0010
+#define PH5             0x0020
+#define PH6             0x0040
+#define PH7             0x0080
+#define PH8             0x0100
+#define PH9             0x0200
+#define PH10    0x0400
+#define PH11    0x0800
+#define PH12    0x1000
+#define PH13    0x2000
+#define PH14    0x4000
+#define PH15    0x8000
+
+
+/* *******************  SERIAL PORT MASKS  **************************************/
+/* SPORTx_TCR1 Masks                                                                                                                    */
+#define TSPEN           0x0001          /* Transmit Enable                                                              */
+#define ITCLK           0x0002          /* Internal Transmit Clock Select                               */
+#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
+#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
+#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
+#define TLSBIT          0x0010          /* Transmit Bit Order                                                   */
+#define ITFS            0x0200          /* Internal Transmit Frame Sync Select                  */
+#define TFSR            0x0400          /* Transmit Frame Sync Required Select                  */
+#define DITFS           0x0800          /* Data-Independent Transmit Frame Sync Select  */
+#define LTFS            0x1000          /* Low Transmit Frame Sync Select                               */
+#define LATFS           0x2000          /* Late Transmit Frame Sync Select                              */
+#define TCKFE           0x4000          /* Clock Falling Edge Select                                    */
+
+/* SPORTx_TCR2 Masks and Macro                                                                                                  */
+#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
+#define TXSE            0x0100          /* TX Secondary Enable                                                  */
+#define TSFSE           0x0200          /* Transmit Stereo Frame Sync Enable                    */
+#define TRFST           0x0400          /* Left/Right Order (1 = Right Channel 1st)             */
+
+/* SPORTx_RCR1 Masks                                                                                                                    */
+#define RSPEN           0x0001          /* Receive Enable                                                               */
+#define IRCLK           0x0002          /* Internal Receive Clock Select                                */
+#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
+#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
+#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
+#define RLSBIT          0x0010          /* Receive Bit Order                                                    */
+#define IRFS            0x0200          /* Internal Receive Frame Sync Select                   */
+#define RFSR            0x0400          /* Receive Frame Sync Required Select                   */
+#define LRFS            0x1000          /* Low Receive Frame Sync Select                                */
+#define LARFS           0x2000          /* Late Receive Frame Sync Select                               */
+#define RCKFE           0x4000          /* Clock Falling Edge Select                                    */
+
+/* SPORTx_RCR2 Masks                                                                                                                    */
+#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
+#define RXSE            0x0100          /* RX Secondary Enable                                                  */
+#define RSFSE           0x0200          /* RX Stereo Frame Sync Enable                                  */
+#define RRFST           0x0400          /* Right-First Data Order                                               */
+
+/* SPORTx_STAT Masks                                                                                                                    */
+#define RXNE            0x0001          /* Receive FIFO Not Empty Status                                */
+#define RUVF            0x0002          /* Sticky Receive Underflow Status                              */
+#define ROVF            0x0004          /* Sticky Receive Overflow Status                               */
+#define TXF                     0x0008          /* Transmit FIFO Full Status                                    */
+#define TUVF            0x0010          /* Sticky Transmit Underflow Status                             */
+#define TOVF            0x0020          /* Sticky Transmit Overflow Status                              */
+#define TXHRE           0x0040          /* Transmit Hold Register Empty                                 */
+
+/* SPORTx_MCMC1 Macros                                                                                                                  */
+#define SP_WOFF(x)      ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
+
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
+#define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
+
+/* SPORTx_MCMC2 Masks                                                                                                                   */
+#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
+#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
+#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
+#define MCDTXPE         0x0004          /* Multichannel DMA Transmit Packing                    */
+#define MCDRXPE         0x0008          /* Multichannel DMA Receive Packing                             */
+#define MCMEN           0x0010          /* Multichannel Frame Mode Enable                               */
+#define FSDR            0x0080          /* Multichannel Frame Sync to Data Relationship */
+#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
+#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
+#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
+#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
+#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
+#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
+#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
+#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
+#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
+#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
+#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
+#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
+#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
+#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
+#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
+#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
+
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
+/* EBIU_AMGCTL Masks                                                                                                                                    */
+#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
+#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
+#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
+#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
+#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
+#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
+
+/* EBIU_AMBCTL0 Masks                                                                                                                                   */
+#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
+#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
+#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
+#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
+#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
+#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
+#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
+#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
+#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
+#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
+#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
+#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
+#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
+#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
+#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
+#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
+#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
+#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
+#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
+#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
+#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
+#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
+#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
+#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
+#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
+#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
+#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
+#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
+#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
+#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
+#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
+#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
+#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
+#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
+#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
+#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
+
+#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
+#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
+#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
+#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
+#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
+#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
+#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
+#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
+#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
+#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
+#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
+#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
+#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
+#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
+#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
+#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
+#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
+#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
+#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
+#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
+#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
+#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
+#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
+#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
+#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
+#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
+#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
+#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
+#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
+#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
+#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
+#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
+#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
+#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
+#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
+#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
+#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
+#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
+#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
+#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
+#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
+
+/* EBIU_AMBCTL1 Masks                                                                                                                                   */
+#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
+#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
+#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
+#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
+#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
+#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
+#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
+#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
+#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
+#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
+#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
+#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
+#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
+#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
+#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
+#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
+#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
+#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
+#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
+#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
+#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
+#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
+#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
+#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
+#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
+#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
+#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
+#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
+#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
+#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
+#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
+#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
+#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
+#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
+#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
+#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
+
+#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
+#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
+#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
+#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
+#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
+#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
+#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
+#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
+#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
+#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
+#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
+#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
+#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
+#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
+#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
+#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
+#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
+#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
+#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
+#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
+#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
+#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
+#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
+#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
+#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
+#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
+#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
+#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
+#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
+#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
+#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
+#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
+#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
+#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
+#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
+#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
+
+
+/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
+/* EBIU_SDGCTL Masks                                                                                                                                                    */
+#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
+#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
+#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
+#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
+#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
+#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
+#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
+#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
+#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
+#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
+#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
+#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
+#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
+#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
+#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
+#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
+#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
+#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
+#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
+#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
+#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
+#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
+#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
+#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
+#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
+#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
+#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
+#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
+#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
+#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
+#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
+#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
+#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
+#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
+#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
+#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
+#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
+#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
+#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
+#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
+#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
+#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
+#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
+#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
+
+/* EBIU_SDBCTL Masks                                                                                                                                            */
+#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
+#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
+#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
+#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
+#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
+#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
+#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
+#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
+#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
+#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
+#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
+
+/* EBIU_SDSTAT Masks                                                                                                            */
+#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
+#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
+#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
+#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
+#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
+#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
+
+
+/* **************************  DMA CONTROLLER MASKS  ********************************/
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
+#define DMAEN                   0x0001          /* DMA Channel Enable                                                   */
+#define WNR                             0x0002          /* Channel Direction (W/R*)                                             */
+#define WDSIZE_8                0x0000          /* Transfer Word Size = 8                                               */
+#define WDSIZE_16               0x0004          /* Transfer Word Size = 16                                              */
+#define WDSIZE_32               0x0008          /* Transfer Word Size = 32                                              */
+#define DMA2D                   0x0010          /* DMA Mode (2D/1D*)                                                    */
+#define RESTART                 0x0020          /* DMA Buffer Clear                                                             */
+#define DI_SEL                  0x0040          /* Data Interrupt Timing Select                                 */
+#define DI_EN                   0x0080          /* Data Interrupt Enable                                                */
+#define NDSIZE_0                0x0000          /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
+#define NDSIZE_1                0x0100          /* Next Descriptor Size = 1                                             */
+#define NDSIZE_2                0x0200          /* Next Descriptor Size = 2                                             */
+#define NDSIZE_3                0x0300          /* Next Descriptor Size = 3                                             */
+#define NDSIZE_4                0x0400          /* Next Descriptor Size = 4                                             */
+#define NDSIZE_5                0x0500          /* Next Descriptor Size = 5                                             */
+#define NDSIZE_6                0x0600          /* Next Descriptor Size = 6                                             */
+#define NDSIZE_7                0x0700          /* Next Descriptor Size = 7                                             */
+#define NDSIZE_8                0x0800          /* Next Descriptor Size = 8                                             */
+#define NDSIZE_9                0x0900          /* Next Descriptor Size = 9                                             */
+#define NDSIZE                  0x0900  /* Next Descriptor Size */
+#define DMAFLOW                 0x7000  /* Flow Control */
+#define DMAFLOW_STOP            0x0000          /* Stop Mode                                                                    */
+#define DMAFLOW_AUTO            0x1000          /* Autobuffer Mode                                                              */
+#define DMAFLOW_ARRAY           0x4000          /* Descriptor Array Mode                                                */
+#define DMAFLOW_SMALL           0x6000          /* Small Model Descriptor List Mode                             */
+#define DMAFLOW_LARGE           0x7000          /* Large Model Descriptor List Mode                             */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
+#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
+#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
+#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
+#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
+#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
+#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
+#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
+#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
+#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
+#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
+#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
+#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
+#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
+#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
+#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
+#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
+#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
+#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
+
+
+/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
+/*  PPI_CONTROL Masks                                                                                                   */
+#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
+#define PORT_DIR                0x0002          /* PPI Port Direction                           */
+#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
+#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
+#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
+#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
+#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
+#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
+#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
+#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
+#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
+#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
+#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
+#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
+#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
+#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
+#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
+#define DLENGTH                 0x3800          /* PPI Data Length  */
+#define POLC                    0x4000          /* PPI Clock Polarity                           */
+#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
+
+/* PPI_STATUS Masks                                                                                                             */
+#define FLD                             0x0400          /* Field Indicator                                      */
+#define FT_ERR                  0x0800          /* Frame Track Error                            */
+#define OVR                             0x1000          /* FIFO Overflow Error                          */
+#define UNDR                    0x2000          /* FIFO Underrun Error                          */
+#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
+#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
+
+
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
+#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
+
+/* TWI_PRESCALE Masks                                                                                                                   */
+#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
+#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
+#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
+
+/* TWI_SLAVE_CTRL Masks                                                                                                                 */
+#define SEN                     0x0001          /* Slave Enable                                                                 */
+#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
+#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
+#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
+
+/* TWI_SLAVE_STAT Masks                                                                                                                 */
+#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002          /* General Call Indicator                                               */
+
+/* TWI_MASTER_CTRL Masks                                                                                                        */
+#define MEN                     0x0001          /* Master Mode Enable                                           */
+#define MADD_LEN        0x0002          /* Master Address Length                                        */
+#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
+#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
+#define STOP            0x0010          /* Issue Stop Condition                                         */
+#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
+#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
+#define SDAOVR          0x4000          /* Serial Data Override                                         */
+#define SCLOVR          0x8000          /* Serial Clock Override                                        */
+
+/* TWI_MASTER_STAT Masks                                                                                                                */
+#define MPROG           0x0001          /* Master Transfer In Progress                                  */
+#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
+#define ANAK            0x0004          /* Address Not Acknowledged                                             */
+#define DNAK            0x0008          /* Data Not Acknowledged                                                */
+#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
+#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
+#define SDASEN          0x0040          /* Serial Data Sense                                                    */
+#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
+#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
+#define SINIT           0x0001          /* Slave Transfer Initiated     */
+#define SCOMP           0x0002          /* Slave Transfer Complete      */
+#define SERR            0x0004          /* Slave Transfer Error         */
+#define SOVF            0x0008          /* Slave Overflow                       */
+#define MCOMP           0x0010          /* Master Transfer Complete     */
+#define MERR            0x0020          /* Master Transfer Error        */
+#define XMTSERV         0x0040          /* Transmit FIFO Service        */
+#define RCVSERV         0x0080          /* Receive FIFO Service         */
+
+/* TWI_FIFO_CTRL Masks                                                                                          */
+#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
+#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
+#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
+#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
+
+/* TWI_FIFO_STAT Masks                                                                                                                  */
+#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
+#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
+#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
+#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
+
+#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
+#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
+#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
+#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
+
+
+/* Omit CAN masks from defBF534.h */
+
+/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
+/* PORT_MUX Masks                                                                                                                       */
+#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
+#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
+#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
+
+#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
+#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
+#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
+#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
+
+#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
+#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
+#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
+
+#define PFTE                    0x0010                  /* Port F Timer Enable                          */
+#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
+#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
+
+#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
+#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
+#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
+
+#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
+#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
+#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
+
+#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
+#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
+#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
+
+#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
+#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
+#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
+
+#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
+#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
+#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
+
+#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
+#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
+#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
+
+#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
+#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
+#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
+
+
+/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
+/* HDMAx_CTL Masks                                                                                                              */
+#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
+#define REP                     0x0002  /* HDMA Request Polarity                                        */
+#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
+#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
+#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
+#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
+#define DRQ                     0x0300  /* HDMA Request Type                                            */
+#define DRQ_NONE        0x0000  /*              No Request                                                      */
+#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
+#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
+#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
+#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
+#define PS                      0x2000  /* HDMA Pin Status                                                      */
+#define OI                      0x4000  /* Overflow Interrupt Generated                         */
+#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
+
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000 
+#define _BOOTROM_FINAL_INIT 0xEF000002 
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define PGDE_UART   PFDE_UART
+#define PGDE_DMA    PFDE_DMA
+#define CKELOW          SCKELOW
+
+/* ==== end from defBF534.h ==== */
+
+/* HOST Port Registers */
+
+#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
+#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
+#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
+
+/* Counter Registers */
+
+#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
+#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
+#define                       CNT_STATUS  0xffc03508   /* Status Register */
+#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
+#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
+#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
+#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
+#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
+
+/* OTP/FUSE Registers */
+
+#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
+#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
+#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
+#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
+
+/* Security Registers */
+
+#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
+#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
+#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+
+/* NFC Registers */
+
+#define                          NFC_CTL  0xffc03700   /* NAND Control Register */
+#define                         NFC_STAT  0xffc03704   /* NAND Status Register */
+#define                      NFC_IRQSTAT  0xffc03708   /* NAND Interrupt Status Register */
+#define                      NFC_IRQMASK  0xffc0370c   /* NAND Interrupt Mask Register */
+#define                         NFC_ECC0  0xffc03710   /* NAND ECC Register 0 */
+#define                         NFC_ECC1  0xffc03714   /* NAND ECC Register 1 */
+#define                         NFC_ECC2  0xffc03718   /* NAND ECC Register 2 */
+#define                         NFC_ECC3  0xffc0371c   /* NAND ECC Register 3 */
+#define                        NFC_COUNT  0xffc03720   /* NAND ECC Count Register */
+#define                          NFC_RST  0xffc03724   /* NAND ECC Reset Register */
+#define                        NFC_PGCTL  0xffc03728   /* NAND Page Control Register */
+#define                         NFC_READ  0xffc0372c   /* NAND Read Data Register */
+#define                         NFC_ADDR  0xffc03740   /* NAND Address Register */
+#define                          NFC_CMD  0xffc03744   /* NAND Command Register */
+#define                      NFC_DATA_WR  0xffc03748   /* NAND Data Write Register */
+#define                      NFC_DATA_RD  0xffc0374c   /* NAND Data Read Register */
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for HOST_CONTROL */
+
+#define                   HOST_EN  0x1        /* Host Enable */
+#define                  nHOST_EN  0x0       
+#define                  HOST_END  0x2        /* Host Endianess */
+#define                 nHOST_END  0x0       
+#define                 DATA_SIZE  0x4        /* Data Size */
+#define                nDATA_SIZE  0x0       
+#define                  HOST_RST  0x8        /* Host Reset */
+#define                 nHOST_RST  0x0       
+#define                  HRDY_OVR  0x20       /* Host Ready Override */
+#define                 nHRDY_OVR  0x0       
+#define                  INT_MODE  0x40       /* Interrupt Mode */
+#define                 nINT_MODE  0x0       
+#define                     BT_EN  0x80       /* Bus Timeout Enable */
+#define                    nBT_EN  0x0       
+#define                       EHW  0x100      /* Enable Host Write */
+#define                      nEHW  0x0       
+#define                       EHR  0x200      /* Enable Host Read */
+#define                      nEHR  0x0       
+#define                       BDR  0x400      /* Burst DMA Requests */
+#define                      nBDR  0x0       
+
+/* Bit masks for HOST_STATUS */
+
+#define                     READY  0x1        /* DMA Ready */
+#define                    nREADY  0x0       
+#define                  FIFOFULL  0x2        /* FIFO Full */
+#define                 nFIFOFULL  0x0       
+#define                 FIFOEMPTY  0x4        /* FIFO Empty */
+#define                nFIFOEMPTY  0x0       
+#define                  COMPLETE  0x8        /* DMA Complete */
+#define                 nCOMPLETE  0x0       
+#define                      HSHK  0x10       /* Host Handshake */
+#define                     nHSHK  0x0       
+#define                   TIMEOUT  0x20       /* Host Timeout */
+#define                  nTIMEOUT  0x0       
+#define                      HIRQ  0x40       /* Host Interrupt Request */
+#define                     nHIRQ  0x0       
+#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
+#define               nALLOW_CNFG  0x0       
+#define                   DMA_DIR  0x100      /* DMA Direction */
+#define                  nDMA_DIR  0x0       
+#define                       BTE  0x200      /* Bus Timeout Enabled */
+#define                      nBTE  0x0       
+#define               HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
+#define              nHOSTRD_DONE  0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
+
+/* Bit masks for CNT_CONFIG */
+
+#define                      CNTE  0x1        /* Counter Enable */
+#define                     nCNTE  0x0       
+#define                      DEBE  0x2        /* Debounce Enable */
+#define                     nDEBE  0x0       
+#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
+#define                   nCDGINV  0x0       
+#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
+#define                   nCUDINV  0x0       
+#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
+#define                   nCZMINV  0x0       
+#define                   CNTMODE  0x700      /* Counter Operating Mode */
+#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
+#define                     nZMZC  0x0       
+#define                   BNDMODE  0x3000     /* Boundary register Mode */
+#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
+#define                   nINPDIS  0x0       
+
+/* Bit masks for CNT_IMASK */
+
+#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
+#define                     nICIE  0x0       
+#define                      UCIE  0x2        /* Up count Interrupt Enable */
+#define                     nUCIE  0x0       
+#define                      DCIE  0x4        /* Down count Interrupt Enable */
+#define                     nDCIE  0x0       
+#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
+#define                   nMINCIE  0x0       
+#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
+#define                   nMAXCIE  0x0       
+#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
+#define                  nCOV31IE  0x0       
+#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
+#define                  nCOV15IE  0x0       
+#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
+#define                  nCZEROIE  0x0       
+#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
+#define                    nCZMIE  0x0       
+#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
+#define                   nCZMEIE  0x0       
+#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
+#define                   nCZMZIE  0x0       
+
+/* Bit masks for CNT_STATUS */
+
+#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
+#define                     nICII  0x0       
+#define                      UCII  0x2        /* Up count Interrupt Identifier */
+#define                     nUCII  0x0       
+#define                      DCII  0x4        /* Down count Interrupt Identifier */
+#define                     nDCII  0x0       
+#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
+#define                   nMINCII  0x0       
+#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
+#define                   nMAXCII  0x0       
+#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
+#define                  nCOV31II  0x0       
+#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
+#define                  nCOV15II  0x0       
+#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
+#define                  nCZEROII  0x0       
+#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
+#define                    nCZMII  0x0       
+#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
+#define                   nCZMEII  0x0       
+#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
+#define                   nCZMZII  0x0       
+
+/* Bit masks for CNT_COMMAND */
+
+#define                    W1LCNT  0xf        /* Load Counter Register */
+#define                    W1LMIN  0xf0       /* Load Min Register */
+#define                    W1LMAX  0xf00      /* Load Max Register */
+#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
+#define                 nW1ZMONCE  0x0       
+
+/* Bit masks for CNT_DEBOUNCE */
+
+#define                 DPRESCALE  0xf        /* Load Counter Register */
+
+/* Bit masks for OTP_CONTROL */
+
+#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
+#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
+#define                     nFIEN  0x0       
+#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
+#define                 nFTESTDEC  0x0       
+#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
+#define                  nFWRTEST  0x0       
+#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
+#define                    nFRDEN  0x0       
+#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
+#define                    nFWREN  0x0       
+
+/* Bit masks for OTP_BEN */
+
+#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
+
+/* Bit masks for OTP_STATUS */
+
+#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
+#define                    nFCOMP  0x0       
+#define                    FERROR  0x2        /* OTP/Fuse Access Error */
+#define                   nFERROR  0x0       
+#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
+#define                 nMMRGLOAD  0x0       
+#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
+#define                 nMMRGLOCK  0x0       
+#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
+#define                   nFPGMEN  0x0       
+
+/* Bit masks for OTP_TIMING */
+
+#define                   USECDIV  0xff       /* Micro Second Divider */
+#define                   READACC  0x7f00     /* Read Access Time */
+#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
+#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
+#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
+#define                   PGMTIME  0xff000000 /* Program Time */
+
+/* Bit masks for SECURE_SYSSWT */
+
+#define                   EMUDABL  0x1        /* Emulation Disable. */
+#define                  nEMUDABL  0x0       
+#define                   RSTDABL  0x2        /* Reset Disable */
+#define                  nRSTDABL  0x0       
+#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
+#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
+#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
+#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
+#define                  nDMA0OVR  0x0       
+#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
+#define                  nDMA1OVR  0x0       
+#define                    EMUOVR  0x4000     /* Emulation Override */
+#define                   nEMUOVR  0x0       
+#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
+#define                   nOTPSEN  0x0       
+#define                    L2DABL  0x70000    /* L2 Memory Disable. */
+
+/* Bit masks for SECURE_CONTROL */
+
+#define                   SECURE0  0x1        /* SECURE 0 */
+#define                  nSECURE0  0x0       
+#define                   SECURE1  0x2        /* SECURE 1 */
+#define                  nSECURE1  0x0       
+#define                   SECURE2  0x4        /* SECURE 2 */
+#define                  nSECURE2  0x0       
+#define                   SECURE3  0x8        /* SECURE 3 */
+#define                  nSECURE3  0x0       
+
+/* Bit masks for SECURE_STATUS */
+
+#define                   SECMODE  0x3        /* Secured Mode Control State */
+#define                       NMI  0x4        /* Non Maskable Interrupt */
+#define                      nNMI  0x0       
+#define                   AFVALID  0x8        /* Authentication Firmware Valid */
+#define                  nAFVALID  0x0       
+#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
+#define                   nAFEXIT  0x0       
+#define                   SECSTAT  0xe0       /* Secure Status */
+
+/* Bit masks for NFC_CTL */
+
+#define                    WR_DLY  0xf        /* Write Strobe Delay */
+#define                    RD_DLY  0xf0       /* Read Strobe Delay */
+#define                    NWIDTH  0x100      /* NAND Data Width */
+#define                   nNWIDTH  0x0       
+#define                   PG_SIZE  0x200      /* Page Size */
+#define                  nPG_SIZE  0x0       
+
+/* Bit masks for NFC_STAT */
+
+#define                     NBUSY  0x1        /* Not Busy */
+#define                    nNBUSY  0x0       
+#define                   WB_FULL  0x2        /* Write Buffer Full */
+#define                  nWB_FULL  0x0       
+#define                PG_WR_STAT  0x4        /* Page Write Pending */
+#define               nPG_WR_STAT  0x0       
+#define                PG_RD_STAT  0x8        /* Page Read Pending */
+#define               nPG_RD_STAT  0x0       
+#define                  WB_EMPTY  0x10       /* Write Buffer Empty */
+#define                 nWB_EMPTY  0x0       
+
+/* Bit masks for NFC_IRQSTAT */
+
+#define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
+#define                 nNBUSYIRQ  0x0       
+#define                    WB_OVF  0x2        /* Write Buffer Overflow */
+#define                   nWB_OVF  0x0       
+#define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
+#define                  nWB_EDGE  0x0       
+#define                    RD_RDY  0x8        /* Read Data Ready */
+#define                   nRD_RDY  0x0       
+#define                   WR_DONE  0x10       /* Page Write Done */
+#define                  nWR_DONE  0x0       
+
+/* Bit masks for NFC_IRQMASK */
+
+#define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
+#define             nMASK_BUSYIRQ  0x0       
+#define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
+#define               nMASK_WBOVF  0x0       
+#define              MASK_WBEMPTY  0x4        /* Mask Write Buffer Empty */
+#define             nMASK_WBEMPTY  0x0       
+#define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
+#define               nMASK_RDRDY  0x0       
+#define               MASK_WRDONE  0x10       /* Mask Write Done */
+#define              nMASK_WRDONE  0x0       
+
+/* Bit masks for NFC_RST */
+
+#define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
+#define                  nECC_RST  0x0       
+
+/* Bit masks for NFC_PGCTL */
+
+#define               PG_RD_START  0x1        /* Page Read Start */
+#define              nPG_RD_START  0x0       
+#define               PG_WR_START  0x2        /* Page Write Start */
+#define              nPG_WR_START  0x0       
+
+/* Bit masks for NFC_ECC0 */
+
+#define                      ECC0  0x7ff      /* Parity Calculation Result0 */
+
+/* Bit masks for NFC_ECC1 */
+
+#define                      ECC1  0x7ff      /* Parity Calculation Result1 */
+
+/* Bit masks for NFC_ECC2 */
+
+#define                      ECC2  0x7ff      /* Parity Calculation Result2 */
+
+/* Bit masks for NFC_ECC3 */
+
+#define                      ECC3  0x7ff      /* Parity Calculation Result3 */
+
+/* Bit masks for NFC_COUNT */
+
+#define                    ECCCNT  0x3ff      /* Transfer Count */
+
+
+#endif /* _DEF_BF52X_H */
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
index 1d7c494ceb64..74f967b235e2 100644
--- a/include/asm-blackfin/mach-bf533/cdefBF532.h
+++ b/include/asm-blackfin/mach-bf533/cdefBF532.h
@@ -51,10 +51,6 @@
 #define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
 #define bfin_read_CHIPID()                   bfin_read32(CHIPID)
-#define bfin_read_SWRST()                    bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
-#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
 #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
 #define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
@@ -63,12 +59,14 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 {
         unsigned long flags, iwr;
 
-        bfin_write16(VR_CTL, val);
-        __builtin_bfin_ssync();
         /* Enable the PLL Wakeup bit in SIC IWR */
         iwr = bfin_read32(SIC_IWR);
         /* Only allow PPL Wakeup) */
         bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+        bfin_write16(VR_CTL, val);
+        __builtin_bfin_ssync();
+
         local_irq_save(flags);
         asm("IDLE;");
         local_irq_restore(flags);
@@ -76,6 +74,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 }
 
 /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
+#define bfin_read_SWRST()                    bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
+#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
 #define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
 #define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
@@ -115,6 +117,18 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_RTC_PREN()                 bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)
 
+/* DMA Traffic controls */
+#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
+#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
+#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
+#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define bfin_read_DMA_TC_PER()               bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)           bfin_write16(DMA_TC_PER,val)
+#define bfin_read_DMA_TC_CNT()               bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)           bfin_write16(DMA_TC_CNT,val)
+
 /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
 #define bfin_read_FIO_DIR()                  bfin_read16(FIO_DIR)
 #define bfin_write_FIO_DIR(val)              bfin_write16(FIO_DIR,val)
@@ -151,16 +165,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_FIO_MASKB_T()              bfin_read16(FIO_MASKB_T)
 #define bfin_write_FIO_MASKB_T(val)          bfin_write16(FIO_MASKB_T,val)
 
-/* DMA Traffic controls */
-#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
-#define bfin_read_DMA_TC_PER()               bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)           bfin_write16(DMA_TC_PER,val)
-#define bfin_read_DMA_TC_CNT()               bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)           bfin_write16(DMA_TC_CNT,val)
-
 /* DMA Controller */
 #define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index b240a082aa09..6a3cf93f8b57 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -46,11 +46,7 @@
 
 #ifndef _DEF_BF532_H
 #define _DEF_BF532_H
-/*
-#if !defined(__ADSPLPBLACKFIN__)
-#warning defBF532.h should only be included for 532 compatible chips
-#endif
-*/
+
 /* include all Core registers and bit definitions */
 #include <asm/mach-common/def_LPBlackfin.h>
 
@@ -65,10 +61,10 @@
 #define PLL_STAT               0xFFC0000C       /* PLL Status register (16-bit) */
 #define PLL_LOCKCNT            0xFFC00010       /* PLL Lock Count register (16-bit) */
 #define CHIPID                 0xFFC00014       /* Chip ID Register */
-#define SWRST                  0xFFC00100       /* Software Reset Register (16-bit) */
-#define SYSCR                  0xFFC00104       /* System Configuration registe */
 
 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST                   0xFFC00100  /* Software Reset Register (16-bit) */
+#define SYSCR                   0xFFC00104  /* System Configuration registe */
 #define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register */
 #define SIC_IMASK                       0xFFC0010C      /* Interrupt Mask Register */
 #define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0 */
@@ -218,11 +214,13 @@
 #define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register */
 
 /* DMA Traffic controls */
-#define DMA_TCPER 0xFFC00B0C    /* Traffic Control Periods Register */
-#define DMA_TCCNT 0xFFC00B10    /* Traffic Control Current Counts Register */
 #define DMA_TC_PER 0xFFC00B0C   /* Traffic Control Periods Register */
 #define DMA_TC_CNT 0xFFC00B10   /* Traffic Control Current Counts Register */
 
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA_TCPER 0xFFC00B0C    /* Traffic Control Periods Register */
+#define DMA_TCCNT 0xFFC00B10    /* Traffic Control Current Counts Register */
+
 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
 #define DMA0_CONFIG             0xFFC00C08      /* DMA Channel 0 Configuration Register */
 #define DMA0_NEXT_DESC_PTR      0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -407,14 +405,25 @@
 /* ********************* PLL AND RESET MASKS ************************ */
 
 /* PLL_CTL Masks */
-#define PLL_CLKIN              0x00000000       /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2         0x00000001       /* Pass CLKIN/2 to PLL */
-#define PLL_OFF                0x00000002       /* Shut off PLL clocks */
-#define STOPCK_OFF             0x00000008       /* Core clock off */
-#define PDWN                   0x00000020       /* Put the PLL in a Deep Sleep state */
-#define BYPASS                 0x00000100       /* Bypass the PLL */
+#define PLL_CLKIN                       0x0000  /* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2                  0x0001  /* Pass CLKIN/2 to PLL */
+#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
+#define PLL_OFF                         0x0002  /* Shut off PLL clocks */
+#define STOPCK_OFF                      0x0008  /* Core clock off */
+#define STOPCK                          0x0008  /* Core Clock Off                                                                       */
+#define PDWN                            0x0020  /* Put the PLL in a Deep Sleep state */
+#if !defined(__ADSPBF538__)
+/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
+# define IN_DELAY        0x0040  /* Add 200ps Delay To EBIU Input Latches */
+# define OUT_DELAY       0x0080  /* Add 200ps Delay To EBIU Output Signals */
+#endif
+#define BYPASS                          0x0100  /* Bypass the PLL */
+/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
+#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
 
 /* PLL_DIV Masks */
+#define SSEL                            0x000F  /* System Select                                                */
+#define CSEL                            0x0030  /* Core Select                                                  */
 
 #define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
 
@@ -422,6 +431,8 @@
 #define CCLK_DIV2              0x00000010       /* CCLK = VCO / 2 */
 #define CCLK_DIV4              0x00000020       /* CCLK = VCO / 4 */
 #define CCLK_DIV8              0x00000030       /* CCLK = VCO / 8 */
+/* PLL_DIV Macros                                                                                                               */
+#define SET_SSEL(x)                     ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
 
 /* PLL_STAT Masks                                                                                                                                       */
 #define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
@@ -429,13 +440,47 @@
 #define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
 #define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
 
+/* VR_CTL Masks                                                                                                                                 */
+#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
+#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
+#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
+#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
+
+#define GAIN                    0x000C  /* Voltage Level Gain   */
+#define GAIN_5                  0x0000  /*              GAIN = 5                */
+#define GAIN_10                 0x0004  /*              GAIN = 10               */
+#define GAIN_20                 0x0008  /*              GAIN = 20               */
+#define GAIN_50                 0x000C  /*              GAIN = 50               */
+
+#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
+#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
+#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
+#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
+#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
+#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
+#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
+#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
+#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
+
+#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
+#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
+
 /* CHIPID Masks */
 #define CHIPID_VERSION         0xF0000000
 #define CHIPID_FAMILY          0x0FFFF000
 #define CHIPID_MANUFACTURE     0x00000FFE
 
 /* SWRST Mask */
-#define SYSTEM_RESET           0x00000007       /* Initiates a system software reset */
+#define SYSTEM_RESET    0x0007  /* Initiates A System Software Reset                    */
+#define DOUBLE_FAULT    0x0008  /* Core Double Fault Causes Reset                               */
+#define RESET_DOUBLE    0x2000  /* SW Reset Generated By Core Double-Fault              */
+#define RESET_WDOG      0x4000  /* SW Reset Generated By Watchdog Timer                 */
+#define RESET_SOFTWARE  0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
+
+/* SYSCR Masks                                                                                                                                                          */
+#define BMODE                   0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins   */
+#define NOBOOT                  0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
 
 /* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
 
@@ -483,23 +528,6 @@
 #define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
 
-/* *********  WATCHDOG TIMER MASKS  ********************8 */
-
-/* Watchdog Timer WDOG_CTL Register */
-#define ICTL(x) ((x<<1) & 0x0006)
-#define ENABLE_RESET     0x00000000     /* Set Watchdog Timer to generate reset */
-#define ENABLE_NMI       0x00000002     /* Set Watchdog Timer to generate non-maskable interrupt */
-#define ENABLE_GPI       0x00000004     /* Set Watchdog Timer to generate general-purpose interrupt */
-#define DISABLE_EVT      0x00000006     /* Disable Watchdog Timer interrupts */
-
-#define TMR_EN          0x0000
-#define TMR_DIS         0x0AD0
-#define TRO             0x8000
-
-#define ICTL_P0         0x01
-#define ICTL_P1         0x02
-#define TRO_P           0x0F
-
 /* ***************************** UART CONTROLLER MASKS ********************** */
 
 /* UART_LCR Register */
@@ -583,6 +611,9 @@
 #define TSPEN    0x0001         /* TX enable  */
 #define ITCLK    0x0002         /* Internal TX Clock Select  */
 #define TDTYPE   0x000C         /* TX Data Formatting Select */
+#define DTYPE_NORM      0x0000          /* Data Format Normal                                                   */
+#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
+#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
 #define TLSBIT   0x0010         /* TX Bit Order */
 #define ITFS     0x0200         /* Internal TX Frame Sync Select  */
 #define TFSR     0x0400         /* TX Frame Sync Required Select  */
@@ -592,7 +623,12 @@
 #define TCKFE    0x4000         /* TX Clock Falling Edge Select  */
 
 /* SPORTx_TCR2 Masks */
-#define SLEN        0x001F      /*TX Word Length  */
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
+    defined(__ADSPBF533__)
+# define SLEN       0x001F      /*TX Word Length  */
+#else
+# define SLEN(x)                ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
+#endif
 #define TXSE        0x0100      /*TX Secondary Enable */
 #define TSFSE       0x0200      /*TX Stereo Frame Sync Enable */
 #define TRFST       0x0400      /*TX Right-First Data Order  */
@@ -601,8 +637,9 @@
 #define RSPEN    0x0001         /* RX enable  */
 #define IRCLK    0x0002         /* Internal RX Clock Select  */
 #define RDTYPE   0x000C         /* RX Data Formatting Select */
-#define RULAW    0x0008         /* u-Law enable  */
-#define RALAW    0x000C         /* A-Law enable  */
+#define DTYPE_NORM      0x0000          /* no companding                                                        */
+#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
+#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
 #define RLSBIT   0x0010         /* RX Bit Order */
 #define IRFS     0x0200         /* Internal RX Frame Sync Select  */
 #define RFSR     0x0400         /* RX Frame Sync Required Select  */
@@ -611,7 +648,7 @@
 #define RCKFE    0x4000         /* RX Clock Falling Edge Select  */
 
 /* SPORTx_RCR2 Masks */
-#define SLEN        0x001F      /*RX Word Length  */
+/* SLEN defined above */
 #define RXSE        0x0100      /*RX Secondary Enable */
 #define RSFSE       0x0200      /*RX Stereo Frame Sync Enable */
 #define RRFST       0x0400      /*Right-First Data Order  */
@@ -628,14 +665,37 @@
 /*SPORTx_MCMC1 Masks */
 #define SP_WSIZE                0x0000F000      /*Multichannel Window Size Field */
 #define SP_WOFF         0x000003FF      /*Multichannel Window Offset Field */
+/* SPORTx_MCMC1 Macros                                                                                                                  */
+#define SET_SP_WOFF(x)  ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
+/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits                                                */
+#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
 
 /*SPORTx_MCMC2 Masks */
-#define MCCRM           0x00000003      /*Multichannel Clock Recovery Mode */
-#define MCDTXPE         0x00000004      /*Multichannel DMA Transmit Packing */
-#define MCDRXPE         0x00000008      /*Multichannel DMA Receive Packing */
-#define MCMEN           0x00000010      /*Multichannel Frame Mode Enable */
-#define FSDR            0x00000080      /*Multichannel Frame Sync to Data Relationship */
-#define MFD             0x0000F000      /*Multichannel Frame Delay    */
+#define MCCRM           0x00000003      /*Multichannel Clock Recovery Mode */
+#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
+#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
+#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
+#define MCDTXPE         0x00000004      /*Multichannel DMA Transmit Packing */
+#define MCDRXPE         0x00000008      /*Multichannel DMA Receive Packing */
+#define MCMEN           0x00000010      /*Multichannel Frame Mode Enable */
+#define FSDR            0x00000080      /*Multichannel Frame Sync to Data Relationship */
+#define MFD             0x0000F000      /*Multichannel Frame Delay    */
+#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
+#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
+#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
+#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
+#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
+#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
+#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
+#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
+#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
+#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
+#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
+#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
+#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
+#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
+#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
+#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
 
 /*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
 
@@ -660,6 +720,8 @@
 #define DLEN_16                 0x3800  /* Data Length = 16 Bits                        */
 #define DLEN(x) (((x-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
 #define POL                  0x0000C000 /* PPI Signal Polarities       */
+#define POLC            0x4000          /* PPI Clock Polarity                           */
+#define POLS            0x8000          /* PPI Frame Sync Polarity                      */
 
 /* PPI_STATUS Masks                                          */
 #define FLD                  0x00000400 /* Field Indicator   */
@@ -729,6 +791,15 @@
 #define PCAPRD              0x00000800  /* DMA Read Operation Indicator */
 #define PMAP                0x00007000  /* DMA Peripheral Map Field */
 
+#define PMAP_PPI                0x0000  /* PMAP PPI Port DMA */
+#define PMAP_SPORT0RX           0x1000  /* PMAP SPORT0 Receive DMA */
+#define PMAP_SPORT0TX           0x2000  /* PMAP SPORT0 Transmit DMA */
+#define PMAP_SPORT1RX           0x3000  /* PMAP SPORT1 Receive DMA */
+#define PMAP_SPORT1TX           0x4000  /* PMAP SPORT1 Transmit DMA */
+#define PMAP_SPI                0x5000  /* PMAP SPI DMA */
+#define PMAP_UARTRX             0x6000  /* PMAP UART Receive DMA */
+#define PMAP_UARTTX             0x7000  /* PMAP UART Transmit DMA */
+
 /*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
 
 /* PWM Timer bit definitions */
@@ -755,9 +826,9 @@
 #define TIMIL0          0x0001
 #define TIMIL1          0x0002
 #define TIMIL2          0x0004
-#define TOVL_ERR0       0x0010
-#define TOVL_ERR1       0x0020
-#define TOVL_ERR2       0x0040
+#define TOVF_ERR0               0x0010  /* Timer 0 Counter Overflow             */
+#define TOVF_ERR1               0x0020  /* Timer 1 Counter Overflow             */
+#define TOVF_ERR2               0x0040  /* Timer 2 Counter Overflow             */
 #define TRUN0           0x1000
 #define TRUN1           0x2000
 #define TRUN2           0x4000
@@ -765,13 +836,21 @@
 #define TIMIL0_P        0x00
 #define TIMIL1_P        0x01
 #define TIMIL2_P        0x02
-#define TOVL_ERR0_P     0x04
-#define TOVL_ERR1_P     0x05
-#define TOVL_ERR2_P     0x06
+#define TOVF_ERR0_P             0x04
+#define TOVF_ERR1_P             0x05
+#define TOVF_ERR2_P             0x06
 #define TRUN0_P         0x0C
 #define TRUN1_P         0x0D
 #define TRUN2_P         0x0E
 
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0               TOVF_ERR0
+#define TOVL_ERR1               TOVF_ERR1
+#define TOVL_ERR2               TOVF_ERR2
+#define TOVL_ERR0_P             TOVF_ERR0_P
+#define TOVL_ERR1_P             TOVF_ERR1_P
+#define TOVL_ERR2_P             TOVF_ERR2_P
+
 /* TIMERx_CONFIG Registers */
 #define PWM_OUT         0x0001
 #define WDTH_CAP        0x0002
@@ -841,6 +920,10 @@
 
 /* SPI_CTL Masks */
 #define TIMOD                  0x00000003       /* Transfer initiation mode and interrupt generation */
+#define RDBR_CORE       0x0000          /*              RDBR Read Initiates, IRQ When RDBR Full         */
+#define TDBR_CORE       0x0001          /*              TDBR Write Initiates, IRQ When TDBR Empty       */
+#define RDBR_DMA        0x0002          /*              DMA Read, DMA Until FIFO Empty                          */
+#define TDBR_DMA        0x0003          /*              DMA Write, DMA Until FIFO Full                          */
 #define SZ                     0x00000004       /* Send Zero (=0) or last (=1) word when TDBR empty. */
 #define GM                     0x00000008       /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
 #define PSSE                   0x00000010       /* Enable (=1) Slave-Select input for Master. */
@@ -894,10 +977,20 @@
 #define RXS                    0x00000020       /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
 #define TXCOL                  0x00000040       /* When set (=1), corrupt data may have been transmitted  */
 
+/* SPIx_FLG Masks                                                                                                                                       */
+#define FLG1E   0xFDFF          /* Activates SPI_FLOUT1                                                         */
+#define FLG2E   0xFBFF          /* Activates SPI_FLOUT2                                                         */
+#define FLG3E   0xF7FF          /* Activates SPI_FLOUT3                                                         */
+#define FLG4E   0xEFFF          /* Activates SPI_FLOUT4                                                         */
+#define FLG5E   0xDFFF          /* Activates SPI_FLOUT5                                                         */
+#define FLG6E   0xBFFF          /* Activates SPI_FLOUT6                                                         */
+#define FLG7E   0x7FFF          /* Activates SPI_FLOUT7                                                         */
+
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
 
 /* AMGCTL Masks */
 #define AMCKEN                  0x00000001      /* Enable CLKOUT */
+#define AMBEN_NONE              0x00000000      /* All Banks Disabled                                                           */
 #define AMBEN_B0                0x00000002      /* Enable Asynchronous Memory Bank 0 only */
 #define AMBEN_B0_B1             0x00000004      /* Enable Asynchronous Memory Banks 0 & 1 only */
 #define AMBEN_B0_B1_B2          0x00000006      /* Enable Asynchronous Memory Banks 0, 1, and 2 */
@@ -1097,6 +1190,9 @@
 #define CL_3                    0x0000000C      /* SDRAM CAS latency = 3 cycles */
 #define PFE                     0x00000010      /* Enable SDRAM prefetch */
 #define PFP                     0x00000020      /* Prefetch has priority over AMC requests */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
 #define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle */
 #define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles */
 #define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles */
@@ -1158,18 +1254,5 @@
 #define SDEASE                0x00000010        /* SDRAM EAB sticky error status - W1C */
 #define BGSTAT                  0x00000020      /* Bus granted */
 
-/*VR_CTL Masks*/
-#define WAKE                    0x100
-#define VLEV_6                  0x60
-#define VLEV_7                  0x70
-#define VLEV_8                  0x80
-#define VLEV_9                  0x90
-#define VLEV_10                 0xA0
-#define VLEV_11                 0xB0
-#define VLEV_12                 0xC0
-#define VLEV_13                 0xD0
-#define VLEV_14                 0xE0
-#define VLEV_15                 0xF0
-#define FREQ_3                  0x03
 
 #endif                          /* _DEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
index 7b658c175f85..84e58fa73dce 100644
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -51,12 +51,14 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 {
         unsigned long flags, iwr;
 
-        bfin_write16(VR_CTL, val);
-        __builtin_bfin_ssync();
         /* Enable the PLL Wakeup bit in SIC IWR */
         iwr = bfin_read32(SIC_IWR);
         /* Only allow PPL Wakeup) */
         bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+        bfin_write16(VR_CTL, val);
+        __builtin_bfin_ssync();
+
         local_irq_save(flags);
         asm("IDLE;");
         local_irq_restore(flags);
@@ -73,7 +75,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
 #define bfin_read_SYSCR()                    bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
-#define pSIC_RVECT                      ((void * volatile *)SIC_RVECT)
 #define bfin_read_SIC_RVECT()                bfin_read32(SIC_RVECT)
 #define bfin_write_SIC_RVECT(val)            bfin_write32(SIC_RVECT,val)
 #define bfin_read_SIC_IMASK()                bfin_read32(SIC_IMASK)
@@ -398,10 +399,14 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
 
 /* DMA Traffic Control Registers                                                                                                        */
-#define pDMA_TCPER                      ((volatile unsigned short *)DMA_TCPER)
+#define bfin_read_DMA_TC_PER()                bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)            bfin_write16(DMA_TC_PER,val)
+#define bfin_read_DMA_TC_CNT()                bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)            bfin_write16(DMA_TC_CNT,val)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
 #define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
 #define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define pDMA_TCCNT                      ((volatile unsigned short *)DMA_TCCNT)
 #define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
 #define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
 
@@ -1076,8 +1081,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_write_CAN_UCRC(val)             bfin_write16(CAN_UCRC,val)
 #define bfin_read_CAN_UCCNF()                bfin_read16(CAN_UCCNF)
 #define bfin_write_CAN_UCCNF(val)            bfin_write16(CAN_UCCNF,val)
-#define bfin_read_CAN_SFCMVER2()             bfin_read16(CAN_SFCMVER2)
-#define bfin_write_CAN_SFCMVER2(val)         bfin_write16(CAN_SFCMVER2,val)
 
 /* Mailbox Acceptance Masks */
 #define bfin_read_CAN_AM00L()                bfin_read16(CAN_AM00L)
diff --git a/include/asm-blackfin/mach-bf537/cdefBF537.h b/include/asm-blackfin/mach-bf537/cdefBF537.h
index 932a1b6b5d14..b8fc949a991f 100644
--- a/include/asm-blackfin/mach-bf537/cdefBF537.h
+++ b/include/asm-blackfin/mach-bf537/cdefBF537.h
@@ -40,7 +40,6 @@
 
 /* Include Macro "Defines" For EMAC (Unique to BF536/BF537              */
 /* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF)                                               */
-#define pEMAC_OPMODE            ((volatile unsigned long  *)EMAC_OPMODE)
 #define bfin_read_EMAC_OPMODE()              bfin_read32(EMAC_OPMODE)
 #define bfin_write_EMAC_OPMODE(val)          bfin_write32(EMAC_OPMODE,val)
 #define bfin_read_EMAC_ADDRLO()              bfin_read32(EMAC_ADDRLO)
@@ -80,7 +79,6 @@
 #define bfin_read_EMAC_WKUP_FFCRC1()         bfin_read32(EMAC_WKUP_FFCRC1)
 #define bfin_write_EMAC_WKUP_FFCRC1(val)     bfin_write32(EMAC_WKUP_FFCRC1,val)
 
-#define pEMAC_SYSCTL            ((volatile unsigned long  *)EMAC_SYSCTL)
 #define bfin_read_EMAC_SYSCTL()              bfin_read32(EMAC_SYSCTL)
 #define bfin_write_EMAC_SYSCTL(val)          bfin_write32(EMAC_SYSCTL,val)
 #define bfin_read_EMAC_SYSTAT()              bfin_read32(EMAC_SYSTAT)
@@ -147,7 +145,6 @@
 #define bfin_write_EMAC_RXC_SHORT(val)       bfin_write32(EMAC_RXC_SHORT,val)
 #define bfin_read_EMAC_RXC_EQ64()            bfin_read32(EMAC_RXC_EQ64)
 #define bfin_write_EMAC_RXC_EQ64(val)        bfin_write32(EMAC_RXC_EQ64,val)
-#define pEMAC_RXC_LT128         ((volatile unsigned long  *)EMAC_RXC_LT128)
 #define bfin_read_EMAC_RXC_LT128()           bfin_read32(EMAC_RXC_LT128)
 #define bfin_write_EMAC_RXC_LT128(val)       bfin_write32(EMAC_RXC_LT128,val)
 #define bfin_read_EMAC_RXC_LT256()           bfin_read32(EMAC_RXC_LT256)
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
index e605e9709004..1859f2fee5a7 100644
--- a/include/asm-blackfin/mach-bf537/defBF534.h
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -216,8 +216,12 @@
 #define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
 
 /* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
+#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
 
 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
 #define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
@@ -563,7 +567,7 @@
 #define CAN_GIF                         0xFFC02A9C      /* Global Interrupt Flag Register                               */
 #define CAN_CONTROL                     0xFFC02AA0      /* Master Control Register                                              */
 #define CAN_INTR                        0xFFC02AA4      /* Interrupt Pending Register                                   */
-#define CAN_SFCMVER                     0xFFC02AA8      /* Version Code Register                                                */
+
 #define CAN_MBTD                        0xFFC02AAC      /* Mailbox Temporary Disable Feature                    */
 #define CAN_EWR                         0xFFC02AB0      /* Programmable Warning Level                                   */
 #define CAN_ESR                         0xFFC02AB4      /* Error Status Register                                                */
@@ -1026,10 +1030,11 @@
 #define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
 
 #define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define PHYWE                   0x0200  /* Enable PHY Wakeup From Hibernate                     */
-#define CANWE                   0x0400  /* Enable CAN Wakeup From Hibernate                     */
-#define PHYCLKOE                0x4000  /* PHY Clock Output Enable                                      */
-#define CKELOW                  0x8000  /* Enable Drive CKE Low During Reset            */
+#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate                     */
+#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
+#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
+#define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
+#define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
 
 /* PLL_STAT Masks                                                                                                                                       */
 #define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
@@ -1050,7 +1055,7 @@
 #define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
 
 /* SYSCR Masks                                                                                                                                                          */
-#define BMODE                           0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins   */
+#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
 #define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
 
 /* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
@@ -1107,19 +1112,9 @@
 #define IWR_ENABLE(x)   (1 << ((x)&0x1F))       /* Wakeup Enable Peripheral #x          */
 #define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
 
-/* ***************  WATCHDOG TIMER MASKS  *******************************************/
-/* WDOG_CTL Masks                                                                                                                                       */
-#define WDOG_RESET              0x0000  /* Generate Reset Event                                                 */
-#define WDOG_NMI                0x0002  /* Generate Non-Maskable Interrupt (NMI) Event  */
-#define WDOG_GPI                0x0004  /* Generate General Purpose (GP) Interrupt              */
-#define WDOG_NONE               0x0006  /* Disable Watchdog Timer Interrupts                    */
-#define TMR_EN                  0x0FF0  /* Watchdog Counter Enable                                              */
-#define TMR_DIS                 0x0AD0  /* Watchdog Counter Disable                                             */
-#define TRO                     0x8000  /* Watchdog Expired                                                     */
-
 /* ************** UART CONTROLLER MASKS *************************/
 /* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          ((((x)&0x3)-5) & 0x03)  /* Word Length Select   */
+#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select   */
 #define STB                     0x04    /* Stop Bits                    */
 #define PEN                     0x08    /* Parity Enable                */
 #define EPS                     0x10    /* Even Parity Select   */
@@ -1128,8 +1123,8 @@
 #define DLAB            0x80    /* Divisor Latch Access */
 
 /* UARTx_MCR Mask                                                                               */
-#define LOOP            0x10    /* Loopback Mode Enable         */
-
+#define LOOP_ENA                0x10    /* Loopback Mode Enable         */
+#define LOOP_ENA_P      0x04
 /* UARTx_LSR Masks                                                                              */
 #define DR                      0x01    /* Data Ready                           */
 #define OE                      0x02    /* Overrun Error                        */
@@ -1229,10 +1224,10 @@
 #define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
 #define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
 #define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
-#define TOVL_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
-#define TOVL_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
-#define TOVL_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
-#define TOVL_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
+#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
+#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
+#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
+#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
 #define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
 #define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
 #define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
@@ -1241,15 +1236,24 @@
 #define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
 #define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
 #define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
-#define TOVL_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
-#define TOVL_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
-#define TOVL_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
-#define TOVL_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
+#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
+#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
+#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
+#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
 #define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
 #define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
 #define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
 #define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
 
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
 /* TIMERx_CONFIG Masks                                                                                                  */
 #define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
 #define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
@@ -1647,6 +1651,8 @@
 #define EBSZ_32                 0x0002  /* SDRAM External Bank Size = 32MB                                              */
 #define EBSZ_64                 0x0004  /* SDRAM External Bank Size = 64MB                                              */
 #define EBSZ_128                0x0006  /* SDRAM External Bank Size = 128MB                                             */
+#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
+#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
 #define EBCAW_8                 0x0000  /* SDRAM External Bank Column Address Width = 8 Bits    */
 #define EBCAW_9                 0x0010  /* SDRAM External Bank Column Address Width = 9 Bits    */
 #define EBCAW_10                0x0020  /* SDRAM External Bank Column Address Width = 10 Bits   */
@@ -1859,8 +1865,10 @@
 #define TXECNT          0xFF00  /* Transmit Error Counter       */
 
 /* CAN_INTR Masks                                                                                       */
-#define MBRIF           0x0001  /* Mailbox Receive Interrupt    */
-#define MBTIF           0x0002  /* Mailbox Transmit Interrupt   */
+#define MBRIRQ  0x0001  /* Mailbox Receive Interrupt    */
+#define MBRIF           MBRIRQ  /* legacy */
+#define MBTIRQ  0x0002  /* Mailbox Transmit Interrupt   */
+#define MBTIF           MBTIRQ  /* legacy */
 #define GIRQ            0x0004  /* Global Interrupt                             */
 #define SMACK           0x0008  /* Sleep Mode Acknowledge               */
 #define CANTX           0x0040  /* CAN TX Bus Value                             */
@@ -2445,8 +2453,8 @@
 #define PJCE_SPI                0x0004  /*              Enable SPI_SSEL7                        */
 
 #define PFDE                    0x0008  /* Port F DMA Request Enable            */
-#define PGDE_UART               0x0000  /*              Enable UART0 RX/TX                      */
-#define PGDE_DMA                0x0008  /*              Enable DMAR1:0                          */
+#define PFDE_UART               0x0000  /*              Enable UART0 RX/TX                      */
+#define PFDE_DMA                0x0008  /*              Enable DMAR1:0                          */
 
 #define PFTE                    0x0010  /* Port F Timer Enable                          */
 #define PFTE_UART               0x0000  /*              Enable UART1 RX/TX                      */
@@ -2498,4 +2506,20 @@
 #define OI                      0x4000  /* Overflow Interrupt Generated                         */
 #define BDI                     0x8000  /* Block Done Interrupt Generated                       */
 
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000 
+#define _BOOTROM_FINAL_INIT 0xEF000002 
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define PGDE_UART   PFDE_UART
+#define PGDE_DMA    PFDE_DMA
+#define CKELOW          SCKELOW
 #endif                          /* _DEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF537.h b/include/asm-blackfin/mach-bf537/defBF537.h
index 26f9c02eb73c..3f455909c418 100644
--- a/include/asm-blackfin/mach-bf537/defBF537.h
+++ b/include/asm-blackfin/mach-bf537/defBF537.h
@@ -32,12 +32,12 @@
 #ifndef _DEF_BF537_H
 #define _DEF_BF537_H
 
-/*include all Core registers and bit definitions*/
-#include "defBF537.h"
-
-/*include core specific register pointer definitions*/
+/* Include all Core registers and bit definitions*/
 #include <asm/mach-common/cdef_LPBlackfin.h>
 
+/* Include all MMR and bit defines common to BF534 */
+#include "defBF534.h"
+
 /************************************************************************************
 ** Define EMAC Section Unique to BF536/BF537
 *************************************************************************************/
diff --git a/include/asm-blackfin/mach-bf548/cdefBF542.h b/include/asm-blackfin/mach-bf548/cdefBF542.h
new file mode 100644
index 000000000000..308b33ab5311
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/cdefBF542.h
@@ -0,0 +1,590 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/cdefBF542.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF542_H
+#define _CDEF_BF542_H
+
+/* include all Core registers and bit definitions */
+#include "defBF542.h"
+
+/* include core sbfin_read_()ecific register pointer definitions */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
+
+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
+#include "cdefBF54x_base.h"
+
+/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
+
+/* ATAPI Registers */
+
+#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
+#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
+#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
+#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
+#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
+#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
+#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
+#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
+#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
+#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
+#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
+#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
+#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
+#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
+#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
+
+/* SDH Registers */
+
+#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
+#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
+#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
+#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
+#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
+#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
+#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
+#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
+#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
+#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
+#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
+#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
+#define bfin_read_SDH_DATA_CNT()        fin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
+#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
+#define bfin_read_SDH_STATUS_CLR()      fin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val)  fin_write16(SDH_STATUS_CLR, val)
+#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
+#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
+#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
+#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
+#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
+#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
+#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
+#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
+#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
+#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
+#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
+#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
+#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
+#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
+#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
+#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
+
+/* USB Control Registers */
+
+#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
+#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
+#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
+#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
+#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
+#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
+#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
+#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
+#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
+#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
+#define bfin_read_USB_TESTMODE()        fin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)    fin_write16(USB_TESTMODE, val)
+#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
+#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val)  bfin_write16(USB_GLOBAL_CTL, val)
+
+/* USB Packet Control Registers */
+
+#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
+#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
+#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
+#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
+#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
+#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
+#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
+#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
+#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
+#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
+#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
+#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
+#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
+
+/* USB Endbfin_read_()oint FIFO Registers */
+
+#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
+#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
+#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
+#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
+#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
+#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
+#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
+#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
+
+/* USB OTG Control Registers */
+
+#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
+#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val)        fin_write16(USB_OTG_VBUS_IRQ, val)
+#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
+
+/* USB Phy Control Registers */
+
+#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
+#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
+#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
+#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
+#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
+#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
+#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
+#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
+
+/* USB Endbfin_read_()oint 0 Control Registers */
+
+#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
+#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
+#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 1 Control Registers */
+
+#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
+#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
+#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 2 Control Registers */
+
+#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
+#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
+#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 3 Control Registers */
+
+#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
+#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
+#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 4 Control Registers */
+
+#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
+#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
+#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 5 Control Registers */
+
+#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
+#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
+#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 6 Control Registers */
+
+#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
+#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
+#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 7 Control Registers */
+
+#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
+#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
+#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
+
+/* USB Channel 0 Config Registers */
+
+#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
+#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
+#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
+#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
+#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
+#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
+#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
+#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
+#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
+#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
+
+/* USB Channel 1 Config Registers */
+
+#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
+#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
+#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
+#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
+#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
+#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
+#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
+#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
+#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
+#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
+
+/* USB Channel 2 Config Registers */
+
+#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
+#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
+#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
+#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
+#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
+#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
+#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
+#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
+#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
+#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
+
+/* USB Channel 3 Config Registers */
+
+#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
+#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
+#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
+#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
+#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
+#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
+#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
+#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
+#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
+#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
+
+/* USB Channel 4 Config Registers */
+
+#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
+#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
+#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
+#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
+#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
+#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
+#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
+#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
+#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
+#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
+
+/* USB Channel 5 Config Registers */
+
+#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
+#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
+#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
+#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
+#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
+#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
+#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
+#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
+#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
+#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
+
+/* USB Channel 6 Config Registers */
+
+#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
+#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
+#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
+#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
+#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
+#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
+#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
+#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
+#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
+#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
+
+/* USB Channel 7 Config Registers */
+
+#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
+#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
+#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
+#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
+#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
+#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
+#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
+#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
+#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
+#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
+
+/* Keybfin_read_()ad Registers */
+
+#define bfin_read_KPAD_CTL()                    bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)                bfin_write16(KPAD_CTL, val)
+#define bfin_read_KPAD_PRESCALE()               bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)           bfin_write16(KPAD_PRESCALE, val)
+#define bfin_read_KPAD_MSEL()                   bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)               bfin_write16(KPAD_MSEL, val)
+#define bfin_read_KPAD_ROWCOL()                 bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)             bfin_write16(KPAD_ROWCOL, val)
+#define bfin_read_KPAD_STAT()                   bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)               bfin_write16(KPAD_STAT, val)
+#define bfin_read_KPAD_SOFTEVAL()               bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)           bfin_write16(KPAD_SOFTEVAL, val)
+
+#endif /* _CDEF_BF542_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF544.h b/include/asm-blackfin/mach-bf548/cdefBF544.h
new file mode 100644
index 000000000000..7a2d177c8dc2
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/cdefBF544.h
@@ -0,0 +1,978 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/cdefBF544.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF544_H
+#define _CDEF_BF544_H
+
+/* include all Core registers and bit definitions */
+#include "defBF544.h"
+
+/* include core sbfin_read_()ecific register pointer definitions */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
+
+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
+#include "cdefBF54x_base.h"
+
+/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
+
+/* Timer Registers */
+
+#define bfin_read_TIMER8_CONFIG()               bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)           bfin_write16(TIMER8_CONFIG, val)
+#define bfin_read_TIMER8_COUNTER()              bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val)          bfin_write32(TIMER8_COUNTER, val)
+#define bfin_read_TIMER8_PERIOD()               bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)           bfin_write32(TIMER8_PERIOD, val)
+#define bfin_read_TIMER8_WIDTH()                bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)            bfin_write32(TIMER8_WIDTH, val)
+#define bfin_read_TIMER9_CONFIG()               bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)           bfin_write16(TIMER9_CONFIG, val)
+#define bfin_read_TIMER9_COUNTER()              bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val)          bfin_write32(TIMER9_COUNTER, val)
+#define bfin_read_TIMER9_PERIOD()               bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)           bfin_write32(TIMER9_PERIOD, val)
+#define bfin_read_TIMER9_WIDTH()                bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)            bfin_write32(TIMER9_WIDTH, val)
+#define bfin_read_TIMER10_CONFIG()              bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val)          bfin_write16(TIMER10_CONFIG, val)
+#define bfin_read_TIMER10_COUNTER()             bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val)         bfin_write32(TIMER10_COUNTER, val)
+#define bfin_read_TIMER10_PERIOD()              bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val)          bfin_write32(TIMER10_PERIOD, val)
+#define bfin_read_TIMER10_WIDTH()               bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)           bfin_write32(TIMER10_WIDTH, val)
+
+/* Timer Groubfin_read_() of 3 */
+
+#define bfin_read_TIMER_ENABLE1()               bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)           bfin_write16(TIMER_ENABLE1, val)
+#define bfin_read_TIMER_DISABLE1()              bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val)          bfin_write16(TIMER_DISABLE1, val)
+#define bfin_read_TIMER_STATUS1()               bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)           bfin_write32(TIMER_STATUS1, val)
+
+/* EPPI0 Registers */
+
+#define bfin_read_EPPI0_STATUS()                bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)            bfin_write16(EPPI0_STATUS, val)
+#define bfin_read_EPPI0_HCOUNT()                bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)            bfin_write16(EPPI0_HCOUNT, val)
+#define bfin_read_EPPI0_HDELAY()                bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)            bfin_write16(EPPI0_HDELAY, val)
+#define bfin_read_EPPI0_VCOUNT()                bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)            bfin_write16(EPPI0_VCOUNT, val)
+#define bfin_read_EPPI0_VDELAY()                bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)            bfin_write16(EPPI0_VDELAY, val)
+#define bfin_read_EPPI0_FRAME()                 bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)             bfin_write16(EPPI0_FRAME, val)
+#define bfin_read_EPPI0_LINE()                  bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)              bfin_write16(EPPI0_LINE, val)
+#define bfin_read_EPPI0_CLKDIV()                bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)            bfin_write16(EPPI0_CLKDIV, val)
+#define bfin_read_EPPI0_CONTROL()               bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)           bfin_write32(EPPI0_CONTROL, val)
+#define bfin_read_EPPI0_FS1W_HBL()              bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val)          bfin_write32(EPPI0_FS1W_HBL, val)
+#define bfin_read_EPPI0_FS1P_AVPL()             bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val)         bfin_write32(EPPI0_FS1P_AVPL, val)
+#define bfin_read_EPPI0_FS2W_LVB()              bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val)          bfin_write32(EPPI0_FS2W_LVB, val)
+#define bfin_read_EPPI0_FS2P_LAVF()             bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val)         bfin_write32(EPPI0_FS2P_LAVF, val)
+#define bfin_read_EPPI0_CLIP()                  bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)              bfin_write32(EPPI0_CLIP, val)
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define bfin_read_TWI1_CLKDIV()                 bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)             bfin_write16(TWI1_CLKDIV, val)
+#define bfin_read_TWI1_CONTROL()                bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)            bfin_write16(TWI1_CONTROL, val)
+#define bfin_read_TWI1_SLAVE_CTRL()             bfin_read16(TWI1_SLAVE_CTRL)
+#define bfin_write_TWI1_SLAVE_CTRL(val)         bfin_write16(TWI1_SLAVE_CTRL, val)
+#define bfin_read_TWI1_SLAVE_STAT()             bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val)         bfin_write16(TWI1_SLAVE_STAT, val)
+#define bfin_read_TWI1_SLAVE_ADDR()             bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val)         bfin_write16(TWI1_SLAVE_ADDR, val)
+#define bfin_read_TWI1_MASTER_CTRL()            bfin_read16(TWI1_MASTER_CTRL)
+#define bfin_write_TWI1_MASTER_CTRL(val)        bfin_write16(TWI1_MASTER_CTRL, val)
+#define bfin_read_TWI1_MASTER_STAT()            bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val)        bfin_write16(TWI1_MASTER_STAT, val)
+#define bfin_read_TWI1_MASTER_ADDR()            bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val)        bfin_write16(TWI1_MASTER_ADDR, val)
+#define bfin_read_TWI1_INT_STAT()               bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)           bfin_write16(TWI1_INT_STAT, val)
+#define bfin_read_TWI1_INT_MASK()               bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)           bfin_write16(TWI1_INT_MASK, val)
+#define bfin_read_TWI1_FIFO_CTRL()              bfin_read16(TWI1_FIFO_CTRL)
+#define bfin_write_TWI1_FIFO_CTRL(val)          bfin_write16(TWI1_FIFO_CTRL, val)
+#define bfin_read_TWI1_FIFO_STAT()              bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val)          bfin_write16(TWI1_FIFO_STAT, val)
+#define bfin_read_TWI1_XMT_DATA8()              bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val)          bfin_write16(TWI1_XMT_DATA8, val)
+#define bfin_read_TWI1_XMT_DATA16()             bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val)         bfin_write16(TWI1_XMT_DATA16, val)
+#define bfin_read_TWI1_RCV_DATA8()              bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val)          bfin_write16(TWI1_RCV_DATA8, val)
+#define bfin_read_TWI1_RCV_DATA16()             bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val)         bfin_write16(TWI1_RCV_DATA16, val)
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define bfin_read_CAN1_MC1()            bfin_read16(CAN1_MC1)
+#define bfin_write_CAN1_MC1(val)        bfin_write16(CAN1_MC1, val)
+#define bfin_read_CAN1_MD1()            bfin_read16(CAN1_MD1)
+#define bfin_write_CAN1_MD1(val)        bfin_write16(CAN1_MD1, val)
+#define bfin_read_CAN1_TRS1()           bfin_read16(CAN1_TRS1)
+#define bfin_write_CAN1_TRS1(val)       bfin_write16(CAN1_TRS1, val)
+#define bfin_read_CAN1_TRR1()           bfin_read16(CAN1_TRR1)
+#define bfin_write_CAN1_TRR1(val)       bfin_write16(CAN1_TRR1, val)
+#define bfin_read_CAN1_TA1()            bfin_read16(CAN1_TA1)
+#define bfin_write_CAN1_TA1(val)        bfin_write16(CAN1_TA1, val)
+#define bfin_read_CAN1_AA1()            bfin_read16(CAN1_AA1)
+#define bfin_write_CAN1_AA1(val)        bfin_write16(CAN1_AA1, val)
+#define bfin_read_CAN1_RMP1()           bfin_read16(CAN1_RMP1)
+#define bfin_write_CAN1_RMP1(val)       bfin_write16(CAN1_RMP1, val)
+#define bfin_read_CAN1_RML1()           bfin_read16(CAN1_RML1)
+#define bfin_write_CAN1_RML1(val)       bfin_write16(CAN1_RML1, val)
+#define bfin_read_CAN1_MBTIF1()         bfin_read16(CAN1_MBTIF1)
+#define bfin_write_CAN1_MBTIF1(val)     bfin_write16(CAN1_MBTIF1, val)
+#define bfin_read_CAN1_MBRIF1()         bfin_read16(CAN1_MBRIF1)
+#define bfin_write_CAN1_MBRIF1(val)     bfin_write16(CAN1_MBRIF1, val)
+#define bfin_read_CAN1_MBIM1()          bfin_read16(CAN1_MBIM1)
+#define bfin_write_CAN1_MBIM1(val)      bfin_write16(CAN1_MBIM1, val)
+#define bfin_read_CAN1_RFH1()           bfin_read16(CAN1_RFH1)
+#define bfin_write_CAN1_RFH1(val)       bfin_write16(CAN1_RFH1, val)
+#define bfin_read_CAN1_OPSS1()          bfin_read16(CAN1_OPSS1)
+#define bfin_write_CAN1_OPSS1(val)      bfin_write16(CAN1_OPSS1, val)
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define bfin_read_CAN1_MC2()            bfin_read16(CAN1_MC2)
+#define bfin_write_CAN1_MC2(val)        bfin_write16(CAN1_MC2, val)
+#define bfin_read_CAN1_MD2()            bfin_read16(CAN1_MD2)
+#define bfin_write_CAN1_MD2(val)        bfin_write16(CAN1_MD2, val)
+#define bfin_read_CAN1_TRS2()           bfin_read16(CAN1_TRS2)
+#define bfin_write_CAN1_TRS2(val)       bfin_write16(CAN1_TRS2, val)
+#define bfin_read_CAN1_TRR2()           bfin_read16(CAN1_TRR2)
+#define bfin_write_CAN1_TRR2(val)       bfin_write16(CAN1_TRR2, val)
+#define bfin_read_CAN1_TA2()            bfin_read16(CAN1_TA2)
+#define bfin_write_CAN1_TA2(val)        bfin_write16(CAN1_TA2, val)
+#define bfin_read_CAN1_AA2()            bfin_read16(CAN1_AA2)
+#define bfin_write_CAN1_AA2(val)        bfin_write16(CAN1_AA2, val)
+#define bfin_read_CAN1_RMP2()           bfin_read16(CAN1_RMP2)
+#define bfin_write_CAN1_RMP2(val)       bfin_write16(CAN1_RMP2, val)
+#define bfin_read_CAN1_RML2()           bfin_read16(CAN1_RML2)
+#define bfin_write_CAN1_RML2(val)       bfin_write16(CAN1_RML2, val)
+#define bfin_read_CAN1_MBTIF2()         bfin_read16(CAN1_MBTIF2)
+#define bfin_write_CAN1_MBTIF2(val)     bfin_write16(CAN1_MBTIF2, val)
+#define bfin_read_CAN1_MBRIF2()         bfin_read16(CAN1_MBRIF2)
+#define bfin_write_CAN1_MBRIF2(val)     bfin_write16(CAN1_MBRIF2, val)
+#define bfin_read_CAN1_MBIM2()          bfin_read16(CAN1_MBIM2)
+#define bfin_write_CAN1_MBIM2(val)      bfin_write16(CAN1_MBIM2, val)
+#define bfin_read_CAN1_RFH2()           bfin_read16(CAN1_RFH2)
+#define bfin_write_CAN1_RFH2(val)       bfin_write16(CAN1_RFH2, val)
+#define bfin_read_CAN1_OPSS2()          bfin_read16(CAN1_OPSS2)
+#define bfin_write_CAN1_OPSS2(val)      bfin_write16(CAN1_OPSS2, val)
+
+/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
+
+#define bfin_read_CAN1_CLOCK()          bfin_read16(CAN1_CLOCK)
+#define bfin_write_CAN1_CLOCK(val)      bfin_write16(CAN1_CLOCK, val)
+#define bfin_read_CAN1_TIMING()         bfin_read16(CAN1_TIMING)
+#define bfin_write_CAN1_TIMING(val)     bfin_write16(CAN1_TIMING, val)
+#define bfin_read_CAN1_DEBUG()          bfin_read16(CAN1_DEBUG)
+#define bfin_write_CAN1_DEBUG(val)      bfin_write16(CAN1_DEBUG, val)
+#define bfin_read_CAN1_STATUS()         bfin_read16(CAN1_STATUS)
+#define bfin_write_CAN1_STATUS(val)     bfin_write16(CAN1_STATUS, val)
+#define bfin_read_CAN1_CEC()            bfin_read16(CAN1_CEC)
+#define bfin_write_CAN1_CEC(val)        bfin_write16(CAN1_CEC, val)
+#define bfin_read_CAN1_GIS()            bfin_read16(CAN1_GIS)
+#define bfin_write_CAN1_GIS(val)        bfin_write16(CAN1_GIS, val)
+#define bfin_read_CAN1_GIM()            bfin_read16(CAN1_GIM)
+#define bfin_write_CAN1_GIM(val)        bfin_write16(CAN1_GIM, val)
+#define bfin_read_CAN1_GIF()            bfin_read16(CAN1_GIF)
+#define bfin_write_CAN1_GIF(val)        bfin_write16(CAN1_GIF, val)
+#define bfin_read_CAN1_CONTROL()        bfin_read16(CAN1_CONTROL)
+#define bfin_write_CAN1_CONTROL(val)    bfin_write16(CAN1_CONTROL, val)
+#define bfin_read_CAN1_INTR()           bfin_read16(CAN1_INTR)
+#define bfin_write_CAN1_INTR(val)       bfin_write16(CAN1_INTR, val)
+#define bfin_read_CAN1_MBTD()           bfin_read16(CAN1_MBTD)
+#define bfin_write_CAN1_MBTD(val)       bfin_write16(CAN1_MBTD, val)
+#define bfin_read_CAN1_EWR()            bfin_read16(CAN1_EWR)
+#define bfin_write_CAN1_EWR(val)        bfin_write16(CAN1_EWR, val)
+#define bfin_read_CAN1_ESR()            bfin_read16(CAN1_ESR)
+#define bfin_write_CAN1_ESR(val)        bfin_write16(CAN1_ESR, val)
+#define bfin_read_CAN1_UCCNT()          bfin_read16(CAN1_UCCNT)
+#define bfin_write_CAN1_UCCNT(val)      bfin_write16(CAN1_UCCNT, val)
+#define bfin_read_CAN1_UCRC()           bfin_read16(CAN1_UCRC)
+#define bfin_write_CAN1_UCRC(val)       bfin_write16(CAN1_UCRC, val)
+#define bfin_read_CAN1_UCCNF()          bfin_read16(CAN1_UCCNF)
+#define bfin_write_CAN1_UCCNF(val)      bfin_write16(CAN1_UCCNF, val)
+
+/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
+
+#define bfin_read_CAN1_AM00L()          bfin_read16(CAN1_AM00L)
+#define bfin_write_CAN1_AM00L(val)      bfin_write16(CAN1_AM00L, val)
+#define bfin_read_CAN1_AM00H()          bfin_read16(CAN1_AM00H)
+#define bfin_write_CAN1_AM00H(val)      bfin_write16(CAN1_AM00H, val)
+#define bfin_read_CAN1_AM01L()          bfin_read16(CAN1_AM01L)
+#define bfin_write_CAN1_AM01L(val)      bfin_write16(CAN1_AM01L, val)
+#define bfin_read_CAN1_AM01H()          bfin_read16(CAN1_AM01H)
+#define bfin_write_CAN1_AM01H(val)      bfin_write16(CAN1_AM01H, val)
+#define bfin_read_CAN1_AM02L()          bfin_read16(CAN1_AM02L)
+#define bfin_write_CAN1_AM02L(val)      bfin_write16(CAN1_AM02L, val)
+#define bfin_read_CAN1_AM02H()          bfin_read16(CAN1_AM02H)
+#define bfin_write_CAN1_AM02H(val)      bfin_write16(CAN1_AM02H, val)
+#define bfin_read_CAN1_AM03L()          bfin_read16(CAN1_AM03L)
+#define bfin_write_CAN1_AM03L(val)      bfin_write16(CAN1_AM03L, val)
+#define bfin_read_CAN1_AM03H()          bfin_read16(CAN1_AM03H)
+#define bfin_write_CAN1_AM03H(val)      bfin_write16(CAN1_AM03H, val)
+#define bfin_read_CAN1_AM04L()          bfin_read16(CAN1_AM04L)
+#define bfin_write_CAN1_AM04L(val)      bfin_write16(CAN1_AM04L, val)
+#define bfin_read_CAN1_AM04H()          bfin_read16(CAN1_AM04H)
+#define bfin_write_CAN1_AM04H(val)      bfin_write16(CAN1_AM04H, val)
+#define bfin_read_CAN1_AM05L()          bfin_read16(CAN1_AM05L)
+#define bfin_write_CAN1_AM05L(val)      bfin_write16(CAN1_AM05L, val)
+#define bfin_read_CAN1_AM05H()          bfin_read16(CAN1_AM05H)
+#define bfin_write_CAN1_AM05H(val)      bfin_write16(CAN1_AM05H, val)
+#define bfin_read_CAN1_AM06L()          bfin_read16(CAN1_AM06L)
+#define bfin_write_CAN1_AM06L(val)      bfin_write16(CAN1_AM06L, val)
+#define bfin_read_CAN1_AM06H()          bfin_read16(CAN1_AM06H)
+#define bfin_write_CAN1_AM06H(val)      bfin_write16(CAN1_AM06H, val)
+#define bfin_read_CAN1_AM07L()          bfin_read16(CAN1_AM07L)
+#define bfin_write_CAN1_AM07L(val)      bfin_write16(CAN1_AM07L, val)
+#define bfin_read_CAN1_AM07H()          bfin_read16(CAN1_AM07H)
+#define bfin_write_CAN1_AM07H(val)      bfin_write16(CAN1_AM07H, val)
+#define bfin_read_CAN1_AM08L()          bfin_read16(CAN1_AM08L)
+#define bfin_write_CAN1_AM08L(val)      bfin_write16(CAN1_AM08L, val)
+#define bfin_read_CAN1_AM08H()          bfin_read16(CAN1_AM08H)
+#define bfin_write_CAN1_AM08H(val)      bfin_write16(CAN1_AM08H, val)
+#define bfin_read_CAN1_AM09L()          bfin_read16(CAN1_AM09L)
+#define bfin_write_CAN1_AM09L(val)      bfin_write16(CAN1_AM09L, val)
+#define bfin_read_CAN1_AM09H()          bfin_read16(CAN1_AM09H)
+#define bfin_write_CAN1_AM09H(val)      bfin_write16(CAN1_AM09H, val)
+#define bfin_read_CAN1_AM10L()          bfin_read16(CAN1_AM10L)
+#define bfin_write_CAN1_AM10L(val)      bfin_write16(CAN1_AM10L, val)
+#define bfin_read_CAN1_AM10H()          bfin_read16(CAN1_AM10H)
+#define bfin_write_CAN1_AM10H(val)      bfin_write16(CAN1_AM10H, val)
+#define bfin_read_CAN1_AM11L()          bfin_read16(CAN1_AM11L)
+#define bfin_write_CAN1_AM11L(val)      bfin_write16(CAN1_AM11L, val)
+#define bfin_read_CAN1_AM11H()          bfin_read16(CAN1_AM11H)
+#define bfin_write_CAN1_AM11H(val)      bfin_write16(CAN1_AM11H, val)
+#define bfin_read_CAN1_AM12L()          bfin_read16(CAN1_AM12L)
+#define bfin_write_CAN1_AM12L(val)      bfin_write16(CAN1_AM12L, val)
+#define bfin_read_CAN1_AM12H()          bfin_read16(CAN1_AM12H)
+#define bfin_write_CAN1_AM12H(val)      bfin_write16(CAN1_AM12H, val)
+#define bfin_read_CAN1_AM13L()          bfin_read16(CAN1_AM13L)
+#define bfin_write_CAN1_AM13L(val)      bfin_write16(CAN1_AM13L, val)
+#define bfin_read_CAN1_AM13H()          bfin_read16(CAN1_AM13H)
+#define bfin_write_CAN1_AM13H(val)      bfin_write16(CAN1_AM13H, val)
+#define bfin_read_CAN1_AM14L()          bfin_read16(CAN1_AM14L)
+#define bfin_write_CAN1_AM14L(val)      bfin_write16(CAN1_AM14L, val)
+#define bfin_read_CAN1_AM14H()          bfin_read16(CAN1_AM14H)
+#define bfin_write_CAN1_AM14H(val)      bfin_write16(CAN1_AM14H, val)
+#define bfin_read_CAN1_AM15L()          bfin_read16(CAN1_AM15L)
+#define bfin_write_CAN1_AM15L(val)      bfin_write16(CAN1_AM15L, val)
+#define bfin_read_CAN1_AM15H()          bfin_read16(CAN1_AM15H)
+#define bfin_write_CAN1_AM15H(val)      bfin_write16(CAN1_AM15H, val)
+
+/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
+
+#define bfin_read_CAN1_AM16L()          bfin_read16(CAN1_AM16L)
+#define bfin_write_CAN1_AM16L(val)      bfin_write16(CAN1_AM16L, val)
+#define bfin_read_CAN1_AM16H()          bfin_read16(CAN1_AM16H)
+#define bfin_write_CAN1_AM16H(val)      bfin_write16(CAN1_AM16H, val)
+#define bfin_read_CAN1_AM17L()          bfin_read16(CAN1_AM17L)
+#define bfin_write_CAN1_AM17L(val)      bfin_write16(CAN1_AM17L, val)
+#define bfin_read_CAN1_AM17H()          bfin_read16(CAN1_AM17H)
+#define bfin_write_CAN1_AM17H(val)      bfin_write16(CAN1_AM17H, val)
+#define bfin_read_CAN1_AM18L()          bfin_read16(CAN1_AM18L)
+#define bfin_write_CAN1_AM18L(val)      bfin_write16(CAN1_AM18L, val)
+#define bfin_read_CAN1_AM18H()          bfin_read16(CAN1_AM18H)
+#define bfin_write_CAN1_AM18H(val)      bfin_write16(CAN1_AM18H, val)
+#define bfin_read_CAN1_AM19L()          bfin_read16(CAN1_AM19L)
+#define bfin_write_CAN1_AM19L(val)      bfin_write16(CAN1_AM19L, val)
+#define bfin_read_CAN1_AM19H()          bfin_read16(CAN1_AM19H)
+#define bfin_write_CAN1_AM19H(val)      bfin_write16(CAN1_AM19H, val)
+#define bfin_read_CAN1_AM20L()          bfin_read16(CAN1_AM20L)
+#define bfin_write_CAN1_AM20L(val)      bfin_write16(CAN1_AM20L, val)
+#define bfin_read_CAN1_AM20H()          bfin_read16(CAN1_AM20H)
+#define bfin_write_CAN1_AM20H(val)      bfin_write16(CAN1_AM20H, val)
+#define bfin_read_CAN1_AM21L()          bfin_read16(CAN1_AM21L)
+#define bfin_write_CAN1_AM21L(val)      bfin_write16(CAN1_AM21L, val)
+#define bfin_read_CAN1_AM21H()          bfin_read16(CAN1_AM21H)
+#define bfin_write_CAN1_AM21H(val)      bfin_write16(CAN1_AM21H, val)
+#define bfin_read_CAN1_AM22L()          bfin_read16(CAN1_AM22L)
+#define bfin_write_CAN1_AM22L(val)      bfin_write16(CAN1_AM22L, val)
+#define bfin_read_CAN1_AM22H()          bfin_read16(CAN1_AM22H)
+#define bfin_write_CAN1_AM22H(val)      bfin_write16(CAN1_AM22H, val)
+#define bfin_read_CAN1_AM23L()          bfin_read16(CAN1_AM23L)
+#define bfin_write_CAN1_AM23L(val)      bfin_write16(CAN1_AM23L, val)
+#define bfin_read_CAN1_AM23H()          bfin_read16(CAN1_AM23H)
+#define bfin_write_CAN1_AM23H(val)      bfin_write16(CAN1_AM23H, val)
+#define bfin_read_CAN1_AM24L()          bfin_read16(CAN1_AM24L)
+#define bfin_write_CAN1_AM24L(val)      bfin_write16(CAN1_AM24L, val)
+#define bfin_read_CAN1_AM24H()          bfin_read16(CAN1_AM24H)
+#define bfin_write_CAN1_AM24H(val)      bfin_write16(CAN1_AM24H, val)
+#define bfin_read_CAN1_AM25L()          bfin_read16(CAN1_AM25L)
+#define bfin_write_CAN1_AM25L(val)      bfin_write16(CAN1_AM25L, val)
+#define bfin_read_CAN1_AM25H()          bfin_read16(CAN1_AM25H)
+#define bfin_write_CAN1_AM25H(val)      bfin_write16(CAN1_AM25H, val)
+#define bfin_read_CAN1_AM26L()          bfin_read16(CAN1_AM26L)
+#define bfin_write_CAN1_AM26L(val)      bfin_write16(CAN1_AM26L, val)
+#define bfin_read_CAN1_AM26H()          bfin_read16(CAN1_AM26H)
+#define bfin_write_CAN1_AM26H(val)      bfin_write16(CAN1_AM26H, val)
+#define bfin_read_CAN1_AM27L()          bfin_read16(CAN1_AM27L)
+#define bfin_write_CAN1_AM27L(val)      bfin_write16(CAN1_AM27L, val)
+#define bfin_read_CAN1_AM27H()          bfin_read16(CAN1_AM27H)
+#define bfin_write_CAN1_AM27H(val)      bfin_write16(CAN1_AM27H, val)
+#define bfin_read_CAN1_AM28L()          bfin_read16(CAN1_AM28L)
+#define bfin_write_CAN1_AM28L(val)      bfin_write16(CAN1_AM28L, val)
+#define bfin_read_CAN1_AM28H()          bfin_read16(CAN1_AM28H)
+#define bfin_write_CAN1_AM28H(val)      bfin_write16(CAN1_AM28H, val)
+#define bfin_read_CAN1_AM29L()          bfin_read16(CAN1_AM29L)
+#define bfin_write_CAN1_AM29L(val)      bfin_write16(CAN1_AM29L, val)
+#define bfin_read_CAN1_AM29H()          bfin_read16(CAN1_AM29H)
+#define bfin_write_CAN1_AM29H(val)      bfin_write16(CAN1_AM29H, val)
+#define bfin_read_CAN1_AM30L()          bfin_read16(CAN1_AM30L)
+#define bfin_write_CAN1_AM30L(val)      bfin_write16(CAN1_AM30L, val)
+#define bfin_read_CAN1_AM30H()          bfin_read16(CAN1_AM30H)
+#define bfin_write_CAN1_AM30H(val)      bfin_write16(CAN1_AM30H, val)
+#define bfin_read_CAN1_AM31L()          bfin_read16(CAN1_AM31L)
+#define bfin_write_CAN1_AM31L(val)      bfin_write16(CAN1_AM31L, val)
+#define bfin_read_CAN1_AM31H()          bfin_read16(CAN1_AM31H)
+#define bfin_write_CAN1_AM31H(val)      bfin_write16(CAN1_AM31H, val)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define bfin_read_CAN1_MB00_DATA0()             bfin_read16(CAN1_MB00_DATA0)
+#define bfin_write_CAN1_MB00_DATA0(val)         bfin_write16(CAN1_MB00_DATA0, val)
+#define bfin_read_CAN1_MB00_DATA1()             bfin_read16(CAN1_MB00_DATA1)
+#define bfin_write_CAN1_MB00_DATA1(val)         bfin_write16(CAN1_MB00_DATA1, val)
+#define bfin_read_CAN1_MB00_DATA2()             bfin_read16(CAN1_MB00_DATA2)
+#define bfin_write_CAN1_MB00_DATA2(val)         bfin_write16(CAN1_MB00_DATA2, val)
+#define bfin_read_CAN1_MB00_DATA3()             bfin_read16(CAN1_MB00_DATA3)
+#define bfin_write_CAN1_MB00_DATA3(val)         bfin_write16(CAN1_MB00_DATA3, val)
+#define bfin_read_CAN1_MB00_LENGTH()            bfin_read16(CAN1_MB00_LENGTH)
+#define bfin_write_CAN1_MB00_LENGTH(val)        bfin_write16(CAN1_MB00_LENGTH, val)
+#define bfin_read_CAN1_MB00_TIMESTAMP()         bfin_read16(CAN1_MB00_TIMESTAMP)
+#define bfin_write_CAN1_MB00_TIMESTAMP(val)     bfin_write16(CAN1_MB00_TIMESTAMP, val)
+#define bfin_read_CAN1_MB00_ID0()               bfin_read16(CAN1_MB00_ID0)
+#define bfin_write_CAN1_MB00_ID0(val)           bfin_write16(CAN1_MB00_ID0, val)
+#define bfin_read_CAN1_MB00_ID1()               bfin_read16(CAN1_MB00_ID1)
+#define bfin_write_CAN1_MB00_ID1(val)           bfin_write16(CAN1_MB00_ID1, val)
+#define bfin_read_CAN1_MB01_DATA0()             bfin_read16(CAN1_MB01_DATA0)
+#define bfin_write_CAN1_MB01_DATA0(val)         bfin_write16(CAN1_MB01_DATA0, val)
+#define bfin_read_CAN1_MB01_DATA1()             bfin_read16(CAN1_MB01_DATA1)
+#define bfin_write_CAN1_MB01_DATA1(val)         bfin_write16(CAN1_MB01_DATA1, val)
+#define bfin_read_CAN1_MB01_DATA2()             bfin_read16(CAN1_MB01_DATA2)
+#define bfin_write_CAN1_MB01_DATA2(val)         bfin_write16(CAN1_MB01_DATA2, val)
+#define bfin_read_CAN1_MB01_DATA3()             bfin_read16(CAN1_MB01_DATA3)
+#define bfin_write_CAN1_MB01_DATA3(val)         bfin_write16(CAN1_MB01_DATA3, val)
+#define bfin_read_CAN1_MB01_LENGTH()            bfin_read16(CAN1_MB01_LENGTH)
+#define bfin_write_CAN1_MB01_LENGTH(val)        bfin_write16(CAN1_MB01_LENGTH, val)
+#define bfin_read_CAN1_MB01_TIMESTAMP()         bfin_read16(CAN1_MB01_TIMESTAMP)
+#define bfin_write_CAN1_MB01_TIMESTAMP(val)     bfin_write16(CAN1_MB01_TIMESTAMP, val)
+#define bfin_read_CAN1_MB01_ID0()               bfin_read16(CAN1_MB01_ID0)
+#define bfin_write_CAN1_MB01_ID0(val)           bfin_write16(CAN1_MB01_ID0, val)
+#define bfin_read_CAN1_MB01_ID1()               bfin_read16(CAN1_MB01_ID1)
+#define bfin_write_CAN1_MB01_ID1(val)           bfin_write16(CAN1_MB01_ID1, val)
+#define bfin_read_CAN1_MB02_DATA0()             bfin_read16(CAN1_MB02_DATA0)
+#define bfin_write_CAN1_MB02_DATA0(val)         bfin_write16(CAN1_MB02_DATA0, val)
+#define bfin_read_CAN1_MB02_DATA1()             bfin_read16(CAN1_MB02_DATA1)
+#define bfin_write_CAN1_MB02_DATA1(val)         bfin_write16(CAN1_MB02_DATA1, val)
+#define bfin_read_CAN1_MB02_DATA2()             bfin_read16(CAN1_MB02_DATA2)
+#define bfin_write_CAN1_MB02_DATA2(val)         bfin_write16(CAN1_MB02_DATA2, val)
+#define bfin_read_CAN1_MB02_DATA3()             bfin_read16(CAN1_MB02_DATA3)
+#define bfin_write_CAN1_MB02_DATA3(val)         bfin_write16(CAN1_MB02_DATA3, val)
+#define bfin_read_CAN1_MB02_LENGTH()            bfin_read16(CAN1_MB02_LENGTH)
+#define bfin_write_CAN1_MB02_LENGTH(val)        bfin_write16(CAN1_MB02_LENGTH, val)
+#define bfin_read_CAN1_MB02_TIMESTAMP()         bfin_read16(CAN1_MB02_TIMESTAMP)
+#define bfin_write_CAN1_MB02_TIMESTAMP(val)     bfin_write16(CAN1_MB02_TIMESTAMP, val)
+#define bfin_read_CAN1_MB02_ID0()               bfin_read16(CAN1_MB02_ID0)
+#define bfin_write_CAN1_MB02_ID0(val)           bfin_write16(CAN1_MB02_ID0, val)
+#define bfin_read_CAN1_MB02_ID1()               bfin_read16(CAN1_MB02_ID1)
+#define bfin_write_CAN1_MB02_ID1(val)           bfin_write16(CAN1_MB02_ID1, val)
+#define bfin_read_CAN1_MB03_DATA0()             bfin_read16(CAN1_MB03_DATA0)
+#define bfin_write_CAN1_MB03_DATA0(val)         bfin_write16(CAN1_MB03_DATA0, val)
+#define bfin_read_CAN1_MB03_DATA1()             bfin_read16(CAN1_MB03_DATA1)
+#define bfin_write_CAN1_MB03_DATA1(val)         bfin_write16(CAN1_MB03_DATA1, val)
+#define bfin_read_CAN1_MB03_DATA2()             bfin_read16(CAN1_MB03_DATA2)
+#define bfin_write_CAN1_MB03_DATA2(val)         bfin_write16(CAN1_MB03_DATA2, val)
+#define bfin_read_CAN1_MB03_DATA3()             bfin_read16(CAN1_MB03_DATA3)
+#define bfin_write_CAN1_MB03_DATA3(val)         bfin_write16(CAN1_MB03_DATA3, val)
+#define bfin_read_CAN1_MB03_LENGTH()            bfin_read16(CAN1_MB03_LENGTH)
+#define bfin_write_CAN1_MB03_LENGTH(val)        bfin_write16(CAN1_MB03_LENGTH, val)
+#define bfin_read_CAN1_MB03_TIMESTAMP()         bfin_read16(CAN1_MB03_TIMESTAMP)
+#define bfin_write_CAN1_MB03_TIMESTAMP(val)     bfin_write16(CAN1_MB03_TIMESTAMP, val)
+#define bfin_read_CAN1_MB03_ID0()               bfin_read16(CAN1_MB03_ID0)
+#define bfin_write_CAN1_MB03_ID0(val)           bfin_write16(CAN1_MB03_ID0, val)
+#define bfin_read_CAN1_MB03_ID1()               bfin_read16(CAN1_MB03_ID1)
+#define bfin_write_CAN1_MB03_ID1(val)           bfin_write16(CAN1_MB03_ID1, val)
+#define bfin_read_CAN1_MB04_DATA0()             bfin_read16(CAN1_MB04_DATA0)
+#define bfin_write_CAN1_MB04_DATA0(val)         bfin_write16(CAN1_MB04_DATA0, val)
+#define bfin_read_CAN1_MB04_DATA1()             bfin_read16(CAN1_MB04_DATA1)
+#define bfin_write_CAN1_MB04_DATA1(val)         bfin_write16(CAN1_MB04_DATA1, val)
+#define bfin_read_CAN1_MB04_DATA2()             bfin_read16(CAN1_MB04_DATA2)
+#define bfin_write_CAN1_MB04_DATA2(val)         bfin_write16(CAN1_MB04_DATA2, val)
+#define bfin_read_CAN1_MB04_DATA3()             bfin_read16(CAN1_MB04_DATA3)
+#define bfin_write_CAN1_MB04_DATA3(val)         bfin_write16(CAN1_MB04_DATA3, val)
+#define bfin_read_CAN1_MB04_LENGTH()            bfin_read16(CAN1_MB04_LENGTH)
+#define bfin_write_CAN1_MB04_LENGTH(val)        bfin_write16(CAN1_MB04_LENGTH, val)
+#define bfin_read_CAN1_MB04_TIMESTAMP()         bfin_read16(CAN1_MB04_TIMESTAMP)
+#define bfin_write_CAN1_MB04_TIMESTAMP(val)     bfin_write16(CAN1_MB04_TIMESTAMP, val)
+#define bfin_read_CAN1_MB04_ID0()               bfin_read16(CAN1_MB04_ID0)
+#define bfin_write_CAN1_MB04_ID0(val)           bfin_write16(CAN1_MB04_ID0, val)
+#define bfin_read_CAN1_MB04_ID1()               bfin_read16(CAN1_MB04_ID1)
+#define bfin_write_CAN1_MB04_ID1(val)           bfin_write16(CAN1_MB04_ID1, val)
+#define bfin_read_CAN1_MB05_DATA0()             bfin_read16(CAN1_MB05_DATA0)
+#define bfin_write_CAN1_MB05_DATA0(val)         bfin_write16(CAN1_MB05_DATA0, val)
+#define bfin_read_CAN1_MB05_DATA1()             bfin_read16(CAN1_MB05_DATA1)
+#define bfin_write_CAN1_MB05_DATA1(val)         bfin_write16(CAN1_MB05_DATA1, val)
+#define bfin_read_CAN1_MB05_DATA2()             bfin_read16(CAN1_MB05_DATA2)
+#define bfin_write_CAN1_MB05_DATA2(val)         bfin_write16(CAN1_MB05_DATA2, val)
+#define bfin_read_CAN1_MB05_DATA3()             bfin_read16(CAN1_MB05_DATA3)
+#define bfin_write_CAN1_MB05_DATA3(val)         bfin_write16(CAN1_MB05_DATA3, val)
+#define bfin_read_CAN1_MB05_LENGTH()            bfin_read16(CAN1_MB05_LENGTH)
+#define bfin_write_CAN1_MB05_LENGTH(val)        bfin_write16(CAN1_MB05_LENGTH, val)
+#define bfin_read_CAN1_MB05_TIMESTAMP()         bfin_read16(CAN1_MB05_TIMESTAMP)
+#define bfin_write_CAN1_MB05_TIMESTAMP(val)     bfin_write16(CAN1_MB05_TIMESTAMP, val)
+#define bfin_read_CAN1_MB05_ID0()               bfin_read16(CAN1_MB05_ID0)
+#define bfin_write_CAN1_MB05_ID0(val)           bfin_write16(CAN1_MB05_ID0, val)
+#define bfin_read_CAN1_MB05_ID1()               bfin_read16(CAN1_MB05_ID1)
+#define bfin_write_CAN1_MB05_ID1(val)           bfin_write16(CAN1_MB05_ID1, val)
+#define bfin_read_CAN1_MB06_DATA0()             bfin_read16(CAN1_MB06_DATA0)
+#define bfin_write_CAN1_MB06_DATA0(val)         bfin_write16(CAN1_MB06_DATA0, val)
+#define bfin_read_CAN1_MB06_DATA1()             bfin_read16(CAN1_MB06_DATA1)
+#define bfin_write_CAN1_MB06_DATA1(val)         bfin_write16(CAN1_MB06_DATA1, val)
+#define bfin_read_CAN1_MB06_DATA2()             bfin_read16(CAN1_MB06_DATA2)
+#define bfin_write_CAN1_MB06_DATA2(val)         bfin_write16(CAN1_MB06_DATA2, val)
+#define bfin_read_CAN1_MB06_DATA3()             bfin_read16(CAN1_MB06_DATA3)
+#define bfin_write_CAN1_MB06_DATA3(val)         bfin_write16(CAN1_MB06_DATA3, val)
+#define bfin_read_CAN1_MB06_LENGTH()            bfin_read16(CAN1_MB06_LENGTH)
+#define bfin_write_CAN1_MB06_LENGTH(val)        bfin_write16(CAN1_MB06_LENGTH, val)
+#define bfin_read_CAN1_MB06_TIMESTAMP()         bfin_read16(CAN1_MB06_TIMESTAMP)
+#define bfin_write_CAN1_MB06_TIMESTAMP(val)     bfin_write16(CAN1_MB06_TIMESTAMP, val)
+#define bfin_read_CAN1_MB06_ID0()               bfin_read16(CAN1_MB06_ID0)
+#define bfin_write_CAN1_MB06_ID0(val)           bfin_write16(CAN1_MB06_ID0, val)
+#define bfin_read_CAN1_MB06_ID1()               bfin_read16(CAN1_MB06_ID1)
+#define bfin_write_CAN1_MB06_ID1(val)           bfin_write16(CAN1_MB06_ID1, val)
+#define bfin_read_CAN1_MB07_DATA0()             bfin_read16(CAN1_MB07_DATA0)
+#define bfin_write_CAN1_MB07_DATA0(val)         bfin_write16(CAN1_MB07_DATA0, val)
+#define bfin_read_CAN1_MB07_DATA1()             bfin_read16(CAN1_MB07_DATA1)
+#define bfin_write_CAN1_MB07_DATA1(val)         bfin_write16(CAN1_MB07_DATA1, val)
+#define bfin_read_CAN1_MB07_DATA2()             bfin_read16(CAN1_MB07_DATA2)
+#define bfin_write_CAN1_MB07_DATA2(val)         bfin_write16(CAN1_MB07_DATA2, val)
+#define bfin_read_CAN1_MB07_DATA3()             bfin_read16(CAN1_MB07_DATA3)
+#define bfin_write_CAN1_MB07_DATA3(val)         bfin_write16(CAN1_MB07_DATA3, val)
+#define bfin_read_CAN1_MB07_LENGTH()            bfin_read16(CAN1_MB07_LENGTH)
+#define bfin_write_CAN1_MB07_LENGTH(val)        bfin_write16(CAN1_MB07_LENGTH, val)
+#define bfin_read_CAN1_MB07_TIMESTAMP()         bfin_read16(CAN1_MB07_TIMESTAMP)
+#define bfin_write_CAN1_MB07_TIMESTAMP(val)     bfin_write16(CAN1_MB07_TIMESTAMP, val)
+#define bfin_read_CAN1_MB07_ID0()               bfin_read16(CAN1_MB07_ID0)
+#define bfin_write_CAN1_MB07_ID0(val)           bfin_write16(CAN1_MB07_ID0, val)
+#define bfin_read_CAN1_MB07_ID1()               bfin_read16(CAN1_MB07_ID1)
+#define bfin_write_CAN1_MB07_ID1(val)           bfin_write16(CAN1_MB07_ID1, val)
+#define bfin_read_CAN1_MB08_DATA0()             bfin_read16(CAN1_MB08_DATA0)
+#define bfin_write_CAN1_MB08_DATA0(val)         bfin_write16(CAN1_MB08_DATA0, val)
+#define bfin_read_CAN1_MB08_DATA1()             bfin_read16(CAN1_MB08_DATA1)
+#define bfin_write_CAN1_MB08_DATA1(val)         bfin_write16(CAN1_MB08_DATA1, val)
+#define bfin_read_CAN1_MB08_DATA2()             bfin_read16(CAN1_MB08_DATA2)
+#define bfin_write_CAN1_MB08_DATA2(val)         bfin_write16(CAN1_MB08_DATA2, val)
+#define bfin_read_CAN1_MB08_DATA3()             bfin_read16(CAN1_MB08_DATA3)
+#define bfin_write_CAN1_MB08_DATA3(val)         bfin_write16(CAN1_MB08_DATA3, val)
+#define bfin_read_CAN1_MB08_LENGTH()            bfin_read16(CAN1_MB08_LENGTH)
+#define bfin_write_CAN1_MB08_LENGTH(val)        bfin_write16(CAN1_MB08_LENGTH, val)
+#define bfin_read_CAN1_MB08_TIMESTAMP()         bfin_read16(CAN1_MB08_TIMESTAMP)
+#define bfin_write_CAN1_MB08_TIMESTAMP(val)     bfin_write16(CAN1_MB08_TIMESTAMP, val)
+#define bfin_read_CAN1_MB08_ID0()               bfin_read16(CAN1_MB08_ID0)
+#define bfin_write_CAN1_MB08_ID0(val)           bfin_write16(CAN1_MB08_ID0, val)
+#define bfin_read_CAN1_MB08_ID1()               bfin_read16(CAN1_MB08_ID1)
+#define bfin_write_CAN1_MB08_ID1(val)           bfin_write16(CAN1_MB08_ID1, val)
+#define bfin_read_CAN1_MB09_DATA0()             bfin_read16(CAN1_MB09_DATA0)
+#define bfin_write_CAN1_MB09_DATA0(val)         bfin_write16(CAN1_MB09_DATA0, val)
+#define bfin_read_CAN1_MB09_DATA1()             bfin_read16(CAN1_MB09_DATA1)
+#define bfin_write_CAN1_MB09_DATA1(val)         bfin_write16(CAN1_MB09_DATA1, val)
+#define bfin_read_CAN1_MB09_DATA2()             bfin_read16(CAN1_MB09_DATA2)
+#define bfin_write_CAN1_MB09_DATA2(val)         bfin_write16(CAN1_MB09_DATA2, val)
+#define bfin_read_CAN1_MB09_DATA3()             bfin_read16(CAN1_MB09_DATA3)
+#define bfin_write_CAN1_MB09_DATA3(val)         bfin_write16(CAN1_MB09_DATA3, val)
+#define bfin_read_CAN1_MB09_LENGTH()            bfin_read16(CAN1_MB09_LENGTH)
+#define bfin_write_CAN1_MB09_LENGTH(val)        bfin_write16(CAN1_MB09_LENGTH, val)
+#define bfin_read_CAN1_MB09_TIMESTAMP()         bfin_read16(CAN1_MB09_TIMESTAMP)
+#define bfin_write_CAN1_MB09_TIMESTAMP(val)     bfin_write16(CAN1_MB09_TIMESTAMP, val)
+#define bfin_read_CAN1_MB09_ID0()               bfin_read16(CAN1_MB09_ID0)
+#define bfin_write_CAN1_MB09_ID0(val)           bfin_write16(CAN1_MB09_ID0, val)
+#define bfin_read_CAN1_MB09_ID1()               bfin_read16(CAN1_MB09_ID1)
+#define bfin_write_CAN1_MB09_ID1(val)           bfin_write16(CAN1_MB09_ID1, val)
+#define bfin_read_CAN1_MB10_DATA0()             bfin_read16(CAN1_MB10_DATA0)
+#define bfin_write_CAN1_MB10_DATA0(val)         bfin_write16(CAN1_MB10_DATA0, val)
+#define bfin_read_CAN1_MB10_DATA1()             bfin_read16(CAN1_MB10_DATA1)
+#define bfin_write_CAN1_MB10_DATA1(val)         bfin_write16(CAN1_MB10_DATA1, val)
+#define bfin_read_CAN1_MB10_DATA2()             bfin_read16(CAN1_MB10_DATA2)
+#define bfin_write_CAN1_MB10_DATA2(val)         bfin_write16(CAN1_MB10_DATA2, val)
+#define bfin_read_CAN1_MB10_DATA3()             bfin_read16(CAN1_MB10_DATA3)
+#define bfin_write_CAN1_MB10_DATA3(val)         bfin_write16(CAN1_MB10_DATA3, val)
+#define bfin_read_CAN1_MB10_LENGTH()            bfin_read16(CAN1_MB10_LENGTH)
+#define bfin_write_CAN1_MB10_LENGTH(val)        bfin_write16(CAN1_MB10_LENGTH, val)
+#define bfin_read_CAN1_MB10_TIMESTAMP()         bfin_read16(CAN1_MB10_TIMESTAMP)
+#define bfin_write_CAN1_MB10_TIMESTAMP(val)     bfin_write16(CAN1_MB10_TIMESTAMP, val)
+#define bfin_read_CAN1_MB10_ID0()               bfin_read16(CAN1_MB10_ID0)
+#define bfin_write_CAN1_MB10_ID0(val)           bfin_write16(CAN1_MB10_ID0, val)
+#define bfin_read_CAN1_MB10_ID1()               bfin_read16(CAN1_MB10_ID1)
+#define bfin_write_CAN1_MB10_ID1(val)           bfin_write16(CAN1_MB10_ID1, val)
+#define bfin_read_CAN1_MB11_DATA0()             bfin_read16(CAN1_MB11_DATA0)
+#define bfin_write_CAN1_MB11_DATA0(val)         bfin_write16(CAN1_MB11_DATA0, val)
+#define bfin_read_CAN1_MB11_DATA1()             bfin_read16(CAN1_MB11_DATA1)
+#define bfin_write_CAN1_MB11_DATA1(val)         bfin_write16(CAN1_MB11_DATA1, val)
+#define bfin_read_CAN1_MB11_DATA2()             bfin_read16(CAN1_MB11_DATA2)
+#define bfin_write_CAN1_MB11_DATA2(val)         bfin_write16(CAN1_MB11_DATA2, val)
+#define bfin_read_CAN1_MB11_DATA3()             bfin_read16(CAN1_MB11_DATA3)
+#define bfin_write_CAN1_MB11_DATA3(val)         bfin_write16(CAN1_MB11_DATA3, val)
+#define bfin_read_CAN1_MB11_LENGTH()            bfin_read16(CAN1_MB11_LENGTH)
+#define bfin_write_CAN1_MB11_LENGTH(val)        bfin_write16(CAN1_MB11_LENGTH, val)
+#define bfin_read_CAN1_MB11_TIMESTAMP()         bfin_read16(CAN1_MB11_TIMESTAMP)
+#define bfin_write_CAN1_MB11_TIMESTAMP(val)     bfin_write16(CAN1_MB11_TIMESTAMP, val)
+#define bfin_read_CAN1_MB11_ID0()               bfin_read16(CAN1_MB11_ID0)
+#define bfin_write_CAN1_MB11_ID0(val)           bfin_write16(CAN1_MB11_ID0, val)
+#define bfin_read_CAN1_MB11_ID1()               bfin_read16(CAN1_MB11_ID1)
+#define bfin_write_CAN1_MB11_ID1(val)           bfin_write16(CAN1_MB11_ID1, val)
+#define bfin_read_CAN1_MB12_DATA0()             bfin_read16(CAN1_MB12_DATA0)
+#define bfin_write_CAN1_MB12_DATA0(val)         bfin_write16(CAN1_MB12_DATA0, val)
+#define bfin_read_CAN1_MB12_DATA1()             bfin_read16(CAN1_MB12_DATA1)
+#define bfin_write_CAN1_MB12_DATA1(val)         bfin_write16(CAN1_MB12_DATA1, val)
+#define bfin_read_CAN1_MB12_DATA2()             bfin_read16(CAN1_MB12_DATA2)
+#define bfin_write_CAN1_MB12_DATA2(val)         bfin_write16(CAN1_MB12_DATA2, val)
+#define bfin_read_CAN1_MB12_DATA3()             bfin_read16(CAN1_MB12_DATA3)
+#define bfin_write_CAN1_MB12_DATA3(val)         bfin_write16(CAN1_MB12_DATA3, val)
+#define bfin_read_CAN1_MB12_LENGTH()            bfin_read16(CAN1_MB12_LENGTH)
+#define bfin_write_CAN1_MB12_LENGTH(val)        bfin_write16(CAN1_MB12_LENGTH, val)
+#define bfin_read_CAN1_MB12_TIMESTAMP()         bfin_read16(CAN1_MB12_TIMESTAMP)
+#define bfin_write_CAN1_MB12_TIMESTAMP(val)     bfin_write16(CAN1_MB12_TIMESTAMP, val)
+#define bfin_read_CAN1_MB12_ID0()               bfin_read16(CAN1_MB12_ID0)
+#define bfin_write_CAN1_MB12_ID0(val)           bfin_write16(CAN1_MB12_ID0, val)
+#define bfin_read_CAN1_MB12_ID1()               bfin_read16(CAN1_MB12_ID1)
+#define bfin_write_CAN1_MB12_ID1(val)           bfin_write16(CAN1_MB12_ID1, val)
+#define bfin_read_CAN1_MB13_DATA0()             bfin_read16(CAN1_MB13_DATA0)
+#define bfin_write_CAN1_MB13_DATA0(val)         bfin_write16(CAN1_MB13_DATA0, val)
+#define bfin_read_CAN1_MB13_DATA1()             bfin_read16(CAN1_MB13_DATA1)
+#define bfin_write_CAN1_MB13_DATA1(val)         bfin_write16(CAN1_MB13_DATA1, val)
+#define bfin_read_CAN1_MB13_DATA2()             bfin_read16(CAN1_MB13_DATA2)
+#define bfin_write_CAN1_MB13_DATA2(val)         bfin_write16(CAN1_MB13_DATA2, val)
+#define bfin_read_CAN1_MB13_DATA3()             bfin_read16(CAN1_MB13_DATA3)
+#define bfin_write_CAN1_MB13_DATA3(val)         bfin_write16(CAN1_MB13_DATA3, val)
+#define bfin_read_CAN1_MB13_LENGTH()            bfin_read16(CAN1_MB13_LENGTH)
+#define bfin_write_CAN1_MB13_LENGTH(val)        bfin_write16(CAN1_MB13_LENGTH, val)
+#define bfin_read_CAN1_MB13_TIMESTAMP()         bfin_read16(CAN1_MB13_TIMESTAMP)
+#define bfin_write_CAN1_MB13_TIMESTAMP(val)     bfin_write16(CAN1_MB13_TIMESTAMP, val)
+#define bfin_read_CAN1_MB13_ID0()               bfin_read16(CAN1_MB13_ID0)
+#define bfin_write_CAN1_MB13_ID0(val)           bfin_write16(CAN1_MB13_ID0, val)
+#define bfin_read_CAN1_MB13_ID1()               bfin_read16(CAN1_MB13_ID1)
+#define bfin_write_CAN1_MB13_ID1(val)           bfin_write16(CAN1_MB13_ID1, val)
+#define bfin_read_CAN1_MB14_DATA0()             bfin_read16(CAN1_MB14_DATA0)
+#define bfin_write_CAN1_MB14_DATA0(val)         bfin_write16(CAN1_MB14_DATA0, val)
+#define bfin_read_CAN1_MB14_DATA1()             bfin_read16(CAN1_MB14_DATA1)
+#define bfin_write_CAN1_MB14_DATA1(val)         bfin_write16(CAN1_MB14_DATA1, val)
+#define bfin_read_CAN1_MB14_DATA2()             bfin_read16(CAN1_MB14_DATA2)
+#define bfin_write_CAN1_MB14_DATA2(val)         bfin_write16(CAN1_MB14_DATA2, val)
+#define bfin_read_CAN1_MB14_DATA3()             bfin_read16(CAN1_MB14_DATA3)
+#define bfin_write_CAN1_MB14_DATA3(val)         bfin_write16(CAN1_MB14_DATA3, val)
+#define bfin_read_CAN1_MB14_LENGTH()            bfin_read16(CAN1_MB14_LENGTH)
+#define bfin_write_CAN1_MB14_LENGTH(val)        bfin_write16(CAN1_MB14_LENGTH, val)
+#define bfin_read_CAN1_MB14_TIMESTAMP()         bfin_read16(CAN1_MB14_TIMESTAMP)
+#define bfin_write_CAN1_MB14_TIMESTAMP(val)     bfin_write16(CAN1_MB14_TIMESTAMP, val)
+#define bfin_read_CAN1_MB14_ID0()               bfin_read16(CAN1_MB14_ID0)
+#define bfin_write_CAN1_MB14_ID0(val)           bfin_write16(CAN1_MB14_ID0, val)
+#define bfin_read_CAN1_MB14_ID1()               bfin_read16(CAN1_MB14_ID1)
+#define bfin_write_CAN1_MB14_ID1(val)           bfin_write16(CAN1_MB14_ID1, val)
+#define bfin_read_CAN1_MB15_DATA0()             bfin_read16(CAN1_MB15_DATA0)
+#define bfin_write_CAN1_MB15_DATA0(val)         bfin_write16(CAN1_MB15_DATA0, val)
+#define bfin_read_CAN1_MB15_DATA1()             bfin_read16(CAN1_MB15_DATA1)
+#define bfin_write_CAN1_MB15_DATA1(val)         bfin_write16(CAN1_MB15_DATA1, val)
+#define bfin_read_CAN1_MB15_DATA2()             bfin_read16(CAN1_MB15_DATA2)
+#define bfin_write_CAN1_MB15_DATA2(val)         bfin_write16(CAN1_MB15_DATA2, val)
+#define bfin_read_CAN1_MB15_DATA3()             bfin_read16(CAN1_MB15_DATA3)
+#define bfin_write_CAN1_MB15_DATA3(val)         bfin_write16(CAN1_MB15_DATA3, val)
+#define bfin_read_CAN1_MB15_LENGTH()            bfin_read16(CAN1_MB15_LENGTH)
+#define bfin_write_CAN1_MB15_LENGTH(val)        bfin_write16(CAN1_MB15_LENGTH, val)
+#define bfin_read_CAN1_MB15_TIMESTAMP()         bfin_read16(CAN1_MB15_TIMESTAMP)
+#define bfin_write_CAN1_MB15_TIMESTAMP(val)     bfin_write16(CAN1_MB15_TIMESTAMP, val)
+#define bfin_read_CAN1_MB15_ID0()               bfin_read16(CAN1_MB15_ID0)
+#define bfin_write_CAN1_MB15_ID0(val)           bfin_write16(CAN1_MB15_ID0, val)
+#define bfin_read_CAN1_MB15_ID1()               bfin_read16(CAN1_MB15_ID1)
+#define bfin_write_CAN1_MB15_ID1(val)           bfin_write16(CAN1_MB15_ID1, val)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define bfin_read_CAN1_MB16_DATA0()             bfin_read16(CAN1_MB16_DATA0)
+#define bfin_write_CAN1_MB16_DATA0(val)         bfin_write16(CAN1_MB16_DATA0, val)
+#define bfin_read_CAN1_MB16_DATA1()             bfin_read16(CAN1_MB16_DATA1)
+#define bfin_write_CAN1_MB16_DATA1(val)         bfin_write16(CAN1_MB16_DATA1, val)
+#define bfin_read_CAN1_MB16_DATA2()             bfin_read16(CAN1_MB16_DATA2)
+#define bfin_write_CAN1_MB16_DATA2(val)         bfin_write16(CAN1_MB16_DATA2, val)
+#define bfin_read_CAN1_MB16_DATA3()             bfin_read16(CAN1_MB16_DATA3)
+#define bfin_write_CAN1_MB16_DATA3(val)         bfin_write16(CAN1_MB16_DATA3, val)
+#define bfin_read_CAN1_MB16_LENGTH()            bfin_read16(CAN1_MB16_LENGTH)
+#define bfin_write_CAN1_MB16_LENGTH(val)        bfin_write16(CAN1_MB16_LENGTH, val)
+#define bfin_read_CAN1_MB16_TIMESTAMP()         bfin_read16(CAN1_MB16_TIMESTAMP)
+#define bfin_write_CAN1_MB16_TIMESTAMP(val)     bfin_write16(CAN1_MB16_TIMESTAMP, val)
+#define bfin_read_CAN1_MB16_ID0()               bfin_read16(CAN1_MB16_ID0)
+#define bfin_write_CAN1_MB16_ID0(val)           bfin_write16(CAN1_MB16_ID0, val)
+#define bfin_read_CAN1_MB16_ID1()               bfin_read16(CAN1_MB16_ID1)
+#define bfin_write_CAN1_MB16_ID1(val)           bfin_write16(CAN1_MB16_ID1, val)
+#define bfin_read_CAN1_MB17_DATA0()             bfin_read16(CAN1_MB17_DATA0)
+#define bfin_write_CAN1_MB17_DATA0(val)         bfin_write16(CAN1_MB17_DATA0, val)
+#define bfin_read_CAN1_MB17_DATA1()             bfin_read16(CAN1_MB17_DATA1)
+#define bfin_write_CAN1_MB17_DATA1(val)         bfin_write16(CAN1_MB17_DATA1, val)
+#define bfin_read_CAN1_MB17_DATA2()             bfin_read16(CAN1_MB17_DATA2)
+#define bfin_write_CAN1_MB17_DATA2(val)         bfin_write16(CAN1_MB17_DATA2, val)
+#define bfin_read_CAN1_MB17_DATA3()             bfin_read16(CAN1_MB17_DATA3)
+#define bfin_write_CAN1_MB17_DATA3(val)         bfin_write16(CAN1_MB17_DATA3, val)
+#define bfin_read_CAN1_MB17_LENGTH()            bfin_read16(CAN1_MB17_LENGTH)
+#define bfin_write_CAN1_MB17_LENGTH(val)        bfin_write16(CAN1_MB17_LENGTH, val)
+#define bfin_read_CAN1_MB17_TIMESTAMP()         bfin_read16(CAN1_MB17_TIMESTAMP)
+#define bfin_write_CAN1_MB17_TIMESTAMP(val)     bfin_write16(CAN1_MB17_TIMESTAMP, val)
+#define bfin_read_CAN1_MB17_ID0()               bfin_read16(CAN1_MB17_ID0)
+#define bfin_write_CAN1_MB17_ID0(val)           bfin_write16(CAN1_MB17_ID0, val)
+#define bfin_read_CAN1_MB17_ID1()               bfin_read16(CAN1_MB17_ID1)
+#define bfin_write_CAN1_MB17_ID1(val)           bfin_write16(CAN1_MB17_ID1, val)
+#define bfin_read_CAN1_MB18_DATA0()             bfin_read16(CAN1_MB18_DATA0)
+#define bfin_write_CAN1_MB18_DATA0(val)         bfin_write16(CAN1_MB18_DATA0, val)
+#define bfin_read_CAN1_MB18_DATA1()             bfin_read16(CAN1_MB18_DATA1)
+#define bfin_write_CAN1_MB18_DATA1(val)         bfin_write16(CAN1_MB18_DATA1, val)
+#define bfin_read_CAN1_MB18_DATA2()             bfin_read16(CAN1_MB18_DATA2)
+#define bfin_write_CAN1_MB18_DATA2(val)         bfin_write16(CAN1_MB18_DATA2, val)
+#define bfin_read_CAN1_MB18_DATA3()             bfin_read16(CAN1_MB18_DATA3)
+#define bfin_write_CAN1_MB18_DATA3(val)         bfin_write16(CAN1_MB18_DATA3, val)
+#define bfin_read_CAN1_MB18_LENGTH()            bfin_read16(CAN1_MB18_LENGTH)
+#define bfin_write_CAN1_MB18_LENGTH(val)        bfin_write16(CAN1_MB18_LENGTH, val)
+#define bfin_read_CAN1_MB18_TIMESTAMP()         bfin_read16(CAN1_MB18_TIMESTAMP)
+#define bfin_write_CAN1_MB18_TIMESTAMP(val)     bfin_write16(CAN1_MB18_TIMESTAMP, val)
+#define bfin_read_CAN1_MB18_ID0()               bfin_read16(CAN1_MB18_ID0)
+#define bfin_write_CAN1_MB18_ID0(val)           bfin_write16(CAN1_MB18_ID0, val)
+#define bfin_read_CAN1_MB18_ID1()               bfin_read16(CAN1_MB18_ID1)
+#define bfin_write_CAN1_MB18_ID1(val)           bfin_write16(CAN1_MB18_ID1, val)
+#define bfin_read_CAN1_MB19_DATA0()             bfin_read16(CAN1_MB19_DATA0)
+#define bfin_write_CAN1_MB19_DATA0(val)         bfin_write16(CAN1_MB19_DATA0, val)
+#define bfin_read_CAN1_MB19_DATA1()             bfin_read16(CAN1_MB19_DATA1)
+#define bfin_write_CAN1_MB19_DATA1(val)         bfin_write16(CAN1_MB19_DATA1, val)
+#define bfin_read_CAN1_MB19_DATA2()             bfin_read16(CAN1_MB19_DATA2)
+#define bfin_write_CAN1_MB19_DATA2(val)         bfin_write16(CAN1_MB19_DATA2, val)
+#define bfin_read_CAN1_MB19_DATA3()             bfin_read16(CAN1_MB19_DATA3)
+#define bfin_write_CAN1_MB19_DATA3(val)         bfin_write16(CAN1_MB19_DATA3, val)
+#define bfin_read_CAN1_MB19_LENGTH()            bfin_read16(CAN1_MB19_LENGTH)
+#define bfin_write_CAN1_MB19_LENGTH(val)        bfin_write16(CAN1_MB19_LENGTH, val)
+#define bfin_read_CAN1_MB19_TIMESTAMP()         bfin_read16(CAN1_MB19_TIMESTAMP)
+#define bfin_write_CAN1_MB19_TIMESTAMP(val)     bfin_write16(CAN1_MB19_TIMESTAMP, val)
+#define bfin_read_CAN1_MB19_ID0()               bfin_read16(CAN1_MB19_ID0)
+#define bfin_write_CAN1_MB19_ID0(val)           bfin_write16(CAN1_MB19_ID0, val)
+#define bfin_read_CAN1_MB19_ID1()               bfin_read16(CAN1_MB19_ID1)
+#define bfin_write_CAN1_MB19_ID1(val)           bfin_write16(CAN1_MB19_ID1, val)
+#define bfin_read_CAN1_MB20_DATA0()             bfin_read16(CAN1_MB20_DATA0)
+#define bfin_write_CAN1_MB20_DATA0(val)         bfin_write16(CAN1_MB20_DATA0, val)
+#define bfin_read_CAN1_MB20_DATA1()             bfin_read16(CAN1_MB20_DATA1)
+#define bfin_write_CAN1_MB20_DATA1(val)         bfin_write16(CAN1_MB20_DATA1, val)
+#define bfin_read_CAN1_MB20_DATA2()             bfin_read16(CAN1_MB20_DATA2)
+#define bfin_write_CAN1_MB20_DATA2(val)         bfin_write16(CAN1_MB20_DATA2, val)
+#define bfin_read_CAN1_MB20_DATA3()             bfin_read16(CAN1_MB20_DATA3)
+#define bfin_write_CAN1_MB20_DATA3(val)         bfin_write16(CAN1_MB20_DATA3, val)
+#define bfin_read_CAN1_MB20_LENGTH()            bfin_read16(CAN1_MB20_LENGTH)
+#define bfin_write_CAN1_MB20_LENGTH(val)        bfin_write16(CAN1_MB20_LENGTH, val)
+#define bfin_read_CAN1_MB20_TIMESTAMP()         bfin_read16(CAN1_MB20_TIMESTAMP)
+#define bfin_write_CAN1_MB20_TIMESTAMP(val)     bfin_write16(CAN1_MB20_TIMESTAMP, val)
+#define bfin_read_CAN1_MB20_ID0()               bfin_read16(CAN1_MB20_ID0)
+#define bfin_write_CAN1_MB20_ID0(val)           bfin_write16(CAN1_MB20_ID0, val)
+#define bfin_read_CAN1_MB20_ID1()               bfin_read16(CAN1_MB20_ID1)
+#define bfin_write_CAN1_MB20_ID1(val)           bfin_write16(CAN1_MB20_ID1, val)
+#define bfin_read_CAN1_MB21_DATA0()             bfin_read16(CAN1_MB21_DATA0)
+#define bfin_write_CAN1_MB21_DATA0(val)         bfin_write16(CAN1_MB21_DATA0, val)
+#define bfin_read_CAN1_MB21_DATA1()             bfin_read16(CAN1_MB21_DATA1)
+#define bfin_write_CAN1_MB21_DATA1(val)         bfin_write16(CAN1_MB21_DATA1, val)
+#define bfin_read_CAN1_MB21_DATA2()             bfin_read16(CAN1_MB21_DATA2)
+#define bfin_write_CAN1_MB21_DATA2(val)         bfin_write16(CAN1_MB21_DATA2, val)
+#define bfin_read_CAN1_MB21_DATA3()             bfin_read16(CAN1_MB21_DATA3)
+#define bfin_write_CAN1_MB21_DATA3(val)         bfin_write16(CAN1_MB21_DATA3, val)
+#define bfin_read_CAN1_MB21_LENGTH()            bfin_read16(CAN1_MB21_LENGTH)
+#define bfin_write_CAN1_MB21_LENGTH(val)        bfin_write16(CAN1_MB21_LENGTH, val)
+#define bfin_read_CAN1_MB21_TIMESTAMP()         bfin_read16(CAN1_MB21_TIMESTAMP)
+#define bfin_write_CAN1_MB21_TIMESTAMP(val)     bfin_write16(CAN1_MB21_TIMESTAMP, val)
+#define bfin_read_CAN1_MB21_ID0()               bfin_read16(CAN1_MB21_ID0)
+#define bfin_write_CAN1_MB21_ID0(val)           bfin_write16(CAN1_MB21_ID0, val)
+#define bfin_read_CAN1_MB21_ID1()               bfin_read16(CAN1_MB21_ID1)
+#define bfin_write_CAN1_MB21_ID1(val)           bfin_write16(CAN1_MB21_ID1, val)
+#define bfin_read_CAN1_MB22_DATA0()             bfin_read16(CAN1_MB22_DATA0)
+#define bfin_write_CAN1_MB22_DATA0(val)         bfin_write16(CAN1_MB22_DATA0, val)
+#define bfin_read_CAN1_MB22_DATA1()             bfin_read16(CAN1_MB22_DATA1)
+#define bfin_write_CAN1_MB22_DATA1(val)         bfin_write16(CAN1_MB22_DATA1, val)
+#define bfin_read_CAN1_MB22_DATA2()             bfin_read16(CAN1_MB22_DATA2)
+#define bfin_write_CAN1_MB22_DATA2(val)         bfin_write16(CAN1_MB22_DATA2, val)
+#define bfin_read_CAN1_MB22_DATA3()             bfin_read16(CAN1_MB22_DATA3)
+#define bfin_write_CAN1_MB22_DATA3(val)         bfin_write16(CAN1_MB22_DATA3, val)
+#define bfin_read_CAN1_MB22_LENGTH()            bfin_read16(CAN1_MB22_LENGTH)
+#define bfin_write_CAN1_MB22_LENGTH(val)        bfin_write16(CAN1_MB22_LENGTH, val)
+#define bfin_read_CAN1_MB22_TIMESTAMP()         bfin_read16(CAN1_MB22_TIMESTAMP)
+#define bfin_write_CAN1_MB22_TIMESTAMP(val)     bfin_write16(CAN1_MB22_TIMESTAMP, val)
+#define bfin_read_CAN1_MB22_ID0()               bfin_read16(CAN1_MB22_ID0)
+#define bfin_write_CAN1_MB22_ID0(val)           bfin_write16(CAN1_MB22_ID0, val)
+#define bfin_read_CAN1_MB22_ID1()               bfin_read16(CAN1_MB22_ID1)
+#define bfin_write_CAN1_MB22_ID1(val)           bfin_write16(CAN1_MB22_ID1, val)
+#define bfin_read_CAN1_MB23_DATA0()             bfin_read16(CAN1_MB23_DATA0)
+#define bfin_write_CAN1_MB23_DATA0(val)         bfin_write16(CAN1_MB23_DATA0, val)
+#define bfin_read_CAN1_MB23_DATA1()             bfin_read16(CAN1_MB23_DATA1)
+#define bfin_write_CAN1_MB23_DATA1(val)         bfin_write16(CAN1_MB23_DATA1, val)
+#define bfin_read_CAN1_MB23_DATA2()             bfin_read16(CAN1_MB23_DATA2)
+#define bfin_write_CAN1_MB23_DATA2(val)         bfin_write16(CAN1_MB23_DATA2, val)
+#define bfin_read_CAN1_MB23_DATA3()             bfin_read16(CAN1_MB23_DATA3)
+#define bfin_write_CAN1_MB23_DATA3(val)         bfin_write16(CAN1_MB23_DATA3, val)
+#define bfin_read_CAN1_MB23_LENGTH()            bfin_read16(CAN1_MB23_LENGTH)
+#define bfin_write_CAN1_MB23_LENGTH(val)        bfin_write16(CAN1_MB23_LENGTH, val)
+#define bfin_read_CAN1_MB23_TIMESTAMP()         bfin_read16(CAN1_MB23_TIMESTAMP)
+#define bfin_write_CAN1_MB23_TIMESTAMP(val)     bfin_write16(CAN1_MB23_TIMESTAMP, val)
+#define bfin_read_CAN1_MB23_ID0()               bfin_read16(CAN1_MB23_ID0)
+#define bfin_write_CAN1_MB23_ID0(val)           bfin_write16(CAN1_MB23_ID0, val)
+#define bfin_read_CAN1_MB23_ID1()               bfin_read16(CAN1_MB23_ID1)
+#define bfin_write_CAN1_MB23_ID1(val)           bfin_write16(CAN1_MB23_ID1, val)
+#define bfin_read_CAN1_MB24_DATA0()             bfin_read16(CAN1_MB24_DATA0)
+#define bfin_write_CAN1_MB24_DATA0(val)         bfin_write16(CAN1_MB24_DATA0, val)
+#define bfin_read_CAN1_MB24_DATA1()             bfin_read16(CAN1_MB24_DATA1)
+#define bfin_write_CAN1_MB24_DATA1(val)         bfin_write16(CAN1_MB24_DATA1, val)
+#define bfin_read_CAN1_MB24_DATA2()             bfin_read16(CAN1_MB24_DATA2)
+#define bfin_write_CAN1_MB24_DATA2(val)         bfin_write16(CAN1_MB24_DATA2, val)
+#define bfin_read_CAN1_MB24_DATA3()             bfin_read16(CAN1_MB24_DATA3)
+#define bfin_write_CAN1_MB24_DATA3(val)         bfin_write16(CAN1_MB24_DATA3, val)
+#define bfin_read_CAN1_MB24_LENGTH()            bfin_read16(CAN1_MB24_LENGTH)
+#define bfin_write_CAN1_MB24_LENGTH(val)        bfin_write16(CAN1_MB24_LENGTH, val)
+#define bfin_read_CAN1_MB24_TIMESTAMP()         bfin_read16(CAN1_MB24_TIMESTAMP)
+#define bfin_write_CAN1_MB24_TIMESTAMP(val)     bfin_write16(CAN1_MB24_TIMESTAMP, val)
+#define bfin_read_CAN1_MB24_ID0()               bfin_read16(CAN1_MB24_ID0)
+#define bfin_write_CAN1_MB24_ID0(val)           bfin_write16(CAN1_MB24_ID0, val)
+#define bfin_read_CAN1_MB24_ID1()               bfin_read16(CAN1_MB24_ID1)
+#define bfin_write_CAN1_MB24_ID1(val)           bfin_write16(CAN1_MB24_ID1, val)
+#define bfin_read_CAN1_MB25_DATA0()             bfin_read16(CAN1_MB25_DATA0)
+#define bfin_write_CAN1_MB25_DATA0(val)         bfin_write16(CAN1_MB25_DATA0, val)
+#define bfin_read_CAN1_MB25_DATA1()             bfin_read16(CAN1_MB25_DATA1)
+#define bfin_write_CAN1_MB25_DATA1(val)         bfin_write16(CAN1_MB25_DATA1, val)
+#define bfin_read_CAN1_MB25_DATA2()             bfin_read16(CAN1_MB25_DATA2)
+#define bfin_write_CAN1_MB25_DATA2(val)         bfin_write16(CAN1_MB25_DATA2, val)
+#define bfin_read_CAN1_MB25_DATA3()             bfin_read16(CAN1_MB25_DATA3)
+#define bfin_write_CAN1_MB25_DATA3(val)         bfin_write16(CAN1_MB25_DATA3, val)
+#define bfin_read_CAN1_MB25_LENGTH()            bfin_read16(CAN1_MB25_LENGTH)
+#define bfin_write_CAN1_MB25_LENGTH(val)        bfin_write16(CAN1_MB25_LENGTH, val)
+#define bfin_read_CAN1_MB25_TIMESTAMP()         bfin_read16(CAN1_MB25_TIMESTAMP)
+#define bfin_write_CAN1_MB25_TIMESTAMP(val)     bfin_write16(CAN1_MB25_TIMESTAMP, val)
+#define bfin_read_CAN1_MB25_ID0()               bfin_read16(CAN1_MB25_ID0)
+#define bfin_write_CAN1_MB25_ID0(val)           bfin_write16(CAN1_MB25_ID0, val)
+#define bfin_read_CAN1_MB25_ID1()               bfin_read16(CAN1_MB25_ID1)
+#define bfin_write_CAN1_MB25_ID1(val)           bfin_write16(CAN1_MB25_ID1, val)
+#define bfin_read_CAN1_MB26_DATA0()             bfin_read16(CAN1_MB26_DATA0)
+#define bfin_write_CAN1_MB26_DATA0(val)         bfin_write16(CAN1_MB26_DATA0, val)
+#define bfin_read_CAN1_MB26_DATA1()             bfin_read16(CAN1_MB26_DATA1)
+#define bfin_write_CAN1_MB26_DATA1(val)         bfin_write16(CAN1_MB26_DATA1, val)
+#define bfin_read_CAN1_MB26_DATA2()             bfin_read16(CAN1_MB26_DATA2)
+#define bfin_write_CAN1_MB26_DATA2(val)         bfin_write16(CAN1_MB26_DATA2, val)
+#define bfin_read_CAN1_MB26_DATA3()             bfin_read16(CAN1_MB26_DATA3)
+#define bfin_write_CAN1_MB26_DATA3(val)         bfin_write16(CAN1_MB26_DATA3, val)
+#define bfin_read_CAN1_MB26_LENGTH()            bfin_read16(CAN1_MB26_LENGTH)
+#define bfin_write_CAN1_MB26_LENGTH(val)        bfin_write16(CAN1_MB26_LENGTH, val)
+#define bfin_read_CAN1_MB26_TIMESTAMP()         bfin_read16(CAN1_MB26_TIMESTAMP)
+#define bfin_write_CAN1_MB26_TIMESTAMP(val)     bfin_write16(CAN1_MB26_TIMESTAMP, val)
+#define bfin_read_CAN1_MB26_ID0()               bfin_read16(CAN1_MB26_ID0)
+#define bfin_write_CAN1_MB26_ID0(val)           bfin_write16(CAN1_MB26_ID0, val)
+#define bfin_read_CAN1_MB26_ID1()               bfin_read16(CAN1_MB26_ID1)
+#define bfin_write_CAN1_MB26_ID1(val)           bfin_write16(CAN1_MB26_ID1, val)
+#define bfin_read_CAN1_MB27_DATA0()             bfin_read16(CAN1_MB27_DATA0)
+#define bfin_write_CAN1_MB27_DATA0(val)         bfin_write16(CAN1_MB27_DATA0, val)
+#define bfin_read_CAN1_MB27_DATA1()             bfin_read16(CAN1_MB27_DATA1)
+#define bfin_write_CAN1_MB27_DATA1(val)         bfin_write16(CAN1_MB27_DATA1, val)
+#define bfin_read_CAN1_MB27_DATA2()             bfin_read16(CAN1_MB27_DATA2)
+#define bfin_write_CAN1_MB27_DATA2(val)         bfin_write16(CAN1_MB27_DATA2, val)
+#define bfin_read_CAN1_MB27_DATA3()             bfin_read16(CAN1_MB27_DATA3)
+#define bfin_write_CAN1_MB27_DATA3(val)         bfin_write16(CAN1_MB27_DATA3, val)
+#define bfin_read_CAN1_MB27_LENGTH()            bfin_read16(CAN1_MB27_LENGTH)
+#define bfin_write_CAN1_MB27_LENGTH(val)        bfin_write16(CAN1_MB27_LENGTH, val)
+#define bfin_read_CAN1_MB27_TIMESTAMP()         bfin_read16(CAN1_MB27_TIMESTAMP)
+#define bfin_write_CAN1_MB27_TIMESTAMP(val)     bfin_write16(CAN1_MB27_TIMESTAMP, val)
+#define bfin_read_CAN1_MB27_ID0()               bfin_read16(CAN1_MB27_ID0)
+#define bfin_write_CAN1_MB27_ID0(val)           bfin_write16(CAN1_MB27_ID0, val)
+#define bfin_read_CAN1_MB27_ID1()               bfin_read16(CAN1_MB27_ID1)
+#define bfin_write_CAN1_MB27_ID1(val)           bfin_write16(CAN1_MB27_ID1, val)
+#define bfin_read_CAN1_MB28_DATA0()             bfin_read16(CAN1_MB28_DATA0)
+#define bfin_write_CAN1_MB28_DATA0(val)         bfin_write16(CAN1_MB28_DATA0, val)
+#define bfin_read_CAN1_MB28_DATA1()             bfin_read16(CAN1_MB28_DATA1)
+#define bfin_write_CAN1_MB28_DATA1(val)         bfin_write16(CAN1_MB28_DATA1, val)
+#define bfin_read_CAN1_MB28_DATA2()             bfin_read16(CAN1_MB28_DATA2)
+#define bfin_write_CAN1_MB28_DATA2(val)         bfin_write16(CAN1_MB28_DATA2, val)
+#define bfin_read_CAN1_MB28_DATA3()             bfin_read16(CAN1_MB28_DATA3)
+#define bfin_write_CAN1_MB28_DATA3(val)         bfin_write16(CAN1_MB28_DATA3, val)
+#define bfin_read_CAN1_MB28_LENGTH()            bfin_read16(CAN1_MB28_LENGTH)
+#define bfin_write_CAN1_MB28_LENGTH(val)        bfin_write16(CAN1_MB28_LENGTH, val)
+#define bfin_read_CAN1_MB28_TIMESTAMP()         bfin_read16(CAN1_MB28_TIMESTAMP)
+#define bfin_write_CAN1_MB28_TIMESTAMP(val)     bfin_write16(CAN1_MB28_TIMESTAMP, val)
+#define bfin_read_CAN1_MB28_ID0()               bfin_read16(CAN1_MB28_ID0)
+#define bfin_write_CAN1_MB28_ID0(val)           bfin_write16(CAN1_MB28_ID0, val)
+#define bfin_read_CAN1_MB28_ID1()               bfin_read16(CAN1_MB28_ID1)
+#define bfin_write_CAN1_MB28_ID1(val)           bfin_write16(CAN1_MB28_ID1, val)
+#define bfin_read_CAN1_MB29_DATA0()             bfin_read16(CAN1_MB29_DATA0)
+#define bfin_write_CAN1_MB29_DATA0(val)         bfin_write16(CAN1_MB29_DATA0, val)
+#define bfin_read_CAN1_MB29_DATA1()             bfin_read16(CAN1_MB29_DATA1)
+#define bfin_write_CAN1_MB29_DATA1(val)         bfin_write16(CAN1_MB29_DATA1, val)
+#define bfin_read_CAN1_MB29_DATA2()             bfin_read16(CAN1_MB29_DATA2)
+#define bfin_write_CAN1_MB29_DATA2(val)         bfin_write16(CAN1_MB29_DATA2, val)
+#define bfin_read_CAN1_MB29_DATA3()             bfin_read16(CAN1_MB29_DATA3)
+#define bfin_write_CAN1_MB29_DATA3(val)         bfin_write16(CAN1_MB29_DATA3, val)
+#define bfin_read_CAN1_MB29_LENGTH()            bfin_read16(CAN1_MB29_LENGTH)
+#define bfin_write_CAN1_MB29_LENGTH(val)        bfin_write16(CAN1_MB29_LENGTH, val)
+#define bfin_read_CAN1_MB29_TIMESTAMP()         bfin_read16(CAN1_MB29_TIMESTAMP)
+#define bfin_write_CAN1_MB29_TIMESTAMP(val)     bfin_write16(CAN1_MB29_TIMESTAMP, val)
+#define bfin_read_CAN1_MB29_ID0()               bfin_read16(CAN1_MB29_ID0)
+#define bfin_write_CAN1_MB29_ID0(val)           bfin_write16(CAN1_MB29_ID0, val)
+#define bfin_read_CAN1_MB29_ID1()               bfin_read16(CAN1_MB29_ID1)
+#define bfin_write_CAN1_MB29_ID1(val)           bfin_write16(CAN1_MB29_ID1, val)
+#define bfin_read_CAN1_MB30_DATA0()             bfin_read16(CAN1_MB30_DATA0)
+#define bfin_write_CAN1_MB30_DATA0(val)         bfin_write16(CAN1_MB30_DATA0, val)
+#define bfin_read_CAN1_MB30_DATA1()             bfin_read16(CAN1_MB30_DATA1)
+#define bfin_write_CAN1_MB30_DATA1(val)         bfin_write16(CAN1_MB30_DATA1, val)
+#define bfin_read_CAN1_MB30_DATA2()             bfin_read16(CAN1_MB30_DATA2)
+#define bfin_write_CAN1_MB30_DATA2(val)         bfin_write16(CAN1_MB30_DATA2, val)
+#define bfin_read_CAN1_MB30_DATA3()             bfin_read16(CAN1_MB30_DATA3)
+#define bfin_write_CAN1_MB30_DATA3(val)         bfin_write16(CAN1_MB30_DATA3, val)
+#define bfin_read_CAN1_MB30_LENGTH()            bfin_read16(CAN1_MB30_LENGTH)
+#define bfin_write_CAN1_MB30_LENGTH(val)        bfin_write16(CAN1_MB30_LENGTH, val)
+#define bfin_read_CAN1_MB30_TIMESTAMP()         bfin_read16(CAN1_MB30_TIMESTAMP)
+#define bfin_write_CAN1_MB30_TIMESTAMP(val)     bfin_write16(CAN1_MB30_TIMESTAMP, val)
+#define bfin_read_CAN1_MB30_ID0()               bfin_read16(CAN1_MB30_ID0)
+#define bfin_write_CAN1_MB30_ID0(val)           bfin_write16(CAN1_MB30_ID0, val)
+#define bfin_read_CAN1_MB30_ID1()               bfin_read16(CAN1_MB30_ID1)
+#define bfin_write_CAN1_MB30_ID1(val)           bfin_write16(CAN1_MB30_ID1, val)
+#define bfin_read_CAN1_MB31_DATA0()             bfin_read16(CAN1_MB31_DATA0)
+#define bfin_write_CAN1_MB31_DATA0(val)         bfin_write16(CAN1_MB31_DATA0, val)
+#define bfin_read_CAN1_MB31_DATA1()             bfin_read16(CAN1_MB31_DATA1)
+#define bfin_write_CAN1_MB31_DATA1(val)         bfin_write16(CAN1_MB31_DATA1, val)
+#define bfin_read_CAN1_MB31_DATA2()             bfin_read16(CAN1_MB31_DATA2)
+#define bfin_write_CAN1_MB31_DATA2(val)         bfin_write16(CAN1_MB31_DATA2, val)
+#define bfin_read_CAN1_MB31_DATA3()             bfin_read16(CAN1_MB31_DATA3)
+#define bfin_write_CAN1_MB31_DATA3(val)         bfin_write16(CAN1_MB31_DATA3, val)
+#define bfin_read_CAN1_MB31_LENGTH()            bfin_read16(CAN1_MB31_LENGTH)
+#define bfin_write_CAN1_MB31_LENGTH(val)        bfin_write16(CAN1_MB31_LENGTH, val)
+#define bfin_read_CAN1_MB31_TIMESTAMP()         bfin_read16(CAN1_MB31_TIMESTAMP)
+#define bfin_write_CAN1_MB31_TIMESTAMP(val)     bfin_write16(CAN1_MB31_TIMESTAMP, val)
+#define bfin_read_CAN1_MB31_ID0()               bfin_read16(CAN1_MB31_ID0)
+#define bfin_write_CAN1_MB31_ID0(val)           bfin_write16(CAN1_MB31_ID0, val)
+#define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
+#define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
+
+/* HOST Port Registers */
+
+#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
+#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
+#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
+
+/* Pixel Combfin_read_()ositor (PIXC) Registers */
+
+#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
+#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
+#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
+#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
+#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
+#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
+#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
+#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
+#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
+#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
+#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
+#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
+#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
+#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
+#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
+#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
+#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
+#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
+#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
+
+/* Handshake MDMA 0 Registers */
+
+#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
+
+/* Handshake MDMA 1 Registers */
+
+#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
+
+#endif /* _CDEF_BF544_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF548.h b/include/asm-blackfin/mach-bf548/cdefBF548.h
new file mode 100644
index 000000000000..674be0216bff
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/cdefBF548.h
@@ -0,0 +1,1610 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/cdefBF548.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF548_H
+#define _CDEF_BF548_H
+
+/* include all Core registers and bit definitions */
+#include "defBF548.h"
+
+/* include core sbfin_read_()ecific register pointer definitions */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
+
+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
+#include "cdefBF54x_base.h"
+
+/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
+
+/* Timer Registers */
+
+#define bfin_read_TIMER8_CONFIG()       bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)   bfin_write16(TIMER8_CONFIG, val)
+#define bfin_read_TIMER8_COUNTER()      bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val)  bfin_write32(TIMER8_COUNTER, val)
+#define bfin_read_TIMER8_PERIOD()       bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)   bfin_write32(TIMER8_PERIOD, val)
+#define bfin_read_TIMER8_WIDTH()        bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)    bfin_write32(TIMER8_WIDTH, val)
+#define bfin_read_TIMER9_CONFIG()       bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)   bfin_write16(TIMER9_CONFIG, val)
+#define bfin_read_TIMER9_COUNTER()      bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val)  bfin_write32(TIMER9_COUNTER, val)
+#define bfin_read_TIMER9_PERIOD()       bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)   bfin_write32(TIMER9_PERIOD, val)
+#define bfin_read_TIMER9_WIDTH()        bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)    bfin_write32(TIMER9_WIDTH, val)
+#define bfin_read_TIMER10_CONFIG()      bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val)  bfin_write16(TIMER10_CONFIG, val)
+#define bfin_read_TIMER10_COUNTER()     bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define bfin_read_TIMER10_PERIOD()      bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val)  bfin_write32(TIMER10_PERIOD, val)
+#define bfin_read_TIMER10_WIDTH()       bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)   bfin_write32(TIMER10_WIDTH, val)
+
+/* Timer Groubfin_read_() of 3 */
+
+#define bfin_read_TIMER_ENABLE1()       bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)   bfin_write16(TIMER_ENABLE1, val)
+#define bfin_read_TIMER_DISABLE1()      bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val)  bfin_write16(TIMER_DISABLE1, val)
+#define bfin_read_TIMER_STATUS1()       bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)   bfin_write32(TIMER_STATUS1, val)
+
+/* SPORT0 Registers */
+
+#define bfin_read_SPORT0_TCR1()         bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)     bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2()         bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)     bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV()      bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)  bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV()       bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)   bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX()           bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)       bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX()           bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)       bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1()         bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)     bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2()         bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)     bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV()      bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)  bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV()       bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)   bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT()         bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)     bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL()         bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)     bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1()        bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)    bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2()        bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)    bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0()        bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)    bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1()        bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)    bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2()        bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)    bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3()        bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)    bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0()        bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)    bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1()        bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)    bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2()        bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)    bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3()        bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)    bfin_write32(SPORT0_MRCS3, val)
+
+/* EPPI0 Registers */
+
+#define bfin_read_EPPI0_STATUS()        bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)    bfin_write16(EPPI0_STATUS, val)
+#define bfin_read_EPPI0_HCOUNT()        bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)    bfin_write16(EPPI0_HCOUNT, val)
+#define bfin_read_EPPI0_HDELAY()        bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)    bfin_write16(EPPI0_HDELAY, val)
+#define bfin_read_EPPI0_VCOUNT()        bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)    bfin_write16(EPPI0_VCOUNT, val)
+#define bfin_read_EPPI0_VDELAY()        bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)    bfin_write16(EPPI0_VDELAY, val)
+#define bfin_read_EPPI0_FRAME()         bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)     bfin_write16(EPPI0_FRAME, val)
+#define bfin_read_EPPI0_LINE()          bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)      bfin_write16(EPPI0_LINE, val)
+#define bfin_read_EPPI0_CLKDIV()        bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)    bfin_write16(EPPI0_CLKDIV, val)
+#define bfin_read_EPPI0_CONTROL()       bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)   bfin_write32(EPPI0_CONTROL, val)
+#define bfin_read_EPPI0_FS1W_HBL()      bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val)  bfin_write32(EPPI0_FS1W_HBL, val)
+#define bfin_read_EPPI0_FS1P_AVPL()     bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
+#define bfin_read_EPPI0_FS2W_LVB()      bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val)  bfin_write32(EPPI0_FS2W_LVB, val)
+#define bfin_read_EPPI0_FS2P_LAVF()     bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
+#define bfin_read_EPPI0_CLIP()          bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)      bfin_write32(EPPI0_CLIP, val)
+
+/* UART2 Registers */
+
+#define bfin_read_UART2_DLL()           bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val)       bfin_write16(UART2_DLL, val)
+#define bfin_read_UART2_DLH()           bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val)       bfin_write16(UART2_DLH, val)
+#define bfin_read_UART2_GCTL()          bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val)      bfin_write16(UART2_GCTL, val)
+#define bfin_read_UART2_LCR()           bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val)       bfin_write16(UART2_LCR, val)
+#define bfin_read_UART2_MCR()           bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val)       bfin_write16(UART2_MCR, val)
+#define bfin_read_UART2_LSR()           bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val)       bfin_write16(UART2_LSR, val)
+#define bfin_read_UART2_MSR()           bfin_read16(UART2_MSR)
+#define bfin_write_UART2_MSR(val)       bfin_write16(UART2_MSR, val)
+#define bfin_read_UART2_SCR()           bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val)       bfin_write16(UART2_SCR, val)
+#define bfin_read_UART2_IER_SET()       bfin_read16(UART2_IER_SET)
+#define bfin_write_UART2_IER_SET(val)   bfin_write16(UART2_IER_SET, val)
+#define bfin_read_UART2_IER_CLEAR()     bfin_read16(UART2_IER_CLEAR)
+#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
+#define bfin_read_UART2_RBR()           bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val)       bfin_write16(UART2_RBR, val)
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define bfin_read_TWI1_CLKDIV()                 bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)             bfin_write16(TWI1_CLKDIV, val)
+#define bfin_read_TWI1_CONTROL()                bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)            bfin_write16(TWI1_CONTROL, val)
+#define bfin_read_TWI1_SLAVE_CTRL()             bfin_read16(TWI1_SLAVE_CTRL)
+#define bfin_write_TWI1_SLAVE_CTRL(val)         bfin_write16(TWI1_SLAVE_CTRL, val)
+#define bfin_read_TWI1_SLAVE_STAT()             bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val)         bfin_write16(TWI1_SLAVE_STAT, val)
+#define bfin_read_TWI1_SLAVE_ADDR()             bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val)         bfin_write16(TWI1_SLAVE_ADDR, val)
+#define bfin_read_TWI1_MASTER_CTRL()            bfin_read16(TWI1_MASTER_CTRL)
+#define bfin_write_TWI1_MASTER_CTRL(val)        bfin_write16(TWI1_MASTER_CTRL, val)
+#define bfin_read_TWI1_MASTER_STAT()            bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val)        bfin_write16(TWI1_MASTER_STAT, val)
+#define bfin_read_TWI1_MASTER_ADDR()            bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val)        bfin_write16(TWI1_MASTER_ADDR, val)
+#define bfin_read_TWI1_INT_STAT()               bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)           bfin_write16(TWI1_INT_STAT, val)
+#define bfin_read_TWI1_INT_MASK()               bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)           bfin_write16(TWI1_INT_MASK, val)
+#define bfin_read_TWI1_FIFO_CTRL()              bfin_read16(TWI1_FIFO_CTRL)
+#define bfin_write_TWI1_FIFO_CTRL(val)          bfin_write16(TWI1_FIFO_CTRL, val)
+#define bfin_read_TWI1_FIFO_STAT()              bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val)          bfin_write16(TWI1_FIFO_STAT, val)
+#define bfin_read_TWI1_XMT_DATA8()              bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val)          bfin_write16(TWI1_XMT_DATA8, val)
+#define bfin_read_TWI1_XMT_DATA16()             bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val)         bfin_write16(TWI1_XMT_DATA16, val)
+#define bfin_read_TWI1_RCV_DATA8()              bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val)          bfin_write16(TWI1_RCV_DATA8, val)
+#define bfin_read_TWI1_RCV_DATA16()             bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val)         bfin_write16(TWI1_RCV_DATA16, val)
+
+/* SPI2  Registers */
+
+#define bfin_read_SPI2_CTL()            bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val)        bfin_write16(SPI2_CTL, val)
+#define bfin_read_SPI2_FLG()            bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val)        bfin_write16(SPI2_FLG, val)
+#define bfin_read_SPI2_STAT()           bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val)       bfin_write16(SPI2_STAT, val)
+#define bfin_read_SPI2_TDBR()           bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val)       bfin_write16(SPI2_TDBR, val)
+#define bfin_read_SPI2_RDBR()           bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val)       bfin_write16(SPI2_RDBR, val)
+#define bfin_read_SPI2_BAUD()           bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val)       bfin_write16(SPI2_BAUD, val)
+#define bfin_read_SPI2_SHADOW()         bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val)     bfin_write16(SPI2_SHADOW, val)
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define bfin_read_CAN1_MC1()            bfin_read16(CAN1_MC1)
+#define bfin_write_CAN1_MC1(val)        bfin_write16(CAN1_MC1, val)
+#define bfin_read_CAN1_MD1()            bfin_read16(CAN1_MD1)
+#define bfin_write_CAN1_MD1(val)        bfin_write16(CAN1_MD1, val)
+#define bfin_read_CAN1_TRS1()           bfin_read16(CAN1_TRS1)
+#define bfin_write_CAN1_TRS1(val)       bfin_write16(CAN1_TRS1, val)
+#define bfin_read_CAN1_TRR1()           bfin_read16(CAN1_TRR1)
+#define bfin_write_CAN1_TRR1(val)       bfin_write16(CAN1_TRR1, val)
+#define bfin_read_CAN1_TA1()            bfin_read16(CAN1_TA1)
+#define bfin_write_CAN1_TA1(val)        bfin_write16(CAN1_TA1, val)
+#define bfin_read_CAN1_AA1()            bfin_read16(CAN1_AA1)
+#define bfin_write_CAN1_AA1(val)        bfin_write16(CAN1_AA1, val)
+#define bfin_read_CAN1_RMP1()           bfin_read16(CAN1_RMP1)
+#define bfin_write_CAN1_RMP1(val)       bfin_write16(CAN1_RMP1, val)
+#define bfin_read_CAN1_RML1()           bfin_read16(CAN1_RML1)
+#define bfin_write_CAN1_RML1(val)       bfin_write16(CAN1_RML1, val)
+#define bfin_read_CAN1_MBTIF1()         bfin_read16(CAN1_MBTIF1)
+#define bfin_write_CAN1_MBTIF1(val)     bfin_write16(CAN1_MBTIF1, val)
+#define bfin_read_CAN1_MBRIF1()         bfin_read16(CAN1_MBRIF1)
+#define bfin_write_CAN1_MBRIF1(val)     bfin_write16(CAN1_MBRIF1, val)
+#define bfin_read_CAN1_MBIM1()          bfin_read16(CAN1_MBIM1)
+#define bfin_write_CAN1_MBIM1(val)      bfin_write16(CAN1_MBIM1, val)
+#define bfin_read_CAN1_RFH1()           bfin_read16(CAN1_RFH1)
+#define bfin_write_CAN1_RFH1(val)       bfin_write16(CAN1_RFH1, val)
+#define bfin_read_CAN1_OPSS1()          bfin_read16(CAN1_OPSS1)
+#define bfin_write_CAN1_OPSS1(val)      bfin_write16(CAN1_OPSS1, val)
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define bfin_read_CAN1_MC2()            bfin_read16(CAN1_MC2)
+#define bfin_write_CAN1_MC2(val)        bfin_write16(CAN1_MC2, val)
+#define bfin_read_CAN1_MD2()            bfin_read16(CAN1_MD2)
+#define bfin_write_CAN1_MD2(val)        bfin_write16(CAN1_MD2, val)
+#define bfin_read_CAN1_TRS2()           bfin_read16(CAN1_TRS2)
+#define bfin_write_CAN1_TRS2(val)       bfin_write16(CAN1_TRS2, val)
+#define bfin_read_CAN1_TRR2()           bfin_read16(CAN1_TRR2)
+#define bfin_write_CAN1_TRR2(val)       bfin_write16(CAN1_TRR2, val)
+#define bfin_read_CAN1_TA2()            bfin_read16(CAN1_TA2)
+#define bfin_write_CAN1_TA2(val)        bfin_write16(CAN1_TA2, val)
+#define bfin_read_CAN1_AA2()            bfin_read16(CAN1_AA2)
+#define bfin_write_CAN1_AA2(val)        bfin_write16(CAN1_AA2, val)
+#define bfin_read_CAN1_RMP2()           bfin_read16(CAN1_RMP2)
+#define bfin_write_CAN1_RMP2(val)       bfin_write16(CAN1_RMP2, val)
+#define bfin_read_CAN1_RML2()           bfin_read16(CAN1_RML2)
+#define bfin_write_CAN1_RML2(val)       bfin_write16(CAN1_RML2, val)
+#define bfin_read_CAN1_MBTIF2()         bfin_read16(CAN1_MBTIF2)
+#define bfin_write_CAN1_MBTIF2(val)     bfin_write16(CAN1_MBTIF2, val)
+#define bfin_read_CAN1_MBRIF2()         bfin_read16(CAN1_MBRIF2)
+#define bfin_write_CAN1_MBRIF2(val)     bfin_write16(CAN1_MBRIF2, val)
+#define bfin_read_CAN1_MBIM2()          bfin_read16(CAN1_MBIM2)
+#define bfin_write_CAN1_MBIM2(val)      bfin_write16(CAN1_MBIM2, val)
+#define bfin_read_CAN1_RFH2()           bfin_read16(CAN1_RFH2)
+#define bfin_write_CAN1_RFH2(val)       bfin_write16(CAN1_RFH2, val)
+#define bfin_read_CAN1_OPSS2()          bfin_read16(CAN1_OPSS2)
+#define bfin_write_CAN1_OPSS2(val)      bfin_write16(CAN1_OPSS2, val)
+
+/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
+
+#define bfin_read_CAN1_CLOCK()          bfin_read16(CAN1_CLOCK)
+#define bfin_write_CAN1_CLOCK(val)      bfin_write16(CAN1_CLOCK, val)
+#define bfin_read_CAN1_TIMING()         bfin_read16(CAN1_TIMING)
+#define bfin_write_CAN1_TIMING(val)     bfin_write16(CAN1_TIMING, val)
+#define bfin_read_CAN1_DEBUG()          bfin_read16(CAN1_DEBUG)
+#define bfin_write_CAN1_DEBUG(val)      bfin_write16(CAN1_DEBUG, val)
+#define bfin_read_CAN1_STATUS()         bfin_read16(CAN1_STATUS)
+#define bfin_write_CAN1_STATUS(val)     bfin_write16(CAN1_STATUS, val)
+#define bfin_read_CAN1_CEC()            bfin_read16(CAN1_CEC)
+#define bfin_write_CAN1_CEC(val)        bfin_write16(CAN1_CEC, val)
+#define bfin_read_CAN1_GIS()            bfin_read16(CAN1_GIS)
+#define bfin_write_CAN1_GIS(val)        bfin_write16(CAN1_GIS, val)
+#define bfin_read_CAN1_GIM()            bfin_read16(CAN1_GIM)
+#define bfin_write_CAN1_GIM(val)        bfin_write16(CAN1_GIM, val)
+#define bfin_read_CAN1_GIF()            bfin_read16(CAN1_GIF)
+#define bfin_write_CAN1_GIF(val)        bfin_write16(CAN1_GIF, val)
+#define bfin_read_CAN1_CONTROL()        bfin_read16(CAN1_CONTROL)
+#define bfin_write_CAN1_CONTROL(val)    bfin_write16(CAN1_CONTROL, val)
+#define bfin_read_CAN1_INTR()           bfin_read16(CAN1_INTR)
+#define bfin_write_CAN1_INTR(val)       bfin_write16(CAN1_INTR, val)
+#define bfin_read_CAN1_MBTD()           bfin_read16(CAN1_MBTD)
+#define bfin_write_CAN1_MBTD(val)       bfin_write16(CAN1_MBTD, val)
+#define bfin_read_CAN1_EWR()            bfin_read16(CAN1_EWR)
+#define bfin_write_CAN1_EWR(val)        bfin_write16(CAN1_EWR, val)
+#define bfin_read_CAN1_ESR()            bfin_read16(CAN1_ESR)
+#define bfin_write_CAN1_ESR(val)        bfin_write16(CAN1_ESR, val)
+#define bfin_read_CAN1_UCCNT()          bfin_read16(CAN1_UCCNT)
+#define bfin_write_CAN1_UCCNT(val)      bfin_write16(CAN1_UCCNT, val)
+#define bfin_read_CAN1_UCRC()           bfin_read16(CAN1_UCRC)
+#define bfin_write_CAN1_UCRC(val)       bfin_write16(CAN1_UCRC, val)
+#define bfin_read_CAN1_UCCNF()          bfin_read16(CAN1_UCCNF)
+#define bfin_write_CAN1_UCCNF(val)      bfin_write16(CAN1_UCCNF, val)
+
+/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
+
+#define bfin_read_CAN1_AM00L()          bfin_read16(CAN1_AM00L)
+#define bfin_write_CAN1_AM00L(val)      bfin_write16(CAN1_AM00L, val)
+#define bfin_read_CAN1_AM00H()          bfin_read16(CAN1_AM00H)
+#define bfin_write_CAN1_AM00H(val)      bfin_write16(CAN1_AM00H, val)
+#define bfin_read_CAN1_AM01L()          bfin_read16(CAN1_AM01L)
+#define bfin_write_CAN1_AM01L(val)      bfin_write16(CAN1_AM01L, val)
+#define bfin_read_CAN1_AM01H()          bfin_read16(CAN1_AM01H)
+#define bfin_write_CAN1_AM01H(val)      bfin_write16(CAN1_AM01H, val)
+#define bfin_read_CAN1_AM02L()          bfin_read16(CAN1_AM02L)
+#define bfin_write_CAN1_AM02L(val)      bfin_write16(CAN1_AM02L, val)
+#define bfin_read_CAN1_AM02H()          bfin_read16(CAN1_AM02H)
+#define bfin_write_CAN1_AM02H(val)      bfin_write16(CAN1_AM02H, val)
+#define bfin_read_CAN1_AM03L()          bfin_read16(CAN1_AM03L)
+#define bfin_write_CAN1_AM03L(val)      bfin_write16(CAN1_AM03L, val)
+#define bfin_read_CAN1_AM03H()          bfin_read16(CAN1_AM03H)
+#define bfin_write_CAN1_AM03H(val)      bfin_write16(CAN1_AM03H, val)
+#define bfin_read_CAN1_AM04L()          bfin_read16(CAN1_AM04L)
+#define bfin_write_CAN1_AM04L(val)      bfin_write16(CAN1_AM04L, val)
+#define bfin_read_CAN1_AM04H()          bfin_read16(CAN1_AM04H)
+#define bfin_write_CAN1_AM04H(val)      bfin_write16(CAN1_AM04H, val)
+#define bfin_read_CAN1_AM05L()          bfin_read16(CAN1_AM05L)
+#define bfin_write_CAN1_AM05L(val)      bfin_write16(CAN1_AM05L, val)
+#define bfin_read_CAN1_AM05H()          bfin_read16(CAN1_AM05H)
+#define bfin_write_CAN1_AM05H(val)      bfin_write16(CAN1_AM05H, val)
+#define bfin_read_CAN1_AM06L()          bfin_read16(CAN1_AM06L)
+#define bfin_write_CAN1_AM06L(val)      bfin_write16(CAN1_AM06L, val)
+#define bfin_read_CAN1_AM06H()          bfin_read16(CAN1_AM06H)
+#define bfin_write_CAN1_AM06H(val)      bfin_write16(CAN1_AM06H, val)
+#define bfin_read_CAN1_AM07L()          bfin_read16(CAN1_AM07L)
+#define bfin_write_CAN1_AM07L(val)      bfin_write16(CAN1_AM07L, val)
+#define bfin_read_CAN1_AM07H()          bfin_read16(CAN1_AM07H)
+#define bfin_write_CAN1_AM07H(val)      bfin_write16(CAN1_AM07H, val)
+#define bfin_read_CAN1_AM08L()          bfin_read16(CAN1_AM08L)
+#define bfin_write_CAN1_AM08L(val)      bfin_write16(CAN1_AM08L, val)
+#define bfin_read_CAN1_AM08H()          bfin_read16(CAN1_AM08H)
+#define bfin_write_CAN1_AM08H(val)      bfin_write16(CAN1_AM08H, val)
+#define bfin_read_CAN1_AM09L()          bfin_read16(CAN1_AM09L)
+#define bfin_write_CAN1_AM09L(val)      bfin_write16(CAN1_AM09L, val)
+#define bfin_read_CAN1_AM09H()          bfin_read16(CAN1_AM09H)
+#define bfin_write_CAN1_AM09H(val)      bfin_write16(CAN1_AM09H, val)
+#define bfin_read_CAN1_AM10L()          bfin_read16(CAN1_AM10L)
+#define bfin_write_CAN1_AM10L(val)      bfin_write16(CAN1_AM10L, val)
+#define bfin_read_CAN1_AM10H()          bfin_read16(CAN1_AM10H)
+#define bfin_write_CAN1_AM10H(val)      bfin_write16(CAN1_AM10H, val)
+#define bfin_read_CAN1_AM11L()          bfin_read16(CAN1_AM11L)
+#define bfin_write_CAN1_AM11L(val)      bfin_write16(CAN1_AM11L, val)
+#define bfin_read_CAN1_AM11H()          bfin_read16(CAN1_AM11H)
+#define bfin_write_CAN1_AM11H(val)      bfin_write16(CAN1_AM11H, val)
+#define bfin_read_CAN1_AM12L()          bfin_read16(CAN1_AM12L)
+#define bfin_write_CAN1_AM12L(val)      bfin_write16(CAN1_AM12L, val)
+#define bfin_read_CAN1_AM12H()          bfin_read16(CAN1_AM12H)
+#define bfin_write_CAN1_AM12H(val)      bfin_write16(CAN1_AM12H, val)
+#define bfin_read_CAN1_AM13L()          bfin_read16(CAN1_AM13L)
+#define bfin_write_CAN1_AM13L(val)      bfin_write16(CAN1_AM13L, val)
+#define bfin_read_CAN1_AM13H()          bfin_read16(CAN1_AM13H)
+#define bfin_write_CAN1_AM13H(val)      bfin_write16(CAN1_AM13H, val)
+#define bfin_read_CAN1_AM14L()          bfin_read16(CAN1_AM14L)
+#define bfin_write_CAN1_AM14L(val)      bfin_write16(CAN1_AM14L, val)
+#define bfin_read_CAN1_AM14H()          bfin_read16(CAN1_AM14H)
+#define bfin_write_CAN1_AM14H(val)      bfin_write16(CAN1_AM14H, val)
+#define bfin_read_CAN1_AM15L()          bfin_read16(CAN1_AM15L)
+#define bfin_write_CAN1_AM15L(val)      bfin_write16(CAN1_AM15L, val)
+#define bfin_read_CAN1_AM15H()          bfin_read16(CAN1_AM15H)
+#define bfin_write_CAN1_AM15H(val)      bfin_write16(CAN1_AM15H, val)
+
+/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
+
+#define bfin_read_CAN1_AM16L()          bfin_read16(CAN1_AM16L)
+#define bfin_write_CAN1_AM16L(val)      bfin_write16(CAN1_AM16L, val)
+#define bfin_read_CAN1_AM16H()          bfin_read16(CAN1_AM16H)
+#define bfin_write_CAN1_AM16H(val)      bfin_write16(CAN1_AM16H, val)
+#define bfin_read_CAN1_AM17L()          bfin_read16(CAN1_AM17L)
+#define bfin_write_CAN1_AM17L(val)      bfin_write16(CAN1_AM17L, val)
+#define bfin_read_CAN1_AM17H()          bfin_read16(CAN1_AM17H)
+#define bfin_write_CAN1_AM17H(val)      bfin_write16(CAN1_AM17H, val)
+#define bfin_read_CAN1_AM18L()          bfin_read16(CAN1_AM18L)
+#define bfin_write_CAN1_AM18L(val)      bfin_write16(CAN1_AM18L, val)
+#define bfin_read_CAN1_AM18H()          bfin_read16(CAN1_AM18H)
+#define bfin_write_CAN1_AM18H(val)      bfin_write16(CAN1_AM18H, val)
+#define bfin_read_CAN1_AM19L()          bfin_read16(CAN1_AM19L)
+#define bfin_write_CAN1_AM19L(val)      bfin_write16(CAN1_AM19L, val)
+#define bfin_read_CAN1_AM19H()          bfin_read16(CAN1_AM19H)
+#define bfin_write_CAN1_AM19H(val)      bfin_write16(CAN1_AM19H, val)
+#define bfin_read_CAN1_AM20L()          bfin_read16(CAN1_AM20L)
+#define bfin_write_CAN1_AM20L(val)      bfin_write16(CAN1_AM20L, val)
+#define bfin_read_CAN1_AM20H()          bfin_read16(CAN1_AM20H)
+#define bfin_write_CAN1_AM20H(val)      bfin_write16(CAN1_AM20H, val)
+#define bfin_read_CAN1_AM21L()          bfin_read16(CAN1_AM21L)
+#define bfin_write_CAN1_AM21L(val)      bfin_write16(CAN1_AM21L, val)
+#define bfin_read_CAN1_AM21H()          bfin_read16(CAN1_AM21H)
+#define bfin_write_CAN1_AM21H(val)      bfin_write16(CAN1_AM21H, val)
+#define bfin_read_CAN1_AM22L()          bfin_read16(CAN1_AM22L)
+#define bfin_write_CAN1_AM22L(val)      bfin_write16(CAN1_AM22L, val)
+#define bfin_read_CAN1_AM22H()          bfin_read16(CAN1_AM22H)
+#define bfin_write_CAN1_AM22H(val)      bfin_write16(CAN1_AM22H, val)
+#define bfin_read_CAN1_AM23L()          bfin_read16(CAN1_AM23L)
+#define bfin_write_CAN1_AM23L(val)      bfin_write16(CAN1_AM23L, val)
+#define bfin_read_CAN1_AM23H()          bfin_read16(CAN1_AM23H)
+#define bfin_write_CAN1_AM23H(val)      bfin_write16(CAN1_AM23H, val)
+#define bfin_read_CAN1_AM24L()          bfin_read16(CAN1_AM24L)
+#define bfin_write_CAN1_AM24L(val)      bfin_write16(CAN1_AM24L, val)
+#define bfin_read_CAN1_AM24H()          bfin_read16(CAN1_AM24H)
+#define bfin_write_CAN1_AM24H(val)      bfin_write16(CAN1_AM24H, val)
+#define bfin_read_CAN1_AM25L()          bfin_read16(CAN1_AM25L)
+#define bfin_write_CAN1_AM25L(val)      bfin_write16(CAN1_AM25L, val)
+#define bfin_read_CAN1_AM25H()          bfin_read16(CAN1_AM25H)
+#define bfin_write_CAN1_AM25H(val)      bfin_write16(CAN1_AM25H, val)
+#define bfin_read_CAN1_AM26L()          bfin_read16(CAN1_AM26L)
+#define bfin_write_CAN1_AM26L(val)      bfin_write16(CAN1_AM26L, val)
+#define bfin_read_CAN1_AM26H()          bfin_read16(CAN1_AM26H)
+#define bfin_write_CAN1_AM26H(val)      bfin_write16(CAN1_AM26H, val)
+#define bfin_read_CAN1_AM27L()          bfin_read16(CAN1_AM27L)
+#define bfin_write_CAN1_AM27L(val)      bfin_write16(CAN1_AM27L, val)
+#define bfin_read_CAN1_AM27H()          bfin_read16(CAN1_AM27H)
+#define bfin_write_CAN1_AM27H(val)      bfin_write16(CAN1_AM27H, val)
+#define bfin_read_CAN1_AM28L()          bfin_read16(CAN1_AM28L)
+#define bfin_write_CAN1_AM28L(val)      bfin_write16(CAN1_AM28L, val)
+#define bfin_read_CAN1_AM28H()          bfin_read16(CAN1_AM28H)
+#define bfin_write_CAN1_AM28H(val)      bfin_write16(CAN1_AM28H, val)
+#define bfin_read_CAN1_AM29L()          bfin_read16(CAN1_AM29L)
+#define bfin_write_CAN1_AM29L(val)      bfin_write16(CAN1_AM29L, val)
+#define bfin_read_CAN1_AM29H()          bfin_read16(CAN1_AM29H)
+#define bfin_write_CAN1_AM29H(val)      bfin_write16(CAN1_AM29H, val)
+#define bfin_read_CAN1_AM30L()          bfin_read16(CAN1_AM30L)
+#define bfin_write_CAN1_AM30L(val)      bfin_write16(CAN1_AM30L, val)
+#define bfin_read_CAN1_AM30H()          bfin_read16(CAN1_AM30H)
+#define bfin_write_CAN1_AM30H(val)      bfin_write16(CAN1_AM30H, val)
+#define bfin_read_CAN1_AM31L()          bfin_read16(CAN1_AM31L)
+#define bfin_write_CAN1_AM31L(val)      bfin_write16(CAN1_AM31L, val)
+#define bfin_read_CAN1_AM31H()          bfin_read16(CAN1_AM31H)
+#define bfin_write_CAN1_AM31H(val)      bfin_write16(CAN1_AM31H, val)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define bfin_read_CAN1_MB00_DATA0()             bfin_read16(CAN1_MB00_DATA0)
+#define bfin_write_CAN1_MB00_DATA0(val)         bfin_write16(CAN1_MB00_DATA0, val)
+#define bfin_read_CAN1_MB00_DATA1()             bfin_read16(CAN1_MB00_DATA1)
+#define bfin_write_CAN1_MB00_DATA1(val)         bfin_write16(CAN1_MB00_DATA1, val)
+#define bfin_read_CAN1_MB00_DATA2()             bfin_read16(CAN1_MB00_DATA2)
+#define bfin_write_CAN1_MB00_DATA2(val)         bfin_write16(CAN1_MB00_DATA2, val)
+#define bfin_read_CAN1_MB00_DATA3()             bfin_read16(CAN1_MB00_DATA3)
+#define bfin_write_CAN1_MB00_DATA3(val)         bfin_write16(CAN1_MB00_DATA3, val)
+#define bfin_read_CAN1_MB00_LENGTH()            bfin_read16(CAN1_MB00_LENGTH)
+#define bfin_write_CAN1_MB00_LENGTH(val)        bfin_write16(CAN1_MB00_LENGTH, val)
+#define bfin_read_CAN1_MB00_TIMESTAMP()         bfin_read16(CAN1_MB00_TIMESTAMP)
+#define bfin_write_CAN1_MB00_TIMESTAMP(val)     bfin_write16(CAN1_MB00_TIMESTAMP, val)
+#define bfin_read_CAN1_MB00_ID0()               bfin_read16(CAN1_MB00_ID0)
+#define bfin_write_CAN1_MB00_ID0(val)           bfin_write16(CAN1_MB00_ID0, val)
+#define bfin_read_CAN1_MB00_ID1()               bfin_read16(CAN1_MB00_ID1)
+#define bfin_write_CAN1_MB00_ID1(val)           bfin_write16(CAN1_MB00_ID1, val)
+#define bfin_read_CAN1_MB01_DATA0()             bfin_read16(CAN1_MB01_DATA0)
+#define bfin_write_CAN1_MB01_DATA0(val)         bfin_write16(CAN1_MB01_DATA0, val)
+#define bfin_read_CAN1_MB01_DATA1()             bfin_read16(CAN1_MB01_DATA1)
+#define bfin_write_CAN1_MB01_DATA1(val)         bfin_write16(CAN1_MB01_DATA1, val)
+#define bfin_read_CAN1_MB01_DATA2()             bfin_read16(CAN1_MB01_DATA2)
+#define bfin_write_CAN1_MB01_DATA2(val)         bfin_write16(CAN1_MB01_DATA2, val)
+#define bfin_read_CAN1_MB01_DATA3()             bfin_read16(CAN1_MB01_DATA3)
+#define bfin_write_CAN1_MB01_DATA3(val)         bfin_write16(CAN1_MB01_DATA3, val)
+#define bfin_read_CAN1_MB01_LENGTH()            bfin_read16(CAN1_MB01_LENGTH)
+#define bfin_write_CAN1_MB01_LENGTH(val)        bfin_write16(CAN1_MB01_LENGTH, val)
+#define bfin_read_CAN1_MB01_TIMESTAMP()         bfin_read16(CAN1_MB01_TIMESTAMP)
+#define bfin_write_CAN1_MB01_TIMESTAMP(val)     bfin_write16(CAN1_MB01_TIMESTAMP, val)
+#define bfin_read_CAN1_MB01_ID0()               bfin_read16(CAN1_MB01_ID0)
+#define bfin_write_CAN1_MB01_ID0(val)           bfin_write16(CAN1_MB01_ID0, val)
+#define bfin_read_CAN1_MB01_ID1()               bfin_read16(CAN1_MB01_ID1)
+#define bfin_write_CAN1_MB01_ID1(val)           bfin_write16(CAN1_MB01_ID1, val)
+#define bfin_read_CAN1_MB02_DATA0()             bfin_read16(CAN1_MB02_DATA0)
+#define bfin_write_CAN1_MB02_DATA0(val)         bfin_write16(CAN1_MB02_DATA0, val)
+#define bfin_read_CAN1_MB02_DATA1()             bfin_read16(CAN1_MB02_DATA1)
+#define bfin_write_CAN1_MB02_DATA1(val)         bfin_write16(CAN1_MB02_DATA1, val)
+#define bfin_read_CAN1_MB02_DATA2()             bfin_read16(CAN1_MB02_DATA2)
+#define bfin_write_CAN1_MB02_DATA2(val)         bfin_write16(CAN1_MB02_DATA2, val)
+#define bfin_read_CAN1_MB02_DATA3()             bfin_read16(CAN1_MB02_DATA3)
+#define bfin_write_CAN1_MB02_DATA3(val)         bfin_write16(CAN1_MB02_DATA3, val)
+#define bfin_read_CAN1_MB02_LENGTH()            bfin_read16(CAN1_MB02_LENGTH)
+#define bfin_write_CAN1_MB02_LENGTH(val)        bfin_write16(CAN1_MB02_LENGTH, val)
+#define bfin_read_CAN1_MB02_TIMESTAMP()         bfin_read16(CAN1_MB02_TIMESTAMP)
+#define bfin_write_CAN1_MB02_TIMESTAMP(val)     bfin_write16(CAN1_MB02_TIMESTAMP, val)
+#define bfin_read_CAN1_MB02_ID0()               bfin_read16(CAN1_MB02_ID0)
+#define bfin_write_CAN1_MB02_ID0(val)           bfin_write16(CAN1_MB02_ID0, val)
+#define bfin_read_CAN1_MB02_ID1()               bfin_read16(CAN1_MB02_ID1)
+#define bfin_write_CAN1_MB02_ID1(val)           bfin_write16(CAN1_MB02_ID1, val)
+#define bfin_read_CAN1_MB03_DATA0()             bfin_read16(CAN1_MB03_DATA0)
+#define bfin_write_CAN1_MB03_DATA0(val)         bfin_write16(CAN1_MB03_DATA0, val)
+#define bfin_read_CAN1_MB03_DATA1()             bfin_read16(CAN1_MB03_DATA1)
+#define bfin_write_CAN1_MB03_DATA1(val)         bfin_write16(CAN1_MB03_DATA1, val)
+#define bfin_read_CAN1_MB03_DATA2()             bfin_read16(CAN1_MB03_DATA2)
+#define bfin_write_CAN1_MB03_DATA2(val)         bfin_write16(CAN1_MB03_DATA2, val)
+#define bfin_read_CAN1_MB03_DATA3()             bfin_read16(CAN1_MB03_DATA3)
+#define bfin_write_CAN1_MB03_DATA3(val)         bfin_write16(CAN1_MB03_DATA3, val)
+#define bfin_read_CAN1_MB03_LENGTH()            bfin_read16(CAN1_MB03_LENGTH)
+#define bfin_write_CAN1_MB03_LENGTH(val)        bfin_write16(CAN1_MB03_LENGTH, val)
+#define bfin_read_CAN1_MB03_TIMESTAMP()         bfin_read16(CAN1_MB03_TIMESTAMP)
+#define bfin_write_CAN1_MB03_TIMESTAMP(val)     bfin_write16(CAN1_MB03_TIMESTAMP, val)
+#define bfin_read_CAN1_MB03_ID0()               bfin_read16(CAN1_MB03_ID0)
+#define bfin_write_CAN1_MB03_ID0(val)           bfin_write16(CAN1_MB03_ID0, val)
+#define bfin_read_CAN1_MB03_ID1()               bfin_read16(CAN1_MB03_ID1)
+#define bfin_write_CAN1_MB03_ID1(val)           bfin_write16(CAN1_MB03_ID1, val)
+#define bfin_read_CAN1_MB04_DATA0()             bfin_read16(CAN1_MB04_DATA0)
+#define bfin_write_CAN1_MB04_DATA0(val)         bfin_write16(CAN1_MB04_DATA0, val)
+#define bfin_read_CAN1_MB04_DATA1()             bfin_read16(CAN1_MB04_DATA1)
+#define bfin_write_CAN1_MB04_DATA1(val)         bfin_write16(CAN1_MB04_DATA1, val)
+#define bfin_read_CAN1_MB04_DATA2()             bfin_read16(CAN1_MB04_DATA2)
+#define bfin_write_CAN1_MB04_DATA2(val)         bfin_write16(CAN1_MB04_DATA2, val)
+#define bfin_read_CAN1_MB04_DATA3()             bfin_read16(CAN1_MB04_DATA3)
+#define bfin_write_CAN1_MB04_DATA3(val)         bfin_write16(CAN1_MB04_DATA3, val)
+#define bfin_read_CAN1_MB04_LENGTH()            bfin_read16(CAN1_MB04_LENGTH)
+#define bfin_write_CAN1_MB04_LENGTH(val)        bfin_write16(CAN1_MB04_LENGTH, val)
+#define bfin_read_CAN1_MB04_TIMESTAMP()         bfin_read16(CAN1_MB04_TIMESTAMP)
+#define bfin_write_CAN1_MB04_TIMESTAMP(val)     bfin_write16(CAN1_MB04_TIMESTAMP, val)
+#define bfin_read_CAN1_MB04_ID0()               bfin_read16(CAN1_MB04_ID0)
+#define bfin_write_CAN1_MB04_ID0(val)           bfin_write16(CAN1_MB04_ID0, val)
+#define bfin_read_CAN1_MB04_ID1()               bfin_read16(CAN1_MB04_ID1)
+#define bfin_write_CAN1_MB04_ID1(val)           bfin_write16(CAN1_MB04_ID1, val)
+#define bfin_read_CAN1_MB05_DATA0()             bfin_read16(CAN1_MB05_DATA0)
+#define bfin_write_CAN1_MB05_DATA0(val)         bfin_write16(CAN1_MB05_DATA0, val)
+#define bfin_read_CAN1_MB05_DATA1()             bfin_read16(CAN1_MB05_DATA1)
+#define bfin_write_CAN1_MB05_DATA1(val)         bfin_write16(CAN1_MB05_DATA1, val)
+#define bfin_read_CAN1_MB05_DATA2()             bfin_read16(CAN1_MB05_DATA2)
+#define bfin_write_CAN1_MB05_DATA2(val)         bfin_write16(CAN1_MB05_DATA2, val)
+#define bfin_read_CAN1_MB05_DATA3()             bfin_read16(CAN1_MB05_DATA3)
+#define bfin_write_CAN1_MB05_DATA3(val)         bfin_write16(CAN1_MB05_DATA3, val)
+#define bfin_read_CAN1_MB05_LENGTH()            bfin_read16(CAN1_MB05_LENGTH)
+#define bfin_write_CAN1_MB05_LENGTH(val)        bfin_write16(CAN1_MB05_LENGTH, val)
+#define bfin_read_CAN1_MB05_TIMESTAMP()         bfin_read16(CAN1_MB05_TIMESTAMP)
+#define bfin_write_CAN1_MB05_TIMESTAMP(val)     bfin_write16(CAN1_MB05_TIMESTAMP, val)
+#define bfin_read_CAN1_MB05_ID0()               bfin_read16(CAN1_MB05_ID0)
+#define bfin_write_CAN1_MB05_ID0(val)           bfin_write16(CAN1_MB05_ID0, val)
+#define bfin_read_CAN1_MB05_ID1()               bfin_read16(CAN1_MB05_ID1)
+#define bfin_write_CAN1_MB05_ID1(val)           bfin_write16(CAN1_MB05_ID1, val)
+#define bfin_read_CAN1_MB06_DATA0()             bfin_read16(CAN1_MB06_DATA0)
+#define bfin_write_CAN1_MB06_DATA0(val)         bfin_write16(CAN1_MB06_DATA0, val)
+#define bfin_read_CAN1_MB06_DATA1()             bfin_read16(CAN1_MB06_DATA1)
+#define bfin_write_CAN1_MB06_DATA1(val)         bfin_write16(CAN1_MB06_DATA1, val)
+#define bfin_read_CAN1_MB06_DATA2()             bfin_read16(CAN1_MB06_DATA2)
+#define bfin_write_CAN1_MB06_DATA2(val)         bfin_write16(CAN1_MB06_DATA2, val)
+#define bfin_read_CAN1_MB06_DATA3()             bfin_read16(CAN1_MB06_DATA3)
+#define bfin_write_CAN1_MB06_DATA3(val)         bfin_write16(CAN1_MB06_DATA3, val)
+#define bfin_read_CAN1_MB06_LENGTH()            bfin_read16(CAN1_MB06_LENGTH)
+#define bfin_write_CAN1_MB06_LENGTH(val)        bfin_write16(CAN1_MB06_LENGTH, val)
+#define bfin_read_CAN1_MB06_TIMESTAMP()         bfin_read16(CAN1_MB06_TIMESTAMP)
+#define bfin_write_CAN1_MB06_TIMESTAMP(val)     bfin_write16(CAN1_MB06_TIMESTAMP, val)
+#define bfin_read_CAN1_MB06_ID0()               bfin_read16(CAN1_MB06_ID0)
+#define bfin_write_CAN1_MB06_ID0(val)           bfin_write16(CAN1_MB06_ID0, val)
+#define bfin_read_CAN1_MB06_ID1()               bfin_read16(CAN1_MB06_ID1)
+#define bfin_write_CAN1_MB06_ID1(val)           bfin_write16(CAN1_MB06_ID1, val)
+#define bfin_read_CAN1_MB07_DATA0()             bfin_read16(CAN1_MB07_DATA0)
+#define bfin_write_CAN1_MB07_DATA0(val)         bfin_write16(CAN1_MB07_DATA0, val)
+#define bfin_read_CAN1_MB07_DATA1()             bfin_read16(CAN1_MB07_DATA1)
+#define bfin_write_CAN1_MB07_DATA1(val)         bfin_write16(CAN1_MB07_DATA1, val)
+#define bfin_read_CAN1_MB07_DATA2()             bfin_read16(CAN1_MB07_DATA2)
+#define bfin_write_CAN1_MB07_DATA2(val)         bfin_write16(CAN1_MB07_DATA2, val)
+#define bfin_read_CAN1_MB07_DATA3()             bfin_read16(CAN1_MB07_DATA3)
+#define bfin_write_CAN1_MB07_DATA3(val)         bfin_write16(CAN1_MB07_DATA3, val)
+#define bfin_read_CAN1_MB07_LENGTH()            bfin_read16(CAN1_MB07_LENGTH)
+#define bfin_write_CAN1_MB07_LENGTH(val)        bfin_write16(CAN1_MB07_LENGTH, val)
+#define bfin_read_CAN1_MB07_TIMESTAMP()         bfin_read16(CAN1_MB07_TIMESTAMP)
+#define bfin_write_CAN1_MB07_TIMESTAMP(val)     bfin_write16(CAN1_MB07_TIMESTAMP, val)
+#define bfin_read_CAN1_MB07_ID0()               bfin_read16(CAN1_MB07_ID0)
+#define bfin_write_CAN1_MB07_ID0(val)           bfin_write16(CAN1_MB07_ID0, val)
+#define bfin_read_CAN1_MB07_ID1()               bfin_read16(CAN1_MB07_ID1)
+#define bfin_write_CAN1_MB07_ID1(val)           bfin_write16(CAN1_MB07_ID1, val)
+#define bfin_read_CAN1_MB08_DATA0()             bfin_read16(CAN1_MB08_DATA0)
+#define bfin_write_CAN1_MB08_DATA0(val)         bfin_write16(CAN1_MB08_DATA0, val)
+#define bfin_read_CAN1_MB08_DATA1()             bfin_read16(CAN1_MB08_DATA1)
+#define bfin_write_CAN1_MB08_DATA1(val)         bfin_write16(CAN1_MB08_DATA1, val)
+#define bfin_read_CAN1_MB08_DATA2()             bfin_read16(CAN1_MB08_DATA2)
+#define bfin_write_CAN1_MB08_DATA2(val)         bfin_write16(CAN1_MB08_DATA2, val)
+#define bfin_read_CAN1_MB08_DATA3()             bfin_read16(CAN1_MB08_DATA3)
+#define bfin_write_CAN1_MB08_DATA3(val)         bfin_write16(CAN1_MB08_DATA3, val)
+#define bfin_read_CAN1_MB08_LENGTH()            bfin_read16(CAN1_MB08_LENGTH)
+#define bfin_write_CAN1_MB08_LENGTH(val)        bfin_write16(CAN1_MB08_LENGTH, val)
+#define bfin_read_CAN1_MB08_TIMESTAMP()         bfin_read16(CAN1_MB08_TIMESTAMP)
+#define bfin_write_CAN1_MB08_TIMESTAMP(val)     bfin_write16(CAN1_MB08_TIMESTAMP, val)
+#define bfin_read_CAN1_MB08_ID0()               bfin_read16(CAN1_MB08_ID0)
+#define bfin_write_CAN1_MB08_ID0(val)           bfin_write16(CAN1_MB08_ID0, val)
+#define bfin_read_CAN1_MB08_ID1()               bfin_read16(CAN1_MB08_ID1)
+#define bfin_write_CAN1_MB08_ID1(val)           bfin_write16(CAN1_MB08_ID1, val)
+#define bfin_read_CAN1_MB09_DATA0()             bfin_read16(CAN1_MB09_DATA0)
+#define bfin_write_CAN1_MB09_DATA0(val)         bfin_write16(CAN1_MB09_DATA0, val)
+#define bfin_read_CAN1_MB09_DATA1()             bfin_read16(CAN1_MB09_DATA1)
+#define bfin_write_CAN1_MB09_DATA1(val)         bfin_write16(CAN1_MB09_DATA1, val)
+#define bfin_read_CAN1_MB09_DATA2()             bfin_read16(CAN1_MB09_DATA2)
+#define bfin_write_CAN1_MB09_DATA2(val)         bfin_write16(CAN1_MB09_DATA2, val)
+#define bfin_read_CAN1_MB09_DATA3()             bfin_read16(CAN1_MB09_DATA3)
+#define bfin_write_CAN1_MB09_DATA3(val)         bfin_write16(CAN1_MB09_DATA3, val)
+#define bfin_read_CAN1_MB09_LENGTH()            bfin_read16(CAN1_MB09_LENGTH)
+#define bfin_write_CAN1_MB09_LENGTH(val)        bfin_write16(CAN1_MB09_LENGTH, val)
+#define bfin_read_CAN1_MB09_TIMESTAMP()         bfin_read16(CAN1_MB09_TIMESTAMP)
+#define bfin_write_CAN1_MB09_TIMESTAMP(val)     bfin_write16(CAN1_MB09_TIMESTAMP, val)
+#define bfin_read_CAN1_MB09_ID0()               bfin_read16(CAN1_MB09_ID0)
+#define bfin_write_CAN1_MB09_ID0(val)           bfin_write16(CAN1_MB09_ID0, val)
+#define bfin_read_CAN1_MB09_ID1()               bfin_read16(CAN1_MB09_ID1)
+#define bfin_write_CAN1_MB09_ID1(val)           bfin_write16(CAN1_MB09_ID1, val)
+#define bfin_read_CAN1_MB10_DATA0()             bfin_read16(CAN1_MB10_DATA0)
+#define bfin_write_CAN1_MB10_DATA0(val)         bfin_write16(CAN1_MB10_DATA0, val)
+#define bfin_read_CAN1_MB10_DATA1()             bfin_read16(CAN1_MB10_DATA1)
+#define bfin_write_CAN1_MB10_DATA1(val)         bfin_write16(CAN1_MB10_DATA1, val)
+#define bfin_read_CAN1_MB10_DATA2()             bfin_read16(CAN1_MB10_DATA2)
+#define bfin_write_CAN1_MB10_DATA2(val)         bfin_write16(CAN1_MB10_DATA2, val)
+#define bfin_read_CAN1_MB10_DATA3()             bfin_read16(CAN1_MB10_DATA3)
+#define bfin_write_CAN1_MB10_DATA3(val)         bfin_write16(CAN1_MB10_DATA3, val)
+#define bfin_read_CAN1_MB10_LENGTH()            bfin_read16(CAN1_MB10_LENGTH)
+#define bfin_write_CAN1_MB10_LENGTH(val)        bfin_write16(CAN1_MB10_LENGTH, val)
+#define bfin_read_CAN1_MB10_TIMESTAMP()         bfin_read16(CAN1_MB10_TIMESTAMP)
+#define bfin_write_CAN1_MB10_TIMESTAMP(val)     bfin_write16(CAN1_MB10_TIMESTAMP, val)
+#define bfin_read_CAN1_MB10_ID0()               bfin_read16(CAN1_MB10_ID0)
+#define bfin_write_CAN1_MB10_ID0(val)           bfin_write16(CAN1_MB10_ID0, val)
+#define bfin_read_CAN1_MB10_ID1()               bfin_read16(CAN1_MB10_ID1)
+#define bfin_write_CAN1_MB10_ID1(val)           bfin_write16(CAN1_MB10_ID1, val)
+#define bfin_read_CAN1_MB11_DATA0()             bfin_read16(CAN1_MB11_DATA0)
+#define bfin_write_CAN1_MB11_DATA0(val)         bfin_write16(CAN1_MB11_DATA0, val)
+#define bfin_read_CAN1_MB11_DATA1()             bfin_read16(CAN1_MB11_DATA1)
+#define bfin_write_CAN1_MB11_DATA1(val)         bfin_write16(CAN1_MB11_DATA1, val)
+#define bfin_read_CAN1_MB11_DATA2()             bfin_read16(CAN1_MB11_DATA2)
+#define bfin_write_CAN1_MB11_DATA2(val)         bfin_write16(CAN1_MB11_DATA2, val)
+#define bfin_read_CAN1_MB11_DATA3()             bfin_read16(CAN1_MB11_DATA3)
+#define bfin_write_CAN1_MB11_DATA3(val)         bfin_write16(CAN1_MB11_DATA3, val)
+#define bfin_read_CAN1_MB11_LENGTH()            bfin_read16(CAN1_MB11_LENGTH)
+#define bfin_write_CAN1_MB11_LENGTH(val)        bfin_write16(CAN1_MB11_LENGTH, val)
+#define bfin_read_CAN1_MB11_TIMESTAMP()         bfin_read16(CAN1_MB11_TIMESTAMP)
+#define bfin_write_CAN1_MB11_TIMESTAMP(val)     bfin_write16(CAN1_MB11_TIMESTAMP, val)
+#define bfin_read_CAN1_MB11_ID0()               bfin_read16(CAN1_MB11_ID0)
+#define bfin_write_CAN1_MB11_ID0(val)           bfin_write16(CAN1_MB11_ID0, val)
+#define bfin_read_CAN1_MB11_ID1()               bfin_read16(CAN1_MB11_ID1)
+#define bfin_write_CAN1_MB11_ID1(val)           bfin_write16(CAN1_MB11_ID1, val)
+#define bfin_read_CAN1_MB12_DATA0()             bfin_read16(CAN1_MB12_DATA0)
+#define bfin_write_CAN1_MB12_DATA0(val)         bfin_write16(CAN1_MB12_DATA0, val)
+#define bfin_read_CAN1_MB12_DATA1()             bfin_read16(CAN1_MB12_DATA1)
+#define bfin_write_CAN1_MB12_DATA1(val)         bfin_write16(CAN1_MB12_DATA1, val)
+#define bfin_read_CAN1_MB12_DATA2()             bfin_read16(CAN1_MB12_DATA2)
+#define bfin_write_CAN1_MB12_DATA2(val)         bfin_write16(CAN1_MB12_DATA2, val)
+#define bfin_read_CAN1_MB12_DATA3()             bfin_read16(CAN1_MB12_DATA3)
+#define bfin_write_CAN1_MB12_DATA3(val)         bfin_write16(CAN1_MB12_DATA3, val)
+#define bfin_read_CAN1_MB12_LENGTH()            bfin_read16(CAN1_MB12_LENGTH)
+#define bfin_write_CAN1_MB12_LENGTH(val)        bfin_write16(CAN1_MB12_LENGTH, val)
+#define bfin_read_CAN1_MB12_TIMESTAMP()         bfin_read16(CAN1_MB12_TIMESTAMP)
+#define bfin_write_CAN1_MB12_TIMESTAMP(val)     bfin_write16(CAN1_MB12_TIMESTAMP, val)
+#define bfin_read_CAN1_MB12_ID0()               bfin_read16(CAN1_MB12_ID0)
+#define bfin_write_CAN1_MB12_ID0(val)           bfin_write16(CAN1_MB12_ID0, val)
+#define bfin_read_CAN1_MB12_ID1()               bfin_read16(CAN1_MB12_ID1)
+#define bfin_write_CAN1_MB12_ID1(val)           bfin_write16(CAN1_MB12_ID1, val)
+#define bfin_read_CAN1_MB13_DATA0()             bfin_read16(CAN1_MB13_DATA0)
+#define bfin_write_CAN1_MB13_DATA0(val)         bfin_write16(CAN1_MB13_DATA0, val)
+#define bfin_read_CAN1_MB13_DATA1()             bfin_read16(CAN1_MB13_DATA1)
+#define bfin_write_CAN1_MB13_DATA1(val)         bfin_write16(CAN1_MB13_DATA1, val)
+#define bfin_read_CAN1_MB13_DATA2()             bfin_read16(CAN1_MB13_DATA2)
+#define bfin_write_CAN1_MB13_DATA2(val)         bfin_write16(CAN1_MB13_DATA2, val)
+#define bfin_read_CAN1_MB13_DATA3()             bfin_read16(CAN1_MB13_DATA3)
+#define bfin_write_CAN1_MB13_DATA3(val)         bfin_write16(CAN1_MB13_DATA3, val)
+#define bfin_read_CAN1_MB13_LENGTH()            bfin_read16(CAN1_MB13_LENGTH)
+#define bfin_write_CAN1_MB13_LENGTH(val)        bfin_write16(CAN1_MB13_LENGTH, val)
+#define bfin_read_CAN1_MB13_TIMESTAMP()         bfin_read16(CAN1_MB13_TIMESTAMP)
+#define bfin_write_CAN1_MB13_TIMESTAMP(val)     bfin_write16(CAN1_MB13_TIMESTAMP, val)
+#define bfin_read_CAN1_MB13_ID0()               bfin_read16(CAN1_MB13_ID0)
+#define bfin_write_CAN1_MB13_ID0(val)           bfin_write16(CAN1_MB13_ID0, val)
+#define bfin_read_CAN1_MB13_ID1()               bfin_read16(CAN1_MB13_ID1)
+#define bfin_write_CAN1_MB13_ID1(val)           bfin_write16(CAN1_MB13_ID1, val)
+#define bfin_read_CAN1_MB14_DATA0()             bfin_read16(CAN1_MB14_DATA0)
+#define bfin_write_CAN1_MB14_DATA0(val)         bfin_write16(CAN1_MB14_DATA0, val)
+#define bfin_read_CAN1_MB14_DATA1()             bfin_read16(CAN1_MB14_DATA1)
+#define bfin_write_CAN1_MB14_DATA1(val)         bfin_write16(CAN1_MB14_DATA1, val)
+#define bfin_read_CAN1_MB14_DATA2()             bfin_read16(CAN1_MB14_DATA2)
+#define bfin_write_CAN1_MB14_DATA2(val)         bfin_write16(CAN1_MB14_DATA2, val)
+#define bfin_read_CAN1_MB14_DATA3()             bfin_read16(CAN1_MB14_DATA3)
+#define bfin_write_CAN1_MB14_DATA3(val)         bfin_write16(CAN1_MB14_DATA3, val)
+#define bfin_read_CAN1_MB14_LENGTH()            bfin_read16(CAN1_MB14_LENGTH)
+#define bfin_write_CAN1_MB14_LENGTH(val)        bfin_write16(CAN1_MB14_LENGTH, val)
+#define bfin_read_CAN1_MB14_TIMESTAMP()         bfin_read16(CAN1_MB14_TIMESTAMP)
+#define bfin_write_CAN1_MB14_TIMESTAMP(val)     bfin_write16(CAN1_MB14_TIMESTAMP, val)
+#define bfin_read_CAN1_MB14_ID0()               bfin_read16(CAN1_MB14_ID0)
+#define bfin_write_CAN1_MB14_ID0(val)           bfin_write16(CAN1_MB14_ID0, val)
+#define bfin_read_CAN1_MB14_ID1()               bfin_read16(CAN1_MB14_ID1)
+#define bfin_write_CAN1_MB14_ID1(val)           bfin_write16(CAN1_MB14_ID1, val)
+#define bfin_read_CAN1_MB15_DATA0()             bfin_read16(CAN1_MB15_DATA0)
+#define bfin_write_CAN1_MB15_DATA0(val)         bfin_write16(CAN1_MB15_DATA0, val)
+#define bfin_read_CAN1_MB15_DATA1()             bfin_read16(CAN1_MB15_DATA1)
+#define bfin_write_CAN1_MB15_DATA1(val)         bfin_write16(CAN1_MB15_DATA1, val)
+#define bfin_read_CAN1_MB15_DATA2()             bfin_read16(CAN1_MB15_DATA2)
+#define bfin_write_CAN1_MB15_DATA2(val)         bfin_write16(CAN1_MB15_DATA2, val)
+#define bfin_read_CAN1_MB15_DATA3()             bfin_read16(CAN1_MB15_DATA3)
+#define bfin_write_CAN1_MB15_DATA3(val)         bfin_write16(CAN1_MB15_DATA3, val)
+#define bfin_read_CAN1_MB15_LENGTH()            bfin_read16(CAN1_MB15_LENGTH)
+#define bfin_write_CAN1_MB15_LENGTH(val)        bfin_write16(CAN1_MB15_LENGTH, val)
+#define bfin_read_CAN1_MB15_TIMESTAMP()         bfin_read16(CAN1_MB15_TIMESTAMP)
+#define bfin_write_CAN1_MB15_TIMESTAMP(val)     bfin_write16(CAN1_MB15_TIMESTAMP, val)
+#define bfin_read_CAN1_MB15_ID0()               bfin_read16(CAN1_MB15_ID0)
+#define bfin_write_CAN1_MB15_ID0(val)           bfin_write16(CAN1_MB15_ID0, val)
+#define bfin_read_CAN1_MB15_ID1()               bfin_read16(CAN1_MB15_ID1)
+#define bfin_write_CAN1_MB15_ID1(val)           bfin_write16(CAN1_MB15_ID1, val)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define bfin_read_CAN1_MB16_DATA0()             bfin_read16(CAN1_MB16_DATA0)
+#define bfin_write_CAN1_MB16_DATA0(val)         bfin_write16(CAN1_MB16_DATA0, val)
+#define bfin_read_CAN1_MB16_DATA1()             bfin_read16(CAN1_MB16_DATA1)
+#define bfin_write_CAN1_MB16_DATA1(val)         bfin_write16(CAN1_MB16_DATA1, val)
+#define bfin_read_CAN1_MB16_DATA2()             bfin_read16(CAN1_MB16_DATA2)
+#define bfin_write_CAN1_MB16_DATA2(val)         bfin_write16(CAN1_MB16_DATA2, val)
+#define bfin_read_CAN1_MB16_DATA3()             bfin_read16(CAN1_MB16_DATA3)
+#define bfin_write_CAN1_MB16_DATA3(val)         bfin_write16(CAN1_MB16_DATA3, val)
+#define bfin_read_CAN1_MB16_LENGTH()            bfin_read16(CAN1_MB16_LENGTH)
+#define bfin_write_CAN1_MB16_LENGTH(val)        bfin_write16(CAN1_MB16_LENGTH, val)
+#define bfin_read_CAN1_MB16_TIMESTAMP()         bfin_read16(CAN1_MB16_TIMESTAMP)
+#define bfin_write_CAN1_MB16_TIMESTAMP(val)     bfin_write16(CAN1_MB16_TIMESTAMP, val)
+#define bfin_read_CAN1_MB16_ID0()               bfin_read16(CAN1_MB16_ID0)
+#define bfin_write_CAN1_MB16_ID0(val)           bfin_write16(CAN1_MB16_ID0, val)
+#define bfin_read_CAN1_MB16_ID1()               bfin_read16(CAN1_MB16_ID1)
+#define bfin_write_CAN1_MB16_ID1(val)           bfin_write16(CAN1_MB16_ID1, val)
+#define bfin_read_CAN1_MB17_DATA0()             bfin_read16(CAN1_MB17_DATA0)
+#define bfin_write_CAN1_MB17_DATA0(val)         bfin_write16(CAN1_MB17_DATA0, val)
+#define bfin_read_CAN1_MB17_DATA1()             bfin_read16(CAN1_MB17_DATA1)
+#define bfin_write_CAN1_MB17_DATA1(val)         bfin_write16(CAN1_MB17_DATA1, val)
+#define bfin_read_CAN1_MB17_DATA2()             bfin_read16(CAN1_MB17_DATA2)
+#define bfin_write_CAN1_MB17_DATA2(val)         bfin_write16(CAN1_MB17_DATA2, val)
+#define bfin_read_CAN1_MB17_DATA3()             bfin_read16(CAN1_MB17_DATA3)
+#define bfin_write_CAN1_MB17_DATA3(val)         bfin_write16(CAN1_MB17_DATA3, val)
+#define bfin_read_CAN1_MB17_LENGTH()            bfin_read16(CAN1_MB17_LENGTH)
+#define bfin_write_CAN1_MB17_LENGTH(val)        bfin_write16(CAN1_MB17_LENGTH, val)
+#define bfin_read_CAN1_MB17_TIMESTAMP()         bfin_read16(CAN1_MB17_TIMESTAMP)
+#define bfin_write_CAN1_MB17_TIMESTAMP(val)     bfin_write16(CAN1_MB17_TIMESTAMP, val)
+#define bfin_read_CAN1_MB17_ID0()               bfin_read16(CAN1_MB17_ID0)
+#define bfin_write_CAN1_MB17_ID0(val)           bfin_write16(CAN1_MB17_ID0, val)
+#define bfin_read_CAN1_MB17_ID1()               bfin_read16(CAN1_MB17_ID1)
+#define bfin_write_CAN1_MB17_ID1(val)           bfin_write16(CAN1_MB17_ID1, val)
+#define bfin_read_CAN1_MB18_DATA0()             bfin_read16(CAN1_MB18_DATA0)
+#define bfin_write_CAN1_MB18_DATA0(val)         bfin_write16(CAN1_MB18_DATA0, val)
+#define bfin_read_CAN1_MB18_DATA1()             bfin_read16(CAN1_MB18_DATA1)
+#define bfin_write_CAN1_MB18_DATA1(val)         bfin_write16(CAN1_MB18_DATA1, val)
+#define bfin_read_CAN1_MB18_DATA2()             bfin_read16(CAN1_MB18_DATA2)
+#define bfin_write_CAN1_MB18_DATA2(val)         bfin_write16(CAN1_MB18_DATA2, val)
+#define bfin_read_CAN1_MB18_DATA3()             bfin_read16(CAN1_MB18_DATA3)
+#define bfin_write_CAN1_MB18_DATA3(val)         bfin_write16(CAN1_MB18_DATA3, val)
+#define bfin_read_CAN1_MB18_LENGTH()            bfin_read16(CAN1_MB18_LENGTH)
+#define bfin_write_CAN1_MB18_LENGTH(val)        bfin_write16(CAN1_MB18_LENGTH, val)
+#define bfin_read_CAN1_MB18_TIMESTAMP()         bfin_read16(CAN1_MB18_TIMESTAMP)
+#define bfin_write_CAN1_MB18_TIMESTAMP(val)     bfin_write16(CAN1_MB18_TIMESTAMP, val)
+#define bfin_read_CAN1_MB18_ID0()               bfin_read16(CAN1_MB18_ID0)
+#define bfin_write_CAN1_MB18_ID0(val)           bfin_write16(CAN1_MB18_ID0, val)
+#define bfin_read_CAN1_MB18_ID1()               bfin_read16(CAN1_MB18_ID1)
+#define bfin_write_CAN1_MB18_ID1(val)           bfin_write16(CAN1_MB18_ID1, val)
+#define bfin_read_CAN1_MB19_DATA0()             bfin_read16(CAN1_MB19_DATA0)
+#define bfin_write_CAN1_MB19_DATA0(val)         bfin_write16(CAN1_MB19_DATA0, val)
+#define bfin_read_CAN1_MB19_DATA1()             bfin_read16(CAN1_MB19_DATA1)
+#define bfin_write_CAN1_MB19_DATA1(val)         bfin_write16(CAN1_MB19_DATA1, val)
+#define bfin_read_CAN1_MB19_DATA2()             bfin_read16(CAN1_MB19_DATA2)
+#define bfin_write_CAN1_MB19_DATA2(val)         bfin_write16(CAN1_MB19_DATA2, val)
+#define bfin_read_CAN1_MB19_DATA3()             bfin_read16(CAN1_MB19_DATA3)
+#define bfin_write_CAN1_MB19_DATA3(val)         bfin_write16(CAN1_MB19_DATA3, val)
+#define bfin_read_CAN1_MB19_LENGTH()            bfin_read16(CAN1_MB19_LENGTH)
+#define bfin_write_CAN1_MB19_LENGTH(val)        bfin_write16(CAN1_MB19_LENGTH, val)
+#define bfin_read_CAN1_MB19_TIMESTAMP()         bfin_read16(CAN1_MB19_TIMESTAMP)
+#define bfin_write_CAN1_MB19_TIMESTAMP(val)     bfin_write16(CAN1_MB19_TIMESTAMP, val)
+#define bfin_read_CAN1_MB19_ID0()               bfin_read16(CAN1_MB19_ID0)
+#define bfin_write_CAN1_MB19_ID0(val)           bfin_write16(CAN1_MB19_ID0, val)
+#define bfin_read_CAN1_MB19_ID1()               bfin_read16(CAN1_MB19_ID1)
+#define bfin_write_CAN1_MB19_ID1(val)           bfin_write16(CAN1_MB19_ID1, val)
+#define bfin_read_CAN1_MB20_DATA0()             bfin_read16(CAN1_MB20_DATA0)
+#define bfin_write_CAN1_MB20_DATA0(val)         bfin_write16(CAN1_MB20_DATA0, val)
+#define bfin_read_CAN1_MB20_DATA1()             bfin_read16(CAN1_MB20_DATA1)
+#define bfin_write_CAN1_MB20_DATA1(val)         bfin_write16(CAN1_MB20_DATA1, val)
+#define bfin_read_CAN1_MB20_DATA2()             bfin_read16(CAN1_MB20_DATA2)
+#define bfin_write_CAN1_MB20_DATA2(val)         bfin_write16(CAN1_MB20_DATA2, val)
+#define bfin_read_CAN1_MB20_DATA3()             bfin_read16(CAN1_MB20_DATA3)
+#define bfin_write_CAN1_MB20_DATA3(val)         bfin_write16(CAN1_MB20_DATA3, val)
+#define bfin_read_CAN1_MB20_LENGTH()            bfin_read16(CAN1_MB20_LENGTH)
+#define bfin_write_CAN1_MB20_LENGTH(val)        bfin_write16(CAN1_MB20_LENGTH, val)
+#define bfin_read_CAN1_MB20_TIMESTAMP()         bfin_read16(CAN1_MB20_TIMESTAMP)
+#define bfin_write_CAN1_MB20_TIMESTAMP(val)     bfin_write16(CAN1_MB20_TIMESTAMP, val)
+#define bfin_read_CAN1_MB20_ID0()               bfin_read16(CAN1_MB20_ID0)
+#define bfin_write_CAN1_MB20_ID0(val)           bfin_write16(CAN1_MB20_ID0, val)
+#define bfin_read_CAN1_MB20_ID1()               bfin_read16(CAN1_MB20_ID1)
+#define bfin_write_CAN1_MB20_ID1(val)           bfin_write16(CAN1_MB20_ID1, val)
+#define bfin_read_CAN1_MB21_DATA0()             bfin_read16(CAN1_MB21_DATA0)
+#define bfin_write_CAN1_MB21_DATA0(val)         bfin_write16(CAN1_MB21_DATA0, val)
+#define bfin_read_CAN1_MB21_DATA1()             bfin_read16(CAN1_MB21_DATA1)
+#define bfin_write_CAN1_MB21_DATA1(val)         bfin_write16(CAN1_MB21_DATA1, val)
+#define bfin_read_CAN1_MB21_DATA2()             bfin_read16(CAN1_MB21_DATA2)
+#define bfin_write_CAN1_MB21_DATA2(val)         bfin_write16(CAN1_MB21_DATA2, val)
+#define bfin_read_CAN1_MB21_DATA3()             bfin_read16(CAN1_MB21_DATA3)
+#define bfin_write_CAN1_MB21_DATA3(val)         bfin_write16(CAN1_MB21_DATA3, val)
+#define bfin_read_CAN1_MB21_LENGTH()            bfin_read16(CAN1_MB21_LENGTH)
+#define bfin_write_CAN1_MB21_LENGTH(val)        bfin_write16(CAN1_MB21_LENGTH, val)
+#define bfin_read_CAN1_MB21_TIMESTAMP()         bfin_read16(CAN1_MB21_TIMESTAMP)
+#define bfin_write_CAN1_MB21_TIMESTAMP(val)     bfin_write16(CAN1_MB21_TIMESTAMP, val)
+#define bfin_read_CAN1_MB21_ID0()               bfin_read16(CAN1_MB21_ID0)
+#define bfin_write_CAN1_MB21_ID0(val)           bfin_write16(CAN1_MB21_ID0, val)
+#define bfin_read_CAN1_MB21_ID1()               bfin_read16(CAN1_MB21_ID1)
+#define bfin_write_CAN1_MB21_ID1(val)           bfin_write16(CAN1_MB21_ID1, val)
+#define bfin_read_CAN1_MB22_DATA0()             bfin_read16(CAN1_MB22_DATA0)
+#define bfin_write_CAN1_MB22_DATA0(val)         bfin_write16(CAN1_MB22_DATA0, val)
+#define bfin_read_CAN1_MB22_DATA1()             bfin_read16(CAN1_MB22_DATA1)
+#define bfin_write_CAN1_MB22_DATA1(val)         bfin_write16(CAN1_MB22_DATA1, val)
+#define bfin_read_CAN1_MB22_DATA2()             bfin_read16(CAN1_MB22_DATA2)
+#define bfin_write_CAN1_MB22_DATA2(val)         bfin_write16(CAN1_MB22_DATA2, val)
+#define bfin_read_CAN1_MB22_DATA3()             bfin_read16(CAN1_MB22_DATA3)
+#define bfin_write_CAN1_MB22_DATA3(val)         bfin_write16(CAN1_MB22_DATA3, val)
+#define bfin_read_CAN1_MB22_LENGTH()            bfin_read16(CAN1_MB22_LENGTH)
+#define bfin_write_CAN1_MB22_LENGTH(val)        bfin_write16(CAN1_MB22_LENGTH, val)
+#define bfin_read_CAN1_MB22_TIMESTAMP()         bfin_read16(CAN1_MB22_TIMESTAMP)
+#define bfin_write_CAN1_MB22_TIMESTAMP(val)     bfin_write16(CAN1_MB22_TIMESTAMP, val)
+#define bfin_read_CAN1_MB22_ID0()               bfin_read16(CAN1_MB22_ID0)
+#define bfin_write_CAN1_MB22_ID0(val)           bfin_write16(CAN1_MB22_ID0, val)
+#define bfin_read_CAN1_MB22_ID1()               bfin_read16(CAN1_MB22_ID1)
+#define bfin_write_CAN1_MB22_ID1(val)           bfin_write16(CAN1_MB22_ID1, val)
+#define bfin_read_CAN1_MB23_DATA0()             bfin_read16(CAN1_MB23_DATA0)
+#define bfin_write_CAN1_MB23_DATA0(val)         bfin_write16(CAN1_MB23_DATA0, val)
+#define bfin_read_CAN1_MB23_DATA1()             bfin_read16(CAN1_MB23_DATA1)
+#define bfin_write_CAN1_MB23_DATA1(val)         bfin_write16(CAN1_MB23_DATA1, val)
+#define bfin_read_CAN1_MB23_DATA2()             bfin_read16(CAN1_MB23_DATA2)
+#define bfin_write_CAN1_MB23_DATA2(val)         bfin_write16(CAN1_MB23_DATA2, val)
+#define bfin_read_CAN1_MB23_DATA3()             bfin_read16(CAN1_MB23_DATA3)
+#define bfin_write_CAN1_MB23_DATA3(val)         bfin_write16(CAN1_MB23_DATA3, val)
+#define bfin_read_CAN1_MB23_LENGTH()            bfin_read16(CAN1_MB23_LENGTH)
+#define bfin_write_CAN1_MB23_LENGTH(val)        bfin_write16(CAN1_MB23_LENGTH, val)
+#define bfin_read_CAN1_MB23_TIMESTAMP()         bfin_read16(CAN1_MB23_TIMESTAMP)
+#define bfin_write_CAN1_MB23_TIMESTAMP(val)     bfin_write16(CAN1_MB23_TIMESTAMP, val)
+#define bfin_read_CAN1_MB23_ID0()               bfin_read16(CAN1_MB23_ID0)
+#define bfin_write_CAN1_MB23_ID0(val)           bfin_write16(CAN1_MB23_ID0, val)
+#define bfin_read_CAN1_MB23_ID1()               bfin_read16(CAN1_MB23_ID1)
+#define bfin_write_CAN1_MB23_ID1(val)           bfin_write16(CAN1_MB23_ID1, val)
+#define bfin_read_CAN1_MB24_DATA0()             bfin_read16(CAN1_MB24_DATA0)
+#define bfin_write_CAN1_MB24_DATA0(val)         bfin_write16(CAN1_MB24_DATA0, val)
+#define bfin_read_CAN1_MB24_DATA1()             bfin_read16(CAN1_MB24_DATA1)
+#define bfin_write_CAN1_MB24_DATA1(val)         bfin_write16(CAN1_MB24_DATA1, val)
+#define bfin_read_CAN1_MB24_DATA2()             bfin_read16(CAN1_MB24_DATA2)
+#define bfin_write_CAN1_MB24_DATA2(val)         bfin_write16(CAN1_MB24_DATA2, val)
+#define bfin_read_CAN1_MB24_DATA3()             bfin_read16(CAN1_MB24_DATA3)
+#define bfin_write_CAN1_MB24_DATA3(val)         bfin_write16(CAN1_MB24_DATA3, val)
+#define bfin_read_CAN1_MB24_LENGTH()            bfin_read16(CAN1_MB24_LENGTH)
+#define bfin_write_CAN1_MB24_LENGTH(val)        bfin_write16(CAN1_MB24_LENGTH, val)
+#define bfin_read_CAN1_MB24_TIMESTAMP()         bfin_read16(CAN1_MB24_TIMESTAMP)
+#define bfin_write_CAN1_MB24_TIMESTAMP(val)     bfin_write16(CAN1_MB24_TIMESTAMP, val)
+#define bfin_read_CAN1_MB24_ID0()               bfin_read16(CAN1_MB24_ID0)
+#define bfin_write_CAN1_MB24_ID0(val)           bfin_write16(CAN1_MB24_ID0, val)
+#define bfin_read_CAN1_MB24_ID1()               bfin_read16(CAN1_MB24_ID1)
+#define bfin_write_CAN1_MB24_ID1(val)           bfin_write16(CAN1_MB24_ID1, val)
+#define bfin_read_CAN1_MB25_DATA0()             bfin_read16(CAN1_MB25_DATA0)
+#define bfin_write_CAN1_MB25_DATA0(val)         bfin_write16(CAN1_MB25_DATA0, val)
+#define bfin_read_CAN1_MB25_DATA1()             bfin_read16(CAN1_MB25_DATA1)
+#define bfin_write_CAN1_MB25_DATA1(val)         bfin_write16(CAN1_MB25_DATA1, val)
+#define bfin_read_CAN1_MB25_DATA2()             bfin_read16(CAN1_MB25_DATA2)
+#define bfin_write_CAN1_MB25_DATA2(val)         bfin_write16(CAN1_MB25_DATA2, val)
+#define bfin_read_CAN1_MB25_DATA3()             bfin_read16(CAN1_MB25_DATA3)
+#define bfin_write_CAN1_MB25_DATA3(val)         bfin_write16(CAN1_MB25_DATA3, val)
+#define bfin_read_CAN1_MB25_LENGTH()            bfin_read16(CAN1_MB25_LENGTH)
+#define bfin_write_CAN1_MB25_LENGTH(val)        bfin_write16(CAN1_MB25_LENGTH, val)
+#define bfin_read_CAN1_MB25_TIMESTAMP()         bfin_read16(CAN1_MB25_TIMESTAMP)
+#define bfin_write_CAN1_MB25_TIMESTAMP(val)     bfin_write16(CAN1_MB25_TIMESTAMP, val)
+#define bfin_read_CAN1_MB25_ID0()               bfin_read16(CAN1_MB25_ID0)
+#define bfin_write_CAN1_MB25_ID0(val)           bfin_write16(CAN1_MB25_ID0, val)
+#define bfin_read_CAN1_MB25_ID1()               bfin_read16(CAN1_MB25_ID1)
+#define bfin_write_CAN1_MB25_ID1(val)           bfin_write16(CAN1_MB25_ID1, val)
+#define bfin_read_CAN1_MB26_DATA0()             bfin_read16(CAN1_MB26_DATA0)
+#define bfin_write_CAN1_MB26_DATA0(val)         bfin_write16(CAN1_MB26_DATA0, val)
+#define bfin_read_CAN1_MB26_DATA1()             bfin_read16(CAN1_MB26_DATA1)
+#define bfin_write_CAN1_MB26_DATA1(val)         bfin_write16(CAN1_MB26_DATA1, val)
+#define bfin_read_CAN1_MB26_DATA2()             bfin_read16(CAN1_MB26_DATA2)
+#define bfin_write_CAN1_MB26_DATA2(val)         bfin_write16(CAN1_MB26_DATA2, val)
+#define bfin_read_CAN1_MB26_DATA3()             bfin_read16(CAN1_MB26_DATA3)
+#define bfin_write_CAN1_MB26_DATA3(val)         bfin_write16(CAN1_MB26_DATA3, val)
+#define bfin_read_CAN1_MB26_LENGTH()            bfin_read16(CAN1_MB26_LENGTH)
+#define bfin_write_CAN1_MB26_LENGTH(val)        bfin_write16(CAN1_MB26_LENGTH, val)
+#define bfin_read_CAN1_MB26_TIMESTAMP()         bfin_read16(CAN1_MB26_TIMESTAMP)
+#define bfin_write_CAN1_MB26_TIMESTAMP(val)     bfin_write16(CAN1_MB26_TIMESTAMP, val)
+#define bfin_read_CAN1_MB26_ID0()               bfin_read16(CAN1_MB26_ID0)
+#define bfin_write_CAN1_MB26_ID0(val)           bfin_write16(CAN1_MB26_ID0, val)
+#define bfin_read_CAN1_MB26_ID1()               bfin_read16(CAN1_MB26_ID1)
+#define bfin_write_CAN1_MB26_ID1(val)           bfin_write16(CAN1_MB26_ID1, val)
+#define bfin_read_CAN1_MB27_DATA0()             bfin_read16(CAN1_MB27_DATA0)
+#define bfin_write_CAN1_MB27_DATA0(val)         bfin_write16(CAN1_MB27_DATA0, val)
+#define bfin_read_CAN1_MB27_DATA1()             bfin_read16(CAN1_MB27_DATA1)
+#define bfin_write_CAN1_MB27_DATA1(val)         bfin_write16(CAN1_MB27_DATA1, val)
+#define bfin_read_CAN1_MB27_DATA2()             bfin_read16(CAN1_MB27_DATA2)
+#define bfin_write_CAN1_MB27_DATA2(val)         bfin_write16(CAN1_MB27_DATA2, val)
+#define bfin_read_CAN1_MB27_DATA3()             bfin_read16(CAN1_MB27_DATA3)
+#define bfin_write_CAN1_MB27_DATA3(val)         bfin_write16(CAN1_MB27_DATA3, val)
+#define bfin_read_CAN1_MB27_LENGTH()            bfin_read16(CAN1_MB27_LENGTH)
+#define bfin_write_CAN1_MB27_LENGTH(val)        bfin_write16(CAN1_MB27_LENGTH, val)
+#define bfin_read_CAN1_MB27_TIMESTAMP()         bfin_read16(CAN1_MB27_TIMESTAMP)
+#define bfin_write_CAN1_MB27_TIMESTAMP(val)     bfin_write16(CAN1_MB27_TIMESTAMP, val)
+#define bfin_read_CAN1_MB27_ID0()               bfin_read16(CAN1_MB27_ID0)
+#define bfin_write_CAN1_MB27_ID0(val)           bfin_write16(CAN1_MB27_ID0, val)
+#define bfin_read_CAN1_MB27_ID1()               bfin_read16(CAN1_MB27_ID1)
+#define bfin_write_CAN1_MB27_ID1(val)           bfin_write16(CAN1_MB27_ID1, val)
+#define bfin_read_CAN1_MB28_DATA0()             bfin_read16(CAN1_MB28_DATA0)
+#define bfin_write_CAN1_MB28_DATA0(val)         bfin_write16(CAN1_MB28_DATA0, val)
+#define bfin_read_CAN1_MB28_DATA1()             bfin_read16(CAN1_MB28_DATA1)
+#define bfin_write_CAN1_MB28_DATA1(val)         bfin_write16(CAN1_MB28_DATA1, val)
+#define bfin_read_CAN1_MB28_DATA2()             bfin_read16(CAN1_MB28_DATA2)
+#define bfin_write_CAN1_MB28_DATA2(val)         bfin_write16(CAN1_MB28_DATA2, val)
+#define bfin_read_CAN1_MB28_DATA3()             bfin_read16(CAN1_MB28_DATA3)
+#define bfin_write_CAN1_MB28_DATA3(val)         bfin_write16(CAN1_MB28_DATA3, val)
+#define bfin_read_CAN1_MB28_LENGTH()            bfin_read16(CAN1_MB28_LENGTH)
+#define bfin_write_CAN1_MB28_LENGTH(val)        bfin_write16(CAN1_MB28_LENGTH, val)
+#define bfin_read_CAN1_MB28_TIMESTAMP()         bfin_read16(CAN1_MB28_TIMESTAMP)
+#define bfin_write_CAN1_MB28_TIMESTAMP(val)     bfin_write16(CAN1_MB28_TIMESTAMP, val)
+#define bfin_read_CAN1_MB28_ID0()               bfin_read16(CAN1_MB28_ID0)
+#define bfin_write_CAN1_MB28_ID0(val)           bfin_write16(CAN1_MB28_ID0, val)
+#define bfin_read_CAN1_MB28_ID1()               bfin_read16(CAN1_MB28_ID1)
+#define bfin_write_CAN1_MB28_ID1(val)           bfin_write16(CAN1_MB28_ID1, val)
+#define bfin_read_CAN1_MB29_DATA0()             bfin_read16(CAN1_MB29_DATA0)
+#define bfin_write_CAN1_MB29_DATA0(val)         bfin_write16(CAN1_MB29_DATA0, val)
+#define bfin_read_CAN1_MB29_DATA1()             bfin_read16(CAN1_MB29_DATA1)
+#define bfin_write_CAN1_MB29_DATA1(val)         bfin_write16(CAN1_MB29_DATA1, val)
+#define bfin_read_CAN1_MB29_DATA2()             bfin_read16(CAN1_MB29_DATA2)
+#define bfin_write_CAN1_MB29_DATA2(val)         bfin_write16(CAN1_MB29_DATA2, val)
+#define bfin_read_CAN1_MB29_DATA3()             bfin_read16(CAN1_MB29_DATA3)
+#define bfin_write_CAN1_MB29_DATA3(val)         bfin_write16(CAN1_MB29_DATA3, val)
+#define bfin_read_CAN1_MB29_LENGTH()            bfin_read16(CAN1_MB29_LENGTH)
+#define bfin_write_CAN1_MB29_LENGTH(val)        bfin_write16(CAN1_MB29_LENGTH, val)
+#define bfin_read_CAN1_MB29_TIMESTAMP()         bfin_read16(CAN1_MB29_TIMESTAMP)
+#define bfin_write_CAN1_MB29_TIMESTAMP(val)     bfin_write16(CAN1_MB29_TIMESTAMP, val)
+#define bfin_read_CAN1_MB29_ID0()               bfin_read16(CAN1_MB29_ID0)
+#define bfin_write_CAN1_MB29_ID0(val)           bfin_write16(CAN1_MB29_ID0, val)
+#define bfin_read_CAN1_MB29_ID1()               bfin_read16(CAN1_MB29_ID1)
+#define bfin_write_CAN1_MB29_ID1(val)           bfin_write16(CAN1_MB29_ID1, val)
+#define bfin_read_CAN1_MB30_DATA0()             bfin_read16(CAN1_MB30_DATA0)
+#define bfin_write_CAN1_MB30_DATA0(val)         bfin_write16(CAN1_MB30_DATA0, val)
+#define bfin_read_CAN1_MB30_DATA1()             bfin_read16(CAN1_MB30_DATA1)
+#define bfin_write_CAN1_MB30_DATA1(val)         bfin_write16(CAN1_MB30_DATA1, val)
+#define bfin_read_CAN1_MB30_DATA2()             bfin_read16(CAN1_MB30_DATA2)
+#define bfin_write_CAN1_MB30_DATA2(val)         bfin_write16(CAN1_MB30_DATA2, val)
+#define bfin_read_CAN1_MB30_DATA3()             bfin_read16(CAN1_MB30_DATA3)
+#define bfin_write_CAN1_MB30_DATA3(val)         bfin_write16(CAN1_MB30_DATA3, val)
+#define bfin_read_CAN1_MB30_LENGTH()            bfin_read16(CAN1_MB30_LENGTH)
+#define bfin_write_CAN1_MB30_LENGTH(val)        bfin_write16(CAN1_MB30_LENGTH, val)
+#define bfin_read_CAN1_MB30_TIMESTAMP()         bfin_read16(CAN1_MB30_TIMESTAMP)
+#define bfin_write_CAN1_MB30_TIMESTAMP(val)     bfin_write16(CAN1_MB30_TIMESTAMP, val)
+#define bfin_read_CAN1_MB30_ID0()               bfin_read16(CAN1_MB30_ID0)
+#define bfin_write_CAN1_MB30_ID0(val)           bfin_write16(CAN1_MB30_ID0, val)
+#define bfin_read_CAN1_MB30_ID1()               bfin_read16(CAN1_MB30_ID1)
+#define bfin_write_CAN1_MB30_ID1(val)           bfin_write16(CAN1_MB30_ID1, val)
+#define bfin_read_CAN1_MB31_DATA0()             bfin_read16(CAN1_MB31_DATA0)
+#define bfin_write_CAN1_MB31_DATA0(val)         bfin_write16(CAN1_MB31_DATA0, val)
+#define bfin_read_CAN1_MB31_DATA1()             bfin_read16(CAN1_MB31_DATA1)
+#define bfin_write_CAN1_MB31_DATA1(val)         bfin_write16(CAN1_MB31_DATA1, val)
+#define bfin_read_CAN1_MB31_DATA2()             bfin_read16(CAN1_MB31_DATA2)
+#define bfin_write_CAN1_MB31_DATA2(val)         bfin_write16(CAN1_MB31_DATA2, val)
+#define bfin_read_CAN1_MB31_DATA3()             bfin_read16(CAN1_MB31_DATA3)
+#define bfin_write_CAN1_MB31_DATA3(val)         bfin_write16(CAN1_MB31_DATA3, val)
+#define bfin_read_CAN1_MB31_LENGTH()            bfin_read16(CAN1_MB31_LENGTH)
+#define bfin_write_CAN1_MB31_LENGTH(val)        bfin_write16(CAN1_MB31_LENGTH, val)
+#define bfin_read_CAN1_MB31_TIMESTAMP()         bfin_read16(CAN1_MB31_TIMESTAMP)
+#define bfin_write_CAN1_MB31_TIMESTAMP(val)     bfin_write16(CAN1_MB31_TIMESTAMP, val)
+#define bfin_read_CAN1_MB31_ID0()               bfin_read16(CAN1_MB31_ID0)
+#define bfin_write_CAN1_MB31_ID0(val)           bfin_write16(CAN1_MB31_ID0, val)
+#define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
+#define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
+
+/* ATAPI Registers */
+
+#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
+#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
+#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
+#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
+#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
+#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
+#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
+#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
+#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
+#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
+#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
+#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
+#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
+#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
+#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
+
+/* SDH Registers */
+
+#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
+#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
+#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
+#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
+#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
+#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
+#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
+#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
+#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
+#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
+#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
+#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
+#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
+#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
+#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
+#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
+#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
+#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
+#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
+#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
+#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
+#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
+#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
+#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
+#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
+#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
+#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
+#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
+#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
+#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
+#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
+
+/* HOST Port Registers */
+
+#define bfin_read_HOST_CONTROL()        bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)    bfin_write16(HOST_CONTROL, val)
+#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)     bfin_write16(HOST_STATUS, val)
+#define bfin_read_HOST_TIMEOUT()        bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)    bfin_write16(HOST_TIMEOUT, val)
+
+/* USB Control Registers */
+
+#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
+#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
+#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
+#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
+#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
+#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
+#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
+#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
+#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
+#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
+#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
+#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
+#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
+
+/* USB Packet Control Registers */
+
+#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
+#define bfin_read_USB_CSR0()            bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)        bfin_write16(USB_CSR0, val)
+#define bfin_read_USB_TXCSR()           bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)       bfin_write16(USB_TXCSR, val)
+#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
+#define bfin_read_USB_RXCSR()           bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)       bfin_write16(USB_RXCSR, val)
+#define bfin_read_USB_COUNT0()          bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)      bfin_write16(USB_COUNT0, val)
+#define bfin_read_USB_RXCOUNT()         bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)     bfin_write16(USB_RXCOUNT, val)
+#define bfin_read_USB_TXTYPE()          bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)      bfin_write16(USB_TXTYPE, val)
+#define bfin_read_USB_NAKLIMIT0()       bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)   bfin_write16(USB_NAKLIMIT0, val)
+#define bfin_read_USB_TXINTERVAL()      bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val)  bfin_write16(USB_TXINTERVAL, val)
+#define bfin_read_USB_RXTYPE()          bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)      bfin_write16(USB_RXTYPE, val)
+#define bfin_read_USB_RXINTERVAL()      bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val)  bfin_write16(USB_RXINTERVAL, val)
+#define bfin_read_USB_TXCOUNT()         bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)     bfin_write16(USB_TXCOUNT, val)
+
+/* USB Endbfin_read_()oint FIFO Registers */
+
+#define bfin_read_USB_EP0_FIFO()        bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)    bfin_write16(USB_EP0_FIFO, val)
+#define bfin_read_USB_EP1_FIFO()        bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)    bfin_write16(USB_EP1_FIFO, val)
+#define bfin_read_USB_EP2_FIFO()        bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)    bfin_write16(USB_EP2_FIFO, val)
+#define bfin_read_USB_EP3_FIFO()        bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)    bfin_write16(USB_EP3_FIFO, val)
+#define bfin_read_USB_EP4_FIFO()        bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)    bfin_write16(USB_EP4_FIFO, val)
+#define bfin_read_USB_EP5_FIFO()        bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)    bfin_write16(USB_EP5_FIFO, val)
+#define bfin_read_USB_EP6_FIFO()        bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)    bfin_write16(USB_EP6_FIFO, val)
+#define bfin_read_USB_EP7_FIFO()        bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)    bfin_write16(USB_EP7_FIFO, val)
+
+/* USB OTG Control Registers */
+
+#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
+#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
+
+/* USB Phy Control Registers */
+
+#define bfin_read_USB_LINKINFO()        bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)    bfin_write16(USB_LINKINFO, val)
+#define bfin_read_USB_VPLEN()           bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)       bfin_write16(USB_VPLEN, val)
+#define bfin_read_USB_HS_EOF1()         bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)     bfin_write16(USB_HS_EOF1, val)
+#define bfin_read_USB_FS_EOF1()         bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)     bfin_write16(USB_FS_EOF1, val)
+#define bfin_read_USB_LS_EOF1()         bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)     bfin_write16(USB_LS_EOF1, val)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
+#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
+#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
+#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
+
+/* USB Endbfin_read_()oint 0 Control Registers */
+
+#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
+#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
+#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 1 Control Registers */
+
+#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
+#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
+#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 2 Control Registers */
+
+#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
+#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
+#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 3 Control Registers */
+
+#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
+#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
+#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 4 Control Registers */
+
+#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
+#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
+#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 5 Control Registers */
+
+#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
+#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
+#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 6 Control Registers */
+
+#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
+#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
+#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 7 Control Registers */
+
+#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
+#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
+#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
+
+/* USB Channel 0 Config Registers */
+
+#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
+#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
+#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
+#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
+#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
+#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
+#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
+#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
+#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
+#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
+
+/* USB Channel 1 Config Registers */
+
+#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
+#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
+#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
+#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
+#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
+#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
+#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
+#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
+#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
+#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
+
+/* USB Channel 2 Config Registers */
+
+#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
+#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
+#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
+#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
+#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
+#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
+#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
+#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
+#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
+#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
+
+/* USB Channel 3 Config Registers */
+
+#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
+#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
+#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
+#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
+#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
+#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
+#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
+#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
+#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
+#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
+
+/* USB Channel 4 Config Registers */
+
+#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
+#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
+#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
+#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
+#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
+#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
+#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
+#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
+#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
+#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
+
+/* USB Channel 5 Config Registers */
+
+#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
+#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
+#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
+#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
+#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
+#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
+#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
+#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
+#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
+#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
+
+/* USB Channel 6 Config Registers */
+
+#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
+#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
+#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
+#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
+#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
+#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
+#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
+#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
+#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
+#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
+
+/* USB Channel 7 Config Registers */
+
+#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
+#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
+#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
+#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
+#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
+#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
+#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
+#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
+#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
+#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
+
+/* Keybfin_read_()ad Registers */
+
+#define bfin_read_KPAD_CTL()            bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)        bfin_write16(KPAD_CTL, val)
+#define bfin_read_KPAD_PRESCALE()       bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)   bfin_write16(KPAD_PRESCALE, val)
+#define bfin_read_KPAD_MSEL()           bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)       bfin_write16(KPAD_MSEL, val)
+#define bfin_read_KPAD_ROWCOL()         bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)     bfin_write16(KPAD_ROWCOL, val)
+#define bfin_read_KPAD_STAT()           bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)       bfin_write16(KPAD_STAT, val)
+#define bfin_read_KPAD_SOFTEVAL()       bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)   bfin_write16(KPAD_SOFTEVAL, val)
+
+/* Pixel Combfin_read_()ositor (PIXC) Registers */
+
+#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
+#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
+#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
+#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
+#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
+#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
+#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
+#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
+#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
+#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
+#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
+#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
+#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
+#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
+#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
+#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
+#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
+#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
+#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
+
+/* Handshake MDMA 0 Registers */
+
+#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
+
+/* Handshake MDMA 1 Registers */
+
+#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
+
+#endif /* _CDEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h
new file mode 100644
index 000000000000..2ab5b7c00820
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/cdefBF549.h
@@ -0,0 +1,1896 @@
+/*
+ * File:         include/asm-blackfin/mach-bf549/cdefBF549.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF549_H
+#define _CDEF_BF549_H
+
+/* include all Core registers and bit definitions */
+#include "defBF549.h"
+
+/* include core sbfin_read_()ecific register pointer definitions */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
+
+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
+#include "cdefBF54x_base.h"
+
+/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
+
+/* Timer Registers */
+
+#define bfin_read_TIMER8_CONFIG()               bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)           bfin_write16(TIMER8_CONFIG, val)
+#define bfin_read_TIMER8_COUNTER()              bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val)          bfin_write32(TIMER8_COUNTER, val)
+#define bfin_read_TIMER8_PERIOD()               bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)           bfin_write32(TIMER8_PERIOD, val)
+#define bfin_read_TIMER8_WIDTH()                bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)            bfin_write32(TIMER8_WIDTH, val)
+#define bfin_read_TIMER9_CONFIG()               bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)           bfin_write16(TIMER9_CONFIG, val)
+#define bfin_read_TIMER9_COUNTER()              bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val)          bfin_write32(TIMER9_COUNTER, val)
+#define bfin_read_TIMER9_PERIOD()               bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)           bfin_write32(TIMER9_PERIOD, val)
+#define bfin_read_TIMER9_WIDTH()                bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)            bfin_write32(TIMER9_WIDTH, val)
+#define bfin_read_TIMER10_CONFIG()              bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val)          bfin_write16(TIMER10_CONFIG, val)
+#define bfin_read_TIMER10_COUNTER()             bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val)         bfin_write32(TIMER10_COUNTER, val)
+#define bfin_read_TIMER10_PERIOD()              bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val)          bfin_write32(TIMER10_PERIOD, val)
+#define bfin_read_TIMER10_WIDTH()               bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)           bfin_write32(TIMER10_WIDTH, val)
+
+/* Timer Groubfin_read_() of 3 */
+
+#define bfin_read_TIMER_ENABLE1()               bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)           bfin_write16(TIMER_ENABLE1, val)
+#define bfin_read_TIMER_DISABLE1()              bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val)          bfin_write16(TIMER_DISABLE1, val)
+#define bfin_read_TIMER_STATUS1()               bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)           bfin_write32(TIMER_STATUS1, val)
+
+/* SPORT0 Registers */
+
+#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
+
+/* EPPI0 Registers */
+
+#define bfin_read_EPPI0_STATUS()                bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)            bfin_write16(EPPI0_STATUS, val)
+#define bfin_read_EPPI0_HCOUNT()                bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)            bfin_write16(EPPI0_HCOUNT, val)
+#define bfin_read_EPPI0_HDELAY()                bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)            bfin_write16(EPPI0_HDELAY, val)
+#define bfin_read_EPPI0_VCOUNT()                bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)            bfin_write16(EPPI0_VCOUNT, val)
+#define bfin_read_EPPI0_VDELAY()                bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)            bfin_write16(EPPI0_VDELAY, val)
+#define bfin_read_EPPI0_FRAME()                 bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)             bfin_write16(EPPI0_FRAME, val)
+#define bfin_read_EPPI0_LINE()                  bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)              bfin_write16(EPPI0_LINE, val)
+#define bfin_read_EPPI0_CLKDIV()                bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)            bfin_write16(EPPI0_CLKDIV, val)
+#define bfin_read_EPPI0_CONTROL()               bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)           bfin_write32(EPPI0_CONTROL, val)
+#define bfin_read_EPPI0_FS1W_HBL()              bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val)          bfin_write32(EPPI0_FS1W_HBL, val)
+#define bfin_read_EPPI0_FS1P_AVPL()             bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val)         bfin_write32(EPPI0_FS1P_AVPL, val)
+#define bfin_read_EPPI0_FS2W_LVB()              bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val)          bfin_write32(EPPI0_FS2W_LVB, val)
+#define bfin_read_EPPI0_FS2P_LAVF()             bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val)         bfin_write32(EPPI0_FS2P_LAVF, val)
+#define bfin_read_EPPI0_CLIP()                  bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)              bfin_write32(EPPI0_CLIP, val)
+
+/* UART2 Registers */
+
+#define bfin_read_UART2_DLL()                   bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val)               bfin_write16(UART2_DLL, val)
+#define bfin_read_UART2_DLH()                   bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val)               bfin_write16(UART2_DLH, val)
+#define bfin_read_UART2_GCTL()                  bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val)              bfin_write16(UART2_GCTL, val)
+#define bfin_read_UART2_LCR()                   bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val)               bfin_write16(UART2_LCR, val)
+#define bfin_read_UART2_MCR()                   bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val)               bfin_write16(UART2_MCR, val)
+#define bfin_read_UART2_LSR()                   bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val)               bfin_write16(UART2_LSR, val)
+#define bfin_read_UART2_MSR()                   bfin_read16(UART2_MSR)
+#define bfin_write_UART2_MSR(val)               bfin_write16(UART2_MSR, val)
+#define bfin_read_UART2_SCR()                   bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val)               bfin_write16(UART2_SCR, val)
+#define bfin_read_UART2_IER_SET()               bfin_read16(UART2_IER_SET)
+#define bfin_write_UART2_IER_SET(val)           bfin_write16(UART2_IER_SET, val)
+#define bfin_read_UART2_IER_CLEAR()             bfin_read16(UART2_IER_CLEAR)
+#define bfin_write_UART2_IER_CLEAR(val)         bfin_write16(UART2_IER_CLEAR, val)
+#define bfin_read_UART2_RBR()                   bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val)               bfin_write16(UART2_RBR, val)
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define bfin_read_TWI1_CLKDIV()                 bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)             bfin_write16(TWI1_CLKDIV, val)
+#define bfin_read_TWI1_CONTROL()                bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)            bfin_write16(TWI1_CONTROL, val)
+#define bfin_read_TWI1_SLAVE_CTRL()             bfin_read16(TWI1_SLAVE_CTRL)
+#define bfin_write_TWI1_SLAVE_CTRL(val)         bfin_write16(TWI1_SLAVE_CTRL, val)
+#define bfin_read_TWI1_SLAVE_STAT()             bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val)         bfin_write16(TWI1_SLAVE_STAT, val)
+#define bfin_read_TWI1_SLAVE_ADDR()             bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val)         bfin_write16(TWI1_SLAVE_ADDR, val)
+#define bfin_read_TWI1_MASTER_CTRL()            bfin_read16(TWI1_MASTER_CTRL)
+#define bfin_write_TWI1_MASTER_CTRL(val)        bfin_write16(TWI1_MASTER_CTRL, val)
+#define bfin_read_TWI1_MASTER_STAT()            bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val)        bfin_write16(TWI1_MASTER_STAT, val)
+#define bfin_read_TWI1_MASTER_ADDR()            bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val)        bfin_write16(TWI1_MASTER_ADDR, val)
+#define bfin_read_TWI1_INT_STAT()               bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)           bfin_write16(TWI1_INT_STAT, val)
+#define bfin_read_TWI1_INT_MASK()               bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)           bfin_write16(TWI1_INT_MASK, val)
+#define bfin_read_TWI1_FIFO_CTRL()              bfin_read16(TWI1_FIFO_CTRL)
+#define bfin_write_TWI1_FIFO_CTRL(val)          bfin_write16(TWI1_FIFO_CTRL, val)
+#define bfin_read_TWI1_FIFO_STAT()              bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val)          bfin_write16(TWI1_FIFO_STAT, val)
+#define bfin_read_TWI1_XMT_DATA8()              bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val)          bfin_write16(TWI1_XMT_DATA8, val)
+#define bfin_read_TWI1_XMT_DATA16()             bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val)         bfin_write16(TWI1_XMT_DATA16, val)
+#define bfin_read_TWI1_RCV_DATA8()              bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val)          bfin_write16(TWI1_RCV_DATA8, val)
+#define bfin_read_TWI1_RCV_DATA16()             bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val)         bfin_write16(TWI1_RCV_DATA16, val)
+
+/* SPI2 Registers */
+
+#define bfin_read_SPI2_CTL()            bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val)        bfin_write16(SPI2_CTL, val)
+#define bfin_read_SPI2_FLG()            bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val)        bfin_write16(SPI2_FLG, val)
+#define bfin_read_SPI2_STAT()           bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val)       bfin_write16(SPI2_STAT, val)
+#define bfin_read_SPI2_TDBR()           bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val)       bfin_write16(SPI2_TDBR, val)
+#define bfin_read_SPI2_RDBR()           bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val)       bfin_write16(SPI2_RDBR, val)
+#define bfin_read_SPI2_BAUD()           bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val)       bfin_write16(SPI2_BAUD, val)
+#define bfin_read_SPI2_SHADOW()         bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val)     bfin_write16(SPI2_SHADOW, val)
+
+/* MXVR Registers */
+
+#define bfin_read_MXVR_CONFIG()                 bfin_read16(MXVR_CONFIG)
+#define bfin_write_MXVR_CONFIG(val)             bfin_write16(MXVR_CONFIG, val)
+#define bfin_read_MXVR_STATE_0()                bfin_read32(MXVR_STATE_0)
+#define bfin_write_MXVR_STATE_0(val)            bfin_write32(MXVR_STATE_0, val)
+#define bfin_read_MXVR_STATE_1()                bfin_read32(MXVR_STATE_1)
+#define bfin_write_MXVR_STATE_1(val)            bfin_write32(MXVR_STATE_1, val)
+#define bfin_read_MXVR_INT_STAT_0()             bfin_read32(MXVR_INT_STAT_0)
+#define bfin_write_MXVR_INT_STAT_0(val)         bfin_write32(MXVR_INT_STAT_0, val)
+#define bfin_read_MXVR_INT_STAT_1()             bfin_read32(MXVR_INT_STAT_1)
+#define bfin_write_MXVR_INT_STAT_1(val)         bfin_write32(MXVR_INT_STAT_1, val)
+#define bfin_read_MXVR_INT_EN_0()               bfin_read32(MXVR_INT_EN_0)
+#define bfin_write_MXVR_INT_EN_0(val)           bfin_write32(MXVR_INT_EN_0, val)
+#define bfin_read_MXVR_INT_EN_1()               bfin_read32(MXVR_INT_EN_1)
+#define bfin_write_MXVR_INT_EN_1(val)           bfin_write32(MXVR_INT_EN_1, val)
+#define bfin_read_MXVR_POSITION()               bfin_read16(MXVR_POSITION)
+#define bfin_write_MXVR_POSITION(val)           bfin_write16(MXVR_POSITION, val)
+#define bfin_read_MXVR_MAX_POSITION()           bfin_read16(MXVR_MAX_POSITION)
+#define bfin_write_MXVR_MAX_POSITION(val)       bfin_write16(MXVR_MAX_POSITION, val)
+#define bfin_read_MXVR_DELAY()                  bfin_read16(MXVR_DELAY)
+#define bfin_write_MXVR_DELAY(val)              bfin_write16(MXVR_DELAY, val)
+#define bfin_read_MXVR_MAX_DELAY()              bfin_read16(MXVR_MAX_DELAY)
+#define bfin_write_MXVR_MAX_DELAY(val)          bfin_write16(MXVR_MAX_DELAY, val)
+#define bfin_read_MXVR_LADDR()                  bfin_read32(MXVR_LADDR)
+#define bfin_write_MXVR_LADDR(val)              bfin_write32(MXVR_LADDR, val)
+#define bfin_read_MXVR_GADDR()                  bfin_read16(MXVR_GADDR)
+#define bfin_write_MXVR_GADDR(val)              bfin_write16(MXVR_GADDR, val)
+#define bfin_read_MXVR_AADDR()                  bfin_read32(MXVR_AADDR)
+#define bfin_write_MXVR_AADDR(val)              bfin_write32(MXVR_AADDR, val)
+
+/* MXVR Allocation Table Registers */
+
+#define bfin_read_MXVR_ALLOC_0()                bfin_read32(MXVR_ALLOC_0)
+#define bfin_write_MXVR_ALLOC_0(val)            bfin_write32(MXVR_ALLOC_0, val)
+#define bfin_read_MXVR_ALLOC_1()                bfin_read32(MXVR_ALLOC_1)
+#define bfin_write_MXVR_ALLOC_1(val)            bfin_write32(MXVR_ALLOC_1, val)
+#define bfin_read_MXVR_ALLOC_2()                bfin_read32(MXVR_ALLOC_2)
+#define bfin_write_MXVR_ALLOC_2(val)            bfin_write32(MXVR_ALLOC_2, val)
+#define bfin_read_MXVR_ALLOC_3()                bfin_read32(MXVR_ALLOC_3)
+#define bfin_write_MXVR_ALLOC_3(val)            bfin_write32(MXVR_ALLOC_3, val)
+#define bfin_read_MXVR_ALLOC_4()                bfin_read32(MXVR_ALLOC_4)
+#define bfin_write_MXVR_ALLOC_4(val)            bfin_write32(MXVR_ALLOC_4, val)
+#define bfin_read_MXVR_ALLOC_5()                bfin_read32(MXVR_ALLOC_5)
+#define bfin_write_MXVR_ALLOC_5(val)            bfin_write32(MXVR_ALLOC_5, val)
+#define bfin_read_MXVR_ALLOC_6()                bfin_read32(MXVR_ALLOC_6)
+#define bfin_write_MXVR_ALLOC_6(val)            bfin_write32(MXVR_ALLOC_6, val)
+#define bfin_read_MXVR_ALLOC_7()                bfin_read32(MXVR_ALLOC_7)
+#define bfin_write_MXVR_ALLOC_7(val)            bfin_write32(MXVR_ALLOC_7, val)
+#define bfin_read_MXVR_ALLOC_8()                bfin_read32(MXVR_ALLOC_8)
+#define bfin_write_MXVR_ALLOC_8(val)            bfin_write32(MXVR_ALLOC_8, val)
+#define bfin_read_MXVR_ALLOC_9()                bfin_read32(MXVR_ALLOC_9)
+#define bfin_write_MXVR_ALLOC_9(val)            bfin_write32(MXVR_ALLOC_9, val)
+#define bfin_read_MXVR_ALLOC_10()               bfin_read32(MXVR_ALLOC_10)
+#define bfin_write_MXVR_ALLOC_10(val)           bfin_write32(MXVR_ALLOC_10, val)
+#define bfin_read_MXVR_ALLOC_11()               bfin_read32(MXVR_ALLOC_11)
+#define bfin_write_MXVR_ALLOC_11(val)           bfin_write32(MXVR_ALLOC_11, val)
+#define bfin_read_MXVR_ALLOC_12()               bfin_read32(MXVR_ALLOC_12)
+#define bfin_write_MXVR_ALLOC_12(val)           bfin_write32(MXVR_ALLOC_12, val)
+#define bfin_read_MXVR_ALLOC_13()               bfin_read32(MXVR_ALLOC_13)
+#define bfin_write_MXVR_ALLOC_13(val)           bfin_write32(MXVR_ALLOC_13, val)
+#define bfin_read_MXVR_ALLOC_14()               bfin_read32(MXVR_ALLOC_14)
+#define bfin_write_MXVR_ALLOC_14(val)           bfin_write32(MXVR_ALLOC_14, val)
+
+/* MXVR Channel Assign Registers */
+
+#define bfin_read_MXVR_SYNC_LCHAN_0()           bfin_read32(MXVR_SYNC_LCHAN_0)
+#define bfin_write_MXVR_SYNC_LCHAN_0(val)       bfin_write32(MXVR_SYNC_LCHAN_0, val)
+#define bfin_read_MXVR_SYNC_LCHAN_1()           bfin_read32(MXVR_SYNC_LCHAN_1)
+#define bfin_write_MXVR_SYNC_LCHAN_1(val)       bfin_write32(MXVR_SYNC_LCHAN_1, val)
+#define bfin_read_MXVR_SYNC_LCHAN_2()           bfin_read32(MXVR_SYNC_LCHAN_2)
+#define bfin_write_MXVR_SYNC_LCHAN_2(val)       bfin_write32(MXVR_SYNC_LCHAN_2, val)
+#define bfin_read_MXVR_SYNC_LCHAN_3()           bfin_read32(MXVR_SYNC_LCHAN_3)
+#define bfin_write_MXVR_SYNC_LCHAN_3(val)       bfin_write32(MXVR_SYNC_LCHAN_3, val)
+#define bfin_read_MXVR_SYNC_LCHAN_4()           bfin_read32(MXVR_SYNC_LCHAN_4)
+#define bfin_write_MXVR_SYNC_LCHAN_4(val)       bfin_write32(MXVR_SYNC_LCHAN_4, val)
+#define bfin_read_MXVR_SYNC_LCHAN_5()           bfin_read32(MXVR_SYNC_LCHAN_5)
+#define bfin_write_MXVR_SYNC_LCHAN_5(val)       bfin_write32(MXVR_SYNC_LCHAN_5, val)
+#define bfin_read_MXVR_SYNC_LCHAN_6()           bfin_read32(MXVR_SYNC_LCHAN_6)
+#define bfin_write_MXVR_SYNC_LCHAN_6(val)       bfin_write32(MXVR_SYNC_LCHAN_6, val)
+#define bfin_read_MXVR_SYNC_LCHAN_7()           bfin_read32(MXVR_SYNC_LCHAN_7)
+#define bfin_write_MXVR_SYNC_LCHAN_7(val)       bfin_write32(MXVR_SYNC_LCHAN_7, val)
+
+/* MXVR DMA0 Registers */
+
+#define bfin_read_MXVR_DMA0_CONFIG()            bfin_read32(MXVR_DMA0_CONFIG)
+#define bfin_write_MXVR_DMA0_CONFIG(val)        bfin_write32(MXVR_DMA0_CONFIG, val)
+#define bfin_read_MXVR_DMA0_START_ADDR()        bfin_read32(MXVR_DMA0_START_ADDR)
+#define bfin_write_MXVR_DMA0_START_ADDR(val)    bfin_write32(MXVR_DMA0_START_ADDR)
+#define bfin_read_MXVR_DMA0_COUNT()             bfin_read16(MXVR_DMA0_COUNT)
+#define bfin_write_MXVR_DMA0_COUNT(val)         bfin_write16(MXVR_DMA0_COUNT, val)
+#define bfin_read_MXVR_DMA0_CURR_ADDR()         bfin_read32(MXVR_DMA0_CURR_ADDR)
+#define bfin_write_MXVR_DMA0_CURR_ADDR(val)     bfin_write32(MXVR_DMA0_CURR_ADDR)
+#define bfin_read_MXVR_DMA0_CURR_COUNT()        bfin_read16(MXVR_DMA0_CURR_COUNT)
+#define bfin_write_MXVR_DMA0_CURR_COUNT(val)    bfin_write16(MXVR_DMA0_CURR_COUNT, val)
+
+/* MXVR DMA1 Registers */
+
+#define bfin_read_MXVR_DMA1_CONFIG()            bfin_read32(MXVR_DMA1_CONFIG)
+#define bfin_write_MXVR_DMA1_CONFIG(val)        bfin_write32(MXVR_DMA1_CONFIG, val)
+#define bfin_read_MXVR_DMA1_START_ADDR()        bfin_read32(MXVR_DMA1_START_ADDR)
+#define bfin_write_MXVR_DMA1_START_ADDR(val)    bfin_write32(MXVR_DMA1_START_ADDR)
+#define bfin_read_MXVR_DMA1_COUNT()             bfin_read16(MXVR_DMA1_COUNT)
+#define bfin_write_MXVR_DMA1_COUNT(val)         bfin_write16(MXVR_DMA1_COUNT, val)
+#define bfin_read_MXVR_DMA1_CURR_ADDR()         bfin_read32(MXVR_DMA1_CURR_ADDR)
+#define bfin_write_MXVR_DMA1_CURR_ADDR(val)     bfin_write32(MXVR_DMA1_CURR_ADDR)
+#define bfin_read_MXVR_DMA1_CURR_COUNT()        bfin_read16(MXVR_DMA1_CURR_COUNT)
+#define bfin_write_MXVR_DMA1_CURR_COUNT(val)    bfin_write16(MXVR_DMA1_CURR_COUNT, val)
+
+/* MXVR DMA2 Registers */
+
+#define bfin_read_MXVR_DMA2_CONFIG()            bfin_read32(MXVR_DMA2_CONFIG)
+#define bfin_write_MXVR_DMA2_CONFIG(val)        bfin_write32(MXVR_DMA2_CONFIG, val)
+#define bfin_read_MXVR_DMA2_START_ADDR()        bfin_read32(MXVR_DMA2_START_ADDR)
+#define bfin_write_MXVR_DMA2_START_ADDR(val)    bfin_write32(MXVR_DMA2_START_ADDR)
+#define bfin_read_MXVR_DMA2_COUNT()             bfin_read16(MXVR_DMA2_COUNT)
+#define bfin_write_MXVR_DMA2_COUNT(val)         bfin_write16(MXVR_DMA2_COUNT, val)
+#define bfin_read_MXVR_DMA2_CURR_ADDR()         bfin_read32(MXVR_DMA2_CURR_ADDR)
+#define bfin_write_MXVR_DMA2_CURR_ADDR(val)     bfin_write32(MXVR_DMA2_CURR_ADDR)
+#define bfin_read_MXVR_DMA2_CURR_COUNT()        bfin_read16(MXVR_DMA2_CURR_COUNT)
+#define bfin_write_MXVR_DMA2_CURR_COUNT(val)    bfin_write16(MXVR_DMA2_CURR_COUNT, val)
+
+/* MXVR DMA3 Registers */
+
+#define bfin_read_MXVR_DMA3_CONFIG()            bfin_read32(MXVR_DMA3_CONFIG)
+#define bfin_write_MXVR_DMA3_CONFIG(val)        bfin_write32(MXVR_DMA3_CONFIG, val)
+#define bfin_read_MXVR_DMA3_START_ADDR()        bfin_read32(MXVR_DMA3_START_ADDR)
+#define bfin_write_MXVR_DMA3_START_ADDR(val)    bfin_write32(MXVR_DMA3_START_ADDR)
+#define bfin_read_MXVR_DMA3_COUNT()             bfin_read16(MXVR_DMA3_COUNT)
+#define bfin_write_MXVR_DMA3_COUNT(val)         bfin_write16(MXVR_DMA3_COUNT, val)
+#define bfin_read_MXVR_DMA3_CURR_ADDR()         bfin_read32(MXVR_DMA3_CURR_ADDR)
+#define bfin_write_MXVR_DMA3_CURR_ADDR(val)     bfin_write32(MXVR_DMA3_CURR_ADDR)
+#define bfin_read_MXVR_DMA3_CURR_COUNT()        bfin_read16(MXVR_DMA3_CURR_COUNT)
+#define bfin_write_MXVR_DMA3_CURR_COUNT(val)    bfin_write16(MXVR_DMA3_CURR_COUNT, val)
+
+/* MXVR DMA4 Registers */
+
+#define bfin_read_MXVR_DMA4_CONFIG()            bfin_read32(MXVR_DMA4_CONFIG)
+#define bfin_write_MXVR_DMA4_CONFIG(val)        bfin_write32(MXVR_DMA4_CONFIG, val)
+#define bfin_read_MXVR_DMA4_START_ADDR()        bfin_read32(MXVR_DMA4_START_ADDR)
+#define bfin_write_MXVR_DMA4_START_ADDR(val)    bfin_write32(MXVR_DMA4_START_ADDR)
+#define bfin_read_MXVR_DMA4_COUNT()             bfin_read16(MXVR_DMA4_COUNT)
+#define bfin_write_MXVR_DMA4_COUNT(val)         bfin_write16(MXVR_DMA4_COUNT, val)
+#define bfin_read_MXVR_DMA4_CURR_ADDR()         bfin_read32(MXVR_DMA4_CURR_ADDR)
+#define bfin_write_MXVR_DMA4_CURR_ADDR(val)     bfin_write32(MXVR_DMA4_CURR_ADDR)
+#define bfin_read_MXVR_DMA4_CURR_COUNT()        bfin_read16(MXVR_DMA4_CURR_COUNT)
+#define bfin_write_MXVR_DMA4_CURR_COUNT(val)    bfin_write16(MXVR_DMA4_CURR_COUNT, val)
+
+/* MXVR DMA5 Registers */
+
+#define bfin_read_MXVR_DMA5_CONFIG()            bfin_read32(MXVR_DMA5_CONFIG)
+#define bfin_write_MXVR_DMA5_CONFIG(val)        bfin_write32(MXVR_DMA5_CONFIG, val)
+#define bfin_read_MXVR_DMA5_START_ADDR()        bfin_read32(MXVR_DMA5_START_ADDR)
+#define bfin_write_MXVR_DMA5_START_ADDR(val)    bfin_write32(MXVR_DMA5_START_ADDR)
+#define bfin_read_MXVR_DMA5_COUNT()             bfin_read16(MXVR_DMA5_COUNT)
+#define bfin_write_MXVR_DMA5_COUNT(val)         bfin_write16(MXVR_DMA5_COUNT, val)
+#define bfin_read_MXVR_DMA5_CURR_ADDR()         bfin_read32(MXVR_DMA5_CURR_ADDR)
+#define bfin_write_MXVR_DMA5_CURR_ADDR(val)     bfin_write32(MXVR_DMA5_CURR_ADDR)
+#define bfin_read_MXVR_DMA5_CURR_COUNT()        bfin_read16(MXVR_DMA5_CURR_COUNT)
+#define bfin_write_MXVR_DMA5_CURR_COUNT(val)    bfin_write16(MXVR_DMA5_CURR_COUNT, val)
+
+/* MXVR DMA6 Registers */
+
+#define bfin_read_MXVR_DMA6_CONFIG()            bfin_read32(MXVR_DMA6_CONFIG)
+#define bfin_write_MXVR_DMA6_CONFIG(val)        bfin_write32(MXVR_DMA6_CONFIG, val)
+#define bfin_read_MXVR_DMA6_START_ADDR()        bfin_read32(MXVR_DMA6_START_ADDR)
+#define bfin_write_MXVR_DMA6_START_ADDR(val)    bfin_write32(MXVR_DMA6_START_ADDR)
+#define bfin_read_MXVR_DMA6_COUNT()             bfin_read16(MXVR_DMA6_COUNT)
+#define bfin_write_MXVR_DMA6_COUNT(val)         bfin_write16(MXVR_DMA6_COUNT, val)
+#define bfin_read_MXVR_DMA6_CURR_ADDR()         bfin_read32(MXVR_DMA6_CURR_ADDR)
+#define bfin_write_MXVR_DMA6_CURR_ADDR(val)     bfin_write32(MXVR_DMA6_CURR_ADDR)
+#define bfin_read_MXVR_DMA6_CURR_COUNT()        bfin_read16(MXVR_DMA6_CURR_COUNT)
+#define bfin_write_MXVR_DMA6_CURR_COUNT(val)    bfin_write16(MXVR_DMA6_CURR_COUNT, val)
+
+/* MXVR DMA7 Registers */
+
+#define bfin_read_MXVR_DMA7_CONFIG()            bfin_read32(MXVR_DMA7_CONFIG)
+#define bfin_write_MXVR_DMA7_CONFIG(val)        bfin_write32(MXVR_DMA7_CONFIG, val)
+#define bfin_read_MXVR_DMA7_START_ADDR()        bfin_read32(MXVR_DMA7_START_ADDR)
+#define bfin_write_MXVR_DMA7_START_ADDR(val)    bfin_write32(MXVR_DMA7_START_ADDR)
+#define bfin_read_MXVR_DMA7_COUNT()             bfin_read16(MXVR_DMA7_COUNT)
+#define bfin_write_MXVR_DMA7_COUNT(val)         bfin_write16(MXVR_DMA7_COUNT, val)
+#define bfin_read_MXVR_DMA7_CURR_ADDR()         bfin_read32(MXVR_DMA7_CURR_ADDR)
+#define bfin_write_MXVR_DMA7_CURR_ADDR(val)     bfin_write32(MXVR_DMA7_CURR_ADDR)
+#define bfin_read_MXVR_DMA7_CURR_COUNT()        bfin_read16(MXVR_DMA7_CURR_COUNT)
+#define bfin_write_MXVR_DMA7_CURR_COUNT(val)    bfin_write16(MXVR_DMA7_CURR_COUNT, val)
+
+/* MXVR Asynch Packet Registers */
+
+#define bfin_read_MXVR_AP_CTL()                 bfin_read16(MXVR_AP_CTL)
+#define bfin_write_MXVR_AP_CTL(val)             bfin_write16(MXVR_AP_CTL, val)
+#define bfin_read_MXVR_APRB_START_ADDR()        bfin_read32(MXVR_APRB_START_ADDR)
+#define bfin_write_MXVR_APRB_START_ADDR(val)    bfin_write32(MXVR_APRB_START_ADDR)
+#define bfin_read_MXVR_APRB_CURR_ADDR()         bfin_read32(MXVR_APRB_CURR_ADDR)
+#define bfin_write_MXVR_APRB_CURR_ADDR(val)     bfin_write32(MXVR_APRB_CURR_ADDR)
+#define bfin_read_MXVR_APTB_START_ADDR()        bfin_read32(MXVR_APTB_START_ADDR)
+#define bfin_write_MXVR_APTB_START_ADDR(val)    bfin_write32(MXVR_APTB_START_ADDR)
+#define bfin_read_MXVR_APTB_CURR_ADDR()         bfin_read32(MXVR_APTB_CURR_ADDR)
+#define bfin_write_MXVR_APTB_CURR_ADDR(val)     bfin_write32(MXVR_APTB_CURR_ADDR)
+
+/* MXVR Control Message Registers */
+
+#define bfin_read_MXVR_CM_CTL()                 bfin_read32(MXVR_CM_CTL)
+#define bfin_write_MXVR_CM_CTL(val)             bfin_write32(MXVR_CM_CTL, val)
+#define bfin_read_MXVR_CMRB_START_ADDR()        bfin_read32(MXVR_CMRB_START_ADDR)
+#define bfin_write_MXVR_CMRB_START_ADDR(val)    bfin_write32(MXVR_CMRB_START_ADDR)
+#define bfin_read_MXVR_CMRB_CURR_ADDR()         bfin_read32(MXVR_CMRB_CURR_ADDR)
+#define bfin_write_MXVR_CMRB_CURR_ADDR(val)     bfin_write32(MXVR_CMRB_CURR_ADDR)
+#define bfin_read_MXVR_CMTB_START_ADDR()        bfin_read32(MXVR_CMTB_START_ADDR)
+#define bfin_write_MXVR_CMTB_START_ADDR(val)    bfin_write32(MXVR_CMTB_START_ADDR)
+#define bfin_read_MXVR_CMTB_CURR_ADDR()         bfin_read32(MXVR_CMTB_CURR_ADDR)
+#define bfin_write_MXVR_CMTB_CURR_ADDR(val)     bfin_write32(MXVR_CMTB_CURR_ADDR)
+
+/* MXVR Remote Read Registers */
+
+#define bfin_read_MXVR_RRDB_START_ADDR()        bfin_read32(MXVR_RRDB_START_ADDR)
+#define bfin_write_MXVR_RRDB_START_ADDR(val)    bfin_write32(MXVR_RRDB_START_ADDR)
+#define bfin_read_MXVR_RRDB_CURR_ADDR()         bfin_read32(MXVR_RRDB_CURR_ADDR)
+#define bfin_write_MXVR_RRDB_CURR_ADDR(val)     bfin_write32(MXVR_RRDB_CURR_ADDR)
+
+/* MXVR Pattern Data Registers */
+
+#define bfin_read_MXVR_PAT_DATA_0()             bfin_read32(MXVR_PAT_DATA_0)
+#define bfin_write_MXVR_PAT_DATA_0(val)         bfin_write32(MXVR_PAT_DATA_0, val)
+#define bfin_read_MXVR_PAT_EN_0()               bfin_read32(MXVR_PAT_EN_0)
+#define bfin_write_MXVR_PAT_EN_0(val)           bfin_write32(MXVR_PAT_EN_0, val)
+#define bfin_read_MXVR_PAT_DATA_1()             bfin_read32(MXVR_PAT_DATA_1)
+#define bfin_write_MXVR_PAT_DATA_1(val)         bfin_write32(MXVR_PAT_DATA_1, val)
+#define bfin_read_MXVR_PAT_EN_1()               bfin_read32(MXVR_PAT_EN_1)
+#define bfin_write_MXVR_PAT_EN_1(val)           bfin_write32(MXVR_PAT_EN_1, val)
+
+/* MXVR Frame Counter Registers */
+
+#define bfin_read_MXVR_FRAME_CNT_0()            bfin_read16(MXVR_FRAME_CNT_0)
+#define bfin_write_MXVR_FRAME_CNT_0(val)        bfin_write16(MXVR_FRAME_CNT_0, val)
+#define bfin_read_MXVR_FRAME_CNT_1()            bfin_read16(MXVR_FRAME_CNT_1)
+#define bfin_write_MXVR_FRAME_CNT_1(val)        bfin_write16(MXVR_FRAME_CNT_1, val)
+
+/* MXVR Routing Table Registers */
+
+#define bfin_read_MXVR_ROUTING_0()              bfin_read32(MXVR_ROUTING_0)
+#define bfin_write_MXVR_ROUTING_0(val)          bfin_write32(MXVR_ROUTING_0, val)
+#define bfin_read_MXVR_ROUTING_1()              bfin_read32(MXVR_ROUTING_1)
+#define bfin_write_MXVR_ROUTING_1(val)          bfin_write32(MXVR_ROUTING_1, val)
+#define bfin_read_MXVR_ROUTING_2()              bfin_read32(MXVR_ROUTING_2)
+#define bfin_write_MXVR_ROUTING_2(val)          bfin_write32(MXVR_ROUTING_2, val)
+#define bfin_read_MXVR_ROUTING_3()              bfin_read32(MXVR_ROUTING_3)
+#define bfin_write_MXVR_ROUTING_3(val)          bfin_write32(MXVR_ROUTING_3, val)
+#define bfin_read_MXVR_ROUTING_4()              bfin_read32(MXVR_ROUTING_4)
+#define bfin_write_MXVR_ROUTING_4(val)          bfin_write32(MXVR_ROUTING_4, val)
+#define bfin_read_MXVR_ROUTING_5()              bfin_read32(MXVR_ROUTING_5)
+#define bfin_write_MXVR_ROUTING_5(val)          bfin_write32(MXVR_ROUTING_5, val)
+#define bfin_read_MXVR_ROUTING_6()              bfin_read32(MXVR_ROUTING_6)
+#define bfin_write_MXVR_ROUTING_6(val)          bfin_write32(MXVR_ROUTING_6, val)
+#define bfin_read_MXVR_ROUTING_7()              bfin_read32(MXVR_ROUTING_7)
+#define bfin_write_MXVR_ROUTING_7(val)          bfin_write32(MXVR_ROUTING_7, val)
+#define bfin_read_MXVR_ROUTING_8()              bfin_read32(MXVR_ROUTING_8)
+#define bfin_write_MXVR_ROUTING_8(val)          bfin_write32(MXVR_ROUTING_8, val)
+#define bfin_read_MXVR_ROUTING_9()              bfin_read32(MXVR_ROUTING_9)
+#define bfin_write_MXVR_ROUTING_9(val)          bfin_write32(MXVR_ROUTING_9, val)
+#define bfin_read_MXVR_ROUTING_10()             bfin_read32(MXVR_ROUTING_10)
+#define bfin_write_MXVR_ROUTING_10(val)         bfin_write32(MXVR_ROUTING_10, val)
+#define bfin_read_MXVR_ROUTING_11()             bfin_read32(MXVR_ROUTING_11)
+#define bfin_write_MXVR_ROUTING_11(val)         bfin_write32(MXVR_ROUTING_11, val)
+#define bfin_read_MXVR_ROUTING_12()             bfin_read32(MXVR_ROUTING_12)
+#define bfin_write_MXVR_ROUTING_12(val)         bfin_write32(MXVR_ROUTING_12, val)
+#define bfin_read_MXVR_ROUTING_13()             bfin_read32(MXVR_ROUTING_13)
+#define bfin_write_MXVR_ROUTING_13(val)         bfin_write32(MXVR_ROUTING_13, val)
+#define bfin_read_MXVR_ROUTING_14()             bfin_read32(MXVR_ROUTING_14)
+#define bfin_write_MXVR_ROUTING_14(val)         bfin_write32(MXVR_ROUTING_14, val)
+
+/* MXVR Counter-Clock-Control Registers */
+
+#define bfin_read_MXVR_BLOCK_CNT()              bfin_read16(MXVR_BLOCK_CNT)
+#define bfin_write_MXVR_BLOCK_CNT(val)          bfin_write16(MXVR_BLOCK_CNT, val)
+#define bfin_read_MXVR_CLK_CTL()                bfin_read32(MXVR_CLK_CTL)
+#define bfin_write_MXVR_CLK_CTL(val)            bfin_write32(MXVR_CLK_CTL, val)
+#define bfin_read_MXVR_CDRPLL_CTL()             bfin_read32(MXVR_CDRPLL_CTL)
+#define bfin_write_MXVR_CDRPLL_CTL(val)         bfin_write32(MXVR_CDRPLL_CTL, val)
+#define bfin_read_MXVR_FMPLL_CTL()              bfin_read32(MXVR_FMPLL_CTL)
+#define bfin_write_MXVR_FMPLL_CTL(val)          bfin_write32(MXVR_FMPLL_CTL, val)
+#define bfin_read_MXVR_PIN_CTL()                bfin_read16(MXVR_PIN_CTL)
+#define bfin_write_MXVR_PIN_CTL(val)            bfin_write16(MXVR_PIN_CTL, val)
+#define bfin_read_MXVR_SCLK_CNT()               bfin_read16(MXVR_SCLK_CNT)
+#define bfin_write_MXVR_SCLK_CNT(val)           bfin_write16(MXVR_SCLK_CNT, val)
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define bfin_read_CAN1_MC1()            bfin_read16(CAN1_MC1)
+#define bfin_write_CAN1_MC1(val)        bfin_write16(CAN1_MC1, val)
+#define bfin_read_CAN1_MD1()            bfin_read16(CAN1_MD1)
+#define bfin_write_CAN1_MD1(val)        bfin_write16(CAN1_MD1, val)
+#define bfin_read_CAN1_TRS1()           bfin_read16(CAN1_TRS1)
+#define bfin_write_CAN1_TRS1(val)       bfin_write16(CAN1_TRS1, val)
+#define bfin_read_CAN1_TRR1()           bfin_read16(CAN1_TRR1)
+#define bfin_write_CAN1_TRR1(val)       bfin_write16(CAN1_TRR1, val)
+#define bfin_read_CAN1_TA1()            bfin_read16(CAN1_TA1)
+#define bfin_write_CAN1_TA1(val)        bfin_write16(CAN1_TA1, val)
+#define bfin_read_CAN1_AA1()            bfin_read16(CAN1_AA1)
+#define bfin_write_CAN1_AA1(val)        bfin_write16(CAN1_AA1, val)
+#define bfin_read_CAN1_RMP1()           bfin_read16(CAN1_RMP1)
+#define bfin_write_CAN1_RMP1(val)       bfin_write16(CAN1_RMP1, val)
+#define bfin_read_CAN1_RML1()           bfin_read16(CAN1_RML1)
+#define bfin_write_CAN1_RML1(val)       bfin_write16(CAN1_RML1, val)
+#define bfin_read_CAN1_MBTIF1()         bfin_read16(CAN1_MBTIF1)
+#define bfin_write_CAN1_MBTIF1(val)     bfin_write16(CAN1_MBTIF1, val)
+#define bfin_read_CAN1_MBRIF1()         bfin_read16(CAN1_MBRIF1)
+#define bfin_write_CAN1_MBRIF1(val)     bfin_write16(CAN1_MBRIF1, val)
+#define bfin_read_CAN1_MBIM1()          bfin_read16(CAN1_MBIM1)
+#define bfin_write_CAN1_MBIM1(val)      bfin_write16(CAN1_MBIM1, val)
+#define bfin_read_CAN1_RFH1()           bfin_read16(CAN1_RFH1)
+#define bfin_write_CAN1_RFH1(val)       bfin_write16(CAN1_RFH1, val)
+#define bfin_read_CAN1_OPSS1()          bfin_read16(CAN1_OPSS1)
+#define bfin_write_CAN1_OPSS1(val)      bfin_write16(CAN1_OPSS1, val)
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define bfin_read_CAN1_MC2()            bfin_read16(CAN1_MC2)
+#define bfin_write_CAN1_MC2(val)        bfin_write16(CAN1_MC2, val)
+#define bfin_read_CAN1_MD2()            bfin_read16(CAN1_MD2)
+#define bfin_write_CAN1_MD2(val)        bfin_write16(CAN1_MD2, val)
+#define bfin_read_CAN1_TRS2()           bfin_read16(CAN1_TRS2)
+#define bfin_write_CAN1_TRS2(val)       bfin_write16(CAN1_TRS2, val)
+#define bfin_read_CAN1_TRR2()           bfin_read16(CAN1_TRR2)
+#define bfin_write_CAN1_TRR2(val)       bfin_write16(CAN1_TRR2, val)
+#define bfin_read_CAN1_TA2()            bfin_read16(CAN1_TA2)
+#define bfin_write_CAN1_TA2(val)        bfin_write16(CAN1_TA2, val)
+#define bfin_read_CAN1_AA2()            bfin_read16(CAN1_AA2)
+#define bfin_write_CAN1_AA2(val)        bfin_write16(CAN1_AA2, val)
+#define bfin_read_CAN1_RMP2()           bfin_read16(CAN1_RMP2)
+#define bfin_write_CAN1_RMP2(val)       bfin_write16(CAN1_RMP2, val)
+#define bfin_read_CAN1_RML2()           bfin_read16(CAN1_RML2)
+#define bfin_write_CAN1_RML2(val)       bfin_write16(CAN1_RML2, val)
+#define bfin_read_CAN1_MBTIF2()         bfin_read16(CAN1_MBTIF2)
+#define bfin_write_CAN1_MBTIF2(val)     bfin_write16(CAN1_MBTIF2, val)
+#define bfin_read_CAN1_MBRIF2()         bfin_read16(CAN1_MBRIF2)
+#define bfin_write_CAN1_MBRIF2(val)     bfin_write16(CAN1_MBRIF2, val)
+#define bfin_read_CAN1_MBIM2()          bfin_read16(CAN1_MBIM2)
+#define bfin_write_CAN1_MBIM2(val)      bfin_write16(CAN1_MBIM2, val)
+#define bfin_read_CAN1_RFH2()           bfin_read16(CAN1_RFH2)
+#define bfin_write_CAN1_RFH2(val)       bfin_write16(CAN1_RFH2, val)
+#define bfin_read_CAN1_OPSS2()          bfin_read16(CAN1_OPSS2)
+#define bfin_write_CAN1_OPSS2(val)      bfin_write16(CAN1_OPSS2, val)
+
+/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
+
+#define bfin_read_CAN1_CLOCK()          bfin_read16(CAN1_CLOCK)
+#define bfin_write_CAN1_CLOCK(val)      bfin_write16(CAN1_CLOCK, val)
+#define bfin_read_CAN1_TIMING()         bfin_read16(CAN1_TIMING)
+#define bfin_write_CAN1_TIMING(val)     bfin_write16(CAN1_TIMING, val)
+#define bfin_read_CAN1_DEBUG()          bfin_read16(CAN1_DEBUG)
+#define bfin_write_CAN1_DEBUG(val)      bfin_write16(CAN1_DEBUG, val)
+#define bfin_read_CAN1_STATUS()         bfin_read16(CAN1_STATUS)
+#define bfin_write_CAN1_STATUS(val)     bfin_write16(CAN1_STATUS, val)
+#define bfin_read_CAN1_CEC()            bfin_read16(CAN1_CEC)
+#define bfin_write_CAN1_CEC(val)        bfin_write16(CAN1_CEC, val)
+#define bfin_read_CAN1_GIS()            bfin_read16(CAN1_GIS)
+#define bfin_write_CAN1_GIS(val)        bfin_write16(CAN1_GIS, val)
+#define bfin_read_CAN1_GIM()            bfin_read16(CAN1_GIM)
+#define bfin_write_CAN1_GIM(val)        bfin_write16(CAN1_GIM, val)
+#define bfin_read_CAN1_GIF()            bfin_read16(CAN1_GIF)
+#define bfin_write_CAN1_GIF(val)        bfin_write16(CAN1_GIF, val)
+#define bfin_read_CAN1_CONTROL()        bfin_read16(CAN1_CONTROL)
+#define bfin_write_CAN1_CONTROL(val)    bfin_write16(CAN1_CONTROL, val)
+#define bfin_read_CAN1_INTR()           bfin_read16(CAN1_INTR)
+#define bfin_write_CAN1_INTR(val)       bfin_write16(CAN1_INTR, val)
+#define bfin_read_CAN1_MBTD()           bfin_read16(CAN1_MBTD)
+#define bfin_write_CAN1_MBTD(val)       bfin_write16(CAN1_MBTD, val)
+#define bfin_read_CAN1_EWR()            bfin_read16(CAN1_EWR)
+#define bfin_write_CAN1_EWR(val)        bfin_write16(CAN1_EWR, val)
+#define bfin_read_CAN1_ESR()            bfin_read16(CAN1_ESR)
+#define bfin_write_CAN1_ESR(val)        bfin_write16(CAN1_ESR, val)
+#define bfin_read_CAN1_UCCNT()          bfin_read16(CAN1_UCCNT)
+#define bfin_write_CAN1_UCCNT(val)      bfin_write16(CAN1_UCCNT, val)
+#define bfin_read_CAN1_UCRC()           bfin_read16(CAN1_UCRC)
+#define bfin_write_CAN1_UCRC(val)       bfin_write16(CAN1_UCRC, val)
+#define bfin_read_CAN1_UCCNF()          bfin_read16(CAN1_UCCNF)
+#define bfin_write_CAN1_UCCNF(val)      bfin_write16(CAN1_UCCNF, val)
+
+/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
+
+#define bfin_read_CAN1_AM00L()          bfin_read16(CAN1_AM00L)
+#define bfin_write_CAN1_AM00L(val)      bfin_write16(CAN1_AM00L, val)
+#define bfin_read_CAN1_AM00H()          bfin_read16(CAN1_AM00H)
+#define bfin_write_CAN1_AM00H(val)      bfin_write16(CAN1_AM00H, val)
+#define bfin_read_CAN1_AM01L()          bfin_read16(CAN1_AM01L)
+#define bfin_write_CAN1_AM01L(val)      bfin_write16(CAN1_AM01L, val)
+#define bfin_read_CAN1_AM01H()          bfin_read16(CAN1_AM01H)
+#define bfin_write_CAN1_AM01H(val)      bfin_write16(CAN1_AM01H, val)
+#define bfin_read_CAN1_AM02L()          bfin_read16(CAN1_AM02L)
+#define bfin_write_CAN1_AM02L(val)      bfin_write16(CAN1_AM02L, val)
+#define bfin_read_CAN1_AM02H()          bfin_read16(CAN1_AM02H)
+#define bfin_write_CAN1_AM02H(val)      bfin_write16(CAN1_AM02H, val)
+#define bfin_read_CAN1_AM03L()          bfin_read16(CAN1_AM03L)
+#define bfin_write_CAN1_AM03L(val)      bfin_write16(CAN1_AM03L, val)
+#define bfin_read_CAN1_AM03H()          bfin_read16(CAN1_AM03H)
+#define bfin_write_CAN1_AM03H(val)      bfin_write16(CAN1_AM03H, val)
+#define bfin_read_CAN1_AM04L()          bfin_read16(CAN1_AM04L)
+#define bfin_write_CAN1_AM04L(val)      bfin_write16(CAN1_AM04L, val)
+#define bfin_read_CAN1_AM04H()          bfin_read16(CAN1_AM04H)
+#define bfin_write_CAN1_AM04H(val)      bfin_write16(CAN1_AM04H, val)
+#define bfin_read_CAN1_AM05L()          bfin_read16(CAN1_AM05L)
+#define bfin_write_CAN1_AM05L(val)      bfin_write16(CAN1_AM05L, val)
+#define bfin_read_CAN1_AM05H()          bfin_read16(CAN1_AM05H)
+#define bfin_write_CAN1_AM05H(val)      bfin_write16(CAN1_AM05H, val)
+#define bfin_read_CAN1_AM06L()          bfin_read16(CAN1_AM06L)
+#define bfin_write_CAN1_AM06L(val)      bfin_write16(CAN1_AM06L, val)
+#define bfin_read_CAN1_AM06H()          bfin_read16(CAN1_AM06H)
+#define bfin_write_CAN1_AM06H(val)      bfin_write16(CAN1_AM06H, val)
+#define bfin_read_CAN1_AM07L()          bfin_read16(CAN1_AM07L)
+#define bfin_write_CAN1_AM07L(val)      bfin_write16(CAN1_AM07L, val)
+#define bfin_read_CAN1_AM07H()          bfin_read16(CAN1_AM07H)
+#define bfin_write_CAN1_AM07H(val)      bfin_write16(CAN1_AM07H, val)
+#define bfin_read_CAN1_AM08L()          bfin_read16(CAN1_AM08L)
+#define bfin_write_CAN1_AM08L(val)      bfin_write16(CAN1_AM08L, val)
+#define bfin_read_CAN1_AM08H()          bfin_read16(CAN1_AM08H)
+#define bfin_write_CAN1_AM08H(val)      bfin_write16(CAN1_AM08H, val)
+#define bfin_read_CAN1_AM09L()          bfin_read16(CAN1_AM09L)
+#define bfin_write_CAN1_AM09L(val)      bfin_write16(CAN1_AM09L, val)
+#define bfin_read_CAN1_AM09H()          bfin_read16(CAN1_AM09H)
+#define bfin_write_CAN1_AM09H(val)      bfin_write16(CAN1_AM09H, val)
+#define bfin_read_CAN1_AM10L()          bfin_read16(CAN1_AM10L)
+#define bfin_write_CAN1_AM10L(val)      bfin_write16(CAN1_AM10L, val)
+#define bfin_read_CAN1_AM10H()          bfin_read16(CAN1_AM10H)
+#define bfin_write_CAN1_AM10H(val)      bfin_write16(CAN1_AM10H, val)
+#define bfin_read_CAN1_AM11L()          bfin_read16(CAN1_AM11L)
+#define bfin_write_CAN1_AM11L(val)      bfin_write16(CAN1_AM11L, val)
+#define bfin_read_CAN1_AM11H()          bfin_read16(CAN1_AM11H)
+#define bfin_write_CAN1_AM11H(val)      bfin_write16(CAN1_AM11H, val)
+#define bfin_read_CAN1_AM12L()          bfin_read16(CAN1_AM12L)
+#define bfin_write_CAN1_AM12L(val)      bfin_write16(CAN1_AM12L, val)
+#define bfin_read_CAN1_AM12H()          bfin_read16(CAN1_AM12H)
+#define bfin_write_CAN1_AM12H(val)      bfin_write16(CAN1_AM12H, val)
+#define bfin_read_CAN1_AM13L()          bfin_read16(CAN1_AM13L)
+#define bfin_write_CAN1_AM13L(val)      bfin_write16(CAN1_AM13L, val)
+#define bfin_read_CAN1_AM13H()          bfin_read16(CAN1_AM13H)
+#define bfin_write_CAN1_AM13H(val)      bfin_write16(CAN1_AM13H, val)
+#define bfin_read_CAN1_AM14L()          bfin_read16(CAN1_AM14L)
+#define bfin_write_CAN1_AM14L(val)      bfin_write16(CAN1_AM14L, val)
+#define bfin_read_CAN1_AM14H()          bfin_read16(CAN1_AM14H)
+#define bfin_write_CAN1_AM14H(val)      bfin_write16(CAN1_AM14H, val)
+#define bfin_read_CAN1_AM15L()          bfin_read16(CAN1_AM15L)
+#define bfin_write_CAN1_AM15L(val)      bfin_write16(CAN1_AM15L, val)
+#define bfin_read_CAN1_AM15H()          bfin_read16(CAN1_AM15H)
+#define bfin_write_CAN1_AM15H(val)      bfin_write16(CAN1_AM15H, val)
+
+/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
+
+#define bfin_read_CAN1_AM16L()          bfin_read16(CAN1_AM16L)
+#define bfin_write_CAN1_AM16L(val)      bfin_write16(CAN1_AM16L, val)
+#define bfin_read_CAN1_AM16H()          bfin_read16(CAN1_AM16H)
+#define bfin_write_CAN1_AM16H(val)      bfin_write16(CAN1_AM16H, val)
+#define bfin_read_CAN1_AM17L()          bfin_read16(CAN1_AM17L)
+#define bfin_write_CAN1_AM17L(val)      bfin_write16(CAN1_AM17L, val)
+#define bfin_read_CAN1_AM17H()          bfin_read16(CAN1_AM17H)
+#define bfin_write_CAN1_AM17H(val)      bfin_write16(CAN1_AM17H, val)
+#define bfin_read_CAN1_AM18L()          bfin_read16(CAN1_AM18L)
+#define bfin_write_CAN1_AM18L(val)      bfin_write16(CAN1_AM18L, val)
+#define bfin_read_CAN1_AM18H()          bfin_read16(CAN1_AM18H)
+#define bfin_write_CAN1_AM18H(val)      bfin_write16(CAN1_AM18H, val)
+#define bfin_read_CAN1_AM19L()          bfin_read16(CAN1_AM19L)
+#define bfin_write_CAN1_AM19L(val)      bfin_write16(CAN1_AM19L, val)
+#define bfin_read_CAN1_AM19H()          bfin_read16(CAN1_AM19H)
+#define bfin_write_CAN1_AM19H(val)      bfin_write16(CAN1_AM19H, val)
+#define bfin_read_CAN1_AM20L()          bfin_read16(CAN1_AM20L)
+#define bfin_write_CAN1_AM20L(val)      bfin_write16(CAN1_AM20L, val)
+#define bfin_read_CAN1_AM20H()          bfin_read16(CAN1_AM20H)
+#define bfin_write_CAN1_AM20H(val)      bfin_write16(CAN1_AM20H, val)
+#define bfin_read_CAN1_AM21L()          bfin_read16(CAN1_AM21L)
+#define bfin_write_CAN1_AM21L(val)      bfin_write16(CAN1_AM21L, val)
+#define bfin_read_CAN1_AM21H()          bfin_read16(CAN1_AM21H)
+#define bfin_write_CAN1_AM21H(val)      bfin_write16(CAN1_AM21H, val)
+#define bfin_read_CAN1_AM22L()          bfin_read16(CAN1_AM22L)
+#define bfin_write_CAN1_AM22L(val)      bfin_write16(CAN1_AM22L, val)
+#define bfin_read_CAN1_AM22H()          bfin_read16(CAN1_AM22H)
+#define bfin_write_CAN1_AM22H(val)      bfin_write16(CAN1_AM22H, val)
+#define bfin_read_CAN1_AM23L()          bfin_read16(CAN1_AM23L)
+#define bfin_write_CAN1_AM23L(val)      bfin_write16(CAN1_AM23L, val)
+#define bfin_read_CAN1_AM23H()          bfin_read16(CAN1_AM23H)
+#define bfin_write_CAN1_AM23H(val)      bfin_write16(CAN1_AM23H, val)
+#define bfin_read_CAN1_AM24L()          bfin_read16(CAN1_AM24L)
+#define bfin_write_CAN1_AM24L(val)      bfin_write16(CAN1_AM24L, val)
+#define bfin_read_CAN1_AM24H()          bfin_read16(CAN1_AM24H)
+#define bfin_write_CAN1_AM24H(val)      bfin_write16(CAN1_AM24H, val)
+#define bfin_read_CAN1_AM25L()          bfin_read16(CAN1_AM25L)
+#define bfin_write_CAN1_AM25L(val)      bfin_write16(CAN1_AM25L, val)
+#define bfin_read_CAN1_AM25H()          bfin_read16(CAN1_AM25H)
+#define bfin_write_CAN1_AM25H(val)      bfin_write16(CAN1_AM25H, val)
+#define bfin_read_CAN1_AM26L()          bfin_read16(CAN1_AM26L)
+#define bfin_write_CAN1_AM26L(val)      bfin_write16(CAN1_AM26L, val)
+#define bfin_read_CAN1_AM26H()          bfin_read16(CAN1_AM26H)
+#define bfin_write_CAN1_AM26H(val)      bfin_write16(CAN1_AM26H, val)
+#define bfin_read_CAN1_AM27L()          bfin_read16(CAN1_AM27L)
+#define bfin_write_CAN1_AM27L(val)      bfin_write16(CAN1_AM27L, val)
+#define bfin_read_CAN1_AM27H()          bfin_read16(CAN1_AM27H)
+#define bfin_write_CAN1_AM27H(val)      bfin_write16(CAN1_AM27H, val)
+#define bfin_read_CAN1_AM28L()          bfin_read16(CAN1_AM28L)
+#define bfin_write_CAN1_AM28L(val)      bfin_write16(CAN1_AM28L, val)
+#define bfin_read_CAN1_AM28H()          bfin_read16(CAN1_AM28H)
+#define bfin_write_CAN1_AM28H(val)      bfin_write16(CAN1_AM28H, val)
+#define bfin_read_CAN1_AM29L()          bfin_read16(CAN1_AM29L)
+#define bfin_write_CAN1_AM29L(val)      bfin_write16(CAN1_AM29L, val)
+#define bfin_read_CAN1_AM29H()          bfin_read16(CAN1_AM29H)
+#define bfin_write_CAN1_AM29H(val)      bfin_write16(CAN1_AM29H, val)
+#define bfin_read_CAN1_AM30L()          bfin_read16(CAN1_AM30L)
+#define bfin_write_CAN1_AM30L(val)      bfin_write16(CAN1_AM30L, val)
+#define bfin_read_CAN1_AM30H()          bfin_read16(CAN1_AM30H)
+#define bfin_write_CAN1_AM30H(val)      bfin_write16(CAN1_AM30H, val)
+#define bfin_read_CAN1_AM31L()          bfin_read16(CAN1_AM31L)
+#define bfin_write_CAN1_AM31L(val)      bfin_write16(CAN1_AM31L, val)
+#define bfin_read_CAN1_AM31H()          bfin_read16(CAN1_AM31H)
+#define bfin_write_CAN1_AM31H(val)      bfin_write16(CAN1_AM31H, val)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define bfin_read_CAN1_MB00_DATA0()             bfin_read16(CAN1_MB00_DATA0)
+#define bfin_write_CAN1_MB00_DATA0(val)         bfin_write16(CAN1_MB00_DATA0, val)
+#define bfin_read_CAN1_MB00_DATA1()             bfin_read16(CAN1_MB00_DATA1)
+#define bfin_write_CAN1_MB00_DATA1(val)         bfin_write16(CAN1_MB00_DATA1, val)
+#define bfin_read_CAN1_MB00_DATA2()             bfin_read16(CAN1_MB00_DATA2)
+#define bfin_write_CAN1_MB00_DATA2(val)         bfin_write16(CAN1_MB00_DATA2, val)
+#define bfin_read_CAN1_MB00_DATA3()             bfin_read16(CAN1_MB00_DATA3)
+#define bfin_write_CAN1_MB00_DATA3(val)         bfin_write16(CAN1_MB00_DATA3, val)
+#define bfin_read_CAN1_MB00_LENGTH()            bfin_read16(CAN1_MB00_LENGTH)
+#define bfin_write_CAN1_MB00_LENGTH(val)        bfin_write16(CAN1_MB00_LENGTH, val)
+#define bfin_read_CAN1_MB00_TIMESTAMP()         bfin_read16(CAN1_MB00_TIMESTAMP)
+#define bfin_write_CAN1_MB00_TIMESTAMP(val)     bfin_write16(CAN1_MB00_TIMESTAMP, val)
+#define bfin_read_CAN1_MB00_ID0()               bfin_read16(CAN1_MB00_ID0)
+#define bfin_write_CAN1_MB00_ID0(val)           bfin_write16(CAN1_MB00_ID0, val)
+#define bfin_read_CAN1_MB00_ID1()               bfin_read16(CAN1_MB00_ID1)
+#define bfin_write_CAN1_MB00_ID1(val)           bfin_write16(CAN1_MB00_ID1, val)
+#define bfin_read_CAN1_MB01_DATA0()             bfin_read16(CAN1_MB01_DATA0)
+#define bfin_write_CAN1_MB01_DATA0(val)         bfin_write16(CAN1_MB01_DATA0, val)
+#define bfin_read_CAN1_MB01_DATA1()             bfin_read16(CAN1_MB01_DATA1)
+#define bfin_write_CAN1_MB01_DATA1(val)         bfin_write16(CAN1_MB01_DATA1, val)
+#define bfin_read_CAN1_MB01_DATA2()             bfin_read16(CAN1_MB01_DATA2)
+#define bfin_write_CAN1_MB01_DATA2(val)         bfin_write16(CAN1_MB01_DATA2, val)
+#define bfin_read_CAN1_MB01_DATA3()             bfin_read16(CAN1_MB01_DATA3)
+#define bfin_write_CAN1_MB01_DATA3(val)         bfin_write16(CAN1_MB01_DATA3, val)
+#define bfin_read_CAN1_MB01_LENGTH()            bfin_read16(CAN1_MB01_LENGTH)
+#define bfin_write_CAN1_MB01_LENGTH(val)        bfin_write16(CAN1_MB01_LENGTH, val)
+#define bfin_read_CAN1_MB01_TIMESTAMP()         bfin_read16(CAN1_MB01_TIMESTAMP)
+#define bfin_write_CAN1_MB01_TIMESTAMP(val)     bfin_write16(CAN1_MB01_TIMESTAMP, val)
+#define bfin_read_CAN1_MB01_ID0()               bfin_read16(CAN1_MB01_ID0)
+#define bfin_write_CAN1_MB01_ID0(val)           bfin_write16(CAN1_MB01_ID0, val)
+#define bfin_read_CAN1_MB01_ID1()               bfin_read16(CAN1_MB01_ID1)
+#define bfin_write_CAN1_MB01_ID1(val)           bfin_write16(CAN1_MB01_ID1, val)
+#define bfin_read_CAN1_MB02_DATA0()             bfin_read16(CAN1_MB02_DATA0)
+#define bfin_write_CAN1_MB02_DATA0(val)         bfin_write16(CAN1_MB02_DATA0, val)
+#define bfin_read_CAN1_MB02_DATA1()             bfin_read16(CAN1_MB02_DATA1)
+#define bfin_write_CAN1_MB02_DATA1(val)         bfin_write16(CAN1_MB02_DATA1, val)
+#define bfin_read_CAN1_MB02_DATA2()             bfin_read16(CAN1_MB02_DATA2)
+#define bfin_write_CAN1_MB02_DATA2(val)         bfin_write16(CAN1_MB02_DATA2, val)
+#define bfin_read_CAN1_MB02_DATA3()             bfin_read16(CAN1_MB02_DATA3)
+#define bfin_write_CAN1_MB02_DATA3(val)         bfin_write16(CAN1_MB02_DATA3, val)
+#define bfin_read_CAN1_MB02_LENGTH()            bfin_read16(CAN1_MB02_LENGTH)
+#define bfin_write_CAN1_MB02_LENGTH(val)        bfin_write16(CAN1_MB02_LENGTH, val)
+#define bfin_read_CAN1_MB02_TIMESTAMP()         bfin_read16(CAN1_MB02_TIMESTAMP)
+#define bfin_write_CAN1_MB02_TIMESTAMP(val)     bfin_write16(CAN1_MB02_TIMESTAMP, val)
+#define bfin_read_CAN1_MB02_ID0()               bfin_read16(CAN1_MB02_ID0)
+#define bfin_write_CAN1_MB02_ID0(val)           bfin_write16(CAN1_MB02_ID0, val)
+#define bfin_read_CAN1_MB02_ID1()               bfin_read16(CAN1_MB02_ID1)
+#define bfin_write_CAN1_MB02_ID1(val)           bfin_write16(CAN1_MB02_ID1, val)
+#define bfin_read_CAN1_MB03_DATA0()             bfin_read16(CAN1_MB03_DATA0)
+#define bfin_write_CAN1_MB03_DATA0(val)         bfin_write16(CAN1_MB03_DATA0, val)
+#define bfin_read_CAN1_MB03_DATA1()             bfin_read16(CAN1_MB03_DATA1)
+#define bfin_write_CAN1_MB03_DATA1(val)         bfin_write16(CAN1_MB03_DATA1, val)
+#define bfin_read_CAN1_MB03_DATA2()             bfin_read16(CAN1_MB03_DATA2)
+#define bfin_write_CAN1_MB03_DATA2(val)         bfin_write16(CAN1_MB03_DATA2, val)
+#define bfin_read_CAN1_MB03_DATA3()             bfin_read16(CAN1_MB03_DATA3)
+#define bfin_write_CAN1_MB03_DATA3(val)         bfin_write16(CAN1_MB03_DATA3, val)
+#define bfin_read_CAN1_MB03_LENGTH()            bfin_read16(CAN1_MB03_LENGTH)
+#define bfin_write_CAN1_MB03_LENGTH(val)        bfin_write16(CAN1_MB03_LENGTH, val)
+#define bfin_read_CAN1_MB03_TIMESTAMP()         bfin_read16(CAN1_MB03_TIMESTAMP)
+#define bfin_write_CAN1_MB03_TIMESTAMP(val)     bfin_write16(CAN1_MB03_TIMESTAMP, val)
+#define bfin_read_CAN1_MB03_ID0()               bfin_read16(CAN1_MB03_ID0)
+#define bfin_write_CAN1_MB03_ID0(val)           bfin_write16(CAN1_MB03_ID0, val)
+#define bfin_read_CAN1_MB03_ID1()               bfin_read16(CAN1_MB03_ID1)
+#define bfin_write_CAN1_MB03_ID1(val)           bfin_write16(CAN1_MB03_ID1, val)
+#define bfin_read_CAN1_MB04_DATA0()             bfin_read16(CAN1_MB04_DATA0)
+#define bfin_write_CAN1_MB04_DATA0(val)         bfin_write16(CAN1_MB04_DATA0, val)
+#define bfin_read_CAN1_MB04_DATA1()             bfin_read16(CAN1_MB04_DATA1)
+#define bfin_write_CAN1_MB04_DATA1(val)         bfin_write16(CAN1_MB04_DATA1, val)
+#define bfin_read_CAN1_MB04_DATA2()             bfin_read16(CAN1_MB04_DATA2)
+#define bfin_write_CAN1_MB04_DATA2(val)         bfin_write16(CAN1_MB04_DATA2, val)
+#define bfin_read_CAN1_MB04_DATA3()             bfin_read16(CAN1_MB04_DATA3)
+#define bfin_write_CAN1_MB04_DATA3(val)         bfin_write16(CAN1_MB04_DATA3, val)
+#define bfin_read_CAN1_MB04_LENGTH()            bfin_read16(CAN1_MB04_LENGTH)
+#define bfin_write_CAN1_MB04_LENGTH(val)        bfin_write16(CAN1_MB04_LENGTH, val)
+#define bfin_read_CAN1_MB04_TIMESTAMP()         bfin_read16(CAN1_MB04_TIMESTAMP)
+#define bfin_write_CAN1_MB04_TIMESTAMP(val)     bfin_write16(CAN1_MB04_TIMESTAMP, val)
+#define bfin_read_CAN1_MB04_ID0()               bfin_read16(CAN1_MB04_ID0)
+#define bfin_write_CAN1_MB04_ID0(val)           bfin_write16(CAN1_MB04_ID0, val)
+#define bfin_read_CAN1_MB04_ID1()               bfin_read16(CAN1_MB04_ID1)
+#define bfin_write_CAN1_MB04_ID1(val)           bfin_write16(CAN1_MB04_ID1, val)
+#define bfin_read_CAN1_MB05_DATA0()             bfin_read16(CAN1_MB05_DATA0)
+#define bfin_write_CAN1_MB05_DATA0(val)         bfin_write16(CAN1_MB05_DATA0, val)
+#define bfin_read_CAN1_MB05_DATA1()             bfin_read16(CAN1_MB05_DATA1)
+#define bfin_write_CAN1_MB05_DATA1(val)         bfin_write16(CAN1_MB05_DATA1, val)
+#define bfin_read_CAN1_MB05_DATA2()             bfin_read16(CAN1_MB05_DATA2)
+#define bfin_write_CAN1_MB05_DATA2(val)         bfin_write16(CAN1_MB05_DATA2, val)
+#define bfin_read_CAN1_MB05_DATA3()             bfin_read16(CAN1_MB05_DATA3)
+#define bfin_write_CAN1_MB05_DATA3(val)         bfin_write16(CAN1_MB05_DATA3, val)
+#define bfin_read_CAN1_MB05_LENGTH()            bfin_read16(CAN1_MB05_LENGTH)
+#define bfin_write_CAN1_MB05_LENGTH(val)        bfin_write16(CAN1_MB05_LENGTH, val)
+#define bfin_read_CAN1_MB05_TIMESTAMP()         bfin_read16(CAN1_MB05_TIMESTAMP)
+#define bfin_write_CAN1_MB05_TIMESTAMP(val)     bfin_write16(CAN1_MB05_TIMESTAMP, val)
+#define bfin_read_CAN1_MB05_ID0()               bfin_read16(CAN1_MB05_ID0)
+#define bfin_write_CAN1_MB05_ID0(val)           bfin_write16(CAN1_MB05_ID0, val)
+#define bfin_read_CAN1_MB05_ID1()               bfin_read16(CAN1_MB05_ID1)
+#define bfin_write_CAN1_MB05_ID1(val)           bfin_write16(CAN1_MB05_ID1, val)
+#define bfin_read_CAN1_MB06_DATA0()             bfin_read16(CAN1_MB06_DATA0)
+#define bfin_write_CAN1_MB06_DATA0(val)         bfin_write16(CAN1_MB06_DATA0, val)
+#define bfin_read_CAN1_MB06_DATA1()             bfin_read16(CAN1_MB06_DATA1)
+#define bfin_write_CAN1_MB06_DATA1(val)         bfin_write16(CAN1_MB06_DATA1, val)
+#define bfin_read_CAN1_MB06_DATA2()             bfin_read16(CAN1_MB06_DATA2)
+#define bfin_write_CAN1_MB06_DATA2(val)         bfin_write16(CAN1_MB06_DATA2, val)
+#define bfin_read_CAN1_MB06_DATA3()             bfin_read16(CAN1_MB06_DATA3)
+#define bfin_write_CAN1_MB06_DATA3(val)         bfin_write16(CAN1_MB06_DATA3, val)
+#define bfin_read_CAN1_MB06_LENGTH()            bfin_read16(CAN1_MB06_LENGTH)
+#define bfin_write_CAN1_MB06_LENGTH(val)        bfin_write16(CAN1_MB06_LENGTH, val)
+#define bfin_read_CAN1_MB06_TIMESTAMP()         bfin_read16(CAN1_MB06_TIMESTAMP)
+#define bfin_write_CAN1_MB06_TIMESTAMP(val)     bfin_write16(CAN1_MB06_TIMESTAMP, val)
+#define bfin_read_CAN1_MB06_ID0()               bfin_read16(CAN1_MB06_ID0)
+#define bfin_write_CAN1_MB06_ID0(val)           bfin_write16(CAN1_MB06_ID0, val)
+#define bfin_read_CAN1_MB06_ID1()               bfin_read16(CAN1_MB06_ID1)
+#define bfin_write_CAN1_MB06_ID1(val)           bfin_write16(CAN1_MB06_ID1, val)
+#define bfin_read_CAN1_MB07_DATA0()             bfin_read16(CAN1_MB07_DATA0)
+#define bfin_write_CAN1_MB07_DATA0(val)         bfin_write16(CAN1_MB07_DATA0, val)
+#define bfin_read_CAN1_MB07_DATA1()             bfin_read16(CAN1_MB07_DATA1)
+#define bfin_write_CAN1_MB07_DATA1(val)         bfin_write16(CAN1_MB07_DATA1, val)
+#define bfin_read_CAN1_MB07_DATA2()             bfin_read16(CAN1_MB07_DATA2)
+#define bfin_write_CAN1_MB07_DATA2(val)         bfin_write16(CAN1_MB07_DATA2, val)
+#define bfin_read_CAN1_MB07_DATA3()             bfin_read16(CAN1_MB07_DATA3)
+#define bfin_write_CAN1_MB07_DATA3(val)         bfin_write16(CAN1_MB07_DATA3, val)
+#define bfin_read_CAN1_MB07_LENGTH()            bfin_read16(CAN1_MB07_LENGTH)
+#define bfin_write_CAN1_MB07_LENGTH(val)        bfin_write16(CAN1_MB07_LENGTH, val)
+#define bfin_read_CAN1_MB07_TIMESTAMP()         bfin_read16(CAN1_MB07_TIMESTAMP)
+#define bfin_write_CAN1_MB07_TIMESTAMP(val)     bfin_write16(CAN1_MB07_TIMESTAMP, val)
+#define bfin_read_CAN1_MB07_ID0()               bfin_read16(CAN1_MB07_ID0)
+#define bfin_write_CAN1_MB07_ID0(val)           bfin_write16(CAN1_MB07_ID0, val)
+#define bfin_read_CAN1_MB07_ID1()               bfin_read16(CAN1_MB07_ID1)
+#define bfin_write_CAN1_MB07_ID1(val)           bfin_write16(CAN1_MB07_ID1, val)
+#define bfin_read_CAN1_MB08_DATA0()             bfin_read16(CAN1_MB08_DATA0)
+#define bfin_write_CAN1_MB08_DATA0(val)         bfin_write16(CAN1_MB08_DATA0, val)
+#define bfin_read_CAN1_MB08_DATA1()             bfin_read16(CAN1_MB08_DATA1)
+#define bfin_write_CAN1_MB08_DATA1(val)         bfin_write16(CAN1_MB08_DATA1, val)
+#define bfin_read_CAN1_MB08_DATA2()             bfin_read16(CAN1_MB08_DATA2)
+#define bfin_write_CAN1_MB08_DATA2(val)         bfin_write16(CAN1_MB08_DATA2, val)
+#define bfin_read_CAN1_MB08_DATA3()             bfin_read16(CAN1_MB08_DATA3)
+#define bfin_write_CAN1_MB08_DATA3(val)         bfin_write16(CAN1_MB08_DATA3, val)
+#define bfin_read_CAN1_MB08_LENGTH()            bfin_read16(CAN1_MB08_LENGTH)
+#define bfin_write_CAN1_MB08_LENGTH(val)        bfin_write16(CAN1_MB08_LENGTH, val)
+#define bfin_read_CAN1_MB08_TIMESTAMP()         bfin_read16(CAN1_MB08_TIMESTAMP)
+#define bfin_write_CAN1_MB08_TIMESTAMP(val)     bfin_write16(CAN1_MB08_TIMESTAMP, val)
+#define bfin_read_CAN1_MB08_ID0()               bfin_read16(CAN1_MB08_ID0)
+#define bfin_write_CAN1_MB08_ID0(val)           bfin_write16(CAN1_MB08_ID0, val)
+#define bfin_read_CAN1_MB08_ID1()               bfin_read16(CAN1_MB08_ID1)
+#define bfin_write_CAN1_MB08_ID1(val)           bfin_write16(CAN1_MB08_ID1, val)
+#define bfin_read_CAN1_MB09_DATA0()             bfin_read16(CAN1_MB09_DATA0)
+#define bfin_write_CAN1_MB09_DATA0(val)         bfin_write16(CAN1_MB09_DATA0, val)
+#define bfin_read_CAN1_MB09_DATA1()             bfin_read16(CAN1_MB09_DATA1)
+#define bfin_write_CAN1_MB09_DATA1(val)         bfin_write16(CAN1_MB09_DATA1, val)
+#define bfin_read_CAN1_MB09_DATA2()             bfin_read16(CAN1_MB09_DATA2)
+#define bfin_write_CAN1_MB09_DATA2(val)         bfin_write16(CAN1_MB09_DATA2, val)
+#define bfin_read_CAN1_MB09_DATA3()             bfin_read16(CAN1_MB09_DATA3)
+#define bfin_write_CAN1_MB09_DATA3(val)         bfin_write16(CAN1_MB09_DATA3, val)
+#define bfin_read_CAN1_MB09_LENGTH()            bfin_read16(CAN1_MB09_LENGTH)
+#define bfin_write_CAN1_MB09_LENGTH(val)        bfin_write16(CAN1_MB09_LENGTH, val)
+#define bfin_read_CAN1_MB09_TIMESTAMP()         bfin_read16(CAN1_MB09_TIMESTAMP)
+#define bfin_write_CAN1_MB09_TIMESTAMP(val)     bfin_write16(CAN1_MB09_TIMESTAMP, val)
+#define bfin_read_CAN1_MB09_ID0()               bfin_read16(CAN1_MB09_ID0)
+#define bfin_write_CAN1_MB09_ID0(val)           bfin_write16(CAN1_MB09_ID0, val)
+#define bfin_read_CAN1_MB09_ID1()               bfin_read16(CAN1_MB09_ID1)
+#define bfin_write_CAN1_MB09_ID1(val)           bfin_write16(CAN1_MB09_ID1, val)
+#define bfin_read_CAN1_MB10_DATA0()             bfin_read16(CAN1_MB10_DATA0)
+#define bfin_write_CAN1_MB10_DATA0(val)         bfin_write16(CAN1_MB10_DATA0, val)
+#define bfin_read_CAN1_MB10_DATA1()             bfin_read16(CAN1_MB10_DATA1)
+#define bfin_write_CAN1_MB10_DATA1(val)         bfin_write16(CAN1_MB10_DATA1, val)
+#define bfin_read_CAN1_MB10_DATA2()             bfin_read16(CAN1_MB10_DATA2)
+#define bfin_write_CAN1_MB10_DATA2(val)         bfin_write16(CAN1_MB10_DATA2, val)
+#define bfin_read_CAN1_MB10_DATA3()             bfin_read16(CAN1_MB10_DATA3)
+#define bfin_write_CAN1_MB10_DATA3(val)         bfin_write16(CAN1_MB10_DATA3, val)
+#define bfin_read_CAN1_MB10_LENGTH()            bfin_read16(CAN1_MB10_LENGTH)
+#define bfin_write_CAN1_MB10_LENGTH(val)        bfin_write16(CAN1_MB10_LENGTH, val)
+#define bfin_read_CAN1_MB10_TIMESTAMP()         bfin_read16(CAN1_MB10_TIMESTAMP)
+#define bfin_write_CAN1_MB10_TIMESTAMP(val)     bfin_write16(CAN1_MB10_TIMESTAMP, val)
+#define bfin_read_CAN1_MB10_ID0()               bfin_read16(CAN1_MB10_ID0)
+#define bfin_write_CAN1_MB10_ID0(val)           bfin_write16(CAN1_MB10_ID0, val)
+#define bfin_read_CAN1_MB10_ID1()               bfin_read16(CAN1_MB10_ID1)
+#define bfin_write_CAN1_MB10_ID1(val)           bfin_write16(CAN1_MB10_ID1, val)
+#define bfin_read_CAN1_MB11_DATA0()             bfin_read16(CAN1_MB11_DATA0)
+#define bfin_write_CAN1_MB11_DATA0(val)         bfin_write16(CAN1_MB11_DATA0, val)
+#define bfin_read_CAN1_MB11_DATA1()             bfin_read16(CAN1_MB11_DATA1)
+#define bfin_write_CAN1_MB11_DATA1(val)         bfin_write16(CAN1_MB11_DATA1, val)
+#define bfin_read_CAN1_MB11_DATA2()             bfin_read16(CAN1_MB11_DATA2)
+#define bfin_write_CAN1_MB11_DATA2(val)         bfin_write16(CAN1_MB11_DATA2, val)
+#define bfin_read_CAN1_MB11_DATA3()             bfin_read16(CAN1_MB11_DATA3)
+#define bfin_write_CAN1_MB11_DATA3(val)         bfin_write16(CAN1_MB11_DATA3, val)
+#define bfin_read_CAN1_MB11_LENGTH()            bfin_read16(CAN1_MB11_LENGTH)
+#define bfin_write_CAN1_MB11_LENGTH(val)        bfin_write16(CAN1_MB11_LENGTH, val)
+#define bfin_read_CAN1_MB11_TIMESTAMP()         bfin_read16(CAN1_MB11_TIMESTAMP)
+#define bfin_write_CAN1_MB11_TIMESTAMP(val)     bfin_write16(CAN1_MB11_TIMESTAMP, val)
+#define bfin_read_CAN1_MB11_ID0()               bfin_read16(CAN1_MB11_ID0)
+#define bfin_write_CAN1_MB11_ID0(val)           bfin_write16(CAN1_MB11_ID0, val)
+#define bfin_read_CAN1_MB11_ID1()               bfin_read16(CAN1_MB11_ID1)
+#define bfin_write_CAN1_MB11_ID1(val)           bfin_write16(CAN1_MB11_ID1, val)
+#define bfin_read_CAN1_MB12_DATA0()             bfin_read16(CAN1_MB12_DATA0)
+#define bfin_write_CAN1_MB12_DATA0(val)         bfin_write16(CAN1_MB12_DATA0, val)
+#define bfin_read_CAN1_MB12_DATA1()             bfin_read16(CAN1_MB12_DATA1)
+#define bfin_write_CAN1_MB12_DATA1(val)         bfin_write16(CAN1_MB12_DATA1, val)
+#define bfin_read_CAN1_MB12_DATA2()             bfin_read16(CAN1_MB12_DATA2)
+#define bfin_write_CAN1_MB12_DATA2(val)         bfin_write16(CAN1_MB12_DATA2, val)
+#define bfin_read_CAN1_MB12_DATA3()             bfin_read16(CAN1_MB12_DATA3)
+#define bfin_write_CAN1_MB12_DATA3(val)         bfin_write16(CAN1_MB12_DATA3, val)
+#define bfin_read_CAN1_MB12_LENGTH()            bfin_read16(CAN1_MB12_LENGTH)
+#define bfin_write_CAN1_MB12_LENGTH(val)        bfin_write16(CAN1_MB12_LENGTH, val)
+#define bfin_read_CAN1_MB12_TIMESTAMP()         bfin_read16(CAN1_MB12_TIMESTAMP)
+#define bfin_write_CAN1_MB12_TIMESTAMP(val)     bfin_write16(CAN1_MB12_TIMESTAMP, val)
+#define bfin_read_CAN1_MB12_ID0()               bfin_read16(CAN1_MB12_ID0)
+#define bfin_write_CAN1_MB12_ID0(val)           bfin_write16(CAN1_MB12_ID0, val)
+#define bfin_read_CAN1_MB12_ID1()               bfin_read16(CAN1_MB12_ID1)
+#define bfin_write_CAN1_MB12_ID1(val)           bfin_write16(CAN1_MB12_ID1, val)
+#define bfin_read_CAN1_MB13_DATA0()             bfin_read16(CAN1_MB13_DATA0)
+#define bfin_write_CAN1_MB13_DATA0(val)         bfin_write16(CAN1_MB13_DATA0, val)
+#define bfin_read_CAN1_MB13_DATA1()             bfin_read16(CAN1_MB13_DATA1)
+#define bfin_write_CAN1_MB13_DATA1(val)         bfin_write16(CAN1_MB13_DATA1, val)
+#define bfin_read_CAN1_MB13_DATA2()             bfin_read16(CAN1_MB13_DATA2)
+#define bfin_write_CAN1_MB13_DATA2(val)         bfin_write16(CAN1_MB13_DATA2, val)
+#define bfin_read_CAN1_MB13_DATA3()             bfin_read16(CAN1_MB13_DATA3)
+#define bfin_write_CAN1_MB13_DATA3(val)         bfin_write16(CAN1_MB13_DATA3, val)
+#define bfin_read_CAN1_MB13_LENGTH()            bfin_read16(CAN1_MB13_LENGTH)
+#define bfin_write_CAN1_MB13_LENGTH(val)        bfin_write16(CAN1_MB13_LENGTH, val)
+#define bfin_read_CAN1_MB13_TIMESTAMP()         bfin_read16(CAN1_MB13_TIMESTAMP)
+#define bfin_write_CAN1_MB13_TIMESTAMP(val)     bfin_write16(CAN1_MB13_TIMESTAMP, val)
+#define bfin_read_CAN1_MB13_ID0()               bfin_read16(CAN1_MB13_ID0)
+#define bfin_write_CAN1_MB13_ID0(val)           bfin_write16(CAN1_MB13_ID0, val)
+#define bfin_read_CAN1_MB13_ID1()               bfin_read16(CAN1_MB13_ID1)
+#define bfin_write_CAN1_MB13_ID1(val)           bfin_write16(CAN1_MB13_ID1, val)
+#define bfin_read_CAN1_MB14_DATA0()             bfin_read16(CAN1_MB14_DATA0)
+#define bfin_write_CAN1_MB14_DATA0(val)         bfin_write16(CAN1_MB14_DATA0, val)
+#define bfin_read_CAN1_MB14_DATA1()             bfin_read16(CAN1_MB14_DATA1)
+#define bfin_write_CAN1_MB14_DATA1(val)         bfin_write16(CAN1_MB14_DATA1, val)
+#define bfin_read_CAN1_MB14_DATA2()             bfin_read16(CAN1_MB14_DATA2)
+#define bfin_write_CAN1_MB14_DATA2(val)         bfin_write16(CAN1_MB14_DATA2, val)
+#define bfin_read_CAN1_MB14_DATA3()             bfin_read16(CAN1_MB14_DATA3)
+#define bfin_write_CAN1_MB14_DATA3(val)         bfin_write16(CAN1_MB14_DATA3, val)
+#define bfin_read_CAN1_MB14_LENGTH()            bfin_read16(CAN1_MB14_LENGTH)
+#define bfin_write_CAN1_MB14_LENGTH(val)        bfin_write16(CAN1_MB14_LENGTH, val)
+#define bfin_read_CAN1_MB14_TIMESTAMP()         bfin_read16(CAN1_MB14_TIMESTAMP)
+#define bfin_write_CAN1_MB14_TIMESTAMP(val)     bfin_write16(CAN1_MB14_TIMESTAMP, val)
+#define bfin_read_CAN1_MB14_ID0()               bfin_read16(CAN1_MB14_ID0)
+#define bfin_write_CAN1_MB14_ID0(val)           bfin_write16(CAN1_MB14_ID0, val)
+#define bfin_read_CAN1_MB14_ID1()               bfin_read16(CAN1_MB14_ID1)
+#define bfin_write_CAN1_MB14_ID1(val)           bfin_write16(CAN1_MB14_ID1, val)
+#define bfin_read_CAN1_MB15_DATA0()             bfin_read16(CAN1_MB15_DATA0)
+#define bfin_write_CAN1_MB15_DATA0(val)         bfin_write16(CAN1_MB15_DATA0, val)
+#define bfin_read_CAN1_MB15_DATA1()             bfin_read16(CAN1_MB15_DATA1)
+#define bfin_write_CAN1_MB15_DATA1(val)         bfin_write16(CAN1_MB15_DATA1, val)
+#define bfin_read_CAN1_MB15_DATA2()             bfin_read16(CAN1_MB15_DATA2)
+#define bfin_write_CAN1_MB15_DATA2(val)         bfin_write16(CAN1_MB15_DATA2, val)
+#define bfin_read_CAN1_MB15_DATA3()             bfin_read16(CAN1_MB15_DATA3)
+#define bfin_write_CAN1_MB15_DATA3(val)         bfin_write16(CAN1_MB15_DATA3, val)
+#define bfin_read_CAN1_MB15_LENGTH()            bfin_read16(CAN1_MB15_LENGTH)
+#define bfin_write_CAN1_MB15_LENGTH(val)        bfin_write16(CAN1_MB15_LENGTH, val)
+#define bfin_read_CAN1_MB15_TIMESTAMP()         bfin_read16(CAN1_MB15_TIMESTAMP)
+#define bfin_write_CAN1_MB15_TIMESTAMP(val)     bfin_write16(CAN1_MB15_TIMESTAMP, val)
+#define bfin_read_CAN1_MB15_ID0()               bfin_read16(CAN1_MB15_ID0)
+#define bfin_write_CAN1_MB15_ID0(val)           bfin_write16(CAN1_MB15_ID0, val)
+#define bfin_read_CAN1_MB15_ID1()               bfin_read16(CAN1_MB15_ID1)
+#define bfin_write_CAN1_MB15_ID1(val)           bfin_write16(CAN1_MB15_ID1, val)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define bfin_read_CAN1_MB16_DATA0()             bfin_read16(CAN1_MB16_DATA0)
+#define bfin_write_CAN1_MB16_DATA0(val)         bfin_write16(CAN1_MB16_DATA0, val)
+#define bfin_read_CAN1_MB16_DATA1()             bfin_read16(CAN1_MB16_DATA1)
+#define bfin_write_CAN1_MB16_DATA1(val)         bfin_write16(CAN1_MB16_DATA1, val)
+#define bfin_read_CAN1_MB16_DATA2()             bfin_read16(CAN1_MB16_DATA2)
+#define bfin_write_CAN1_MB16_DATA2(val)         bfin_write16(CAN1_MB16_DATA2, val)
+#define bfin_read_CAN1_MB16_DATA3()             bfin_read16(CAN1_MB16_DATA3)
+#define bfin_write_CAN1_MB16_DATA3(val)         bfin_write16(CAN1_MB16_DATA3, val)
+#define bfin_read_CAN1_MB16_LENGTH()            bfin_read16(CAN1_MB16_LENGTH)
+#define bfin_write_CAN1_MB16_LENGTH(val)        bfin_write16(CAN1_MB16_LENGTH, val)
+#define bfin_read_CAN1_MB16_TIMESTAMP()         bfin_read16(CAN1_MB16_TIMESTAMP)
+#define bfin_write_CAN1_MB16_TIMESTAMP(val)     bfin_write16(CAN1_MB16_TIMESTAMP, val)
+#define bfin_read_CAN1_MB16_ID0()               bfin_read16(CAN1_MB16_ID0)
+#define bfin_write_CAN1_MB16_ID0(val)           bfin_write16(CAN1_MB16_ID0, val)
+#define bfin_read_CAN1_MB16_ID1()               bfin_read16(CAN1_MB16_ID1)
+#define bfin_write_CAN1_MB16_ID1(val)           bfin_write16(CAN1_MB16_ID1, val)
+#define bfin_read_CAN1_MB17_DATA0()             bfin_read16(CAN1_MB17_DATA0)
+#define bfin_write_CAN1_MB17_DATA0(val)         bfin_write16(CAN1_MB17_DATA0, val)
+#define bfin_read_CAN1_MB17_DATA1()             bfin_read16(CAN1_MB17_DATA1)
+#define bfin_write_CAN1_MB17_DATA1(val)         bfin_write16(CAN1_MB17_DATA1, val)
+#define bfin_read_CAN1_MB17_DATA2()             bfin_read16(CAN1_MB17_DATA2)
+#define bfin_write_CAN1_MB17_DATA2(val)         bfin_write16(CAN1_MB17_DATA2, val)
+#define bfin_read_CAN1_MB17_DATA3()             bfin_read16(CAN1_MB17_DATA3)
+#define bfin_write_CAN1_MB17_DATA3(val)         bfin_write16(CAN1_MB17_DATA3, val)
+#define bfin_read_CAN1_MB17_LENGTH()            bfin_read16(CAN1_MB17_LENGTH)
+#define bfin_write_CAN1_MB17_LENGTH(val)        bfin_write16(CAN1_MB17_LENGTH, val)
+#define bfin_read_CAN1_MB17_TIMESTAMP()         bfin_read16(CAN1_MB17_TIMESTAMP)
+#define bfin_write_CAN1_MB17_TIMESTAMP(val)     bfin_write16(CAN1_MB17_TIMESTAMP, val)
+#define bfin_read_CAN1_MB17_ID0()               bfin_read16(CAN1_MB17_ID0)
+#define bfin_write_CAN1_MB17_ID0(val)           bfin_write16(CAN1_MB17_ID0, val)
+#define bfin_read_CAN1_MB17_ID1()               bfin_read16(CAN1_MB17_ID1)
+#define bfin_write_CAN1_MB17_ID1(val)           bfin_write16(CAN1_MB17_ID1, val)
+#define bfin_read_CAN1_MB18_DATA0()             bfin_read16(CAN1_MB18_DATA0)
+#define bfin_write_CAN1_MB18_DATA0(val)         bfin_write16(CAN1_MB18_DATA0, val)
+#define bfin_read_CAN1_MB18_DATA1()             bfin_read16(CAN1_MB18_DATA1)
+#define bfin_write_CAN1_MB18_DATA1(val)         bfin_write16(CAN1_MB18_DATA1, val)
+#define bfin_read_CAN1_MB18_DATA2()             bfin_read16(CAN1_MB18_DATA2)
+#define bfin_write_CAN1_MB18_DATA2(val)         bfin_write16(CAN1_MB18_DATA2, val)
+#define bfin_read_CAN1_MB18_DATA3()             bfin_read16(CAN1_MB18_DATA3)
+#define bfin_write_CAN1_MB18_DATA3(val)         bfin_write16(CAN1_MB18_DATA3, val)
+#define bfin_read_CAN1_MB18_LENGTH()            bfin_read16(CAN1_MB18_LENGTH)
+#define bfin_write_CAN1_MB18_LENGTH(val)        bfin_write16(CAN1_MB18_LENGTH, val)
+#define bfin_read_CAN1_MB18_TIMESTAMP()         bfin_read16(CAN1_MB18_TIMESTAMP)
+#define bfin_write_CAN1_MB18_TIMESTAMP(val)     bfin_write16(CAN1_MB18_TIMESTAMP, val)
+#define bfin_read_CAN1_MB18_ID0()               bfin_read16(CAN1_MB18_ID0)
+#define bfin_write_CAN1_MB18_ID0(val)           bfin_write16(CAN1_MB18_ID0, val)
+#define bfin_read_CAN1_MB18_ID1()               bfin_read16(CAN1_MB18_ID1)
+#define bfin_write_CAN1_MB18_ID1(val)           bfin_write16(CAN1_MB18_ID1, val)
+#define bfin_read_CAN1_MB19_DATA0()             bfin_read16(CAN1_MB19_DATA0)
+#define bfin_write_CAN1_MB19_DATA0(val)         bfin_write16(CAN1_MB19_DATA0, val)
+#define bfin_read_CAN1_MB19_DATA1()             bfin_read16(CAN1_MB19_DATA1)
+#define bfin_write_CAN1_MB19_DATA1(val)         bfin_write16(CAN1_MB19_DATA1, val)
+#define bfin_read_CAN1_MB19_DATA2()             bfin_read16(CAN1_MB19_DATA2)
+#define bfin_write_CAN1_MB19_DATA2(val)         bfin_write16(CAN1_MB19_DATA2, val)
+#define bfin_read_CAN1_MB19_DATA3()             bfin_read16(CAN1_MB19_DATA3)
+#define bfin_write_CAN1_MB19_DATA3(val)         bfin_write16(CAN1_MB19_DATA3, val)
+#define bfin_read_CAN1_MB19_LENGTH()            bfin_read16(CAN1_MB19_LENGTH)
+#define bfin_write_CAN1_MB19_LENGTH(val)        bfin_write16(CAN1_MB19_LENGTH, val)
+#define bfin_read_CAN1_MB19_TIMESTAMP()         bfin_read16(CAN1_MB19_TIMESTAMP)
+#define bfin_write_CAN1_MB19_TIMESTAMP(val)     bfin_write16(CAN1_MB19_TIMESTAMP, val)
+#define bfin_read_CAN1_MB19_ID0()               bfin_read16(CAN1_MB19_ID0)
+#define bfin_write_CAN1_MB19_ID0(val)           bfin_write16(CAN1_MB19_ID0, val)
+#define bfin_read_CAN1_MB19_ID1()               bfin_read16(CAN1_MB19_ID1)
+#define bfin_write_CAN1_MB19_ID1(val)           bfin_write16(CAN1_MB19_ID1, val)
+#define bfin_read_CAN1_MB20_DATA0()             bfin_read16(CAN1_MB20_DATA0)
+#define bfin_write_CAN1_MB20_DATA0(val)         bfin_write16(CAN1_MB20_DATA0, val)
+#define bfin_read_CAN1_MB20_DATA1()             bfin_read16(CAN1_MB20_DATA1)
+#define bfin_write_CAN1_MB20_DATA1(val)         bfin_write16(CAN1_MB20_DATA1, val)
+#define bfin_read_CAN1_MB20_DATA2()             bfin_read16(CAN1_MB20_DATA2)
+#define bfin_write_CAN1_MB20_DATA2(val)         bfin_write16(CAN1_MB20_DATA2, val)
+#define bfin_read_CAN1_MB20_DATA3()             bfin_read16(CAN1_MB20_DATA3)
+#define bfin_write_CAN1_MB20_DATA3(val)         bfin_write16(CAN1_MB20_DATA3, val)
+#define bfin_read_CAN1_MB20_LENGTH()            bfin_read16(CAN1_MB20_LENGTH)
+#define bfin_write_CAN1_MB20_LENGTH(val)        bfin_write16(CAN1_MB20_LENGTH, val)
+#define bfin_read_CAN1_MB20_TIMESTAMP()         bfin_read16(CAN1_MB20_TIMESTAMP)
+#define bfin_write_CAN1_MB20_TIMESTAMP(val)     bfin_write16(CAN1_MB20_TIMESTAMP, val)
+#define bfin_read_CAN1_MB20_ID0()               bfin_read16(CAN1_MB20_ID0)
+#define bfin_write_CAN1_MB20_ID0(val)           bfin_write16(CAN1_MB20_ID0, val)
+#define bfin_read_CAN1_MB20_ID1()               bfin_read16(CAN1_MB20_ID1)
+#define bfin_write_CAN1_MB20_ID1(val)           bfin_write16(CAN1_MB20_ID1, val)
+#define bfin_read_CAN1_MB21_DATA0()             bfin_read16(CAN1_MB21_DATA0)
+#define bfin_write_CAN1_MB21_DATA0(val)         bfin_write16(CAN1_MB21_DATA0, val)
+#define bfin_read_CAN1_MB21_DATA1()             bfin_read16(CAN1_MB21_DATA1)
+#define bfin_write_CAN1_MB21_DATA1(val)         bfin_write16(CAN1_MB21_DATA1, val)
+#define bfin_read_CAN1_MB21_DATA2()             bfin_read16(CAN1_MB21_DATA2)
+#define bfin_write_CAN1_MB21_DATA2(val)         bfin_write16(CAN1_MB21_DATA2, val)
+#define bfin_read_CAN1_MB21_DATA3()             bfin_read16(CAN1_MB21_DATA3)
+#define bfin_write_CAN1_MB21_DATA3(val)         bfin_write16(CAN1_MB21_DATA3, val)
+#define bfin_read_CAN1_MB21_LENGTH()            bfin_read16(CAN1_MB21_LENGTH)
+#define bfin_write_CAN1_MB21_LENGTH(val)        bfin_write16(CAN1_MB21_LENGTH, val)
+#define bfin_read_CAN1_MB21_TIMESTAMP()         bfin_read16(CAN1_MB21_TIMESTAMP)
+#define bfin_write_CAN1_MB21_TIMESTAMP(val)     bfin_write16(CAN1_MB21_TIMESTAMP, val)
+#define bfin_read_CAN1_MB21_ID0()               bfin_read16(CAN1_MB21_ID0)
+#define bfin_write_CAN1_MB21_ID0(val)           bfin_write16(CAN1_MB21_ID0, val)
+#define bfin_read_CAN1_MB21_ID1()               bfin_read16(CAN1_MB21_ID1)
+#define bfin_write_CAN1_MB21_ID1(val)           bfin_write16(CAN1_MB21_ID1, val)
+#define bfin_read_CAN1_MB22_DATA0()             bfin_read16(CAN1_MB22_DATA0)
+#define bfin_write_CAN1_MB22_DATA0(val)         bfin_write16(CAN1_MB22_DATA0, val)
+#define bfin_read_CAN1_MB22_DATA1()             bfin_read16(CAN1_MB22_DATA1)
+#define bfin_write_CAN1_MB22_DATA1(val)         bfin_write16(CAN1_MB22_DATA1, val)
+#define bfin_read_CAN1_MB22_DATA2()             bfin_read16(CAN1_MB22_DATA2)
+#define bfin_write_CAN1_MB22_DATA2(val)         bfin_write16(CAN1_MB22_DATA2, val)
+#define bfin_read_CAN1_MB22_DATA3()             bfin_read16(CAN1_MB22_DATA3)
+#define bfin_write_CAN1_MB22_DATA3(val)         bfin_write16(CAN1_MB22_DATA3, val)
+#define bfin_read_CAN1_MB22_LENGTH()            bfin_read16(CAN1_MB22_LENGTH)
+#define bfin_write_CAN1_MB22_LENGTH(val)        bfin_write16(CAN1_MB22_LENGTH, val)
+#define bfin_read_CAN1_MB22_TIMESTAMP()         bfin_read16(CAN1_MB22_TIMESTAMP)
+#define bfin_write_CAN1_MB22_TIMESTAMP(val)     bfin_write16(CAN1_MB22_TIMESTAMP, val)
+#define bfin_read_CAN1_MB22_ID0()               bfin_read16(CAN1_MB22_ID0)
+#define bfin_write_CAN1_MB22_ID0(val)           bfin_write16(CAN1_MB22_ID0, val)
+#define bfin_read_CAN1_MB22_ID1()               bfin_read16(CAN1_MB22_ID1)
+#define bfin_write_CAN1_MB22_ID1(val)           bfin_write16(CAN1_MB22_ID1, val)
+#define bfin_read_CAN1_MB23_DATA0()             bfin_read16(CAN1_MB23_DATA0)
+#define bfin_write_CAN1_MB23_DATA0(val)         bfin_write16(CAN1_MB23_DATA0, val)
+#define bfin_read_CAN1_MB23_DATA1()             bfin_read16(CAN1_MB23_DATA1)
+#define bfin_write_CAN1_MB23_DATA1(val)         bfin_write16(CAN1_MB23_DATA1, val)
+#define bfin_read_CAN1_MB23_DATA2()             bfin_read16(CAN1_MB23_DATA2)
+#define bfin_write_CAN1_MB23_DATA2(val)         bfin_write16(CAN1_MB23_DATA2, val)
+#define bfin_read_CAN1_MB23_DATA3()             bfin_read16(CAN1_MB23_DATA3)
+#define bfin_write_CAN1_MB23_DATA3(val)         bfin_write16(CAN1_MB23_DATA3, val)
+#define bfin_read_CAN1_MB23_LENGTH()            bfin_read16(CAN1_MB23_LENGTH)
+#define bfin_write_CAN1_MB23_LENGTH(val)        bfin_write16(CAN1_MB23_LENGTH, val)
+#define bfin_read_CAN1_MB23_TIMESTAMP()         bfin_read16(CAN1_MB23_TIMESTAMP)
+#define bfin_write_CAN1_MB23_TIMESTAMP(val)     bfin_write16(CAN1_MB23_TIMESTAMP, val)
+#define bfin_read_CAN1_MB23_ID0()               bfin_read16(CAN1_MB23_ID0)
+#define bfin_write_CAN1_MB23_ID0(val)           bfin_write16(CAN1_MB23_ID0, val)
+#define bfin_read_CAN1_MB23_ID1()               bfin_read16(CAN1_MB23_ID1)
+#define bfin_write_CAN1_MB23_ID1(val)           bfin_write16(CAN1_MB23_ID1, val)
+#define bfin_read_CAN1_MB24_DATA0()             bfin_read16(CAN1_MB24_DATA0)
+#define bfin_write_CAN1_MB24_DATA0(val)         bfin_write16(CAN1_MB24_DATA0, val)
+#define bfin_read_CAN1_MB24_DATA1()             bfin_read16(CAN1_MB24_DATA1)
+#define bfin_write_CAN1_MB24_DATA1(val)         bfin_write16(CAN1_MB24_DATA1, val)
+#define bfin_read_CAN1_MB24_DATA2()             bfin_read16(CAN1_MB24_DATA2)
+#define bfin_write_CAN1_MB24_DATA2(val)         bfin_write16(CAN1_MB24_DATA2, val)
+#define bfin_read_CAN1_MB24_DATA3()             bfin_read16(CAN1_MB24_DATA3)
+#define bfin_write_CAN1_MB24_DATA3(val)         bfin_write16(CAN1_MB24_DATA3, val)
+#define bfin_read_CAN1_MB24_LENGTH()            bfin_read16(CAN1_MB24_LENGTH)
+#define bfin_write_CAN1_MB24_LENGTH(val)        bfin_write16(CAN1_MB24_LENGTH, val)
+#define bfin_read_CAN1_MB24_TIMESTAMP()         bfin_read16(CAN1_MB24_TIMESTAMP)
+#define bfin_write_CAN1_MB24_TIMESTAMP(val)     bfin_write16(CAN1_MB24_TIMESTAMP, val)
+#define bfin_read_CAN1_MB24_ID0()               bfin_read16(CAN1_MB24_ID0)
+#define bfin_write_CAN1_MB24_ID0(val)           bfin_write16(CAN1_MB24_ID0, val)
+#define bfin_read_CAN1_MB24_ID1()               bfin_read16(CAN1_MB24_ID1)
+#define bfin_write_CAN1_MB24_ID1(val)           bfin_write16(CAN1_MB24_ID1, val)
+#define bfin_read_CAN1_MB25_DATA0()             bfin_read16(CAN1_MB25_DATA0)
+#define bfin_write_CAN1_MB25_DATA0(val)         bfin_write16(CAN1_MB25_DATA0, val)
+#define bfin_read_CAN1_MB25_DATA1()             bfin_read16(CAN1_MB25_DATA1)
+#define bfin_write_CAN1_MB25_DATA1(val)         bfin_write16(CAN1_MB25_DATA1, val)
+#define bfin_read_CAN1_MB25_DATA2()             bfin_read16(CAN1_MB25_DATA2)
+#define bfin_write_CAN1_MB25_DATA2(val)         bfin_write16(CAN1_MB25_DATA2, val)
+#define bfin_read_CAN1_MB25_DATA3()             bfin_read16(CAN1_MB25_DATA3)
+#define bfin_write_CAN1_MB25_DATA3(val)         bfin_write16(CAN1_MB25_DATA3, val)
+#define bfin_read_CAN1_MB25_LENGTH()            bfin_read16(CAN1_MB25_LENGTH)
+#define bfin_write_CAN1_MB25_LENGTH(val)        bfin_write16(CAN1_MB25_LENGTH, val)
+#define bfin_read_CAN1_MB25_TIMESTAMP()         bfin_read16(CAN1_MB25_TIMESTAMP)
+#define bfin_write_CAN1_MB25_TIMESTAMP(val)     bfin_write16(CAN1_MB25_TIMESTAMP, val)
+#define bfin_read_CAN1_MB25_ID0()               bfin_read16(CAN1_MB25_ID0)
+#define bfin_write_CAN1_MB25_ID0(val)           bfin_write16(CAN1_MB25_ID0, val)
+#define bfin_read_CAN1_MB25_ID1()               bfin_read16(CAN1_MB25_ID1)
+#define bfin_write_CAN1_MB25_ID1(val)           bfin_write16(CAN1_MB25_ID1, val)
+#define bfin_read_CAN1_MB26_DATA0()             bfin_read16(CAN1_MB26_DATA0)
+#define bfin_write_CAN1_MB26_DATA0(val)         bfin_write16(CAN1_MB26_DATA0, val)
+#define bfin_read_CAN1_MB26_DATA1()             bfin_read16(CAN1_MB26_DATA1)
+#define bfin_write_CAN1_MB26_DATA1(val)         bfin_write16(CAN1_MB26_DATA1, val)
+#define bfin_read_CAN1_MB26_DATA2()             bfin_read16(CAN1_MB26_DATA2)
+#define bfin_write_CAN1_MB26_DATA2(val)         bfin_write16(CAN1_MB26_DATA2, val)
+#define bfin_read_CAN1_MB26_DATA3()             bfin_read16(CAN1_MB26_DATA3)
+#define bfin_write_CAN1_MB26_DATA3(val)         bfin_write16(CAN1_MB26_DATA3, val)
+#define bfin_read_CAN1_MB26_LENGTH()            bfin_read16(CAN1_MB26_LENGTH)
+#define bfin_write_CAN1_MB26_LENGTH(val)        bfin_write16(CAN1_MB26_LENGTH, val)
+#define bfin_read_CAN1_MB26_TIMESTAMP()         bfin_read16(CAN1_MB26_TIMESTAMP)
+#define bfin_write_CAN1_MB26_TIMESTAMP(val)     bfin_write16(CAN1_MB26_TIMESTAMP, val)
+#define bfin_read_CAN1_MB26_ID0()               bfin_read16(CAN1_MB26_ID0)
+#define bfin_write_CAN1_MB26_ID0(val)           bfin_write16(CAN1_MB26_ID0, val)
+#define bfin_read_CAN1_MB26_ID1()               bfin_read16(CAN1_MB26_ID1)
+#define bfin_write_CAN1_MB26_ID1(val)           bfin_write16(CAN1_MB26_ID1, val)
+#define bfin_read_CAN1_MB27_DATA0()             bfin_read16(CAN1_MB27_DATA0)
+#define bfin_write_CAN1_MB27_DATA0(val)         bfin_write16(CAN1_MB27_DATA0, val)
+#define bfin_read_CAN1_MB27_DATA1()             bfin_read16(CAN1_MB27_DATA1)
+#define bfin_write_CAN1_MB27_DATA1(val)         bfin_write16(CAN1_MB27_DATA1, val)
+#define bfin_read_CAN1_MB27_DATA2()             bfin_read16(CAN1_MB27_DATA2)
+#define bfin_write_CAN1_MB27_DATA2(val)         bfin_write16(CAN1_MB27_DATA2, val)
+#define bfin_read_CAN1_MB27_DATA3()             bfin_read16(CAN1_MB27_DATA3)
+#define bfin_write_CAN1_MB27_DATA3(val)         bfin_write16(CAN1_MB27_DATA3, val)
+#define bfin_read_CAN1_MB27_LENGTH()            bfin_read16(CAN1_MB27_LENGTH)
+#define bfin_write_CAN1_MB27_LENGTH(val)        bfin_write16(CAN1_MB27_LENGTH, val)
+#define bfin_read_CAN1_MB27_TIMESTAMP()         bfin_read16(CAN1_MB27_TIMESTAMP)
+#define bfin_write_CAN1_MB27_TIMESTAMP(val)     bfin_write16(CAN1_MB27_TIMESTAMP, val)
+#define bfin_read_CAN1_MB27_ID0()               bfin_read16(CAN1_MB27_ID0)
+#define bfin_write_CAN1_MB27_ID0(val)           bfin_write16(CAN1_MB27_ID0, val)
+#define bfin_read_CAN1_MB27_ID1()               bfin_read16(CAN1_MB27_ID1)
+#define bfin_write_CAN1_MB27_ID1(val)           bfin_write16(CAN1_MB27_ID1, val)
+#define bfin_read_CAN1_MB28_DATA0()             bfin_read16(CAN1_MB28_DATA0)
+#define bfin_write_CAN1_MB28_DATA0(val)         bfin_write16(CAN1_MB28_DATA0, val)
+#define bfin_read_CAN1_MB28_DATA1()             bfin_read16(CAN1_MB28_DATA1)
+#define bfin_write_CAN1_MB28_DATA1(val)         bfin_write16(CAN1_MB28_DATA1, val)
+#define bfin_read_CAN1_MB28_DATA2()             bfin_read16(CAN1_MB28_DATA2)
+#define bfin_write_CAN1_MB28_DATA2(val)         bfin_write16(CAN1_MB28_DATA2, val)
+#define bfin_read_CAN1_MB28_DATA3()             bfin_read16(CAN1_MB28_DATA3)
+#define bfin_write_CAN1_MB28_DATA3(val)         bfin_write16(CAN1_MB28_DATA3, val)
+#define bfin_read_CAN1_MB28_LENGTH()            bfin_read16(CAN1_MB28_LENGTH)
+#define bfin_write_CAN1_MB28_LENGTH(val)        bfin_write16(CAN1_MB28_LENGTH, val)
+#define bfin_read_CAN1_MB28_TIMESTAMP()         bfin_read16(CAN1_MB28_TIMESTAMP)
+#define bfin_write_CAN1_MB28_TIMESTAMP(val)     bfin_write16(CAN1_MB28_TIMESTAMP, val)
+#define bfin_read_CAN1_MB28_ID0()               bfin_read16(CAN1_MB28_ID0)
+#define bfin_write_CAN1_MB28_ID0(val)           bfin_write16(CAN1_MB28_ID0, val)
+#define bfin_read_CAN1_MB28_ID1()               bfin_read16(CAN1_MB28_ID1)
+#define bfin_write_CAN1_MB28_ID1(val)           bfin_write16(CAN1_MB28_ID1, val)
+#define bfin_read_CAN1_MB29_DATA0()             bfin_read16(CAN1_MB29_DATA0)
+#define bfin_write_CAN1_MB29_DATA0(val)         bfin_write16(CAN1_MB29_DATA0, val)
+#define bfin_read_CAN1_MB29_DATA1()             bfin_read16(CAN1_MB29_DATA1)
+#define bfin_write_CAN1_MB29_DATA1(val)         bfin_write16(CAN1_MB29_DATA1, val)
+#define bfin_read_CAN1_MB29_DATA2()             bfin_read16(CAN1_MB29_DATA2)
+#define bfin_write_CAN1_MB29_DATA2(val)         bfin_write16(CAN1_MB29_DATA2, val)
+#define bfin_read_CAN1_MB29_DATA3()             bfin_read16(CAN1_MB29_DATA3)
+#define bfin_write_CAN1_MB29_DATA3(val)         bfin_write16(CAN1_MB29_DATA3, val)
+#define bfin_read_CAN1_MB29_LENGTH()            bfin_read16(CAN1_MB29_LENGTH)
+#define bfin_write_CAN1_MB29_LENGTH(val)        bfin_write16(CAN1_MB29_LENGTH, val)
+#define bfin_read_CAN1_MB29_TIMESTAMP()         bfin_read16(CAN1_MB29_TIMESTAMP)
+#define bfin_write_CAN1_MB29_TIMESTAMP(val)     bfin_write16(CAN1_MB29_TIMESTAMP, val)
+#define bfin_read_CAN1_MB29_ID0()               bfin_read16(CAN1_MB29_ID0)
+#define bfin_write_CAN1_MB29_ID0(val)           bfin_write16(CAN1_MB29_ID0, val)
+#define bfin_read_CAN1_MB29_ID1()               bfin_read16(CAN1_MB29_ID1)
+#define bfin_write_CAN1_MB29_ID1(val)           bfin_write16(CAN1_MB29_ID1, val)
+#define bfin_read_CAN1_MB30_DATA0()             bfin_read16(CAN1_MB30_DATA0)
+#define bfin_write_CAN1_MB30_DATA0(val)         bfin_write16(CAN1_MB30_DATA0, val)
+#define bfin_read_CAN1_MB30_DATA1()             bfin_read16(CAN1_MB30_DATA1)
+#define bfin_write_CAN1_MB30_DATA1(val)         bfin_write16(CAN1_MB30_DATA1, val)
+#define bfin_read_CAN1_MB30_DATA2()             bfin_read16(CAN1_MB30_DATA2)
+#define bfin_write_CAN1_MB30_DATA2(val)         bfin_write16(CAN1_MB30_DATA2, val)
+#define bfin_read_CAN1_MB30_DATA3()             bfin_read16(CAN1_MB30_DATA3)
+#define bfin_write_CAN1_MB30_DATA3(val)         bfin_write16(CAN1_MB30_DATA3, val)
+#define bfin_read_CAN1_MB30_LENGTH()            bfin_read16(CAN1_MB30_LENGTH)
+#define bfin_write_CAN1_MB30_LENGTH(val)        bfin_write16(CAN1_MB30_LENGTH, val)
+#define bfin_read_CAN1_MB30_TIMESTAMP()         bfin_read16(CAN1_MB30_TIMESTAMP)
+#define bfin_write_CAN1_MB30_TIMESTAMP(val)     bfin_write16(CAN1_MB30_TIMESTAMP, val)
+#define bfin_read_CAN1_MB30_ID0()               bfin_read16(CAN1_MB30_ID0)
+#define bfin_write_CAN1_MB30_ID0(val)           bfin_write16(CAN1_MB30_ID0, val)
+#define bfin_read_CAN1_MB30_ID1()               bfin_read16(CAN1_MB30_ID1)
+#define bfin_write_CAN1_MB30_ID1(val)           bfin_write16(CAN1_MB30_ID1, val)
+#define bfin_read_CAN1_MB31_DATA0()             bfin_read16(CAN1_MB31_DATA0)
+#define bfin_write_CAN1_MB31_DATA0(val)         bfin_write16(CAN1_MB31_DATA0, val)
+#define bfin_read_CAN1_MB31_DATA1()             bfin_read16(CAN1_MB31_DATA1)
+#define bfin_write_CAN1_MB31_DATA1(val)         bfin_write16(CAN1_MB31_DATA1, val)
+#define bfin_read_CAN1_MB31_DATA2()             bfin_read16(CAN1_MB31_DATA2)
+#define bfin_write_CAN1_MB31_DATA2(val)         bfin_write16(CAN1_MB31_DATA2, val)
+#define bfin_read_CAN1_MB31_DATA3()             bfin_read16(CAN1_MB31_DATA3)
+#define bfin_write_CAN1_MB31_DATA3(val)         bfin_write16(CAN1_MB31_DATA3, val)
+#define bfin_read_CAN1_MB31_LENGTH()            bfin_read16(CAN1_MB31_LENGTH)
+#define bfin_write_CAN1_MB31_LENGTH(val)        bfin_write16(CAN1_MB31_LENGTH, val)
+#define bfin_read_CAN1_MB31_TIMESTAMP()         bfin_read16(CAN1_MB31_TIMESTAMP)
+#define bfin_write_CAN1_MB31_TIMESTAMP(val)     bfin_write16(CAN1_MB31_TIMESTAMP, val)
+#define bfin_read_CAN1_MB31_ID0()               bfin_read16(CAN1_MB31_ID0)
+#define bfin_write_CAN1_MB31_ID0(val)           bfin_write16(CAN1_MB31_ID0, val)
+#define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
+#define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
+
+/* ATAPI Registers */
+
+#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
+#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
+#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
+#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
+#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
+#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
+#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
+#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
+#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
+#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
+#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
+#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
+#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
+#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
+#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
+
+/* SDH Registers */
+
+#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
+#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
+#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
+#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
+#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
+#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
+#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
+#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
+#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
+#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
+#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
+#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
+#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
+#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
+#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
+#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
+#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
+#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
+#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
+#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
+#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
+#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
+#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
+#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
+#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
+#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
+#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
+#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
+#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
+#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
+#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
+
+/* HOST Port Registers */
+
+#define bfin_read_HOST_CONTROL()        bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)    bfin_write16(HOST_CONTROL, val)
+#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)     bfin_write16(HOST_STATUS, val)
+#define bfin_read_HOST_TIMEOUT()        bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)    bfin_write16(HOST_TIMEOUT, val)
+
+/* USB Control Registers */
+
+#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
+#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
+#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
+#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
+#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
+#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
+#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
+#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
+#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
+#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
+#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
+#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
+#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val)  bfin_write16(USB_GLOBAL_CTL, val)
+
+/* USB Packet Control Registers */
+
+#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
+#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
+#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
+#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
+#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
+#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
+#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
+#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
+#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
+#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
+#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
+#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
+#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
+
+/* USB Endbfin_read_()oint FIFO Registers */
+
+#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
+#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
+#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
+#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
+#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
+#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
+#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
+#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
+
+/* USB OTG Control Registers */
+
+#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
+#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
+
+/* USB Phy Control Registers */
+
+#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
+#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
+#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
+#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
+#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
+#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
+#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
+#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
+
+/* USB Endbfin_read_()oint 0 Control Registers */
+
+#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
+#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
+#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 1 Control Registers */
+
+#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
+#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
+#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 2 Control Registers */
+
+#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
+#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
+#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 3 Control Registers */
+
+#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
+#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
+#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 4 Control Registers */
+
+#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
+#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
+#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 5 Control Registers */
+
+#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
+#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
+#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 6 Control Registers */
+
+#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
+#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
+#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 7 Control Registers */
+
+#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
+#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
+#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
+
+/* USB Channel 0 Config Registers */
+
+#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
+#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
+#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
+#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
+#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
+#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
+#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
+#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
+#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
+#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
+
+/* USB Channel 1 Config Registers */
+
+#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
+#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
+#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
+#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
+#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
+#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
+#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
+#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
+#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
+#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
+
+/* USB Channel 2 Config Registers */
+
+#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
+#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
+#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
+#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
+#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
+#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
+#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
+#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
+#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
+#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
+
+/* USB Channel 3 Config Registers */
+
+#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
+#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
+#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
+#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
+#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
+#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
+#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
+#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
+#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
+#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
+
+/* USB Channel 4 Config Registers */
+
+#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
+#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
+#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
+#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
+#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
+#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
+#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
+#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
+#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
+#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
+
+/* USB Channel 5 Config Registers */
+
+#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
+#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
+#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
+#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
+#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
+#define bfin_write_USB_DMA5ADDRHIGH(val)                bfin_write16(USB_DMA5ADDRHIGH, val)
+#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
+#define bfin_write_USB_DMA5COUNTLOW(val)        fin_write16(USB_DMA5COUNTLOW, val)
+#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
+#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
+
+/* USB Channel 6 Config Registers */
+
+#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
+#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
+#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
+#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
+#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
+#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
+#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
+#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
+#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
+#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
+
+/* USB Channel 7 Config Registers */
+
+#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
+#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
+#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
+#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
+#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
+#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
+#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
+#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
+#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
+#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
+
+/* Keybfin_read_()ad Registers */
+
+#define bfin_read_KPAD_CTL()            bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)        bfin_write16(KPAD_CTL, val)
+#define bfin_read_KPAD_PRESCALE()       bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)   bfin_write16(KPAD_PRESCALE, val)
+#define bfin_read_KPAD_MSEL()           bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)       bfin_write16(KPAD_MSEL, val)
+#define bfin_read_KPAD_ROWCOL()         bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)     bfin_write16(KPAD_ROWCOL, val)
+#define bfin_read_KPAD_STAT()           bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)       bfin_write16(KPAD_STAT, val)
+#define bfin_read_KPAD_SOFTEVAL()       bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)   bfin_write16(KPAD_SOFTEVAL, val)
+
+/* Pixel Combfin_read_()ositor (PIXC) Registers */
+
+#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
+#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
+#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
+#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
+#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
+#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
+#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
+#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
+#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
+#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
+#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
+#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
+#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
+#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
+#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
+#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
+#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
+#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
+#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
+
+/* Handshake MDMA 0 Registers */
+
+#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
+
+/* Handshake MDMA 1 Registers */
+
+#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
+
+#endif /* _CDEF_BF549_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
new file mode 100644
index 000000000000..6bbcefeb3627
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -0,0 +1,2722 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF54X_H
+#define _CDEF_BF54X_H
+
+#include <defBF54x_base.h>
+
+/* ************************************************************** */
+/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
+/* ************************************************************** */
+
+/* PLL Registers */
+
+#define bfin_read_PLL_CTL()             bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)         bfin_write16(PLL_CTL, val)
+#define bfin_read_PLL_DIV()             bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)         bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL()              bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)          bfin_write16(VR_CTL, val)
+#define bfin_read_PLL_STAT()            bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)        bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT()         bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)     bfin_write16(PLL_LOCKCNT, val)
+
+/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
+
+#define bfin_read_CHIPID()              bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)          bfin_write32(CHIPID, val)
+
+/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
+
+#define bfin_read_SWRST()               bfin_read16(SWRST)
+#define bfin_write_SWRST(val)           bfin_write16(SWRST, val)
+#define bfin_read_SYSCR()               bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)           bfin_write16(SYSCR, val)
+
+/* SIC Registers */
+
+#define bfin_read_SIC_IMASK0()          bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)      bfin_write32(SIC_IMASK0, val)
+#define bfin_read_SIC_IMASK1()          bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)      bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_IMASK2()          bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)      bfin_write32(SIC_IMASK2, val)
+#define bfin_read_SIC_ISR0()            bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)        bfin_write32(SIC_ISR0, val)
+#define bfin_read_SIC_ISR1()            bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)        bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_ISR2()            bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)        bfin_write32(SIC_ISR2, val)
+#define bfin_read_SIC_IWR0()            bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)        bfin_write32(SIC_IWR0, val)
+#define bfin_read_SIC_IWR1()            bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)        bfin_write32(SIC_IWR1, val)
+#define bfin_read_SIC_IWR2()            bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)        bfin_write32(SIC_IWR2, val)
+#define bfin_read_SIC_IAR0()            bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)        bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1()            bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)        bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2()            bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)        bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3()            bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)        bfin_write32(SIC_IAR3, val)
+#define bfin_read_SIC_IAR4()            bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)        bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5()            bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)        bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6()            bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)        bfin_write32(SIC_IAR6, val)
+#define bfin_read_SIC_IAR7()            bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)        bfin_write32(SIC_IAR7, val)
+#define bfin_read_SIC_IAR8()            bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)        bfin_write32(SIC_IAR8, val)
+#define bfin_read_SIC_IAR9()            bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)        bfin_write32(SIC_IAR9, val)
+#define bfin_read_SIC_IAR10()           bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)       bfin_write32(SIC_IAR10, val)
+#define bfin_read_SIC_IAR11()           bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)       bfin_write32(SIC_IAR11, val)
+
+/* Watchdog Timer Registers */
+
+#define bfin_read_WDOG_CTL()            bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)        bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT()            bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)        bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT()           bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)       bfin_write32(WDOG_STAT, val)
+
+/* RTC Registers */
+
+#define bfin_read_RTC_STAT()            bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)        bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL()            bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)        bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT()           bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)       bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT()           bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)       bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM()           bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)       bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_PREN()            bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)        bfin_write16(RTC_PREN, val)
+
+/* UART0 Registers */
+
+#define bfin_read_UART0_DLL()           bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)       bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_DLH()           bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)       bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_GCTL()          bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)      bfin_write16(UART0_GCTL, val)
+#define bfin_read_UART0_LCR()           bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)       bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR()           bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)       bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR()           bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)       bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_MSR()           bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)       bfin_write16(UART0_MSR, val)
+#define bfin_read_UART0_SCR()           bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)       bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_IER_SET()       bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)   bfin_write16(UART0_IER_SET, val)
+#define bfin_read_UART0_IER_CLEAR()     bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define bfin_read_UART0_THR()           bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)       bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR()           bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)       bfin_write16(UART0_RBR, val)
+
+/* SPI0 Registers */
+
+#define bfin_read_SPI0_CTL()            bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)        bfin_write16(SPI0_CTL, val)
+#define bfin_read_SPI0_FLG()            bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)        bfin_write16(SPI0_FLG, val)
+#define bfin_read_SPI0_STAT()           bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)       bfin_write16(SPI0_STAT, val)
+#define bfin_read_SPI0_TDBR()           bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)       bfin_write16(SPI0_TDBR, val)
+#define bfin_read_SPI0_RDBR()           bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)       bfin_write16(SPI0_RDBR, val)
+#define bfin_read_SPI0_BAUD()           bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)       bfin_write16(SPI0_BAUD, val)
+#define bfin_read_SPI0_SHADOW()         bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)     bfin_write16(SPI0_SHADOW, val)
+
+/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
+
+/* Two Wire Interface Registers (TWI0) */
+
+#define bfin_read_TWI0_CLKDIV()                 bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)             bfin_write16(TWI0_CLKDIV, val)
+#define bfin_read_TWI0_CONTROL()                bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)            bfin_write16(TWI0_CONTROL, val)
+#define bfin_read_TWI0_SLAVE_CTRL()             bfin_read16(TWI0_SLAVE_CTRL)
+#define bfin_write_TWI0_SLAVE_CTRL(val)         bfin_write16(TWI0_SLAVE_CTRL, val)
+#define bfin_read_TWI0_SLAVE_STAT()             bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val)         bfin_write16(TWI0_SLAVE_STAT, val)
+#define bfin_read_TWI0_SLAVE_ADDR()             bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val)         bfin_write16(TWI0_SLAVE_ADDR, val)
+#define bfin_read_TWI0_MASTER_CTRL()            bfin_read16(TWI0_MASTER_CTRL)
+#define bfin_write_TWI0_MASTER_CTRL(val)        bfin_write16(TWI0_MASTER_CTRL, val)
+#define bfin_read_TWI0_MASTER_STAT()            bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val)        bfin_write16(TWI0_MASTER_STAT, val)
+#define bfin_read_TWI0_MASTER_ADDR()            bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val)        bfin_write16(TWI0_MASTER_ADDR, val)
+#define bfin_read_TWI0_INT_STAT()               bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)           bfin_write16(TWI0_INT_STAT, val)
+#define bfin_read_TWI0_INT_MASK()               bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)           bfin_write16(TWI0_INT_MASK, val)
+#define bfin_read_TWI0_FIFO_CTRL()              bfin_read16(TWI0_FIFO_CTRL)
+#define bfin_write_TWI0_FIFO_CTRL(val)          bfin_write16(TWI0_FIFO_CTRL, val)
+#define bfin_read_TWI0_FIFO_STAT()              bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val)          bfin_write16(TWI0_FIFO_STAT, val)
+#define bfin_read_TWI0_XMT_DATA8()              bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val)          bfin_write16(TWI0_XMT_DATA8, val)
+#define bfin_read_TWI0_XMT_DATA16()             bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val)         bfin_write16(TWI0_XMT_DATA16, val)
+#define bfin_read_TWI0_RCV_DATA8()              bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val)          bfin_write16(TWI0_RCV_DATA8, val)
+#define bfin_read_TWI0_RCV_DATA16()             bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val)         bfin_write16(TWI0_RCV_DATA16, val)
+
+/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
+
+/* SPORT1 Registers */
+
+#define bfin_read_SPORT1_TCR1()         bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)     bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2()         bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)     bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV()      bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)  bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV()       bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)   bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_read_SPORT1_TX()           bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)       bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX()           bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)       bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1()         bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)     bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2()         bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)     bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV()      bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)  bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV()       bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)   bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT()         bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)     bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL()         bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)     bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1()        bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)    bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2()        bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)    bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0()        bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)    bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1()        bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)    bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2()        bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)    bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3()        bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)    bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0()        bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)    bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1()        bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)    bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2()        bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)    bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3()        bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)    bfin_write32(SPORT1_MRCS3, val)
+
+/* Asynchronous Memory Control Registers */
+
+#define bfin_read_EBIU_AMGCTL()         bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)     bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0()        bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)    bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1()        bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)    bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_MBSCTL()         bfin_read16(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)     bfin_write16(EBIU_MBSCTL, val)
+#define bfin_read_EBIU_ARBSTAT()        bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)    bfin_write32(EBIU_ARBSTAT, val)
+#define bfin_read_EBIU_MODE()           bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)       bfin_write32(EBIU_MODE, val)
+#define bfin_read_EBIU_FCTL()           bfin_read16(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)       bfin_write16(EBIU_FCTL, val)
+
+/* DDR Memory Control Registers */
+
+#define bfin_read_EBIU_DDRCTL0()        bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)    bfin_write32(EBIU_DDRCTL0, val)
+#define bfin_read_EBIU_DDRCTL1()        bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)    bfin_write32(EBIU_DDRCTL1, val)
+#define bfin_read_EBIU_DDRCTL2()        bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)    bfin_write32(EBIU_DDRCTL2, val)
+#define bfin_read_EBIU_DDRCTL3()        bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)    bfin_write32(EBIU_DDRCTL3, val)
+#define bfin_read_EBIU_DDRQUE()         bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)     bfin_write32(EBIU_DDRQUE, val)
+#define bfin_read_EBIU_ERRADD()         bfin_read32(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)     bfin_write32(EBIU_ERRADD)
+#define bfin_read_EBIU_ERRMST()         bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)     bfin_write16(EBIU_ERRMST, val)
+#define bfin_read_EBIU_RSTCTL()         bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)     bfin_write16(EBIU_RSTCTL, val)
+
+/* DDR BankRead and Write Count Registers */
+
+#define bfin_read_EBIU_DDRBRC0()        bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)    bfin_write32(EBIU_DDRBRC0, val)
+#define bfin_read_EBIU_DDRBRC1()        bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)    bfin_write32(EBIU_DDRBRC1, val)
+#define bfin_read_EBIU_DDRBRC2()        bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)    bfin_write32(EBIU_DDRBRC2, val)
+#define bfin_read_EBIU_DDRBRC3()        bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)    bfin_write32(EBIU_DDRBRC3, val)
+#define bfin_read_EBIU_DDRBRC4()        bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)    bfin_write32(EBIU_DDRBRC4, val)
+#define bfin_read_EBIU_DDRBRC5()        bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)    bfin_write32(EBIU_DDRBRC5, val)
+#define bfin_read_EBIU_DDRBRC6()        bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)    bfin_write32(EBIU_DDRBRC6, val)
+#define bfin_read_EBIU_DDRBRC7()        bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)    bfin_write32(EBIU_DDRBRC7, val)
+#define bfin_read_EBIU_DDRBWC0()        bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)    bfin_write32(EBIU_DDRBWC0, val)
+#define bfin_read_EBIU_DDRBWC1()        bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)    bfin_write32(EBIU_DDRBWC1, val)
+#define bfin_read_EBIU_DDRBWC2()        bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)    bfin_write32(EBIU_DDRBWC2, val)
+#define bfin_read_EBIU_DDRBWC3()        bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)    bfin_write32(EBIU_DDRBWC3, val)
+#define bfin_read_EBIU_DDRBWC4()        bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)    bfin_write32(EBIU_DDRBWC4, val)
+#define bfin_read_EBIU_DDRBWC5()        bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)    bfin_write32(EBIU_DDRBWC5, val)
+#define bfin_read_EBIU_DDRBWC6()        bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)    bfin_write32(EBIU_DDRBWC6, val)
+#define bfin_read_EBIU_DDRBWC7()        bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)    bfin_write32(EBIU_DDRBWC7, val)
+#define bfin_read_EBIU_DDRACCT()        bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)    bfin_write32(EBIU_DDRACCT, val)
+#define bfin_read_EBIU_DDRTACT()        bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)    bfin_write32(EBIU_DDRTACT, val)
+#define bfin_read_EBIU_DDRARCT()        bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)    bfin_write32(EBIU_DDRARCT, val)
+#define bfin_read_EBIU_DDRGC0()         bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)     bfin_write32(EBIU_DDRGC0, val)
+#define bfin_read_EBIU_DDRGC1()         bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)     bfin_write32(EBIU_DDRGC1, val)
+#define bfin_read_EBIU_DDRGC2()         bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)     bfin_write32(EBIU_DDRGC2, val)
+#define bfin_read_EBIU_DDRGC3()         bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)     bfin_write32(EBIU_DDRGC3, val)
+#define bfin_read_EBIU_DDRMCEN()        bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)    bfin_write32(EBIU_DDRMCEN, val)
+#define bfin_read_EBIU_DDRMCCL()        bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)    bfin_write32(EBIU_DDRMCCL, val)
+
+/* DMAC0 Registers */
+
+#define bfin_read_DMAC0_TCPER()         bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)     bfin_write16(DMAC0_TCPER, val)
+#define bfin_read_DMAC0_TCCNT()         bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)     bfin_write16(DMAC0_TCCNT, val)
+
+/* DMA Channel 0 Registers */
+
+#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR)
+#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR)
+#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY)
+#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY)
+#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR)
+#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR)
+#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
+
+/* DMA Channel 1 Registers */
+
+#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR)
+#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR)
+#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY)
+#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY)
+#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR)
+#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR)
+#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
+
+/* DMA Channel 2 Registers */
+
+#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR)
+#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR)
+#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY)
+#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY)
+#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR)
+#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR)
+#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
+
+/* DMA Channel 3 Registers */
+
+#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR)
+#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR)
+#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY)
+#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY)
+#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR)
+#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR)
+#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
+
+/* DMA Channel 4 Registers */
+
+#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR)
+#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR)
+#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY)
+#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY)
+#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR)
+#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR)
+#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
+
+/* DMA Channel 5 Registers */
+
+#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR)
+#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR)
+#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY)
+#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY)
+#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR)
+#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR)
+#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
+
+/* DMA Channel 6 Registers */
+
+#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR)
+#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR)
+#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY)
+#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY)
+#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR)
+#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR)
+#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
+
+/* DMA Channel 7 Registers */
+
+#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR)
+#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR)
+#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY)
+#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY)
+#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR)
+#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR)
+#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
+
+/* DMA Channel 8 Registers */
+
+#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR)
+#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR)
+#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
+#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY)
+#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY)
+#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR)
+#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR)
+#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
+
+/* DMA Channel 9 Registers */
+
+#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR)
+#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR)
+#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
+#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY)
+#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY)
+#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR)
+#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR)
+#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
+
+/* DMA Channel 10 Registers */
+
+#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR)
+#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR)
+#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
+#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY)
+#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY)
+#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR)
+#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR)
+#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
+
+/* DMA Channel 11 Registers */
+
+#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR)
+#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR)
+#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
+#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY)
+#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY)
+#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR)
+#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR)
+#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
+
+/* MDMA Stream 0 Registers */
+
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR)
+#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY)
+#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR)
+#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR)
+#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY)
+#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR)
+#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+
+/* MDMA Stream 1 Registers */
+
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR)
+#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY)
+#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR)
+#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR)
+#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY)
+#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR)
+#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+
+/* EPPI1 Registers */
+
+#define bfin_read_EPPI1_STATUS()                bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)            bfin_write16(EPPI1_STATUS, val)
+#define bfin_read_EPPI1_HCOUNT()                bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)            bfin_write16(EPPI1_HCOUNT, val)
+#define bfin_read_EPPI1_HDELAY()                bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)            bfin_write16(EPPI1_HDELAY, val)
+#define bfin_read_EPPI1_VCOUNT()                bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)            bfin_write16(EPPI1_VCOUNT, val)
+#define bfin_read_EPPI1_VDELAY()                bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)            bfin_write16(EPPI1_VDELAY, val)
+#define bfin_read_EPPI1_FRAME()                 bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)             bfin_write16(EPPI1_FRAME, val)
+#define bfin_read_EPPI1_LINE()                  bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)              bfin_write16(EPPI1_LINE, val)
+#define bfin_read_EPPI1_CLKDIV()                bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)            bfin_write16(EPPI1_CLKDIV, val)
+#define bfin_read_EPPI1_CONTROL()               bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)           bfin_write32(EPPI1_CONTROL, val)
+#define bfin_read_EPPI1_FS1W_HBL()              bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val)          bfin_write32(EPPI1_FS1W_HBL, val)
+#define bfin_read_EPPI1_FS1P_AVPL()             bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val)         bfin_write32(EPPI1_FS1P_AVPL, val)
+#define bfin_read_EPPI1_FS2W_LVB()              bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val)          bfin_write32(EPPI1_FS2W_LVB, val)
+#define bfin_read_EPPI1_FS2P_LAVF()             bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val)         bfin_write32(EPPI1_FS2P_LAVF, val)
+#define bfin_read_EPPI1_CLIP()                  bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)              bfin_write32(EPPI1_CLIP, val)
+
+/* Port Interrubfin_read_()t 0 Registers (32-bit) */
+
+#define bfin_read_PINT0_MASK_SET()              bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val)          bfin_write32(PINT0_MASK_SET, val)
+#define bfin_read_PINT0_MASK_CLEAR()            bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val)        bfin_write32(PINT0_MASK_CLEAR, val)
+#define bfin_read_PINT0_REQUEST()               bfin_read32(PINT0_REQUEST)
+#define bfin_write_PINT0_REQUEST(val)           bfin_write32(PINT0_REQUEST, val)
+#define bfin_read_PINT0_ASSIGN()                bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)            bfin_write32(PINT0_ASSIGN, val)
+#define bfin_read_PINT0_EDGE_SET()              bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val)          bfin_write32(PINT0_EDGE_SET, val)
+#define bfin_read_PINT0_EDGE_CLEAR()            bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val)        bfin_write32(PINT0_EDGE_CLEAR, val)
+#define bfin_read_PINT0_INVERT_SET()            bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val)        bfin_write32(PINT0_INVERT_SET, val)
+#define bfin_read_PINT0_INVERT_CLEAR()          bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val)      bfin_write32(PINT0_INVERT_CLEAR, val)
+#define bfin_read_PINT0_PINSTATE()              bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val)          bfin_write32(PINT0_PINSTATE, val)
+#define bfin_read_PINT0_LATCH()                 bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)             bfin_write32(PINT0_LATCH, val)
+
+/* Port Interrubfin_read_()t 1 Registers (32-bit) */
+
+#define bfin_read_PINT1_MASK_SET()              bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val)          bfin_write32(PINT1_MASK_SET, val)
+#define bfin_read_PINT1_MASK_CLEAR()            bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val)        bfin_write32(PINT1_MASK_CLEAR, val)
+#define bfin_read_PINT1_REQUEST()               bfin_read32(PINT1_REQUEST)
+#define bfin_write_PINT1_REQUEST(val)           bfin_write32(PINT1_REQUEST, val)
+#define bfin_read_PINT1_ASSIGN()                bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)            bfin_write32(PINT1_ASSIGN, val)
+#define bfin_read_PINT1_EDGE_SET()              bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val)          bfin_write32(PINT1_EDGE_SET, val)
+#define bfin_read_PINT1_EDGE_CLEAR()            bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val)        bfin_write32(PINT1_EDGE_CLEAR, val)
+#define bfin_read_PINT1_INVERT_SET()            bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val)        bfin_write32(PINT1_INVERT_SET, val)
+#define bfin_read_PINT1_INVERT_CLEAR()          bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val)      bfin_write32(PINT1_INVERT_CLEAR, val)
+#define bfin_read_PINT1_PINSTATE()              bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val)          bfin_write32(PINT1_PINSTATE, val)
+#define bfin_read_PINT1_LATCH()                 bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)             bfin_write32(PINT1_LATCH, val)
+
+/* Port Interrubfin_read_()t 2 Registers (32-bit) */
+
+#define bfin_read_PINT2_MASK_SET()              bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val)          bfin_write32(PINT2_MASK_SET, val)
+#define bfin_read_PINT2_MASK_CLEAR()            bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val)        bfin_write32(PINT2_MASK_CLEAR, val)
+#define bfin_read_PINT2_REQUEST()               bfin_read32(PINT2_REQUEST)
+#define bfin_write_PINT2_REQUEST(val)           bfin_write32(PINT2_REQUEST, val)
+#define bfin_read_PINT2_ASSIGN()                bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)            bfin_write32(PINT2_ASSIGN, val)
+#define bfin_read_PINT2_EDGE_SET()              bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val)          bfin_write32(PINT2_EDGE_SET, val)
+#define bfin_read_PINT2_EDGE_CLEAR()            bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val)        bfin_write32(PINT2_EDGE_CLEAR, val)
+#define bfin_read_PINT2_INVERT_SET()            bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val)        bfin_write32(PINT2_INVERT_SET, val)
+#define bfin_read_PINT2_INVERT_CLEAR()          bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val)      bfin_write32(PINT2_INVERT_CLEAR, val)
+#define bfin_read_PINT2_PINSTATE()              bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val)          bfin_write32(PINT2_PINSTATE, val)
+#define bfin_read_PINT2_LATCH()                 bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)             bfin_write32(PINT2_LATCH, val)
+
+/* Port Interrubfin_read_()t 3 Registers (32-bit) */
+
+#define bfin_read_PINT3_MASK_SET()              bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val)          bfin_write32(PINT3_MASK_SET, val)
+#define bfin_read_PINT3_MASK_CLEAR()            bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val)        bfin_write32(PINT3_MASK_CLEAR, val)
+#define bfin_read_PINT3_REQUEST()               bfin_read32(PINT3_REQUEST)
+#define bfin_write_PINT3_REQUEST(val)           bfin_write32(PINT3_REQUEST, val)
+#define bfin_read_PINT3_ASSIGN()                bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)            bfin_write32(PINT3_ASSIGN, val)
+#define bfin_read_PINT3_EDGE_SET()              bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val)          bfin_write32(PINT3_EDGE_SET, val)
+#define bfin_read_PINT3_EDGE_CLEAR()            bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val)        bfin_write32(PINT3_EDGE_CLEAR, val)
+#define bfin_read_PINT3_INVERT_SET()            bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val)        bfin_write32(PINT3_INVERT_SET, val)
+#define bfin_read_PINT3_INVERT_CLEAR()          bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val)      bfin_write32(PINT3_INVERT_CLEAR, val)
+#define bfin_read_PINT3_PINSTATE()              bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val)          bfin_write32(PINT3_PINSTATE, val)
+#define bfin_read_PINT3_LATCH()                 bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)             bfin_write32(PINT3_LATCH, val)
+
+/* Port A Registers */
+
+#define bfin_read_PORTA_FER()           bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)       bfin_write16(PORTA_FER, val)
+#define bfin_read_PORTA()               bfin_read16(PORTA)
+#define bfin_write_PORTA(val)           bfin_write16(PORTA, val)
+#define bfin_read_PORTA_SET()           bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)       bfin_write16(PORTA_SET, val)
+#define bfin_read_PORTA_CLEAR()         bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)     bfin_write16(PORTA_CLEAR, val)
+#define bfin_read_PORTA_DIR_SET()       bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)   bfin_write16(PORTA_DIR_SET, val)
+#define bfin_read_PORTA_DIR_CLEAR()     bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define bfin_read_PORTA_INEN()          bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)      bfin_write16(PORTA_INEN, val)
+#define bfin_read_PORTA_MUX()           bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)       bfin_write32(PORTA_MUX, val)
+
+/* Port B Registers */
+
+#define bfin_read_PORTB_FER()           bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)       bfin_write16(PORTB_FER, val)
+#define bfin_read_PORTB()               bfin_read16(PORTB)
+#define bfin_write_PORTB(val)           bfin_write16(PORTB, val)
+#define bfin_read_PORTB_SET()           bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)       bfin_write16(PORTB_SET, val)
+#define bfin_read_PORTB_CLEAR()         bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)     bfin_write16(PORTB_CLEAR, val)
+#define bfin_read_PORTB_DIR_SET()       bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)   bfin_write16(PORTB_DIR_SET, val)
+#define bfin_read_PORTB_DIR_CLEAR()     bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define bfin_read_PORTB_INEN()          bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)      bfin_write16(PORTB_INEN, val)
+#define bfin_read_PORTB_MUX()           bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)       bfin_write32(PORTB_MUX, val)
+
+/* Port C Registers */
+
+#define bfin_read_PORTC_FER()           bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)       bfin_write16(PORTC_FER, val)
+#define bfin_read_PORTC()               bfin_read16(PORTC)
+#define bfin_write_PORTC(val)           bfin_write16(PORTC, val)
+#define bfin_read_PORTC_SET()           bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)       bfin_write16(PORTC_SET, val)
+#define bfin_read_PORTC_CLEAR()         bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)     bfin_write16(PORTC_CLEAR, val)
+#define bfin_read_PORTC_DIR_SET()       bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)   bfin_write16(PORTC_DIR_SET, val)
+#define bfin_read_PORTC_DIR_CLEAR()     bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define bfin_read_PORTC_INEN()          bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)      bfin_write16(PORTC_INEN, val)
+#define bfin_read_PORTC_MUX()           bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)       bfin_write32(PORTC_MUX, val)
+
+/* Port D Registers */
+
+#define bfin_read_PORTD_FER()           bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)       bfin_write16(PORTD_FER, val)
+#define bfin_read_PORTD()               bfin_read16(PORTD)
+#define bfin_write_PORTD(val)           bfin_write16(PORTD, val)
+#define bfin_read_PORTD_SET()           bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)       bfin_write16(PORTD_SET, val)
+#define bfin_read_PORTD_CLEAR()         bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)     bfin_write16(PORTD_CLEAR, val)
+#define bfin_read_PORTD_DIR_SET()       bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)   bfin_write16(PORTD_DIR_SET, val)
+#define bfin_read_PORTD_DIR_CLEAR()     bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define bfin_read_PORTD_INEN()          bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)      bfin_write16(PORTD_INEN, val)
+#define bfin_read_PORTD_MUX()           bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)       bfin_write32(PORTD_MUX, val)
+
+/* Port E Registers */
+
+#define bfin_read_PORTE_FER()           bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)       bfin_write16(PORTE_FER, val)
+#define bfin_read_PORTE()               bfin_read16(PORTE)
+#define bfin_write_PORTE(val)           bfin_write16(PORTE, val)
+#define bfin_read_PORTE_SET()           bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)       bfin_write16(PORTE_SET, val)
+#define bfin_read_PORTE_CLEAR()         bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)     bfin_write16(PORTE_CLEAR, val)
+#define bfin_read_PORTE_DIR_SET()       bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)   bfin_write16(PORTE_DIR_SET, val)
+#define bfin_read_PORTE_DIR_CLEAR()     bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define bfin_read_PORTE_INEN()          bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)      bfin_write16(PORTE_INEN, val)
+#define bfin_read_PORTE_MUX()           bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)       bfin_write32(PORTE_MUX, val)
+
+/* Port F Registers */
+
+#define bfin_read_PORTF_FER()           bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)       bfin_write16(PORTF_FER, val)
+#define bfin_read_PORTF()               bfin_read16(PORTF)
+#define bfin_write_PORTF(val)           bfin_write16(PORTF, val)
+#define bfin_read_PORTF_SET()           bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)       bfin_write16(PORTF_SET, val)
+#define bfin_read_PORTF_CLEAR()         bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)     bfin_write16(PORTF_CLEAR, val)
+#define bfin_read_PORTF_DIR_SET()       bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)   bfin_write16(PORTF_DIR_SET, val)
+#define bfin_read_PORTF_DIR_CLEAR()     bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define bfin_read_PORTF_INEN()          bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)      bfin_write16(PORTF_INEN, val)
+#define bfin_read_PORTF_MUX()           bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)       bfin_write32(PORTF_MUX, val)
+
+/* Port G Registers */
+
+#define bfin_read_PORTG_FER()           bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)       bfin_write16(PORTG_FER, val)
+#define bfin_read_PORTG()               bfin_read16(PORTG)
+#define bfin_write_PORTG(val)           bfin_write16(PORTG, val)
+#define bfin_read_PORTG_SET()           bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)       bfin_write16(PORTG_SET, val)
+#define bfin_read_PORTG_CLEAR()         bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)     bfin_write16(PORTG_CLEAR, val)
+#define bfin_read_PORTG_DIR_SET()       bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)   bfin_write16(PORTG_DIR_SET, val)
+#define bfin_read_PORTG_DIR_CLEAR()     bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define bfin_read_PORTG_INEN()          bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)      bfin_write16(PORTG_INEN, val)
+#define bfin_read_PORTG_MUX()           bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)       bfin_write32(PORTG_MUX, val)
+
+/* Port H Registers */
+
+#define bfin_read_PORTH_FER()           bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)       bfin_write16(PORTH_FER, val)
+#define bfin_read_PORTH()               bfin_read16(PORTH)
+#define bfin_write_PORTH(val)           bfin_write16(PORTH, val)
+#define bfin_read_PORTH_SET()           bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)       bfin_write16(PORTH_SET, val)
+#define bfin_read_PORTH_CLEAR()         bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)     bfin_write16(PORTH_CLEAR, val)
+#define bfin_read_PORTH_DIR_SET()       bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)   bfin_write16(PORTH_DIR_SET, val)
+#define bfin_read_PORTH_DIR_CLEAR()     bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define bfin_read_PORTH_INEN()          bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)      bfin_write16(PORTH_INEN, val)
+#define bfin_read_PORTH_MUX()           bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)       bfin_write32(PORTH_MUX, val)
+
+/* Port I Registers */
+
+#define bfin_read_PORTI_FER()           bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)       bfin_write16(PORTI_FER, val)
+#define bfin_read_PORTI()               bfin_read16(PORTI)
+#define bfin_write_PORTI(val)           bfin_write16(PORTI, val)
+#define bfin_read_PORTI_SET()           bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)       bfin_write16(PORTI_SET, val)
+#define bfin_read_PORTI_CLEAR()         bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)     bfin_write16(PORTI_CLEAR, val)
+#define bfin_read_PORTI_DIR_SET()       bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)   bfin_write16(PORTI_DIR_SET, val)
+#define bfin_read_PORTI_DIR_CLEAR()     bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define bfin_read_PORTI_INEN()          bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)      bfin_write16(PORTI_INEN, val)
+#define bfin_read_PORTI_MUX()           bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)       bfin_write32(PORTI_MUX, val)
+
+/* Port J Registers */
+
+#define bfin_read_PORTJ_FER()           bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)       bfin_write16(PORTJ_FER, val)
+#define bfin_read_PORTJ()               bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)           bfin_write16(PORTJ, val)
+#define bfin_read_PORTJ_SET()           bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)       bfin_write16(PORTJ_SET, val)
+#define bfin_read_PORTJ_CLEAR()         bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)     bfin_write16(PORTJ_CLEAR, val)
+#define bfin_read_PORTJ_DIR_SET()       bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)   bfin_write16(PORTJ_DIR_SET, val)
+#define bfin_read_PORTJ_DIR_CLEAR()     bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define bfin_read_PORTJ_INEN()          bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)      bfin_write16(PORTJ_INEN, val)
+#define bfin_read_PORTJ_MUX()           bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)       bfin_write32(PORTJ_MUX, val)
+
+/* PWM Timer Registers */
+
+#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
+#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
+#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
+#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
+#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
+#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
+#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
+#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
+
+/* Timer Groubfin_read_() of 8 */
+
+#define bfin_read_TIMER_ENABLE0()               bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)           bfin_write16(TIMER_ENABLE0, val)
+#define bfin_read_TIMER_DISABLE0()              bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val)          bfin_write16(TIMER_DISABLE0, val)
+#define bfin_read_TIMER_STATUS0()               bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)           bfin_write32(TIMER_STATUS0, val)
+
+/* DMAC1 Registers */
+
+#define bfin_read_DMAC1_TCPER()                 bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)             bfin_write16(DMAC1_TCPER, val)
+#define bfin_read_DMAC1_TCCNT()                 bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)             bfin_write16(DMAC1_TCCNT, val)
+
+/* DMA Channel 12 Registers */
+
+#define bfin_read_DMA12_NEXT_DESC_PTR()         bfin_read32(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val)     bfin_write32(DMA12_NEXT_DESC_PTR)
+#define bfin_read_DMA12_START_ADDR()            bfin_read32(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val)        bfin_write32(DMA12_START_ADDR)
+#define bfin_read_DMA12_CONFIG()                bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)            bfin_write16(DMA12_CONFIG, val)
+#define bfin_read_DMA12_X_COUNT()               bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)           bfin_write16(DMA12_X_COUNT, val)
+#define bfin_read_DMA12_X_MODIFY()              bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val)          bfin_write16(DMA12_X_MODIFY)
+#define bfin_read_DMA12_Y_COUNT()               bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)           bfin_write16(DMA12_Y_COUNT, val)
+#define bfin_read_DMA12_Y_MODIFY()              bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val)          bfin_write16(DMA12_Y_MODIFY)
+#define bfin_read_DMA12_CURR_DESC_PTR()         bfin_read32(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val)     bfin_write32(DMA12_CURR_DESC_PTR)
+#define bfin_read_DMA12_CURR_ADDR()             bfin_read32(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val)         bfin_write32(DMA12_CURR_ADDR)
+#define bfin_read_DMA12_IRQ_STATUS()            bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val)        bfin_write16(DMA12_IRQ_STATUS, val)
+#define bfin_read_DMA12_PERIPHERAL_MAP()        bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val)    bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define bfin_read_DMA12_CURR_X_COUNT()          bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val)      bfin_write16(DMA12_CURR_X_COUNT, val)
+#define bfin_read_DMA12_CURR_Y_COUNT()          bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val)      bfin_write16(DMA12_CURR_Y_COUNT, val)
+
+/* DMA Channel 13 Registers */
+
+#define bfin_read_DMA13_NEXT_DESC_PTR()         bfin_read32(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val)     bfin_write32(DMA13_NEXT_DESC_PTR)
+#define bfin_read_DMA13_START_ADDR()            bfin_read32(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val)        bfin_write32(DMA13_START_ADDR)
+#define bfin_read_DMA13_CONFIG()                bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)            bfin_write16(DMA13_CONFIG, val)
+#define bfin_read_DMA13_X_COUNT()               bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)           bfin_write16(DMA13_X_COUNT, val)
+#define bfin_read_DMA13_X_MODIFY()              bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val)          bfin_write16(DMA13_X_MODIFY)
+#define bfin_read_DMA13_Y_COUNT()               bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)           bfin_write16(DMA13_Y_COUNT, val)
+#define bfin_read_DMA13_Y_MODIFY()              bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val)          bfin_write16(DMA13_Y_MODIFY)
+#define bfin_read_DMA13_CURR_DESC_PTR()         bfin_read32(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val)     bfin_write32(DMA13_CURR_DESC_PTR)
+#define bfin_read_DMA13_CURR_ADDR()             bfin_read32(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val)         bfin_write32(DMA13_CURR_ADDR)
+#define bfin_read_DMA13_IRQ_STATUS()            bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val)        bfin_write16(DMA13_IRQ_STATUS, val)
+#define bfin_read_DMA13_PERIPHERAL_MAP()        bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val)    bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define bfin_read_DMA13_CURR_X_COUNT()          bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val)      bfin_write16(DMA13_CURR_X_COUNT, val)
+#define bfin_read_DMA13_CURR_Y_COUNT()          bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val)      bfin_write16(DMA13_CURR_Y_COUNT, val)
+
+/* DMA Channel 14 Registers */
+
+#define bfin_read_DMA14_NEXT_DESC_PTR()         bfin_read32(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val)     bfin_write32(DMA14_NEXT_DESC_PTR)
+#define bfin_read_DMA14_START_ADDR()            bfin_read32(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val)        bfin_write32(DMA14_START_ADDR)
+#define bfin_read_DMA14_CONFIG()                bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)            bfin_write16(DMA14_CONFIG, val)
+#define bfin_read_DMA14_X_COUNT()               bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)           bfin_write16(DMA14_X_COUNT, val)
+#define bfin_read_DMA14_X_MODIFY()              bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val)          bfin_write16(DMA14_X_MODIFY)
+#define bfin_read_DMA14_Y_COUNT()               bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)           bfin_write16(DMA14_Y_COUNT, val)
+#define bfin_read_DMA14_Y_MODIFY()              bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val)          bfin_write16(DMA14_Y_MODIFY)
+#define bfin_read_DMA14_CURR_DESC_PTR()         bfin_read32(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val)     bfin_write32(DMA14_CURR_DESC_PTR)
+#define bfin_read_DMA14_CURR_ADDR()             bfin_read32(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val)         bfin_write32(DMA14_CURR_ADDR)
+#define bfin_read_DMA14_IRQ_STATUS()            bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val)        bfin_write16(DMA14_IRQ_STATUS, val)
+#define bfin_read_DMA14_PERIPHERAL_MAP()        bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val)    bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define bfin_read_DMA14_CURR_X_COUNT()          bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val)      bfin_write16(DMA14_CURR_X_COUNT, val)
+#define bfin_read_DMA14_CURR_Y_COUNT()          bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val)      bfin_write16(DMA14_CURR_Y_COUNT, val)
+
+/* DMA Channel 15 Registers */
+
+#define bfin_read_DMA15_NEXT_DESC_PTR()         bfin_read32(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val)     bfin_write32(DMA15_NEXT_DESC_PTR)
+#define bfin_read_DMA15_START_ADDR()            bfin_read32(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val)        bfin_write32(DMA15_START_ADDR)
+#define bfin_read_DMA15_CONFIG()                bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)            bfin_write16(DMA15_CONFIG, val)
+#define bfin_read_DMA15_X_COUNT()               bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)           bfin_write16(DMA15_X_COUNT, val)
+#define bfin_read_DMA15_X_MODIFY()              bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val)          bfin_write16(DMA15_X_MODIFY)
+#define bfin_read_DMA15_Y_COUNT()               bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)           bfin_write16(DMA15_Y_COUNT, val)
+#define bfin_read_DMA15_Y_MODIFY()              bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val)          bfin_write16(DMA15_Y_MODIFY)
+#define bfin_read_DMA15_CURR_DESC_PTR()         bfin_read32(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val)     bfin_write32(DMA15_CURR_DESC_PTR)
+#define bfin_read_DMA15_CURR_ADDR()             bfin_read32(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val)         bfin_write32(DMA15_CURR_ADDR)
+#define bfin_read_DMA15_IRQ_STATUS()            bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val)        bfin_write16(DMA15_IRQ_STATUS, val)
+#define bfin_read_DMA15_PERIPHERAL_MAP()        bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val)    bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define bfin_read_DMA15_CURR_X_COUNT()          bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val)      bfin_write16(DMA15_CURR_X_COUNT, val)
+#define bfin_read_DMA15_CURR_Y_COUNT()          bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val)      bfin_write16(DMA15_CURR_Y_COUNT, val)
+
+/* DMA Channel 16 Registers */
+
+#define bfin_read_DMA16_NEXT_DESC_PTR()         bfin_read32(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val)     bfin_write32(DMA16_NEXT_DESC_PTR)
+#define bfin_read_DMA16_START_ADDR()            bfin_read32(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val)        bfin_write32(DMA16_START_ADDR)
+#define bfin_read_DMA16_CONFIG()                bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)            bfin_write16(DMA16_CONFIG, val)
+#define bfin_read_DMA16_X_COUNT()               bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)           bfin_write16(DMA16_X_COUNT, val)
+#define bfin_read_DMA16_X_MODIFY()              bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val)          bfin_write16(DMA16_X_MODIFY)
+#define bfin_read_DMA16_Y_COUNT()               bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)           bfin_write16(DMA16_Y_COUNT, val)
+#define bfin_read_DMA16_Y_MODIFY()              bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val)          bfin_write16(DMA16_Y_MODIFY)
+#define bfin_read_DMA16_CURR_DESC_PTR()         bfin_read32(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val)     bfin_write32(DMA16_CURR_DESC_PTR)
+#define bfin_read_DMA16_CURR_ADDR()             bfin_read32(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val)         bfin_write32(DMA16_CURR_ADDR)
+#define bfin_read_DMA16_IRQ_STATUS()            bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val)        bfin_write16(DMA16_IRQ_STATUS, val)
+#define bfin_read_DMA16_PERIPHERAL_MAP()        bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val)    bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define bfin_read_DMA16_CURR_X_COUNT()          bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val)      bfin_write16(DMA16_CURR_X_COUNT, val)
+#define bfin_read_DMA16_CURR_Y_COUNT()          bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val)      bfin_write16(DMA16_CURR_Y_COUNT, val)
+
+/* DMA Channel 17 Registers */
+
+#define bfin_read_DMA17_NEXT_DESC_PTR()         bfin_read32(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val)     bfin_write32(DMA17_NEXT_DESC_PTR)
+#define bfin_read_DMA17_START_ADDR()            bfin_read32(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val)        bfin_write32(DMA17_START_ADDR)
+#define bfin_read_DMA17_CONFIG()                bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)            bfin_write16(DMA17_CONFIG, val)
+#define bfin_read_DMA17_X_COUNT()               bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)           bfin_write16(DMA17_X_COUNT, val)
+#define bfin_read_DMA17_X_MODIFY()              bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val)          bfin_write16(DMA17_X_MODIFY)
+#define bfin_read_DMA17_Y_COUNT()               bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)           bfin_write16(DMA17_Y_COUNT, val)
+#define bfin_read_DMA17_Y_MODIFY()              bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val)          bfin_write16(DMA17_Y_MODIFY)
+#define bfin_read_DMA17_CURR_DESC_PTR()         bfin_read32(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val)     bfin_write32(DMA17_CURR_DESC_PTR)
+#define bfin_read_DMA17_CURR_ADDR()             bfin_read32(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val)         bfin_write32(DMA17_CURR_ADDR)
+#define bfin_read_DMA17_IRQ_STATUS()            bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val)        bfin_write16(DMA17_IRQ_STATUS, val)
+#define bfin_read_DMA17_PERIPHERAL_MAP()        bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val)    bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define bfin_read_DMA17_CURR_X_COUNT()          bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val)      bfin_write16(DMA17_CURR_X_COUNT, val)
+#define bfin_read_DMA17_CURR_Y_COUNT()          bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val)      bfin_write16(DMA17_CURR_Y_COUNT, val)
+
+/* DMA Channel 18 Registers */
+
+#define bfin_read_DMA18_NEXT_DESC_PTR()         bfin_read32(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val)     bfin_write32(DMA18_NEXT_DESC_PTR)
+#define bfin_read_DMA18_START_ADDR()            bfin_read32(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val)        bfin_write32(DMA18_START_ADDR)
+#define bfin_read_DMA18_CONFIG()                bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)            bfin_write16(DMA18_CONFIG, val)
+#define bfin_read_DMA18_X_COUNT()               bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)           bfin_write16(DMA18_X_COUNT, val)
+#define bfin_read_DMA18_X_MODIFY()              bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val)          bfin_write16(DMA18_X_MODIFY)
+#define bfin_read_DMA18_Y_COUNT()               bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)           bfin_write16(DMA18_Y_COUNT, val)
+#define bfin_read_DMA18_Y_MODIFY()              bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val)          bfin_write16(DMA18_Y_MODIFY)
+#define bfin_read_DMA18_CURR_DESC_PTR()         bfin_read32(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val)     bfin_write32(DMA18_CURR_DESC_PTR)
+#define bfin_read_DMA18_CURR_ADDR()             bfin_read32(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val)         bfin_write32(DMA18_CURR_ADDR)
+#define bfin_read_DMA18_IRQ_STATUS()            bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val)        bfin_write16(DMA18_IRQ_STATUS, val)
+#define bfin_read_DMA18_PERIPHERAL_MAP()        bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val)    bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define bfin_read_DMA18_CURR_X_COUNT()          bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val)      bfin_write16(DMA18_CURR_X_COUNT, val)
+#define bfin_read_DMA18_CURR_Y_COUNT()          bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val)      bfin_write16(DMA18_CURR_Y_COUNT, val)
+
+/* DMA Channel 19 Registers */
+
+#define bfin_read_DMA19_NEXT_DESC_PTR()         bfin_read32(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val)     bfin_write32(DMA19_NEXT_DESC_PTR)
+#define bfin_read_DMA19_START_ADDR()            bfin_read32(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val)        bfin_write32(DMA19_START_ADDR)
+#define bfin_read_DMA19_CONFIG()                bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)            bfin_write16(DMA19_CONFIG, val)
+#define bfin_read_DMA19_X_COUNT()               bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)           bfin_write16(DMA19_X_COUNT, val)
+#define bfin_read_DMA19_X_MODIFY()              bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val)          bfin_write16(DMA19_X_MODIFY)
+#define bfin_read_DMA19_Y_COUNT()               bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)           bfin_write16(DMA19_Y_COUNT, val)
+#define bfin_read_DMA19_Y_MODIFY()              bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val)          bfin_write16(DMA19_Y_MODIFY)
+#define bfin_read_DMA19_CURR_DESC_PTR()         bfin_read32(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val)     bfin_write32(DMA19_CURR_DESC_PTR)
+#define bfin_read_DMA19_CURR_ADDR()             bfin_read32(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val)         bfin_write32(DMA19_CURR_ADDR)
+#define bfin_read_DMA19_IRQ_STATUS()            bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val)        bfin_write16(DMA19_IRQ_STATUS, val)
+#define bfin_read_DMA19_PERIPHERAL_MAP()        bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val)    bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define bfin_read_DMA19_CURR_X_COUNT()          bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val)      bfin_write16(DMA19_CURR_X_COUNT, val)
+#define bfin_read_DMA19_CURR_Y_COUNT()          bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val)      bfin_write16(DMA19_CURR_Y_COUNT, val)
+
+/* DMA Channel 20 Registers */
+
+#define bfin_read_DMA20_NEXT_DESC_PTR()         bfin_read32(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val)     bfin_write32(DMA20_NEXT_DESC_PTR)
+#define bfin_read_DMA20_START_ADDR()            bfin_read32(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val)        bfin_write32(DMA20_START_ADDR)
+#define bfin_read_DMA20_CONFIG()                bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)            bfin_write16(DMA20_CONFIG, val)
+#define bfin_read_DMA20_X_COUNT()               bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)           bfin_write16(DMA20_X_COUNT, val)
+#define bfin_read_DMA20_X_MODIFY()              bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val)          bfin_write16(DMA20_X_MODIFY)
+#define bfin_read_DMA20_Y_COUNT()               bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)           bfin_write16(DMA20_Y_COUNT, val)
+#define bfin_read_DMA20_Y_MODIFY()              bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val)          bfin_write16(DMA20_Y_MODIFY)
+#define bfin_read_DMA20_CURR_DESC_PTR()         bfin_read32(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val)     bfin_write32(DMA20_CURR_DESC_PTR)
+#define bfin_read_DMA20_CURR_ADDR()             bfin_read32(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val)         bfin_write32(DMA20_CURR_ADDR)
+#define bfin_read_DMA20_IRQ_STATUS()            bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val)        bfin_write16(DMA20_IRQ_STATUS, val)
+#define bfin_read_DMA20_PERIPHERAL_MAP()        bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val)    bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define bfin_read_DMA20_CURR_X_COUNT()          bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val)      bfin_write16(DMA20_CURR_X_COUNT, val)
+#define bfin_read_DMA20_CURR_Y_COUNT()          bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val)      bfin_write16(DMA20_CURR_Y_COUNT, val)
+
+/* DMA Channel 21 Registers */
+
+#define bfin_read_DMA21_NEXT_DESC_PTR()         bfin_read32(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val)     bfin_write32(DMA21_NEXT_DESC_PTR)
+#define bfin_read_DMA21_START_ADDR()            bfin_read32(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val)        bfin_write32(DMA21_START_ADDR)
+#define bfin_read_DMA21_CONFIG()                bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)            bfin_write16(DMA21_CONFIG, val)
+#define bfin_read_DMA21_X_COUNT()               bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)           bfin_write16(DMA21_X_COUNT, val)
+#define bfin_read_DMA21_X_MODIFY()              bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val)          bfin_write16(DMA21_X_MODIFY)
+#define bfin_read_DMA21_Y_COUNT()               bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)           bfin_write16(DMA21_Y_COUNT, val)
+#define bfin_read_DMA21_Y_MODIFY()              bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val)          bfin_write16(DMA21_Y_MODIFY)
+#define bfin_read_DMA21_CURR_DESC_PTR()         bfin_read32(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val)     bfin_write32(DMA21_CURR_DESC_PTR)
+#define bfin_read_DMA21_CURR_ADDR()             bfin_read32(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val)         bfin_write32(DMA21_CURR_ADDR)
+#define bfin_read_DMA21_IRQ_STATUS()            bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val)        bfin_write16(DMA21_IRQ_STATUS, val)
+#define bfin_read_DMA21_PERIPHERAL_MAP()        bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val)    bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define bfin_read_DMA21_CURR_X_COUNT()          bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val)      bfin_write16(DMA21_CURR_X_COUNT, val)
+#define bfin_read_DMA21_CURR_Y_COUNT()          bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val)      bfin_write16(DMA21_CURR_Y_COUNT, val)
+
+/* DMA Channel 22 Registers */
+
+#define bfin_read_DMA22_NEXT_DESC_PTR()         bfin_read32(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val)     bfin_write32(DMA22_NEXT_DESC_PTR)
+#define bfin_read_DMA22_START_ADDR()            bfin_read32(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val)        bfin_write32(DMA22_START_ADDR)
+#define bfin_read_DMA22_CONFIG()                bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)            bfin_write16(DMA22_CONFIG, val)
+#define bfin_read_DMA22_X_COUNT()               bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)           bfin_write16(DMA22_X_COUNT, val)
+#define bfin_read_DMA22_X_MODIFY()              bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val)          bfin_write16(DMA22_X_MODIFY)
+#define bfin_read_DMA22_Y_COUNT()               bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)           bfin_write16(DMA22_Y_COUNT, val)
+#define bfin_read_DMA22_Y_MODIFY()              bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val)          bfin_write16(DMA22_Y_MODIFY)
+#define bfin_read_DMA22_CURR_DESC_PTR()         bfin_read32(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val)     bfin_write32(DMA22_CURR_DESC_PTR)
+#define bfin_read_DMA22_CURR_ADDR()             bfin_read32(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val)         bfin_write32(DMA22_CURR_ADDR)
+#define bfin_read_DMA22_IRQ_STATUS()            bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val)        bfin_write16(DMA22_IRQ_STATUS, val)
+#define bfin_read_DMA22_PERIPHERAL_MAP()        bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val)    bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define bfin_read_DMA22_CURR_X_COUNT()          bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val)      bfin_write16(DMA22_CURR_X_COUNT, val)
+#define bfin_read_DMA22_CURR_Y_COUNT()          bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val)      bfin_write16(DMA22_CURR_Y_COUNT, val)
+
+/* DMA Channel 23 Registers */
+
+#define bfin_read_DMA23_NEXT_DESC_PTR()                 bfin_read32(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val)             bfin_write32(DMA23_NEXT_DESC_PTR)
+#define bfin_read_DMA23_START_ADDR()                    bfin_read32(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val)                bfin_write32(DMA23_START_ADDR)
+#define bfin_read_DMA23_CONFIG()                        bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)                    bfin_write16(DMA23_CONFIG, val)
+#define bfin_read_DMA23_X_COUNT()                       bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)                   bfin_write16(DMA23_X_COUNT, val)
+#define bfin_read_DMA23_X_MODIFY()                      bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val)                  bfin_write16(DMA23_X_MODIFY)
+#define bfin_read_DMA23_Y_COUNT()                       bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)                   bfin_write16(DMA23_Y_COUNT, val)
+#define bfin_read_DMA23_Y_MODIFY()                      bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val)                  bfin_write16(DMA23_Y_MODIFY)
+#define bfin_read_DMA23_CURR_DESC_PTR()                 bfin_read32(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val)             bfin_write32(DMA23_CURR_DESC_PTR)
+#define bfin_read_DMA23_CURR_ADDR()                     bfin_read32(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val)                 bfin_write32(DMA23_CURR_ADDR)
+#define bfin_read_DMA23_IRQ_STATUS()                    bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val)                bfin_write16(DMA23_IRQ_STATUS, val)
+#define bfin_read_DMA23_PERIPHERAL_MAP()                bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val)            bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define bfin_read_DMA23_CURR_X_COUNT()                  bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val)              bfin_write16(DMA23_CURR_X_COUNT, val)
+#define bfin_read_DMA23_CURR_Y_COUNT()                  bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val)              bfin_write16(DMA23_CURR_Y_COUNT, val)
+
+/* MDMA Stream 2 Registers */
+
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR()               bfin_read32(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val)           bfin_write32(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_read_MDMA_D2_START_ADDR()                  bfin_read32(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val)              bfin_write32(MDMA_D2_START_ADDR)
+#define bfin_read_MDMA_D2_CONFIG()                      bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val)                  bfin_write16(MDMA_D2_CONFIG, val)
+#define bfin_read_MDMA_D2_X_COUNT()                     bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val)                 bfin_write16(MDMA_D2_X_COUNT, val)
+#define bfin_read_MDMA_D2_X_MODIFY()                    bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val)                bfin_write16(MDMA_D2_X_MODIFY)
+#define bfin_read_MDMA_D2_Y_COUNT()                     bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val)                 bfin_write16(MDMA_D2_Y_COUNT, val)
+#define bfin_read_MDMA_D2_Y_MODIFY()                    bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val)                bfin_write16(MDMA_D2_Y_MODIFY)
+#define bfin_read_MDMA_D2_CURR_DESC_PTR()               bfin_read32(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val)           bfin_write32(MDMA_D2_CURR_DESC_PTR)
+#define bfin_read_MDMA_D2_CURR_ADDR()                   bfin_read32(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val)               bfin_write32(MDMA_D2_CURR_ADDR)
+#define bfin_read_MDMA_D2_IRQ_STATUS()                  bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val)              bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP()              bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val)          bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D2_CURR_X_COUNT()                bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val)            bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D2_CURR_Y_COUNT()                bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val)            bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR()               bfin_read32(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val)           bfin_write32(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_read_MDMA_S2_START_ADDR()                  bfin_read32(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val)              bfin_write32(MDMA_S2_START_ADDR)
+#define bfin_read_MDMA_S2_CONFIG()                      bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val)                  bfin_write16(MDMA_S2_CONFIG, val)
+#define bfin_read_MDMA_S2_X_COUNT()                     bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val)                 bfin_write16(MDMA_S2_X_COUNT, val)
+#define bfin_read_MDMA_S2_X_MODIFY()                    bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val)                bfin_write16(MDMA_S2_X_MODIFY)
+#define bfin_read_MDMA_S2_Y_COUNT()                     bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val)                 bfin_write16(MDMA_S2_Y_COUNT, val)
+#define bfin_read_MDMA_S2_Y_MODIFY()                    bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val)                bfin_write16(MDMA_S2_Y_MODIFY)
+#define bfin_read_MDMA_S2_CURR_DESC_PTR()               bfin_read32(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val)           bfin_write32(MDMA_S2_CURR_DESC_PTR)
+#define bfin_read_MDMA_S2_CURR_ADDR()                   bfin_read32(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val)               bfin_write32(MDMA_S2_CURR_ADDR)
+#define bfin_read_MDMA_S2_IRQ_STATUS()                  bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val)              bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP()              bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val)          bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S2_CURR_X_COUNT()                bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val)            bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S2_CURR_Y_COUNT()                bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val)            bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+
+/* MDMA Stream 3 Registers */
+
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR()               bfin_read32(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val)           bfin_write32(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_read_MDMA_D3_START_ADDR()                  bfin_read32(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val)              bfin_write32(MDMA_D3_START_ADDR)
+#define bfin_read_MDMA_D3_CONFIG()                      bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val)                  bfin_write16(MDMA_D3_CONFIG, val)
+#define bfin_read_MDMA_D3_X_COUNT()                     bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val)                 bfin_write16(MDMA_D3_X_COUNT, val)
+#define bfin_read_MDMA_D3_X_MODIFY()                    bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val)                bfin_write16(MDMA_D3_X_MODIFY)
+#define bfin_read_MDMA_D3_Y_COUNT()                     bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val)                 bfin_write16(MDMA_D3_Y_COUNT, val)
+#define bfin_read_MDMA_D3_Y_MODIFY()                    bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val)                bfin_write16(MDMA_D3_Y_MODIFY)
+#define bfin_read_MDMA_D3_CURR_DESC_PTR()               bfin_read32(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val)           bfin_write32(MDMA_D3_CURR_DESC_PTR)
+#define bfin_read_MDMA_D3_CURR_ADDR()                   bfin_read32(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val)               bfin_write32(MDMA_D3_CURR_ADDR)
+#define bfin_read_MDMA_D3_IRQ_STATUS()                  bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val)              bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP()              bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val)          bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D3_CURR_X_COUNT()                bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val)            bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D3_CURR_Y_COUNT()                bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val)            bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR()               bfin_read32(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val)           bfin_write32(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_read_MDMA_S3_START_ADDR()                  bfin_read32(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val)              bfin_write32(MDMA_S3_START_ADDR)
+#define bfin_read_MDMA_S3_CONFIG()                      bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val)                  bfin_write16(MDMA_S3_CONFIG, val)
+#define bfin_read_MDMA_S3_X_COUNT()                     bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val)                 bfin_write16(MDMA_S3_X_COUNT, val)
+#define bfin_read_MDMA_S3_X_MODIFY()                    bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val)                bfin_write16(MDMA_S3_X_MODIFY)
+#define bfin_read_MDMA_S3_Y_COUNT()                     bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val)                 bfin_write16(MDMA_S3_Y_COUNT, val)
+#define bfin_read_MDMA_S3_Y_MODIFY()                    bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val)                bfin_write16(MDMA_S3_Y_MODIFY)
+#define bfin_read_MDMA_S3_CURR_DESC_PTR()               bfin_read32(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val)           bfin_write32(MDMA_S3_CURR_DESC_PTR)
+#define bfin_read_MDMA_S3_CURR_ADDR()                   bfin_read32(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val)               bfin_write32(MDMA_S3_CURR_ADDR)
+#define bfin_read_MDMA_S3_IRQ_STATUS()                  bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val)              bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP()              bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val)          bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S3_CURR_X_COUNT()                bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val)            bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S3_CURR_Y_COUNT()                bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val)            bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+
+/* UART1 Registers */
+
+#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
+#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
+#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
+#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
+#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
+#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
+#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
+#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
+#define bfin_read_UART1_IER_SET()               bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)           bfin_write16(UART1_IER_SET, val)
+#define bfin_read_UART1_IER_CLEAR()             bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val)         bfin_write16(UART1_IER_CLEAR, val)
+#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
+#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
+
+/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
+
+/* SPI1 Registers */
+
+#define bfin_read_SPI1_CTL()                    bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)                bfin_write16(SPI1_CTL, val)
+#define bfin_read_SPI1_FLG()                    bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)                bfin_write16(SPI1_FLG, val)
+#define bfin_read_SPI1_STAT()                   bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)               bfin_write16(SPI1_STAT, val)
+#define bfin_read_SPI1_TDBR()                   bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)               bfin_write16(SPI1_TDBR, val)
+#define bfin_read_SPI1_RDBR()                   bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)               bfin_write16(SPI1_RDBR, val)
+#define bfin_read_SPI1_BAUD()                   bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)               bfin_write16(SPI1_BAUD, val)
+#define bfin_read_SPI1_SHADOW()                 bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)             bfin_write16(SPI1_SHADOW, val)
+
+/* SPORT2 Registers */
+
+#define bfin_read_SPORT2_TCR1()                 bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)             bfin_write16(SPORT2_TCR1, val)
+#define bfin_read_SPORT2_TCR2()                 bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)             bfin_write16(SPORT2_TCR2, val)
+#define bfin_read_SPORT2_TCLKDIV()              bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val)          bfin_write16(SPORT2_TCLKDIV, val)
+#define bfin_read_SPORT2_TFSDIV()               bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)           bfin_write16(SPORT2_TFSDIV, val)
+#define bfin_read_SPORT2_TX()                   bfin_read32(SPORT2_TX)
+#define bfin_write_SPORT2_TX(val)               bfin_write32(SPORT2_TX, val)
+#define bfin_read_SPORT2_RX()                   bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)               bfin_write32(SPORT2_RX, val)
+#define bfin_read_SPORT2_RCR1()                 bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)             bfin_write16(SPORT2_RCR1, val)
+#define bfin_read_SPORT2_RCR2()                 bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)             bfin_write16(SPORT2_RCR2, val)
+#define bfin_read_SPORT2_RCLKDIV()              bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val)          bfin_write16(SPORT2_RCLKDIV, val)
+#define bfin_read_SPORT2_RFSDIV()               bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)           bfin_write16(SPORT2_RFSDIV, val)
+#define bfin_read_SPORT2_STAT()                 bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)             bfin_write16(SPORT2_STAT, val)
+#define bfin_read_SPORT2_CHNL()                 bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)             bfin_write16(SPORT2_CHNL, val)
+#define bfin_read_SPORT2_MCMC1()                bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)            bfin_write16(SPORT2_MCMC1, val)
+#define bfin_read_SPORT2_MCMC2()                bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)            bfin_write16(SPORT2_MCMC2, val)
+#define bfin_read_SPORT2_MTCS0()                bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)            bfin_write32(SPORT2_MTCS0, val)
+#define bfin_read_SPORT2_MTCS1()                bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)            bfin_write32(SPORT2_MTCS1, val)
+#define bfin_read_SPORT2_MTCS2()                bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)            bfin_write32(SPORT2_MTCS2, val)
+#define bfin_read_SPORT2_MTCS3()                bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)            bfin_write32(SPORT2_MTCS3, val)
+#define bfin_read_SPORT2_MRCS0()                bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)            bfin_write32(SPORT2_MRCS0, val)
+#define bfin_read_SPORT2_MRCS1()                bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)            bfin_write32(SPORT2_MRCS1, val)
+#define bfin_read_SPORT2_MRCS2()                bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)            bfin_write32(SPORT2_MRCS2, val)
+#define bfin_read_SPORT2_MRCS3()                bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)            bfin_write32(SPORT2_MRCS3, val)
+
+/* SPORT3 Registers */
+
+#define bfin_read_SPORT3_TCR1()                 bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)             bfin_write16(SPORT3_TCR1, val)
+#define bfin_read_SPORT3_TCR2()                 bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)             bfin_write16(SPORT3_TCR2, val)
+#define bfin_read_SPORT3_TCLKDIV()              bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val)          bfin_write16(SPORT3_TCLKDIV, val)
+#define bfin_read_SPORT3_TFSDIV()               bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)           bfin_write16(SPORT3_TFSDIV, val)
+#define bfin_read_SPORT3_TX()                   bfin_read32(SPORT3_TX)
+#define bfin_write_SPORT3_TX(val)               bfin_write32(SPORT3_TX, val)
+#define bfin_read_SPORT3_RX()                   bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)               bfin_write32(SPORT3_RX, val)
+#define bfin_read_SPORT3_RCR1()                 bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)             bfin_write16(SPORT3_RCR1, val)
+#define bfin_read_SPORT3_RCR2()                 bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)             bfin_write16(SPORT3_RCR2, val)
+#define bfin_read_SPORT3_RCLKDIV()              bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val)          bfin_write16(SPORT3_RCLKDIV, val)
+#define bfin_read_SPORT3_RFSDIV()               bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)           bfin_write16(SPORT3_RFSDIV, val)
+#define bfin_read_SPORT3_STAT()                 bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)             bfin_write16(SPORT3_STAT, val)
+#define bfin_read_SPORT3_CHNL()                 bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)             bfin_write16(SPORT3_CHNL, val)
+#define bfin_read_SPORT3_MCMC1()                bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)            bfin_write16(SPORT3_MCMC1, val)
+#define bfin_read_SPORT3_MCMC2()                bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)            bfin_write16(SPORT3_MCMC2, val)
+#define bfin_read_SPORT3_MTCS0()                bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)            bfin_write32(SPORT3_MTCS0, val)
+#define bfin_read_SPORT3_MTCS1()                bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)            bfin_write32(SPORT3_MTCS1, val)
+#define bfin_read_SPORT3_MTCS2()                bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)            bfin_write32(SPORT3_MTCS2, val)
+#define bfin_read_SPORT3_MTCS3()                bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)            bfin_write32(SPORT3_MTCS3, val)
+#define bfin_read_SPORT3_MRCS0()                bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)            bfin_write32(SPORT3_MRCS0, val)
+#define bfin_read_SPORT3_MRCS1()                bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)            bfin_write32(SPORT3_MRCS1, val)
+#define bfin_read_SPORT3_MRCS2()                bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)            bfin_write32(SPORT3_MRCS2, val)
+#define bfin_read_SPORT3_MRCS3()                bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)            bfin_write32(SPORT3_MRCS3, val)
+
+/* EPPI2 Registers */
+
+#define bfin_read_EPPI2_STATUS()                bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)            bfin_write16(EPPI2_STATUS, val)
+#define bfin_read_EPPI2_HCOUNT()                bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)            bfin_write16(EPPI2_HCOUNT, val)
+#define bfin_read_EPPI2_HDELAY()                bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)            bfin_write16(EPPI2_HDELAY, val)
+#define bfin_read_EPPI2_VCOUNT()                bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)            bfin_write16(EPPI2_VCOUNT, val)
+#define bfin_read_EPPI2_VDELAY()                bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)            bfin_write16(EPPI2_VDELAY, val)
+#define bfin_read_EPPI2_FRAME()                 bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)             bfin_write16(EPPI2_FRAME, val)
+#define bfin_read_EPPI2_LINE()                  bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)              bfin_write16(EPPI2_LINE, val)
+#define bfin_read_EPPI2_CLKDIV()                bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)            bfin_write16(EPPI2_CLKDIV, val)
+#define bfin_read_EPPI2_CONTROL()               bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)           bfin_write32(EPPI2_CONTROL, val)
+#define bfin_read_EPPI2_FS1W_HBL()              bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val)          bfin_write32(EPPI2_FS1W_HBL, val)
+#define bfin_read_EPPI2_FS1P_AVPL()             bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val)         bfin_write32(EPPI2_FS1P_AVPL, val)
+#define bfin_read_EPPI2_FS2W_LVB()              bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val)          bfin_write32(EPPI2_FS2W_LVB, val)
+#define bfin_read_EPPI2_FS2P_LAVF()             bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val)         bfin_write32(EPPI2_FS2P_LAVF, val)
+#define bfin_read_EPPI2_CLIP()                  bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)              bfin_write32(EPPI2_CLIP, val)
+
+/* CAN Controller 0 Config 1 Registers */
+
+#define bfin_read_CAN0_MC1()            bfin_read16(CAN0_MC1)
+#define bfin_write_CAN0_MC1(val)        bfin_write16(CAN0_MC1, val)
+#define bfin_read_CAN0_MD1()            bfin_read16(CAN0_MD1)
+#define bfin_write_CAN0_MD1(val)        bfin_write16(CAN0_MD1, val)
+#define bfin_read_CAN0_TRS1()           bfin_read16(CAN0_TRS1)
+#define bfin_write_CAN0_TRS1(val)       bfin_write16(CAN0_TRS1, val)
+#define bfin_read_CAN0_TRR1()           bfin_read16(CAN0_TRR1)
+#define bfin_write_CAN0_TRR1(val)       bfin_write16(CAN0_TRR1, val)
+#define bfin_read_CAN0_TA1()            bfin_read16(CAN0_TA1)
+#define bfin_write_CAN0_TA1(val)        bfin_write16(CAN0_TA1, val)
+#define bfin_read_CAN0_AA1()            bfin_read16(CAN0_AA1)
+#define bfin_write_CAN0_AA1(val)        bfin_write16(CAN0_AA1, val)
+#define bfin_read_CAN0_RMP1()           bfin_read16(CAN0_RMP1)
+#define bfin_write_CAN0_RMP1(val)       bfin_write16(CAN0_RMP1, val)
+#define bfin_read_CAN0_RML1()           bfin_read16(CAN0_RML1)
+#define bfin_write_CAN0_RML1(val)       bfin_write16(CAN0_RML1, val)
+#define bfin_read_CAN0_MBTIF1()         bfin_read16(CAN0_MBTIF1)
+#define bfin_write_CAN0_MBTIF1(val)     bfin_write16(CAN0_MBTIF1, val)
+#define bfin_read_CAN0_MBRIF1()         bfin_read16(CAN0_MBRIF1)
+#define bfin_write_CAN0_MBRIF1(val)     bfin_write16(CAN0_MBRIF1, val)
+#define bfin_read_CAN0_MBIM1()          bfin_read16(CAN0_MBIM1)
+#define bfin_write_CAN0_MBIM1(val)      bfin_write16(CAN0_MBIM1, val)
+#define bfin_read_CAN0_RFH1()           bfin_read16(CAN0_RFH1)
+#define bfin_write_CAN0_RFH1(val)       bfin_write16(CAN0_RFH1, val)
+#define bfin_read_CAN0_OPSS1()          bfin_read16(CAN0_OPSS1)
+#define bfin_write_CAN0_OPSS1(val)      bfin_write16(CAN0_OPSS1, val)
+
+/* CAN Controller 0 Config 2 Registers */
+
+#define bfin_read_CAN0_MC2()            bfin_read16(CAN0_MC2)
+#define bfin_write_CAN0_MC2(val)        bfin_write16(CAN0_MC2, val)
+#define bfin_read_CAN0_MD2()            bfin_read16(CAN0_MD2)
+#define bfin_write_CAN0_MD2(val)        bfin_write16(CAN0_MD2, val)
+#define bfin_read_CAN0_TRS2()           bfin_read16(CAN0_TRS2)
+#define bfin_write_CAN0_TRS2(val)       bfin_write16(CAN0_TRS2, val)
+#define bfin_read_CAN0_TRR2()           bfin_read16(CAN0_TRR2)
+#define bfin_write_CAN0_TRR2(val)       bfin_write16(CAN0_TRR2, val)
+#define bfin_read_CAN0_TA2()            bfin_read16(CAN0_TA2)
+#define bfin_write_CAN0_TA2(val)        bfin_write16(CAN0_TA2, val)
+#define bfin_read_CAN0_AA2()            bfin_read16(CAN0_AA2)
+#define bfin_write_CAN0_AA2(val)        bfin_write16(CAN0_AA2, val)
+#define bfin_read_CAN0_RMP2()           bfin_read16(CAN0_RMP2)
+#define bfin_write_CAN0_RMP2(val)       bfin_write16(CAN0_RMP2, val)
+#define bfin_read_CAN0_RML2()           bfin_read16(CAN0_RML2)
+#define bfin_write_CAN0_RML2(val)       bfin_write16(CAN0_RML2, val)
+#define bfin_read_CAN0_MBTIF2()         bfin_read16(CAN0_MBTIF2)
+#define bfin_write_CAN0_MBTIF2(val)     bfin_write16(CAN0_MBTIF2, val)
+#define bfin_read_CAN0_MBRIF2()         bfin_read16(CAN0_MBRIF2)
+#define bfin_write_CAN0_MBRIF2(val)     bfin_write16(CAN0_MBRIF2, val)
+#define bfin_read_CAN0_MBIM2()          bfin_read16(CAN0_MBIM2)
+#define bfin_write_CAN0_MBIM2(val)      bfin_write16(CAN0_MBIM2, val)
+#define bfin_read_CAN0_RFH2()           bfin_read16(CAN0_RFH2)
+#define bfin_write_CAN0_RFH2(val)       bfin_write16(CAN0_RFH2, val)
+#define bfin_read_CAN0_OPSS2()          bfin_read16(CAN0_OPSS2)
+#define bfin_write_CAN0_OPSS2(val)      bfin_write16(CAN0_OPSS2, val)
+
+/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
+
+#define bfin_read_CAN0_CLOCK()          bfin_read16(CAN0_CLOCK)
+#define bfin_write_CAN0_CLOCK(val)      bfin_write16(CAN0_CLOCK, val)
+#define bfin_read_CAN0_TIMING()         bfin_read16(CAN0_TIMING)
+#define bfin_write_CAN0_TIMING(val)     bfin_write16(CAN0_TIMING, val)
+#define bfin_read_CAN0_DEBUG()          bfin_read16(CAN0_DEBUG)
+#define bfin_write_CAN0_DEBUG(val)      bfin_write16(CAN0_DEBUG, val)
+#define bfin_read_CAN0_STATUS()         bfin_read16(CAN0_STATUS)
+#define bfin_write_CAN0_STATUS(val)     bfin_write16(CAN0_STATUS, val)
+#define bfin_read_CAN0_CEC()            bfin_read16(CAN0_CEC)
+#define bfin_write_CAN0_CEC(val)        bfin_write16(CAN0_CEC, val)
+#define bfin_read_CAN0_GIS()            bfin_read16(CAN0_GIS)
+#define bfin_write_CAN0_GIS(val)        bfin_write16(CAN0_GIS, val)
+#define bfin_read_CAN0_GIM()            bfin_read16(CAN0_GIM)
+#define bfin_write_CAN0_GIM(val)        bfin_write16(CAN0_GIM, val)
+#define bfin_read_CAN0_GIF()            bfin_read16(CAN0_GIF)
+#define bfin_write_CAN0_GIF(val)        bfin_write16(CAN0_GIF, val)
+#define bfin_read_CAN0_CONTROL()        bfin_read16(CAN0_CONTROL)
+#define bfin_write_CAN0_CONTROL(val)    bfin_write16(CAN0_CONTROL, val)
+#define bfin_read_CAN0_INTR()           bfin_read16(CAN0_INTR)
+#define bfin_write_CAN0_INTR(val)       bfin_write16(CAN0_INTR, val)
+#define bfin_read_CAN0_MBTD()           bfin_read16(CAN0_MBTD)
+#define bfin_write_CAN0_MBTD(val)       bfin_write16(CAN0_MBTD, val)
+#define bfin_read_CAN0_EWR()            bfin_read16(CAN0_EWR)
+#define bfin_write_CAN0_EWR(val)        bfin_write16(CAN0_EWR, val)
+#define bfin_read_CAN0_ESR()            bfin_read16(CAN0_ESR)
+#define bfin_write_CAN0_ESR(val)        bfin_write16(CAN0_ESR, val)
+#define bfin_read_CAN0_UCCNT()          bfin_read16(CAN0_UCCNT)
+#define bfin_write_CAN0_UCCNT(val)      bfin_write16(CAN0_UCCNT, val)
+#define bfin_read_CAN0_UCRC()           bfin_read16(CAN0_UCRC)
+#define bfin_write_CAN0_UCRC(val)       bfin_write16(CAN0_UCRC, val)
+#define bfin_read_CAN0_UCCNF()          bfin_read16(CAN0_UCCNF)
+#define bfin_write_CAN0_UCCNF(val)      bfin_write16(CAN0_UCCNF, val)
+
+/* CAN Controller 0 Accebfin_read_()tance Registers */
+
+#define bfin_read_CAN0_AM00L()          bfin_read16(CAN0_AM00L)
+#define bfin_write_CAN0_AM00L(val)      bfin_write16(CAN0_AM00L, val)
+#define bfin_read_CAN0_AM00H()          bfin_read16(CAN0_AM00H)
+#define bfin_write_CAN0_AM00H(val)      bfin_write16(CAN0_AM00H, val)
+#define bfin_read_CAN0_AM01L()          bfin_read16(CAN0_AM01L)
+#define bfin_write_CAN0_AM01L(val)      bfin_write16(CAN0_AM01L, val)
+#define bfin_read_CAN0_AM01H()          bfin_read16(CAN0_AM01H)
+#define bfin_write_CAN0_AM01H(val)      bfin_write16(CAN0_AM01H, val)
+#define bfin_read_CAN0_AM02L()          bfin_read16(CAN0_AM02L)
+#define bfin_write_CAN0_AM02L(val)      bfin_write16(CAN0_AM02L, val)
+#define bfin_read_CAN0_AM02H()          bfin_read16(CAN0_AM02H)
+#define bfin_write_CAN0_AM02H(val)      bfin_write16(CAN0_AM02H, val)
+#define bfin_read_CAN0_AM03L()          bfin_read16(CAN0_AM03L)
+#define bfin_write_CAN0_AM03L(val)      bfin_write16(CAN0_AM03L, val)
+#define bfin_read_CAN0_AM03H()          bfin_read16(CAN0_AM03H)
+#define bfin_write_CAN0_AM03H(val)      bfin_write16(CAN0_AM03H, val)
+#define bfin_read_CAN0_AM04L()          bfin_read16(CAN0_AM04L)
+#define bfin_write_CAN0_AM04L(val)      bfin_write16(CAN0_AM04L, val)
+#define bfin_read_CAN0_AM04H()          bfin_read16(CAN0_AM04H)
+#define bfin_write_CAN0_AM04H(val)      bfin_write16(CAN0_AM04H, val)
+#define bfin_read_CAN0_AM05L()          bfin_read16(CAN0_AM05L)
+#define bfin_write_CAN0_AM05L(val)      bfin_write16(CAN0_AM05L, val)
+#define bfin_read_CAN0_AM05H()          bfin_read16(CAN0_AM05H)
+#define bfin_write_CAN0_AM05H(val)      bfin_write16(CAN0_AM05H, val)
+#define bfin_read_CAN0_AM06L()          bfin_read16(CAN0_AM06L)
+#define bfin_write_CAN0_AM06L(val)      bfin_write16(CAN0_AM06L, val)
+#define bfin_read_CAN0_AM06H()          bfin_read16(CAN0_AM06H)
+#define bfin_write_CAN0_AM06H(val)      bfin_write16(CAN0_AM06H, val)
+#define bfin_read_CAN0_AM07L()          bfin_read16(CAN0_AM07L)
+#define bfin_write_CAN0_AM07L(val)      bfin_write16(CAN0_AM07L, val)
+#define bfin_read_CAN0_AM07H()          bfin_read16(CAN0_AM07H)
+#define bfin_write_CAN0_AM07H(val)      bfin_write16(CAN0_AM07H, val)
+#define bfin_read_CAN0_AM08L()          bfin_read16(CAN0_AM08L)
+#define bfin_write_CAN0_AM08L(val)      bfin_write16(CAN0_AM08L, val)
+#define bfin_read_CAN0_AM08H()          bfin_read16(CAN0_AM08H)
+#define bfin_write_CAN0_AM08H(val)      bfin_write16(CAN0_AM08H, val)
+#define bfin_read_CAN0_AM09L()          bfin_read16(CAN0_AM09L)
+#define bfin_write_CAN0_AM09L(val)      bfin_write16(CAN0_AM09L, val)
+#define bfin_read_CAN0_AM09H()          bfin_read16(CAN0_AM09H)
+#define bfin_write_CAN0_AM09H(val)      bfin_write16(CAN0_AM09H, val)
+#define bfin_read_CAN0_AM10L()          bfin_read16(CAN0_AM10L)
+#define bfin_write_CAN0_AM10L(val)      bfin_write16(CAN0_AM10L, val)
+#define bfin_read_CAN0_AM10H()          bfin_read16(CAN0_AM10H)
+#define bfin_write_CAN0_AM10H(val)      bfin_write16(CAN0_AM10H, val)
+#define bfin_read_CAN0_AM11L()          bfin_read16(CAN0_AM11L)
+#define bfin_write_CAN0_AM11L(val)      bfin_write16(CAN0_AM11L, val)
+#define bfin_read_CAN0_AM11H()          bfin_read16(CAN0_AM11H)
+#define bfin_write_CAN0_AM11H(val)      bfin_write16(CAN0_AM11H, val)
+#define bfin_read_CAN0_AM12L()          bfin_read16(CAN0_AM12L)
+#define bfin_write_CAN0_AM12L(val)      bfin_write16(CAN0_AM12L, val)
+#define bfin_read_CAN0_AM12H()          bfin_read16(CAN0_AM12H)
+#define bfin_write_CAN0_AM12H(val)      bfin_write16(CAN0_AM12H, val)
+#define bfin_read_CAN0_AM13L()          bfin_read16(CAN0_AM13L)
+#define bfin_write_CAN0_AM13L(val)      bfin_write16(CAN0_AM13L, val)
+#define bfin_read_CAN0_AM13H()          bfin_read16(CAN0_AM13H)
+#define bfin_write_CAN0_AM13H(val)      bfin_write16(CAN0_AM13H, val)
+#define bfin_read_CAN0_AM14L()          bfin_read16(CAN0_AM14L)
+#define bfin_write_CAN0_AM14L(val)      bfin_write16(CAN0_AM14L, val)
+#define bfin_read_CAN0_AM14H()          bfin_read16(CAN0_AM14H)
+#define bfin_write_CAN0_AM14H(val)      bfin_write16(CAN0_AM14H, val)
+#define bfin_read_CAN0_AM15L()          bfin_read16(CAN0_AM15L)
+#define bfin_write_CAN0_AM15L(val)      bfin_write16(CAN0_AM15L, val)
+#define bfin_read_CAN0_AM15H()          bfin_read16(CAN0_AM15H)
+#define bfin_write_CAN0_AM15H(val)      bfin_write16(CAN0_AM15H, val)
+
+/* CAN Controller 0 Accebfin_read_()tance Registers */
+
+#define bfin_read_CAN0_AM16L()          bfin_read16(CAN0_AM16L)
+#define bfin_write_CAN0_AM16L(val)      bfin_write16(CAN0_AM16L, val)
+#define bfin_read_CAN0_AM16H()          bfin_read16(CAN0_AM16H)
+#define bfin_write_CAN0_AM16H(val)      bfin_write16(CAN0_AM16H, val)
+#define bfin_read_CAN0_AM17L()          bfin_read16(CAN0_AM17L)
+#define bfin_write_CAN0_AM17L(val)      bfin_write16(CAN0_AM17L, val)
+#define bfin_read_CAN0_AM17H()          bfin_read16(CAN0_AM17H)
+#define bfin_write_CAN0_AM17H(val)      bfin_write16(CAN0_AM17H, val)
+#define bfin_read_CAN0_AM18L()          bfin_read16(CAN0_AM18L)
+#define bfin_write_CAN0_AM18L(val)      bfin_write16(CAN0_AM18L, val)
+#define bfin_read_CAN0_AM18H()          bfin_read16(CAN0_AM18H)
+#define bfin_write_CAN0_AM18H(val)      bfin_write16(CAN0_AM18H, val)
+#define bfin_read_CAN0_AM19L()          bfin_read16(CAN0_AM19L)
+#define bfin_write_CAN0_AM19L(val)      bfin_write16(CAN0_AM19L, val)
+#define bfin_read_CAN0_AM19H()          bfin_read16(CAN0_AM19H)
+#define bfin_write_CAN0_AM19H(val)      bfin_write16(CAN0_AM19H, val)
+#define bfin_read_CAN0_AM20L()          bfin_read16(CAN0_AM20L)
+#define bfin_write_CAN0_AM20L(val)      bfin_write16(CAN0_AM20L, val)
+#define bfin_read_CAN0_AM20H()          bfin_read16(CAN0_AM20H)
+#define bfin_write_CAN0_AM20H(val)      bfin_write16(CAN0_AM20H, val)
+#define bfin_read_CAN0_AM21L()          bfin_read16(CAN0_AM21L)
+#define bfin_write_CAN0_AM21L(val)      bfin_write16(CAN0_AM21L, val)
+#define bfin_read_CAN0_AM21H()          bfin_read16(CAN0_AM21H)
+#define bfin_write_CAN0_AM21H(val)      bfin_write16(CAN0_AM21H, val)
+#define bfin_read_CAN0_AM22L()          bfin_read16(CAN0_AM22L)
+#define bfin_write_CAN0_AM22L(val)      bfin_write16(CAN0_AM22L, val)
+#define bfin_read_CAN0_AM22H()          bfin_read16(CAN0_AM22H)
+#define bfin_write_CAN0_AM22H(val)      bfin_write16(CAN0_AM22H, val)
+#define bfin_read_CAN0_AM23L()          bfin_read16(CAN0_AM23L)
+#define bfin_write_CAN0_AM23L(val)      bfin_write16(CAN0_AM23L, val)
+#define bfin_read_CAN0_AM23H()          bfin_read16(CAN0_AM23H)
+#define bfin_write_CAN0_AM23H(val)      bfin_write16(CAN0_AM23H, val)
+#define bfin_read_CAN0_AM24L()          bfin_read16(CAN0_AM24L)
+#define bfin_write_CAN0_AM24L(val)      bfin_write16(CAN0_AM24L, val)
+#define bfin_read_CAN0_AM24H()          bfin_read16(CAN0_AM24H)
+#define bfin_write_CAN0_AM24H(val)      bfin_write16(CAN0_AM24H, val)
+#define bfin_read_CAN0_AM25L()          bfin_read16(CAN0_AM25L)
+#define bfin_write_CAN0_AM25L(val)      bfin_write16(CAN0_AM25L, val)
+#define bfin_read_CAN0_AM25H()          bfin_read16(CAN0_AM25H)
+#define bfin_write_CAN0_AM25H(val)      bfin_write16(CAN0_AM25H, val)
+#define bfin_read_CAN0_AM26L()          bfin_read16(CAN0_AM26L)
+#define bfin_write_CAN0_AM26L(val)      bfin_write16(CAN0_AM26L, val)
+#define bfin_read_CAN0_AM26H()          bfin_read16(CAN0_AM26H)
+#define bfin_write_CAN0_AM26H(val)      bfin_write16(CAN0_AM26H, val)
+#define bfin_read_CAN0_AM27L()          bfin_read16(CAN0_AM27L)
+#define bfin_write_CAN0_AM27L(val)      bfin_write16(CAN0_AM27L, val)
+#define bfin_read_CAN0_AM27H()          bfin_read16(CAN0_AM27H)
+#define bfin_write_CAN0_AM27H(val)      bfin_write16(CAN0_AM27H, val)
+#define bfin_read_CAN0_AM28L()          bfin_read16(CAN0_AM28L)
+#define bfin_write_CAN0_AM28L(val)      bfin_write16(CAN0_AM28L, val)
+#define bfin_read_CAN0_AM28H()          bfin_read16(CAN0_AM28H)
+#define bfin_write_CAN0_AM28H(val)      bfin_write16(CAN0_AM28H, val)
+#define bfin_read_CAN0_AM29L()          bfin_read16(CAN0_AM29L)
+#define bfin_write_CAN0_AM29L(val)      bfin_write16(CAN0_AM29L, val)
+#define bfin_read_CAN0_AM29H()          bfin_read16(CAN0_AM29H)
+#define bfin_write_CAN0_AM29H(val)      bfin_write16(CAN0_AM29H, val)
+#define bfin_read_CAN0_AM30L()          bfin_read16(CAN0_AM30L)
+#define bfin_write_CAN0_AM30L(val)      bfin_write16(CAN0_AM30L, val)
+#define bfin_read_CAN0_AM30H()          bfin_read16(CAN0_AM30H)
+#define bfin_write_CAN0_AM30H(val)      bfin_write16(CAN0_AM30H, val)
+#define bfin_read_CAN0_AM31L()          bfin_read16(CAN0_AM31L)
+#define bfin_write_CAN0_AM31L(val)      bfin_write16(CAN0_AM31L, val)
+#define bfin_read_CAN0_AM31H()          bfin_read16(CAN0_AM31H)
+#define bfin_write_CAN0_AM31H(val)      bfin_write16(CAN0_AM31H, val)
+
+/* CAN Controller 0 Mailbox Data Registers */
+
+#define bfin_read_CAN0_MB00_DATA0()             bfin_read16(CAN0_MB00_DATA0)
+#define bfin_write_CAN0_MB00_DATA0(val)         bfin_write16(CAN0_MB00_DATA0, val)
+#define bfin_read_CAN0_MB00_DATA1()             bfin_read16(CAN0_MB00_DATA1)
+#define bfin_write_CAN0_MB00_DATA1(val)         bfin_write16(CAN0_MB00_DATA1, val)
+#define bfin_read_CAN0_MB00_DATA2()             bfin_read16(CAN0_MB00_DATA2)
+#define bfin_write_CAN0_MB00_DATA2(val)         bfin_write16(CAN0_MB00_DATA2, val)
+#define bfin_read_CAN0_MB00_DATA3()             bfin_read16(CAN0_MB00_DATA3)
+#define bfin_write_CAN0_MB00_DATA3(val)         bfin_write16(CAN0_MB00_DATA3, val)
+#define bfin_read_CAN0_MB00_LENGTH()            bfin_read16(CAN0_MB00_LENGTH)
+#define bfin_write_CAN0_MB00_LENGTH(val)        bfin_write16(CAN0_MB00_LENGTH, val)
+#define bfin_read_CAN0_MB00_TIMESTAMP()         bfin_read16(CAN0_MB00_TIMESTAMP)
+#define bfin_write_CAN0_MB00_TIMESTAMP(val)     bfin_write16(CAN0_MB00_TIMESTAMP, val)
+#define bfin_read_CAN0_MB00_ID0()               bfin_read16(CAN0_MB00_ID0)
+#define bfin_write_CAN0_MB00_ID0(val)           bfin_write16(CAN0_MB00_ID0, val)
+#define bfin_read_CAN0_MB00_ID1()               bfin_read16(CAN0_MB00_ID1)
+#define bfin_write_CAN0_MB00_ID1(val)           bfin_write16(CAN0_MB00_ID1, val)
+#define bfin_read_CAN0_MB01_DATA0()             bfin_read16(CAN0_MB01_DATA0)
+#define bfin_write_CAN0_MB01_DATA0(val)         bfin_write16(CAN0_MB01_DATA0, val)
+#define bfin_read_CAN0_MB01_DATA1()             bfin_read16(CAN0_MB01_DATA1)
+#define bfin_write_CAN0_MB01_DATA1(val)         bfin_write16(CAN0_MB01_DATA1, val)
+#define bfin_read_CAN0_MB01_DATA2()             bfin_read16(CAN0_MB01_DATA2)
+#define bfin_write_CAN0_MB01_DATA2(val)         bfin_write16(CAN0_MB01_DATA2, val)
+#define bfin_read_CAN0_MB01_DATA3()             bfin_read16(CAN0_MB01_DATA3)
+#define bfin_write_CAN0_MB01_DATA3(val)         bfin_write16(CAN0_MB01_DATA3, val)
+#define bfin_read_CAN0_MB01_LENGTH()            bfin_read16(CAN0_MB01_LENGTH)
+#define bfin_write_CAN0_MB01_LENGTH(val)        bfin_write16(CAN0_MB01_LENGTH, val)
+#define bfin_read_CAN0_MB01_TIMESTAMP()         bfin_read16(CAN0_MB01_TIMESTAMP)
+#define bfin_write_CAN0_MB01_TIMESTAMP(val)     bfin_write16(CAN0_MB01_TIMESTAMP, val)
+#define bfin_read_CAN0_MB01_ID0()               bfin_read16(CAN0_MB01_ID0)
+#define bfin_write_CAN0_MB01_ID0(val)           bfin_write16(CAN0_MB01_ID0, val)
+#define bfin_read_CAN0_MB01_ID1()               bfin_read16(CAN0_MB01_ID1)
+#define bfin_write_CAN0_MB01_ID1(val)           bfin_write16(CAN0_MB01_ID1, val)
+#define bfin_read_CAN0_MB02_DATA0()             bfin_read16(CAN0_MB02_DATA0)
+#define bfin_write_CAN0_MB02_DATA0(val)         bfin_write16(CAN0_MB02_DATA0, val)
+#define bfin_read_CAN0_MB02_DATA1()             bfin_read16(CAN0_MB02_DATA1)
+#define bfin_write_CAN0_MB02_DATA1(val)         bfin_write16(CAN0_MB02_DATA1, val)
+#define bfin_read_CAN0_MB02_DATA2()             bfin_read16(CAN0_MB02_DATA2)
+#define bfin_write_CAN0_MB02_DATA2(val)         bfin_write16(CAN0_MB02_DATA2, val)
+#define bfin_read_CAN0_MB02_DATA3()             bfin_read16(CAN0_MB02_DATA3)
+#define bfin_write_CAN0_MB02_DATA3(val)         bfin_write16(CAN0_MB02_DATA3, val)
+#define bfin_read_CAN0_MB02_LENGTH()            bfin_read16(CAN0_MB02_LENGTH)
+#define bfin_write_CAN0_MB02_LENGTH(val)        bfin_write16(CAN0_MB02_LENGTH, val)
+#define bfin_read_CAN0_MB02_TIMESTAMP()         bfin_read16(CAN0_MB02_TIMESTAMP)
+#define bfin_write_CAN0_MB02_TIMESTAMP(val)     bfin_write16(CAN0_MB02_TIMESTAMP, val)
+#define bfin_read_CAN0_MB02_ID0()               bfin_read16(CAN0_MB02_ID0)
+#define bfin_write_CAN0_MB02_ID0(val)           bfin_write16(CAN0_MB02_ID0, val)
+#define bfin_read_CAN0_MB02_ID1()               bfin_read16(CAN0_MB02_ID1)
+#define bfin_write_CAN0_MB02_ID1(val)           bfin_write16(CAN0_MB02_ID1, val)
+#define bfin_read_CAN0_MB03_DATA0()             bfin_read16(CAN0_MB03_DATA0)
+#define bfin_write_CAN0_MB03_DATA0(val)         bfin_write16(CAN0_MB03_DATA0, val)
+#define bfin_read_CAN0_MB03_DATA1()             bfin_read16(CAN0_MB03_DATA1)
+#define bfin_write_CAN0_MB03_DATA1(val)         bfin_write16(CAN0_MB03_DATA1, val)
+#define bfin_read_CAN0_MB03_DATA2()             bfin_read16(CAN0_MB03_DATA2)
+#define bfin_write_CAN0_MB03_DATA2(val)         bfin_write16(CAN0_MB03_DATA2, val)
+#define bfin_read_CAN0_MB03_DATA3()             bfin_read16(CAN0_MB03_DATA3)
+#define bfin_write_CAN0_MB03_DATA3(val)         bfin_write16(CAN0_MB03_DATA3, val)
+#define bfin_read_CAN0_MB03_LENGTH()            bfin_read16(CAN0_MB03_LENGTH)
+#define bfin_write_CAN0_MB03_LENGTH(val)        bfin_write16(CAN0_MB03_LENGTH, val)
+#define bfin_read_CAN0_MB03_TIMESTAMP()         bfin_read16(CAN0_MB03_TIMESTAMP)
+#define bfin_write_CAN0_MB03_TIMESTAMP(val)     bfin_write16(CAN0_MB03_TIMESTAMP, val)
+#define bfin_read_CAN0_MB03_ID0()               bfin_read16(CAN0_MB03_ID0)
+#define bfin_write_CAN0_MB03_ID0(val)           bfin_write16(CAN0_MB03_ID0, val)
+#define bfin_read_CAN0_MB03_ID1()               bfin_read16(CAN0_MB03_ID1)
+#define bfin_write_CAN0_MB03_ID1(val)           bfin_write16(CAN0_MB03_ID1, val)
+#define bfin_read_CAN0_MB04_DATA0()             bfin_read16(CAN0_MB04_DATA0)
+#define bfin_write_CAN0_MB04_DATA0(val)         bfin_write16(CAN0_MB04_DATA0, val)
+#define bfin_read_CAN0_MB04_DATA1()             bfin_read16(CAN0_MB04_DATA1)
+#define bfin_write_CAN0_MB04_DATA1(val)         bfin_write16(CAN0_MB04_DATA1, val)
+#define bfin_read_CAN0_MB04_DATA2()             bfin_read16(CAN0_MB04_DATA2)
+#define bfin_write_CAN0_MB04_DATA2(val)         bfin_write16(CAN0_MB04_DATA2, val)
+#define bfin_read_CAN0_MB04_DATA3()             bfin_read16(CAN0_MB04_DATA3)
+#define bfin_write_CAN0_MB04_DATA3(val)         bfin_write16(CAN0_MB04_DATA3, val)
+#define bfin_read_CAN0_MB04_LENGTH()            bfin_read16(CAN0_MB04_LENGTH)
+#define bfin_write_CAN0_MB04_LENGTH(val)        bfin_write16(CAN0_MB04_LENGTH, val)
+#define bfin_read_CAN0_MB04_TIMESTAMP()         bfin_read16(CAN0_MB04_TIMESTAMP)
+#define bfin_write_CAN0_MB04_TIMESTAMP(val)     bfin_write16(CAN0_MB04_TIMESTAMP, val)
+#define bfin_read_CAN0_MB04_ID0()               bfin_read16(CAN0_MB04_ID0)
+#define bfin_write_CAN0_MB04_ID0(val)           bfin_write16(CAN0_MB04_ID0, val)
+#define bfin_read_CAN0_MB04_ID1()               bfin_read16(CAN0_MB04_ID1)
+#define bfin_write_CAN0_MB04_ID1(val)           bfin_write16(CAN0_MB04_ID1, val)
+#define bfin_read_CAN0_MB05_DATA0()             bfin_read16(CAN0_MB05_DATA0)
+#define bfin_write_CAN0_MB05_DATA0(val)         bfin_write16(CAN0_MB05_DATA0, val)
+#define bfin_read_CAN0_MB05_DATA1()             bfin_read16(CAN0_MB05_DATA1)
+#define bfin_write_CAN0_MB05_DATA1(val)         bfin_write16(CAN0_MB05_DATA1, val)
+#define bfin_read_CAN0_MB05_DATA2()             bfin_read16(CAN0_MB05_DATA2)
+#define bfin_write_CAN0_MB05_DATA2(val)         bfin_write16(CAN0_MB05_DATA2, val)
+#define bfin_read_CAN0_MB05_DATA3()             bfin_read16(CAN0_MB05_DATA3)
+#define bfin_write_CAN0_MB05_DATA3(val)         bfin_write16(CAN0_MB05_DATA3, val)
+#define bfin_read_CAN0_MB05_LENGTH()            bfin_read16(CAN0_MB05_LENGTH)
+#define bfin_write_CAN0_MB05_LENGTH(val)        bfin_write16(CAN0_MB05_LENGTH, val)
+#define bfin_read_CAN0_MB05_TIMESTAMP()         bfin_read16(CAN0_MB05_TIMESTAMP)
+#define bfin_write_CAN0_MB05_TIMESTAMP(val)     bfin_write16(CAN0_MB05_TIMESTAMP, val)
+#define bfin_read_CAN0_MB05_ID0()               bfin_read16(CAN0_MB05_ID0)
+#define bfin_write_CAN0_MB05_ID0(val)           bfin_write16(CAN0_MB05_ID0, val)
+#define bfin_read_CAN0_MB05_ID1()               bfin_read16(CAN0_MB05_ID1)
+#define bfin_write_CAN0_MB05_ID1(val)           bfin_write16(CAN0_MB05_ID1, val)
+#define bfin_read_CAN0_MB06_DATA0()             bfin_read16(CAN0_MB06_DATA0)
+#define bfin_write_CAN0_MB06_DATA0(val)         bfin_write16(CAN0_MB06_DATA0, val)
+#define bfin_read_CAN0_MB06_DATA1()             bfin_read16(CAN0_MB06_DATA1)
+#define bfin_write_CAN0_MB06_DATA1(val)         bfin_write16(CAN0_MB06_DATA1, val)
+#define bfin_read_CAN0_MB06_DATA2()             bfin_read16(CAN0_MB06_DATA2)
+#define bfin_write_CAN0_MB06_DATA2(val)         bfin_write16(CAN0_MB06_DATA2, val)
+#define bfin_read_CAN0_MB06_DATA3()             bfin_read16(CAN0_MB06_DATA3)
+#define bfin_write_CAN0_MB06_DATA3(val)         bfin_write16(CAN0_MB06_DATA3, val)
+#define bfin_read_CAN0_MB06_LENGTH()            bfin_read16(CAN0_MB06_LENGTH)
+#define bfin_write_CAN0_MB06_LENGTH(val)        bfin_write16(CAN0_MB06_LENGTH, val)
+#define bfin_read_CAN0_MB06_TIMESTAMP()         bfin_read16(CAN0_MB06_TIMESTAMP)
+#define bfin_write_CAN0_MB06_TIMESTAMP(val)     bfin_write16(CAN0_MB06_TIMESTAMP, val)
+#define bfin_read_CAN0_MB06_ID0()               bfin_read16(CAN0_MB06_ID0)
+#define bfin_write_CAN0_MB06_ID0(val)           bfin_write16(CAN0_MB06_ID0, val)
+#define bfin_read_CAN0_MB06_ID1()               bfin_read16(CAN0_MB06_ID1)
+#define bfin_write_CAN0_MB06_ID1(val)           bfin_write16(CAN0_MB06_ID1, val)
+#define bfin_read_CAN0_MB07_DATA0()             bfin_read16(CAN0_MB07_DATA0)
+#define bfin_write_CAN0_MB07_DATA0(val)         bfin_write16(CAN0_MB07_DATA0, val)
+#define bfin_read_CAN0_MB07_DATA1()             bfin_read16(CAN0_MB07_DATA1)
+#define bfin_write_CAN0_MB07_DATA1(val)         bfin_write16(CAN0_MB07_DATA1, val)
+#define bfin_read_CAN0_MB07_DATA2()             bfin_read16(CAN0_MB07_DATA2)
+#define bfin_write_CAN0_MB07_DATA2(val)         bfin_write16(CAN0_MB07_DATA2, val)
+#define bfin_read_CAN0_MB07_DATA3()             bfin_read16(CAN0_MB07_DATA3)
+#define bfin_write_CAN0_MB07_DATA3(val)         bfin_write16(CAN0_MB07_DATA3, val)
+#define bfin_read_CAN0_MB07_LENGTH()            bfin_read16(CAN0_MB07_LENGTH)
+#define bfin_write_CAN0_MB07_LENGTH(val)        bfin_write16(CAN0_MB07_LENGTH, val)
+#define bfin_read_CAN0_MB07_TIMESTAMP()         bfin_read16(CAN0_MB07_TIMESTAMP)
+#define bfin_write_CAN0_MB07_TIMESTAMP(val)     bfin_write16(CAN0_MB07_TIMESTAMP, val)
+#define bfin_read_CAN0_MB07_ID0()               bfin_read16(CAN0_MB07_ID0)
+#define bfin_write_CAN0_MB07_ID0(val)           bfin_write16(CAN0_MB07_ID0, val)
+#define bfin_read_CAN0_MB07_ID1()               bfin_read16(CAN0_MB07_ID1)
+#define bfin_write_CAN0_MB07_ID1(val)           bfin_write16(CAN0_MB07_ID1, val)
+#define bfin_read_CAN0_MB08_DATA0()             bfin_read16(CAN0_MB08_DATA0)
+#define bfin_write_CAN0_MB08_DATA0(val)         bfin_write16(CAN0_MB08_DATA0, val)
+#define bfin_read_CAN0_MB08_DATA1()             bfin_read16(CAN0_MB08_DATA1)
+#define bfin_write_CAN0_MB08_DATA1(val)         bfin_write16(CAN0_MB08_DATA1, val)
+#define bfin_read_CAN0_MB08_DATA2()             bfin_read16(CAN0_MB08_DATA2)
+#define bfin_write_CAN0_MB08_DATA2(val)         bfin_write16(CAN0_MB08_DATA2, val)
+#define bfin_read_CAN0_MB08_DATA3()             bfin_read16(CAN0_MB08_DATA3)
+#define bfin_write_CAN0_MB08_DATA3(val)         bfin_write16(CAN0_MB08_DATA3, val)
+#define bfin_read_CAN0_MB08_LENGTH()            bfin_read16(CAN0_MB08_LENGTH)
+#define bfin_write_CAN0_MB08_LENGTH(val)        bfin_write16(CAN0_MB08_LENGTH, val)
+#define bfin_read_CAN0_MB08_TIMESTAMP()         bfin_read16(CAN0_MB08_TIMESTAMP)
+#define bfin_write_CAN0_MB08_TIMESTAMP(val)     bfin_write16(CAN0_MB08_TIMESTAMP, val)
+#define bfin_read_CAN0_MB08_ID0()               bfin_read16(CAN0_MB08_ID0)
+#define bfin_write_CAN0_MB08_ID0(val)           bfin_write16(CAN0_MB08_ID0, val)
+#define bfin_read_CAN0_MB08_ID1()               bfin_read16(CAN0_MB08_ID1)
+#define bfin_write_CAN0_MB08_ID1(val)           bfin_write16(CAN0_MB08_ID1, val)
+#define bfin_read_CAN0_MB09_DATA0()             bfin_read16(CAN0_MB09_DATA0)
+#define bfin_write_CAN0_MB09_DATA0(val)         bfin_write16(CAN0_MB09_DATA0, val)
+#define bfin_read_CAN0_MB09_DATA1()             bfin_read16(CAN0_MB09_DATA1)
+#define bfin_write_CAN0_MB09_DATA1(val)         bfin_write16(CAN0_MB09_DATA1, val)
+#define bfin_read_CAN0_MB09_DATA2()             bfin_read16(CAN0_MB09_DATA2)
+#define bfin_write_CAN0_MB09_DATA2(val)         bfin_write16(CAN0_MB09_DATA2, val)
+#define bfin_read_CAN0_MB09_DATA3()             bfin_read16(CAN0_MB09_DATA3)
+#define bfin_write_CAN0_MB09_DATA3(val)         bfin_write16(CAN0_MB09_DATA3, val)
+#define bfin_read_CAN0_MB09_LENGTH()            bfin_read16(CAN0_MB09_LENGTH)
+#define bfin_write_CAN0_MB09_LENGTH(val)        bfin_write16(CAN0_MB09_LENGTH, val)
+#define bfin_read_CAN0_MB09_TIMESTAMP()         bfin_read16(CAN0_MB09_TIMESTAMP)
+#define bfin_write_CAN0_MB09_TIMESTAMP(val)     bfin_write16(CAN0_MB09_TIMESTAMP, val)
+#define bfin_read_CAN0_MB09_ID0()               bfin_read16(CAN0_MB09_ID0)
+#define bfin_write_CAN0_MB09_ID0(val)           bfin_write16(CAN0_MB09_ID0, val)
+#define bfin_read_CAN0_MB09_ID1()               bfin_read16(CAN0_MB09_ID1)
+#define bfin_write_CAN0_MB09_ID1(val)           bfin_write16(CAN0_MB09_ID1, val)
+#define bfin_read_CAN0_MB10_DATA0()             bfin_read16(CAN0_MB10_DATA0)
+#define bfin_write_CAN0_MB10_DATA0(val)         bfin_write16(CAN0_MB10_DATA0, val)
+#define bfin_read_CAN0_MB10_DATA1()             bfin_read16(CAN0_MB10_DATA1)
+#define bfin_write_CAN0_MB10_DATA1(val)         bfin_write16(CAN0_MB10_DATA1, val)
+#define bfin_read_CAN0_MB10_DATA2()             bfin_read16(CAN0_MB10_DATA2)
+#define bfin_write_CAN0_MB10_DATA2(val)         bfin_write16(CAN0_MB10_DATA2, val)
+#define bfin_read_CAN0_MB10_DATA3()             bfin_read16(CAN0_MB10_DATA3)
+#define bfin_write_CAN0_MB10_DATA3(val)         bfin_write16(CAN0_MB10_DATA3, val)
+#define bfin_read_CAN0_MB10_LENGTH()            bfin_read16(CAN0_MB10_LENGTH)
+#define bfin_write_CAN0_MB10_LENGTH(val)        bfin_write16(CAN0_MB10_LENGTH, val)
+#define bfin_read_CAN0_MB10_TIMESTAMP()         bfin_read16(CAN0_MB10_TIMESTAMP)
+#define bfin_write_CAN0_MB10_TIMESTAMP(val)     bfin_write16(CAN0_MB10_TIMESTAMP, val)
+#define bfin_read_CAN0_MB10_ID0()               bfin_read16(CAN0_MB10_ID0)
+#define bfin_write_CAN0_MB10_ID0(val)           bfin_write16(CAN0_MB10_ID0, val)
+#define bfin_read_CAN0_MB10_ID1()               bfin_read16(CAN0_MB10_ID1)
+#define bfin_write_CAN0_MB10_ID1(val)           bfin_write16(CAN0_MB10_ID1, val)
+#define bfin_read_CAN0_MB11_DATA0()             bfin_read16(CAN0_MB11_DATA0)
+#define bfin_write_CAN0_MB11_DATA0(val)         bfin_write16(CAN0_MB11_DATA0, val)
+#define bfin_read_CAN0_MB11_DATA1()             bfin_read16(CAN0_MB11_DATA1)
+#define bfin_write_CAN0_MB11_DATA1(val)         bfin_write16(CAN0_MB11_DATA1, val)
+#define bfin_read_CAN0_MB11_DATA2()             bfin_read16(CAN0_MB11_DATA2)
+#define bfin_write_CAN0_MB11_DATA2(val)         bfin_write16(CAN0_MB11_DATA2, val)
+#define bfin_read_CAN0_MB11_DATA3()             bfin_read16(CAN0_MB11_DATA3)
+#define bfin_write_CAN0_MB11_DATA3(val)         bfin_write16(CAN0_MB11_DATA3, val)
+#define bfin_read_CAN0_MB11_LENGTH()            bfin_read16(CAN0_MB11_LENGTH)
+#define bfin_write_CAN0_MB11_LENGTH(val)        bfin_write16(CAN0_MB11_LENGTH, val)
+#define bfin_read_CAN0_MB11_TIMESTAMP()         bfin_read16(CAN0_MB11_TIMESTAMP)
+#define bfin_write_CAN0_MB11_TIMESTAMP(val)     bfin_write16(CAN0_MB11_TIMESTAMP, val)
+#define bfin_read_CAN0_MB11_ID0()               bfin_read16(CAN0_MB11_ID0)
+#define bfin_write_CAN0_MB11_ID0(val)           bfin_write16(CAN0_MB11_ID0, val)
+#define bfin_read_CAN0_MB11_ID1()               bfin_read16(CAN0_MB11_ID1)
+#define bfin_write_CAN0_MB11_ID1(val)           bfin_write16(CAN0_MB11_ID1, val)
+#define bfin_read_CAN0_MB12_DATA0()             bfin_read16(CAN0_MB12_DATA0)
+#define bfin_write_CAN0_MB12_DATA0(val)         bfin_write16(CAN0_MB12_DATA0, val)
+#define bfin_read_CAN0_MB12_DATA1()             bfin_read16(CAN0_MB12_DATA1)
+#define bfin_write_CAN0_MB12_DATA1(val)         bfin_write16(CAN0_MB12_DATA1, val)
+#define bfin_read_CAN0_MB12_DATA2()             bfin_read16(CAN0_MB12_DATA2)
+#define bfin_write_CAN0_MB12_DATA2(val)         bfin_write16(CAN0_MB12_DATA2, val)
+#define bfin_read_CAN0_MB12_DATA3()             bfin_read16(CAN0_MB12_DATA3)
+#define bfin_write_CAN0_MB12_DATA3(val)         bfin_write16(CAN0_MB12_DATA3, val)
+#define bfin_read_CAN0_MB12_LENGTH()            bfin_read16(CAN0_MB12_LENGTH)
+#define bfin_write_CAN0_MB12_LENGTH(val)        bfin_write16(CAN0_MB12_LENGTH, val)
+#define bfin_read_CAN0_MB12_TIMESTAMP()         bfin_read16(CAN0_MB12_TIMESTAMP)
+#define bfin_write_CAN0_MB12_TIMESTAMP(val)     bfin_write16(CAN0_MB12_TIMESTAMP, val)
+#define bfin_read_CAN0_MB12_ID0()               bfin_read16(CAN0_MB12_ID0)
+#define bfin_write_CAN0_MB12_ID0(val)           bfin_write16(CAN0_MB12_ID0, val)
+#define bfin_read_CAN0_MB12_ID1()               bfin_read16(CAN0_MB12_ID1)
+#define bfin_write_CAN0_MB12_ID1(val)           bfin_write16(CAN0_MB12_ID1, val)
+#define bfin_read_CAN0_MB13_DATA0()             bfin_read16(CAN0_MB13_DATA0)
+#define bfin_write_CAN0_MB13_DATA0(val)         bfin_write16(CAN0_MB13_DATA0, val)
+#define bfin_read_CAN0_MB13_DATA1()             bfin_read16(CAN0_MB13_DATA1)
+#define bfin_write_CAN0_MB13_DATA1(val)         bfin_write16(CAN0_MB13_DATA1, val)
+#define bfin_read_CAN0_MB13_DATA2()             bfin_read16(CAN0_MB13_DATA2)
+#define bfin_write_CAN0_MB13_DATA2(val)         bfin_write16(CAN0_MB13_DATA2, val)
+#define bfin_read_CAN0_MB13_DATA3()             bfin_read16(CAN0_MB13_DATA3)
+#define bfin_write_CAN0_MB13_DATA3(val)         bfin_write16(CAN0_MB13_DATA3, val)
+#define bfin_read_CAN0_MB13_LENGTH()            bfin_read16(CAN0_MB13_LENGTH)
+#define bfin_write_CAN0_MB13_LENGTH(val)        bfin_write16(CAN0_MB13_LENGTH, val)
+#define bfin_read_CAN0_MB13_TIMESTAMP()         bfin_read16(CAN0_MB13_TIMESTAMP)
+#define bfin_write_CAN0_MB13_TIMESTAMP(val)     bfin_write16(CAN0_MB13_TIMESTAMP, val)
+#define bfin_read_CAN0_MB13_ID0()               bfin_read16(CAN0_MB13_ID0)
+#define bfin_write_CAN0_MB13_ID0(val)           bfin_write16(CAN0_MB13_ID0, val)
+#define bfin_read_CAN0_MB13_ID1()               bfin_read16(CAN0_MB13_ID1)
+#define bfin_write_CAN0_MB13_ID1(val)           bfin_write16(CAN0_MB13_ID1, val)
+#define bfin_read_CAN0_MB14_DATA0()             bfin_read16(CAN0_MB14_DATA0)
+#define bfin_write_CAN0_MB14_DATA0(val)         bfin_write16(CAN0_MB14_DATA0, val)
+#define bfin_read_CAN0_MB14_DATA1()             bfin_read16(CAN0_MB14_DATA1)
+#define bfin_write_CAN0_MB14_DATA1(val)         bfin_write16(CAN0_MB14_DATA1, val)
+#define bfin_read_CAN0_MB14_DATA2()             bfin_read16(CAN0_MB14_DATA2)
+#define bfin_write_CAN0_MB14_DATA2(val)         bfin_write16(CAN0_MB14_DATA2, val)
+#define bfin_read_CAN0_MB14_DATA3()             bfin_read16(CAN0_MB14_DATA3)
+#define bfin_write_CAN0_MB14_DATA3(val)         bfin_write16(CAN0_MB14_DATA3, val)
+#define bfin_read_CAN0_MB14_LENGTH()            bfin_read16(CAN0_MB14_LENGTH)
+#define bfin_write_CAN0_MB14_LENGTH(val)        bfin_write16(CAN0_MB14_LENGTH, val)
+#define bfin_read_CAN0_MB14_TIMESTAMP()         bfin_read16(CAN0_MB14_TIMESTAMP)
+#define bfin_write_CAN0_MB14_TIMESTAMP(val)     bfin_write16(CAN0_MB14_TIMESTAMP, val)
+#define bfin_read_CAN0_MB14_ID0()               bfin_read16(CAN0_MB14_ID0)
+#define bfin_write_CAN0_MB14_ID0(val)           bfin_write16(CAN0_MB14_ID0, val)
+#define bfin_read_CAN0_MB14_ID1()               bfin_read16(CAN0_MB14_ID1)
+#define bfin_write_CAN0_MB14_ID1(val)           bfin_write16(CAN0_MB14_ID1, val)
+#define bfin_read_CAN0_MB15_DATA0()             bfin_read16(CAN0_MB15_DATA0)
+#define bfin_write_CAN0_MB15_DATA0(val)         bfin_write16(CAN0_MB15_DATA0, val)
+#define bfin_read_CAN0_MB15_DATA1()             bfin_read16(CAN0_MB15_DATA1)
+#define bfin_write_CAN0_MB15_DATA1(val)         bfin_write16(CAN0_MB15_DATA1, val)
+#define bfin_read_CAN0_MB15_DATA2()             bfin_read16(CAN0_MB15_DATA2)
+#define bfin_write_CAN0_MB15_DATA2(val)         bfin_write16(CAN0_MB15_DATA2, val)
+#define bfin_read_CAN0_MB15_DATA3()             bfin_read16(CAN0_MB15_DATA3)
+#define bfin_write_CAN0_MB15_DATA3(val)         bfin_write16(CAN0_MB15_DATA3, val)
+#define bfin_read_CAN0_MB15_LENGTH()            bfin_read16(CAN0_MB15_LENGTH)
+#define bfin_write_CAN0_MB15_LENGTH(val)        bfin_write16(CAN0_MB15_LENGTH, val)
+#define bfin_read_CAN0_MB15_TIMESTAMP()         bfin_read16(CAN0_MB15_TIMESTAMP)
+#define bfin_write_CAN0_MB15_TIMESTAMP(val)     bfin_write16(CAN0_MB15_TIMESTAMP, val)
+#define bfin_read_CAN0_MB15_ID0()               bfin_read16(CAN0_MB15_ID0)
+#define bfin_write_CAN0_MB15_ID0(val)           bfin_write16(CAN0_MB15_ID0, val)
+#define bfin_read_CAN0_MB15_ID1()               bfin_read16(CAN0_MB15_ID1)
+#define bfin_write_CAN0_MB15_ID1(val)           bfin_write16(CAN0_MB15_ID1, val)
+
+/* CAN Controller 0 Mailbox Data Registers */
+
+#define bfin_read_CAN0_MB16_DATA0()             bfin_read16(CAN0_MB16_DATA0)
+#define bfin_write_CAN0_MB16_DATA0(val)         bfin_write16(CAN0_MB16_DATA0, val)
+#define bfin_read_CAN0_MB16_DATA1()             bfin_read16(CAN0_MB16_DATA1)
+#define bfin_write_CAN0_MB16_DATA1(val)         bfin_write16(CAN0_MB16_DATA1, val)
+#define bfin_read_CAN0_MB16_DATA2()             bfin_read16(CAN0_MB16_DATA2)
+#define bfin_write_CAN0_MB16_DATA2(val)         bfin_write16(CAN0_MB16_DATA2, val)
+#define bfin_read_CAN0_MB16_DATA3()             bfin_read16(CAN0_MB16_DATA3)
+#define bfin_write_CAN0_MB16_DATA3(val)         bfin_write16(CAN0_MB16_DATA3, val)
+#define bfin_read_CAN0_MB16_LENGTH()            bfin_read16(CAN0_MB16_LENGTH)
+#define bfin_write_CAN0_MB16_LENGTH(val)        bfin_write16(CAN0_MB16_LENGTH, val)
+#define bfin_read_CAN0_MB16_TIMESTAMP()         bfin_read16(CAN0_MB16_TIMESTAMP)
+#define bfin_write_CAN0_MB16_TIMESTAMP(val)     bfin_write16(CAN0_MB16_TIMESTAMP, val)
+#define bfin_read_CAN0_MB16_ID0()               bfin_read16(CAN0_MB16_ID0)
+#define bfin_write_CAN0_MB16_ID0(val)           bfin_write16(CAN0_MB16_ID0, val)
+#define bfin_read_CAN0_MB16_ID1()               bfin_read16(CAN0_MB16_ID1)
+#define bfin_write_CAN0_MB16_ID1(val)           bfin_write16(CAN0_MB16_ID1, val)
+#define bfin_read_CAN0_MB17_DATA0()             bfin_read16(CAN0_MB17_DATA0)
+#define bfin_write_CAN0_MB17_DATA0(val)         bfin_write16(CAN0_MB17_DATA0, val)
+#define bfin_read_CAN0_MB17_DATA1()             bfin_read16(CAN0_MB17_DATA1)
+#define bfin_write_CAN0_MB17_DATA1(val)         bfin_write16(CAN0_MB17_DATA1, val)
+#define bfin_read_CAN0_MB17_DATA2()             bfin_read16(CAN0_MB17_DATA2)
+#define bfin_write_CAN0_MB17_DATA2(val)         bfin_write16(CAN0_MB17_DATA2, val)
+#define bfin_read_CAN0_MB17_DATA3()             bfin_read16(CAN0_MB17_DATA3)
+#define bfin_write_CAN0_MB17_DATA3(val)         bfin_write16(CAN0_MB17_DATA3, val)
+#define bfin_read_CAN0_MB17_LENGTH()            bfin_read16(CAN0_MB17_LENGTH)
+#define bfin_write_CAN0_MB17_LENGTH(val)        bfin_write16(CAN0_MB17_LENGTH, val)
+#define bfin_read_CAN0_MB17_TIMESTAMP()         bfin_read16(CAN0_MB17_TIMESTAMP)
+#define bfin_write_CAN0_MB17_TIMESTAMP(val)     bfin_write16(CAN0_MB17_TIMESTAMP, val)
+#define bfin_read_CAN0_MB17_ID0()               bfin_read16(CAN0_MB17_ID0)
+#define bfin_write_CAN0_MB17_ID0(val)           bfin_write16(CAN0_MB17_ID0, val)
+#define bfin_read_CAN0_MB17_ID1()               bfin_read16(CAN0_MB17_ID1)
+#define bfin_write_CAN0_MB17_ID1(val)           bfin_write16(CAN0_MB17_ID1, val)
+#define bfin_read_CAN0_MB18_DATA0()             bfin_read16(CAN0_MB18_DATA0)
+#define bfin_write_CAN0_MB18_DATA0(val)         bfin_write16(CAN0_MB18_DATA0, val)
+#define bfin_read_CAN0_MB18_DATA1()             bfin_read16(CAN0_MB18_DATA1)
+#define bfin_write_CAN0_MB18_DATA1(val)         bfin_write16(CAN0_MB18_DATA1, val)
+#define bfin_read_CAN0_MB18_DATA2()             bfin_read16(CAN0_MB18_DATA2)
+#define bfin_write_CAN0_MB18_DATA2(val)         bfin_write16(CAN0_MB18_DATA2, val)
+#define bfin_read_CAN0_MB18_DATA3()             bfin_read16(CAN0_MB18_DATA3)
+#define bfin_write_CAN0_MB18_DATA3(val)         bfin_write16(CAN0_MB18_DATA3, val)
+#define bfin_read_CAN0_MB18_LENGTH()            bfin_read16(CAN0_MB18_LENGTH)
+#define bfin_write_CAN0_MB18_LENGTH(val)        bfin_write16(CAN0_MB18_LENGTH, val)
+#define bfin_read_CAN0_MB18_TIMESTAMP()         bfin_read16(CAN0_MB18_TIMESTAMP)
+#define bfin_write_CAN0_MB18_TIMESTAMP(val)     bfin_write16(CAN0_MB18_TIMESTAMP, val)
+#define bfin_read_CAN0_MB18_ID0()               bfin_read16(CAN0_MB18_ID0)
+#define bfin_write_CAN0_MB18_ID0(val)           bfin_write16(CAN0_MB18_ID0, val)
+#define bfin_read_CAN0_MB18_ID1()               bfin_read16(CAN0_MB18_ID1)
+#define bfin_write_CAN0_MB18_ID1(val)           bfin_write16(CAN0_MB18_ID1, val)
+#define bfin_read_CAN0_MB19_DATA0()             bfin_read16(CAN0_MB19_DATA0)
+#define bfin_write_CAN0_MB19_DATA0(val)         bfin_write16(CAN0_MB19_DATA0, val)
+#define bfin_read_CAN0_MB19_DATA1()             bfin_read16(CAN0_MB19_DATA1)
+#define bfin_write_CAN0_MB19_DATA1(val)         bfin_write16(CAN0_MB19_DATA1, val)
+#define bfin_read_CAN0_MB19_DATA2()             bfin_read16(CAN0_MB19_DATA2)
+#define bfin_write_CAN0_MB19_DATA2(val)         bfin_write16(CAN0_MB19_DATA2, val)
+#define bfin_read_CAN0_MB19_DATA3()             bfin_read16(CAN0_MB19_DATA3)
+#define bfin_write_CAN0_MB19_DATA3(val)         bfin_write16(CAN0_MB19_DATA3, val)
+#define bfin_read_CAN0_MB19_LENGTH()            bfin_read16(CAN0_MB19_LENGTH)
+#define bfin_write_CAN0_MB19_LENGTH(val)        bfin_write16(CAN0_MB19_LENGTH, val)
+#define bfin_read_CAN0_MB19_TIMESTAMP()         bfin_read16(CAN0_MB19_TIMESTAMP)
+#define bfin_write_CAN0_MB19_TIMESTAMP(val)     bfin_write16(CAN0_MB19_TIMESTAMP, val)
+#define bfin_read_CAN0_MB19_ID0()               bfin_read16(CAN0_MB19_ID0)
+#define bfin_write_CAN0_MB19_ID0(val)           bfin_write16(CAN0_MB19_ID0, val)
+#define bfin_read_CAN0_MB19_ID1()               bfin_read16(CAN0_MB19_ID1)
+#define bfin_write_CAN0_MB19_ID1(val)           bfin_write16(CAN0_MB19_ID1, val)
+#define bfin_read_CAN0_MB20_DATA0()             bfin_read16(CAN0_MB20_DATA0)
+#define bfin_write_CAN0_MB20_DATA0(val)         bfin_write16(CAN0_MB20_DATA0, val)
+#define bfin_read_CAN0_MB20_DATA1()             bfin_read16(CAN0_MB20_DATA1)
+#define bfin_write_CAN0_MB20_DATA1(val)         bfin_write16(CAN0_MB20_DATA1, val)
+#define bfin_read_CAN0_MB20_DATA2()             bfin_read16(CAN0_MB20_DATA2)
+#define bfin_write_CAN0_MB20_DATA2(val)         bfin_write16(CAN0_MB20_DATA2, val)
+#define bfin_read_CAN0_MB20_DATA3()             bfin_read16(CAN0_MB20_DATA3)
+#define bfin_write_CAN0_MB20_DATA3(val)         bfin_write16(CAN0_MB20_DATA3, val)
+#define bfin_read_CAN0_MB20_LENGTH()            bfin_read16(CAN0_MB20_LENGTH)
+#define bfin_write_CAN0_MB20_LENGTH(val)        bfin_write16(CAN0_MB20_LENGTH, val)
+#define bfin_read_CAN0_MB20_TIMESTAMP()         bfin_read16(CAN0_MB20_TIMESTAMP)
+#define bfin_write_CAN0_MB20_TIMESTAMP(val)     bfin_write16(CAN0_MB20_TIMESTAMP, val)
+#define bfin_read_CAN0_MB20_ID0()               bfin_read16(CAN0_MB20_ID0)
+#define bfin_write_CAN0_MB20_ID0(val)           bfin_write16(CAN0_MB20_ID0, val)
+#define bfin_read_CAN0_MB20_ID1()               bfin_read16(CAN0_MB20_ID1)
+#define bfin_write_CAN0_MB20_ID1(val)           bfin_write16(CAN0_MB20_ID1, val)
+#define bfin_read_CAN0_MB21_DATA0()             bfin_read16(CAN0_MB21_DATA0)
+#define bfin_write_CAN0_MB21_DATA0(val)         bfin_write16(CAN0_MB21_DATA0, val)
+#define bfin_read_CAN0_MB21_DATA1()             bfin_read16(CAN0_MB21_DATA1)
+#define bfin_write_CAN0_MB21_DATA1(val)         bfin_write16(CAN0_MB21_DATA1, val)
+#define bfin_read_CAN0_MB21_DATA2()             bfin_read16(CAN0_MB21_DATA2)
+#define bfin_write_CAN0_MB21_DATA2(val)         bfin_write16(CAN0_MB21_DATA2, val)
+#define bfin_read_CAN0_MB21_DATA3()             bfin_read16(CAN0_MB21_DATA3)
+#define bfin_write_CAN0_MB21_DATA3(val)         bfin_write16(CAN0_MB21_DATA3, val)
+#define bfin_read_CAN0_MB21_LENGTH()            bfin_read16(CAN0_MB21_LENGTH)
+#define bfin_write_CAN0_MB21_LENGTH(val)        bfin_write16(CAN0_MB21_LENGTH, val)
+#define bfin_read_CAN0_MB21_TIMESTAMP()         bfin_read16(CAN0_MB21_TIMESTAMP)
+#define bfin_write_CAN0_MB21_TIMESTAMP(val)     bfin_write16(CAN0_MB21_TIMESTAMP, val)
+#define bfin_read_CAN0_MB21_ID0()               bfin_read16(CAN0_MB21_ID0)
+#define bfin_write_CAN0_MB21_ID0(val)           bfin_write16(CAN0_MB21_ID0, val)
+#define bfin_read_CAN0_MB21_ID1()               bfin_read16(CAN0_MB21_ID1)
+#define bfin_write_CAN0_MB21_ID1(val)           bfin_write16(CAN0_MB21_ID1, val)
+#define bfin_read_CAN0_MB22_DATA0()             bfin_read16(CAN0_MB22_DATA0)
+#define bfin_write_CAN0_MB22_DATA0(val)         bfin_write16(CAN0_MB22_DATA0, val)
+#define bfin_read_CAN0_MB22_DATA1()             bfin_read16(CAN0_MB22_DATA1)
+#define bfin_write_CAN0_MB22_DATA1(val)         bfin_write16(CAN0_MB22_DATA1, val)
+#define bfin_read_CAN0_MB22_DATA2()             bfin_read16(CAN0_MB22_DATA2)
+#define bfin_write_CAN0_MB22_DATA2(val)         bfin_write16(CAN0_MB22_DATA2, val)
+#define bfin_read_CAN0_MB22_DATA3()             bfin_read16(CAN0_MB22_DATA3)
+#define bfin_write_CAN0_MB22_DATA3(val)         bfin_write16(CAN0_MB22_DATA3, val)
+#define bfin_read_CAN0_MB22_LENGTH()            bfin_read16(CAN0_MB22_LENGTH)
+#define bfin_write_CAN0_MB22_LENGTH(val)        bfin_write16(CAN0_MB22_LENGTH, val)
+#define bfin_read_CAN0_MB22_TIMESTAMP()         bfin_read16(CAN0_MB22_TIMESTAMP)
+#define bfin_write_CAN0_MB22_TIMESTAMP(val)     bfin_write16(CAN0_MB22_TIMESTAMP, val)
+#define bfin_read_CAN0_MB22_ID0()               bfin_read16(CAN0_MB22_ID0)
+#define bfin_write_CAN0_MB22_ID0(val)           bfin_write16(CAN0_MB22_ID0, val)
+#define bfin_read_CAN0_MB22_ID1()               bfin_read16(CAN0_MB22_ID1)
+#define bfin_write_CAN0_MB22_ID1(val)           bfin_write16(CAN0_MB22_ID1, val)
+#define bfin_read_CAN0_MB23_DATA0()             bfin_read16(CAN0_MB23_DATA0)
+#define bfin_write_CAN0_MB23_DATA0(val)         bfin_write16(CAN0_MB23_DATA0, val)
+#define bfin_read_CAN0_MB23_DATA1()             bfin_read16(CAN0_MB23_DATA1)
+#define bfin_write_CAN0_MB23_DATA1(val)         bfin_write16(CAN0_MB23_DATA1, val)
+#define bfin_read_CAN0_MB23_DATA2()             bfin_read16(CAN0_MB23_DATA2)
+#define bfin_write_CAN0_MB23_DATA2(val)         bfin_write16(CAN0_MB23_DATA2, val)
+#define bfin_read_CAN0_MB23_DATA3()             bfin_read16(CAN0_MB23_DATA3)
+#define bfin_write_CAN0_MB23_DATA3(val)         bfin_write16(CAN0_MB23_DATA3, val)
+#define bfin_read_CAN0_MB23_LENGTH()            bfin_read16(CAN0_MB23_LENGTH)
+#define bfin_write_CAN0_MB23_LENGTH(val)        bfin_write16(CAN0_MB23_LENGTH, val)
+#define bfin_read_CAN0_MB23_TIMESTAMP()         bfin_read16(CAN0_MB23_TIMESTAMP)
+#define bfin_write_CAN0_MB23_TIMESTAMP(val)     bfin_write16(CAN0_MB23_TIMESTAMP, val)
+#define bfin_read_CAN0_MB23_ID0()               bfin_read16(CAN0_MB23_ID0)
+#define bfin_write_CAN0_MB23_ID0(val)           bfin_write16(CAN0_MB23_ID0, val)
+#define bfin_read_CAN0_MB23_ID1()               bfin_read16(CAN0_MB23_ID1)
+#define bfin_write_CAN0_MB23_ID1(val)           bfin_write16(CAN0_MB23_ID1, val)
+#define bfin_read_CAN0_MB24_DATA0()             bfin_read16(CAN0_MB24_DATA0)
+#define bfin_write_CAN0_MB24_DATA0(val)         bfin_write16(CAN0_MB24_DATA0, val)
+#define bfin_read_CAN0_MB24_DATA1()             bfin_read16(CAN0_MB24_DATA1)
+#define bfin_write_CAN0_MB24_DATA1(val)         bfin_write16(CAN0_MB24_DATA1, val)
+#define bfin_read_CAN0_MB24_DATA2()             bfin_read16(CAN0_MB24_DATA2)
+#define bfin_write_CAN0_MB24_DATA2(val)         bfin_write16(CAN0_MB24_DATA2, val)
+#define bfin_read_CAN0_MB24_DATA3()             bfin_read16(CAN0_MB24_DATA3)
+#define bfin_write_CAN0_MB24_DATA3(val)         bfin_write16(CAN0_MB24_DATA3, val)
+#define bfin_read_CAN0_MB24_LENGTH()            bfin_read16(CAN0_MB24_LENGTH)
+#define bfin_write_CAN0_MB24_LENGTH(val)        bfin_write16(CAN0_MB24_LENGTH, val)
+#define bfin_read_CAN0_MB24_TIMESTAMP()         bfin_read16(CAN0_MB24_TIMESTAMP)
+#define bfin_write_CAN0_MB24_TIMESTAMP(val)     bfin_write16(CAN0_MB24_TIMESTAMP, val)
+#define bfin_read_CAN0_MB24_ID0()               bfin_read16(CAN0_MB24_ID0)
+#define bfin_write_CAN0_MB24_ID0(val)           bfin_write16(CAN0_MB24_ID0, val)
+#define bfin_read_CAN0_MB24_ID1()               bfin_read16(CAN0_MB24_ID1)
+#define bfin_write_CAN0_MB24_ID1(val)           bfin_write16(CAN0_MB24_ID1, val)
+#define bfin_read_CAN0_MB25_DATA0()             bfin_read16(CAN0_MB25_DATA0)
+#define bfin_write_CAN0_MB25_DATA0(val)         bfin_write16(CAN0_MB25_DATA0, val)
+#define bfin_read_CAN0_MB25_DATA1()             bfin_read16(CAN0_MB25_DATA1)
+#define bfin_write_CAN0_MB25_DATA1(val)         bfin_write16(CAN0_MB25_DATA1, val)
+#define bfin_read_CAN0_MB25_DATA2()             bfin_read16(CAN0_MB25_DATA2)
+#define bfin_write_CAN0_MB25_DATA2(val)         bfin_write16(CAN0_MB25_DATA2, val)
+#define bfin_read_CAN0_MB25_DATA3()             bfin_read16(CAN0_MB25_DATA3)
+#define bfin_write_CAN0_MB25_DATA3(val)         bfin_write16(CAN0_MB25_DATA3, val)
+#define bfin_read_CAN0_MB25_LENGTH()            bfin_read16(CAN0_MB25_LENGTH)
+#define bfin_write_CAN0_MB25_LENGTH(val)        bfin_write16(CAN0_MB25_LENGTH, val)
+#define bfin_read_CAN0_MB25_TIMESTAMP()         bfin_read16(CAN0_MB25_TIMESTAMP)
+#define bfin_write_CAN0_MB25_TIMESTAMP(val)     bfin_write16(CAN0_MB25_TIMESTAMP, val)
+#define bfin_read_CAN0_MB25_ID0()               bfin_read16(CAN0_MB25_ID0)
+#define bfin_write_CAN0_MB25_ID0(val)           bfin_write16(CAN0_MB25_ID0, val)
+#define bfin_read_CAN0_MB25_ID1()               bfin_read16(CAN0_MB25_ID1)
+#define bfin_write_CAN0_MB25_ID1(val)           bfin_write16(CAN0_MB25_ID1, val)
+#define bfin_read_CAN0_MB26_DATA0()             bfin_read16(CAN0_MB26_DATA0)
+#define bfin_write_CAN0_MB26_DATA0(val)         bfin_write16(CAN0_MB26_DATA0, val)
+#define bfin_read_CAN0_MB26_DATA1()             bfin_read16(CAN0_MB26_DATA1)
+#define bfin_write_CAN0_MB26_DATA1(val)         bfin_write16(CAN0_MB26_DATA1, val)
+#define bfin_read_CAN0_MB26_DATA2()             bfin_read16(CAN0_MB26_DATA2)
+#define bfin_write_CAN0_MB26_DATA2(val)         bfin_write16(CAN0_MB26_DATA2, val)
+#define bfin_read_CAN0_MB26_DATA3()             bfin_read16(CAN0_MB26_DATA3)
+#define bfin_write_CAN0_MB26_DATA3(val)         bfin_write16(CAN0_MB26_DATA3, val)
+#define bfin_read_CAN0_MB26_LENGTH()            bfin_read16(CAN0_MB26_LENGTH)
+#define bfin_write_CAN0_MB26_LENGTH(val)        bfin_write16(CAN0_MB26_LENGTH, val)
+#define bfin_read_CAN0_MB26_TIMESTAMP()         bfin_read16(CAN0_MB26_TIMESTAMP)
+#define bfin_write_CAN0_MB26_TIMESTAMP(val)     bfin_write16(CAN0_MB26_TIMESTAMP, val)
+#define bfin_read_CAN0_MB26_ID0()               bfin_read16(CAN0_MB26_ID0)
+#define bfin_write_CAN0_MB26_ID0(val)           bfin_write16(CAN0_MB26_ID0, val)
+#define bfin_read_CAN0_MB26_ID1()               bfin_read16(CAN0_MB26_ID1)
+#define bfin_write_CAN0_MB26_ID1(val)           bfin_write16(CAN0_MB26_ID1, val)
+#define bfin_read_CAN0_MB27_DATA0()             bfin_read16(CAN0_MB27_DATA0)
+#define bfin_write_CAN0_MB27_DATA0(val)         bfin_write16(CAN0_MB27_DATA0, val)
+#define bfin_read_CAN0_MB27_DATA1()             bfin_read16(CAN0_MB27_DATA1)
+#define bfin_write_CAN0_MB27_DATA1(val)         bfin_write16(CAN0_MB27_DATA1, val)
+#define bfin_read_CAN0_MB27_DATA2()             bfin_read16(CAN0_MB27_DATA2)
+#define bfin_write_CAN0_MB27_DATA2(val)         bfin_write16(CAN0_MB27_DATA2, val)
+#define bfin_read_CAN0_MB27_DATA3()             bfin_read16(CAN0_MB27_DATA3)
+#define bfin_write_CAN0_MB27_DATA3(val)         bfin_write16(CAN0_MB27_DATA3, val)
+#define bfin_read_CAN0_MB27_LENGTH()            bfin_read16(CAN0_MB27_LENGTH)
+#define bfin_write_CAN0_MB27_LENGTH(val)        bfin_write16(CAN0_MB27_LENGTH, val)
+#define bfin_read_CAN0_MB27_TIMESTAMP()         bfin_read16(CAN0_MB27_TIMESTAMP)
+#define bfin_write_CAN0_MB27_TIMESTAMP(val)     bfin_write16(CAN0_MB27_TIMESTAMP, val)
+#define bfin_read_CAN0_MB27_ID0()               bfin_read16(CAN0_MB27_ID0)
+#define bfin_write_CAN0_MB27_ID0(val)           bfin_write16(CAN0_MB27_ID0, val)
+#define bfin_read_CAN0_MB27_ID1()               bfin_read16(CAN0_MB27_ID1)
+#define bfin_write_CAN0_MB27_ID1(val)           bfin_write16(CAN0_MB27_ID1, val)
+#define bfin_read_CAN0_MB28_DATA0()             bfin_read16(CAN0_MB28_DATA0)
+#define bfin_write_CAN0_MB28_DATA0(val)         bfin_write16(CAN0_MB28_DATA0, val)
+#define bfin_read_CAN0_MB28_DATA1()             bfin_read16(CAN0_MB28_DATA1)
+#define bfin_write_CAN0_MB28_DATA1(val)         bfin_write16(CAN0_MB28_DATA1, val)
+#define bfin_read_CAN0_MB28_DATA2()             bfin_read16(CAN0_MB28_DATA2)
+#define bfin_write_CAN0_MB28_DATA2(val)         bfin_write16(CAN0_MB28_DATA2, val)
+#define bfin_read_CAN0_MB28_DATA3()             bfin_read16(CAN0_MB28_DATA3)
+#define bfin_write_CAN0_MB28_DATA3(val)         bfin_write16(CAN0_MB28_DATA3, val)
+#define bfin_read_CAN0_MB28_LENGTH()            bfin_read16(CAN0_MB28_LENGTH)
+#define bfin_write_CAN0_MB28_LENGTH(val)        bfin_write16(CAN0_MB28_LENGTH, val)
+#define bfin_read_CAN0_MB28_TIMESTAMP()         bfin_read16(CAN0_MB28_TIMESTAMP)
+#define bfin_write_CAN0_MB28_TIMESTAMP(val)     bfin_write16(CAN0_MB28_TIMESTAMP, val)
+#define bfin_read_CAN0_MB28_ID0()               bfin_read16(CAN0_MB28_ID0)
+#define bfin_write_CAN0_MB28_ID0(val)           bfin_write16(CAN0_MB28_ID0, val)
+#define bfin_read_CAN0_MB28_ID1()               bfin_read16(CAN0_MB28_ID1)
+#define bfin_write_CAN0_MB28_ID1(val)           bfin_write16(CAN0_MB28_ID1, val)
+#define bfin_read_CAN0_MB29_DATA0()             bfin_read16(CAN0_MB29_DATA0)
+#define bfin_write_CAN0_MB29_DATA0(val)         bfin_write16(CAN0_MB29_DATA0, val)
+#define bfin_read_CAN0_MB29_DATA1()             bfin_read16(CAN0_MB29_DATA1)
+#define bfin_write_CAN0_MB29_DATA1(val)         bfin_write16(CAN0_MB29_DATA1, val)
+#define bfin_read_CAN0_MB29_DATA2()             bfin_read16(CAN0_MB29_DATA2)
+#define bfin_write_CAN0_MB29_DATA2(val)         bfin_write16(CAN0_MB29_DATA2, val)
+#define bfin_read_CAN0_MB29_DATA3()             bfin_read16(CAN0_MB29_DATA3)
+#define bfin_write_CAN0_MB29_DATA3(val)         bfin_write16(CAN0_MB29_DATA3, val)
+#define bfin_read_CAN0_MB29_LENGTH()            bfin_read16(CAN0_MB29_LENGTH)
+#define bfin_write_CAN0_MB29_LENGTH(val)        bfin_write16(CAN0_MB29_LENGTH, val)
+#define bfin_read_CAN0_MB29_TIMESTAMP()         bfin_read16(CAN0_MB29_TIMESTAMP)
+#define bfin_write_CAN0_MB29_TIMESTAMP(val)     bfin_write16(CAN0_MB29_TIMESTAMP, val)
+#define bfin_read_CAN0_MB29_ID0()               bfin_read16(CAN0_MB29_ID0)
+#define bfin_write_CAN0_MB29_ID0(val)           bfin_write16(CAN0_MB29_ID0, val)
+#define bfin_read_CAN0_MB29_ID1()               bfin_read16(CAN0_MB29_ID1)
+#define bfin_write_CAN0_MB29_ID1(val)           bfin_write16(CAN0_MB29_ID1, val)
+#define bfin_read_CAN0_MB30_DATA0()             bfin_read16(CAN0_MB30_DATA0)
+#define bfin_write_CAN0_MB30_DATA0(val)         bfin_write16(CAN0_MB30_DATA0, val)
+#define bfin_read_CAN0_MB30_DATA1()             bfin_read16(CAN0_MB30_DATA1)
+#define bfin_write_CAN0_MB30_DATA1(val)         bfin_write16(CAN0_MB30_DATA1, val)
+#define bfin_read_CAN0_MB30_DATA2()             bfin_read16(CAN0_MB30_DATA2)
+#define bfin_write_CAN0_MB30_DATA2(val)         bfin_write16(CAN0_MB30_DATA2, val)
+#define bfin_read_CAN0_MB30_DATA3()             bfin_read16(CAN0_MB30_DATA3)
+#define bfin_write_CAN0_MB30_DATA3(val)         bfin_write16(CAN0_MB30_DATA3, val)
+#define bfin_read_CAN0_MB30_LENGTH()            bfin_read16(CAN0_MB30_LENGTH)
+#define bfin_write_CAN0_MB30_LENGTH(val)        bfin_write16(CAN0_MB30_LENGTH, val)
+#define bfin_read_CAN0_MB30_TIMESTAMP()         bfin_read16(CAN0_MB30_TIMESTAMP)
+#define bfin_write_CAN0_MB30_TIMESTAMP(val)     bfin_write16(CAN0_MB30_TIMESTAMP, val)
+#define bfin_read_CAN0_MB30_ID0()               bfin_read16(CAN0_MB30_ID0)
+#define bfin_write_CAN0_MB30_ID0(val)           bfin_write16(CAN0_MB30_ID0, val)
+#define bfin_read_CAN0_MB30_ID1()               bfin_read16(CAN0_MB30_ID1)
+#define bfin_write_CAN0_MB30_ID1(val)           bfin_write16(CAN0_MB30_ID1, val)
+#define bfin_read_CAN0_MB31_DATA0()             bfin_read16(CAN0_MB31_DATA0)
+#define bfin_write_CAN0_MB31_DATA0(val)         bfin_write16(CAN0_MB31_DATA0, val)
+#define bfin_read_CAN0_MB31_DATA1()             bfin_read16(CAN0_MB31_DATA1)
+#define bfin_write_CAN0_MB31_DATA1(val)         bfin_write16(CAN0_MB31_DATA1, val)
+#define bfin_read_CAN0_MB31_DATA2()             bfin_read16(CAN0_MB31_DATA2)
+#define bfin_write_CAN0_MB31_DATA2(val)         bfin_write16(CAN0_MB31_DATA2, val)
+#define bfin_read_CAN0_MB31_DATA3()             bfin_read16(CAN0_MB31_DATA3)
+#define bfin_write_CAN0_MB31_DATA3(val)         bfin_write16(CAN0_MB31_DATA3, val)
+#define bfin_read_CAN0_MB31_LENGTH()            bfin_read16(CAN0_MB31_LENGTH)
+#define bfin_write_CAN0_MB31_LENGTH(val)        bfin_write16(CAN0_MB31_LENGTH, val)
+#define bfin_read_CAN0_MB31_TIMESTAMP()         bfin_read16(CAN0_MB31_TIMESTAMP)
+#define bfin_write_CAN0_MB31_TIMESTAMP(val)     bfin_write16(CAN0_MB31_TIMESTAMP, val)
+#define bfin_read_CAN0_MB31_ID0()               bfin_read16(CAN0_MB31_ID0)
+#define bfin_write_CAN0_MB31_ID0(val)           bfin_write16(CAN0_MB31_ID0, val)
+#define bfin_read_CAN0_MB31_ID1()               bfin_read16(CAN0_MB31_ID1)
+#define bfin_write_CAN0_MB31_ID1(val)           bfin_write16(CAN0_MB31_ID1, val)
+
+/* UART3 Registers */
+
+#define bfin_read_UART3_DLL()           bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)       bfin_write16(UART3_DLL, val)
+#define bfin_read_UART3_DLH()           bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)       bfin_write16(UART3_DLH, val)
+#define bfin_read_UART3_GCTL()          bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)      bfin_write16(UART3_GCTL, val)
+#define bfin_read_UART3_LCR()           bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)       bfin_write16(UART3_LCR, val)
+#define bfin_read_UART3_MCR()           bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)       bfin_write16(UART3_MCR, val)
+#define bfin_read_UART3_LSR()           bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)       bfin_write16(UART3_LSR, val)
+#define bfin_read_UART3_MSR()           bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)       bfin_write16(UART3_MSR, val)
+#define bfin_read_UART3_SCR()           bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)       bfin_write16(UART3_SCR, val)
+#define bfin_read_UART3_IER_SET()       bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)   bfin_write16(UART3_IER_SET, val)
+#define bfin_read_UART3_IER_CLEAR()     bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define bfin_read_UART3_THR()           bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)       bfin_write16(UART3_THR, val)
+#define bfin_read_UART3_RBR()           bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)       bfin_write16(UART3_RBR, val)
+
+/* NFC Registers */
+
+#define bfin_read_NFC_CTL()             bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)         bfin_write16(NFC_CTL, val)
+#define bfin_read_NFC_STAT()            bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)        bfin_write16(NFC_STAT, val)
+#define bfin_read_NFC_IRQSTAT()         bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)     bfin_write16(NFC_IRQSTAT, val)
+#define bfin_read_NFC_IRQMASK()         bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)     bfin_write16(NFC_IRQMASK, val)
+#define bfin_read_NFC_ECC0()            bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)        bfin_write16(NFC_ECC0, val)
+#define bfin_read_NFC_ECC1()            bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)        bfin_write16(NFC_ECC1, val)
+#define bfin_read_NFC_ECC2()            bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)        bfin_write16(NFC_ECC2, val)
+#define bfin_read_NFC_ECC3()            bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)        bfin_write16(NFC_ECC3, val)
+#define bfin_read_NFC_COUNT()           bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)       bfin_write16(NFC_COUNT, val)
+#define bfin_read_NFC_RST()             bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)         bfin_write16(NFC_RST, val)
+#define bfin_read_NFC_PGCTL()           bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)       bfin_write16(NFC_PGCTL, val)
+#define bfin_read_NFC_READ()            bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)        bfin_write16(NFC_READ, val)
+#define bfin_read_NFC_ADDR()            bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)        bfin_write16(NFC_ADDR, val)
+#define bfin_read_NFC_CMD()             bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)         bfin_write16(NFC_CMD, val)
+#define bfin_read_NFC_DATA_WR()         bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)     bfin_write16(NFC_DATA_WR, val)
+#define bfin_read_NFC_DATA_RD()         bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)     bfin_write16(NFC_DATA_RD, val)
+
+/* Counter Registers */
+
+#define bfin_read_CNT_CONFIG()          bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)      bfin_write16(CNT_CONFIG, val)
+#define bfin_read_CNT_IMASK()           bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)       bfin_write16(CNT_IMASK, val)
+#define bfin_read_CNT_STATUS()          bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)      bfin_write16(CNT_STATUS, val)
+#define bfin_read_CNT_COMMAND()         bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)     bfin_write16(CNT_COMMAND, val)
+#define bfin_read_CNT_DEBOUNCE()        bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)    bfin_write16(CNT_DEBOUNCE, val)
+#define bfin_read_CNT_COUNTER()         bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)     bfin_write32(CNT_COUNTER, val)
+#define bfin_read_CNT_MAX()             bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)         bfin_write32(CNT_MAX, val)
+#define bfin_read_CNT_MIN()             bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)         bfin_write32(CNT_MIN, val)
+
+/* OTP/FUSE Registers */
+
+#define bfin_read_OTP_CONTROL()         bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)     bfin_write16(OTP_CONTROL, val)
+#define bfin_read_OTP_BEN()             bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)         bfin_write16(OTP_BEN, val)
+#define bfin_read_OTP_STATUS()          bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)      bfin_write16(OTP_STATUS, val)
+#define bfin_read_OTP_TIMING()          bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)      bfin_write32(OTP_TIMING, val)
+
+/* Security Registers */
+
+#define bfin_read_SECURE_SYSSWT()       bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)   bfin_write32(SECURE_SYSSWT, val)
+#define bfin_read_SECURE_CONTROL()      bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val)  bfin_write16(SECURE_CONTROL, val)
+#define bfin_read_SECURE_STATUS()       bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)   bfin_write16(SECURE_STATUS, val)
+
+/* DMA Peribfin_read_()heral Mux Register */
+
+#define bfin_read_DMAC1_PERIMUX()       bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)   bfin_write16(DMAC1_PERIMUX, val)
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define bfin_read_OTP_DATA0()           bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)       bfin_write32(OTP_DATA0, val)
+#define bfin_read_OTP_DATA1()           bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)       bfin_write32(OTP_DATA1, val)
+#define bfin_read_OTP_DATA2()           bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)       bfin_write32(OTP_DATA2, val)
+#define bfin_read_OTP_DATA3()           bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)       bfin_write32(OTP_DATA3, val)
+
+/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
+
+/* legacy definitions */
+#define bfin_read_EBIU_AMCBCTL0         bfin_read_EBIU_AMBCTL0
+#define bfin_write_EBIU_AMCBCTL0        bfin_write_EBIU_AMBCTL0
+#define bfin_read_EBIU_AMCBCTL1         bfin_read_EBIU_AMBCTL1
+#define bfin_write_EBIU_AMCBCTL1        bfin_write_EBIU_AMBCTL1
+#define bfin_read_PINT0_IRQ             bfin_read_PINT0_REQUEST
+#define bfin_write_PINT0_IRQ            bfin_write_PINT0_REQUEST
+#define bfin_read_PINT1_IRQ             bfin_read_PINT1_REQUEST
+#define bfin_write_PINT1_IRQ            bfin_write_PINT1_REQUEST
+#define bfin_read_PINT2_IRQ             bfin_read_PINT2_REQUEST
+#define bfin_write_PINT2_IRQ            bfin_write_PINT2_REQUEST
+#define bfin_read_PINT3_IRQ             bfin_read_PINT3_REQUEST
+#define bfin_write_PINT3_IRQ            bfin_write_PINT3_REQUEST
+
+#endif /* _CDEF_BF54X_H */
+
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
new file mode 100644
index 000000000000..ac968fca5cc5
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/defBF542.h
@@ -0,0 +1,1206 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/defBF542.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF542_H
+#define _DEF_BF542_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
+
+/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include "defBF54x_base.h"
+
+/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
+
+/* ATAPI Registers */
+
+#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
+#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
+#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
+#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
+#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
+#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
+#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
+#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
+#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
+#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
+#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
+#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
+#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
+#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
+#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
+#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
+#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
+#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
+#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
+#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
+#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
+#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
+#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
+#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
+#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
+
+/* SDH Registers */
+
+#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
+#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
+#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
+#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
+#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
+#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
+#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
+#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
+#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
+#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
+#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
+#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
+#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
+#define                       SDH_STATUS  0xffc03934   /* SDH Status */
+#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
+#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
+#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
+#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
+#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
+#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
+#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
+#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
+#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
+#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
+#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
+#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
+#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
+#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
+#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
+#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
+#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
+
+/* USB Control Registers */
+
+#define                        USB_FADDR  0xffc03c00   /* Function address register */
+#define                        USB_POWER  0xffc03c04   /* Power management register */
+#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
+#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
+#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
+#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
+#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
+#define                        USB_FRAME  0xffc03c20   /* USB frame number */
+#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
+#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
+#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
+#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
+#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
+#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
+#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
+#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
+#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
+#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
+#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
+#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
+#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
+#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
+#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
+#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
+#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
+#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
+#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
+#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
+#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
+#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
+#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
+#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
+#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
+#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
+#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
+#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+
+/* USB Endpoint 1 Control Registers */
+
+#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
+#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
+#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
+#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
+#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
+#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
+#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+
+/* USB Endpoint 2 Control Registers */
+
+#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
+#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
+#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
+#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
+#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
+#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
+#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+
+/* USB Endpoint 3 Control Registers */
+
+#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
+#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
+#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
+#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
+#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
+#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
+#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+
+/* USB Endpoint 4 Control Registers */
+
+#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
+#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
+#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
+#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
+#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
+#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
+#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+
+/* USB Endpoint 5 Control Registers */
+
+#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
+#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
+#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
+#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
+#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
+#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
+#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+
+/* USB Endpoint 6 Control Registers */
+
+#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
+#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
+#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
+#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
+#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
+#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
+#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+
+/* USB Endpoint 7 Control Registers */
+
+#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
+#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
+#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
+#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
+#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
+#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
+#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
+#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
+#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
+#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
+#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
+#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
+#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
+#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
+#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Keypad Registers */
+
+#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
+#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
+#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
+#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
+#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
+#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
+
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for KPAD_CTL */
+
+#define                   KPAD_EN  0x1        /* Keypad Enable */
+#define                  nKPAD_EN  0x0       
+#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
+#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
+#define                KPAD_COLEN  0xe000     /* Column Enable Width */
+
+/* Bit masks for KPAD_PRESCALE */
+
+#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
+
+/* Bit masks for KPAD_MSEL */
+
+#define                DBON_SCALE  0xff       /* Debounce Scale Value */
+#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
+
+/* Bit masks for KPAD_ROWCOL */
+
+#define                  KPAD_ROW  0xff       /* Rows Pressed */
+#define                  KPAD_COL  0xff00     /* Columns Pressed */
+
+/* Bit masks for KPAD_STAT */
+
+#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
+#define                 nKPAD_IRQ  0x0       
+#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
+#define              KPAD_PRESSED  0x8        /* Key press current status */
+#define             nKPAD_PRESSED  0x0       
+
+/* Bit masks for KPAD_SOFTEVAL */
+
+#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
+#define          nKPAD_SOFTEVAL_E  0x0       
+
+/* Bit masks for SDH_COMMAND */
+
+#define                   CMD_IDX  0x3f       /* Command Index */
+#define                   CMD_RSP  0x40       /* Response */
+#define                  nCMD_RSP  0x0       
+#define                 CMD_L_RSP  0x80       /* Long Response */
+#define                nCMD_L_RSP  0x0       
+#define                 CMD_INT_E  0x100      /* Command Interrupt */
+#define                nCMD_INT_E  0x0       
+#define                CMD_PEND_E  0x200      /* Command Pending */
+#define               nCMD_PEND_E  0x0       
+#define                     CMD_E  0x400      /* Command Enable */
+#define                    nCMD_E  0x0       
+
+/* Bit masks for SDH_PWR_CTL */
+
+#define                    PWR_ON  0x3        /* Power On */
+#if 0
+#define                       TBD  0x3c       /* TBD */
+#endif
+#define                 SD_CMD_OD  0x40       /* Open Drain Output */
+#define                nSD_CMD_OD  0x0       
+#define                   ROD_CTL  0x80       /* Rod Control */
+#define                  nROD_CTL  0x0       
+
+/* Bit masks for SDH_CLK_CTL */
+
+#define                    CLKDIV  0xff       /* MC_CLK Divisor */
+#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
+#define                    nCLK_E  0x0       
+#define                  PWR_SV_E  0x200      /* Power Save Enable */
+#define                 nPWR_SV_E  0x0       
+#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
+#define            nCLKDIV_BYPASS  0x0       
+#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
+#define                 nWIDE_BUS  0x0       
+
+/* Bit masks for SDH_RESP_CMD */
+
+#define                  RESP_CMD  0x3f       /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+
+#define                     DTX_E  0x1        /* Data Transfer Enable */
+#define                    nDTX_E  0x0       
+#define                   DTX_DIR  0x2        /* Data Transfer Direction */
+#define                  nDTX_DIR  0x0       
+#define                  DTX_MODE  0x4        /* Data Transfer Mode */
+#define                 nDTX_MODE  0x0       
+#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
+#define                nDTX_DMA_E  0x0       
+#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+
+#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
+#define             nCMD_CRC_FAIL  0x0       
+#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
+#define             nDAT_CRC_FAIL  0x0       
+#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
+#define              nCMD_TIMEOUT  0x0       
+#define               DAT_TIMEOUT  0x8        /* Data Time Out */
+#define              nDAT_TIMEOUT  0x0       
+#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
+#define              nTX_UNDERRUN  0x0       
+#define                RX_OVERRUN  0x20       /* Receive Overrun */
+#define               nRX_OVERRUN  0x0       
+#define              CMD_RESP_END  0x40       /* CMD Response End */
+#define             nCMD_RESP_END  0x0       
+#define                  CMD_SENT  0x80       /* CMD Sent */
+#define                 nCMD_SENT  0x0       
+#define                   DAT_END  0x100      /* Data End */
+#define                  nDAT_END  0x0       
+#define             START_BIT_ERR  0x200      /* Start Bit Error */
+#define            nSTART_BIT_ERR  0x0       
+#define               DAT_BLK_END  0x400      /* Data Block End */
+#define              nDAT_BLK_END  0x0       
+#define                   CMD_ACT  0x800      /* CMD Active */
+#define                  nCMD_ACT  0x0       
+#define                    TX_ACT  0x1000     /* Transmit Active */
+#define                   nTX_ACT  0x0       
+#define                    RX_ACT  0x2000     /* Receive Active */
+#define                   nRX_ACT  0x0       
+#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
+#define             nTX_FIFO_STAT  0x0       
+#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
+#define             nRX_FIFO_STAT  0x0       
+#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
+#define             nTX_FIFO_FULL  0x0       
+#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
+#define             nRX_FIFO_FULL  0x0       
+#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
+#define             nTX_FIFO_ZERO  0x0       
+#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
+#define              nRX_DAT_ZERO  0x0       
+#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
+#define               nTX_DAT_RDY  0x0       
+#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
+#define              nRX_FIFO_RDY  0x0       
+
+/* Bit masks for SDH_STATUS_CLR */
+
+#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
+#define        nCMD_CRC_FAIL_STAT  0x0       
+#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
+#define        nDAT_CRC_FAIL_STAT  0x0       
+#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
+#define         nCMD_TIMEOUT_STAT  0x0       
+#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
+#define         nDAT_TIMEOUT_STAT  0x0       
+#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
+#define         nTX_UNDERRUN_STAT  0x0       
+#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
+#define          nRX_OVERRUN_STAT  0x0       
+#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
+#define        nCMD_RESP_END_STAT  0x0       
+#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
+#define            nCMD_SENT_STAT  0x0       
+#define              DAT_END_STAT  0x100      /* Data End Status */
+#define             nDAT_END_STAT  0x0       
+#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
+#define       nSTART_BIT_ERR_STAT  0x0       
+#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
+#define         nDAT_BLK_END_STAT  0x0       
+
+/* Bit masks for SDH_MASK0 */
+
+#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
+#define        nCMD_CRC_FAIL_MASK  0x0       
+#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
+#define        nDAT_CRC_FAIL_MASK  0x0       
+#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
+#define         nCMD_TIMEOUT_MASK  0x0       
+#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
+#define         nDAT_TIMEOUT_MASK  0x0       
+#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
+#define         nTX_UNDERRUN_MASK  0x0       
+#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
+#define          nRX_OVERRUN_MASK  0x0       
+#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
+#define        nCMD_RESP_END_MASK  0x0       
+#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
+#define            nCMD_SENT_MASK  0x0       
+#define              DAT_END_MASK  0x100      /* Data End Mask */
+#define             nDAT_END_MASK  0x0       
+#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
+#define       nSTART_BIT_ERR_MASK  0x0       
+#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
+#define         nDAT_BLK_END_MASK  0x0       
+#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
+#define             nCMD_ACT_MASK  0x0       
+#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
+#define              nTX_ACT_MASK  0x0       
+#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
+#define              nRX_ACT_MASK  0x0       
+#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
+#define        nTX_FIFO_STAT_MASK  0x0       
+#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
+#define        nRX_FIFO_STAT_MASK  0x0       
+#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
+#define        nTX_FIFO_FULL_MASK  0x0       
+#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
+#define        nRX_FIFO_FULL_MASK  0x0       
+#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
+#define        nTX_FIFO_ZERO_MASK  0x0       
+#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
+#define         nRX_DAT_ZERO_MASK  0x0       
+#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
+#define          nTX_DAT_RDY_MASK  0x0       
+#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
+#define         nRX_FIFO_RDY_MASK  0x0       
+
+/* Bit masks for SDH_FIFO_CNT */
+
+#define                FIFO_COUNT  0x7fff     /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+
+#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
+#define             nSDIO_INT_DET  0x0       
+#define               SD_CARD_DET  0x10       /* SD Card Detect */
+#define              nSD_CARD_DET  0x0       
+
+/* Bit masks for SDH_E_MASK */
+
+#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
+#define                 nSDIO_MSK  0x0       
+#define                   SCD_MSK  0x40       /* Mask Card Detect */
+#define                  nSCD_MSK  0x0       
+
+/* Bit masks for SDH_CFG */
+
+#define                   CLKS_EN  0x1        /* Clocks Enable */
+#define                  nCLKS_EN  0x0       
+#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
+#define                     nSD4E  0x0       
+#define                       MWE  0x8        /* Moving Window Enable */
+#define                      nMWE  0x0       
+#define                    SD_RST  0x10       /* SDMMC Reset */
+#define                   nSD_RST  0x0       
+#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
+#define                nPUP_SDDAT  0x0       
+#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
+#define               nPUP_SDDAT3  0x0       
+#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
+#define                nPD_SDDAT3  0x0       
+
+/* Bit masks for SDH_RD_WAIT_EN */
+
+#define                       RWR  0x1        /* Read Wait Request */
+#define                      nRWR  0x0       
+
+/* Bit masks for ATAPI_CONTROL */
+
+#define                 PIO_START  0x1        /* Start PIO/Reg Op */
+#define                nPIO_START  0x0       
+#define               MULTI_START  0x2        /* Start Multi-DMA Op */
+#define              nMULTI_START  0x0       
+#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
+#define              nULTRA_START  0x0       
+#define                  XFER_DIR  0x8        /* Transfer Direction */
+#define                 nXFER_DIR  0x0       
+#define                  IORDY_EN  0x10       /* IORDY Enable */
+#define                 nIORDY_EN  0x0       
+#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
+#define               nFIFO_FLUSH  0x0       
+#define                  SOFT_RST  0x40       /* Soft Reset */
+#define                 nSOFT_RST  0x0       
+#define                   DEV_RST  0x80       /* Device Reset */
+#define                  nDEV_RST  0x0       
+#define                TFRCNT_RST  0x100      /* Trans Count Reset */
+#define               nTFRCNT_RST  0x0       
+#define               END_ON_TERM  0x200      /* End/Terminate Select */
+#define              nEND_ON_TERM  0x0       
+#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
+#define              nPIO_USE_DMA  0x0       
+#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+
+#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
+#define              nPIO_XFER_ON  0x0       
+#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
+#define            nMULTI_XFER_ON  0x0       
+#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
+#define            nULTRA_XFER_ON  0x0       
+#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+
+#define                  DEV_ADDR  0x1f       /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+
+#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
+#define       nATAPI_DEV_INT_MASK  0x0       
+#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
+#define            nPIO_DONE_MASK  0x0       
+#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
+#define          nMULTI_DONE_MASK  0x0       
+#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
+#define         nUDMAIN_DONE_MASK  0x0       
+#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
+#define        nUDMAOUT_DONE_MASK  0x0       
+#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
+#define      nHOST_TERM_XFER_MASK  0x0       
+#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
+#define          nMULTI_TERM_MASK  0x0       
+#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define         nUDMAIN_TERM_MASK  0x0       
+#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
+#define        nUDMAOUT_TERM_MASK  0x0       
+
+/* Bit masks for ATAPI_INT_STATUS */
+
+#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
+#define            nATAPI_DEV_INT  0x0       
+#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
+#define             nPIO_DONE_INT  0x0       
+#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
+#define           nMULTI_DONE_INT  0x0       
+#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
+#define          nUDMAIN_DONE_INT  0x0       
+#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
+#define         nUDMAOUT_DONE_INT  0x0       
+#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
+#define       nHOST_TERM_XFER_INT  0x0       
+#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
+#define           nMULTI_TERM_INT  0x0       
+#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define          nUDMAIN_TERM_INT  0x0       
+#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
+#define         nUDMAOUT_TERM_INT  0x0       
+
+/* Bit masks for ATAPI_LINE_STATUS */
+
+#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
+#define               nATAPI_INTR  0x0       
+#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
+#define               nATAPI_DASP  0x0       
+#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
+#define               nATAPI_CS0N  0x0       
+#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
+#define               nATAPI_CS1N  0x0       
+#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
+#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
+#define             nATAPI_DMAREQ  0x0       
+#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
+#define            nATAPI_DMAACKN  0x0       
+#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
+#define              nATAPI_DIOWN  0x0       
+#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
+#define              nATAPI_DIORN  0x0       
+#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
+#define              nATAPI_IORDY  0x0       
+
+/* Bit masks for ATAPI_SM_STATE */
+
+#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
+#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
+#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
+#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+
+#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
+#define          nATAPI_HOST_TERM  0x0       
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+
+#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
+#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+
+#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
+#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
+#define                    T4_REG  0xf000     /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+
+#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+
+#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
+#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+
+#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
+#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+
+#define                        TH  0xff       /* Selects DIOW data hold */
+#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+
+#define                      TACK  0xff       /* Selects setup and hold times for TACK */
+#define                      TENV  0xff00     /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+
+#define                      TDVS  0xff       /* Selects data valid setup time */
+#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+
+#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define                      TMLI  0xff00     /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+
+#define                      TZAH  0xff       /* Selects minimum delay required for output */
+#define               READY_PAUSE  0xff00     /* Selects ready to pause */
+
+/* Bit masks for USB_FADDR */
+
+#define          FUNCTION_ADDRESS  0x7f       /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
+#define          nENABLE_SUSPENDM  0x0       
+#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
+#define             nSUSPEND_MODE  0x0       
+#define               RESUME_MODE  0x4        /* DMA Mode */
+#define              nRESUME_MODE  0x0       
+#define                     RESET  0x8        /* Reset indicator */
+#define                    nRESET  0x0       
+#define                   HS_MODE  0x10       /* High Speed mode indicator */
+#define                  nHS_MODE  0x0       
+#define                 HS_ENABLE  0x20       /* high Speed Enable */
+#define                nHS_ENABLE  0x0       
+#define                 SOFT_CONN  0x40       /* Soft connect */
+#define                nSOFT_CONN  0x0       
+#define                ISO_UPDATE  0x80       /* Isochronous update */
+#define               nISO_UPDATE  0x0       
+
+/* Bit masks for USB_INTRTX */
+
+#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
+#define                   nEP0_TX  0x0       
+#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
+#define                   nEP1_TX  0x0       
+#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
+#define                   nEP2_TX  0x0       
+#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
+#define                   nEP3_TX  0x0       
+#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
+#define                   nEP4_TX  0x0       
+#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
+#define                   nEP5_TX  0x0       
+#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
+#define                   nEP6_TX  0x0       
+#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
+#define                   nEP7_TX  0x0       
+
+/* Bit masks for USB_INTRRX */
+
+#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
+#define                   nEP1_RX  0x0       
+#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
+#define                   nEP2_RX  0x0       
+#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
+#define                   nEP3_RX  0x0       
+#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
+#define                   nEP4_RX  0x0       
+#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
+#define                   nEP5_RX  0x0       
+#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
+#define                   nEP6_RX  0x0       
+#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
+#define                   nEP7_RX  0x0       
+
+/* Bit masks for USB_INTRTXE */
+
+#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
+#define                 nEP0_TX_E  0x0       
+#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
+#define                 nEP1_TX_E  0x0       
+#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
+#define                 nEP2_TX_E  0x0       
+#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
+#define                 nEP3_TX_E  0x0       
+#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
+#define                 nEP4_TX_E  0x0       
+#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
+#define                 nEP5_TX_E  0x0       
+#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
+#define                 nEP6_TX_E  0x0       
+#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
+#define                 nEP7_TX_E  0x0       
+
+/* Bit masks for USB_INTRRXE */
+
+#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
+#define                 nEP1_RX_E  0x0       
+#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
+#define                 nEP2_RX_E  0x0       
+#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
+#define                 nEP3_RX_E  0x0       
+#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
+#define                 nEP4_RX_E  0x0       
+#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
+#define                 nEP5_RX_E  0x0       
+#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
+#define                 nEP6_RX_E  0x0       
+#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
+#define                 nEP7_RX_E  0x0       
+
+/* Bit masks for USB_INTRUSB */
+
+#define                 SUSPEND_B  0x1        /* Suspend indicator */
+#define                nSUSPEND_B  0x0       
+#define                  RESUME_B  0x2        /* Resume indicator */
+#define                 nRESUME_B  0x0       
+#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
+#define         nRESET_OR_BABLE_B  0x0       
+#define                     SOF_B  0x8        /* Start of frame */
+#define                    nSOF_B  0x0       
+#define                    CONN_B  0x10       /* Connection indicator */
+#define                   nCONN_B  0x0       
+#define                  DISCON_B  0x20       /* Disconnect indicator */
+#define                 nDISCON_B  0x0       
+#define             SESSION_REQ_B  0x40       /* Session Request */
+#define            nSESSION_REQ_B  0x0       
+#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
+#define             nVBUS_ERROR_B  0x0       
+
+/* Bit masks for USB_INTRUSBE */
+
+#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
+#define               nSUSPEND_BE  0x0       
+#define                 RESUME_BE  0x2        /* Resume indicator int enable */
+#define                nRESUME_BE  0x0       
+#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
+#define        nRESET_OR_BABLE_BE  0x0       
+#define                    SOF_BE  0x8        /* Start of frame int enable */
+#define                   nSOF_BE  0x0       
+#define                   CONN_BE  0x10       /* Connection indicator int enable */
+#define                  nCONN_BE  0x0       
+#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
+#define                nDISCON_BE  0x0       
+#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
+#define           nSESSION_REQ_BE  0x0       
+#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
+#define            nVBUS_ERROR_BE  0x0       
+
+/* Bit masks for USB_FRAME */
+
+#define              FRAME_NUMBER  0x7ff      /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define                GLOBAL_ENA  0x1        /* enables USB module */
+#define               nGLOBAL_ENA  0x0       
+#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
+#define               nEP1_TX_ENA  0x0       
+#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
+#define               nEP2_TX_ENA  0x0       
+#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
+#define               nEP3_TX_ENA  0x0       
+#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
+#define               nEP4_TX_ENA  0x0       
+#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
+#define               nEP5_TX_ENA  0x0       
+#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
+#define               nEP6_TX_ENA  0x0       
+#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
+#define               nEP7_TX_ENA  0x0       
+#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
+#define               nEP1_RX_ENA  0x0       
+#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
+#define               nEP2_RX_ENA  0x0       
+#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
+#define               nEP3_RX_ENA  0x0       
+#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
+#define               nEP4_RX_ENA  0x0       
+#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
+#define               nEP5_RX_ENA  0x0       
+#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
+#define               nEP6_RX_ENA  0x0       
+#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
+#define               nEP7_RX_ENA  0x0       
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define                   SESSION  0x1        /* session indicator */
+#define                  nSESSION  0x0       
+#define                  HOST_REQ  0x2        /* Host negotiation request */
+#define                 nHOST_REQ  0x0       
+#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
+#define                nHOST_MODE  0x0       
+#define                     VBUS0  0x8        /* Vbus level indicator[0] */
+#define                    nVBUS0  0x0       
+#define                     VBUS1  0x10       /* Vbus level indicator[1] */
+#define                    nVBUS1  0x0       
+#define                     LSDEV  0x20       /* Low-speed indicator */
+#define                    nLSDEV  0x0       
+#define                     FSDEV  0x40       /* Full or High-speed indicator */
+#define                    nFSDEV  0x0       
+#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
+#define                 nB_DEVICE  0x0       
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
+#define            nDRIVE_VBUS_ON  0x0       
+#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
+#define           nDRIVE_VBUS_OFF  0x0       
+#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
+#define          nCHRG_VBUS_START  0x0       
+#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
+#define            nCHRG_VBUS_END  0x0       
+#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
+#define       nDISCHRG_VBUS_START  0x0       
+#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
+#define         nDISCHRG_VBUS_END  0x0       
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
+#define        nDRIVE_VBUS_ON_ENA  0x0       
+#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
+#define       nDRIVE_VBUS_OFF_ENA  0x0       
+#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
+#define      nCHRG_VBUS_START_ENA  0x0       
+#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
+#define        nCHRG_VBUS_END_ENA  0x0       
+#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
+#define   nDISCHRG_VBUS_START_ENA  0x0       
+#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
+#define     nDISCHRG_VBUS_END_ENA  0x0       
+
+/* Bit masks for USB_CSR0 */
+
+#define                  RXPKTRDY  0x1        /* data packet receive indicator */
+#define                 nRXPKTRDY  0x0       
+#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
+#define                 nTXPKTRDY  0x0       
+#define                STALL_SENT  0x4        /* STALL handshake sent */
+#define               nSTALL_SENT  0x0       
+#define                   DATAEND  0x8        /* Data end indicator */
+#define                  nDATAEND  0x0       
+#define                  SETUPEND  0x10       /* Setup end */
+#define                 nSETUPEND  0x0       
+#define                 SENDSTALL  0x20       /* Send STALL handshake */
+#define                nSENDSTALL  0x0       
+#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
+#define        nSERVICED_RXPKTRDY  0x0       
+#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
+#define        nSERVICED_SETUPEND  0x0       
+#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
+#define                nFLUSHFIFO  0x0       
+#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
+#define         nSTALL_RECEIVED_H  0x0       
+#define                SETUPPKT_H  0x8        /* send Setup token host mode */
+#define               nSETUPPKT_H  0x0       
+#define                   ERROR_H  0x10       /* timeout error indicator host mode */
+#define                  nERROR_H  0x0       
+#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
+#define                 nREQPKT_H  0x0       
+#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
+#define              nSTATUSPKT_H  0x0       
+#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
+#define            nNAK_TIMEOUT_H  0x0       
+
+/* Bit masks for USB_COUNT0 */
+
+#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
+#define               nTXPKTRDY_T  0x0       
+#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
+#define         nFIFO_NOT_EMPTY_T  0x0       
+#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
+#define               nUNDERRUN_T  0x0       
+#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
+#define              nFLUSHFIFO_T  0x0       
+#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
+#define             nSTALL_SEND_T  0x0       
+#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
+#define             nSTALL_SENT_T  0x0       
+#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
+#define       nCLEAR_DATATOGGLE_T  0x0       
+#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
+#define               nINCOMPTX_T  0x0       
+#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
+#define             nDMAREQMODE_T  0x0       
+#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
+#define       nFORCE_DATATOGGLE_T  0x0       
+#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
+#define             nDMAREQ_ENA_T  0x0       
+#define                     ISO_T  0x4000     /* enable Isochronous transfers */
+#define                    nISO_T  0x0       
+#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
+#define                nAUTOSET_T  0x0       
+#define                  ERROR_TH  0x4        /* error condition host mode */
+#define                 nERROR_TH  0x0       
+#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
+#define        nSTALL_RECEIVED_TH  0x0       
+#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
+#define           nNAK_TIMEOUT_TH  0x0       
+
+/* Bit masks for USB_TXCOUNT */
+
+#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
+#define               nRXPKTRDY_R  0x0       
+#define               FIFO_FULL_R  0x2        /* FIFO not empty */
+#define              nFIFO_FULL_R  0x0       
+#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
+#define                nOVERRUN_R  0x0       
+#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
+#define              nDATAERROR_R  0x0       
+#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
+#define              nFLUSHFIFO_R  0x0       
+#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
+#define             nSTALL_SEND_R  0x0       
+#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
+#define             nSTALL_SENT_R  0x0       
+#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
+#define       nCLEAR_DATATOGGLE_R  0x0       
+#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
+#define               nINCOMPRX_R  0x0       
+#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
+#define             nDMAREQMODE_R  0x0       
+#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
+#define                nDISNYET_R  0x0       
+#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
+#define             nDMAREQ_ENA_R  0x0       
+#define                     ISO_R  0x4000     /* enable Isochronous transfers */
+#define                    nISO_R  0x0       
+#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
+#define              nAUTOCLEAR_R  0x0       
+#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
+#define                 nERROR_RH  0x0       
+#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
+#define                nREQPKT_RH  0x0       
+#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
+#define        nSTALL_RECEIVED_RH  0x0       
+#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
+#define              nINCOMPRX_RH  0x0       
+#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
+#define            nDMAREQMODE_RH  0x0       
+#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
+#define               nAUTOREQ_RH  0x0       
+
+/* Bit masks for USB_RXCOUNT */
+
+#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define            TARGET_EP_NO_T  0xf        /* EP number */
+#define                PROTOCOL_T  0xc        /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define            TARGET_EP_NO_R  0xf        /* EP number */
+#define                PROTOCOL_R  0xc        /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
+#define                 nDMA0_INT  0x0       
+#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
+#define                 nDMA1_INT  0x0       
+#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
+#define                 nDMA2_INT  0x0       
+#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
+#define                 nDMA3_INT  0x0       
+#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
+#define                 nDMA4_INT  0x0       
+#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
+#define                 nDMA5_INT  0x0       
+#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
+#define                 nDMA6_INT  0x0       
+#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
+#define                 nDMA7_INT  0x0       
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define                   DMA_ENA  0x1        /* DMA enable */
+#define                  nDMA_ENA  0x0       
+#define                 DIRECTION  0x2        /* direction of DMA transfer */
+#define                nDIRECTION  0x0       
+#define                      MODE  0x4        /* DMA Bus error */
+#define                     nMODE  0x0       
+#define                   INT_ENA  0x8        /* Interrupt enable */
+#define                  nINT_ENA  0x0       
+#define                     EPNUM  0xf0       /* EP number */
+#define                  BUSERROR  0x100      /* DMA Bus error */
+#define                 nBUSERROR  0x0       
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+
+/* ******************************************* */
+/*     MULTI BIT MACRO ENUMERATIONS            */
+/* ******************************************* */
+
+
+#endif /* _DEF_BF542_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
new file mode 100644
index 000000000000..8fc77ea12aa9
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -0,0 +1,766 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/defBF544.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF544_H
+#define _DEF_BF544_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
+
+/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include "defBF54x_base.h"
+
+/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
+
+/* Timer Registers */
+
+#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
+#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
+#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
+#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
+#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
+#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
+#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
+#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
+#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
+#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
+#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
+#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
+
+/* Timer Group of 3 Registers */
+
+#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
+#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
+#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
+
+/* EPPI0 Registers */
+
+#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
+#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
+#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
+#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
+#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
+#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
+#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
+#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
+#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
+#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
+#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
+#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
+#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
+#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
+#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
+#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
+#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
+#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
+#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
+#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
+#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
+#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
+#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
+#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
+#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
+#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
+#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
+#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
+#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
+#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
+#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
+#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
+#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+
+/* CAN Controller 1 Clock/Interrupt/Counter Registers */
+
+#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
+#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
+#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
+#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
+#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
+#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
+#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
+#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
+#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
+#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
+#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
+#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
+#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
+#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
+#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
+#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
+#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
+#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
+#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
+#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
+#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
+#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
+#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
+#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
+#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
+#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
+#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
+#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
+#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
+#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
+#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
+#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
+#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
+#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
+#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
+#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
+#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
+#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
+#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
+#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
+#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
+#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
+#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
+#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
+#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
+#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
+#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
+
+/* HOST Port Registers */
+
+#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
+#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
+#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
+#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
+#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
+#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
+#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
+#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
+#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
+#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
+#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
+#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
+#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
+#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
+#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
+#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
+#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
+
+/* Handshake MDMA 0 Registers */
+
+#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
+#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
+#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
+#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
+#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
+
+/* Handshake MDMA 1 Registers */
+
+#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
+#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
+#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
+#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
+#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
+
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for PIXC_CTL */
+
+#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
+#define                  nPIXC_EN  0x0       
+#define                  OVR_A_EN  0x2        /* Overlay A Enable */
+#define                 nOVR_A_EN  0x0       
+#define                  OVR_B_EN  0x4        /* Overlay B Enable */
+#define                 nOVR_B_EN  0x0       
+#define                  IMG_FORM  0x8        /* Image Data Format */
+#define                 nIMG_FORM  0x0       
+#define                  OVR_FORM  0x10       /* Overlay Data Format */
+#define                 nOVR_FORM  0x0       
+#define                  OUT_FORM  0x20       /* Output Data Format */
+#define                 nOUT_FORM  0x0       
+#define                   UDS_MOD  0x40       /* Resampling Mode */
+#define                  nUDS_MOD  0x0       
+#define                     TC_EN  0x80       /* Transparent Color Enable */
+#define                    nTC_EN  0x0       
+#define                  IMG_STAT  0x300      /* Image FIFO Status */
+#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
+#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
+
+/* Bit masks for PIXC_AHSTART */
+
+#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_AHEND */
+
+#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_AVSTART */
+
+#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_AVEND */
+
+#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_ATRANSP */
+
+#define                  A_TRANSP  0xf        /* Transparency Value */
+
+/* Bit masks for PIXC_BHSTART */
+
+#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_BHEND */
+
+#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_BVSTART */
+
+#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_BVEND */
+
+#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_BTRANSP */
+
+#define                  B_TRANSP  0xf        /* Transparency Value */
+
+/* Bit masks for PIXC_INTRSTAT */
+
+#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
+#define               nOVR_INT_EN  0x0       
+#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
+#define               nFRM_INT_EN  0x0       
+#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
+#define             nOVR_INT_STAT  0x0       
+#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
+#define             nFRM_INT_STAT  0x0       
+
+/* Bit masks for PIXC_RYCON */
+
+#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
+#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
+#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
+#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
+#define                 nRY_MULT4  0x0       
+
+/* Bit masks for PIXC_GUCON */
+
+#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
+#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
+#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
+#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
+#define                 nGU_MULT4  0x0       
+
+/* Bit masks for PIXC_BVCON */
+
+#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
+#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
+#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
+#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
+#define                 nBV_MULT4  0x0       
+
+/* Bit masks for PIXC_CCBIAS */
+
+#define                       A14  0x3ff      /* A14 in the Bias Vector */
+#define                       A24  0xffc00    /* A24 in the Bias Vector */
+#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
+
+/* Bit masks for PIXC_TC */
+
+#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
+#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
+#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
+
+/* Bit masks for HOST_CONTROL */
+
+#define                   HOST_EN  0x1        /* Host Enable */
+#define                  nHOST_EN  0x0       
+#define                  HOST_END  0x2        /* Host Endianess */
+#define                 nHOST_END  0x0       
+#define                 DATA_SIZE  0x4        /* Data Size */
+#define                nDATA_SIZE  0x0       
+#define                  HOST_RST  0x8        /* Host Reset */
+#define                 nHOST_RST  0x0       
+#define                  HRDY_OVR  0x20       /* Host Ready Override */
+#define                 nHRDY_OVR  0x0       
+#define                  INT_MODE  0x40       /* Interrupt Mode */
+#define                 nINT_MODE  0x0       
+#define                     BT_EN  0x80       /* Bus Timeout Enable */
+#define                    nBT_EN  0x0       
+#define                       EHW  0x100      /* Enable Host Write */
+#define                      nEHW  0x0       
+#define                       EHR  0x200      /* Enable Host Read */
+#define                      nEHR  0x0       
+#define                       BDR  0x400      /* Burst DMA Requests */
+#define                      nBDR  0x0       
+
+/* Bit masks for HOST_STATUS */
+
+#define                     READY  0x1        /* DMA Ready */
+#define                    nREADY  0x0       
+#define                  FIFOFULL  0x2        /* FIFO Full */
+#define                 nFIFOFULL  0x0       
+#define                 FIFOEMPTY  0x4        /* FIFO Empty */
+#define                nFIFOEMPTY  0x0       
+#define                  COMPLETE  0x8        /* DMA Complete */
+#define                 nCOMPLETE  0x0       
+#define                      HSHK  0x10       /* Host Handshake */
+#define                     nHSHK  0x0       
+#define                   TIMEOUT  0x20       /* Host Timeout */
+#define                  nTIMEOUT  0x0       
+#define                      HIRQ  0x40       /* Host Interrupt Request */
+#define                     nHIRQ  0x0       
+#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
+#define               nALLOW_CNFG  0x0       
+#define                   DMA_DIR  0x100      /* DMA Direction */
+#define                  nDMA_DIR  0x0       
+#define                       BTE  0x200      /* Bus Timeout Enabled */
+#define                      nBTE  0x0       
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
+
+/* Bit masks for TIMER_ENABLE1 */
+
+#define                    TIMEN8  0x1        /* Timer 8 Enable */
+#define                   nTIMEN8  0x0       
+#define                    TIMEN9  0x2        /* Timer 9 Enable */
+#define                   nTIMEN9  0x0       
+#define                   TIMEN10  0x4        /* Timer 10 Enable */
+#define                  nTIMEN10  0x0       
+
+/* Bit masks for TIMER_DISABLE1 */
+
+#define                   TIMDIS8  0x1        /* Timer 8 Disable */
+#define                  nTIMDIS8  0x0       
+#define                   TIMDIS9  0x2        /* Timer 9 Disable */
+#define                  nTIMDIS9  0x0       
+#define                  TIMDIS10  0x4        /* Timer 10 Disable */
+#define                 nTIMDIS10  0x0       
+
+/* Bit masks for TIMER_STATUS1 */
+
+#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
+#define                   nTIMIL8  0x0       
+#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
+#define                   nTIMIL9  0x0       
+#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
+#define                  nTIMIL10  0x0       
+#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
+#define                nTOVF_ERR8  0x0       
+#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
+#define                nTOVF_ERR9  0x0       
+#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
+#define               nTOVF_ERR10  0x0       
+#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
+#define                    nTRUN8  0x0       
+#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
+#define                    nTRUN9  0x0       
+#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
+#define                   nTRUN10  0x0       
+
+/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
+
+/* Bit masks for HMDMAx_CONTROL */
+
+#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
+#define                  nHMDMAEN  0x0       
+#define                       REP  0x2        /* Handshake MDMA Request Polarity */
+#define                      nREP  0x0       
+#define                       UTE  0x8        /* Urgency Threshold Enable */
+#define                      nUTE  0x0       
+#define                       OIE  0x10       /* Overflow Interrupt Enable */
+#define                      nOIE  0x0       
+#define                      BDIE  0x20       /* Block Done Interrupt Enable */
+#define                     nBDIE  0x0       
+#define                      MBDI  0x40       /* Mask Block Done Interrupt */
+#define                     nMBDI  0x0       
+#define                       DRQ  0x300      /* Handshake MDMA Request Type */
+#define                       RBC  0x1000     /* Force Reload of BCOUNT */
+#define                      nRBC  0x0       
+#define                        PS  0x2000     /* Pin Status */
+#define                       nPS  0x0       
+#define                        OI  0x4000     /* Overflow Interrupt Generated */
+#define                       nOI  0x0       
+#define                       BDI  0x8000     /* Block Done Interrupt Generated */
+#define                      nBDI  0x0       
+
+/* ******************************************* */
+/*     MULTI BIT MACRO ENUMERATIONS            */
+/* ******************************************* */
+
+#endif /* _DEF_BF544_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
new file mode 100644
index 000000000000..d9e3062a9117
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -0,0 +1,1966 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/defBF548.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF548_H
+#define _DEF_BF548_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
+
+/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include "defBF54x_base.h"
+
+/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
+
+/* Timer Registers */
+
+#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
+#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
+#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
+#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
+#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
+#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
+#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
+#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
+#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
+#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
+#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
+#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
+
+/* Timer Group of 3 Registers */
+
+#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
+#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
+#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
+
+/* SPORT0 Registers */
+
+#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
+#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
+#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
+#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
+#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
+#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
+#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
+#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
+#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
+#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
+#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
+#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
+#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
+#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
+#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
+#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
+#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
+#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
+#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
+#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
+#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
+#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
+
+/* EPPI0 Registers */
+
+#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
+#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
+#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
+#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
+#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
+#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
+#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
+#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
+#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
+#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
+
+/* UART2 Registers */
+
+#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
+#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
+#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
+#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
+#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
+#define                        UART2_LSR  0xffc02114   /* Line Status Register */
+#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
+#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
+#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
+#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
+#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
+#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
+#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
+#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
+#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
+#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
+#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
+#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
+#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
+#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
+#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
+#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
+#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
+#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
+#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
+#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
+
+/* SPI2  Registers */
+
+#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
+#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
+#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
+#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
+#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
+#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
+#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
+#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
+#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
+#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
+#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
+#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
+#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
+#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
+#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+
+/* CAN Controller 1 Clock/Interrupt/Counter Registers */
+
+#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
+#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
+#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
+#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
+#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
+#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
+#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
+#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
+#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
+#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
+#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
+#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
+#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
+#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
+#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
+#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
+#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
+#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
+#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
+#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
+#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
+#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
+#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
+#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
+#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
+#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
+#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
+#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
+#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
+#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
+#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
+#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
+#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
+#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
+#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
+#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
+#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
+#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
+#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
+#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
+#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
+#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
+#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
+#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
+#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
+#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
+#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
+
+/* ATAPI Registers */
+
+#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
+#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
+#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
+#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
+#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
+#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
+#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
+#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
+#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
+#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
+#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
+#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
+#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
+#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
+#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
+#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
+#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
+#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
+#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
+#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
+#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
+#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
+#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
+#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
+#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
+
+/* SDH Registers */
+
+#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
+#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
+#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
+#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
+#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
+#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
+#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
+#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
+#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
+#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
+#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
+#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
+#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
+#define                       SDH_STATUS  0xffc03934   /* SDH Status */
+#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
+#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
+#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
+#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
+#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
+#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
+#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
+#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
+#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
+#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
+#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
+#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
+#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
+#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
+#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
+#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
+#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
+
+/* HOST Port Registers */
+
+#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
+#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
+#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
+
+/* USB Control Registers */
+
+#define                        USB_FADDR  0xffc03c00   /* Function address register */
+#define                        USB_POWER  0xffc03c04   /* Power management register */
+#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
+#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
+#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
+#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
+#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
+#define                        USB_FRAME  0xffc03c20   /* USB frame number */
+#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
+#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
+#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
+#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
+#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
+#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
+#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
+#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
+#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
+#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
+#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
+#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
+#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
+#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
+#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
+#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
+#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
+#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
+#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
+#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
+#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
+#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
+#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
+#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
+#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
+#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
+#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
+#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+
+/* USB Endpoint 1 Control Registers */
+
+#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
+#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
+#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
+#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
+#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
+#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
+#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+
+/* USB Endpoint 2 Control Registers */
+
+#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
+#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
+#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
+#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
+#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
+#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
+#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+
+/* USB Endpoint 3 Control Registers */
+
+#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
+#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
+#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
+#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
+#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
+#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
+#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+
+/* USB Endpoint 4 Control Registers */
+
+#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
+#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
+#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
+#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
+#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
+#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
+#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+
+/* USB Endpoint 5 Control Registers */
+
+#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
+#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
+#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
+#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
+#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
+#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
+#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+
+/* USB Endpoint 6 Control Registers */
+
+#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
+#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
+#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
+#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
+#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
+#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
+#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+
+/* USB Endpoint 7 Control Registers */
+
+#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
+#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
+#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
+#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
+#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
+#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
+#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
+#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
+#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
+#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
+#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
+#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
+#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
+#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
+#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Keypad Registers */
+
+#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
+#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
+#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
+#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
+#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
+#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
+#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
+#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
+#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
+#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
+#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
+#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
+#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
+#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
+#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
+#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
+#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
+#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
+#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
+#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
+
+/* Handshake MDMA 0 Registers */
+
+#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
+#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
+#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
+#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
+#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
+
+/* Handshake MDMA 1 Registers */
+
+#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
+#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
+#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
+#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
+#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
+
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for PIXC_CTL */
+
+#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
+#define                  nPIXC_EN  0x0       
+#define                  OVR_A_EN  0x2        /* Overlay A Enable */
+#define                 nOVR_A_EN  0x0       
+#define                  OVR_B_EN  0x4        /* Overlay B Enable */
+#define                 nOVR_B_EN  0x0       
+#define                  IMG_FORM  0x8        /* Image Data Format */
+#define                 nIMG_FORM  0x0       
+#define                  OVR_FORM  0x10       /* Overlay Data Format */
+#define                 nOVR_FORM  0x0       
+#define                  OUT_FORM  0x20       /* Output Data Format */
+#define                 nOUT_FORM  0x0       
+#define                   UDS_MOD  0x40       /* Resampling Mode */
+#define                  nUDS_MOD  0x0       
+#define                     TC_EN  0x80       /* Transparent Color Enable */
+#define                    nTC_EN  0x0       
+#define                  IMG_STAT  0x300      /* Image FIFO Status */
+#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
+#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
+
+/* Bit masks for PIXC_AHSTART */
+
+#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_AHEND */
+
+#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_AVSTART */
+
+#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_AVEND */
+
+#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_ATRANSP */
+
+#define                  A_TRANSP  0xf        /* Transparency Value */
+
+/* Bit masks for PIXC_BHSTART */
+
+#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_BHEND */
+
+#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_BVSTART */
+
+#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_BVEND */
+
+#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_BTRANSP */
+
+#define                  B_TRANSP  0xf        /* Transparency Value */
+
+/* Bit masks for PIXC_INTRSTAT */
+
+#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
+#define               nOVR_INT_EN  0x0       
+#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
+#define               nFRM_INT_EN  0x0       
+#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
+#define             nOVR_INT_STAT  0x0       
+#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
+#define             nFRM_INT_STAT  0x0       
+
+/* Bit masks for PIXC_RYCON */
+
+#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
+#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
+#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
+#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
+#define                 nRY_MULT4  0x0       
+
+/* Bit masks for PIXC_GUCON */
+
+#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
+#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
+#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
+#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
+#define                 nGU_MULT4  0x0       
+
+/* Bit masks for PIXC_BVCON */
+
+#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
+#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
+#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
+#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
+#define                 nBV_MULT4  0x0       
+
+/* Bit masks for PIXC_CCBIAS */
+
+#define                       A14  0x3ff      /* A14 in the Bias Vector */
+#define                       A24  0xffc00    /* A24 in the Bias Vector */
+#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
+
+/* Bit masks for PIXC_TC */
+
+#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
+#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
+#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
+
+/* Bit masks for HOST_CONTROL */
+
+#define                   HOST_EN  0x1        /* Host Enable */
+#define                  nHOST_EN  0x0       
+#define                  HOST_END  0x2        /* Host Endianess */
+#define                 nHOST_END  0x0       
+#define                 DATA_SIZE  0x4        /* Data Size */
+#define                nDATA_SIZE  0x0       
+#define                  HOST_RST  0x8        /* Host Reset */
+#define                 nHOST_RST  0x0       
+#define                  HRDY_OVR  0x20       /* Host Ready Override */
+#define                 nHRDY_OVR  0x0       
+#define                  INT_MODE  0x40       /* Interrupt Mode */
+#define                 nINT_MODE  0x0       
+#define                     BT_EN  0x80       /* Bus Timeout Enable */
+#define                    nBT_EN  0x0       
+#define                       EHW  0x100      /* Enable Host Write */
+#define                      nEHW  0x0       
+#define                       EHR  0x200      /* Enable Host Read */
+#define                      nEHR  0x0       
+#define                       BDR  0x400      /* Burst DMA Requests */
+#define                      nBDR  0x0       
+
+/* Bit masks for HOST_STATUS */
+
+#define                     READY  0x1        /* DMA Ready */
+#define                    nREADY  0x0       
+#define                  FIFOFULL  0x2        /* FIFO Full */
+#define                 nFIFOFULL  0x0       
+#define                 FIFOEMPTY  0x4        /* FIFO Empty */
+#define                nFIFOEMPTY  0x0       
+#define                  COMPLETE  0x8        /* DMA Complete */
+#define                 nCOMPLETE  0x0       
+#define                      HSHK  0x10       /* Host Handshake */
+#define                     nHSHK  0x0       
+#define                   TIMEOUT  0x20       /* Host Timeout */
+#define                  nTIMEOUT  0x0       
+#define                      HIRQ  0x40       /* Host Interrupt Request */
+#define                     nHIRQ  0x0       
+#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
+#define               nALLOW_CNFG  0x0       
+#define                   DMA_DIR  0x100      /* DMA Direction */
+#define                  nDMA_DIR  0x0       
+#define                       BTE  0x200      /* Bus Timeout Enabled */
+#define                      nBTE  0x0       
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
+
+/* Bit masks for KPAD_CTL */
+
+#define                   KPAD_EN  0x1        /* Keypad Enable */
+#define                  nKPAD_EN  0x0       
+#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
+#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
+#define                KPAD_COLEN  0xe000     /* Column Enable Width */
+
+/* Bit masks for KPAD_PRESCALE */
+
+#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
+
+/* Bit masks for KPAD_MSEL */
+
+#define                DBON_SCALE  0xff       /* Debounce Scale Value */
+#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
+
+/* Bit masks for KPAD_ROWCOL */
+
+#define                  KPAD_ROW  0xff       /* Rows Pressed */
+#define                  KPAD_COL  0xff00     /* Columns Pressed */
+
+/* Bit masks for KPAD_STAT */
+
+#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
+#define                 nKPAD_IRQ  0x0       
+#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
+#define              KPAD_PRESSED  0x8        /* Key press current status */
+#define             nKPAD_PRESSED  0x0       
+
+/* Bit masks for KPAD_SOFTEVAL */
+
+#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
+#define          nKPAD_SOFTEVAL_E  0x0       
+
+/* Bit masks for SDH_COMMAND */
+
+#define                   CMD_IDX  0x3f       /* Command Index */
+#define                   CMD_RSP  0x40       /* Response */
+#define                  nCMD_RSP  0x0       
+#define                 CMD_L_RSP  0x80       /* Long Response */
+#define                nCMD_L_RSP  0x0       
+#define                 CMD_INT_E  0x100      /* Command Interrupt */
+#define                nCMD_INT_E  0x0       
+#define                CMD_PEND_E  0x200      /* Command Pending */
+#define               nCMD_PEND_E  0x0       
+#define                     CMD_E  0x400      /* Command Enable */
+#define                    nCMD_E  0x0       
+
+/* Bit masks for SDH_PWR_CTL */
+
+#define                    PWR_ON  0x3        /* Power On */
+#if 0
+#define                       TBD  0x3c       /* TBD */
+#endif
+#define                 SD_CMD_OD  0x40       /* Open Drain Output */
+#define                nSD_CMD_OD  0x0       
+#define                   ROD_CTL  0x80       /* Rod Control */
+#define                  nROD_CTL  0x0       
+
+/* Bit masks for SDH_CLK_CTL */
+
+#define                    CLKDIV  0xff       /* MC_CLK Divisor */
+#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
+#define                    nCLK_E  0x0       
+#define                  PWR_SV_E  0x200      /* Power Save Enable */
+#define                 nPWR_SV_E  0x0       
+#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
+#define            nCLKDIV_BYPASS  0x0       
+#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
+#define                 nWIDE_BUS  0x0       
+
+/* Bit masks for SDH_RESP_CMD */
+
+#define                  RESP_CMD  0x3f       /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+
+#define                     DTX_E  0x1        /* Data Transfer Enable */
+#define                    nDTX_E  0x0       
+#define                   DTX_DIR  0x2        /* Data Transfer Direction */
+#define                  nDTX_DIR  0x0       
+#define                  DTX_MODE  0x4        /* Data Transfer Mode */
+#define                 nDTX_MODE  0x0       
+#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
+#define                nDTX_DMA_E  0x0       
+#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+
+#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
+#define             nCMD_CRC_FAIL  0x0       
+#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
+#define             nDAT_CRC_FAIL  0x0       
+#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
+#define              nCMD_TIMEOUT  0x0       
+#define               DAT_TIMEOUT  0x8        /* Data Time Out */
+#define              nDAT_TIMEOUT  0x0       
+#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
+#define              nTX_UNDERRUN  0x0       
+#define                RX_OVERRUN  0x20       /* Receive Overrun */
+#define               nRX_OVERRUN  0x0       
+#define              CMD_RESP_END  0x40       /* CMD Response End */
+#define             nCMD_RESP_END  0x0       
+#define                  CMD_SENT  0x80       /* CMD Sent */
+#define                 nCMD_SENT  0x0       
+#define                   DAT_END  0x100      /* Data End */
+#define                  nDAT_END  0x0       
+#define             START_BIT_ERR  0x200      /* Start Bit Error */
+#define            nSTART_BIT_ERR  0x0       
+#define               DAT_BLK_END  0x400      /* Data Block End */
+#define              nDAT_BLK_END  0x0       
+#define                   CMD_ACT  0x800      /* CMD Active */
+#define                  nCMD_ACT  0x0       
+#define                    TX_ACT  0x1000     /* Transmit Active */
+#define                   nTX_ACT  0x0       
+#define                    RX_ACT  0x2000     /* Receive Active */
+#define                   nRX_ACT  0x0       
+#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
+#define             nTX_FIFO_STAT  0x0       
+#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
+#define             nRX_FIFO_STAT  0x0       
+#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
+#define             nTX_FIFO_FULL  0x0       
+#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
+#define             nRX_FIFO_FULL  0x0       
+#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
+#define             nTX_FIFO_ZERO  0x0       
+#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
+#define              nRX_DAT_ZERO  0x0       
+#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
+#define               nTX_DAT_RDY  0x0       
+#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
+#define              nRX_FIFO_RDY  0x0       
+
+/* Bit masks for SDH_STATUS_CLR */
+
+#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
+#define        nCMD_CRC_FAIL_STAT  0x0       
+#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
+#define        nDAT_CRC_FAIL_STAT  0x0       
+#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
+#define         nCMD_TIMEOUT_STAT  0x0       
+#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
+#define         nDAT_TIMEOUT_STAT  0x0       
+#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
+#define         nTX_UNDERRUN_STAT  0x0       
+#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
+#define          nRX_OVERRUN_STAT  0x0       
+#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
+#define        nCMD_RESP_END_STAT  0x0       
+#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
+#define            nCMD_SENT_STAT  0x0       
+#define              DAT_END_STAT  0x100      /* Data End Status */
+#define             nDAT_END_STAT  0x0       
+#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
+#define       nSTART_BIT_ERR_STAT  0x0       
+#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
+#define         nDAT_BLK_END_STAT  0x0       
+
+/* Bit masks for SDH_MASK0 */
+
+#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
+#define        nCMD_CRC_FAIL_MASK  0x0       
+#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
+#define        nDAT_CRC_FAIL_MASK  0x0       
+#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
+#define         nCMD_TIMEOUT_MASK  0x0       
+#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
+#define         nDAT_TIMEOUT_MASK  0x0       
+#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
+#define         nTX_UNDERRUN_MASK  0x0       
+#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
+#define          nRX_OVERRUN_MASK  0x0       
+#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
+#define        nCMD_RESP_END_MASK  0x0       
+#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
+#define            nCMD_SENT_MASK  0x0       
+#define              DAT_END_MASK  0x100      /* Data End Mask */
+#define             nDAT_END_MASK  0x0       
+#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
+#define       nSTART_BIT_ERR_MASK  0x0       
+#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
+#define         nDAT_BLK_END_MASK  0x0       
+#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
+#define             nCMD_ACT_MASK  0x0       
+#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
+#define              nTX_ACT_MASK  0x0       
+#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
+#define              nRX_ACT_MASK  0x0       
+#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
+#define        nTX_FIFO_STAT_MASK  0x0       
+#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
+#define        nRX_FIFO_STAT_MASK  0x0       
+#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
+#define        nTX_FIFO_FULL_MASK  0x0       
+#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
+#define        nRX_FIFO_FULL_MASK  0x0       
+#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
+#define        nTX_FIFO_ZERO_MASK  0x0       
+#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
+#define         nRX_DAT_ZERO_MASK  0x0       
+#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
+#define          nTX_DAT_RDY_MASK  0x0       
+#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
+#define         nRX_FIFO_RDY_MASK  0x0       
+
+/* Bit masks for SDH_FIFO_CNT */
+
+#define                FIFO_COUNT  0x7fff     /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+
+#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
+#define             nSDIO_INT_DET  0x0       
+#define               SD_CARD_DET  0x10       /* SD Card Detect */
+#define              nSD_CARD_DET  0x0       
+
+/* Bit masks for SDH_E_MASK */
+
+#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
+#define                 nSDIO_MSK  0x0       
+#define                   SCD_MSK  0x40       /* Mask Card Detect */
+#define                  nSCD_MSK  0x0       
+
+/* Bit masks for SDH_CFG */
+
+#define                   CLKS_EN  0x1        /* Clocks Enable */
+#define                  nCLKS_EN  0x0       
+#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
+#define                     nSD4E  0x0       
+#define                       MWE  0x8        /* Moving Window Enable */
+#define                      nMWE  0x0       
+#define                    SD_RST  0x10       /* SDMMC Reset */
+#define                   nSD_RST  0x0       
+#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
+#define                nPUP_SDDAT  0x0       
+#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
+#define               nPUP_SDDAT3  0x0       
+#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
+#define                nPD_SDDAT3  0x0       
+
+/* Bit masks for SDH_RD_WAIT_EN */
+
+#define                       RWR  0x1        /* Read Wait Request */
+#define                      nRWR  0x0       
+
+/* Bit masks for ATAPI_CONTROL */
+
+#define                 PIO_START  0x1        /* Start PIO/Reg Op */
+#define                nPIO_START  0x0       
+#define               MULTI_START  0x2        /* Start Multi-DMA Op */
+#define              nMULTI_START  0x0       
+#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
+#define              nULTRA_START  0x0       
+#define                  XFER_DIR  0x8        /* Transfer Direction */
+#define                 nXFER_DIR  0x0       
+#define                  IORDY_EN  0x10       /* IORDY Enable */
+#define                 nIORDY_EN  0x0       
+#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
+#define               nFIFO_FLUSH  0x0       
+#define                  SOFT_RST  0x40       /* Soft Reset */
+#define                 nSOFT_RST  0x0       
+#define                   DEV_RST  0x80       /* Device Reset */
+#define                  nDEV_RST  0x0       
+#define                TFRCNT_RST  0x100      /* Trans Count Reset */
+#define               nTFRCNT_RST  0x0       
+#define               END_ON_TERM  0x200      /* End/Terminate Select */
+#define              nEND_ON_TERM  0x0       
+#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
+#define              nPIO_USE_DMA  0x0       
+#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+
+#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
+#define              nPIO_XFER_ON  0x0       
+#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
+#define            nMULTI_XFER_ON  0x0       
+#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
+#define            nULTRA_XFER_ON  0x0       
+#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+
+#define                  DEV_ADDR  0x1f       /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+
+#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
+#define       nATAPI_DEV_INT_MASK  0x0       
+#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
+#define            nPIO_DONE_MASK  0x0       
+#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
+#define          nMULTI_DONE_MASK  0x0       
+#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
+#define         nUDMAIN_DONE_MASK  0x0       
+#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
+#define        nUDMAOUT_DONE_MASK  0x0       
+#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
+#define      nHOST_TERM_XFER_MASK  0x0       
+#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
+#define          nMULTI_TERM_MASK  0x0       
+#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define         nUDMAIN_TERM_MASK  0x0       
+#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
+#define        nUDMAOUT_TERM_MASK  0x0       
+
+/* Bit masks for ATAPI_INT_STATUS */
+
+#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
+#define            nATAPI_DEV_INT  0x0       
+#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
+#define             nPIO_DONE_INT  0x0       
+#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
+#define           nMULTI_DONE_INT  0x0       
+#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
+#define          nUDMAIN_DONE_INT  0x0       
+#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
+#define         nUDMAOUT_DONE_INT  0x0       
+#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
+#define       nHOST_TERM_XFER_INT  0x0       
+#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
+#define           nMULTI_TERM_INT  0x0       
+#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define          nUDMAIN_TERM_INT  0x0       
+#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
+#define         nUDMAOUT_TERM_INT  0x0       
+
+/* Bit masks for ATAPI_LINE_STATUS */
+
+#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
+#define               nATAPI_INTR  0x0       
+#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
+#define               nATAPI_DASP  0x0       
+#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
+#define               nATAPI_CS0N  0x0       
+#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
+#define               nATAPI_CS1N  0x0       
+#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
+#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
+#define             nATAPI_DMAREQ  0x0       
+#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
+#define            nATAPI_DMAACKN  0x0       
+#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
+#define              nATAPI_DIOWN  0x0       
+#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
+#define              nATAPI_DIORN  0x0       
+#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
+#define              nATAPI_IORDY  0x0       
+
+/* Bit masks for ATAPI_SM_STATE */
+
+#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
+#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
+#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
+#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+
+#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
+#define          nATAPI_HOST_TERM  0x0       
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+
+#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
+#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+
+#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
+#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
+#define                    T4_REG  0xf000     /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+
+#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+
+#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
+#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+
+#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
+#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+
+#define                        TH  0xff       /* Selects DIOW data hold */
+#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+
+#define                      TACK  0xff       /* Selects setup and hold times for TACK */
+#define                      TENV  0xff00     /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+
+#define                      TDVS  0xff       /* Selects data valid setup time */
+#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+
+#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define                      TMLI  0xff00     /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+
+#define                      TZAH  0xff       /* Selects minimum delay required for output */
+#define               READY_PAUSE  0xff00     /* Selects ready to pause */
+
+/* Bit masks for TIMER_ENABLE1 */
+
+#define                    TIMEN8  0x1        /* Timer 8 Enable */
+#define                   nTIMEN8  0x0       
+#define                    TIMEN9  0x2        /* Timer 9 Enable */
+#define                   nTIMEN9  0x0       
+#define                   TIMEN10  0x4        /* Timer 10 Enable */
+#define                  nTIMEN10  0x0       
+
+/* Bit masks for TIMER_DISABLE1 */
+
+#define                   TIMDIS8  0x1        /* Timer 8 Disable */
+#define                  nTIMDIS8  0x0       
+#define                   TIMDIS9  0x2        /* Timer 9 Disable */
+#define                  nTIMDIS9  0x0       
+#define                  TIMDIS10  0x4        /* Timer 10 Disable */
+#define                 nTIMDIS10  0x0       
+
+/* Bit masks for TIMER_STATUS1 */
+
+#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
+#define                   nTIMIL8  0x0       
+#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
+#define                   nTIMIL9  0x0       
+#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
+#define                  nTIMIL10  0x0       
+#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
+#define                nTOVF_ERR8  0x0       
+#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
+#define                nTOVF_ERR9  0x0       
+#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
+#define               nTOVF_ERR10  0x0       
+#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
+#define                    nTRUN8  0x0       
+#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
+#define                    nTRUN9  0x0       
+#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
+#define                   nTRUN10  0x0       
+
+/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
+
+/* Bit masks for USB_FADDR */
+
+#define          FUNCTION_ADDRESS  0x7f       /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
+#define          nENABLE_SUSPENDM  0x0       
+#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
+#define             nSUSPEND_MODE  0x0       
+#define               RESUME_MODE  0x4        /* DMA Mode */
+#define              nRESUME_MODE  0x0       
+#define                     RESET  0x8        /* Reset indicator */
+#define                    nRESET  0x0       
+#define                   HS_MODE  0x10       /* High Speed mode indicator */
+#define                  nHS_MODE  0x0       
+#define                 HS_ENABLE  0x20       /* high Speed Enable */
+#define                nHS_ENABLE  0x0       
+#define                 SOFT_CONN  0x40       /* Soft connect */
+#define                nSOFT_CONN  0x0       
+#define                ISO_UPDATE  0x80       /* Isochronous update */
+#define               nISO_UPDATE  0x0       
+
+/* Bit masks for USB_INTRTX */
+
+#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
+#define                   nEP0_TX  0x0       
+#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
+#define                   nEP1_TX  0x0       
+#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
+#define                   nEP2_TX  0x0       
+#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
+#define                   nEP3_TX  0x0       
+#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
+#define                   nEP4_TX  0x0       
+#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
+#define                   nEP5_TX  0x0       
+#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
+#define                   nEP6_TX  0x0       
+#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
+#define                   nEP7_TX  0x0       
+
+/* Bit masks for USB_INTRRX */
+
+#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
+#define                   nEP1_RX  0x0       
+#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
+#define                   nEP2_RX  0x0       
+#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
+#define                   nEP3_RX  0x0       
+#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
+#define                   nEP4_RX  0x0       
+#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
+#define                   nEP5_RX  0x0       
+#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
+#define                   nEP6_RX  0x0       
+#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
+#define                   nEP7_RX  0x0       
+
+/* Bit masks for USB_INTRTXE */
+
+#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
+#define                 nEP0_TX_E  0x0       
+#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
+#define                 nEP1_TX_E  0x0       
+#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
+#define                 nEP2_TX_E  0x0       
+#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
+#define                 nEP3_TX_E  0x0       
+#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
+#define                 nEP4_TX_E  0x0       
+#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
+#define                 nEP5_TX_E  0x0       
+#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
+#define                 nEP6_TX_E  0x0       
+#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
+#define                 nEP7_TX_E  0x0       
+
+/* Bit masks for USB_INTRRXE */
+
+#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
+#define                 nEP1_RX_E  0x0       
+#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
+#define                 nEP2_RX_E  0x0       
+#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
+#define                 nEP3_RX_E  0x0       
+#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
+#define                 nEP4_RX_E  0x0       
+#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
+#define                 nEP5_RX_E  0x0       
+#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
+#define                 nEP6_RX_E  0x0       
+#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
+#define                 nEP7_RX_E  0x0       
+
+/* Bit masks for USB_INTRUSB */
+
+#define                 SUSPEND_B  0x1        /* Suspend indicator */
+#define                nSUSPEND_B  0x0       
+#define                  RESUME_B  0x2        /* Resume indicator */
+#define                 nRESUME_B  0x0       
+#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
+#define         nRESET_OR_BABLE_B  0x0       
+#define                     SOF_B  0x8        /* Start of frame */
+#define                    nSOF_B  0x0       
+#define                    CONN_B  0x10       /* Connection indicator */
+#define                   nCONN_B  0x0       
+#define                  DISCON_B  0x20       /* Disconnect indicator */
+#define                 nDISCON_B  0x0       
+#define             SESSION_REQ_B  0x40       /* Session Request */
+#define            nSESSION_REQ_B  0x0       
+#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
+#define             nVBUS_ERROR_B  0x0       
+
+/* Bit masks for USB_INTRUSBE */
+
+#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
+#define               nSUSPEND_BE  0x0       
+#define                 RESUME_BE  0x2        /* Resume indicator int enable */
+#define                nRESUME_BE  0x0       
+#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
+#define        nRESET_OR_BABLE_BE  0x0       
+#define                    SOF_BE  0x8        /* Start of frame int enable */
+#define                   nSOF_BE  0x0       
+#define                   CONN_BE  0x10       /* Connection indicator int enable */
+#define                  nCONN_BE  0x0       
+#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
+#define                nDISCON_BE  0x0       
+#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
+#define           nSESSION_REQ_BE  0x0       
+#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
+#define            nVBUS_ERROR_BE  0x0       
+
+/* Bit masks for USB_FRAME */
+
+#define              FRAME_NUMBER  0x7ff      /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define                GLOBAL_ENA  0x1        /* enables USB module */
+#define               nGLOBAL_ENA  0x0       
+#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
+#define               nEP1_TX_ENA  0x0       
+#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
+#define               nEP2_TX_ENA  0x0       
+#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
+#define               nEP3_TX_ENA  0x0       
+#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
+#define               nEP4_TX_ENA  0x0       
+#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
+#define               nEP5_TX_ENA  0x0       
+#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
+#define               nEP6_TX_ENA  0x0       
+#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
+#define               nEP7_TX_ENA  0x0       
+#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
+#define               nEP1_RX_ENA  0x0       
+#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
+#define               nEP2_RX_ENA  0x0       
+#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
+#define               nEP3_RX_ENA  0x0       
+#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
+#define               nEP4_RX_ENA  0x0       
+#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
+#define               nEP5_RX_ENA  0x0       
+#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
+#define               nEP6_RX_ENA  0x0       
+#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
+#define               nEP7_RX_ENA  0x0       
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define                   SESSION  0x1        /* session indicator */
+#define                  nSESSION  0x0       
+#define                  HOST_REQ  0x2        /* Host negotiation request */
+#define                 nHOST_REQ  0x0       
+#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
+#define                nHOST_MODE  0x0       
+#define                     VBUS0  0x8        /* Vbus level indicator[0] */
+#define                    nVBUS0  0x0       
+#define                     VBUS1  0x10       /* Vbus level indicator[1] */
+#define                    nVBUS1  0x0       
+#define                     LSDEV  0x20       /* Low-speed indicator */
+#define                    nLSDEV  0x0       
+#define                     FSDEV  0x40       /* Full or High-speed indicator */
+#define                    nFSDEV  0x0       
+#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
+#define                 nB_DEVICE  0x0       
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
+#define            nDRIVE_VBUS_ON  0x0       
+#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
+#define           nDRIVE_VBUS_OFF  0x0       
+#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
+#define          nCHRG_VBUS_START  0x0       
+#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
+#define            nCHRG_VBUS_END  0x0       
+#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
+#define       nDISCHRG_VBUS_START  0x0       
+#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
+#define         nDISCHRG_VBUS_END  0x0       
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
+#define        nDRIVE_VBUS_ON_ENA  0x0       
+#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
+#define       nDRIVE_VBUS_OFF_ENA  0x0       
+#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
+#define      nCHRG_VBUS_START_ENA  0x0       
+#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
+#define        nCHRG_VBUS_END_ENA  0x0       
+#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
+#define   nDISCHRG_VBUS_START_ENA  0x0       
+#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
+#define     nDISCHRG_VBUS_END_ENA  0x0       
+
+/* Bit masks for USB_CSR0 */
+
+#define                  RXPKTRDY  0x1        /* data packet receive indicator */
+#define                 nRXPKTRDY  0x0       
+#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
+#define                 nTXPKTRDY  0x0       
+#define                STALL_SENT  0x4        /* STALL handshake sent */
+#define               nSTALL_SENT  0x0       
+#define                   DATAEND  0x8        /* Data end indicator */
+#define                  nDATAEND  0x0       
+#define                  SETUPEND  0x10       /* Setup end */
+#define                 nSETUPEND  0x0       
+#define                 SENDSTALL  0x20       /* Send STALL handshake */
+#define                nSENDSTALL  0x0       
+#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
+#define        nSERVICED_RXPKTRDY  0x0       
+#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
+#define        nSERVICED_SETUPEND  0x0       
+#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
+#define                nFLUSHFIFO  0x0       
+#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
+#define         nSTALL_RECEIVED_H  0x0       
+#define                SETUPPKT_H  0x8        /* send Setup token host mode */
+#define               nSETUPPKT_H  0x0       
+#define                   ERROR_H  0x10       /* timeout error indicator host mode */
+#define                  nERROR_H  0x0       
+#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
+#define                 nREQPKT_H  0x0       
+#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
+#define              nSTATUSPKT_H  0x0       
+#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
+#define            nNAK_TIMEOUT_H  0x0       
+
+/* Bit masks for USB_COUNT0 */
+
+#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
+#define               nTXPKTRDY_T  0x0       
+#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
+#define         nFIFO_NOT_EMPTY_T  0x0       
+#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
+#define               nUNDERRUN_T  0x0       
+#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
+#define              nFLUSHFIFO_T  0x0       
+#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
+#define             nSTALL_SEND_T  0x0       
+#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
+#define             nSTALL_SENT_T  0x0       
+#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
+#define       nCLEAR_DATATOGGLE_T  0x0       
+#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
+#define               nINCOMPTX_T  0x0       
+#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
+#define             nDMAREQMODE_T  0x0       
+#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
+#define       nFORCE_DATATOGGLE_T  0x0       
+#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
+#define             nDMAREQ_ENA_T  0x0       
+#define                     ISO_T  0x4000     /* enable Isochronous transfers */
+#define                    nISO_T  0x0       
+#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
+#define                nAUTOSET_T  0x0       
+#define                  ERROR_TH  0x4        /* error condition host mode */
+#define                 nERROR_TH  0x0       
+#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
+#define        nSTALL_RECEIVED_TH  0x0       
+#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
+#define           nNAK_TIMEOUT_TH  0x0       
+
+/* Bit masks for USB_TXCOUNT */
+
+#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
+#define               nRXPKTRDY_R  0x0       
+#define               FIFO_FULL_R  0x2        /* FIFO not empty */
+#define              nFIFO_FULL_R  0x0       
+#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
+#define                nOVERRUN_R  0x0       
+#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
+#define              nDATAERROR_R  0x0       
+#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
+#define              nFLUSHFIFO_R  0x0       
+#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
+#define             nSTALL_SEND_R  0x0       
+#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
+#define             nSTALL_SENT_R  0x0       
+#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
+#define       nCLEAR_DATATOGGLE_R  0x0       
+#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
+#define               nINCOMPRX_R  0x0       
+#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
+#define             nDMAREQMODE_R  0x0       
+#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
+#define                nDISNYET_R  0x0       
+#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
+#define             nDMAREQ_ENA_R  0x0       
+#define                     ISO_R  0x4000     /* enable Isochronous transfers */
+#define                    nISO_R  0x0       
+#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
+#define              nAUTOCLEAR_R  0x0       
+#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
+#define                 nERROR_RH  0x0       
+#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
+#define                nREQPKT_RH  0x0       
+#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
+#define        nSTALL_RECEIVED_RH  0x0       
+#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
+#define              nINCOMPRX_RH  0x0       
+#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
+#define            nDMAREQMODE_RH  0x0       
+#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
+#define               nAUTOREQ_RH  0x0       
+
+/* Bit masks for USB_RXCOUNT */
+
+#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define            TARGET_EP_NO_T  0xf        /* EP number */
+#define                PROTOCOL_T  0xc        /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define            TARGET_EP_NO_R  0xf        /* EP number */
+#define                PROTOCOL_R  0xc        /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
+#define                 nDMA0_INT  0x0       
+#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
+#define                 nDMA1_INT  0x0       
+#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
+#define                 nDMA2_INT  0x0       
+#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
+#define                 nDMA3_INT  0x0       
+#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
+#define                 nDMA4_INT  0x0       
+#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
+#define                 nDMA5_INT  0x0       
+#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
+#define                 nDMA6_INT  0x0       
+#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
+#define                 nDMA7_INT  0x0       
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define                   DMA_ENA  0x1        /* DMA enable */
+#define                  nDMA_ENA  0x0       
+#define                 DIRECTION  0x2        /* direction of DMA transfer */
+#define                nDIRECTION  0x0       
+#define                      MODE  0x4        /* DMA Bus error */
+#define                     nMODE  0x0       
+#define                   INT_ENA  0x8        /* Interrupt enable */
+#define                  nINT_ENA  0x0       
+#define                     EPNUM  0xf0       /* EP number */
+#define                  BUSERROR  0x100      /* DMA Bus error */
+#define                 nBUSERROR  0x0       
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for HMDMAx_CONTROL */
+
+#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
+#define                  nHMDMAEN  0x0       
+#define                       REP  0x2        /* Handshake MDMA Request Polarity */
+#define                      nREP  0x0       
+#define                       UTE  0x8        /* Urgency Threshold Enable */
+#define                      nUTE  0x0       
+#define                       OIE  0x10       /* Overflow Interrupt Enable */
+#define                      nOIE  0x0       
+#define                      BDIE  0x20       /* Block Done Interrupt Enable */
+#define                     nBDIE  0x0       
+#define                      MBDI  0x40       /* Mask Block Done Interrupt */
+#define                     nMBDI  0x0       
+#define                       DRQ  0x300      /* Handshake MDMA Request Type */
+#define                       RBC  0x1000     /* Force Reload of BCOUNT */
+#define                      nRBC  0x0       
+#define                        PS  0x2000     /* Pin Status */
+#define                       nPS  0x0       
+#define                        OI  0x4000     /* Overflow Interrupt Generated */
+#define                       nOI  0x0       
+#define                       BDI  0x8000     /* Block Done Interrupt Generated */
+#define                      nBDI  0x0       
+
+/* ******************************************* */
+/*     MULTI BIT MACRO ENUMERATIONS            */
+/* ******************************************* */
+
+
+#endif /* _DEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
new file mode 100644
index 000000000000..b1cc1c073b41
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/defBF549.h
@@ -0,0 +1,3472 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/defBF549.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF549_H
+#define _DEF_BF549_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
+
+/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include "defBF54x_base.h"
+
+/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
+
+/* Timer Registers */
+
+#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
+#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
+#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
+#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
+#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
+#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
+#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
+#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
+#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
+#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
+#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
+#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
+
+/* Timer Group of 3 Registers */
+
+#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
+#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
+#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
+
+/* SPORT0 Registers */
+
+#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
+#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
+#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
+#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
+#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
+#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
+#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
+#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
+#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
+#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
+#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
+#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
+#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
+#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
+#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
+#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
+#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
+#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
+#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
+#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
+#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
+#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
+
+/* EPPI0 Registers */
+
+#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
+#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
+#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
+#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
+#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
+#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
+#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
+#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
+#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
+#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
+
+/* UART2 Registers */
+
+#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
+#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
+#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
+#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
+#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
+#define                        UART2_LSR  0xffc02114   /* Line Status Register */
+#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
+#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
+#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
+#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
+#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
+#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
+#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
+#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
+#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
+#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
+#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
+#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
+#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
+#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
+#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
+#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
+#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
+#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
+#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
+#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
+
+/* SPI2  Registers */
+
+#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
+#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
+#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
+#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
+#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
+#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
+#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
+
+/* MXVR Registers */
+
+#define                      MXVR_CONFIG  0xffc02700   /* MXVR Configuration Register */
+#define                     MXVR_STATE_0  0xffc02708   /* MXVR State Register 0 */
+#define                     MXVR_STATE_1  0xffc0270c   /* MXVR State Register 1 */
+#define                  MXVR_INT_STAT_0  0xffc02710   /* MXVR Interrupt Status Register 0 */
+#define                  MXVR_INT_STAT_1  0xffc02714   /* MXVR Interrupt Status Register 1 */
+#define                    MXVR_INT_EN_0  0xffc02718   /* MXVR Interrupt Enable Register 0 */
+#define                    MXVR_INT_EN_1  0xffc0271c   /* MXVR Interrupt Enable Register 1 */
+#define                    MXVR_POSITION  0xffc02720   /* MXVR Node Position Register */
+#define                MXVR_MAX_POSITION  0xffc02724   /* MXVR Maximum Node Position Register */
+#define                       MXVR_DELAY  0xffc02728   /* MXVR Node Frame Delay Register */
+#define                   MXVR_MAX_DELAY  0xffc0272c   /* MXVR Maximum Node Frame Delay Register */
+#define                       MXVR_LADDR  0xffc02730   /* MXVR Logical Address Register */
+#define                       MXVR_GADDR  0xffc02734   /* MXVR Group Address Register */
+#define                       MXVR_AADDR  0xffc02738   /* MXVR Alternate Address Register */
+
+/* MXVR Allocation Table Registers */
+
+#define                     MXVR_ALLOC_0  0xffc0273c   /* MXVR Allocation Table Register 0 */
+#define                     MXVR_ALLOC_1  0xffc02740   /* MXVR Allocation Table Register 1 */
+#define                     MXVR_ALLOC_2  0xffc02744   /* MXVR Allocation Table Register 2 */
+#define                     MXVR_ALLOC_3  0xffc02748   /* MXVR Allocation Table Register 3 */
+#define                     MXVR_ALLOC_4  0xffc0274c   /* MXVR Allocation Table Register 4 */
+#define                     MXVR_ALLOC_5  0xffc02750   /* MXVR Allocation Table Register 5 */
+#define                     MXVR_ALLOC_6  0xffc02754   /* MXVR Allocation Table Register 6 */
+#define                     MXVR_ALLOC_7  0xffc02758   /* MXVR Allocation Table Register 7 */
+#define                     MXVR_ALLOC_8  0xffc0275c   /* MXVR Allocation Table Register 8 */
+#define                     MXVR_ALLOC_9  0xffc02760   /* MXVR Allocation Table Register 9 */
+#define                    MXVR_ALLOC_10  0xffc02764   /* MXVR Allocation Table Register 10 */
+#define                    MXVR_ALLOC_11  0xffc02768   /* MXVR Allocation Table Register 11 */
+#define                    MXVR_ALLOC_12  0xffc0276c   /* MXVR Allocation Table Register 12 */
+#define                    MXVR_ALLOC_13  0xffc02770   /* MXVR Allocation Table Register 13 */
+#define                    MXVR_ALLOC_14  0xffc02774   /* MXVR Allocation Table Register 14 */
+
+/* MXVR Channel Assign Registers */
+
+#define                MXVR_SYNC_LCHAN_0  0xffc02778   /* MXVR Sync Data Logical Channel Assign Register 0 */
+#define                MXVR_SYNC_LCHAN_1  0xffc0277c   /* MXVR Sync Data Logical Channel Assign Register 1 */
+#define                MXVR_SYNC_LCHAN_2  0xffc02780   /* MXVR Sync Data Logical Channel Assign Register 2 */
+#define                MXVR_SYNC_LCHAN_3  0xffc02784   /* MXVR Sync Data Logical Channel Assign Register 3 */
+#define                MXVR_SYNC_LCHAN_4  0xffc02788   /* MXVR Sync Data Logical Channel Assign Register 4 */
+#define                MXVR_SYNC_LCHAN_5  0xffc0278c   /* MXVR Sync Data Logical Channel Assign Register 5 */
+#define                MXVR_SYNC_LCHAN_6  0xffc02790   /* MXVR Sync Data Logical Channel Assign Register 6 */
+#define                MXVR_SYNC_LCHAN_7  0xffc02794   /* MXVR Sync Data Logical Channel Assign Register 7 */
+
+/* MXVR DMA0 Registers */
+
+#define                 MXVR_DMA0_CONFIG  0xffc02798   /* MXVR Sync Data DMA0 Config Register */
+#define             MXVR_DMA0_START_ADDR  0xffc0279c   /* MXVR Sync Data DMA0 Start Address */
+#define                  MXVR_DMA0_COUNT  0xffc027a0   /* MXVR Sync Data DMA0 Loop Count Register */
+#define              MXVR_DMA0_CURR_ADDR  0xffc027a4   /* MXVR Sync Data DMA0 Current Address */
+#define             MXVR_DMA0_CURR_COUNT  0xffc027a8   /* MXVR Sync Data DMA0 Current Loop Count */
+
+/* MXVR DMA1 Registers */
+
+#define                 MXVR_DMA1_CONFIG  0xffc027ac   /* MXVR Sync Data DMA1 Config Register */
+#define             MXVR_DMA1_START_ADDR  0xffc027b0   /* MXVR Sync Data DMA1 Start Address */
+#define                  MXVR_DMA1_COUNT  0xffc027b4   /* MXVR Sync Data DMA1 Loop Count Register */
+#define              MXVR_DMA1_CURR_ADDR  0xffc027b8   /* MXVR Sync Data DMA1 Current Address */
+#define             MXVR_DMA1_CURR_COUNT  0xffc027bc   /* MXVR Sync Data DMA1 Current Loop Count */
+
+/* MXVR DMA2 Registers */
+
+#define                 MXVR_DMA2_CONFIG  0xffc027c0   /* MXVR Sync Data DMA2 Config Register */
+#define             MXVR_DMA2_START_ADDR  0xffc027c4   /* MXVR Sync Data DMA2 Start Address */
+#define                  MXVR_DMA2_COUNT  0xffc027c8   /* MXVR Sync Data DMA2 Loop Count Register */
+#define              MXVR_DMA2_CURR_ADDR  0xffc027cc   /* MXVR Sync Data DMA2 Current Address */
+#define             MXVR_DMA2_CURR_COUNT  0xffc027d0   /* MXVR Sync Data DMA2 Current Loop Count */
+
+/* MXVR DMA3 Registers */
+
+#define                 MXVR_DMA3_CONFIG  0xffc027d4   /* MXVR Sync Data DMA3 Config Register */
+#define             MXVR_DMA3_START_ADDR  0xffc027d8   /* MXVR Sync Data DMA3 Start Address */
+#define                  MXVR_DMA3_COUNT  0xffc027dc   /* MXVR Sync Data DMA3 Loop Count Register */
+#define              MXVR_DMA3_CURR_ADDR  0xffc027e0   /* MXVR Sync Data DMA3 Current Address */
+#define             MXVR_DMA3_CURR_COUNT  0xffc027e4   /* MXVR Sync Data DMA3 Current Loop Count */
+
+/* MXVR DMA4 Registers */
+
+#define                 MXVR_DMA4_CONFIG  0xffc027e8   /* MXVR Sync Data DMA4 Config Register */
+#define             MXVR_DMA4_START_ADDR  0xffc027ec   /* MXVR Sync Data DMA4 Start Address */
+#define                  MXVR_DMA4_COUNT  0xffc027f0   /* MXVR Sync Data DMA4 Loop Count Register */
+#define              MXVR_DMA4_CURR_ADDR  0xffc027f4   /* MXVR Sync Data DMA4 Current Address */
+#define             MXVR_DMA4_CURR_COUNT  0xffc027f8   /* MXVR Sync Data DMA4 Current Loop Count */
+
+/* MXVR DMA5 Registers */
+
+#define                 MXVR_DMA5_CONFIG  0xffc027fc   /* MXVR Sync Data DMA5 Config Register */
+#define             MXVR_DMA5_START_ADDR  0xffc02800   /* MXVR Sync Data DMA5 Start Address */
+#define                  MXVR_DMA5_COUNT  0xffc02804   /* MXVR Sync Data DMA5 Loop Count Register */
+#define              MXVR_DMA5_CURR_ADDR  0xffc02808   /* MXVR Sync Data DMA5 Current Address */
+#define             MXVR_DMA5_CURR_COUNT  0xffc0280c   /* MXVR Sync Data DMA5 Current Loop Count */
+
+/* MXVR DMA6 Registers */
+
+#define                 MXVR_DMA6_CONFIG  0xffc02810   /* MXVR Sync Data DMA6 Config Register */
+#define             MXVR_DMA6_START_ADDR  0xffc02814   /* MXVR Sync Data DMA6 Start Address */
+#define                  MXVR_DMA6_COUNT  0xffc02818   /* MXVR Sync Data DMA6 Loop Count Register */
+#define              MXVR_DMA6_CURR_ADDR  0xffc0281c   /* MXVR Sync Data DMA6 Current Address */
+#define             MXVR_DMA6_CURR_COUNT  0xffc02820   /* MXVR Sync Data DMA6 Current Loop Count */
+
+/* MXVR DMA7 Registers */
+
+#define                 MXVR_DMA7_CONFIG  0xffc02824   /* MXVR Sync Data DMA7 Config Register */
+#define             MXVR_DMA7_START_ADDR  0xffc02828   /* MXVR Sync Data DMA7 Start Address */
+#define                  MXVR_DMA7_COUNT  0xffc0282c   /* MXVR Sync Data DMA7 Loop Count Register */
+#define              MXVR_DMA7_CURR_ADDR  0xffc02830   /* MXVR Sync Data DMA7 Current Address */
+#define             MXVR_DMA7_CURR_COUNT  0xffc02834   /* MXVR Sync Data DMA7 Current Loop Count */
+
+/* MXVR Asynch Packet Registers */
+
+#define                      MXVR_AP_CTL  0xffc02838   /* MXVR Async Packet Control Register */
+#define             MXVR_APRB_START_ADDR  0xffc0283c   /* MXVR Async Packet RX Buffer Start Addr Register */
+#define              MXVR_APRB_CURR_ADDR  0xffc02840   /* MXVR Async Packet RX Buffer Current Addr Register */
+#define             MXVR_APTB_START_ADDR  0xffc02844   /* MXVR Async Packet TX Buffer Start Addr Register */
+#define              MXVR_APTB_CURR_ADDR  0xffc02848   /* MXVR Async Packet TX Buffer Current Addr Register */
+
+/* MXVR Control Message Registers */
+
+#define                      MXVR_CM_CTL  0xffc0284c   /* MXVR Control Message Control Register */
+#define             MXVR_CMRB_START_ADDR  0xffc02850   /* MXVR Control Message RX Buffer Start Addr Register */
+#define              MXVR_CMRB_CURR_ADDR  0xffc02854   /* MXVR Control Message RX Buffer Current Address */
+#define             MXVR_CMTB_START_ADDR  0xffc02858   /* MXVR Control Message TX Buffer Start Addr Register */
+#define              MXVR_CMTB_CURR_ADDR  0xffc0285c   /* MXVR Control Message TX Buffer Current Address */
+
+/* MXVR Remote Read Registers */
+
+#define             MXVR_RRDB_START_ADDR  0xffc02860   /* MXVR Remote Read Buffer Start Addr Register */
+#define              MXVR_RRDB_CURR_ADDR  0xffc02864   /* MXVR Remote Read Buffer Current Addr Register */
+
+/* MXVR Pattern Data Registers */
+
+#define                  MXVR_PAT_DATA_0  0xffc02868   /* MXVR Pattern Data Register 0 */
+#define                    MXVR_PAT_EN_0  0xffc0286c   /* MXVR Pattern Enable Register 0 */
+#define                  MXVR_PAT_DATA_1  0xffc02870   /* MXVR Pattern Data Register 1 */
+#define                    MXVR_PAT_EN_1  0xffc02874   /* MXVR Pattern Enable Register 1 */
+
+/* MXVR Frame Counter Registers */
+
+#define                 MXVR_FRAME_CNT_0  0xffc02878   /* MXVR Frame Counter 0 */
+#define                 MXVR_FRAME_CNT_1  0xffc0287c   /* MXVR Frame Counter 1 */
+
+/* MXVR Routing Table Registers */
+
+#define                   MXVR_ROUTING_0  0xffc02880   /* MXVR Routing Table Register 0 */
+#define                   MXVR_ROUTING_1  0xffc02884   /* MXVR Routing Table Register 1 */
+#define                   MXVR_ROUTING_2  0xffc02888   /* MXVR Routing Table Register 2 */
+#define                   MXVR_ROUTING_3  0xffc0288c   /* MXVR Routing Table Register 3 */
+#define                   MXVR_ROUTING_4  0xffc02890   /* MXVR Routing Table Register 4 */
+#define                   MXVR_ROUTING_5  0xffc02894   /* MXVR Routing Table Register 5 */
+#define                   MXVR_ROUTING_6  0xffc02898   /* MXVR Routing Table Register 6 */
+#define                   MXVR_ROUTING_7  0xffc0289c   /* MXVR Routing Table Register 7 */
+#define                   MXVR_ROUTING_8  0xffc028a0   /* MXVR Routing Table Register 8 */
+#define                   MXVR_ROUTING_9  0xffc028a4   /* MXVR Routing Table Register 9 */
+#define                  MXVR_ROUTING_10  0xffc028a8   /* MXVR Routing Table Register 10 */
+#define                  MXVR_ROUTING_11  0xffc028ac   /* MXVR Routing Table Register 11 */
+#define                  MXVR_ROUTING_12  0xffc028b0   /* MXVR Routing Table Register 12 */
+#define                  MXVR_ROUTING_13  0xffc028b4   /* MXVR Routing Table Register 13 */
+#define                  MXVR_ROUTING_14  0xffc028b8   /* MXVR Routing Table Register 14 */
+
+/* MXVR Counter-Clock-Control Registers */
+
+#define                   MXVR_BLOCK_CNT  0xffc028c0   /* MXVR Block Counter */
+#define                     MXVR_CLK_CTL  0xffc028d0   /* MXVR Clock Control Register */
+#define                  MXVR_CDRPLL_CTL  0xffc028d4   /* MXVR Clock/Data Recovery PLL Control Register */
+#define                   MXVR_FMPLL_CTL  0xffc028d8   /* MXVR Frequency Multiply PLL Control Register */
+#define                     MXVR_PIN_CTL  0xffc028dc   /* MXVR Pin Control Register */
+#define                    MXVR_SCLK_CNT  0xffc028e0   /* MXVR System Clock Counter Register */
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
+#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
+#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
+#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
+#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
+#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
+#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
+#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
+#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+
+/* CAN Controller 1 Clock/Interrupt/Counter Registers */
+
+#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
+#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
+#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
+#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
+#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
+#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
+#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
+#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
+#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
+#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
+#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
+#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
+#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
+#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
+#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
+#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
+#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
+#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
+#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
+#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
+#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
+#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
+#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
+#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
+#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
+#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
+#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
+#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
+#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
+#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
+#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
+#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
+#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
+#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
+#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
+#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
+#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
+#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
+#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
+#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
+#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
+#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
+#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
+#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
+#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
+#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
+#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
+
+/* ATAPI Registers */
+
+#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
+#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
+#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
+#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
+#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
+#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
+#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
+#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
+#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
+#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
+#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
+#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
+#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
+#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
+#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
+#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
+#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
+#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
+#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
+#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
+#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
+#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
+#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
+#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
+#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
+
+/* SDH Registers */
+
+#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
+#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
+#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
+#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
+#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
+#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
+#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
+#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
+#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
+#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
+#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
+#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
+#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
+#define                       SDH_STATUS  0xffc03934   /* SDH Status */
+#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
+#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
+#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
+#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
+#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
+#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
+#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
+#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
+#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
+#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
+#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
+#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
+#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
+#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
+#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
+#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
+#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
+
+/* HOST Port Registers */
+
+#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
+#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
+#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
+
+/* USB Control Registers */
+
+#define                        USB_FADDR  0xffc03c00   /* Function address register */
+#define                        USB_POWER  0xffc03c04   /* Power management register */
+#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
+#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
+#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
+#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
+#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
+#define                        USB_FRAME  0xffc03c20   /* USB frame number */
+#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
+#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
+#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
+#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
+#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
+#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
+#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
+#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
+#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
+#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
+#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
+#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
+#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
+#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
+#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
+#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
+#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
+#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
+#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
+#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
+#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
+#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
+#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
+#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
+#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
+#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
+#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
+#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+
+/* USB Endpoint 1 Control Registers */
+
+#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
+#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
+#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
+#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
+#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
+#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
+#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+
+/* USB Endpoint 2 Control Registers */
+
+#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
+#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
+#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
+#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
+#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
+#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
+#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+
+/* USB Endpoint 3 Control Registers */
+
+#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
+#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
+#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
+#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
+#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
+#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
+#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+
+/* USB Endpoint 4 Control Registers */
+
+#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
+#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
+#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
+#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
+#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
+#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
+#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+
+/* USB Endpoint 5 Control Registers */
+
+#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
+#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
+#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
+#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
+#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
+#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
+#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+
+/* USB Endpoint 6 Control Registers */
+
+#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
+#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
+#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
+#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
+#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
+#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
+#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+
+/* USB Endpoint 7 Control Registers */
+
+#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
+#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
+#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
+#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
+#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
+#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
+#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
+#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
+#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
+#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
+#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
+#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
+#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
+#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
+#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Keypad Registers */
+
+#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
+#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
+#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
+#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
+#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
+#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
+#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
+#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
+#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
+#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
+#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
+#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
+#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
+#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
+#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
+#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
+#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
+#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
+#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
+#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
+
+/* Handshake MDMA 0 Registers */
+
+#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
+#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
+#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
+#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
+#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
+
+/* Handshake MDMA 1 Registers */
+
+#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
+#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
+#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
+#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
+#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
+
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for PIXC_CTL */
+
+#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
+#define                  nPIXC_EN  0x0       
+#define                  OVR_A_EN  0x2        /* Overlay A Enable */
+#define                 nOVR_A_EN  0x0       
+#define                  OVR_B_EN  0x4        /* Overlay B Enable */
+#define                 nOVR_B_EN  0x0       
+#define                  IMG_FORM  0x8        /* Image Data Format */
+#define                 nIMG_FORM  0x0       
+#define                  OVR_FORM  0x10       /* Overlay Data Format */
+#define                 nOVR_FORM  0x0       
+#define                  OUT_FORM  0x20       /* Output Data Format */
+#define                 nOUT_FORM  0x0       
+#define                   UDS_MOD  0x40       /* Resampling Mode */
+#define                  nUDS_MOD  0x0       
+#define                     TC_EN  0x80       /* Transparent Color Enable */
+#define                    nTC_EN  0x0       
+#define                  IMG_STAT  0x300      /* Image FIFO Status */
+#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
+#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
+
+/* Bit masks for PIXC_AHSTART */
+
+#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_AHEND */
+
+#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_AVSTART */
+
+#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_AVEND */
+
+#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_ATRANSP */
+
+#define                  A_TRANSP  0xf        /* Transparency Value */
+
+/* Bit masks for PIXC_BHSTART */
+
+#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_BHEND */
+
+#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_BVSTART */
+
+#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_BVEND */
+
+#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_BTRANSP */
+
+#define                  B_TRANSP  0xf        /* Transparency Value */
+
+/* Bit masks for PIXC_INTRSTAT */
+
+#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
+#define               nOVR_INT_EN  0x0       
+#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
+#define               nFRM_INT_EN  0x0       
+#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
+#define             nOVR_INT_STAT  0x0       
+#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
+#define             nFRM_INT_STAT  0x0       
+
+/* Bit masks for PIXC_RYCON */
+
+#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
+#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
+#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
+#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
+#define                 nRY_MULT4  0x0       
+
+/* Bit masks for PIXC_GUCON */
+
+#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
+#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
+#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
+#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
+#define                 nGU_MULT4  0x0       
+
+/* Bit masks for PIXC_BVCON */
+
+#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
+#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
+#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
+#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
+#define                 nBV_MULT4  0x0       
+
+/* Bit masks for PIXC_CCBIAS */
+
+#define                       A14  0x3ff      /* A14 in the Bias Vector */
+#define                       A24  0xffc00    /* A24 in the Bias Vector */
+#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
+
+/* Bit masks for PIXC_TC */
+
+#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
+#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
+#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
+
+/* Bit masks for HOST_CONTROL */
+
+#define                   HOST_EN  0x1        /* Host Enable */
+#define                  nHOST_EN  0x0       
+#define                  HOST_END  0x2        /* Host Endianess */
+#define                 nHOST_END  0x0       
+#define                 DATA_SIZE  0x4        /* Data Size */
+#define                nDATA_SIZE  0x0       
+#define                  HOST_RST  0x8        /* Host Reset */
+#define                 nHOST_RST  0x0       
+#define                  HRDY_OVR  0x20       /* Host Ready Override */
+#define                 nHRDY_OVR  0x0       
+#define                  INT_MODE  0x40       /* Interrupt Mode */
+#define                 nINT_MODE  0x0       
+#define                     BT_EN  0x80       /* Bus Timeout Enable */
+#define                    nBT_EN  0x0       
+#define                       EHW  0x100      /* Enable Host Write */
+#define                      nEHW  0x0       
+#define                       EHR  0x200      /* Enable Host Read */
+#define                      nEHR  0x0       
+#define                       BDR  0x400      /* Burst DMA Requests */
+#define                      nBDR  0x0       
+
+/* Bit masks for HOST_STATUS */
+
+#define                     READY  0x1        /* DMA Ready */
+#define                    nREADY  0x0       
+#define                  FIFOFULL  0x2        /* FIFO Full */
+#define                 nFIFOFULL  0x0       
+#define                 FIFOEMPTY  0x4        /* FIFO Empty */
+#define                nFIFOEMPTY  0x0       
+#define                  COMPLETE  0x8        /* DMA Complete */
+#define                 nCOMPLETE  0x0       
+#define                      HSHK  0x10       /* Host Handshake */
+#define                     nHSHK  0x0       
+#define                   TIMEOUT  0x20       /* Host Timeout */
+#define                  nTIMEOUT  0x0       
+#define                      HIRQ  0x40       /* Host Interrupt Request */
+#define                     nHIRQ  0x0       
+#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
+#define               nALLOW_CNFG  0x0       
+#define                   DMA_DIR  0x100      /* DMA Direction */
+#define                  nDMA_DIR  0x0       
+#define                       BTE  0x200      /* Bus Timeout Enabled */
+#define                      nBTE  0x0       
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
+
+/* Bit masks for MXVR_CONFIG */
+
+#define                    MXVREN  0x1        /* MXVR Enable */
+#define                   nMXVREN  0x0       
+#define                      MMSM  0x2        /* MXVR Master/Slave Mode Select */
+#define                     nMMSM  0x0       
+#define                    ACTIVE  0x4        /* Active Mode */
+#define                   nACTIVE  0x0       
+#define                    SDELAY  0x8        /* Synchronous Data Delay */
+#define                   nSDELAY  0x0       
+#define                   NCMRXEN  0x10       /* Normal Control Message Receive Enable */
+#define                  nNCMRXEN  0x0       
+#define                   RWRRXEN  0x20       /* Remote Write Receive Enable */
+#define                  nRWRRXEN  0x0       
+#define                     MTXEN  0x40       /* MXVR Transmit Data Enable */
+#define                    nMTXEN  0x0       
+#define                    MTXONB  0x80       /* MXVR Phy Transmitter On */
+#define                   nMTXONB  0x0       
+#define                   EPARITY  0x100      /* Even Parity Select */
+#define                  nEPARITY  0x0       
+#define                       MSB  0x1e00     /* Master Synchronous Boundary */
+#define                    APRXEN  0x2000     /* Asynchronous Packet Receive Enable */
+#define                   nAPRXEN  0x0       
+#define                    WAKEUP  0x4000     /* Wake-Up */
+#define                   nWAKEUP  0x0       
+#define                     LMECH  0x8000     /* Lock Mechanism Select */
+#define                    nLMECH  0x0       
+
+/* Bit masks for MXVR_STATE_0 */
+
+#define                      NACT  0x1        /* Network Activity */
+#define                     nNACT  0x0       
+#define                    SBLOCK  0x2        /* Super Block Lock */
+#define                   nSBLOCK  0x0       
+#define                   FMPLLST  0xc        /* Frequency Multiply PLL SM State */
+#define                  CDRPLLST  0xe0       /* Clock/Data Recovery PLL SM State */
+#define                     APBSY  0x100      /* Asynchronous Packet Transmit Buffer Busy */
+#define                    nAPBSY  0x0       
+#define                     APARB  0x200      /* Asynchronous Packet Arbitrating */
+#define                    nAPARB  0x0       
+#define                      APTX  0x400      /* Asynchronous Packet Transmitting */
+#define                     nAPTX  0x0       
+#define                      APRX  0x800      /* Receiving Asynchronous Packet */
+#define                     nAPRX  0x0       
+#define                     CMBSY  0x1000     /* Control Message Transmit Buffer Busy */
+#define                    nCMBSY  0x0       
+#define                     CMARB  0x2000     /* Control Message Arbitrating */
+#define                    nCMARB  0x0       
+#define                      CMTX  0x4000     /* Control Message Transmitting */
+#define                     nCMTX  0x0       
+#define                      CMRX  0x8000     /* Receiving Control Message */
+#define                     nCMRX  0x0       
+#define                    MRXONB  0x10000    /* MRXONB Pin State */
+#define                   nMRXONB  0x0       
+#define                     RGSIP  0x20000    /* Remote Get Source In Progress */
+#define                    nRGSIP  0x0       
+#define                     DALIP  0x40000    /* Resource Deallocate In Progress */
+#define                    nDALIP  0x0       
+#define                      ALIP  0x80000    /* Resource Allocate In Progress */
+#define                     nALIP  0x0       
+#define                     RRDIP  0x100000   /* Remote Read In Progress */
+#define                    nRRDIP  0x0       
+#define                     RWRIP  0x200000   /* Remote Write In Progress */
+#define                    nRWRIP  0x0       
+#define                     FLOCK  0x400000   /* Frame Lock */
+#define                    nFLOCK  0x0       
+#define                     BLOCK  0x800000   /* Block Lock */
+#define                    nBLOCK  0x0       
+#define                       RSB  0xf000000  /* Received Synchronous Boundary */
+#define                   DERRNUM  0xf0000000 /* DMA Error Channel Number */
+
+/* Bit masks for MXVR_STATE_1 */
+
+#define                   SRXNUMB  0xf        /* Synchronous Receive FIFO Number of Bytes */
+#define                   STXNUMB  0xf0       /* Synchronous Transmit FIFO Number of Bytes */
+#define                    APCONT  0x100      /* Asynchronous Packet Continuation */
+#define                   nAPCONT  0x0       
+#define                  OBERRNUM  0xe00      /* DMA Out of Bounds Error Channel Number */
+#define                DMAACTIVE0  0x10000    /* DMA0 Active */
+#define               nDMAACTIVE0  0x0       
+#define                DMAACTIVE1  0x20000    /* DMA1 Active */
+#define               nDMAACTIVE1  0x0       
+#define                DMAACTIVE2  0x40000    /* DMA2 Active */
+#define               nDMAACTIVE2  0x0       
+#define                DMAACTIVE3  0x80000    /* DMA3 Active */
+#define               nDMAACTIVE3  0x0       
+#define                DMAACTIVE4  0x100000   /* DMA4 Active */
+#define               nDMAACTIVE4  0x0       
+#define                DMAACTIVE5  0x200000   /* DMA5 Active */
+#define               nDMAACTIVE5  0x0       
+#define                DMAACTIVE6  0x400000   /* DMA6 Active */
+#define               nDMAACTIVE6  0x0       
+#define                DMAACTIVE7  0x800000   /* DMA7 Active */
+#define               nDMAACTIVE7  0x0       
+#define                  DMAPMEN0  0x1000000  /* DMA0 Pattern Matching Enabled */
+#define                 nDMAPMEN0  0x0       
+#define                  DMAPMEN1  0x2000000  /* DMA1 Pattern Matching Enabled */
+#define                 nDMAPMEN1  0x0       
+#define                  DMAPMEN2  0x4000000  /* DMA2 Pattern Matching Enabled */
+#define                 nDMAPMEN2  0x0       
+#define                  DMAPMEN3  0x8000000  /* DMA3 Pattern Matching Enabled */
+#define                 nDMAPMEN3  0x0       
+#define                  DMAPMEN4  0x10000000 /* DMA4 Pattern Matching Enabled */
+#define                 nDMAPMEN4  0x0       
+#define                  DMAPMEN5  0x20000000 /* DMA5 Pattern Matching Enabled */
+#define                 nDMAPMEN5  0x0       
+#define                  DMAPMEN6  0x40000000 /* DMA6 Pattern Matching Enabled */
+#define                 nDMAPMEN6  0x0       
+#define                  DMAPMEN7  0x80000000 /* DMA7 Pattern Matching Enabled */
+#define                 nDMAPMEN7  0x0       
+
+/* Bit masks for MXVR_INT_STAT_0 */
+
+#define                      NI2A  0x1        /* Network Inactive to Active */
+#define                     nNI2A  0x0       
+#define                      NA2I  0x2        /* Network Active to Inactive */
+#define                     nNA2I  0x0       
+#define                     SBU2L  0x4        /* Super Block Unlock to Lock */
+#define                    nSBU2L  0x0       
+#define                     SBL2U  0x8        /* Super Block Lock to Unlock */
+#define                    nSBL2U  0x0       
+#define                       PRU  0x10       /* Position Register Updated */
+#define                      nPRU  0x0       
+#define                      MPRU  0x20       /* Maximum Position Register Updated */
+#define                     nMPRU  0x0       
+#define                       DRU  0x40       /* Delay Register Updated */
+#define                      nDRU  0x0       
+#define                      MDRU  0x80       /* Maximum Delay Register Updated */
+#define                     nMDRU  0x0       
+#define                       SBU  0x100      /* Synchronous Boundary Updated */
+#define                      nSBU  0x0       
+#define                       ATU  0x200      /* Allocation Table Updated */
+#define                      nATU  0x0       
+#define                      FCZ0  0x400      /* Frame Counter 0 Zero */
+#define                     nFCZ0  0x0       
+#define                      FCZ1  0x800      /* Frame Counter 1 Zero */
+#define                     nFCZ1  0x0       
+#define                      PERR  0x1000     /* Parity Error */
+#define                     nPERR  0x0       
+#define                      MH2L  0x2000     /* MRXONB High to Low */
+#define                     nMH2L  0x0       
+#define                      ML2H  0x4000     /* MRXONB Low to High */
+#define                     nML2H  0x0       
+#define                       WUP  0x8000     /* Wake-Up Preamble Received */
+#define                      nWUP  0x0       
+#define                      FU2L  0x10000    /* Frame Unlock to Lock */
+#define                     nFU2L  0x0       
+#define                      FL2U  0x20000    /* Frame Lock to Unlock */
+#define                     nFL2U  0x0       
+#define                      BU2L  0x40000    /* Block Unlock to Lock */
+#define                     nBU2L  0x0       
+#define                      BL2U  0x80000    /* Block Lock to Unlock */
+#define                     nBL2U  0x0       
+#define                     OBERR  0x100000   /* DMA Out of Bounds Error */
+#define                    nOBERR  0x0       
+#define                       PFL  0x200000   /* PLL Frequency Locked */
+#define                      nPFL  0x0       
+#define                       SCZ  0x400000   /* System Clock Counter Zero */
+#define                      nSCZ  0x0       
+#define                      FERR  0x800000   /* FIFO Error */
+#define                     nFERR  0x0       
+#define                       CMR  0x1000000  /* Control Message Received */
+#define                      nCMR  0x0       
+#define                     CMROF  0x2000000  /* Control Message Receive Buffer Overflow */
+#define                    nCMROF  0x0       
+#define                      CMTS  0x4000000  /* Control Message Transmit Buffer Successfully Sent */
+#define                     nCMTS  0x0       
+#define                      CMTC  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled */
+#define                     nCMTC  0x0       
+#define                      RWRC  0x10000000 /* Remote Write Control Message Completed */
+#define                     nRWRC  0x0       
+#define                       BCZ  0x20000000 /* Block Counter Zero */
+#define                      nBCZ  0x0       
+#define                     BMERR  0x40000000 /* Biphase Mark Coding Error */
+#define                    nBMERR  0x0       
+#define                      DERR  0x80000000 /* DMA Error */
+#define                     nDERR  0x0       
+
+/* Bit masks for MXVR_INT_STAT_1 */
+
+#define                    HDONE0  0x1        /* DMA0 Half Done */
+#define                   nHDONE0  0x0       
+#define                     DONE0  0x2        /* DMA0 Done */
+#define                    nDONE0  0x0       
+#define                       APR  0x4        /* Asynchronous Packet Received */
+#define                      nAPR  0x0       
+#define                     APROF  0x8        /* Asynchronous Packet Receive Buffer Overflow */
+#define                    nAPROF  0x0       
+#define                    HDONE1  0x10       /* DMA1 Half Done */
+#define                   nHDONE1  0x0       
+#define                     DONE1  0x20       /* DMA1 Done */
+#define                    nDONE1  0x0       
+#define                      APTS  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent */
+#define                     nAPTS  0x0       
+#define                      APTC  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
+#define                     nAPTC  0x0       
+#define                    HDONE2  0x100      /* DMA2 Half Done */
+#define                   nHDONE2  0x0       
+#define                     DONE2  0x200      /* DMA2 Done */
+#define                    nDONE2  0x0       
+#define                     APRCE  0x400      /* Asynchronous Packet Receive CRC Error */
+#define                    nAPRCE  0x0       
+#define                     APRPE  0x800      /* Asynchronous Packet Receive Packet Error */
+#define                    nAPRPE  0x0       
+#define                    HDONE3  0x1000     /* DMA3 Half Done */
+#define                   nHDONE3  0x0       
+#define                     DONE3  0x2000     /* DMA3 Done */
+#define                    nDONE3  0x0       
+#define                    HDONE4  0x10000    /* DMA4 Half Done */
+#define                   nHDONE4  0x0       
+#define                     DONE4  0x20000    /* DMA4 Done */
+#define                    nDONE4  0x0       
+#define                    HDONE5  0x100000   /* DMA5 Half Done */
+#define                   nHDONE5  0x0       
+#define                     DONE5  0x200000   /* DMA5 Done */
+#define                    nDONE5  0x0       
+#define                    HDONE6  0x1000000  /* DMA6 Half Done */
+#define                   nHDONE6  0x0       
+#define                     DONE6  0x2000000  /* DMA6 Done */
+#define                    nDONE6  0x0       
+#define                    HDONE7  0x10000000 /* DMA7 Half Done */
+#define                   nHDONE7  0x0       
+#define                     DONE7  0x20000000 /* DMA7 Done */
+#define                    nDONE7  0x0       
+
+/* Bit masks for MXVR_INT_EN_0 */
+
+#define                    NI2AEN  0x1        /* Network Inactive to Active Interrupt Enable */
+#define                   nNI2AEN  0x0       
+#define                    NA2IEN  0x2        /* Network Active to Inactive Interrupt Enable */
+#define                   nNA2IEN  0x0       
+#define                   SBU2LEN  0x4        /* Super Block Unlock to Lock Interrupt Enable */
+#define                  nSBU2LEN  0x0       
+#define                   SBL2UEN  0x8        /* Super Block Lock to Unlock Interrupt Enable */
+#define                  nSBL2UEN  0x0       
+#define                     PRUEN  0x10       /* Position Register Updated Interrupt Enable */
+#define                    nPRUEN  0x0       
+#define                    MPRUEN  0x20       /* Maximum Position Register Updated Interrupt Enable */
+#define                   nMPRUEN  0x0       
+#define                     DRUEN  0x40       /* Delay Register Updated Interrupt Enable */
+#define                    nDRUEN  0x0       
+#define                    MDRUEN  0x80       /* Maximum Delay Register Updated Interrupt Enable */
+#define                   nMDRUEN  0x0       
+#define                     SBUEN  0x100      /* Synchronous Boundary Updated Interrupt Enable */
+#define                    nSBUEN  0x0       
+#define                     ATUEN  0x200      /* Allocation Table Updated Interrupt Enable */
+#define                    nATUEN  0x0       
+#define                    FCZ0EN  0x400      /* Frame Counter 0 Zero Interrupt Enable */
+#define                   nFCZ0EN  0x0       
+#define                    FCZ1EN  0x800      /* Frame Counter 1 Zero Interrupt Enable */
+#define                   nFCZ1EN  0x0       
+#define                    PERREN  0x1000     /* Parity Error Interrupt Enable */
+#define                   nPERREN  0x0       
+#define                    MH2LEN  0x2000     /* MRXONB High to Low Interrupt Enable */
+#define                   nMH2LEN  0x0       
+#define                    ML2HEN  0x4000     /* MRXONB Low to High Interrupt Enable */
+#define                   nML2HEN  0x0       
+#define                     WUPEN  0x8000     /* Wake-Up Preamble Received Interrupt Enable */
+#define                    nWUPEN  0x0       
+#define                    FU2LEN  0x10000    /* Frame Unlock to Lock Interrupt Enable */
+#define                   nFU2LEN  0x0       
+#define                    FL2UEN  0x20000    /* Frame Lock to Unlock Interrupt Enable */
+#define                   nFL2UEN  0x0       
+#define                    BU2LEN  0x40000    /* Block Unlock to Lock Interrupt Enable */
+#define                   nBU2LEN  0x0       
+#define                    BL2UEN  0x80000    /* Block Lock to Unlock Interrupt Enable */
+#define                   nBL2UEN  0x0       
+#define                   OBERREN  0x100000   /* DMA Out of Bounds Error Interrupt Enable */
+#define                  nOBERREN  0x0       
+#define                     PFLEN  0x200000   /* PLL Frequency Locked Interrupt Enable */
+#define                    nPFLEN  0x0       
+#define                     SCZEN  0x400000   /* System Clock Counter Zero Interrupt Enable */
+#define                    nSCZEN  0x0       
+#define                    FERREN  0x800000   /* FIFO Error Interrupt Enable */
+#define                   nFERREN  0x0       
+#define                     CMREN  0x1000000  /* Control Message Received Interrupt Enable */
+#define                    nCMREN  0x0       
+#define                   CMROFEN  0x2000000  /* Control Message Receive Buffer Overflow Interrupt Enable */
+#define                  nCMROFEN  0x0       
+#define                    CMTSEN  0x4000000  /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
+#define                   nCMTSEN  0x0       
+#define                    CMTCEN  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
+#define                   nCMTCEN  0x0       
+#define                    RWRCEN  0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
+#define                   nRWRCEN  0x0       
+#define                     BCZEN  0x20000000 /* Block Counter Zero Interrupt Enable */
+#define                    nBCZEN  0x0       
+#define                   BMERREN  0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
+#define                  nBMERREN  0x0       
+#define                    DERREN  0x80000000 /* DMA Error Interrupt Enable */
+#define                   nDERREN  0x0       
+
+/* Bit masks for MXVR_INT_EN_1 */
+
+#define                  HDONEEN0  0x1        /* DMA0 Half Done Interrupt Enable */
+#define                 nHDONEEN0  0x0       
+#define                   DONEEN0  0x2        /* DMA0 Done Interrupt Enable */
+#define                  nDONEEN0  0x0       
+#define                     APREN  0x4        /* Asynchronous Packet Received Interrupt Enable */
+#define                    nAPREN  0x0       
+#define                   APROFEN  0x8        /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
+#define                  nAPROFEN  0x0       
+#define                  HDONEEN1  0x10       /* DMA1 Half Done Interrupt Enable */
+#define                 nHDONEEN1  0x0       
+#define                   DONEEN1  0x20       /* DMA1 Done Interrupt Enable */
+#define                  nDONEEN1  0x0       
+#define                    APTSEN  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
+#define                   nAPTSEN  0x0       
+#define                    APTCEN  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
+#define                   nAPTCEN  0x0       
+#define                  HDONEEN2  0x100      /* DMA2 Half Done Interrupt Enable */
+#define                 nHDONEEN2  0x0       
+#define                   DONEEN2  0x200      /* DMA2 Done Interrupt Enable */
+#define                  nDONEEN2  0x0       
+#define                   APRCEEN  0x400      /* Asynchronous Packet Receive CRC Error Interrupt Enable */
+#define                  nAPRCEEN  0x0       
+#define                   APRPEEN  0x800      /* Asynchronous Packet Receive Packet Error Interrupt Enable */
+#define                  nAPRPEEN  0x0       
+#define                  HDONEEN3  0x1000     /* DMA3 Half Done Interrupt Enable */
+#define                 nHDONEEN3  0x0       
+#define                   DONEEN3  0x2000     /* DMA3 Done Interrupt Enable */
+#define                  nDONEEN3  0x0       
+#define                  HDONEEN4  0x10000    /* DMA4 Half Done Interrupt Enable */
+#define                 nHDONEEN4  0x0       
+#define                   DONEEN4  0x20000    /* DMA4 Done Interrupt Enable */
+#define                  nDONEEN4  0x0       
+#define                  HDONEEN5  0x100000   /* DMA5 Half Done Interrupt Enable */
+#define                 nHDONEEN5  0x0       
+#define                   DONEEN5  0x200000   /* DMA5 Done Interrupt Enable */
+#define                  nDONEEN5  0x0       
+#define                  HDONEEN6  0x1000000  /* DMA6 Half Done Interrupt Enable */
+#define                 nHDONEEN6  0x0       
+#define                   DONEEN6  0x2000000  /* DMA6 Done Interrupt Enable */
+#define                  nDONEEN6  0x0       
+#define                  HDONEEN7  0x10000000 /* DMA7 Half Done Interrupt Enable */
+#define                 nHDONEEN7  0x0       
+#define                   DONEEN7  0x20000000 /* DMA7 Done Interrupt Enable */
+#define                  nDONEEN7  0x0       
+
+/* Bit masks for MXVR_POSITION */
+
+#define                  POSITION  0x3f       /* Node Position */
+#define                    PVALID  0x8000     /* Node Position Valid */
+#define                   nPVALID  0x0       
+
+/* Bit masks for MXVR_MAX_POSITION */
+
+#define                 MPOSITION  0x3f       /* Maximum Node Position */
+#define                   MPVALID  0x8000     /* Maximum Node Position Valid */
+#define                  nMPVALID  0x0       
+
+/* Bit masks for MXVR_DELAY */
+
+#define                     DELAY  0x3f       /* Node Frame Delay */
+#define                    DVALID  0x8000     /* Node Frame Delay Valid */
+#define                   nDVALID  0x0       
+
+/* Bit masks for MXVR_MAX_DELAY */
+
+#define                    MDELAY  0x3f       /* Maximum Node Frame Delay */
+#define                   MDVALID  0x8000     /* Maximum Node Frame Delay Valid */
+#define                  nMDVALID  0x0       
+
+/* Bit masks for MXVR_LADDR */
+
+#define                     LADDR  0xffff     /* Logical Address */
+#define                    LVALID  0x80000000 /* Logical Address Valid */
+#define                   nLVALID  0x0       
+
+/* Bit masks for MXVR_GADDR */
+
+#define                    GADDRL  0xff       /* Group Address Lower Byte */
+#define                    GVALID  0x8000     /* Group Address Valid */
+#define                   nGVALID  0x0       
+
+/* Bit masks for MXVR_AADDR */
+
+#define                     AADDR  0xffff     /* Alternate Address */
+#define                    AVALID  0x80000000 /* Alternate Address Valid */
+#define                   nAVALID  0x0       
+
+/* Bit masks for MXVR_ALLOC_0 */
+
+#define                       CL0  0x7f       /* Channel 0 Connection Label */
+#define                      CIU0  0x80       /* Channel 0 In Use */
+#define                     nCIU0  0x0       
+#define                       CL1  0x7f00     /* Channel 0 Connection Label */
+#define                      CIU1  0x8000     /* Channel 0 In Use */
+#define                     nCIU1  0x0       
+#define                       CL2  0x7f0000   /* Channel 0 Connection Label */
+#define                      CIU2  0x800000   /* Channel 0 In Use */
+#define                     nCIU2  0x0       
+#define                       CL3  0x7f000000 /* Channel 0 Connection Label */
+#define                      CIU3  0x80000000 /* Channel 0 In Use */
+#define                     nCIU3  0x0       
+
+/* Bit masks for MXVR_ALLOC_1 */
+
+#define                       CL4  0x7f       /* Channel 4 Connection Label */
+#define                      CIU4  0x80       /* Channel 4 In Use */
+#define                     nCIU4  0x0       
+#define                       CL5  0x7f00     /* Channel 5 Connection Label */
+#define                      CIU5  0x8000     /* Channel 5 In Use */
+#define                     nCIU5  0x0       
+#define                       CL6  0x7f0000   /* Channel 6 Connection Label */
+#define                      CIU6  0x800000   /* Channel 6 In Use */
+#define                     nCIU6  0x0       
+#define                       CL7  0x7f000000 /* Channel 7 Connection Label */
+#define                      CIU7  0x80000000 /* Channel 7 In Use */
+#define                     nCIU7  0x0       
+
+/* Bit masks for MXVR_ALLOC_2 */
+
+#define                       CL8  0x7f       /* Channel 8 Connection Label */
+#define                      CIU8  0x80       /* Channel 8 In Use */
+#define                     nCIU8  0x0       
+#define                       CL9  0x7f00     /* Channel 9 Connection Label */
+#define                      CIU9  0x8000     /* Channel 9 In Use */
+#define                     nCIU9  0x0       
+#define                      CL10  0x7f0000   /* Channel 10 Connection Label */
+#define                     CIU10  0x800000   /* Channel 10 In Use */
+#define                    nCIU10  0x0       
+#define                      CL11  0x7f000000 /* Channel 11 Connection Label */
+#define                     CIU11  0x80000000 /* Channel 11 In Use */
+#define                    nCIU11  0x0       
+
+/* Bit masks for MXVR_ALLOC_3 */
+
+#define                      CL12  0x7f       /* Channel 12 Connection Label */
+#define                     CIU12  0x80       /* Channel 12 In Use */
+#define                    nCIU12  0x0       
+#define                      CL13  0x7f00     /* Channel 13 Connection Label */
+#define                     CIU13  0x8000     /* Channel 13 In Use */
+#define                    nCIU13  0x0       
+#define                      CL14  0x7f0000   /* Channel 14 Connection Label */
+#define                     CIU14  0x800000   /* Channel 14 In Use */
+#define                    nCIU14  0x0       
+#define                      CL15  0x7f000000 /* Channel 15 Connection Label */
+#define                     CIU15  0x80000000 /* Channel 15 In Use */
+#define                    nCIU15  0x0       
+
+/* Bit masks for MXVR_ALLOC_4 */
+
+#define                      CL16  0x7f       /* Channel 16 Connection Label */
+#define                     CIU16  0x80       /* Channel 16 In Use */
+#define                    nCIU16  0x0       
+#define                      CL17  0x7f00     /* Channel 17 Connection Label */
+#define                     CIU17  0x8000     /* Channel 17 In Use */
+#define                    nCIU17  0x0       
+#define                      CL18  0x7f0000   /* Channel 18 Connection Label */
+#define                     CIU18  0x800000   /* Channel 18 In Use */
+#define                    nCIU18  0x0       
+#define                      CL19  0x7f000000 /* Channel 19 Connection Label */
+#define                     CIU19  0x80000000 /* Channel 19 In Use */
+#define                    nCIU19  0x0       
+
+/* Bit masks for MXVR_ALLOC_5 */
+
+#define                      CL20  0x7f       /* Channel 20 Connection Label */
+#define                     CIU20  0x80       /* Channel 20 In Use */
+#define                    nCIU20  0x0       
+#define                      CL21  0x7f00     /* Channel 21 Connection Label */
+#define                     CIU21  0x8000     /* Channel 21 In Use */
+#define                    nCIU21  0x0       
+#define                      CL22  0x7f0000   /* Channel 22 Connection Label */
+#define                     CIU22  0x800000   /* Channel 22 In Use */
+#define                    nCIU22  0x0       
+#define                      CL23  0x7f000000 /* Channel 23 Connection Label */
+#define                     CIU23  0x80000000 /* Channel 23 In Use */
+#define                    nCIU23  0x0       
+
+/* Bit masks for MXVR_ALLOC_6 */
+
+#define                      CL24  0x7f       /* Channel 24 Connection Label */
+#define                     CIU24  0x80       /* Channel 24 In Use */
+#define                    nCIU24  0x0       
+#define                      CL25  0x7f00     /* Channel 25 Connection Label */
+#define                     CIU25  0x8000     /* Channel 25 In Use */
+#define                    nCIU25  0x0       
+#define                      CL26  0x7f0000   /* Channel 26 Connection Label */
+#define                     CIU26  0x800000   /* Channel 26 In Use */
+#define                    nCIU26  0x0       
+#define                      CL27  0x7f000000 /* Channel 27 Connection Label */
+#define                     CIU27  0x80000000 /* Channel 27 In Use */
+#define                    nCIU27  0x0       
+
+/* Bit masks for MXVR_ALLOC_7 */
+
+#define                      CL28  0x7f       /* Channel 28 Connection Label */
+#define                     CIU28  0x80       /* Channel 28 In Use */
+#define                    nCIU28  0x0       
+#define                      CL29  0x7f00     /* Channel 29 Connection Label */
+#define                     CIU29  0x8000     /* Channel 29 In Use */
+#define                    nCIU29  0x0       
+#define                      CL30  0x7f0000   /* Channel 30 Connection Label */
+#define                     CIU30  0x800000   /* Channel 30 In Use */
+#define                    nCIU30  0x0       
+#define                      CL31  0x7f000000 /* Channel 31 Connection Label */
+#define                     CIU31  0x80000000 /* Channel 31 In Use */
+#define                    nCIU31  0x0       
+
+/* Bit masks for MXVR_ALLOC_8 */
+
+#define                      CL32  0x7f       /* Channel 32 Connection Label */
+#define                     CIU32  0x80       /* Channel 32 In Use */
+#define                    nCIU32  0x0       
+#define                      CL33  0x7f00     /* Channel 33 Connection Label */
+#define                     CIU33  0x8000     /* Channel 33 In Use */
+#define                    nCIU33  0x0       
+#define                      CL34  0x7f0000   /* Channel 34 Connection Label */
+#define                     CIU34  0x800000   /* Channel 34 In Use */
+#define                    nCIU34  0x0       
+#define                      CL35  0x7f000000 /* Channel 35 Connection Label */
+#define                     CIU35  0x80000000 /* Channel 35 In Use */
+#define                    nCIU35  0x0       
+
+/* Bit masks for MXVR_ALLOC_9 */
+
+#define                      CL36  0x7f       /* Channel 36 Connection Label */
+#define                     CIU36  0x80       /* Channel 36 In Use */
+#define                    nCIU36  0x0       
+#define                      CL37  0x7f00     /* Channel 37 Connection Label */
+#define                     CIU37  0x8000     /* Channel 37 In Use */
+#define                    nCIU37  0x0       
+#define                      CL38  0x7f0000   /* Channel 38 Connection Label */
+#define                     CIU38  0x800000   /* Channel 38 In Use */
+#define                    nCIU38  0x0       
+#define                      CL39  0x7f000000 /* Channel 39 Connection Label */
+#define                     CIU39  0x80000000 /* Channel 39 In Use */
+#define                    nCIU39  0x0       
+
+/* Bit masks for MXVR_ALLOC_10 */
+
+#define                      CL40  0x7f       /* Channel 40 Connection Label */
+#define                     CIU40  0x80       /* Channel 40 In Use */
+#define                    nCIU40  0x0       
+#define                      CL41  0x7f00     /* Channel 41 Connection Label */
+#define                     CIU41  0x8000     /* Channel 41 In Use */
+#define                    nCIU41  0x0       
+#define                      CL42  0x7f0000   /* Channel 42 Connection Label */
+#define                     CIU42  0x800000   /* Channel 42 In Use */
+#define                    nCIU42  0x0       
+#define                      CL43  0x7f000000 /* Channel 43 Connection Label */
+#define                     CIU43  0x80000000 /* Channel 43 In Use */
+#define                    nCIU43  0x0       
+
+/* Bit masks for MXVR_ALLOC_11 */
+
+#define                      CL44  0x7f       /* Channel 44 Connection Label */
+#define                     CIU44  0x80       /* Channel 44 In Use */
+#define                    nCIU44  0x0       
+#define                      CL45  0x7f00     /* Channel 45 Connection Label */
+#define                     CIU45  0x8000     /* Channel 45 In Use */
+#define                    nCIU45  0x0       
+#define                      CL46  0x7f0000   /* Channel 46 Connection Label */
+#define                     CIU46  0x800000   /* Channel 46 In Use */
+#define                    nCIU46  0x0       
+#define                      CL47  0x7f000000 /* Channel 47 Connection Label */
+#define                     CIU47  0x80000000 /* Channel 47 In Use */
+#define                    nCIU47  0x0       
+
+/* Bit masks for MXVR_ALLOC_12 */
+
+#define                      CL48  0x7f       /* Channel 48 Connection Label */
+#define                     CIU48  0x80       /* Channel 48 In Use */
+#define                    nCIU48  0x0       
+#define                      CL49  0x7f00     /* Channel 49 Connection Label */
+#define                     CIU49  0x8000     /* Channel 49 In Use */
+#define                    nCIU49  0x0       
+#define                      CL50  0x7f0000   /* Channel 50 Connection Label */
+#define                     CIU50  0x800000   /* Channel 50 In Use */
+#define                    nCIU50  0x0       
+#define                      CL51  0x7f000000 /* Channel 51 Connection Label */
+#define                     CIU51  0x80000000 /* Channel 51 In Use */
+#define                    nCIU51  0x0       
+
+/* Bit masks for MXVR_ALLOC_13 */
+
+#define                      CL52  0x7f       /* Channel 52 Connection Label */
+#define                     CIU52  0x80       /* Channel 52 In Use */
+#define                    nCIU52  0x0       
+#define                      CL53  0x7f00     /* Channel 53 Connection Label */
+#define                     CIU53  0x8000     /* Channel 53 In Use */
+#define                    nCIU53  0x0       
+#define                      CL54  0x7f0000   /* Channel 54 Connection Label */
+#define                     CIU54  0x800000   /* Channel 54 In Use */
+#define                    nCIU54  0x0       
+#define                      CL55  0x7f000000 /* Channel 55 Connection Label */
+#define                     CIU55  0x80000000 /* Channel 55 In Use */
+#define                    nCIU55  0x0       
+
+/* Bit masks for MXVR_ALLOC_14 */
+
+#define                      CL56  0x7f       /* Channel 56 Connection Label */
+#define                     CIU56  0x80       /* Channel 56 In Use */
+#define                    nCIU56  0x0       
+#define                      CL57  0x7f00     /* Channel 57 Connection Label */
+#define                     CIU57  0x8000     /* Channel 57 In Use */
+#define                    nCIU57  0x0       
+#define                      CL58  0x7f0000   /* Channel 58 Connection Label */
+#define                     CIU58  0x800000   /* Channel 58 In Use */
+#define                    nCIU58  0x0       
+#define                      CL59  0x7f000000 /* Channel 59 Connection Label */
+#define                     CIU59  0x80000000 /* Channel 59 In Use */
+#define                    nCIU59  0x0       
+
+/* MXVR_SYNC_LCHAN_0 Masks */
+
+#define LCHANPC0     0x0000000Flu
+#define LCHANPC1     0x000000F0lu
+#define LCHANPC2     0x00000F00lu
+#define LCHANPC3     0x0000F000lu
+#define LCHANPC4     0x000F0000lu
+#define LCHANPC5     0x00F00000lu
+#define LCHANPC6     0x0F000000lu
+#define LCHANPC7     0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_1 Masks */
+
+#define LCHANPC8     0x0000000Flu
+#define LCHANPC9     0x000000F0lu
+#define LCHANPC10    0x00000F00lu
+#define LCHANPC11    0x0000F000lu
+#define LCHANPC12    0x000F0000lu
+#define LCHANPC13    0x00F00000lu
+#define LCHANPC14    0x0F000000lu
+#define LCHANPC15    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_2 Masks */
+
+#define LCHANPC16    0x0000000Flu
+#define LCHANPC17    0x000000F0lu
+#define LCHANPC18    0x00000F00lu
+#define LCHANPC19    0x0000F000lu
+#define LCHANPC20    0x000F0000lu
+#define LCHANPC21    0x00F00000lu
+#define LCHANPC22    0x0F000000lu
+#define LCHANPC23    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_3 Masks */
+
+#define LCHANPC24    0x0000000Flu
+#define LCHANPC25    0x000000F0lu
+#define LCHANPC26    0x00000F00lu
+#define LCHANPC27    0x0000F000lu
+#define LCHANPC28    0x000F0000lu
+#define LCHANPC29    0x00F00000lu
+#define LCHANPC30    0x0F000000lu
+#define LCHANPC31    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_4 Masks */
+
+#define LCHANPC32    0x0000000Flu
+#define LCHANPC33    0x000000F0lu
+#define LCHANPC34    0x00000F00lu
+#define LCHANPC35    0x0000F000lu
+#define LCHANPC36    0x000F0000lu
+#define LCHANPC37    0x00F00000lu
+#define LCHANPC38    0x0F000000lu
+#define LCHANPC39    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_5 Masks */
+
+#define LCHANPC40    0x0000000Flu
+#define LCHANPC41    0x000000F0lu
+#define LCHANPC42    0x00000F00lu
+#define LCHANPC43    0x0000F000lu
+#define LCHANPC44    0x000F0000lu
+#define LCHANPC45    0x00F00000lu
+#define LCHANPC46    0x0F000000lu
+#define LCHANPC47    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_6 Masks */
+
+#define LCHANPC48    0x0000000Flu
+#define LCHANPC49    0x000000F0lu
+#define LCHANPC50    0x00000F00lu
+#define LCHANPC51    0x0000F000lu
+#define LCHANPC52    0x000F0000lu
+#define LCHANPC53    0x00F00000lu
+#define LCHANPC54    0x0F000000lu
+#define LCHANPC55    0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_7 Masks */
+
+#define LCHANPC56    0x0000000Flu
+#define LCHANPC57    0x000000F0lu
+#define LCHANPC58    0x00000F00lu
+#define LCHANPC59    0x0000F000lu
+
+/* Bit masks for MXVR_DMAx_CONFIG */
+
+#define                    MDMAEN  0x1        /* DMA Channel Enable */
+#define                   nMDMAEN  0x0       
+#define                        DD  0x2        /* DMA Channel Direction */
+#define                       nDD  0x0       
+#define                 BY4SWAPEN  0x20       /* DMA Channel Four Byte Swap Enable */
+#define                nBY4SWAPEN  0x0       
+#define                     LCHAN  0x3c0      /* DMA Channel Logical Channel */
+#define                 BITSWAPEN  0x400      /* DMA Channel Bit Swap Enable */
+#define                nBITSWAPEN  0x0       
+#define                 BY2SWAPEN  0x800      /* DMA Channel Two Byte Swap Enable */
+#define                nBY2SWAPEN  0x0       
+#define                     MFLOW  0x7000     /* DMA Channel Operation Flow */
+#define                   FIXEDPM  0x80000    /* DMA Channel Fixed Pattern Matching Select */
+#define                  nFIXEDPM  0x0       
+#define                  STARTPAT  0x300000   /* DMA Channel Start Pattern Select */
+#define                   STOPPAT  0xc00000   /* DMA Channel Stop Pattern Select */
+#define                  COUNTPOS  0x1c000000 /* DMA Channel Count Position */
+
+/* Bit masks for MXVR_AP_CTL */
+
+#define                   STARTAP  0x1        /* Start Asynchronous Packet Transmission */
+#define                  nSTARTAP  0x0       
+#define                  CANCELAP  0x2        /* Cancel Asynchronous Packet Transmission */
+#define                 nCANCELAP  0x0       
+#define                   RESETAP  0x4        /* Reset Asynchronous Packet Arbitration */
+#define                  nRESETAP  0x0       
+#define                    APRBE0  0x4000     /* Asynchronous Packet Receive Buffer Entry 0 */
+#define                   nAPRBE0  0x0       
+#define                    APRBE1  0x8000     /* Asynchronous Packet Receive Buffer Entry 1 */
+#define                   nAPRBE1  0x0       
+
+/* Bit masks for MXVR_APRB_START_ADDR */
+
+#define      MXVR_APRB_START_ADDR  0x1fffffe  /* Asynchronous Packet Receive Buffer Start Address */
+
+/* Bit masks for MXVR_APRB_CURR_ADDR */
+
+#define       MXVR_APRB_CURR_ADDR  0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
+
+/* Bit masks for MXVR_APTB_START_ADDR */
+
+#define       MXVR_APTB_START_ADDR  0x1fffffe  /* Asynchronous Packet Transmit Buffer Start Address */
+
+/* Bit masks for MXVR_APTB_CURR_ADDR */
+
+#define        MXVR_APTB_CURR_ADDR  0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
+
+/* Bit masks for MXVR_CM_CTL */
+
+#define                   STARTCM  0x1        /* Start Control Message Transmission */
+#define                  nSTARTCM  0x0       
+#define                  CANCELCM  0x2        /* Cancel Control Message Transmission */
+#define                 nCANCELCM  0x0       
+#define                    CMRBE0  0x10000    /* Control Message Receive Buffer Entry 0 */
+#define                   nCMRBE0  0x0       
+#define                    CMRBE1  0x20000    /* Control Message Receive Buffer Entry 1 */
+#define                   nCMRBE1  0x0       
+#define                    CMRBE2  0x40000    /* Control Message Receive Buffer Entry 2 */
+#define                   nCMRBE2  0x0       
+#define                    CMRBE3  0x80000    /* Control Message Receive Buffer Entry 3 */
+#define                   nCMRBE3  0x0       
+#define                    CMRBE4  0x100000   /* Control Message Receive Buffer Entry 4 */
+#define                   nCMRBE4  0x0       
+#define                    CMRBE5  0x200000   /* Control Message Receive Buffer Entry 5 */
+#define                   nCMRBE5  0x0       
+#define                    CMRBE6  0x400000   /* Control Message Receive Buffer Entry 6 */
+#define                   nCMRBE6  0x0       
+#define                    CMRBE7  0x800000   /* Control Message Receive Buffer Entry 7 */
+#define                   nCMRBE7  0x0       
+#define                    CMRBE8  0x1000000  /* Control Message Receive Buffer Entry 8 */
+#define                   nCMRBE8  0x0       
+#define                    CMRBE9  0x2000000  /* Control Message Receive Buffer Entry 9 */
+#define                   nCMRBE9  0x0       
+#define                   CMRBE10  0x4000000  /* Control Message Receive Buffer Entry 10 */
+#define                  nCMRBE10  0x0       
+#define                   CMRBE11  0x8000000  /* Control Message Receive Buffer Entry 11 */
+#define                  nCMRBE11  0x0       
+#define                   CMRBE12  0x10000000 /* Control Message Receive Buffer Entry 12 */
+#define                  nCMRBE12  0x0       
+#define                   CMRBE13  0x20000000 /* Control Message Receive Buffer Entry 13 */
+#define                  nCMRBE13  0x0       
+#define                   CMRBE14  0x40000000 /* Control Message Receive Buffer Entry 14 */
+#define                  nCMRBE14  0x0       
+#define                   CMRBE15  0x80000000 /* Control Message Receive Buffer Entry 15 */
+#define                  nCMRBE15  0x0       
+
+/* Bit masks for MXVR_CMRB_START_ADDR */
+
+#define      MXVR_CMRB_START_ADDR  0x1fffffe  /* Control Message Receive Buffer Start Address */
+
+/* Bit masks for MXVR_CMRB_CURR_ADDR */
+
+#define       MXVR_CMRB_CURR_ADDR  0xffffffff /* Control Message Receive Buffer Current Address */
+
+/* Bit masks for MXVR_CMTB_START_ADDR */
+
+#define      MXVR_CMTB_START_ADDR  0x1fffffe  /* Control Message Transmit Buffer Start Address */
+
+/* Bit masks for MXVR_CMTB_CURR_ADDR */
+
+#define       MXVR_CMTB_CURR_ADDR  0xffffffff /* Control Message Transmit Buffer Current Address */
+
+/* Bit masks for MXVR_RRDB_START_ADDR */
+
+#define      MXVR_RRDB_START_ADDR  0x1fffffe  /* Remote Read Buffer Start Address */
+
+/* Bit masks for MXVR_RRDB_CURR_ADDR */
+
+#define       MXVR_RRDB_CURR_ADDR  0xffffffff /* Remote Read Buffer Current Address */
+
+/* Bit masks for MXVR_PAT_DATAx */
+
+#define              MATCH_DATA_0  0xff       /* Pattern Match Data Byte 0 */
+#define              MATCH_DATA_1  0xff00     /* Pattern Match Data Byte 1 */
+#define              MATCH_DATA_2  0xff0000   /* Pattern Match Data Byte 2 */
+#define              MATCH_DATA_3  0xff000000 /* Pattern Match Data Byte 3 */
+
+/* Bit masks for MXVR_PAT_EN_0 */
+
+#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
+#define             nMATCH_EN_0_0  0x0       
+#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
+#define             nMATCH_EN_0_1  0x0       
+#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
+#define             nMATCH_EN_0_2  0x0       
+#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
+#define             nMATCH_EN_0_3  0x0       
+#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
+#define             nMATCH_EN_0_4  0x0       
+#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
+#define             nMATCH_EN_0_5  0x0       
+#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
+#define             nMATCH_EN_0_6  0x0       
+#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
+#define             nMATCH_EN_0_7  0x0       
+#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
+#define             nMATCH_EN_1_0  0x0       
+#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
+#define             nMATCH_EN_1_1  0x0       
+#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
+#define             nMATCH_EN_1_2  0x0       
+#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
+#define             nMATCH_EN_1_3  0x0       
+#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
+#define             nMATCH_EN_1_4  0x0       
+#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
+#define             nMATCH_EN_1_5  0x0       
+#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
+#define             nMATCH_EN_1_6  0x0       
+#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
+#define             nMATCH_EN_1_7  0x0       
+#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
+#define             nMATCH_EN_2_0  0x0       
+#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
+#define             nMATCH_EN_2_1  0x0       
+#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
+#define             nMATCH_EN_2_2  0x0       
+#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
+#define             nMATCH_EN_2_3  0x0       
+#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
+#define             nMATCH_EN_2_4  0x0       
+#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
+#define             nMATCH_EN_2_5  0x0       
+#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
+#define             nMATCH_EN_2_6  0x0       
+#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
+#define             nMATCH_EN_2_7  0x0       
+#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
+#define             nMATCH_EN_3_0  0x0       
+#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
+#define             nMATCH_EN_3_1  0x0       
+#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
+#define             nMATCH_EN_3_2  0x0       
+#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
+#define             nMATCH_EN_3_3  0x0       
+#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
+#define             nMATCH_EN_3_4  0x0       
+#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
+#define             nMATCH_EN_3_5  0x0       
+#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
+#define             nMATCH_EN_3_6  0x0       
+#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
+#define             nMATCH_EN_3_7  0x0       
+
+/* Bit masks for MXVR_PAT_EN_1 */
+
+#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
+#define             nMATCH_EN_0_0  0x0       
+#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
+#define             nMATCH_EN_0_1  0x0       
+#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
+#define             nMATCH_EN_0_2  0x0       
+#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
+#define             nMATCH_EN_0_3  0x0       
+#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
+#define             nMATCH_EN_0_4  0x0       
+#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
+#define             nMATCH_EN_0_5  0x0       
+#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
+#define             nMATCH_EN_0_6  0x0       
+#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
+#define             nMATCH_EN_0_7  0x0       
+#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
+#define             nMATCH_EN_1_0  0x0       
+#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
+#define             nMATCH_EN_1_1  0x0       
+#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
+#define             nMATCH_EN_1_2  0x0       
+#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
+#define             nMATCH_EN_1_3  0x0       
+#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
+#define             nMATCH_EN_1_4  0x0       
+#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
+#define             nMATCH_EN_1_5  0x0       
+#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
+#define             nMATCH_EN_1_6  0x0       
+#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
+#define             nMATCH_EN_1_7  0x0       
+#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
+#define             nMATCH_EN_2_0  0x0       
+#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
+#define             nMATCH_EN_2_1  0x0       
+#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
+#define             nMATCH_EN_2_2  0x0       
+#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
+#define             nMATCH_EN_2_3  0x0       
+#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
+#define             nMATCH_EN_2_4  0x0       
+#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
+#define             nMATCH_EN_2_5  0x0       
+#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
+#define             nMATCH_EN_2_6  0x0       
+#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
+#define             nMATCH_EN_2_7  0x0       
+#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
+#define             nMATCH_EN_3_0  0x0       
+#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
+#define             nMATCH_EN_3_1  0x0       
+#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
+#define             nMATCH_EN_3_2  0x0       
+#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
+#define             nMATCH_EN_3_3  0x0       
+#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
+#define             nMATCH_EN_3_4  0x0       
+#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
+#define             nMATCH_EN_3_5  0x0       
+#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
+#define             nMATCH_EN_3_6  0x0       
+#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
+#define             nMATCH_EN_3_7  0x0       
+
+/* Bit masks for MXVR_FRAME_CNT_0 */
+
+#define                      FCNT  0xffff     /* Frame Count */
+
+/* Bit masks for MXVR_FRAME_CNT_1 */
+
+#define                      FCNT  0xffff     /* Frame Count */
+
+/* Bit masks for MXVR_ROUTING_0 */
+
+#define                    TX_CH0  0x3f       /* Transmit Channel 0 */
+#define                  MUTE_CH0  0x80       /* Mute Channel 0 */
+#define                 nMUTE_CH0  0x0       
+#define                    TX_CH1  0x3f00     /* Transmit Channel 0 */
+#define                  MUTE_CH1  0x8000     /* Mute Channel 0 */
+#define                 nMUTE_CH1  0x0       
+#define                    TX_CH2  0x3f0000   /* Transmit Channel 0 */
+#define                  MUTE_CH2  0x800000   /* Mute Channel 0 */
+#define                 nMUTE_CH2  0x0       
+#define                    TX_CH3  0x3f000000 /* Transmit Channel 0 */
+#define                  MUTE_CH3  0x80000000 /* Mute Channel 0 */
+#define                 nMUTE_CH3  0x0       
+
+/* Bit masks for MXVR_ROUTING_1 */
+
+#define                    TX_CH4  0x3f       /* Transmit Channel 4 */
+#define                  MUTE_CH4  0x80       /* Mute Channel 4 */
+#define                 nMUTE_CH4  0x0       
+#define                    TX_CH5  0x3f00     /* Transmit Channel 5 */
+#define                  MUTE_CH5  0x8000     /* Mute Channel 5 */
+#define                 nMUTE_CH5  0x0       
+#define                    TX_CH6  0x3f0000   /* Transmit Channel 6 */
+#define                  MUTE_CH6  0x800000   /* Mute Channel 6 */
+#define                 nMUTE_CH6  0x0       
+#define                    TX_CH7  0x3f000000 /* Transmit Channel 7 */
+#define                  MUTE_CH7  0x80000000 /* Mute Channel 7 */
+#define                 nMUTE_CH7  0x0       
+
+/* Bit masks for MXVR_ROUTING_2 */
+
+#define                    TX_CH8  0x3f       /* Transmit Channel 8 */
+#define                  MUTE_CH8  0x80       /* Mute Channel 8 */
+#define                 nMUTE_CH8  0x0       
+#define                    TX_CH9  0x3f00     /* Transmit Channel 9 */
+#define                  MUTE_CH9  0x8000     /* Mute Channel 9 */
+#define                 nMUTE_CH9  0x0       
+#define                   TX_CH10  0x3f0000   /* Transmit Channel 10 */
+#define                 MUTE_CH10  0x800000   /* Mute Channel 10 */
+#define                nMUTE_CH10  0x0       
+#define                   TX_CH11  0x3f000000 /* Transmit Channel 11 */
+#define                 MUTE_CH11  0x80000000 /* Mute Channel 11 */
+#define                nMUTE_CH11  0x0       
+
+/* Bit masks for MXVR_ROUTING_3 */
+
+#define                   TX_CH12  0x3f       /* Transmit Channel 12 */
+#define                 MUTE_CH12  0x80       /* Mute Channel 12 */
+#define                nMUTE_CH12  0x0       
+#define                   TX_CH13  0x3f00     /* Transmit Channel 13 */
+#define                 MUTE_CH13  0x8000     /* Mute Channel 13 */
+#define                nMUTE_CH13  0x0       
+#define                   TX_CH14  0x3f0000   /* Transmit Channel 14 */
+#define                 MUTE_CH14  0x800000   /* Mute Channel 14 */
+#define                nMUTE_CH14  0x0       
+#define                   TX_CH15  0x3f000000 /* Transmit Channel 15 */
+#define                 MUTE_CH15  0x80000000 /* Mute Channel 15 */
+#define                nMUTE_CH15  0x0       
+
+/* Bit masks for MXVR_ROUTING_4 */
+
+#define                   TX_CH16  0x3f       /* Transmit Channel 16 */
+#define                 MUTE_CH16  0x80       /* Mute Channel 16 */
+#define                nMUTE_CH16  0x0       
+#define                   TX_CH17  0x3f00     /* Transmit Channel 17 */
+#define                 MUTE_CH17  0x8000     /* Mute Channel 17 */
+#define                nMUTE_CH17  0x0       
+#define                   TX_CH18  0x3f0000   /* Transmit Channel 18 */
+#define                 MUTE_CH18  0x800000   /* Mute Channel 18 */
+#define                nMUTE_CH18  0x0       
+#define                   TX_CH19  0x3f000000 /* Transmit Channel 19 */
+#define                 MUTE_CH19  0x80000000 /* Mute Channel 19 */
+#define                nMUTE_CH19  0x0       
+
+/* Bit masks for MXVR_ROUTING_5 */
+
+#define                   TX_CH20  0x3f       /* Transmit Channel 20 */
+#define                 MUTE_CH20  0x80       /* Mute Channel 20 */
+#define                nMUTE_CH20  0x0       
+#define                   TX_CH21  0x3f00     /* Transmit Channel 21 */
+#define                 MUTE_CH21  0x8000     /* Mute Channel 21 */
+#define                nMUTE_CH21  0x0       
+#define                   TX_CH22  0x3f0000   /* Transmit Channel 22 */
+#define                 MUTE_CH22  0x800000   /* Mute Channel 22 */
+#define                nMUTE_CH22  0x0       
+#define                   TX_CH23  0x3f000000 /* Transmit Channel 23 */
+#define                 MUTE_CH23  0x80000000 /* Mute Channel 23 */
+#define                nMUTE_CH23  0x0       
+
+/* Bit masks for MXVR_ROUTING_6 */
+
+#define                   TX_CH24  0x3f       /* Transmit Channel 24 */
+#define                 MUTE_CH24  0x80       /* Mute Channel 24 */
+#define                nMUTE_CH24  0x0       
+#define                   TX_CH25  0x3f00     /* Transmit Channel 25 */
+#define                 MUTE_CH25  0x8000     /* Mute Channel 25 */
+#define                nMUTE_CH25  0x0       
+#define                   TX_CH26  0x3f0000   /* Transmit Channel 26 */
+#define                 MUTE_CH26  0x800000   /* Mute Channel 26 */
+#define                nMUTE_CH26  0x0       
+#define                   TX_CH27  0x3f000000 /* Transmit Channel 27 */
+#define                 MUTE_CH27  0x80000000 /* Mute Channel 27 */
+#define                nMUTE_CH27  0x0       
+
+/* Bit masks for MXVR_ROUTING_7 */
+
+#define                   TX_CH28  0x3f       /* Transmit Channel 28 */
+#define                 MUTE_CH28  0x80       /* Mute Channel 28 */
+#define                nMUTE_CH28  0x0       
+#define                   TX_CH29  0x3f00     /* Transmit Channel 29 */
+#define                 MUTE_CH29  0x8000     /* Mute Channel 29 */
+#define                nMUTE_CH29  0x0       
+#define                   TX_CH30  0x3f0000   /* Transmit Channel 30 */
+#define                 MUTE_CH30  0x800000   /* Mute Channel 30 */
+#define                nMUTE_CH30  0x0       
+#define                   TX_CH31  0x3f000000 /* Transmit Channel 31 */
+#define                 MUTE_CH31  0x80000000 /* Mute Channel 31 */
+#define                nMUTE_CH31  0x0       
+
+/* Bit masks for MXVR_ROUTING_8 */
+
+#define                   TX_CH32  0x3f       /* Transmit Channel 32 */
+#define                 MUTE_CH32  0x80       /* Mute Channel 32 */
+#define                nMUTE_CH32  0x0       
+#define                   TX_CH33  0x3f00     /* Transmit Channel 33 */
+#define                 MUTE_CH33  0x8000     /* Mute Channel 33 */
+#define                nMUTE_CH33  0x0       
+#define                   TX_CH34  0x3f0000   /* Transmit Channel 34 */
+#define                 MUTE_CH34  0x800000   /* Mute Channel 34 */
+#define                nMUTE_CH34  0x0       
+#define                   TX_CH35  0x3f000000 /* Transmit Channel 35 */
+#define                 MUTE_CH35  0x80000000 /* Mute Channel 35 */
+#define                nMUTE_CH35  0x0       
+
+/* Bit masks for MXVR_ROUTING_9 */
+
+#define                   TX_CH36  0x3f       /* Transmit Channel 36 */
+#define                 MUTE_CH36  0x80       /* Mute Channel 36 */
+#define                nMUTE_CH36  0x0       
+#define                   TX_CH37  0x3f00     /* Transmit Channel 37 */
+#define                 MUTE_CH37  0x8000     /* Mute Channel 37 */
+#define                nMUTE_CH37  0x0       
+#define                   TX_CH38  0x3f0000   /* Transmit Channel 38 */
+#define                 MUTE_CH38  0x800000   /* Mute Channel 38 */
+#define                nMUTE_CH38  0x0       
+#define                   TX_CH39  0x3f000000 /* Transmit Channel 39 */
+#define                 MUTE_CH39  0x80000000 /* Mute Channel 39 */
+#define                nMUTE_CH39  0x0       
+
+/* Bit masks for MXVR_ROUTING_10 */
+
+#define                   TX_CH40  0x3f       /* Transmit Channel 40 */
+#define                 MUTE_CH40  0x80       /* Mute Channel 40 */
+#define                nMUTE_CH40  0x0       
+#define                   TX_CH41  0x3f00     /* Transmit Channel 41 */
+#define                 MUTE_CH41  0x8000     /* Mute Channel 41 */
+#define                nMUTE_CH41  0x0       
+#define                   TX_CH42  0x3f0000   /* Transmit Channel 42 */
+#define                 MUTE_CH42  0x800000   /* Mute Channel 42 */
+#define                nMUTE_CH42  0x0       
+#define                   TX_CH43  0x3f000000 /* Transmit Channel 43 */
+#define                 MUTE_CH43  0x80000000 /* Mute Channel 43 */
+#define                nMUTE_CH43  0x0       
+
+/* Bit masks for MXVR_ROUTING_11 */
+
+#define                   TX_CH44  0x3f       /* Transmit Channel 44 */
+#define                 MUTE_CH44  0x80       /* Mute Channel 44 */
+#define                nMUTE_CH44  0x0       
+#define                   TX_CH45  0x3f00     /* Transmit Channel 45 */
+#define                 MUTE_CH45  0x8000     /* Mute Channel 45 */
+#define                nMUTE_CH45  0x0       
+#define                   TX_CH46  0x3f0000   /* Transmit Channel 46 */
+#define                 MUTE_CH46  0x800000   /* Mute Channel 46 */
+#define                nMUTE_CH46  0x0       
+#define                   TX_CH47  0x3f000000 /* Transmit Channel 47 */
+#define                 MUTE_CH47  0x80000000 /* Mute Channel 47 */
+#define                nMUTE_CH47  0x0       
+
+/* Bit masks for MXVR_ROUTING_12 */
+
+#define                   TX_CH48  0x3f       /* Transmit Channel 48 */
+#define                 MUTE_CH48  0x80       /* Mute Channel 48 */
+#define                nMUTE_CH48  0x0       
+#define                   TX_CH49  0x3f00     /* Transmit Channel 49 */
+#define                 MUTE_CH49  0x8000     /* Mute Channel 49 */
+#define                nMUTE_CH49  0x0       
+#define                   TX_CH50  0x3f0000   /* Transmit Channel 50 */
+#define                 MUTE_CH50  0x800000   /* Mute Channel 50 */
+#define                nMUTE_CH50  0x0       
+#define                   TX_CH51  0x3f000000 /* Transmit Channel 51 */
+#define                 MUTE_CH51  0x80000000 /* Mute Channel 51 */
+#define                nMUTE_CH51  0x0       
+
+/* Bit masks for MXVR_ROUTING_13 */
+
+#define                   TX_CH52  0x3f       /* Transmit Channel 52 */
+#define                 MUTE_CH52  0x80       /* Mute Channel 52 */
+#define                nMUTE_CH52  0x0       
+#define                   TX_CH53  0x3f00     /* Transmit Channel 53 */
+#define                 MUTE_CH53  0x8000     /* Mute Channel 53 */
+#define                nMUTE_CH53  0x0       
+#define                   TX_CH54  0x3f0000   /* Transmit Channel 54 */
+#define                 MUTE_CH54  0x800000   /* Mute Channel 54 */
+#define                nMUTE_CH54  0x0       
+#define                   TX_CH55  0x3f000000 /* Transmit Channel 55 */
+#define                 MUTE_CH55  0x80000000 /* Mute Channel 55 */
+#define                nMUTE_CH55  0x0       
+
+/* Bit masks for MXVR_ROUTING_14 */
+
+#define                   TX_CH56  0x3f       /* Transmit Channel 56 */
+#define                 MUTE_CH56  0x80       /* Mute Channel 56 */
+#define                nMUTE_CH56  0x0       
+#define                   TX_CH57  0x3f00     /* Transmit Channel 57 */
+#define                 MUTE_CH57  0x8000     /* Mute Channel 57 */
+#define                nMUTE_CH57  0x0       
+#define                   TX_CH58  0x3f0000   /* Transmit Channel 58 */
+#define                 MUTE_CH58  0x800000   /* Mute Channel 58 */
+#define                nMUTE_CH58  0x0       
+#define                   TX_CH59  0x3f000000 /* Transmit Channel 59 */
+#define                 MUTE_CH59  0x80000000 /* Mute Channel 59 */
+#define                nMUTE_CH59  0x0       
+
+/* Bit masks for MXVR_BLOCK_CNT */
+
+#define                      BCNT  0xffff     /* Block Count */
+
+/* Bit masks for MXVR_CLK_CTL */
+
+#define                  MXTALCEN  0x1        /* MXVR Crystal Oscillator Clock Enable */
+#define                 nMXTALCEN  0x0       
+#define                  MXTALFEN  0x2        /* MXVR Crystal Oscillator Feedback Enable */
+#define                 nMXTALFEN  0x0       
+#define                  MXTALMUL  0x30       /* MXVR Crystal Multiplier */
+#define                  CLKX3SEL  0x80       /* Clock Generation Source Select */
+#define                 nCLKX3SEL  0x0       
+#define                   MMCLKEN  0x100      /* Master Clock Enable */
+#define                  nMMCLKEN  0x0       
+#define                  MMCLKMUL  0x1e00     /* Master Clock Multiplication Factor */
+#define                   PLLSMPS  0xe000     /* MXVR PLL State Machine Prescaler */
+#define                   MBCLKEN  0x10000    /* Bit Clock Enable */
+#define                  nMBCLKEN  0x0       
+#define                  MBCLKDIV  0x1e0000   /* Bit Clock Divide Factor */
+#define                     INVRX  0x800000   /* Invert Receive Data */
+#define                    nINVRX  0x0       
+#define                     MFSEN  0x1000000  /* Frame Sync Enable */
+#define                    nMFSEN  0x0       
+#define                    MFSDIV  0x1e000000 /* Frame Sync Divide Factor */
+#define                    MFSSEL  0x60000000 /* Frame Sync Select */
+#define                   MFSSYNC  0x80000000 /* Frame Sync Synchronization Select */
+#define                  nMFSSYNC  0x0       
+
+/* Bit masks for MXVR_CDRPLL_CTL */
+
+#define                   CDRSMEN  0x1        /* MXVR CDRPLL State Machine Enable */
+#define                  nCDRSMEN  0x0       
+#define                   CDRRSTB  0x2        /* MXVR CDRPLL Reset */
+#define                  nCDRRSTB  0x0       
+#define                   CDRSVCO  0x4        /* MXVR CDRPLL Start VCO */
+#define                  nCDRSVCO  0x0       
+#define                   CDRMODE  0x8        /* MXVR CDRPLL CDR Mode Select */
+#define                  nCDRMODE  0x0       
+#define                   CDRSCNT  0x3f0      /* MXVR CDRPLL Start Counter */
+#define                   CDRLCNT  0xfc00     /* MXVR CDRPLL Lock Counter */
+#define                 CDRSHPSEL  0x3f0000   /* MXVR CDRPLL Shaper Select */
+#define                  CDRSHPEN  0x800000   /* MXVR CDRPLL Shaper Enable */
+#define                 nCDRSHPEN  0x0       
+#define                  CDRCPSEL  0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
+
+/* Bit masks for MXVR_FMPLL_CTL */
+
+#define                    FMSMEN  0x1        /* MXVR FMPLL State Machine Enable */
+#define                   nFMSMEN  0x0       
+#define                    FMRSTB  0x2        /* MXVR FMPLL Reset */
+#define                   nFMRSTB  0x0       
+#define                    FMSVCO  0x4        /* MXVR FMPLL Start VCO */
+#define                   nFMSVCO  0x0       
+#define                    FMSCNT  0x3f0      /* MXVR FMPLL Start Counter */
+#define                    FMLCNT  0xfc00     /* MXVR FMPLL Lock Counter */
+#define                   FMCPSEL  0xff000000 /* MXVR FMPLL Charge Pump Current Select */
+
+/* Bit masks for MXVR_PIN_CTL */
+
+#define                  MTXONBOD  0x1        /* MTXONB Open Drain Select */
+#define                 nMTXONBOD  0x0       
+#define                   MTXONBG  0x2        /* MTXONB Gates MTX Select */
+#define                  nMTXONBG  0x0       
+#define                     MFSOE  0x10       /* MFS Output Enable */
+#define                    nMFSOE  0x0       
+#define                  MFSGPSEL  0x20       /* MFS General Purpose Output Select */
+#define                 nMFSGPSEL  0x0       
+#define                  MFSGPDAT  0x40       /* MFS General Purpose Output Data */
+#define                 nMFSGPDAT  0x0       
+
+/* Bit masks for MXVR_SCLK_CNT */
+
+#define                      SCNT  0xffff     /* System Clock Count */
+
+/* Bit masks for KPAD_CTL */
+
+#define                   KPAD_EN  0x1        /* Keypad Enable */
+#define                  nKPAD_EN  0x0       
+#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
+#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
+#define                KPAD_COLEN  0xe000     /* Column Enable Width */
+
+/* Bit masks for KPAD_PRESCALE */
+
+#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
+
+/* Bit masks for KPAD_MSEL */
+
+#define                DBON_SCALE  0xff       /* Debounce Scale Value */
+#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
+
+/* Bit masks for KPAD_ROWCOL */
+
+#define                  KPAD_ROW  0xff       /* Rows Pressed */
+#define                  KPAD_COL  0xff00     /* Columns Pressed */
+
+/* Bit masks for KPAD_STAT */
+
+#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
+#define                 nKPAD_IRQ  0x0       
+#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
+#define              KPAD_PRESSED  0x8        /* Key press current status */
+#define             nKPAD_PRESSED  0x0       
+
+/* Bit masks for KPAD_SOFTEVAL */
+
+#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
+#define          nKPAD_SOFTEVAL_E  0x0       
+
+/* Bit masks for SDH_COMMAND */
+
+#define                   CMD_IDX  0x3f       /* Command Index */
+#define                   CMD_RSP  0x40       /* Response */
+#define                  nCMD_RSP  0x0       
+#define                 CMD_L_RSP  0x80       /* Long Response */
+#define                nCMD_L_RSP  0x0       
+#define                 CMD_INT_E  0x100      /* Command Interrupt */
+#define                nCMD_INT_E  0x0       
+#define                CMD_PEND_E  0x200      /* Command Pending */
+#define               nCMD_PEND_E  0x0       
+#define                     CMD_E  0x400      /* Command Enable */
+#define                    nCMD_E  0x0       
+
+/* Bit masks for SDH_PWR_CTL */
+
+#define                    PWR_ON  0x3        /* Power On */
+#if 0
+#define                       TBD  0x3c       /* TBD */
+#endif
+#define                 SD_CMD_OD  0x40       /* Open Drain Output */
+#define                nSD_CMD_OD  0x0       
+#define                   ROD_CTL  0x80       /* Rod Control */
+#define                  nROD_CTL  0x0       
+
+/* Bit masks for SDH_CLK_CTL */
+
+#define                    CLKDIV  0xff       /* MC_CLK Divisor */
+#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
+#define                    nCLK_E  0x0       
+#define                  PWR_SV_E  0x200      /* Power Save Enable */
+#define                 nPWR_SV_E  0x0       
+#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
+#define            nCLKDIV_BYPASS  0x0       
+#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
+#define                 nWIDE_BUS  0x0       
+
+/* Bit masks for SDH_RESP_CMD */
+
+#define                  RESP_CMD  0x3f       /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+
+#define                     DTX_E  0x1        /* Data Transfer Enable */
+#define                    nDTX_E  0x0       
+#define                   DTX_DIR  0x2        /* Data Transfer Direction */
+#define                  nDTX_DIR  0x0       
+#define                  DTX_MODE  0x4        /* Data Transfer Mode */
+#define                 nDTX_MODE  0x0       
+#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
+#define                nDTX_DMA_E  0x0       
+#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+
+#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
+#define             nCMD_CRC_FAIL  0x0       
+#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
+#define             nDAT_CRC_FAIL  0x0       
+#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
+#define              nCMD_TIMEOUT  0x0       
+#define               DAT_TIMEOUT  0x8        /* Data Time Out */
+#define              nDAT_TIMEOUT  0x0       
+#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
+#define              nTX_UNDERRUN  0x0       
+#define                RX_OVERRUN  0x20       /* Receive Overrun */
+#define               nRX_OVERRUN  0x0       
+#define              CMD_RESP_END  0x40       /* CMD Response End */
+#define             nCMD_RESP_END  0x0       
+#define                  CMD_SENT  0x80       /* CMD Sent */
+#define                 nCMD_SENT  0x0       
+#define                   DAT_END  0x100      /* Data End */
+#define                  nDAT_END  0x0       
+#define             START_BIT_ERR  0x200      /* Start Bit Error */
+#define            nSTART_BIT_ERR  0x0       
+#define               DAT_BLK_END  0x400      /* Data Block End */
+#define              nDAT_BLK_END  0x0       
+#define                   CMD_ACT  0x800      /* CMD Active */
+#define                  nCMD_ACT  0x0       
+#define                    TX_ACT  0x1000     /* Transmit Active */
+#define                   nTX_ACT  0x0       
+#define                    RX_ACT  0x2000     /* Receive Active */
+#define                   nRX_ACT  0x0       
+#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
+#define             nTX_FIFO_STAT  0x0       
+#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
+#define             nRX_FIFO_STAT  0x0       
+#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
+#define             nTX_FIFO_FULL  0x0       
+#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
+#define             nRX_FIFO_FULL  0x0       
+#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
+#define             nTX_FIFO_ZERO  0x0       
+#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
+#define              nRX_DAT_ZERO  0x0       
+#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
+#define               nTX_DAT_RDY  0x0       
+#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
+#define              nRX_FIFO_RDY  0x0       
+
+/* Bit masks for SDH_STATUS_CLR */
+
+#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
+#define        nCMD_CRC_FAIL_STAT  0x0       
+#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
+#define        nDAT_CRC_FAIL_STAT  0x0       
+#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
+#define         nCMD_TIMEOUT_STAT  0x0       
+#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
+#define         nDAT_TIMEOUT_STAT  0x0       
+#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
+#define         nTX_UNDERRUN_STAT  0x0       
+#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
+#define          nRX_OVERRUN_STAT  0x0       
+#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
+#define        nCMD_RESP_END_STAT  0x0       
+#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
+#define            nCMD_SENT_STAT  0x0       
+#define              DAT_END_STAT  0x100      /* Data End Status */
+#define             nDAT_END_STAT  0x0       
+#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
+#define       nSTART_BIT_ERR_STAT  0x0       
+#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
+#define         nDAT_BLK_END_STAT  0x0       
+
+/* Bit masks for SDH_MASK0 */
+
+#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
+#define        nCMD_CRC_FAIL_MASK  0x0       
+#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
+#define        nDAT_CRC_FAIL_MASK  0x0       
+#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
+#define         nCMD_TIMEOUT_MASK  0x0       
+#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
+#define         nDAT_TIMEOUT_MASK  0x0       
+#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
+#define         nTX_UNDERRUN_MASK  0x0       
+#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
+#define          nRX_OVERRUN_MASK  0x0       
+#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
+#define        nCMD_RESP_END_MASK  0x0       
+#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
+#define            nCMD_SENT_MASK  0x0       
+#define              DAT_END_MASK  0x100      /* Data End Mask */
+#define             nDAT_END_MASK  0x0       
+#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
+#define       nSTART_BIT_ERR_MASK  0x0       
+#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
+#define         nDAT_BLK_END_MASK  0x0       
+#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
+#define             nCMD_ACT_MASK  0x0       
+#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
+#define              nTX_ACT_MASK  0x0       
+#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
+#define              nRX_ACT_MASK  0x0       
+#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
+#define        nTX_FIFO_STAT_MASK  0x0       
+#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
+#define        nRX_FIFO_STAT_MASK  0x0       
+#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
+#define        nTX_FIFO_FULL_MASK  0x0       
+#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
+#define        nRX_FIFO_FULL_MASK  0x0       
+#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
+#define        nTX_FIFO_ZERO_MASK  0x0       
+#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
+#define         nRX_DAT_ZERO_MASK  0x0       
+#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
+#define          nTX_DAT_RDY_MASK  0x0       
+#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
+#define         nRX_FIFO_RDY_MASK  0x0       
+
+/* Bit masks for SDH_FIFO_CNT */
+
+#define                FIFO_COUNT  0x7fff     /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+
+#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
+#define             nSDIO_INT_DET  0x0       
+#define               SD_CARD_DET  0x10       /* SD Card Detect */
+#define              nSD_CARD_DET  0x0       
+
+/* Bit masks for SDH_E_MASK */
+
+#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
+#define                 nSDIO_MSK  0x0       
+#define                   SCD_MSK  0x40       /* Mask Card Detect */
+#define                  nSCD_MSK  0x0       
+
+/* Bit masks for SDH_CFG */
+
+#define                   CLKS_EN  0x1        /* Clocks Enable */
+#define                  nCLKS_EN  0x0       
+#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
+#define                     nSD4E  0x0       
+#define                       MWE  0x8        /* Moving Window Enable */
+#define                      nMWE  0x0       
+#define                    SD_RST  0x10       /* SDMMC Reset */
+#define                   nSD_RST  0x0       
+#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
+#define                nPUP_SDDAT  0x0       
+#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
+#define               nPUP_SDDAT3  0x0       
+#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
+#define                nPD_SDDAT3  0x0       
+
+/* Bit masks for SDH_RD_WAIT_EN */
+
+#define                       RWR  0x1        /* Read Wait Request */
+#define                      nRWR  0x0       
+
+/* Bit masks for ATAPI_CONTROL */
+
+#define                 PIO_START  0x1        /* Start PIO/Reg Op */
+#define                nPIO_START  0x0       
+#define               MULTI_START  0x2        /* Start Multi-DMA Op */
+#define              nMULTI_START  0x0       
+#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
+#define              nULTRA_START  0x0       
+#define                  XFER_DIR  0x8        /* Transfer Direction */
+#define                 nXFER_DIR  0x0       
+#define                  IORDY_EN  0x10       /* IORDY Enable */
+#define                 nIORDY_EN  0x0       
+#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
+#define               nFIFO_FLUSH  0x0       
+#define                  SOFT_RST  0x40       /* Soft Reset */
+#define                 nSOFT_RST  0x0       
+#define                   DEV_RST  0x80       /* Device Reset */
+#define                  nDEV_RST  0x0       
+#define                TFRCNT_RST  0x100      /* Trans Count Reset */
+#define               nTFRCNT_RST  0x0       
+#define               END_ON_TERM  0x200      /* End/Terminate Select */
+#define              nEND_ON_TERM  0x0       
+#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
+#define              nPIO_USE_DMA  0x0       
+#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+
+#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
+#define              nPIO_XFER_ON  0x0       
+#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
+#define            nMULTI_XFER_ON  0x0       
+#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
+#define            nULTRA_XFER_ON  0x0       
+#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+
+#define                  DEV_ADDR  0x1f       /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+
+#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
+#define       nATAPI_DEV_INT_MASK  0x0       
+#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
+#define            nPIO_DONE_MASK  0x0       
+#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
+#define          nMULTI_DONE_MASK  0x0       
+#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
+#define         nUDMAIN_DONE_MASK  0x0       
+#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
+#define        nUDMAOUT_DONE_MASK  0x0       
+#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
+#define      nHOST_TERM_XFER_MASK  0x0       
+#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
+#define          nMULTI_TERM_MASK  0x0       
+#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define         nUDMAIN_TERM_MASK  0x0       
+#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
+#define        nUDMAOUT_TERM_MASK  0x0       
+
+/* Bit masks for ATAPI_INT_STATUS */
+
+#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
+#define            nATAPI_DEV_INT  0x0       
+#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
+#define             nPIO_DONE_INT  0x0       
+#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
+#define           nMULTI_DONE_INT  0x0       
+#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
+#define          nUDMAIN_DONE_INT  0x0       
+#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
+#define         nUDMAOUT_DONE_INT  0x0       
+#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
+#define       nHOST_TERM_XFER_INT  0x0       
+#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
+#define           nMULTI_TERM_INT  0x0       
+#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define          nUDMAIN_TERM_INT  0x0       
+#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
+#define         nUDMAOUT_TERM_INT  0x0       
+
+/* Bit masks for ATAPI_LINE_STATUS */
+
+#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
+#define               nATAPI_INTR  0x0       
+#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
+#define               nATAPI_DASP  0x0       
+#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
+#define               nATAPI_CS0N  0x0       
+#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
+#define               nATAPI_CS1N  0x0       
+#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
+#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
+#define             nATAPI_DMAREQ  0x0       
+#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
+#define            nATAPI_DMAACKN  0x0       
+#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
+#define              nATAPI_DIOWN  0x0       
+#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
+#define              nATAPI_DIORN  0x0       
+#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
+#define              nATAPI_IORDY  0x0       
+
+/* Bit masks for ATAPI_SM_STATE */
+
+#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
+#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
+#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
+#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+
+#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
+#define          nATAPI_HOST_TERM  0x0       
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+
+#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
+#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+
+#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
+#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
+#define                    T4_REG  0xf000     /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+
+#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+
+#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
+#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+
+#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
+#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+
+#define                        TH  0xff       /* Selects DIOW data hold */
+#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+
+#define                      TACK  0xff       /* Selects setup and hold times for TACK */
+#define                      TENV  0xff00     /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+
+#define                      TDVS  0xff       /* Selects data valid setup time */
+#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+
+#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define                      TMLI  0xff00     /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+
+#define                      TZAH  0xff       /* Selects minimum delay required for output */
+#define               READY_PAUSE  0xff00     /* Selects ready to pause */
+
+/* Bit masks for TIMER_ENABLE1 */
+
+#define                    TIMEN8  0x1        /* Timer 8 Enable */
+#define                   nTIMEN8  0x0       
+#define                    TIMEN9  0x2        /* Timer 9 Enable */
+#define                   nTIMEN9  0x0       
+#define                   TIMEN10  0x4        /* Timer 10 Enable */
+#define                  nTIMEN10  0x0       
+
+/* Bit masks for TIMER_DISABLE1 */
+
+#define                   TIMDIS8  0x1        /* Timer 8 Disable */
+#define                  nTIMDIS8  0x0       
+#define                   TIMDIS9  0x2        /* Timer 9 Disable */
+#define                  nTIMDIS9  0x0       
+#define                  TIMDIS10  0x4        /* Timer 10 Disable */
+#define                 nTIMDIS10  0x0       
+
+/* Bit masks for TIMER_STATUS1 */
+
+#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
+#define                   nTIMIL8  0x0       
+#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
+#define                   nTIMIL9  0x0       
+#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
+#define                  nTIMIL10  0x0       
+#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
+#define                nTOVF_ERR8  0x0       
+#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
+#define                nTOVF_ERR9  0x0       
+#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
+#define               nTOVF_ERR10  0x0       
+#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
+#define                    nTRUN8  0x0       
+#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
+#define                    nTRUN9  0x0       
+#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
+#define                   nTRUN10  0x0       
+
+/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
+
+/* Bit masks for USB_FADDR */
+
+#define          FUNCTION_ADDRESS  0x7f       /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
+#define          nENABLE_SUSPENDM  0x0       
+#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
+#define             nSUSPEND_MODE  0x0       
+#define               RESUME_MODE  0x4        /* DMA Mode */
+#define              nRESUME_MODE  0x0       
+#define                     RESET  0x8        /* Reset indicator */
+#define                    nRESET  0x0       
+#define                   HS_MODE  0x10       /* High Speed mode indicator */
+#define                  nHS_MODE  0x0       
+#define                 HS_ENABLE  0x20       /* high Speed Enable */
+#define                nHS_ENABLE  0x0       
+#define                 SOFT_CONN  0x40       /* Soft connect */
+#define                nSOFT_CONN  0x0       
+#define                ISO_UPDATE  0x80       /* Isochronous update */
+#define               nISO_UPDATE  0x0       
+
+/* Bit masks for USB_INTRTX */
+
+#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
+#define                   nEP0_TX  0x0       
+#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
+#define                   nEP1_TX  0x0       
+#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
+#define                   nEP2_TX  0x0       
+#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
+#define                   nEP3_TX  0x0       
+#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
+#define                   nEP4_TX  0x0       
+#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
+#define                   nEP5_TX  0x0       
+#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
+#define                   nEP6_TX  0x0       
+#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
+#define                   nEP7_TX  0x0       
+
+/* Bit masks for USB_INTRRX */
+
+#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
+#define                   nEP1_RX  0x0       
+#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
+#define                   nEP2_RX  0x0       
+#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
+#define                   nEP3_RX  0x0       
+#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
+#define                   nEP4_RX  0x0       
+#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
+#define                   nEP5_RX  0x0       
+#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
+#define                   nEP6_RX  0x0       
+#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
+#define                   nEP7_RX  0x0       
+
+/* Bit masks for USB_INTRTXE */
+
+#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
+#define                 nEP0_TX_E  0x0       
+#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
+#define                 nEP1_TX_E  0x0       
+#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
+#define                 nEP2_TX_E  0x0       
+#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
+#define                 nEP3_TX_E  0x0       
+#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
+#define                 nEP4_TX_E  0x0       
+#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
+#define                 nEP5_TX_E  0x0       
+#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
+#define                 nEP6_TX_E  0x0       
+#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
+#define                 nEP7_TX_E  0x0       
+
+/* Bit masks for USB_INTRRXE */
+
+#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
+#define                 nEP1_RX_E  0x0       
+#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
+#define                 nEP2_RX_E  0x0       
+#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
+#define                 nEP3_RX_E  0x0       
+#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
+#define                 nEP4_RX_E  0x0       
+#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
+#define                 nEP5_RX_E  0x0       
+#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
+#define                 nEP6_RX_E  0x0       
+#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
+#define                 nEP7_RX_E  0x0       
+
+/* Bit masks for USB_INTRUSB */
+
+#define                 SUSPEND_B  0x1        /* Suspend indicator */
+#define                nSUSPEND_B  0x0       
+#define                  RESUME_B  0x2        /* Resume indicator */
+#define                 nRESUME_B  0x0       
+#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
+#define         nRESET_OR_BABLE_B  0x0       
+#define                     SOF_B  0x8        /* Start of frame */
+#define                    nSOF_B  0x0       
+#define                    CONN_B  0x10       /* Connection indicator */
+#define                   nCONN_B  0x0       
+#define                  DISCON_B  0x20       /* Disconnect indicator */
+#define                 nDISCON_B  0x0       
+#define             SESSION_REQ_B  0x40       /* Session Request */
+#define            nSESSION_REQ_B  0x0       
+#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
+#define             nVBUS_ERROR_B  0x0       
+
+/* Bit masks for USB_INTRUSBE */
+
+#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
+#define               nSUSPEND_BE  0x0       
+#define                 RESUME_BE  0x2        /* Resume indicator int enable */
+#define                nRESUME_BE  0x0       
+#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
+#define        nRESET_OR_BABLE_BE  0x0       
+#define                    SOF_BE  0x8        /* Start of frame int enable */
+#define                   nSOF_BE  0x0       
+#define                   CONN_BE  0x10       /* Connection indicator int enable */
+#define                  nCONN_BE  0x0       
+#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
+#define                nDISCON_BE  0x0       
+#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
+#define           nSESSION_REQ_BE  0x0       
+#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
+#define            nVBUS_ERROR_BE  0x0       
+
+/* Bit masks for USB_FRAME */
+
+#define              FRAME_NUMBER  0x7ff      /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define                GLOBAL_ENA  0x1        /* enables USB module */
+#define               nGLOBAL_ENA  0x0       
+#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
+#define               nEP1_TX_ENA  0x0       
+#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
+#define               nEP2_TX_ENA  0x0       
+#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
+#define               nEP3_TX_ENA  0x0       
+#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
+#define               nEP4_TX_ENA  0x0       
+#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
+#define               nEP5_TX_ENA  0x0       
+#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
+#define               nEP6_TX_ENA  0x0       
+#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
+#define               nEP7_TX_ENA  0x0       
+#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
+#define               nEP1_RX_ENA  0x0       
+#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
+#define               nEP2_RX_ENA  0x0       
+#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
+#define               nEP3_RX_ENA  0x0       
+#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
+#define               nEP4_RX_ENA  0x0       
+#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
+#define               nEP5_RX_ENA  0x0       
+#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
+#define               nEP6_RX_ENA  0x0       
+#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
+#define               nEP7_RX_ENA  0x0       
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define                   SESSION  0x1        /* session indicator */
+#define                  nSESSION  0x0       
+#define                  HOST_REQ  0x2        /* Host negotiation request */
+#define                 nHOST_REQ  0x0       
+#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
+#define                nHOST_MODE  0x0       
+#define                     VBUS0  0x8        /* Vbus level indicator[0] */
+#define                    nVBUS0  0x0       
+#define                     VBUS1  0x10       /* Vbus level indicator[1] */
+#define                    nVBUS1  0x0       
+#define                     LSDEV  0x20       /* Low-speed indicator */
+#define                    nLSDEV  0x0       
+#define                     FSDEV  0x40       /* Full or High-speed indicator */
+#define                    nFSDEV  0x0       
+#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
+#define                 nB_DEVICE  0x0       
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
+#define            nDRIVE_VBUS_ON  0x0       
+#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
+#define           nDRIVE_VBUS_OFF  0x0       
+#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
+#define          nCHRG_VBUS_START  0x0       
+#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
+#define            nCHRG_VBUS_END  0x0       
+#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
+#define       nDISCHRG_VBUS_START  0x0       
+#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
+#define         nDISCHRG_VBUS_END  0x0       
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
+#define        nDRIVE_VBUS_ON_ENA  0x0       
+#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
+#define       nDRIVE_VBUS_OFF_ENA  0x0       
+#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
+#define      nCHRG_VBUS_START_ENA  0x0       
+#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
+#define        nCHRG_VBUS_END_ENA  0x0       
+#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
+#define   nDISCHRG_VBUS_START_ENA  0x0       
+#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
+#define     nDISCHRG_VBUS_END_ENA  0x0       
+
+/* Bit masks for USB_CSR0 */
+
+#define                  RXPKTRDY  0x1        /* data packet receive indicator */
+#define                 nRXPKTRDY  0x0       
+#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
+#define                 nTXPKTRDY  0x0       
+#define                STALL_SENT  0x4        /* STALL handshake sent */
+#define               nSTALL_SENT  0x0       
+#define                   DATAEND  0x8        /* Data end indicator */
+#define                  nDATAEND  0x0       
+#define                  SETUPEND  0x10       /* Setup end */
+#define                 nSETUPEND  0x0       
+#define                 SENDSTALL  0x20       /* Send STALL handshake */
+#define                nSENDSTALL  0x0       
+#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
+#define        nSERVICED_RXPKTRDY  0x0       
+#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
+#define        nSERVICED_SETUPEND  0x0       
+#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
+#define                nFLUSHFIFO  0x0       
+#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
+#define         nSTALL_RECEIVED_H  0x0       
+#define                SETUPPKT_H  0x8        /* send Setup token host mode */
+#define               nSETUPPKT_H  0x0       
+#define                   ERROR_H  0x10       /* timeout error indicator host mode */
+#define                  nERROR_H  0x0       
+#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
+#define                 nREQPKT_H  0x0       
+#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
+#define              nSTATUSPKT_H  0x0       
+#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
+#define            nNAK_TIMEOUT_H  0x0       
+
+/* Bit masks for USB_COUNT0 */
+
+#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
+#define               nTXPKTRDY_T  0x0       
+#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
+#define         nFIFO_NOT_EMPTY_T  0x0       
+#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
+#define               nUNDERRUN_T  0x0       
+#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
+#define              nFLUSHFIFO_T  0x0       
+#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
+#define             nSTALL_SEND_T  0x0       
+#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
+#define             nSTALL_SENT_T  0x0       
+#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
+#define       nCLEAR_DATATOGGLE_T  0x0       
+#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
+#define               nINCOMPTX_T  0x0       
+#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
+#define             nDMAREQMODE_T  0x0       
+#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
+#define       nFORCE_DATATOGGLE_T  0x0       
+#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
+#define             nDMAREQ_ENA_T  0x0       
+#define                     ISO_T  0x4000     /* enable Isochronous transfers */
+#define                    nISO_T  0x0       
+#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
+#define                nAUTOSET_T  0x0       
+#define                  ERROR_TH  0x4        /* error condition host mode */
+#define                 nERROR_TH  0x0       
+#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
+#define        nSTALL_RECEIVED_TH  0x0       
+#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
+#define           nNAK_TIMEOUT_TH  0x0       
+
+/* Bit masks for USB_TXCOUNT */
+
+#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
+#define               nRXPKTRDY_R  0x0       
+#define               FIFO_FULL_R  0x2        /* FIFO not empty */
+#define              nFIFO_FULL_R  0x0       
+#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
+#define                nOVERRUN_R  0x0       
+#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
+#define              nDATAERROR_R  0x0       
+#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
+#define              nFLUSHFIFO_R  0x0       
+#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
+#define             nSTALL_SEND_R  0x0       
+#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
+#define             nSTALL_SENT_R  0x0       
+#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
+#define       nCLEAR_DATATOGGLE_R  0x0       
+#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
+#define               nINCOMPRX_R  0x0       
+#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
+#define             nDMAREQMODE_R  0x0       
+#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
+#define                nDISNYET_R  0x0       
+#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
+#define             nDMAREQ_ENA_R  0x0       
+#define                     ISO_R  0x4000     /* enable Isochronous transfers */
+#define                    nISO_R  0x0       
+#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
+#define              nAUTOCLEAR_R  0x0       
+#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
+#define                 nERROR_RH  0x0       
+#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
+#define                nREQPKT_RH  0x0       
+#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
+#define        nSTALL_RECEIVED_RH  0x0       
+#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
+#define              nINCOMPRX_RH  0x0       
+#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
+#define            nDMAREQMODE_RH  0x0       
+#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
+#define               nAUTOREQ_RH  0x0       
+
+/* Bit masks for USB_RXCOUNT */
+
+#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define            TARGET_EP_NO_T  0xf        /* EP number */
+#define                PROTOCOL_T  0xc        /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define            TARGET_EP_NO_R  0xf        /* EP number */
+#define                PROTOCOL_R  0xc        /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
+#define                 nDMA0_INT  0x0       
+#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
+#define                 nDMA1_INT  0x0       
+#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
+#define                 nDMA2_INT  0x0       
+#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
+#define                 nDMA3_INT  0x0       
+#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
+#define                 nDMA4_INT  0x0       
+#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
+#define                 nDMA5_INT  0x0       
+#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
+#define                 nDMA6_INT  0x0       
+#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
+#define                 nDMA7_INT  0x0       
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define                   DMA_ENA  0x1        /* DMA enable */
+#define                  nDMA_ENA  0x0       
+#define                 DIRECTION  0x2        /* direction of DMA transfer */
+#define                nDIRECTION  0x0       
+#define                      MODE  0x4        /* DMA Bus error */
+#define                     nMODE  0x0       
+#define                   INT_ENA  0x8        /* Interrupt enable */
+#define                  nINT_ENA  0x0       
+#define                     EPNUM  0xf0       /* EP number */
+#define                  BUSERROR  0x100      /* DMA Bus error */
+#define                 nBUSERROR  0x0       
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for HMDMAx_CONTROL */
+
+#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
+#define                  nHMDMAEN  0x0       
+#define                       REP  0x2        /* Handshake MDMA Request Polarity */
+#define                      nREP  0x0       
+#define                       UTE  0x8        /* Urgency Threshold Enable */
+#define                      nUTE  0x0       
+#define                       OIE  0x10       /* Overflow Interrupt Enable */
+#define                      nOIE  0x0       
+#define                      BDIE  0x20       /* Block Done Interrupt Enable */
+#define                     nBDIE  0x0       
+#define                      MBDI  0x40       /* Mask Block Done Interrupt */
+#define                     nMBDI  0x0       
+#define                       DRQ  0x300      /* Handshake MDMA Request Type */
+#define                       RBC  0x1000     /* Force Reload of BCOUNT */
+#define                      nRBC  0x0       
+#define                        PS  0x2000     /* Pin Status */
+#define                       nPS  0x0       
+#define                        OI  0x4000     /* Overflow Interrupt Generated */
+#define                       nOI  0x0       
+#define                       BDI  0x8000     /* Block Done Interrupt Generated */
+#define                      nBDI  0x0       
+
+/* ******************************************* */
+/*     MULTI BIT MACRO ENUMERATIONS            */
+/* ******************************************* */
+
+/* ************************ */
+/*   MXVR Address Offsets   */
+/* ************************ */
+
+/* Control Message Receive Buffer (CMRB) Address Offsets */
+
+#define CMRB_STRIDE       0x00000016lu
+
+#define CMRB_DST_OFFSET   0x00000000lu
+#define CMRB_SRC_OFFSET   0x00000002lu
+#define CMRB_DATA_OFFSET  0x00000005lu
+
+/* Control Message Transmit Buffer (CMTB) Address Offsets */
+
+#define CMTB_PRIO_OFFSET    0x00000000lu
+#define CMTB_DST_OFFSET     0x00000002lu
+#define CMTB_SRC_OFFSET     0x00000004lu
+#define CMTB_TYPE_OFFSET    0x00000006lu
+#define CMTB_DATA_OFFSET    0x00000007lu
+
+#define CMTB_ANSWER_OFFSET  0x0000000Alu
+
+#define CMTB_STAT_N_OFFSET  0x00000018lu
+#define CMTB_STAT_A_OFFSET  0x00000016lu
+#define CMTB_STAT_D_OFFSET  0x0000000Elu
+#define CMTB_STAT_R_OFFSET  0x00000014lu
+#define CMTB_STAT_W_OFFSET  0x00000014lu
+#define CMTB_STAT_G_OFFSET  0x00000014lu
+
+/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
+
+#define APRB_STRIDE       0x00000400lu
+
+#define APRB_DST_OFFSET   0x00000000lu
+#define APRB_LEN_OFFSET   0x00000002lu
+#define APRB_SRC_OFFSET   0x00000004lu
+#define APRB_DATA_OFFSET  0x00000006lu
+
+/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
+
+#define APTB_PRIO_OFFSET  0x00000000lu
+#define APTB_DST_OFFSET   0x00000002lu
+#define APTB_LEN_OFFSET   0x00000004lu
+#define APTB_SRC_OFFSET   0x00000006lu
+#define APTB_DATA_OFFSET  0x00000008lu
+
+/* Remote Read Buffer (RRDB) Address Offsets */
+
+#define RRDB_WADDR_OFFSET 0x00000100lu
+#define RRDB_WLEN_OFFSET  0x00000101lu
+
+/* **************** */
+/*   MXVR Macros    */
+/* **************** */
+
+/* MXVR_CONFIG Macros */
+
+#define SET_MSB(x)       ( ( (x) & 0xF  ) << 9)
+
+/* MXVR_INT_STAT_1 Macros */
+
+#define DONEX(x)         (0x00000002 << (4 * (x)))
+#define HDONEX(x)        (0x00000001 << (4 * (x)))
+
+/* MXVR_INT_EN_1 Macros */
+
+#define DONEENX(x)       (0x00000002 << (4 * (x)))
+#define HDONEENX(x)      (0x00000001 << (4 * (x)))
+
+/* MXVR_CDRPLL_CTL Macros */
+
+#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
+
+/* MXVR_FMPLL_CTL Macros */
+
+#define SET_CDRCPSEL(x)  ( ( (x) & 0xFF ) << 24)
+#define SET_FMCPSEL(x)   ( ( (x) & 0xFF ) << 24)
+
+#endif /* _DEF_BF549_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
new file mode 100644
index 000000000000..a1b200fe6a1f
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -0,0 +1,4902 @@
+/*
+ * File:         include/asm-blackfin/mach-bf548/defBF54x_base.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF54X_H
+#define _DEF_BF54X_H
+
+
+/* ************************************************************** */
+/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
+/* ************************************************************** */
+
+/* PLL Registers */
+
+#define                          PLL_CTL  0xffc00000   /* PLL Control Register */
+#define                          PLL_DIV  0xffc00004   /* PLL Divisor Register */
+#define                           VR_CTL  0xffc00008   /* Voltage Regulator Control Register */
+#define                         PLL_STAT  0xffc0000c   /* PLL Status Register */
+#define                      PLL_LOCKCNT  0xffc00010   /* PLL Lock Count Register */
+
+/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
+
+#define                           CHIPID  0xffc00014   
+
+/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
+
+#define                            SWRST  0xffc00100   /* Software Reset Register */
+#define                            SYSCR  0xffc00104   /* System Configuration register */
+
+/* SIC Registers */
+
+#define                       SIC_IMASK0  0xffc0010c   /* System Interrupt Mask Register 0 */
+#define                       SIC_IMASK1  0xffc00110   /* System Interrupt Mask Register 1 */
+#define                       SIC_IMASK2  0xffc00114   /* System Interrupt Mask Register 2 */
+#define                         SIC_ISR0  0xffc00118   /* System Interrupt Status Register 0 */
+#define                         SIC_ISR1  0xffc0011c   /* System Interrupt Status Register 1 */
+#define                         SIC_ISR2  0xffc00120   /* System Interrupt Status Register 2 */
+#define                         SIC_IWR0  0xffc00124   /* System Interrupt Wakeup Register 0 */
+#define                         SIC_IWR1  0xffc00128   /* System Interrupt Wakeup Register 1 */
+#define                         SIC_IWR2  0xffc0012c   /* System Interrupt Wakeup Register 2 */
+#define                         SIC_IAR0  0xffc00130   /* System Interrupt Assignment Register 0 */
+#define                         SIC_IAR1  0xffc00134   /* System Interrupt Assignment Register 1 */
+#define                         SIC_IAR2  0xffc00138   /* System Interrupt Assignment Register 2 */
+#define                         SIC_IAR3  0xffc0013c   /* System Interrupt Assignment Register 3 */
+#define                         SIC_IAR4  0xffc00140   /* System Interrupt Assignment Register 4 */
+#define                         SIC_IAR5  0xffc00144   /* System Interrupt Assignment Register 5 */
+#define                         SIC_IAR6  0xffc00148   /* System Interrupt Assignment Register 6 */
+#define                         SIC_IAR7  0xffc0014c   /* System Interrupt Assignment Register 7 */
+#define                         SIC_IAR8  0xffc00150   /* System Interrupt Assignment Register 8 */
+#define                         SIC_IAR9  0xffc00154   /* System Interrupt Assignment Register 9 */
+#define                        SIC_IAR10  0xffc00158   /* System Interrupt Assignment Register 10 */
+#define                        SIC_IAR11  0xffc0015c   /* System Interrupt Assignment Register 11 */
+
+/* Watchdog Timer Registers */
+
+#define                         WDOG_CTL  0xffc00200   /* Watchdog Control Register */
+#define                         WDOG_CNT  0xffc00204   /* Watchdog Count Register */
+#define                        WDOG_STAT  0xffc00208   /* Watchdog Status Register */
+
+/* RTC Registers */
+
+#define                         RTC_STAT  0xffc00300   /* RTC Status Register */
+#define                         RTC_ICTL  0xffc00304   /* RTC Interrupt Control Register */
+#define                        RTC_ISTAT  0xffc00308   /* RTC Interrupt Status Register */
+#define                        RTC_SWCNT  0xffc0030c   /* RTC Stopwatch Count Register */
+#define                        RTC_ALARM  0xffc00310   /* RTC Alarm Register */
+#define                         RTC_PREN  0xffc00314   /* RTC Prescaler Enable Register */
+
+/* UART0 Registers */
+
+#define                        UART0_DLL  0xffc00400   /* Divisor Latch Low Byte */
+#define                        UART0_DLH  0xffc00404   /* Divisor Latch High Byte */
+#define                       UART0_GCTL  0xffc00408   /* Global Control Register */
+#define                        UART0_LCR  0xffc0040c   /* Line Control Register */
+#define                        UART0_MCR  0xffc00410   /* Modem Control Register */
+#define                        UART0_LSR  0xffc00414   /* Line Status Register */
+#define                        UART0_MSR  0xffc00418   /* Modem Status Register */
+#define                        UART0_SCR  0xffc0041c   /* Scratch Register */
+#define                    UART0_IER_SET  0xffc00420   /* Interrupt Enable Register Set */
+#define                  UART0_IER_CLEAR  0xffc00424   /* Interrupt Enable Register Clear */
+#define                        UART0_THR  0xffc00428   /* Transmit Hold Register */
+#define                        UART0_RBR  0xffc0042c   /* Receive Buffer Register */
+
+/* SPI0 Registers */
+
+#define                         SPI0_CTL  0xffc00500   /* SPI0 Control Register */
+#define                         SPI0_FLG  0xffc00504   /* SPI0 Flag Register */
+#define                        SPI0_STAT  0xffc00508   /* SPI0 Status Register */
+#define                        SPI0_TDBR  0xffc0050c   /* SPI0 Transmit Data Buffer Register */
+#define                        SPI0_RDBR  0xffc00510   /* SPI0 Receive Data Buffer Register */
+#define                        SPI0_BAUD  0xffc00514   /* SPI0 Baud Rate Register */
+#define                      SPI0_SHADOW  0xffc00518   /* SPI0 Receive Data Buffer Shadow Register */
+
+/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
+
+/* Two Wire Interface Registers (TWI0) */
+
+#define                      TWI0_CLKDIV  0xffc00700   /* Clock Divider Register */
+#define                     TWI0_CONTROL  0xffc00704   /* TWI Control Register */
+#define                  TWI0_SLAVE_CTRL  0xffc00708   /* TWI Slave Mode Control Register */
+#define                  TWI0_SLAVE_STAT  0xffc0070c   /* TWI Slave Mode Status Register */
+#define                  TWI0_SLAVE_ADDR  0xffc00710   /* TWI Slave Mode Address Register */
+#define                 TWI0_MASTER_CTRL  0xffc00714   /* TWI Master Mode Control Register */
+#define                 TWI0_MASTER_STAT  0xffc00718   /* TWI Master Mode Status Register */
+#define                 TWI0_MASTER_ADDR  0xffc0071c   /* TWI Master Mode Address Register */
+#define                    TWI0_INT_STAT  0xffc00720   /* TWI Interrupt Status Register */
+#define                    TWI0_INT_MASK  0xffc00724   /* TWI Interrupt Mask Register */
+#define                   TWI0_FIFO_CTRL  0xffc00728   /* TWI FIFO Control Register */
+#define                   TWI0_FIFO_STAT  0xffc0072c   /* TWI FIFO Status Register */
+#define                   TWI0_XMT_DATA8  0xffc00780   /* TWI FIFO Transmit Data Single Byte Register */
+#define                  TWI0_XMT_DATA16  0xffc00784   /* TWI FIFO Transmit Data Double Byte Register */
+#define                   TWI0_RCV_DATA8  0xffc00788   /* TWI FIFO Receive Data Single Byte Register */
+#define                  TWI0_RCV_DATA16  0xffc0078c   /* TWI FIFO Receive Data Double Byte Register */
+
+/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
+
+/* SPORT1 Registers */
+
+#define                      SPORT1_TCR1  0xffc00900   /* SPORT1 Transmit Configuration 1 Register */
+#define                      SPORT1_TCR2  0xffc00904   /* SPORT1 Transmit Configuration 2 Register */
+#define                   SPORT1_TCLKDIV  0xffc00908   /* SPORT1 Transmit Serial Clock Divider Register */
+#define                    SPORT1_TFSDIV  0xffc0090c   /* SPORT1 Transmit Frame Sync Divider Register */
+#define                        SPORT1_TX  0xffc00910   /* SPORT1 Transmit Data Register */
+#define                        SPORT1_RX  0xffc00918   /* SPORT1 Receive Data Register */
+#define                      SPORT1_RCR1  0xffc00920   /* SPORT1 Receive Configuration 1 Register */
+#define                      SPORT1_RCR2  0xffc00924   /* SPORT1 Receive Configuration 2 Register */
+#define                   SPORT1_RCLKDIV  0xffc00928   /* SPORT1 Receive Serial Clock Divider Register */
+#define                    SPORT1_RFSDIV  0xffc0092c   /* SPORT1 Receive Frame Sync Divider Register */
+#define                      SPORT1_STAT  0xffc00930   /* SPORT1 Status Register */
+#define                      SPORT1_CHNL  0xffc00934   /* SPORT1 Current Channel Register */
+#define                     SPORT1_MCMC1  0xffc00938   /* SPORT1 Multi channel Configuration Register 1 */
+#define                     SPORT1_MCMC2  0xffc0093c   /* SPORT1 Multi channel Configuration Register 2 */
+#define                     SPORT1_MTCS0  0xffc00940   /* SPORT1 Multi channel Transmit Select Register 0 */
+#define                     SPORT1_MTCS1  0xffc00944   /* SPORT1 Multi channel Transmit Select Register 1 */
+#define                     SPORT1_MTCS2  0xffc00948   /* SPORT1 Multi channel Transmit Select Register 2 */
+#define                     SPORT1_MTCS3  0xffc0094c   /* SPORT1 Multi channel Transmit Select Register 3 */
+#define                     SPORT1_MRCS0  0xffc00950   /* SPORT1 Multi channel Receive Select Register 0 */
+#define                     SPORT1_MRCS1  0xffc00954   /* SPORT1 Multi channel Receive Select Register 1 */
+#define                     SPORT1_MRCS2  0xffc00958   /* SPORT1 Multi channel Receive Select Register 2 */
+#define                     SPORT1_MRCS3  0xffc0095c   /* SPORT1 Multi channel Receive Select Register 3 */
+
+/* Asynchronous Memory Control Registers */
+
+#define                      EBIU_AMGCTL  0xffc00a00   /* Asynchronous Memory Global Control Register */
+#define                    EBIU_AMBCTL0   0xffc00a04   /* Asynchronous Memory Bank Control Register */
+#define                    EBIU_AMBCTL1   0xffc00a08   /* Asynchronous Memory Bank Control Register */
+#define                      EBIU_MBSCTL  0xffc00a0c   /* Asynchronous Memory Bank Select Control Register */
+#define                     EBIU_ARBSTAT  0xffc00a10   /* Asynchronous Memory Arbiter Status Register */
+#define                        EBIU_MODE  0xffc00a14   /* Asynchronous Mode Control Register */
+#define                        EBIU_FCTL  0xffc00a18   /* Asynchronous Memory Flash Control Register */
+
+/* DDR Memory Control Registers */
+
+#define                     EBIU_DDRCTL0  0xffc00a20   /* DDR Memory Control 0 Register */
+#define                     EBIU_DDRCTL1  0xffc00a24   /* DDR Memory Control 1 Register */
+#define                     EBIU_DDRCTL2  0xffc00a28   /* DDR Memory Control 2 Register */
+#define                     EBIU_DDRCTL3  0xffc00a2c   /* DDR Memory Control 3 Register */
+#define                      EBIU_DDRQUE  0xffc00a30   /* DDR Queue Configuration Register */
+#define                      EBIU_ERRADD  0xffc00a34   /* DDR Error Address Register */
+#define                      EBIU_ERRMST  0xffc00a38   /* DDR Error Master Register */
+#define                      EBIU_RSTCTL  0xffc00a3c   /* DDR Reset Control Register */
+
+/* DDR BankRead and Write Count Registers */
+
+#define                     EBIU_DDRBRC0  0xffc00a60   /* DDR Bank0 Read Count Register */
+#define                     EBIU_DDRBRC1  0xffc00a64   /* DDR Bank1 Read Count Register */
+#define                     EBIU_DDRBRC2  0xffc00a68   /* DDR Bank2 Read Count Register */
+#define                     EBIU_DDRBRC3  0xffc00a6c   /* DDR Bank3 Read Count Register */
+#define                     EBIU_DDRBRC4  0xffc00a70   /* DDR Bank4 Read Count Register */
+#define                     EBIU_DDRBRC5  0xffc00a74   /* DDR Bank5 Read Count Register */
+#define                     EBIU_DDRBRC6  0xffc00a78   /* DDR Bank6 Read Count Register */
+#define                     EBIU_DDRBRC7  0xffc00a7c   /* DDR Bank7 Read Count Register */
+#define                     EBIU_DDRBWC0  0xffc00a80   /* DDR Bank0 Write Count Register */
+#define                     EBIU_DDRBWC1  0xffc00a84   /* DDR Bank1 Write Count Register */
+#define                     EBIU_DDRBWC2  0xffc00a88   /* DDR Bank2 Write Count Register */
+#define                     EBIU_DDRBWC3  0xffc00a8c   /* DDR Bank3 Write Count Register */
+#define                     EBIU_DDRBWC4  0xffc00a90   /* DDR Bank4 Write Count Register */
+#define                     EBIU_DDRBWC5  0xffc00a94   /* DDR Bank5 Write Count Register */
+#define                     EBIU_DDRBWC6  0xffc00a98   /* DDR Bank6 Write Count Register */
+#define                     EBIU_DDRBWC7  0xffc00a9c   /* DDR Bank7 Write Count Register */
+#define                     EBIU_DDRACCT  0xffc00aa0   /* DDR Activation Count Register */
+#define                     EBIU_DDRTACT  0xffc00aa8   /* DDR Turn Around Count Register */
+#define                     EBIU_DDRARCT  0xffc00aac   /* DDR Auto-refresh Count Register */
+#define                      EBIU_DDRGC0  0xffc00ab0   /* DDR Grant Count 0 Register */
+#define                      EBIU_DDRGC1  0xffc00ab4   /* DDR Grant Count 1 Register */
+#define                      EBIU_DDRGC2  0xffc00ab8   /* DDR Grant Count 2 Register */
+#define                      EBIU_DDRGC3  0xffc00abc   /* DDR Grant Count 3 Register */
+#define                     EBIU_DDRMCEN  0xffc00ac0   /* DDR Metrics Counter Enable Register */
+#define                     EBIU_DDRMCCL  0xffc00ac4   /* DDR Metrics Counter Clear Register */
+
+/* DMAC0 Registers */
+
+#define                      DMAC0_TCPER  0xffc00b0c   /* DMA Controller 0 Traffic Control Periods Register */
+#define                      DMAC0_TCCNT  0xffc00b10   /* DMA Controller 0 Current Counts Register */
+
+/* DMA Channel 0 Registers */
+
+#define               DMA0_NEXT_DESC_PTR  0xffc00c00   /* DMA Channel 0 Next Descriptor Pointer Register */
+#define                  DMA0_START_ADDR  0xffc00c04   /* DMA Channel 0 Start Address Register */
+#define                      DMA0_CONFIG  0xffc00c08   /* DMA Channel 0 Configuration Register */
+#define                     DMA0_X_COUNT  0xffc00c10   /* DMA Channel 0 X Count Register */
+#define                    DMA0_X_MODIFY  0xffc00c14   /* DMA Channel 0 X Modify Register */
+#define                     DMA0_Y_COUNT  0xffc00c18   /* DMA Channel 0 Y Count Register */
+#define                    DMA0_Y_MODIFY  0xffc00c1c   /* DMA Channel 0 Y Modify Register */
+#define               DMA0_CURR_DESC_PTR  0xffc00c20   /* DMA Channel 0 Current Descriptor Pointer Register */
+#define                   DMA0_CURR_ADDR  0xffc00c24   /* DMA Channel 0 Current Address Register */
+#define                  DMA0_IRQ_STATUS  0xffc00c28   /* DMA Channel 0 Interrupt/Status Register */
+#define              DMA0_PERIPHERAL_MAP  0xffc00c2c   /* DMA Channel 0 Peripheral Map Register */
+#define                DMA0_CURR_X_COUNT  0xffc00c30   /* DMA Channel 0 Current X Count Register */
+#define                DMA0_CURR_Y_COUNT  0xffc00c38   /* DMA Channel 0 Current Y Count Register */
+
+/* DMA Channel 1 Registers */
+
+#define               DMA1_NEXT_DESC_PTR  0xffc00c40   /* DMA Channel 1 Next Descriptor Pointer Register */
+#define                  DMA1_START_ADDR  0xffc00c44   /* DMA Channel 1 Start Address Register */
+#define                      DMA1_CONFIG  0xffc00c48   /* DMA Channel 1 Configuration Register */
+#define                     DMA1_X_COUNT  0xffc00c50   /* DMA Channel 1 X Count Register */
+#define                    DMA1_X_MODIFY  0xffc00c54   /* DMA Channel 1 X Modify Register */
+#define                     DMA1_Y_COUNT  0xffc00c58   /* DMA Channel 1 Y Count Register */
+#define                    DMA1_Y_MODIFY  0xffc00c5c   /* DMA Channel 1 Y Modify Register */
+#define               DMA1_CURR_DESC_PTR  0xffc00c60   /* DMA Channel 1 Current Descriptor Pointer Register */
+#define                   DMA1_CURR_ADDR  0xffc00c64   /* DMA Channel 1 Current Address Register */
+#define                  DMA1_IRQ_STATUS  0xffc00c68   /* DMA Channel 1 Interrupt/Status Register */
+#define              DMA1_PERIPHERAL_MAP  0xffc00c6c   /* DMA Channel 1 Peripheral Map Register */
+#define                DMA1_CURR_X_COUNT  0xffc00c70   /* DMA Channel 1 Current X Count Register */
+#define                DMA1_CURR_Y_COUNT  0xffc00c78   /* DMA Channel 1 Current Y Count Register */
+
+/* DMA Channel 2 Registers */
+
+#define               DMA2_NEXT_DESC_PTR  0xffc00c80   /* DMA Channel 2 Next Descriptor Pointer Register */
+#define                  DMA2_START_ADDR  0xffc00c84   /* DMA Channel 2 Start Address Register */
+#define                      DMA2_CONFIG  0xffc00c88   /* DMA Channel 2 Configuration Register */
+#define                     DMA2_X_COUNT  0xffc00c90   /* DMA Channel 2 X Count Register */
+#define                    DMA2_X_MODIFY  0xffc00c94   /* DMA Channel 2 X Modify Register */
+#define                     DMA2_Y_COUNT  0xffc00c98   /* DMA Channel 2 Y Count Register */
+#define                    DMA2_Y_MODIFY  0xffc00c9c   /* DMA Channel 2 Y Modify Register */
+#define               DMA2_CURR_DESC_PTR  0xffc00ca0   /* DMA Channel 2 Current Descriptor Pointer Register */
+#define                   DMA2_CURR_ADDR  0xffc00ca4   /* DMA Channel 2 Current Address Register */
+#define                  DMA2_IRQ_STATUS  0xffc00ca8   /* DMA Channel 2 Interrupt/Status Register */
+#define              DMA2_PERIPHERAL_MAP  0xffc00cac   /* DMA Channel 2 Peripheral Map Register */
+#define                DMA2_CURR_X_COUNT  0xffc00cb0   /* DMA Channel 2 Current X Count Register */
+#define                DMA2_CURR_Y_COUNT  0xffc00cb8   /* DMA Channel 2 Current Y Count Register */
+
+/* DMA Channel 3 Registers */
+
+#define               DMA3_NEXT_DESC_PTR  0xffc00cc0   /* DMA Channel 3 Next Descriptor Pointer Register */
+#define                  DMA3_START_ADDR  0xffc00cc4   /* DMA Channel 3 Start Address Register */
+#define                      DMA3_CONFIG  0xffc00cc8   /* DMA Channel 3 Configuration Register */
+#define                     DMA3_X_COUNT  0xffc00cd0   /* DMA Channel 3 X Count Register */
+#define                    DMA3_X_MODIFY  0xffc00cd4   /* DMA Channel 3 X Modify Register */
+#define                     DMA3_Y_COUNT  0xffc00cd8   /* DMA Channel 3 Y Count Register */
+#define                    DMA3_Y_MODIFY  0xffc00cdc   /* DMA Channel 3 Y Modify Register */
+#define               DMA3_CURR_DESC_PTR  0xffc00ce0   /* DMA Channel 3 Current Descriptor Pointer Register */
+#define                   DMA3_CURR_ADDR  0xffc00ce4   /* DMA Channel 3 Current Address Register */
+#define                  DMA3_IRQ_STATUS  0xffc00ce8   /* DMA Channel 3 Interrupt/Status Register */
+#define              DMA3_PERIPHERAL_MAP  0xffc00cec   /* DMA Channel 3 Peripheral Map Register */
+#define                DMA3_CURR_X_COUNT  0xffc00cf0   /* DMA Channel 3 Current X Count Register */
+#define                DMA3_CURR_Y_COUNT  0xffc00cf8   /* DMA Channel 3 Current Y Count Register */
+
+/* DMA Channel 4 Registers */
+
+#define               DMA4_NEXT_DESC_PTR  0xffc00d00   /* DMA Channel 4 Next Descriptor Pointer Register */
+#define                  DMA4_START_ADDR  0xffc00d04   /* DMA Channel 4 Start Address Register */
+#define                      DMA4_CONFIG  0xffc00d08   /* DMA Channel 4 Configuration Register */
+#define                     DMA4_X_COUNT  0xffc00d10   /* DMA Channel 4 X Count Register */
+#define                    DMA4_X_MODIFY  0xffc00d14   /* DMA Channel 4 X Modify Register */
+#define                     DMA4_Y_COUNT  0xffc00d18   /* DMA Channel 4 Y Count Register */
+#define                    DMA4_Y_MODIFY  0xffc00d1c   /* DMA Channel 4 Y Modify Register */
+#define               DMA4_CURR_DESC_PTR  0xffc00d20   /* DMA Channel 4 Current Descriptor Pointer Register */
+#define                   DMA4_CURR_ADDR  0xffc00d24   /* DMA Channel 4 Current Address Register */
+#define                  DMA4_IRQ_STATUS  0xffc00d28   /* DMA Channel 4 Interrupt/Status Register */
+#define              DMA4_PERIPHERAL_MAP  0xffc00d2c   /* DMA Channel 4 Peripheral Map Register */
+#define                DMA4_CURR_X_COUNT  0xffc00d30   /* DMA Channel 4 Current X Count Register */
+#define                DMA4_CURR_Y_COUNT  0xffc00d38   /* DMA Channel 4 Current Y Count Register */
+
+/* DMA Channel 5 Registers */
+
+#define               DMA5_NEXT_DESC_PTR  0xffc00d40   /* DMA Channel 5 Next Descriptor Pointer Register */
+#define                  DMA5_START_ADDR  0xffc00d44   /* DMA Channel 5 Start Address Register */
+#define                      DMA5_CONFIG  0xffc00d48   /* DMA Channel 5 Configuration Register */
+#define                     DMA5_X_COUNT  0xffc00d50   /* DMA Channel 5 X Count Register */
+#define                    DMA5_X_MODIFY  0xffc00d54   /* DMA Channel 5 X Modify Register */
+#define                     DMA5_Y_COUNT  0xffc00d58   /* DMA Channel 5 Y Count Register */
+#define                    DMA5_Y_MODIFY  0xffc00d5c   /* DMA Channel 5 Y Modify Register */
+#define               DMA5_CURR_DESC_PTR  0xffc00d60   /* DMA Channel 5 Current Descriptor Pointer Register */
+#define                   DMA5_CURR_ADDR  0xffc00d64   /* DMA Channel 5 Current Address Register */
+#define                  DMA5_IRQ_STATUS  0xffc00d68   /* DMA Channel 5 Interrupt/Status Register */
+#define              DMA5_PERIPHERAL_MAP  0xffc00d6c   /* DMA Channel 5 Peripheral Map Register */
+#define                DMA5_CURR_X_COUNT  0xffc00d70   /* DMA Channel 5 Current X Count Register */
+#define                DMA5_CURR_Y_COUNT  0xffc00d78   /* DMA Channel 5 Current Y Count Register */
+
+/* DMA Channel 6 Registers */
+
+#define               DMA6_NEXT_DESC_PTR  0xffc00d80   /* DMA Channel 6 Next Descriptor Pointer Register */
+#define                  DMA6_START_ADDR  0xffc00d84   /* DMA Channel 6 Start Address Register */
+#define                      DMA6_CONFIG  0xffc00d88   /* DMA Channel 6 Configuration Register */
+#define                     DMA6_X_COUNT  0xffc00d90   /* DMA Channel 6 X Count Register */
+#define                    DMA6_X_MODIFY  0xffc00d94   /* DMA Channel 6 X Modify Register */
+#define                     DMA6_Y_COUNT  0xffc00d98   /* DMA Channel 6 Y Count Register */
+#define                    DMA6_Y_MODIFY  0xffc00d9c   /* DMA Channel 6 Y Modify Register */
+#define               DMA6_CURR_DESC_PTR  0xffc00da0   /* DMA Channel 6 Current Descriptor Pointer Register */
+#define                   DMA6_CURR_ADDR  0xffc00da4   /* DMA Channel 6 Current Address Register */
+#define                  DMA6_IRQ_STATUS  0xffc00da8   /* DMA Channel 6 Interrupt/Status Register */
+#define              DMA6_PERIPHERAL_MAP  0xffc00dac   /* DMA Channel 6 Peripheral Map Register */
+#define                DMA6_CURR_X_COUNT  0xffc00db0   /* DMA Channel 6 Current X Count Register */
+#define                DMA6_CURR_Y_COUNT  0xffc00db8   /* DMA Channel 6 Current Y Count Register */
+
+/* DMA Channel 7 Registers */
+
+#define               DMA7_NEXT_DESC_PTR  0xffc00dc0   /* DMA Channel 7 Next Descriptor Pointer Register */
+#define                  DMA7_START_ADDR  0xffc00dc4   /* DMA Channel 7 Start Address Register */
+#define                      DMA7_CONFIG  0xffc00dc8   /* DMA Channel 7 Configuration Register */
+#define                     DMA7_X_COUNT  0xffc00dd0   /* DMA Channel 7 X Count Register */
+#define                    DMA7_X_MODIFY  0xffc00dd4   /* DMA Channel 7 X Modify Register */
+#define                     DMA7_Y_COUNT  0xffc00dd8   /* DMA Channel 7 Y Count Register */
+#define                    DMA7_Y_MODIFY  0xffc00ddc   /* DMA Channel 7 Y Modify Register */
+#define               DMA7_CURR_DESC_PTR  0xffc00de0   /* DMA Channel 7 Current Descriptor Pointer Register */
+#define                   DMA7_CURR_ADDR  0xffc00de4   /* DMA Channel 7 Current Address Register */
+#define                  DMA7_IRQ_STATUS  0xffc00de8   /* DMA Channel 7 Interrupt/Status Register */
+#define              DMA7_PERIPHERAL_MAP  0xffc00dec   /* DMA Channel 7 Peripheral Map Register */
+#define                DMA7_CURR_X_COUNT  0xffc00df0   /* DMA Channel 7 Current X Count Register */
+#define                DMA7_CURR_Y_COUNT  0xffc00df8   /* DMA Channel 7 Current Y Count Register */
+
+/* DMA Channel 8 Registers */
+
+#define               DMA8_NEXT_DESC_PTR  0xffc00e00   /* DMA Channel 8 Next Descriptor Pointer Register */
+#define                  DMA8_START_ADDR  0xffc00e04   /* DMA Channel 8 Start Address Register */
+#define                      DMA8_CONFIG  0xffc00e08   /* DMA Channel 8 Configuration Register */
+#define                     DMA8_X_COUNT  0xffc00e10   /* DMA Channel 8 X Count Register */
+#define                    DMA8_X_MODIFY  0xffc00e14   /* DMA Channel 8 X Modify Register */
+#define                     DMA8_Y_COUNT  0xffc00e18   /* DMA Channel 8 Y Count Register */
+#define                    DMA8_Y_MODIFY  0xffc00e1c   /* DMA Channel 8 Y Modify Register */
+#define               DMA8_CURR_DESC_PTR  0xffc00e20   /* DMA Channel 8 Current Descriptor Pointer Register */
+#define                   DMA8_CURR_ADDR  0xffc00e24   /* DMA Channel 8 Current Address Register */
+#define                  DMA8_IRQ_STATUS  0xffc00e28   /* DMA Channel 8 Interrupt/Status Register */
+#define              DMA8_PERIPHERAL_MAP  0xffc00e2c   /* DMA Channel 8 Peripheral Map Register */
+#define                DMA8_CURR_X_COUNT  0xffc00e30   /* DMA Channel 8 Current X Count Register */
+#define                DMA8_CURR_Y_COUNT  0xffc00e38   /* DMA Channel 8 Current Y Count Register */
+
+/* DMA Channel 9 Registers */
+
+#define               DMA9_NEXT_DESC_PTR  0xffc00e40   /* DMA Channel 9 Next Descriptor Pointer Register */
+#define                  DMA9_START_ADDR  0xffc00e44   /* DMA Channel 9 Start Address Register */
+#define                      DMA9_CONFIG  0xffc00e48   /* DMA Channel 9 Configuration Register */
+#define                     DMA9_X_COUNT  0xffc00e50   /* DMA Channel 9 X Count Register */
+#define                    DMA9_X_MODIFY  0xffc00e54   /* DMA Channel 9 X Modify Register */
+#define                     DMA9_Y_COUNT  0xffc00e58   /* DMA Channel 9 Y Count Register */
+#define                    DMA9_Y_MODIFY  0xffc00e5c   /* DMA Channel 9 Y Modify Register */
+#define               DMA9_CURR_DESC_PTR  0xffc00e60   /* DMA Channel 9 Current Descriptor Pointer Register */
+#define                   DMA9_CURR_ADDR  0xffc00e64   /* DMA Channel 9 Current Address Register */
+#define                  DMA9_IRQ_STATUS  0xffc00e68   /* DMA Channel 9 Interrupt/Status Register */
+#define              DMA9_PERIPHERAL_MAP  0xffc00e6c   /* DMA Channel 9 Peripheral Map Register */
+#define                DMA9_CURR_X_COUNT  0xffc00e70   /* DMA Channel 9 Current X Count Register */
+#define                DMA9_CURR_Y_COUNT  0xffc00e78   /* DMA Channel 9 Current Y Count Register */
+
+/* DMA Channel 10 Registers */
+
+#define              DMA10_NEXT_DESC_PTR  0xffc00e80   /* DMA Channel 10 Next Descriptor Pointer Register */
+#define                 DMA10_START_ADDR  0xffc00e84   /* DMA Channel 10 Start Address Register */
+#define                     DMA10_CONFIG  0xffc00e88   /* DMA Channel 10 Configuration Register */
+#define                    DMA10_X_COUNT  0xffc00e90   /* DMA Channel 10 X Count Register */
+#define                   DMA10_X_MODIFY  0xffc00e94   /* DMA Channel 10 X Modify Register */
+#define                    DMA10_Y_COUNT  0xffc00e98   /* DMA Channel 10 Y Count Register */
+#define                   DMA10_Y_MODIFY  0xffc00e9c   /* DMA Channel 10 Y Modify Register */
+#define              DMA10_CURR_DESC_PTR  0xffc00ea0   /* DMA Channel 10 Current Descriptor Pointer Register */
+#define                  DMA10_CURR_ADDR  0xffc00ea4   /* DMA Channel 10 Current Address Register */
+#define                 DMA10_IRQ_STATUS  0xffc00ea8   /* DMA Channel 10 Interrupt/Status Register */
+#define             DMA10_PERIPHERAL_MAP  0xffc00eac   /* DMA Channel 10 Peripheral Map Register */
+#define               DMA10_CURR_X_COUNT  0xffc00eb0   /* DMA Channel 10 Current X Count Register */
+#define               DMA10_CURR_Y_COUNT  0xffc00eb8   /* DMA Channel 10 Current Y Count Register */
+
+/* DMA Channel 11 Registers */
+
+#define              DMA11_NEXT_DESC_PTR  0xffc00ec0   /* DMA Channel 11 Next Descriptor Pointer Register */
+#define                 DMA11_START_ADDR  0xffc00ec4   /* DMA Channel 11 Start Address Register */
+#define                     DMA11_CONFIG  0xffc00ec8   /* DMA Channel 11 Configuration Register */
+#define                    DMA11_X_COUNT  0xffc00ed0   /* DMA Channel 11 X Count Register */
+#define                   DMA11_X_MODIFY  0xffc00ed4   /* DMA Channel 11 X Modify Register */
+#define                    DMA11_Y_COUNT  0xffc00ed8   /* DMA Channel 11 Y Count Register */
+#define                   DMA11_Y_MODIFY  0xffc00edc   /* DMA Channel 11 Y Modify Register */
+#define              DMA11_CURR_DESC_PTR  0xffc00ee0   /* DMA Channel 11 Current Descriptor Pointer Register */
+#define                  DMA11_CURR_ADDR  0xffc00ee4   /* DMA Channel 11 Current Address Register */
+#define                 DMA11_IRQ_STATUS  0xffc00ee8   /* DMA Channel 11 Interrupt/Status Register */
+#define             DMA11_PERIPHERAL_MAP  0xffc00eec   /* DMA Channel 11 Peripheral Map Register */
+#define               DMA11_CURR_X_COUNT  0xffc00ef0   /* DMA Channel 11 Current X Count Register */
+#define               DMA11_CURR_Y_COUNT  0xffc00ef8   /* DMA Channel 11 Current Y Count Register */
+
+/* MDMA Stream 0 Registers */
+
+#define            MDMA_D0_NEXT_DESC_PTR  0xffc00f00   /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define               MDMA_D0_START_ADDR  0xffc00f04   /* Memory DMA Stream 0 Destination Start Address Register */
+#define                   MDMA_D0_CONFIG  0xffc00f08   /* Memory DMA Stream 0 Destination Configuration Register */
+#define                  MDMA_D0_X_COUNT  0xffc00f10   /* Memory DMA Stream 0 Destination X Count Register */
+#define                 MDMA_D0_X_MODIFY  0xffc00f14   /* Memory DMA Stream 0 Destination X Modify Register */
+#define                  MDMA_D0_Y_COUNT  0xffc00f18   /* Memory DMA Stream 0 Destination Y Count Register */
+#define                 MDMA_D0_Y_MODIFY  0xffc00f1c   /* Memory DMA Stream 0 Destination Y Modify Register */
+#define            MDMA_D0_CURR_DESC_PTR  0xffc00f20   /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define                MDMA_D0_CURR_ADDR  0xffc00f24   /* Memory DMA Stream 0 Destination Current Address Register */
+#define               MDMA_D0_IRQ_STATUS  0xffc00f28   /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define           MDMA_D0_PERIPHERAL_MAP  0xffc00f2c   /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define             MDMA_D0_CURR_X_COUNT  0xffc00f30   /* Memory DMA Stream 0 Destination Current X Count Register */
+#define             MDMA_D0_CURR_Y_COUNT  0xffc00f38   /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define            MDMA_S0_NEXT_DESC_PTR  0xffc00f40   /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define               MDMA_S0_START_ADDR  0xffc00f44   /* Memory DMA Stream 0 Source Start Address Register */
+#define                   MDMA_S0_CONFIG  0xffc00f48   /* Memory DMA Stream 0 Source Configuration Register */
+#define                  MDMA_S0_X_COUNT  0xffc00f50   /* Memory DMA Stream 0 Source X Count Register */
+#define                 MDMA_S0_X_MODIFY  0xffc00f54   /* Memory DMA Stream 0 Source X Modify Register */
+#define                  MDMA_S0_Y_COUNT  0xffc00f58   /* Memory DMA Stream 0 Source Y Count Register */
+#define                 MDMA_S0_Y_MODIFY  0xffc00f5c   /* Memory DMA Stream 0 Source Y Modify Register */
+#define            MDMA_S0_CURR_DESC_PTR  0xffc00f60   /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define                MDMA_S0_CURR_ADDR  0xffc00f64   /* Memory DMA Stream 0 Source Current Address Register */
+#define               MDMA_S0_IRQ_STATUS  0xffc00f68   /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define           MDMA_S0_PERIPHERAL_MAP  0xffc00f6c   /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define             MDMA_S0_CURR_X_COUNT  0xffc00f70   /* Memory DMA Stream 0 Source Current X Count Register */
+#define             MDMA_S0_CURR_Y_COUNT  0xffc00f78   /* Memory DMA Stream 0 Source Current Y Count Register */
+
+/* MDMA Stream 1 Registers */
+
+#define            MDMA_D1_NEXT_DESC_PTR  0xffc00f80   /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define               MDMA_D1_START_ADDR  0xffc00f84   /* Memory DMA Stream 1 Destination Start Address Register */
+#define                   MDMA_D1_CONFIG  0xffc00f88   /* Memory DMA Stream 1 Destination Configuration Register */
+#define                  MDMA_D1_X_COUNT  0xffc00f90   /* Memory DMA Stream 1 Destination X Count Register */
+#define                 MDMA_D1_X_MODIFY  0xffc00f94   /* Memory DMA Stream 1 Destination X Modify Register */
+#define                  MDMA_D1_Y_COUNT  0xffc00f98   /* Memory DMA Stream 1 Destination Y Count Register */
+#define                 MDMA_D1_Y_MODIFY  0xffc00f9c   /* Memory DMA Stream 1 Destination Y Modify Register */
+#define            MDMA_D1_CURR_DESC_PTR  0xffc00fa0   /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define                MDMA_D1_CURR_ADDR  0xffc00fa4   /* Memory DMA Stream 1 Destination Current Address Register */
+#define               MDMA_D1_IRQ_STATUS  0xffc00fa8   /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define           MDMA_D1_PERIPHERAL_MAP  0xffc00fac   /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define             MDMA_D1_CURR_X_COUNT  0xffc00fb0   /* Memory DMA Stream 1 Destination Current X Count Register */
+#define             MDMA_D1_CURR_Y_COUNT  0xffc00fb8   /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define            MDMA_S1_NEXT_DESC_PTR  0xffc00fc0   /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define               MDMA_S1_START_ADDR  0xffc00fc4   /* Memory DMA Stream 1 Source Start Address Register */
+#define                   MDMA_S1_CONFIG  0xffc00fc8   /* Memory DMA Stream 1 Source Configuration Register */
+#define                  MDMA_S1_X_COUNT  0xffc00fd0   /* Memory DMA Stream 1 Source X Count Register */
+#define                 MDMA_S1_X_MODIFY  0xffc00fd4   /* Memory DMA Stream 1 Source X Modify Register */
+#define                  MDMA_S1_Y_COUNT  0xffc00fd8   /* Memory DMA Stream 1 Source Y Count Register */
+#define                 MDMA_S1_Y_MODIFY  0xffc00fdc   /* Memory DMA Stream 1 Source Y Modify Register */
+#define            MDMA_S1_CURR_DESC_PTR  0xffc00fe0   /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define                MDMA_S1_CURR_ADDR  0xffc00fe4   /* Memory DMA Stream 1 Source Current Address Register */
+#define               MDMA_S1_IRQ_STATUS  0xffc00fe8   /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define           MDMA_S1_PERIPHERAL_MAP  0xffc00fec   /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define             MDMA_S1_CURR_X_COUNT  0xffc00ff0   /* Memory DMA Stream 1 Source Current X Count Register */
+#define             MDMA_S1_CURR_Y_COUNT  0xffc00ff8   /* Memory DMA Stream 1 Source Current Y Count Register */
+
+/* UART3 Registers */
+
+#define                        UART3_DLL  0xffc03100   /* Divisor Latch Low Byte */
+#define                        UART3_DLH  0xffc03104   /* Divisor Latch High Byte */
+#define                       UART3_GCTL  0xffc03108   /* Global Control Register */
+#define                        UART3_LCR  0xffc0310c   /* Line Control Register */
+#define                        UART3_MCR  0xffc03110   /* Modem Control Register */
+#define                        UART3_LSR  0xffc03114   /* Line Status Register */
+#define                        UART3_MSR  0xffc03118   /* Modem Status Register */
+#define                        UART3_SCR  0xffc0311c   /* Scratch Register */
+#define                    UART3_IER_SET  0xffc03120   /* Interrupt Enable Register Set */
+#define                  UART3_IER_CLEAR  0xffc03124   /* Interrupt Enable Register Clear */
+#define                        UART3_THR  0xffc03128   /* Transmit Hold Register */
+#define                        UART3_RBR  0xffc0312c   /* Receive Buffer Register */
+
+/* EPPI1 Registers */
+
+#define                     EPPI1_STATUS  0xffc01300   /* EPPI1 Status Register */
+#define                     EPPI1_HCOUNT  0xffc01304   /* EPPI1 Horizontal Transfer Count Register */
+#define                     EPPI1_HDELAY  0xffc01308   /* EPPI1 Horizontal Delay Count Register */
+#define                     EPPI1_VCOUNT  0xffc0130c   /* EPPI1 Vertical Transfer Count Register */
+#define                     EPPI1_VDELAY  0xffc01310   /* EPPI1 Vertical Delay Count Register */
+#define                      EPPI1_FRAME  0xffc01314   /* EPPI1 Lines per Frame Register */
+#define                       EPPI1_LINE  0xffc01318   /* EPPI1 Samples per Line Register */
+#define                     EPPI1_CLKDIV  0xffc0131c   /* EPPI1 Clock Divide Register */
+#define                    EPPI1_CONTROL  0xffc01320   /* EPPI1 Control Register */
+#define                   EPPI1_FS1W_HBL  0xffc01324   /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define                  EPPI1_FS1P_AVPL  0xffc01328   /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define                   EPPI1_FS2W_LVB  0xffc0132c   /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define                  EPPI1_FS2P_LAVF  0xffc01330   /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define                       EPPI1_CLIP  0xffc01334   /* EPPI1 Clipping Register */
+
+/* Port Interrupt 0 Registers (32-bit) */
+
+#define                   PINT0_MASK_SET  0xffc01400   /* Pin Interrupt 0 Mask Set Register */
+#define                 PINT0_MASK_CLEAR  0xffc01404   /* Pin Interrupt 0 Mask Clear Register */
+#define                    PINT0_REQUEST  0xffc01408   /* Pin Interrupt 0 Interrupt Request Register */
+#define                     PINT0_ASSIGN  0xffc0140c   /* Pin Interrupt 0 Port Assign Register */
+#define                   PINT0_EDGE_SET  0xffc01410   /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define                 PINT0_EDGE_CLEAR  0xffc01414   /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define                 PINT0_INVERT_SET  0xffc01418   /* Pin Interrupt 0 Inversion Set Register */
+#define               PINT0_INVERT_CLEAR  0xffc0141c   /* Pin Interrupt 0 Inversion Clear Register */
+#define                   PINT0_PINSTATE  0xffc01420   /* Pin Interrupt 0 Pin Status Register */
+#define                      PINT0_LATCH  0xffc01424   /* Pin Interrupt 0 Latch Register */
+
+/* Port Interrupt 1 Registers (32-bit) */
+
+#define                   PINT1_MASK_SET  0xffc01430   /* Pin Interrupt 1 Mask Set Register */
+#define                 PINT1_MASK_CLEAR  0xffc01434   /* Pin Interrupt 1 Mask Clear Register */
+#define                    PINT1_REQUEST  0xffc01438   /* Pin Interrupt 1 Interrupt Request Register */
+#define                     PINT1_ASSIGN  0xffc0143c   /* Pin Interrupt 1 Port Assign Register */
+#define                   PINT1_EDGE_SET  0xffc01440   /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define                 PINT1_EDGE_CLEAR  0xffc01444   /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define                 PINT1_INVERT_SET  0xffc01448   /* Pin Interrupt 1 Inversion Set Register */
+#define               PINT1_INVERT_CLEAR  0xffc0144c   /* Pin Interrupt 1 Inversion Clear Register */
+#define                   PINT1_PINSTATE  0xffc01450   /* Pin Interrupt 1 Pin Status Register */
+#define                      PINT1_LATCH  0xffc01454   /* Pin Interrupt 1 Latch Register */
+
+/* Port Interrupt 2 Registers (32-bit) */
+
+#define                   PINT2_MASK_SET  0xffc01460   /* Pin Interrupt 2 Mask Set Register */
+#define                 PINT2_MASK_CLEAR  0xffc01464   /* Pin Interrupt 2 Mask Clear Register */
+#define                    PINT2_REQUEST  0xffc01468   /* Pin Interrupt 2 Interrupt Request Register */
+#define                     PINT2_ASSIGN  0xffc0146c   /* Pin Interrupt 2 Port Assign Register */
+#define                   PINT2_EDGE_SET  0xffc01470   /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define                 PINT2_EDGE_CLEAR  0xffc01474   /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define                 PINT2_INVERT_SET  0xffc01478   /* Pin Interrupt 2 Inversion Set Register */
+#define               PINT2_INVERT_CLEAR  0xffc0147c   /* Pin Interrupt 2 Inversion Clear Register */
+#define                   PINT2_PINSTATE  0xffc01480   /* Pin Interrupt 2 Pin Status Register */
+#define                      PINT2_LATCH  0xffc01484   /* Pin Interrupt 2 Latch Register */
+
+/* Port Interrupt 3 Registers (32-bit) */
+
+#define                   PINT3_MASK_SET  0xffc01490   /* Pin Interrupt 3 Mask Set Register */
+#define                 PINT3_MASK_CLEAR  0xffc01494   /* Pin Interrupt 3 Mask Clear Register */
+#define                    PINT3_REQUEST  0xffc01498   /* Pin Interrupt 3 Interrupt Request Register */
+#define                     PINT3_ASSIGN  0xffc0149c   /* Pin Interrupt 3 Port Assign Register */
+#define                   PINT3_EDGE_SET  0xffc014a0   /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define                 PINT3_EDGE_CLEAR  0xffc014a4   /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define                 PINT3_INVERT_SET  0xffc014a8   /* Pin Interrupt 3 Inversion Set Register */
+#define               PINT3_INVERT_CLEAR  0xffc014ac   /* Pin Interrupt 3 Inversion Clear Register */
+#define                   PINT3_PINSTATE  0xffc014b0   /* Pin Interrupt 3 Pin Status Register */
+#define                      PINT3_LATCH  0xffc014b4   /* Pin Interrupt 3 Latch Register */
+
+/* Port A Registers */
+
+#define                        PORTA_FER  0xffc014c0   /* Function Enable Register */
+#define                            PORTA  0xffc014c4   /* GPIO Data Register */
+#define                        PORTA_SET  0xffc014c8   /* GPIO Data Set Register */
+#define                      PORTA_CLEAR  0xffc014cc   /* GPIO Data Clear Register */
+#define                    PORTA_DIR_SET  0xffc014d0   /* GPIO Direction Set Register */
+#define                  PORTA_DIR_CLEAR  0xffc014d4   /* GPIO Direction Clear Register */
+#define                       PORTA_INEN  0xffc014d8   /* GPIO Input Enable Register */
+#define                        PORTA_MUX  0xffc014dc   /* Multiplexer Control Register */
+
+/* Port B Registers */
+
+#define                        PORTB_FER  0xffc014e0   /* Function Enable Register */
+#define                            PORTB  0xffc014e4   /* GPIO Data Register */
+#define                        PORTB_SET  0xffc014e8   /* GPIO Data Set Register */
+#define                      PORTB_CLEAR  0xffc014ec   /* GPIO Data Clear Register */
+#define                    PORTB_DIR_SET  0xffc014f0   /* GPIO Direction Set Register */
+#define                  PORTB_DIR_CLEAR  0xffc014f4   /* GPIO Direction Clear Register */
+#define                       PORTB_INEN  0xffc014f8   /* GPIO Input Enable Register */
+#define                        PORTB_MUX  0xffc014fc   /* Multiplexer Control Register */
+
+/* Port C Registers */
+
+#define                        PORTC_FER  0xffc01500   /* Function Enable Register */
+#define                            PORTC  0xffc01504   /* GPIO Data Register */
+#define                        PORTC_SET  0xffc01508   /* GPIO Data Set Register */
+#define                      PORTC_CLEAR  0xffc0150c   /* GPIO Data Clear Register */
+#define                    PORTC_DIR_SET  0xffc01510   /* GPIO Direction Set Register */
+#define                  PORTC_DIR_CLEAR  0xffc01514   /* GPIO Direction Clear Register */
+#define                       PORTC_INEN  0xffc01518   /* GPIO Input Enable Register */
+#define                        PORTC_MUX  0xffc0151c   /* Multiplexer Control Register */
+
+/* Port D Registers */
+
+#define                        PORTD_FER  0xffc01520   /* Function Enable Register */
+#define                            PORTD  0xffc01524   /* GPIO Data Register */
+#define                        PORTD_SET  0xffc01528   /* GPIO Data Set Register */
+#define                      PORTD_CLEAR  0xffc0152c   /* GPIO Data Clear Register */
+#define                    PORTD_DIR_SET  0xffc01530   /* GPIO Direction Set Register */
+#define                  PORTD_DIR_CLEAR  0xffc01534   /* GPIO Direction Clear Register */
+#define                       PORTD_INEN  0xffc01538   /* GPIO Input Enable Register */
+#define                        PORTD_MUX  0xffc0153c   /* Multiplexer Control Register */
+
+/* Port E Registers */
+
+#define                        PORTE_FER  0xffc01540   /* Function Enable Register */
+#define                            PORTE  0xffc01544   /* GPIO Data Register */
+#define                        PORTE_SET  0xffc01548   /* GPIO Data Set Register */
+#define                      PORTE_CLEAR  0xffc0154c   /* GPIO Data Clear Register */
+#define                    PORTE_DIR_SET  0xffc01550   /* GPIO Direction Set Register */
+#define                  PORTE_DIR_CLEAR  0xffc01554   /* GPIO Direction Clear Register */
+#define                       PORTE_INEN  0xffc01558   /* GPIO Input Enable Register */
+#define                        PORTE_MUX  0xffc0155c   /* Multiplexer Control Register */
+
+/* Port F Registers */
+
+#define                        PORTF_FER  0xffc01560   /* Function Enable Register */
+#define                            PORTF  0xffc01564   /* GPIO Data Register */
+#define                        PORTF_SET  0xffc01568   /* GPIO Data Set Register */
+#define                      PORTF_CLEAR  0xffc0156c   /* GPIO Data Clear Register */
+#define                    PORTF_DIR_SET  0xffc01570   /* GPIO Direction Set Register */
+#define                  PORTF_DIR_CLEAR  0xffc01574   /* GPIO Direction Clear Register */
+#define                       PORTF_INEN  0xffc01578   /* GPIO Input Enable Register */
+#define                        PORTF_MUX  0xffc0157c   /* Multiplexer Control Register */
+
+/* Port G Registers */
+
+#define                        PORTG_FER  0xffc01580   /* Function Enable Register */
+#define                            PORTG  0xffc01584   /* GPIO Data Register */
+#define                        PORTG_SET  0xffc01588   /* GPIO Data Set Register */
+#define                      PORTG_CLEAR  0xffc0158c   /* GPIO Data Clear Register */
+#define                    PORTG_DIR_SET  0xffc01590   /* GPIO Direction Set Register */
+#define                  PORTG_DIR_CLEAR  0xffc01594   /* GPIO Direction Clear Register */
+#define                       PORTG_INEN  0xffc01598   /* GPIO Input Enable Register */
+#define                        PORTG_MUX  0xffc0159c   /* Multiplexer Control Register */
+
+/* Port H Registers */
+
+#define                        PORTH_FER  0xffc015a0   /* Function Enable Register */
+#define                            PORTH  0xffc015a4   /* GPIO Data Register */
+#define                        PORTH_SET  0xffc015a8   /* GPIO Data Set Register */
+#define                      PORTH_CLEAR  0xffc015ac   /* GPIO Data Clear Register */
+#define                    PORTH_DIR_SET  0xffc015b0   /* GPIO Direction Set Register */
+#define                  PORTH_DIR_CLEAR  0xffc015b4   /* GPIO Direction Clear Register */
+#define                       PORTH_INEN  0xffc015b8   /* GPIO Input Enable Register */
+#define                        PORTH_MUX  0xffc015bc   /* Multiplexer Control Register */
+
+/* Port I Registers */
+
+#define                        PORTI_FER  0xffc015c0   /* Function Enable Register */
+#define                            PORTI  0xffc015c4   /* GPIO Data Register */
+#define                        PORTI_SET  0xffc015c8   /* GPIO Data Set Register */
+#define                      PORTI_CLEAR  0xffc015cc   /* GPIO Data Clear Register */
+#define                    PORTI_DIR_SET  0xffc015d0   /* GPIO Direction Set Register */
+#define                  PORTI_DIR_CLEAR  0xffc015d4   /* GPIO Direction Clear Register */
+#define                       PORTI_INEN  0xffc015d8   /* GPIO Input Enable Register */
+#define                        PORTI_MUX  0xffc015dc   /* Multiplexer Control Register */
+
+/* Port J Registers */
+
+#define                        PORTJ_FER  0xffc015e0   /* Function Enable Register */
+#define                            PORTJ  0xffc015e4   /* GPIO Data Register */
+#define                        PORTJ_SET  0xffc015e8   /* GPIO Data Set Register */
+#define                      PORTJ_CLEAR  0xffc015ec   /* GPIO Data Clear Register */
+#define                    PORTJ_DIR_SET  0xffc015f0   /* GPIO Direction Set Register */
+#define                  PORTJ_DIR_CLEAR  0xffc015f4   /* GPIO Direction Clear Register */
+#define                       PORTJ_INEN  0xffc015f8   /* GPIO Input Enable Register */
+#define                        PORTJ_MUX  0xffc015fc   /* Multiplexer Control Register */
+
+/* PWM Timer Registers */
+
+#define                    TIMER0_CONFIG  0xffc01600   /* Timer 0 Configuration Register */
+#define                   TIMER0_COUNTER  0xffc01604   /* Timer 0 Counter Register */
+#define                    TIMER0_PERIOD  0xffc01608   /* Timer 0 Period Register */
+#define                     TIMER0_WIDTH  0xffc0160c   /* Timer 0 Width Register */
+#define                    TIMER1_CONFIG  0xffc01610   /* Timer 1 Configuration Register */
+#define                   TIMER1_COUNTER  0xffc01614   /* Timer 1 Counter Register */
+#define                    TIMER1_PERIOD  0xffc01618   /* Timer 1 Period Register */
+#define                     TIMER1_WIDTH  0xffc0161c   /* Timer 1 Width Register */
+#define                    TIMER2_CONFIG  0xffc01620   /* Timer 2 Configuration Register */
+#define                   TIMER2_COUNTER  0xffc01624   /* Timer 2 Counter Register */
+#define                    TIMER2_PERIOD  0xffc01628   /* Timer 2 Period Register */
+#define                     TIMER2_WIDTH  0xffc0162c   /* Timer 2 Width Register */
+#define                    TIMER3_CONFIG  0xffc01630   /* Timer 3 Configuration Register */
+#define                   TIMER3_COUNTER  0xffc01634   /* Timer 3 Counter Register */
+#define                    TIMER3_PERIOD  0xffc01638   /* Timer 3 Period Register */
+#define                     TIMER3_WIDTH  0xffc0163c   /* Timer 3 Width Register */
+#define                    TIMER4_CONFIG  0xffc01640   /* Timer 4 Configuration Register */
+#define                   TIMER4_COUNTER  0xffc01644   /* Timer 4 Counter Register */
+#define                    TIMER4_PERIOD  0xffc01648   /* Timer 4 Period Register */
+#define                     TIMER4_WIDTH  0xffc0164c   /* Timer 4 Width Register */
+#define                    TIMER5_CONFIG  0xffc01650   /* Timer 5 Configuration Register */
+#define                   TIMER5_COUNTER  0xffc01654   /* Timer 5 Counter Register */
+#define                    TIMER5_PERIOD  0xffc01658   /* Timer 5 Period Register */
+#define                     TIMER5_WIDTH  0xffc0165c   /* Timer 5 Width Register */
+#define                    TIMER6_CONFIG  0xffc01660   /* Timer 6 Configuration Register */
+#define                   TIMER6_COUNTER  0xffc01664   /* Timer 6 Counter Register */
+#define                    TIMER6_PERIOD  0xffc01668   /* Timer 6 Period Register */
+#define                     TIMER6_WIDTH  0xffc0166c   /* Timer 6 Width Register */
+#define                    TIMER7_CONFIG  0xffc01670   /* Timer 7 Configuration Register */
+#define                   TIMER7_COUNTER  0xffc01674   /* Timer 7 Counter Register */
+#define                    TIMER7_PERIOD  0xffc01678   /* Timer 7 Period Register */
+#define                     TIMER7_WIDTH  0xffc0167c   /* Timer 7 Width Register */
+
+/* Timer Group of 8 */
+
+#define                    TIMER_ENABLE0  0xffc01680   /* Timer Group of 8 Enable Register */
+#define                   TIMER_DISABLE0  0xffc01684   /* Timer Group of 8 Disable Register */
+#define                    TIMER_STATUS0  0xffc01688   /* Timer Group of 8 Status Register */
+
+/* DMAC1 Registers */
+
+#define                      DMAC1_TCPER  0xffc01b0c   /* DMA Controller 1 Traffic Control Periods Register */
+#define                      DMAC1_TCCNT  0xffc01b10   /* DMA Controller 1 Current Counts Register */
+
+/* DMA Channel 12 Registers */
+
+#define              DMA12_NEXT_DESC_PTR  0xffc01c00   /* DMA Channel 12 Next Descriptor Pointer Register */
+#define                 DMA12_START_ADDR  0xffc01c04   /* DMA Channel 12 Start Address Register */
+#define                     DMA12_CONFIG  0xffc01c08   /* DMA Channel 12 Configuration Register */
+#define                    DMA12_X_COUNT  0xffc01c10   /* DMA Channel 12 X Count Register */
+#define                   DMA12_X_MODIFY  0xffc01c14   /* DMA Channel 12 X Modify Register */
+#define                    DMA12_Y_COUNT  0xffc01c18   /* DMA Channel 12 Y Count Register */
+#define                   DMA12_Y_MODIFY  0xffc01c1c   /* DMA Channel 12 Y Modify Register */
+#define              DMA12_CURR_DESC_PTR  0xffc01c20   /* DMA Channel 12 Current Descriptor Pointer Register */
+#define                  DMA12_CURR_ADDR  0xffc01c24   /* DMA Channel 12 Current Address Register */
+#define                 DMA12_IRQ_STATUS  0xffc01c28   /* DMA Channel 12 Interrupt/Status Register */
+#define             DMA12_PERIPHERAL_MAP  0xffc01c2c   /* DMA Channel 12 Peripheral Map Register */
+#define               DMA12_CURR_X_COUNT  0xffc01c30   /* DMA Channel 12 Current X Count Register */
+#define               DMA12_CURR_Y_COUNT  0xffc01c38   /* DMA Channel 12 Current Y Count Register */
+
+/* DMA Channel 13 Registers */
+
+#define              DMA13_NEXT_DESC_PTR  0xffc01c40   /* DMA Channel 13 Next Descriptor Pointer Register */
+#define                 DMA13_START_ADDR  0xffc01c44   /* DMA Channel 13 Start Address Register */
+#define                     DMA13_CONFIG  0xffc01c48   /* DMA Channel 13 Configuration Register */
+#define                    DMA13_X_COUNT  0xffc01c50   /* DMA Channel 13 X Count Register */
+#define                   DMA13_X_MODIFY  0xffc01c54   /* DMA Channel 13 X Modify Register */
+#define                    DMA13_Y_COUNT  0xffc01c58   /* DMA Channel 13 Y Count Register */
+#define                   DMA13_Y_MODIFY  0xffc01c5c   /* DMA Channel 13 Y Modify Register */
+#define              DMA13_CURR_DESC_PTR  0xffc01c60   /* DMA Channel 13 Current Descriptor Pointer Register */
+#define                  DMA13_CURR_ADDR  0xffc01c64   /* DMA Channel 13 Current Address Register */
+#define                 DMA13_IRQ_STATUS  0xffc01c68   /* DMA Channel 13 Interrupt/Status Register */
+#define             DMA13_PERIPHERAL_MAP  0xffc01c6c   /* DMA Channel 13 Peripheral Map Register */
+#define               DMA13_CURR_X_COUNT  0xffc01c70   /* DMA Channel 13 Current X Count Register */
+#define               DMA13_CURR_Y_COUNT  0xffc01c78   /* DMA Channel 13 Current Y Count Register */
+
+/* DMA Channel 14 Registers */
+
+#define              DMA14_NEXT_DESC_PTR  0xffc01c80   /* DMA Channel 14 Next Descriptor Pointer Register */
+#define                 DMA14_START_ADDR  0xffc01c84   /* DMA Channel 14 Start Address Register */
+#define                     DMA14_CONFIG  0xffc01c88   /* DMA Channel 14 Configuration Register */
+#define                    DMA14_X_COUNT  0xffc01c90   /* DMA Channel 14 X Count Register */
+#define                   DMA14_X_MODIFY  0xffc01c94   /* DMA Channel 14 X Modify Register */
+#define                    DMA14_Y_COUNT  0xffc01c98   /* DMA Channel 14 Y Count Register */
+#define                   DMA14_Y_MODIFY  0xffc01c9c   /* DMA Channel 14 Y Modify Register */
+#define              DMA14_CURR_DESC_PTR  0xffc01ca0   /* DMA Channel 14 Current Descriptor Pointer Register */
+#define                  DMA14_CURR_ADDR  0xffc01ca4   /* DMA Channel 14 Current Address Register */
+#define                 DMA14_IRQ_STATUS  0xffc01ca8   /* DMA Channel 14 Interrupt/Status Register */
+#define             DMA14_PERIPHERAL_MAP  0xffc01cac   /* DMA Channel 14 Peripheral Map Register */
+#define               DMA14_CURR_X_COUNT  0xffc01cb0   /* DMA Channel 14 Current X Count Register */
+#define               DMA14_CURR_Y_COUNT  0xffc01cb8   /* DMA Channel 14 Current Y Count Register */
+
+/* DMA Channel 15 Registers */
+
+#define              DMA15_NEXT_DESC_PTR  0xffc01cc0   /* DMA Channel 15 Next Descriptor Pointer Register */
+#define                 DMA15_START_ADDR  0xffc01cc4   /* DMA Channel 15 Start Address Register */
+#define                     DMA15_CONFIG  0xffc01cc8   /* DMA Channel 15 Configuration Register */
+#define                    DMA15_X_COUNT  0xffc01cd0   /* DMA Channel 15 X Count Register */
+#define                   DMA15_X_MODIFY  0xffc01cd4   /* DMA Channel 15 X Modify Register */
+#define                    DMA15_Y_COUNT  0xffc01cd8   /* DMA Channel 15 Y Count Register */
+#define                   DMA15_Y_MODIFY  0xffc01cdc   /* DMA Channel 15 Y Modify Register */
+#define              DMA15_CURR_DESC_PTR  0xffc01ce0   /* DMA Channel 15 Current Descriptor Pointer Register */
+#define                  DMA15_CURR_ADDR  0xffc01ce4   /* DMA Channel 15 Current Address Register */
+#define                 DMA15_IRQ_STATUS  0xffc01ce8   /* DMA Channel 15 Interrupt/Status Register */
+#define             DMA15_PERIPHERAL_MAP  0xffc01cec   /* DMA Channel 15 Peripheral Map Register */
+#define               DMA15_CURR_X_COUNT  0xffc01cf0   /* DMA Channel 15 Current X Count Register */
+#define               DMA15_CURR_Y_COUNT  0xffc01cf8   /* DMA Channel 15 Current Y Count Register */
+
+/* DMA Channel 16 Registers */
+
+#define              DMA16_NEXT_DESC_PTR  0xffc01d00   /* DMA Channel 16 Next Descriptor Pointer Register */
+#define                 DMA16_START_ADDR  0xffc01d04   /* DMA Channel 16 Start Address Register */
+#define                     DMA16_CONFIG  0xffc01d08   /* DMA Channel 16 Configuration Register */
+#define                    DMA16_X_COUNT  0xffc01d10   /* DMA Channel 16 X Count Register */
+#define                   DMA16_X_MODIFY  0xffc01d14   /* DMA Channel 16 X Modify Register */
+#define                    DMA16_Y_COUNT  0xffc01d18   /* DMA Channel 16 Y Count Register */
+#define                   DMA16_Y_MODIFY  0xffc01d1c   /* DMA Channel 16 Y Modify Register */
+#define              DMA16_CURR_DESC_PTR  0xffc01d20   /* DMA Channel 16 Current Descriptor Pointer Register */
+#define                  DMA16_CURR_ADDR  0xffc01d24   /* DMA Channel 16 Current Address Register */
+#define                 DMA16_IRQ_STATUS  0xffc01d28   /* DMA Channel 16 Interrupt/Status Register */
+#define             DMA16_PERIPHERAL_MAP  0xffc01d2c   /* DMA Channel 16 Peripheral Map Register */
+#define               DMA16_CURR_X_COUNT  0xffc01d30   /* DMA Channel 16 Current X Count Register */
+#define               DMA16_CURR_Y_COUNT  0xffc01d38   /* DMA Channel 16 Current Y Count Register */
+
+/* DMA Channel 17 Registers */
+
+#define              DMA17_NEXT_DESC_PTR  0xffc01d40   /* DMA Channel 17 Next Descriptor Pointer Register */
+#define                 DMA17_START_ADDR  0xffc01d44   /* DMA Channel 17 Start Address Register */
+#define                     DMA17_CONFIG  0xffc01d48   /* DMA Channel 17 Configuration Register */
+#define                    DMA17_X_COUNT  0xffc01d50   /* DMA Channel 17 X Count Register */
+#define                   DMA17_X_MODIFY  0xffc01d54   /* DMA Channel 17 X Modify Register */
+#define                    DMA17_Y_COUNT  0xffc01d58   /* DMA Channel 17 Y Count Register */
+#define                   DMA17_Y_MODIFY  0xffc01d5c   /* DMA Channel 17 Y Modify Register */
+#define              DMA17_CURR_DESC_PTR  0xffc01d60   /* DMA Channel 17 Current Descriptor Pointer Register */
+#define                  DMA17_CURR_ADDR  0xffc01d64   /* DMA Channel 17 Current Address Register */
+#define                 DMA17_IRQ_STATUS  0xffc01d68   /* DMA Channel 17 Interrupt/Status Register */
+#define             DMA17_PERIPHERAL_MAP  0xffc01d6c   /* DMA Channel 17 Peripheral Map Register */
+#define               DMA17_CURR_X_COUNT  0xffc01d70   /* DMA Channel 17 Current X Count Register */
+#define               DMA17_CURR_Y_COUNT  0xffc01d78   /* DMA Channel 17 Current Y Count Register */
+
+/* DMA Channel 18 Registers */
+
+#define              DMA18_NEXT_DESC_PTR  0xffc01d80   /* DMA Channel 18 Next Descriptor Pointer Register */
+#define                 DMA18_START_ADDR  0xffc01d84   /* DMA Channel 18 Start Address Register */
+#define                     DMA18_CONFIG  0xffc01d88   /* DMA Channel 18 Configuration Register */
+#define                    DMA18_X_COUNT  0xffc01d90   /* DMA Channel 18 X Count Register */
+#define                   DMA18_X_MODIFY  0xffc01d94   /* DMA Channel 18 X Modify Register */
+#define                    DMA18_Y_COUNT  0xffc01d98   /* DMA Channel 18 Y Count Register */
+#define                   DMA18_Y_MODIFY  0xffc01d9c   /* DMA Channel 18 Y Modify Register */
+#define              DMA18_CURR_DESC_PTR  0xffc01da0   /* DMA Channel 18 Current Descriptor Pointer Register */
+#define                  DMA18_CURR_ADDR  0xffc01da4   /* DMA Channel 18 Current Address Register */
+#define                 DMA18_IRQ_STATUS  0xffc01da8   /* DMA Channel 18 Interrupt/Status Register */
+#define             DMA18_PERIPHERAL_MAP  0xffc01dac   /* DMA Channel 18 Peripheral Map Register */
+#define               DMA18_CURR_X_COUNT  0xffc01db0   /* DMA Channel 18 Current X Count Register */
+#define               DMA18_CURR_Y_COUNT  0xffc01db8   /* DMA Channel 18 Current Y Count Register */
+
+/* DMA Channel 19 Registers */
+
+#define              DMA19_NEXT_DESC_PTR  0xffc01dc0   /* DMA Channel 19 Next Descriptor Pointer Register */
+#define                 DMA19_START_ADDR  0xffc01dc4   /* DMA Channel 19 Start Address Register */
+#define                     DMA19_CONFIG  0xffc01dc8   /* DMA Channel 19 Configuration Register */
+#define                    DMA19_X_COUNT  0xffc01dd0   /* DMA Channel 19 X Count Register */
+#define                   DMA19_X_MODIFY  0xffc01dd4   /* DMA Channel 19 X Modify Register */
+#define                    DMA19_Y_COUNT  0xffc01dd8   /* DMA Channel 19 Y Count Register */
+#define                   DMA19_Y_MODIFY  0xffc01ddc   /* DMA Channel 19 Y Modify Register */
+#define              DMA19_CURR_DESC_PTR  0xffc01de0   /* DMA Channel 19 Current Descriptor Pointer Register */
+#define                  DMA19_CURR_ADDR  0xffc01de4   /* DMA Channel 19 Current Address Register */
+#define                 DMA19_IRQ_STATUS  0xffc01de8   /* DMA Channel 19 Interrupt/Status Register */
+#define             DMA19_PERIPHERAL_MAP  0xffc01dec   /* DMA Channel 19 Peripheral Map Register */
+#define               DMA19_CURR_X_COUNT  0xffc01df0   /* DMA Channel 19 Current X Count Register */
+#define               DMA19_CURR_Y_COUNT  0xffc01df8   /* DMA Channel 19 Current Y Count Register */
+
+/* DMA Channel 20 Registers */
+
+#define              DMA20_NEXT_DESC_PTR  0xffc01e00   /* DMA Channel 20 Next Descriptor Pointer Register */
+#define                 DMA20_START_ADDR  0xffc01e04   /* DMA Channel 20 Start Address Register */
+#define                     DMA20_CONFIG  0xffc01e08   /* DMA Channel 20 Configuration Register */
+#define                    DMA20_X_COUNT  0xffc01e10   /* DMA Channel 20 X Count Register */
+#define                   DMA20_X_MODIFY  0xffc01e14   /* DMA Channel 20 X Modify Register */
+#define                    DMA20_Y_COUNT  0xffc01e18   /* DMA Channel 20 Y Count Register */
+#define                   DMA20_Y_MODIFY  0xffc01e1c   /* DMA Channel 20 Y Modify Register */
+#define              DMA20_CURR_DESC_PTR  0xffc01e20   /* DMA Channel 20 Current Descriptor Pointer Register */
+#define                  DMA20_CURR_ADDR  0xffc01e24   /* DMA Channel 20 Current Address Register */
+#define                 DMA20_IRQ_STATUS  0xffc01e28   /* DMA Channel 20 Interrupt/Status Register */
+#define             DMA20_PERIPHERAL_MAP  0xffc01e2c   /* DMA Channel 20 Peripheral Map Register */
+#define               DMA20_CURR_X_COUNT  0xffc01e30   /* DMA Channel 20 Current X Count Register */
+#define               DMA20_CURR_Y_COUNT  0xffc01e38   /* DMA Channel 20 Current Y Count Register */
+
+/* DMA Channel 21 Registers */
+
+#define              DMA21_NEXT_DESC_PTR  0xffc01e40   /* DMA Channel 21 Next Descriptor Pointer Register */
+#define                 DMA21_START_ADDR  0xffc01e44   /* DMA Channel 21 Start Address Register */
+#define                     DMA21_CONFIG  0xffc01e48   /* DMA Channel 21 Configuration Register */
+#define                    DMA21_X_COUNT  0xffc01e50   /* DMA Channel 21 X Count Register */
+#define                   DMA21_X_MODIFY  0xffc01e54   /* DMA Channel 21 X Modify Register */
+#define                    DMA21_Y_COUNT  0xffc01e58   /* DMA Channel 21 Y Count Register */
+#define                   DMA21_Y_MODIFY  0xffc01e5c   /* DMA Channel 21 Y Modify Register */
+#define              DMA21_CURR_DESC_PTR  0xffc01e60   /* DMA Channel 21 Current Descriptor Pointer Register */
+#define                  DMA21_CURR_ADDR  0xffc01e64   /* DMA Channel 21 Current Address Register */
+#define                 DMA21_IRQ_STATUS  0xffc01e68   /* DMA Channel 21 Interrupt/Status Register */
+#define             DMA21_PERIPHERAL_MAP  0xffc01e6c   /* DMA Channel 21 Peripheral Map Register */
+#define               DMA21_CURR_X_COUNT  0xffc01e70   /* DMA Channel 21 Current X Count Register */
+#define               DMA21_CURR_Y_COUNT  0xffc01e78   /* DMA Channel 21 Current Y Count Register */
+
+/* DMA Channel 22 Registers */
+
+#define              DMA22_NEXT_DESC_PTR  0xffc01e80   /* DMA Channel 22 Next Descriptor Pointer Register */
+#define                 DMA22_START_ADDR  0xffc01e84   /* DMA Channel 22 Start Address Register */
+#define                     DMA22_CONFIG  0xffc01e88   /* DMA Channel 22 Configuration Register */
+#define                    DMA22_X_COUNT  0xffc01e90   /* DMA Channel 22 X Count Register */
+#define                   DMA22_X_MODIFY  0xffc01e94   /* DMA Channel 22 X Modify Register */
+#define                    DMA22_Y_COUNT  0xffc01e98   /* DMA Channel 22 Y Count Register */
+#define                   DMA22_Y_MODIFY  0xffc01e9c   /* DMA Channel 22 Y Modify Register */
+#define              DMA22_CURR_DESC_PTR  0xffc01ea0   /* DMA Channel 22 Current Descriptor Pointer Register */
+#define                  DMA22_CURR_ADDR  0xffc01ea4   /* DMA Channel 22 Current Address Register */
+#define                 DMA22_IRQ_STATUS  0xffc01ea8   /* DMA Channel 22 Interrupt/Status Register */
+#define             DMA22_PERIPHERAL_MAP  0xffc01eac   /* DMA Channel 22 Peripheral Map Register */
+#define               DMA22_CURR_X_COUNT  0xffc01eb0   /* DMA Channel 22 Current X Count Register */
+#define               DMA22_CURR_Y_COUNT  0xffc01eb8   /* DMA Channel 22 Current Y Count Register */
+
+/* DMA Channel 23 Registers */
+
+#define              DMA23_NEXT_DESC_PTR  0xffc01ec0   /* DMA Channel 23 Next Descriptor Pointer Register */
+#define                 DMA23_START_ADDR  0xffc01ec4   /* DMA Channel 23 Start Address Register */
+#define                     DMA23_CONFIG  0xffc01ec8   /* DMA Channel 23 Configuration Register */
+#define                    DMA23_X_COUNT  0xffc01ed0   /* DMA Channel 23 X Count Register */
+#define                   DMA23_X_MODIFY  0xffc01ed4   /* DMA Channel 23 X Modify Register */
+#define                    DMA23_Y_COUNT  0xffc01ed8   /* DMA Channel 23 Y Count Register */
+#define                   DMA23_Y_MODIFY  0xffc01edc   /* DMA Channel 23 Y Modify Register */
+#define              DMA23_CURR_DESC_PTR  0xffc01ee0   /* DMA Channel 23 Current Descriptor Pointer Register */
+#define                  DMA23_CURR_ADDR  0xffc01ee4   /* DMA Channel 23 Current Address Register */
+#define                 DMA23_IRQ_STATUS  0xffc01ee8   /* DMA Channel 23 Interrupt/Status Register */
+#define             DMA23_PERIPHERAL_MAP  0xffc01eec   /* DMA Channel 23 Peripheral Map Register */
+#define               DMA23_CURR_X_COUNT  0xffc01ef0   /* DMA Channel 23 Current X Count Register */
+#define               DMA23_CURR_Y_COUNT  0xffc01ef8   /* DMA Channel 23 Current Y Count Register */
+
+/* MDMA Stream 2 Registers */
+
+#define            MDMA_D2_NEXT_DESC_PTR  0xffc01f00   /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define               MDMA_D2_START_ADDR  0xffc01f04   /* Memory DMA Stream 2 Destination Start Address Register */
+#define                   MDMA_D2_CONFIG  0xffc01f08   /* Memory DMA Stream 2 Destination Configuration Register */
+#define                  MDMA_D2_X_COUNT  0xffc01f10   /* Memory DMA Stream 2 Destination X Count Register */
+#define                 MDMA_D2_X_MODIFY  0xffc01f14   /* Memory DMA Stream 2 Destination X Modify Register */
+#define                  MDMA_D2_Y_COUNT  0xffc01f18   /* Memory DMA Stream 2 Destination Y Count Register */
+#define                 MDMA_D2_Y_MODIFY  0xffc01f1c   /* Memory DMA Stream 2 Destination Y Modify Register */
+#define            MDMA_D2_CURR_DESC_PTR  0xffc01f20   /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define                MDMA_D2_CURR_ADDR  0xffc01f24   /* Memory DMA Stream 2 Destination Current Address Register */
+#define               MDMA_D2_IRQ_STATUS  0xffc01f28   /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define           MDMA_D2_PERIPHERAL_MAP  0xffc01f2c   /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define             MDMA_D2_CURR_X_COUNT  0xffc01f30   /* Memory DMA Stream 2 Destination Current X Count Register */
+#define             MDMA_D2_CURR_Y_COUNT  0xffc01f38   /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define            MDMA_S2_NEXT_DESC_PTR  0xffc01f40   /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define               MDMA_S2_START_ADDR  0xffc01f44   /* Memory DMA Stream 2 Source Start Address Register */
+#define                   MDMA_S2_CONFIG  0xffc01f48   /* Memory DMA Stream 2 Source Configuration Register */
+#define                  MDMA_S2_X_COUNT  0xffc01f50   /* Memory DMA Stream 2 Source X Count Register */
+#define                 MDMA_S2_X_MODIFY  0xffc01f54   /* Memory DMA Stream 2 Source X Modify Register */
+#define                  MDMA_S2_Y_COUNT  0xffc01f58   /* Memory DMA Stream 2 Source Y Count Register */
+#define                 MDMA_S2_Y_MODIFY  0xffc01f5c   /* Memory DMA Stream 2 Source Y Modify Register */
+#define            MDMA_S2_CURR_DESC_PTR  0xffc01f60   /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define                MDMA_S2_CURR_ADDR  0xffc01f64   /* Memory DMA Stream 2 Source Current Address Register */
+#define               MDMA_S2_IRQ_STATUS  0xffc01f68   /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define           MDMA_S2_PERIPHERAL_MAP  0xffc01f6c   /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define             MDMA_S2_CURR_X_COUNT  0xffc01f70   /* Memory DMA Stream 2 Source Current X Count Register */
+#define             MDMA_S2_CURR_Y_COUNT  0xffc01f78   /* Memory DMA Stream 2 Source Current Y Count Register */
+
+/* MDMA Stream 3 Registers */
+
+#define            MDMA_D3_NEXT_DESC_PTR  0xffc01f80   /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define               MDMA_D3_START_ADDR  0xffc01f84   /* Memory DMA Stream 3 Destination Start Address Register */
+#define                   MDMA_D3_CONFIG  0xffc01f88   /* Memory DMA Stream 3 Destination Configuration Register */
+#define                  MDMA_D3_X_COUNT  0xffc01f90   /* Memory DMA Stream 3 Destination X Count Register */
+#define                 MDMA_D3_X_MODIFY  0xffc01f94   /* Memory DMA Stream 3 Destination X Modify Register */
+#define                  MDMA_D3_Y_COUNT  0xffc01f98   /* Memory DMA Stream 3 Destination Y Count Register */
+#define                 MDMA_D3_Y_MODIFY  0xffc01f9c   /* Memory DMA Stream 3 Destination Y Modify Register */
+#define            MDMA_D3_CURR_DESC_PTR  0xffc01fa0   /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define                MDMA_D3_CURR_ADDR  0xffc01fa4   /* Memory DMA Stream 3 Destination Current Address Register */
+#define               MDMA_D3_IRQ_STATUS  0xffc01fa8   /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define           MDMA_D3_PERIPHERAL_MAP  0xffc01fac   /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define             MDMA_D3_CURR_X_COUNT  0xffc01fb0   /* Memory DMA Stream 3 Destination Current X Count Register */
+#define             MDMA_D3_CURR_Y_COUNT  0xffc01fb8   /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define            MDMA_S3_NEXT_DESC_PTR  0xffc01fc0   /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define               MDMA_S3_START_ADDR  0xffc01fc4   /* Memory DMA Stream 3 Source Start Address Register */
+#define                   MDMA_S3_CONFIG  0xffc01fc8   /* Memory DMA Stream 3 Source Configuration Register */
+#define                  MDMA_S3_X_COUNT  0xffc01fd0   /* Memory DMA Stream 3 Source X Count Register */
+#define                 MDMA_S3_X_MODIFY  0xffc01fd4   /* Memory DMA Stream 3 Source X Modify Register */
+#define                  MDMA_S3_Y_COUNT  0xffc01fd8   /* Memory DMA Stream 3 Source Y Count Register */
+#define                 MDMA_S3_Y_MODIFY  0xffc01fdc   /* Memory DMA Stream 3 Source Y Modify Register */
+#define            MDMA_S3_CURR_DESC_PTR  0xffc01fe0   /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define                MDMA_S3_CURR_ADDR  0xffc01fe4   /* Memory DMA Stream 3 Source Current Address Register */
+#define               MDMA_S3_IRQ_STATUS  0xffc01fe8   /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define           MDMA_S3_PERIPHERAL_MAP  0xffc01fec   /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define             MDMA_S3_CURR_X_COUNT  0xffc01ff0   /* Memory DMA Stream 3 Source Current X Count Register */
+#define             MDMA_S3_CURR_Y_COUNT  0xffc01ff8   /* Memory DMA Stream 3 Source Current Y Count Register */
+
+/* UART1 Registers */
+
+#define                        UART1_DLL  0xffc02000   /* Divisor Latch Low Byte */
+#define                        UART1_DLH  0xffc02004   /* Divisor Latch High Byte */
+#define                       UART1_GCTL  0xffc02008   /* Global Control Register */
+#define                        UART1_LCR  0xffc0200c   /* Line Control Register */
+#define                        UART1_MCR  0xffc02010   /* Modem Control Register */
+#define                        UART1_LSR  0xffc02014   /* Line Status Register */
+#define                        UART1_MSR  0xffc02018   /* Modem Status Register */
+#define                        UART1_SCR  0xffc0201c   /* Scratch Register */
+#define                    UART1_IER_SET  0xffc02020   /* Interrupt Enable Register Set */
+#define                  UART1_IER_CLEAR  0xffc02024   /* Interrupt Enable Register Clear */
+#define                        UART1_THR  0xffc02028   /* Transmit Hold Register */
+#define                        UART1_RBR  0xffc0202c   /* Receive Buffer Register */
+
+/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
+
+/* SPI1 Registers */
+
+#define                         SPI1_CTL  0xffc02300   /* SPI1 Control Register */
+#define                         SPI1_FLG  0xffc02304   /* SPI1 Flag Register */
+#define                        SPI1_STAT  0xffc02308   /* SPI1 Status Register */
+#define                        SPI1_TDBR  0xffc0230c   /* SPI1 Transmit Data Buffer Register */
+#define                        SPI1_RDBR  0xffc02310   /* SPI1 Receive Data Buffer Register */
+#define                        SPI1_BAUD  0xffc02314   /* SPI1 Baud Rate Register */
+#define                      SPI1_SHADOW  0xffc02318   /* SPI1 Receive Data Buffer Shadow Register */
+
+/* SPORT2 Registers */
+
+#define                      SPORT2_TCR1  0xffc02500   /* SPORT2 Transmit Configuration 1 Register */
+#define                      SPORT2_TCR2  0xffc02504   /* SPORT2 Transmit Configuration 2 Register */
+#define                   SPORT2_TCLKDIV  0xffc02508   /* SPORT2 Transmit Serial Clock Divider Register */
+#define                    SPORT2_TFSDIV  0xffc0250c   /* SPORT2 Transmit Frame Sync Divider Register */
+#define                        SPORT2_TX  0xffc02510   /* SPORT2 Transmit Data Register */
+#define                        SPORT2_RX  0xffc02518   /* SPORT2 Receive Data Register */
+#define                      SPORT2_RCR1  0xffc02520   /* SPORT2 Receive Configuration 1 Register */
+#define                      SPORT2_RCR2  0xffc02524   /* SPORT2 Receive Configuration 2 Register */
+#define                   SPORT2_RCLKDIV  0xffc02528   /* SPORT2 Receive Serial Clock Divider Register */
+#define                    SPORT2_RFSDIV  0xffc0252c   /* SPORT2 Receive Frame Sync Divider Register */
+#define                      SPORT2_STAT  0xffc02530   /* SPORT2 Status Register */
+#define                      SPORT2_CHNL  0xffc02534   /* SPORT2 Current Channel Register */
+#define                     SPORT2_MCMC1  0xffc02538   /* SPORT2 Multi channel Configuration Register 1 */
+#define                     SPORT2_MCMC2  0xffc0253c   /* SPORT2 Multi channel Configuration Register 2 */
+#define                     SPORT2_MTCS0  0xffc02540   /* SPORT2 Multi channel Transmit Select Register 0 */
+#define                     SPORT2_MTCS1  0xffc02544   /* SPORT2 Multi channel Transmit Select Register 1 */
+#define                     SPORT2_MTCS2  0xffc02548   /* SPORT2 Multi channel Transmit Select Register 2 */
+#define                     SPORT2_MTCS3  0xffc0254c   /* SPORT2 Multi channel Transmit Select Register 3 */
+#define                     SPORT2_MRCS0  0xffc02550   /* SPORT2 Multi channel Receive Select Register 0 */
+#define                     SPORT2_MRCS1  0xffc02554   /* SPORT2 Multi channel Receive Select Register 1 */
+#define                     SPORT2_MRCS2  0xffc02558   /* SPORT2 Multi channel Receive Select Register 2 */
+#define                     SPORT2_MRCS3  0xffc0255c   /* SPORT2 Multi channel Receive Select Register 3 */
+
+/* SPORT3 Registers */
+
+#define                      SPORT3_TCR1  0xffc02600   /* SPORT3 Transmit Configuration 1 Register */
+#define                      SPORT3_TCR2  0xffc02604   /* SPORT3 Transmit Configuration 2 Register */
+#define                   SPORT3_TCLKDIV  0xffc02608   /* SPORT3 Transmit Serial Clock Divider Register */
+#define                    SPORT3_TFSDIV  0xffc0260c   /* SPORT3 Transmit Frame Sync Divider Register */
+#define                        SPORT3_TX  0xffc02610   /* SPORT3 Transmit Data Register */
+#define                        SPORT3_RX  0xffc02618   /* SPORT3 Receive Data Register */
+#define                      SPORT3_RCR1  0xffc02620   /* SPORT3 Receive Configuration 1 Register */
+#define                      SPORT3_RCR2  0xffc02624   /* SPORT3 Receive Configuration 2 Register */
+#define                   SPORT3_RCLKDIV  0xffc02628   /* SPORT3 Receive Serial Clock Divider Register */
+#define                    SPORT3_RFSDIV  0xffc0262c   /* SPORT3 Receive Frame Sync Divider Register */
+#define                      SPORT3_STAT  0xffc02630   /* SPORT3 Status Register */
+#define                      SPORT3_CHNL  0xffc02634   /* SPORT3 Current Channel Register */
+#define                     SPORT3_MCMC1  0xffc02638   /* SPORT3 Multi channel Configuration Register 1 */
+#define                     SPORT3_MCMC2  0xffc0263c   /* SPORT3 Multi channel Configuration Register 2 */
+#define                     SPORT3_MTCS0  0xffc02640   /* SPORT3 Multi channel Transmit Select Register 0 */
+#define                     SPORT3_MTCS1  0xffc02644   /* SPORT3 Multi channel Transmit Select Register 1 */
+#define                     SPORT3_MTCS2  0xffc02648   /* SPORT3 Multi channel Transmit Select Register 2 */
+#define                     SPORT3_MTCS3  0xffc0264c   /* SPORT3 Multi channel Transmit Select Register 3 */
+#define                     SPORT3_MRCS0  0xffc02650   /* SPORT3 Multi channel Receive Select Register 0 */
+#define                     SPORT3_MRCS1  0xffc02654   /* SPORT3 Multi channel Receive Select Register 1 */
+#define                     SPORT3_MRCS2  0xffc02658   /* SPORT3 Multi channel Receive Select Register 2 */
+#define                     SPORT3_MRCS3  0xffc0265c   /* SPORT3 Multi channel Receive Select Register 3 */
+
+/* EPPI2 Registers */
+
+#define                     EPPI2_STATUS  0xffc02900   /* EPPI2 Status Register */
+#define                     EPPI2_HCOUNT  0xffc02904   /* EPPI2 Horizontal Transfer Count Register */
+#define                     EPPI2_HDELAY  0xffc02908   /* EPPI2 Horizontal Delay Count Register */
+#define                     EPPI2_VCOUNT  0xffc0290c   /* EPPI2 Vertical Transfer Count Register */
+#define                     EPPI2_VDELAY  0xffc02910   /* EPPI2 Vertical Delay Count Register */
+#define                      EPPI2_FRAME  0xffc02914   /* EPPI2 Lines per Frame Register */
+#define                       EPPI2_LINE  0xffc02918   /* EPPI2 Samples per Line Register */
+#define                     EPPI2_CLKDIV  0xffc0291c   /* EPPI2 Clock Divide Register */
+#define                    EPPI2_CONTROL  0xffc02920   /* EPPI2 Control Register */
+#define                   EPPI2_FS1W_HBL  0xffc02924   /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define                  EPPI2_FS1P_AVPL  0xffc02928   /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define                   EPPI2_FS2W_LVB  0xffc0292c   /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define                  EPPI2_FS2P_LAVF  0xffc02930   /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define                       EPPI2_CLIP  0xffc02934   /* EPPI2 Clipping Register */
+
+/* CAN Controller 0 Config 1 Registers */
+
+#define                         CAN0_MC1  0xffc02a00   /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define                         CAN0_MD1  0xffc02a04   /* CAN Controller 0 Mailbox Direction Register 1 */
+#define                        CAN0_TRS1  0xffc02a08   /* CAN Controller 0 Transmit Request Set Register 1 */
+#define                        CAN0_TRR1  0xffc02a0c   /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define                         CAN0_TA1  0xffc02a10   /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define                         CAN0_AA1  0xffc02a14   /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define                        CAN0_RMP1  0xffc02a18   /* CAN Controller 0 Receive Message Pending Register 1 */
+#define                        CAN0_RML1  0xffc02a1c   /* CAN Controller 0 Receive Message Lost Register 1 */
+#define                      CAN0_MBTIF1  0xffc02a20   /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define                      CAN0_MBRIF1  0xffc02a24   /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define                       CAN0_MBIM1  0xffc02a28   /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define                        CAN0_RFH1  0xffc02a2c   /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define                       CAN0_OPSS1  0xffc02a30   /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+
+/* CAN Controller 0 Config 2 Registers */
+
+#define                         CAN0_MC2  0xffc02a40   /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define                         CAN0_MD2  0xffc02a44   /* CAN Controller 0 Mailbox Direction Register 2 */
+#define                        CAN0_TRS2  0xffc02a48   /* CAN Controller 0 Transmit Request Set Register 2 */
+#define                        CAN0_TRR2  0xffc02a4c   /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define                         CAN0_TA2  0xffc02a50   /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define                         CAN0_AA2  0xffc02a54   /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define                        CAN0_RMP2  0xffc02a58   /* CAN Controller 0 Receive Message Pending Register 2 */
+#define                        CAN0_RML2  0xffc02a5c   /* CAN Controller 0 Receive Message Lost Register 2 */
+#define                      CAN0_MBTIF2  0xffc02a60   /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define                      CAN0_MBRIF2  0xffc02a64   /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define                       CAN0_MBIM2  0xffc02a68   /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define                        CAN0_RFH2  0xffc02a6c   /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define                       CAN0_OPSS2  0xffc02a70   /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+
+/* CAN Controller 0 Clock/Interrupt/Counter Registers */
+
+#define                       CAN0_CLOCK  0xffc02a80   /* CAN Controller 0 Clock Register */
+#define                      CAN0_TIMING  0xffc02a84   /* CAN Controller 0 Timing Register */
+#define                       CAN0_DEBUG  0xffc02a88   /* CAN Controller 0 Debug Register */
+#define                      CAN0_STATUS  0xffc02a8c   /* CAN Controller 0 Global Status Register */
+#define                         CAN0_CEC  0xffc02a90   /* CAN Controller 0 Error Counter Register */
+#define                         CAN0_GIS  0xffc02a94   /* CAN Controller 0 Global Interrupt Status Register */
+#define                         CAN0_GIM  0xffc02a98   /* CAN Controller 0 Global Interrupt Mask Register */
+#define                         CAN0_GIF  0xffc02a9c   /* CAN Controller 0 Global Interrupt Flag Register */
+#define                     CAN0_CONTROL  0xffc02aa0   /* CAN Controller 0 Master Control Register */
+#define                        CAN0_INTR  0xffc02aa4   /* CAN Controller 0 Interrupt Pending Register */
+#define                        CAN0_MBTD  0xffc02aac   /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define                         CAN0_EWR  0xffc02ab0   /* CAN Controller 0 Programmable Warning Level Register */
+#define                         CAN0_ESR  0xffc02ab4   /* CAN Controller 0 Error Status Register */
+#define                       CAN0_UCCNT  0xffc02ac4   /* CAN Controller 0 Universal Counter Register */
+#define                        CAN0_UCRC  0xffc02ac8   /* CAN Controller 0 Universal Counter Force Reload Register */
+#define                       CAN0_UCCNF  0xffc02acc   /* CAN Controller 0 Universal Counter Configuration Register */
+
+/* CAN Controller 0 Acceptance Registers */
+
+#define                       CAN0_AM00L  0xffc02b00   /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define                       CAN0_AM00H  0xffc02b04   /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define                       CAN0_AM01L  0xffc02b08   /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define                       CAN0_AM01H  0xffc02b0c   /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define                       CAN0_AM02L  0xffc02b10   /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define                       CAN0_AM02H  0xffc02b14   /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define                       CAN0_AM03L  0xffc02b18   /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define                       CAN0_AM03H  0xffc02b1c   /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define                       CAN0_AM04L  0xffc02b20   /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define                       CAN0_AM04H  0xffc02b24   /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define                       CAN0_AM05L  0xffc02b28   /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define                       CAN0_AM05H  0xffc02b2c   /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define                       CAN0_AM06L  0xffc02b30   /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define                       CAN0_AM06H  0xffc02b34   /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define                       CAN0_AM07L  0xffc02b38   /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define                       CAN0_AM07H  0xffc02b3c   /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define                       CAN0_AM08L  0xffc02b40   /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define                       CAN0_AM08H  0xffc02b44   /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define                       CAN0_AM09L  0xffc02b48   /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define                       CAN0_AM09H  0xffc02b4c   /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define                       CAN0_AM10L  0xffc02b50   /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define                       CAN0_AM10H  0xffc02b54   /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define                       CAN0_AM11L  0xffc02b58   /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define                       CAN0_AM11H  0xffc02b5c   /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define                       CAN0_AM12L  0xffc02b60   /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define                       CAN0_AM12H  0xffc02b64   /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define                       CAN0_AM13L  0xffc02b68   /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define                       CAN0_AM13H  0xffc02b6c   /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define                       CAN0_AM14L  0xffc02b70   /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define                       CAN0_AM14H  0xffc02b74   /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define                       CAN0_AM15L  0xffc02b78   /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define                       CAN0_AM15H  0xffc02b7c   /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+
+/* CAN Controller 0 Acceptance Registers */
+
+#define                       CAN0_AM16L  0xffc02b80   /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define                       CAN0_AM16H  0xffc02b84   /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define                       CAN0_AM17L  0xffc02b88   /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define                       CAN0_AM17H  0xffc02b8c   /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define                       CAN0_AM18L  0xffc02b90   /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define                       CAN0_AM18H  0xffc02b94   /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define                       CAN0_AM19L  0xffc02b98   /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define                       CAN0_AM19H  0xffc02b9c   /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define                       CAN0_AM20L  0xffc02ba0   /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define                       CAN0_AM20H  0xffc02ba4   /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define                       CAN0_AM21L  0xffc02ba8   /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define                       CAN0_AM21H  0xffc02bac   /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define                       CAN0_AM22L  0xffc02bb0   /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define                       CAN0_AM22H  0xffc02bb4   /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define                       CAN0_AM23L  0xffc02bb8   /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define                       CAN0_AM23H  0xffc02bbc   /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define                       CAN0_AM24L  0xffc02bc0   /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define                       CAN0_AM24H  0xffc02bc4   /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define                       CAN0_AM25L  0xffc02bc8   /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define                       CAN0_AM25H  0xffc02bcc   /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define                       CAN0_AM26L  0xffc02bd0   /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define                       CAN0_AM26H  0xffc02bd4   /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define                       CAN0_AM27L  0xffc02bd8   /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define                       CAN0_AM27H  0xffc02bdc   /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define                       CAN0_AM28L  0xffc02be0   /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define                       CAN0_AM28H  0xffc02be4   /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define                       CAN0_AM29L  0xffc02be8   /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define                       CAN0_AM29H  0xffc02bec   /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define                       CAN0_AM30L  0xffc02bf0   /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define                       CAN0_AM30H  0xffc02bf4   /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define                       CAN0_AM31L  0xffc02bf8   /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define                       CAN0_AM31H  0xffc02bfc   /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+
+/* CAN Controller 0 Mailbox Data Registers */
+
+#define                  CAN0_MB00_DATA0  0xffc02c00   /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define                  CAN0_MB00_DATA1  0xffc02c04   /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define                  CAN0_MB00_DATA2  0xffc02c08   /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define                  CAN0_MB00_DATA3  0xffc02c0c   /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define                 CAN0_MB00_LENGTH  0xffc02c10   /* CAN Controller 0 Mailbox 0 Length Register */
+#define              CAN0_MB00_TIMESTAMP  0xffc02c14   /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define                    CAN0_MB00_ID0  0xffc02c18   /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define                    CAN0_MB00_ID1  0xffc02c1c   /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define                  CAN0_MB01_DATA0  0xffc02c20   /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define                  CAN0_MB01_DATA1  0xffc02c24   /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define                  CAN0_MB01_DATA2  0xffc02c28   /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define                  CAN0_MB01_DATA3  0xffc02c2c   /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define                 CAN0_MB01_LENGTH  0xffc02c30   /* CAN Controller 0 Mailbox 1 Length Register */
+#define              CAN0_MB01_TIMESTAMP  0xffc02c34   /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define                    CAN0_MB01_ID0  0xffc02c38   /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define                    CAN0_MB01_ID1  0xffc02c3c   /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define                  CAN0_MB02_DATA0  0xffc02c40   /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define                  CAN0_MB02_DATA1  0xffc02c44   /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define                  CAN0_MB02_DATA2  0xffc02c48   /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define                  CAN0_MB02_DATA3  0xffc02c4c   /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define                 CAN0_MB02_LENGTH  0xffc02c50   /* CAN Controller 0 Mailbox 2 Length Register */
+#define              CAN0_MB02_TIMESTAMP  0xffc02c54   /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define                    CAN0_MB02_ID0  0xffc02c58   /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define                    CAN0_MB02_ID1  0xffc02c5c   /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define                  CAN0_MB03_DATA0  0xffc02c60   /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define                  CAN0_MB03_DATA1  0xffc02c64   /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define                  CAN0_MB03_DATA2  0xffc02c68   /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define                  CAN0_MB03_DATA3  0xffc02c6c   /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define                 CAN0_MB03_LENGTH  0xffc02c70   /* CAN Controller 0 Mailbox 3 Length Register */
+#define              CAN0_MB03_TIMESTAMP  0xffc02c74   /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define                    CAN0_MB03_ID0  0xffc02c78   /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define                    CAN0_MB03_ID1  0xffc02c7c   /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define                  CAN0_MB04_DATA0  0xffc02c80   /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define                  CAN0_MB04_DATA1  0xffc02c84   /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define                  CAN0_MB04_DATA2  0xffc02c88   /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define                  CAN0_MB04_DATA3  0xffc02c8c   /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define                 CAN0_MB04_LENGTH  0xffc02c90   /* CAN Controller 0 Mailbox 4 Length Register */
+#define              CAN0_MB04_TIMESTAMP  0xffc02c94   /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define                    CAN0_MB04_ID0  0xffc02c98   /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define                    CAN0_MB04_ID1  0xffc02c9c   /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define                  CAN0_MB05_DATA0  0xffc02ca0   /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define                  CAN0_MB05_DATA1  0xffc02ca4   /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define                  CAN0_MB05_DATA2  0xffc02ca8   /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define                  CAN0_MB05_DATA3  0xffc02cac   /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define                 CAN0_MB05_LENGTH  0xffc02cb0   /* CAN Controller 0 Mailbox 5 Length Register */
+#define              CAN0_MB05_TIMESTAMP  0xffc02cb4   /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define                    CAN0_MB05_ID0  0xffc02cb8   /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define                    CAN0_MB05_ID1  0xffc02cbc   /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define                  CAN0_MB06_DATA0  0xffc02cc0   /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define                  CAN0_MB06_DATA1  0xffc02cc4   /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define                  CAN0_MB06_DATA2  0xffc02cc8   /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define                  CAN0_MB06_DATA3  0xffc02ccc   /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define                 CAN0_MB06_LENGTH  0xffc02cd0   /* CAN Controller 0 Mailbox 6 Length Register */
+#define              CAN0_MB06_TIMESTAMP  0xffc02cd4   /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define                    CAN0_MB06_ID0  0xffc02cd8   /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define                    CAN0_MB06_ID1  0xffc02cdc   /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define                  CAN0_MB07_DATA0  0xffc02ce0   /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define                  CAN0_MB07_DATA1  0xffc02ce4   /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define                  CAN0_MB07_DATA2  0xffc02ce8   /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define                  CAN0_MB07_DATA3  0xffc02cec   /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define                 CAN0_MB07_LENGTH  0xffc02cf0   /* CAN Controller 0 Mailbox 7 Length Register */
+#define              CAN0_MB07_TIMESTAMP  0xffc02cf4   /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define                    CAN0_MB07_ID0  0xffc02cf8   /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define                    CAN0_MB07_ID1  0xffc02cfc   /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define                  CAN0_MB08_DATA0  0xffc02d00   /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define                  CAN0_MB08_DATA1  0xffc02d04   /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define                  CAN0_MB08_DATA2  0xffc02d08   /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define                  CAN0_MB08_DATA3  0xffc02d0c   /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define                 CAN0_MB08_LENGTH  0xffc02d10   /* CAN Controller 0 Mailbox 8 Length Register */
+#define              CAN0_MB08_TIMESTAMP  0xffc02d14   /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define                    CAN0_MB08_ID0  0xffc02d18   /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define                    CAN0_MB08_ID1  0xffc02d1c   /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define                  CAN0_MB09_DATA0  0xffc02d20   /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define                  CAN0_MB09_DATA1  0xffc02d24   /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define                  CAN0_MB09_DATA2  0xffc02d28   /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define                  CAN0_MB09_DATA3  0xffc02d2c   /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define                 CAN0_MB09_LENGTH  0xffc02d30   /* CAN Controller 0 Mailbox 9 Length Register */
+#define              CAN0_MB09_TIMESTAMP  0xffc02d34   /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define                    CAN0_MB09_ID0  0xffc02d38   /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define                    CAN0_MB09_ID1  0xffc02d3c   /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define                  CAN0_MB10_DATA0  0xffc02d40   /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define                  CAN0_MB10_DATA1  0xffc02d44   /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define                  CAN0_MB10_DATA2  0xffc02d48   /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define                  CAN0_MB10_DATA3  0xffc02d4c   /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define                 CAN0_MB10_LENGTH  0xffc02d50   /* CAN Controller 0 Mailbox 10 Length Register */
+#define              CAN0_MB10_TIMESTAMP  0xffc02d54   /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define                    CAN0_MB10_ID0  0xffc02d58   /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define                    CAN0_MB10_ID1  0xffc02d5c   /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define                  CAN0_MB11_DATA0  0xffc02d60   /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define                  CAN0_MB11_DATA1  0xffc02d64   /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define                  CAN0_MB11_DATA2  0xffc02d68   /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define                  CAN0_MB11_DATA3  0xffc02d6c   /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define                 CAN0_MB11_LENGTH  0xffc02d70   /* CAN Controller 0 Mailbox 11 Length Register */
+#define              CAN0_MB11_TIMESTAMP  0xffc02d74   /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define                    CAN0_MB11_ID0  0xffc02d78   /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define                    CAN0_MB11_ID1  0xffc02d7c   /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define                  CAN0_MB12_DATA0  0xffc02d80   /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define                  CAN0_MB12_DATA1  0xffc02d84   /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define                  CAN0_MB12_DATA2  0xffc02d88   /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define                  CAN0_MB12_DATA3  0xffc02d8c   /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define                 CAN0_MB12_LENGTH  0xffc02d90   /* CAN Controller 0 Mailbox 12 Length Register */
+#define              CAN0_MB12_TIMESTAMP  0xffc02d94   /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define                    CAN0_MB12_ID0  0xffc02d98   /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define                    CAN0_MB12_ID1  0xffc02d9c   /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define                  CAN0_MB13_DATA0  0xffc02da0   /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define                  CAN0_MB13_DATA1  0xffc02da4   /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define                  CAN0_MB13_DATA2  0xffc02da8   /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define                  CAN0_MB13_DATA3  0xffc02dac   /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define                 CAN0_MB13_LENGTH  0xffc02db0   /* CAN Controller 0 Mailbox 13 Length Register */
+#define              CAN0_MB13_TIMESTAMP  0xffc02db4   /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define                    CAN0_MB13_ID0  0xffc02db8   /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define                    CAN0_MB13_ID1  0xffc02dbc   /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define                  CAN0_MB14_DATA0  0xffc02dc0   /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define                  CAN0_MB14_DATA1  0xffc02dc4   /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define                  CAN0_MB14_DATA2  0xffc02dc8   /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define                  CAN0_MB14_DATA3  0xffc02dcc   /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define                 CAN0_MB14_LENGTH  0xffc02dd0   /* CAN Controller 0 Mailbox 14 Length Register */
+#define              CAN0_MB14_TIMESTAMP  0xffc02dd4   /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define                    CAN0_MB14_ID0  0xffc02dd8   /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define                    CAN0_MB14_ID1  0xffc02ddc   /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define                  CAN0_MB15_DATA0  0xffc02de0   /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define                  CAN0_MB15_DATA1  0xffc02de4   /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define                  CAN0_MB15_DATA2  0xffc02de8   /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define                  CAN0_MB15_DATA3  0xffc02dec   /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define                 CAN0_MB15_LENGTH  0xffc02df0   /* CAN Controller 0 Mailbox 15 Length Register */
+#define              CAN0_MB15_TIMESTAMP  0xffc02df4   /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define                    CAN0_MB15_ID0  0xffc02df8   /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define                    CAN0_MB15_ID1  0xffc02dfc   /* CAN Controller 0 Mailbox 15 ID1 Register */
+
+/* CAN Controller 0 Mailbox Data Registers */
+
+#define                  CAN0_MB16_DATA0  0xffc02e00   /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define                  CAN0_MB16_DATA1  0xffc02e04   /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define                  CAN0_MB16_DATA2  0xffc02e08   /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define                  CAN0_MB16_DATA3  0xffc02e0c   /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define                 CAN0_MB16_LENGTH  0xffc02e10   /* CAN Controller 0 Mailbox 16 Length Register */
+#define              CAN0_MB16_TIMESTAMP  0xffc02e14   /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define                    CAN0_MB16_ID0  0xffc02e18   /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define                    CAN0_MB16_ID1  0xffc02e1c   /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define                  CAN0_MB17_DATA0  0xffc02e20   /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define                  CAN0_MB17_DATA1  0xffc02e24   /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define                  CAN0_MB17_DATA2  0xffc02e28   /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define                  CAN0_MB17_DATA3  0xffc02e2c   /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define                 CAN0_MB17_LENGTH  0xffc02e30   /* CAN Controller 0 Mailbox 17 Length Register */
+#define              CAN0_MB17_TIMESTAMP  0xffc02e34   /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define                    CAN0_MB17_ID0  0xffc02e38   /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define                    CAN0_MB17_ID1  0xffc02e3c   /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define                  CAN0_MB18_DATA0  0xffc02e40   /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define                  CAN0_MB18_DATA1  0xffc02e44   /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define                  CAN0_MB18_DATA2  0xffc02e48   /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define                  CAN0_MB18_DATA3  0xffc02e4c   /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define                 CAN0_MB18_LENGTH  0xffc02e50   /* CAN Controller 0 Mailbox 18 Length Register */
+#define              CAN0_MB18_TIMESTAMP  0xffc02e54   /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define                    CAN0_MB18_ID0  0xffc02e58   /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define                    CAN0_MB18_ID1  0xffc02e5c   /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define                  CAN0_MB19_DATA0  0xffc02e60   /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define                  CAN0_MB19_DATA1  0xffc02e64   /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define                  CAN0_MB19_DATA2  0xffc02e68   /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define                  CAN0_MB19_DATA3  0xffc02e6c   /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define                 CAN0_MB19_LENGTH  0xffc02e70   /* CAN Controller 0 Mailbox 19 Length Register */
+#define              CAN0_MB19_TIMESTAMP  0xffc02e74   /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define                    CAN0_MB19_ID0  0xffc02e78   /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define                    CAN0_MB19_ID1  0xffc02e7c   /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define                  CAN0_MB20_DATA0  0xffc02e80   /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define                  CAN0_MB20_DATA1  0xffc02e84   /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define                  CAN0_MB20_DATA2  0xffc02e88   /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define                  CAN0_MB20_DATA3  0xffc02e8c   /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define                 CAN0_MB20_LENGTH  0xffc02e90   /* CAN Controller 0 Mailbox 20 Length Register */
+#define              CAN0_MB20_TIMESTAMP  0xffc02e94   /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define                    CAN0_MB20_ID0  0xffc02e98   /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define                    CAN0_MB20_ID1  0xffc02e9c   /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define                  CAN0_MB21_DATA0  0xffc02ea0   /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define                  CAN0_MB21_DATA1  0xffc02ea4   /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define                  CAN0_MB21_DATA2  0xffc02ea8   /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define                  CAN0_MB21_DATA3  0xffc02eac   /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define                 CAN0_MB21_LENGTH  0xffc02eb0   /* CAN Controller 0 Mailbox 21 Length Register */
+#define              CAN0_MB21_TIMESTAMP  0xffc02eb4   /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define                    CAN0_MB21_ID0  0xffc02eb8   /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define                    CAN0_MB21_ID1  0xffc02ebc   /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define                  CAN0_MB22_DATA0  0xffc02ec0   /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define                  CAN0_MB22_DATA1  0xffc02ec4   /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define                  CAN0_MB22_DATA2  0xffc02ec8   /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define                  CAN0_MB22_DATA3  0xffc02ecc   /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define                 CAN0_MB22_LENGTH  0xffc02ed0   /* CAN Controller 0 Mailbox 22 Length Register */
+#define              CAN0_MB22_TIMESTAMP  0xffc02ed4   /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define                    CAN0_MB22_ID0  0xffc02ed8   /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define                    CAN0_MB22_ID1  0xffc02edc   /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define                  CAN0_MB23_DATA0  0xffc02ee0   /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define                  CAN0_MB23_DATA1  0xffc02ee4   /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define                  CAN0_MB23_DATA2  0xffc02ee8   /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define                  CAN0_MB23_DATA3  0xffc02eec   /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define                 CAN0_MB23_LENGTH  0xffc02ef0   /* CAN Controller 0 Mailbox 23 Length Register */
+#define              CAN0_MB23_TIMESTAMP  0xffc02ef4   /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define                    CAN0_MB23_ID0  0xffc02ef8   /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define                    CAN0_MB23_ID1  0xffc02efc   /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define                  CAN0_MB24_DATA0  0xffc02f00   /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define                  CAN0_MB24_DATA1  0xffc02f04   /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define                  CAN0_MB24_DATA2  0xffc02f08   /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define                  CAN0_MB24_DATA3  0xffc02f0c   /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define                 CAN0_MB24_LENGTH  0xffc02f10   /* CAN Controller 0 Mailbox 24 Length Register */
+#define              CAN0_MB24_TIMESTAMP  0xffc02f14   /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define                    CAN0_MB24_ID0  0xffc02f18   /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define                    CAN0_MB24_ID1  0xffc02f1c   /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define                  CAN0_MB25_DATA0  0xffc02f20   /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define                  CAN0_MB25_DATA1  0xffc02f24   /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define                  CAN0_MB25_DATA2  0xffc02f28   /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define                  CAN0_MB25_DATA3  0xffc02f2c   /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define                 CAN0_MB25_LENGTH  0xffc02f30   /* CAN Controller 0 Mailbox 25 Length Register */
+#define              CAN0_MB25_TIMESTAMP  0xffc02f34   /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define                    CAN0_MB25_ID0  0xffc02f38   /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define                    CAN0_MB25_ID1  0xffc02f3c   /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define                  CAN0_MB26_DATA0  0xffc02f40   /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define                  CAN0_MB26_DATA1  0xffc02f44   /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define                  CAN0_MB26_DATA2  0xffc02f48   /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define                  CAN0_MB26_DATA3  0xffc02f4c   /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define                 CAN0_MB26_LENGTH  0xffc02f50   /* CAN Controller 0 Mailbox 26 Length Register */
+#define              CAN0_MB26_TIMESTAMP  0xffc02f54   /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define                    CAN0_MB26_ID0  0xffc02f58   /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define                    CAN0_MB26_ID1  0xffc02f5c   /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define                  CAN0_MB27_DATA0  0xffc02f60   /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define                  CAN0_MB27_DATA1  0xffc02f64   /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define                  CAN0_MB27_DATA2  0xffc02f68   /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define                  CAN0_MB27_DATA3  0xffc02f6c   /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define                 CAN0_MB27_LENGTH  0xffc02f70   /* CAN Controller 0 Mailbox 27 Length Register */
+#define              CAN0_MB27_TIMESTAMP  0xffc02f74   /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define                    CAN0_MB27_ID0  0xffc02f78   /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define                    CAN0_MB27_ID1  0xffc02f7c   /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define                  CAN0_MB28_DATA0  0xffc02f80   /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define                  CAN0_MB28_DATA1  0xffc02f84   /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define                  CAN0_MB28_DATA2  0xffc02f88   /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define                  CAN0_MB28_DATA3  0xffc02f8c   /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define                 CAN0_MB28_LENGTH  0xffc02f90   /* CAN Controller 0 Mailbox 28 Length Register */
+#define              CAN0_MB28_TIMESTAMP  0xffc02f94   /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define                    CAN0_MB28_ID0  0xffc02f98   /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define                    CAN0_MB28_ID1  0xffc02f9c   /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define                  CAN0_MB29_DATA0  0xffc02fa0   /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define                  CAN0_MB29_DATA1  0xffc02fa4   /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define                  CAN0_MB29_DATA2  0xffc02fa8   /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define                  CAN0_MB29_DATA3  0xffc02fac   /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define                 CAN0_MB29_LENGTH  0xffc02fb0   /* CAN Controller 0 Mailbox 29 Length Register */
+#define              CAN0_MB29_TIMESTAMP  0xffc02fb4   /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define                    CAN0_MB29_ID0  0xffc02fb8   /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define                    CAN0_MB29_ID1  0xffc02fbc   /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define                  CAN0_MB30_DATA0  0xffc02fc0   /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define                  CAN0_MB30_DATA1  0xffc02fc4   /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define                  CAN0_MB30_DATA2  0xffc02fc8   /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define                  CAN0_MB30_DATA3  0xffc02fcc   /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define                 CAN0_MB30_LENGTH  0xffc02fd0   /* CAN Controller 0 Mailbox 30 Length Register */
+#define              CAN0_MB30_TIMESTAMP  0xffc02fd4   /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define                    CAN0_MB30_ID0  0xffc02fd8   /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define                    CAN0_MB30_ID1  0xffc02fdc   /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define                  CAN0_MB31_DATA0  0xffc02fe0   /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define                  CAN0_MB31_DATA1  0xffc02fe4   /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define                  CAN0_MB31_DATA2  0xffc02fe8   /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define                  CAN0_MB31_DATA3  0xffc02fec   /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define                 CAN0_MB31_LENGTH  0xffc02ff0   /* CAN Controller 0 Mailbox 31 Length Register */
+#define              CAN0_MB31_TIMESTAMP  0xffc02ff4   /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define                    CAN0_MB31_ID0  0xffc02ff8   /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define                    CAN0_MB31_ID1  0xffc02ffc   /* CAN Controller 0 Mailbox 31 ID1 Register */
+
+/* UART3 Registers */
+
+#define                        UART3_DLL  0xffc03100   /* Divisor Latch Low Byte */
+#define                        UART3_DLH  0xffc03104   /* Divisor Latch High Byte */
+#define                       UART3_GCTL  0xffc03108   /* Global Control Register */
+#define                        UART3_LCR  0xffc0310c   /* Line Control Register */
+#define                        UART3_MCR  0xffc03110   /* Modem Control Register */
+#define                        UART3_LSR  0xffc03114   /* Line Status Register */
+#define                        UART3_MSR  0xffc03118   /* Modem Status Register */
+#define                        UART3_SCR  0xffc0311c   /* Scratch Register */
+#define                    UART3_IER_SET  0xffc03120   /* Interrupt Enable Register Set */
+#define                  UART3_IER_CLEAR  0xffc03124   /* Interrupt Enable Register Clear */
+#define                        UART3_THR  0xffc03128   /* Transmit Hold Register */
+#define                        UART3_RBR  0xffc0312c   /* Receive Buffer Register */
+
+/* NFC Registers */
+
+#define                          NFC_CTL  0xffc03b00   /* NAND Control Register */
+#define                         NFC_STAT  0xffc03b04   /* NAND Status Register */
+#define                      NFC_IRQSTAT  0xffc03b08   /* NAND Interrupt Status Register */
+#define                      NFC_IRQMASK  0xffc03b0c   /* NAND Interrupt Mask Register */
+#define                         NFC_ECC0  0xffc03b10   /* NAND ECC Register 0 */
+#define                         NFC_ECC1  0xffc03b14   /* NAND ECC Register 1 */
+#define                         NFC_ECC2  0xffc03b18   /* NAND ECC Register 2 */
+#define                         NFC_ECC3  0xffc03b1c   /* NAND ECC Register 3 */
+#define                        NFC_COUNT  0xffc03b20   /* NAND ECC Count Register */
+#define                          NFC_RST  0xffc03b24   /* NAND ECC Reset Register */
+#define                        NFC_PGCTL  0xffc03b28   /* NAND Page Control Register */
+#define                         NFC_READ  0xffc03b2c   /* NAND Read Data Register */
+#define                         NFC_ADDR  0xffc03b40   /* NAND Address Register */
+#define                          NFC_CMD  0xffc03b44   /* NAND Command Register */
+#define                      NFC_DATA_WR  0xffc03b48   /* NAND Data Write Register */
+#define                      NFC_DATA_RD  0xffc03b4c   /* NAND Data Read Register */
+
+/* Counter Registers */
+
+#define                       CNT_CONFIG  0xffc04200   /* Configuration Register */
+#define                        CNT_IMASK  0xffc04204   /* Interrupt Mask Register */
+#define                       CNT_STATUS  0xffc04208   /* Status Register */
+#define                      CNT_COMMAND  0xffc0420c   /* Command Register */
+#define                     CNT_DEBOUNCE  0xffc04210   /* Debounce Register */
+#define                      CNT_COUNTER  0xffc04214   /* Counter Register */
+#define                          CNT_MAX  0xffc04218   /* Maximal Count Register */
+#define                          CNT_MIN  0xffc0421c   /* Minimal Count Register */
+
+/* OTP/FUSE Registers */
+
+#define                      OTP_CONTROL  0xffc04300   /* OTP/Fuse Control Register */
+#define                          OTP_BEN  0xffc04304   /* OTP/Fuse Byte Enable */
+#define                       OTP_STATUS  0xffc04308   /* OTP/Fuse Status */
+#define                       OTP_TIMING  0xffc0430c   /* OTP/Fuse Access Timing */
+
+/* Security Registers */
+
+#define                    SECURE_SYSSWT  0xffc04320   /* Secure System Switches */
+#define                   SECURE_CONTROL  0xffc04324   /* Secure Control */
+#define                    SECURE_STATUS  0xffc04328   /* Secure Status */
+
+/* DMA Peripheral Mux Register */
+
+#define                    DMAC1_PERIMUX  0xffc04340   /* DMA Controller 1 Peripheral Multiplexer Register */
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define                        OTP_DATA0  0xffc04380   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA1  0xffc04384   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA2  0xffc04388   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA3  0xffc0438c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+
+/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for SIC_IAR0 */
+
+#define            IRQ_PLL_WAKEUP  0x1        /* PLL Wakeup */
+#define           nIRQ_PLL_WAKEUP  0x0       
+
+/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
+
+#define              IRQ_DMA0_ERR  0x2        /* DMA Controller 0 Error */
+#define             nIRQ_DMA0_ERR  0x0       
+#define             IRQ_EPPI0_ERR  0x4        /* EPPI0 Error */
+#define            nIRQ_EPPI0_ERR  0x0       
+#define            IRQ_SPORT0_ERR  0x8        /* SPORT0 Error */
+#define           nIRQ_SPORT0_ERR  0x0       
+#define            IRQ_SPORT1_ERR  0x10       /* SPORT1 Error */
+#define           nIRQ_SPORT1_ERR  0x0       
+#define              IRQ_SPI0_ERR  0x20       /* SPI0 Error */
+#define             nIRQ_SPI0_ERR  0x0       
+#define             IRQ_UART0_ERR  0x40       /* UART0 Error */
+#define            nIRQ_UART0_ERR  0x0       
+#define                   IRQ_RTC  0x80       /* Real-Time Clock */
+#define                  nIRQ_RTC  0x0       
+#define                 IRQ_DMA12  0x100      /* DMA Channel 12 */
+#define                nIRQ_DMA12  0x0       
+#define                  IRQ_DMA0  0x200      /* DMA Channel 0 */
+#define                 nIRQ_DMA0  0x0       
+#define                  IRQ_DMA1  0x400      /* DMA Channel 1 */
+#define                 nIRQ_DMA1  0x0       
+#define                  IRQ_DMA2  0x800      /* DMA Channel 2 */
+#define                 nIRQ_DMA2  0x0       
+#define                  IRQ_DMA3  0x1000     /* DMA Channel 3 */
+#define                 nIRQ_DMA3  0x0       
+#define                  IRQ_DMA4  0x2000     /* DMA Channel 4 */
+#define                 nIRQ_DMA4  0x0       
+#define                  IRQ_DMA6  0x4000     /* DMA Channel 6 */
+#define                 nIRQ_DMA6  0x0       
+#define                  IRQ_DMA7  0x8000     /* DMA Channel 7 */
+#define                 nIRQ_DMA7  0x0       
+#define                 IRQ_PINT0  0x80000    /* Pin Interrupt 0 */
+#define                nIRQ_PINT0  0x0       
+#define                 IRQ_PINT1  0x100000   /* Pin Interrupt 1 */
+#define                nIRQ_PINT1  0x0       
+#define                 IRQ_MDMA0  0x200000   /* Memory DMA Stream 0 */
+#define                nIRQ_MDMA0  0x0       
+#define                 IRQ_MDMA1  0x400000   /* Memory DMA Stream 1 */
+#define                nIRQ_MDMA1  0x0       
+#define                  IRQ_WDOG  0x800000   /* Watchdog Timer */
+#define                 nIRQ_WDOG  0x0       
+#define              IRQ_DMA1_ERR  0x1000000  /* DMA Controller 1 Error */
+#define             nIRQ_DMA1_ERR  0x0       
+#define            IRQ_SPORT2_ERR  0x2000000  /* SPORT2 Error */
+#define           nIRQ_SPORT2_ERR  0x0       
+#define            IRQ_SPORT3_ERR  0x4000000  /* SPORT3 Error */
+#define           nIRQ_SPORT3_ERR  0x0       
+#define               IRQ_MXVR_SD  0x8000000  /* MXVR Synchronous Data */
+#define              nIRQ_MXVR_SD  0x0       
+#define              IRQ_SPI1_ERR  0x10000000 /* SPI1 Error */
+#define             nIRQ_SPI1_ERR  0x0       
+#define              IRQ_SPI2_ERR  0x20000000 /* SPI2 Error */
+#define             nIRQ_SPI2_ERR  0x0       
+#define             IRQ_UART1_ERR  0x40000000 /* UART1 Error */
+#define            nIRQ_UART1_ERR  0x0       
+#define             IRQ_UART2_ERR  0x80000000 /* UART2 Error */
+#define            nIRQ_UART2_ERR  0x0       
+
+/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
+
+#define              IRQ_CAN0_ERR  0x1        /* CAN0 Error */
+#define             nIRQ_CAN0_ERR  0x0       
+#define                 IRQ_DMA18  0x2        /* DMA Channel 18 */
+#define                nIRQ_DMA18  0x0       
+#define                 IRQ_DMA19  0x4        /* DMA Channel 19 */
+#define                nIRQ_DMA19  0x0       
+#define                 IRQ_DMA20  0x8        /* DMA Channel 20 */
+#define                nIRQ_DMA20  0x0       
+#define                 IRQ_DMA21  0x10       /* DMA Channel 21 */
+#define                nIRQ_DMA21  0x0       
+#define                 IRQ_DMA13  0x20       /* DMA Channel 13 */
+#define                nIRQ_DMA13  0x0       
+#define                 IRQ_DMA14  0x40       /* DMA Channel 14 */
+#define                nIRQ_DMA14  0x0       
+#define                  IRQ_DMA5  0x80       /* DMA Channel 5 */
+#define                 nIRQ_DMA5  0x0       
+#define                 IRQ_DMA23  0x100      /* DMA Channel 23 */
+#define                nIRQ_DMA23  0x0       
+#define                  IRQ_DMA8  0x200      /* DMA Channel 8 */
+#define                 nIRQ_DMA8  0x0       
+#define                  IRQ_DMA9  0x400      /* DMA Channel 9 */
+#define                 nIRQ_DMA9  0x0       
+#define                 IRQ_DMA10  0x800      /* DMA Channel 10 */
+#define                nIRQ_DMA10  0x0       
+#define                 IRQ_DMA11  0x1000     /* DMA Channel 11 */
+#define                nIRQ_DMA11  0x0       
+#define                  IRQ_TWI0  0x2000     /* TWI0 */
+#define                 nIRQ_TWI0  0x0       
+#define                  IRQ_TWI1  0x4000     /* TWI1 */
+#define                 nIRQ_TWI1  0x0       
+#define               IRQ_CAN0_RX  0x8000     /* CAN0 Receive */
+#define              nIRQ_CAN0_RX  0x0       
+#define               IRQ_CAN0_TX  0x10000    /* CAN0 Transmit */
+#define              nIRQ_CAN0_TX  0x0       
+#define                 IRQ_MDMA2  0x20000    /* Memory DMA Stream 0 */
+#define                nIRQ_MDMA2  0x0       
+#define                 IRQ_MDMA3  0x40000    /* Memory DMA Stream 1 */
+#define                nIRQ_MDMA3  0x0       
+#define             IRQ_MXVR_STAT  0x80000    /* MXVR Status */
+#define            nIRQ_MXVR_STAT  0x0       
+#define               IRQ_MXVR_CM  0x100000   /* MXVR Control Message */
+#define              nIRQ_MXVR_CM  0x0       
+#define               IRQ_MXVR_AP  0x200000   /* MXVR Asynchronous Packet */
+#define              nIRQ_MXVR_AP  0x0       
+#define             IRQ_EPPI1_ERR  0x400000   /* EPPI1 Error */
+#define            nIRQ_EPPI1_ERR  0x0       
+#define             IRQ_EPPI2_ERR  0x800000   /* EPPI2 Error */
+#define            nIRQ_EPPI2_ERR  0x0       
+#define             IRQ_UART3_ERR  0x1000000  /* UART3 Error */
+#define            nIRQ_UART3_ERR  0x0       
+#define              IRQ_HOST_ERR  0x2000000  /* Host DMA Port Error */
+#define             nIRQ_HOST_ERR  0x0       
+#define               IRQ_USB_ERR  0x4000000  /* USB Error */
+#define              nIRQ_USB_ERR  0x0       
+#define              IRQ_PIXC_ERR  0x8000000  /* Pixel Compositor Error */
+#define             nIRQ_PIXC_ERR  0x0       
+#define               IRQ_NFC_ERR  0x10000000 /* Nand Flash Controller Error */
+#define              nIRQ_NFC_ERR  0x0       
+#define             IRQ_ATAPI_ERR  0x20000000 /* ATAPI Error */
+#define            nIRQ_ATAPI_ERR  0x0       
+#define              IRQ_CAN1_ERR  0x40000000 /* CAN1 Error */
+#define             nIRQ_CAN1_ERR  0x0       
+#define             IRQ_DMAR0_ERR  0x80000000 /* DMAR0 Overflow Error */
+#define            nIRQ_DMAR0_ERR  0x0       
+#define             IRQ_DMAR1_ERR  0x80000000 /* DMAR1 Overflow Error */
+#define            nIRQ_DMAR1_ERR  0x0       
+#define                 IRQ_DMAR0  0x80000000 /* DMAR0 Block */
+#define                nIRQ_DMAR0  0x0       
+#define                 IRQ_DMAR1  0x80000000 /* DMAR1 Block */
+#define                nIRQ_DMAR1  0x0       
+
+/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
+
+#define                 IRQ_DMA15  0x1        /* DMA Channel 15 */
+#define                nIRQ_DMA15  0x0       
+#define                 IRQ_DMA16  0x2        /* DMA Channel 16 */
+#define                nIRQ_DMA16  0x0       
+#define                 IRQ_DMA17  0x4        /* DMA Channel 17 */
+#define                nIRQ_DMA17  0x0       
+#define                 IRQ_DMA22  0x8        /* DMA Channel 22 */
+#define                nIRQ_DMA22  0x0       
+#define                   IRQ_CNT  0x10       /* Counter */
+#define                  nIRQ_CNT  0x0       
+#define                   IRQ_KEY  0x20       /* Keypad */
+#define                  nIRQ_KEY  0x0       
+#define               IRQ_CAN1_RX  0x40       /* CAN1 Receive */
+#define              nIRQ_CAN1_RX  0x0       
+#define               IRQ_CAN1_TX  0x80       /* CAN1 Transmit */
+#define              nIRQ_CAN1_TX  0x0       
+#define             IRQ_SDH_MASK0  0x100      /* SDH Mask 0 */
+#define            nIRQ_SDH_MASK0  0x0       
+#define             IRQ_SDH_MASK1  0x200      /* SDH Mask 1 */
+#define            nIRQ_SDH_MASK1  0x0       
+#define              IRQ_USB_EINT  0x400      /* USB Exception */
+#define             nIRQ_USB_EINT  0x0       
+#define              IRQ_USB_INT0  0x800      /* USB Interrupt 0 */
+#define             nIRQ_USB_INT0  0x0       
+#define              IRQ_USB_INT1  0x1000     /* USB Interrupt 1 */
+#define             nIRQ_USB_INT1  0x0       
+#define              IRQ_USB_INT2  0x2000     /* USB Interrupt 2 */
+#define             nIRQ_USB_INT2  0x0       
+#define            IRQ_USB_DMAINT  0x4000     /* USB DMA */
+#define           nIRQ_USB_DMAINT  0x0       
+#define                IRQ_OTPSEC  0x8000     /* OTP Access Complete */
+#define               nIRQ_OTPSEC  0x0       
+#define                IRQ_TIMER0  0x400000   /* Timer 0 */
+#define               nIRQ_TIMER0  0x0       
+#define                IRQ_TIMER1  0x800000   /* Timer 1 */
+#define               nIRQ_TIMER1  0x0       
+#define                IRQ_TIMER2  0x1000000  /* Timer 2 */
+#define               nIRQ_TIMER2  0x0       
+#define                IRQ_TIMER3  0x2000000  /* Timer 3 */
+#define               nIRQ_TIMER3  0x0       
+#define                IRQ_TIMER4  0x4000000  /* Timer 4 */
+#define               nIRQ_TIMER4  0x0       
+#define                IRQ_TIMER5  0x8000000  /* Timer 5 */
+#define               nIRQ_TIMER5  0x0       
+#define                IRQ_TIMER6  0x10000000 /* Timer 6 */
+#define               nIRQ_TIMER6  0x0       
+#define                IRQ_TIMER7  0x20000000 /* Timer 7 */
+#define               nIRQ_TIMER7  0x0       
+#define                 IRQ_PINT2  0x40000000 /* Pin Interrupt 2 */
+#define                nIRQ_PINT2  0x0       
+#define                 IRQ_PINT3  0x80000000 /* Pin Interrupt 3 */
+#define                nIRQ_PINT3  0x0       
+
+/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
+
+#define                     DMAEN  0x1        /* DMA Channel Enable */
+#define                    nDMAEN  0x0       
+#define                       WNR  0x2        /* DMA Direction */
+#define                      nWNR  0x0       
+#define                    WDSIZE  0xc        /* Transfer Word Size */
+#define                     DMA2D  0x10       /* DMA Mode */
+#define                    nDMA2D  0x0       
+#define                   RESTART  0x20       /* Work Unit Transitions */
+#define                  nRESTART  0x0       
+#define                    DI_SEL  0x40       /* Data Interrupt Timing Select */
+#define                   nDI_SEL  0x0       
+#define                     DI_EN  0x80       /* Data Interrupt Enable */
+#define                    nDI_EN  0x0       
+#define                    NDSIZE  0xf00      /* Flex Descriptor Size */
+#define                   DMAFLOW  0xf000     /* Next Operation */
+
+/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
+
+#define                  DMA_DONE  0x1        /* DMA Completion Interrupt Status */
+#define                 nDMA_DONE  0x0       
+#define                   DMA_ERR  0x2        /* DMA Error Interrupt Status */
+#define                  nDMA_ERR  0x0       
+#define                    DFETCH  0x4        /* DMA Descriptor Fetch */
+#define                   nDFETCH  0x0       
+#define                   DMA_RUN  0x8        /* DMA Channel Running */
+#define                  nDMA_RUN  0x0       
+
+/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
+
+#define                     CTYPE  0x40       /* DMA Channel Type */
+#define                    nCTYPE  0x0       
+#define                      PMAP  0xf000     /* Peripheral Mapped To This Channel */
+
+/* Bit masks for DMACx_TCPER */
+
+#define        DCB_TRAFFIC_PERIOD  0xf        /* DCB Traffic Control Period */
+#define        DEB_TRAFFIC_PERIOD  0xf0       /* DEB Traffic Control Period */
+#define        DAB_TRAFFIC_PERIOD  0x700      /* DAB Traffic Control Period */
+#define   MDMA_ROUND_ROBIN_PERIOD  0xf800     /* MDMA Round Robin Period */
+
+/* Bit masks for DMACx_TCCNT */
+
+#define         DCB_TRAFFIC_COUNT  0xf        /* DCB Traffic Control Count */
+#define         DEB_TRAFFIC_COUNT  0xf0       /* DEB Traffic Control Count */
+#define         DAB_TRAFFIC_COUNT  0x700      /* DAB Traffic Control Count */
+#define    MDMA_ROUND_ROBIN_COUNT  0xf800     /* MDMA Round Robin Count */
+
+/* Bit masks for DMAC1_PERIMUX */
+
+#define                   PMUXSDH  0x1        /* Peripheral Select for DMA22 channel */
+#define                  nPMUXSDH  0x0       
+
+/* Bit masks for EBIU_AMGCTL */
+
+#define                    AMCKEN  0x1        /* Async Memory Enable */
+#define                   nAMCKEN  0x0       
+#define                     AMBEN  0xe        /* Async bank enable */
+
+/* Bit masks for EBIU_AMBCTL0 */
+
+#define                   B0RDYEN  0x1        /* Bank 0 ARDY Enable */
+#define                  nB0RDYEN  0x0       
+#define                  B0RDYPOL  0x2        /* Bank 0 ARDY Polarity */
+#define                 nB0RDYPOL  0x0       
+#define                      B0TT  0xc        /* Bank 0 transition time */
+#define                      B0ST  0x30       /* Bank 0 Setup time */
+#define                      B0HT  0xc0       /* Bank 0 Hold time */
+#define                     B0RAT  0xf00      /* Bank 0 Read access time */
+#define                     B0WAT  0xf000     /* Bank 0 write access time */
+#define                   B1RDYEN  0x10000    /* Bank 1 ARDY Enable */
+#define                  nB1RDYEN  0x0       
+#define                  B1RDYPOL  0x20000    /* Bank 1 ARDY Polarity */
+#define                 nB1RDYPOL  0x0       
+#define                      B1TT  0xc0000    /* Bank 1 transition time */
+#define                      B1ST  0x300000   /* Bank 1 Setup time */
+#define                      B1HT  0xc00000   /* Bank 1 Hold time */
+#define                     B1RAT  0xf000000  /* Bank 1 Read access time */
+#define                     B1WAT  0xf0000000 /* Bank 1 write access time */
+
+/* Bit masks for EBIU_AMBCTL1 */
+
+#define                   B2RDYEN  0x1        /* Bank 2 ARDY Enable */
+#define                  nB2RDYEN  0x0       
+#define                  B2RDYPOL  0x2        /* Bank 2 ARDY Polarity */
+#define                 nB2RDYPOL  0x0       
+#define                      B2TT  0xc        /* Bank 2 transition time */
+#define                      B2ST  0x30       /* Bank 2 Setup time */
+#define                      B2HT  0xc0       /* Bank 2 Hold time */
+#define                     B2RAT  0xf00      /* Bank 2 Read access time */
+#define                     B2WAT  0xf000     /* Bank 2 write access time */
+#define                   B3RDYEN  0x10000    /* Bank 3 ARDY Enable */
+#define                  nB3RDYEN  0x0       
+#define                  B3RDYPOL  0x20000    /* Bank 3 ARDY Polarity */
+#define                 nB3RDYPOL  0x0       
+#define                      B3TT  0xc0000    /* Bank 3 transition time */
+#define                      B3ST  0x300000   /* Bank 3 Setup time */
+#define                      B3HT  0xc00000   /* Bank 3 Hold time */
+#define                     B3RAT  0xf000000  /* Bank 3 Read access time */
+#define                     B3WAT  0xf0000000 /* Bank 3 write access time */
+
+/* Bit masks for EBIU_MBSCTL */
+
+#define                  AMSB0CTL  0x3        /* Async Memory Bank 0 select */
+#define                  AMSB1CTL  0xc        /* Async Memory Bank 1 select */
+#define                  AMSB2CTL  0x30       /* Async Memory Bank 2 select */
+#define                  AMSB3CTL  0xc0       /* Async Memory Bank 3 select */
+
+/* Bit masks for EBIU_MODE */
+
+#define                    B0MODE  0x3        /* Async Memory Bank 0 Access Mode */
+#define                    B1MODE  0xc        /* Async Memory Bank 1 Access Mode */
+#define                    B2MODE  0x30       /* Async Memory Bank 2 Access Mode */
+#define                    B3MODE  0xc0       /* Async Memory Bank 3 Access Mode */
+
+/* Bit masks for EBIU_FCTL */
+
+#define               TESTSETLOCK  0x1        /* Test set lock */
+#define              nTESTSETLOCK  0x0       
+#define                      BCLK  0x6        /* Burst clock frequency */
+#define                      PGWS  0x38       /* Page wait states */
+#define                      PGSZ  0x40       /* Page size */
+#define                     nPGSZ  0x0       
+#define                      RDDL  0x380      /* Read data delay */
+
+/* Bit masks for EBIU_ARBSTAT */
+
+#define                   ARBSTAT  0x1        /* Arbitration status */
+#define                  nARBSTAT  0x0       
+#define                    BGSTAT  0x2        /* Bus grant status */
+#define                   nBGSTAT  0x0       
+
+/* Bit masks for EBIU_DDRCTL0 */
+
+#define                     TREFI  0x3fff     /* Refresh Interval */
+#define                      TRFC  0x3c000    /* Auto-refresh command period */
+#define                       TRP  0x3c0000   /* Pre charge-to-active command period */
+#define                      TRAS  0x3c00000  /* Min Active-to-pre charge time */
+#define                       TRC  0x3c000000 /* Active-to-active time */
+
+/* Bit masks for EBIU_DDRCTL1 */
+
+#define                      TRCD  0xf        /* Active-to-Read/write delay */
+#define                       MRD  0xf0       /* Mode register set to active */
+#define                       TWR  0x300      /* Write Recovery time */
+#define               DDRDATWIDTH  0x3000     /* DDR data width */
+#define                  EXTBANKS  0xc000     /* External banks */
+#define               DDRDEVWIDTH  0x30000    /* DDR device width */
+#define                DDRDEVSIZE  0xc0000    /* DDR device size */
+#define                     TWWTR  0xf0000000 /* Write-to-read delay */
+
+/* Bit masks for EBIU_DDRCTL2 */
+
+#define               BURSTLENGTH  0x7        /* Burst length */
+#define                CASLATENCY  0x70       /* CAS latency */
+#define                  DLLRESET  0x100      /* DLL Reset */
+#define                 nDLLRESET  0x0       
+#define                      REGE  0x1000     /* Register mode enable */
+#define                     nREGE  0x0       
+
+/* Bit masks for EBIU_DDRCTL3 */
+
+#define                      PASR  0x7        /* Partial array self-refresh */
+
+/* Bit masks for EBIU_DDRQUE */
+
+#define                DEB1_PFLEN  0x3        /* Pre fetch length for DEB1 accesses */
+#define                DEB2_PFLEN  0xc        /* Pre fetch length for DEB2 accesses */
+#define                DEB3_PFLEN  0x30       /* Pre fetch length for DEB3 accesses */
+#define          DEB_ARB_PRIORITY  0x700      /* Arbitration between DEB busses */
+#define               DEB1_URGENT  0x1000     /* DEB1 Urgent */
+#define              nDEB1_URGENT  0x0       
+#define               DEB2_URGENT  0x2000     /* DEB2 Urgent */
+#define              nDEB2_URGENT  0x0       
+#define               DEB3_URGENT  0x4000     /* DEB3 Urgent */
+#define              nDEB3_URGENT  0x0       
+
+/* Bit masks for EBIU_ERRMST */
+
+#define                DEB1_ERROR  0x1        /* DEB1 Error */
+#define               nDEB1_ERROR  0x0       
+#define                DEB2_ERROR  0x2        /* DEB2 Error */
+#define               nDEB2_ERROR  0x0       
+#define                DEB3_ERROR  0x4        /* DEB3 Error */
+#define               nDEB3_ERROR  0x0       
+#define                CORE_ERROR  0x8        /* Core error */
+#define               nCORE_ERROR  0x0       
+#define                DEB_MERROR  0x10       /* DEB1 Error (2nd) */
+#define               nDEB_MERROR  0x0       
+#define               DEB2_MERROR  0x20       /* DEB2 Error (2nd) */
+#define              nDEB2_MERROR  0x0       
+#define               DEB3_MERROR  0x40       /* DEB3 Error (2nd) */
+#define              nDEB3_MERROR  0x0       
+#define               CORE_MERROR  0x80       /* Core Error (2nd) */
+#define              nCORE_MERROR  0x0       
+
+/* Bit masks for EBIU_ERRADD */
+
+#define             ERROR_ADDRESS  0xffffffff /* Error Address */
+
+/* Bit masks for EBIU_RSTCTL */
+
+#define                 DDRSRESET  0x1        /* DDR soft reset */
+#define                nDDRSRESET  0x0       
+#define               PFTCHSRESET  0x4        /* DDR prefetch reset */
+#define              nPFTCHSRESET  0x0       
+#define                     SRREQ  0x8        /* Self-refresh request */
+#define                    nSRREQ  0x0       
+#define                     SRACK  0x10       /* Self-refresh acknowledge */
+#define                    nSRACK  0x0       
+#define                MDDRENABLE  0x20       /* Mobile DDR enable */
+#define               nMDDRENABLE  0x0       
+
+/* Bit masks for EBIU_DDRBRC0 */
+
+#define                      BRC0  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC1 */
+
+#define                      BRC1  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC2 */
+
+#define                      BRC2  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC3 */
+
+#define                      BRC3  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC4 */
+
+#define                      BRC4  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC5 */
+
+#define                      BRC5  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC6 */
+
+#define                      BRC6  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC7 */
+
+#define                      BRC7  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC0 */
+
+#define                      BWC0  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC1 */
+
+#define                      BWC1  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC2 */
+
+#define                      BWC2  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC3 */
+
+#define                      BWC3  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC4 */
+
+#define                      BWC4  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC5 */
+
+#define                      BWC5  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC6 */
+
+#define                      BWC6  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC7 */
+
+#define                      BWC7  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRACCT */
+
+#define                      ACCT  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRTACT */
+
+#define                      TECT  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRARCT */
+
+#define                      ARCT  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRGC0 */
+
+#define                       GC0  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRGC1 */
+
+#define                       GC1  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRGC2 */
+
+#define                       GC2  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRGC3 */
+
+#define                       GC3  0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRMCEN */
+
+#define                B0WCENABLE  0x1        /* Bank 0 write count enable */
+#define               nB0WCENABLE  0x0       
+#define                B1WCENABLE  0x2        /* Bank 1 write count enable */
+#define               nB1WCENABLE  0x0       
+#define                B2WCENABLE  0x4        /* Bank 2 write count enable */
+#define               nB2WCENABLE  0x0       
+#define                B3WCENABLE  0x8        /* Bank 3 write count enable */
+#define               nB3WCENABLE  0x0       
+#define                B4WCENABLE  0x10       /* Bank 4 write count enable */
+#define               nB4WCENABLE  0x0       
+#define                B5WCENABLE  0x20       /* Bank 5 write count enable */
+#define               nB5WCENABLE  0x0       
+#define                B6WCENABLE  0x40       /* Bank 6 write count enable */
+#define               nB6WCENABLE  0x0       
+#define                B7WCENABLE  0x80       /* Bank 7 write count enable */
+#define               nB7WCENABLE  0x0       
+#define                B0RCENABLE  0x100      /* Bank 0 read count enable */
+#define               nB0RCENABLE  0x0       
+#define                B1RCENABLE  0x200      /* Bank 1 read count enable */
+#define               nB1RCENABLE  0x0       
+#define                B2RCENABLE  0x400      /* Bank 2 read count enable */
+#define               nB2RCENABLE  0x0       
+#define                B3RCENABLE  0x800      /* Bank 3 read count enable */
+#define               nB3RCENABLE  0x0       
+#define                B4RCENABLE  0x1000     /* Bank 4 read count enable */
+#define               nB4RCENABLE  0x0       
+#define                B5RCENABLE  0x2000     /* Bank 5 read count enable */
+#define               nB5RCENABLE  0x0       
+#define                B6RCENABLE  0x4000     /* Bank 6 read count enable */
+#define               nB6RCENABLE  0x0       
+#define                B7RCENABLE  0x8000     /* Bank 7 read count enable */
+#define               nB7RCENABLE  0x0       
+#define             ROWACTCENABLE  0x10000    /* DDR Row activate count enable */
+#define            nROWACTCENABLE  0x0       
+#define                RWTCENABLE  0x20000    /* DDR R/W Turn around count enable */
+#define               nRWTCENABLE  0x0       
+#define                 ARCENABLE  0x40000    /* DDR Auto-refresh count enable */
+#define                nARCENABLE  0x0       
+#define                 GC0ENABLE  0x100000   /* DDR Grant count 0 enable */
+#define                nGC0ENABLE  0x0       
+#define                 GC1ENABLE  0x200000   /* DDR Grant count 1 enable */
+#define                nGC1ENABLE  0x0       
+#define                 GC2ENABLE  0x400000   /* DDR Grant count 2 enable */
+#define                nGC2ENABLE  0x0       
+#define                 GC3ENABLE  0x800000   /* DDR Grant count 3 enable */
+#define                nGC3ENABLE  0x0       
+#define                 GCCONTROL  0x3000000  /* DDR Grant Count Control */
+
+/* Bit masks for EBIU_DDRMCCL */
+
+#define                 CB0WCOUNT  0x1        /* Clear write count 0 */
+#define                nCB0WCOUNT  0x0       
+#define                 CB1WCOUNT  0x2        /* Clear write count 1 */
+#define                nCB1WCOUNT  0x0       
+#define                 CB2WCOUNT  0x4        /* Clear write count 2 */
+#define                nCB2WCOUNT  0x0       
+#define                 CB3WCOUNT  0x8        /* Clear write count 3 */
+#define                nCB3WCOUNT  0x0       
+#define                 CB4WCOUNT  0x10       /* Clear write count 4 */
+#define                nCB4WCOUNT  0x0       
+#define                 CB5WCOUNT  0x20       /* Clear write count 5 */
+#define                nCB5WCOUNT  0x0       
+#define                 CB6WCOUNT  0x40       /* Clear write count 6 */
+#define                nCB6WCOUNT  0x0       
+#define                 CB7WCOUNT  0x80       /* Clear write count 7 */
+#define                nCB7WCOUNT  0x0       
+#define                  CBRCOUNT  0x100      /* Clear read count 0 */
+#define                 nCBRCOUNT  0x0       
+#define                 CB1RCOUNT  0x200      /* Clear read count 1 */
+#define                nCB1RCOUNT  0x0       
+#define                 CB2RCOUNT  0x400      /* Clear read count 2 */
+#define                nCB2RCOUNT  0x0       
+#define                 CB3RCOUNT  0x800      /* Clear read count 3 */
+#define                nCB3RCOUNT  0x0       
+#define                 CB4RCOUNT  0x1000     /* Clear read count 4 */
+#define                nCB4RCOUNT  0x0       
+#define                 CB5RCOUNT  0x2000     /* Clear read count 5 */
+#define                nCB5RCOUNT  0x0       
+#define                 CB6RCOUNT  0x4000     /* Clear read count 6 */
+#define                nCB6RCOUNT  0x0       
+#define                 CB7RCOUNT  0x8000     /* Clear read count 7 */
+#define                nCB7RCOUNT  0x0       
+#define                  CRACOUNT  0x10000    /* Clear row activation count */
+#define                 nCRACOUNT  0x0       
+#define                CRWTACOUNT  0x20000    /* Clear R/W turn-around count */
+#define               nCRWTACOUNT  0x0       
+#define                  CARCOUNT  0x40000    /* Clear auto-refresh count */
+#define                 nCARCOUNT  0x0       
+#define                  CG0COUNT  0x100000   /* Clear grant count 0 */
+#define                 nCG0COUNT  0x0       
+#define                  CG1COUNT  0x200000   /* Clear grant count 1 */
+#define                 nCG1COUNT  0x0       
+#define                  CG2COUNT  0x400000   /* Clear grant count 2 */
+#define                 nCG2COUNT  0x0       
+#define                  CG3COUNT  0x800000   /* Clear grant count 3 */
+#define                 nCG3COUNT  0x0       
+
+/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
+
+#define                       Px0  0x1        /* GPIO 0 */
+#define                      nPx0  0x0       
+#define                       Px1  0x2        /* GPIO 1 */
+#define                      nPx1  0x0       
+#define                       Px2  0x4        /* GPIO 2 */
+#define                      nPx2  0x0       
+#define                       Px3  0x8        /* GPIO 3 */
+#define                      nPx3  0x0       
+#define                       Px4  0x10       /* GPIO 4 */
+#define                      nPx4  0x0       
+#define                       Px5  0x20       /* GPIO 5 */
+#define                      nPx5  0x0       
+#define                       Px6  0x40       /* GPIO 6 */
+#define                      nPx6  0x0       
+#define                       Px7  0x80       /* GPIO 7 */
+#define                      nPx7  0x0       
+#define                       Px8  0x100      /* GPIO 8 */
+#define                      nPx8  0x0       
+#define                       Px9  0x200      /* GPIO 9 */
+#define                      nPx9  0x0       
+#define                      Px10  0x400      /* GPIO 10 */
+#define                     nPx10  0x0       
+#define                      Px11  0x800      /* GPIO 11 */
+#define                     nPx11  0x0       
+#define                      Px12  0x1000     /* GPIO 12 */
+#define                     nPx12  0x0       
+#define                      Px13  0x2000     /* GPIO 13 */
+#define                     nPx13  0x0       
+#define                      Px14  0x4000     /* GPIO 14 */
+#define                     nPx14  0x0       
+#define                      Px15  0x8000     /* GPIO 15 */
+#define                     nPx15  0x0       
+
+/* Bit masks for PORTA_MUX - PORTJ_MUX */
+
+#define                      PxM0  0x3        /* GPIO Mux 0 */
+#define                      PxM1  0xc        /* GPIO Mux 1 */
+#define                      PxM2  0x30       /* GPIO Mux 2 */
+#define                      PxM3  0xc0       /* GPIO Mux 3 */
+#define                      PxM4  0x300      /* GPIO Mux 4 */
+#define                      PxM5  0xc00      /* GPIO Mux 5 */
+#define                      PxM6  0x3000     /* GPIO Mux 6 */
+#define                      PxM7  0xc000     /* GPIO Mux 7 */
+#define                      PxM8  0x30000    /* GPIO Mux 8 */
+#define                      PxM9  0xc0000    /* GPIO Mux 9 */
+#define                     PxM10  0x300000   /* GPIO Mux 10 */
+#define                     PxM11  0xc00000   /* GPIO Mux 11 */
+#define                     PxM12  0x3000000  /* GPIO Mux 12 */
+#define                     PxM13  0xc000000  /* GPIO Mux 13 */
+#define                     PxM14  0x30000000 /* GPIO Mux 14 */
+#define                     PxM15  0xc0000000 /* GPIO Mux 15 */
+
+
+/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
+
+#define                       IB0  0x1        /* Interrupt Bit 0 */
+#define                      nIB0  0x0       
+#define                       IB1  0x2        /* Interrupt Bit 1 */
+#define                      nIB1  0x0       
+#define                       IB2  0x4        /* Interrupt Bit 2 */
+#define                      nIB2  0x0       
+#define                       IB3  0x8        /* Interrupt Bit 3 */
+#define                      nIB3  0x0       
+#define                       IB4  0x10       /* Interrupt Bit 4 */
+#define                      nIB4  0x0       
+#define                       IB5  0x20       /* Interrupt Bit 5 */
+#define                      nIB5  0x0       
+#define                       IB6  0x40       /* Interrupt Bit 6 */
+#define                      nIB6  0x0       
+#define                       IB7  0x80       /* Interrupt Bit 7 */
+#define                      nIB7  0x0       
+#define                       IB8  0x100      /* Interrupt Bit 8 */
+#define                      nIB8  0x0       
+#define                       IB9  0x200      /* Interrupt Bit 9 */
+#define                      nIB9  0x0       
+#define                      IB10  0x400      /* Interrupt Bit 10 */
+#define                     nIB10  0x0       
+#define                      IB11  0x800      /* Interrupt Bit 11 */
+#define                     nIB11  0x0       
+#define                      IB12  0x1000     /* Interrupt Bit 12 */
+#define                     nIB12  0x0       
+#define                      IB13  0x2000     /* Interrupt Bit 13 */
+#define                     nIB13  0x0       
+#define                      IB14  0x4000     /* Interrupt Bit 14 */
+#define                     nIB14  0x0       
+#define                      IB15  0x8000     /* Interrupt Bit 15 */
+#define                     nIB15  0x0       
+
+/* Bit masks for TIMERx_CONFIG */
+
+#define                     TMODE  0x3        /* Timer Mode */
+#define                  PULSE_HI  0x4        /* Pulse Polarity */
+#define                 nPULSE_HI  0x0       
+#define                PERIOD_CNT  0x8        /* Period Count */
+#define               nPERIOD_CNT  0x0       
+#define                   IRQ_ENA  0x10       /* Interrupt Request Enable */
+#define                  nIRQ_ENA  0x0       
+#define                   TIN_SEL  0x20       /* Timer Input Select */
+#define                  nTIN_SEL  0x0       
+#define                   OUT_DIS  0x40       /* Output Pad Disable */
+#define                  nOUT_DIS  0x0       
+#define                   CLK_SEL  0x80       /* Timer Clock Select */
+#define                  nCLK_SEL  0x0       
+#define                 TOGGLE_HI  0x100      /* Toggle Mode */
+#define                nTOGGLE_HI  0x0       
+#define                   EMU_RUN  0x200      /* Emulation Behavior Select */
+#define                  nEMU_RUN  0x0       
+#define                   ERR_TYP  0xc000     /* Error Type */
+
+/* Bit masks for TIMER_ENABLE0 */
+
+#define                    TIMEN0  0x1        /* Timer 0 Enable */
+#define                   nTIMEN0  0x0       
+#define                    TIMEN1  0x2        /* Timer 1 Enable */
+#define                   nTIMEN1  0x0       
+#define                    TIMEN2  0x4        /* Timer 2 Enable */
+#define                   nTIMEN2  0x0       
+#define                    TIMEN3  0x8        /* Timer 3 Enable */
+#define                   nTIMEN3  0x0       
+#define                    TIMEN4  0x10       /* Timer 4 Enable */
+#define                   nTIMEN4  0x0       
+#define                    TIMEN5  0x20       /* Timer 5 Enable */
+#define                   nTIMEN5  0x0       
+#define                    TIMEN6  0x40       /* Timer 6 Enable */
+#define                   nTIMEN6  0x0       
+#define                    TIMEN7  0x80       /* Timer 7 Enable */
+#define                   nTIMEN7  0x0       
+
+/* Bit masks for TIMER_DISABLE0 */
+
+#define                   TIMDIS0  0x1        /* Timer 0 Disable */
+#define                  nTIMDIS0  0x0       
+#define                   TIMDIS1  0x2        /* Timer 1 Disable */
+#define                  nTIMDIS1  0x0       
+#define                   TIMDIS2  0x4        /* Timer 2 Disable */
+#define                  nTIMDIS2  0x0       
+#define                   TIMDIS3  0x8        /* Timer 3 Disable */
+#define                  nTIMDIS3  0x0       
+#define                   TIMDIS4  0x10       /* Timer 4 Disable */
+#define                  nTIMDIS4  0x0       
+#define                   TIMDIS5  0x20       /* Timer 5 Disable */
+#define                  nTIMDIS5  0x0       
+#define                   TIMDIS6  0x40       /* Timer 6 Disable */
+#define                  nTIMDIS6  0x0       
+#define                   TIMDIS7  0x80       /* Timer 7 Disable */
+#define                  nTIMDIS7  0x0       
+
+/* Bit masks for TIMER_STATUS0 */
+
+#define                    TIMIL0  0x1        /* Timer 0 Interrupt */
+#define                   nTIMIL0  0x0       
+#define                    TIMIL1  0x2        /* Timer 1 Interrupt */
+#define                   nTIMIL1  0x0       
+#define                    TIMIL2  0x4        /* Timer 2 Interrupt */
+#define                   nTIMIL2  0x0       
+#define                    TIMIL3  0x8        /* Timer 3 Interrupt */
+#define                   nTIMIL3  0x0       
+#define                 TOVF_ERR0  0x10       /* Timer 0 Counter Overflow */
+#define                nTOVF_ERR0  0x0       
+#define                 TOVF_ERR1  0x20       /* Timer 1 Counter Overflow */
+#define                nTOVF_ERR1  0x0       
+#define                 TOVF_ERR2  0x40       /* Timer 2 Counter Overflow */
+#define                nTOVF_ERR2  0x0       
+#define                 TOVF_ERR3  0x80       /* Timer 3 Counter Overflow */
+#define                nTOVF_ERR3  0x0       
+#define                     TRUN0  0x1000     /* Timer 0 Slave Enable Status */
+#define                    nTRUN0  0x0       
+#define                     TRUN1  0x2000     /* Timer 1 Slave Enable Status */
+#define                    nTRUN1  0x0       
+#define                     TRUN2  0x4000     /* Timer 2 Slave Enable Status */
+#define                    nTRUN2  0x0       
+#define                     TRUN3  0x8000     /* Timer 3 Slave Enable Status */
+#define                    nTRUN3  0x0       
+#define                    TIMIL4  0x10000    /* Timer 4 Interrupt */
+#define                   nTIMIL4  0x0       
+#define                    TIMIL5  0x20000    /* Timer 5 Interrupt */
+#define                   nTIMIL5  0x0       
+#define                    TIMIL6  0x40000    /* Timer 6 Interrupt */
+#define                   nTIMIL6  0x0       
+#define                    TIMIL7  0x80000    /* Timer 7 Interrupt */
+#define                   nTIMIL7  0x0       
+#define                 TOVF_ERR4  0x100000   /* Timer 4 Counter Overflow */
+#define                nTOVF_ERR4  0x0       
+#define                 TOVF_ERR5  0x200000   /* Timer 5 Counter Overflow */
+#define                nTOVF_ERR5  0x0       
+#define                 TOVF_ERR6  0x400000   /* Timer 6 Counter Overflow */
+#define                nTOVF_ERR6  0x0       
+#define                 TOVF_ERR7  0x800000   /* Timer 7 Counter Overflow */
+#define                nTOVF_ERR7  0x0       
+#define                     TRUN4  0x10000000 /* Timer 4 Slave Enable Status */
+#define                    nTRUN4  0x0       
+#define                     TRUN5  0x20000000 /* Timer 5 Slave Enable Status */
+#define                    nTRUN5  0x0       
+#define                     TRUN6  0x40000000 /* Timer 6 Slave Enable Status */
+#define                    nTRUN6  0x0       
+#define                     TRUN7  0x80000000 /* Timer 7 Slave Enable Status */
+#define                    nTRUN7  0x0       
+
+/* Bit masks for WDOG_CTL */
+
+#define                      WDEV  0x6        /* Watchdog Event */
+#define                      WDEN  0xff0      /* Watchdog Enable */
+#define                      WDRO  0x8000     /* Watchdog Rolled Over */
+#define                     nWDRO  0x0       
+
+/* Bit masks for CNT_CONFIG */
+
+#define                      CNTE  0x1        /* Counter Enable */
+#define                     nCNTE  0x0       
+#define                      DEBE  0x2        /* Debounce Enable */
+#define                     nDEBE  0x0       
+#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
+#define                   nCDGINV  0x0       
+#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
+#define                   nCUDINV  0x0       
+#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
+#define                   nCZMINV  0x0       
+#define                   CNTMODE  0x700      /* Counter Operating Mode */
+#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
+#define                     nZMZC  0x0       
+#define                   BNDMODE  0x3000     /* Boundary register Mode */
+#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
+#define                   nINPDIS  0x0       
+
+/* Bit masks for CNT_IMASK */
+
+#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
+#define                     nICIE  0x0       
+#define                      UCIE  0x2        /* Up count Interrupt Enable */
+#define                     nUCIE  0x0       
+#define                      DCIE  0x4        /* Down count Interrupt Enable */
+#define                     nDCIE  0x0       
+#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
+#define                   nMINCIE  0x0       
+#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
+#define                   nMAXCIE  0x0       
+#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
+#define                  nCOV31IE  0x0       
+#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
+#define                  nCOV15IE  0x0       
+#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
+#define                  nCZEROIE  0x0       
+#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
+#define                    nCZMIE  0x0       
+#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
+#define                   nCZMEIE  0x0       
+#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
+#define                   nCZMZIE  0x0       
+
+/* Bit masks for CNT_STATUS */
+
+#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
+#define                     nICII  0x0       
+#define                      UCII  0x2        /* Up count Interrupt Identifier */
+#define                     nUCII  0x0       
+#define                      DCII  0x4        /* Down count Interrupt Identifier */
+#define                     nDCII  0x0       
+#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
+#define                   nMINCII  0x0       
+#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
+#define                   nMAXCII  0x0       
+#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
+#define                  nCOV31II  0x0       
+#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
+#define                  nCOV15II  0x0       
+#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
+#define                  nCZEROII  0x0       
+#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
+#define                    nCZMII  0x0       
+#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
+#define                   nCZMEII  0x0       
+#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
+#define                   nCZMZII  0x0       
+
+/* Bit masks for CNT_COMMAND */
+
+#define                    W1LCNT  0xf        /* Load Counter Register */
+#define                    W1LMIN  0xf0       /* Load Min Register */
+#define                    W1LMAX  0xf00      /* Load Max Register */
+#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
+#define                 nW1ZMONCE  0x0       
+
+/* Bit masks for CNT_DEBOUNCE */
+
+#define                 DPRESCALE  0xf        /* Load Counter Register */
+
+/* Bit masks for RTC_STAT */
+
+#define                   SECONDS  0x3f       /* Seconds */
+#define                   MINUTES  0xfc0      /* Minutes */
+#define                     HOURS  0x1f000    /* Hours */
+#define               DAY_COUNTER  0xfffe0000 /* Day Counter */
+
+/* Bit masks for RTC_ICTL */
+
+#define STOPWATCH_INTERRUPT_ENABLE  0x1        /* Stopwatch Interrupt Enable */
+#define nSTOPWATCH_INTERRUPT_ENABLE  0x0       
+#define    ALARM_INTERRUPT_ENABLE  0x2        /* Alarm Interrupt Enable */
+#define   nALARM_INTERRUPT_ENABLE  0x0       
+#define  SECONDS_INTERRUPT_ENABLE  0x4        /* Seconds Interrupt Enable */
+#define nSECONDS_INTERRUPT_ENABLE  0x0       
+#define  MINUTES_INTERRUPT_ENABLE  0x8        /* Minutes Interrupt Enable */
+#define nMINUTES_INTERRUPT_ENABLE  0x0       
+#define    HOURS_INTERRUPT_ENABLE  0x10       /* Hours Interrupt Enable */
+#define   nHOURS_INTERRUPT_ENABLE  0x0       
+#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x20       /* 24 Hours Interrupt Enable */
+#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x0       
+#define DAY_ALARM_INTERRUPT_ENABLE  0x40       /* Day Alarm Interrupt Enable */
+#define nDAY_ALARM_INTERRUPT_ENABLE  0x0       
+#define WRITE_COMPLETE_INTERRUPT_ENABLE  0x8000     /* Write Complete Interrupt Enable */
+#define nWRITE_COMPLETE_INTERRUPT_ENABLE  0x0       
+
+/* Bit masks for RTC_ISTAT */
+
+#define      STOPWATCH_EVENT_FLAG  0x1        /* Stopwatch Event Flag */
+#define     nSTOPWATCH_EVENT_FLAG  0x0       
+#define          ALARM_EVENT_FLAG  0x2        /* Alarm Event Flag */
+#define         nALARM_EVENT_FLAG  0x0       
+#define        SECONDS_EVENT_FLAG  0x4        /* Seconds Event Flag */
+#define       nSECONDS_EVENT_FLAG  0x0       
+#define        MINUTES_EVENT_FLAG  0x8        /* Minutes Event Flag */
+#define       nMINUTES_EVENT_FLAG  0x0       
+#define          HOURS_EVENT_FLAG  0x10       /* Hours Event Flag */
+#define         nHOURS_EVENT_FLAG  0x0       
+#define TWENTY_FOUR_HOURS_EVENT_FLAG  0x20       /* 24 Hours Event Flag */
+#define nTWENTY_FOUR_HOURS_EVENT_FLAG  0x0       
+#define      DAY_ALARM_EVENT_FLAG  0x40       /* Day Alarm Event Flag */
+#define     nDAY_ALARM_EVENT_FLAG  0x0       
+#define     WRITE_PENDING__STATUS  0x4000     /* Write Pending  Status */
+#define    nWRITE_PENDING__STATUS  0x0       
+#define            WRITE_COMPLETE  0x8000     /* Write Complete */
+#define           nWRITE_COMPLETE  0x0       
+
+/* Bit masks for RTC_SWCNT */
+
+#define           STOPWATCH_COUNT  0xffff     /* Stopwatch Count */
+
+/* Bit masks for RTC_ALARM */
+
+#define                   SECONDS  0x3f       /* Seconds */
+#define                   MINUTES  0xfc0      /* Minutes */
+#define                     HOURS  0x1f000    /* Hours */
+#define                       DAY  0xfffe0000 /* Day */
+
+/* Bit masks for RTC_PREN */
+
+#define                      PREN  0x1        /* Prescaler Enable */
+#define                     nPREN  0x0       
+
+/* Bit masks for OTP_CONTROL */
+
+#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
+#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
+#define                     nFIEN  0x0       
+#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
+#define                 nFTESTDEC  0x0       
+#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
+#define                  nFWRTEST  0x0       
+#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
+#define                    nFRDEN  0x0       
+#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
+#define                    nFWREN  0x0       
+
+/* Bit masks for OTP_BEN */
+
+#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
+
+/* Bit masks for OTP_STATUS */
+
+#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
+#define                    nFCOMP  0x0       
+#define                    FERROR  0x2        /* OTP/Fuse Access Error */
+#define                   nFERROR  0x0       
+#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
+#define                 nMMRGLOAD  0x0       
+#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
+#define                 nMMRGLOCK  0x0       
+#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
+#define                   nFPGMEN  0x0       
+
+/* Bit masks for OTP_TIMING */
+
+#define                   USECDIV  0xff       /* Micro Second Divider */
+#define                   READACC  0x7f00     /* Read Access Time */
+#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
+#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
+#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
+#define                   PGMTIME  0xff000000 /* Program Time */
+
+/* Bit masks for SECURE_SYSSWT */
+
+#define                   EMUDABL  0x1        /* Emulation Disable. */
+#define                  nEMUDABL  0x0       
+#define                   RSTDABL  0x2        /* Reset Disable */
+#define                  nRSTDABL  0x0       
+#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
+#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
+#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
+#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
+#define                  nDMA0OVR  0x0       
+#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
+#define                  nDMA1OVR  0x0       
+#define                    EMUOVR  0x4000     /* Emulation Override */
+#define                   nEMUOVR  0x0       
+#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
+#define                   nOTPSEN  0x0       
+#define                    L2DABL  0x70000    /* L2 Memory Disable. */
+
+/* Bit masks for SECURE_CONTROL */
+
+#define                   SECURE0  0x1        /* SECURE 0 */
+#define                  nSECURE0  0x0       
+#define                   SECURE1  0x2        /* SECURE 1 */
+#define                  nSECURE1  0x0       
+#define                   SECURE2  0x4        /* SECURE 2 */
+#define                  nSECURE2  0x0       
+#define                   SECURE3  0x8        /* SECURE 3 */
+#define                  nSECURE3  0x0       
+
+/* Bit masks for SECURE_STATUS */
+
+#define                   SECMODE  0x3        /* Secured Mode Control State */
+#define                       NMI  0x4        /* Non Maskable Interrupt */
+#define                      nNMI  0x0       
+#define                   AFVALID  0x8        /* Authentication Firmware Valid */
+#define                  nAFVALID  0x0       
+#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
+#define                   nAFEXIT  0x0       
+#define                   SECSTAT  0xe0       /* Secure Status */
+
+/* Bit masks for PLL_DIV */
+
+#define                      CSEL  0x30       /* Core Select */
+#define                      SSEL  0xf        /* System Select */
+
+/* Bit masks for PLL_CTL */
+
+#define                      MSEL  0x7e00     /* Multiplier Select */
+#define                    BYPASS  0x100      /* PLL Bypass Enable */
+#define                   nBYPASS  0x0       
+#define              OUTPUT_DELAY  0x80       /* External Memory Output Delay Enable */
+#define             nOUTPUT_DELAY  0x0       
+#define               INPUT_DELAY  0x40       /* External Memory Input Delay Enable */
+#define              nINPUT_DELAY  0x0       
+#define                      PDWN  0x20       /* Power Down */
+#define                     nPDWN  0x0       
+#define                    STOPCK  0x8        /* Stop Clock */
+#define                   nSTOPCK  0x0       
+#define                   PLL_OFF  0x2        /* Disable PLL */
+#define                  nPLL_OFF  0x0       
+#define                        DF  0x1        /* Divide Frequency */
+#define                       nDF  0x0       
+
+/* Bit masks for PLL_STAT */
+
+#define                PLL_LOCKED  0x20       /* PLL Locked Status */
+#define               nPLL_LOCKED  0x0       
+#define        ACTIVE_PLLDISABLED  0x4        /* Active Mode With PLL Disabled */
+#define       nACTIVE_PLLDISABLED  0x0       
+#define                   FULL_ON  0x2        /* Full-On Mode */
+#define                  nFULL_ON  0x0       
+#define         ACTIVE_PLLENABLED  0x1        /* Active Mode With PLL Enabled */
+#define        nACTIVE_PLLENABLED  0x0       
+#define                     RTCWS  0x400      /* RTC/Reset Wake-Up Status */
+#define                    nRTCWS  0x0       
+#define                     CANWS  0x800      /* CAN Wake-Up Status */
+#define                    nCANWS  0x0       
+#define                     USBWS  0x2000     /* USB Wake-Up Status */
+#define                    nUSBWS  0x0       
+#define                    KPADWS  0x4000     /* Keypad Wake-Up Status */
+#define                   nKPADWS  0x0       
+#define                     ROTWS  0x8000     /* Rotary Wake-Up Status */
+#define                    nROTWS  0x0       
+#define                      GPWS  0x1000     /* General-Purpose Wake-Up Status */
+#define                     nGPWS  0x0       
+
+/* Bit masks for VR_CTL */
+
+#define                      FREQ  0x3        /* Regulator Switching Frequency */
+#define                      GAIN  0xc        /* Voltage Output Level Gain */
+#define                      VLEV  0xf0       /* Internal Voltage Level */
+#define                   SCKELOW  0x8000     /* Drive SCKE Low During Reset Enable */
+#define                  nSCKELOW  0x0       
+#define                      WAKE  0x100      /* RTC/Reset Wake-Up Enable */
+#define                     nWAKE  0x0       
+#define                     CANWE  0x200      /* CAN0/1 Wake-Up Enable */
+#define                    nCANWE  0x0       
+#define                      GPWE  0x400      /* General-Purpose Wake-Up Enable */
+#define                     nGPWE  0x0       
+#define                     USBWE  0x800      /* USB Wake-Up Enable */
+#define                    nUSBWE  0x0       
+#define                    KPADWE  0x1000     /* Keypad Wake-Up Enable */
+#define                   nKPADWE  0x0       
+#define                     ROTWE  0x2000     /* Rotary Wake-Up Enable */
+#define                    nROTWE  0x0       
+
+/* Bit masks for NFC_CTL */
+
+#define                    WR_DLY  0xf        /* Write Strobe Delay */
+#define                    RD_DLY  0xf0       /* Read Strobe Delay */
+#define                    NWIDTH  0x100      /* NAND Data Width */
+#define                   nNWIDTH  0x0       
+#define                   PG_SIZE  0x200      /* Page Size */
+#define                  nPG_SIZE  0x0       
+
+/* Bit masks for NFC_STAT */
+
+#define                     NBUSY  0x1        /* Not Busy */
+#define                    nNBUSY  0x0       
+#define                   WB_FULL  0x2        /* Write Buffer Full */
+#define                  nWB_FULL  0x0       
+#define                PG_WR_STAT  0x4        /* Page Write Pending */
+#define               nPG_WR_STAT  0x0       
+#define                PG_RD_STAT  0x8        /* Page Read Pending */
+#define               nPG_RD_STAT  0x0       
+#define                  WB_EMPTY  0x10       /* Write Buffer Empty */
+#define                 nWB_EMPTY  0x0       
+
+/* Bit masks for NFC_IRQSTAT */
+
+#define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
+#define                 nNBUSYIRQ  0x0       
+#define                    WB_OVF  0x2        /* Write Buffer Overflow */
+#define                   nWB_OVF  0x0       
+#define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
+#define                  nWB_EDGE  0x0       
+#define                    RD_RDY  0x8        /* Read Data Ready */
+#define                   nRD_RDY  0x0       
+#define                   WR_DONE  0x10       /* Page Write Done */
+#define                  nWR_DONE  0x0       
+
+/* Bit masks for NFC_IRQMASK */
+
+#define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
+#define             nMASK_BUSYIRQ  0x0       
+#define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
+#define               nMASK_WBOVF  0x0       
+#define              MASK_WBEMPTY  0x4        /* Mask Write Buffer Empty */
+#define             nMASK_WBEMPTY  0x0       
+#define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
+#define               nMASK_RDRDY  0x0       
+#define               MASK_WRDONE  0x10       /* Mask Write Done */
+#define              nMASK_WRDONE  0x0       
+
+/* Bit masks for NFC_RST */
+
+#define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
+#define                  nECC_RST  0x0       
+
+/* Bit masks for NFC_PGCTL */
+
+#define               PG_RD_START  0x1        /* Page Read Start */
+#define              nPG_RD_START  0x0       
+#define               PG_WR_START  0x2        /* Page Write Start */
+#define              nPG_WR_START  0x0       
+
+/* Bit masks for NFC_ECC0 */
+
+#define                      ECC0  0x7ff      /* Parity Calculation Result0 */
+
+/* Bit masks for NFC_ECC1 */
+
+#define                      ECC1  0x7ff      /* Parity Calculation Result1 */
+
+/* Bit masks for NFC_ECC2 */
+
+#define                      ECC2  0x7ff      /* Parity Calculation Result2 */
+
+/* Bit masks for NFC_ECC3 */
+
+#define                      ECC3  0x7ff      /* Parity Calculation Result3 */
+
+/* Bit masks for NFC_COUNT */
+
+#define                    ECCCNT  0x3ff      /* Transfer Count */
+
+/* Bit masks for CAN0_CONTROL */
+
+#define                       SRS  0x1        /* Software Reset */
+#define                      nSRS  0x0       
+#define                       DNM  0x2        /* DeviceNet Mode */
+#define                      nDNM  0x0       
+#define                       ABO  0x4        /* Auto Bus On */
+#define                      nABO  0x0       
+#define                       WBA  0x10       /* Wakeup On CAN Bus Activity */
+#define                      nWBA  0x0       
+#define                       SMR  0x20       /* Sleep Mode Request */
+#define                      nSMR  0x0       
+#define                       CSR  0x40       /* CAN Suspend Mode Request */
+#define                      nCSR  0x0       
+#define                       CCR  0x80       /* CAN Configuration Mode Request */
+#define                      nCCR  0x0       
+
+/* Bit masks for CAN0_STATUS */
+
+#define                        WT  0x1        /* CAN Transmit Warning Flag */
+#define                       nWT  0x0       
+#define                        WR  0x2        /* CAN Receive Warning Flag */
+#define                       nWR  0x0       
+#define                        EP  0x4        /* CAN Error Passive Mode */
+#define                       nEP  0x0       
+#define                       EBO  0x8        /* CAN Error Bus Off Mode */
+#define                      nEBO  0x0       
+#define                       CSA  0x40       /* CAN Suspend Mode Acknowledge */
+#define                      nCSA  0x0       
+#define                       CCA  0x80       /* CAN Configuration Mode Acknowledge */
+#define                      nCCA  0x0       
+#define                     MBPTR  0x1f00     /* Mailbox Pointer */
+#define                       TRM  0x4000     /* Transmit Mode Status */
+#define                      nTRM  0x0       
+#define                       REC  0x8000     /* Receive Mode Status */
+#define                      nREC  0x0       
+
+/* Bit masks for CAN0_DEBUG */
+
+#define                       DEC  0x1        /* Disable Transmit/Receive Error Counters */
+#define                      nDEC  0x0       
+#define                       DRI  0x2        /* Disable CANRX Input Pin */
+#define                      nDRI  0x0       
+#define                       DTO  0x4        /* Disable CANTX Output Pin */
+#define                      nDTO  0x0       
+#define                       DIL  0x8        /* Disable Internal Loop */
+#define                      nDIL  0x0       
+#define                       MAA  0x10       /* Mode Auto-Acknowledge */
+#define                      nMAA  0x0       
+#define                       MRB  0x20       /* Mode Read Back */
+#define                      nMRB  0x0       
+#define                       CDE  0x8000     /* CAN Debug Mode Enable */
+#define                      nCDE  0x0       
+
+/* Bit masks for CAN0_CLOCK */
+
+#define                       BRP  0x3ff      /* CAN Bit Rate Prescaler */
+
+/* Bit masks for CAN0_TIMING */
+
+#define                       SJW  0x300      /* Synchronization Jump Width */
+#define                       SAM  0x80       /* Sampling */
+#define                      nSAM  0x0       
+#define                     TSEG2  0x70       /* Time Segment 2 */
+#define                     TSEG1  0xf        /* Time Segment 1 */
+
+/* Bit masks for CAN0_INTR */
+
+#define                     CANRX  0x80       /* Serial Input From Transceiver */
+#define                    nCANRX  0x0       
+#define                     CANTX  0x40       /* Serial Output To Transceiver */
+#define                    nCANTX  0x0       
+#define                     SMACK  0x8        /* Sleep Mode Acknowledge */
+#define                    nSMACK  0x0       
+#define                      GIRQ  0x4        /* Global Interrupt Request Status */
+#define                     nGIRQ  0x0       
+#define                    MBTIRQ  0x2        /* Mailbox Transmit Interrupt Request */
+#define                   nMBTIRQ  0x0       
+#define                    MBRIRQ  0x1        /* Mailbox Receive Interrupt Request */
+#define                   nMBRIRQ  0x0       
+
+/* Bit masks for CAN0_GIM */
+
+#define                     EWTIM  0x1        /* Error Warning Transmit Interrupt Mask */
+#define                    nEWTIM  0x0       
+#define                     EWRIM  0x2        /* Error Warning Receive Interrupt Mask */
+#define                    nEWRIM  0x0       
+#define                      EPIM  0x4        /* Error Passive Interrupt Mask */
+#define                     nEPIM  0x0       
+#define                      BOIM  0x8        /* Bus Off Interrupt Mask */
+#define                     nBOIM  0x0       
+#define                      WUIM  0x10       /* Wakeup Interrupt Mask */
+#define                     nWUIM  0x0       
+#define                     UIAIM  0x20       /* Unimplemented Address Interrupt Mask */
+#define                    nUIAIM  0x0       
+#define                      AAIM  0x40       /* Abort Acknowledge Interrupt Mask */
+#define                     nAAIM  0x0       
+#define                     RMLIM  0x80       /* Receive Message Lost Interrupt Mask */
+#define                    nRMLIM  0x0       
+#define                     UCEIM  0x100      /* Universal Counter Exceeded Interrupt Mask */
+#define                    nUCEIM  0x0       
+#define                      ADIM  0x400      /* Access Denied Interrupt Mask */
+#define                     nADIM  0x0       
+
+/* Bit masks for CAN0_GIS */
+
+#define                     EWTIS  0x1        /* Error Warning Transmit Interrupt Status */
+#define                    nEWTIS  0x0       
+#define                     EWRIS  0x2        /* Error Warning Receive Interrupt Status */
+#define                    nEWRIS  0x0       
+#define                      EPIS  0x4        /* Error Passive Interrupt Status */
+#define                     nEPIS  0x0       
+#define                      BOIS  0x8        /* Bus Off Interrupt Status */
+#define                     nBOIS  0x0       
+#define                      WUIS  0x10       /* Wakeup Interrupt Status */
+#define                     nWUIS  0x0       
+#define                     UIAIS  0x20       /* Unimplemented Address Interrupt Status */
+#define                    nUIAIS  0x0       
+#define                      AAIS  0x40       /* Abort Acknowledge Interrupt Status */
+#define                     nAAIS  0x0       
+#define                     RMLIS  0x80       /* Receive Message Lost Interrupt Status */
+#define                    nRMLIS  0x0       
+#define                     UCEIS  0x100      /* Universal Counter Exceeded Interrupt Status */
+#define                    nUCEIS  0x0       
+#define                      ADIS  0x400      /* Access Denied Interrupt Status */
+#define                     nADIS  0x0       
+
+/* Bit masks for CAN0_GIF */
+
+#define                     EWTIF  0x1        /* Error Warning Transmit Interrupt Flag */
+#define                    nEWTIF  0x0       
+#define                     EWRIF  0x2        /* Error Warning Receive Interrupt Flag */
+#define                    nEWRIF  0x0       
+#define                      EPIF  0x4        /* Error Passive Interrupt Flag */
+#define                     nEPIF  0x0       
+#define                      BOIF  0x8        /* Bus Off Interrupt Flag */
+#define                     nBOIF  0x0       
+#define                      WUIF  0x10       /* Wakeup Interrupt Flag */
+#define                     nWUIF  0x0       
+#define                     UIAIF  0x20       /* Unimplemented Address Interrupt Flag */
+#define                    nUIAIF  0x0       
+#define                      AAIF  0x40       /* Abort Acknowledge Interrupt Flag */
+#define                     nAAIF  0x0       
+#define                     RMLIF  0x80       /* Receive Message Lost Interrupt Flag */
+#define                    nRMLIF  0x0       
+#define                     UCEIF  0x100      /* Universal Counter Exceeded Interrupt Flag */
+#define                    nUCEIF  0x0       
+#define                      ADIF  0x400      /* Access Denied Interrupt Flag */
+#define                     nADIF  0x0       
+
+/* Bit masks for CAN0_MBTD */
+
+#define                       TDR  0x80       /* Temporary Disable Request */
+#define                      nTDR  0x0       
+#define                       TDA  0x40       /* Temporary Disable Acknowledge */
+#define                      nTDA  0x0       
+#define                     TDPTR  0x1f       /* Temporary Disable Pointer */
+
+/* Bit masks for CAN0_UCCNF */
+
+#define                     UCCNF  0xf        /* Universal Counter Configuration */
+#define                      UCRC  0x20       /* Universal Counter Reload/Clear */
+#define                     nUCRC  0x0       
+#define                      UCCT  0x40       /* Universal Counter CAN Trigger */
+#define                     nUCCT  0x0       
+#define                       UCE  0x80       /* Universal Counter Enable */
+#define                      nUCE  0x0       
+
+/* Bit masks for CAN0_UCCNT */
+
+#define                     UCCNT  0xffff     /* Universal Counter Count Value */
+
+/* Bit masks for CAN0_UCRC */
+
+#define                     UCVAL  0xffff     /* Universal Counter Reload/Capture Value */
+
+/* Bit masks for CAN0_CEC */
+
+#define                    RXECNT  0xff       /* Receive Error Counter */
+#define                    TXECNT  0xff00     /* Transmit Error Counter */
+
+/* Bit masks for CAN0_ESR */
+
+#define                       FER  0x80       /* Form Error */
+#define                      nFER  0x0       
+#define                       BEF  0x40       /* Bit Error Flag */
+#define                      nBEF  0x0       
+#define                       SA0  0x20       /* Stuck At Dominant */
+#define                      nSA0  0x0       
+#define                      CRCE  0x10       /* CRC Error */
+#define                     nCRCE  0x0       
+#define                       SER  0x8        /* Stuff Bit Error */
+#define                      nSER  0x0       
+#define                      ACKE  0x4        /* Acknowledge Error */
+#define                     nACKE  0x0       
+
+/* Bit masks for CAN0_EWR */
+
+#define                    EWLTEC  0xff00     /* Transmit Error Warning Limit */
+#define                    EWLREC  0xff       /* Receive Error Warning Limit */
+
+/* Bit masks for CAN0_AMxx_H */
+
+#define                       FDF  0x8000     /* Filter On Data Field */
+#define                      nFDF  0x0       
+#define                       FMD  0x4000     /* Full Mask Data */
+#define                      nFMD  0x0       
+#define                     AMIDE  0x2000     /* Acceptance Mask Identifier Extension */
+#define                    nAMIDE  0x0       
+#define                    BASEID  0x1ffc     /* Base Identifier */
+#define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
+
+/* Bit masks for CAN0_AMxx_L */
+
+#define                  EXTID_LO  0xffff     /* Extended Identifier Low Bits */
+#define                       DFM  0xffff     /* Data Field Mask */
+
+/* Bit masks for CAN0_MBxx_ID1 */
+
+#define                       AME  0x8000     /* Acceptance Mask Enable */
+#define                      nAME  0x0       
+#define                       RTR  0x4000     /* Remote Transmission Request */
+#define                      nRTR  0x0       
+#define                       IDE  0x2000     /* Identifier Extension */
+#define                      nIDE  0x0       
+#define                    BASEID  0x1ffc     /* Base Identifier */
+#define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
+
+/* Bit masks for CAN0_MBxx_ID0 */
+
+#define                  EXTID_LO  0xffff     /* Extended Identifier Low Bits */
+#define                       DFM  0xffff     /* Data Field Mask */
+
+/* Bit masks for CAN0_MBxx_TIMESTAMP */
+
+#define                       TSV  0xffff     /* Time Stamp Value */
+
+/* Bit masks for CAN0_MBxx_LENGTH */
+
+#define                       DLC  0xf        /* Data Length Code */
+
+/* Bit masks for CAN0_MBxx_DATA3 */
+
+#define                 CAN_BYTE0  0xff00     /* Data Field Byte 0 */
+#define                 CAN_BYTE1  0xff       /* Data Field Byte 1 */
+
+/* Bit masks for CAN0_MBxx_DATA2 */
+
+#define                 CAN_BYTE2  0xff00     /* Data Field Byte 2 */
+#define                 CAN_BYTE3  0xff       /* Data Field Byte 3 */
+
+/* Bit masks for CAN0_MBxx_DATA1 */
+
+#define                 CAN_BYTE4  0xff00     /* Data Field Byte 4 */
+#define                 CAN_BYTE5  0xff       /* Data Field Byte 5 */
+
+/* Bit masks for CAN0_MBxx_DATA0 */
+
+#define                 CAN_BYTE6  0xff00     /* Data Field Byte 6 */
+#define                 CAN_BYTE7  0xff       /* Data Field Byte 7 */
+
+/* Bit masks for CAN0_MC1 */
+
+#define                       MC0  0x1        /* Mailbox 0 Enable */
+#define                      nMC0  0x0       
+#define                       MC1  0x2        /* Mailbox 1 Enable */
+#define                      nMC1  0x0       
+#define                       MC2  0x4        /* Mailbox 2 Enable */
+#define                      nMC2  0x0       
+#define                       MC3  0x8        /* Mailbox 3 Enable */
+#define                      nMC3  0x0       
+#define                       MC4  0x10       /* Mailbox 4 Enable */
+#define                      nMC4  0x0       
+#define                       MC5  0x20       /* Mailbox 5 Enable */
+#define                      nMC5  0x0       
+#define                       MC6  0x40       /* Mailbox 6 Enable */
+#define                      nMC6  0x0       
+#define                       MC7  0x80       /* Mailbox 7 Enable */
+#define                      nMC7  0x0       
+#define                       MC8  0x100      /* Mailbox 8 Enable */
+#define                      nMC8  0x0       
+#define                       MC9  0x200      /* Mailbox 9 Enable */
+#define                      nMC9  0x0       
+#define                      MC10  0x400      /* Mailbox 10 Enable */
+#define                     nMC10  0x0       
+#define                      MC11  0x800      /* Mailbox 11 Enable */
+#define                     nMC11  0x0       
+#define                      MC12  0x1000     /* Mailbox 12 Enable */
+#define                     nMC12  0x0       
+#define                      MC13  0x2000     /* Mailbox 13 Enable */
+#define                     nMC13  0x0       
+#define                      MC14  0x4000     /* Mailbox 14 Enable */
+#define                     nMC14  0x0       
+#define                      MC15  0x8000     /* Mailbox 15 Enable */
+#define                     nMC15  0x0       
+
+/* Bit masks for CAN0_MC2 */
+
+#define                      MC16  0x1        /* Mailbox 16 Enable */
+#define                     nMC16  0x0       
+#define                      MC17  0x2        /* Mailbox 17 Enable */
+#define                     nMC17  0x0       
+#define                      MC18  0x4        /* Mailbox 18 Enable */
+#define                     nMC18  0x0       
+#define                      MC19  0x8        /* Mailbox 19 Enable */
+#define                     nMC19  0x0       
+#define                      MC20  0x10       /* Mailbox 20 Enable */
+#define                     nMC20  0x0       
+#define                      MC21  0x20       /* Mailbox 21 Enable */
+#define                     nMC21  0x0       
+#define                      MC22  0x40       /* Mailbox 22 Enable */
+#define                     nMC22  0x0       
+#define                      MC23  0x80       /* Mailbox 23 Enable */
+#define                     nMC23  0x0       
+#define                      MC24  0x100      /* Mailbox 24 Enable */
+#define                     nMC24  0x0       
+#define                      MC25  0x200      /* Mailbox 25 Enable */
+#define                     nMC25  0x0       
+#define                      MC26  0x400      /* Mailbox 26 Enable */
+#define                     nMC26  0x0       
+#define                      MC27  0x800      /* Mailbox 27 Enable */
+#define                     nMC27  0x0       
+#define                      MC28  0x1000     /* Mailbox 28 Enable */
+#define                     nMC28  0x0       
+#define                      MC29  0x2000     /* Mailbox 29 Enable */
+#define                     nMC29  0x0       
+#define                      MC30  0x4000     /* Mailbox 30 Enable */
+#define                     nMC30  0x0       
+#define                      MC31  0x8000     /* Mailbox 31 Enable */
+#define                     nMC31  0x0       
+
+/* Bit masks for CAN0_MD1 */
+
+#define                       MD0  0x1        /* Mailbox 0 Receive Enable */
+#define                      nMD0  0x0       
+#define                       MD1  0x2        /* Mailbox 1 Receive Enable */
+#define                      nMD1  0x0       
+#define                       MD2  0x4        /* Mailbox 2 Receive Enable */
+#define                      nMD2  0x0       
+#define                       MD3  0x8        /* Mailbox 3 Receive Enable */
+#define                      nMD3  0x0       
+#define                       MD4  0x10       /* Mailbox 4 Receive Enable */
+#define                      nMD4  0x0       
+#define                       MD5  0x20       /* Mailbox 5 Receive Enable */
+#define                      nMD5  0x0       
+#define                       MD6  0x40       /* Mailbox 6 Receive Enable */
+#define                      nMD6  0x0       
+#define                       MD7  0x80       /* Mailbox 7 Receive Enable */
+#define                      nMD7  0x0       
+#define                       MD8  0x100      /* Mailbox 8 Receive Enable */
+#define                      nMD8  0x0       
+#define                       MD9  0x200      /* Mailbox 9 Receive Enable */
+#define                      nMD9  0x0       
+#define                      MD10  0x400      /* Mailbox 10 Receive Enable */
+#define                     nMD10  0x0       
+#define                      MD11  0x800      /* Mailbox 11 Receive Enable */
+#define                     nMD11  0x0       
+#define                      MD12  0x1000     /* Mailbox 12 Receive Enable */
+#define                     nMD12  0x0       
+#define                      MD13  0x2000     /* Mailbox 13 Receive Enable */
+#define                     nMD13  0x0       
+#define                      MD14  0x4000     /* Mailbox 14 Receive Enable */
+#define                     nMD14  0x0       
+#define                      MD15  0x8000     /* Mailbox 15 Receive Enable */
+#define                     nMD15  0x0       
+
+/* Bit masks for CAN0_MD2 */
+
+#define                      MD16  0x1        /* Mailbox 16 Receive Enable */
+#define                     nMD16  0x0       
+#define                      MD17  0x2        /* Mailbox 17 Receive Enable */
+#define                     nMD17  0x0       
+#define                      MD18  0x4        /* Mailbox 18 Receive Enable */
+#define                     nMD18  0x0       
+#define                      MD19  0x8        /* Mailbox 19 Receive Enable */
+#define                     nMD19  0x0       
+#define                      MD20  0x10       /* Mailbox 20 Receive Enable */
+#define                     nMD20  0x0       
+#define                      MD21  0x20       /* Mailbox 21 Receive Enable */
+#define                     nMD21  0x0       
+#define                      MD22  0x40       /* Mailbox 22 Receive Enable */
+#define                     nMD22  0x0       
+#define                      MD23  0x80       /* Mailbox 23 Receive Enable */
+#define                     nMD23  0x0       
+#define                      MD24  0x100      /* Mailbox 24 Receive Enable */
+#define                     nMD24  0x0       
+#define                      MD25  0x200      /* Mailbox 25 Receive Enable */
+#define                     nMD25  0x0       
+#define                      MD26  0x400      /* Mailbox 26 Receive Enable */
+#define                     nMD26  0x0       
+#define                      MD27  0x800      /* Mailbox 27 Receive Enable */
+#define                     nMD27  0x0       
+#define                      MD28  0x1000     /* Mailbox 28 Receive Enable */
+#define                     nMD28  0x0       
+#define                      MD29  0x2000     /* Mailbox 29 Receive Enable */
+#define                     nMD29  0x0       
+#define                      MD30  0x4000     /* Mailbox 30 Receive Enable */
+#define                     nMD30  0x0       
+#define                      MD31  0x8000     /* Mailbox 31 Receive Enable */
+#define                     nMD31  0x0       
+
+/* Bit masks for CAN0_RMP1 */
+
+#define                      RMP0  0x1        /* Mailbox 0 Receive Message Pending */
+#define                     nRMP0  0x0       
+#define                      RMP1  0x2        /* Mailbox 1 Receive Message Pending */
+#define                     nRMP1  0x0       
+#define                      RMP2  0x4        /* Mailbox 2 Receive Message Pending */
+#define                     nRMP2  0x0       
+#define                      RMP3  0x8        /* Mailbox 3 Receive Message Pending */
+#define                     nRMP3  0x0       
+#define                      RMP4  0x10       /* Mailbox 4 Receive Message Pending */
+#define                     nRMP4  0x0       
+#define                      RMP5  0x20       /* Mailbox 5 Receive Message Pending */
+#define                     nRMP5  0x0       
+#define                      RMP6  0x40       /* Mailbox 6 Receive Message Pending */
+#define                     nRMP6  0x0       
+#define                      RMP7  0x80       /* Mailbox 7 Receive Message Pending */
+#define                     nRMP7  0x0       
+#define                      RMP8  0x100      /* Mailbox 8 Receive Message Pending */
+#define                     nRMP8  0x0       
+#define                      RMP9  0x200      /* Mailbox 9 Receive Message Pending */
+#define                     nRMP9  0x0       
+#define                     RMP10  0x400      /* Mailbox 10 Receive Message Pending */
+#define                    nRMP10  0x0       
+#define                     RMP11  0x800      /* Mailbox 11 Receive Message Pending */
+#define                    nRMP11  0x0       
+#define                     RMP12  0x1000     /* Mailbox 12 Receive Message Pending */
+#define                    nRMP12  0x0       
+#define                     RMP13  0x2000     /* Mailbox 13 Receive Message Pending */
+#define                    nRMP13  0x0       
+#define                     RMP14  0x4000     /* Mailbox 14 Receive Message Pending */
+#define                    nRMP14  0x0       
+#define                     RMP15  0x8000     /* Mailbox 15 Receive Message Pending */
+#define                    nRMP15  0x0       
+
+/* Bit masks for CAN0_RMP2 */
+
+#define                     RMP16  0x1        /* Mailbox 16 Receive Message Pending */
+#define                    nRMP16  0x0       
+#define                     RMP17  0x2        /* Mailbox 17 Receive Message Pending */
+#define                    nRMP17  0x0       
+#define                     RMP18  0x4        /* Mailbox 18 Receive Message Pending */
+#define                    nRMP18  0x0       
+#define                     RMP19  0x8        /* Mailbox 19 Receive Message Pending */
+#define                    nRMP19  0x0       
+#define                     RMP20  0x10       /* Mailbox 20 Receive Message Pending */
+#define                    nRMP20  0x0       
+#define                     RMP21  0x20       /* Mailbox 21 Receive Message Pending */
+#define                    nRMP21  0x0       
+#define                     RMP22  0x40       /* Mailbox 22 Receive Message Pending */
+#define                    nRMP22  0x0       
+#define                     RMP23  0x80       /* Mailbox 23 Receive Message Pending */
+#define                    nRMP23  0x0       
+#define                     RMP24  0x100      /* Mailbox 24 Receive Message Pending */
+#define                    nRMP24  0x0       
+#define                     RMP25  0x200      /* Mailbox 25 Receive Message Pending */
+#define                    nRMP25  0x0       
+#define                     RMP26  0x400      /* Mailbox 26 Receive Message Pending */
+#define                    nRMP26  0x0       
+#define                     RMP27  0x800      /* Mailbox 27 Receive Message Pending */
+#define                    nRMP27  0x0       
+#define                     RMP28  0x1000     /* Mailbox 28 Receive Message Pending */
+#define                    nRMP28  0x0       
+#define                     RMP29  0x2000     /* Mailbox 29 Receive Message Pending */
+#define                    nRMP29  0x0       
+#define                     RMP30  0x4000     /* Mailbox 30 Receive Message Pending */
+#define                    nRMP30  0x0       
+#define                     RMP31  0x8000     /* Mailbox 31 Receive Message Pending */
+#define                    nRMP31  0x0       
+
+/* Bit masks for CAN0_RML1 */
+
+#define                      RML0  0x1        /* Mailbox 0 Receive Message Lost */
+#define                     nRML0  0x0       
+#define                      RML1  0x2        /* Mailbox 1 Receive Message Lost */
+#define                     nRML1  0x0       
+#define                      RML2  0x4        /* Mailbox 2 Receive Message Lost */
+#define                     nRML2  0x0       
+#define                      RML3  0x8        /* Mailbox 3 Receive Message Lost */
+#define                     nRML3  0x0       
+#define                      RML4  0x10       /* Mailbox 4 Receive Message Lost */
+#define                     nRML4  0x0       
+#define                      RML5  0x20       /* Mailbox 5 Receive Message Lost */
+#define                     nRML5  0x0       
+#define                      RML6  0x40       /* Mailbox 6 Receive Message Lost */
+#define                     nRML6  0x0       
+#define                      RML7  0x80       /* Mailbox 7 Receive Message Lost */
+#define                     nRML7  0x0       
+#define                      RML8  0x100      /* Mailbox 8 Receive Message Lost */
+#define                     nRML8  0x0       
+#define                      RML9  0x200      /* Mailbox 9 Receive Message Lost */
+#define                     nRML9  0x0       
+#define                     RML10  0x400      /* Mailbox 10 Receive Message Lost */
+#define                    nRML10  0x0       
+#define                     RML11  0x800      /* Mailbox 11 Receive Message Lost */
+#define                    nRML11  0x0       
+#define                     RML12  0x1000     /* Mailbox 12 Receive Message Lost */
+#define                    nRML12  0x0       
+#define                     RML13  0x2000     /* Mailbox 13 Receive Message Lost */
+#define                    nRML13  0x0       
+#define                     RML14  0x4000     /* Mailbox 14 Receive Message Lost */
+#define                    nRML14  0x0       
+#define                     RML15  0x8000     /* Mailbox 15 Receive Message Lost */
+#define                    nRML15  0x0       
+
+/* Bit masks for CAN0_RML2 */
+
+#define                     RML16  0x1        /* Mailbox 16 Receive Message Lost */
+#define                    nRML16  0x0       
+#define                     RML17  0x2        /* Mailbox 17 Receive Message Lost */
+#define                    nRML17  0x0       
+#define                     RML18  0x4        /* Mailbox 18 Receive Message Lost */
+#define                    nRML18  0x0       
+#define                     RML19  0x8        /* Mailbox 19 Receive Message Lost */
+#define                    nRML19  0x0       
+#define                     RML20  0x10       /* Mailbox 20 Receive Message Lost */
+#define                    nRML20  0x0       
+#define                     RML21  0x20       /* Mailbox 21 Receive Message Lost */
+#define                    nRML21  0x0       
+#define                     RML22  0x40       /* Mailbox 22 Receive Message Lost */
+#define                    nRML22  0x0       
+#define                     RML23  0x80       /* Mailbox 23 Receive Message Lost */
+#define                    nRML23  0x0       
+#define                     RML24  0x100      /* Mailbox 24 Receive Message Lost */
+#define                    nRML24  0x0       
+#define                     RML25  0x200      /* Mailbox 25 Receive Message Lost */
+#define                    nRML25  0x0       
+#define                     RML26  0x400      /* Mailbox 26 Receive Message Lost */
+#define                    nRML26  0x0       
+#define                     RML27  0x800      /* Mailbox 27 Receive Message Lost */
+#define                    nRML27  0x0       
+#define                     RML28  0x1000     /* Mailbox 28 Receive Message Lost */
+#define                    nRML28  0x0       
+#define                     RML29  0x2000     /* Mailbox 29 Receive Message Lost */
+#define                    nRML29  0x0       
+#define                     RML30  0x4000     /* Mailbox 30 Receive Message Lost */
+#define                    nRML30  0x0       
+#define                     RML31  0x8000     /* Mailbox 31 Receive Message Lost */
+#define                    nRML31  0x0       
+
+/* Bit masks for CAN0_OPSS1 */
+
+#define                     OPSS0  0x1        /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
+#define                    nOPSS0  0x0       
+#define                     OPSS1  0x2        /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
+#define                    nOPSS1  0x0       
+#define                     OPSS2  0x4        /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
+#define                    nOPSS2  0x0       
+#define                     OPSS3  0x8        /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
+#define                    nOPSS3  0x0       
+#define                     OPSS4  0x10       /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
+#define                    nOPSS4  0x0       
+#define                     OPSS5  0x20       /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
+#define                    nOPSS5  0x0       
+#define                     OPSS6  0x40       /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
+#define                    nOPSS6  0x0       
+#define                     OPSS7  0x80       /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
+#define                    nOPSS7  0x0       
+#define                     OPSS8  0x100      /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
+#define                    nOPSS8  0x0       
+#define                     OPSS9  0x200      /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
+#define                    nOPSS9  0x0       
+#define                    OPSS10  0x400      /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS10  0x0       
+#define                    OPSS11  0x800      /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS11  0x0       
+#define                    OPSS12  0x1000     /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS12  0x0       
+#define                    OPSS13  0x2000     /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS13  0x0       
+#define                    OPSS14  0x4000     /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS14  0x0       
+#define                    OPSS15  0x8000     /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS15  0x0       
+
+/* Bit masks for CAN0_OPSS2 */
+
+#define                    OPSS16  0x1        /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS16  0x0       
+#define                    OPSS17  0x2        /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS17  0x0       
+#define                    OPSS18  0x4        /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS18  0x0       
+#define                    OPSS19  0x8        /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS19  0x0       
+#define                    OPSS20  0x10       /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS20  0x0       
+#define                    OPSS21  0x20       /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS21  0x0       
+#define                    OPSS22  0x40       /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS22  0x0       
+#define                    OPSS23  0x80       /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS23  0x0       
+#define                    OPSS24  0x100      /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS24  0x0       
+#define                    OPSS25  0x200      /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS25  0x0       
+#define                    OPSS26  0x400      /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS26  0x0       
+#define                    OPSS27  0x800      /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS27  0x0       
+#define                    OPSS28  0x1000     /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS28  0x0       
+#define                    OPSS29  0x2000     /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS29  0x0       
+#define                    OPSS30  0x4000     /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS30  0x0       
+#define                    OPSS31  0x8000     /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
+#define                   nOPSS31  0x0       
+
+/* Bit masks for CAN0_TRS1 */
+
+#define                      TRS0  0x1        /* Mailbox 0 Transmit Request Set */
+#define                     nTRS0  0x0       
+#define                      TRS1  0x2        /* Mailbox 1 Transmit Request Set */
+#define                     nTRS1  0x0       
+#define                      TRS2  0x4        /* Mailbox 2 Transmit Request Set */
+#define                     nTRS2  0x0       
+#define                      TRS3  0x8        /* Mailbox 3 Transmit Request Set */
+#define                     nTRS3  0x0       
+#define                      TRS4  0x10       /* Mailbox 4 Transmit Request Set */
+#define                     nTRS4  0x0       
+#define                      TRS5  0x20       /* Mailbox 5 Transmit Request Set */
+#define                     nTRS5  0x0       
+#define                      TRS6  0x40       /* Mailbox 6 Transmit Request Set */
+#define                     nTRS6  0x0       
+#define                      TRS7  0x80       /* Mailbox 7 Transmit Request Set */
+#define                     nTRS7  0x0       
+#define                      TRS8  0x100      /* Mailbox 8 Transmit Request Set */
+#define                     nTRS8  0x0       
+#define                      TRS9  0x200      /* Mailbox 9 Transmit Request Set */
+#define                     nTRS9  0x0       
+#define                     TRS10  0x400      /* Mailbox 10 Transmit Request Set */
+#define                    nTRS10  0x0       
+#define                     TRS11  0x800      /* Mailbox 11 Transmit Request Set */
+#define                    nTRS11  0x0       
+#define                     TRS12  0x1000     /* Mailbox 12 Transmit Request Set */
+#define                    nTRS12  0x0       
+#define                     TRS13  0x2000     /* Mailbox 13 Transmit Request Set */
+#define                    nTRS13  0x0       
+#define                     TRS14  0x4000     /* Mailbox 14 Transmit Request Set */
+#define                    nTRS14  0x0       
+#define                     TRS15  0x8000     /* Mailbox 15 Transmit Request Set */
+#define                    nTRS15  0x0       
+
+/* Bit masks for CAN0_TRS2 */
+
+#define                     TRS16  0x1        /* Mailbox 16 Transmit Request Set */
+#define                    nTRS16  0x0       
+#define                     TRS17  0x2        /* Mailbox 17 Transmit Request Set */
+#define                    nTRS17  0x0       
+#define                     TRS18  0x4        /* Mailbox 18 Transmit Request Set */
+#define                    nTRS18  0x0       
+#define                     TRS19  0x8        /* Mailbox 19 Transmit Request Set */
+#define                    nTRS19  0x0       
+#define                     TRS20  0x10       /* Mailbox 20 Transmit Request Set */
+#define                    nTRS20  0x0       
+#define                     TRS21  0x20       /* Mailbox 21 Transmit Request Set */
+#define                    nTRS21  0x0       
+#define                     TRS22  0x40       /* Mailbox 22 Transmit Request Set */
+#define                    nTRS22  0x0       
+#define                     TRS23  0x80       /* Mailbox 23 Transmit Request Set */
+#define                    nTRS23  0x0       
+#define                     TRS24  0x100      /* Mailbox 24 Transmit Request Set */
+#define                    nTRS24  0x0       
+#define                     TRS25  0x200      /* Mailbox 25 Transmit Request Set */
+#define                    nTRS25  0x0       
+#define                     TRS26  0x400      /* Mailbox 26 Transmit Request Set */
+#define                    nTRS26  0x0       
+#define                     TRS27  0x800      /* Mailbox 27 Transmit Request Set */
+#define                    nTRS27  0x0       
+#define                     TRS28  0x1000     /* Mailbox 28 Transmit Request Set */
+#define                    nTRS28  0x0       
+#define                     TRS29  0x2000     /* Mailbox 29 Transmit Request Set */
+#define                    nTRS29  0x0       
+#define                     TRS30  0x4000     /* Mailbox 30 Transmit Request Set */
+#define                    nTRS30  0x0       
+#define                     TRS31  0x8000     /* Mailbox 31 Transmit Request Set */
+#define                    nTRS31  0x0       
+
+/* Bit masks for CAN0_TRR1 */
+
+#define                      TRR0  0x1        /* Mailbox 0 Transmit Request Reset */
+#define                     nTRR0  0x0       
+#define                      TRR1  0x2        /* Mailbox 1 Transmit Request Reset */
+#define                     nTRR1  0x0       
+#define                      TRR2  0x4        /* Mailbox 2 Transmit Request Reset */
+#define                     nTRR2  0x0       
+#define                      TRR3  0x8        /* Mailbox 3 Transmit Request Reset */
+#define                     nTRR3  0x0       
+#define                      TRR4  0x10       /* Mailbox 4 Transmit Request Reset */
+#define                     nTRR4  0x0       
+#define                      TRR5  0x20       /* Mailbox 5 Transmit Request Reset */
+#define                     nTRR5  0x0       
+#define                      TRR6  0x40       /* Mailbox 6 Transmit Request Reset */
+#define                     nTRR6  0x0       
+#define                      TRR7  0x80       /* Mailbox 7 Transmit Request Reset */
+#define                     nTRR7  0x0       
+#define                      TRR8  0x100      /* Mailbox 8 Transmit Request Reset */
+#define                     nTRR8  0x0       
+#define                      TRR9  0x200      /* Mailbox 9 Transmit Request Reset */
+#define                     nTRR9  0x0       
+#define                     TRR10  0x400      /* Mailbox 10 Transmit Request Reset */
+#define                    nTRR10  0x0       
+#define                     TRR11  0x800      /* Mailbox 11 Transmit Request Reset */
+#define                    nTRR11  0x0       
+#define                     TRR12  0x1000     /* Mailbox 12 Transmit Request Reset */
+#define                    nTRR12  0x0       
+#define                     TRR13  0x2000     /* Mailbox 13 Transmit Request Reset */
+#define                    nTRR13  0x0       
+#define                     TRR14  0x4000     /* Mailbox 14 Transmit Request Reset */
+#define                    nTRR14  0x0       
+#define                     TRR15  0x8000     /* Mailbox 15 Transmit Request Reset */
+#define                    nTRR15  0x0       
+
+/* Bit masks for CAN0_TRR2 */
+
+#define                     TRR16  0x1        /* Mailbox 16 Transmit Request Reset */
+#define                    nTRR16  0x0       
+#define                     TRR17  0x2        /* Mailbox 17 Transmit Request Reset */
+#define                    nTRR17  0x0       
+#define                     TRR18  0x4        /* Mailbox 18 Transmit Request Reset */
+#define                    nTRR18  0x0       
+#define                     TRR19  0x8        /* Mailbox 19 Transmit Request Reset */
+#define                    nTRR19  0x0       
+#define                     TRR20  0x10       /* Mailbox 20 Transmit Request Reset */
+#define                    nTRR20  0x0       
+#define                     TRR21  0x20       /* Mailbox 21 Transmit Request Reset */
+#define                    nTRR21  0x0       
+#define                     TRR22  0x40       /* Mailbox 22 Transmit Request Reset */
+#define                    nTRR22  0x0       
+#define                     TRR23  0x80       /* Mailbox 23 Transmit Request Reset */
+#define                    nTRR23  0x0       
+#define                     TRR24  0x100      /* Mailbox 24 Transmit Request Reset */
+#define                    nTRR24  0x0       
+#define                     TRR25  0x200      /* Mailbox 25 Transmit Request Reset */
+#define                    nTRR25  0x0       
+#define                     TRR26  0x400      /* Mailbox 26 Transmit Request Reset */
+#define                    nTRR26  0x0       
+#define                     TRR27  0x800      /* Mailbox 27 Transmit Request Reset */
+#define                    nTRR27  0x0       
+#define                     TRR28  0x1000     /* Mailbox 28 Transmit Request Reset */
+#define                    nTRR28  0x0       
+#define                     TRR29  0x2000     /* Mailbox 29 Transmit Request Reset */
+#define                    nTRR29  0x0       
+#define                     TRR30  0x4000     /* Mailbox 30 Transmit Request Reset */
+#define                    nTRR30  0x0       
+#define                     TRR31  0x8000     /* Mailbox 31 Transmit Request Reset */
+#define                    nTRR31  0x0       
+
+/* Bit masks for CAN0_AA1 */
+
+#define                       AA0  0x1        /* Mailbox 0 Abort Acknowledge */
+#define                      nAA0  0x0       
+#define                       AA1  0x2        /* Mailbox 1 Abort Acknowledge */
+#define                      nAA1  0x0       
+#define                       AA2  0x4        /* Mailbox 2 Abort Acknowledge */
+#define                      nAA2  0x0       
+#define                       AA3  0x8        /* Mailbox 3 Abort Acknowledge */
+#define                      nAA3  0x0       
+#define                       AA4  0x10       /* Mailbox 4 Abort Acknowledge */
+#define                      nAA4  0x0       
+#define                       AA5  0x20       /* Mailbox 5 Abort Acknowledge */
+#define                      nAA5  0x0       
+#define                       AA6  0x40       /* Mailbox 6 Abort Acknowledge */
+#define                      nAA6  0x0       
+#define                       AA7  0x80       /* Mailbox 7 Abort Acknowledge */
+#define                      nAA7  0x0       
+#define                       AA8  0x100      /* Mailbox 8 Abort Acknowledge */
+#define                      nAA8  0x0       
+#define                       AA9  0x200      /* Mailbox 9 Abort Acknowledge */
+#define                      nAA9  0x0       
+#define                      AA10  0x400      /* Mailbox 10 Abort Acknowledge */
+#define                     nAA10  0x0       
+#define                      AA11  0x800      /* Mailbox 11 Abort Acknowledge */
+#define                     nAA11  0x0       
+#define                      AA12  0x1000     /* Mailbox 12 Abort Acknowledge */
+#define                     nAA12  0x0       
+#define                      AA13  0x2000     /* Mailbox 13 Abort Acknowledge */
+#define                     nAA13  0x0       
+#define                      AA14  0x4000     /* Mailbox 14 Abort Acknowledge */
+#define                     nAA14  0x0       
+#define                      AA15  0x8000     /* Mailbox 15 Abort Acknowledge */
+#define                     nAA15  0x0       
+
+/* Bit masks for CAN0_AA2 */
+
+#define                      AA16  0x1        /* Mailbox 16 Abort Acknowledge */
+#define                     nAA16  0x0       
+#define                      AA17  0x2        /* Mailbox 17 Abort Acknowledge */
+#define                     nAA17  0x0       
+#define                      AA18  0x4        /* Mailbox 18 Abort Acknowledge */
+#define                     nAA18  0x0       
+#define                      AA19  0x8        /* Mailbox 19 Abort Acknowledge */
+#define                     nAA19  0x0       
+#define                      AA20  0x10       /* Mailbox 20 Abort Acknowledge */
+#define                     nAA20  0x0       
+#define                      AA21  0x20       /* Mailbox 21 Abort Acknowledge */
+#define                     nAA21  0x0       
+#define                      AA22  0x40       /* Mailbox 22 Abort Acknowledge */
+#define                     nAA22  0x0       
+#define                      AA23  0x80       /* Mailbox 23 Abort Acknowledge */
+#define                     nAA23  0x0       
+#define                      AA24  0x100      /* Mailbox 24 Abort Acknowledge */
+#define                     nAA24  0x0       
+#define                      AA25  0x200      /* Mailbox 25 Abort Acknowledge */
+#define                     nAA25  0x0       
+#define                      AA26  0x400      /* Mailbox 26 Abort Acknowledge */
+#define                     nAA26  0x0       
+#define                      AA27  0x800      /* Mailbox 27 Abort Acknowledge */
+#define                     nAA27  0x0       
+#define                      AA28  0x1000     /* Mailbox 28 Abort Acknowledge */
+#define                     nAA28  0x0       
+#define                      AA29  0x2000     /* Mailbox 29 Abort Acknowledge */
+#define                     nAA29  0x0       
+#define                      AA30  0x4000     /* Mailbox 30 Abort Acknowledge */
+#define                     nAA30  0x0       
+#define                      AA31  0x8000     /* Mailbox 31 Abort Acknowledge */
+#define                     nAA31  0x0       
+
+/* Bit masks for CAN0_TA1 */
+
+#define                       TA0  0x1        /* Mailbox 0 Transmit Acknowledge */
+#define                      nTA0  0x0       
+#define                       TA1  0x2        /* Mailbox 1 Transmit Acknowledge */
+#define                      nTA1  0x0       
+#define                       TA2  0x4        /* Mailbox 2 Transmit Acknowledge */
+#define                      nTA2  0x0       
+#define                       TA3  0x8        /* Mailbox 3 Transmit Acknowledge */
+#define                      nTA3  0x0       
+#define                       TA4  0x10       /* Mailbox 4 Transmit Acknowledge */
+#define                      nTA4  0x0       
+#define                       TA5  0x20       /* Mailbox 5 Transmit Acknowledge */
+#define                      nTA5  0x0       
+#define                       TA6  0x40       /* Mailbox 6 Transmit Acknowledge */
+#define                      nTA6  0x0       
+#define                       TA7  0x80       /* Mailbox 7 Transmit Acknowledge */
+#define                      nTA7  0x0       
+#define                       TA8  0x100      /* Mailbox 8 Transmit Acknowledge */
+#define                      nTA8  0x0       
+#define                       TA9  0x200      /* Mailbox 9 Transmit Acknowledge */
+#define                      nTA9  0x0       
+#define                      TA10  0x400      /* Mailbox 10 Transmit Acknowledge */
+#define                     nTA10  0x0       
+#define                      TA11  0x800      /* Mailbox 11 Transmit Acknowledge */
+#define                     nTA11  0x0       
+#define                      TA12  0x1000     /* Mailbox 12 Transmit Acknowledge */
+#define                     nTA12  0x0       
+#define                      TA13  0x2000     /* Mailbox 13 Transmit Acknowledge */
+#define                     nTA13  0x0       
+#define                      TA14  0x4000     /* Mailbox 14 Transmit Acknowledge */
+#define                     nTA14  0x0       
+#define                      TA15  0x8000     /* Mailbox 15 Transmit Acknowledge */
+#define                     nTA15  0x0       
+
+/* Bit masks for CAN0_TA2 */
+
+#define                      TA16  0x1        /* Mailbox 16 Transmit Acknowledge */
+#define                     nTA16  0x0       
+#define                      TA17  0x2        /* Mailbox 17 Transmit Acknowledge */
+#define                     nTA17  0x0       
+#define                      TA18  0x4        /* Mailbox 18 Transmit Acknowledge */
+#define                     nTA18  0x0       
+#define                      TA19  0x8        /* Mailbox 19 Transmit Acknowledge */
+#define                     nTA19  0x0       
+#define                      TA20  0x10       /* Mailbox 20 Transmit Acknowledge */
+#define                     nTA20  0x0       
+#define                      TA21  0x20       /* Mailbox 21 Transmit Acknowledge */
+#define                     nTA21  0x0       
+#define                      TA22  0x40       /* Mailbox 22 Transmit Acknowledge */
+#define                     nTA22  0x0       
+#define                      TA23  0x80       /* Mailbox 23 Transmit Acknowledge */
+#define                     nTA23  0x0       
+#define                      TA24  0x100      /* Mailbox 24 Transmit Acknowledge */
+#define                     nTA24  0x0       
+#define                      TA25  0x200      /* Mailbox 25 Transmit Acknowledge */
+#define                     nTA25  0x0       
+#define                      TA26  0x400      /* Mailbox 26 Transmit Acknowledge */
+#define                     nTA26  0x0       
+#define                      TA27  0x800      /* Mailbox 27 Transmit Acknowledge */
+#define                     nTA27  0x0       
+#define                      TA28  0x1000     /* Mailbox 28 Transmit Acknowledge */
+#define                     nTA28  0x0       
+#define                      TA29  0x2000     /* Mailbox 29 Transmit Acknowledge */
+#define                     nTA29  0x0       
+#define                      TA30  0x4000     /* Mailbox 30 Transmit Acknowledge */
+#define                     nTA30  0x0       
+#define                      TA31  0x8000     /* Mailbox 31 Transmit Acknowledge */
+#define                     nTA31  0x0       
+
+/* Bit masks for CAN0_RFH1 */
+
+#define                      RFH0  0x1        /* Mailbox 0 Remote Frame Handling Enable */
+#define                     nRFH0  0x0       
+#define                      RFH1  0x2        /* Mailbox 1 Remote Frame Handling Enable */
+#define                     nRFH1  0x0       
+#define                      RFH2  0x4        /* Mailbox 2 Remote Frame Handling Enable */
+#define                     nRFH2  0x0       
+#define                      RFH3  0x8        /* Mailbox 3 Remote Frame Handling Enable */
+#define                     nRFH3  0x0       
+#define                      RFH4  0x10       /* Mailbox 4 Remote Frame Handling Enable */
+#define                     nRFH4  0x0       
+#define                      RFH5  0x20       /* Mailbox 5 Remote Frame Handling Enable */
+#define                     nRFH5  0x0       
+#define                      RFH6  0x40       /* Mailbox 6 Remote Frame Handling Enable */
+#define                     nRFH6  0x0       
+#define                      RFH7  0x80       /* Mailbox 7 Remote Frame Handling Enable */
+#define                     nRFH7  0x0       
+#define                      RFH8  0x100      /* Mailbox 8 Remote Frame Handling Enable */
+#define                     nRFH8  0x0       
+#define                      RFH9  0x200      /* Mailbox 9 Remote Frame Handling Enable */
+#define                     nRFH9  0x0       
+#define                     RFH10  0x400      /* Mailbox 10 Remote Frame Handling Enable */
+#define                    nRFH10  0x0       
+#define                     RFH11  0x800      /* Mailbox 11 Remote Frame Handling Enable */
+#define                    nRFH11  0x0       
+#define                     RFH12  0x1000     /* Mailbox 12 Remote Frame Handling Enable */
+#define                    nRFH12  0x0       
+#define                     RFH13  0x2000     /* Mailbox 13 Remote Frame Handling Enable */
+#define                    nRFH13  0x0       
+#define                     RFH14  0x4000     /* Mailbox 14 Remote Frame Handling Enable */
+#define                    nRFH14  0x0       
+#define                     RFH15  0x8000     /* Mailbox 15 Remote Frame Handling Enable */
+#define                    nRFH15  0x0       
+
+/* Bit masks for CAN0_RFH2 */
+
+#define                     RFH16  0x1        /* Mailbox 16 Remote Frame Handling Enable */
+#define                    nRFH16  0x0       
+#define                     RFH17  0x2        /* Mailbox 17 Remote Frame Handling Enable */
+#define                    nRFH17  0x0       
+#define                     RFH18  0x4        /* Mailbox 18 Remote Frame Handling Enable */
+#define                    nRFH18  0x0       
+#define                     RFH19  0x8        /* Mailbox 19 Remote Frame Handling Enable */
+#define                    nRFH19  0x0       
+#define                     RFH20  0x10       /* Mailbox 20 Remote Frame Handling Enable */
+#define                    nRFH20  0x0       
+#define                     RFH21  0x20       /* Mailbox 21 Remote Frame Handling Enable */
+#define                    nRFH21  0x0       
+#define                     RFH22  0x40       /* Mailbox 22 Remote Frame Handling Enable */
+#define                    nRFH22  0x0       
+#define                     RFH23  0x80       /* Mailbox 23 Remote Frame Handling Enable */
+#define                    nRFH23  0x0       
+#define                     RFH24  0x100      /* Mailbox 24 Remote Frame Handling Enable */
+#define                    nRFH24  0x0       
+#define                     RFH25  0x200      /* Mailbox 25 Remote Frame Handling Enable */
+#define                    nRFH25  0x0       
+#define                     RFH26  0x400      /* Mailbox 26 Remote Frame Handling Enable */
+#define                    nRFH26  0x0       
+#define                     RFH27  0x800      /* Mailbox 27 Remote Frame Handling Enable */
+#define                    nRFH27  0x0       
+#define                     RFH28  0x1000     /* Mailbox 28 Remote Frame Handling Enable */
+#define                    nRFH28  0x0       
+#define                     RFH29  0x2000     /* Mailbox 29 Remote Frame Handling Enable */
+#define                    nRFH29  0x0       
+#define                     RFH30  0x4000     /* Mailbox 30 Remote Frame Handling Enable */
+#define                    nRFH30  0x0       
+#define                     RFH31  0x8000     /* Mailbox 31 Remote Frame Handling Enable */
+#define                    nRFH31  0x0       
+
+/* Bit masks for CAN0_MBIM1 */
+
+#define                     MBIM0  0x1        /* Mailbox 0 Mailbox Interrupt Mask */
+#define                    nMBIM0  0x0       
+#define                     MBIM1  0x2        /* Mailbox 1 Mailbox Interrupt Mask */
+#define                    nMBIM1  0x0       
+#define                     MBIM2  0x4        /* Mailbox 2 Mailbox Interrupt Mask */
+#define                    nMBIM2  0x0       
+#define                     MBIM3  0x8        /* Mailbox 3 Mailbox Interrupt Mask */
+#define                    nMBIM3  0x0       
+#define                     MBIM4  0x10       /* Mailbox 4 Mailbox Interrupt Mask */
+#define                    nMBIM4  0x0       
+#define                     MBIM5  0x20       /* Mailbox 5 Mailbox Interrupt Mask */
+#define                    nMBIM5  0x0       
+#define                     MBIM6  0x40       /* Mailbox 6 Mailbox Interrupt Mask */
+#define                    nMBIM6  0x0       
+#define                     MBIM7  0x80       /* Mailbox 7 Mailbox Interrupt Mask */
+#define                    nMBIM7  0x0       
+#define                     MBIM8  0x100      /* Mailbox 8 Mailbox Interrupt Mask */
+#define                    nMBIM8  0x0       
+#define                     MBIM9  0x200      /* Mailbox 9 Mailbox Interrupt Mask */
+#define                    nMBIM9  0x0       
+#define                    MBIM10  0x400      /* Mailbox 10 Mailbox Interrupt Mask */
+#define                   nMBIM10  0x0       
+#define                    MBIM11  0x800      /* Mailbox 11 Mailbox Interrupt Mask */
+#define                   nMBIM11  0x0       
+#define                    MBIM12  0x1000     /* Mailbox 12 Mailbox Interrupt Mask */
+#define                   nMBIM12  0x0       
+#define                    MBIM13  0x2000     /* Mailbox 13 Mailbox Interrupt Mask */
+#define                   nMBIM13  0x0       
+#define                    MBIM14  0x4000     /* Mailbox 14 Mailbox Interrupt Mask */
+#define                   nMBIM14  0x0       
+#define                    MBIM15  0x8000     /* Mailbox 15 Mailbox Interrupt Mask */
+#define                   nMBIM15  0x0       
+
+/* Bit masks for CAN0_MBIM2 */
+
+#define                    MBIM16  0x1        /* Mailbox 16 Mailbox Interrupt Mask */
+#define                   nMBIM16  0x0       
+#define                    MBIM17  0x2        /* Mailbox 17 Mailbox Interrupt Mask */
+#define                   nMBIM17  0x0       
+#define                    MBIM18  0x4        /* Mailbox 18 Mailbox Interrupt Mask */
+#define                   nMBIM18  0x0       
+#define                    MBIM19  0x8        /* Mailbox 19 Mailbox Interrupt Mask */
+#define                   nMBIM19  0x0       
+#define                    MBIM20  0x10       /* Mailbox 20 Mailbox Interrupt Mask */
+#define                   nMBIM20  0x0       
+#define                    MBIM21  0x20       /* Mailbox 21 Mailbox Interrupt Mask */
+#define                   nMBIM21  0x0       
+#define                    MBIM22  0x40       /* Mailbox 22 Mailbox Interrupt Mask */
+#define                   nMBIM22  0x0       
+#define                    MBIM23  0x80       /* Mailbox 23 Mailbox Interrupt Mask */
+#define                   nMBIM23  0x0       
+#define                    MBIM24  0x100      /* Mailbox 24 Mailbox Interrupt Mask */
+#define                   nMBIM24  0x0       
+#define                    MBIM25  0x200      /* Mailbox 25 Mailbox Interrupt Mask */
+#define                   nMBIM25  0x0       
+#define                    MBIM26  0x400      /* Mailbox 26 Mailbox Interrupt Mask */
+#define                   nMBIM26  0x0       
+#define                    MBIM27  0x800      /* Mailbox 27 Mailbox Interrupt Mask */
+#define                   nMBIM27  0x0       
+#define                    MBIM28  0x1000     /* Mailbox 28 Mailbox Interrupt Mask */
+#define                   nMBIM28  0x0       
+#define                    MBIM29  0x2000     /* Mailbox 29 Mailbox Interrupt Mask */
+#define                   nMBIM29  0x0       
+#define                    MBIM30  0x4000     /* Mailbox 30 Mailbox Interrupt Mask */
+#define                   nMBIM30  0x0       
+#define                    MBIM31  0x8000     /* Mailbox 31 Mailbox Interrupt Mask */
+#define                   nMBIM31  0x0       
+
+/* Bit masks for CAN0_MBTIF1 */
+
+#define                    MBTIF0  0x1        /* Mailbox 0 Mailbox Transmit Interrupt Flag */
+#define                   nMBTIF0  0x0       
+#define                    MBTIF1  0x2        /* Mailbox 1 Mailbox Transmit Interrupt Flag */
+#define                   nMBTIF1  0x0       
+#define                    MBTIF2  0x4        /* Mailbox 2 Mailbox Transmit Interrupt Flag */
+#define                   nMBTIF2  0x0       
+#define                    MBTIF3  0x8        /* Mailbox 3 Mailbox Transmit Interrupt Flag */
+#define                   nMBTIF3  0x0       
+#define                    MBTIF4  0x10       /* Mailbox 4 Mailbox Transmit Interrupt Flag */
+#define                   nMBTIF4  0x0       
+#define                    MBTIF5  0x20       /* Mailbox 5 Mailbox Transmit Interrupt Flag */
+#define                   nMBTIF5  0x0       
+#define                    MBTIF6  0x40       /* Mailbox 6 Mailbox Transmit Interrupt Flag */
+#define                   nMBTIF6  0x0       
+#define                    MBTIF7  0x80       /* Mailbox 7 Mailbox Transmit Interrupt Flag */
+#define                   nMBTIF7  0x0       
+#define                    MBTIF8  0x100      /* Mailbox 8 Mailbox Transmit Interrupt Flag */
+#define                   nMBTIF8  0x0       
+#define                    MBTIF9  0x200      /* Mailbox 9 Mailbox Transmit Interrupt Flag */
+#define                   nMBTIF9  0x0       
+#define                   MBTIF10  0x400      /* Mailbox 10 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF10  0x0       
+#define                   MBTIF11  0x800      /* Mailbox 11 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF11  0x0       
+#define                   MBTIF12  0x1000     /* Mailbox 12 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF12  0x0       
+#define                   MBTIF13  0x2000     /* Mailbox 13 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF13  0x0       
+#define                   MBTIF14  0x4000     /* Mailbox 14 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF14  0x0       
+#define                   MBTIF15  0x8000     /* Mailbox 15 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF15  0x0       
+
+/* Bit masks for CAN0_MBTIF2 */
+
+#define                   MBTIF16  0x1        /* Mailbox 16 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF16  0x0       
+#define                   MBTIF17  0x2        /* Mailbox 17 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF17  0x0       
+#define                   MBTIF18  0x4        /* Mailbox 18 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF18  0x0       
+#define                   MBTIF19  0x8        /* Mailbox 19 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF19  0x0       
+#define                   MBTIF20  0x10       /* Mailbox 20 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF20  0x0       
+#define                   MBTIF21  0x20       /* Mailbox 21 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF21  0x0       
+#define                   MBTIF22  0x40       /* Mailbox 22 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF22  0x0       
+#define                   MBTIF23  0x80       /* Mailbox 23 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF23  0x0       
+#define                   MBTIF24  0x100      /* Mailbox 24 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF24  0x0       
+#define                   MBTIF25  0x200      /* Mailbox 25 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF25  0x0       
+#define                   MBTIF26  0x400      /* Mailbox 26 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF26  0x0       
+#define                   MBTIF27  0x800      /* Mailbox 27 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF27  0x0       
+#define                   MBTIF28  0x1000     /* Mailbox 28 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF28  0x0       
+#define                   MBTIF29  0x2000     /* Mailbox 29 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF29  0x0       
+#define                   MBTIF30  0x4000     /* Mailbox 30 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF30  0x0       
+#define                   MBTIF31  0x8000     /* Mailbox 31 Mailbox Transmit Interrupt Flag */
+#define                  nMBTIF31  0x0       
+
+/* Bit masks for CAN0_MBRIF1 */
+
+#define                    MBRIF0  0x1        /* Mailbox 0 Mailbox Receive Interrupt Flag */
+#define                   nMBRIF0  0x0       
+#define                    MBRIF1  0x2        /* Mailbox 1 Mailbox Receive Interrupt Flag */
+#define                   nMBRIF1  0x0       
+#define                    MBRIF2  0x4        /* Mailbox 2 Mailbox Receive Interrupt Flag */
+#define                   nMBRIF2  0x0       
+#define                    MBRIF3  0x8        /* Mailbox 3 Mailbox Receive Interrupt Flag */
+#define                   nMBRIF3  0x0       
+#define                    MBRIF4  0x10       /* Mailbox 4 Mailbox Receive Interrupt Flag */
+#define                   nMBRIF4  0x0       
+#define                    MBRIF5  0x20       /* Mailbox 5 Mailbox Receive Interrupt Flag */
+#define                   nMBRIF5  0x0       
+#define                    MBRIF6  0x40       /* Mailbox 6 Mailbox Receive Interrupt Flag */
+#define                   nMBRIF6  0x0       
+#define                    MBRIF7  0x80       /* Mailbox 7 Mailbox Receive Interrupt Flag */
+#define                   nMBRIF7  0x0       
+#define                    MBRIF8  0x100      /* Mailbox 8 Mailbox Receive Interrupt Flag */
+#define                   nMBRIF8  0x0       
+#define                    MBRIF9  0x200      /* Mailbox 9 Mailbox Receive Interrupt Flag */
+#define                   nMBRIF9  0x0       
+#define                   MBRIF10  0x400      /* Mailbox 10 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF10  0x0       
+#define                   MBRIF11  0x800      /* Mailbox 11 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF11  0x0       
+#define                   MBRIF12  0x1000     /* Mailbox 12 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF12  0x0       
+#define                   MBRIF13  0x2000     /* Mailbox 13 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF13  0x0       
+#define                   MBRIF14  0x4000     /* Mailbox 14 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF14  0x0       
+#define                   MBRIF15  0x8000     /* Mailbox 15 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF15  0x0       
+
+/* Bit masks for CAN0_MBRIF2 */
+
+#define                   MBRIF16  0x1        /* Mailbox 16 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF16  0x0       
+#define                   MBRIF17  0x2        /* Mailbox 17 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF17  0x0       
+#define                   MBRIF18  0x4        /* Mailbox 18 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF18  0x0       
+#define                   MBRIF19  0x8        /* Mailbox 19 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF19  0x0       
+#define                   MBRIF20  0x10       /* Mailbox 20 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF20  0x0       
+#define                   MBRIF21  0x20       /* Mailbox 21 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF21  0x0       
+#define                   MBRIF22  0x40       /* Mailbox 22 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF22  0x0       
+#define                   MBRIF23  0x80       /* Mailbox 23 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF23  0x0       
+#define                   MBRIF24  0x100      /* Mailbox 24 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF24  0x0       
+#define                   MBRIF25  0x200      /* Mailbox 25 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF25  0x0       
+#define                   MBRIF26  0x400      /* Mailbox 26 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF26  0x0       
+#define                   MBRIF27  0x800      /* Mailbox 27 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF27  0x0       
+#define                   MBRIF28  0x1000     /* Mailbox 28 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF28  0x0       
+#define                   MBRIF29  0x2000     /* Mailbox 29 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF29  0x0       
+#define                   MBRIF30  0x4000     /* Mailbox 30 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF30  0x0       
+#define                   MBRIF31  0x8000     /* Mailbox 31 Mailbox Receive Interrupt Flag */
+#define                  nMBRIF31  0x0       
+
+/* Bit masks for EPPIx_STATUS */
+
+#define                 CFIFO_ERR  0x1        /* Chroma FIFO Error */
+#define                nCFIFO_ERR  0x0       
+#define                 YFIFO_ERR  0x2        /* Luma FIFO Error */
+#define                nYFIFO_ERR  0x0       
+#define                 LTERR_OVR  0x4        /* Line Track Overflow */
+#define                nLTERR_OVR  0x0       
+#define                LTERR_UNDR  0x8        /* Line Track Underflow */
+#define               nLTERR_UNDR  0x0       
+#define                 FTERR_OVR  0x10       /* Frame Track Overflow */
+#define                nFTERR_OVR  0x0       
+#define                FTERR_UNDR  0x20       /* Frame Track Underflow */
+#define               nFTERR_UNDR  0x0       
+#define                  ERR_NCOR  0x40       /* Preamble Error Not Corrected */
+#define                 nERR_NCOR  0x0       
+#define                   DMA1URQ  0x80       /* DMA1 Urgent Request */
+#define                  nDMA1URQ  0x0       
+#define                   DMA0URQ  0x100      /* DMA0 Urgent Request */
+#define                  nDMA0URQ  0x0       
+#define                   ERR_DET  0x4000     /* Preamble Error Detected */
+#define                  nERR_DET  0x0       
+#define                       FLD  0x8000     /* Field */
+#define                      nFLD  0x0       
+
+/* Bit masks for EPPIx_CONTROL */
+
+#define                   EPPI_EN  0x1        /* Enable */
+#define                  nEPPI_EN  0x0       
+#define                  EPPI_DIR  0x2        /* Direction */
+#define                 nEPPI_DIR  0x0       
+#define                  XFR_TYPE  0xc        /* Operating Mode */
+#define                    FS_CFG  0x30       /* Frame Sync Configuration */
+#define                   FLD_SEL  0x40       /* Field Select/Trigger */
+#define                  nFLD_SEL  0x0       
+#define                  ITU_TYPE  0x80       /* ITU Interlaced or Progressive */
+#define                 nITU_TYPE  0x0       
+#define                  BLANKGEN  0x100      /* ITU Output Mode with Internal Blanking Generation */
+#define                 nBLANKGEN  0x0       
+#define                   ICLKGEN  0x200      /* Internal Clock Generation */
+#define                  nICLKGEN  0x0       
+#define                    IFSGEN  0x400      /* Internal Frame Sync Generation */
+#define                   nIFSGEN  0x0       
+#define                      POLC  0x1800     /* Frame Sync and Data Driving/Sampling Edges */
+#define                      POLS  0x6000     /* Frame Sync Polarity */
+#define                   DLENGTH  0x38000    /* Data Length */
+#define                   SKIP_EN  0x40000    /* Skip Enable */
+#define                  nSKIP_EN  0x0       
+#define                   SKIP_EO  0x80000    /* Skip Even or Odd */
+#define                  nSKIP_EO  0x0       
+#define                    PACKEN  0x100000   /* Packing/Unpacking Enable */
+#define                   nPACKEN  0x0       
+#define                    SWAPEN  0x200000   /* Swap Enable */
+#define                   nSWAPEN  0x0       
+#define                  SIGN_EXT  0x400000   /* Sign Extension or Zero-filled / Data Split Format */
+#define                 nSIGN_EXT  0x0       
+#define             SPLT_EVEN_ODD  0x800000   /* Split Even and Odd Data Samples */
+#define            nSPLT_EVEN_ODD  0x0       
+#define               SUBSPLT_ODD  0x1000000  /* Sub-split Odd Samples */
+#define              nSUBSPLT_ODD  0x0       
+#define                    DMACFG  0x2000000  /* One or Two DMA Channels Mode */
+#define                   nDMACFG  0x0       
+#define                RGB_FMT_EN  0x4000000  /* RGB Formatting Enable */
+#define               nRGB_FMT_EN  0x0       
+#define                  FIFO_RWM  0x18000000 /* FIFO Regular Watermarks */
+#define                  FIFO_UWM  0x60000000 /* FIFO Urgent Watermarks */
+
+/* Bit masks for EPPIx_FS2W_LVB */
+
+#define                   F1VB_BD  0xff       /* Vertical Blanking before Field 1 Active Data */
+#define                   F1VB_AD  0xff00     /* Vertical Blanking after Field 1 Active Data */
+#define                   F2VB_BD  0xff0000   /* Vertical Blanking before Field 2 Active Data */
+#define                   F2VB_AD  0xff000000 /* Vertical Blanking after Field 2 Active Data */
+
+/* Bit masks for EPPIx_FS2W_LAVF */
+
+#define                    F1_ACT  0xffff     /* Number of Lines of Active Data in Field 1 */
+#define                    F2_ACT  0xffff0000 /* Number of Lines of Active Data in Field 2 */
+
+/* Bit masks for EPPIx_CLIP */
+
+#define                   LOW_ODD  0xff       /* Lower Limit for Odd Bytes (Chroma) */
+#define                  HIGH_ODD  0xff00     /* Upper Limit for Odd Bytes (Chroma) */
+#define                  LOW_EVEN  0xff0000   /* Lower Limit for Even Bytes (Luma) */
+#define                 HIGH_EVEN  0xff000000 /* Upper Limit for Even Bytes (Luma) */
+
+/* Bit masks for SPIx_BAUD */
+
+#define                  SPI_BAUD  0xffff     /* Baud Rate */
+
+/* Bit masks for SPIx_CTL */
+
+#define                       SPE  0x4000     /* SPI Enable */
+#define                      nSPE  0x0       
+#define                       WOM  0x2000     /* Write Open Drain Master */
+#define                      nWOM  0x0       
+#define                      MSTR  0x1000     /* Master Mode */
+#define                     nMSTR  0x0       
+#define                      CPOL  0x800      /* Clock Polarity */
+#define                     nCPOL  0x0       
+#define                      CPHA  0x400      /* Clock Phase */
+#define                     nCPHA  0x0       
+#define                      LSBF  0x200      /* LSB First */
+#define                     nLSBF  0x0       
+#define                      SIZE  0x100      /* Size of Words */
+#define                     nSIZE  0x0       
+#define                     EMISO  0x20       /* Enable MISO Output */
+#define                    nEMISO  0x0       
+#define                      PSSE  0x10       /* Slave-Select Enable */
+#define                     nPSSE  0x0       
+#define                        GM  0x8        /* Get More Data */
+#define                       nGM  0x0       
+#define                        SZ  0x4        /* Send Zero */
+#define                       nSZ  0x0       
+#define                     TIMOD  0x3        /* Transfer Initiation Mode */
+
+/* Bit masks for SPIx_FLG */
+
+#define                      FLS1  0x2        /* Slave Select Enable 1 */
+#define                     nFLS1  0x0       
+#define                      FLS2  0x4        /* Slave Select Enable 2 */
+#define                     nFLS2  0x0       
+#define                      FLS3  0x8        /* Slave Select Enable 3 */
+#define                     nFLS3  0x0       
+#define                      FLG1  0x200      /* Slave Select Value 1 */
+#define                     nFLG1  0x0       
+#define                      FLG2  0x400      /* Slave Select Value 2 */
+#define                     nFLG2  0x0       
+#define                      FLG3  0x800      /* Slave Select Value 3 */
+#define                     nFLG3  0x0       
+
+/* Bit masks for SPIx_STAT */
+
+#define                     TXCOL  0x40       /* Transmit Collision Error */
+#define                    nTXCOL  0x0       
+#define                       RXS  0x20       /* RDBR Data Buffer Status */
+#define                      nRXS  0x0       
+#define                      RBSY  0x10       /* Receive Error */
+#define                     nRBSY  0x0       
+#define                       TXS  0x8        /* TDBR Data Buffer Status */
+#define                      nTXS  0x0       
+#define                       TXE  0x4        /* Transmission Error */
+#define                      nTXE  0x0       
+#define                      MODF  0x2        /* Mode Fault Error */
+#define                     nMODF  0x0       
+#define                      SPIF  0x1        /* SPI Finished */
+#define                     nSPIF  0x0       
+
+/* Bit masks for SPIx_TDBR */
+
+#define                      TDBR  0xffff     /* Transmit Data Buffer */
+
+/* Bit masks for SPIx_RDBR */
+
+#define                      RDBR  0xffff     /* Receive Data Buffer */
+
+/* Bit masks for SPIx_SHADOW */
+
+#define                    SHADOW  0xffff     /* RDBR Shadow */
+
+/* ************************************************ */
+/* The TWI bit masks fields are from the ADSP-BF538 */
+/* and they have not been verified as the final     */
+/* ones for the Moab processors ... bz 1/19/2007    */
+/* ************************************************ */
+
+/* Bit masks for TWIx_CONTROL */
+
+#define                  PRESCALE  0x7f       /* Prescale Value */
+#define                   TWI_ENA  0x80       /* TWI Enable */
+#define                  nTWI_ENA  0x0       
+#define                      SCCB  0x200      /* Serial Camera Control Bus */
+#define                     nSCCB  0x0       
+
+/* Bit maskes for TWIx_CLKDIV */
+
+#define                    CLKLOW  0xff       /* Clock Low */
+#define                     CLKHI  0xff00     /* Clock High */
+
+/* Bit maskes for TWIx_SLAVE_CTL */
+
+#define                       SEN  0x1        /* Slave Enable */
+#define                      nSEN  0x0       
+#define                    STDVAL  0x4        /* Slave Transmit Data Valid */
+#define                   nSTDVAL  0x0       
+#define                       NAK  0x8        /* Not Acknowledge */
+#define                      nNAK  0x0       
+#define                       GEN  0x10       /* General Call Enable */
+#define                      nGEN  0x0       
+
+/* Bit maskes for TWIx_SLAVE_ADDR */
+
+#define                     SADDR  0x7f       /* Slave Mode Address */
+
+/* Bit maskes for TWIx_SLAVE_STAT */
+
+#define                      SDIR  0x1        /* Slave Transfer Direction */
+#define                     nSDIR  0x0       
+#define                     GCALL  0x2        /* General Call */
+#define                    nGCALL  0x0       
+
+/* Bit maskes for TWIx_MASTER_CTL */
+
+#define                       MEN  0x1        /* Master Mode Enable */
+#define                      nMEN  0x0       
+#define                      MDIR  0x4        /* Master Transfer Direction */
+#define                     nMDIR  0x0       
+#define                      FAST  0x8        /* Fast Mode */
+#define                     nFAST  0x0       
+#define                      STOP  0x10       /* Issue Stop Condition */
+#define                     nSTOP  0x0       
+#define                    RSTART  0x20       /* Repeat Start */
+#define                   nRSTART  0x0       
+#define                      DCNT  0x3fc0     /* Data Transfer Count */
+#define                    SDAOVR  0x4000     /* Serial Data Override */
+#define                   nSDAOVR  0x0       
+#define                    SCLOVR  0x8000     /* Serial Clock Override */
+#define                   nSCLOVR  0x0       
+
+/* Bit maskes for TWIx_MASTER_ADDR */
+
+#define                     MADDR  0x7f       /* Master Mode Address */
+
+/* Bit maskes for TWIx_MASTER_STAT */
+
+#define                     MPROG  0x1        /* Master Transfer in Progress */
+#define                    nMPROG  0x0       
+#define                   LOSTARB  0x2        /* Lost Arbitration */
+#define                  nLOSTARB  0x0       
+#define                      ANAK  0x4        /* Address Not Acknowledged */
+#define                     nANAK  0x0       
+#define                      DNAK  0x8        /* Data Not Acknowledged */
+#define                     nDNAK  0x0       
+#define                  BUFRDERR  0x10       /* Buffer Read Error */
+#define                 nBUFRDERR  0x0       
+#define                  BUFWRERR  0x20       /* Buffer Write Error */
+#define                 nBUFWRERR  0x0       
+#define                    SDASEN  0x40       /* Serial Data Sense */
+#define                   nSDASEN  0x0       
+#define                    SCLSEN  0x80       /* Serial Clock Sense */
+#define                   nSCLSEN  0x0       
+#define                   BUSBUSY  0x100      /* Bus Busy */
+#define                  nBUSBUSY  0x0       
+
+/* Bit maskes for TWIx_FIFO_CTL */
+
+#define                  XMTFLUSH  0x1        /* Transmit Buffer Flush */
+#define                 nXMTFLUSH  0x0       
+#define                  RCVFLUSH  0x2        /* Receive Buffer Flush */
+#define                 nRCVFLUSH  0x0       
+#define                 XMTINTLEN  0x4        /* Transmit Buffer Interrupt Length */
+#define                nXMTINTLEN  0x0       
+#define                 RCVINTLEN  0x8        /* Receive Buffer Interrupt Length */
+#define                nRCVINTLEN  0x0       
+
+/* Bit maskes for TWIx_FIFO_STAT */
+
+#define                   XMTSTAT  0x3        /* Transmit FIFO Status */
+#define                   RCVSTAT  0xc        /* Receive FIFO Status */
+
+/* Bit maskes for TWIx_INT_MASK */
+
+#define                    SINITM  0x1        /* Slave Transfer Initiated Interrupt Mask */
+#define                   nSINITM  0x0       
+#define                    SCOMPM  0x2        /* Slave Transfer Complete Interrupt Mask */
+#define                   nSCOMPM  0x0       
+#define                     SERRM  0x4        /* Slave Transfer Error Interrupt Mask */
+#define                    nSERRM  0x0       
+#define                     SOVFM  0x8        /* Slave Overflow Interrupt Mask */
+#define                    nSOVFM  0x0       
+#define                    MCOMPM  0x10       /* Master Transfer Complete Interrupt Mask */
+#define                   nMCOMPM  0x0       
+#define                     MERRM  0x20       /* Master Transfer Error Interrupt Mask */
+#define                    nMERRM  0x0       
+#define                  XMTSERVM  0x40       /* Transmit FIFO Service Interrupt Mask */
+#define                 nXMTSERVM  0x0       
+#define                  RCVSERVM  0x80       /* Receive FIFO Service Interrupt Mask */
+#define                 nRCVSERVM  0x0       
+
+/* Bit maskes for TWIx_INT_STAT */
+
+#define                     SINIT  0x1        /* Slave Transfer Initiated */
+#define                    nSINIT  0x0       
+#define                     SCOMP  0x2        /* Slave Transfer Complete */
+#define                    nSCOMP  0x0       
+#define                      SERR  0x4        /* Slave Transfer Error */
+#define                     nSERR  0x0       
+#define                      SOVF  0x8        /* Slave Overflow */
+#define                     nSOVF  0x0       
+#define                     MCOMP  0x10       /* Master Transfer Complete */
+#define                    nMCOMP  0x0       
+#define                      MERR  0x20       /* Master Transfer Error */
+#define                     nMERR  0x0       
+#define                   XMTSERV  0x40       /* Transmit FIFO Service */
+#define                  nXMTSERV  0x0       
+#define                   RCVSERV  0x80       /* Receive FIFO Service */
+#define                  nRCVSERV  0x0       
+
+/* Bit maskes for TWIx_XMT_DATA8 */
+
+#define                  XMTDATA8  0xff       /* Transmit FIFO 8-Bit Data */
+
+/* Bit maskes for TWIx_XMT_DATA16 */
+
+#define                 XMTDATA16  0xffff     /* Transmit FIFO 16-Bit Data */
+
+/* Bit maskes for TWIx_RCV_DATA8 */
+
+#define                  RCVDATA8  0xff       /* Receive FIFO 8-Bit Data */
+
+/* Bit maskes for TWIx_RCV_DATA16 */
+
+#define                 RCVDATA16  0xffff     /* Receive FIFO 16-Bit Data */
+
+/* Bit masks for SPORTx_TCR1 */
+
+#define                     TCKFE  0x4000     /* Clock Falling Edge Select */
+#define                    nTCKFE  0x0       
+#define                     LATFS  0x2000     /* Late Transmit Frame Sync */
+#define                    nLATFS  0x0       
+#define                      LTFS  0x1000     /* Low Transmit Frame Sync Select */
+#define                     nLTFS  0x0       
+#define                     DITFS  0x800      /* Data-Independent Transmit Frame Sync Select */
+#define                    nDITFS  0x0       
+#define                      TFSR  0x400      /* Transmit Frame Sync Required Select */
+#define                     nTFSR  0x0       
+#define                      ITFS  0x200      /* Internal Transmit Frame Sync Select */
+#define                     nITFS  0x0       
+#define                    TLSBIT  0x10       /* Transmit Bit Order */
+#define                   nTLSBIT  0x0       
+#define                    TDTYPE  0xc        /* Data Formatting Type Select */
+#define                     ITCLK  0x2        /* Internal Transmit Clock Select */
+#define                    nITCLK  0x0       
+#define                     TSPEN  0x1        /* Transmit Enable */
+#define                    nTSPEN  0x0       
+
+/* Bit masks for SPORTx_TCR2 */
+
+#define                     TRFST  0x400      /* Left/Right Order */
+#define                    nTRFST  0x0       
+#define                     TSFSE  0x200      /* Transmit Stereo Frame Sync Enable */
+#define                    nTSFSE  0x0       
+#define                      TXSE  0x100      /* TxSEC Enable */
+#define                     nTXSE  0x0       
+#define                    SLEN_T  0x1f       /* SPORT Word Length */
+
+/* Bit masks for SPORTx_RCR1 */
+
+#define                     RCKFE  0x4000     /* Clock Falling Edge Select */
+#define                    nRCKFE  0x0       
+#define                     LARFS  0x2000     /* Late Receive Frame Sync */
+#define                    nLARFS  0x0       
+#define                      LRFS  0x1000     /* Low Receive Frame Sync Select */
+#define                     nLRFS  0x0       
+#define                      RFSR  0x400      /* Receive Frame Sync Required Select */
+#define                     nRFSR  0x0       
+#define                      IRFS  0x200      /* Internal Receive Frame Sync Select */
+#define                     nIRFS  0x0       
+#define                    RLSBIT  0x10       /* Receive Bit Order */
+#define                   nRLSBIT  0x0       
+#define                    RDTYPE  0xc        /* Data Formatting Type Select */
+#define                     IRCLK  0x2        /* Internal Receive Clock Select */
+#define                    nIRCLK  0x0       
+#define                     RSPEN  0x1        /* Receive Enable */
+#define                    nRSPEN  0x0       
+
+/* Bit masks for SPORTx_RCR2 */
+
+#define                     RRFST  0x400      /* Left/Right Order */
+#define                    nRRFST  0x0       
+#define                     RSFSE  0x200      /* Receive Stereo Frame Sync Enable */
+#define                    nRSFSE  0x0       
+#define                      RXSE  0x100      /* RxSEC Enable */
+#define                     nRXSE  0x0       
+#define                    SLEN_R  0x1f       /* SPORT Word Length */
+
+/* Bit masks for SPORTx_STAT */
+
+#define                     TXHRE  0x40       /* Transmit Hold Register Empty */
+#define                    nTXHRE  0x0       
+#define                      TOVF  0x20       /* Sticky Transmit Overflow Status */
+#define                     nTOVF  0x0       
+#define                      TUVF  0x10       /* Sticky Transmit Underflow Status */
+#define                     nTUVF  0x0       
+#define                       TXF  0x8        /* Transmit FIFO Full Status */
+#define                      nTXF  0x0       
+#define                      ROVF  0x4        /* Sticky Receive Overflow Status */
+#define                     nROVF  0x0       
+#define                      RUVF  0x2        /* Sticky Receive Underflow Status */
+#define                     nRUVF  0x0       
+#define                      RXNE  0x1        /* Receive FIFO Not Empty Status */
+#define                     nRXNE  0x0       
+
+/* Bit masks for SPORTx_MCMC1 */
+
+#define                  SP_WSIZE  0xf000     /* Window Size */
+#define                   SP_WOFF  0x3ff      /* Windows Offset */
+
+/* Bit masks for SPORTx_MCMC2 */
+
+#define                       MFD  0xf000     /* Multi channel Frame Delay */
+#define                      FSDR  0x80       /* Frame Sync to Data Relationship */
+#define                     nFSDR  0x0       
+#define                     MCMEM  0x10       /* Multi channel Frame Mode Enable */
+#define                    nMCMEM  0x0       
+#define                   MCDRXPE  0x8        /* Multi channel DMA Receive Packing */
+#define                  nMCDRXPE  0x0       
+#define                   MCDTXPE  0x4        /* Multi channel DMA Transmit Packing */
+#define                  nMCDTXPE  0x0       
+#define                     MCCRM  0x3        /* 2X Clock Recovery Mode */
+
+/* Bit masks for SPORTx_CHNL */
+
+#define                  CUR_CHNL  0x3ff      /* Current Channel Indicator */
+
+/* Bit masks for UARTx_LCR */
+
+#if 0
+/* conflicts with legacy one in last section */
+#define                       WLS  0x3        /* Word Length Select */
+#endif
+#define                       STB  0x4        /* Stop Bits */
+#define                      nSTB  0x0       
+#define                       PEN  0x8        /* Parity Enable */
+#define                      nPEN  0x0       
+#define                       EPS  0x10       /* Even Parity Select */
+#define                      nEPS  0x0       
+#define                       STP  0x20       /* Sticky Parity */
+#define                      nSTP  0x0       
+#define                        SB  0x40       /* Set Break */
+#define                       nSB  0x0       
+
+/* Bit masks for UARTx_MCR */
+
+#define                      XOFF  0x1        /* Transmitter Off */
+#define                     nXOFF  0x0       
+#define                      MRTS  0x2        /* Manual Request To Send */
+#define                     nMRTS  0x0       
+#define                      RFIT  0x4        /* Receive FIFO IRQ Threshold */
+#define                     nRFIT  0x0       
+#define                      RFRT  0x8        /* Receive FIFO RTS Threshold */
+#define                     nRFRT  0x0       
+#define                  LOOP_ENA  0x10       /* Loopback Mode Enable */
+#define                 nLOOP_ENA  0x0       
+#define                     FCPOL  0x20       /* Flow Control Pin Polarity */
+#define                    nFCPOL  0x0       
+#define                      ARTS  0x40       /* Automatic Request To Send */
+#define                     nARTS  0x0       
+#define                      ACTS  0x80       /* Automatic Clear To Send */
+#define                     nACTS  0x0       
+
+/* Bit masks for UARTx_LSR */
+
+#define                        DR  0x1        /* Data Ready */
+#define                       nDR  0x0       
+#define                        OE  0x2        /* Overrun Error */
+#define                       nOE  0x0       
+#define                        PE  0x4        /* Parity Error */
+#define                       nPE  0x0       
+#define                        FE  0x8        /* Framing Error */
+#define                       nFE  0x0       
+#define                        BI  0x10       /* Break Interrupt */
+#define                       nBI  0x0       
+#define                      THRE  0x20       /* THR Empty */
+#define                     nTHRE  0x0       
+#define                      TEMT  0x40       /* Transmitter Empty */
+#define                     nTEMT  0x0       
+#define                       TFI  0x80       /* Transmission Finished Indicator */
+#define                      nTFI  0x0       
+
+/* Bit masks for UARTx_MSR */
+
+#define                      SCTS  0x1        /* Sticky CTS */
+#define                     nSCTS  0x0       
+#define                       CTS  0x10       /* Clear To Send */
+#define                      nCTS  0x0       
+#define                      RFCS  0x20       /* Receive FIFO Count Status */
+#define                     nRFCS  0x0       
+
+/* Bit masks for UARTx_IER_SET */
+
+#define                   ERBFI_S  0x1        /* Enable Receive Buffer Full Interrupt */
+#define                  nERBFI_S  0x0       
+#define                   ETBEI_S  0x2        /* Enable Transmit Buffer Empty Interrupt */
+#define                  nETBEI_S  0x0       
+#define                    ELSI_S  0x4        /* Enable Receive Status Interrupt */
+#define                   nELSI_S  0x0       
+#define                   EDSSI_S  0x8        /* Enable Modem Status Interrupt */
+#define                  nEDSSI_S  0x0       
+#define                  EDTPTI_S  0x10       /* Enable DMA Transmit PIRQ Interrupt */
+#define                 nEDTPTI_S  0x0       
+#define                    ETFI_S  0x20       /* Enable Transmission Finished Interrupt */
+#define                   nETFI_S  0x0       
+#define                   ERFCI_S  0x40       /* Enable Receive FIFO Count Interrupt */
+#define                  nERFCI_S  0x0       
+
+/* Bit masks for UARTx_IER_CLEAR */
+
+#define                   ERBFI_C  0x1        /* Enable Receive Buffer Full Interrupt */
+#define                  nERBFI_C  0x0       
+#define                   ETBEI_C  0x2        /* Enable Transmit Buffer Empty Interrupt */
+#define                  nETBEI_C  0x0       
+#define                    ELSI_C  0x4        /* Enable Receive Status Interrupt */
+#define                   nELSI_C  0x0       
+#define                   EDSSI_C  0x8        /* Enable Modem Status Interrupt */
+#define                  nEDSSI_C  0x0       
+#define                  EDTPTI_C  0x10       /* Enable DMA Transmit PIRQ Interrupt */
+#define                 nEDTPTI_C  0x0       
+#define                    ETFI_C  0x20       /* Enable Transmission Finished Interrupt */
+#define                   nETFI_C  0x0       
+#define                   ERFCI_C  0x40       /* Enable Receive FIFO Count Interrupt */
+#define                  nERFCI_C  0x0       
+
+/* Bit masks for UARTx_GCTL */
+
+#define                      UCEN  0x1        /* UART Enable */
+#define                     nUCEN  0x0       
+#define                      IREN  0x2        /* IrDA Mode Enable */
+#define                     nIREN  0x0       
+#define                     TPOLC  0x4        /* IrDA TX Polarity Change */
+#define                    nTPOLC  0x0       
+#define                     RPOLC  0x8        /* IrDA RX Polarity Change */
+#define                    nRPOLC  0x0       
+#define                       FPE  0x10       /* Force Parity Error */
+#define                      nFPE  0x0       
+#define                       FFE  0x20       /* Force Framing Error */
+#define                      nFFE  0x0       
+#define                      EDBO  0x40       /* Enable Divide-by-One */
+#define                     nEDBO  0x0       
+#define                     EGLSI  0x80       /* Enable Global LS Interrupt */
+#define                    nEGLSI  0x0       
+
+
+/* ******************************************* */
+/*     MULTI BIT MACRO ENUMERATIONS            */
+/* ******************************************* */
+
+/* BCODE bit field options (SYSCFG register) */
+
+#define BCODE_WAKEUP    0x0000  /* boot according to wake-up condition */
+#define BCODE_FULLBOOT  0x0010  /* always perform full boot */ 
+#define BCODE_QUICKBOOT 0x0020  /* always perform quick boot */
+#define BCODE_NOBOOT    0x0030  /* always perform full boot */
+
+/* CNT_COMMAND bit field options */
+ 
+#define W1LCNT_ZERO   0x0001   /* write 1 to load CNT_COUNTER with zero */
+#define W1LCNT_MIN    0x0004   /* write 1 to load CNT_COUNTER from CNT_MIN */
+#define W1LCNT_MAX    0x0008   /* write 1 to load CNT_COUNTER from CNT_MAX */
+ 
+#define W1LMIN_ZERO   0x0010   /* write 1 to load CNT_MIN with zero */
+#define W1LMIN_CNT    0x0020   /* write 1 to load CNT_MIN from CNT_COUNTER */
+#define W1LMIN_MAX    0x0080   /* write 1 to load CNT_MIN from CNT_MAX */
+ 
+#define W1LMAX_ZERO   0x0100   /* write 1 to load CNT_MAX with zero */
+#define W1LMAX_CNT    0x0200   /* write 1 to load CNT_MAX from CNT_COUNTER */
+#define W1LMAX_MIN    0x0400   /* write 1 to load CNT_MAX from CNT_MIN */
+ 
+/* CNT_CONFIG bit field options */
+ 
+#define CNTMODE_QUADENC  0x0000  /* quadrature encoder mode */
+#define CNTMODE_BINENC   0x0100  /* binary encoder mode */
+#define CNTMODE_UDCNT    0x0200  /* up/down counter mode */
+#define CNTMODE_DIRCNT   0x0400  /* direction counter mode */
+#define CNTMODE_DIRTMR   0x0500  /* direction timer mode */
+ 
+#define BNDMODE_COMP     0x0000  /* boundary compare mode */
+#define BNDMODE_ZERO     0x1000  /* boundary compare and zero mode */
+#define BNDMODE_CAPT     0x2000  /* boundary capture mode */
+#define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
+
+/* TMODE in TIMERx_CONFIG bit field options */
+
+#define PWM_OUT  0x0001
+#define WDTH_CAP 0x0002
+#define EXT_CLK  0x0003
+
+/* UARTx_LCR bit field options */
+ 
+#define WLS_5   0x0000    /* 5 data bits */
+#define WLS_6   0x0001    /* 6 data bits */
+#define WLS_7   0x0002    /* 7 data bits */
+#define WLS_8   0x0003    /* 8 data bits */
+
+/* PINTx Register Bit Definitions */
+
+#define PIQ0 0x00000001
+#define PIQ1 0x00000002
+#define PIQ2 0x00000004
+#define PIQ3 0x00000008
+
+#define PIQ4 0x00000010
+#define PIQ5 0x00000020
+#define PIQ6 0x00000040
+#define PIQ7 0x00000080
+
+#define PIQ8 0x00000100
+#define PIQ9 0x00000200
+#define PIQ10 0x00000400
+#define PIQ11 0x00000800
+
+#define PIQ12 0x00001000
+#define PIQ13 0x00002000
+#define PIQ14 0x00004000
+#define PIQ15 0x00008000
+
+#define PIQ16 0x00010000
+#define PIQ17 0x00020000
+#define PIQ18 0x00040000
+#define PIQ19 0x00080000
+
+#define PIQ20 0x00100000
+#define PIQ21 0x00200000
+#define PIQ22 0x00400000
+#define PIQ23 0x00800000
+
+#define PIQ24 0x01000000
+#define PIQ25 0x02000000
+#define PIQ26 0x04000000
+#define PIQ27 0x08000000
+
+#define PIQ28 0x10000000
+#define PIQ29 0x20000000
+#define PIQ30 0x40000000
+#define PIQ31 0x80000000
+
+/* PORT A Bit Definitions for the registers 
+PORTA, PORTA_SET, PORTA_CLEAR,
+PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
+PORTA_FER registers
+*/
+
+#define PA0 0x0001
+#define PA1 0x0002
+#define PA2 0x0004
+#define PA3 0x0008
+#define PA4 0x0010
+#define PA5 0x0020
+#define PA6 0x0040
+#define PA7 0x0080
+#define PA8 0x0100
+#define PA9 0x0200
+#define PA10 0x0400
+#define PA11 0x0800
+#define PA12 0x1000
+#define PA13 0x2000
+#define PA14 0x4000
+#define PA15 0x8000
+
+/* PORT B Bit Definitions for the registers 
+PORTB, PORTB_SET, PORTB_CLEAR,
+PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
+PORTB_FER registers
+*/
+
+#define PB0 0x0001
+#define PB1 0x0002
+#define PB2 0x0004
+#define PB3 0x0008
+#define PB4 0x0010
+#define PB5 0x0020
+#define PB6 0x0040
+#define PB7 0x0080
+#define PB8 0x0100
+#define PB9 0x0200
+#define PB10 0x0400
+#define PB11 0x0800
+#define PB12 0x1000
+#define PB13 0x2000
+#define PB14 0x4000
+
+
+/* PORT C Bit Definitions for the registers 
+PORTC, PORTC_SET, PORTC_CLEAR,
+PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
+PORTC_FER registers
+*/
+
+
+#define PC0 0x0001
+#define PC1 0x0002
+#define PC2 0x0004
+#define PC3 0x0008
+#define PC4 0x0010
+#define PC5 0x0020
+#define PC6 0x0040
+#define PC7 0x0080
+#define PC8 0x0100
+#define PC9 0x0200
+#define PC10 0x0400
+#define PC11 0x0800
+#define PC12 0x1000
+#define PC13 0x2000
+
+
+/* PORT D Bit Definitions for the registers 
+PORTD, PORTD_SET, PORTD_CLEAR,
+PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
+PORTD_FER registers
+*/
+
+#define PD0 0x0001
+#define PD1 0x0002
+#define PD2 0x0004
+#define PD3 0x0008
+#define PD4 0x0010
+#define PD5 0x0020
+#define PD6 0x0040
+#define PD7 0x0080
+#define PD8 0x0100
+#define PD9 0x0200
+#define PD10 0x0400
+#define PD11 0x0800
+#define PD12 0x1000
+#define PD13 0x2000
+#define PD14 0x4000
+#define PD15 0x8000
+
+/* PORT E Bit Definitions for the registers 
+PORTE, PORTE_SET, PORTE_CLEAR,
+PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
+PORTE_FER registers
+*/
+
+
+#define PE0 0x0001
+#define PE1 0x0002
+#define PE2 0x0004
+#define PE3 0x0008
+#define PE4 0x0010
+#define PE5 0x0020
+#define PE6 0x0040
+#define PE7 0x0080
+#define PE8 0x0100
+#define PE9 0x0200
+#define PE10 0x0400
+#define PE11 0x0800
+#define PE12 0x1000
+#define PE13 0x2000
+#define PE14 0x4000
+#define PE15 0x8000
+
+/* PORT F Bit Definitions for the registers 
+PORTF, PORTF_SET, PORTF_CLEAR,
+PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
+PORTF_FER registers
+*/
+
+
+#define PF0 0x0001
+#define PF1 0x0002
+#define PF2 0x0004
+#define PF3 0x0008
+#define PF4 0x0010
+#define PF5 0x0020
+#define PF6 0x0040
+#define PF7 0x0080
+#define PF8 0x0100
+#define PF9 0x0200
+#define PF10 0x0400
+#define PF11 0x0800
+#define PF12 0x1000
+#define PF13 0x2000
+#define PF14 0x4000
+#define PF15 0x8000
+
+/* PORT G Bit Definitions for the registers 
+PORTG, PORTG_SET, PORTG_CLEAR,
+PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
+PORTG_FER registers
+*/
+
+
+#define PG0 0x0001
+#define PG1 0x0002
+#define PG2 0x0004
+#define PG3 0x0008
+#define PG4 0x0010
+#define PG5 0x0020
+#define PG6 0x0040
+#define PG7 0x0080
+#define PG8 0x0100
+#define PG9 0x0200
+#define PG10 0x0400
+#define PG11 0x0800
+#define PG12 0x1000
+#define PG13 0x2000
+#define PG14 0x4000
+#define PG15 0x8000
+
+/* PORT H Bit Definitions for the registers 
+PORTH, PORTH_SET, PORTH_CLEAR,
+PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
+PORTH_FER registers
+*/
+
+
+#define PH0 0x0001
+#define PH1 0x0002
+#define PH2 0x0004
+#define PH3 0x0008
+#define PH4 0x0010
+#define PH5 0x0020
+#define PH6 0x0040
+#define PH7 0x0080
+#define PH8 0x0100
+#define PH9 0x0200
+#define PH10 0x0400
+#define PH11 0x0800
+#define PH12 0x1000
+#define PH13 0x2000
+
+
+/* PORT I Bit Definitions for the registers 
+PORTI, PORTI_SET, PORTI_CLEAR,
+PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
+PORTI_FER registers
+*/
+
+
+#define PI0 0x0001
+#define PI1 0x0002
+#define PI2 0x0004
+#define PI3 0x0008
+#define PI4 0x0010
+#define PI5 0x0020
+#define PI6 0x0040
+#define PI7 0x0080
+#define PI8 0x0100
+#define PI9 0x0200
+#define PI10 0x0400
+#define PI11 0x0800
+#define PI12 0x1000
+#define PI13 0x2000
+#define PI14 0x4000
+#define PI15 0x8000
+
+/* PORT J Bit Definitions for the registers 
+PORTJ, PORTJ_SET, PORTJ_CLEAR,
+PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
+PORTJ_FER registers
+*/
+
+
+#define PJ0 0x0001
+#define PJ1 0x0002
+#define PJ2 0x0004
+#define PJ3 0x0008
+#define PJ4 0x0010
+#define PJ5 0x0020
+#define PJ6 0x0040
+#define PJ7 0x0080
+#define PJ8 0x0100
+#define PJ9 0x0200
+#define PJ10 0x0400
+#define PJ11 0x0800
+#define PJ12 0x1000
+#define PJ13 0x2000
+ 
+
+/* Port Muxing Bit Fields for PORTx_MUX Registers */
+
+#define MUX0 0x00000003
+#define MUX0_0 0x00000000
+#define MUX0_1 0x00000001
+#define MUX0_2 0x00000002
+#define MUX0_3 0x00000003
+
+#define MUX1 0x0000000C
+#define MUX1_0 0x00000000
+#define MUX1_1 0x00000004
+#define MUX1_2 0x00000008
+#define MUX1_3 0x0000000C
+
+#define MUX2 0x00000030
+#define MUX2_0 0x00000000
+#define MUX2_1 0x00000010
+#define MUX2_2 0x00000020
+#define MUX2_3 0x00000030
+
+#define MUX3 0x000000C0
+#define MUX3_0 0x00000000
+#define MUX3_1 0x00000040
+#define MUX3_2 0x00000080
+#define MUX3_3 0x000000C0
+
+#define MUX4 0x00000300
+#define MUX4_0 0x00000000
+#define MUX4_1 0x00000100
+#define MUX4_2 0x00000200
+#define MUX4_3 0x00000300
+
+#define MUX5 0x00000C00
+#define MUX5_0 0x00000000
+#define MUX5_1 0x00000400
+#define MUX5_2 0x00000800
+#define MUX5_3 0x00000C00
+
+#define MUX6 0x00003000
+#define MUX6_0 0x00000000
+#define MUX6_1 0x00001000
+#define MUX6_2 0x00002000
+#define MUX6_3 0x00003000
+
+#define MUX7 0x0000C000
+#define MUX7_0 0x00000000
+#define MUX7_1 0x00004000
+#define MUX7_2 0x00008000
+#define MUX7_3 0x0000C000
+
+#define MUX8 0x00030000
+#define MUX8_0 0x00000000
+#define MUX8_1 0x00010000
+#define MUX8_2 0x00020000
+#define MUX8_3 0x00030000
+
+#define MUX9 0x000C0000
+#define MUX9_0 0x00000000
+#define MUX9_1 0x00040000
+#define MUX9_2 0x00080000
+#define MUX9_3 0x000C0000
+
+#define MUX10 0x00300000
+#define MUX10_0 0x00000000
+#define MUX10_1 0x00100000
+#define MUX10_2 0x00200000
+#define MUX10_3 0x00300000
+
+#define MUX11 0x00C00000
+#define MUX11_0 0x00000000
+#define MUX11_1 0x00400000
+#define MUX11_2 0x00800000
+#define MUX11_3 0x00C00000
+
+#define MUX12 0x03000000
+#define MUX12_0 0x00000000
+#define MUX12_1 0x01000000
+#define MUX12_2 0x02000000
+#define MUX12_3 0x03000000
+
+#define MUX13 0x0C000000
+#define MUX13_0 0x00000000
+#define MUX13_1 0x04000000
+#define MUX13_2 0x08000000
+#define MUX13_3 0x0C000000
+
+#define MUX14 0x30000000
+#define MUX14_0 0x00000000
+#define MUX14_1 0x10000000
+#define MUX14_2 0x20000000
+#define MUX14_3 0x30000000
+
+#define MUX15 0xC0000000
+#define MUX15_0 0x00000000
+#define MUX15_1 0x40000000
+#define MUX15_2 0x80000000
+#define MUX15_3 0xC0000000
+
+#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
+    ((((b15)&3) << 30) | \
+     (((b14)&3) << 28) | \
+     (((b13)&3) << 26) | \
+     (((b12)&3) << 24) | \
+     (((b11)&3) << 22) | \
+     (((b10)&3) << 20) | \
+     (((b9) &3) << 18) | \
+     (((b8) &3) << 16) | \
+     (((b7) &3) << 14) | \
+     (((b6) &3) << 12) | \
+     (((b5) &3) << 10) | \
+     (((b4) &3) << 8)  | \
+     (((b3) &3) << 6)  | \
+     (((b2) &3) << 4)  | \
+     (((b1) &3) << 2)  | \
+     (((b0) &3)))
+
+/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
+
+#define B0MAP 0x000000FF     /* Byte 0 Lower Half Port Mapping */
+#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
+#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
+#define B1MAP 0x0000FF00     /* Byte 1 Upper Half Port Mapping */
+#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
+#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
+#define B2MAP 0x00FF0000     /* Byte 2 Lower Half Port Mapping */
+#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
+#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
+#define B3MAP 0xFF000000     /* Byte 3 Upper Half Port Mapping */
+#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
+#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
+
+/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
+
+#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
+#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
+#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
+#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
+#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
+#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
+#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
+#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
+
+#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ 
+#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
+#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
+#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
+#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
+#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
+#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
+#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
+
+#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ 
+#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ 
+#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ 
+#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ 
+#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ 
+#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ 
+#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ 
+#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ 
+
+#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ 
+#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ 
+#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ 
+#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ 
+#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ 
+#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ 
+#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ 
+#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ 
+
+
+/* for legacy compatibility */
+ 
+#define WLS(x)  (((x)-5) & 0x03) /* Word Length Select */
+#define W1LMAX_MAX W1LMAX_MIN
+#define EBIU_AMCBCTL0 EBIU_AMBCTL0
+#define EBIU_AMCBCTL1 EBIU_AMBCTL1
+#define PINT0_IRQ PINT0_REQUEST
+#define PINT1_IRQ PINT1_REQUEST
+#define PINT2_IRQ PINT2_REQUEST
+#define PINT3_IRQ PINT3_REQUEST
+
+#endif /* _DEF_BF54X_H */
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 5dc0ed835447..b14f872e5703 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -59,12 +59,14 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 {
         unsigned long flags, iwr;
 
-        bfin_write16(VR_CTL, val);
-        __builtin_bfin_ssync();
         /* Enable the PLL Wakeup bit in SIC IWR */
         iwr = bfin_read32(SICA_IWR0);
         /* Only allow PPL Wakeup) */
         bfin_write32(SICA_IWR0, IWR_ENABLE(0));
+
+        bfin_write16(VR_CTL, val);
+        __builtin_bfin_ssync();
+
         local_irq_save(flags);
         asm("IDLE;");
         local_irq_restore(flags);
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index a6de4c69ba55..89150ecb909d 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -904,23 +904,6 @@
 #define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
 
-/* *********  WATCHDOG TIMER MASKS  ********************8 */
-
-/* Watchdog Timer WDOG_CTL Register */
-#define ICTL(x) ((x<<1) & 0x0006)
-#define ENABLE_RESET     0x00000000     /* Set Watchdog Timer to generate reset */
-#define ENABLE_NMI       0x00000002     /* Set Watchdog Timer to generate non-maskable interrupt */
-#define ENABLE_GPI       0x00000004     /* Set Watchdog Timer to generate general-purpose interrupt */
-#define DISABLE_EVT      0x00000006     /* Disable Watchdog Timer interrupts */
-
-#define TMR_EN          0x0000
-#define TMR_DIS         0x0AD0
-#define TRO             0x8000
-
-#define ICTL_P0         0x01
-#define ICTL_P1         0x02
-#define TRO_P           0x0F
-
 /* ***************************** UART CONTROLLER MASKS ********************** */
 
 /* UART_LCR Register */
@@ -1214,18 +1197,18 @@
 #define TIMIL9          0x0002
 #define TIMIL10         0x0004
 #define TIMIL11         0x0008
-#define TOVL_ERR0       0x00000010
-#define TOVL_ERR1       0x00000020
-#define TOVL_ERR2       0x00000040
-#define TOVL_ERR3       0x00000080
-#define TOVL_ERR4       0x00100000
-#define TOVL_ERR5       0x00200000
-#define TOVL_ERR6       0x00400000
-#define TOVL_ERR7       0x00800000
-#define TOVL_ERR8       0x0010
-#define TOVL_ERR9       0x0020
-#define TOVL_ERR10      0x0040
-#define TOVL_ERR11      0x0080
+#define TOVF_ERR0       0x00000010
+#define TOVF_ERR1       0x00000020
+#define TOVF_ERR2       0x00000040
+#define TOVF_ERR3       0x00000080
+#define TOVF_ERR4       0x00100000
+#define TOVF_ERR5       0x00200000
+#define TOVF_ERR6       0x00400000
+#define TOVF_ERR7       0x00800000
+#define TOVF_ERR8       0x0010
+#define TOVF_ERR9       0x0020
+#define TOVF_ERR10      0x0040
+#define TOVF_ERR11      0x0080
 #define TRUN0           0x00001000
 #define TRUN1           0x00002000
 #define TRUN2           0x00004000
@@ -1251,18 +1234,18 @@
 #define TIMIL9_P        0x01
 #define TIMIL10_P       0x02
 #define TIMIL11_P       0x03
-#define TOVL_ERR0_P     0x04
-#define TOVL_ERR1_P     0x05
-#define TOVL_ERR2_P     0x06
-#define TOVL_ERR3_P     0x07
-#define TOVL_ERR4_P     0x14
-#define TOVL_ERR5_P     0x15
-#define TOVL_ERR6_P     0x16
-#define TOVL_ERR7_P     0x17
-#define TOVL_ERR8_P     0x04
-#define TOVL_ERR9_P     0x05
-#define TOVL_ERR10_P    0x06
-#define TOVL_ERR11_P    0x07
+#define TOVF_ERR0_P     0x04
+#define TOVF_ERR1_P     0x05
+#define TOVF_ERR2_P     0x06
+#define TOVF_ERR3_P     0x07
+#define TOVF_ERR4_P     0x14
+#define TOVF_ERR5_P     0x15
+#define TOVF_ERR6_P     0x16
+#define TOVF_ERR7_P     0x17
+#define TOVF_ERR8_P     0x04
+#define TOVF_ERR9_P     0x05
+#define TOVF_ERR10_P    0x06
+#define TOVF_ERR11_P    0x07
 #define TRUN0_P         0x0C
 #define TRUN1_P         0x0D
 #define TRUN2_P         0x0E
@@ -1276,6 +1259,32 @@
 #define TRUN10_P        0x0E
 #define TRUN11_P        0x0F
 
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+#define TOVL_ERR8 TOVF_ERR8
+#define TOVL_ERR9 TOVF_ERR9
+#define TOVL_ERR10 TOVF_ERR10
+#define TOVL_ERR11 TOVF_ERR11
+#define TOVL_ERR0_P TOVF_ERR0_P
+#define TOVL_ERR1_P TOVF_ERR1_P
+#define TOVL_ERR2_P TOVF_ERR2_P
+#define TOVL_ERR3_P TOVF_ERR3_P
+#define TOVL_ERR4_P TOVF_ERR4_P
+#define TOVL_ERR5_P TOVF_ERR5_P
+#define TOVL_ERR6_P TOVF_ERR6_P
+#define TOVL_ERR7_P TOVF_ERR7_P
+#define TOVL_ERR8_P TOVF_ERR8_P
+#define TOVL_ERR9_P TOVF_ERR9_P
+#define TOVL_ERR10_P TOVF_ERR10_P
+#define TOVL_ERR11_P TOVF_ERR11_P
+
 /* TIMERx_CONFIG Registers */
 #define PWM_OUT         0x0001
 #define WDTH_CAP        0x0002
@@ -1700,18 +1709,4 @@
 #define SDEASE              0x00000010  /* SDRAM EAB sticky error status - W1C */
 #define BGSTAT                  0x00000020      /* Bus granted */
 
-/*VR_CTL Masks*/
-#define WAKE                    0x100
-#define VLEV_6                  0x60
-#define VLEV_7                  0x70
-#define VLEV_8                  0x80
-#define VLEV_9                  0x90
-#define VLEV_10                 0xA0
-#define VLEV_11                 0xB0
-#define VLEV_12                 0xC0
-#define VLEV_13                 0xD0
-#define VLEV_14                 0xE0
-#define VLEV_15                 0xF0
-#define FREQ_3                  0x03
-
 #endif                          /* _DEF_BF561_H */
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
index 22aa5e637993..d39c396f850d 100644
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -36,417 +36,288 @@
 #include <asm/mach-common/def_LPBlackfin.h>
 
 /*Cache & SRAM Memory*/
-#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
 #define bfin_read_SRAM_BASE_ADDRESS()        bfin_read32(SRAM_BASE_ADDRESS)
 #define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
-#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
 #define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
-#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
 #define bfin_read_DCPLB_STATUS()             bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)         bfin_write32(DCPLB_STATUS,val)
-#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
 #define bfin_read_DCPLB_FAULT_ADDR()         bfin_read32(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val)     bfin_write32(DCPLB_FAULT_ADDR,val)
 /*
 #define MMR_TIMEOUT            0xFFE00010
 */
-#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
 #define bfin_read_DCPLB_ADDR0()              bfin_read32(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)          bfin_write32(DCPLB_ADDR0,val)
-#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
 #define bfin_read_DCPLB_ADDR1()              bfin_read32(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)          bfin_write32(DCPLB_ADDR1,val)
-#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
 #define bfin_read_DCPLB_ADDR2()              bfin_read32(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)          bfin_write32(DCPLB_ADDR2,val)
-#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3)
 #define bfin_read_DCPLB_ADDR3()              bfin_read32(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)          bfin_write32(DCPLB_ADDR3,val)
-#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4)
 #define bfin_read_DCPLB_ADDR4()              bfin_read32(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)          bfin_write32(DCPLB_ADDR4,val)
-#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5)
 #define bfin_read_DCPLB_ADDR5()              bfin_read32(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)          bfin_write32(DCPLB_ADDR5,val)
-#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6)
 #define bfin_read_DCPLB_ADDR6()              bfin_read32(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)          bfin_write32(DCPLB_ADDR6,val)
-#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7)
 #define bfin_read_DCPLB_ADDR7()              bfin_read32(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)          bfin_write32(DCPLB_ADDR7,val)
-#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8)
 #define bfin_read_DCPLB_ADDR8()              bfin_read32(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)          bfin_write32(DCPLB_ADDR8,val)
-#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9)
 #define bfin_read_DCPLB_ADDR9()              bfin_read32(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)          bfin_write32(DCPLB_ADDR9,val)
-#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10)
 #define bfin_read_DCPLB_ADDR10()             bfin_read32(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)         bfin_write32(DCPLB_ADDR10,val)
-#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11)
 #define bfin_read_DCPLB_ADDR11()             bfin_read32(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)         bfin_write32(DCPLB_ADDR11,val)
-#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12)
 #define bfin_read_DCPLB_ADDR12()             bfin_read32(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)         bfin_write32(DCPLB_ADDR12,val)
-#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13)
 #define bfin_read_DCPLB_ADDR13()             bfin_read32(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)         bfin_write32(DCPLB_ADDR13,val)
-#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14)
 #define bfin_read_DCPLB_ADDR14()             bfin_read32(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)         bfin_write32(DCPLB_ADDR14,val)
-#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15)
 #define bfin_read_DCPLB_ADDR15()             bfin_read32(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)         bfin_write32(DCPLB_ADDR15,val)
-#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
 #define bfin_read_DCPLB_DATA0()              bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)          bfin_write32(DCPLB_DATA0,val)
-#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
 #define bfin_read_DCPLB_DATA1()              bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)          bfin_write32(DCPLB_DATA1,val)
-#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
 #define bfin_read_DCPLB_DATA2()              bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)          bfin_write32(DCPLB_DATA2,val)
-#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
 #define bfin_read_DCPLB_DATA3()              bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)          bfin_write32(DCPLB_DATA3,val)
-#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
 #define bfin_read_DCPLB_DATA4()              bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)          bfin_write32(DCPLB_DATA4,val)
-#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
 #define bfin_read_DCPLB_DATA5()              bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)          bfin_write32(DCPLB_DATA5,val)
-#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
 #define bfin_read_DCPLB_DATA6()              bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)          bfin_write32(DCPLB_DATA6,val)
-#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
 #define bfin_read_DCPLB_DATA7()              bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)          bfin_write32(DCPLB_DATA7,val)
-#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
 #define bfin_read_DCPLB_DATA8()              bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)          bfin_write32(DCPLB_DATA8,val)
-#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
 #define bfin_read_DCPLB_DATA9()              bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)          bfin_write32(DCPLB_DATA9,val)
-#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
 #define bfin_read_DCPLB_DATA10()             bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)         bfin_write32(DCPLB_DATA10,val)
-#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
 #define bfin_read_DCPLB_DATA11()             bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)         bfin_write32(DCPLB_DATA11,val)
-#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
 #define bfin_read_DCPLB_DATA12()             bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)         bfin_write32(DCPLB_DATA12,val)
-#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
 #define bfin_read_DCPLB_DATA13()             bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)         bfin_write32(DCPLB_DATA13,val)
-#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
 #define bfin_read_DCPLB_DATA14()             bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)         bfin_write32(DCPLB_DATA14,val)
-#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
 #define bfin_read_DCPLB_DATA15()             bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)         bfin_write32(DCPLB_DATA15,val)
-#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
 #define bfin_read_DTEST_COMMAND()            bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)        bfin_write32(DTEST_COMMAND,val)
 /*
 #define DTEST_INDEX            0xFFE00304
 */
-#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
 #define bfin_read_DTEST_DATA0()              bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)          bfin_write32(DTEST_DATA0,val)
-#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
 #define bfin_read_DTEST_DATA1()              bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)          bfin_write32(DTEST_DATA1,val)
 /*
 #define DTEST_DATA2            0xFFE00408
 #define DTEST_DATA3            0xFFE0040C
 */
-#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
 #define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
-#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
 #define bfin_read_ICPLB_STATUS()             bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)         bfin_write32(ICPLB_STATUS,val)
-#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
 #define bfin_read_ICPLB_FAULT_ADDR()         bfin_read32(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val)     bfin_write32(ICPLB_FAULT_ADDR,val)
-#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0)
 #define bfin_read_ICPLB_ADDR0()              bfin_read32(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)          bfin_write32(ICPLB_ADDR0,val)
-#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1)
 #define bfin_read_ICPLB_ADDR1()              bfin_read32(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)          bfin_write32(ICPLB_ADDR1,val)
-#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2)
 #define bfin_read_ICPLB_ADDR2()              bfin_read32(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)          bfin_write32(ICPLB_ADDR2,val)
-#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3)
 #define bfin_read_ICPLB_ADDR3()              bfin_read32(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)          bfin_write32(ICPLB_ADDR3,val)
-#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4)
 #define bfin_read_ICPLB_ADDR4()              bfin_read32(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)          bfin_write32(ICPLB_ADDR4,val)
-#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5)
 #define bfin_read_ICPLB_ADDR5()              bfin_read32(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)          bfin_write32(ICPLB_ADDR5,val)
-#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6)
 #define bfin_read_ICPLB_ADDR6()              bfin_read32(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)          bfin_write32(ICPLB_ADDR6,val)
-#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7)
 #define bfin_read_ICPLB_ADDR7()              bfin_read32(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)          bfin_write32(ICPLB_ADDR7,val)
-#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8)
 #define bfin_read_ICPLB_ADDR8()              bfin_read32(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)          bfin_write32(ICPLB_ADDR8,val)
-#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9)
 #define bfin_read_ICPLB_ADDR9()              bfin_read32(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)          bfin_write32(ICPLB_ADDR9,val)
-#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10)
 #define bfin_read_ICPLB_ADDR10()             bfin_read32(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)         bfin_write32(ICPLB_ADDR10,val)
-#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11)
 #define bfin_read_ICPLB_ADDR11()             bfin_read32(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)         bfin_write32(ICPLB_ADDR11,val)
-#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12)
 #define bfin_read_ICPLB_ADDR12()             bfin_read32(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)         bfin_write32(ICPLB_ADDR12,val)
-#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13)
 #define bfin_read_ICPLB_ADDR13()             bfin_read32(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)         bfin_write32(ICPLB_ADDR13,val)
-#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14)
 #define bfin_read_ICPLB_ADDR14()             bfin_read32(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)         bfin_write32(ICPLB_ADDR14,val)
-#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15)
 #define bfin_read_ICPLB_ADDR15()             bfin_read32(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)         bfin_write32(ICPLB_ADDR15,val)
-#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
 #define bfin_read_ICPLB_DATA0()              bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)          bfin_write32(ICPLB_DATA0,val)
-#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
 #define bfin_read_ICPLB_DATA1()              bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)          bfin_write32(ICPLB_DATA1,val)
-#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
 #define bfin_read_ICPLB_DATA2()              bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)          bfin_write32(ICPLB_DATA2,val)
-#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
 #define bfin_read_ICPLB_DATA3()              bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)          bfin_write32(ICPLB_DATA3,val)
-#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
 #define bfin_read_ICPLB_DATA4()              bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)          bfin_write32(ICPLB_DATA4,val)
-#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
 #define bfin_read_ICPLB_DATA5()              bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)          bfin_write32(ICPLB_DATA5,val)
-#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
 #define bfin_read_ICPLB_DATA6()              bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)          bfin_write32(ICPLB_DATA6,val)
-#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
 #define bfin_read_ICPLB_DATA7()              bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)          bfin_write32(ICPLB_DATA7,val)
-#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
 #define bfin_read_ICPLB_DATA8()              bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)          bfin_write32(ICPLB_DATA8,val)
-#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
 #define bfin_read_ICPLB_DATA9()              bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)          bfin_write32(ICPLB_DATA9,val)
-#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
 #define bfin_read_ICPLB_DATA10()             bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)         bfin_write32(ICPLB_DATA10,val)
-#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
 #define bfin_read_ICPLB_DATA11()             bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)         bfin_write32(ICPLB_DATA11,val)
-#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
 #define bfin_read_ICPLB_DATA12()             bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)         bfin_write32(ICPLB_DATA12,val)
-#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
 #define bfin_read_ICPLB_DATA13()             bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)         bfin_write32(ICPLB_DATA13,val)
-#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
 #define bfin_read_ICPLB_DATA14()             bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)         bfin_write32(ICPLB_DATA14,val)
-#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
 #define bfin_read_ICPLB_DATA15()             bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)         bfin_write32(ICPLB_DATA15,val)
-#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
 #define bfin_read_ITEST_COMMAND()            bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)        bfin_write32(ITEST_COMMAND,val)
 #if 0
 #define ITEST_INDEX            0xFFE01304   /* Instruction Test Index Register */
 #endif
-#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
 #define bfin_read_ITEST_DATA0()              bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)          bfin_write32(ITEST_DATA0,val)
-#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
 #define bfin_read_ITEST_DATA1()              bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)          bfin_write32(ITEST_DATA1,val)
 
 /* Event/Interrupt Registers*/
 
-#define pEVT0 ((volatile void **)EVT0)
 #define bfin_read_EVT0()                     bfin_read32(EVT0)
 #define bfin_write_EVT0(val)                 bfin_write32(EVT0,val)
-#define pEVT1 ((volatile void **)EVT1)
 #define bfin_read_EVT1()                     bfin_read32(EVT1)
 #define bfin_write_EVT1(val)                 bfin_write32(EVT1,val)
-#define pEVT2 ((volatile void **)EVT2)
 #define bfin_read_EVT2()                     bfin_read32(EVT2)
 #define bfin_write_EVT2(val)                 bfin_write32(EVT2,val)
-#define pEVT3 ((volatile void **)EVT3)
 #define bfin_read_EVT3()                     bfin_read32(EVT3)
 #define bfin_write_EVT3(val)                 bfin_write32(EVT3,val)
-#define pEVT4 ((volatile void **)EVT4)
 #define bfin_read_EVT4()                     bfin_read32(EVT4)
 #define bfin_write_EVT4(val)                 bfin_write32(EVT4,val)
-#define pEVT5 ((volatile void **)EVT5)
 #define bfin_read_EVT5()                     bfin_read32(EVT5)
 #define bfin_write_EVT5(val)                 bfin_write32(EVT5,val)
-#define pEVT6 ((volatile void **)EVT6)
 #define bfin_read_EVT6()                     bfin_read32(EVT6)
 #define bfin_write_EVT6(val)                 bfin_write32(EVT6,val)
-#define pEVT7 ((volatile void **)EVT7)
 #define bfin_read_EVT7()                     bfin_read32(EVT7)
 #define bfin_write_EVT7(val)                 bfin_write32(EVT7,val)
-#define pEVT8 ((volatile void **)EVT8)
 #define bfin_read_EVT8()                     bfin_read32(EVT8)
 #define bfin_write_EVT8(val)                 bfin_write32(EVT8,val)
-#define pEVT9 ((volatile void **)EVT9)
 #define bfin_read_EVT9()                     bfin_read32(EVT9)
 #define bfin_write_EVT9(val)                 bfin_write32(EVT9,val)
-#define pEVT10 ((volatile void **)EVT10)
 #define bfin_read_EVT10()                    bfin_read32(EVT10)
 #define bfin_write_EVT10(val)                bfin_write32(EVT10,val)
-#define pEVT11 ((volatile void **)EVT11)
 #define bfin_read_EVT11()                    bfin_read32(EVT11)
 #define bfin_write_EVT11(val)                bfin_write32(EVT11,val)
-#define pEVT12 ((volatile void **)EVT12)
 #define bfin_read_EVT12()                    bfin_read32(EVT12)
 #define bfin_write_EVT12(val)                bfin_write32(EVT12,val)
-#define pEVT13 ((volatile void **)EVT13)
 #define bfin_read_EVT13()                    bfin_read32(EVT13)
 #define bfin_write_EVT13(val)                bfin_write32(EVT13,val)
-#define pEVT14 ((volatile void **)EVT14)
 #define bfin_read_EVT14()                    bfin_read32(EVT14)
 #define bfin_write_EVT14(val)                bfin_write32(EVT14,val)
-#define pEVT15 ((volatile void **)EVT15)
 #define bfin_read_EVT15()                    bfin_read32(EVT15)
 #define bfin_write_EVT15(val)                bfin_write32(EVT15,val)
-#define pIMASK ((volatile unsigned long *)IMASK)
 #define bfin_read_IMASK()                    bfin_read32(IMASK)
 #define bfin_write_IMASK(val)                bfin_write32(IMASK,val)
-#define pIPEND ((volatile unsigned long *)IPEND)
 #define bfin_read_IPEND()                    bfin_read32(IPEND)
 #define bfin_write_IPEND(val)                bfin_write32(IPEND,val)
-#define pILAT ((volatile unsigned long *)ILAT)
 #define bfin_read_ILAT()                     bfin_read32(ILAT)
 #define bfin_write_ILAT(val)                 bfin_write32(ILAT,val)
 
 /*Core Timer Registers*/
-#define pTCNTL ((volatile unsigned long *)TCNTL)
 #define bfin_read_TCNTL()                    bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)                bfin_write32(TCNTL,val)
-#define pTPERIOD ((volatile unsigned long *)TPERIOD)
 #define bfin_read_TPERIOD()                  bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)              bfin_write32(TPERIOD,val)
-#define pTSCALE ((volatile unsigned long *)TSCALE)
 #define bfin_read_TSCALE()                   bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)               bfin_write32(TSCALE,val)
-#define pTCOUNT ((volatile unsigned long *)TCOUNT)
 #define bfin_read_TCOUNT()                   bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)               bfin_write32(TCOUNT,val)
 
 /*Debug/MP/Emulation Registers*/
-#define pDSPID ((volatile unsigned long *)DSPID)
 #define bfin_read_DSPID()                    bfin_read32(DSPID)
 #define bfin_write_DSPID(val)                bfin_write32(DSPID,val)
-#define pDBGCTL ((volatile unsigned long *)DBGCTL)
 #define bfin_read_DBGCTL()                   bfin_read32(DBGCTL)
 #define bfin_write_DBGCTL(val)               bfin_write32(DBGCTL,val)
-#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
 #define bfin_read_DBGSTAT()                  bfin_read32(DBGSTAT)
 #define bfin_write_DBGSTAT(val)              bfin_write32(DBGSTAT,val)
-#define pEMUDAT ((volatile unsigned long *)EMUDAT)
 #define bfin_read_EMUDAT()                   bfin_read32(EMUDAT)
 #define bfin_write_EMUDAT(val)               bfin_write32(EMUDAT,val)
 
 /*Trace Buffer Registers*/
-#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
 #define bfin_read_TBUFCTL()                  bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)              bfin_write32(TBUFCTL,val)
-#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
 #define bfin_read_TBUFSTAT()                 bfin_read32(TBUFSTAT)
 #define bfin_write_TBUFSTAT(val)             bfin_write32(TBUFSTAT,val)
-#define pTBUF ((volatile void **)TBUF)
 #define bfin_read_TBUF()                     bfin_read32(TBUF)
 #define bfin_write_TBUF(val)                 bfin_write32(TBUF,val)
 
 /*Watch Point Control Registers*/
-#define pWPIACTL ((volatile unsigned long *)WPIACTL)
 #define bfin_read_WPIACTL()                  bfin_read32(WPIACTL)
 #define bfin_write_WPIACTL(val)              bfin_write32(WPIACTL,val)
-#define pWPIA0 ((volatile void **)WPIA0)
 #define bfin_read_WPIA0()                    bfin_read32(WPIA0)
 #define bfin_write_WPIA0(val)                bfin_write32(WPIA0,val)
-#define pWPIA1 ((volatile void **)WPIA1)
 #define bfin_read_WPIA1()                    bfin_read32(WPIA1)
 #define bfin_write_WPIA1(val)                bfin_write32(WPIA1,val)
-#define pWPIA2 ((volatile void **)WPIA2)
 #define bfin_read_WPIA2()                    bfin_read32(WPIA2)
 #define bfin_write_WPIA2(val)                bfin_write32(WPIA2,val)
-#define pWPIA3 ((volatile void **)WPIA3)
 #define bfin_read_WPIA3()                    bfin_read32(WPIA3)
 #define bfin_write_WPIA3(val)                bfin_write32(WPIA3,val)
-#define pWPIA4 ((volatile void **)WPIA4)
 #define bfin_read_WPIA4()                    bfin_read32(WPIA4)
 #define bfin_write_WPIA4(val)                bfin_write32(WPIA4,val)
-#define pWPIA5 ((volatile void **)WPIA5)
 #define bfin_read_WPIA5()                    bfin_read32(WPIA5)
 #define bfin_write_WPIA5(val)                bfin_write32(WPIA5,val)
-#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
 #define bfin_read_WPIACNT0()                 bfin_read32(WPIACNT0)
 #define bfin_write_WPIACNT0(val)             bfin_write32(WPIACNT0,val)
-#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
 #define bfin_read_WPIACNT1()                 bfin_read32(WPIACNT1)
 #define bfin_write_WPIACNT1(val)             bfin_write32(WPIACNT1,val)
-#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
 #define bfin_read_WPIACNT2()                 bfin_read32(WPIACNT2)
 #define bfin_write_WPIACNT2(val)             bfin_write32(WPIACNT2,val)
-#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
 #define bfin_read_WPIACNT3()                 bfin_read32(WPIACNT3)
 #define bfin_write_WPIACNT3(val)             bfin_write32(WPIACNT3,val)
-#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
 #define bfin_read_WPIACNT4()                 bfin_read32(WPIACNT4)
 #define bfin_write_WPIACNT4(val)             bfin_write32(WPIACNT4,val)
-#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
 #define bfin_read_WPIACNT5()                 bfin_read32(WPIACNT5)
 #define bfin_write_WPIACNT5(val)             bfin_write32(WPIACNT5,val)
-#define pWPDACTL ((volatile unsigned long *)WPDACTL)
 #define bfin_read_WPDACTL()                  bfin_read32(WPDACTL)
 #define bfin_write_WPDACTL(val)              bfin_write32(WPDACTL,val)
-#define pWPDA0 ((volatile void **)WPDA0)
 #define bfin_read_WPDA0()                    bfin_read32(WPDA0)
 #define bfin_write_WPDA0(val)                bfin_write32(WPDA0,val)
-#define pWPDA1 ((volatile void **)WPDA1)
 #define bfin_read_WPDA1()                    bfin_read32(WPDA1)
 #define bfin_write_WPDA1(val)                bfin_write32(WPDA1,val)
-#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
 #define bfin_read_WPDACNT0()                 bfin_read32(WPDACNT0)
 #define bfin_write_WPDACNT0(val)             bfin_write32(WPDACNT0,val)
-#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
 #define bfin_read_WPDACNT1()                 bfin_read32(WPDACNT1)
 #define bfin_write_WPDACNT1(val)             bfin_write32(WPDACNT1,val)
-#define pWPSTAT ((volatile unsigned long *)WPSTAT)
 #define bfin_read_WPSTAT()                   bfin_read32(WPSTAT)
 #define bfin_write_WPSTAT(val)               bfin_write32(WPSTAT,val)
 
 /*Performance Monitor Registers*/
-#define pPFCTL ((volatile unsigned long *)PFCTL)
 #define bfin_read_PFCTL()                    bfin_read32(PFCTL)
 #define bfin_write_PFCTL(val)                bfin_write32(PFCTL,val)
-#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
 #define bfin_read_PFCNTR0()                  bfin_read32(PFCNTR0)
 #define bfin_write_PFCNTR0(val)              bfin_write32(PFCNTR0,val)
-#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
 #define bfin_read_PFCNTR1()                  bfin_read32(PFCNTR1)
 #define bfin_write_PFCNTR1(val)              bfin_write32(PFCNTR1,val)
 
@@ -454,18 +325,4 @@
 #define IPRIO                  0xFFE02110
 */
 
-#if defined(CONFIG_BFIN_ALIVE_LED)
-#define pCONFIG_BFIN_ALIVE_LED_DPORT \
-        (volatile unsigned short *)CONFIG_BFIN_ALIVE_LED_DPORT
-#define pCONFIG_BFIN_ALIVE_LED_PORT \
-        (volatile unsigned short *)CONFIG_BFIN_ALIVE_LED_PORT
-#endif
-
-#if defined(CONFIG_BFIN_IDLE_LED)
-#define pCONFIG_BFIN_IDLE_LED_DPORT \
-        (volatile unsigned short *)CONFIG_BFIN_IDLE_LED_DPORT
-#define pCONFIG_BFIN_IDLE_LED_PORT \
-        (volatile unsigned short *)CONFIG_BFIN_IDLE_LED_PORT
-#endif
-
 #endif                          /* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
index 0336ff132c16..aba2b30a8ed8 100644
--- a/include/asm-blackfin/processor.h
+++ b/include/asm-blackfin/processor.h
@@ -104,13 +104,13 @@ unsigned long get_wchan(struct task_struct *p);
 #define cpu_relax()     barrier()
 
 /* Get the Silicon Revision of the chip */
-static inline uint32_t bfin_revid(void)
+static inline __attribute_pure__ uint32_t bfin_revid(void)
 {
         /* stored in the upper 4 bits */
         return bfin_read_CHIPID() >> 28;
 }
 
-static inline uint32_t bfin_compiled_revid(void)
+static inline __attribute_pure__ uint32_t bfin_compiled_revid(void)
 {
 #if defined(CONFIG_BF_REV_0_0)
         return 0;
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index bfcb6794c672..2233f8f9314d 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -14,7 +14,7 @@
 #include <linux/string.h>
 
 #include <asm/segment.h>
-#ifndef CONFIG_NO_ACCESS_CHECK
+#ifdef CONFIG_ACCESS_CHECK
 # include <asm/bfin-global.h>
 #endif
 
@@ -56,7 +56,7 @@ static inline int is_in_rom(unsigned long addr)
  * get_fs() == KERNEL_DS, checking is bypassed.
  */
 
-#ifdef CONFIG_NO_ACCESS_CHECK
+#ifndef CONFIG_ACCESS_CHECK
 static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
 #else
 #ifdef CONFIG_ACCESS_OK_L1
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 14fae1fa87df..7f30cce52857 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -35,7 +35,7 @@ struct bug_entry {
 #define WARN_ON(condition) ({                                           \
         typeof(condition) __ret_warn_on = (condition);                  \
         if (unlikely(__ret_warn_on)) {                                  \
-                printk("BUG: at %s:%d %s()\n", __FILE__,                \
+                printk("WARNING: at %s:%d %s()\n", __FILE__,            \
                         __LINE__, __FUNCTION__);                        \
                 dump_stack();                                           \
         }                                                               \
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index f3806a74c478..8307b1bb337a 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -9,6 +9,11 @@
 /* Align . to a 8 byte boundary equals to maximum function alignment. */
 #define ALIGN_FUNCTION()  . = ALIGN(8)
 
+/* .data section */
+#define DATA_DATA                                                       \
+        *(.data)                                                        \
+        *(.data.init.refok)
+
 #define RODATA                                                          \
         . = ALIGN(4096);                                                \
         .rodata           : AT(ADDR(.rodata) - LOAD_OFFSET) {           \
@@ -139,6 +144,13 @@
                 VMLINUX_SYMBOL(__security_initcall_end) = .;            \
         }
 
+/* .text section. Map to function alignment to avoid address changes
+ * during second ld run in second ld pass when generating System.map */
+#define TEXT_TEXT                                                       \
+                ALIGN_FUNCTION();                                       \
+                *(.text)                                                \
+                *(.text.init.refok)
+
 /* sched.text is aling to function alignment to secure we have same
  * address even at second ld pass when generating System.map */
 #define SCHED_TEXT                                                      \
diff --git a/include/asm-i386/atomic.h b/include/asm-i386/atomic.h
index 0baa2f89463c..437aac801711 100644
--- a/include/asm-i386/atomic.h
+++ b/include/asm-i386/atomic.h
@@ -182,7 +182,7 @@ static __inline__ int atomic_add_return(int i, atomic_t *v)
         int __i;
 #ifdef CONFIG_M386
         unsigned long flags;
-        if(unlikely(boot_cpu_data.x86==3))
+        if(unlikely(boot_cpu_data.x86 <= 3))
                 goto no_xadd;
 #endif
         /* Modern 486+ processor */
diff --git a/include/asm-i386/local.h b/include/asm-i386/local.h
index e13d3e98823f..6e85975b9ed2 100644
--- a/include/asm-i386/local.h
+++ b/include/asm-i386/local.h
@@ -135,7 +135,7 @@ static __inline__ long local_add_return(long i, local_t *l)
         long __i;
 #ifdef CONFIG_M386
         unsigned long flags;
-        if(unlikely(boot_cpu_data.x86==3))
+        if(unlikely(boot_cpu_data.x86 <= 3))
                 goto no_xadd;
 #endif
         /* Modern 486+ processor */
diff --git a/include/asm-i386/tlbflush.h b/include/asm-i386/tlbflush.h
index db7f77eacfa0..fc525c5cd5a9 100644
--- a/include/asm-i386/tlbflush.h
+++ b/include/asm-i386/tlbflush.h
@@ -90,6 +90,8 @@
 
 #ifndef CONFIG_SMP
 
+#include <linux/sched.h>
+
 #define flush_tlb() __flush_tlb()
 #define flush_tlb_all() __flush_tlb_all()
 #define local_flush_tlb() __flush_tlb()
diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h
index 5d03792d4f65..5b526357d178 100644
--- a/include/asm-ia64/acpi.h
+++ b/include/asm-ia64/acpi.h
@@ -30,6 +30,8 @@
 
 #ifdef __KERNEL__
 
+#include <acpi/pdc_intel.h>
+
 #include <linux/init.h>
 #include <linux/numa.h>
 #include <asm/system.h>
@@ -119,11 +121,6 @@ extern int __devinitdata pxm_to_nid_map[MAX_PXM_DOMAINS];
 extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
 #endif
 
-/*
- * Refer Intel ACPI _PDC support document for bit definitions
- */
-#define ACPI_PDC_EST_CAPABILITY_SMP     0x8
-
 #endif /*__KERNEL__*/
 
 #endif /*_ASM_ACPI_H*/
diff --git a/include/asm-ia64/kdebug.h b/include/asm-ia64/kdebug.h
index ba211e011a1d..320cd8e754ea 100644
--- a/include/asm-ia64/kdebug.h
+++ b/include/asm-ia64/kdebug.h
@@ -28,14 +28,24 @@
  */
 #include <linux/notifier.h>
 
-extern int register_page_fault_notifier(struct notifier_block *);
-extern int unregister_page_fault_notifier(struct notifier_block *);
+/*
+ * These are only here because kprobes.c wants them to implement a
+ * blatant layering violation.  Will hopefully go away soon once all
+ * architectures are updated.
+ */
+static inline int register_page_fault_notifier(struct notifier_block *nb)
+{
+        return 0;
+}
+static inline int unregister_page_fault_notifier(struct notifier_block *nb)
+{
+        return 0;
+}
 
 enum die_val {
         DIE_BREAK = 1,
         DIE_FAULT,
         DIE_OOPS,
-        DIE_PAGE_FAULT,
         DIE_MACHINE_HALT,
         DIE_MACHINE_RESTART,
         DIE_MCA_MONARCH_ENTER,
diff --git a/include/asm-ia64/kprobes.h b/include/asm-ia64/kprobes.h
index 2abc98b336f3..6382e52ec227 100644
--- a/include/asm-ia64/kprobes.h
+++ b/include/asm-ia64/kprobes.h
@@ -120,6 +120,7 @@ struct arch_specific_insn {
         unsigned short slot;
 };
 
+extern int kprobes_fault_handler(struct pt_regs *regs, int trapnr);
 extern int kprobe_exceptions_notify(struct notifier_block *self,
                                     unsigned long val, void *data);
 
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h
index f049bc40ca7d..441c9e001776 100644
--- a/include/asm-ia64/unistd.h
+++ b/include/asm-ia64/unistd.h
@@ -296,11 +296,27 @@
 #define __NR_getcpu                     1304
 #define __NR_epoll_pwait                1305
 #define __NR_utimensat                  1306
+#define __NR_signalfd                   1307
+#define __NR_timerfd                    1308
+#define __NR_eventfd                    1309
 
 #ifdef __KERNEL__
 
 
-#define NR_syscalls                     283 /* length of syscall table */
+#define NR_syscalls                     286 /* length of syscall table */
+
+/*
+ * The following defines stop scripts/checksyscalls.sh from complaining about
+ * unimplemented system calls.  Glibc provides for each of these by using
+ * more modern equivalent system calls.
+ */
+#define __IGNORE_fork           /* clone() */
+#define __IGNORE_time           /* gettimeofday() */
+#define __IGNORE_alarm          /* setitimer(ITIMER_REAL, ... */
+#define __IGNORE_pause          /* rt_sigprocmask(), rt_sigsuspend() */
+#define __IGNORE_utime          /* utimes() */
+#define __IGNORE_getpgrp        /* getpgid() */
+#define __IGNORE_vfork          /* clone() */
 
 #define __ARCH_WANT_SYS_RT_SIGACTION
 #define __ARCH_WANT_SYS_RT_SIGSUSPEND
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
index 5685d4fc7881..9fb57c035213 100644
--- a/include/asm-mips/pgalloc.h
+++ b/include/asm-mips/pgalloc.h
@@ -11,6 +11,7 @@
 
 #include <linux/highmem.h>
 #include <linux/mm.h>
+#include <linux/sched.h>
 
 static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
         pte_t *pte)
diff --git a/include/asm-parisc/mmu_context.h b/include/asm-parisc/mmu_context.h
index bad690298f0c..85856c74ad1d 100644
--- a/include/asm-parisc/mmu_context.h
+++ b/include/asm-parisc/mmu_context.h
@@ -2,6 +2,7 @@
 #define __PARISC_MMU_CONTEXT_H
 
 #include <linux/mm.h>
+#include <linux/sched.h>
 #include <asm/atomic.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
diff --git a/include/asm-parisc/tlbflush.h b/include/asm-parisc/tlbflush.h
index 3313da9ea00f..270cf309772b 100644
--- a/include/asm-parisc/tlbflush.h
+++ b/include/asm-parisc/tlbflush.h
@@ -4,6 +4,7 @@
 /* TLB flushing routines.... */
 
 #include <linux/mm.h>
+#include <linux/sched.h>
 #include <asm/mmu_context.h>
 
 
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 434524931ef3..82d595a52109 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -302,6 +302,12 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
+#define CPU_FTRS_7448   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
+            CPU_FTR_USE_TB | \
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+            CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
+            CPU_FTR_PPC_LE)
 #define CPU_FTRS_82XX   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 #define CPU_FTRS_G2_LE  (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
diff --git a/include/asm-powerpc/mmu-44x.h b/include/asm-powerpc/mmu-44x.h
index d5ce7a8dfe9f..62772ae839ca 100644
--- a/include/asm-powerpc/mmu-44x.h
+++ b/include/asm-powerpc/mmu-44x.h
@@ -55,8 +55,6 @@
 
 typedef unsigned long long phys_addr_t;
 
-extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
-
 typedef struct {
         unsigned long id;
         unsigned long vdso_base;
diff --git a/include/asm-powerpc/mmu_context.h b/include/asm-powerpc/mmu_context.h
index c0d7795e3d25..40c9e5a13ff1 100644
--- a/include/asm-powerpc/mmu_context.h
+++ b/include/asm-powerpc/mmu_context.h
@@ -8,6 +8,7 @@
 
 #include <linux/kernel.h>       
 #include <linux/mm.h>   
+#include <linux/sched.h>
 #include <asm/mmu.h>    
 #include <asm/cputable.h>
 #include <asm-generic/mm_hooks.h>
diff --git a/include/asm-powerpc/mpc8260.h b/include/asm-powerpc/mpc8260.h
index f1b83b09ab2e..e0d480790e12 100644
--- a/include/asm-powerpc/mpc8260.h
+++ b/include/asm-powerpc/mpc8260.h
@@ -5,8 +5,8 @@
  * this one and the configuration switching is done here.
  */
 #ifdef __KERNEL__
-#ifndef __ASM_PPC_MPC8260_H__
-#define __ASM_PPC_MPC8260_H__
+#ifndef __ASM_POWERPC_MPC8260_H__
+#define __ASM_POWERPC_MPC8260_H__
 
 
 #ifdef CONFIG_8260
@@ -20,5 +20,5 @@
 #endif
 
 #endif /* CONFIG_8260 */
-#endif /* !__ASM_PPC_MPC8260_H__ */
+#endif /* !__ASM_POWERPC_MPC8260_H__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 09662a24f226..c863bdb2889c 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -782,23 +782,8 @@ extern void kernel_set_cachemode (unsigned long address, unsigned long size,
 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 #define kern_addr_valid(addr)   (1)
 
-#ifdef CONFIG_PHYS_64BIT
-extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
-                        unsigned long paddr, unsigned long size, pgprot_t prot);
-
-static inline int io_remap_pfn_range(struct vm_area_struct *vma,
-                                        unsigned long vaddr,
-                                        unsigned long pfn,
-                                        unsigned long size,
-                                        pgprot_t prot)
-{
-        phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
-        return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
-}
-#else
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
-#endif
 
 /*
  * No page table caches to initialise
diff --git a/include/asm-powerpc/pmac_feature.h b/include/asm-powerpc/pmac_feature.h
index d43d91beba9b..26bcb0aa164a 100644
--- a/include/asm-powerpc/pmac_feature.h
+++ b/include/asm-powerpc/pmac_feature.h
@@ -28,8 +28,8 @@
  */
 
 #ifdef __KERNEL__
-#ifndef __PPC_ASM_PMAC_FEATURE_H
-#define __PPC_ASM_PMAC_FEATURE_H
+#ifndef __ASM_POWERPC_PMAC_FEATURE_H
+#define __ASM_POWERPC_PMAC_FEATURE_H
 
 #include <asm/macio.h>
 #include <asm/machdep.h>
@@ -393,5 +393,5 @@ extern u32 __iomem *uninorth_base;
 #define UN_BIC(r,v)     (UN_OUT((r), UN_IN(r) & ~(v)))
 
 
-#endif /* __PPC_ASM_PMAC_FEATURE_H */
+#endif /* __ASM_POWERPC_PMAC_FEATURE_H */
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/systbl.h b/include/asm-powerpc/systbl.h
index 3d44446fb74f..700ca5928741 100644
--- a/include/asm-powerpc/systbl.h
+++ b/include/asm-powerpc/systbl.h
@@ -308,3 +308,6 @@ COMPAT_SYS_SPU(move_pages)
 SYSCALL_SPU(getcpu)
 COMPAT_SYS(epoll_pwait)
 COMPAT_SYS_SPU(utimensat)
+COMPAT_SYS_SPU(signalfd)
+COMPAT_SYS_SPU(timerfd)
+SYSCALL_SPU(eventfd)
diff --git a/include/asm-powerpc/tsi108_irq.h b/include/asm-powerpc/tsi108_irq.h
index 3e4d04effa57..6ed93979fbe4 100644
--- a/include/asm-powerpc/tsi108_irq.h
+++ b/include/asm-powerpc/tsi108_irq.h
@@ -26,8 +26,8 @@
  * demultiplexing on TSI108EMU/SVB boards.
  */
 
-#ifndef _ASM_PPC_TSI108_IRQ_H
-#define _ASM_PPC_TSI108_IRQ_H
+#ifndef _ASM_POWERPC_TSI108_IRQ_H
+#define _ASM_POWERPC_TSI108_IRQ_H
 
 /*
  * Tsi108 interrupts
@@ -121,4 +121,4 @@ typedef enum {
         TSI108_IRQ_DIRECTED,
         TSI108_IRQ_DISTRIBUTED,
 } TSI108_IRQ_MODE;
-#endif                          /*  _ASM_PPC_TSI108_IRQ_H */
+#endif                          /*  _ASM_POWERPC_TSI108_IRQ_H */
diff --git a/include/asm-powerpc/tsi108_pci.h b/include/asm-powerpc/tsi108_pci.h
index a9f92f73232c..5653d7cc3e24 100644
--- a/include/asm-powerpc/tsi108_pci.h
+++ b/include/asm-powerpc/tsi108_pci.h
@@ -18,8 +18,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _ASM_PPC_TSI108_PCI_H
-#define _ASM_PPC_TSI108_PCI_H
+#ifndef _ASM_POWERPC_TSI108_PCI_H
+#define _ASM_POWERPC_TSI108_PCI_H
 
 #include <asm/tsi108.h>
 
@@ -42,4 +42,4 @@ extern void tsi108_pci_int_init(struct device_node *node);
 extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
 extern void tsi108_clear_pci_cfg_error(void);
 
-#endif                          /*  _ASM_PPC_TSI108_PCI_H */
+#endif                          /*  _ASM_POWERPC_TSI108_PCI_H */
diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h
index 21f004aef508..e3c28dc31abf 100644
--- a/include/asm-powerpc/unistd.h
+++ b/include/asm-powerpc/unistd.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_PPC_UNISTD_H_
-#define _ASM_PPC_UNISTD_H_
+#ifndef _ASM_POWERPC_UNISTD_H_
+#define _ASM_POWERPC_UNISTD_H_
 
 /*
  * This file contains the system call numbers.
@@ -327,10 +327,13 @@
 #define __NR_getcpu             302
 #define __NR_epoll_pwait        303
 #define __NR_utimensat          304
+#define __NR_signalfd           305
+#define __NR_timerfd            306
+#define __NR_eventfd            307
 
 #ifdef __KERNEL__
 
-#define __NR_syscalls           305
+#define __NR_syscalls           308
 
 #define __NR__exit __NR_exit
 #define NR_syscalls     __NR_syscalls
@@ -381,4 +384,4 @@
 #endif          /* __ASSEMBLY__ */
 #endif          /* __KERNEL__ */
 
-#endif /* _ASM_PPC_UNISTD_H_ */
+#endif /* _ASM_POWERPC_UNISTD_H_ */
diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h
index 5c6f00d62df8..790c1c557417 100644
--- a/include/asm-s390/unistd.h
+++ b/include/asm-s390/unistd.h
@@ -251,8 +251,12 @@
 #define __NR_getcpu             311
 #define __NR_epoll_pwait        312
 #define __NR_utimes             313
-
-#define NR_syscalls 314
+/* Number 314 is reserved for new sys_fallocate */
+#define __NR_utimensat          315
+#define __NR_signalfd           316
+#define __NR_timerfd            317
+#define __NR_eventfd            318
+#define NR_syscalls 319
 
 /* 
  * There are some system calls that are not present on 64 bit, some
@@ -346,6 +350,19 @@
 
 #ifdef __KERNEL__
 
+#ifndef CONFIG_64BIT
+#define __IGNORE_select
+#else
+#define __IGNORE_time
+#endif
+
+/* Ignore NUMA system calls. Not wired up on s390. */
+#define __IGNORE_mbind
+#define __IGNORE_get_mempolicy
+#define __IGNORE_set_mempolicy
+#define __IGNORE_migrate_pages
+#define __IGNORE_move_pages
+
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_SYS_ALARM
diff --git a/include/asm-sh/dreamcast/sysasic.h b/include/asm-sh/dreamcast/sysasic.h
index 7874e3dac736..f33426608a87 100644
--- a/include/asm-sh/dreamcast/sysasic.h
+++ b/include/asm-sh/dreamcast/sysasic.h
@@ -23,7 +23,7 @@
    takes.
 */
 
-#define HW_EVENT_IRQ_BASE  OFFCHIP_IRQ_BASE /* 48 */
+#define HW_EVENT_IRQ_BASE  48
 
 /* IRQ 13 */
 #define HW_EVENT_VSYNC     (HW_EVENT_IRQ_BASE +  5) /* VSync */
diff --git a/include/asm-sh/kdebug.h b/include/asm-sh/kdebug.h
index 16578b7c9da1..382cfc7deb73 100644
--- a/include/asm-sh/kdebug.h
+++ b/include/asm-sh/kdebug.h
@@ -6,10 +6,6 @@
 /* Grossly misnamed. */
 enum die_val {
         DIE_TRAP,
-        DIE_PAGE_FAULT,
 };
 
-int register_page_fault_notifier(struct notifier_block *nb);
-int unregister_page_fault_notifier(struct notifier_block *nb);
-
 #endif /* __ASM_SH_KDEBUG_H */
diff --git a/include/asm-sh/landisk/gio.h b/include/asm-sh/landisk/gio.h
index 3fce4c451a46..35d7368b718a 100644
--- a/include/asm-sh/landisk/gio.h
+++ b/include/asm-sh/landisk/gio.h
@@ -29,16 +29,8 @@
 #define GIODRV_IOCGGIODATA4   _IOR(GIODRV_IOC_MAGIC,  6, unsigned long *)
 #define GIODRV_IOCSGIOSETADDR _IOW(GIODRV_IOC_MAGIC,  7, unsigned long *)
 #define GIODRV_IOCHARDRESET   _IO(GIODRV_IOC_MAGIC, 8) /* debugging tool */
-
-#define GIODRV_IOCSGIO_LED    _IOW(GIODRV_IOC_MAGIC,  9, unsigned long *)
-#define GIODRV_IOCGGIO_LED    _IOR(GIODRV_IOC_MAGIC,  10, unsigned long *)
-#define GIODRV_IOCSGIO_BUZZER _IOW(GIODRV_IOC_MAGIC,  11, unsigned long *)
-#define GIODRV_IOCGGIO_LANDISK _IOR(GIODRV_IOC_MAGIC,  14, unsigned long *)
-#define GIODRV_IOCGGIO_BTN _IOR(GIODRV_IOC_MAGIC,  22, unsigned long *)
-#define GIODRV_IOCSGIO_BTNPID _IOW(GIODRV_IOC_MAGIC,  23, unsigned long *)
-#define GIODRV_IOCGGIO_BTNPID _IOR(GIODRV_IOC_MAGIC,  24, unsigned long *)
-
 #define GIODRV_IOC_MAXNR 8
+
 #define GIO_READ 0x00000000
 #define GIO_WRITE 0x00000001
 
diff --git a/include/asm-sh/landisk/iodata_landisk.h b/include/asm-sh/landisk/iodata_landisk.h
index c74d3c73f377..6fb04ab38b9f 100644
--- a/include/asm-sh/landisk/iodata_landisk.h
+++ b/include/asm-sh/landisk/iodata_landisk.h
@@ -22,16 +22,6 @@
 /* 2003.10.31 I-O DATA NSD NWG  add.    for shutdown port clear */
 #define PA_PWRINT_CLR   0xb0000006      /* Shutdown Interrupt clear Register */
 
-#define PA_LCD_CLRDSP   0x00            /* LCD Clear Display Offset */
-#define PA_LCD_RTNHOME  0x00            /* LCD Return Home Offset */
-#define PA_LCD_ENTMODE  0x00            /* LCD Entry Mode Offset */
-#define PA_LCD_DSPCTL   0x00            /* LCD Display ON/OFF Control Offset */
-#define PA_LCD_FUNC     0x00            /* LCD Function Set Offset */
-#define PA_LCD_CGRAM    0x00            /* LCD Set CGRAM Address Offset */
-#define PA_LCD_DDRAM    0x00            /* LCD Set DDRAM Address Offset */
-#define PA_LCD_RDFLAG   0x01            /* LCD Read Busy Flag Offset */
-#define PA_LCD_WTDATA   0x02            /* LCD Write Datat to RAM Offset */
-#define PA_LCD_RDDATA   0x03            /* LCD Read Data from RAM Offset */
 #define PA_PIDE_OFFSET  0x40            /* CF IDE Offset */
 #define PA_SIDE_OFFSET  0x40            /* HDD IDE Offset */
 
@@ -45,33 +35,6 @@
 #define IRQ_BUTTON      12              /* USL-5P Button IRQ */
 #define IRQ_FAULT       13              /* USL-5P Fault  IRQ */
 
-#define SHUTDOWN_BTN_MAJOR      99      /* Shutdown button device major no. */
-
-#define SHUTDOWN_LOOP_CNT       5       /* Shutdown button Detection loop */
-#define SHUTDOWN_DELAY          200     /* Shutdown button delay value(ms) */
-
-
-/* added by kogiidena */
-/*
- *  landisk_ledparam
- *
- * led  ------10 -6543210 -6543210 -6543210
- *     |000000..|0.......|0.......|U.......|
- *     |  HARD  |fastblik| blink  |   on   |
- *
- *   led0: power       U:update flag
- *   led1: error
- *   led2: usb1
- *   led3: usb2
- *   led4: usb3
- *   led5: usb4
- *   led6: usb5
- *
- */
-extern int landisk_ledparam;    /* from setup.c */
-extern int landisk_buzzerparam; /* from setup.c */
-extern int landisk_arch;        /* from setup.c */
-
 #define __IO_PREFIX landisk
 #include <asm/io_generic.h>
 
diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h
index af71e379a5ee..77bcb09d6ac8 100644
--- a/include/asm-sh/unistd.h
+++ b/include/asm-sh/unistd.h
@@ -329,8 +329,11 @@
 #define __NR_getcpu             318
 #define __NR_epoll_pwait        319
 #define __NR_utimensat          320
+#define __NR_signalfd           321
+#define __NR_timerfd            322
+#define __NR_eventfd            323
 
-#define NR_syscalls 321
+#define NR_syscalls 324
 
 #ifdef __KERNEL__
 
diff --git a/include/asm-sparc/atomic.h b/include/asm-sparc/atomic.h
index 731fa56e0c37..bdca5416d8b0 100644
--- a/include/asm-sparc/atomic.h
+++ b/include/asm-sparc/atomic.h
@@ -2,6 +2,7 @@
  *
  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  * Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)
+ * Copyright (C) 2007 Kyle McMartin (kyle@parisc-linux.org)
  *
  * Additions by Keith M Wesolowski (wesolows@foobazco.org) based
  * on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>.
@@ -10,11 +11,48 @@
 #ifndef __ARCH_SPARC_ATOMIC__
 #define __ARCH_SPARC_ATOMIC__
 
+#include <linux/types.h>
 
 typedef struct { volatile int counter; } atomic_t;
 
 #ifdef __KERNEL__
 
+/* Emulate cmpxchg() the same way we emulate atomics,
+ * by hashing the object address and indexing into an array
+ * of spinlocks to get a bit of performance...
+ *
+ * See arch/sparc/lib/atomic32.c for implementation.
+ *
+ * Cribbed from <asm-parisc/atomic.h>
+ */
+#define __HAVE_ARCH_CMPXCHG     1
+
+/* bug catcher for when unsupported size is used - won't link */
+extern void __cmpxchg_called_with_bad_pointer(void);
+/* we only need to support cmpxchg of a u32 on sparc */
+extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
+
+/* don't worry...optimizer will get rid of most of this */
+static __inline__ unsigned long
+__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
+{
+        switch(size) {
+        case 4:
+                return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
+        default:
+                __cmpxchg_called_with_bad_pointer();
+                break;
+        }
+        return old;
+}
+
+#define cmpxchg(ptr,o,n) ({                                             \
+        __typeof__(*(ptr)) _o_ = (o);                                   \
+        __typeof__(*(ptr)) _n_ = (n);                                   \
+        (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,       \
+                        (unsigned long)_n_, sizeof(*(ptr)));            \
+})
+
 #define ATOMIC_INIT(i)  { (i) }
 
 extern int __atomic_add_return(int, atomic_t *);
diff --git a/include/asm-sparc64/bugs.h b/include/asm-sparc64/bugs.h
index 120422fdb02f..bf39d86c0c9e 100644
--- a/include/asm-sparc64/bugs.h
+++ b/include/asm-sparc64/bugs.h
@@ -1,9 +1,8 @@
-/*  $Id: bugs.h,v 1.1 1996/12/26 13:25:20 davem Exp $
- *  include/asm-sparc64/bugs.h:  Sparc probes for various bugs.
+/* bugs.h: Sparc64 probes for various bugs.
  *
- *  Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
  */
-
+#include <asm/sstate.h>
 
 extern unsigned long loops_per_jiffy;
 
@@ -12,4 +11,5 @@ static void __init check_bugs(void)
 #ifndef CONFIG_SMP
         cpu_data(0).udelay_val = loops_per_jiffy;
 #endif
+        sstate_running();
 }
diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h
index e89922d6718c..03c385de7619 100644
--- a/include/asm-sparc64/cpudata.h
+++ b/include/asm-sparc64/cpudata.h
@@ -17,11 +17,11 @@
 typedef struct {
         /* Dcache line 1 */
         unsigned int    __softirq_pending; /* must be 1st, see rtrap.S */
-        unsigned int    __pad0_1;
-        unsigned int    __pad0_2;
-        unsigned int    __pad1;
+        unsigned int    __pad0;
         unsigned long   clock_tick;     /* %tick's per second */
         unsigned long   udelay_val;
+        unsigned int    __pad1;
+        unsigned int    __pad2;
 
         /* Dcache line 2, rarely used */
         unsigned int    dcache_size;
@@ -30,8 +30,8 @@ typedef struct {
         unsigned int    icache_line_size;
         unsigned int    ecache_size;
         unsigned int    ecache_line_size;
+        int             core_id;
         unsigned int    __pad3;
-        unsigned int    __pad4;
 } cpuinfo_sparc;
 
 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
@@ -76,12 +76,18 @@ struct trap_per_cpu {
 
 /* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
         unsigned int            irq_worklist;
-        unsigned int            __pad1;
-        unsigned long           __pad2[3];
+        unsigned int            cpu_mondo_qmask;
+        unsigned int            dev_mondo_qmask;
+        unsigned int            resum_qmask;
+        unsigned int            nonresum_qmask;
+        unsigned int            __pad2[3];
 } __attribute__((aligned(64)));
 extern struct trap_per_cpu trap_block[NR_CPUS];
 extern void init_cur_cpu_trap(struct thread_info *);
 extern void setup_tba(void);
+extern int ncpus_probed;
+
+extern unsigned long real_hard_smp_processor_id(void);
 
 struct cpuid_patch_entry {
         unsigned int    addr;
@@ -122,6 +128,10 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
 #define TRAP_PER_CPU_TSB_HUGE           0xd0
 #define TRAP_PER_CPU_TSB_HUGE_TEMP      0xd8
 #define TRAP_PER_CPU_IRQ_WORKLIST       0xe0
+#define TRAP_PER_CPU_CPU_MONDO_QMASK    0xe4
+#define TRAP_PER_CPU_DEV_MONDO_QMASK    0xe8
+#define TRAP_PER_CPU_RESUM_QMASK        0xec
+#define TRAP_PER_CPU_NONRESUM_QMASK     0xf0
 
 #define TRAP_BLOCK_SZ_SHIFT             8
 
@@ -192,7 +202,7 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
  * the calculations done by the macro mid-stream.
  */
 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)  \
-        ldub    [THR + TI_CPU], REG1;                   \
+        lduh    [THR + TI_CPU], REG1;                   \
         sethi   %hi(__per_cpu_shift), REG3;             \
         sethi   %hi(__per_cpu_base), REG2;              \
         ldx     [REG3 + %lo(__per_cpu_shift)], REG3;    \
diff --git a/include/asm-sparc64/hypervisor.h b/include/asm-sparc64/hypervisor.h
index 612bf319753f..5cdb1ff04838 100644
--- a/include/asm-sparc64/hypervisor.h
+++ b/include/asm-sparc64/hypervisor.h
@@ -73,6 +73,8 @@
 #define HV_ENOTSUPPORTED                13 /* Function not supported       */
 #define HV_ENOMAP                       14 /* No mapping found             */
 #define HV_ETOOMANY                     15 /* Too many items specified     */
+#define HV_ECHANNEL                     16 /* Invalid LDC channel          */
+#define HV_EBUSY                        17 /* Resource busy                */
 
 /* mach_exit()
  * TRAP:        HV_FAST_TRAP
@@ -95,6 +97,10 @@
  */
 #define HV_FAST_MACH_EXIT               0x00
 
+#ifndef __ASSEMBLY__
+extern void sun4v_mach_exit(unsigned long exit_core);
+#endif
+
 /* Domain services.  */
 
 /* mach_desc()
@@ -120,7 +126,13 @@
  */
 #define HV_FAST_MACH_DESC               0x01
 
-/* mach_exit()
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mach_desc(unsigned long buffer_pa,
+                                     unsigned long buf_len,
+                                     unsigned long *real_buf_len);
+#endif
+
+/* mach_sir()
  * TRAP:        HV_FAST_TRAP
  * FUNCTION:    HV_FAST_MACH_SIR
  * ERRORS:      This service does not return.
@@ -135,53 +147,66 @@
  */
 #define HV_FAST_MACH_SIR                0x02
 
-/* mach_set_soft_state()
+#ifndef __ASSEMBLY__
+extern void sun4v_mach_sir(void);
+#endif
+
+/* mach_set_watchdog()
  * TRAP:        HV_FAST_TRAP
- * FUNCTION:    HV_FAST_MACH_SET_SOFT_STATE
- * ARG0:        software state
- * ARG1:        software state description pointer
+ * FUNCTION:    HV_FAST_MACH_SET_WATCHDOG
+ * ARG0:        timeout in milliseconds
  * RET0:        status
- * ERRORS:      EINVAL          software state not valid or software state
- *                              description is not NULL terminated
- *              ENORADDR        software state description pointer is not a
- *                              valid real address
- *              EBADALIGNED     software state description is not correctly
- *                              aligned
+ * RET1:        time remaining in milliseconds
  *
- * This allows the guest to report it's soft state to the hypervisor.  There
- * are two primary components to this state.  The first part states whether
- * the guest software is running or not.  The second containts optional
- * details specific to the software.
+ * A guest uses this API to set a watchdog timer.  Once the gues has set
+ * the timer, it must call the timer service again either to disable or
+ * postpone the expiration.  If the timer expires before being reset or
+ * disabled, then the hypervisor take a platform specific action leading
+ * to guest termination within a bounded time period.  The platform action
+ * may include recovery actions such as reporting the expiration to a
+ * Service Processor, and/or automatically restarting the gues.
  *
- * The software state argument is defined below in HV_SOFT_STATE_*, and
- * indicates whether the guest is operating normally or in a transitional
- * state.
+ * The 'timeout' parameter is specified in milliseconds, however the
+ * implementated granularity is given by the 'watchdog-resolution'
+ * property in the 'platform' node of the guest's machine description.
+ * The largest allowed timeout value is specified by the
+ * 'watchdog-max-timeout' property of the 'platform' node.
  *
- * The software state description argument is a real address of a data buffer
- * of size 32-bytes aligned on a 32-byte boundary.  It is treated as a NULL
- * terminated 7-bit ASCII string of up to 31 characters not including the
- * NULL termination.
- */
-#define HV_FAST_MACH_SET_SOFT_STATE     0x03
-#define  HV_SOFT_STATE_NORMAL            0x01
-#define  HV_SOFT_STATE_TRANSITION        0x02
-
-/* mach_get_soft_state()
- * TRAP:        HV_FAST_TRAP
- * FUNCTION:    HV_FAST_MACH_GET_SOFT_STATE
- * ARG0:        software state description pointer
- * RET0:        status
- * RET1:        software state
- * ERRORS:      ENORADDR        software state description pointer is not a
- *                              valid real address
- *              EBADALIGNED     software state description is not correctly
- *                              aligned
+ * If the 'timeout' argument is not zero, the watchdog timer is set to
+ * expire after a minimum of 'timeout' milliseconds.
  *
- * Retrieve the current value of the guest's software state.  The rules
- * for the software state pointer are the same as for mach_set_soft_state()
- * above.
+ * If the 'timeout' argument is zero, the watchdog timer is disabled.
+ *
+ * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
+ * property, the hypervisor leaves the watchdog timer state unchanged,
+ * and returns a status of EINVAL.
+ *
+ * The 'time remaining' return value is valid regardless of whether the
+ * return status is EOK or EINVAL.  A non-zero return value indicates the
+ * number of milliseconds that were remaining until the timer was to expire.
+ * If less than one millisecond remains, the return value is '1'.  If the
+ * watchdog timer was disabled at the time of the call, the return value is
+ * zero.
+ *
+ * If the hypervisor cannot support the exact timeout value requested, but
+ * can support a larger timeout value, the hypervisor may round the actual
+ * timeout to a value larger than the requested timeout, consequently the
+ * 'time remaining' return value may be larger than the previously requested
+ * timeout value.
+ *
+ * Any guest OS debugger should be aware that the watchdog service may be in
+ * use.  Consequently, it is recommended that the watchdog service is
+ * disabled upon debugger entry (e.g. reaching a breakpoint), and then
+ * re-enabled upon returning to normal execution.  The API has been designed
+ * with this in mind, and the 'time remaining' result of the disable call may
+ * be used directly as the timeout argument of the re-enable call.
  */
-#define HV_FAST_MACH_GET_SOFT_STATE     0x04
+#define HV_FAST_MACH_SET_WATCHDOG       0x05
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
+                                             unsigned long *orig_timeout);
+#endif
 
 /* CPU services.
  *
@@ -206,8 +231,8 @@
  * FUNCTION:    HV_FAST_CPU_START
  * ARG0:        CPU ID
  * ARG1:        PC
- * ARG1:        RTBA
- * ARG1:        target ARG0
+ * ARG2:        RTBA
+ * ARG3:        target ARG0
  * RET0:        status
  * ERRORS:      ENOCPU          Invalid CPU ID
  *              EINVAL          Target CPU ID is not in the stopped state
@@ -224,6 +249,13 @@
  */
 #define HV_FAST_CPU_START               0x10
 
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_start(unsigned long cpuid,
+                                     unsigned long pc,
+                                     unsigned long rtba,
+                                     unsigned long arg0);
+#endif
+
 /* cpu_stop()
  * TRAP:        HV_FAST_TRAP
  * FUNCTION:    HV_FAST_CPU_STOP
@@ -245,6 +277,10 @@
  */
 #define HV_FAST_CPU_STOP                0x11
 
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_cpu_stop(unsigned long cpuid);
+#endif
+
 /* cpu_yield()
  * TRAP:        HV_FAST_TRAP
  * FUNCTION:    HV_FAST_CPU_YIELD
@@ -588,6 +624,11 @@ struct hv_fault_status {
  */
 #define HV_FAST_MMU_TSB_CTX0            0x20
 
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
+                                        unsigned long tsb_desc_ra);
+#endif
+
 /* mmu_tsb_ctxnon0()
  * TRAP:        HV_FAST_TRAP
  * FUNCTION:    HV_FAST_MMU_TSB_CTXNON0
@@ -694,6 +735,13 @@ struct hv_fault_status {
  */
 #define HV_FAST_MMU_MAP_PERM_ADDR       0x25
 
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
+                                             unsigned long set_to_zero,
+                                             unsigned long tte,
+                                             unsigned long flags);
+#endif
+
 /* mmu_fault_area_conf()
  * TRAP:        HV_FAST_TRAP
  * FUNCTION:    HV_FAST_MMU_FAULT_AREA_CONF
@@ -892,6 +940,10 @@ struct hv_fault_status {
  */
 #define HV_FAST_TOD_GET                 0x50
 
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_tod_get(unsigned long *time);
+#endif
+
 /* tod_set()
  * TRAP:        HV_FAST_TRAP
  * FUNCTION:    HV_FAST_TOD_SET
@@ -905,6 +957,10 @@ struct hv_fault_status {
  */
 #define HV_FAST_TOD_SET                 0x51
 
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_tod_set(unsigned long time);
+#endif
+
 /* Console services */
 
 /* con_getchar()
@@ -940,6 +996,107 @@ struct hv_fault_status {
  */
 #define HV_FAST_CONS_PUTCHAR            0x61
 
+/* con_read()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CONS_READ
+ * ARG0:        buffer real address
+ * ARG1:        buffer size in bytes
+ * RET0:        status
+ * RET1:        bytes read or BREAK or HUP
+ * ERRORS:      EWOULDBLOCK     No character available.
+ *
+ * Reads characters into a buffer from the console device.  If no
+ * character is available then an EWOULDBLOCK error is returned.
+ * If a character is available, then the returned status is EOK
+ * and the number of bytes read into the given buffer is provided
+ * in RET1.
+ *
+ * A virtual BREAK is represented by the 64-bit RET1 value -1.
+ *
+ * A virtual HUP signal is represented by the 64-bit RET1 value -2.
+ *
+ * If BREAK or HUP are indicated, no bytes were read into buffer.
+ */
+#define HV_FAST_CONS_READ               0x62
+
+/* con_write()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_CONS_WRITE
+ * ARG0:        buffer real address
+ * ARG1:        buffer size in bytes
+ * RET0:        status
+ * RET1:        bytes written
+ * ERRORS:      EWOULDBLOCK     Output buffer currently full, would block
+ *
+ * Send a characters in buffer to the console device.  Breaks must be
+ * sent using con_putchar().
+ */
+#define HV_FAST_CONS_WRITE              0x63
+
+#ifndef __ASSEMBLY__
+extern long sun4v_con_getchar(long *status);
+extern long sun4v_con_putchar(long c);
+extern long sun4v_con_read(unsigned long buffer,
+                           unsigned long size,
+                           unsigned long *bytes_read);
+extern unsigned long sun4v_con_write(unsigned long buffer,
+                                     unsigned long size,
+                                     unsigned long *bytes_written);
+#endif
+
+/* mach_set_soft_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MACH_SET_SOFT_STATE
+ * ARG0:        software state
+ * ARG1:        software state description pointer
+ * RET0:        status
+ * ERRORS:      EINVAL          software state not valid or software state
+ *                              description is not NULL terminated
+ *              ENORADDR        software state description pointer is not a
+ *                              valid real address
+ *              EBADALIGNED     software state description is not correctly
+ *                              aligned
+ *
+ * This allows the guest to report it's soft state to the hypervisor.  There
+ * are two primary components to this state.  The first part states whether
+ * the guest software is running or not.  The second containts optional
+ * details specific to the software.
+ *
+ * The software state argument is defined below in HV_SOFT_STATE_*, and
+ * indicates whether the guest is operating normally or in a transitional
+ * state.
+ *
+ * The software state description argument is a real address of a data buffer
+ * of size 32-bytes aligned on a 32-byte boundary.  It is treated as a NULL
+ * terminated 7-bit ASCII string of up to 31 characters not including the
+ * NULL termination.
+ */
+#define HV_FAST_MACH_SET_SOFT_STATE     0x70
+#define  HV_SOFT_STATE_NORMAL            0x01
+#define  HV_SOFT_STATE_TRANSITION        0x02
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
+                                               unsigned long msg_string_ra);
+#endif
+
+/* mach_get_soft_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_MACH_GET_SOFT_STATE
+ * ARG0:        software state description pointer
+ * RET0:        status
+ * RET1:        software state
+ * ERRORS:      ENORADDR        software state description pointer is not a
+ *                              valid real address
+ *              EBADALIGNED     software state description is not correctly
+ *                              aligned
+ *
+ * Retrieve the current value of the guest's software state.  The rules
+ * for the software state pointer are the same as for mach_set_soft_state()
+ * above.
+ */
+#define HV_FAST_MACH_GET_SOFT_STATE     0x71
+
 /* Trap trace services.
  *
  * The hypervisor provides a trap tracing capability for privileged
@@ -1331,6 +1488,113 @@ extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
 extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
 #endif
 
+/* vintr_get_cookie()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_GET_COOKIE
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * RET0:        status
+ * RET1:        cookie
+ */
+#define HV_FAST_VINTR_GET_COOKIE        0xa7
+
+/* vintr_set_cookie()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_SET_COOKIE
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * ARG2:        cookie
+ * RET0:        status
+ */
+#define HV_FAST_VINTR_SET_COOKIE        0xa8
+
+/* vintr_get_valid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_GET_VALID
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * RET0:        status
+ * RET1:        valid state
+ */
+#define HV_FAST_VINTR_GET_VALID         0xa9
+
+/* vintr_set_valid()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_SET_VALID
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * ARG2:        valid state
+ * RET0:        status
+ */
+#define HV_FAST_VINTR_SET_VALID         0xaa
+
+/* vintr_get_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_GET_STATE
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * RET0:        status
+ * RET1:        state
+ */
+#define HV_FAST_VINTR_GET_STATE         0xab
+
+/* vintr_set_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_SET_STATE
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * ARG2:        state
+ * RET0:        status
+ */
+#define HV_FAST_VINTR_SET_STATE         0xac
+
+/* vintr_get_target()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_GET_TARGET
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * RET0:        status
+ * RET1:        cpuid
+ */
+#define HV_FAST_VINTR_GET_TARGET        0xad
+
+/* vintr_set_target()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_VINTR_SET_TARGET
+ * ARG0:        device handle
+ * ARG1:        device ino
+ * ARG2:        cpuid
+ * RET0:        status
+ */
+#define HV_FAST_VINTR_SET_TARGET        0xae
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
+                                            unsigned long dev_ino,
+                                            unsigned long *cookie);
+extern unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
+                                            unsigned long dev_ino,
+                                            unsigned long cookie);
+extern unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
+                                           unsigned long dev_ino,
+                                           unsigned long *valid);
+extern unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
+                                           unsigned long dev_ino,
+                                           unsigned long valid);
+extern unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
+                                           unsigned long dev_ino,
+                                           unsigned long *state);
+extern unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
+                                           unsigned long dev_ino,
+                                           unsigned long state);
+extern unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
+                                            unsigned long dev_ino,
+                                            unsigned long *cpuid);
+extern unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
+                                            unsigned long dev_ino,
+                                            unsigned long cpuid);
+#endif
+
 /* PCI IO services.
  *
  * See the terminology descriptions in the device interrupt services
@@ -1989,6 +2253,346 @@ extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cp
  */
 #define HV_FAST_PCI_MSG_SETVALID        0xd3
 
+/* Logical Domain Channel services.  */
+
+#define LDC_CHANNEL_DOWN                0
+#define LDC_CHANNEL_UP                  1
+#define LDC_CHANNEL_RESETTING           2
+
+/* ldc_tx_qconf()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_TX_QCONF
+ * ARG0:        channel ID
+ * ARG1:        real address base of queue
+ * ARG2:        num entries in queue
+ * RET0:        status
+ *
+ * Configure transmit queue for the LDC endpoint specified by the
+ * given channel ID, to be placed at the given real address, and
+ * be of the given num entries.  Num entries must be a power of two.
+ * The real address base of the queue must be aligned on the queue
+ * size.  Each queue entry is 64-bytes, so for example, a 32 entry
+ * queue must be aligned on a 2048 byte real address boundary.
+ *
+ * Upon configuration of a valid transmit queue the head and tail
+ * pointers are set to a hypervisor specific identical value indicating
+ * that the queue initially is empty.
+ *
+ * The endpoint's transmit queue is un-configured if num entries is zero.
+ *
+ * The maximum number of entries for each queue for a specific cpu may be
+ * determined from the machine description.  A transmit queue may be
+ * specified even in the event that the LDC is down (peer endpoint has no
+ * receive queue specified).  Transmission will begin as soon as the peer
+ * endpoint defines a receive queue.
+ *
+ * It is recommended that a guest wait for a transmit queue to empty prior
+ * to reconfiguring it, or un-configuring it.  Re or un-configuring of a
+ * non-empty transmit queue behaves exactly as defined above, however it
+ * is undefined as to how many of the pending entries in the original queue
+ * will be delivered prior to the re-configuration taking effect.
+ * Furthermore, as the queue configuration causes a reset of the head and
+ * tail pointers there is no way for a guest to determine how many entries
+ * have been sent after the configuration operation.
+ */
+#define HV_FAST_LDC_TX_QCONF            0xe0
+
+/* ldc_tx_qinfo()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_TX_QINFO
+ * ARG0:        channel ID
+ * RET0:        status
+ * RET1:        real address base of queue
+ * RET2:        num entries in queue
+ *
+ * Return the configuration info for the transmit queue of LDC endpoint
+ * defined by the given channel ID.  The real address is the currently
+ * defined real address base of the defined queue, and num entries is the
+ * size of the queue in terms of number of entries.
+ *
+ * If the specified channel ID is a valid endpoint number, but no transmit
+ * queue has been defined this service will return success, but with num
+ * entries set to zero and the real address will have an undefined value.
+ */
+#define HV_FAST_LDC_TX_QINFO            0xe1
+
+/* ldc_tx_get_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_TX_GET_STATE
+ * ARG0:        channel ID
+ * RET0:        status
+ * RET1:        head offset
+ * RET2:        tail offset
+ * RET3:        channel state
+ *
+ * Return the transmit state, and the head and tail queue pointers, for
+ * the transmit queue of the LDC endpoint defined by the given channel ID.
+ * The head and tail values are the byte offset of the head and tail
+ * positions of the transmit queue for the specified endpoint.
+ */
+#define HV_FAST_LDC_TX_GET_STATE        0xe2
+
+/* ldc_tx_set_qtail()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_TX_SET_QTAIL
+ * ARG0:        channel ID
+ * ARG1:        tail offset
+ * RET0:        status
+ *
+ * Update the tail pointer for the transmit queue associated with the LDC
+ * endpoint defined by the given channel ID.  The tail offset specified
+ * must be aligned on a 64 byte boundary, and calculated so as to increase
+ * the number of pending entries on the transmit queue.  Any attempt to
+ * decrease the number of pending transmit queue entires is considered
+ * an invalid tail offset and will result in an EINVAL error.
+ *
+ * Since the tail of the transmit queue may not be moved backwards, the
+ * transmit queue may be flushed by configuring a new transmit queue,
+ * whereupon the hypervisor will configure the initial transmit head and
+ * tail pointers to be equal.
+ */
+#define HV_FAST_LDC_TX_SET_QTAIL        0xe3
+
+/* ldc_rx_qconf()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_RX_QCONF
+ * ARG0:        channel ID
+ * ARG1:        real address base of queue
+ * ARG2:        num entries in queue
+ * RET0:        status
+ *
+ * Configure receive queue for the LDC endpoint specified by the
+ * given channel ID, to be placed at the given real address, and
+ * be of the given num entries.  Num entries must be a power of two.
+ * The real address base of the queue must be aligned on the queue
+ * size.  Each queue entry is 64-bytes, so for example, a 32 entry
+ * queue must be aligned on a 2048 byte real address boundary.
+ *
+ * The endpoint's transmit queue is un-configured if num entries is zero.
+ *
+ * If a valid receive queue is specified for a local endpoint the LDC is
+ * in the up state for the purpose of transmission to this endpoint.
+ *
+ * The maximum number of entries for each queue for a specific cpu may be
+ * determined from the machine description.
+ *
+ * As receive queue configuration causes a reset of the queue's head and
+ * tail pointers there is no way for a gues to determine how many entries
+ * have been received between a preceeding ldc_get_rx_state() API call
+ * and the completion of the configuration operation.  It should be noted
+ * that datagram delivery is not guarenteed via domain channels anyway,
+ * and therefore any higher protocol should be resilient to datagram
+ * loss if necessary.  However, to overcome this specific race potential
+ * it is recommended, for example, that a higher level protocol be employed
+ * to ensure either retransmission, or ensure that no datagrams are pending
+ * on the peer endpoint's transmit queue prior to the configuration process.
+ */
+#define HV_FAST_LDC_RX_QCONF            0xe4
+
+/* ldc_rx_qinfo()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_RX_QINFO
+ * ARG0:        channel ID
+ * RET0:        status
+ * RET1:        real address base of queue
+ * RET2:        num entries in queue
+ *
+ * Return the configuration info for the receive queue of LDC endpoint
+ * defined by the given channel ID.  The real address is the currently
+ * defined real address base of the defined queue, and num entries is the
+ * size of the queue in terms of number of entries.
+ *
+ * If the specified channel ID is a valid endpoint number, but no receive
+ * queue has been defined this service will return success, but with num
+ * entries set to zero and the real address will have an undefined value.
+ */
+#define HV_FAST_LDC_RX_QINFO            0xe5
+
+/* ldc_rx_get_state()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_RX_GET_STATE
+ * ARG0:        channel ID
+ * RET0:        status
+ * RET1:        head offset
+ * RET2:        tail offset
+ * RET3:        channel state
+ *
+ * Return the receive state, and the head and tail queue pointers, for
+ * the receive queue of the LDC endpoint defined by the given channel ID.
+ * The head and tail values are the byte offset of the head and tail
+ * positions of the receive queue for the specified endpoint.
+ */
+#define HV_FAST_LDC_RX_GET_STATE        0xe6
+
+/* ldc_rx_set_qhead()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_RX_SET_QHEAD
+ * ARG0:        channel ID
+ * ARG1:        head offset
+ * RET0:        status
+ *
+ * Update the head pointer for the receive queue associated with the LDC
+ * endpoint defined by the given channel ID.  The head offset specified
+ * must be aligned on a 64 byte boundary, and calculated so as to decrease
+ * the number of pending entries on the receive queue.  Any attempt to
+ * increase the number of pending receive queue entires is considered
+ * an invalid head offset and will result in an EINVAL error.
+ *
+ * The receive queue may be flushed by setting the head offset equal
+ * to the current tail offset.
+ */
+#define HV_FAST_LDC_RX_SET_QHEAD        0xe7
+
+/* LDC Map Table Entry.  Each slot is defined by a translation table
+ * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
+ * hypervisor invalidation cookie.
+ */
+#define LDC_MTE_PADDR   0x0fffffffffffe000 /* pa[55:13]          */
+#define LDC_MTE_COPY_W  0x0000000000000400 /* copy write access  */
+#define LDC_MTE_COPY_R  0x0000000000000200 /* copy read access   */
+#define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
+#define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access  */
+#define LDC_MTE_EXEC    0x0000000000000040 /* execute            */
+#define LDC_MTE_WRITE   0x0000000000000020 /* read               */
+#define LDC_MTE_READ    0x0000000000000010 /* write              */
+#define LDC_MTE_SZALL   0x000000000000000f /* page size bits     */
+#define LDC_MTE_SZ16GB  0x0000000000000007 /* 16GB page          */
+#define LDC_MTE_SZ2GB   0x0000000000000006 /* 2GB page           */
+#define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page         */
+#define LDC_MTE_SZ32MB  0x0000000000000004 /* 32MB page          */
+#define LDC_MTE_SZ4MB   0x0000000000000003 /* 4MB page           */
+#define LDC_MTE_SZ512K  0x0000000000000002 /* 512K page          */
+#define LDC_MTE_SZ64K   0x0000000000000001 /* 64K page           */
+#define LDC_MTE_SZ8K    0x0000000000000000 /* 8K page            */
+
+#ifndef __ASSEMBLY__
+struct ldc_mtable_entry {
+        unsigned long   mte;
+        unsigned long   cookie;
+};
+#endif
+
+/* ldc_set_map_table()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_SET_MAP_TABLE
+ * ARG0:        channel ID
+ * ARG1:        table real address
+ * ARG2:        num entries
+ * RET0:        status
+ *
+ * Register the MTE table at the given table real address, with the
+ * specified num entries, for the LDC indicated by the given channel
+ * ID.
+ */
+#define HV_FAST_LDC_SET_MAP_TABLE       0xea
+
+/* ldc_get_map_table()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_GET_MAP_TABLE
+ * ARG0:        channel ID
+ * RET0:        status
+ * RET1:        table real address
+ * RET2:        num entries
+ *
+ * Return the configuration of the current mapping table registered
+ * for the given channel ID.
+ */
+#define HV_FAST_LDC_GET_MAP_TABLE       0xeb
+
+#define LDC_COPY_IN     0
+#define LDC_COPY_OUT    1
+
+/* ldc_copy()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_COPY
+ * ARG0:        channel ID
+ * ARG1:        LDC_COPY_* direction code
+ * ARG2:        target real address
+ * ARG3:        local real address
+ * ARG4:        length in bytes
+ * RET0:        status
+ * RET1:        actual length in bytes
+ */
+#define HV_FAST_LDC_COPY                0xec
+
+#define LDC_MEM_READ    1
+#define LDC_MEM_WRITE   2
+#define LDC_MEM_EXEC    4
+
+/* ldc_mapin()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_MAPIN
+ * ARG0:        channel ID
+ * ARG1:        cookie
+ * RET0:        status
+ * RET1:        real address
+ * RET2:        LDC_MEM_* permissions
+ */
+#define HV_FAST_LDC_MAPIN               0xed
+
+/* ldc_unmap()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_UNMAP
+ * ARG0:        real address
+ * RET0:        status
+ */
+#define HV_FAST_LDC_UNMAP               0xee
+
+/* ldc_revoke()
+ * TRAP:        HV_FAST_TRAP
+ * FUNCTION:    HV_FAST_LDC_REVOKE
+ * ARG0:        cookie
+ * ARG1:        ldc_mtable_entry cookie
+ * RET0:        status
+ */
+#define HV_FAST_LDC_REVOKE              0xef
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
+                                        unsigned long ra,
+                                        unsigned long num_entries);
+extern unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
+                                        unsigned long *ra,
+                                        unsigned long *num_entries);
+extern unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
+                                            unsigned long *head_off,
+                                            unsigned long *tail_off,
+                                            unsigned long *chan_state);
+extern unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
+                                            unsigned long tail_off);
+extern unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
+                                        unsigned long ra,
+                                        unsigned long num_entries);
+extern unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
+                                        unsigned long *ra,
+                                        unsigned long *num_entries);
+extern unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
+                                            unsigned long *head_off,
+                                            unsigned long *tail_off,
+                                            unsigned long *chan_state);
+extern unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
+                                            unsigned long head_off);
+extern unsigned long sun4v_ldc_set_map_table(unsigned long channel,
+                                             unsigned long ra,
+                                             unsigned long num_entries);
+extern unsigned long sun4v_ldc_get_map_table(unsigned long channel,
+                                             unsigned long *ra,
+                                             unsigned long *num_entries);
+extern unsigned long sun4v_ldc_copy(unsigned long channel,
+                                    unsigned long dir_code,
+                                    unsigned long tgt_raddr,
+                                    unsigned long lcl_raddr,
+                                    unsigned long len,
+                                    unsigned long *actual_len);
+extern unsigned long sun4v_ldc_mapin(unsigned long channel,
+                                     unsigned long cookie,
+                                     unsigned long *ra,
+                                     unsigned long *perm);
+extern unsigned long sun4v_ldc_unmap(unsigned long ra);
+extern unsigned long sun4v_ldc_revoke(unsigned long cookie,
+                                      unsigned long mte_cookie);
+#endif
+
 /* Performance counter services.  */
 
 #define HV_PERF_JBUS_PERF_CTRL_REG      0x00
@@ -2121,8 +2725,42 @@ struct hv_mmu_statistics {
 #define HV_FAST_MMUSTAT_INFO            0x103
 
 /* Function numbers for HV_CORE_TRAP.  */
-#define HV_CORE_VER                     0x00
+#define HV_CORE_SET_VER                 0x00
 #define HV_CORE_PUTCHAR                 0x01
 #define HV_CORE_EXIT                    0x02
+#define HV_CORE_GET_VER                 0x03
+
+/* Hypervisor API groups for use with HV_CORE_SET_VER and
+ * HV_CORE_GET_VER.
+ */
+#define HV_GRP_SUN4V                    0x0000
+#define HV_GRP_CORE                     0x0001
+#define HV_GRP_INTR                     0x0002
+#define HV_GRP_SOFT_STATE               0x0003
+#define HV_GRP_PCI                      0x0100
+#define HV_GRP_LDOM                     0x0101
+#define HV_GRP_SVC_CHAN                 0x0102
+#define HV_GRP_NCS                      0x0103
+#define HV_GRP_NIAG_PERF                0x0200
+#define HV_GRP_FIRE_PERF                0x0201
+#define HV_GRP_DIAG                     0x0300
+
+#ifndef __ASSEMBLY__
+extern unsigned long sun4v_get_version(unsigned long group,
+                                       unsigned long *major,
+                                       unsigned long *minor);
+extern unsigned long sun4v_set_version(unsigned long group,
+                                       unsigned long major,
+                                       unsigned long minor,
+                                       unsigned long *actual_minor);
+
+extern int sun4v_hvapi_register(unsigned long group, unsigned long major,
+                                unsigned long *minor);
+extern void sun4v_hvapi_unregister(unsigned long group);
+extern int sun4v_hvapi_get(unsigned long group,
+                           unsigned long *major,
+                           unsigned long *minor);
+extern void sun4v_hvapi_init(void);
+#endif
 
 #endif /* !(_SPARC64_HYPERVISOR_H) */
diff --git a/include/asm-sparc64/kdebug.h b/include/asm-sparc64/kdebug.h
index 627e3396a5f0..9974c7b0aebc 100644
--- a/include/asm-sparc64/kdebug.h
+++ b/include/asm-sparc64/kdebug.h
@@ -32,7 +32,6 @@ enum die_val {
         DIE_TRAP,
         DIE_TRAP_TL1,
         DIE_CALL,
-        DIE_PAGE_FAULT,
 };
 
 #endif
diff --git a/include/asm-sparc64/mdesc.h b/include/asm-sparc64/mdesc.h
new file mode 100644
index 000000000000..124eb8ca2378
--- /dev/null
+++ b/include/asm-sparc64/mdesc.h
@@ -0,0 +1,39 @@
+#ifndef _SPARC64_MDESC_H
+#define _SPARC64_MDESC_H
+
+#include <linux/types.h>
+#include <asm/prom.h>
+
+struct mdesc_node;
+struct mdesc_arc {
+        const char              *name;
+        struct mdesc_node       *arc;
+};
+
+struct mdesc_node {
+        const char              *name;
+        u64                     node;
+        unsigned int            unique_id;
+        unsigned int            num_arcs;
+        struct property         *properties;
+        struct mdesc_node       *hash_next;
+        struct mdesc_node       *allnodes_next;
+        struct mdesc_arc        arcs[0];
+};
+
+extern struct mdesc_node *md_find_node_by_name(struct mdesc_node *from,
+                                               const char *name);
+#define md_for_each_node_by_name(__mn, __name) \
+        for (__mn = md_find_node_by_name(NULL, __name); __mn; \
+             __mn = md_find_node_by_name(__mn, __name))
+
+extern struct property *md_find_property(const struct mdesc_node *mp,
+                                         const char *name,
+                                         int *lenp);
+extern const void *md_get_property(const struct mdesc_node *mp,
+                                   const char *name,
+                                   int *lenp);
+
+extern void sun4v_mdesc_init(void);
+
+#endif
diff --git a/include/asm-sparc64/oplib.h b/include/asm-sparc64/oplib.h
index 6a0da3b1695c..992f9f7a476c 100644
--- a/include/asm-sparc64/oplib.h
+++ b/include/asm-sparc64/oplib.h
@@ -316,11 +316,8 @@ extern int prom_setprop(int node, const char *prop_name, char *prop_value,
                         
 extern int prom_pathtoinode(const char *path);
 extern int prom_inst2pkg(int);
-
-/* CPU probing helpers.  */
-struct device_node;
-int cpu_find_by_instance(int instance, struct device_node **dev_node, int *mid);
-int cpu_find_by_mid(int mid, struct device_node **prom_node);
+extern int prom_service_exists(const char *service_name);
+extern void prom_sun4v_guest_soft_state(void);
 
 /* Client interface level routines. */
 extern void prom_set_trap_table(unsigned long tba);
diff --git a/include/asm-sparc64/percpu.h b/include/asm-sparc64/percpu.h
index ced8cbde046d..88db872ce2f8 100644
--- a/include/asm-sparc64/percpu.h
+++ b/include/asm-sparc64/percpu.h
@@ -5,7 +5,8 @@
 
 #ifdef CONFIG_SMP
 
-extern void setup_per_cpu_areas(void);
+#define setup_per_cpu_areas()                   do { } while (0)
+extern void real_setup_per_cpu_areas(void);
 
 extern unsigned long __per_cpu_base;
 extern unsigned long __per_cpu_shift;
@@ -34,6 +35,7 @@ do {								\
 } while (0)
 #else /* ! SMP */
 
+#define real_setup_per_cpu_areas()              do { } while (0)
 #define DEFINE_PER_CPU(type, name) \
     __typeof__(type) per_cpu__##name
 
diff --git a/include/asm-sparc64/prom.h b/include/asm-sparc64/prom.h
index ddad5f99ac7f..b4df3042add0 100644
--- a/include/asm-sparc64/prom.h
+++ b/include/asm-sparc64/prom.h
@@ -90,6 +90,7 @@ extern struct device_node *of_find_compatible_node(struct device_node *from,
         const char *type, const char *compat);
 extern struct device_node *of_find_node_by_path(const char *path);
 extern struct device_node *of_find_node_by_phandle(phandle handle);
+extern struct device_node *of_find_node_by_cpuid(int cpuid);
 extern struct device_node *of_get_parent(const struct device_node *node);
 extern struct device_node *of_get_next_child(const struct device_node *node,
                                              struct device_node *prev);
diff --git a/include/asm-sparc64/smp.h b/include/asm-sparc64/smp.h
index 869d16fb907b..f76e1492add5 100644
--- a/include/asm-sparc64/smp.h
+++ b/include/asm-sparc64/smp.h
@@ -41,7 +41,7 @@ extern cpumask_t cpu_sibling_map[NR_CPUS];
 extern int hard_smp_processor_id(void);
 #define raw_smp_processor_id() (current_thread_info()->cpu)
 
-extern void smp_setup_cpu_possible_map(void);
+extern void smp_fill_in_sib_core_maps(void);
 extern unsigned char boot_cpu_id;
 
 #endif /* !(__ASSEMBLY__) */
@@ -49,7 +49,7 @@ extern unsigned char boot_cpu_id;
 #else
 
 #define hard_smp_processor_id()         0
-#define smp_setup_cpu_possible_map() do { } while (0)
+#define smp_fill_in_sib_core_maps() do { } while (0)
 #define boot_cpu_id     (0)
 
 #endif /* !(CONFIG_SMP) */
diff --git a/include/asm-sparc64/sstate.h b/include/asm-sparc64/sstate.h
new file mode 100644
index 000000000000..a7c35dbcb281
--- /dev/null
+++ b/include/asm-sparc64/sstate.h
@@ -0,0 +1,13 @@
+#ifndef _SPARC64_SSTATE_H
+#define _SPARC64_SSTATE_H
+
+extern void sstate_booting(void);
+extern void sstate_running(void);
+extern void sstate_halt(void);
+extern void sstate_poweroff(void);
+extern void sstate_panic(void);
+extern void sstate_reboot(void);
+
+extern void sun4v_sstate_init(void);
+
+#endif /* _SPARC64_SSTATE_H */
diff --git a/include/asm-sparc64/thread_info.h b/include/asm-sparc64/thread_info.h
index 2ebf7f27bf91..98252cd44dd6 100644
--- a/include/asm-sparc64/thread_info.h
+++ b/include/asm-sparc64/thread_info.h
@@ -38,8 +38,8 @@ struct thread_info {
         /* D$ line 1 */
         struct task_struct      *task;
         unsigned long           flags;
-        __u8                    cpu;
         __u8                    fpsaved[7];
+        __u8                    pad;
         unsigned long           ksp;
 
         /* D$ line 2 */
@@ -49,7 +49,7 @@ struct thread_info {
         int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
         __u8                    new_child;
         __u8                    syscall_noerror;
-        __u16                   __pad;
+        __u16                   cpu;
 
         unsigned long           *utraps;
 
@@ -83,8 +83,7 @@ struct thread_info {
 #define TI_CURRENT_DS   (TI_FLAGS + TI_FLAG_BYTE_CURRENT_DS)
 #define TI_FPDEPTH      (TI_FLAGS + TI_FLAG_BYTE_FPDEPTH)
 #define TI_WSAVED       (TI_FLAGS + TI_FLAG_BYTE_WSAVED)
-#define TI_CPU          0x00000010
-#define TI_FPSAVED      0x00000011
+#define TI_FPSAVED      0x00000010
 #define TI_KSP          0x00000018
 #define TI_FAULT_ADDR   0x00000020
 #define TI_KREGS        0x00000028
@@ -92,6 +91,7 @@ struct thread_info {
 #define TI_PRE_COUNT    0x00000038
 #define TI_NEW_CHILD    0x0000003c
 #define TI_SYS_NOERROR  0x0000003d
+#define TI_CPU          0x0000003e
 #define TI_UTRAPS       0x00000040
 #define TI_REG_WINDOW   0x00000048
 #define TI_RWIN_SPTRS   0x000003c8      
diff --git a/include/asm-sparc64/topology.h b/include/asm-sparc64/topology.h
index 98a6c613589d..e0d450d600ec 100644
--- a/include/asm-sparc64/topology.h
+++ b/include/asm-sparc64/topology.h
@@ -6,4 +6,7 @@
 
 #include <asm-generic/topology.h>
 
+#define topology_core_id(cpu)                   (cpu_data(cpu).core_id)
+#define topology_thread_siblings(cpu)           (cpu_sibling_map[cpu])
+
 #endif /* _ASM_SPARC64_TOPOLOGY_H */
diff --git a/include/asm-sparc64/tsb.h b/include/asm-sparc64/tsb.h
index ab55ffcb7bf4..76e4299dd9bc 100644
--- a/include/asm-sparc64/tsb.h
+++ b/include/asm-sparc64/tsb.h
@@ -271,7 +271,7 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
 #define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
         sethi           %hi(swapper_4m_tsb), REG1; \
         or              REG1, %lo(swapper_4m_tsb), REG1; \
-        and             TAG, (KERNEL_TSB_NENTRIES - 1), REG2; \
+        and             TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
         sllx            REG2, 4, REG2; \
         add             REG1, REG2, REG2; \
         KTSB_LOAD_QUAD(REG2, REG3); \
diff --git a/include/asm-x86_64/calgary.h b/include/asm-x86_64/calgary.h
index 7ee900645719..4d5747a0923c 100644
--- a/include/asm-x86_64/calgary.h
+++ b/include/asm-x86_64/calgary.h
@@ -27,6 +27,7 @@
 #include <linux/spinlock.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
+#include <linux/timer.h>
 #include <asm/types.h>
 
 struct iommu_table {
diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86_64/tlbflush.h
index 512401b8725f..8516225a8389 100644
--- a/include/asm-x86_64/tlbflush.h
+++ b/include/asm-x86_64/tlbflush.h
@@ -2,6 +2,7 @@
 #define _X8664_TLBFLUSH_H
 
 #include <linux/mm.h>
+#include <linux/sched.h>
 #include <asm/processor.h>
 #include <asm/system.h>
 
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index bcd01f269f60..e1013156c25e 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -239,6 +239,7 @@ unifdef-y += ipc.h
 unifdef-y += ipmi.h
 unifdef-y += ipv6.h
 unifdef-y += ipv6_route.h
+unifdef-y += ip6_tunnel.h
 unifdef-y += isdn.h
 unifdef-y += isdnif.h
 unifdef-y += isdn_divertif.h
diff --git a/include/linux/binfmts.h b/include/linux/binfmts.h
index 2d956cd566ae..e1a708337be3 100644
--- a/include/linux/binfmts.h
+++ b/include/linux/binfmts.h
@@ -17,6 +17,8 @@ struct pt_regs;
 
 #ifdef __KERNEL__
 
+#define CORENAME_MAX_SIZE 128
+
 /*
  * This structure is used to hold the arguments that are used when loading binaries.
  */
diff --git a/include/linux/capability.h b/include/linux/capability.h
index 6548b35ab9f6..bbf8df7de28f 100644
--- a/include/linux/capability.h
+++ b/include/linux/capability.h
@@ -16,6 +16,8 @@
 #include <linux/types.h>
 #include <linux/compiler.h>
 
+struct task_struct;
+
 /* User-level do most of the mapping between kernel and user
    capabilities based on the version tag given by the kernel. The
    kernel might be somewhat backwards compatible, but don't bet on
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index 498c35920762..8287a72bb6a9 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -36,9 +36,7 @@ extern void __chk_io_ptr(const void __iomem *);
 
 #ifdef __KERNEL__
 
-#if __GNUC__ > 4
-#error no compiler-gcc.h file for this gcc version
-#elif __GNUC__ == 4
+#if __GNUC__ >= 4
 # include <linux/compiler-gcc4.h>
 #elif __GNUC__ == 3 && __GNUC_MINOR__ >= 2
 # include <linux/compiler-gcc3.h>
diff --git a/include/linux/freezer.h b/include/linux/freezer.h
index 5e75e26d4787..4631086f5060 100644
--- a/include/linux/freezer.h
+++ b/include/linux/freezer.h
@@ -37,25 +37,25 @@ static inline void do_not_freeze(struct task_struct *p)
 
 /*
  * Wake up a frozen process
+ *
+ * task_lock() is taken to prevent the race with refrigerator() which may
+ * occur if the freezing of tasks fails.  Namely, without the lock, if the
+ * freezing of tasks failed, thaw_tasks() might have run before a task in
+ * refrigerator() could call frozen_process(), in which case the task would be
+ * frozen and no one would thaw it.
  */
 static inline int thaw_process(struct task_struct *p)
 {
+        task_lock(p);
         if (frozen(p)) {
                 p->flags &= ~PF_FROZEN;
+                task_unlock(p);
                 wake_up_process(p);
                 return 1;
         }
-        return 0;
-}
-
-/*
- * freezing is complete, mark process as frozen
- */
-static inline void frozen_process(struct task_struct *p)
-{
-        p->flags |= PF_FROZEN;
-        wmb();
         clear_tsk_thread_flag(p, TIF_FREEZE);
+        task_unlock(p);
+        return 0;
 }
 
 extern void refrigerator(void);
@@ -71,14 +71,55 @@ static inline int try_to_freeze(void)
                 return 0;
 }
 
-extern void thaw_some_processes(int all);
+/*
+ * The PF_FREEZER_SKIP flag should be set by a vfork parent right before it
+ * calls wait_for_completion(&vfork) and reset right after it returns from this
+ * function.  Next, the parent should call try_to_freeze() to freeze itself
+ * appropriately in case the child has exited before the freezing of tasks is
+ * complete.  However, we don't want kernel threads to be frozen in unexpected
+ * places, so we allow them to block freeze_processes() instead or to set
+ * PF_NOFREEZE if needed and PF_FREEZER_SKIP is only set for userland vfork
+ * parents.  Fortunately, in the ____call_usermodehelper() case the parent won't
+ * really block freeze_processes(), since ____call_usermodehelper() (the child)
+ * does a little before exec/exit and it can't be frozen before waking up the
+ * parent.
+ */
+
+/*
+ * If the current task is a user space one, tell the freezer not to count it as
+ * freezable.
+ */
+static inline void freezer_do_not_count(void)
+{
+        if (current->mm)
+                current->flags |= PF_FREEZER_SKIP;
+}
+
+/*
+ * If the current task is a user space one, tell the freezer to count it as
+ * freezable again and try to freeze it.
+ */
+static inline void freezer_count(void)
+{
+        if (current->mm) {
+                current->flags &= ~PF_FREEZER_SKIP;
+                try_to_freeze();
+        }
+}
+
+/*
+ * Check if the task should be counted as freezeable by the freezer
+ */
+static inline int freezer_should_skip(struct task_struct *p)
+{
+        return !!(p->flags & PF_FREEZER_SKIP);
+}
 
 #else
 static inline int frozen(struct task_struct *p) { return 0; }
 static inline int freezing(struct task_struct *p) { return 0; }
 static inline void freeze(struct task_struct *p) { BUG(); }
 static inline int thaw_process(struct task_struct *p) { return 1; }
-static inline void frozen_process(struct task_struct *p) { BUG(); }
 
 static inline void refrigerator(void) {}
 static inline int freeze_processes(void) { BUG(); return 0; }
@@ -86,5 +127,7 @@ static inline void thaw_processes(void) {}
 
 static inline int try_to_freeze(void) { return 0; }
 
-
+static inline void freezer_do_not_count(void) {}
+static inline void freezer_count(void) {}
+static inline int freezer_should_skip(struct task_struct *p) { return 0; }
 #endif
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index 4c03ee353e78..9756fc102a83 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -66,6 +66,7 @@ struct partition {
 #include <linux/smp.h>
 #include <linux/string.h>
 #include <linux/fs.h>
+#include <linux/workqueue.h>
 
 struct partition {
         unsigned char boot_ind;         /* 0x80 - active */
@@ -94,6 +95,7 @@ struct hd_struct {
 
 #define GENHD_FL_REMOVABLE                      1
 #define GENHD_FL_DRIVERFS                       2
+#define GENHD_FL_MEDIA_CHANGE_NOTIFY            4
 #define GENHD_FL_CD                             8
 #define GENHD_FL_UP                             16
 #define GENHD_FL_SUPPRESS_PARTITION_INFO        32
@@ -138,6 +140,7 @@ struct gendisk {
 #else
         struct disk_stats dkstats;
 #endif
+        struct work_struct async_notify;
 };
 
 /* Structure for sysfs attributes on block devices */
@@ -419,7 +422,7 @@ extern struct gendisk *alloc_disk_node(int minors, int node_id);
 extern struct gendisk *alloc_disk(int minors);
 extern struct kobject *get_disk(struct gendisk *disk);
 extern void put_disk(struct gendisk *disk);
-
+extern void genhd_media_change_notify(struct gendisk *disk);
 extern void blk_register_region(dev_t dev, unsigned long range,
                         struct module *module,
                         struct kobject *(*probe)(dev_t, int *, void *),
diff --git a/include/linux/if_ether.h b/include/linux/if_ether.h
index 1db774cf9dc2..3213f6f4aa58 100644
--- a/include/linux/if_ether.h
+++ b/include/linux/if_ether.h
@@ -33,6 +33,7 @@
 #define ETH_ZLEN        60              /* Min. octets in frame sans FCS */
 #define ETH_DATA_LEN    1500            /* Max. octets in payload        */
 #define ETH_FRAME_LEN   1514            /* Max. octets in frame sans FCS */
+#define ETH_FCS_LEN     4               /* Octets in the FCS             */
 
 /*
  *      These are the defined Ethernet Protocol ID's.
diff --git a/include/linux/init.h b/include/linux/init.h
index e007ae4dc41e..56ec4c62eee0 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -45,6 +45,19 @@
 #define __exitdata      __attribute__ ((__section__(".exit.data")))
 #define __exit_call     __attribute_used__ __attribute__ ((__section__ (".exitcall.exit")))
 
+/* modpost check for section mismatches during the kernel build.
+ * A section mismatch happens when there are references from a
+ * code or data section to an init section (both code or data).
+ * The init sections are (for most archs) discarded by the kernel
+ * when early init has completed so all such references are potential bugs.
+ * For exit sections the same issue exists.
+ * The following markers are used for the cases where the reference to
+ * the init/exit section (code or data) is valid and will teach modpost
+ * not to issue a warning.
+ * The markers follow same syntax rules as __init / __initdata. */
+#define __init_refok     noinline __attribute__ ((__section__ (".text.init.refok")))
+#define __initdata_refok          __attribute__ ((__section__ (".data.init.refok")))
+
 #ifdef MODULE
 #define __exit          __attribute__ ((__section__(".exit.text")))
 #else
diff --git a/include/linux/kmalloc_sizes.h b/include/linux/kmalloc_sizes.h
index bda23e00ed71..e576b848ce10 100644
--- a/include/linux/kmalloc_sizes.h
+++ b/include/linux/kmalloc_sizes.h
@@ -19,17 +19,27 @@
         CACHE(32768)
         CACHE(65536)
         CACHE(131072)
-#if (NR_CPUS > 512) || (MAX_NUMNODES > 256) || !defined(CONFIG_MMU)
+#if KMALLOC_MAX_SIZE >= 262144
         CACHE(262144)
 #endif
-#ifndef CONFIG_MMU
+#if KMALLOC_MAX_SIZE >= 524288
         CACHE(524288)
+#endif
+#if KMALLOC_MAX_SIZE >= 1048576
         CACHE(1048576)
-#ifdef CONFIG_LARGE_ALLOCS
+#endif
+#if KMALLOC_MAX_SIZE >= 2097152
         CACHE(2097152)
+#endif
+#if KMALLOC_MAX_SIZE >= 4194304
         CACHE(4194304)
+#endif
+#if KMALLOC_MAX_SIZE >= 8388608
         CACHE(8388608)
+#endif
+#if KMALLOC_MAX_SIZE >= 16777216
         CACHE(16777216)
+#endif
+#if KMALLOC_MAX_SIZE >= 33554432
         CACHE(33554432)
-#endif /* CONFIG_LARGE_ALLOCS */
-#endif /* CONFIG_MMU */
+#endif
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 27d936279574..85f7b1bd1482 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -140,6 +140,7 @@ enum {
 
         ATA_DFLAG_PIO           = (1 << 8), /* device limited to PIO mode */
         ATA_DFLAG_NCQ_OFF       = (1 << 9), /* device limited to non-NCQ mode */
+        ATA_DFLAG_SPUNDOWN      = (1 << 10), /* XXX: for spindown_compat */
         ATA_DFLAG_INIT_MASK     = (1 << 16) - 1,
 
         ATA_DFLAG_DETACH        = (1 << 16),
@@ -173,6 +174,7 @@ enum {
         ATA_FLAG_SETXFER_POLLING= (1 << 14), /* use polling for SETXFER */
         ATA_FLAG_IGN_SIMPLEX    = (1 << 15), /* ignore SIMPLEX */
         ATA_FLAG_NO_IORDY       = (1 << 16), /* controller lacks iordy */
+        ATA_FLAG_ACPI_SATA      = (1 << 17), /* need native SATA ACPI layout */
 
         /* The following flag belongs to ap->pflags but is kept in
          * ap->flags because it's referenced in many LLDs and will be
@@ -431,7 +433,6 @@ struct ata_device {
         struct scsi_device      *sdev;          /* attached SCSI device */
         /* n_sector is used as CLEAR_OFFSET, read comment above CLEAR_OFFSET */
         u64                     n_sectors;      /* size of device, if ATA */
-        u64                     n_sectors_boot; /* size of ATA device at startup */
         unsigned int            class;          /* ATA_DEV_xxx */
         u16                     id[ATA_ID_WORDS]; /* IDENTIFY xxx DEVICE data */
         u8                      pio_mode;
@@ -573,8 +574,6 @@ struct ata_port_operations {
         void (*phy_reset) (struct ata_port *ap); /* obsolete */
         int  (*set_mode) (struct ata_port *ap, struct ata_device **r_failed_dev);
 
-        void (*post_set_mode) (struct ata_port *ap);
-
         int (*cable_detect) (struct ata_port *ap);
 
         int  (*check_atapi_dma) (struct ata_queued_cmd *qc);
diff --git a/include/linux/lockd/xdr4.h b/include/linux/lockd/xdr4.h
index dd12b4c9e613..12bfe09de2b1 100644
--- a/include/linux/lockd/xdr4.h
+++ b/include/linux/lockd/xdr4.h
@@ -42,5 +42,6 @@ int	nlmclt_encode_lockargs(struct rpc_rqst *, u32 *, struct nlm_args *);
 int     nlmclt_encode_cancargs(struct rpc_rqst *, u32 *, struct nlm_args *);
 int     nlmclt_encode_unlockargs(struct rpc_rqst *, u32 *, struct nlm_args *);
  */
+extern struct rpc_version nlm_version4;
 
 #endif /* LOCKD_XDR4_H */
diff --git a/include/linux/log2.h b/include/linux/log2.h
index 57e641e19a81..1b8a2c1cb0e3 100644
--- a/include/linux/log2.h
+++ b/include/linux/log2.h
@@ -159,7 +159,7 @@ unsigned long __roundup_pow_of_two(unsigned long n)
 #define roundup_pow_of_two(n)                   \
 (                                               \
         __builtin_constant_p(n) ? (             \
-                (n == 1) ? 0 :                  \
+                (n == 1) ? 1 :                  \
                 (1UL << (ilog2((n) - 1) + 1))   \
                                    ) :          \
         __roundup_pow_of_two(n)                 \
diff --git a/include/linux/mii.h b/include/linux/mii.h
index beddc6d3b0f6..151b7e0182c7 100644
--- a/include/linux/mii.h
+++ b/include/linux/mii.h
@@ -56,8 +56,8 @@
 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 #define BMSR_RESV               0x00c0  /* Unused...                   */
 #define BMSR_ESTATEN            0x0100  /* Extended Status in R15 */
-#define BMSR_100FULL2           0x0200  /* Can do 100BASE-T2 HDX */
-#define BMSR_100HALF2           0x0400  /* Can do 100BASE-T2 FDX */
+#define BMSR_100HALF2           0x0200  /* Can do 100BASE-T2 HDX */
+#define BMSR_100FULL2           0x0400  /* Can do 100BASE-T2 FDX */
 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
 #define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
 #define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 4670ebd1f622..e4183c6c7de3 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1,7 +1,6 @@
 #ifndef _LINUX_MM_H
 #define _LINUX_MM_H
 
-#include <linux/sched.h>
 #include <linux/errno.h>
 #include <linux/capability.h>
 
@@ -20,6 +19,7 @@
 
 struct mempolicy;
 struct anon_vma;
+struct user_struct;
 
 #ifndef CONFIG_DISCONTIGMEM          /* Don't use mapnrs, do it properly */
 extern unsigned long max_mapnr;
@@ -717,14 +717,7 @@ extern unsigned long shmem_get_unmapped_area(struct file *file,
                                              unsigned long flags);
 #endif
 
-static inline int can_do_mlock(void)
-{
-        if (capable(CAP_IPC_LOCK))
-                return 1;
-        if (current->signal->rlim[RLIMIT_MEMLOCK].rlim_cur != 0)
-                return 1;
-        return 0;
-}
+extern int can_do_mlock(void);
 extern int user_shm_lock(size_t, struct user_struct *);
 extern void user_shm_unlock(size_t, struct user_struct *);
 
diff --git a/include/linux/netfilter/nf_conntrack_ftp.h b/include/linux/netfilter/nf_conntrack_ftp.h
index 81453ea7e4c2..b7c360ffd0d0 100644
--- a/include/linux/netfilter/nf_conntrack_ftp.h
+++ b/include/linux/netfilter/nf_conntrack_ftp.h
@@ -37,8 +37,7 @@ extern unsigned int (*nf_nat_ftp_hook)(struct sk_buff **pskb,
                                        enum nf_ct_ftp_type type,
                                        unsigned int matchoff,
                                        unsigned int matchlen,
-                                       struct nf_conntrack_expect *exp,
-                                       u32 *seq);
+                                       struct nf_conntrack_expect *exp);
 #endif /* __KERNEL__ */
 
 #endif /* _NF_CONNTRACK_FTP_H */
diff --git a/include/linux/netfilter/nf_conntrack_h323_types.h b/include/linux/netfilter/nf_conntrack_h323_types.h
index 38d74d5c9700..f35b6b4801e7 100644
--- a/include/linux/netfilter/nf_conntrack_h323_types.h
+++ b/include/linux/netfilter/nf_conntrack_h323_types.h
@@ -1,4 +1,4 @@
-/* Generated by Jing Min Zhao's ASN.1 parser, Apr 20 2006
+/* Generated by Jing Min Zhao's ASN.1 parser, May 16 2007
  *
  * Copyright (c) 2006 Jing Min Zhao <zhaojingmin@users.sourceforge.net>
  *
@@ -12,7 +12,7 @@ typedef struct TransportAddress_ipAddress {	/* SEQUENCE */
 
 typedef struct TransportAddress_ip6Address {    /* SEQUENCE */
         int options;            /* No use */
-        unsigned ip6;
+        unsigned ip;
 } TransportAddress_ip6Address;
 
 typedef struct TransportAddress {       /* CHOICE */
@@ -364,23 +364,6 @@ typedef struct Alerting_UUIE {	/* SEQUENCE */
         Alerting_UUIE_fastStart fastStart;
 } Alerting_UUIE;
 
-typedef struct Information_UUIE_fastStart {     /* SEQUENCE OF */
-        int count;
-        OpenLogicalChannel item[30];
-} Information_UUIE_fastStart;
-
-typedef struct Information_UUIE {       /* SEQUENCE */
-        enum {
-                eInformation_UUIE_callIdentifier = (1 << 31),
-                eInformation_UUIE_tokens = (1 << 30),
-                eInformation_UUIE_cryptoTokens = (1 << 29),
-                eInformation_UUIE_fastStart = (1 << 28),
-                eInformation_UUIE_fastConnectRefused = (1 << 27),
-                eInformation_UUIE_circuitInfo = (1 << 26),
-        } options;
-        Information_UUIE_fastStart fastStart;
-} Information_UUIE;
-
 typedef struct FacilityReason { /* CHOICE */
         enum {
                 eFacilityReason_routeCallToGatekeeper,
@@ -471,7 +454,6 @@ typedef struct H323_UU_PDU_h323_message_body {	/* CHOICE */
                 CallProceeding_UUIE callProceeding;
                 Connect_UUIE connect;
                 Alerting_UUIE alerting;
-                Information_UUIE information;
                 Facility_UUIE facility;
                 Progress_UUIE progress;
         };
@@ -561,6 +543,7 @@ typedef struct OpenLogicalChannelAck {	/* SEQUENCE */
         } options;
         OpenLogicalChannelAck_reverseLogicalChannelParameters
             reverseLogicalChannelParameters;
+        NetworkAccessParameters separateStack;
         OpenLogicalChannelAck_forwardMultiplexAckParameters
             forwardMultiplexAckParameters;
 } OpenLogicalChannelAck;
diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h
index 1be5be88debe..7e7f33a38fc0 100644
--- a/include/linux/nfs4.h
+++ b/include/linux/nfs4.h
@@ -16,6 +16,7 @@
 #include <linux/types.h>
 
 #define NFS4_VERIFIER_SIZE      8
+#define NFS4_STATEID_SIZE       16
 #define NFS4_FHSIZE             128
 #define NFS4_MAXPATHLEN         PATH_MAX
 #define NFS4_MAXNAMLEN          NAME_MAX
@@ -113,7 +114,7 @@ struct nfs4_acl {
 };
 
 typedef struct { char data[NFS4_VERIFIER_SIZE]; } nfs4_verifier;
-typedef struct { char data[16]; } nfs4_stateid;
+typedef struct { char data[NFS4_STATEID_SIZE]; } nfs4_stateid;
 
 enum nfs_opnum4 {
         OP_ACCESS = 3,
diff --git a/include/linux/nfs_page.h b/include/linux/nfs_page.h
index 41afab6b5f09..bd193af80162 100644
--- a/include/linux/nfs_page.h
+++ b/include/linux/nfs_page.h
@@ -81,6 +81,7 @@ extern	void nfs_pageio_init(struct nfs_pageio_descriptor *desc,
 extern  int nfs_pageio_add_request(struct nfs_pageio_descriptor *,
                                    struct nfs_page *);
 extern  void nfs_pageio_complete(struct nfs_pageio_descriptor *desc);
+extern  void nfs_pageio_cond_complete(struct nfs_pageio_descriptor *, pgoff_t);
 extern  int nfs_wait_on_request(struct nfs_page *);
 extern  void nfs_unlock_request(struct nfs_page *req);
 extern  int nfs_set_page_writeback_locked(struct nfs_page *req);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 3b1fbf49fa7d..4712e269d8d3 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -371,6 +371,7 @@
 #define PCI_DEVICE_ID_ATI_IXP600_SMBUS  0x4385
 #define PCI_DEVICE_ID_ATI_IXP600_IDE    0x438c
 #define PCI_DEVICE_ID_ATI_IXP700_SATA   0x4390
+#define PCI_DEVICE_ID_ATI_IXP700_IDE    0x439c
 
 #define PCI_VENDOR_ID_VLSI              0x1004
 #define PCI_DEVICE_ID_VLSI_82C592       0x0005
@@ -471,6 +472,7 @@
 #define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2 0x0219
 #define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX         0x021A
 #define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM     0x0251
+#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361
 #define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL  0x252
 
 #define PCI_VENDOR_ID_COMPEX2           0x101a /* pci.ids says "AT&T GIS (NCR)" */
diff --git a/include/linux/raid/bitmap.h b/include/linux/raid/bitmap.h
index 6db9a4c15355..dd5a05d03d4f 100644
--- a/include/linux/raid/bitmap.h
+++ b/include/linux/raid/bitmap.h
@@ -232,6 +232,7 @@ struct bitmap {
         struct page **filemap; /* list of cache pages for the file */
         unsigned long *filemap_attr; /* attributes associated w/ filemap pages */
         unsigned long file_pages; /* number of pages in the file */
+        int last_page_size; /* bytes in the last page */
 
         unsigned long flags;
 
diff --git a/include/linux/rmap.h b/include/linux/rmap.h
index bdd277223af0..97347f22fc20 100644
--- a/include/linux/rmap.h
+++ b/include/linux/rmap.h
@@ -74,17 +74,14 @@ void page_add_new_anon_rmap(struct page *, struct vm_area_struct *, unsigned lon
 void page_add_file_rmap(struct page *);
 void page_remove_rmap(struct page *, struct vm_area_struct *);
 
-/**
- * page_dup_rmap - duplicate pte mapping to a page
- * @page:       the page to add the mapping to
- *
- * For copy_page_range only: minimal extract from page_add_rmap,
- * avoiding unnecessary tests (already checked) so it's quicker.
- */
-static inline void page_dup_rmap(struct page *page)
+#ifdef CONFIG_DEBUG_VM
+void page_dup_rmap(struct page *page, struct vm_area_struct *vma, unsigned long address);
+#else
+static inline void page_dup_rmap(struct page *page, struct vm_area_struct *vma, unsigned long address)
 {
         atomic_inc(&page->_mapcount);
 }
+#endif
 
 /*
  * Called from mm/vmscan.c to handle paging out
diff --git a/include/linux/sched.h b/include/linux/sched.h
index a81897e2a244..d58e74b98367 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -1182,6 +1182,7 @@ static inline void put_task_struct(struct task_struct *t)
 #define PF_SPREAD_SLAB  0x02000000      /* Spread some slab caches over cpuset */
 #define PF_MEMPOLICY    0x10000000      /* Non-default NUMA mempolicy */
 #define PF_MUTEX_TESTER 0x20000000      /* Thread belongs to the rt mutex tester */
+#define PF_FREEZER_SKIP 0x40000000      /* Freezer should not count it as freezeable */
 
 /*
  * Only the _current_ task can read/write to tsk->flags, but other
@@ -1615,11 +1616,13 @@ static inline int lock_need_resched(spinlock_t *lock)
         return 0;
 }
 
-/* Reevaluate whether the task has signals pending delivery.
-   This is required every time the blocked sigset_t changes.
-   callers must hold sighand->siglock.  */
-
-extern FASTCALL(void recalc_sigpending_tsk(struct task_struct *t));
+/*
+ * Reevaluate whether the task has signals pending delivery.
+ * Wake the task if so.
+ * This is required every time the blocked sigset_t changes.
+ * callers must hold sighand->siglock.
+ */
+extern void recalc_sigpending_and_wake(struct task_struct *t);
 extern void recalc_sigpending(void);
 
 extern void signal_wake_up(struct task_struct *t, int resume_stopped);
diff --git a/include/linux/slab.h b/include/linux/slab.h
index 71829efc40ba..a015236cc572 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -32,9 +32,6 @@ typedef struct kmem_cache kmem_cache_t __deprecated;
 #define SLAB_MEM_SPREAD         0x00100000UL    /* Spread some memory over cpuset */
 #define SLAB_TRACE              0x00200000UL    /* Trace allocations and frees */
 
-/* Flags passed to a constructor functions */
-#define SLAB_CTOR_CONSTRUCTOR   0x001UL         /* If not set, then deconstructor */
-
 /*
  * struct kmem_cache related prototypes
  */
@@ -77,6 +74,21 @@ static inline void *kmem_cache_alloc_node(struct kmem_cache *cachep,
 #endif
 
 /*
+ * The largest kmalloc size supported by the slab allocators is
+ * 32 megabyte (2^25) or the maximum allocatable page order if that is
+ * less than 32 MB.
+ *
+ * WARNING: Its not easy to increase this value since the allocators have
+ * to do various tricks to work around compiler limitations in order to
+ * ensure proper constant folding.
+ */
+#define KMALLOC_SHIFT_HIGH      ((MAX_ORDER + PAGE_SHIFT) <= 25 ? \
+                                (MAX_ORDER + PAGE_SHIFT) : 25)
+
+#define KMALLOC_MAX_SIZE        (1UL << KMALLOC_SHIFT_HIGH)
+#define KMALLOC_MAX_ORDER       (KMALLOC_SHIFT_HIGH - PAGE_SHIFT)
+
+/*
  * Common kmalloc functions provided by all allocators
  */
 void *__kmalloc(size_t, gfp_t);
@@ -233,9 +245,6 @@ extern void *__kmalloc_node_track_caller(size_t, gfp_t, int, void *);
 
 #endif /* DEBUG_SLAB */
 
-extern const struct seq_operations slabinfo_op;
-ssize_t slabinfo_write(struct file *, const char __user *, size_t, loff_t *);
-
 #endif  /* __KERNEL__ */
 #endif  /* _LINUX_SLAB_H */
 
diff --git a/include/linux/slab_def.h b/include/linux/slab_def.h
index 5e4364644ed1..8d81a60518e4 100644
--- a/include/linux/slab_def.h
+++ b/include/linux/slab_def.h
@@ -109,4 +109,7 @@ found:
 
 #endif  /* CONFIG_NUMA */
 
+extern const struct seq_operations slabinfo_op;
+ssize_t slabinfo_write(struct file *, const char __user *, size_t, loff_t *);
+
 #endif  /* _LINUX_SLAB_DEF_H */
diff --git a/include/linux/slub_def.h b/include/linux/slub_def.h
index fd6627e2d115..0764c829d967 100644
--- a/include/linux/slub_def.h
+++ b/include/linux/slub_def.h
@@ -40,7 +40,6 @@ struct kmem_cache {
         int objects;            /* Number of objects in slab */
         int refcount;           /* Refcount for slab cache destroy */
         void (*ctor)(void *, struct kmem_cache *, unsigned long);
-        void (*dtor)(void *, struct kmem_cache *, unsigned long);
         int inuse;              /* Offset to metadata */
         int align;              /* Alignment */
         const char *name;       /* Name (only for display!) */
@@ -59,17 +58,6 @@ struct kmem_cache {
  */
 #define KMALLOC_SHIFT_LOW 3
 
-#ifdef CONFIG_LARGE_ALLOCS
-#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT) =< 25 ? \
-                                (MAX_ORDER + PAGE_SHIFT - 1) : 25)
-#else
-#if !defined(CONFIG_MMU) || NR_CPUS > 512 || MAX_NUMNODES > 256
-#define KMALLOC_SHIFT_HIGH 20
-#else
-#define KMALLOC_SHIFT_HIGH 18
-#endif
-#endif
-
 /*
  * We keep the general caches in an array of slab caches that are used for
  * 2^x bytes of allocations.
@@ -80,7 +68,7 @@ extern struct kmem_cache kmalloc_caches[KMALLOC_SHIFT_HIGH + 1];
  * Sorry that the following has to be that ugly but some versions of GCC
  * have trouble with constant propagation and loops.
  */
-static inline int kmalloc_index(int size)
+static inline int kmalloc_index(size_t size)
 {
         /*
          * We should return 0 if size == 0 but we use the smallest object
@@ -88,7 +76,7 @@ static inline int kmalloc_index(int size)
          */
         WARN_ON_ONCE(size == 0);
 
-        if (size >= (1 << KMALLOC_SHIFT_HIGH))
+        if (size > KMALLOC_MAX_SIZE)
                 return -1;
 
         if (size > 64 && size <= 96)
@@ -111,17 +99,13 @@ static inline int kmalloc_index(int size)
         if (size <=  64 * 1024) return 16;
         if (size <= 128 * 1024) return 17;
         if (size <= 256 * 1024) return 18;
-#if KMALLOC_SHIFT_HIGH > 18
         if (size <=  512 * 1024) return 19;
         if (size <= 1024 * 1024) return 20;
-#endif
-#if KMALLOC_SHIFT_HIGH > 20
         if (size <=  2 * 1024 * 1024) return 21;
         if (size <=  4 * 1024 * 1024) return 22;
         if (size <=  8 * 1024 * 1024) return 23;
         if (size <= 16 * 1024 * 1024) return 24;
         if (size <= 32 * 1024 * 1024) return 25;
-#endif
         return -1;
 
 /*
@@ -146,7 +130,12 @@ static inline struct kmem_cache *kmalloc_slab(size_t size)
         if (index == 0)
                 return NULL;
 
-        if (index < 0) {
+        /*
+         * This function only gets expanded if __builtin_constant_p(size), so
+         * testing it here shouldn't be needed.  But some versions of gcc need
+         * help.
+         */
+        if (__builtin_constant_p(size) && index < 0) {
                 /*
                  * Generate a link failure. Would be great if we could
                  * do something to stop the compile here.
diff --git a/include/linux/smb_fs.h b/include/linux/smb_fs.h
index 13b3af547864..2c5cd55f44ff 100644
--- a/include/linux/smb_fs.h
+++ b/include/linux/smb_fs.h
@@ -29,6 +29,7 @@
 #include <linux/pagemap.h>
 #include <linux/vmalloc.h>
 #include <linux/smb_mount.h>
+#include <linux/jiffies.h>
 #include <asm/unaligned.h>
 
 static inline struct smb_sb_info *SMB_SB(struct super_block *sb)
diff --git a/include/linux/smp.h b/include/linux/smp.h
index 3f70149eabbb..96ac21f8dd73 100644
--- a/include/linux/smp.h
+++ b/include/linux/smp.h
@@ -6,6 +6,7 @@
  *              Alan Cox. <alan@redhat.com>
  */
 
+#include <linux/errno.h>
 
 extern void cpu_idle(void);
 
@@ -99,11 +100,9 @@ static inline void smp_send_reschedule(int cpu) { }
 #define num_booting_cpus()                      1
 #define smp_prepare_boot_cpu()                  do {} while (0)
 static inline int smp_call_function_single(int cpuid, void (*func) (void *info),
-                                void *info, int retry, int wait)
+                                           void *info, int retry, int wait)
 {
-        /* Disable interrupts here? */
-        func(info);
-        return 0;
+        return -EBUSY;
 }
 
 #endif /* !SMP */
diff --git a/include/linux/sunrpc/rpc_pipe_fs.h b/include/linux/sunrpc/rpc_pipe_fs.h
index 4a68125b6de6..ad293760f6eb 100644
--- a/include/linux/sunrpc/rpc_pipe_fs.h
+++ b/include/linux/sunrpc/rpc_pipe_fs.h
@@ -47,6 +47,8 @@ extern struct dentry *rpc_mkpipe(struct dentry *, const char *, void *, struct r
 extern int rpc_unlink(struct dentry *);
 extern struct vfsmount *rpc_get_mount(void);
 extern void rpc_put_mount(void);
+extern int register_rpc_pipefs(void);
+extern void unregister_rpc_pipefs(void);
 
 #endif
 #endif
diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h
index fa89ce6ce076..34f7590506fa 100644
--- a/include/linux/sunrpc/xprt.h
+++ b/include/linux/sunrpc/xprt.h
@@ -244,6 +244,8 @@ void			xprt_disconnect(struct rpc_xprt *xprt);
  */
 struct rpc_xprt *       xs_setup_udp(struct sockaddr *addr, size_t addrlen, struct rpc_timeout *to);
 struct rpc_xprt *       xs_setup_tcp(struct sockaddr *addr, size_t addrlen, struct rpc_timeout *to);
+int                     init_socket_xprt(void);
+void                    cleanup_socket_xprt(void);
 
 /*
  * Reserved bit positions in xprt->state
diff --git a/include/linux/task_io_accounting_ops.h b/include/linux/task_io_accounting_ops.h
index 1218733ec6b5..ff46c6fad79d 100644
--- a/include/linux/task_io_accounting_ops.h
+++ b/include/linux/task_io_accounting_ops.h
@@ -4,6 +4,8 @@
 #ifndef __TASK_IO_ACCOUNTING_OPS_INCLUDED
 #define __TASK_IO_ACCOUNTING_OPS_INCLUDED
 
+#include <linux/sched.h>
+
 #ifdef CONFIG_TASK_IO_ACCOUNTING
 static inline void task_io_account_read(size_t bytes)
 {
diff --git a/include/linux/timer.h b/include/linux/timer.h
index e0c5c16c992f..c661710d3627 100644
--- a/include/linux/timer.h
+++ b/include/linux/timer.h
@@ -69,6 +69,12 @@ extern int __mod_timer(struct timer_list *timer, unsigned long expires);
 extern int mod_timer(struct timer_list *timer, unsigned long expires);
 
 /*
+ * The jiffies value which is added to now, when there is no timer
+ * in the timer wheel:
+ */
+#define NEXT_TIMER_MAX_DELTA    ((1UL << 30) - 1)
+
+/*
  * Return when the next timer-wheel timeout occurs (in absolute jiffies),
  * locks the timer base:
  */
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index a25c2afa67e1..e7560389079c 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -267,8 +267,6 @@ struct v4l2_pix_format
         __u32                   sizeimage;
         enum v4l2_colorspace    colorspace;
         __u32                   priv;           /* private data, depends on pixelformat */
-        __u32                   left;   /* only valid if V4L2_CAP_VIDEO_OUTPUT_POS is set */
-        __u32                   top;    /* only valid if V4L2_CAP_VIDEO_OUTPUT_POS is set */
 };
 
 /*      Pixel format         FOURCC                        depth  Description  */
diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h
index d555f31c0746..ce0719a2cfeb 100644
--- a/include/linux/workqueue.h
+++ b/include/linux/workqueue.h
@@ -122,7 +122,7 @@ extern struct workqueue_struct *__create_workqueue(const char *name,
                                                     int singlethread,
                                                     int freezeable);
 #define create_workqueue(name) __create_workqueue((name), 0, 0)
-#define create_freezeable_workqueue(name) __create_workqueue((name), 0, 1)
+#define create_freezeable_workqueue(name) __create_workqueue((name), 1, 1)
 #define create_singlethread_workqueue(name) __create_workqueue((name), 1, 0)
 
 extern void destroy_workqueue(struct workqueue_struct *wq);
@@ -160,7 +160,7 @@ static inline int cancel_delayed_work(struct delayed_work *work)
 {
         int ret;
 
-        ret = del_timer(&work->timer);
+        ret = del_timer_sync(&work->timer);
         if (ret)
                 work_clear_pending(&work->work);
         return ret;
diff --git a/include/linux/writeback.h b/include/linux/writeback.h
index 050915b59576..4ef4d22e5e43 100644
--- a/include/linux/writeback.h
+++ b/include/linux/writeback.h
@@ -4,6 +4,8 @@
 #ifndef WRITEBACK_H
 #define WRITEBACK_H
 
+#include <linux/sched.h>
+
 struct backing_dev_info;
 
 extern spinlock_t inode_lock;
diff --git a/include/net/bluetooth/l2cap.h b/include/net/bluetooth/l2cap.h
index 8242a0ee1f58..87df4e87622d 100644
--- a/include/net/bluetooth/l2cap.h
+++ b/include/net/bluetooth/l2cap.h
@@ -129,8 +129,10 @@ struct l2cap_conf_rsp {
         __u8       data[0];
 } __attribute__ ((packed));
 
-#define L2CAP_CONF_SUCCESS      0x00
-#define L2CAP_CONF_UNACCEPT     0x01
+#define L2CAP_CONF_SUCCESS      0x0000
+#define L2CAP_CONF_UNACCEPT     0x0001
+#define L2CAP_CONF_REJECT       0x0002
+#define L2CAP_CONF_UNKNOWN      0x0003
 
 struct l2cap_conf_opt {
         __u8       type;
@@ -215,6 +217,8 @@ struct l2cap_pinfo {
 
         __u32           link_mode;
 
+        __u8            conf_req[64];
+        __u8            conf_len;
         __u8            conf_state;
         __u8            conf_retry;
         __u16           conf_mtu;
diff --git a/include/net/dst.h b/include/net/dst.h
index e12a8ce0b9b3..82270f9332db 100644
--- a/include/net/dst.h
+++ b/include/net/dst.h
@@ -265,9 +265,16 @@ static inline int xfrm_lookup(struct dst_entry **dst_p, struct flowi *fl,
 {
         return 0;
 } 
+static inline int __xfrm_lookup(struct dst_entry **dst_p, struct flowi *fl,
+                                struct sock *sk, int flags)
+{
+        return 0;
+}
 #else
 extern int xfrm_lookup(struct dst_entry **dst_p, struct flowi *fl,
                        struct sock *sk, int flags);
+extern int __xfrm_lookup(struct dst_entry **dst_p, struct flowi *fl,
+                         struct sock *sk, int flags);
 #endif
 #endif
 
diff --git a/include/net/ipv6.h b/include/net/ipv6.h
index 4fa5dfe886c4..78a0d06d98d5 100644
--- a/include/net/ipv6.h
+++ b/include/net/ipv6.h
@@ -469,6 +469,9 @@ extern void			ip6_flush_pending_frames(struct sock *sk);
 extern int                      ip6_dst_lookup(struct sock *sk,
                                                struct dst_entry **dst,
                                                struct flowi *fl);
+extern int                      ip6_dst_blackhole(struct sock *sk,
+                                                  struct dst_entry **dst,
+                                                  struct flowi *fl);
 extern int                      ip6_sk_dst_lookup(struct sock *sk,
                                                   struct dst_entry **dst,
                                                   struct flowi *fl);
diff --git a/include/rdma/ib_umem.h b/include/rdma/ib_umem.h
index b3a36f7d79e5..c533d6c7903f 100644
--- a/include/rdma/ib_umem.h
+++ b/include/rdma/ib_umem.h
@@ -35,6 +35,7 @@
 
 #include <linux/list.h>
 #include <linux/scatterlist.h>
+#include <linux/workqueue.h>
 
 struct ib_ucontext;
 
diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h
index 47cefca59c89..0627a6aa282a 100644
--- a/include/rdma/ib_verbs.h
+++ b/include/rdma/ib_verbs.h
@@ -890,6 +890,8 @@ struct ib_device {
         spinlock_t                    client_data_lock;
 
         struct ib_cache               cache;
+        int                          *pkey_tbl_len;
+        int                          *gid_tbl_len;
 
         u32                           flags;
 
@@ -1118,6 +1120,12 @@ int ib_modify_port(struct ib_device *device,
                    u8 port_num, int port_modify_mask,
                    struct ib_port_modify *port_modify);
 
+int ib_find_gid(struct ib_device *device, union ib_gid *gid,
+                u8 *port_num, u16 *index);
+
+int ib_find_pkey(struct ib_device *device,
+                 u8 port_num, u16 pkey, u16 *index);
+
 /**
  * ib_alloc_pd - Allocates an unused protection domain.
  * @device: The device on which to allocate the protection domain.
diff --git a/include/sound/soc.h b/include/sound/soc.h
index b1dc364b8f74..db6edba8ef08 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -22,7 +22,7 @@
 #include <sound/control.h>
 #include <sound/ac97_codec.h>
 
-#define SND_SOC_VERSION "0.13.0"
+#define SND_SOC_VERSION "0.13.1"
 
 /*
  * Convenience kcontrol builders
@@ -83,6 +83,7 @@
 #define SND_SOC_DAI_AC97        0x1
 #define SND_SOC_DAI_I2S         0x2
 #define SND_SOC_DAI_PCM         0x4
+#define SND_SOC_DAI_AC97_BUS    0x8     /* for custom i.e. non ac97_codec.c */
 
 /*
  * DAI hardware audio formats
@@ -278,6 +279,7 @@ struct snd_soc_cpu_ops {
 struct snd_soc_codec_dai {
         char *name;
         int id;
+        unsigned char type;
 
         /* DAI capabilities */
         struct snd_soc_pcm_stream playback;
diff --git a/include/sound/version.h b/include/sound/version.h
index e820f0e7bdd3..50ee4fd420fa 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
 /* include/version.h.  Generated by alsa/ksync script.  */
 #define CONFIG_SND_VERSION "1.0.14rc4"
-#define CONFIG_SND_DATE " (Wed May 09 09:51:39 2007 UTC)"
+#define CONFIG_SND_DATE " (Wed May 16 09:45:46 2007 UTC)"