1 files changed, 36 insertions, 0 deletions

diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index be94be6d6f17..d7079f42624b 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -509,6 +509,7 @@ typedef struct {
 #define DRM_RADEON_GEM_SET_TILING       0x28
 #define DRM_RADEON_GEM_GET_TILING       0x29
 #define DRM_RADEON_GEM_BUSY             0x2a
+#define DRM_RADEON_GEM_VA               0x2b
 
 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
@@ -550,6 +551,7 @@ typedef struct {
 #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
 #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
 #define DRM_IOCTL_RADEON_GEM_BUSY       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
+#define DRM_IOCTL_RADEON_GEM_VA         DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
 
 typedef struct drm_radeon_init {
         enum {
@@ -872,12 +874,42 @@ struct drm_radeon_gem_pwrite {
         uint64_t data_ptr;
 };
 
+#define RADEON_VA_MAP                   1
+#define RADEON_VA_UNMAP                 2
+
+#define RADEON_VA_RESULT_OK             0
+#define RADEON_VA_RESULT_ERROR          1
+#define RADEON_VA_RESULT_VA_EXIST       2
+
+#define RADEON_VM_PAGE_VALID            (1 << 0)
+#define RADEON_VM_PAGE_READABLE         (1 << 1)
+#define RADEON_VM_PAGE_WRITEABLE        (1 << 2)
+#define RADEON_VM_PAGE_SYSTEM           (1 << 3)
+#define RADEON_VM_PAGE_SNOOPED          (1 << 4)
+
+struct drm_radeon_gem_va {
+        uint32_t                handle;
+        uint32_t                operation;
+        uint32_t                vm_id;
+        uint32_t                flags;
+        uint64_t                offset;
+};
+
 #define RADEON_CHUNK_ID_RELOCS  0x01
 #define RADEON_CHUNK_ID_IB      0x02
 #define RADEON_CHUNK_ID_FLAGS   0x03
 
 /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
+#define RADEON_CS_USE_VM            0x02
+/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
+#define RADEON_CS_RING_GFX          0
+#define RADEON_CS_RING_COMPUTE      1
+/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
+/* 0 = normal, + = higher priority, - = lower priority */
+struct drm_radeon_cs_ring_priority {
+        int32_t                 priority;
+};
 
 struct drm_radeon_cs_chunk {
         uint32_t                chunk_id;
@@ -916,6 +948,10 @@ struct drm_radeon_cs {
 #define RADEON_INFO_NUM_TILE_PIPES      0x0b /* tile pipes for r600+ */
 #define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
 #define RADEON_INFO_BACKEND_MAP         0x0d /* pipe to backend map, needed by mesa */
+/* virtual address start, va < start are reserved by the kernel */
+#define RADEON_INFO_VA_START            0x0e
+/* maximum size of ib using the virtual memory cs */
+#define RADEON_INFO_IB_VM_MAX_SIZE      0x0f
 
 struct drm_radeon_info {
         uint32_t                request;