4 files changed, 57 insertions, 48 deletions
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 37134aaf9954..17e1548cec08 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -88,20 +88,25 @@
 #define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Register (alternate macro) */
 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR                         0xFFC00400     /* Transmit Holding register */
-#define UART_RBR                         0xFFC00400     /* Receive Buffer register */
+/*
-#define UART_DLL                         0xFFC00400     /* Divisor Latch (Low-Byte) */
+ * Because include/linux/serial_reg.h have defined UART_*,
-#define UART_IER                         0xFFC00404     /* Interrupt Enable Register */
+ * So we define blackfin uart regs to BFIN_UART_*.
-#define UART_DLH                         0xFFC00404     /* Divisor Latch (High-Byte) */
+ */
-#define UART_IIR                         0xFFC00408     /* Interrupt Identification Register */
+#define BFIN_UART_THR                   0xFFC00400      /* Transmit Holding register */
-#define UART_LCR                         0xFFC0040C     /* Line Control Register */
+#define BFIN_UART_RBR                   0xFFC00400      /* Receive Buffer register */
-#define UART_MCR                         0xFFC00410     /* Modem Control Register */
+#define BFIN_UART_DLL                   0xFFC00400      /* Divisor Latch (Low-Byte) */
-#define UART_LSR                         0xFFC00414     /* Line Status Register */
+#define BFIN_UART_IER                   0xFFC00404      /* Interrupt Enable Register */
+#define BFIN_UART_DLH                   0xFFC00404      /* Divisor Latch (High-Byte) */
+#define BFIN_UART_IIR                   0xFFC00408      /* Interrupt Identification Register */
+#define BFIN_UART_LCR                   0xFFC0040C      /* Line Control Register */
+#define BFIN_UART_MCR                   0xFFC00410      /* Modem Control Register */
+#define BFIN_UART_LSR                   0xFFC00414      /* Line Status Register */
 #if 0
-#define UART_MSR                         0xFFC00418   /* Modem Status Register (UNUSED in ADSP-BF532) */
+#define BFIN_UART_MSR                   0xFFC00418      /* Modem Status Register (UNUSED in ADSP-BF532) */
 #endif
-#define UART_SCR                         0xFFC0041C     /* SCR Scratch Register */
+#define BFIN_UART_SCR                   0xFFC0041C      /* SCR Scratch Register */
-#define UART_GCTL                        0xFFC00424     /* Global Control Register */
+#define BFIN_UART_GCTL                  0xFFC00424      /* Global Control Register */
 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
 #define SPI0_REGBASE                    0xFFC00500
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
index 53fcfa3408d0..4f10ee0ae10d 100644
--- a/include/asm-blackfin/mach-bf537/blackfin.h
+++ b/include/asm-blackfin/mach-bf537/blackfin.h
@@ -82,8 +82,6 @@
 #define STATUS_P1       0x02
 #define STATUS_P0       0x01
-/* UART 0*/
 /* DMA Channnel */
 #define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
 #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
@@ -106,37 +104,37 @@
 /* MMR Registers*/
 #define bfin_read_UART_THR() bfin_read_UART0_THR()
 #define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
-#define UART_THR UART0_THR
+#define BFIN_UART_THR UART0_THR
 #define bfin_read_UART_RBR() bfin_read_UART0_RBR()
 #define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
-#define UART_RBR UART0_RBR
+#define BFIN_UART_RBR UART0_RBR
 #define bfin_read_UART_DLL() bfin_read_UART0_DLL()
 #define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
-#define UART_DLL UART0_DLL
+#define BFIN_UART_DLL UART0_DLL
 #define bfin_read_UART_IER() bfin_read_UART0_IER()
 #define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
-#define UART_IER UART0_IER
+#define BFIN_UART_IER UART0_IER
 #define bfin_read_UART_DLH() bfin_read_UART0_DLH()
 #define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
-#define UART_DLH UART0_DLH
+#define BFIN_UART_DLH UART0_DLH
 #define bfin_read_UART_IIR() bfin_read_UART0_IIR()
 #define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
-#define UART_IIR UART0_IIR
+#define BFIN_UART_IIR UART0_IIR
 #define bfin_read_UART_LCR() bfin_read_UART0_LCR()
 #define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
-#define UART_LCR UART0_LCR
+#define BFIN_UART_LCR UART0_LCR
 #define bfin_read_UART_MCR() bfin_read_UART0_MCR()
 #define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
-#define UART_MCR UART0_MCR
+#define BFIN_UART_MCR UART0_MCR
 #define bfin_read_UART_LSR() bfin_read_UART0_LSR()
 #define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
-#define UART_LSR UART0_LSR
+#define BFIN_UART_LSR UART0_LSR
 #define bfin_read_UART_SCR() bfin_read_UART0_SCR()
 #define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
-#define UART_SCR  UART0_SCR
+#define BFIN_UART_SCR  UART0_SCR
 #define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
 #define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
-#define UART_GCTL UART0_GCTL
+#define BFIN_UART_GCTL UART0_GCTL
 /* DPMC*/
 #define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
index 3bd67da86053..b8509c16ecd4 100644
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -153,17 +153,18 @@
 #define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
 #define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
 #define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
-#define UART_THR                        UART1_THR
-#define UART_RBR                        UART1_RBR
+#define BFIN_UART_THR                   UART1_THR
-#define UART_DLL                        UART1_DLL
+#define BFIN_UART_RBR                   UART1_RBR
-#define UART_IER                        UART1_IER
+#define BFIN_UART_DLL                   UART1_DLL
-#define UART_DLH                        UART1_DLH
+#define BFIN_UART_IER                   UART1_IER
-#define UART_IIR                        UART1_IIR
+#define BFIN_UART_DLH                   UART1_DLH
-#define UART_LCR                        UART1_LCR
+#define BFIN_UART_IIR                   UART1_IIR
-#define UART_MCR                        UART1_MCR
+#define BFIN_UART_LCR                   UART1_LCR
-#define UART_LSR                        UART1_LSR
+#define BFIN_UART_MCR                   UART1_MCR
-#define UART_SCR                        UART1_SCR
+#define BFIN_UART_LSR                   UART1_LSR
-#define UART_GCTL                       UART1_GCTL
+#define BFIN_UART_SCR                   UART1_SCR
+#define BFIN_UART_GCTL                  UART1_GCTL
 /* PLL_DIV Masks */
 #define CCLK_DIV1 CSEL_DIV1     /* CCLK = VCO / 1 */
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index c3c0eb13c819..bee30230187b 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -110,18 +110,23 @@
 #define WDOGB_STAT                              0xFFC01208      /* Watchdog Status register */
 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR                0xFFC00400      /* Transmit Holding register */
-#define UART_RBR                0xFFC00400      /* Receive Buffer register */
+/*
-#define UART_DLL                0xFFC00400      /* Divisor Latch (Low-Byte) */
+ * Because include/linux/serial_reg.h have defined UART_*,
-#define UART_IER                0xFFC00404      /* Interrupt Enable Register */
+ * So we define blackfin uart regs to BFIN_UART0_*.
-#define UART_DLH                0xFFC00404      /* Divisor Latch (High-Byte) */
+ */
-#define UART_IIR                0xFFC00408      /* Interrupt Identification Register */
+#define BFIN_UART_THR                   0xFFC00400  /* Transmit Holding register */
-#define UART_LCR                0xFFC0040C      /* Line Control Register */
+#define BFIN_UART_RBR                   0xFFC00400  /* Receive Buffer register */
-#define UART_MCR                                0xFFC00410      /* Modem Control Register */
+#define BFIN_UART_DLL                   0xFFC00400  /* Divisor Latch (Low-Byte) */
-#define UART_LSR                0xFFC00414      /* Line Status Register */
+#define BFIN_UART_IER                   0xFFC00404  /* Interrupt Enable Register */
-#define UART_MSR                0xFFC00418      /* Modem Status Register */
+#define BFIN_UART_DLH                   0xFFC00404  /* Divisor Latch (High-Byte) */
-#define UART_SCR                0xFFC0041C      /* SCR Scratch Register */
+#define BFIN_UART_IIR                   0xFFC00408  /* Interrupt Identification Register */
-#define UART_GCTL               0xFFC00424      /* Global Control Register */
+#define BFIN_UART_LCR                   0xFFC0040C  /* Line Control Register */
+#define BFIN_UART_MCR                   0xFFC00410  /* Modem Control Register */
+#define BFIN_UART_LSR                   0xFFC00414  /* Line Status Register */
+#define BFIN_UART_MSR                   0xFFC00418  /* Modem Status Register */
+#define BFIN_UART_SCR                   0xFFC0041C  /* SCR Scratch Register */
+#define BFIN_UART_GCTL                  0xFFC00424  /* Global Control Register */
 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
 #define SPI0_REGBASE                    0xFFC00500

diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h index 37134aaf9954..17e1548cec08 100644 --- a/include/asm-blackfin/mach-bf533/defBF532.h +++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -88,20 +88,25 @@
88	#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */	88	#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
89		89
90	/* UART Controller (0xFFC00400 - 0xFFC004FF) */	90	/* UART Controller (0xFFC00400 - 0xFFC004FF) */
91	#define UART_THR 0xFFC00400 /* Transmit Holding register */	91
92	#define UART_RBR 0xFFC00400 /* Receive Buffer register */	92	/*
93	#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */	93	* Because include/linux/serial_reg.h have defined UART_*,
94	#define UART_IER 0xFFC00404 /* Interrupt Enable Register */	94	* So we define blackfin uart regs to BFIN_UART_*.
95	#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */	95	*/
96	#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */	96	#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
97	#define UART_LCR 0xFFC0040C /* Line Control Register */	97	#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
98	#define UART_MCR 0xFFC00410 /* Modem Control Register */	98	#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
99	#define UART_LSR 0xFFC00414 /* Line Status Register */	99	#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
		100	#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
		101	#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
		102	#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
		103	#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
		104	#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
100	#if 0	105	#if 0
101	#define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */	106	#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
102	#endif	107	#endif
103	#define UART_SCR 0xFFC0041C /* SCR Scratch Register */	108	#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
104	#define UART_GCTL 0xFFC00424 /* Global Control Register */	109	#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
105		110
106	/* SPI Controller (0xFFC00500 - 0xFFC005FF) */	111	/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
107	#define SPI0_REGBASE 0xFFC00500	112	#define SPI0_REGBASE 0xFFC00500


diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h index 53fcfa3408d0..4f10ee0ae10d 100644 --- a/include/asm-blackfin/mach-bf537/blackfin.h +++ b/include/asm-blackfin/mach-bf537/blackfin.h
@@ -82,8 +82,6 @@
82	#define STATUS_P1 0x02	82	#define STATUS_P1 0x02
83	#define STATUS_P0 0x01	83	#define STATUS_P0 0x01
84		84
85	/* UART 0*/
86
87	/* DMA Channnel */	85	/* DMA Channnel */
88	#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()	86	#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
89	#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)	87	#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
@@ -106,37 +104,37 @@
106	/* MMR Registers*/	104	/* MMR Registers*/
107	#define bfin_read_UART_THR() bfin_read_UART0_THR()	105	#define bfin_read_UART_THR() bfin_read_UART0_THR()
108	#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)	106	#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
109	#define UART_THR UART0_THR	107	#define BFIN_UART_THR UART0_THR
110	#define bfin_read_UART_RBR() bfin_read_UART0_RBR()	108	#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
111	#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)	109	#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
112	#define UART_RBR UART0_RBR	110	#define BFIN_UART_RBR UART0_RBR
113	#define bfin_read_UART_DLL() bfin_read_UART0_DLL()	111	#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
114	#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)	112	#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
115	#define UART_DLL UART0_DLL	113	#define BFIN_UART_DLL UART0_DLL
116	#define bfin_read_UART_IER() bfin_read_UART0_IER()	114	#define bfin_read_UART_IER() bfin_read_UART0_IER()
117	#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)	115	#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
118	#define UART_IER UART0_IER	116	#define BFIN_UART_IER UART0_IER
119	#define bfin_read_UART_DLH() bfin_read_UART0_DLH()	117	#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
120	#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)	118	#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
121	#define UART_DLH UART0_DLH	119	#define BFIN_UART_DLH UART0_DLH
122	#define bfin_read_UART_IIR() bfin_read_UART0_IIR()	120	#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
123	#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)	121	#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
124	#define UART_IIR UART0_IIR	122	#define BFIN_UART_IIR UART0_IIR
125	#define bfin_read_UART_LCR() bfin_read_UART0_LCR()	123	#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
126	#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)	124	#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
127	#define UART_LCR UART0_LCR	125	#define BFIN_UART_LCR UART0_LCR
128	#define bfin_read_UART_MCR() bfin_read_UART0_MCR()	126	#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
129	#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)	127	#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
130	#define UART_MCR UART0_MCR	128	#define BFIN_UART_MCR UART0_MCR
131	#define bfin_read_UART_LSR() bfin_read_UART0_LSR()	129	#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
132	#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)	130	#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
133	#define UART_LSR UART0_LSR	131	#define BFIN_UART_LSR UART0_LSR
134	#define bfin_read_UART_SCR() bfin_read_UART0_SCR()	132	#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
135	#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)	133	#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
136	#define UART_SCR UART0_SCR	134	#define BFIN_UART_SCR UART0_SCR
137	#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()	135	#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
138	#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)	136	#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
139	#define UART_GCTL UART0_GCTL	137	#define BFIN_UART_GCTL UART0_GCTL
140		138
141	/* DPMC*/	139	/* DPMC*/
142	#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()	140	#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()


diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h index 3bd67da86053..b8509c16ecd4 100644 --- a/include/asm-blackfin/mach-bf548/blackfin.h +++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -153,17 +153,18 @@
153	#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)	153	#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
154	#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()	154	#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
155	#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)	155	#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
156	#define UART_THR UART1_THR	156
157	#define UART_RBR UART1_RBR	157	#define BFIN_UART_THR UART1_THR
158	#define UART_DLL UART1_DLL	158	#define BFIN_UART_RBR UART1_RBR
159	#define UART_IER UART1_IER	159	#define BFIN_UART_DLL UART1_DLL
160	#define UART_DLH UART1_DLH	160	#define BFIN_UART_IER UART1_IER
161	#define UART_IIR UART1_IIR	161	#define BFIN_UART_DLH UART1_DLH
162	#define UART_LCR UART1_LCR	162	#define BFIN_UART_IIR UART1_IIR
163	#define UART_MCR UART1_MCR	163	#define BFIN_UART_LCR UART1_LCR
164	#define UART_LSR UART1_LSR	164	#define BFIN_UART_MCR UART1_MCR
165	#define UART_SCR UART1_SCR	165	#define BFIN_UART_LSR UART1_LSR
166	#define UART_GCTL UART1_GCTL	166	#define BFIN_UART_SCR UART1_SCR
		167	#define BFIN_UART_GCTL UART1_GCTL
167		168
168	/* PLL_DIV Masks */	169	/* PLL_DIV Masks */
169	#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */	170	#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */


diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index c3c0eb13c819..bee30230187b 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -110,18 +110,23 @@
110	#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */	110	#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
111		111
112	/* UART Controller (0xFFC00400 - 0xFFC004FF) */	112	/* UART Controller (0xFFC00400 - 0xFFC004FF) */
113	#define UART_THR 0xFFC00400 /* Transmit Holding register */	113
114	#define UART_RBR 0xFFC00400 /* Receive Buffer register */	114	/*
115	#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */	115	* Because include/linux/serial_reg.h have defined UART_*,
116	#define UART_IER 0xFFC00404 /* Interrupt Enable Register */	116	* So we define blackfin uart regs to BFIN_UART0_*.
117	#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */	117	*/
118	#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */	118	#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
119	#define UART_LCR 0xFFC0040C /* Line Control Register */	119	#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
120	#define UART_MCR 0xFFC00410 /* Modem Control Register */	120	#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
121	#define UART_LSR 0xFFC00414 /* Line Status Register */	121	#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
122	#define UART_MSR 0xFFC00418 /* Modem Status Register */	122	#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
123	#define UART_SCR 0xFFC0041C /* SCR Scratch Register */	123	#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
124	#define UART_GCTL 0xFFC00424 /* Global Control Register */	124	#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
		125	#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
		126	#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
		127	#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
		128	#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
		129	#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
125		130
126	/* SPI Controller (0xFFC00500 - 0xFFC005FF) */	131	/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
127	#define SPI0_REGBASE 0xFFC00500	132	#define SPI0_REGBASE 0xFFC00500