aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/addrspace.h40
-rw-r--r--include/asm-mips/atomic.h10
-rw-r--r--include/asm-mips/bitops.h65
-rw-r--r--include/asm-mips/bug.h12
-rw-r--r--include/asm-mips/cpu-info.h10
-rw-r--r--include/asm-mips/dec/kn02.h2
-rw-r--r--include/asm-mips/dma.h2
-rw-r--r--include/asm-mips/gt64120.h14
-rw-r--r--include/asm-mips/io.h2
-rw-r--r--include/asm-mips/irq.h8
-rw-r--r--include/asm-mips/kexec.h32
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h29
-rw-r--r--include/asm-mips/mach-cobalt/mach-gt64120.h28
-rw-r--r--include/asm-mips/mipsregs.h56
-rw-r--r--include/asm-mips/page.h16
-rw-r--r--include/asm-mips/pgtable-64.h13
-rw-r--r--include/asm-mips/pgtable.h2
-rw-r--r--include/asm-mips/ptrace.h2
-rw-r--r--include/asm-mips/time.h9
-rw-r--r--include/linux/kexec.h2
20 files changed, 172 insertions, 182 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 45c706e34df1..c6275088cf65 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -19,12 +19,16 @@
19#define _ATYPE_ 19#define _ATYPE_
20#define _ATYPE32_ 20#define _ATYPE32_
21#define _ATYPE64_ 21#define _ATYPE64_
22#define _LLCONST_(x) x 22#define _CONST64_(x) x
23#else 23#else
24#define _ATYPE_ __PTRDIFF_TYPE__ 24#define _ATYPE_ __PTRDIFF_TYPE__
25#define _ATYPE32_ int 25#define _ATYPE32_ int
26#define _ATYPE64_ long long 26#define _ATYPE64_ __s64
27#define _LLCONST_(x) x ## LL 27#ifdef CONFIG_64BIT
28#define _CONST64_(x) x ## L
29#else
30#define _CONST64_(x) x ## LL
31#endif
28#endif 32#endif
29 33
30/* 34/*
@@ -48,7 +52,7 @@
48 */ 52 */
49#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) 53#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
50#define XPHYSADDR(a) ((_ACAST64_(a)) & \ 54#define XPHYSADDR(a) ((_ACAST64_(a)) & \
51 _LLCONST_(0x000000ffffffffff)) 55 _CONST64_(0x000000ffffffffff))
52 56
53#ifdef CONFIG_64BIT 57#ifdef CONFIG_64BIT
54 58
@@ -57,14 +61,14 @@
57 * The compatibility segments use the full 64-bit sign extended value. Note 61 * The compatibility segments use the full 64-bit sign extended value. Note
58 * the R8000 doesn't have them so don't reference these in generic MIPS code. 62 * the R8000 doesn't have them so don't reference these in generic MIPS code.
59 */ 63 */
60#define XKUSEG _LLCONST_(0x0000000000000000) 64#define XKUSEG _CONST64_(0x0000000000000000)
61#define XKSSEG _LLCONST_(0x4000000000000000) 65#define XKSSEG _CONST64_(0x4000000000000000)
62#define XKPHYS _LLCONST_(0x8000000000000000) 66#define XKPHYS _CONST64_(0x8000000000000000)
63#define XKSEG _LLCONST_(0xc000000000000000) 67#define XKSEG _CONST64_(0xc000000000000000)
64#define CKSEG0 _LLCONST_(0xffffffff80000000) 68#define CKSEG0 _CONST64_(0xffffffff80000000)
65#define CKSEG1 _LLCONST_(0xffffffffa0000000) 69#define CKSEG1 _CONST64_(0xffffffffa0000000)
66#define CKSSEG _LLCONST_(0xffffffffc0000000) 70#define CKSSEG _CONST64_(0xffffffffc0000000)
67#define CKSEG3 _LLCONST_(0xffffffffe0000000) 71#define CKSEG3 _CONST64_(0xffffffffe0000000)
68 72
69#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) 73#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
70#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) 74#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
@@ -122,7 +126,7 @@
122#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) 126#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
123#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) 127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
124#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) 128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
125#define PHYS_TO_XKPHYS(cm,a) (_LLCONST_(0x8000000000000000) | \ 129#define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \
126 ((cm)<<59) | (a)) 130 ((cm)<<59) | (a))
127 131
128#if defined (CONFIG_CPU_R4300) \ 132#if defined (CONFIG_CPU_R4300) \
@@ -132,20 +136,20 @@
132 || defined (CONFIG_CPU_NEVADA) \ 136 || defined (CONFIG_CPU_NEVADA) \
133 || defined (CONFIG_CPU_TX49XX) \ 137 || defined (CONFIG_CPU_TX49XX) \
134 || defined (CONFIG_CPU_MIPS64) 138 || defined (CONFIG_CPU_MIPS64)
135#define TO_PHYS_MASK _LLCONST_(0x0000000fffffffff) /* 2^^36 - 1 */ 139#define TO_PHYS_MASK _CONST64_(0x0000000fffffffff) /* 2^^36 - 1 */
136#endif 140#endif
137 141
138#if defined (CONFIG_CPU_R8000) 142#if defined (CONFIG_CPU_R8000)
139/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */ 143/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
140#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ 144#define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */
141#endif 145#endif
142 146
143#if defined (CONFIG_CPU_R10000) 147#if defined (CONFIG_CPU_R10000)
144#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ 148#define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */
145#endif 149#endif
146 150
147#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A) 151#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
148#define TO_PHYS_MASK _LLCONST_(0x00000fffffffffff) /* 2^^44 - 1 */ 152#define TO_PHYS_MASK _CONST64_(0x00000fffffffffff) /* 2^^44 - 1 */
149#endif 153#endif
150 154
151#ifndef CONFIG_CPU_R8000 155#ifndef CONFIG_CPU_R8000
@@ -155,7 +159,7 @@
155 * in order to catch bugs in the source code. 159 * in order to catch bugs in the source code.
156 */ 160 */
157 161
158#define COMPAT_K1BASE32 _LLCONST_(0xffffffffa0000000) 162#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
159#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ 163#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
160 164
161#endif 165#endif
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index e64abc0d8221..7978d8e11647 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -9,16 +9,8 @@
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details. 10 * for more details.
11 * 11 *
12 * Copyright (C) 1996, 97, 99, 2000, 03, 04 by Ralf Baechle 12 * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
13 */ 13 */
14
15/*
16 * As workaround for the ATOMIC_DEC_AND_LOCK / atomic_dec_and_lock mess in
17 * <linux/spinlock.h> we have to include <linux/spinlock.h> outside the
18 * main big wrapper ...
19 */
20#include <linux/spinlock.h>
21
22#ifndef _ASM_ATOMIC_H 14#ifndef _ASM_ATOMIC_H
23#define _ASM_ATOMIC_H 15#define _ASM_ATOMIC_H
24 16
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 1bb89c5a10ee..b9007411b60f 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -10,31 +10,26 @@
10#define _ASM_BITOPS_H 10#define _ASM_BITOPS_H
11 11
12#include <linux/compiler.h> 12#include <linux/compiler.h>
13#include <linux/irqflags.h>
13#include <linux/types.h> 14#include <linux/types.h>
14#include <asm/bug.h> 15#include <asm/bug.h>
15#include <asm/byteorder.h> /* sigh ... */ 16#include <asm/byteorder.h> /* sigh ... */
16#include <asm/cpu-features.h> 17#include <asm/cpu-features.h>
18#include <asm/sgidefs.h>
19#include <asm/war.h>
17 20
18#if (_MIPS_SZLONG == 32) 21#if (_MIPS_SZLONG == 32)
19#define SZLONG_LOG 5 22#define SZLONG_LOG 5
20#define SZLONG_MASK 31UL 23#define SZLONG_MASK 31UL
21#define __LL "ll " 24#define __LL "ll "
22#define __SC "sc " 25#define __SC "sc "
23#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
24#elif (_MIPS_SZLONG == 64) 26#elif (_MIPS_SZLONG == 64)
25#define SZLONG_LOG 6 27#define SZLONG_LOG 6
26#define SZLONG_MASK 63UL 28#define SZLONG_MASK 63UL
27#define __LL "lld " 29#define __LL "lld "
28#define __SC "scd " 30#define __SC "scd "
29#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
30#endif 31#endif
31 32
32#ifdef __KERNEL__
33
34#include <linux/irqflags.h>
35#include <asm/sgidefs.h>
36#include <asm/war.h>
37
38/* 33/*
39 * clear_bit() doesn't provide any barrier for the compiler. 34 * clear_bit() doesn't provide any barrier for the compiler.
40 */ 35 */
@@ -42,20 +37,6 @@
42#define smp_mb__after_clear_bit() smp_mb() 37#define smp_mb__after_clear_bit() smp_mb()
43 38
44/* 39/*
45 * Only disable interrupt for kernel mode stuff to keep usermode stuff
46 * that dares to use kernel include files alive.
47 */
48
49#define __bi_flags unsigned long flags
50#define __bi_local_irq_save(x) local_irq_save(x)
51#define __bi_local_irq_restore(x) local_irq_restore(x)
52#else
53#define __bi_flags
54#define __bi_local_irq_save(x)
55#define __bi_local_irq_restore(x)
56#endif /* __KERNEL__ */
57
58/*
59 * set_bit - Atomically set a bit in memory 40 * set_bit - Atomically set a bit in memory
60 * @nr: the bit to set 41 * @nr: the bit to set
61 * @addr: the address to start counting from 42 * @addr: the address to start counting from
@@ -93,13 +74,13 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
93 } else { 74 } else {
94 volatile unsigned long *a = addr; 75 volatile unsigned long *a = addr;
95 unsigned long mask; 76 unsigned long mask;
96 __bi_flags; 77 unsigned long flags;
97 78
98 a += nr >> SZLONG_LOG; 79 a += nr >> SZLONG_LOG;
99 mask = 1UL << (nr & SZLONG_MASK); 80 mask = 1UL << (nr & SZLONG_MASK);
100 __bi_local_irq_save(flags); 81 local_irq_save(flags);
101 *a |= mask; 82 *a |= mask;
102 __bi_local_irq_restore(flags); 83 local_irq_restore(flags);
103 } 84 }
104} 85}
105 86
@@ -141,13 +122,13 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
141 } else { 122 } else {
142 volatile unsigned long *a = addr; 123 volatile unsigned long *a = addr;
143 unsigned long mask; 124 unsigned long mask;
144 __bi_flags; 125 unsigned long flags;
145 126
146 a += nr >> SZLONG_LOG; 127 a += nr >> SZLONG_LOG;
147 mask = 1UL << (nr & SZLONG_MASK); 128 mask = 1UL << (nr & SZLONG_MASK);
148 __bi_local_irq_save(flags); 129 local_irq_save(flags);
149 *a &= ~mask; 130 *a &= ~mask;
150 __bi_local_irq_restore(flags); 131 local_irq_restore(flags);
151 } 132 }
152} 133}
153 134
@@ -191,13 +172,13 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
191 } else { 172 } else {
192 volatile unsigned long *a = addr; 173 volatile unsigned long *a = addr;
193 unsigned long mask; 174 unsigned long mask;
194 __bi_flags; 175 unsigned long flags;
195 176
196 a += nr >> SZLONG_LOG; 177 a += nr >> SZLONG_LOG;
197 mask = 1UL << (nr & SZLONG_MASK); 178 mask = 1UL << (nr & SZLONG_MASK);
198 __bi_local_irq_save(flags); 179 local_irq_save(flags);
199 *a ^= mask; 180 *a ^= mask;
200 __bi_local_irq_restore(flags); 181 local_irq_restore(flags);
201 } 182 }
202} 183}
203 184
@@ -258,14 +239,14 @@ static inline int test_and_set_bit(unsigned long nr,
258 volatile unsigned long *a = addr; 239 volatile unsigned long *a = addr;
259 unsigned long mask; 240 unsigned long mask;
260 int retval; 241 int retval;
261 __bi_flags; 242 unsigned long flags;
262 243
263 a += nr >> SZLONG_LOG; 244 a += nr >> SZLONG_LOG;
264 mask = 1UL << (nr & SZLONG_MASK); 245 mask = 1UL << (nr & SZLONG_MASK);
265 __bi_local_irq_save(flags); 246 local_irq_save(flags);
266 retval = (mask & *a) != 0; 247 retval = (mask & *a) != 0;
267 *a |= mask; 248 *a |= mask;
268 __bi_local_irq_restore(flags); 249 local_irq_restore(flags);
269 250
270 return retval; 251 return retval;
271 } 252 }
@@ -330,14 +311,14 @@ static inline int test_and_clear_bit(unsigned long nr,
330 volatile unsigned long *a = addr; 311 volatile unsigned long *a = addr;
331 unsigned long mask; 312 unsigned long mask;
332 int retval; 313 int retval;
333 __bi_flags; 314 unsigned long flags;
334 315
335 a += nr >> SZLONG_LOG; 316 a += nr >> SZLONG_LOG;
336 mask = 1UL << (nr & SZLONG_MASK); 317 mask = 1UL << (nr & SZLONG_MASK);
337 __bi_local_irq_save(flags); 318 local_irq_save(flags);
338 retval = (mask & *a) != 0; 319 retval = (mask & *a) != 0;
339 *a &= ~mask; 320 *a &= ~mask;
340 __bi_local_irq_restore(flags); 321 local_irq_restore(flags);
341 322
342 return retval; 323 return retval;
343 } 324 }
@@ -399,23 +380,19 @@ static inline int test_and_change_bit(unsigned long nr,
399 } else { 380 } else {
400 volatile unsigned long *a = addr; 381 volatile unsigned long *a = addr;
401 unsigned long mask, retval; 382 unsigned long mask, retval;
402 __bi_flags; 383 unsigned long flags;
403 384
404 a += nr >> SZLONG_LOG; 385 a += nr >> SZLONG_LOG;
405 mask = 1UL << (nr & SZLONG_MASK); 386 mask = 1UL << (nr & SZLONG_MASK);
406 __bi_local_irq_save(flags); 387 local_irq_save(flags);
407 retval = (mask & *a) != 0; 388 retval = (mask & *a) != 0;
408 *a ^= mask; 389 *a ^= mask;
409 __bi_local_irq_restore(flags); 390 local_irq_restore(flags);
410 391
411 return retval; 392 return retval;
412 } 393 }
413} 394}
414 395
415#undef __bi_flags
416#undef __bi_local_irq_save
417#undef __bi_local_irq_restore
418
419#include <asm-generic/bitops/non-atomic.h> 396#include <asm-generic/bitops/non-atomic.h>
420 397
421/* 398/*
diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h
index 7b4739dc8f3f..4d560a533940 100644
--- a/include/asm-mips/bug.h
+++ b/include/asm-mips/bug.h
@@ -1,6 +1,7 @@
1#ifndef __ASM_BUG_H 1#ifndef __ASM_BUG_H
2#define __ASM_BUG_H 2#define __ASM_BUG_H
3 3
4#include <asm/sgidefs.h>
4 5
5#ifdef CONFIG_BUG 6#ifdef CONFIG_BUG
6 7
@@ -13,6 +14,17 @@ do { \
13 14
14#define HAVE_ARCH_BUG 15#define HAVE_ARCH_BUG
15 16
17#if (_MIPS_ISA > _MIPS_ISA_MIPS1)
18
19#define BUG_ON(condition) \
20do { \
21 __asm__ __volatile__("tne $0, %0" : : "r" (condition)); \
22} while (0)
23
24#define HAVE_ARCH_BUG_ON
25
26#endif /* _MIPS_ISA > _MIPS_ISA_MIPS1 */
27
16#endif 28#endif
17 29
18#include <asm-generic/bug.h> 30#include <asm-generic/bug.h>
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index a2f0c8ea9160..610d0cdeaa9e 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -22,12 +22,12 @@
22 * Descriptor for a cache 22 * Descriptor for a cache
23 */ 23 */
24struct cache_desc { 24struct cache_desc {
25 unsigned short linesz; /* Size of line in bytes */
26 unsigned short ways; /* Number of ways */
27 unsigned short sets; /* Number of lines per set */
28 unsigned int waysize; /* Bytes per way */ 25 unsigned int waysize; /* Bytes per way */
29 unsigned int waybit; /* Bits to select in a cache set */ 26 unsigned short sets; /* Number of lines per set */
30 unsigned int flags; /* Flags describing cache properties */ 27 unsigned char ways; /* Number of ways */
28 unsigned char linesz; /* Size of line in bytes */
29 unsigned char waybit; /* Bits to select in a cache set */
30 unsigned char flags; /* Flags describing cache properties */
31}; 31};
32 32
33/* 33/*
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
index 8319ad77b250..93430b5f4724 100644
--- a/include/asm-mips/dec/kn02.h
+++ b/include/asm-mips/dec/kn02.h
@@ -82,11 +82,9 @@
82 82
83#ifndef __ASSEMBLY__ 83#ifndef __ASSEMBLY__
84 84
85#include <linux/spinlock.h>
86#include <linux/types.h> 85#include <linux/types.h>
87 86
88extern u32 cached_kn02_csr; 87extern u32 cached_kn02_csr;
89extern spinlock_t kn02_lock;
90extern void init_kn02_irqs(int base); 88extern void init_kn02_irqs(int base);
91#endif 89#endif
92 90
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
index e85849ac165f..23f789c80845 100644
--- a/include/asm-mips/dma.h
+++ b/include/asm-mips/dma.h
@@ -74,7 +74,9 @@
74 * 74 *
75 */ 75 */
76 76
77#ifndef GENERIC_ISA_DMA_SUPPORT_BROKEN
77#define MAX_DMA_CHANNELS 8 78#define MAX_DMA_CHANNELS 8
79#endif
78 80
79/* 81/*
80 * The maximum address in KSEG0 that we can perform a DMA transfer to on this 82 * The maximum address in KSEG0 that we can perform a DMA transfer to on this
diff --git a/include/asm-mips/gt64120.h b/include/asm-mips/gt64120.h
index 2edd171bb6cd..4bf8e28f8850 100644
--- a/include/asm-mips/gt64120.h
+++ b/include/asm-mips/gt64120.h
@@ -451,6 +451,13 @@
451#define GT_SDRAM_OPMODE_OP_MODE 3 451#define GT_SDRAM_OPMODE_OP_MODE 3
452#define GT_SDRAM_OPMODE_OP_CBR 4 452#define GT_SDRAM_OPMODE_OP_CBR 4
453 453
454#define GT_TC_CONTROL_ENTC0_SHF 0
455#define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
456#define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK
457#define GT_TC_CONTROL_SELTC0_SHF 1
458#define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
459#define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK
460
454 461
455#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 462#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
456#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) 463#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
@@ -523,6 +530,13 @@
523#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) 530#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
524#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK 531#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
525 532
533#define GT_INTR_T0EXP_SHF 8
534#define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF)
535#define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK
536#define GT_INTR_RETRYCTR0_SHF 20
537#define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF)
538#define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK
539
526/* 540/*
527 * Misc 541 * Misc
528 */ 542 */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index bc5f3c53155f..d77b657c09c7 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -113,7 +113,7 @@ static inline void set_io_port_base(unsigned long base)
113 * almost all conceivable cases a device driver should not be using 113 * almost all conceivable cases a device driver should not be using
114 * this function 114 * this function
115 */ 115 */
116static inline unsigned long virt_to_phys(volatile void * address) 116static inline unsigned long virt_to_phys(volatile const void *address)
117{ 117{
118 return (unsigned long)address - PAGE_OFFSET; 118 return (unsigned long)address - PAGE_OFFSET;
119} 119}
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 35a05ca5560c..67657089efa7 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -24,8 +24,6 @@ static inline int irq_canonicalize(int irq)
24#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ 24#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
25#endif 25#endif
26 26
27extern asmlinkage unsigned int do_IRQ(unsigned int irq);
28
29#ifdef CONFIG_MIPS_MT_SMTC 27#ifdef CONFIG_MIPS_MT_SMTC
30/* 28/*
31 * Clear interrupt mask handling "backstop" if irq_hwmask 29 * Clear interrupt mask handling "backstop" if irq_hwmask
@@ -43,8 +41,6 @@ do { \
43#define __DO_IRQ_SMTC_HOOK() do { } while (0) 41#define __DO_IRQ_SMTC_HOOK() do { } while (0)
44#endif 42#endif
45 43
46#ifdef CONFIG_PREEMPT
47
48/* 44/*
49 * do_IRQ handles all normal device IRQ's (the special 45 * do_IRQ handles all normal device IRQ's (the special
50 * SMP cross-CPU interrupts have their own specific 46 * SMP cross-CPU interrupts have their own specific
@@ -57,12 +53,10 @@ do { \
57do { \ 53do { \
58 irq_enter(); \ 54 irq_enter(); \
59 __DO_IRQ_SMTC_HOOK(); \ 55 __DO_IRQ_SMTC_HOOK(); \
60 __do_IRQ((irq)); \ 56 generic_handle_irq(irq); \
61 irq_exit(); \ 57 irq_exit(); \
62} while (0) 58} while (0)
63 59
64#endif
65
66extern void arch_init_irq(void); 60extern void arch_init_irq(void);
67extern void spurious_interrupt(void); 61extern void spurious_interrupt(void);
68 62
diff --git a/include/asm-mips/kexec.h b/include/asm-mips/kexec.h
new file mode 100644
index 000000000000..b25267ebcb09
--- /dev/null
+++ b/include/asm-mips/kexec.h
@@ -0,0 +1,32 @@
1/*
2 * kexec.h for kexec
3 * Created by <nschichan@corp.free.fr> on Thu Oct 12 14:59:34 2006
4 *
5 * This source code is licensed under the GNU General Public License,
6 * Version 2. See the file COPYING for more details.
7 */
8
9#ifndef _MIPS_KEXEC
10# define _MIPS_KEXEC
11
12/* Maximum physical address we can use pages from */
13#define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000)
14/* Maximum address we can reach in physical address mode */
15#define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000)
16 /* Maximum address we can use for the control code buffer */
17#define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000)
18
19#define KEXEC_CONTROL_CODE_SIZE 4096
20
21/* The native architecture */
22#define KEXEC_ARCH KEXEC_ARCH_MIPS
23
24#define MAX_NOTE_BYTES 1024
25
26static inline void crash_setup_regs(struct pt_regs *newregs,
27 struct pt_regs *oldregs)
28{
29 /* Dummy implementation for now */
30}
31
32#endif /* !_MIPS_KEXEC */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index b3c5ecbec03c..00b0fc68d5cb 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -67,34 +67,9 @@
67#define COBALT_BRD_ID_QUBE2 0x5 67#define COBALT_BRD_ID_QUBE2 0x5
68#define COBALT_BRD_ID_RAQ2 0x6 68#define COBALT_BRD_ID_RAQ2 0x6
69 69
70/*
71 * Galileo chipset access macros for the Cobalt. The base address for
72 * the GT64111 chip is 0x14000000
73 *
74 * Most of this really should go into a separate GT64111 header file.
75 */
76#define GT64111_IO_BASE 0x10000000UL
77#define GT64111_IO_END 0x11ffffffUL
78#define GT64111_MEM_BASE 0x12000000UL
79#define GT64111_MEM_END 0x13ffffffUL
80#define GT64111_BASE 0x14000000UL
81#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
82
83#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port))
84#define GALILEO_OUTL(val, port) \
85do { \
86 *(volatile unsigned int *) GALILEO_REG(port) = (val); \
87} while (0)
88
89#define GALILEO_INTR_T0EXP (1 << 8)
90#define GALILEO_INTR_RETRY_CTR (1 << 20)
91
92#define GALILEO_ENTC0 0x01
93#define GALILEO_SELTC0 0x02
94
95#define PCI_CFG_SET(devfn,where) \ 70#define PCI_CFG_SET(devfn,where) \
96 GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ 71 GT_WRITE(GT_PCI0_CFGADDR_OFS, (0x80000000 | (PCI_SLOT (devfn) << 11) | \
97 (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS) 72 (PCI_FUNC (devfn) << 8) | (where)))
98 73
99#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) 74#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
100# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ 75# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */
diff --git a/include/asm-mips/mach-cobalt/mach-gt64120.h b/include/asm-mips/mach-cobalt/mach-gt64120.h
index 587fc4378f44..ae9c5523c7ef 100644
--- a/include/asm-mips/mach-cobalt/mach-gt64120.h
+++ b/include/asm-mips/mach-cobalt/mach-gt64120.h
@@ -1 +1,27 @@
1/* there's something here ... in the dark */ 1/*
2 * Copyright (C) 2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef _COBALT_MACH_GT64120_H
19#define _COBALT_MACH_GT64120_H
20
21/*
22 * Cobalt uses GT64111. GT64111 is almost the same as GT64120.
23 */
24
25#define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)
26
27#endif /* _COBALT_MACH_GT64120_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 1f318d707998..9985cb7c16e7 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -545,62 +545,6 @@
545#define MIPS_FPIR_L (_ULCAST_(1) << 21) 545#define MIPS_FPIR_L (_ULCAST_(1) << 21)
546#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 546#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
547 547
548/*
549 * R10000 performance counter definitions.
550 *
551 * FIXME: The R10000 performance counter opens a nice way to implement CPU
552 * time accounting with a precission of one cycle. I don't have
553 * R10000 silicon but just a manual, so ...
554 */
555
556/*
557 * Events counted by counter #0
558 */
559#define CE0_CYCLES 0
560#define CE0_INSN_ISSUED 1
561#define CE0_LPSC_ISSUED 2
562#define CE0_S_ISSUED 3
563#define CE0_SC_ISSUED 4
564#define CE0_SC_FAILED 5
565#define CE0_BRANCH_DECODED 6
566#define CE0_QW_WB_SECONDARY 7
567#define CE0_CORRECTED_ECC_ERRORS 8
568#define CE0_ICACHE_MISSES 9
569#define CE0_SCACHE_I_MISSES 10
570#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
571#define CE0_EXT_INTERVENTIONS_REQ 12
572#define CE0_EXT_INVALIDATE_REQ 13
573#define CE0_VIRTUAL_COHERENCY_COND 14
574#define CE0_INSN_GRADUATED 15
575
576/*
577 * Events counted by counter #1
578 */
579#define CE1_CYCLES 0
580#define CE1_INSN_GRADUATED 1
581#define CE1_LPSC_GRADUATED 2
582#define CE1_S_GRADUATED 3
583#define CE1_SC_GRADUATED 4
584#define CE1_FP_INSN_GRADUATED 5
585#define CE1_QW_WB_PRIMARY 6
586#define CE1_TLB_REFILL 7
587#define CE1_BRANCH_MISSPREDICTED 8
588#define CE1_DCACHE_MISS 9
589#define CE1_SCACHE_D_MISSES 10
590#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
591#define CE1_EXT_INTERVENTION_HITS 12
592#define CE1_EXT_INVALIDATE_REQ 13
593#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
594#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
595
596/*
597 * These flags define in which privilege mode the counters count events
598 */
599#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
600#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
601#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
602#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
603
604#ifndef __ASSEMBLY__ 548#ifndef __ASSEMBLY__
605 549
606/* 550/*
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 85b258ee7090..0dc1a45c27ed 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -34,7 +34,9 @@
34 34
35#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
36 36
37#include <linux/pfn.h>
37#include <asm/cpu-features.h> 38#include <asm/cpu-features.h>
39#include <asm/io.h>
38 40
39extern void clear_page(void * page); 41extern void clear_page(void * page);
40extern void copy_page(void * to, void * from); 42extern void copy_page(void * to, void * from);
@@ -134,8 +136,14 @@ typedef struct { unsigned long pgprot; } pgprot_t;
134/* to align the pointer to the (next) page boundary */ 136/* to align the pointer to the (next) page boundary */
135#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) 137#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
136 138
137#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) 139#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
138#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) 140#define __pa_page_offset(x) ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0)
141#else
142#define __pa_page_offset(x) PAGE_OFFSET
143#endif
144#define __pa(x) ((unsigned long)(x) - __pa_page_offset(x))
145#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0))
146#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
139 147
140#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) 148#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
141 149
@@ -160,8 +168,8 @@ typedef struct { unsigned long pgprot; } pgprot_t;
160 168
161#endif 169#endif
162 170
163#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) 171#define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys(kaddr)))
164#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) 172#define virt_addr_valid(kaddr) pfn_valid(PFN_DOWN(virt_to_phys(kaddr)))
165 173
166#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ 174#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
167 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) 175 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index 7e7320300aa3..b9b1e86493ee 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -14,6 +14,7 @@
14#include <asm/addrspace.h> 14#include <asm/addrspace.h>
15#include <asm/page.h> 15#include <asm/page.h>
16#include <asm/cachectl.h> 16#include <asm/cachectl.h>
17#include <asm/fixmap.h>
17 18
18#include <asm-generic/pgtable-nopud.h> 19#include <asm-generic/pgtable-nopud.h>
19 20
@@ -103,6 +104,13 @@
103#define VMALLOC_START MAP_BASE 104#define VMALLOC_START MAP_BASE
104#define VMALLOC_END \ 105#define VMALLOC_END \
105 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) 106 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
107#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64) && \
108 VMALLOC_START != CKSSEG
109/* Load modules into 32bit-compatible segment. */
110#define MODULE_START CKSSEG
111#define MODULE_END (FIXADDR_START-2*PAGE_SIZE)
112extern pgd_t module_pg_dir[PTRS_PER_PGD];
113#endif
106 114
107#define pte_ERROR(e) \ 115#define pte_ERROR(e) \
108 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 116 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
@@ -174,7 +182,12 @@ static inline void pud_clear(pud_t *pudp)
174#define __pmd_offset(address) pmd_index(address) 182#define __pmd_offset(address) pmd_index(address)
175 183
176/* to find an entry in a kernel page-table-directory */ 184/* to find an entry in a kernel page-table-directory */
185#ifdef MODULE_START
186#define pgd_offset_k(address) \
187 ((address) >= MODULE_START ? module_pg_dir : pgd_offset(&init_mm, 0UL))
188#else
177#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL) 189#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL)
190#endif
178 191
179#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 192#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
180#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 193#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 1ca4d1e185c7..f2e1325fec6c 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -67,7 +67,7 @@ extern unsigned long empty_zero_page;
67extern unsigned long zero_page_mask; 67extern unsigned long zero_page_mask;
68 68
69#define ZERO_PAGE(vaddr) \ 69#define ZERO_PAGE(vaddr) \
70 (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))) 70 (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
71 71
72#define __HAVE_ARCH_MOVE_PTE 72#define __HAVE_ARCH_MOVE_PTE
73#define move_pte(pte, prot, old_addr, new_addr) \ 73#define move_pte(pte, prot, old_addr, new_addr) \
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 5f3a9075cd28..30bf555faeaa 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -80,8 +80,6 @@ struct pt_regs {
80#define instruction_pointer(regs) ((regs)->cp0_epc) 80#define instruction_pointer(regs) ((regs)->cp0_epc)
81#define profile_pc(regs) instruction_pointer(regs) 81#define profile_pc(regs) instruction_pointer(regs)
82 82
83extern void show_regs(struct pt_regs *);
84
85extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit); 83extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
86 84
87#endif 85#endif
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index 625acd337bc3..a632cef830a2 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -21,6 +21,7 @@
21#include <linux/ptrace.h> 21#include <linux/ptrace.h>
22#include <linux/rtc.h> 22#include <linux/rtc.h>
23#include <linux/spinlock.h> 23#include <linux/spinlock.h>
24#include <linux/clocksource.h>
24 25
25extern spinlock_t rtc_lock; 26extern spinlock_t rtc_lock;
26 27
@@ -44,12 +45,10 @@ extern int (*mips_timer_state)(void);
44extern void (*mips_timer_ack)(void); 45extern void (*mips_timer_ack)(void);
45 46
46/* 47/*
47 * High precision timer functions. 48 * High precision timer clocksource.
48 * If mips_hpt_read is NULL, an R4k-compatible timer setup is attempted. 49 * If .read is NULL, an R4k-compatible timer setup is attempted.
49 */ 50 */
50extern unsigned int (*mips_hpt_read)(void); 51extern struct clocksource clocksource_mips;
51extern void (*mips_hpt_init)(void);
52extern unsigned int mips_hpt_mask;
53 52
54/* 53/*
55 * to_tm() converts system time back to (year, mon, day, hour, min, sec). 54 * to_tm() converts system time back to (year, mon, day, hour, min, sec).
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index 6427949ddf99..a4ede62b339d 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -122,6 +122,8 @@ extern struct kimage *kexec_crash_image;
122#define KEXEC_ARCH_IA_64 (50 << 16) 122#define KEXEC_ARCH_IA_64 (50 << 16)
123#define KEXEC_ARCH_S390 (22 << 16) 123#define KEXEC_ARCH_S390 (22 << 16)
124#define KEXEC_ARCH_SH (42 << 16) 124#define KEXEC_ARCH_SH (42 << 16)
125#define KEXEC_ARCH_MIPS_LE (10 << 16)
126#define KEXEC_ARCH_MIPS ( 8 << 16)
125 127
126#define KEXEC_FLAGS (KEXEC_ON_CRASH) /* List of defined/legal kexec flags */ 128#define KEXEC_FLAGS (KEXEC_ON_CRASH) /* List of defined/legal kexec flags */
127 129
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 22:28:59 -0500