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-rw-r--r--include/asm-alpha/pci.h13
-rw-r--r--include/asm-arm/arch-pxa/hardware.h18
-rw-r--r--include/asm-arm/arch-pxa/i2c.h70
-rw-r--r--include/asm-arm/arch-pxa/mmc.h1
-rw-r--r--include/asm-arm/arch-sa1100/hardware.h18
-rw-r--r--include/asm-arm/cacheflush.h7
-rw-r--r--include/asm-arm/pci.h13
-rw-r--r--include/asm-generic/pci.h13
-rw-r--r--include/asm-ia64/pci.h13
-rw-r--r--include/asm-parisc/pci.h13
-rw-r--r--include/asm-ppc/pci.h13
-rw-r--r--include/asm-ppc64/pci.h13
-rw-r--r--include/asm-sparc64/pci.h2
-rw-r--r--include/asm-sparc64/system.h49
-rw-r--r--include/linux/i2c-pxa.h48
-rw-r--r--include/linux/in6.h36
-rw-r--r--include/linux/ipv6.h15
-rw-r--r--include/linux/mempolicy.h1
-rw-r--r--include/linux/mmc/host.h10
-rw-r--r--include/linux/pci.h511
-rw-r--r--include/linux/pci_regs.h448
-rw-r--r--include/linux/serial_8250.h15
-rw-r--r--include/linux/serial_core.h3
-rw-r--r--include/linux/skbuff.h2
-rw-r--r--include/net/ax25.h2
-rw-r--r--include/net/compat.h5
-rw-r--r--include/net/ipv6.h5
-rw-r--r--include/net/transp_v6.h2
28 files changed, 831 insertions, 528 deletions
diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h
index f681e675b823..4e115f368d5f 100644
--- a/include/asm-alpha/pci.h
+++ b/include/asm-alpha/pci.h
@@ -254,6 +254,19 @@ extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
254extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 254extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
255 struct pci_bus_region *region); 255 struct pci_bus_region *region);
256 256
257static inline struct resource *
258pcibios_select_root(struct pci_dev *pdev, struct resource *res)
259{
260 struct resource *root = NULL;
261
262 if (res->flags & IORESOURCE_IO)
263 root = &ioport_resource;
264 if (res->flags & IORESOURCE_MEM)
265 root = &iomem_resource;
266
267 return root;
268}
269
257#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index 270#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
258 271
259static inline int pci_proc_domain(struct pci_bus *bus) 272static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index 72b04d846a23..cf35721cfa45 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -44,24 +44,12 @@
44 44
45#ifndef __ASSEMBLY__ 45#ifndef __ASSEMBLY__
46 46
47#if 0 47# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
48# define __REG(x) (*((volatile u32 *)io_p2v(x)))
49#else
50/*
51 * This __REG() version gives the same results as the one above, except
52 * that we are fooling gcc somehow so it generates far better and smaller
53 * assembly code for access to contigous registers. It's a shame that gcc
54 * doesn't guess this by itself.
55 */
56#include <asm/types.h>
57typedef struct { volatile u32 offset[4096]; } __regbase;
58# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
59# define __REG(x) __REGP(io_p2v(x))
60#endif
61 48
62/* With indexed regs we don't want to feed the index through io_p2v() 49/* With indexed regs we don't want to feed the index through io_p2v()
63 especially if it is a variable, otherwise horrible code will result. */ 50 especially if it is a variable, otherwise horrible code will result. */
64# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) 51# define __REG2(x,y) \
52 (*(volatile unsigned long *)((unsigned long)&__REG(x) + (y)))
65 53
66# define __PREG(x) (io_v2p((u32)&(x))) 54# define __PREG(x) (io_v2p((u32)&(x)))
67 55
diff --git a/include/asm-arm/arch-pxa/i2c.h b/include/asm-arm/arch-pxa/i2c.h
new file mode 100644
index 000000000000..46ec2243974a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/i2c.h
@@ -0,0 +1,70 @@
1/*
2 * i2c_pxa.h
3 *
4 * Copyright (C) 2002 Intrinsyc Software Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#ifndef _I2C_PXA_H_
12#define _I2C_PXA_H_
13
14#if 0
15#define DEF_TIMEOUT 3
16#else
17/* need a longer timeout if we're dealing with the fact we may well be
18 * looking at a multi-master environment
19*/
20#define DEF_TIMEOUT 32
21#endif
22
23#define BUS_ERROR (-EREMOTEIO)
24#define XFER_NAKED (-ECONNREFUSED)
25#define I2C_RETRY (-2000) /* an error has occurred retry transmit */
26
27/* ICR initialize bit values
28*
29* 15. FM 0 (100 Khz operation)
30* 14. UR 0 (No unit reset)
31* 13. SADIE 0 (Disables the unit from interrupting on slave addresses
32* matching its slave address)
33* 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration
34* in master mode)
35* 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
36* 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
37* 9. IRFIE 1 (Enable interrupts from full buffer received)
38* 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
39* 7. GCD 1 (Disables i2c unit response to general call messages as a slave)
40* 6. IUE 0 (Disable unit until we change settings)
41* 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
42* 4. MA 0 (Only send stop with the ICR stop bit)
43* 3. TB 0 (We are not transmitting a byte initially)
44* 2. ACKNAK 0 (Send an ACK after the unit receives a byte)
45* 1. STOP 0 (Do not send a STOP)
46* 0. START 0 (Do not send a START)
47*
48*/
49#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
50
51/* I2C status register init values
52 *
53 * 10. BED 1 (Clear bus error detected)
54 * 9. SAD 1 (Clear slave address detected)
55 * 7. IRF 1 (Clear IDBR Receive Full)
56 * 6. ITE 1 (Clear IDBR Transmit Empty)
57 * 5. ALD 1 (Clear Arbitration Loss Detected)
58 * 4. SSD 1 (Clear Slave Stop Detected)
59 */
60#define I2C_ISR_INIT 0x7FF /* status register init */
61
62struct i2c_slave_client;
63
64struct i2c_pxa_platform_data {
65 unsigned int slave_addr;
66 struct i2c_slave_client *slave;
67};
68
69extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
70#endif
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
index 9718063a2119..88c17dd02ed2 100644
--- a/include/asm-arm/arch-pxa/mmc.h
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -9,6 +9,7 @@ struct mmc_host;
9 9
10struct pxamci_platform_data { 10struct pxamci_platform_data {
11 unsigned int ocr_mask; /* available voltages */ 11 unsigned int ocr_mask; /* available voltages */
12 unsigned long detect_delay; /* delay in jiffies before detecting cards after interrupt */
12 int (*init)(struct device *, irqreturn_t (*)(int, void *, struct pt_regs *), void *); 13 int (*init)(struct device *, irqreturn_t (*)(int, void *, struct pt_regs *), void *);
13 int (*get_ro)(struct device *); 14 int (*get_ro)(struct device *);
14 void (*setpower)(struct device *, unsigned int); 15 void (*setpower)(struct device *, unsigned int);
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
index 10c62db34362..19c3b1e186bb 100644
--- a/include/asm-arm/arch-sa1100/hardware.h
+++ b/include/asm-arm/arch-sa1100/hardware.h
@@ -49,23 +49,9 @@
49 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) 49 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
50 50
51#ifndef __ASSEMBLY__ 51#ifndef __ASSEMBLY__
52#include <asm/types.h>
53 52
54#if 0 53# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
55# define __REG(x) (*((volatile u32 *)io_p2v(x))) 54# define __PREG(x) (io_v2p((unsigned long)&(x)))
56#else
57/*
58 * This __REG() version gives the same results as the one above, except
59 * that we are fooling gcc somehow so it generates far better and smaller
60 * assembly code for access to contigous registers. It's a shame that gcc
61 * doesn't guess this by itself.
62 */
63typedef struct { volatile u32 offset[4096]; } __regbase;
64# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
65# define __REG(x) __REGP(io_p2v(x))
66#endif
67
68# define __PREG(x) (io_v2p((u32)&(x)))
69 55
70#else 56#else
71 57
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 035cdcff43d2..e81baff4f54b 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -256,7 +256,7 @@ extern void dmac_flush_range(unsigned long, unsigned long);
256 * Convert calls to our calling convention. 256 * Convert calls to our calling convention.
257 */ 257 */
258#define flush_cache_all() __cpuc_flush_kern_all() 258#define flush_cache_all() __cpuc_flush_kern_all()
259 259#ifndef CONFIG_CPU_CACHE_VIPT
260static inline void flush_cache_mm(struct mm_struct *mm) 260static inline void flush_cache_mm(struct mm_struct *mm)
261{ 261{
262 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) 262 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
@@ -279,6 +279,11 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned l
279 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); 279 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
280 } 280 }
281} 281}
282#else
283extern void flush_cache_mm(struct mm_struct *mm);
284extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
285extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
286#endif
282 287
283/* 288/*
284 * flush_cache_user_range is used when we want to ensure that the 289 * flush_cache_user_range is used when we want to ensure that the
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index 38ea5899a580..ead3ced38cb8 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -64,6 +64,19 @@ extern void
64pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 64pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
65 struct pci_bus_region *region); 65 struct pci_bus_region *region);
66 66
67static inline struct resource *
68pcibios_select_root(struct pci_dev *pdev, struct resource *res)
69{
70 struct resource *root = NULL;
71
72 if (res->flags & IORESOURCE_IO)
73 root = &ioport_resource;
74 if (res->flags & IORESOURCE_MEM)
75 root = &iomem_resource;
76
77 return root;
78}
79
67static inline void pcibios_add_platform_entries(struct pci_dev *dev) 80static inline void pcibios_add_platform_entries(struct pci_dev *dev)
68{ 81{
69} 82}
diff --git a/include/asm-generic/pci.h b/include/asm-generic/pci.h
index ee1d8b5d8168..c36a77d3bf44 100644
--- a/include/asm-generic/pci.h
+++ b/include/asm-generic/pci.h
@@ -30,6 +30,19 @@ pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
30 res->end = region->end; 30 res->end = region->end;
31} 31}
32 32
33static inline struct resource *
34pcibios_select_root(struct pci_dev *pdev, struct resource *res)
35{
36 struct resource *root = NULL;
37
38 if (res->flags & IORESOURCE_IO)
39 root = &ioport_resource;
40 if (res->flags & IORESOURCE_MEM)
41 root = &iomem_resource;
42
43 return root;
44}
45
33#define pcibios_scan_all_fns(a, b) 0 46#define pcibios_scan_all_fns(a, b) 0
34 47
35#ifndef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ 48#ifndef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h
index dba9f220be71..ef616fd4cb1b 100644
--- a/include/asm-ia64/pci.h
+++ b/include/asm-ia64/pci.h
@@ -156,6 +156,19 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev,
156extern void pcibios_bus_to_resource(struct pci_dev *dev, 156extern void pcibios_bus_to_resource(struct pci_dev *dev,
157 struct resource *res, struct pci_bus_region *region); 157 struct resource *res, struct pci_bus_region *region);
158 158
159static inline struct resource *
160pcibios_select_root(struct pci_dev *pdev, struct resource *res)
161{
162 struct resource *root = NULL;
163
164 if (res->flags & IORESOURCE_IO)
165 root = &ioport_resource;
166 if (res->flags & IORESOURCE_MEM)
167 root = &iomem_resource;
168
169 return root;
170}
171
159#define pcibios_scan_all_fns(a, b) 0 172#define pcibios_scan_all_fns(a, b) 0
160 173
161#endif /* _ASM_IA64_PCI_H */ 174#endif /* _ASM_IA64_PCI_H */
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
index 98d79a3d54fa..d0b761f690b5 100644
--- a/include/asm-parisc/pci.h
+++ b/include/asm-parisc/pci.h
@@ -257,6 +257,19 @@ extern void
257pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 257pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
258 struct pci_bus_region *region); 258 struct pci_bus_region *region);
259 259
260static inline struct resource *
261pcibios_select_root(struct pci_dev *pdev, struct resource *res)
262{
263 struct resource *root = NULL;
264
265 if (res->flags & IORESOURCE_IO)
266 root = &ioport_resource;
267 if (res->flags & IORESOURCE_MEM)
268 root = &iomem_resource;
269
270 return root;
271}
272
260static inline void pcibios_add_platform_entries(struct pci_dev *dev) 273static inline void pcibios_add_platform_entries(struct pci_dev *dev)
261{ 274{
262} 275}
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index a811e440c978..9dd06cd40096 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -109,6 +109,19 @@ extern void
109pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 109pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
110 struct pci_bus_region *region); 110 struct pci_bus_region *region);
111 111
112static inline struct resource *
113pcibios_select_root(struct pci_dev *pdev, struct resource *res)
114{
115 struct resource *root = NULL;
116
117 if (res->flags & IORESOURCE_IO)
118 root = &ioport_resource;
119 if (res->flags & IORESOURCE_MEM)
120 root = &iomem_resource;
121
122 return root;
123}
124
112extern void pcibios_add_platform_entries(struct pci_dev *dev); 125extern void pcibios_add_platform_entries(struct pci_dev *dev);
113 126
114struct file; 127struct file;
diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h
index 4d057452f59b..a88bbfc26967 100644
--- a/include/asm-ppc64/pci.h
+++ b/include/asm-ppc64/pci.h
@@ -138,6 +138,19 @@ extern void
138pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 138pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
139 struct pci_bus_region *region); 139 struct pci_bus_region *region);
140 140
141static inline struct resource *
142pcibios_select_root(struct pci_dev *pdev, struct resource *res)
143{
144 struct resource *root = NULL;
145
146 if (res->flags & IORESOURCE_IO)
147 root = &ioport_resource;
148 if (res->flags & IORESOURCE_MEM)
149 root = &iomem_resource;
150
151 return root;
152}
153
141extern int 154extern int
142unmap_bus_range(struct pci_bus *bus); 155unmap_bus_range(struct pci_bus *bus);
143 156
diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h
index a4ab0ec7143a..89bd71b1c0d8 100644
--- a/include/asm-sparc64/pci.h
+++ b/include/asm-sparc64/pci.h
@@ -269,6 +269,8 @@ extern void
269pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 269pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
270 struct pci_bus_region *region); 270 struct pci_bus_region *region);
271 271
272extern struct resource *pcibios_select_root(struct pci_dev *, struct resource *);
273
272static inline void pcibios_add_platform_entries(struct pci_dev *dev) 274static inline void pcibios_add_platform_entries(struct pci_dev *dev)
273{ 275{
274} 276}
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index 5e94c05dc2fc..b5417529f6f1 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -28,13 +28,48 @@ enum sparc_cpu {
28#define ARCH_SUN4C_SUN4 0 28#define ARCH_SUN4C_SUN4 0
29#define ARCH_SUN4 0 29#define ARCH_SUN4 0
30 30
31extern void mb(void); 31/* These are here in an effort to more fully work around Spitfire Errata
32extern void rmb(void); 32 * #51. Essentially, if a memory barrier occurs soon after a mispredicted
33extern void wmb(void); 33 * branch, the chip can stop executing instructions until a trap occurs.
34extern void membar_storeload(void); 34 * Therefore, if interrupts are disabled, the chip can hang forever.
35extern void membar_storeload_storestore(void); 35 *
36extern void membar_storeload_loadload(void); 36 * It used to be believed that the memory barrier had to be right in the
37extern void membar_storestore_loadstore(void); 37 * delay slot, but a case has been traced recently wherein the memory barrier
38 * was one instruction after the branch delay slot and the chip still hung.
39 * The offending sequence was the following in sym_wakeup_done() of the
40 * sym53c8xx_2 driver:
41 *
42 * call sym_ccb_from_dsa, 0
43 * movge %icc, 0, %l0
44 * brz,pn %o0, .LL1303
45 * mov %o0, %l2
46 * membar #LoadLoad
47 *
48 * The branch has to be mispredicted for the bug to occur. Therefore, we put
49 * the memory barrier explicitly into a "branch always, predicted taken"
50 * delay slot to avoid the problem case.
51 */
52#define membar_safe(type) \
53do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
54 " membar " type "\n" \
55 "1:\n" \
56 : : : "memory"); \
57} while (0)
58
59#define mb() \
60 membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
61#define rmb() \
62 membar_safe("#LoadLoad")
63#define wmb() \
64 membar_safe("#StoreStore")
65#define membar_storeload() \
66 membar_safe("#StoreLoad")
67#define membar_storeload_storestore() \
68 membar_safe("#StoreLoad | #StoreStore")
69#define membar_storeload_loadload() \
70 membar_safe("#StoreLoad | #LoadLoad")
71#define membar_storestore_loadstore() \
72 membar_safe("#StoreStore | #LoadStore")
38 73
39#endif 74#endif
40 75
diff --git a/include/linux/i2c-pxa.h b/include/linux/i2c-pxa.h
new file mode 100644
index 000000000000..5f3eaf802223
--- /dev/null
+++ b/include/linux/i2c-pxa.h
@@ -0,0 +1,48 @@
1#ifndef _LINUX_I2C_ALGO_PXA_H
2#define _LINUX_I2C_ALGO_PXA_H
3
4struct i2c_eeprom_emu_watcher {
5 void (*write)(void *, unsigned int addr, unsigned char newval);
6};
7
8struct i2c_eeprom_emu_watch {
9 struct list_head node;
10 unsigned int start;
11 unsigned int end;
12 struct i2c_eeprom_emu_watcher *ops;
13 void *data;
14};
15
16#define I2C_EEPROM_EMU_SIZE (256)
17
18struct i2c_eeprom_emu {
19 unsigned int size;
20 unsigned int ptr;
21 unsigned int seen_start;
22 struct list_head watch;
23
24 unsigned char bytes[I2C_EEPROM_EMU_SIZE];
25};
26
27typedef enum i2c_slave_event_e {
28 I2C_SLAVE_EVENT_START_READ,
29 I2C_SLAVE_EVENT_START_WRITE,
30 I2C_SLAVE_EVENT_STOP
31} i2c_slave_event_t;
32
33struct i2c_slave_client {
34 void *data;
35 void (*event)(void *ptr, i2c_slave_event_t event);
36 int (*read) (void *ptr);
37 void (*write)(void *ptr, unsigned int val);
38};
39
40extern int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *, void *data,
41 unsigned int addr, unsigned int size,
42 struct i2c_eeprom_emu_watcher *);
43
44extern void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *, void *data, struct i2c_eeprom_emu_watcher *watcher);
45
46extern struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void);
47
48#endif /* _LINUX_I2C_ALGO_PXA_H */
diff --git a/include/linux/in6.h b/include/linux/in6.h
index dcf5720ffcbb..bd32b79d6295 100644
--- a/include/linux/in6.h
+++ b/include/linux/in6.h
@@ -148,13 +148,13 @@ struct in6_flowlabel_req
148 */ 148 */
149 149
150#define IPV6_ADDRFORM 1 150#define IPV6_ADDRFORM 1
151#define IPV6_PKTINFO 2 151#define IPV6_2292PKTINFO 2
152#define IPV6_HOPOPTS 3 152#define IPV6_2292HOPOPTS 3
153#define IPV6_DSTOPTS 4 153#define IPV6_2292DSTOPTS 4
154#define IPV6_RTHDR 5 154#define IPV6_2292RTHDR 5
155#define IPV6_PKTOPTIONS 6 155#define IPV6_2292PKTOPTIONS 6
156#define IPV6_CHECKSUM 7 156#define IPV6_CHECKSUM 7
157#define IPV6_HOPLIMIT 8 157#define IPV6_2292HOPLIMIT 8
158#define IPV6_NEXTHOP 9 158#define IPV6_NEXTHOP 9
159#define IPV6_AUTHHDR 10 /* obsolete */ 159#define IPV6_AUTHHDR 10 /* obsolete */
160#define IPV6_FLOWINFO 11 160#define IPV6_FLOWINFO 11
@@ -198,4 +198,28 @@ struct in6_flowlabel_req
198 * MCAST_MSFILTER 48 198 * MCAST_MSFILTER 48
199 */ 199 */
200 200
201/* RFC3542 advanced socket options (50-67) */
202#define IPV6_RECVPKTINFO 50
203#define IPV6_PKTINFO 51
204#if 0
205#define IPV6_RECVPATHMTU 52
206#define IPV6_PATHMTU 53
207#define IPV6_DONTFRAG 54
208#define IPV6_USE_MIN_MTU 55
209#endif
210#define IPV6_RECVHOPOPTS 56
211#define IPV6_HOPOPTS 57
212#if 0
213#define IPV6_RECVRTHDRDSTOPTS 58 /* Unused, see net/ipv6/datagram.c */
214#endif
215#define IPV6_RTHDRDSTOPTS 59
216#define IPV6_RECVRTHDR 60
217#define IPV6_RTHDR 61
218#define IPV6_RECVDSTOPTS 62
219#define IPV6_DSTOPTS 63
220#define IPV6_RECVHOPLIMIT 64
221#define IPV6_HOPLIMIT 65
222#define IPV6_RECVTCLASS 66
223#define IPV6_TCLASS 67
224
201#endif 225#endif
diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h
index 3c7dbc6a0a70..6c5f7b39a4b0 100644
--- a/include/linux/ipv6.h
+++ b/include/linux/ipv6.h
@@ -189,6 +189,7 @@ struct inet6_skb_parm {
189 __u16 dst0; 189 __u16 dst0;
190 __u16 srcrt; 190 __u16 srcrt;
191 __u16 dst1; 191 __u16 dst1;
192 __u16 lastopt;
192}; 193};
193 194
194#define IP6CB(skb) ((struct inet6_skb_parm*)((skb)->cb)) 195#define IP6CB(skb) ((struct inet6_skb_parm*)((skb)->cb))
@@ -234,14 +235,20 @@ struct ipv6_pinfo {
234 /* pktoption flags */ 235 /* pktoption flags */
235 union { 236 union {
236 struct { 237 struct {
237 __u8 srcrt:2, 238 __u16 srcrt:2,
239 osrcrt:2,
238 rxinfo:1, 240 rxinfo:1,
241 rxoinfo:1,
239 rxhlim:1, 242 rxhlim:1,
243 rxohlim:1,
240 hopopts:1, 244 hopopts:1,
245 ohopopts:1,
241 dstopts:1, 246 dstopts:1,
242 rxflow:1; 247 odstopts:1,
248 rxflow:1,
249 rxtclass:1;
243 } bits; 250 } bits;
244 __u8 all; 251 __u16 all;
245 } rxopt; 252 } rxopt;
246 253
247 /* sockopt flags */ 254 /* sockopt flags */
@@ -250,6 +257,7 @@ struct ipv6_pinfo {
250 sndflow:1, 257 sndflow:1,
251 pmtudisc:2, 258 pmtudisc:2,
252 ipv6only:1; 259 ipv6only:1;
260 __u8 tclass;
253 261
254 __u32 dst_cookie; 262 __u32 dst_cookie;
255 263
@@ -263,6 +271,7 @@ struct ipv6_pinfo {
263 struct ipv6_txoptions *opt; 271 struct ipv6_txoptions *opt;
264 struct rt6_info *rt; 272 struct rt6_info *rt;
265 int hop_limit; 273 int hop_limit;
274 int tclass;
266 } cork; 275 } cork;
267}; 276};
268 277
diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h
index 94a46f38c532..58385ee1c0ac 100644
--- a/include/linux/mempolicy.h
+++ b/include/linux/mempolicy.h
@@ -155,6 +155,7 @@ struct mempolicy *get_vma_policy(struct task_struct *task,
155 155
156extern void numa_default_policy(void); 156extern void numa_default_policy(void);
157extern void numa_policy_init(void); 157extern void numa_policy_init(void);
158extern struct mempolicy default_policy;
158 159
159#else 160#else
160 161
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 6014160d9c06..c1f021eddffa 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -109,6 +109,8 @@ struct mmc_host {
109 struct mmc_card *card_selected; /* the selected MMC card */ 109 struct mmc_card *card_selected; /* the selected MMC card */
110 110
111 struct work_struct detect; 111 struct work_struct detect;
112
113 unsigned long private[0] ____cacheline_aligned;
112}; 114};
113 115
114extern struct mmc_host *mmc_alloc_host(int extra, struct device *); 116extern struct mmc_host *mmc_alloc_host(int extra, struct device *);
@@ -116,14 +118,18 @@ extern int mmc_add_host(struct mmc_host *);
116extern void mmc_remove_host(struct mmc_host *); 118extern void mmc_remove_host(struct mmc_host *);
117extern void mmc_free_host(struct mmc_host *); 119extern void mmc_free_host(struct mmc_host *);
118 120
119#define mmc_priv(x) ((void *)((x) + 1)) 121static inline void *mmc_priv(struct mmc_host *host)
122{
123 return (void *)host->private;
124}
125
120#define mmc_dev(x) ((x)->dev) 126#define mmc_dev(x) ((x)->dev)
121#define mmc_hostname(x) ((x)->class_dev.class_id) 127#define mmc_hostname(x) ((x)->class_dev.class_id)
122 128
123extern int mmc_suspend_host(struct mmc_host *, pm_message_t); 129extern int mmc_suspend_host(struct mmc_host *, pm_message_t);
124extern int mmc_resume_host(struct mmc_host *); 130extern int mmc_resume_host(struct mmc_host *);
125 131
126extern void mmc_detect_change(struct mmc_host *); 132extern void mmc_detect_change(struct mmc_host *, unsigned long delay);
127extern void mmc_request_done(struct mmc_host *, struct mmc_request *); 133extern void mmc_request_done(struct mmc_host *, struct mmc_request *);
128 134
129#endif 135#endif
diff --git a/include/linux/pci.h b/include/linux/pci.h
index bc4c40000c0d..6caaba0af469 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -19,436 +19,10 @@
19 19
20#include <linux/mod_devicetable.h> 20#include <linux/mod_devicetable.h>
21 21
22/* 22/* Include the pci register defines */
23 * Under PCI, each device has 256 bytes of configuration address space, 23#include <linux/pci_regs.h>
24 * of which the first 64 bytes are standardized as follows:
25 */
26#define PCI_VENDOR_ID 0x00 /* 16 bits */
27#define PCI_DEVICE_ID 0x02 /* 16 bits */
28#define PCI_COMMAND 0x04 /* 16 bits */
29#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
30#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
31#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
32#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
33#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
34#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
35#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
36#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
37#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
38#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
39#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
40
41#define PCI_STATUS 0x06 /* 16 bits */
42#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
43#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
44#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
45#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
46#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
47#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
48#define PCI_STATUS_DEVSEL_FAST 0x000
49#define PCI_STATUS_DEVSEL_MEDIUM 0x200
50#define PCI_STATUS_DEVSEL_SLOW 0x400
51#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
52#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
53#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
54#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
55#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
56
57#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
58 revision */
59#define PCI_REVISION_ID 0x08 /* Revision ID */
60#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
61#define PCI_CLASS_DEVICE 0x0a /* Device class */
62
63#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
64#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
65#define PCI_HEADER_TYPE 0x0e /* 8 bits */
66#define PCI_HEADER_TYPE_NORMAL 0
67#define PCI_HEADER_TYPE_BRIDGE 1
68#define PCI_HEADER_TYPE_CARDBUS 2
69
70#define PCI_BIST 0x0f /* 8 bits */
71#define PCI_BIST_CODE_MASK 0x0f /* Return result */
72#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
73#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
74
75/*
76 * Base addresses specify locations in memory or I/O space.
77 * Decoded size can be determined by writing a value of
78 * 0xffffffff to the register, and reading it back. Only
79 * 1 bits are decoded.
80 */
81#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
82#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
83#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
84#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
85#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
86#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
87#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
88#define PCI_BASE_ADDRESS_SPACE_IO 0x01
89#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
90#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
91#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
92#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
93#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
94#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
95#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
96#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
97/* bit 1 is reserved if address_space = 1 */
98
99/* Header type 0 (normal devices) */
100#define PCI_CARDBUS_CIS 0x28
101#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
102#define PCI_SUBSYSTEM_ID 0x2e
103#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
104#define PCI_ROM_ADDRESS_ENABLE 0x01
105#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
106
107#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
108
109/* 0x35-0x3b are reserved */
110#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
111#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
112#define PCI_MIN_GNT 0x3e /* 8 bits */
113#define PCI_MAX_LAT 0x3f /* 8 bits */
114
115/* Header type 1 (PCI-to-PCI bridges) */
116#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
117#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
118#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
119#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
120#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
121#define PCI_IO_LIMIT 0x1d
122#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
123#define PCI_IO_RANGE_TYPE_16 0x00
124#define PCI_IO_RANGE_TYPE_32 0x01
125#define PCI_IO_RANGE_MASK (~0x0fUL)
126#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
127#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
128#define PCI_MEMORY_LIMIT 0x22
129#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
130#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
131#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
132#define PCI_PREF_MEMORY_LIMIT 0x26
133#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
134#define PCI_PREF_RANGE_TYPE_32 0x00
135#define PCI_PREF_RANGE_TYPE_64 0x01
136#define PCI_PREF_RANGE_MASK (~0x0fUL)
137#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
138#define PCI_PREF_LIMIT_UPPER32 0x2c
139#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
140#define PCI_IO_LIMIT_UPPER16 0x32
141/* 0x34 same as for htype 0 */
142/* 0x35-0x3b is reserved */
143#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
144/* 0x3c-0x3d are same as for htype 0 */
145#define PCI_BRIDGE_CONTROL 0x3e
146#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
147#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
148#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
149#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
150#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
151#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
152#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
153
154/* Header type 2 (CardBus bridges) */
155#define PCI_CB_CAPABILITY_LIST 0x14
156/* 0x15 reserved */
157#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
158#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
159#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
160#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
161#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
162#define PCI_CB_MEMORY_BASE_0 0x1c
163#define PCI_CB_MEMORY_LIMIT_0 0x20
164#define PCI_CB_MEMORY_BASE_1 0x24
165#define PCI_CB_MEMORY_LIMIT_1 0x28
166#define PCI_CB_IO_BASE_0 0x2c
167#define PCI_CB_IO_BASE_0_HI 0x2e
168#define PCI_CB_IO_LIMIT_0 0x30
169#define PCI_CB_IO_LIMIT_0_HI 0x32
170#define PCI_CB_IO_BASE_1 0x34
171#define PCI_CB_IO_BASE_1_HI 0x36
172#define PCI_CB_IO_LIMIT_1 0x38
173#define PCI_CB_IO_LIMIT_1_HI 0x3a
174#define PCI_CB_IO_RANGE_MASK (~0x03UL)
175/* 0x3c-0x3d are same as for htype 0 */
176#define PCI_CB_BRIDGE_CONTROL 0x3e
177#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
178#define PCI_CB_BRIDGE_CTL_SERR 0x02
179#define PCI_CB_BRIDGE_CTL_ISA 0x04
180#define PCI_CB_BRIDGE_CTL_VGA 0x08
181#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
182#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
183#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
184#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
185#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
186#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
187#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
188#define PCI_CB_SUBSYSTEM_ID 0x42
189#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
190/* 0x48-0x7f reserved */
191
192/* Capability lists */
193
194#define PCI_CAP_LIST_ID 0 /* Capability ID */
195#define PCI_CAP_ID_PM 0x01 /* Power Management */
196#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
197#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
198#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
199#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
200#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
201#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
202#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
203#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
204#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
205#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
206#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
207#define PCI_CAP_SIZEOF 4
208
209/* Power Management Registers */
210
211#define PCI_PM_PMC 2 /* PM Capabilities Register */
212#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
213#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
214#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
215#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
216#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
217#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
218#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
219#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
220#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
221#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
222#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
223#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
224#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
225#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
226#define PCI_PM_CTRL 4 /* PM control and status register */
227#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
228#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
229#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
230#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
231#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
232#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
233#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
234#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
235#define PCI_PM_DATA_REGISTER 7 /* (??) */
236#define PCI_PM_SIZEOF 8
237
238/* AGP registers */
239
240#define PCI_AGP_VERSION 2 /* BCD version number */
241#define PCI_AGP_RFU 3 /* Rest of capability flags */
242#define PCI_AGP_STATUS 4 /* Status register */
243#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
244#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
245#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
246#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
247#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
248#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
249#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
250#define PCI_AGP_COMMAND 8 /* Control register */
251#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
252#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
253#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
254#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
255#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
256#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
257#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
258#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
259#define PCI_AGP_SIZEOF 12
260
261/* Vital Product Data */
262
263#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
264#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
265#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
266#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
267
268/* Slot Identification */
269
270#define PCI_SID_ESR 2 /* Expansion Slot Register */
271#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
272#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
273#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
274
275/* Message Signalled Interrupts registers */
276
277#define PCI_MSI_FLAGS 2 /* Various flags */
278#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
279#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
280#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
281#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
282#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
283#define PCI_MSI_RFU 3 /* Rest of capability flags */
284#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
285#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
286#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
287#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
288#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
289
290/* CompactPCI Hotswap Register */
291
292#define PCI_CHSWP_CSR 2 /* Control and Status Register */
293#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
294#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
295#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
296#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
297#define PCI_CHSWP_PI 0x30 /* Programming Interface */
298#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
299#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
300
301/* PCI-X registers */
302
303#define PCI_X_CMD 2 /* Modes & Features */
304#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
305#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
306#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
307#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
308#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
309#define PCI_X_STATUS 4 /* PCI-X capabilities */
310#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
311#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
312#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
313#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
314#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
315#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
316#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
317#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
318#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
319#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
320#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
321#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
322#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
323
324/* PCI Express capability registers */
325
326#define PCI_EXP_FLAGS 2 /* Capabilities register */
327#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
328#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
329#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
330#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
331#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
332#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
333#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
334#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
335#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
336#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
337#define PCI_EXP_DEVCAP 4 /* Device capabilities */
338#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
339#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
340#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
341#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
342#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
343#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
344#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
345#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
346#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
347#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
348#define PCI_EXP_DEVCTL 8 /* Device Control */
349#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
350#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
351#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
352#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
353#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
354#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
355#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
356#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
357#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
358#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
359#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
360#define PCI_EXP_DEVSTA 10 /* Device Status */
361#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
362#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
363#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
364#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
365#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
366#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
367#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
368#define PCI_EXP_LNKCTL 16 /* Link Control */
369#define PCI_EXP_LNKSTA 18 /* Link Status */
370#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
371#define PCI_EXP_SLTCTL 24 /* Slot Control */
372#define PCI_EXP_SLTSTA 26 /* Slot Status */
373#define PCI_EXP_RTCTL 28 /* Root Control */
374#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
375#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
376#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
377#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
378#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
379#define PCI_EXP_RTCAP 30 /* Root Capabilities */
380#define PCI_EXP_RTSTA 32 /* Root Status */
381
382/* Extended Capabilities (PCI-X 2.0 and Express) */
383#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
384#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
385#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
386
387#define PCI_EXT_CAP_ID_ERR 1
388#define PCI_EXT_CAP_ID_VC 2
389#define PCI_EXT_CAP_ID_DSN 3
390#define PCI_EXT_CAP_ID_PWR 4
391
392/* Advanced Error Reporting */
393#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
394#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
395#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
396#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
397#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
398#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
399#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
400#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
401#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
402#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
403#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
404#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
405#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
406 /* Same bits as above */
407#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
408 /* Same bits as above */
409#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
410#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
411#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
412#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
413#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
414#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
415#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
416 /* Same bits as above */
417#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
418#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
419#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
420#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
421#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
422#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
423#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
424#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
425#define PCI_ERR_ROOT_STATUS 48
426#define PCI_ERR_ROOT_COR_SRC 52
427#define PCI_ERR_ROOT_SRC 54
428
429/* Virtual Channel */
430#define PCI_VC_PORT_REG1 4
431#define PCI_VC_PORT_REG2 8
432#define PCI_VC_PORT_CTRL 12
433#define PCI_VC_PORT_STATUS 14
434#define PCI_VC_RES_CAP 16
435#define PCI_VC_RES_CTRL 20
436#define PCI_VC_RES_STATUS 26
437
438/* Power Budgeting */
439#define PCI_PWR_DSR 4 /* Data Select Register */
440#define PCI_PWR_DATA 8 /* Data Register */
441#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
442#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
443#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
444#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
445#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
446#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
447#define PCI_PWR_CAP 12 /* Capability */
448#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
449 24
450/* Include the ID list */ 25/* Include the ID list */
451
452#include <linux/pci_ids.h> 26#include <linux/pci_ids.h>
453 27
454/* 28/*
@@ -496,11 +70,12 @@ enum pci_mmap_state {
496 70
497typedef int __bitwise pci_power_t; 71typedef int __bitwise pci_power_t;
498 72
499#define PCI_D0 ((pci_power_t __force) 0) 73#define PCI_D0 ((pci_power_t __force) 0)
500#define PCI_D1 ((pci_power_t __force) 1) 74#define PCI_D1 ((pci_power_t __force) 1)
501#define PCI_D2 ((pci_power_t __force) 2) 75#define PCI_D2 ((pci_power_t __force) 2)
502#define PCI_D3hot ((pci_power_t __force) 3) 76#define PCI_D3hot ((pci_power_t __force) 3)
503#define PCI_D3cold ((pci_power_t __force) 4) 77#define PCI_D3cold ((pci_power_t __force) 4)
78#define PCI_UNKNOWN ((pci_power_t __force) 5)
504#define PCI_POWER_ERROR ((pci_power_t __force) -1) 79#define PCI_POWER_ERROR ((pci_power_t __force) -1)
505 80
506/* 81/*
@@ -562,11 +137,6 @@ struct pci_dev {
562 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 137 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
563 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 138 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
564 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 139 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
565#ifdef CONFIG_PCI_NAMES
566#define PCI_NAME_SIZE 255
567#define PCI_NAME_HALF __stringify(43) /* less than half to handle slop */
568 char pretty_name[PCI_NAME_SIZE]; /* pretty name for users to see */
569#endif
570}; 140};
571 141
572#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list) 142#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
@@ -582,15 +152,15 @@ struct pci_dev {
582 * 7-10 bridges: address space assigned to buses behind the bridge 152 * 7-10 bridges: address space assigned to buses behind the bridge
583 */ 153 */
584 154
585#define PCI_ROM_RESOURCE 6 155#define PCI_ROM_RESOURCE 6
586#define PCI_BRIDGE_RESOURCES 7 156#define PCI_BRIDGE_RESOURCES 7
587#define PCI_NUM_RESOURCES 11 157#define PCI_NUM_RESOURCES 11
588 158
589#ifndef PCI_BUS_NUM_RESOURCES 159#ifndef PCI_BUS_NUM_RESOURCES
590#define PCI_BUS_NUM_RESOURCES 8 160#define PCI_BUS_NUM_RESOURCES 8
591#endif 161#endif
592 162
593#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 163#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
594 164
595struct pci_bus { 165struct pci_bus {
596 struct list_head node; /* node in list of buses */ 166 struct list_head node; /* node in list of buses */
@@ -699,7 +269,7 @@ struct pci_driver {
699 * @dev_class_mask: the class mask for this device 269 * @dev_class_mask: the class mask for this device
700 * 270 *
701 * This macro is used to create a struct pci_device_id that matches a 271 * This macro is used to create a struct pci_device_id that matches a
702 * specific PCI class. The vendor, device, subvendor, and subdevice 272 * specific PCI class. The vendor, device, subvendor, and subdevice
703 * fields will be set to PCI_ANY_ID. 273 * fields will be set to PCI_ANY_ID.
704 */ 274 */
705#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 275#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
@@ -707,7 +277,7 @@ struct pci_driver {
707 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 277 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
708 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 278 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
709 279
710/* 280/*
711 * pci_module_init is obsolete, this stays here till we fix up all usages of it 281 * pci_module_init is obsolete, this stays here till we fix up all usages of it
712 * in the tree. 282 * in the tree.
713 */ 283 */
@@ -749,8 +319,6 @@ int pci_scan_slot(struct pci_bus *bus, int devfn);
749struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn); 319struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
750unsigned int pci_scan_child_bus(struct pci_bus *bus); 320unsigned int pci_scan_child_bus(struct pci_bus *bus);
751void pci_bus_add_device(struct pci_dev *dev); 321void pci_bus_add_device(struct pci_dev *dev);
752void pci_name_device(struct pci_dev *dev);
753char *pci_class_name(u32 class);
754void pci_read_bridge_bases(struct pci_bus *child); 322void pci_read_bridge_bases(struct pci_bus *child);
755struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res); 323struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
756int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 324int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
@@ -815,9 +383,12 @@ void pci_set_master(struct pci_dev *dev);
815#define HAVE_PCI_SET_MWI 383#define HAVE_PCI_SET_MWI
816int pci_set_mwi(struct pci_dev *dev); 384int pci_set_mwi(struct pci_dev *dev);
817void pci_clear_mwi(struct pci_dev *dev); 385void pci_clear_mwi(struct pci_dev *dev);
386void pci_intx(struct pci_dev *dev, int enable);
818int pci_set_dma_mask(struct pci_dev *dev, u64 mask); 387int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
819int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); 388int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
389void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
820int pci_assign_resource(struct pci_dev *dev, int i); 390int pci_assign_resource(struct pci_dev *dev, int i);
391void pci_restore_bars(struct pci_dev *dev);
821 392
822/* ROM control related routines */ 393/* ROM control related routines */
823void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size); 394void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size);
@@ -865,6 +436,9 @@ const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_
865const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev); 436const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
866int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass); 437int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
867 438
439void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
440 void *userdata);
441
868/* kmem_cache style wrapper around pci_alloc_consistent() */ 442/* kmem_cache style wrapper around pci_alloc_consistent() */
869 443
870#include <linux/dmapool.h> 444#include <linux/dmapool.h>
@@ -912,18 +486,26 @@ extern void pci_disable_msix(struct pci_dev *dev);
912extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); 486extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
913#endif 487#endif
914 488
915#endif /* CONFIG_PCI */ 489/*
916 490 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
917/* Include architecture-dependent settings and functions */ 491 * a PCI domain is defined to be a set of PCI busses which share
492 * configuration space.
493 */
494#ifndef CONFIG_PCI_DOMAINS
495static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
496static inline int pci_proc_domain(struct pci_bus *bus)
497{
498 return 0;
499}
500#endif
918 501
919#include <asm/pci.h> 502#else /* CONFIG_PCI is not enabled */
920 503
921/* 504/*
922 * If the system does not have PCI, clearly these return errors. Define 505 * If the system does not have PCI, clearly these return errors. Define
923 * these as simple inline functions to avoid hair in drivers. 506 * these as simple inline functions to avoid hair in drivers.
924 */ 507 */
925 508
926#ifndef CONFIG_PCI
927#define _PCI_NOP(o,s,t) \ 509#define _PCI_NOP(o,s,t) \
928 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \ 510 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
929 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 511 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
@@ -974,21 +556,11 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int en
974 556
975#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) 557#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
976 558
977#else 559#endif /* CONFIG_PCI */
978 560
979/* 561/* Include architecture-dependent settings and functions */
980 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 562
981 * a PCI domain is defined to be a set of PCI busses which share 563#include <asm/pci.h>
982 * configuration space.
983 */
984#ifndef CONFIG_PCI_DOMAINS
985static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
986static inline int pci_proc_domain(struct pci_bus *bus)
987{
988 return 0;
989}
990#endif
991#endif /* !CONFIG_PCI */
992 564
993/* these helpers provide future and backwards compatibility 565/* these helpers provide future and backwards compatibility
994 * for accessing popular PCI BAR info */ 566 * for accessing popular PCI BAR info */
@@ -1025,13 +597,6 @@ static inline char *pci_name(struct pci_dev *pdev)
1025 return pdev->dev.bus_id; 597 return pdev->dev.bus_id;
1026} 598}
1027 599
1028/* Some archs want to see the pretty pci name, so use this macro */
1029#ifdef CONFIG_PCI_NAMES
1030#define pci_pretty_name(dev) ((dev)->pretty_name)
1031#else
1032#define pci_pretty_name(dev) ""
1033#endif
1034
1035 600
1036/* Some archs don't want to expose struct resource to userland as-is 601/* Some archs don't want to expose struct resource to userland as-is
1037 * in sysfs and /proc 602 * in sysfs and /proc
@@ -1067,7 +632,7 @@ enum pci_fixup_pass {
1067 632
1068/* Anonymous variables would be nice... */ 633/* Anonymous variables would be nice... */
1069#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ 634#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1070 static struct pci_fixup __pci_fixup_##name __attribute_used__ \ 635 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
1071 __attribute__((__section__(#section))) = { vendor, device, hook }; 636 __attribute__((__section__(#section))) = { vendor, device, hook };
1072#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 637#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1073 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 638 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
new file mode 100644
index 000000000000..e2a089b051ed
--- /dev/null
+++ b/include/linux/pci_regs.h
@@ -0,0 +1,448 @@
1/*
2 * pci_regs.h
3 *
4 * PCI standard defines
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_REGS_H
18#define LINUX_PCI_REGS_H
19
20/*
21 * Under PCI, each device has 256 bytes of configuration address space,
22 * of which the first 64 bytes are standardized as follows:
23 */
24#define PCI_VENDOR_ID 0x00 /* 16 bits */
25#define PCI_DEVICE_ID 0x02 /* 16 bits */
26#define PCI_COMMAND 0x04 /* 16 bits */
27#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
28#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
29#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
30#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
31#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
32#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
33#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
34#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
35#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
36#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
37#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
38
39#define PCI_STATUS 0x06 /* 16 bits */
40#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
41#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
42#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
43#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
44#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
45#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
46#define PCI_STATUS_DEVSEL_FAST 0x000
47#define PCI_STATUS_DEVSEL_MEDIUM 0x200
48#define PCI_STATUS_DEVSEL_SLOW 0x400
49#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
50#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
51#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
52#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
53#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
54
55#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
56#define PCI_REVISION_ID 0x08 /* Revision ID */
57#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
58#define PCI_CLASS_DEVICE 0x0a /* Device class */
59
60#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
61#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
62#define PCI_HEADER_TYPE 0x0e /* 8 bits */
63#define PCI_HEADER_TYPE_NORMAL 0
64#define PCI_HEADER_TYPE_BRIDGE 1
65#define PCI_HEADER_TYPE_CARDBUS 2
66
67#define PCI_BIST 0x0f /* 8 bits */
68#define PCI_BIST_CODE_MASK 0x0f /* Return result */
69#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
70#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
71
72/*
73 * Base addresses specify locations in memory or I/O space.
74 * Decoded size can be determined by writing a value of
75 * 0xffffffff to the register, and reading it back. Only
76 * 1 bits are decoded.
77 */
78#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
79#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
80#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
81#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
82#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
83#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
84#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
85#define PCI_BASE_ADDRESS_SPACE_IO 0x01
86#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
87#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
88#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
89#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
90#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
91#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
92#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
93#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
94/* bit 1 is reserved if address_space = 1 */
95
96/* Header type 0 (normal devices) */
97#define PCI_CARDBUS_CIS 0x28
98#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
99#define PCI_SUBSYSTEM_ID 0x2e
100#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
101#define PCI_ROM_ADDRESS_ENABLE 0x01
102#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
103
104#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
105
106/* 0x35-0x3b are reserved */
107#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
108#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
109#define PCI_MIN_GNT 0x3e /* 8 bits */
110#define PCI_MAX_LAT 0x3f /* 8 bits */
111
112/* Header type 1 (PCI-to-PCI bridges) */
113#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
114#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
115#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
116#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
117#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
118#define PCI_IO_LIMIT 0x1d
119#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
120#define PCI_IO_RANGE_TYPE_16 0x00
121#define PCI_IO_RANGE_TYPE_32 0x01
122#define PCI_IO_RANGE_MASK (~0x0fUL)
123#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
124#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
125#define PCI_MEMORY_LIMIT 0x22
126#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
127#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
128#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
129#define PCI_PREF_MEMORY_LIMIT 0x26
130#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
131#define PCI_PREF_RANGE_TYPE_32 0x00
132#define PCI_PREF_RANGE_TYPE_64 0x01
133#define PCI_PREF_RANGE_MASK (~0x0fUL)
134#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
135#define PCI_PREF_LIMIT_UPPER32 0x2c
136#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
137#define PCI_IO_LIMIT_UPPER16 0x32
138/* 0x34 same as for htype 0 */
139/* 0x35-0x3b is reserved */
140#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
141/* 0x3c-0x3d are same as for htype 0 */
142#define PCI_BRIDGE_CONTROL 0x3e
143#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
144#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
145#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
146#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
147#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
148#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
149#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
150
151/* Header type 2 (CardBus bridges) */
152#define PCI_CB_CAPABILITY_LIST 0x14
153/* 0x15 reserved */
154#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
155#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
156#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
157#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
158#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
159#define PCI_CB_MEMORY_BASE_0 0x1c
160#define PCI_CB_MEMORY_LIMIT_0 0x20
161#define PCI_CB_MEMORY_BASE_1 0x24
162#define PCI_CB_MEMORY_LIMIT_1 0x28
163#define PCI_CB_IO_BASE_0 0x2c
164#define PCI_CB_IO_BASE_0_HI 0x2e
165#define PCI_CB_IO_LIMIT_0 0x30
166#define PCI_CB_IO_LIMIT_0_HI 0x32
167#define PCI_CB_IO_BASE_1 0x34
168#define PCI_CB_IO_BASE_1_HI 0x36
169#define PCI_CB_IO_LIMIT_1 0x38
170#define PCI_CB_IO_LIMIT_1_HI 0x3a
171#define PCI_CB_IO_RANGE_MASK (~0x03UL)
172/* 0x3c-0x3d are same as for htype 0 */
173#define PCI_CB_BRIDGE_CONTROL 0x3e
174#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
175#define PCI_CB_BRIDGE_CTL_SERR 0x02
176#define PCI_CB_BRIDGE_CTL_ISA 0x04
177#define PCI_CB_BRIDGE_CTL_VGA 0x08
178#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
179#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
180#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
181#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
182#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
183#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
184#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
185#define PCI_CB_SUBSYSTEM_ID 0x42
186#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
187/* 0x48-0x7f reserved */
188
189/* Capability lists */
190
191#define PCI_CAP_LIST_ID 0 /* Capability ID */
192#define PCI_CAP_ID_PM 0x01 /* Power Management */
193#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
194#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
195#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
196#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
197#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
198#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
199#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
200#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
201#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
202#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
203#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
204#define PCI_CAP_SIZEOF 4
205
206/* Power Management Registers */
207
208#define PCI_PM_PMC 2 /* PM Capabilities Register */
209#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
210#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
211#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
212#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
213#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
214#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
215#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
216#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
217#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
218#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
219#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
220#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
221#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
222#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
223#define PCI_PM_CTRL 4 /* PM control and status register */
224#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
225#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */
226#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
227#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
228#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
229#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
230#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
231#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
232#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
233#define PCI_PM_DATA_REGISTER 7 /* (??) */
234#define PCI_PM_SIZEOF 8
235
236/* AGP registers */
237
238#define PCI_AGP_VERSION 2 /* BCD version number */
239#define PCI_AGP_RFU 3 /* Rest of capability flags */
240#define PCI_AGP_STATUS 4 /* Status register */
241#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
242#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
243#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
244#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
245#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
246#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
247#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
248#define PCI_AGP_COMMAND 8 /* Control register */
249#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
250#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
251#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
252#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
253#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
254#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
255#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
256#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
257#define PCI_AGP_SIZEOF 12
258
259/* Vital Product Data */
260
261#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
262#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
263#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
264#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
265
266/* Slot Identification */
267
268#define PCI_SID_ESR 2 /* Expansion Slot Register */
269#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
270#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
271#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
272
273/* Message Signalled Interrupts registers */
274
275#define PCI_MSI_FLAGS 2 /* Various flags */
276#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
277#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
278#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
279#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
280#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
281#define PCI_MSI_RFU 3 /* Rest of capability flags */
282#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
283#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
284#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
285#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
286#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
287
288/* CompactPCI Hotswap Register */
289
290#define PCI_CHSWP_CSR 2 /* Control and Status Register */
291#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
292#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
293#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
294#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
295#define PCI_CHSWP_PI 0x30 /* Programming Interface */
296#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
297#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
298
299/* PCI-X registers */
300
301#define PCI_X_CMD 2 /* Modes & Features */
302#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
303#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
304#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
305#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
306#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
307#define PCI_X_STATUS 4 /* PCI-X capabilities */
308#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
309#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
310#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
311#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
312#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
313#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
314#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
315#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
316#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
317#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
318#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
319#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
320#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
321
322/* PCI Express capability registers */
323
324#define PCI_EXP_FLAGS 2 /* Capabilities register */
325#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
326#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
327#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
328#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
329#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
330#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
331#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
332#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
333#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
334#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
335#define PCI_EXP_DEVCAP 4 /* Device capabilities */
336#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
337#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
338#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
339#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
340#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
341#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
342#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
343#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
344#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
345#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
346#define PCI_EXP_DEVCTL 8 /* Device Control */
347#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
348#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
349#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
350#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
351#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
352#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
353#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
354#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
355#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
356#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
357#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
358#define PCI_EXP_DEVSTA 10 /* Device Status */
359#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
360#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
361#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
362#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
363#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
364#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
365#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
366#define PCI_EXP_LNKCTL 16 /* Link Control */
367#define PCI_EXP_LNKSTA 18 /* Link Status */
368#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
369#define PCI_EXP_SLTCTL 24 /* Slot Control */
370#define PCI_EXP_SLTSTA 26 /* Slot Status */
371#define PCI_EXP_RTCTL 28 /* Root Control */
372#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
373#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
374#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
375#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
376#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
377#define PCI_EXP_RTCAP 30 /* Root Capabilities */
378#define PCI_EXP_RTSTA 32 /* Root Status */
379
380/* Extended Capabilities (PCI-X 2.0 and Express) */
381#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
382#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
383#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
384
385#define PCI_EXT_CAP_ID_ERR 1
386#define PCI_EXT_CAP_ID_VC 2
387#define PCI_EXT_CAP_ID_DSN 3
388#define PCI_EXT_CAP_ID_PWR 4
389
390/* Advanced Error Reporting */
391#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
392#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
393#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
394#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
395#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
396#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
397#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
398#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
399#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
400#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
401#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
402#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
403#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
404 /* Same bits as above */
405#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
406 /* Same bits as above */
407#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
408#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
409#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
410#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
411#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
412#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
413#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
414 /* Same bits as above */
415#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
416#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
417#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
418#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
419#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
420#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
421#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
422#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
423#define PCI_ERR_ROOT_STATUS 48
424#define PCI_ERR_ROOT_COR_SRC 52
425#define PCI_ERR_ROOT_SRC 54
426
427/* Virtual Channel */
428#define PCI_VC_PORT_REG1 4
429#define PCI_VC_PORT_REG2 8
430#define PCI_VC_PORT_CTRL 12
431#define PCI_VC_PORT_STATUS 14
432#define PCI_VC_RES_CAP 16
433#define PCI_VC_RES_CTRL 20
434#define PCI_VC_RES_STATUS 26
435
436/* Power Budgeting */
437#define PCI_PWR_DSR 4 /* Data Select Register */
438#define PCI_PWR_DATA 8 /* Data Register */
439#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
440#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
441#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
442#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
443#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
444#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
445#define PCI_PWR_CAP 12 /* Capability */
446#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
447
448#endif /* LINUX_PCI_REGS_H */
diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h
index d8a023d804d4..317a979b24de 100644
--- a/include/linux/serial_8250.h
+++ b/include/linux/serial_8250.h
@@ -30,6 +30,21 @@ struct plat_serial8250_port {
30}; 30};
31 31
32/* 32/*
33 * Allocate 8250 platform device IDs. Nothing is implied by
34 * the numbering here, except for the legacy entry being -1.
35 */
36enum {
37 PLAT8250_DEV_LEGACY = -1,
38 PLAT8250_DEV_PLATFORM,
39 PLAT8250_DEV_PLATFORM1,
40 PLAT8250_DEV_FOURPORT,
41 PLAT8250_DEV_ACCENT,
42 PLAT8250_DEV_BOCA,
43 PLAT8250_DEV_HUB6,
44 PLAT8250_DEV_MCA,
45};
46
47/*
33 * This should be used by drivers which want to register 48 * This should be used by drivers which want to register
34 * their own 8250 ports without registering their own 49 * their own 8250 ports without registering their own
35 * platform device. Using these will make your driver 50 * platform device. Using these will make your driver
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 9b12fe731612..27db8da43aa4 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -401,6 +401,9 @@ uart_handle_sysrq_char(struct uart_port *port, unsigned int ch,
401#endif 401#endif
402 return 0; 402 return 0;
403} 403}
404#ifndef SUPPORT_SYSRQ
405#define uart_handle_sysrq_char(port,ch,regs) uart_handle_sysrq_char(port, 0, NULL)
406#endif
404 407
405/* 408/*
406 * We do the SysRQ and SAK checking like this... 409 * We do the SysRQ and SAK checking like this...
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index da7da9c0ed1b..2741c0c55e83 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -1167,7 +1167,7 @@ static inline void skb_postpull_rcsum(struct sk_buff *skb,
1167 1167
1168static inline int pskb_trim_rcsum(struct sk_buff *skb, unsigned int len) 1168static inline int pskb_trim_rcsum(struct sk_buff *skb, unsigned int len)
1169{ 1169{
1170 if (len >= skb->len) 1170 if (likely(len >= skb->len))
1171 return 0; 1171 return 0;
1172 if (skb->ip_summed == CHECKSUM_HW) 1172 if (skb->ip_summed == CHECKSUM_HW)
1173 skb->ip_summed = CHECKSUM_NONE; 1173 skb->ip_summed = CHECKSUM_NONE;
diff --git a/include/net/ax25.h b/include/net/ax25.h
index 364b046e9f47..227d3378decd 100644
--- a/include/net/ax25.h
+++ b/include/net/ax25.h
@@ -258,7 +258,7 @@ extern struct sock *ax25_make_new(struct sock *, struct ax25_dev *);
258/* ax25_addr.c */ 258/* ax25_addr.c */
259extern ax25_address null_ax25_address; 259extern ax25_address null_ax25_address;
260extern char *ax2asc(char *buf, ax25_address *); 260extern char *ax2asc(char *buf, ax25_address *);
261extern ax25_address *asc2ax(char *); 261extern void asc2ax(ax25_address *addr, char *callsign);
262extern int ax25cmp(ax25_address *, ax25_address *); 262extern int ax25cmp(ax25_address *, ax25_address *);
263extern int ax25digicmp(ax25_digi *, ax25_digi *); 263extern int ax25digicmp(ax25_digi *, ax25_digi *);
264extern unsigned char *ax25_addr_parse(unsigned char *, int, ax25_address *, ax25_address *, ax25_digi *, int *, int *); 264extern unsigned char *ax25_addr_parse(unsigned char *, int, ax25_address *, ax25_address *, ax25_digi *, int *, int *);
diff --git a/include/net/compat.h b/include/net/compat.h
index 482eb820f13a..290bab46d457 100644
--- a/include/net/compat.h
+++ b/include/net/compat.h
@@ -33,7 +33,8 @@ extern asmlinkage long compat_sys_sendmsg(int,struct compat_msghdr __user *,unsi
33extern asmlinkage long compat_sys_recvmsg(int,struct compat_msghdr __user *,unsigned); 33extern asmlinkage long compat_sys_recvmsg(int,struct compat_msghdr __user *,unsigned);
34extern asmlinkage long compat_sys_getsockopt(int, int, int, char __user *, int __user *); 34extern asmlinkage long compat_sys_getsockopt(int, int, int, char __user *, int __user *);
35extern int put_cmsg_compat(struct msghdr*, int, int, int, void *); 35extern int put_cmsg_compat(struct msghdr*, int, int, int, void *);
36extern int cmsghdr_from_user_compat_to_kern(struct msghdr *, struct sock *, unsigned char *, 36
37 int); 37struct sock;
38extern int cmsghdr_from_user_compat_to_kern(struct msghdr *, struct sock *, unsigned char *, int);
38 39
39#endif /* NET_COMPAT_H */ 40#endif /* NET_COMPAT_H */
diff --git a/include/net/ipv6.h b/include/net/ipv6.h
index 3203eaff4bd4..65ec86678a08 100644
--- a/include/net/ipv6.h
+++ b/include/net/ipv6.h
@@ -233,6 +233,10 @@ extern int ip6_ra_control(struct sock *sk, int sel,
233extern int ipv6_parse_hopopts(struct sk_buff *skb, int); 233extern int ipv6_parse_hopopts(struct sk_buff *skb, int);
234 234
235extern struct ipv6_txoptions * ipv6_dup_options(struct sock *sk, struct ipv6_txoptions *opt); 235extern struct ipv6_txoptions * ipv6_dup_options(struct sock *sk, struct ipv6_txoptions *opt);
236extern struct ipv6_txoptions * ipv6_renew_options(struct sock *sk, struct ipv6_txoptions *opt,
237 int newtype,
238 struct ipv6_opt_hdr __user *newopt,
239 int newoptlen);
236 240
237extern int ip6_frag_nqueues; 241extern int ip6_frag_nqueues;
238extern atomic_t ip6_frag_mem; 242extern atomic_t ip6_frag_mem;
@@ -373,6 +377,7 @@ extern int ip6_append_data(struct sock *sk,
373 int length, 377 int length,
374 int transhdrlen, 378 int transhdrlen,
375 int hlimit, 379 int hlimit,
380 int tclass,
376 struct ipv6_txoptions *opt, 381 struct ipv6_txoptions *opt,
377 struct flowi *fl, 382 struct flowi *fl,
378 struct rt6_info *rt, 383 struct rt6_info *rt,
diff --git a/include/net/transp_v6.h b/include/net/transp_v6.h
index 8b075ab7a26c..4e86f2de6638 100644
--- a/include/net/transp_v6.h
+++ b/include/net/transp_v6.h
@@ -37,7 +37,7 @@ extern int datagram_recv_ctl(struct sock *sk,
37extern int datagram_send_ctl(struct msghdr *msg, 37extern int datagram_send_ctl(struct msghdr *msg,
38 struct flowi *fl, 38 struct flowi *fl,
39 struct ipv6_txoptions *opt, 39 struct ipv6_txoptions *opt,
40 int *hlimit); 40 int *hlimit, int *tclass);
41 41
42#define LOOPBACK4_IPV6 __constant_htonl(0x7f000006) 42#define LOOPBACK4_IPV6 __constant_htonl(0x7f000006)
43 43
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 21:42:53 -0500