aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/linux/mlx4/cq.h14
-rw-r--r--include/linux/mlx4/qp.h10
2 files changed, 18 insertions, 6 deletions
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h
index 0181e0a57cbf..1243ebace561 100644
--- a/include/linux/mlx4/cq.h
+++ b/include/linux/mlx4/cq.h
@@ -45,11 +45,11 @@ struct mlx4_cqe {
45 u8 sl; 45 u8 sl;
46 u8 reserved1; 46 u8 reserved1;
47 __be16 rlid; 47 __be16 rlid;
48 u32 reserved2; 48 __be32 ipoib_status;
49 __be32 byte_cnt; 49 __be32 byte_cnt;
50 __be16 wqe_index; 50 __be16 wqe_index;
51 __be16 checksum; 51 __be16 checksum;
52 u8 reserved3[3]; 52 u8 reserved2[3];
53 u8 owner_sr_opcode; 53 u8 owner_sr_opcode;
54}; 54};
55 55
@@ -85,6 +85,16 @@ enum {
85 MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22, 85 MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
86}; 86};
87 87
88enum {
89 MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22,
90 MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23,
91 MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24,
92 MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25,
93 MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26,
94 MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27,
95 MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28,
96};
97
88static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd, 98static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
89 void __iomem *uar_page, 99 void __iomem *uar_page,
90 spinlock_t *doorbell_lock) 100 spinlock_t *doorbell_lock)
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index 09a2230923f2..31f9eb3ccbb3 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -158,10 +158,12 @@ struct mlx4_qp_context {
158#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 158#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
159 159
160enum { 160enum {
161 MLX4_WQE_CTRL_NEC = 1 << 29, 161 MLX4_WQE_CTRL_NEC = 1 << 29,
162 MLX4_WQE_CTRL_FENCE = 1 << 6, 162 MLX4_WQE_CTRL_FENCE = 1 << 6,
163 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 163 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
164 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 164 MLX4_WQE_CTRL_SOLICITED = 1 << 1,
165 MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
166 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
165}; 167};
166 168
167struct mlx4_wqe_ctrl_seg { 169struct mlx4_wqe_ctrl_seg {