4 files changed, 407 insertions, 0 deletions

diff --git a/include/linux/amba/pl022.h b/include/linux/amba/pl022.h
new file mode 100644
index 000000000000..dcad0ffd1755
--- /dev/null
+++ b/include/linux/amba/pl022.h
@@ -0,0 +1,264 @@
+/*
+ * include/linux/amba/pl022.h
+ *
+ * Copyright (C) 2008-2009 ST-Ericsson AB
+ * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
+ *
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ *
+ * Initial version inspired by:
+ *      linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
+ * Initial adoption to PL022 by:
+ *      Sachin Verma <sachin.verma@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SSP_PL022_H
+#define _SSP_PL022_H
+
+#include <linux/device.h>
+
+/**
+ * whether SSP is in loopback mode or not
+ */
+enum ssp_loopback {
+        LOOPBACK_DISABLED,
+        LOOPBACK_ENABLED
+};
+
+/**
+ * enum ssp_interface - interfaces allowed for this SSP Controller
+ * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
+ * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
+ * interface
+ * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
+ * interface
+ * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
+ * &STn8815 only)
+ */
+enum ssp_interface {
+        SSP_INTERFACE_MOTOROLA_SPI,
+        SSP_INTERFACE_TI_SYNC_SERIAL,
+        SSP_INTERFACE_NATIONAL_MICROWIRE,
+        SSP_INTERFACE_UNIDIRECTIONAL
+};
+
+/**
+ * enum ssp_hierarchy - whether SSP is configured as Master or Slave
+ */
+enum ssp_hierarchy {
+        SSP_MASTER,
+        SSP_SLAVE
+};
+
+/**
+ * enum ssp_clock_params - clock parameters, to set SSP clock at a
+ * desired freq
+ */
+struct ssp_clock_params {
+        u8 cpsdvsr; /* value from 2 to 254 (even only!) */
+        u8 scr;     /* value from 0 to 255 */
+};
+
+/**
+ * enum ssp_rx_endian - endianess of Rx FIFO Data
+ */
+enum ssp_rx_endian {
+        SSP_RX_MSB,
+        SSP_RX_LSB
+};
+
+/**
+ * enum ssp_tx_endian - endianess of Tx FIFO Data
+ */
+enum ssp_tx_endian {
+        SSP_TX_MSB,
+        SSP_TX_LSB
+};
+
+/**
+ * enum ssp_data_size - number of bits in one data element
+ */
+enum ssp_data_size {
+        SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6,
+        SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9,
+        SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12,
+        SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15,
+        SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18,
+        SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21,
+        SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24,
+        SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27,
+        SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30,
+        SSP_DATA_BITS_31, SSP_DATA_BITS_32
+};
+
+/**
+ * enum ssp_mode - SSP mode of operation (Communication modes)
+ */
+enum ssp_mode {
+        INTERRUPT_TRANSFER,
+        POLLING_TRANSFER,
+        DMA_TRANSFER
+};
+
+/**
+ * enum ssp_rx_level_trig - receive FIFO watermark level which triggers
+ * IT: Interrupt fires when _N_ or more elements in RX FIFO.
+ */
+enum ssp_rx_level_trig {
+        SSP_RX_1_OR_MORE_ELEM,
+        SSP_RX_4_OR_MORE_ELEM,
+        SSP_RX_8_OR_MORE_ELEM,
+        SSP_RX_16_OR_MORE_ELEM,
+        SSP_RX_32_OR_MORE_ELEM
+};
+
+/**
+ * Transmit FIFO watermark level which triggers (IT Interrupt fires
+ * when _N_ or more empty locations in TX FIFO)
+ */
+enum ssp_tx_level_trig {
+        SSP_TX_1_OR_MORE_EMPTY_LOC,
+        SSP_TX_4_OR_MORE_EMPTY_LOC,
+        SSP_TX_8_OR_MORE_EMPTY_LOC,
+        SSP_TX_16_OR_MORE_EMPTY_LOC,
+        SSP_TX_32_OR_MORE_EMPTY_LOC
+};
+
+/**
+ * enum SPI Clock Phase - clock phase (Motorola SPI interface only)
+ * @SSP_CLK_RISING_EDGE: Receive data on rising edge
+ * @SSP_CLK_FALLING_EDGE: Receive data on falling edge
+ */
+enum ssp_spi_clk_phase {
+        SSP_CLK_RISING_EDGE,
+        SSP_CLK_FALLING_EDGE
+};
+
+/**
+ * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only)
+ * @SSP_CLK_POL_IDLE_LOW: Low inactive level
+ * @SSP_CLK_POL_IDLE_HIGH: High inactive level
+ */
+enum ssp_spi_clk_pol {
+        SSP_CLK_POL_IDLE_LOW,
+        SSP_CLK_POL_IDLE_HIGH
+};
+
+/**
+ * Microwire Conrol Lengths Command size in microwire format
+ */
+enum ssp_microwire_ctrl_len {
+        SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6,
+        SSP_BITS_7, SSP_BITS_8, SSP_BITS_9,
+        SSP_BITS_10, SSP_BITS_11, SSP_BITS_12,
+        SSP_BITS_13, SSP_BITS_14, SSP_BITS_15,
+        SSP_BITS_16, SSP_BITS_17, SSP_BITS_18,
+        SSP_BITS_19, SSP_BITS_20, SSP_BITS_21,
+        SSP_BITS_22, SSP_BITS_23, SSP_BITS_24,
+        SSP_BITS_25, SSP_BITS_26, SSP_BITS_27,
+        SSP_BITS_28, SSP_BITS_29, SSP_BITS_30,
+        SSP_BITS_31, SSP_BITS_32
+};
+
+/**
+ * enum Microwire Wait State
+ * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit
+ * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit
+ */
+enum ssp_microwire_wait_state {
+        SSP_MWIRE_WAIT_ZERO,
+        SSP_MWIRE_WAIT_ONE
+};
+
+/**
+ * enum Microwire - whether Full/Half Duplex
+ * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
+ *     SSPRXD not used
+ * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
+ *     an input.
+ */
+enum ssp_duplex {
+        SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
+        SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
+};
+
+/**
+ * CHIP select/deselect commands
+ */
+enum ssp_chip_select {
+        SSP_CHIP_SELECT,
+        SSP_CHIP_DESELECT
+};
+
+
+/**
+ * struct pl022_ssp_master - device.platform_data for SPI controller devices.
+ * @num_chipselect: chipselects are used to distinguish individual
+ *     SPI slaves, and are numbered from zero to num_chipselects - 1.
+ *     each slave has a chipselect signal, but it's common that not
+ *     every chipselect is connected to a slave.
+ * @enable_dma: if true enables DMA driven transfers.
+ */
+struct pl022_ssp_controller {
+        u16 bus_id;
+        u8 num_chipselect;
+        u8 enable_dma:1;
+};
+
+/**
+ * struct ssp_config_chip - spi_board_info.controller_data for SPI
+ * slave devices, copied to spi_device.controller_data.
+ *
+ * @lbm: used for test purpose to internally connect RX and TX
+ * @iface: Interface type(Motorola, TI, Microwire, Universal)
+ * @hierarchy: sets whether interface is master or slave
+ * @slave_tx_disable: SSPTXD is disconnected (in slave mode only)
+ * @clk_freq: Tune freq parameters of SSP(when in master mode)
+ * @endian_rx: Endianess of Data in Rx FIFO
+ * @endian_tx: Endianess of Data in Tx FIFO
+ * @data_size: Width of data element(4 to 32 bits)
+ * @com_mode: communication mode: polling, Interrupt or DMA
+ * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode)
+ * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode)
+ * @clk_phase: Motorola SPI interface Clock phase
+ * @clk_pol: Motorola SPI interface Clock polarity
+ * @ctrl_len: Microwire interface: Control length
+ * @wait_state: Microwire interface: Wait state
+ * @duplex: Microwire interface: Full/Half duplex
+ * @cs_control: function pointer to board-specific function to
+ * assert/deassert I/O port to control HW generation of devices chip-select.
+ * @dma_xfer_type: Type of DMA xfer (Mem-to-periph or Periph-to-Periph)
+ * @dma_config: DMA configuration for SSP controller and peripheral
+ */
+struct pl022_config_chip {
+        struct device *dev;
+        enum ssp_loopback lbm;
+        enum ssp_interface iface;
+        enum ssp_hierarchy hierarchy;
+        bool slave_tx_disable;
+        struct ssp_clock_params clk_freq;
+        enum ssp_rx_endian endian_rx;
+        enum ssp_tx_endian endian_tx;
+        enum ssp_data_size data_size;
+        enum ssp_mode com_mode;
+        enum ssp_rx_level_trig rx_lev_trig;
+        enum ssp_tx_level_trig tx_lev_trig;
+        enum ssp_spi_clk_phase clk_phase;
+        enum ssp_spi_clk_pol clk_pol;
+        enum ssp_microwire_ctrl_len ctrl_len;
+        enum ssp_microwire_wait_state wait_state;
+        enum ssp_duplex duplex;
+        void (*cs_control) (u32 control);
+};
+
+#endif /* _SSP_PL022_H */
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index 64a982ea5d5f..5a5a7fd62490 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -114,6 +114,9 @@
 #define UART011_IFLS_TX4_8      (2 << 0)
 #define UART011_IFLS_TX6_8      (3 << 0)
 #define UART011_IFLS_TX7_8      (4 << 0)
+/* special values for ST vendor with deeper fifo */
+#define UART011_IFLS_RX_HALF    (5 << 3)
+#define UART011_IFLS_TX_HALF    (5 << 0)
 
 #define UART011_OEIM            (1 << 10)       /* overrun error interrupt mask */
 #define UART011_BEIM            (1 << 9)        /* break error interrupt mask */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 1db9bbf444a3..1d37f42ac294 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -142,4 +142,17 @@ struct clk *clk_get_parent(struct clk *clk);
  */
 struct clk *clk_get_sys(const char *dev_id, const char *con_id);
 
+/**
+ * clk_add_alias - add a new clock alias
+ * @alias: name for clock alias
+ * @alias_dev_name: device name
+ * @id: platform specific clock name
+ * @dev: device
+ *
+ * Allows using generic clock names for drivers by adding a new alias.
+ * Assumes clkdev, see clkdev.h for more info.
+ */
+int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
+                        struct device *dev);
+
 #endif
diff --git a/include/video/pxa168fb.h b/include/video/pxa168fb.h
new file mode 100644
index 000000000000..b5cc72fe0461
--- /dev/null
+++ b/include/video/pxa168fb.h
@@ -0,0 +1,127 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/pxa168fb.h
+ *
+ *  Copyright (C) 2009 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_PXA168FB_H
+#define __ASM_MACH_PXA168FB_H
+
+#include <linux/fb.h>
+#include <linux/interrupt.h>
+
+/* Dumb interface */
+#define PIN_MODE_DUMB_24                0
+#define PIN_MODE_DUMB_18_SPI            1
+#define PIN_MODE_DUMB_18_GPIO           2
+#define PIN_MODE_DUMB_16_SPI            3
+#define PIN_MODE_DUMB_16_GPIO           4
+#define PIN_MODE_DUMB_12_SPI_GPIO       5
+#define PIN_MODE_SMART_18_SPI           6
+#define PIN_MODE_SMART_16_SPI           7
+#define PIN_MODE_SMART_8_SPI_GPIO       8
+
+/* Dumb interface pin allocation */
+#define DUMB_MODE_RGB565                0
+#define DUMB_MODE_RGB565_UPPER          1
+#define DUMB_MODE_RGB666                2
+#define DUMB_MODE_RGB666_UPPER          3
+#define DUMB_MODE_RGB444                4
+#define DUMB_MODE_RGB444_UPPER          5
+#define DUMB_MODE_RGB888                6
+
+/* default fb buffer size WVGA-32bits */
+#define DEFAULT_FB_SIZE (800 * 480 * 4)
+
+/*
+ * Buffer pixel format
+ * bit0 is for rb swap.
+ * bit12 is for Y UorV swap
+ */
+#define PIX_FMT_RGB565          0
+#define PIX_FMT_BGR565          1
+#define PIX_FMT_RGB1555         2
+#define PIX_FMT_BGR1555         3
+#define PIX_FMT_RGB888PACK      4
+#define PIX_FMT_BGR888PACK      5
+#define PIX_FMT_RGB888UNPACK    6
+#define PIX_FMT_BGR888UNPACK    7
+#define PIX_FMT_RGBA888         8
+#define PIX_FMT_BGRA888         9
+#define PIX_FMT_YUV422PACK      10
+#define PIX_FMT_YVU422PACK      11
+#define PIX_FMT_YUV422PLANAR    12
+#define PIX_FMT_YVU422PLANAR    13
+#define PIX_FMT_YUV420PLANAR    14
+#define PIX_FMT_YVU420PLANAR    15
+#define PIX_FMT_PSEUDOCOLOR     20
+#define PIX_FMT_UYVY422PACK     (0x1000|PIX_FMT_YUV422PACK)
+
+/*
+ * PXA LCD controller private state.
+ */
+struct pxa168fb_info {
+        struct device           *dev;
+        struct clk              *clk;
+        struct fb_info          *info;
+
+        void __iomem            *reg_base;
+        dma_addr_t              fb_start_dma;
+        u32                     pseudo_palette[16];
+
+        int                     pix_fmt;
+        unsigned                is_blanked:1;
+        unsigned                panel_rbswap:1;
+        unsigned                active:1;
+};
+
+/*
+ * PXA fb machine information
+ */
+struct pxa168fb_mach_info {
+        char    id[16];
+
+        int             num_modes;
+        struct fb_videomode *modes;
+
+        /*
+         * Pix_fmt
+         */
+        unsigned        pix_fmt;
+
+        /*
+         * I/O pin allocation.
+         */
+        unsigned        io_pin_allocation_mode:4;
+
+        /*
+         * Dumb panel -- assignment of R/G/B component info to the 24
+         * available external data lanes.
+         */
+        unsigned        dumb_mode:4;
+        unsigned        panel_rgb_reverse_lanes:1;
+
+        /*
+         * Dumb panel -- GPIO output data.
+         */
+        unsigned        gpio_output_mask:8;
+        unsigned        gpio_output_data:8;
+
+        /*
+         * Dumb panel -- configurable output signal polarity.
+         */
+        unsigned        invert_composite_blank:1;
+        unsigned        invert_pix_val_ena:1;
+        unsigned        invert_pixclock:1;
+        unsigned        invert_vsync:1;
+        unsigned        invert_hsync:1;
+        unsigned        panel_rbswap:1;
+        unsigned        active:1;
+        unsigned        enable_lcd:1;
+};
+
+#endif /* __ASM_MACH_PXA168FB_H */