201 files changed, 4496 insertions, 2101 deletions
diff --git a/include/asm-arm/arch-s3c2410/anubis-cpld.h b/include/asm-arm/arch-s3c2410/anubis-cpld.h
index dcebf6d61903..168b93fee529 100644
--- a/include/asm-arm/arch-s3c2410/anubis-cpld.h
+++ b/include/asm-arm/arch-s3c2410/anubis-cpld.h
@@ -18,4 +18,8 @@
 #define ANUBIS_CTRL1_NANDSEL            (0x3)
+/* IDREG - revision */
+#define ANUBIS_IDREG_REVMASK            (0x7)
 #endif /* __ASM_ARCH_ANUBISCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h
index ab076de4a0d0..830d114261da 100644
--- a/include/asm-arm/arch-s3c2410/anubis-map.h
+++ b/include/asm-arm/arch-s3c2410/anubis-map.h
@@ -27,14 +27,8 @@
 #define ANUBIS_VA_CTRL1     ANUBIS_IOADDR(0x00000000)    /* 0x01800000 */
 #define ANUBIS_PA_CTRL1     (ANUBIS_PA_CPLD)
-#define ANUBIS_VA_CTRL2     ANUBIS_IOADDR(0x00100000)    /* 0x01900000 */
+#define ANUBIS_VA_IDREG     ANUBIS_IOADDR(0x00300000)    /* 0x01B00000 */
-#define ANUBIS_PA_CTRL2     (ANUBIS_PA_CPLD)
+#define ANUBIS_PA_IDREG     (ANUBIS_PA_CPLD + (3<<23))
-#define ANUBIS_VA_CTRL3     ANUBIS_IOADDR(0x00200000)    /* 0x01A00000 */
-#define ANUBIS_PA_CTRL3     (ANUBIS_PA_CPLD)
-#define ANUBIS_VA_CTRL4     ANUBIS_IOADDR(0x00300000)    /* 0x01B00000 */
-#define ANUBIS_PA_CTRL4     (ANUBIS_PA_CPLD)
 #define ANUBIS_IDEPRI       ANUBIS_IOADDR(0x01000000)
 #define ANUBIS_IDEPRIAUX    ANUBIS_IOADDR(0x01100000)
diff --git a/include/asm-arm/arch-s3c2410/osiris-cpld.h b/include/asm-arm/arch-s3c2410/osiris-cpld.h
index 3b6498468d62..229ab2351db6 100644
--- a/include/asm-arm/arch-s3c2410/osiris-cpld.h
+++ b/include/asm-arm/arch-s3c2410/osiris-cpld.h
@@ -1,6 +1,6 @@
 /* linux/include/asm-arm/arch-s3c2410/osiris-cpld.h
 *
- * Copyright (c) 2005 Simtec Electronics
+ * Copyright 2005 Simtec Electronics
 *      http://www.simtec.co.uk/products/
 *      Ben Dooks <ben@simtec.co.uk>
 *
@@ -14,12 +14,17 @@
 #ifndef __ASM_ARCH_OSIRISCPLD_H
 #define __ASM_ARCH_OSIRISCPLD_H
-/* CTRL1 - NAND WP control */
+/* CTRL0 - NAND WP control */
-#define OSIRIS_CTRL1_NANDSEL            (0x3)
+#define OSIRIS_CTRL0_NANDSEL            (0x3)
-#define OSIRIS_CTRL1_BOOT_INT           (1<<3)
+#define OSIRIS_CTRL0_BOOT_INT           (1<<3)
-#define OSIRIS_CTRL1_PCMCIA             (1<<4)
+#define OSIRIS_CTRL0_PCMCIA             (1<<4)
-#define OSIRIS_CTRL1_PCMCIA_nWAIT       (1<<6)
+#define OSIRIS_CTRL0_FIX8               (1<<5)
-#define OSIRIS_CTRL1_PCMCIA_nIOIS16     (1<<7)
+#define OSIRIS_CTRL0_PCMCIA_nWAIT       (1<<6)
+#define OSIRIS_CTRL0_PCMCIA_nIOIS16     (1<<7)
+#define OSIRIS_CTRL1_FIX8               (1<<0)
+#define OSIRIS_ID_REVMASK               (0x7)
 #endif /* __ASM_ARCH_OSIRISCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h
index a14164dfa525..b5c74d2b9aaa 100644
--- a/include/asm-arm/arch-s3c2410/osiris-map.h
+++ b/include/asm-arm/arch-s3c2410/osiris-map.h
@@ -24,16 +24,19 @@
 /* we put the CPLD registers next, to get them out of the way */
-#define OSIRIS_VA_CTRL1     OSIRIS_IOADDR(0x00000000)
+#define OSIRIS_VA_CTRL0         OSIRIS_IOADDR(0x00000000)
-#define OSIRIS_PA_CTRL1     (OSIRIS_PA_CPLD)
+#define OSIRIS_PA_CTRL0         (OSIRIS_PA_CPLD)
-#define OSIRIS_VA_CTRL2     OSIRIS_IOADDR(0x00100000)
+#define OSIRIS_VA_CTRL1         OSIRIS_IOADDR(0x00100000)
-#define OSIRIS_PA_CTRL2     (OSIRIS_PA_CPLD + (1<<23))
+#define OSIRIS_PA_CTRL1         (OSIRIS_PA_CPLD + (1<<23))
-#define OSIRIS_VA_CTRL3     OSIRIS_IOADDR(0x00200000)
+#define OSIRIS_VA_CTRL2         OSIRIS_IOADDR(0x00200000)
-#define OSIRIS_PA_CTRL3     (OSIRIS_PA_CPLD + (2<<23))
+#define OSIRIS_PA_CTRL2         (OSIRIS_PA_CPLD + (2<<23))
-#define OSIRIS_VA_CTRL4     OSIRIS_IOADDR(0x00300000)
+#define OSIRIS_VA_CTRL3         OSIRIS_IOADDR(0x00300000)
-#define OSIRIS_PA_CTRL4     (OSIRIS_PA_CPLD + (3<<23))
+#define OSIRIS_PA_CTRL3         (OSIRIS_PA_CPLD + (2<<23))
+#define OSIRIS_VA_IDREG         OSIRIS_IOADDR(0x00700000)
+#define OSIRIS_PA_IDREG         (OSIRIS_PA_CPLD + (7<<23))
 #endif /* __ASM_ARCH_OSIRISMAP_H */
diff --git a/include/asm-arm/linkage.h b/include/asm-arm/linkage.h
index dbe4b4e31a5b..5a25632b1bc0 100644
--- a/include/asm-arm/linkage.h
+++ b/include/asm-arm/linkage.h
@@ -4,4 +4,8 @@
 #define __ALIGN .align 0
 #define __ALIGN_STR ".align 0"
+#define ENDPROC(name) \
+  .type name, %function; \
+  END(name)
 #endif
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
index 2d0dad8c10ac..ee3d93c281d8 100644
--- a/include/asm-arm/ptrace.h
+++ b/include/asm-arm/ptrace.h
@@ -112,9 +112,6 @@ struct pt_regs {
 #define fast_interrupts_enabled(regs) \
        (!((regs)->ARM_cpsr & PSR_F_BIT))
-#define condition_codes(regs) \
-        ((regs)->ARM_cpsr & (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT))
-        
 /* Are the current registers suitable for user mode?
 * (used to maintain security in signal handlers)
 */
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index 250d7f145aca..bfdbebebdc1b 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -367,6 +367,7 @@
 #define __NR_get_robust_list            (__NR_SYSCALL_BASE+339)
 #define __NR_splice                     (__NR_SYSCALL_BASE+340)
 #define __NR_arm_sync_file_range        (__NR_SYSCALL_BASE+341)
+#define __NR_sync_file_range2           __NR_arm_sync_file_range
 #define __NR_tee                        (__NR_SYSCALL_BASE+342)
 #define __NR_vmsplice                   (__NR_SYSCALL_BASE+343)
 #define __NR_move_pages                 (__NR_SYSCALL_BASE+344)
diff --git a/include/asm-arm26/termbits.h b/include/asm-arm26/termbits.h
index a3f4fe1742d0..f66b51804736 100644
--- a/include/asm-arm26/termbits.h
+++ b/include/asm-arm26/termbits.h
@@ -15,7 +15,7 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
-struct ktermios {
+struct termios2 {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
        tcflag_t c_cflag;               /* control mode flags */
@@ -26,6 +26,16 @@ struct ktermios {
        speed_t c_ospeed;               /* output speed */
 };
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 /* c_cc characters */
 #define VINTR 0
diff --git a/include/asm-avr32/arch-at32ap/gpio.h b/include/asm-avr32/arch-at32ap/gpio.h
index 80a21aa9ae77..af7f9535bab3 100644
--- a/include/asm-avr32/arch-at32ap/gpio.h
+++ b/include/asm-avr32/arch-at32ap/gpio.h
@@ -14,6 +14,8 @@ int gpio_direction_output(unsigned int gpio, int value);
 int gpio_get_value(unsigned int gpio);
 void gpio_set_value(unsigned int gpio, int value);
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
 static inline int gpio_to_irq(unsigned int gpio)
 {
        return gpio + GPIO_IRQ_BASE;
diff --git a/include/asm-avr32/cache.h b/include/asm-avr32/cache.h
index dabb955f3c00..d3cf35ab11ab 100644
--- a/include/asm-avr32/cache.h
+++ b/include/asm-avr32/cache.h
@@ -4,6 +4,15 @@
 #define L1_CACHE_SHIFT 5
 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+/*
+ * Memory returned by kmalloc() may be used for DMA, so we must make
+ * sure that all such allocations are cache aligned. Otherwise,
+ * unrelated code may cause parts of the buffer to be read into the
+ * cache before the transfer is done, causing old data to be seen by
+ * the CPU.
+ */
+#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
 #ifndef __ASSEMBLER__
 struct cache_info {
        unsigned int ways;
diff --git a/include/asm-avr32/termbits.h b/include/asm-avr32/termbits.h
index c215fafdae4d..db2daab31fdb 100644
--- a/include/asm-avr32/termbits.h
+++ b/include/asm-avr32/termbits.h
@@ -17,6 +17,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
index 14e58de73973..25b934b7f829 100644
--- a/include/asm-blackfin/blackfin.h
+++ b/include/asm-blackfin/blackfin.h
@@ -6,7 +6,11 @@
 #ifndef _BLACKFIN_H_
 #define _BLACKFIN_H_
-#include <asm/macros.h>
+#define LO(con32) ((con32) & 0xFFFF)
+#define lo(con32) ((con32) & 0xFFFF)
+#define HI(con32) (((con32) >> 16) & 0xFFFF)
+#define hi(con32) (((con32) >> 16) & 0xFFFF)
 #include <asm/mach/blackfin.h>
 #include <asm/bfin-global.h>
@@ -35,7 +39,9 @@ static inline void SSYNC (void)
 #elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
 static inline void SSYNC (void)
 {
-        __builtin_bfin_ssync();
+        __asm__ __volatile__ ("nop; nop; nop;\n\t"
+                        "ssync;\n\t"
+                        ::);
 }
 #elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
 static inline void SSYNC (void)
@@ -67,7 +73,9 @@ static inline void CSYNC (void)
 #elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
 static inline void CSYNC (void)
 {
-        __builtin_bfin_csync();
+        __asm__ __volatile__ ("nop; nop; nop;\n\t"
+                        "ssync;\n\t"
+                        ::);
 }
 #elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
 static inline void CSYNC (void)
@@ -76,6 +84,31 @@ static inline void CSYNC (void)
 }
 #endif
+#else  /* __ASSEMBLY__ */
+/* SSYNC & CSYNC implementations for assembly files */
+#define ssync(x) SSYNC(x)
+#define csync(x) CSYNC(x)
+#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
+#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
+#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
+#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
+#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+#define SSYNC(scratch) nop; nop; nop; SSYNC;
+#define CSYNC(scratch) nop; nop; nop; CSYNC;
+#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+#define SSYNC(scratch) SSYNC;
+#define CSYNC(scratch) CSYNC;
+#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
 #endif /* __ASSEMBLY__ */
 #endif                          /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h
index 7a77d7fe3a33..282fabccf6a6 100644
--- a/include/asm-blackfin/dma-mapping.h
+++ b/include/asm-blackfin/dma-mapping.h
@@ -15,6 +15,8 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#define dma_mapping_error
 /*
 * Map a single buffer of the indicated size for DMA in streaming mode.
 * The 32-bit bus address to use is returned.
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index aa0d5503e232..d98d77ad71f7 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -332,6 +332,7 @@ struct gpio_port_s {
        unsigned short inen;
        unsigned short fer;
+        unsigned short reserved;
 };
 #endif /*CONFIG_PM*/
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index eac8bcaf64c2..142cb333db29 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -20,7 +20,7 @@
 */
 #ifndef __ASSEMBLY__
-static inline unsigned char readb(void __iomem *addr)
+static inline unsigned char readb(const volatile void __iomem *addr)
 {
        unsigned int val;
        int tmp;
@@ -35,7 +35,7 @@ static inline unsigned char readb(void __iomem *addr)
        return (unsigned char) val;
 }
-static inline unsigned short readw(void __iomem *addr)
+static inline unsigned short readw(const volatile void __iomem *addr)
 {
        unsigned int val;
        int tmp;
@@ -50,7 +50,7 @@ static inline unsigned short readw(void __iomem *addr)
        return (unsigned short) val;
 }
-static inline unsigned int readl(void __iomem *addr)
+static inline unsigned int readl(const volatile void __iomem *addr)
 {
        unsigned int val;
        int tmp;
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index a84d3909345e..7302f290b93d 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -43,7 +43,8 @@
 #endif
 /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
-#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
+#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
+                || defined(CONFIG_BF_REV_0_3))
 #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
                            slot1 and store of a P register in slot 2 is not
                            supported */
@@ -76,11 +77,16 @@
                            control */
 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
                            killed in a particular stage*/
+#define ANOMALY_05000311 /* Erroneous flag pin operations under specific
+                            sequences */
 #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
                            registers are interrupted */
-#define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/
+#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer  */
+#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
-#endif
+                          *  Next System MMR Access */
+#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V
+                          *  and 1.15V Not Allowed for LQFP Packages */
+#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
 /* These issues only occur on 0.3 or 0.4 BF533 */
 #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
@@ -134,14 +140,14 @@
                            internal voltage regulator (VDDint) to increase. */
 #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
                            internal voltage regulator (VDDint) to decrease */
-#endif
+#endif /* issues only occur on 0.3 or 0.4 BF533 */
 /* These issues are only on 0.4 silicon */
 #if (defined(CONFIG_BF_REV_0_4))
 #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
 #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
                            (TDM) */
-#endif
+#endif /* issues are only on 0.4 silicon */
 /* These issues are only on 0.3 silicon */
 #if defined(CONFIG_BF_REV_0_3)
@@ -170,6 +176,72 @@
 #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
                            Sync Transmit Mode */
 #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
+#endif /* only on 0.3 silicon */
+#if defined(CONFIG_BF_REV_0_2)
+#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not
+                          *  supported */
+#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at
+                          *  power on */
+#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into
+                          *  emulation mode and/or exception, NMI, reset
+                          *  handlers */
+#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be
+                          *  incorrect if data cache or DMA is active */
+#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1,
+                          *  or 1:1 */
+#define ANOMALY_05000125 /* Erroneous exception when enabling cache */
+#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect
+                          *  during booting */
+#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */
+#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill
+                          * block in the loader file */
+#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an
+                          *  overflow */
+#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence
+                          *  of consecutive dual dag events */
+#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input
+                          *  flag is configured to be edge sensitive */
+#define ANOMALY_05000143 /* A read from external memory may return a wrong
+                          *  value with data cache enabled */
+#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing
+                          *  external memory */
+#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to
+                          *  generate a waveform from PPI_CLK */
+#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor
+                          *  chain */
+#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA
+                          *  Error */
+#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory
+                          *  device, the upper 8-bits of each word must be
+                          *  0x00 */
+#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode
+                          *  outside of valid channels */
+#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a
+                          *  certain PPI mode is in use */
+#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to
+                          *  the next system MMR access thinking it should be
+                          *  32-bit. */
+#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame
+                          *  sync in certain conditions */
+#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
+#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost
+                          *  write-through cache data writes */
+#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */
+#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
+#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
+#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
+                          *  accumulator saturation */
+#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
+                          *  registers */
+#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
+#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in
+                          *  Transmit Modes */
+#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs
+                          *  POLC */
+#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */
 #endif
 #endif /*  _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index 23bf76aa3451..e043cafa3c42 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -78,6 +78,7 @@ struct bfin_serial_res {
 };
 struct bfin_serial_res bfin_serial_resource[] = {
+        {
        0xFFC00400,
        IRQ_UART_RX,
 #ifdef CONFIG_SERIAL_BFIN_DMA
@@ -88,6 +89,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
        CONFIG_UART0_CTS_PIN,
        CONFIG_UART0_RTS_PIN,
 #endif
+        }
 };
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 7f040f5ba018..4453e614c3b1 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -73,8 +73,13 @@
                            control */
 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
                            killed in a particular stage*/
+#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
+                          *  boundary of reserved memory */
 #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
                            registers are interrupted */
+#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
+#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
+                          *  received properly */
 #endif
 #if defined(CONFIG_BF_REV_0_2)
@@ -114,7 +119,21 @@
                            DMA system instability */
 #define ANOMALY_05000280 /* SPI Master boot mode does not work well with
                            Atmel Dataflash devices */
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
+                          *  is not restored */
+#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
+                          *  control */
+#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When
+                          *  Killed in a Particular Stage */
+#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment
+                          *  (Not Available On Older Silicon) */
+#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
+#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously
+                          *  On Next System MMR Access */
+#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex
+                          *  mode */
+#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
+                          *  status No Carrier */
 #endif  /* CONFIG_BF_REV_0_2 */
 #endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 23bf76aa3451..e043cafa3c42 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -78,6 +78,7 @@ struct bfin_serial_res {
 };
 struct bfin_serial_res bfin_serial_resource[] = {
+        {
        0xFFC00400,
        IRQ_UART_RX,
 #ifdef CONFIG_SERIAL_BFIN_DMA
@@ -88,6 +89,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
        CONFIG_UART0_CTS_PIN,
        CONFIG_UART0_RTS_PIN,
 #endif
+        }
 };
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
index d39c396f850d..58f878947cbc 100644
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -39,7 +39,20 @@
 #define bfin_read_SRAM_BASE_ADDRESS()        bfin_read32(SRAM_BASE_ADDRESS)
 #define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
 #define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
+#ifdef ANOMALY_05000125
+static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val)
+{
+        unsigned long flags, iwr;
+        local_irq_save(flags);
+        __asm__(".align 8\n");
+        bfin_write32(IMEM_CONTROL, val);
+        __builtin_bfin_ssync();
+        local_irq_restore(flags);
+}
+#else
 #define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
+#endif
 #define bfin_read_DCPLB_STATUS()             bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)         bfin_write32(DCPLB_STATUS,val)
 #define bfin_read_DCPLB_FAULT_ADDR()         bfin_read32(DCPLB_FAULT_ADDR)
@@ -125,7 +138,21 @@
 #define DTEST_DATA3            0xFFE0040C
 */
 #define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
+#ifdef ANOMALY_05000125
+static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val)
+{
+        unsigned long flags, iwr;
+        local_irq_save(flags);
+        __asm__(".align 8\n");
+        bfin_write32(IMEM_CONTROL, val);
+        __builtin_bfin_ssync();
+        local_irq_restore(flags);
+}
+#else
 #define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
+#endif
 #define bfin_read_ICPLB_STATUS()             bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)         bfin_write32(ICPLB_STATUS,val)
 #define bfin_read_ICPLB_FAULT_ADDR()         bfin_read32(ICPLB_FAULT_ADDR)
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index 76103526aec1..be1ece8c0c27 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -42,6 +42,12 @@
 #if defined(ANOMALY_05000198)
+#define bfin_read8(addr) ({ unsigned char __v; \
+                __asm__ __volatile__ ("NOP;\n\t" \
+                        "%0 = b[%1] (z);\n\t" \
+                        : "=d"(__v) : "a"(addr)); \
+                __v; })
 #define bfin_read16(addr) ({ unsigned __v; \
                       __asm__ __volatile__ ("NOP;\n\t"\
                                                                "%0 = w[%1] (z);\n\t"\
@@ -52,6 +58,11 @@
                                            "%0 = [%1];\n\t"\
  : "=d"(__v) : "a"(addr)); __v; })
+#define bfin_write8(addr, val) ({ \
+                __asm__ __volatile__ ("NOP;\n\t" \
+                        "b[%0] = %1;\n\t" \
+                        : : "a"(addr), "d"(val) : "memory");})
 #define bfin_write16(addr,val) ({\
                      __asm__ __volatile__ ("NOP;\n\t"\
                                            "w[%0] = %1;\n\t"\
@@ -64,6 +75,12 @@
 #else
+#define bfin_read8(addr) ({ unsigned char __v; \
+                __asm__ __volatile__ ( \
+                        "%0 = b[%1] (z);\n\t" \
+                        :"=d"(__v) : "a"(addr)); \
+                __v; })
 #define bfin_read16(addr) ({ unsigned __v; \
                       __asm__ __volatile__ (\
                                                                "%0 = w[%1] (z);\n\t"\
@@ -74,6 +91,11 @@
                                            "%0 = [%1];\n\t"\
  : "=d"(__v) : "a"(addr)); __v; })
+#define bfin_write8(addr, val) ({ \
+                __asm__ __volatile__ ( \
+                        "b[%0] = %1; \n\t" \
+                        ::"a"(addr), "d"(val) : "memory");})
 #define bfin_write16(addr,val) ({\
                      __asm__ __volatile__ (\
                                            "w[%0] = %1;\n\t"\
diff --git a/include/asm-blackfin/macros.h b/include/asm-blackfin/macros.h
deleted file mode 100644
index c0c04a2f2dd5..000000000000
--- a/include/asm-blackfin/macros.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/************************************************************************
- *
- * macros.h
- *
- * (c) Copyright 2001-2003 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-/* Defines various assembly macros. */
-#ifndef _MACROS_H
-#define _MACROS_H
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-/*
- * Set the corresponding bits in a System Register (SR);
- * All bits set in "mask" will be set in the system register
- * specified by "sys_reg" bitset_SR(sys_reg, mask), where
- * sys_reg is the system register and mask are the bits to be set.
- */
-#define bitset_SR(sys_reg, mask)\
-                [--SP] = (R7:6);\
-                r7 = sys_reg;\
-                r6.l = (mask) & 0xffff;\
-                r6.h = (mask) >> 16;\
-                r7 = r7 | r6;\
-                sys_reg = r7;\
-                csync;\
-                (R7:6) = [SP++]
-/*
- * Clear the corresponding bits in a System Register (SR);
- * All bits set in "mask" will be cleared in the SR
- * specified by "sys_reg" bitclr_SR(sys_reg, mask), where
- * sys_reg is the SR and mask are the bits to be cleared.
- */
-#define bitclr_SR(sys_reg, mask)\
-                [--SP] = (R7:6);\
-                r7 = sys_reg;\
-                r7 =~ r7;\
-                r6.l = (mask) & 0xffff;\
-                r6.h = (mask) >> 16;\
-                r7 = r7 | r6;\
-                r7 =~ r7;\
-                sys_reg = r7;\
-                csync;\
-                (R7:6) = [SP++]
-/*
- * Set the corresponding bits in a Memory Mapped Register (MMR);
- * All bits set in "mask" will be set in the MMR specified by "mmr_reg"
- * bitset_MMR(mmr_reg, mask), where mmr_reg is the MMR and mask are
- * the bits to be set.
- */
-#define bitset_MMR(mmr_reg, mask)\
-                [--SP] = (R7:6);\
-                [--SP] = P5;\
-                p5.l = mmr_reg & 0xffff;\
-                p5.h = mmr_reg >> 16;\
-                r7 = [p5];\
-                r6.l = (mask) & 0xffff;\
-                r6.h = (mask) >> 16;\
-                r7 = r7 | r6;\
-                [p5] = r7;\
-                csync;\
-                p5 = [SP++];\
-                (R7:6) = [SP++]
-/*
- * Clear the corresponding bits in a Memory Mapped Register (MMR);
- * All bits set in "mask" will be cleared in the MMR specified by "mmr_reg"
- * bitclr_MMRreg(mmr_reg, mask), where sys_reg is the MMR and mask are
- * the bits to be cleared.
- */
-#define bitclr_MMR(mmr_reg, mask)\
-                [--SP] = (R7:6);\
-                [--SP] = P5;\
-                p5.l = mmr_reg & 0xffff;\
-                p5.h = mmr_reg >> 16;\
-                r7 = [p5];\
-                r7 =~ r7;\
-                r6.l = (mask) & 0xffff;\
-                r6.h = (mask) >> 16;\
-                r7 = r7 | r6;\
-                r7 =~ r7;\
-                [p5] = r7;\
-                csync;\
-                p5 = [SP++];\
-                (R7:6) = [SP++]
-#endif                          /* _MACROS_H */
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
index aba2b30a8ed8..6bb3e0d4705d 100644
--- a/include/asm-blackfin/processor.h
+++ b/include/asm-blackfin/processor.h
@@ -124,6 +124,10 @@ static inline __attribute_pure__ uint32_t bfin_compiled_revid(void)
        return 4;
 #elif defined(CONFIG_BF_REV_0_5)
        return 5;
+#elif defined(CONFIG_BF_REV_ANY)
+        return 0xffff;
+#else
+        return -1;
 #endif
 }
diff --git a/include/asm-blackfin/termbits.h b/include/asm-blackfin/termbits.h
index 2fd9dabdba77..4eac38de8ce1 100644
--- a/include/asm-blackfin/termbits.h
+++ b/include/asm-blackfin/termbits.h
@@ -17,6 +17,17 @@ struct termios {
        cc_t c_cc[NCCS];        /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
index 4df8790a67d5..0df9f2d322a3 100644
--- a/include/asm-blackfin/unistd.h
+++ b/include/asm-blackfin/unistd.h
@@ -369,7 +369,6 @@
 #define __ARCH_WANT_SYS_NICE
 #define __ARCH_WANT_SYS_RT_SIGACTION
 #define __ARCH_WANT_SYS_RT_SIGSUSPEND
-#endif
 /*
 * "Conditional" syscalls
@@ -379,4 +378,6 @@
 */
 #define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
+#endif  /* __KERNEL__ */
 #endif                          /* __ASM_BFIN_UNISTD_H */
diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h
index 8d8cec225fe1..6cc2e2736f7b 100644
--- a/include/asm-cris/termbits.h
+++ b/include/asm-cris/termbits.h
@@ -19,6 +19,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h
index 2687c7715120..114aefae2701 100644
--- a/include/asm-frv/pgtable.h
+++ b/include/asm-frv/pgtable.h
@@ -25,7 +25,7 @@
 #include <linux/slab.h>
 #include <linux/list.h>
 #include <linux/spinlock.h>
-struct mm_struct;
+#include <linux/sched.h>
 struct vm_area_struct;
 #endif
diff --git a/include/asm-frv/termbits.h b/include/asm-frv/termbits.h
index 2d6d389cff49..74851b424d4f 100644
--- a/include/asm-frv/termbits.h
+++ b/include/asm-frv/termbits.h
@@ -17,6 +17,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-generic/bitops/sched.h b/include/asm-generic/bitops/sched.h
index 815bb0148060..604fab7031a6 100644
--- a/include/asm-generic/bitops/sched.h
+++ b/include/asm-generic/bitops/sched.h
@@ -6,28 +6,23 @@
 /*
 * Every architecture must define this function. It's the fastest
- * way of searching a 140-bit bitmap where the first 100 bits are
+ * way of searching a 100-bit bitmap.  It's guaranteed that at least
- * unlikely to be set. It's guaranteed that at least one of the 140
+ * one of the 100 bits is cleared.
- * bits is cleared.
 */
 static inline int sched_find_first_bit(const unsigned long *b)
 {
 #if BITS_PER_LONG == 64
-        if (unlikely(b[0]))
+        if (b[0])
                return __ffs(b[0]);
-        if (likely(b[1]))
+        return __ffs(b[1]) + 64;
-                return __ffs(b[1]) + 64;
-        return __ffs(b[2]) + 128;
 #elif BITS_PER_LONG == 32
-        if (unlikely(b[0]))
+        if (b[0])
                return __ffs(b[0]);
-        if (unlikely(b[1]))
+        if (b[1])
                return __ffs(b[1]) + 32;
-        if (unlikely(b[2]))
+        if (b[2])
                return __ffs(b[2]) + 64;
-        if (b[3])
+        return __ffs(b[3]) + 96;
-                return __ffs(b[3]) + 96;
-        return __ffs(b[4]) + 128;
 #else
 #error BITS_PER_LONG not defined
 #endif
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index dc8f99ee305f..7d7bcf990e99 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -27,13 +27,20 @@ do {				  					\
 * Largely same as above, but only sets the access flags (dirty,
 * accessed, and writable). Furthermore, we know it always gets set
 * to a "more permissive" setting, which allows most architectures
- * to optimize this.
+ * to optimize this. We return whether the PTE actually changed, which
+ * in turn instructs the caller to do things like update__mmu_cache.
+ * This used to be done in the caller, but sparc needs minor faults to
+ * force that call on sun4c so we changed this macro slightly
 */
 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-do {                                                                      \
+({                                                                        \
-        set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry);         \
+        int __changed = !pte_same(*(__ptep), __entry);                    \
-        flush_tlb_page(__vma, __address);                                 \
+        if (__changed) {                                                  \
-} while (0)
+                set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
+                flush_tlb_page(__vma, __address);                         \
+        }                                                                 \
+        __changed;                                                        \
+})
 #endif
 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
diff --git a/include/asm-h8300/termbits.h b/include/asm-h8300/termbits.h
index 6a1f4d3807b4..e877b40ac5ba 100644
--- a/include/asm-h8300/termbits.h
+++ b/include/asm-h8300/termbits.h
@@ -17,6 +17,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-i386/dma-mapping.h b/include/asm-i386/dma-mapping.h
index 183eebeebbdc..f1d72d177f68 100644
--- a/include/asm-i386/dma-mapping.h
+++ b/include/asm-i386/dma-mapping.h
@@ -123,6 +123,8 @@ dma_mapping_error(dma_addr_t dma_addr)
        return 0;
 }
+extern int forbid_dac;
 static inline int
 dma_supported(struct device *dev, u64 mask)
 {
@@ -134,6 +136,10 @@ dma_supported(struct device *dev, u64 mask)
        if(mask < 0x00ffffff)
                return 0;
+        /* Work around chipset bugs */
+        if (forbid_dac > 0 && mask > 0xffffffffULL)
+                return 0;
        return 1;
 }
diff --git a/include/asm-i386/mach-es7000/mach_apic.h b/include/asm-i386/mach-es7000/mach_apic.h
index 2d978928a395..caec64be516d 100644
--- a/include/asm-i386/mach-es7000/mach_apic.h
+++ b/include/asm-i386/mach-es7000/mach_apic.h
@@ -73,6 +73,10 @@ static inline void init_apic_ldr(void)
        apic_write_around(APIC_LDR, val);
 }
+#ifndef CONFIG_X86_GENERICARCH
+extern void enable_apic_mode(void);
+#endif
 extern int apic_version [MAX_APICS];
 static inline void setup_apic_routing(void)
 {
diff --git a/include/asm-i386/mach-es7000/mach_mpparse.h b/include/asm-i386/mach-es7000/mach_mpparse.h
index b9fb784e1fd5..8aa10547b4b1 100644
--- a/include/asm-i386/mach-es7000/mach_mpparse.h
+++ b/include/asm-i386/mach-es7000/mach_mpparse.h
@@ -18,6 +18,12 @@ extern int parse_unisys_oem (char *oemptr);
 extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
 extern void setup_unisys(void);
+#ifndef CONFIG_X86_GENERICARCH
+extern int acpi_madt_oem_check(char *oem_id, char *oem_table_id);
+extern int mps_oem_check(struct mp_config_table *mpc, char *oem,
+                                char *productid);
+#endif
 #ifdef CONFIG_ACPI
 static inline int es7000_check_dsdt(void)
diff --git a/include/asm-i386/paravirt.h b/include/asm-i386/paravirt.h
index d7a0512f88e0..7f846a7d6bcc 100644
--- a/include/asm-i386/paravirt.h
+++ b/include/asm-i386/paravirt.h
@@ -539,7 +539,7 @@ static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
        val = paravirt_read_msr(msr, &_err);    \
 } while(0)
-#define wrmsrl(msr,val)         ((void)paravirt_write_msr(msr, val, 0))
+#define wrmsrl(msr,val)         wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
 #define wrmsr_safe(msr,a,b)     paravirt_write_msr(msr, a, b)
 /* rdmsr with exception handling */
diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h
index 2394589786ba..628fa7747d0c 100644
--- a/include/asm-i386/pgtable.h
+++ b/include/asm-i386/pgtable.h
@@ -285,32 +285,36 @@ static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep)
 */
 #define  __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 #define ptep_set_access_flags(vma, address, ptep, entry, dirty)         \
-do {                                                                    \
+({                                                                      \
-        if (dirty) {                                                    \
+        int __changed = !pte_same(*(ptep), entry);                      \
+        if (__changed && dirty) {                                       \
                (ptep)->pte_low = (entry).pte_low;                      \
                pte_update_defer((vma)->vm_mm, (address), (ptep));      \
                flush_tlb_page(vma, address);                           \
        }                                                               \
-} while (0)
+        __changed;                                                      \
+})
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 #define ptep_test_and_clear_dirty(vma, addr, ptep) ({                   \
-        int ret = 0;                                                    \
+        int __ret = 0;                                                  \
-        if (pte_dirty(*ptep))                                           \
+        if (pte_dirty(*(ptep)))                                         \
-                ret = test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte_low); \
+                __ret = test_and_clear_bit(_PAGE_BIT_DIRTY,             \
-        if (ret)                                                        \
+                                                &(ptep)->pte_low);      \
-                pte_update_defer(vma->vm_mm, addr, ptep);               \
+        if (__ret)                                                      \
-        ret;                                                            \
+                pte_update((vma)->vm_mm, addr, ptep);                   \
+        __ret;                                                          \
 })
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 #define ptep_test_and_clear_young(vma, addr, ptep) ({                   \
-        int ret = 0;                                                    \
+        int __ret = 0;                                                  \
-        if (pte_young(*ptep))                                           \
+        if (pte_young(*(ptep)))                                         \
-                ret = test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte_low); \
+                __ret = test_and_clear_bit(_PAGE_BIT_ACCESSED,          \
-        if (ret)                                                        \
+                                                &(ptep)->pte_low);      \
-                pte_update_defer(vma->vm_mm, addr, ptep);               \
+        if (__ret)                                                      \
-        ret;                                                            \
+                pte_update((vma)->vm_mm, addr, ptep);                   \
+        __ret;                                                          \
 })
 /*
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h
index 670b706411b8..6580f31b3135 100644
--- a/include/asm-ia64/pgtable.h
+++ b/include/asm-ia64/pgtable.h
@@ -533,16 +533,23 @@ extern void lazy_mmu_prot_update (pte_t pte);
 * daccess_bit in ivt.S).
 */
 #ifdef CONFIG_SMP
-# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable)       \
+# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
-do {                                                                                    \
+({                                                                      \
-        if (__safely_writable) {                                                        \
+        int __changed = !pte_same(*(__ptep), __entry);                  \
-                set_pte(__ptep, __entry);                                               \
+        if (__changed && __safely_writable) {                           \
-                flush_tlb_page(__vma, __addr);                                          \
+                set_pte(__ptep, __entry);                               \
-        }                                                                               \
+                flush_tlb_page(__vma, __addr);                          \
-} while (0)
+        }                                                               \
+        __changed;                                                      \
+})
 #else
-# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable)       \
+# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
-        ptep_establish(__vma, __addr, __ptep, __entry)
+({                                                                      \
+        int __changed = !pte_same(*(__ptep), __entry);                  \
+        if (__changed)                                                  \
+                ptep_establish(__vma, __addr, __ptep, __entry);         \
+        __changed;                                                      \
+})
 #endif
 #  ifdef CONFIG_VIRTUAL_MEM_MAP
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index 291e8ceed6e6..d3566a298fa4 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -696,8 +696,8 @@ static inline int
 sn_change_coherence(u64 *new_domain, u64 *old_domain)
 {
        struct ia64_sal_retval ret_stuff;
-        ia64_sal_oemcall(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain,
+        ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain,
-                         (u64)old_domain, 0, 0, 0, 0, 0);
+                                (u64)old_domain, 0, 0, 0, 0, 0);
        return ret_stuff.status;
 }
diff --git a/include/asm-ia64/termbits.h b/include/asm-ia64/termbits.h
index 4531a511bde5..7fae3109ef47 100644
--- a/include/asm-ia64/termbits.h
+++ b/include/asm-ia64/termbits.h
@@ -26,6 +26,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-m32r/termbits.h b/include/asm-m32r/termbits.h
index e402641dfbad..6be3b8a39841 100644
--- a/include/asm-m32r/termbits.h
+++ b/include/asm-m32r/termbits.h
@@ -17,6 +17,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-m68k/termbits.h b/include/asm-m68k/termbits.h
index a194092240fb..0e520f328f53 100644
--- a/include/asm-m68k/termbits.h
+++ b/include/asm-m68k/termbits.h
@@ -17,6 +17,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index c6275088cf65..0b3ff9c48409 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -129,28 +129,12 @@
 #define PHYS_TO_XKPHYS(cm,a)            (_CONST64_(0x8000000000000000) | \
                                         ((cm)<<59) | (a))
-#if defined (CONFIG_CPU_R4300)                                          \
+/*
-    || defined (CONFIG_CPU_R4X00)                                       \
+ * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
-    || defined (CONFIG_CPU_R5000)                                       \
+ * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
-    || defined (CONFIG_CPU_RM7000)                                      \
+ * R8000 implements most with its 48-bit physical address space.
-    || defined (CONFIG_CPU_NEVADA)                                      \
+ */
-    || defined (CONFIG_CPU_TX49XX)                                      \
+#define TO_PHYS_MASK    _CONST64_(0x07ffffffffffffff)   /* 2^^59 - 1 */
-    || defined (CONFIG_CPU_MIPS64)
-#define TO_PHYS_MASK    _CONST64_(0x0000000fffffffff)   /* 2^^36 - 1 */
-#endif
-#if defined (CONFIG_CPU_R8000)
-/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
-#define TO_PHYS_MASK    _CONST64_(0x000000ffffffffff)   /* 2^^40 - 1 */
-#endif
-#if defined (CONFIG_CPU_R10000)
-#define TO_PHYS_MASK    _CONST64_(0x000000ffffffffff)   /* 2^^40 - 1 */
-#endif
-#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
-#define TO_PHYS_MASK    _CONST64_(0x00000fffffffffff)   /* 2^^44 - 1 */
-#endif
 #ifndef CONFIG_CPU_R8000
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index ffe245b4258f..d9e81af53f78 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -310,7 +310,7 @@ static inline int test_and_clear_bit(unsigned long nr,
        if (cpu_has_llsc && R10000_LLSC_WAR) {
                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp, res;
+                unsigned long temp;
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b0c329783ac5..087126a5faf9 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -109,18 +109,12 @@
 #define  MACH_COSINE_ORION      0
 /*
- * Valid machtype for group GALILEO
- */
-#define MACH_GROUP_GALILEO     11       /* Galileo Eval Boards          */
-#define  MACH_EV64120A          0       /* EV64120A */
-/*
 * Valid machtype for group MOMENCO
 */
 #define MACH_GROUP_MOMENCO      12      /* Momentum Boards              */
 #define  MACH_MOMENCO_OCELOT    0
 #define  MACH_MOMENCO_OCELOT_G  1       /* no more supported (may 2007) */
-#define  MACH_MOMENCO_OCELOT_C  2
+#define  MACH_MOMENCO_OCELOT_C  2       /* no more supported (jun 2007) */
 #define  MACH_MOMENCO_JAGUAR_ATX 3      /* no more supported (may 2007) */
 #define  MACH_MOMENCO_OCELOT_3  4
@@ -194,13 +188,6 @@
 #define  MACH_HP_LASERJET       1
 /*
- * Valid machtype for group LASAT
- */
-#define MACH_GROUP_LASAT       21
-#define  MACH_LASAT_100         0       /* Masquerade II/SP100/SP50/SP25 */
-#define  MACH_LASAT_200         1       /* Masquerade PRO/SP200 */
-/*
 * Valid machtype for group TITAN
 */
 #define MACH_GROUP_TITAN       22       /* PMC-Sierra Titan             */
@@ -213,6 +200,27 @@
 #define MACH_GROUP_NEC_EMMA2RH 25       /* NEC EMMA2RH (was 23)         */
 #define  MACH_NEC_MARKEINS      0       /* NEC EMMA2RH Mark-eins        */
+/*
+ * Valid machtype for group LEMOTE
+ */
+#define MACH_GROUP_LEMOTE          27
+#define  MACH_LEMOTE_FULONG        0
+/*
+ * Valid machtype for group PMC-MSP
+ */
+#define MACH_GROUP_MSP         26       /* PMC-Sierra MSP boards/CPUs    */
+#define MACH_MSP4200_EVAL       0       /* PMC-Sierra MSP4200 Evaluation */
+#define MACH_MSP4200_GW         1       /* PMC-Sierra MSP4200 Gateway demo */
+#define MACH_MSP4200_FPGA       2       /* PMC-Sierra MSP4200 Emulation */
+#define MACH_MSP7120_EVAL       3       /* PMC-Sierra MSP7120 Evaluation */
+#define MACH_MSP7120_GW         4       /* PMC-Sierra MSP7120 Residential GW */
+#define MACH_MSP7120_FPGA       5       /* PMC-Sierra MSP7120 Emulation */
+#define MACH_MSP_OTHER        255       /* PMC-Sierra unknown board type */
+#define MACH_GROUP_WINDRIVER   28       /* Windriver boards */
+#define MACH_WRPPMC             1
 #define CL_SIZE                 COMMAND_LINE_SIZE
 const char *get_system_type(void);
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
index c4a1ec31ff6a..df7f2deb3b56 100644
--- a/include/asm-mips/cacheops.h
+++ b/include/asm-mips/cacheops.h
@@ -20,7 +20,11 @@
 #define Index_Load_Tag_D        0x05
 #define Index_Store_Tag_I       0x08
 #define Index_Store_Tag_D       0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I        0x00
+#else
 #define Hit_Invalidate_I        0x10
+#endif
 #define Hit_Invalidate_D        0x11
 #define Hit_Writeback_Inv_D     0x15
diff --git a/include/asm-mips/compat-signal.h b/include/asm-mips/compat-signal.h
index 6599a901b63e..368a99e5c3e1 100644
--- a/include/asm-mips/compat-signal.h
+++ b/include/asm-mips/compat-signal.h
@@ -10,6 +10,68 @@
 #include <asm/uaccess.h>
+#define SI_PAD_SIZE32   ((SI_MAX_SIZE/sizeof(int)) - 3)
+typedef struct compat_siginfo {
+        int si_signo;
+        int si_code;
+        int si_errno;
+        union {
+                int _pad[SI_PAD_SIZE32];
+                /* kill() */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        compat_uid_t _uid;      /* sender's uid */
+                } _kill;
+                /* SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        compat_uid_t _uid;      /* sender's uid */
+                        int _status;            /* exit code */
+                        compat_clock_t _utime;
+                        compat_clock_t _stime;
+                } _sigchld;
+                /* IRIX SIGCHLD */
+                struct {
+                        compat_pid_t _pid;      /* which child */
+                        compat_clock_t _utime;
+                        int _status;            /* exit code */
+                        compat_clock_t _stime;
+                } _irix_sigchld;
+                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
+                struct {
+                        s32 _addr; /* faulting insn/memory ref. */
+                } _sigfault;
+                /* SIGPOLL, SIGXFSZ (To do ...)  */
+                struct {
+                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        int _fd;
+                } _sigpoll;
+                /* POSIX.1b timers */
+                struct {
+                        timer_t _tid;           /* timer id */
+                        int _overrun;           /* overrun count */
+                        compat_sigval_t _sigval;/* same as below */
+                        int _sys_private;       /* not to be passed to user */
+                } _timer;
+                /* POSIX.1b signals */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        compat_uid_t _uid;      /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+        } _sifields;
+} compat_siginfo_t;
 static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
        const sigset_t *s)
 {
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 5e4bed123b48..d95a83e3e1d7 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -150,6 +150,10 @@
 #define cpu_has_mipsmt          (cpu_data[0].ases & MIPS_ASE_MIPSMT)
 #endif
+#ifndef cpu_has_userlocal
+#define cpu_has_userlocal       (cpu_data[0].options & MIPS_CPU_ULRI)
+#endif
 #ifdef CONFIG_32BIT
 # ifndef cpu_has_nofpuex
 # define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index d38fdbf845b2..3857358fb6de 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -89,6 +89,8 @@
 #define PRID_IMP_34K            0x9500
 #define PRID_IMP_24KE           0x9600
 #define PRID_IMP_74K            0x9700
+#define PRID_IMP_LOONGSON1      0x4200
+#define PRID_IMP_LOONGSON2      0x6300
 /*
 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -107,6 +109,7 @@
 * Definitions for 7:0 on legacy processors
 */
+#define PRID_REV_MASK           0x00ff
 #define PRID_REV_TX4927         0x0022
 #define PRID_REV_TX4937         0x0030
@@ -123,6 +126,18 @@
 #define PRID_REV_VR4122         0x0070
 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
 #define PRID_REV_VR4130         0x0080
+#define PRID_REV_34K_V1_0_2     0x0022
+/*
+ * Older processors used to encode processor version and revision in two
+ * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
+ * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
+ * the patch number.  *ARGH*
+ */
+#define PRID_REV_ENCODE_44(ver, rev)                                    \
+        ((ver) << 4 | (rev))
+#define PRID_REV_ENCODE_332(ver, rev, patch)                            \
+        ((ver) << 5 | (rev) << 2 | (patch))
 /*
 * FPU implementation/revision register (CP1 control register 0).
@@ -200,7 +215,10 @@
 #define CPU_SB1A                62
 #define CPU_74K                 63
 #define CPU_R14000              64
-#define CPU_LAST                64
+#define CPU_LOONGSON1           65
+#define CPU_LOONGSON2           66
+#define CPU_LAST                66
 /*
 * ISA Level encodings
@@ -246,6 +264,7 @@
 #define MIPS_CPU_PREFETCH       0x00080000 /* CPU has usable prefetch */
 #define MIPS_CPU_VINT           0x00100000 /* CPU supports MIPSR2 vectored interrupts */
 #define MIPS_CPU_VEIC           0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */
+#define MIPS_CPU_ULRI           0x00400000 /* CPU has ULRI feature */
 /*
 * CPU ASE encodings
diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h
index 66189f5f6399..716371bd0980 100644
--- a/include/asm-mips/div64.h
+++ b/include/asm-mips/div64.h
@@ -20,7 +20,7 @@
 */
 #define do_div64_32(res, high, low, base) ({ \
-        unsigned long __quot, __mod; \
+        unsigned long __quot32, __mod32; \
        unsigned long __cf, __tmp, __tmp2, __i; \
        \
        __asm__(".set   push\n\t" \
@@ -48,12 +48,13 @@
                "bnez   %4, 0b\n\t" \
                " srl   %5, %1, 0x1f\n\t" \
                ".set   pop" \
-                : "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \
+                : "=&r" (__mod32), "=&r" (__tmp), \
+                  "=&r" (__quot32), "=&r" (__cf), \
                  "=&r" (__i), "=&r" (__tmp2) \
                : "Jr" (base), "0" (high), "1" (low)); \
        \
-        (res) = __quot; \
+        (res) = __quot32; \
-        __mod; })
+        __mod32; })
 #define do_div(n, base) ({ \
        unsigned long long __quot; \
diff --git a/include/asm-mips/gpio.h b/include/asm-mips/gpio.h
new file mode 100644
index 000000000000..06e46faf862d
--- /dev/null
+++ b/include/asm-mips/gpio.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_MIPS_GPIO_H
+#define __ASM_MIPS_GPIO_H
+#include <gpio.h>
+#endif /* __ASM_MIPS_GPIO_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 92ec2618560c..12bcc1f9fba9 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -178,6 +178,11 @@ extern void __iounmap(const volatile void __iomem *addr);
 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
        unsigned long flags)
 {
+        void __iomem *addr = plat_ioremap(offset, size, flags);
+        if (addr)
+                return addr;
 #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
        if (cpu_has_64bit_addresses) {
@@ -282,6 +287,9 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
 static inline void iounmap(const volatile void __iomem *addr)
 {
+        if (plat_iounmap(addr))
+                return;
 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
        if (cpu_has_64bit_addresses ||
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 91803ba30ff2..3ca6a076124d 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -72,4 +72,13 @@ extern int allocate_irqno(void);
 extern void alloc_legacy_irqno(void);
 extern void free_irqno(unsigned int irq);
+/*
+ * Before R2 the timer and performance counter interrupts were both fixed to
+ * IE7.  Since R2 their number has to be read from the c0_intctl register.
+ */
+#define CP0_LEGACY_COMPARE_IRQ 7
+extern int cp0_compare_irq;
+extern int cp0_perfcount_irq;
 #endif /* _ASM_IRQ_H */
diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h
deleted file mode 100644
index edcd7544b358..000000000000
--- a/include/asm-mips/lasat/ds1603.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#include <asm/addrspace.h>
-/* Lasat 100    */
-#define DS1603_REG_100          (KSEG1ADDR(0x1c810000))
-#define DS1603_RST_100          (1 << 2)
-#define DS1603_CLK_100          (1 << 0)
-#define DS1603_DATA_SHIFT_100   1
-#define DS1603_DATA_100         (1 << DS1603_DATA_SHIFT_100)
-/* Lasat 200    */
-#define DS1603_REG_200          (KSEG1ADDR(0x11000000))
-#define DS1603_RST_200          (1 << 3)
-#define DS1603_CLK_200          (1 << 4)
-#define DS1603_DATA_200         (1 << 5)
-#define DS1603_DATA_REG_200             (DS1603_REG_200 + 0x10000)
-#define DS1603_DATA_READ_SHIFT_200      9
-#define DS1603_DATA_READ_200    (1 << DS1603_DATA_READ_SHIFT_200)
diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h
deleted file mode 100644
index 7b53edd5cd5f..000000000000
--- a/include/asm-mips/lasat/eeprom.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#include <asm/addrspace.h>
-/* lasat 100 */
-#define AT93C_REG_100               KSEG1ADDR(0x1c810000)
-#define AT93C_RDATA_REG_100         AT93C_REG_100
-#define AT93C_RDATA_SHIFT_100       4
-#define AT93C_WDATA_SHIFT_100       4
-#define AT93C_CS_M_100              ( 1 << 5 )
-#define AT93C_CLK_M_100             ( 1 << 3 )
-/* lasat 200 */
-#define AT93C_REG_200           KSEG1ADDR(0x11000000)
-#define AT93C_RDATA_REG_200     (AT93C_REG_200+0x10000)
-#define AT93C_RDATA_SHIFT_200   8
-#define AT93C_WDATA_SHIFT_200   2
-#define AT93C_CS_M_200          ( 1 << 0 )
-#define AT93C_CLK_M_200         ( 1 << 1 )
diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h
deleted file mode 100644
index f5589f31a197..000000000000
--- a/include/asm-mips/lasat/head.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Image header stuff
- */
-#ifndef _HEAD_H
-#define _HEAD_H
-#define LASAT_K_MAGIC0_VAL      0xfedeabba
-#define LASAT_K_MAGIC1_VAL      0x00bedead
-#ifndef _LANGUAGE_ASSEMBLY
-#include <linux/types.h>
-struct bootloader_header {
-        u32 magic[2];
-        u32 version;
-        u32 image_start;
-        u32 image_size;
-        u32 kernel_start;
-        u32 kernel_entry;
-};
-#endif
-#endif /* _HEAD_H */
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
deleted file mode 100644
index 42077e367a5b..000000000000
--- a/include/asm-mips/lasat/lasat.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * lasat.h
- *
- * Thomas Horsten <thh@lasat.com>
- * Copyright (C) 2000 LASAT Networks A/S.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Configuration for LASAT boards, loads the appropriate include files.
- */
-#ifndef _LASAT_H
-#define _LASAT_H
-#ifndef _LANGUAGE_ASSEMBLY
-extern struct lasat_misc {
-        volatile u32 *reset_reg;
-        volatile u32 *flash_wp_reg;
-        u32 flash_wp_bit;
-} *lasat_misc;
-enum lasat_mtdparts {
-        LASAT_MTD_BOOTLOADER,
-        LASAT_MTD_SERVICE,
-        LASAT_MTD_NORMAL,
-        LASAT_MTD_CONFIG,
-        LASAT_MTD_FS,
-        LASAT_MTD_LAST
-};
-/*
- * The format of the data record in the EEPROM.
- * See Documentation/LASAT/eeprom.txt for a detailed description
- * of the fields in this struct, and the LASAT Hardware Configuration
- * field specification for a detailed description of the config
- * field.
- */
-#include <linux/types.h>
-#define LASAT_EEPROM_VERSION 7
-struct lasat_eeprom_struct {
-        unsigned int  version;
-        unsigned int  cfg[3];
-        unsigned char hwaddr[6];
-        unsigned char print_partno[12];
-        unsigned char term0;
-        unsigned char print_serial[14];
-        unsigned char term1;
-        unsigned char prod_partno[12];
-        unsigned char term2;
-        unsigned char prod_serial[14];
-        unsigned char term3;
-        unsigned char passwd_hash[16];
-        unsigned char pwdnull;
-        unsigned char vendid;
-        unsigned char ts_ref;
-        unsigned char ts_signoff;
-        unsigned char reserved[11];
-        unsigned char debugaccess;
-        unsigned short prid;
-        unsigned int  serviceflag;
-        unsigned int  ipaddr;
-        unsigned int  netmask;
-        unsigned int  crc32;
-};
-struct lasat_eeprom_struct_pre7 {
-        unsigned int  version;
-        unsigned int  flags[3];
-        unsigned char hwaddr0[6];
-        unsigned char hwaddr1[6];
-        unsigned char print_partno[9];
-        unsigned char term0;
-        unsigned char print_serial[14];
-        unsigned char term1;
-        unsigned char prod_partno[9];
-        unsigned char term2;
-        unsigned char prod_serial[14];
-        unsigned char term3;
-        unsigned char passwd_hash[24];
-        unsigned char pwdnull;
-        unsigned char vendor;
-        unsigned char ts_ref;
-        unsigned char ts_signoff;
-        unsigned char reserved[6];
-        unsigned int  writecount;
-        unsigned int  ipaddr;
-        unsigned int  netmask;
-        unsigned int  crc32;
-};
-/* Configuration descriptor encoding - see the doc for details */
-#define LASAT_W0_DSCTYPE(v)             ( ( (v)         ) & 0xf )
-#define LASAT_W0_BMID(v)                ( ( (v) >> 0x04 ) & 0xf )
-#define LASAT_W0_CPUTYPE(v)             ( ( (v) >> 0x08 ) & 0xf )
-#define LASAT_W0_BUSSPEED(v)            ( ( (v) >> 0x0c ) & 0xf )
-#define LASAT_W0_CPUCLK(v)              ( ( (v) >> 0x10 ) & 0xf )
-#define LASAT_W0_SDRAMBANKSZ(v)         ( ( (v) >> 0x14 ) & 0xf )
-#define LASAT_W0_SDRAMBANKS(v)          ( ( (v) >> 0x18 ) & 0xf )
-#define LASAT_W0_L2CACHE(v)             ( ( (v) >> 0x1c ) & 0xf )
-#define LASAT_W1_EDHAC(v)               ( ( (v)         ) & 0xf )
-#define LASAT_W1_HIFN(v)                ( ( (v) >> 0x04 ) & 0x1 )
-#define LASAT_W1_ISDN(v)                ( ( (v) >> 0x05 ) & 0x1 )
-#define LASAT_W1_IDE(v)                 ( ( (v) >> 0x06 ) & 0x1 )
-#define LASAT_W1_HDLC(v)                ( ( (v) >> 0x07 ) & 0x1 )
-#define LASAT_W1_USVERSION(v)           ( ( (v) >> 0x08 ) & 0x1 )
-#define LASAT_W1_4MACS(v)               ( ( (v) >> 0x09 ) & 0x1 )
-#define LASAT_W1_EXTSERIAL(v)           ( ( (v) >> 0x0a ) & 0x1 )
-#define LASAT_W1_FLASHSIZE(v)           ( ( (v) >> 0x0c ) & 0xf )
-#define LASAT_W1_PCISLOTS(v)            ( ( (v) >> 0x10 ) & 0xf )
-#define LASAT_W1_PCI1OPT(v)             ( ( (v) >> 0x14 ) & 0xf )
-#define LASAT_W1_PCI2OPT(v)             ( ( (v) >> 0x18 ) & 0xf )
-#define LASAT_W1_PCI3OPT(v)             ( ( (v) >> 0x1c ) & 0xf )
-/* Routines specific to LASAT boards */
-#define LASAT_BMID_MASQUERADE2          0
-#define LASAT_BMID_MASQUERADEPRO        1
-#define LASAT_BMID_SAFEPIPE25                   2
-#define LASAT_BMID_SAFEPIPE50                   3
-#define LASAT_BMID_SAFEPIPE100          4
-#define LASAT_BMID_SAFEPIPE5000         5
-#define LASAT_BMID_SAFEPIPE7000         6
-#define LASAT_BMID_SAFEPIPE1000         7
-//#define LASAT_BMID_SAFEPIPE30         7
-//#define LASAT_BMID_SAFEPIPE5100       8
-//#define LASAT_BMID_SAFEPIPE7100       9
-#define LASAT_BMID_UNKNOWN                              0xf
-#define LASAT_MAX_BMID_NAMES                    9   // no larger than 15!
-#define LASAT_HAS_EDHAC                 ( 1 << 0 )
-#define LASAT_EDHAC_FAST                ( 1 << 1 )
-#define LASAT_HAS_EADI                  ( 1 << 2 )
-#define LASAT_HAS_HIFN                  ( 1 << 3 )
-#define LASAT_HAS_ISDN                  ( 1 << 4 )
-#define LASAT_HAS_LEASEDLINE_IF         ( 1 << 5 )
-#define LASAT_HAS_HDC                   ( 1 << 6 )
-#define LASAT_PRID_MASQUERADE2          0
-#define LASAT_PRID_MASQUERADEPRO        1
-#define LASAT_PRID_SAFEPIPE25                   2
-#define LASAT_PRID_SAFEPIPE50                   3
-#define LASAT_PRID_SAFEPIPE100          4
-#define LASAT_PRID_SAFEPIPE5000         5
-#define LASAT_PRID_SAFEPIPE7000         6
-#define LASAT_PRID_SAFEPIPE30                   7
-#define LASAT_PRID_SAFEPIPE5100         8
-#define LASAT_PRID_SAFEPIPE7100         9
-#define LASAT_PRID_SAFEPIPE1110         10
-#define LASAT_PRID_SAFEPIPE3020         11
-#define LASAT_PRID_SAFEPIPE3030         12
-#define LASAT_PRID_SAFEPIPE5020         13
-#define LASAT_PRID_SAFEPIPE5030         14
-#define LASAT_PRID_SAFEPIPE1120         15
-#define LASAT_PRID_SAFEPIPE1130         16
-#define LASAT_PRID_SAFEPIPE6010         17
-#define LASAT_PRID_SAFEPIPE6110         18
-#define LASAT_PRID_SAFEPIPE6210         19
-#define LASAT_PRID_SAFEPIPE1020         20
-#define LASAT_PRID_SAFEPIPE1040         21
-#define LASAT_PRID_SAFEPIPE1060         22
-struct lasat_info {
-        unsigned int  li_cpu_hz;
-        unsigned int  li_bus_hz;
-        unsigned int  li_bmid;
-        unsigned int  li_memsize;
-        unsigned int  li_flash_size;
-        unsigned int  li_prid;
-        unsigned char li_bmstr[16];
-        unsigned char li_namestr[32];
-        unsigned char li_typestr[16];
-        /* Info on the Flash layout */
-        unsigned int  li_flash_base;
-        unsigned long li_flashpart_base[LASAT_MTD_LAST];
-        unsigned long li_flashpart_size[LASAT_MTD_LAST];
-        struct lasat_eeprom_struct li_eeprom_info;
-        unsigned int  li_eeprom_upgrade_version;
-        unsigned int  li_debugaccess;
-};
-extern struct lasat_info lasat_board_info;
-static inline unsigned long lasat_flash_partition_start(int partno)
-{
-        if (partno < 0 || partno >= LASAT_MTD_LAST)
-                return 0;
-        return lasat_board_info.li_flashpart_base[partno];
-}
-static inline unsigned long lasat_flash_partition_size(int partno)
-{
-        if (partno < 0 || partno >= LASAT_MTD_LAST)
-                return 0;
-        return lasat_board_info.li_flashpart_size[partno];
-}
-/* Called from setup() to initialize the global board_info struct */
-extern int lasat_init_board_info(void);
-/* Write the modified EEPROM info struct */
-extern void lasat_write_eeprom_info(void);
-#define N_MACHTYPES             2
-/* for calibration of delays */
-/* the lasat_ndelay function is necessary because it is used at an
- * early stage of the boot process where ndelay is not calibrated.
- * It is used for the bit-banging rtc and eeprom drivers */
-#include <asm/delay.h>
-/* calculating with the slowest board with 100 MHz clock */
-#define LASAT_100_DIVIDER 20
-/* All 200's run at 250 MHz clock */
-#define LASAT_200_DIVIDER 8
-extern unsigned int lasat_ndelay_divider;
-static inline void lasat_ndelay(unsigned int ns)
-{
-            __delay(ns / lasat_ndelay_divider);
-}
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
-#define LASAT_SERVICEMODE_MAGIC_1     0xdeadbeef
-#define LASAT_SERVICEMODE_MAGIC_2     0xfedeabba
-/* Lasat 100 boards */
-#define LASAT_GT_BASE           (KSEG1ADDR(0x14000000))
-/* Lasat 200 boards */
-#define Vrc5074_PHYS_BASE       0x1fa00000
-#define Vrc5074_BASE            (KSEG1ADDR(Vrc5074_PHYS_BASE))
-#define PCI_WINDOW1             0x1a000000
-#endif /* _LASAT_H */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
deleted file mode 100644
index 065474feeccc..000000000000
--- a/include/asm-mips/lasat/lasatint.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#define LASATINT_END 16
-/* lasat 100 */
-#define LASAT_INT_STATUS_REG_100        (KSEG1ADDR(0x1c880000))
-#define LASAT_INT_MASK_REG_100          (KSEG1ADDR(0x1c890000))
-#define LASATINT_MASK_SHIFT_100         0
-/* lasat 200 */
-#define LASAT_INT_STATUS_REG_200        (KSEG1ADDR(0x1104003c))
-#define LASAT_INT_MASK_REG_200          (KSEG1ADDR(0x1104003c))
-#define LASATINT_MASK_SHIFT_200         16
diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h
deleted file mode 100644
index 42a492edc40e..000000000000
--- a/include/asm-mips/lasat/picvue.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Lasat 100 */
-#define PVC_REG_100             KSEG1ADDR(0x1c820000)
-#define PVC_DATA_SHIFT_100      0
-#define PVC_DATA_M_100          0xFF
-#define PVC_E_100               (1 << 8)
-#define PVC_RW_100              (1 << 9)
-#define PVC_RS_100              (1 << 10)
-/* Lasat 200 */
-#define PVC_REG_200             KSEG1ADDR(0x11000000)
-#define PVC_DATA_SHIFT_200      24
-#define PVC_DATA_M_200          (0xFF << PVC_DATA_SHIFT_200)
-#define PVC_E_200               (1 << 16)
-#define PVC_RW_200              (1 << 17)
-#define PVC_RS_200              (1 << 18)
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
deleted file mode 100644
index 9e88c7669c7a..000000000000
--- a/include/asm-mips/lasat/serial.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#include <asm/lasat/lasat.h>
-/* Lasat 100 boards serial configuration */
-#define LASAT_BASE_BAUD_100             ( 7372800 / 16 )
-#define LASAT_UART_REGS_BASE_100        0x1c8b0000
-#define LASAT_UART_REGS_SHIFT_100       2
-#define LASATINT_UART_100               8
-/* * LASAT 200 boards serial configuration */
-#define LASAT_BASE_BAUD_200             (100000000 / 16 / 12)
-#define LASAT_UART_REGS_BASE_200        (Vrc5074_PHYS_BASE + 0x0300)
-#define LASAT_UART_REGS_SHIFT_200       3
-#define LASATINT_UART_200               13
diff --git a/include/asm-mips/mach-au1x00/au1xxx_gpio.h b/include/asm-mips/mach-au1x00/au1xxx_gpio.h
deleted file mode 100644
index 27911e054ffc..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_gpio.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __AU1XXX_GPIO_H
-#define __AU1XXX_GPIO_H
-void au1xxx_gpio1_set_inputs(void);
-void au1xxx_gpio_tristate(int signal);
-void au1xxx_gpio_write(int signal, int value);
-int  au1xxx_gpio_read(int signal);
-typedef volatile struct
-{
-        u32 dir;
-        u32 reserved;
-        u32 output;
-        u32 pinstate;
-        u32 inten;
-        u32 enable;
-} AU1X00_GPIO2;
-#endif //__AU1XXX_GPIO_H
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
index 8fcae21adbd5..4663e8b415c9 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -88,26 +88,26 @@ static const struct drive_list_entry dma_white_list [] = {
 /*
 * Hitachi
 */
-        { "HITACHI_DK14FA-20"    ,       "ALL"           },
+        { "HITACHI_DK14FA-20"    ,       NULL            },
-        { "HTS726060M9AT00"      ,       "ALL"           },
+        { "HTS726060M9AT00"      ,       NULL            },
 /*
 * Maxtor
 */
-        { "Maxtor 6E040L0"      ,       "ALL"           },
+        { "Maxtor 6E040L0"      ,       NULL            },
-        { "Maxtor 6Y080P0"      ,       "ALL"           },
+        { "Maxtor 6Y080P0"      ,       NULL            },
-        { "Maxtor 6Y160P0"      ,       "ALL"           },
+        { "Maxtor 6Y160P0"      ,       NULL            },
 /*
 * Seagate
 */
-        { "ST3120026A"          ,       "ALL"           },
+        { "ST3120026A"          ,       NULL            },
-        { "ST320014A"           ,       "ALL"           },
+        { "ST320014A"           ,       NULL            },
-        { "ST94011A"            ,       "ALL"           },
+        { "ST94011A"            ,       NULL            },
-        { "ST340016A"           ,       "ALL"           },
+        { "ST340016A"           ,       NULL            },
 /*
 * Western Digital
 */
-        { "WDC WD400UE-00HCT0"  ,       "ALL"           },
+        { "WDC WD400UE-00HCT0"  ,       NULL            },
-        { "WDC WD400JB-00JJC0"  ,       "ALL"           },
+        { "WDC WD400JB-00JJC0"  ,       NULL            },
        { NULL                  ,       NULL            }
 };
@@ -116,9 +116,9 @@ static const struct drive_list_entry dma_black_list [] = {
 /*
 * Western Digital
 */
-        { "WDC WD100EB-00CGH0"  ,       "ALL"           },
+        { "WDC WD100EB-00CGH0"  ,       NULL            },
-        { "WDC WD200BB-00AUA1"  ,       "ALL"           },
+        { "WDC WD200BB-00AUA1"  ,       NULL            },
-        { "WDC AC24300L"        ,       "ALL"           },
+        { "WDC AC24300L"        ,       NULL            },
        { NULL                  ,       NULL            }
 };
 #endif
diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h
new file mode 100644
index 000000000000..2dc61e009a08
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/gpio.h
@@ -0,0 +1,69 @@
+#ifndef _AU1XXX_GPIO_H_
+#define _AU1XXX_GPIO_H_
+#include <linux/types.h>
+#define AU1XXX_GPIO_BASE        200
+struct au1x00_gpio2 {
+        u32     dir;
+        u32     reserved;
+        u32     output;
+        u32     pinstate;
+        u32     inten;
+        u32     enable;
+};
+extern int au1xxx_gpio_get_value(unsigned gpio);
+extern void au1xxx_gpio_set_value(unsigned gpio, int value);
+extern int au1xxx_gpio_direction_input(unsigned gpio);
+extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
+/* Wrappers for the arch-neutral GPIO API */
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        /* Not yet implemented */
+        return 0;
+}
+static inline void gpio_free(unsigned gpio)
+{
+        /* Not yet implemented */
+}
+static inline int gpio_direction_input(unsigned gpio)
+{
+        return au1xxx_gpio_direction_input(gpio);
+}
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        return au1xxx_gpio_direction_output(gpio, value);
+}
+static inline int gpio_get_value(unsigned gpio)
+{
+        return au1xxx_gpio_get_value(gpio);
+}
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        au1xxx_gpio_set_value(gpio, value);
+}
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return gpio;
+}
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq;
+}
+/* For cansleep */
+#include <asm-generic/gpio.h>
+#endif /* _AU1XXX_GPIO_H_ */
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h
index 098fca4289bb..364cea2dc71f 100644
--- a/include/asm-mips/mach-au1x00/ioremap.h
+++ b/include/asm-mips/mach-au1x00/ioremap.h
@@ -28,4 +28,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
        return __fixup_bigphys_addr(phys_addr, size);
 }
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+        return NULL;
+}
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return 0;
+}
 #endif /* __ASM_MACH_AU1X00_IOREMAP_H */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index 684a501c04cf..9c9d2b998ca4 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -30,7 +30,6 @@
 #define COBALT_CPU_IRQ          MIPS_CPU_IRQ_BASE
 #define COBALT_GALILEO_IRQ      (COBALT_CPU_IRQ + 2)
-#define COBALT_SCC_IRQ          (COBALT_CPU_IRQ + 3)    /* pre-production has 85C30 */
 #define COBALT_RAQ_SCSI_IRQ     (COBALT_CPU_IRQ + 3)
 #define COBALT_ETH0_IRQ         (COBALT_CPU_IRQ + 3)
 #define COBALT_QUBE1_ETH0_IRQ   (COBALT_CPU_IRQ + 4)
@@ -71,10 +70,6 @@
 extern int cobalt_board_id;
-#define PCI_CFG_SET(devfn,where)                                        \
-        GT_WRITE(GT_PCI0_CFGADDR_OFS, (0x80000000 | (PCI_SLOT (devfn) << 11) |          \
-                (PCI_FUNC (devfn) << 8) | (where)))
 #define COBALT_LED_PORT         (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
 # define COBALT_LED_BAR_LEFT    (1 << 0)        /* Qube */
 # define COBALT_LED_BAR_RIGHT   (1 << 1)        /* Qube */
diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h
deleted file mode 100644
index 7e272ce57ea3..000000000000
--- a/include/asm-mips/mach-ev64120/mach-gt64120.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- *  This is a direct copy of the ev96100.h file, with a global
- * search and replace.  The numbers are the same.
- *
- *  The reason I'm duplicating this is so that the 64120/96100
- * defines won't be confusing in the source code.
- */
-#ifndef __ASM_GALILEO_BOARDS_MIPS_EV64120_H
-#define __ASM_GALILEO_BOARDS_MIPS_EV64120_H
-/*
- *   GT64120 config space base address
- */
-extern unsigned long gt64120_base;
-#define GT64120_BASE    (gt64120_base)
-/*
- *   PCI Bus allocation
- */
-#define GT_PCI_MEM_BASE 0x12000000UL
-#define GT_PCI_MEM_SIZE 0x02000000UL
-#define GT_PCI_IO_BASE  0x10000000UL
-#define GT_PCI_IO_SIZE  0x02000000UL
-#define GT_ISA_IO_BASE  PCI_IO_BASE
-/*
- *   Duart I/O ports.
- */
-#define EV64120_COM1_BASE_ADDR  (0x1d000000 + 0x20)
-#define EV64120_COM2_BASE_ADDR  (0x1d000000 + 0x00)
-/*
- *   EV64120 interrupt controller register base.
- */
-#define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
-/*
- *   EV64120 UART register base.
- */
-#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
-#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
-#define EV64120_BASE_BAUD ( 3686400 / 16 )
-#define EV64120_UART_IRQ        6
-/*
- * PCI interrupts will come in on either the INTA or INTD interrups lines,
- * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our
- * boards, they all either come in on IntD or they all come in on IntA, they
- * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
- * "requested" interrupt numbers and go through the list whenever we get an
- * IntA/D.
- *
- * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
- * INTD is 11.
- */
-#define GT_TIMER        4
-#define GT_INTA         2
-#define GT_INTD         5
-#endif /* __ASM_GALILEO_BOARDS_MIPS_EV64120_H */
diff --git a/include/asm-mips/mach-generic/gpio.h b/include/asm-mips/mach-generic/gpio.h
new file mode 100644
index 000000000000..6eaf5efedf3a
--- /dev/null
+++ b/include/asm-mips/mach-generic/gpio.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_MACH_GENERIC_GPIO_H
+#define __ASM_MACH_GENERIC_GPIO_H
+int gpio_request(unsigned gpio, const char *label);
+void gpio_free(unsigned gpio);
+int gpio_direction_input(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_value(unsigned gpio, int value);
+int gpio_to_irq(unsigned gpio);
+int irq_to_gpio(unsigned irq);
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+#endif /* __ASM_MACH_GENERIC_GPIO_H */
diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h
index 9b64ff6e485d..b379938d47f0 100644
--- a/include/asm-mips/mach-generic/ioremap.h
+++ b/include/asm-mips/mach-generic/ioremap.h
@@ -20,4 +20,15 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
        return phys_addr;
 }
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+        return NULL;
+}
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return 0;
+}
 #endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
index 0ae9997bc9a8..c9fa4b14968d 100644
--- a/include/asm-mips/mach-generic/spaces.h
+++ b/include/asm-mips/mach-generic/spaces.h
@@ -10,38 +10,54 @@
 #ifndef _ASM_MACH_GENERIC_SPACES_H
 #define _ASM_MACH_GENERIC_SPACES_H
+#include <linux/const.h>
+/*
+ * This gives the physical RAM offset.
+ */
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET             _AC(0, UL)
+#endif
 #ifdef CONFIG_32BIT
-#define CAC_BASE                0x80000000
+#define CAC_BASE                _AC(0x80000000, UL)
-#define IO_BASE                 0xa0000000
+#define IO_BASE                 _AC(0xa0000000, UL)
-#define UNCAC_BASE              0xa0000000
+#define UNCAC_BASE              _AC(0xa0000000, UL)
-#define MAP_BASE                0xc0000000
-/*
+#ifndef MAP_BASE
- * This handles the memory map.
+#define MAP_BASE                _AC(0xc0000000, UL)
- * We handle pages at KSEG0 for kernels with 32 bit address space.
+#endif
- */
-#define PAGE_OFFSET             0x80000000UL
 /*
 * Memory above this physical address will be considered highmem.
 */
 #ifndef HIGHMEM_START
-#define HIGHMEM_START           0x20000000UL
+#define HIGHMEM_START           _AC(0x20000000, UL)
 #endif
 #endif /* CONFIG_32BIT */
 #ifdef CONFIG_64BIT
-/*
+#ifndef CAC_BASE
- * This handles the memory map.
- */
 #ifdef CONFIG_DMA_NONCOHERENT
-#define PAGE_OFFSET     0x9800000000000000UL
+#define CAC_BASE                _AC(0x9800000000000000, UL)
 #else
-#define PAGE_OFFSET     0xa800000000000000UL
+#define CAC_BASE                _AC(0xa800000000000000, UL)
+#endif
+#endif
+#ifndef IO_BASE
+#define IO_BASE                 _AC(0x9000000000000000, UL)
+#endif
+#ifndef UNCAC_BASE
+#define UNCAC_BASE              _AC(0x9000000000000000, UL)
+#endif
+#ifndef MAP_BASE
+#define MAP_BASE                _AC(0xc000000000000000, UL)
 #endif
 /*
@@ -50,22 +66,20 @@
 * in the distant future.  Nobody will care for a few years :-)
 */
 #ifndef HIGHMEM_START
-#define HIGHMEM_START           (1UL << 59UL)
+#define HIGHMEM_START           (_AC(1, UL) << _AC(59, UL))
 #endif
-#ifdef CONFIG_DMA_NONCOHERENT
-#define CAC_BASE                0x9800000000000000UL
-#else
-#define CAC_BASE                0xa800000000000000UL
-#endif
-#define IO_BASE                 0x9000000000000000UL
-#define UNCAC_BASE              0x9000000000000000UL
-#define MAP_BASE                0xc000000000000000UL
 #define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
 #define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 #endif /* CONFIG_64BIT */
+/*
+ * This handles the memory map.
+ */
+#ifndef PAGE_OFFSET
+#define PAGE_OFFSET             (CAC_BASE + PHYS_OFFSET)
+#endif
 #endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
index ab20c026fd19..7f9fa6f66059 100644
--- a/include/asm-mips/mach-ip22/spaces.h
+++ b/include/asm-mips/mach-ip22/spaces.h
@@ -11,44 +11,17 @@
 #define _ASM_MACH_IP22_SPACES_H
-#ifdef CONFIG_32BIT
-#define CAC_BASE                0x80000000
-#define IO_BASE                 0xa0000000
-#define UNCAC_BASE              0xa0000000
-#define MAP_BASE                0xc0000000
-/*
- * This handles the memory map.
- * We handle pages at KSEG0 for kernels with 32 bit address space.
- */
-#define PAGE_OFFSET             0x80000000UL
-/*
- * Memory above this physical address will be considered highmem.
- */
-#ifndef HIGHMEM_START
-#define HIGHMEM_START           0x20000000UL
-#endif
-#endif /* CONFIG_32BIT */
 #ifdef CONFIG_64BIT
-#define PAGE_OFFSET             0xffffffff80000000UL
-#ifndef HIGHMEM_START
+#define PAGE_OFFSET             0xffffffff80000000UL
-#define HIGHMEM_START           (1UL << 59UL)
-#endif
 #define CAC_BASE                0xffffffff80000000
 #define IO_BASE                 0xffffffffa0000000
 #define UNCAC_BASE              0xffffffffa0000000
 #define MAP_BASE                0xc000000000000000
-#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
-#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
-#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 #endif /* CONFIG_64BIT */
+#include <asm/mach-generic/spaces.h>
 #endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h
index 45e61785ef42..b18802a0b17e 100644
--- a/include/asm-mips/mach-ip27/spaces.h
+++ b/include/asm-mips/mach-ip27/spaces.h
@@ -14,22 +14,17 @@
 * IP27 uses the R10000's uncached attribute feature.  Attribute 3 selects
 * uncached memory addressing.
 */
-#define CAC_BASE                0xa800000000000000
 #define HSPEC_BASE              0x9000000000000000
 #define IO_BASE                 0x9200000000000000
 #define MSPEC_BASE              0x9400000000000000
 #define UNCAC_BASE              0x9600000000000000
-#define MAP_BASE                0xc000000000000000
-#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
-#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
-#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 #define TO_MSPEC(x)             (MSPEC_BASE | ((x) & TO_PHYS_MASK))
 #define TO_HSPEC(x)             (HSPEC_BASE | ((x) & TO_PHYS_MASK))
-#define PAGE_OFFSET             CAC_BASE
 #define HIGHMEM_START           (~0UL)
+#include <asm/mach-generic/spaces.h>
 #endif /* _ASM_MACH_IP27_SPACES_H */
diff --git a/include/asm-mips/mach-ip32/dma-coherence.h b/include/asm-mips/mach-ip32/dma-coherence.h
index c3f9a6a20eb0..a5511ebb2d53 100644
--- a/include/asm-mips/mach-ip32/dma-coherence.h
+++ b/include/asm-mips/mach-ip32/dma-coherence.h
@@ -6,8 +6,8 @@
 * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
 *
 */
-#ifndef __ASM_MACH_IP35_DMA_COHERENCE_H
+#ifndef __ASM_MACH_IP32_DMA_COHERENCE_H
-#define __ASM_MACH_IP35_DMA_COHERENCE_H
+#define __ASM_MACH_IP32_DMA_COHERENCE_H
 #include <asm/ip32/crime.h>
@@ -69,4 +69,4 @@ static inline int plat_device_is_coherent(struct device *dev)
        return 0;               /* IP32 is non-cohernet */
 }
-#endif /* __ASM_MACH_IP35_DMA_COHERENCE_H */
+#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h
deleted file mode 100644
index 44abe5c02389..000000000000
--- a/include/asm-mips/mach-ip32/spaces.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 1999, 2000, 03, 04, 05 Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 2000, 2002  Maciej W. Rozycki
- * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_MACH_IP32_SPACES_H
-#define _ASM_MACH_IP32_SPACES_H
-/*
- * Memory above this physical address will be considered highmem.
- * Fixme: 59 bits is a fictive number and makes assumptions about processors
- * in the distant future.  Nobody will care for a few years :-)
- */
-#ifndef HIGHMEM_START
-#define HIGHMEM_START           (1UL << 59UL)
-#endif
-#define CAC_BASE                0x9800000000000000UL
-#define IO_BASE                 0x9000000000000000UL
-#define UNCAC_BASE              0x9000000000000000UL
-#define MAP_BASE                0xc000000000000000UL
-#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
-#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
-#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
-/*
- * This handles the memory map.
- */
-#define PAGE_OFFSET             CAC_BASE
-#endif /* __ASM_MACH_IP32_SPACES_H */
diff --git a/include/asm-mips/mach-jmr3927/ioremap.h b/include/asm-mips/mach-jmr3927/ioremap.h
new file mode 100644
index 000000000000..aa131ad7f717
--- /dev/null
+++ b/include/asm-mips/mach-jmr3927/ioremap.h
@@ -0,0 +1,38 @@
+/*
+ *      include/asm-mips/mach-jmr3927/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_JMR3927_IOREMAP_H
+#define __ASM_MACH_JMR3927_IOREMAP_H
+#include <linux/types.h>
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+#define TXX9_DIRECTMAP_BASE     0xff000000ul
+        if (offset >= TXX9_DIRECTMAP_BASE &&
+            offset < TXX9_DIRECTMAP_BASE + 0xf0000)
+                return (void __iomem *)offset;
+        return NULL;
+}
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
+}
+#endif /* __ASM_MACH_JMR3927_IOREMAP_H */
diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h
deleted file mode 100644
index 1a9ad45cc135..000000000000
--- a/include/asm-mips/mach-lasat/mach-gt64120.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  This is a direct copy of the ev96100.h file, with a global
- * search and replace.  The numbers are the same.
- *
- *  The reason I'm duplicating this is so that the 64120/96100
- * defines won't be confusing in the source code.
- */
-#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H
-#define _ASM_GT64120_LASAT_GT64120_DEP_H
-/*
- *   GT64120 config space base address on Lasat 100
- */
-#define GT64120_BASE    (KSEG1ADDR(0x14000000))
-/*
- *   PCI Bus allocation
- *
- *   (Guessing ...)
- */
-#define GT_PCI_MEM_BASE 0x12000000UL
-#define GT_PCI_MEM_SIZE 0x02000000UL
-#define GT_PCI_IO_BASE  0x10000000UL
-#define GT_PCI_IO_SIZE  0x02000000UL
-#define GT_ISA_IO_BASE  PCI_IO_BASE
-#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h
new file mode 100644
index 000000000000..7e914777ebc4
--- /dev/null
+++ b/include/asm-mips/mach-lemote/dma-coherence.h
@@ -0,0 +1,42 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006, 07  Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
+ * Author: Fuxin Zhang, zhangfx@lemote.com
+ *
+ */
+#ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H
+#define __ASM_MACH_LEMOTE_DMA_COHERENCE_H
+struct device;
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+                                          size_t size)
+{
+        return virt_to_phys(addr) | 0x80000000;
+}
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+                                               struct page *page)
+{
+        return page_to_phys(page) | 0x80000000;
+}
+static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+{
+        return dma_addr & 0x7fffffff;
+}
+static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
+{
+}
+static inline int plat_device_is_coherent(struct device *dev)
+{
+        return 0;
+}
+#endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h
new file mode 100644
index 000000000000..ed5147e11085
--- /dev/null
+++ b/include/asm-mips/mach-lemote/mc146818rtc.h
@@ -0,0 +1,36 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_LEMOTE_MC146818RTC_H
+#define __ASM_MACH_LEMOTE_MC146818RTC_H
+#include <linux/io.h>
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_IRQ         8
+static inline unsigned char CMOS_READ(unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        return inb_p(RTC_PORT(1));
+}
+static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
+{
+        outb_p(addr, RTC_PORT(0));
+        outb_p(data, RTC_PORT(1));
+}
+#define RTC_ALWAYS_BCD  0
+#ifndef mc146818_decode_year
+#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
+#endif
+#endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */
diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-mips/kernel-entry-init.h
new file mode 100644
index 000000000000..0b793e7bf67e
--- /dev/null
+++ b/include/asm-mips/mach-mips/kernel-entry-init.h
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Chris Dearman (chris@mips.com)
+ * Copyright (C) 2007 Mips Technologies, Inc.
+ */
+#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
+        .macro  kernel_entry_setup
+#ifdef CONFIG_MIPS_MT_SMTC
+        mfc0    t0, CP0_CONFIG
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 1
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 2
+        bgez    t0, 9f
+        mfc0    t0, CP0_CONFIG, 3
+        and     t0, 1<<2
+        bnez    t0, 0f
+9:
+        /* Assume we came from YAMON... */
+        PTR_LA  v0, 0x9fc00534  /* YAMON print */
+        lw      v0, (v0)
+        move    a0, zero
+        PTR_LA  a1, nonmt_processor
+        jal     v0
+        PTR_LA  v0, 0x9fc00520  /* YAMON exit */
+        lw      v0, (v0)
+        li      a0, 1
+        jal     v0
+1:      b       1b
+        __INITDATA
+nonmt_processor:
+        .asciz  "SMTC kernel requires the MT ASE to run\n"
+        __FINIT
+0:
+#endif
+        .endm
+/*
+ * Do SMP slave processor setup necessary before we can safely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h
index 779b02205737..779b02205737 100644
--- a/include/asm-mips/mach-sim/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
deleted file mode 100644
index 57a12ded0613..000000000000
--- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 MontaVista Software Inc.
- * Author: Manish Lachwani, mlachwani@mvista.com
- * Copyright (C) 2004 Ralf Baechle
- */
-#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
-/*
- * Momentum Ocelot-3 is based on Rm7900 processor which
- * is based on the E9000 core.
- */
-#define cpu_has_watch           1
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        1
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_icache_snoops_remote_store  0
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-#define cpu_has_inclusive_pcaches       0
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  32
-#define cpu_scache_line_size()  32
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-tx49xx/ioremap.h b/include/asm-mips/mach-tx49xx/ioremap.h
new file mode 100644
index 000000000000..88cf546719b8
--- /dev/null
+++ b/include/asm-mips/mach-tx49xx/ioremap.h
@@ -0,0 +1,42 @@
+/*
+ *      include/asm-mips/mach-tx49xx/ioremap.h
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_TX49XX_IOREMAP_H
+#define __ASM_MACH_TX49XX_IOREMAP_H
+#include <linux/types.h>
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+        unsigned long flags)
+{
+#ifdef CONFIG_64BIT
+#define TXX9_DIRECTMAP_BASE     0xfff000000ul
+#else
+#define TXX9_DIRECTMAP_BASE     0xff000000ul
+#endif
+        if (offset >= TXX9_DIRECTMAP_BASE &&
+            offset < TXX9_DIRECTMAP_BASE + 0x400000)
+                return (void __iomem *)(unsigned long)(int)offset;
+        return NULL;
+}
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return (unsigned long)addr >= (unsigned long)(int)TXX9_DIRECTMAP_BASE;
+}
+#endif /* __ASM_MACH_TX49XX_IOREMAP_H */
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h
index 76add42e486e..93ba1c1b2a4f 100644
--- a/include/asm-mips/mips-boards/atlasint.h
+++ b/include/asm-mips/mips-boards/atlasint.h
@@ -28,11 +28,6 @@
 #include <irq.h>
-/*
- * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
- */
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
 /* CPU interrupt offsets */
 #define MIPSCPU_INT_SW0         0
 #define MIPSCPU_INT_SW1         1
@@ -42,7 +37,6 @@
 #define MIPSCPU_INT_MB2         4
 #define MIPSCPU_INT_MB3         5
 #define MIPSCPU_INT_MB4         6
-#define MIPSCPU_INT_CPUCTR      7
 /*
 * Interrupts 8..39 are used for Atlas interrupt controller interrupts
diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h
index cd7125610100..dc3fc32eedd8 100644
--- a/include/asm-mips/mips-boards/bonito64.h
+++ b/include/asm-mips/mips-boards/bonito64.h
@@ -26,7 +26,12 @@
 /* offsets from base register */
 #define BONITO(x)       (x)
-#else /* !__ASSEMBLY__ */
+#elif defined(CONFIG_LEMOTE_FULONG)
+#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
+#define BONITO_IRQ_BASE   32
+#else
 /*
 * Algorithmics Bonito64 system controller register base.
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index b98f1658cfd0..c8ebcc3e1267 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -73,12 +73,28 @@
 *  CoreEMUL with   Bonito   System Controller is treated like a Core20K
 *  CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
 */
-#define MIPS_REVISION_CORID_CORE_EMUL_BON  0x63
+#define MIPS_REVISION_CORID_CORE_EMUL_BON  -1
-#define MIPS_REVISION_CORID_CORE_EMUL_MSC  0x65
+#define MIPS_REVISION_CORID_CORE_EMUL_MSC  -2
 #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
-extern unsigned int mips_revision_corid;
+extern int mips_revision_corid;
+#define MIPS_REVISION_SCON_OTHER           0
+#define MIPS_REVISION_SCON_SOCITSC         1
+#define MIPS_REVISION_SCON_SOCITSCP        2
+/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
+#define MIPS_REVISION_SCON_UNKNOWN         -1
+#define MIPS_REVISION_SCON_GT64120         -2
+#define MIPS_REVISION_SCON_BONITO          -3
+#define MIPS_REVISION_SCON_BRTL            -4
+#define MIPS_REVISION_SCON_SOCIT           -5
+#define MIPS_REVISION_SCON_ROCIT           -6
+#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
+extern int mips_revision_sconid;
 #ifdef CONFIG_PCI
 extern void mips_pcibios_init(void);
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
index 9180d6466113..7461318f1cd1 100644
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -32,11 +32,6 @@
 */
 #define MALTA_INT_BASE          0
-/*
- * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
- */
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
 /* CPU interrupt offsets */
 #define MIPSCPU_INT_SW0         0
 #define MIPSCPU_INT_SW1         1
@@ -49,7 +44,6 @@
 #define MIPSCPU_INT_COREHI      MIPSCPU_INT_MB3
 #define MIPSCPU_INT_MB4         6
 #define MIPSCPU_INT_CORELO      MIPSCPU_INT_MB4
-#define MIPSCPU_INT_CPUCTR      7
 /*
 * Interrupts 64..127 are used for Soc-it Classic interrupts
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
index 8eaefb837b9d..e036b7dd6deb 100644
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ b/include/asm-mips/mips-boards/msc01_pci.h
@@ -208,6 +208,7 @@
 * latter, they should be moved elsewhere.
 */
 #define MIPS_MSC01_PCI_REG_BASE         0x1bd00000
+#define MIPS_SOCITSC_PCI_REG_BASE       0x1ff10000
 extern unsigned long _pcictrl_msc;
diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h
index 4f6a3933699d..e710bae07340 100644
--- a/include/asm-mips/mips-boards/seadint.h
+++ b/include/asm-mips/mips-boards/seadint.h
@@ -22,14 +22,7 @@
 #include <irq.h>
-/*
- * Interrupts 0..7 are used for SEAD CPU interrupts
- */
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
 #define MIPSCPU_INT_UART0       2
 #define MIPSCPU_INT_UART1       3
-#define MIPSCPU_INT_CPUCTR      7
 #endif /* !(_MIPS_SEADINT_H) */
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h
index 54f2fe621d69..8ef6db76d5c1 100644
--- a/include/asm-mips/mips-boards/simint.h
+++ b/include/asm-mips/mips-boards/simint.h
@@ -21,15 +21,11 @@
 #define SIM_INT_BASE            0
 #define MIPSCPU_INT_MB0         2
-#define MIPSCPU_INT_BASE        MIPS_CPU_IRQ_BASE
 #define MIPS_CPU_TIMER_IRQ      7
-#define MIPSCPU_INT_CPUCTR      7
 #define MSC01E_INT_BASE         64
-#define MIPSCPU_INT_CPUCTR      7
 #define MSC01E_INT_CPUCTR       11
 #endif
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 9985cb7c16e7..706b3691f57e 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -7,7 +7,7 @@
 * Copyright (C) 2000 Silicon Graphics, Inc.
 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
 * Copyright (C) 2003, 2004  Maciej W. Rozycki
 */
 #ifndef _ASM_MIPSREGS_H
@@ -15,6 +15,7 @@
 #include <linux/linkage.h>
 #include <asm/hazards.h>
+#include <asm/war.h>
 /*
 * The following macros are especially useful for __asm__
@@ -533,6 +534,12 @@
 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
+#define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
+#define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
+#define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 /*
 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
@@ -770,6 +777,9 @@ do {									\
 #define read_c0_context()       __read_ulong_c0_register($4, 0)
 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
+#define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
+#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
@@ -1292,10 +1302,39 @@ static inline void tlb_probe(void)
 static inline void tlb_read(void)
 {
+#if MIPS34K_MISSED_ITLB_WAR
+        int res = 0;
+        __asm__ __volatile__(
+        "       .set    push                                    \n"
+        "       .set    noreorder                               \n"
+        "       .set    noat                                    \n"
+        "       .set    mips32r2                                \n"
+        "       .word   0x41610001              # dvpe $1       \n"
+        "       move    %0, $1                                  \n"
+        "       ehb                                             \n"
+        "       .set    pop                                     \n"
+        : "=r" (res));
+        instruction_hazard();
+#endif
        __asm__ __volatile__(
                ".set noreorder\n\t"
                "tlbr\n\t"
                ".set reorder");
+#if MIPS34K_MISSED_ITLB_WAR
+        if ((res & _ULCAST_(1)))
+                __asm__ __volatile__(
+                "       .set    push                            \n"
+                "       .set    noreorder                       \n"
+                "       .set    noat                            \n"
+                "       .set    mips32r2                        \n"
+                "       .word   0x41600021      # evpe          \n"
+                "       ehb                                     \n"
+                "       .set    pop                             \n");
+#endif
 }
 static inline void tlb_write_indexed(void)
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index 399d03f1c4fc..de6d09ebbd80 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -112,6 +112,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "RM9000 "
 #elif defined CONFIG_CPU_SB1
 #define MODULE_PROC_FAMILY "SB1 "
+#elif defined CONFIG_CPU_LOONGSON2
+#define MODULE_PROC_FAMILY "LOONGSON2 "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
@@ -122,6 +124,13 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_KERNEL_TYPE "64BIT "
 #endif
-#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_KERNEL_TYPE
+#ifdef CONFIG_MIPS_MT_SMTC
+#define MODULE_KERNEL_SMTC "MT_SMTC "
+#else
+#define MODULE_KERNEL_SMTC ""
+#endif
+#define MODULE_ARCH_VERMAGIC \
+        MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC
 #endif /* _ASM_MODULE_H */
diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h
deleted file mode 100644
index c3ca959aa4d9..000000000000
--- a/include/asm-mips/nile4.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- *  asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- *
- *  This file is based on the following documentation:
- *
- *      NEC Vrc 5074 System Controller Data Sheet, June 1998
- */
-#ifndef _ASM_NILE4_H
-#define _ASM_NILE4_H
-#define NILE4_BASE              0xbfa00000
-#define NILE4_SIZE              0x00200000              /* 2 MB */
-    /*
-     *  Physical Device Address Registers (PDARs)
-     */
-#define NILE4_SDRAM0    0x0000  /* SDRAM Bank 0 [R/W] */
-#define NILE4_SDRAM1    0x0008  /* SDRAM Bank 1 [R/W] */
-#define NILE4_DCS2      0x0010  /* Device Chip-Select 2 [R/W] */
-#define NILE4_DCS3      0x0018  /* Device Chip-Select 3 [R/W] */
-#define NILE4_DCS4      0x0020  /* Device Chip-Select 4 [R/W] */
-#define NILE4_DCS5      0x0028  /* Device Chip-Select 5 [R/W] */
-#define NILE4_DCS6      0x0030  /* Device Chip-Select 6 [R/W] */
-#define NILE4_DCS7      0x0038  /* Device Chip-Select 7 [R/W] */
-#define NILE4_DCS8      0x0040  /* Device Chip-Select 8 [R/W] */
-#define NILE4_PCIW0     0x0060  /* PCI Address Window 0 [R/W] */
-#define NILE4_PCIW1     0x0068  /* PCI Address Window 1 [R/W] */
-#define NILE4_INTCS     0x0070  /* Controller Internal Registers and Devices */
-                                /* [R/W] */
-#define NILE4_BOOTCS    0x0078  /* Boot ROM Chip-Select [R/W] */
-    /*
-     *  CPU Interface Registers
-     */
-#define NILE4_CPUSTAT   0x0080  /* CPU Status [R/W] */
-#define NILE4_INTCTRL   0x0088  /* Interrupt Control [R/W] */
-#define NILE4_INTSTAT0  0x0090  /* Interrupt Status 0 [R] */
-#define NILE4_INTSTAT1  0x0098  /* Interrupt Status 1 and CPU Interrupt */
-                                /* Enable [R/W] */
-#define NILE4_INTCLR    0x00A0  /* Interrupt Clear [R/W] */
-#define NILE4_INTPPES   0x00A8  /* PCI Interrupt Control [R/W] */
-    /*
-     *  Memory-Interface Registers
-     */
-#define NILE4_MEMCTRL   0x00C0  /* Memory Control */
-#define NILE4_ACSTIME   0x00C8  /* Memory Access Timing [R/W] */
-#define NILE4_CHKERR    0x00D0  /* Memory Check Error Status [R] */
-    /*
-     *  PCI-Bus Registers
-     */
-#define NILE4_PCICTRL   0x00E0  /* PCI Control [R/W] */
-#define NILE4_PCIARB    0x00E8  /* PCI Arbiter [R/W] */
-#define NILE4_PCIINIT0  0x00F0  /* PCI Master (Initiator) 0 [R/W] */
-#define NILE4_PCIINIT1  0x00F8  /* PCI Master (Initiator) 1 [R/W] */
-#define NILE4_PCIERR    0x00B8  /* PCI Error [R/W] */
-    /*
-     *  Local-Bus Registers
-     */
-#define NILE4_LCNFG     0x0100  /* Local Bus Configuration [R/W] */
-#define NILE4_LCST2     0x0110  /* Local Bus Chip-Select Timing 2 [R/W] */
-#define NILE4_LCST3     0x0118  /* Local Bus Chip-Select Timing 3 [R/W] */
-#define NILE4_LCST4     0x0120  /* Local Bus Chip-Select Timing 4 [R/W] */
-#define NILE4_LCST5     0x0128  /* Local Bus Chip-Select Timing 5 [R/W] */
-#define NILE4_LCST6     0x0130  /* Local Bus Chip-Select Timing 6 [R/W] */
-#define NILE4_LCST7     0x0138  /* Local Bus Chip-Select Timing 7 [R/W] */
-#define NILE4_LCST8     0x0140  /* Local Bus Chip-Select Timing 8 [R/W] */
-#define NILE4_DCSFN     0x0150  /* Device Chip-Select Muxing and Output */
-                                /* Enables [R/W] */
-#define NILE4_DCSIO     0x0158  /* Device Chip-Selects As I/O Bits [R/W] */
-#define NILE4_BCST      0x0178  /* Local Boot Chip-Select Timing [R/W] */
-    /*
-     *  DMA Registers
-     */
-#define NILE4_DMACTRL0  0x0180  /* DMA Control 0 [R/W] */
-#define NILE4_DMASRCA0  0x0188  /* DMA Source Address 0 [R/W] */
-#define NILE4_DMADESA0  0x0190  /* DMA Destination Address 0 [R/W] */
-#define NILE4_DMACTRL1  0x0198  /* DMA Control 1 [R/W] */
-#define NILE4_DMASRCA1  0x01A0  /* DMA Source Address 1 [R/W] */
-#define NILE4_DMADESA1  0x01A8  /* DMA Destination Address 1 [R/W] */
-    /*
-     *  Timer Registers
-     */
-#define NILE4_T0CTRL    0x01C0  /* SDRAM Refresh Control [R/W] */
-#define NILE4_T0CNTR    0x01C8  /* SDRAM Refresh Counter [R/W] */
-#define NILE4_T1CTRL    0x01D0  /* CPU-Bus Read Time-Out Control [R/W] */
-#define NILE4_T1CNTR    0x01D8  /* CPU-Bus Read Time-Out Counter [R/W] */
-#define NILE4_T2CTRL    0x01E0  /* General-Purpose Timer Control [R/W] */
-#define NILE4_T2CNTR    0x01E8  /* General-Purpose Timer Counter [R/W] */
-#define NILE4_T3CTRL    0x01F0  /* Watchdog Timer Control [R/W] */
-#define NILE4_T3CNTR    0x01F8  /* Watchdog Timer Counter [R/W] */
-    /*
-     *  PCI Configuration Space Registers
-     */
-#define NILE4_PCI_BASE  0x0200
-#define NILE4_VID       0x0200  /* PCI Vendor ID [R] */
-#define NILE4_DID       0x0202  /* PCI Device ID [R] */
-#define NILE4_PCICMD    0x0204  /* PCI Command [R/W] */
-#define NILE4_PCISTS    0x0206  /* PCI Status [R/W] */
-#define NILE4_REVID     0x0208  /* PCI Revision ID [R] */
-#define NILE4_CLASS     0x0209  /* PCI Class Code [R] */
-#define NILE4_CLSIZ     0x020C  /* PCI Cache Line Size [R/W] */
-#define NILE4_MLTIM     0x020D  /* PCI Latency Timer [R/W] */
-#define NILE4_HTYPE     0x020E  /* PCI Header Type [R] */
-#define NILE4_BIST      0x020F  /* BIST [R] (unimplemented) */
-#define NILE4_BARC      0x0210  /* PCI Base Address Register Control [R/W] */
-#define NILE4_BAR0      0x0218  /* PCI Base Address Register 0 [R/W] */
-#define NILE4_BAR1      0x0220  /* PCI Base Address Register 1 [R/W] */
-#define NILE4_CIS       0x0228  /* PCI Cardbus CIS Pointer [R] */
-                                /* (unimplemented) */
-#define NILE4_SSVID     0x022C  /* PCI Sub-System Vendor ID [R/W] */
-#define NILE4_SSID      0x022E  /* PCI Sub-System ID [R/W] */
-#define NILE4_ROM       0x0230  /* Expansion ROM Base Address [R] */
-                                /* (unimplemented) */
-#define NILE4_INTLIN    0x023C  /* PCI Interrupt Line [R/W] */
-#define NILE4_INTPIN    0x023D  /* PCI Interrupt Pin [R] */
-#define NILE4_MINGNT    0x023E  /* PCI Min_Gnt [R] (unimplemented) */
-#define NILE4_MAXLAT    0x023F  /* PCI Max_Lat [R] (unimplemented) */
-#define NILE4_BAR2      0x0240  /* PCI Base Address Register 2 [R/W] */
-#define NILE4_BAR3      0x0248  /* PCI Base Address Register 3 [R/W] */
-#define NILE4_BAR4      0x0250  /* PCI Base Address Register 4 [R/W] */
-#define NILE4_BAR5      0x0258  /* PCI Base Address Register 5 [R/W] */
-#define NILE4_BAR6      0x0260  /* PCI Base Address Register 6 [R/W] */
-#define NILE4_BAR7      0x0268  /* PCI Base Address Register 7 [R/W] */
-#define NILE4_BAR8      0x0270  /* PCI Base Address Register 8 [R/W] */
-#define NILE4_BARB      0x0278  /* PCI Base Address Register BOOT [R/W] */
-    /*
-     *  Serial-Port Registers
-     */
-#define NILE4_UART_BASE 0x0300
-#define NILE4_UARTRBR   0x0300  /* UART Receiver Data Buffer [R] */
-#define NILE4_UARTTHR   0x0300  /* UART Transmitter Data Holding [W] */
-#define NILE4_UARTIER   0x0308  /* UART Interrupt Enable [R/W] */
-#define NILE4_UARTDLL   0x0300  /* UART Divisor Latch LSB [R/W] */
-#define NILE4_UARTDLM   0x0308  /* UART Divisor Latch MSB [R/W] */
-#define NILE4_UARTIIR   0x0310  /* UART Interrupt ID [R] */
-#define NILE4_UARTFCR   0x0310  /* UART FIFO Control [W] */
-#define NILE4_UARTLCR   0x0318  /* UART Line Control [R/W] */
-#define NILE4_UARTMCR   0x0320  /* UART Modem Control [R/W] */
-#define NILE4_UARTLSR   0x0328  /* UART Line Status [R/W] */
-#define NILE4_UARTMSR   0x0330  /* UART Modem Status [R/W] */
-#define NILE4_UARTSCR   0x0338  /* UART Scratch [R/W] */
-#define NILE4_UART_BASE_BAUD    520833  /* 100 MHz / 12 / 16 */
-    /*
-     *  Interrupt Lines
-     */
-#define NILE4_INT_CPCE  0       /* CPU-Interface Parity-Error Interrupt */
-#define NILE4_INT_CNTD  1       /* CPU No-Target Decode Interrupt */
-#define NILE4_INT_MCE   2       /* Memory-Check Error Interrupt */
-#define NILE4_INT_DMA   3       /* DMA Controller Interrupt */
-#define NILE4_INT_UART  4       /* UART Interrupt */
-#define NILE4_INT_WDOG  5       /* Watchdog Timer Interrupt */
-#define NILE4_INT_GPT   6       /* General-Purpose Timer Interrupt */
-#define NILE4_INT_LBRTD 7       /* Local-Bus Ready Timer Interrupt */
-#define NILE4_INT_INTA  8       /* PCI Interrupt Signal INTA# */
-#define NILE4_INT_INTB  9       /* PCI Interrupt Signal INTB# */
-#define NILE4_INT_INTC  10      /* PCI Interrupt Signal INTC# */
-#define NILE4_INT_INTD  11      /* PCI Interrupt Signal INTD# */
-#define NILE4_INT_INTE  12      /* PCI Interrupt Signal INTE# (ISA cascade) */
-#define NILE4_INT_RESV  13      /* Reserved */
-#define NILE4_INT_PCIS  14      /* PCI SERR# Interrupt */
-#define NILE4_INT_PCIE  15      /* PCI Internal Error Interrupt */
-    /*
-     *  Nile 4 Register Access
-     */
-static inline void nile4_sync(void)
-{
-    volatile u32 *p = (volatile u32 *)0xbfc00000;
-    (void)(*p);
-}
-static inline void nile4_out32(u32 offset, u32 val)
-{
-    *(volatile u32 *)(NILE4_BASE+offset) = val;
-    nile4_sync();
-}
-static inline u32 nile4_in32(u32 offset)
-{
-    u32 val = *(volatile u32 *)(NILE4_BASE+offset);
-    nile4_sync();
-    return val;
-}
-static inline void nile4_out16(u32 offset, u16 val)
-{
-    *(volatile u16 *)(NILE4_BASE+offset) = val;
-    nile4_sync();
-}
-static inline u16 nile4_in16(u32 offset)
-{
-    u16 val = *(volatile u16 *)(NILE4_BASE+offset);
-    nile4_sync();
-    return val;
-}
-static inline void nile4_out8(u32 offset, u8 val)
-{
-    *(volatile u8 *)(NILE4_BASE+offset) = val;
-    nile4_sync();
-}
-static inline u8 nile4_in8(u32 offset)
-{
-    u8 val = *(volatile u8 *)(NILE4_BASE+offset);
-    nile4_sync();
-    return val;
-}
-    /*
-     *  Physical Device Address Registers
-     */
-extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
-                           int on_memory_bus, int visible);
-    /*
-     *  PCI Master Registers
-     */
-#define NILE4_PCICMD_IACK       0       /* PCI Interrupt Acknowledge */
-#define NILE4_PCICMD_IO         1       /* PCI I/O Space */
-#define NILE4_PCICMD_MEM        3       /* PCI Memory Space */
-#define NILE4_PCICMD_CFG        5       /* PCI Configuration Space */
-    /*
-     *  PCI Address Spaces
-     *
-     *  Note that these are multiplexed using PCIINIT[01]!
-     */
-#define NILE4_PCI_IO_BASE       0xa6000000
-#define NILE4_PCI_MEM_BASE      0xa8000000
-#define NILE4_PCI_CFG_BASE      NILE4_PCI_MEM_BASE
-#define NILE4_PCI_IACK_BASE     NILE4_PCI_IO_BASE
-extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
-    /*
-     *  Interrupt Programming
-     */
-#define NUM_I8259_INTERRUPTS    16
-#define NUM_NILE4_INTERRUPTS    16
-#define IRQ_I8259_CASCADE       NILE4_INT_INTE
-#define is_i8259_irq(irq)       ((irq) < NUM_I8259_INTERRUPTS)
-#define nile4_to_irq(n)         ((n)+NUM_I8259_INTERRUPTS)
-#define irq_to_nile4(n)         ((n)-NUM_I8259_INTERRUPTS)
-extern void nile4_map_irq(int nile4_irq, int cpu_irq);
-extern void nile4_map_irq_all(int cpu_irq);
-extern void nile4_enable_irq(unsigned int nile4_irq);
-extern void nile4_disable_irq(unsigned int nile4_irq);
-extern void nile4_disable_irq_all(void);
-extern u16 nile4_get_irq_stat(int cpu_irq);
-extern void nile4_enable_irq_output(int cpu_irq);
-extern void nile4_disable_irq_output(int cpu_irq);
-extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
-extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
-extern void nile4_clear_irq(int nile4_irq);
-extern void nile4_clear_irq_mask(u32 mask);
-extern u8 nile4_i8259_iack(void);
-extern void nile4_dump_irq_status(void);        /* Debug */
-#endif
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 5c3239dad0f2..b92dd8c760da 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -34,12 +34,8 @@
 #ifndef __ASSEMBLY__
-/*
+#include <linux/pfn.h>
- * This gives the physical RAM offset.
+#include <asm/io.h>
- */
-#ifndef PHYS_OFFSET
-#define PHYS_OFFSET             0UL
-#endif
 /*
 * It's normally defined only for FLATMEM config but it's
@@ -48,9 +44,6 @@
 */
 #define ARCH_PFN_OFFSET         PFN_UP(PHYS_OFFSET)
-#include <linux/pfn.h>
-#include <asm/io.h>
 extern void clear_page(void * page);
 extern void copy_page(void * to, void * from);
@@ -150,11 +143,15 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 * __pa()/__va() should be used only during mem init.
 */
 #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
-#define __pa_page_offset(x)     ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0)
+#define __pa(x)                                                         \
+({                                                                      \
+    unsigned long __x = (unsigned long)(x);                             \
+    __x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x);                     \
+})
 #else
-#define __pa_page_offset(x)     PAGE_OFFSET
+#define __pa(x)                                                         \
+    ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
 #endif
-#define __pa(x)         ((unsigned long)(x) - __pa_page_offset(x) + PHYS_OFFSET)
 #define __va(x)         ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
 #define __pa_symbol(x)  __pa(RELOC_HIDE((unsigned long)(x),0))
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index 3eea3ba0fca5..a59d54749eef 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -56,7 +56,7 @@ extern void register_pci_controller(struct pci_controller *hose);
 /*
 * board supplied pci irq fixup routine
 */
-extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
+extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 /* Can be used to override the logic in pci_scan_bus for skipping
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
new file mode 100644
index 000000000000..c84bcf9570b1
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
@@ -0,0 +1,151 @@
+/*
+ * Defines for the MSP interrupt controller.
+ *
+ * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
+ * Author: Carsten Langgaard, carstenl@mips.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+#ifndef _MSP_CIC_INT_H
+#define _MSP_CIC_INT_H
+/*
+ * The PMC-Sierra CIC interrupts are all centrally managed by the
+ * CIC sub-system.
+ * We attempt to keep the interrupt numbers as consistent as possible
+ * across all of the MSP devices, but some differences will creep in ...
+ * The interrupts which are directly forwarded to the MIPS core interrupts
+ * are assigned interrupts in the range 0-7, interrupts cascaded through
+ * the CIC are assigned interrupts 8-39.  The cascade occurs on C_IRQ4
+ * (MSP_INT_CIC).  Currently we don't really distinguish between VPE1
+ * and VPE0 (or thread contexts for that matter).  Will have to fix.
+ * The PER interrupts are assigned interrupts in the range 40-71.
+*/
+/*
+ * IRQs directly forwarded to the CPU
+ */
+#define MSP_MIPS_INTBASE        0
+#define MSP_INT_SW0             0       /* IRQ for swint0,       C_SW0  */
+#define MSP_INT_SW1             1       /* IRQ for swint1,       C_SW1  */
+#define MSP_INT_MAC0            2       /* IRQ for MAC 0,        C_IRQ0 */
+#define MSP_INT_MAC1            3       /* IRQ for MAC 1,        C_IRQ1 */
+#define MSP_INT_USB             4       /* IRQ for USB,          C_IRQ2 */
+#define MSP_INT_SAR             5       /* IRQ for ADSL2+ SAR,   C_IRQ3 */
+#define MSP_INT_CIC             6       /* IRQ for CIC block,    C_IRQ4 */
+#define MSP_INT_SEC             7       /* IRQ for Sec engine,   C_IRQ5 */
+/*
+ * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
+ * These defines should be tied to the register definitions for the CIC
+ * interrupt routine.  For now, just use hard-coded values.
+ */
+#define MSP_CIC_INTBASE         (MSP_MIPS_INTBASE + 8)
+#define MSP_INT_EXT0            (MSP_CIC_INTBASE + 0)
+                                        /* External interrupt 0         */
+#define MSP_INT_EXT1            (MSP_CIC_INTBASE + 1)
+                                        /* External interrupt 1         */
+#define MSP_INT_EXT2            (MSP_CIC_INTBASE + 2)
+                                        /* External interrupt 2         */
+#define MSP_INT_EXT3            (MSP_CIC_INTBASE + 3)
+                                        /* External interrupt 3         */
+#define MSP_INT_CPUIF           (MSP_CIC_INTBASE + 4)
+                                        /* CPU interface interrupt      */
+#define MSP_INT_EXT4            (MSP_CIC_INTBASE + 5)
+                                        /* External interrupt 4         */
+#define MSP_INT_CIC_USB         (MSP_CIC_INTBASE + 6)
+                                        /* Cascaded IRQ for USB         */
+#define MSP_INT_MBOX            (MSP_CIC_INTBASE + 7)
+                                        /* Sec engine mailbox IRQ       */
+#define MSP_INT_EXT5            (MSP_CIC_INTBASE + 8)
+                                        /* External interrupt 5         */
+#define MSP_INT_TDM             (MSP_CIC_INTBASE + 9)
+                                        /* TDM interrupt                */
+#define MSP_INT_CIC_MAC0        (MSP_CIC_INTBASE + 10)
+                                        /* Cascaded IRQ for MAC 0       */
+#define MSP_INT_CIC_MAC1        (MSP_CIC_INTBASE + 11)
+                                        /* Cascaded IRQ for MAC 1       */
+#define MSP_INT_CIC_SEC         (MSP_CIC_INTBASE + 12)
+                                        /* Cascaded IRQ for sec engine  */
+#define MSP_INT_PER             (MSP_CIC_INTBASE + 13)
+                                        /* Peripheral interrupt         */
+#define MSP_INT_TIMER0          (MSP_CIC_INTBASE + 14)
+                                        /* SLP timer 0                  */
+#define MSP_INT_TIMER1          (MSP_CIC_INTBASE + 15)
+                                        /* SLP timer 1                  */
+#define MSP_INT_TIMER2          (MSP_CIC_INTBASE + 16)
+                                        /* SLP timer 2                  */
+#define MSP_INT_VPE0_TIMER      (MSP_CIC_INTBASE + 17)
+                                        /* VPE0 MIPS timer              */
+#define MSP_INT_BLKCP           (MSP_CIC_INTBASE + 18)
+                                        /* Block Copy                   */
+#define MSP_INT_UART0           (MSP_CIC_INTBASE + 19)
+                                        /* UART 0                       */
+#define MSP_INT_PCI             (MSP_CIC_INTBASE + 20)
+                                        /* PCI subsystem                */
+#define MSP_INT_EXT6            (MSP_CIC_INTBASE + 21)
+                                        /* External interrupt 5         */
+#define MSP_INT_PCI_MSI         (MSP_CIC_INTBASE + 22)
+                                        /* PCI Message Signal           */
+#define MSP_INT_CIC_SAR         (MSP_CIC_INTBASE + 23)
+                                        /* Cascaded ADSL2+ SAR IRQ      */
+#define MSP_INT_DSL             (MSP_CIC_INTBASE + 24)
+                                        /* ADSL2+ IRQ                   */
+#define MSP_INT_CIC_ERR         (MSP_CIC_INTBASE + 25)
+                                        /* SLP error condition          */
+#define MSP_INT_VPE1_TIMER      (MSP_CIC_INTBASE + 26)
+                                        /* VPE1 MIPS timer              */
+#define MSP_INT_VPE0_PC         (MSP_CIC_INTBASE + 27)
+                                        /* VPE0 Performance counter     */
+#define MSP_INT_VPE1_PC         (MSP_CIC_INTBASE + 28)
+                                        /* VPE1 Performance counter     */
+#define MSP_INT_EXT7            (MSP_CIC_INTBASE + 29)
+                                        /* External interrupt 5         */
+#define MSP_INT_VPE0_SW         (MSP_CIC_INTBASE + 30)
+                                        /* VPE0 Software interrupt      */
+#define MSP_INT_VPE1_SW         (MSP_CIC_INTBASE + 31)
+                                        /* VPE0 Software interrupt      */
+/*
+ * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
+ */
+#define MSP_PER_INTBASE         (MSP_CIC_INTBASE + 32)
+/* Reserved                                        0-1                  */
+#define MSP_INT_UART1           (MSP_PER_INTBASE + 2)
+                                        /* UART 1                       */
+/* Reserved                                        3-5                  */
+#define MSP_INT_2WIRE           (MSP_PER_INTBASE + 6)
+                                        /* 2-wire                       */
+#define MSP_INT_TM0             (MSP_PER_INTBASE + 7)
+                                        /* Peripheral timer block out 0 */
+#define MSP_INT_TM1             (MSP_PER_INTBASE + 8)
+                                        /* Peripheral timer block out 1 */
+/* Reserved                                        9                    */
+#define MSP_INT_SPRX            (MSP_PER_INTBASE + 10)
+                                        /* SPI RX complete              */
+#define MSP_INT_SPTX            (MSP_PER_INTBASE + 11)
+                                        /* SPI TX complete              */
+#define MSP_INT_GPIO            (MSP_PER_INTBASE + 12)
+                                        /* GPIO                         */
+#define MSP_INT_PER_ERR         (MSP_PER_INTBASE + 13)
+                                        /* Peripheral error             */
+/* Reserved                                        14-31                */
+#endif /* !_MSP_CIC_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
new file mode 100644
index 000000000000..1d9f05474820
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
@@ -0,0 +1,43 @@
+/*
+ * Defines for the MSP interrupt handlers.
+ *
+ * Copyright (C) 2005, PMC-Sierra, Inc.  All rights reserved.
+ * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+#ifndef _MSP_INT_H
+#define _MSP_INT_H
+/*
+ * The PMC-Sierra MSP product line has at least two different interrupt
+ * controllers, the SLP register based scheme and the CIC interrupt
+ * controller block mechanism.  This file distinguishes between them
+ * so that devices see a uniform interface.
+ */
+#if defined(CONFIG_IRQ_MSP_SLP)
+        #include "msp_slp_int.h"
+#elif defined(CONFIG_IRQ_MSP_CIC)
+        #include "msp_cic_int.h"
+#else
+        #error "What sort of interrupt controller does *your* MSP have?"
+#endif
+#endif /* !_MSP_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h
new file mode 100644
index 000000000000..415606903617
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2000-2006 PMC-Sierra INC.
+ *
+ *     This program is free software; you can redistribute it
+ *     and/or modify it under the terms of the GNU General
+ *     Public License as published by the Free Software
+ *     Foundation; either version 2 of the License, or (at your
+ *     option) any later version.
+ *
+ *     This program is distributed in the hope that it will be
+ *     useful, but WITHOUT ANY WARRANTY; without even the implied
+ *     warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ *     PURPOSE.  See the GNU General Public License for more
+ *     details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this program; if not, write to the Free
+ *     Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
+ *     02139, USA.
+ *
+ * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
+ * SOFTWARE.
+ */
+#ifndef _MSP_PCI_H_
+#define _MSP_PCI_H_
+#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
+/*
+ * It is convenient to program the OATRAN register so that
+ * Athena virtual address space and PCI address space are
+ * the same. This is not a requirement, just a convenience.
+ *
+ * The only hard restrictions on the value of OATRAN is that
+ * OATRAN must not be programmed to allow translated memory
+ * addresses to fall within the lowest 512MB of
+ * PCI address space. This region is hardcoded
+ * for use as Athena PCI Host Controller target
+ * access memory space to the Athena's SDRAM.
+ *
+ * Note that OATRAN applies only to memory accesses, not
+ * to I/O accesses.
+ *
+ * To program OATRAN to make Athena virtual address space
+ * and PCI address space have the same values, OATRAN
+ * is to be programmed to 0xB8000000. The top seven
+ * bits of the value mimic the seven bits clipped off
+ * by the PCI Host controller.
+ *
+ * With OATRAN at the said value, when the CPU does
+ * an access to its virtual address at, say 0xB900_5000,
+ * the address appearing on the PCI bus will be
+ * 0xB900_5000.
+ *    - Michael Penner
+ */
+#define MSP_PCI_OATRAN          0xB8000000UL
+#define MSP_PCI_SPACE_BASE      (MSP_PCI_OATRAN + 0x1002000UL)
+#define MSP_PCI_SPACE_SIZE      (0x3000000UL - 0x2000)
+#define MSP_PCI_SPACE_END \
+                (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
+#define MSP_PCI_IOSPACE_BASE    (MSP_PCI_OATRAN + 0x1001000UL)
+#define MSP_PCI_IOSPACE_SIZE    0x1000
+#define MSP_PCI_IOSPACE_END  \
+                (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)
+/* IRQ for PCI status interrupts */
+#define PCI_STAT_IRQ    20
+#define QFLUSH_REG_1    0xB7F40000
+typedef volatile unsigned int pcireg;
+typedef void * volatile ppcireg;
+struct pci_block_copy
+{
+    pcireg   unused1; /* +0x00 */
+    pcireg   unused2; /* +0x04 */
+    ppcireg  unused3; /* +0x08 */
+    ppcireg  unused4; /* +0x0C */
+    pcireg   unused5; /* +0x10 */
+    pcireg   unused6; /* +0x14 */
+    pcireg   unused7; /* +0x18 */
+    ppcireg  unused8; /* +0x1C */
+    ppcireg  unused9; /* +0x20 */
+    pcireg   unusedA; /* +0x24 */
+    ppcireg  unusedB; /* +0x28 */
+    ppcireg  unusedC; /* +0x2C */
+};
+enum
+{
+    config_device_vendor,  /* 0 */
+    config_status_command, /* 1 */
+    config_class_revision, /* 2 */
+    config_BIST_header_latency_cache, /* 3 */
+    config_BAR0,           /* 4 */
+    config_BAR1,           /* 5 */
+    config_BAR2,           /* 6 */
+    config_not_used7,      /* 7 */
+    config_not_used8,      /* 8 */
+    config_not_used9,      /* 9 */
+    config_CIS,            /* 10 */
+    config_subsystem,      /* 11 */
+    config_not_used12,     /* 12 */
+    config_capabilities,   /* 13 */
+    config_not_used14,     /* 14 */
+    config_lat_grant_irq,  /* 15 */
+    config_message_control,/* 16 */
+    config_message_addr,   /* 17 */
+    config_message_data,   /* 18 */
+    config_VPD_addr,       /* 19 */
+    config_VPD_data,       /* 20 */
+    config_maxregs         /* 21 - number of registers */
+};
+struct msp_pci_regs
+{
+    pcireg hop_unused_00; /* +0x00 */
+    pcireg hop_unused_04; /* +0x04 */
+    pcireg hop_unused_08; /* +0x08 */
+    pcireg hop_unused_0C; /* +0x0C */
+    pcireg hop_unused_10; /* +0x10 */
+    pcireg hop_unused_14; /* +0x14 */
+    pcireg hop_unused_18; /* +0x18 */
+    pcireg hop_unused_1C; /* +0x1C */
+    pcireg hop_unused_20; /* +0x20 */
+    pcireg hop_unused_24; /* +0x24 */
+    pcireg hop_unused_28; /* +0x28 */
+    pcireg hop_unused_2C; /* +0x2C */
+    pcireg hop_unused_30; /* +0x30 */
+    pcireg hop_unused_34; /* +0x34 */
+    pcireg if_control;    /* +0x38 */
+    pcireg oatran;        /* +0x3C */
+    pcireg reset_ctl;     /* +0x40 */
+    pcireg config_addr;   /* +0x44 */
+    pcireg hop_unused_48; /* +0x48 */
+    pcireg msg_signaled_int_status; /* +0x4C */
+    pcireg msg_signaled_int_mask;   /* +0x50 */
+    pcireg if_status;     /* +0x54 */
+    pcireg if_mask;       /* +0x58 */
+    pcireg hop_unused_5C; /* +0x5C */
+    pcireg hop_unused_60; /* +0x60 */
+    pcireg hop_unused_64; /* +0x64 */
+    pcireg hop_unused_68; /* +0x68 */
+    pcireg hop_unused_6C; /* +0x6C */
+    pcireg hop_unused_70; /* +0x70 */
+    struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));
+    pcireg error_hdr1; /* +0xE0 */
+    pcireg error_hdr2; /* +0xE4 */
+    pcireg config[config_maxregs] __attribute__((aligned(256)));
+};
+#define BPCI_CFGADDR_BUSNUM_SHF 16
+#define BPCI_CFGADDR_FUNCTNUM_SHF 8
+#define BPCI_CFGADDR_REGNUM_SHF 2
+#define BPCI_CFGADDR_ENABLE (1<<31)
+#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
+#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
+#define BPCI_IFCONTROL_CTO_SHF 12  /* Shift count for CTO bits */
+#define BPCI_IFCONTROL_SE  (1<<5)  /* Enable exceptions on errors */
+#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
+#define BPCI_IFCONTROL_CAP (1<<3)  /* Enable capabilities */
+#define BPCI_IFCONTROL_MMC_SHF 0   /* Shift count for MMC bits */
+#define BPCI_IFSTATUS_MGT  (1<<8)  /* Master Grant timeout */
+#define BPCI_IFSTATUS_MTT  (1<<9)  /* Master TRDY timeout */
+#define BPCI_IFSTATUS_MRT  (1<<10) /* Master retry timeout */
+#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
+#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
+#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
+#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
+#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
+#define BPCI_IFSTATUS_RTO  (1<<18) /* Retry time out */
+#define BPCI_IFSTATUS_SER  (1<<19) /* System error */
+#define BPCI_IFSTATUS_PER  (1<<20) /* Parity error */
+#define BPCI_IFSTATUS_LCA  (1<<21) /* Local CPU abort */
+#define BPCI_IFSTATUS_MEM  (1<<22) /* Memory prot. violation */
+#define BPCI_IFSTATUS_ARB  (1<<23) /* Arbiter timed out */
+#define BPCI_IFSTATUS_STA  (1<<27) /* Signaled target abort */
+#define BPCI_IFSTATUS_TA   (1<<28) /* Target abort */
+#define BPCI_IFSTATUS_MA   (1<<29) /* Master abort */
+#define BPCI_IFSTATUS_PEI  (1<<30) /* Parity error as initiator */
+#define BPCI_IFSTATUS_PET  (1<<31) /* Parity error as target */
+#define BPCI_RESETCTL_PR (1<<0)    /* True if reset asserted */
+#define BPCI_RESETCTL_RT (1<<4)    /* Release time */
+#define BPCI_RESETCTL_CT (1<<8)    /* Config time */
+#define BPCI_RESETCTL_PE (1<<12)   /* PCI enabled */
+#define BPCI_RESETCTL_HM (1<<13)   /* PCI host mode */
+#define BPCI_RESETCTL_RI (1<<14)   /* PCI reset in */
+extern struct msp_pci_regs msp_pci_regs
+                        __attribute__((section(".register")));
+extern unsigned long msp_pci_config_space
+                        __attribute__((section(".register")));
+#endif /* !_MSP_PCI_H_ */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
new file mode 100644
index 000000000000..14ca7dc382a8
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
@@ -0,0 +1,176 @@
+/*
+ * MIPS boards bootprom interface for the Linux kernel.
+ *
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Author: Carsten Langgaard, carstenl@mips.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+#ifndef _ASM_MSP_PROM_H
+#define _ASM_MSP_PROM_H
+#include <linux/types.h>
+#define DEVICEID                        "deviceid"
+#define FEATURES                        "features"
+#define PROM_ENV                        "prom_env"
+#define PROM_ENV_FILE                   "/proc/"PROM_ENV
+#define PROM_ENV_SIZE                   256
+#define CPU_DEVID_FAMILY                0x0000ff00
+#define CPU_DEVID_REVISION              0x000000ff
+#define FPGA_IS_POLO(revision) \
+                (((revision >= 0xb0) && (revision < 0xd0)))
+#define FPGA_IS_5000(revision) \
+                ((revision >= 0x80) && (revision <= 0x90))
+#define FPGA_IS_ZEUS(revision)          ((revision < 0x7f))
+#define FPGA_IS_DUET(revision) \
+                (((revision >= 0xa0) && (revision < 0xb0)))
+#define FPGA_IS_MSP4200(revision)       ((revision >= 0xd0))
+#define FPGA_IS_MSP7100(revision)       ((revision >= 0xd0))
+#define MACHINE_TYPE_POLO               "POLO"
+#define MACHINE_TYPE_DUET               "DUET"
+#define MACHINE_TYPE_ZEUS               "ZEUS"
+#define MACHINE_TYPE_MSP2000REVB        "MSP2000REVB"
+#define MACHINE_TYPE_MSP5000            "MSP5000"
+#define MACHINE_TYPE_MSP4200            "MSP4200"
+#define MACHINE_TYPE_MSP7120            "MSP7120"
+#define MACHINE_TYPE_MSP7130            "MSP7130"
+#define MACHINE_TYPE_OTHER              "OTHER"
+#define MACHINE_TYPE_POLO_FPGA          "POLO-FPGA"
+#define MACHINE_TYPE_DUET_FPGA          "DUET-FPGA"
+#define MACHINE_TYPE_ZEUS_FPGA          "ZEUS_FPGA"
+#define MACHINE_TYPE_MSP2000REVB_FPGA   "MSP2000REVB-FPGA"
+#define MACHINE_TYPE_MSP5000_FPGA       "MSP5000-FPGA"
+#define MACHINE_TYPE_MSP4200_FPGA       "MSP4200-FPGA"
+#define MACHINE_TYPE_MSP7100_FPGA       "MSP7100-FPGA"
+#define MACHINE_TYPE_OTHER_FPGA         "OTHER-FPGA"
+/* Device Family definitions */
+#define FAMILY_FPGA                     0x0000
+#define FAMILY_ZEUS                     0x1000
+#define FAMILY_POLO                     0x2000
+#define FAMILY_DUET                     0x4000
+#define FAMILY_TRIAD                    0x5000
+#define FAMILY_MSP4200                  0x4200
+#define FAMILY_MSP4200_FPGA             0x4f00
+#define FAMILY_MSP7100                  0x7100
+#define FAMILY_MSP7100_FPGA             0x7f00
+/* Device Type definitions */
+#define TYPE_MSP7120                    0x7120
+#define TYPE_MSP7130                    0x7130
+#define ENET_KEY                'E'
+#define ENETTXD_KEY             'e'
+#define PCI_KEY                 'P'
+#define PCIMUX_KEY              'p'
+#define SEC_KEY                 'S'
+#define SPAD_KEY                'D'
+#define TDM_KEY                 'T'
+#define ZSP_KEY                 'Z'
+#define FEATURE_NOEXIST         '-'
+#define FEATURE_EXIST           '+'
+#define ENET_MII                'M'
+#define ENET_RMII               'R'
+#define ENETTXD_FALLING         'F'
+#define ENETTXD_RISING          'R'
+#define PCI_HOST                'H'
+#define PCI_PERIPHERAL          'P'
+#define PCIMUX_FULL             'F'
+#define PCIMUX_SINGLE           'S'
+#define SEC_DUET                'D'
+#define SEC_POLO                'P'
+#define SEC_SLOW                'S'
+#define SEC_TRIAD               'T'
+#define SPAD_POLO               'P'
+#define TDM_DUET                'D'     /* DUET TDMs might exist */
+#define TDM_POLO                'P'     /* POLO TDMs might exist */
+#define TDM_TRIAD               'T'     /* TRIAD TDMs might exist */
+#define ZSP_DUET                'D'     /* one DUET zsp engine */
+#define ZSP_TRIAD               'T'     /* two TRIAD zsp engines */
+extern char *prom_getcmdline(void);
+extern char *prom_getenv(char *name);
+extern void prom_init_cmdline(void);
+extern void prom_meminit(void);
+extern void prom_fixup_mem_map(unsigned long start_mem,
+                               unsigned long end_mem);
+#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
+extern bool get_ramroot(void **start, unsigned long *size);
+#endif
+extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
+extern unsigned long get_deviceid(void);
+extern char identify_enet(unsigned long interface_num);
+extern char identify_enetTxD(unsigned long interface_num);
+extern char identify_pci(void);
+extern char identify_sec(void);
+extern char identify_spad(void);
+extern char identify_sec(void);
+extern char identify_tdm(void);
+extern char identify_zsp(void);
+extern unsigned long identify_family(void);
+extern unsigned long identify_revision(void);
+/*
+ * The following macro calls prom_printf and puts the format string
+ * into an init section so it can be reclaimed.
+ */
+#define ppfinit(f, x...) \
+        do { \
+                static char _f[] __initdata = KERN_INFO f; \
+                printk(_f, ## x); \
+        } while (0)
+/* Memory descriptor management. */
+#define PROM_MAX_PMEMBLOCKS    7        /* 6 used */
+enum yamon_memtypes {
+        yamon_dontuse,
+        yamon_prom,
+        yamon_free,
+};
+struct prom_pmemblock {
+        unsigned long base; /* Within KSEG0. */
+        unsigned int size;  /* In bytes. */
+        unsigned int type;  /* free or prom memory */
+};
+extern int prom_argc;
+extern char **prom_argv;
+extern char **prom_envp;
+extern int *prom_vec;
+extern struct prom_pmemblock *prom_getmdesc(void);
+#endif /* !_ASM_MSP_PROM_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
new file mode 100644
index 000000000000..60a5a38dd5b2
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
@@ -0,0 +1,236 @@
+/*
+ * SMP/VPE-safe functions to access "registers" (see note).
+ *
+ * NOTES:
+* - These macros use ll/sc instructions, so it is your responsibility to
+ * ensure these are available on your platform before including this file.
+ * - The MIPS32 spec states that ll/sc results are undefined for uncached
+ * accesses. This means they can't be used on HW registers accessed
+ * through kseg1. Code which requires these macros for this purpose must
+ * front-end the registers with cached memory "registers" and have a single
+ * thread update the actual HW registers.
+ * - A maximum of 2k of code can be inserted between ll and sc. Every
+ * memory accesses between the instructions will increase the chance of
+ * sc failing and having to loop.
+ * - When using custom_read_reg32/custom_write_reg32 only perform the
+ * necessary logical operations on the register value in between these
+ * two calls. All other logic should be performed before the first call.
+  * - There is a bug on the R10000 chips which has a workaround. If you
+ * are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
+ * to be non-zero.  If you are using this header from within linux, you may
+ * include <asm/war.h> before including this file to have this defined
+ * appropriately for you.
+ *
+ * Copyright 2005-2007 PMC-Sierra, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
+ *  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF USE,
+ *  DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc., 675
+ *  Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_REGOPS_H__
+#define __ASM_REGOPS_H__
+#include <linux/types.h>
+#include <asm/war.h>
+#ifndef R10000_LLSC_WAR
+#define R10000_LLSC_WAR 0
+#endif
+#if R10000_LLSC_WAR == 1
+#define __beqz  "beqzl  "
+#else
+#define __beqz  "beqz   "
+#endif
+#ifndef _LINUX_TYPES_H
+typedef unsigned int u32;
+#endif
+/*
+ * Sets all the masked bits to the corresponding value bits
+ */
+static inline void set_value_reg32(volatile u32 *const addr,
+                                        u32 const mask,
+                                        u32 const value)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1  # set_value_reg32       \n"
+        "       and     %0, %2                          \n"
+        "       or      %0, %3                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (~mask), "ir" (value), "m" (*addr));
+}
+/*
+ * Sets all the masked bits to '1'
+ */
+static inline void set_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1          # set_reg32     \n"
+        "       or      %0, %2                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (mask), "m" (*addr));
+}
+/*
+ * Sets all the masked bits to '0'
+ */
+static inline void clear_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1          # clear_reg32   \n"
+        "       and     %0, %2                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (~mask), "m" (*addr));
+}
+/*
+ * Toggles all masked bits from '0' to '1' and '1' to '0'
+ */
+static inline void toggle_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    mips3                           \n"
+        "1:     ll      %0, %1          # toggle_reg32  \n"
+        "       xor     %0, %2                          \n"
+        "       sc      %0, %1                          \n"
+        "       "__beqz"%0, 1b                          \n"
+        "       nop                                     \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp), "=m" (*addr)
+        : "ir" (mask), "m" (*addr));
+}
+/*
+ * Read all masked bits others are returned as '0'
+ */
+static inline u32 read_reg32(volatile u32 *const addr,
+                                u32 const mask)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    noreorder                       \n"
+        "       lw      %0, %1          # read          \n"
+        "       and     %0, %2          # mask          \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp)
+        : "m" (*addr), "ir" (mask));
+        return temp;
+}
+/*
+ * blocking_read_reg32 - Read address with blocking load
+ *
+ * Uncached writes need to be read back to ensure they reach RAM.
+ * The returned value must be 'used' to prevent from becoming a
+ * non-blocking load.
+ */
+static inline u32 blocking_read_reg32(volatile u32 *const addr)
+{
+        u32 temp;
+        __asm__ __volatile__(
+        "       .set    push                            \n"
+        "       .set    noreorder                       \n"
+        "       lw      %0, %1          # read          \n"
+        "       move    %0, %0          # block         \n"
+        "       .set    pop                             \n"
+        : "=&r" (temp)
+        : "m" (*addr));
+        return temp;
+}
+/*
+ * For special strange cases only:
+ *
+ * If you need custom processing within a ll/sc loop, use the following macros
+ * VERY CAREFULLY:
+ *
+ *   u32 tmp;                           <-- Define a variable to hold the data
+ *
+ *   custom_read_reg32(address, tmp);   <-- Reads the address and put the value
+ *                                              in the 'tmp' variable given
+ *
+ *      From here on out, you are (basicly) atomic, so don't do anything too
+ *      fancy!
+ *      Also, this code may loop if the end of this block fails to write
+ *      everything back safely due do the other CPU, so do NOT do anything
+ *      with side-effects!
+ *
+ *   custom_write_reg32(address, tmp);  <-- Writes back 'tmp' safely.
+ */
+#define custom_read_reg32(address, tmp)                         \
+        __asm__ __volatile__(                                   \
+        "       .set    push                            \n"     \
+        "       .set    mips3                           \n"     \
+        "1:     ll      %0, %1  #custom_read_reg32      \n"     \
+        "       .set    pop                             \n"     \
+        : "=r" (tmp), "=m" (*address)                           \
+        : "m" (*address))
+#define custom_write_reg32(address, tmp)                        \
+        __asm__ __volatile__(                                   \
+        "       .set    push                            \n"     \
+        "       .set    mips3                           \n"     \
+        "       sc      %0, %1  #custom_write_reg32     \n"     \
+        "       "__beqz"%0, 1b                          \n"     \
+        "       nop                                     \n"     \
+        "       .set    pop                             \n"     \
+        : "=&r" (tmp), "=m" (*address)                          \
+        : "0" (tmp), "m" (*address))
+#endif  /* __ASM_REGOPS_H__ */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
new file mode 100644
index 000000000000..0b56f55206c6
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
@@ -0,0 +1,667 @@
+/*
+ * Defines for the address space, registers and register configuration
+ * (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
+ * This file contains addess maps for all the devices in the line of
+ * products but only has register definitions and configuration masks for
+ * registers which aren't definitely associated with any device.  Things
+ * like clock settings, reset access, the ELB etc.  Individual device
+ * drivers will reference the appropriate XXX_BASE value defined here
+ * and have individual registers offset from that.
+ *
+ * Copyright (C) 2005-2007 PMC-Sierra, Inc.  All rights reserved.
+ * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+#include <asm/addrspace.h>
+#include <linux/types.h>
+#ifndef _ASM_MSP_REGS_H
+#define _ASM_MSP_REGS_H
+/*
+ ########################################################################
+ #  Address space and device base definitions                           #
+ ########################################################################
+ */
+/*
+ ***************************************************************************
+ * System Logic and Peripherals (ELB, UART0, etc) device address space     *
+ ***************************************************************************
+ */
+#define MSP_SLP_BASE            0x1c000000
+                                        /* System Logic and Peripherals */
+#define MSP_RST_BASE            (MSP_SLP_BASE + 0x10)
+                                        /* System reset register base   */
+#define MSP_RST_SIZE            0x0C    /* System reset register space  */
+#define MSP_WTIMER_BASE         (MSP_SLP_BASE + 0x04C)
+                                        /* watchdog timer base          */
+#define MSP_ITIMER_BASE         (MSP_SLP_BASE + 0x054)
+                                        /* internal timer base          */
+#define MSP_UART0_BASE          (MSP_SLP_BASE + 0x100)
+                                        /* UART0 controller base        */
+#define MSP_BCPY_CTRL_BASE      (MSP_SLP_BASE + 0x120)
+                                        /* Block Copy controller base   */
+#define MSP_BCPY_DESC_BASE      (MSP_SLP_BASE + 0x160)
+                                        /* Block Copy descriptor base   */
+/*
+ ***************************************************************************
+ * PCI address space                                                       *
+ ***************************************************************************
+ */
+#define MSP_PCI_BASE            0x19000000
+/*
+ ***************************************************************************
+ * MSbus device address space                                              *
+ ***************************************************************************
+ */
+#define MSP_MSB_BASE            0x18000000
+                                        /* MSbus address start          */
+#define MSP_PER_BASE            (MSP_MSB_BASE + 0x400000)
+                                        /* Peripheral device registers  */
+#define MSP_MAC0_BASE           (MSP_MSB_BASE + 0x600000)
+                                        /* MAC A device registers       */
+#define MSP_MAC1_BASE           (MSP_MSB_BASE + 0x700000)
+                                        /* MAC B device registers       */
+#define MSP_MAC_SIZE            0xE0    /* MAC register space           */
+#define MSP_SEC_BASE            (MSP_MSB_BASE + 0x800000)
+                                        /* Security Engine registers    */
+#define MSP_MAC2_BASE           (MSP_MSB_BASE + 0x900000)
+                                        /* MAC C device registers       */
+#define MSP_ADSL2_BASE          (MSP_MSB_BASE + 0xA80000)
+                                        /* ADSL2 device registers       */
+#define MSP_USB_BASE            (MSP_MSB_BASE + 0xB40000)
+                                        /* USB device registers         */
+#define MSP_USB_BASE_START      (MSP_MSB_BASE + 0xB40100)
+                                        /* USB device registers         */
+#define MSP_USB_BASE_END        (MSP_MSB_BASE + 0xB401FF)
+                                        /* USB device registers         */
+#define MSP_CPUIF_BASE          (MSP_MSB_BASE + 0xC00000)
+                                        /* CPU interface registers      */
+/* Devices within the MSbus peripheral block */
+#define MSP_UART1_BASE          (MSP_PER_BASE + 0x030)
+                                        /* UART1 controller base        */
+#define MSP_SPI_BASE            (MSP_PER_BASE + 0x058)
+                                        /* SPI/MPI control registers    */
+#define MSP_TWI_BASE            (MSP_PER_BASE + 0x090)
+                                        /* Two-wire control registers   */
+#define MSP_PTIMER_BASE         (MSP_PER_BASE + 0x0F0)
+                                        /* Programmable timer control   */
+/*
+ ***************************************************************************
+ * Physical Memory configuration address space                             *
+ ***************************************************************************
+ */
+#define MSP_MEM_CFG_BASE        0x17f00000
+#define MSP_MEM_INDIRECT_CTL_10 0x10
+/*
+ * Notes:
+ *  1) The SPI registers are split into two blocks, one offset from the
+ *     MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
+ *     0x68.  The SPI driver definitions for the register must be aware
+ *     of this.
+ *  2) The block copy engine register are divided into two regions, one
+ *     for the control/configuration of the engine proper and one for the
+ *     values of the descriptors used in the copy process.  These have
+ *     different base defines (CTRL_BASE vs DESC_BASE)
+ *  3) These constants are for physical addresses which means that they
+ *     work correctly with "ioremap" and friends.  This means that device
+ *     drivers will need to remap these addresses using ioremap and perhaps
+ *     the readw/writew macros.  Or they could use the regptr() macro
+ *     defined below, but the readw/writew calls are the correct thing.
+ *  4) The UARTs have an additional status register offset from the base
+ *     address.  This register isn't used in the standard 8250 driver but
+ *     may be used in other software.  Consult the hardware datasheet for
+ *     offset details.
+ *  5) For some unknown reason the security engine (MSP_SEC_BASE) registers
+ *     start at an offset of 0x84 from the base address but the block of
+ *     registers before this is reserved for the security engine.  The
+ *     driver will have to be aware of this but it makes the register
+ *     definitions line up better with the documentation.
+ */
+/*
+ ########################################################################
+ #  System register definitions.  Not associated with a specific device #
+ ########################################################################
+ */
+/*
+ * This macro maps the physical register number into uncached space
+ * and (for C code) casts it into a u32 pointer so it can be dereferenced
+ * Normally these would be accessed with ioremap and readX/writeX, but
+ * these are convenient for a lot of internal kernel code.
+ */
+#ifdef __ASSEMBLER__
+        #define regptr(addr) (KSEG1ADDR(addr))
+#else
+        #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
+#endif
+/*
+ ***************************************************************************
+ * System Logic and Peripherals (RESET, ELB, etc) registers                *
+ ***************************************************************************
+ */
+/* System Control register definitions */
+#define DEV_ID_REG      regptr(MSP_SLP_BASE + 0x00)
+                                        /* Device-ID                 RO */
+#define FWR_ID_REG      regptr(MSP_SLP_BASE + 0x04)
+                                        /* Firmware-ID Register      RW */
+#define SYS_ID_REG0     regptr(MSP_SLP_BASE + 0x08)
+                                        /* System-ID Register-0      RW */
+#define SYS_ID_REG1     regptr(MSP_SLP_BASE + 0x0C)
+                                        /* System-ID Register-1      RW */
+/* System Reset register definitions */
+#define RST_STS_REG     regptr(MSP_SLP_BASE + 0x10)
+                                        /* System Reset Status       RO */
+#define RST_SET_REG     regptr(MSP_SLP_BASE + 0x14)
+                                        /* System Set Reset          WO */
+#define RST_CLR_REG     regptr(MSP_SLP_BASE + 0x18)
+                                        /* System Clear Reset        WO */
+/* System Clock Registers */
+#define PCI_SLP_REG     regptr(MSP_SLP_BASE + 0x1C)
+                                        /* PCI clock generator       RW */
+#define URT_SLP_REG     regptr(MSP_SLP_BASE + 0x20)
+                                        /* UART clock generator      RW */
+/* reserved                   (MSP_SLP_BASE + 0x24)                     */
+/* reserved                   (MSP_SLP_BASE + 0x28)                     */
+#define PLL1_SLP_REG    regptr(MSP_SLP_BASE + 0x2C)
+                                        /* PLL1 clock generator      RW */
+#define PLL0_SLP_REG    regptr(MSP_SLP_BASE + 0x30)
+                                        /* PLL0 clock generator      RW */
+#define MIPS_SLP_REG    regptr(MSP_SLP_BASE + 0x34)
+                                        /* MIPS clock generator      RW */
+#define VE_SLP_REG      regptr(MSP_SLP_BASE + 0x38)
+                                        /* Voice Eng clock generator RW */
+/* reserved                   (MSP_SLP_BASE + 0x3C)                     */
+#define MSB_SLP_REG     regptr(MSP_SLP_BASE + 0x40)
+                                        /* MS-Bus clock generator    RW */
+#define SMAC_SLP_REG    regptr(MSP_SLP_BASE + 0x44)
+                                        /* Sec & MAC clock generator RW */
+#define PERF_SLP_REG    regptr(MSP_SLP_BASE + 0x48)
+                                        /* Per & TDM clock generator RW */
+/* Interrupt Controller Registers */
+#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
+                                        /* Interrupt status register RW */
+#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
+                                        /* Interrupt enable/mask     RW */
+#define SE_MBOX_REG     regptr(MSP_SLP_BASE + 0x78)
+                                        /* Security Engine mailbox   RW */
+#define VE_MBOX_REG     regptr(MSP_SLP_BASE + 0x7C)
+                                        /* Voice Engine mailbox      RW */
+/* ELB Controller Registers */
+#define CS0_CNFG_REG    regptr(MSP_SLP_BASE + 0x80)
+                                        /* ELB CS0 Configuration Reg    */
+#define CS0_ADDR_REG    regptr(MSP_SLP_BASE + 0x84)
+                                        /* ELB CS0 Base Address Reg     */
+#define CS0_MASK_REG    regptr(MSP_SLP_BASE + 0x88)
+                                        /* ELB CS0 Mask Register        */
+#define CS0_ACCESS_REG  regptr(MSP_SLP_BASE + 0x8C)
+                                        /* ELB CS0 access register      */
+#define CS1_CNFG_REG    regptr(MSP_SLP_BASE + 0x90)
+                                        /* ELB CS1 Configuration Reg    */
+#define CS1_ADDR_REG    regptr(MSP_SLP_BASE + 0x94)
+                                        /* ELB CS1 Base Address Reg     */
+#define CS1_MASK_REG    regptr(MSP_SLP_BASE + 0x98)
+                                        /* ELB CS1 Mask Register        */
+#define CS1_ACCESS_REG  regptr(MSP_SLP_BASE + 0x9C)
+                                        /* ELB CS1 access register      */
+#define CS2_CNFG_REG    regptr(MSP_SLP_BASE + 0xA0)
+                                        /* ELB CS2 Configuration Reg    */
+#define CS2_ADDR_REG    regptr(MSP_SLP_BASE + 0xA4)
+                                        /* ELB CS2 Base Address Reg     */
+#define CS2_MASK_REG    regptr(MSP_SLP_BASE + 0xA8)
+                                        /* ELB CS2 Mask Register        */
+#define CS2_ACCESS_REG  regptr(MSP_SLP_BASE + 0xAC)
+                                        /* ELB CS2 access register      */
+#define CS3_CNFG_REG    regptr(MSP_SLP_BASE + 0xB0)
+                                        /* ELB CS3 Configuration Reg    */
+#define CS3_ADDR_REG    regptr(MSP_SLP_BASE + 0xB4)
+                                        /* ELB CS3 Base Address Reg     */
+#define CS3_MASK_REG    regptr(MSP_SLP_BASE + 0xB8)
+                                        /* ELB CS3 Mask Register        */
+#define CS3_ACCESS_REG  regptr(MSP_SLP_BASE + 0xBC)
+                                        /* ELB CS3 access register      */
+#define CS4_CNFG_REG    regptr(MSP_SLP_BASE + 0xC0)
+                                        /* ELB CS4 Configuration Reg    */
+#define CS4_ADDR_REG    regptr(MSP_SLP_BASE + 0xC4)
+                                        /* ELB CS4 Base Address Reg     */
+#define CS4_MASK_REG    regptr(MSP_SLP_BASE + 0xC8)
+                                        /* ELB CS4 Mask Register        */
+#define CS4_ACCESS_REG  regptr(MSP_SLP_BASE + 0xCC)
+                                        /* ELB CS4 access register      */
+#define CS5_CNFG_REG    regptr(MSP_SLP_BASE + 0xD0)
+                                        /* ELB CS5 Configuration Reg    */
+#define CS5_ADDR_REG    regptr(MSP_SLP_BASE + 0xD4)
+                                        /* ELB CS5 Base Address Reg     */
+#define CS5_MASK_REG    regptr(MSP_SLP_BASE + 0xD8)
+                                        /* ELB CS5 Mask Register        */
+#define CS5_ACCESS_REG  regptr(MSP_SLP_BASE + 0xDC)
+                                        /* ELB CS5 access register      */
+/* reserved                            0xE0 - 0xE8                      */
+#define ELB_1PC_EN_REG  regptr(MSP_SLP_BASE + 0xEC)
+                                        /* ELB single PC card detect    */
+/* reserved                            0xF0 - 0xF8                      */
+#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
+                                        /* SDRAM read/ELB timing Reg    */
+/* Extended UART status registers */
+#define UART0_STATUS_REG        regptr(MSP_UART0_BASE + 0x0c0)
+                                        /* UART Status Register 0       */
+#define UART1_STATUS_REG        regptr(MSP_UART1_BASE + 0x170)
+                                        /* UART Status Register 1       */
+/* Performance monitoring registers */
+#define PERF_MON_CTRL_REG       regptr(MSP_SLP_BASE + 0x140)
+                                        /* Performance monitor control  */
+#define PERF_MON_CLR_REG        regptr(MSP_SLP_BASE + 0x144)
+                                        /* Performance monitor clear    */
+#define PERF_MON_CNTH_REG       regptr(MSP_SLP_BASE + 0x148)
+                                        /* Perf monitor counter high    */
+#define PERF_MON_CNTL_REG       regptr(MSP_SLP_BASE + 0x14C)
+                                        /* Perf monitor counter low     */
+/* System control registers */
+#define SYS_CTRL_REG            regptr(MSP_SLP_BASE + 0x150)
+                                        /* System control register      */
+#define SYS_ERR1_REG            regptr(MSP_SLP_BASE + 0x154)
+                                        /* System Error status 1        */
+#define SYS_ERR2_REG            regptr(MSP_SLP_BASE + 0x158)
+                                        /* System Error status 2        */
+#define SYS_INT_CFG_REG         regptr(MSP_SLP_BASE + 0x15C)
+                                        /* System Interrupt config      */
+/* Voice Engine Memory configuration */
+#define VE_MEM_REG              regptr(MSP_SLP_BASE + 0x17C)
+                                        /* Voice engine memory config   */
+/* CPU/SLP Error Status registers */
+#define CPU_ERR1_REG            regptr(MSP_SLP_BASE + 0x180)
+                                        /* CPU/SLP Error status 1       */
+#define CPU_ERR2_REG            regptr(MSP_SLP_BASE + 0x184)
+                                        /* CPU/SLP Error status 1       */
+#define EXTENDED_GPIO_REG       regptr(MSP_SLP_BASE + 0x188)
+                                        /* Extended GPIO register       */
+/* System Error registers */
+#define SLP_ERR_STS_REG         regptr(MSP_SLP_BASE + 0x190)
+                                        /* Int status for SLP errors    */
+#define SLP_ERR_MSK_REG         regptr(MSP_SLP_BASE + 0x194)
+                                        /* Int mask for SLP errors      */
+#define SLP_ELB_ERST_REG        regptr(MSP_SLP_BASE + 0x198)
+                                        /* External ELB reset           */
+#define SLP_BOOT_STS_REG        regptr(MSP_SLP_BASE + 0x19C)
+                                        /* Boot Status                  */
+/* Extended ELB addressing */
+#define CS0_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A0)
+                                        /* CS0 Extended address         */
+#define CS1_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A4)
+                                        /* CS1 Extended address         */
+#define CS2_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A8)
+                                        /* CS2 Extended address         */
+#define CS3_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1AC)
+                                        /* CS3 Extended address         */
+/* reserved                                           0x1B0             */
+#define CS5_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1B4)
+                                        /* CS5 Extended address         */
+/* PLL Adjustment registers */
+#define PLL_LOCK_REG            regptr(MSP_SLP_BASE + 0x200)
+                                        /* PLL0 lock status             */
+#define PLL_ARST_REG            regptr(MSP_SLP_BASE + 0x204)
+                                        /* PLL Analog reset status      */
+#define PLL0_ADJ_REG            regptr(MSP_SLP_BASE + 0x208)
+                                        /* PLL0 Adjustment value        */
+#define PLL1_ADJ_REG            regptr(MSP_SLP_BASE + 0x20C)
+                                        /* PLL1 Adjustment value        */
+/*
+ ***************************************************************************
+ * Peripheral Register definitions                                         *
+ ***************************************************************************
+ */
+/* Peripheral status */
+#define PER_CTRL_REG            regptr(MSP_PER_BASE + 0x50)
+                                        /* Peripheral control register  */
+#define PER_STS_REG             regptr(MSP_PER_BASE + 0x54)
+                                        /* Peripheral status register   */
+/* SPI/MPI Registers */
+#define SMPI_TX_SZ_REG          regptr(MSP_PER_BASE + 0x58)
+                                        /* SPI/MPI Tx Size register     */
+#define SMPI_RX_SZ_REG          regptr(MSP_PER_BASE + 0x5C)
+                                        /* SPI/MPI Rx Size register     */
+#define SMPI_CTL_REG            regptr(MSP_PER_BASE + 0x60)
+                                        /* SPI/MPI Control register     */
+#define SMPI_MS_REG             regptr(MSP_PER_BASE + 0x64)
+                                        /* SPI/MPI Chip Select reg      */
+#define SMPI_CORE_DATA_REG      regptr(MSP_PER_BASE + 0xC0)
+                                        /* SPI/MPI Core Data reg        */
+#define SMPI_CORE_CTRL_REG      regptr(MSP_PER_BASE + 0xC4)
+                                        /* SPI/MPI Core Control reg     */
+#define SMPI_CORE_STAT_REG      regptr(MSP_PER_BASE + 0xC8)
+                                        /* SPI/MPI Core Status reg      */
+#define SMPI_CORE_SSEL_REG      regptr(MSP_PER_BASE + 0xCC)
+                                        /* SPI/MPI Core Ssel reg        */
+#define SMPI_FIFO_REG           regptr(MSP_PER_BASE + 0xD0)
+                                        /* SPI/MPI Data FIFO reg        */
+/* Peripheral Block Error Registers           */
+#define PER_ERR_STS_REG         regptr(MSP_PER_BASE + 0x70)
+                                        /* Error Bit Status Register    */
+#define PER_ERR_MSK_REG         regptr(MSP_PER_BASE + 0x74)
+                                        /* Error Bit Mask Register      */
+#define PER_HDR1_REG            regptr(MSP_PER_BASE + 0x78)
+                                        /* Error Header 1 Register      */
+#define PER_HDR2_REG            regptr(MSP_PER_BASE + 0x7C)
+                                        /* Error Header 2 Register      */
+/* Peripheral Block Interrupt Registers       */
+#define PER_INT_STS_REG         regptr(MSP_PER_BASE + 0x80)
+                                        /* Interrupt status register    */
+#define PER_INT_MSK_REG         regptr(MSP_PER_BASE + 0x84)
+                                        /* Interrupt Mask Register      */
+#define GPIO_INT_STS_REG        regptr(MSP_PER_BASE + 0x88)
+                                        /* GPIO interrupt status reg    */
+#define GPIO_INT_MSK_REG        regptr(MSP_PER_BASE + 0x8C)
+                                        /* GPIO interrupt MASK Reg      */
+/* POLO GPIO registers                        */
+#define POLO_GPIO_DAT1_REG      regptr(MSP_PER_BASE + 0x0E0)
+                                        /* Polo GPIO[8:0]  data reg     */
+#define POLO_GPIO_CFG1_REG      regptr(MSP_PER_BASE + 0x0E4)
+                                        /* Polo GPIO[7:0]  config reg   */
+#define POLO_GPIO_CFG2_REG      regptr(MSP_PER_BASE + 0x0E8)
+                                        /* Polo GPIO[15:8] config reg   */
+#define POLO_GPIO_OD1_REG       regptr(MSP_PER_BASE + 0x0EC)
+                                        /* Polo GPIO[31:0] output drive */
+#define POLO_GPIO_CFG3_REG      regptr(MSP_PER_BASE + 0x170)
+                                        /* Polo GPIO[23:16] config reg  */
+#define POLO_GPIO_DAT2_REG      regptr(MSP_PER_BASE + 0x174)
+                                        /* Polo GPIO[15:9]  data reg    */
+#define POLO_GPIO_DAT3_REG      regptr(MSP_PER_BASE + 0x178)
+                                        /* Polo GPIO[23:16]  data reg   */
+#define POLO_GPIO_DAT4_REG      regptr(MSP_PER_BASE + 0x17C)
+                                        /* Polo GPIO[31:24]  data reg   */
+#define POLO_GPIO_DAT5_REG      regptr(MSP_PER_BASE + 0x180)
+                                        /* Polo GPIO[39:32]  data reg   */
+#define POLO_GPIO_DAT6_REG      regptr(MSP_PER_BASE + 0x184)
+                                        /* Polo GPIO[47:40]  data reg   */
+#define POLO_GPIO_DAT7_REG      regptr(MSP_PER_BASE + 0x188)
+                                        /* Polo GPIO[54:48]  data reg   */
+#define POLO_GPIO_CFG4_REG      regptr(MSP_PER_BASE + 0x18C)
+                                        /* Polo GPIO[31:24] config reg  */
+#define POLO_GPIO_CFG5_REG      regptr(MSP_PER_BASE + 0x190)
+                                        /* Polo GPIO[39:32] config reg  */
+#define POLO_GPIO_CFG6_REG      regptr(MSP_PER_BASE + 0x194)
+                                        /* Polo GPIO[47:40] config reg  */
+#define POLO_GPIO_CFG7_REG      regptr(MSP_PER_BASE + 0x198)
+                                        /* Polo GPIO[54:48] config reg  */
+#define POLO_GPIO_OD2_REG       regptr(MSP_PER_BASE + 0x19C)
+                                        /* Polo GPIO[54:32] output drive */
+/* Generic GPIO registers                     */
+#define GPIO_DATA1_REG          regptr(MSP_PER_BASE + 0x170)
+                                        /* GPIO[1:0] data register      */
+#define GPIO_DATA2_REG          regptr(MSP_PER_BASE + 0x174)
+                                        /* GPIO[5:2] data register      */
+#define GPIO_DATA3_REG          regptr(MSP_PER_BASE + 0x178)
+                                        /* GPIO[9:6] data register      */
+#define GPIO_DATA4_REG          regptr(MSP_PER_BASE + 0x17C)
+                                        /* GPIO[15:10] data register    */
+#define GPIO_CFG1_REG           regptr(MSP_PER_BASE + 0x180)
+                                        /* GPIO[1:0] config register    */
+#define GPIO_CFG2_REG           regptr(MSP_PER_BASE + 0x184)
+                                        /* GPIO[5:2] config register    */
+#define GPIO_CFG3_REG           regptr(MSP_PER_BASE + 0x188)
+                                        /* GPIO[9:6] config register    */
+#define GPIO_CFG4_REG           regptr(MSP_PER_BASE + 0x18C)
+                                        /* GPIO[15:10] config register  */
+#define GPIO_OD_REG             regptr(MSP_PER_BASE + 0x190)
+                                        /* GPIO[15:0] output drive      */
+/*
+ ***************************************************************************
+ * CPU Interface register definitions                                      *
+ ***************************************************************************
+ */
+#define PCI_FLUSH_REG           regptr(MSP_CPUIF_BASE + 0x00)
+                                        /* PCI-SDRAM queue flush trigger */
+#define OCP_ERR1_REG            regptr(MSP_CPUIF_BASE + 0x04)
+                                        /* OCP Error Attribute 1        */
+#define OCP_ERR2_REG            regptr(MSP_CPUIF_BASE + 0x08)
+                                        /* OCP Error Attribute 2        */
+#define OCP_STS_REG             regptr(MSP_CPUIF_BASE + 0x0C)
+                                        /* OCP Error Status             */
+#define CPUIF_PM_REG            regptr(MSP_CPUIF_BASE + 0x10)
+                                        /* CPU policy configuration     */
+#define CPUIF_CFG_REG           regptr(MSP_CPUIF_BASE + 0x10)
+                                        /* Misc configuration options   */
+/* Central Interrupt Controller Registers */
+#define MSP_CIC_BASE            (MSP_CPUIF_BASE + 0x8000)
+                                        /* Central Interrupt registers  */
+#define CIC_EXT_CFG_REG         regptr(MSP_CIC_BASE + 0x00)
+                                        /* External interrupt config    */
+#define CIC_STS_REG             regptr(MSP_CIC_BASE + 0x04)
+                                        /* CIC Interrupt Status         */
+#define CIC_VPE0_MSK_REG        regptr(MSP_CIC_BASE + 0x08)
+                                        /* VPE0 Interrupt Mask          */
+#define CIC_VPE1_MSK_REG        regptr(MSP_CIC_BASE + 0x0C)
+                                        /* VPE1 Interrupt Mask          */
+#define CIC_TC0_MSK_REG         regptr(MSP_CIC_BASE + 0x10)
+                                        /* Thread Context 0 Int Mask    */
+#define CIC_TC1_MSK_REG         regptr(MSP_CIC_BASE + 0x14)
+                                        /* Thread Context 1 Int Mask    */
+#define CIC_TC2_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
+                                        /* Thread Context 2 Int Mask    */
+#define CIC_TC3_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
+                                        /* Thread Context 3 Int Mask    */
+#define CIC_TC4_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
+                                        /* Thread Context 4 Int Mask    */
+#define CIC_PCIMSI_STS_REG      regptr(MSP_CIC_BASE + 0x18)
+#define CIC_PCIMSI_MSK_REG      regptr(MSP_CIC_BASE + 0x18)
+#define CIC_PCIFLSH_REG         regptr(MSP_CIC_BASE + 0x18)
+#define CIC_VPE0_SWINT_REG      regptr(MSP_CIC_BASE + 0x08)
+/*
+ ***************************************************************************
+ * Memory controller registers                                             *
+ ***************************************************************************
+ */
+#define MEM_CFG1_REG            regptr(MSP_MEM_CFG_BASE + 0x00)
+#define MEM_SS_ADDR             regptr(MSP_MEM_CFG_BASE + 0x00)
+#define MEM_SS_DATA             regptr(MSP_MEM_CFG_BASE + 0x04)
+#define MEM_SS_WRITE            regptr(MSP_MEM_CFG_BASE + 0x08)
+/*
+ ***************************************************************************
+ * PCI controller registers                                                *
+ ***************************************************************************
+ */
+#define PCI_BASE_REG            regptr(MSP_PCI_BASE + 0x00)
+#define PCI_CONFIG_SPACE_REG    regptr(MSP_PCI_BASE + 0x800)
+#define PCI_JTAG_DEVID_REG      regptr(MSP_SLP_BASE + 0x13c)
+/*
+ ########################################################################
+ #  Register content & macro definitions                                #
+ ########################################################################
+ */
+/*
+ ***************************************************************************
+ * DEV_ID defines                                                          *
+ ***************************************************************************
+ */
+#define DEV_ID_PCI_DIS          (1 << 26)       /* Set if PCI disabled */
+#define DEV_ID_PCI_HOST         (1 << 20)       /* Set if PCI host */
+#define DEV_ID_SINGLE_PC        (1 << 19)       /* Set if single PC Card */
+#define DEV_ID_FAMILY           (0xff << 8)     /* family ID code */
+#define POLO_ZEUS_SUB_FAMILY    (0x7  << 16)    /* sub family for Polo/Zeus */
+#define MSPFPGA_ID              (0x00  << 8)    /* you are on your own here */
+#define MSP5000_ID              (0x50  << 8)
+#define MSP4F00_ID              (0x4f  << 8)    /* FPGA version of MSP4200 */
+#define MSP4E00_ID              (0x4f  << 8)    /* FPGA version of MSP7120 */
+#define MSP4200_ID              (0x42  << 8)
+#define MSP4000_ID              (0x40  << 8)
+#define MSP2XXX_ID              (0x20  << 8)
+#define MSPZEUS_ID              (0x10  << 8)
+#define MSP2004_SUB_ID          (0x0   << 16)
+#define MSP2005_SUB_ID          (0x1   << 16)
+#define MSP2006_SUB_ID          (0x1   << 16)
+#define MSP2007_SUB_ID          (0x2   << 16)
+#define MSP2010_SUB_ID          (0x3   << 16)
+#define MSP2015_SUB_ID          (0x4   << 16)
+#define MSP2020_SUB_ID          (0x5   << 16)
+#define MSP2100_SUB_ID          (0x6   << 16)
+/*
+ ***************************************************************************
+ * RESET defines                                                           *
+ ***************************************************************************
+ */
+#define MSP_GR_RST              (0x01 << 0)     /* Global reset bit     */
+#define MSP_MR_RST              (0x01 << 1)     /* MIPS reset bit       */
+#define MSP_PD_RST              (0x01 << 2)     /* PVC DMA reset bit    */
+#define MSP_PP_RST              (0x01 << 3)     /* PVC reset bit        */
+/* reserved                                                             */
+#define MSP_EA_RST              (0x01 << 6)     /* Mac A reset bit      */
+#define MSP_EB_RST              (0x01 << 7)     /* Mac B reset bit      */
+#define MSP_SE_RST              (0x01 << 8)     /* Security Eng reset bit */
+#define MSP_PB_RST              (0x01 << 9)     /* Per block reset bit  */
+#define MSP_EC_RST              (0x01 << 10)    /* Mac C reset bit      */
+#define MSP_TW_RST              (0x01 << 11)    /* TWI reset bit        */
+#define MSP_SPI_RST             (0x01 << 12)    /* SPI/MPI reset bit    */
+#define MSP_U1_RST              (0x01 << 13)    /* UART1 reset bit      */
+#define MSP_U0_RST              (0x01 << 14)    /* UART0 reset bit      */
+/*
+ ***************************************************************************
+ * UART defines                                                            *
+ ***************************************************************************
+ */
+#ifndef CONFIG_MSP_FPGA
+#define MSP_BASE_BAUD           25000000
+#else
+#define MSP_BASE_BAUD           6000000
+#endif
+#define MSP_UART_REG_LEN        0x20
+/*
+ ***************************************************************************
+ * ELB defines                                                             *
+ ***************************************************************************
+ */
+#define PCCARD_32               0x02    /* Set if is PCCARD 32 (Cardbus) */
+#define SINGLE_PCCARD           0x01    /* Set to enable single PC card */
+/*
+ ***************************************************************************
+ * CIC defines                                                             *
+ ***************************************************************************
+ */
+/* CIC_EXT_CFG_REG */
+#define EXT_INT_POL(eirq)                       (1 << (eirq + 8))
+#define EXT_INT_EDGE(eirq)                      (1 << eirq)
+#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq)    (reg &= ~EXT_INT_EDGE(eirq))
+#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq)     (reg |= EXT_INT_EDGE(eirq))
+#define CIC_EXT_SET_ACTIVE_HI(reg, eirq)        (reg |= EXT_INT_POL(eirq))
+#define CIC_EXT_SET_ACTIVE_LO(reg, eirq)        (reg &= ~EXT_INT_POL(eirq))
+#define CIC_EXT_SET_ACTIVE_RISING               CIC_EXT_SET_ACTIVE_HI
+#define CIC_EXT_SET_ACTIVE_FALLING              CIC_EXT_SET_ACTIVE_LO
+#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
+                                ((reg & EXT_INT_EDGE(eirq)) == 0)
+#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq)      (reg & EXT_INT_EDGE(eirq))
+#define CIC_EXT_IS_ACTIVE_HI(reg, eirq)         (reg & EXT_INT_POL(eirq))
+#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
+                                ((reg & EXT_INT_POL(eirq)) == 0)
+#define CIC_EXT_IS_ACTIVE_RISING                CIC_EXT_IS_ACTIVE_HI
+#define CIC_EXT_IS_ACTIVE_FALLING               CIC_EXT_IS_ACTIVE_LO
+/*
+ ***************************************************************************
+ * Memory Controller defines                                               *
+ ***************************************************************************
+ */
+/* Indirect memory controller registers */
+#define DDRC_CFG(n)             (n)
+#define DDRC_DEBUG(n)           (0x04 + n)
+#define DDRC_CTL(n)             (0x40 + n)
+/* Macro to perform DDRC indirect write */
+#define DDRC_INDIRECT_WRITE(reg, mask, value) \
+({ \
+        *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
+        *MEM_SS_DATA = (value); \
+        *MEM_SS_WRITE = 1; \
+})
+/*
+ ***************************************************************************
+ * SPI/MPI Mode                                                            *
+ ***************************************************************************
+ */
+#define SPI_MPI_RX_BUSY         0x00008000      /* SPI/MPI Receive Busy */
+#define SPI_MPI_FIFO_EMPTY      0x00004000      /* SPI/MPI Fifo Empty   */
+#define SPI_MPI_TX_BUSY         0x00002000      /* SPI/MPI Transmit Busy */
+#define SPI_MPI_FIFO_FULL       0x00001000      /* SPI/MPU FIFO full    */
+/*
+ ***************************************************************************
+ * SPI/MPI Control Register                                                *
+ ***************************************************************************
+ */
+#define SPI_MPI_RX_START        0x00000004      /* Start receive command */
+#define SPI_MPI_FLUSH_Q         0x00000002      /* Flush SPI/MPI Queue */
+#define SPI_MPI_TX_START        0x00000001      /* Start Transmit Command */
+#endif /* !_ASM_MSP_REGS_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
new file mode 100644
index 000000000000..96d4c8ce8c83
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
@@ -0,0 +1,141 @@
+/*
+ * Defines for the MSP interrupt controller.
+ *
+ * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
+ * Author: Carsten Langgaard, carstenl@mips.com
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ */
+#ifndef _MSP_SLP_INT_H
+#define _MSP_SLP_INT_H
+/*
+ * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
+ * hierarchical system.  The first level are the direct MIPS interrupts
+ * and are assigned the interrupt range 0-7.  The second level is the SLM
+ * interrupt controller and is assigned the range 8-39.  The third level
+ * comprises the Peripherial block, the PCI block, the PCI MSI block and
+ * the SLP.  The PCI interrupts and the SLP errors are handled by the
+ * relevant subsystems so the core interrupt code needs only concern
+ * itself with the Peripheral block.  These are assigned interrupts in
+ * the range 40-71.
+ */
+/*
+ * IRQs directly connected to CPU
+ */
+#define MSP_MIPS_INTBASE        0
+#define MSP_INT_SW0             0  /* IRQ for swint0,         C_SW0  */
+#define MSP_INT_SW1             1  /* IRQ for swint1,         C_SW1  */
+#define MSP_INT_MAC0            2  /* IRQ for MAC 0,          C_IRQ0 */
+#define MSP_INT_MAC1            3  /* IRQ for MAC 1,          C_IRQ1 */
+#define MSP_INT_C_IRQ2          4  /* Wired off,              C_IRQ2 */
+#define MSP_INT_VE              5  /* IRQ for Voice Engine,   C_IRQ3 */
+#define MSP_INT_SLP             6  /* IRQ for SLM block,      C_IRQ4 */
+#define MSP_INT_TIMER           7  /* IRQ for the MIPS timer, C_IRQ5 */
+/*
+ * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
+ * These defines should be tied to the register definition for the SLM
+ * interrupt routine.  For now, just use hard-coded values.
+ */
+#define MSP_SLP_INTBASE         (MSP_MIPS_INTBASE + 8)
+#define MSP_INT_EXT0            (MSP_SLP_INTBASE + 0)
+                                        /* External interrupt 0         */
+#define MSP_INT_EXT1            (MSP_SLP_INTBASE + 1)
+                                        /* External interrupt 1         */
+#define MSP_INT_EXT2            (MSP_SLP_INTBASE + 2)
+                                        /* External interrupt 2         */
+#define MSP_INT_EXT3            (MSP_SLP_INTBASE + 3)
+                                        /* External interrupt 3         */
+/* Reserved                                        4-7                  */
+/*
+ *************************************************************************
+ * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
+ * Some MSP produces have this interrupt labelled as Voice and some are  *
+ * SEC mbox ...                                                          *
+ *************************************************************************
+ */
+#define MSP_INT_SLP_VE          (MSP_SLP_INTBASE + 8)
+                                        /* Cascaded IRQ for Voice Engine*/
+#define MSP_INT_SLP_TDM         (MSP_SLP_INTBASE + 9)
+                                        /* TDM interrupt                */
+#define MSP_INT_SLP_MAC0        (MSP_SLP_INTBASE + 10)
+                                        /* Cascaded IRQ for MAC 0       */
+#define MSP_INT_SLP_MAC1        (MSP_SLP_INTBASE + 11)
+                                        /* Cascaded IRQ for MAC 1       */
+#define MSP_INT_SEC             (MSP_SLP_INTBASE + 12)
+                                        /* IRQ for security engine      */
+#define MSP_INT_PER             (MSP_SLP_INTBASE + 13)
+                                        /* Peripheral interrupt         */
+#define MSP_INT_TIMER0          (MSP_SLP_INTBASE + 14)
+                                        /* SLP timer 0                  */
+#define MSP_INT_TIMER1          (MSP_SLP_INTBASE + 15)
+                                        /* SLP timer 1                  */
+#define MSP_INT_TIMER2          (MSP_SLP_INTBASE + 16)
+                                        /* SLP timer 2                  */
+#define MSP_INT_SLP_TIMER       (MSP_SLP_INTBASE + 17)
+                                        /* Cascaded MIPS timer          */
+#define MSP_INT_BLKCP           (MSP_SLP_INTBASE + 18)
+                                        /* Block Copy                   */
+#define MSP_INT_UART0           (MSP_SLP_INTBASE + 19)
+                                        /* UART 0                       */
+#define MSP_INT_PCI             (MSP_SLP_INTBASE + 20)
+                                        /* PCI subsystem                */
+#define MSP_INT_PCI_DBELL       (MSP_SLP_INTBASE + 21)
+                                        /* PCI doorbell                 */
+#define MSP_INT_PCI_MSI         (MSP_SLP_INTBASE + 22)
+                                        /* PCI Message Signal           */
+#define MSP_INT_PCI_BC0         (MSP_SLP_INTBASE + 23)
+                                        /* PCI Block Copy 0             */
+#define MSP_INT_PCI_BC1         (MSP_SLP_INTBASE + 24)
+                                        /* PCI Block Copy 1             */
+#define MSP_INT_SLP_ERR         (MSP_SLP_INTBASE + 25)
+                                        /* SLP error condition          */
+#define MSP_INT_MAC2            (MSP_SLP_INTBASE + 26)
+                                        /* IRQ for MAC2                 */
+/* Reserved                                        26-31                */
+/*
+ * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
+ */
+#define MSP_PER_INTBASE         (MSP_SLP_INTBASE + 32)
+/* Reserved                                        0-1                  */
+#define MSP_INT_UART1           (MSP_PER_INTBASE + 2)
+                                        /* UART 1                       */
+/* Reserved                                        3-5                  */
+#define MSP_INT_2WIRE           (MSP_PER_INTBASE + 6)
+                                        /* 2-wire                       */
+#define MSP_INT_TM0             (MSP_PER_INTBASE + 7)
+                                        /* Peripheral timer block out 0 */
+#define MSP_INT_TM1             (MSP_PER_INTBASE + 8)
+                                        /* Peripheral timer block out 1 */
+/* Reserved                                        9                    */
+#define MSP_INT_SPRX            (MSP_PER_INTBASE + 10)
+                                        /* SPI RX complete              */
+#define MSP_INT_SPTX            (MSP_PER_INTBASE + 11)
+                                        /* SPI TX complete              */
+#define MSP_INT_GPIO            (MSP_PER_INTBASE + 12)
+                                        /* GPIO                         */
+#define MSP_INT_PER_ERR         (MSP_PER_INTBASE + 13)
+                                        /* Peripheral error             */
+/* Reserved                                        14-31                */
+#endif /* !_MSP_SLP_INT_H */
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index 5f80ba71ab92..1d8b9a8ae324 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -82,10 +82,6 @@ struct mips_fpu_struct {
        unsigned int    fcr31;
 };
-#define INIT_FPU { \
-        {0,} \
-}
 #define NUM_DSP_REGS   6
 typedef __u32 dspreg_t;
@@ -95,8 +91,6 @@ struct mips_dsp_state {
        unsigned int    dspcontrol;
 };
-#define INIT_DSP {{0,},}
 #define INIT_CPUMASK { \
        {0,} \
 }
@@ -155,41 +149,63 @@ struct thread_struct {
 #define MF_N64          0
 #ifdef CONFIG_MIPS_MT_FPAFF
-#define FPAFF_INIT 0, INIT_CPUMASK,
+#define FPAFF_INIT                                              \
+        .emulated_fp                    = 0,                    \
+        .user_cpus_allowed              = INIT_CPUMASK,
 #else
 #define FPAFF_INIT
 #endif /* CONFIG_MIPS_MT_FPAFF */
-#define INIT_THREAD  { \
+#define INIT_THREAD  {                                          \
-        /* \
+        /*                                                      \
-         * saved main processor registers \
+         * Saved main processor registers                       \
-         */ \
+         */                                                     \
-        0, 0, 0, 0, 0, 0, 0, 0, \
+        .reg16                  = 0,                            \
-                       0, 0, 0, \
+        .reg17                  = 0,                            \
-        /* \
+        .reg18                  = 0,                            \
-         * saved cp0 stuff \
+        .reg19                  = 0,                            \
-         */ \
+        .reg20                  = 0,                            \
-        0, \
+        .reg21                  = 0,                            \
-        /* \
+        .reg22                  = 0,                            \
-         * saved fpu/fpu emulator stuff \
+        .reg23                  = 0,                            \
-         */ \
+        .reg29                  = 0,                            \
-        INIT_FPU, \
+        .reg30                  = 0,                            \
-        /* \
+        .reg31                  = 0,                            \
-         * fpu affinity state (null if not FPAFF) \
+        /*                                                      \
-         */ \
+         * Saved cp0 stuff                                      \
-        FPAFF_INIT \
+         */                                                     \
-        /* \
+        .cp0_status             = 0,                            \
-         * saved dsp/dsp emulator stuff \
+        /*                                                      \
-         */ \
+         * Saved FPU/FPU emulator stuff                         \
-        INIT_DSP, \
+         */                                                     \
-        /* \
+        .fpu                    = {                             \
-         * Other stuff associated with the process \
+                .fpr            = {0,},                         \
-         */ \
+                .fcr31          = 0,                            \
-        0, 0, 0, 0, \
+        },                                                      \
-        /* \
+        /*                                                      \
-         * For now the default is to fix address errors \
+         * FPU affinity state (null if not FPAFF)               \
-         */ \
+         */                                                     \
-        MF_FIXADE, 0, 0 \
+        FPAFF_INIT                                              \
+        /*                                                      \
+         * Saved DSP stuff                                      \
+         */                                                     \
+        .dsp                    = {                             \
+                .dspr           = {0, },                        \
+                .dspcontrol     = 0,                            \
+        },                                                      \
+        /*                                                      \
+         * Other stuff associated with the process              \
+         */                                                     \
+        .cp0_badvaddr           = 0,                            \
+        .cp0_baduaddr           = 0,                            \
+        .error_code             = 0,                            \
+        .trap_no                = 0,                            \
+        /*                                                      \
+         * For now the default is to fix address errors         \
+         */                                                     \
+        .mflags                 = MF_FIXADE,                    \
+        .irix_trampoline        = 0,                            \
+        .irix_oldctx            = 0,                            \
 }
 struct task_struct;
@@ -237,7 +253,7 @@ unsigned long get_wchan(struct task_struct *p);
 #define ARCH_HAS_PREFETCH
-extern inline void prefetch(const void *addr)
+static inline void prefetch(const void *addr)
 {
        __asm__ __volatile__(
        "       .set    mips4           \n"
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 1906938285c0..85b44366343a 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -86,7 +86,7 @@ struct pt_regs {
 extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
-extern NORET_TYPE void die(const char *, struct pt_regs *);
+extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET;
 static inline void die_if_kernel(const char *str, struct pt_regs *regs)
 {
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index ce51213d84f9..c07ebd8eb9e7 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -19,159 +19,4 @@
 */
 #define BASE_BAUD (1843200 / 16)
-/* Standard COM flags (except for COM4, because of the 8514 problem) */
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
-#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
-#endif
-#ifdef CONFIG_MACH_JAZZ
-#include <asm/jazz.h>
-#ifndef CONFIG_OLIVETTI_M700
-   /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
-      exactly which ones ... XXX */
-#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
-#else
-/* but the M700 isn't such a strange beast */
-#define JAZZ_BASE_BAUD BASE_BAUD
-#endif
-#define _JAZZ_SERIAL_INIT(int, base)                                    \
-        { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,      \
-          .iomem_base = (u8 *) base, .iomem_reg_shift = 0,                      \
-          .io_type = SERIAL_IO_MEM }
-#define JAZZ_SERIAL_PORT_DEFNS                                          \
-        _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE),         \
-        _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
-#else
-#define JAZZ_SERIAL_PORT_DEFNS
-#endif
-/*
- * Galileo EV64120 evaluation board
- */
-#ifdef CONFIG_MIPS_EV64120
-#include <mach-gt64120.h>
-#define EV64120_SERIAL_PORT_DEFNS                                  \
-    { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
-      .flags = STD_COM_FLAGS,  \
-      .iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \
-      .io_type = SERIAL_IO_MEM }, \
-    { .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
-      .flags = STD_COM_FLAGS, \
-      .iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \
-      .io_type = SERIAL_IO_MEM },
-#else
-#define EV64120_SERIAL_PORT_DEFNS
-#endif
-#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
-#define STD_SERIAL_PORT_DEFNS                   \
-        /* UART CLK   PORT IRQ     FLAGS        */                      \
-        { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
-        { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
-        { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
-        { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
-#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
-#define STD_SERIAL_PORT_DEFNS
-#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
-#ifdef CONFIG_MOMENCO_OCELOT_3
-#define OCELOT_3_BASE_BAUD      ( 20000000 / 16 )
-#define OCELOT_3_SERIAL_IRQ     6
-#define OCELOT_3_SERIAL_BASE    (signed)0xfd000020
-#define _OCELOT_3_SERIAL_INIT(int, base)                                \
-        { .baud_base = OCELOT_3_BASE_BAUD, irq: int,                    \
-          .flags = STD_COM_FLAGS,                                               \
-          .iomem_base = (u8 *) base, iomem_reg_shift: 2,                        \
-          io_type: SERIAL_IO_MEM }
-#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS                              \
-        _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
-#else
-#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
-#endif
-#ifdef CONFIG_MOMENCO_OCELOT
-/* Ordinary NS16552 duart with a 20MHz crystal.  */
-#define OCELOT_BASE_BAUD ( 20000000 / 16 )
-#define OCELOT_SERIAL1_IRQ      4
-#define OCELOT_SERIAL1_BASE     0xe0001020
-#define _OCELOT_SERIAL_INIT(int, base)                                  \
-        { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,    \
-          .iomem_base = (u8 *) base, .iomem_reg_shift = 2,                      \
-          .io_type = SERIAL_IO_MEM }
-#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS                                \
-        _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
-#else
-#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
-#endif
-#ifdef CONFIG_MOMENCO_OCELOT_C
-/* Ordinary NS16552 duart with a 20MHz crystal.  */
-#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
-#define OCELOT_C_SERIAL1_IRQ    80
-#define OCELOT_C_SERIAL1_BASE   0xfd000020
-#define OCELOT_C_SERIAL2_IRQ    81
-#define OCELOT_C_SERIAL2_BASE   0xfd000000
-#define _OCELOT_C_SERIAL_INIT(int, base)                                \
-        { .baud_base            = OCELOT_C_BASE_BAUD,                   \
-          .irq                  = (int),                                \
-          .flags                = STD_COM_FLAGS,                        \
-          .iomem_base           = (u8 *) base,                          \
-          .iomem_reg_shift      = 2,                                    \
-          .io_type              = SERIAL_IO_MEM                         \
-         }
-#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS                              \
-        _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
-        _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
-#else
-#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
-#endif
-#ifdef CONFIG_DDB5477
-#include <asm/ddb5xxx/ddb5477.h>
-#define DDB5477_SERIAL_PORT_DEFNS                                       \
-        { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0,             \
-          .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200,        \
-          .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},              \
-        { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1,             \
-          .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240,        \
-          .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
-#else
-#define DDB5477_SERIAL_PORT_DEFNS
-#endif
-#ifdef CONFIG_SGI_IP32
-/*
- * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
- * They are initialized in ip32_setup
- */
-#define IP32_SERIAL_PORT_DEFNS                          \
-        {},{},
-#else
-#define IP32_SERIAL_PORT_DEFNS
-#endif /* CONFIG_SGI_IP32 */
-#define SERIAL_PORT_DFNS                                \
-        DDB5477_SERIAL_PORT_DEFNS                       \
-        EV64120_SERIAL_PORT_DEFNS                       \
-        IP32_SERIAL_PORT_DEFNS                          \
-        JAZZ_SERIAL_PORT_DEFNS                          \
-        STD_SERIAL_PORT_DEFNS                           \
-        MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS              \
-        MOMENCO_OCELOT_SERIAL_PORT_DEFNS                \
-        MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
 #endif /* _ASM_SERIAL_H */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 1608fd71d6f7..13aef6af422c 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -49,13 +49,6 @@ extern struct call_data_struct *call_data;
 extern cpumask_t phys_cpu_present_map;
 #define cpu_possible_map        phys_cpu_present_map
-extern cpumask_t cpu_callout_map;
-/* We don't mark CPUs online until __cpu_up(), so we need another measure */
-static inline int num_booting_cpus(void)
-{
-        return cpus_weight(cpu_callout_map);
-}
 /*
 * These are defined by the board-specific code.
 */
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index f257509b914f..ddaf36a1e389 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -146,9 +146,6 @@ extern unsigned int sni_brd_type;
 #define SNI_A20R_IRQ_BASE       MIPS_CPU_IRQ_BASE
 #define SNI_A20R_IRQ_TIMER      (SNI_A20R_IRQ_BASE+5)
-#define SNI_DS1216_A20R_BASE    0xbc081ffc
-#define SNI_DS1216_RM200_BASE   0xbcd41ffc
 #define SNI_PCIT_INT_REG        0xbfff000c
 #define SNI_PCIT_INT_START      24
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index bb0b289dbc9e..46bdb3f566f9 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -44,7 +44,7 @@ struct task_struct;
 * different thread.
 */
-#define switch_to(prev,next,last)                                       \
+#define __mips_mt_fpaff_switch_to(prev)                                 \
 do {                                                                    \
        if (cpu_has_fpu &&                                              \
            (prev->thread.mflags & MF_FPUBOUND) &&                      \
@@ -52,24 +52,24 @@ do {									\
                prev->thread.mflags &= ~MF_FPUBOUND;                    \
                prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
        }                                                               \
-        if (cpu_has_dsp)                                                \
-                __save_dsp(prev);                                       \
        next->thread.emulated_fp = 0;                                   \
-        (last) = resume(prev, next, task_thread_info(next));            \
-        if (cpu_has_dsp)                                                \
-                __restore_dsp(current);                                 \
 } while(0)
 #else
+#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
+#endif
 #define switch_to(prev,next,last)                                       \
 do {                                                                    \
+        __mips_mt_fpaff_switch_to(prev);                                \
        if (cpu_has_dsp)                                                \
                __save_dsp(prev);                                       \
        (last) = resume(prev, next, task_thread_info(next));            \
        if (cpu_has_dsp)                                                \
                __restore_dsp(current);                                 \
+        if (cpu_has_userlocal)                                          \
+                write_c0_userlocal(task_thread_info(current)->tp_value);\
 } while(0)
-#endif
 /*
 * On SMP systems, when the scheduler does migration-cost autodetection,
diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h
index 0bbe07b42a07..5bfdc3b64510 100644
--- a/include/asm-mips/termbits.h
+++ b/include/asm-mips/termbits.h
@@ -30,6 +30,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index 0fbedafdcea8..74e7d8061e58 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -105,12 +105,6 @@
 #define rbtx4938_pcireset_ptr   \
        ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
-/* SPI */
-#define RBTX4938_SEEPROM1_CHIPID        0
-#define RBTX4938_SEEPROM2_CHIPID        1
-#define RBTX4938_SEEPROM3_CHIPID        2
-#define RBTX4938_SRTC_CHIPID    3
 /*
 * IRQ mappings
 */
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h
index 0dbbab820a5a..6a60c83e152b 100644
--- a/include/asm-mips/tx4938/spi.h
+++ b/include/asm-mips/tx4938/spi.h
@@ -14,61 +14,7 @@
 #ifndef __ASM_TX_BOARDS_TX4938_SPI_H
 #define __ASM_TX_BOARDS_TX4938_SPI_H
-/* SPI */
+extern int spi_eeprom_register(int chipid);
-struct spi_dev_desc {
-        unsigned int baud;
-        unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */
-        unsigned int byteorder:1;       /* 0:LSB-First, 1:MSB-First */
-        unsigned int polarity:1;        /* 0:High-Active */
-        unsigned int phase:1;           /* 0:Sample-Then-Shift */
-};
-extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init;
-extern void txx9_spi_irqinit(int irc_irq) __init;
-extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
-                       unsigned char **inbufs, unsigned int *incounts,
-                       unsigned char **outbufs, unsigned int *outcounts,
-                       int cansleep);
-extern int spi_eeprom_write_enable(int chipid, int enable);
-extern int spi_eeprom_read_status(int chipid);
 extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
-extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len);
-extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init;
-#define TXX9_IMCLK     (txx9_gbus_clock / 2)
-/*
-* SPI
-*/
-/* SPMCR : SPI Master Control */
-#define TXx9_SPMCR_OPMODE       0xc0
-#define TXx9_SPMCR_CONFIG       0x40
-#define TXx9_SPMCR_ACTIVE       0x80
-#define TXx9_SPMCR_SPSTP        0x02
-#define TXx9_SPMCR_BCLR 0x01
-/* SPCR0 : SPI Status */
-#define TXx9_SPCR0_TXIFL_MASK   0xc000
-#define TXx9_SPCR0_RXIFL_MASK   0x3000
-#define TXx9_SPCR0_SIDIE        0x0800
-#define TXx9_SPCR0_SOEIE        0x0400
-#define TXx9_SPCR0_RBSIE        0x0200
-#define TXx9_SPCR0_TBSIE        0x0100
-#define TXx9_SPCR0_IFSPSE       0x0010
-#define TXx9_SPCR0_SBOS 0x0004
-#define TXx9_SPCR0_SPHA 0x0002
-#define TXx9_SPCR0_SPOL 0x0001
-/* SPSR : SPI Status */
-#define TXx9_SPSR_TBSI  0x8000
-#define TXx9_SPSR_RBSI  0x4000
-#define TXx9_SPSR_TBS_MASK      0x3800
-#define TXx9_SPSR_RBS_MASK      0x0700
-#define TXx9_SPSR_SPOE  0x0080
-#define TXx9_SPSR_IFSD  0x0008
-#define TXx9_SPSR_SIDLE 0x0004
-#define TXx9_SPSR_STRDY 0x0002
-#define TXx9_SPSR_SRRDY 0x0001
 #endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 59d6fec8fbff..ed16de0a6398 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -977,6 +977,22 @@
 #  define __ARCH_WANT_COMPAT_SYS_TIME
 # endif
+/* whitelists for checksyscalls */
+#define __IGNORE_select
+#define __IGNORE_vfork
+#define __IGNORE_time
+#define __IGNORE_uselib
+#define __IGNORE_fadvise64_64
+#define __IGNORE_getdents64
+#if _MIPS_SIM == _MIPS_SIM_NABI32
+#define __IGNORE_truncate64
+#define __IGNORE_ftruncate64
+#define __IGNORE_stat64
+#define __IGNORE_lstat64
+#define __IGNORE_fstat64
+#define __IGNORE_fstatat64
+#endif
 #endif /* !__ASSEMBLY__ */
 /*
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index 13a3502eef44..9de52a5b0f3d 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -169,26 +169,28 @@
 /*
 * On the RM9000 there is a problem which makes the CreateDirtyExclusive
- * cache operation unusable on SMP systems.
+ * eache operation unusable on SMP systems.
 */
-#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
+#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
-    defined(CONFIG_BASLER_EXCITE)
 #define  RM9000_CDEX_SMP_WAR            1
 #endif
 /*
- * The RM9000 has a bug (though PMC-Sierra opposes it being called that)
+ * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
- * where invalid instructions in the same I-cache line worth of instructions
+ * opposes it being called that) where invalid instructions in the same
- * being fetched may case spurious exceptions.
+ * I-cache line worth of instructions being fetched may case spurious
+ * exceptions.
 */
-#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
+#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \
-    defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
+    defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \
+    defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \
+    defined(CONFIG_WR_PPMC)
 #define ICACHE_REFILLS_WORKAROUND_WAR   1
 #endif
 /*
- * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
+ * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
 * may cause ll / sc and lld / scd sequences to execute non-atomically.
 */
 #ifdef CONFIG_SGI_IP27
@@ -196,6 +198,14 @@
 #endif
 /*
+ * 34K core erratum: "Problems Executing the TLBR Instruction"
+ */
+#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
+        defined(CONFIG_PMC_MSP7120_FPGA)
+#define MIPS34K_MISSED_ITLB_WAR         1
+#endif
+/*
 * Workarounds default to off
 */
 #ifndef ICACHE_REFILLS_WORKAROUND_WAR
@@ -234,5 +244,8 @@
 #ifndef R10000_LLSC_WAR
 #define R10000_LLSC_WAR                 0
 #endif
+#ifndef MIPS34K_MISSED_ITLB_WAR
+#define MIPS34K_MISSED_ITLB_WAR         0
+#endif
 #endif /* _ASM_WAR_H */
diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h
deleted file mode 100644
index 6aa90cae1114..000000000000
--- a/include/asm-mips/watch.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1998, 2000, 2001 by Ralf Baechle
- */
-#ifndef _ASM_WATCH_H
-#define _ASM_WATCH_H
-#include <linux/linkage.h>
-/*
- * Types of reference for watch_set()
- */
-enum wref_type {
-        wr_save = 1,
-        wr_load = 2
-};
-extern asmlinkage void __watch_set(unsigned long addr, enum wref_type ref);
-extern asmlinkage void __watch_clear(void);
-extern asmlinkage void __watch_reenable(void);
-#define watch_set(addr, ref)                                    \
-        if (cpu_has_watch)                                      \
-                __watch_set(addr, ref)
-#define watch_clear()                                           \
-        if (cpu_has_watch)                                      \
-                __watch_clear()
-#define watch_reenable()                                        \
-        if (cpu_has_watch)                                      \
-                __watch_reenable()
-#endif /* _ASM_WATCH_H */
diff --git a/include/asm-parisc/hardware.h b/include/asm-parisc/hardware.h
index 76d880dc4bae..4e9626836bab 100644
--- a/include/asm-parisc/hardware.h
+++ b/include/asm-parisc/hardware.h
@@ -31,10 +31,11 @@ enum cpu_type {
        pcxw    = 8, /* pa8500          pa 2.0  */
        pcxw_   = 9, /* pa8600  (w+)    pa 2.0  */
        pcxw2   = 10, /* pa8700         pa 2.0  */
-        mako    = 11  /* pa8800         pa 2.0  */
+        mako    = 11, /* pa8800         pa 2.0  */
+        mako2   = 12  /* pa8900         pa 2.0  */
 };
-extern char *cpu_name_version[][2]; /* mapping from enum cpu_type to strings */
+extern const char * const cpu_name_version[][2]; /* mapping from enum cpu_type to strings */
 struct parisc_driver;
diff --git a/include/asm-parisc/linkage.h b/include/asm-parisc/linkage.h
index 7a09d911b538..ad8cd0d069ea 100644
--- a/include/asm-parisc/linkage.h
+++ b/include/asm-parisc/linkage.h
@@ -8,8 +8,10 @@
 /*
 * In parisc assembly a semicolon marks a comment while a
- * exclamation mark is used to seperate independend lines.
+ * exclamation mark is used to seperate independent lines.
 */
+#ifdef __ASSEMBLY__
 #define ENTRY(name) \
        .export name !\
        ALIGN !\
@@ -24,5 +26,6 @@ name:
        END(name)
 #endif
+#endif /* __ASSEMBLY__ */
 #endif  /* __ASM_PARISC_LINKAGE_H */
diff --git a/include/asm-parisc/processor.h b/include/asm-parisc/processor.h
index d2f396721d3e..6b294fb07a23 100644
--- a/include/asm-parisc/processor.h
+++ b/include/asm-parisc/processor.h
@@ -69,8 +69,8 @@ struct system_cpuinfo_parisc {
                char   sys_model_name[81]; /* PDC-ROM returnes this model name */
        } pdc;
-        char            *cpu_name;      /* e.g. "PA7300LC (PCX-L2)" */
+        const char      *cpu_name;      /* e.g. "PA7300LC (PCX-L2)" */
-        char            *family_name;   /* e.g. "1.1e" */
+        const char      *family_name;   /* e.g. "1.1e" */
 };
@@ -334,8 +334,8 @@ extern unsigned long get_wchan(struct task_struct *p);
 static inline int parisc_requires_coherency(void)
 {
 #ifdef CONFIG_PA8X00
-        /* FIXME: also pa8900 - when we see one */
+        return (boot_cpu_data.cpu_type == mako) ||
-        return boot_cpu_data.cpu_type == mako;
+                (boot_cpu_data.cpu_type == mako2);
 #else
        return 0;
 #endif
diff --git a/include/asm-parisc/system.h b/include/asm-parisc/system.h
index 7e9afa720d43..21fbfc5afd02 100644
--- a/include/asm-parisc/system.h
+++ b/include/asm-parisc/system.h
@@ -188,7 +188,6 @@ static inline void set_eiem(unsigned long val)
 # define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
 #endif
-#define KERNEL_START (0x10100000 - 0x1000)
 #define arch_align_stack(x) (x)
 #endif
diff --git a/include/asm-parisc/termbits.h b/include/asm-parisc/termbits.h
index a46e299a9391..e847fe979684 100644
--- a/include/asm-parisc/termbits.h
+++ b/include/asm-parisc/termbits.h
@@ -17,6 +17,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-parisc/unistd.h b/include/asm-parisc/unistd.h
index 2f7c40861c91..f74099bdca3c 100644
--- a/include/asm-parisc/unistd.h
+++ b/include/asm-parisc/unistd.h
@@ -792,8 +792,19 @@
 #define __NR_epoll_pwait        (__NR_Linux + 297)
 #define __NR_statfs64           (__NR_Linux + 298)
 #define __NR_fstatfs64          (__NR_Linux + 299)
+#define __NR_kexec_load         (__NR_Linux + 300)
+#define __NR_utimensat          (__NR_Linux + 301)
+#define __NR_signalfd           (__NR_Linux + 302)
+#define __NR_timerfd            (__NR_Linux + 303)
+#define __NR_eventfd            (__NR_Linux + 304)
+#define __NR_Linux_syscalls     (__NR_eventfd + 1)
+#define __IGNORE_select         /* newselect */
+#define __IGNORE_fadvise64      /* fadvise64_64 */
+#define __IGNORE_utimes         /* utime */
-#define __NR_Linux_syscalls     (__NR_fstatfs64 + 1)
 #define HPUX_GATEWAY_ADDR       0xC0000004
 #define LINUX_GATEWAY_ADDR      0x100
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 5b14536d4af8..b2b880a6f631 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -661,10 +661,14 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 }
 #define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-        do {                                                               \
+({                                                                         \
-                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+        int __changed = !pte_same(*(__ptep), __entry);                     \
-                flush_tlb_page_nohash(__vma, __address);                   \
+        if (__changed) {                                                   \
-        } while(0)
+                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+                flush_tlb_page_nohash(__vma, __address);                   \
+        }                                                                  \
+        __changed;                                                         \
+})
 /*
 * Macro to mark a page protection value as "uncacheable".
diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h
index d61178dea670..4ea99922a75c 100644
--- a/include/asm-powerpc/pgtable-ppc64.h
+++ b/include/asm-powerpc/pgtable-ppc64.h
@@ -408,10 +408,14 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
        :"cc");
 }
 #define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-        do {                                                               \
+({                                                                         \
-                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+        int __changed = !pte_same(*(__ptep), __entry);                     \
-                flush_tlb_page_nohash(__vma, __address);                   \
+        if (__changed) {                                                   \
-        } while(0)
+                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+                flush_tlb_page_nohash(__vma, __address);                   \
+        }                                                                  \
+        __changed;                                                         \
+})
 /*
 * Macro to mark a page protection value as "uncacheable".
diff --git a/include/asm-powerpc/systbl.h b/include/asm-powerpc/systbl.h
index 700ca5928741..1cc3f9cb6f4e 100644
--- a/include/asm-powerpc/systbl.h
+++ b/include/asm-powerpc/systbl.h
@@ -311,3 +311,4 @@ COMPAT_SYS_SPU(utimensat)
 COMPAT_SYS_SPU(signalfd)
 COMPAT_SYS_SPU(timerfd)
 SYSCALL_SPU(eventfd)
+COMPAT_SYS_SPU(sync_file_range2)
diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h
index e3c28dc31abf..f71c6061f1ec 100644
--- a/include/asm-powerpc/unistd.h
+++ b/include/asm-powerpc/unistd.h
@@ -330,10 +330,11 @@
 #define __NR_signalfd           305
 #define __NR_timerfd            306
 #define __NR_eventfd            307
+#define __NR_sync_file_range2   308
 #ifdef __KERNEL__
-#define __NR_syscalls           308
+#define __NR_syscalls           309
 #define __NR__exit __NR_exit
 #define NR_syscalls     __NR_syscalls
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index bed452d4a5f0..9d0ce9ff5840 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -694,10 +694,14 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 }
 #define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-        do {                                                               \
+({                                                                         \
-                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+        int __changed = !pte_same(*(__ptep), __entry);                     \
-                flush_tlb_page_nohash(__vma, __address);                   \
+        if (__changed) {                                                   \
-        } while(0)
+                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+                flush_tlb_page_nohash(__vma, __address);                   \
+        }                                                                  \
+        __changed;                                                         \
+})
 /*
 * Macro to mark a page protection value as "uncacheable".
diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h
index c17bdbf22067..ea486952f778 100644
--- a/include/asm-s390/atomic.h
+++ b/include/asm-s390/atomic.h
@@ -24,7 +24,7 @@
 */
 typedef struct {
-        volatile int counter;
+        int counter;
 } __attribute__ ((aligned (4))) atomic_t;
 #define ATOMIC_INIT(i)  { (i) }
@@ -141,7 +141,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
 #ifdef __s390x__
 typedef struct {
-        volatile long long counter;
+        long long counter;
 } __attribute__ ((aligned (8))) atomic64_t;
 #define ATOMIC64_INIT(i)  { (i) }
diff --git a/include/asm-s390/cmb.h b/include/asm-s390/cmb.h
index 241756f80df3..021e7c3223ec 100644
--- a/include/asm-s390/cmb.h
+++ b/include/asm-s390/cmb.h
@@ -88,7 +88,6 @@ extern u64 cmf_read(struct ccw_device *cdev, int index);
 *    any
 **/
 extern int cmf_readall(struct ccw_device *cdev, struct cmbdata*data);
-extern void cmf_reset(struct ccw_device *cdev);
 #endif /* __KERNEL__ */
 #endif /* S390_CMB_H */
diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h
index 8fe8d42e64c3..0a307bb2f353 100644
--- a/include/asm-s390/pgtable.h
+++ b/include/asm-s390/pgtable.h
@@ -744,7 +744,12 @@ ptep_establish(struct vm_area_struct *vma,
 }
 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-        ptep_establish(__vma, __address, __ptep, __entry)
+({                                                                        \
+        int __changed = !pte_same(*(__ptep), __entry);                    \
+        if (__changed)                                                    \
+                ptep_establish(__vma, __address, __ptep, __entry);        \
+        __changed;                                                        \
+})
 /*
 * Test and clear dirty bit in storage key.
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
index e0fcea8c64c3..3b972d4c6b29 100644
--- a/include/asm-s390/processor.h
+++ b/include/asm-s390/processor.h
@@ -216,6 +216,11 @@ static inline void cpu_relax(void)
        barrier();
 }
+static inline void psw_set_key(unsigned int key)
+{
+        asm volatile("spka 0(%0)" : : "d" (key));
+}
 /*
 * Set PSW to specified value.
 */
@@ -352,8 +357,8 @@ extern void (*s390_base_ext_handler_fn)(void);
 /*
 * CPU idle notifier chain.
 */
-#define CPU_IDLE        0
+#define S390_CPU_IDLE           0
-#define CPU_NOT_IDLE    1
+#define S390_CPU_NOT_IDLE       1
 struct notifier_block;
 int register_idle_notifier(struct notifier_block *nb);
diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h
index fa6ca87080e8..332ee73688fc 100644
--- a/include/asm-s390/ptrace.h
+++ b/include/asm-s390/ptrace.h
@@ -470,14 +470,7 @@ struct user_regs_struct
 #define regs_return_value(regs)((regs)->gprs[2])
 #define profile_pc(regs) instruction_pointer(regs)
 extern void show_regs(struct pt_regs * regs);
-#endif
+#endif /* __KERNEL__ */
-static inline void
-psw_set_key(unsigned int key)
-{
-        asm volatile("spka 0(%0)" : : "d" (key));
-}
 #endif /* __ASSEMBLY__ */
 #endif /* _S390_PTRACE_H */
diff --git a/include/asm-s390/sclp.h b/include/asm-s390/sclp.h
index 21ed64773210..cb9faf1ea5cf 100644
--- a/include/asm-s390/sclp.h
+++ b/include/asm-s390/sclp.h
@@ -11,29 +11,6 @@
 #include <linux/types.h>
 #include <asm/chpid.h>
-struct sccb_header {
-        u16     length;
-        u8      function_code;
-        u8      control_mask[3];
-        u16     response_code;
-} __attribute__((packed));
-#define LOADPARM_LEN 8
-struct sclp_readinfo_sccb {
-        struct  sccb_header header;     /* 0-7 */
-        u16     rnmax;                  /* 8-9 */
-        u8      rnsize;                 /* 10 */
-        u8      _reserved0[24 - 11];    /* 11-23 */
-        u8      loadparm[LOADPARM_LEN]; /* 24-31 */
-        u8      _reserved1[91 - 32];    /* 32-90 */
-        u8      flags;                  /* 91 */
-        u8      _reserved2[100 - 92];   /* 92-99 */
-        u32     rnsize2;                /* 100-103 */
-        u64     rnmax2;                 /* 104-111 */
-        u8      _reserved3[4096 - 112]; /* 112-4095 */
-} __attribute__((packed, aligned(4096)));
 #define SCLP_CHP_INFO_MASK_SIZE         32
 struct sclp_chp_info {
@@ -42,12 +19,22 @@ struct sclp_chp_info {
        u8 configured[SCLP_CHP_INFO_MASK_SIZE];
 };
-extern struct sclp_readinfo_sccb s390_readinfo_sccb;
+#define LOADPARM_LEN 8
-extern void sclp_readinfo_early(void);
-extern int sclp_sdias_blk_count(void);
+struct sclp_ipl_info {
-extern int sclp_sdias_copy(void *dest, int blk_num, int nr_blks);
+        int is_valid;
-extern int sclp_chp_configure(struct chp_id chpid);
+        int has_dump;
-extern int sclp_chp_deconfigure(struct chp_id chpid);
+        char loadparm[LOADPARM_LEN];
-extern int sclp_chp_read_info(struct sclp_chp_info *info);
+};
+void sclp_readinfo_early(void);
+void sclp_facilities_detect(void);
+unsigned long long sclp_memory_detect(void);
+int sclp_sdias_blk_count(void);
+int sclp_sdias_copy(void *dest, int blk_num, int nr_blks);
+int sclp_chp_configure(struct chp_id chpid);
+int sclp_chp_deconfigure(struct chp_id chpid);
+int sclp_chp_read_info(struct sclp_chp_info *info);
+void sclp_get_ipl_info(struct sclp_ipl_info *info);
 #endif /* _ASM_S390_SCLP_H */
diff --git a/include/asm-s390/sfp-machine.h b/include/asm-s390/sfp-machine.h
index 8ca8c77b2d04..4e16aede4b06 100644
--- a/include/asm-s390/sfp-machine.h
+++ b/include/asm-s390/sfp-machine.h
@@ -27,9 +27,9 @@
   
 #define _FP_W_TYPE_SIZE         32
-#define _FP_W_TYPE              unsigned long
+#define _FP_W_TYPE              unsigned int
-#define _FP_WS_TYPE             signed long
+#define _FP_WS_TYPE             signed int
-#define _FP_I_TYPE              long
+#define _FP_I_TYPE              int
 #define _FP_MUL_MEAT_S(R,X,Y)                                   \
  _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
diff --git a/include/asm-s390/sfp-util.h b/include/asm-s390/sfp-util.h
index 8cabcd23d976..0addc6466d95 100644
--- a/include/asm-s390/sfp-util.h
+++ b/include/asm-s390/sfp-util.h
@@ -51,6 +51,16 @@
        wl = __wl;                                      \
 })
+#ifdef __s390x__
+#define udiv_qrnnd(q, r, n1, n0, d)                     \
+  do { unsigned long __n;                               \
+       unsigned int __r, __d;                           \
+    __n = ((unsigned long)(n1) << 32) + n0;             \
+    __d = (d);                                          \
+    (q) = __n / __d;                                    \
+    (r) = __n % __d;                                    \
+  } while (0)
+#else
 #define udiv_qrnnd(q, r, n1, n0, d)                     \
  do { unsigned int __r;                                \
    (q) = __udiv_qrnnd (&__r, (n1), (n0), (d));         \
@@ -58,6 +68,7 @@
  } while (0)
 extern unsigned long __udiv_qrnnd (unsigned int *, unsigned int,
                                   unsigned int , unsigned int);
+#endif
 #define UDIV_NEEDS_NORMALIZATION 0
diff --git a/include/asm-s390/termbits.h b/include/asm-s390/termbits.h
index 585c78a6e407..811b9a9cdc08 100644
--- a/include/asm-s390/termbits.h
+++ b/include/asm-s390/termbits.h
@@ -25,6 +25,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-sh/termbits.h b/include/asm-sh/termbits.h
index f1b7b46f4e9a..7ee1b42eeab0 100644
--- a/include/asm-sh/termbits.h
+++ b/include/asm-sh/termbits.h
@@ -17,6 +17,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h
index 4f0a5ba0d6a0..59229aeba27b 100644
--- a/include/asm-sparc/pgtable.h
+++ b/include/asm-sparc/pgtable.h
@@ -446,6 +446,17 @@ extern int io_remap_pfn_range(struct vm_area_struct *vma,
 #define GET_IOSPACE(pfn)                (pfn >> (BITS_PER_LONG - 4))
 #define GET_PFN(pfn)                    (pfn & 0x0fffffffUL)
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+({                                                                        \
+        int __changed = !pte_same(*(__ptep), __entry);                    \
+        if (__changed) {                                                  \
+                set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
+                flush_tlb_page(__vma, __address);                         \
+        }                                                                 \
+        (sparc_cpu_model == sun4c) || __changed;                          \
+})
 #include <asm-generic/pgtable.h>
 #endif /* !(__ASSEMBLY__) */
diff --git a/include/asm-sparc64/dma-mapping.h b/include/asm-sparc64/dma-mapping.h
index 4e21c2f3065c..c58ec1661df8 100644
--- a/include/asm-sparc64/dma-mapping.h
+++ b/include/asm-sparc64/dma-mapping.h
@@ -15,8 +15,7 @@
 static inline int
 dma_supported(struct device *dev, u64 mask)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        return pci_dma_supported(to_pci_dev(dev), mask);
 }
@@ -24,8 +23,7 @@ dma_supported(struct device *dev, u64 mask)
 static inline int
 dma_set_mask(struct device *dev, u64 dma_mask)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        return pci_set_dma_mask(to_pci_dev(dev), dma_mask);
 }
@@ -34,8 +32,7 @@ static inline void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
                   gfp_t flag)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        return pci_iommu_ops->alloc_consistent(to_pci_dev(dev), size, dma_handle, flag);
 }
@@ -44,8 +41,7 @@ static inline void
 dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
                    dma_addr_t dma_handle)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        pci_free_consistent(to_pci_dev(dev), size, cpu_addr, dma_handle);
 }
@@ -54,8 +50,7 @@ static inline dma_addr_t
 dma_map_single(struct device *dev, void *cpu_addr, size_t size,
               enum dma_data_direction direction)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        return pci_map_single(to_pci_dev(dev), cpu_addr, size, (int)direction);
 }
@@ -64,8 +59,7 @@ static inline void
 dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
                 enum dma_data_direction direction)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        pci_unmap_single(to_pci_dev(dev), dma_addr, size, (int)direction);
 }
@@ -75,8 +69,7 @@ dma_map_page(struct device *dev, struct page *page,
             unsigned long offset, size_t size,
             enum dma_data_direction direction)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        return pci_map_page(to_pci_dev(dev), page, offset, size, (int)direction);
 }
@@ -85,8 +78,7 @@ static inline void
 dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
               enum dma_data_direction direction)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        pci_unmap_page(to_pci_dev(dev), dma_address, size, (int)direction);
 }
@@ -95,8 +87,7 @@ static inline int
 dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
           enum dma_data_direction direction)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        return pci_map_sg(to_pci_dev(dev), sg, nents, (int)direction);
 }
@@ -105,8 +96,7 @@ static inline void
 dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
             enum dma_data_direction direction)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        pci_unmap_sg(to_pci_dev(dev), sg, nhwentries, (int)direction);
 }
@@ -115,8 +105,7 @@ static inline void
 dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
                        enum dma_data_direction direction)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        pci_dma_sync_single_for_cpu(to_pci_dev(dev), dma_handle,
                                    size, (int)direction);
@@ -126,8 +115,7 @@ static inline void
 dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
                           enum dma_data_direction direction)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        pci_dma_sync_single_for_device(to_pci_dev(dev), dma_handle,
                                       size, (int)direction);
@@ -137,8 +125,7 @@ static inline void
 dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
                    enum dma_data_direction direction)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        pci_dma_sync_sg_for_cpu(to_pci_dev(dev), sg, nelems, (int)direction);
 }
@@ -147,8 +134,7 @@ static inline void
 dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
                       enum dma_data_direction direction)
 {
-        BUG_ON(dev->bus != &pci_bus_type &&
+        BUG_ON(dev->bus != &pci_bus_type);
-               dev->bus != &ebus_bus_type);
        pci_dma_sync_sg_for_device(to_pci_dev(dev), sg, nelems, (int)direction);
 }
diff --git a/include/asm-sparc64/hypervisor.h b/include/asm-sparc64/hypervisor.h
index 5c2f9d4b9f06..db2130a95d68 100644
--- a/include/asm-sparc64/hypervisor.h
+++ b/include/asm-sparc64/hypervisor.h
@@ -2615,8 +2615,9 @@ struct ldc_mtable_entry {
 /* ldc_revoke()
 * TRAP:        HV_FAST_TRAP
 * FUNCTION:    HV_FAST_LDC_REVOKE
- * ARG0:        cookie
+ * ARG0:        channel ID
- * ARG1:        ldc_mtable_entry cookie
+ * ARG1:        cookie
+ * ARG2:        ldc_mtable_entry cookie
 * RET0:        status
 */
 #define HV_FAST_LDC_REVOKE              0xef
@@ -2663,7 +2664,8 @@ extern unsigned long sun4v_ldc_mapin(unsigned long channel,
                                     unsigned long *ra,
                                     unsigned long *perm);
 extern unsigned long sun4v_ldc_unmap(unsigned long ra);
-extern unsigned long sun4v_ldc_revoke(unsigned long cookie,
+extern unsigned long sun4v_ldc_revoke(unsigned long channel,
+                                      unsigned long cookie,
                                      unsigned long mte_cookie);
 #endif
diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
index 5d233b42fe13..90781e34a95c 100644
--- a/include/asm-sparc64/irq.h
+++ b/include/asm-sparc64/irq.h
@@ -46,6 +46,7 @@ extern void irq_install_pre_handler(int virt_irq,
 #define irq_canonicalize(irq)   (irq)
 extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
 extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
+extern unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino);
 extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
                                    unsigned int msi_devino_start,
                                    unsigned int msi_devino_end);
diff --git a/include/asm-sparc64/mdesc.h b/include/asm-sparc64/mdesc.h
index 124eb8ca2378..c6383982b53d 100644
--- a/include/asm-sparc64/mdesc.h
+++ b/include/asm-sparc64/mdesc.h
@@ -15,6 +15,7 @@ struct mdesc_node {
        u64                     node;
        unsigned int            unique_id;
        unsigned int            num_arcs;
+        unsigned int            irqs[2];
        struct property         *properties;
        struct mdesc_node       *hash_next;
        struct mdesc_node       *allnodes_next;
diff --git a/include/asm-sparc64/parport.h b/include/asm-sparc64/parport.h
index 6340a5253a34..23cc63f049a8 100644
--- a/include/asm-sparc64/parport.h
+++ b/include/asm-sparc64/parport.h
@@ -145,7 +145,7 @@ static int parport_isa_probe(int count)
                         */
                        if (parport_pc_probe_port(base, base + 0x400,
                                                  child->irq, PARPORT_DMA_NOFIFO,
-                                                  child->bus->self))
+                                                  &child->bus->self->dev))
                                count++;
                }
        }
@@ -199,7 +199,8 @@ static int parport_pc_find_nonpci_ports (int autoirq, int autodma)
                                if (parport_pc_probe_port(base, base + 0x400,
                                                          edev->irqs[0],
-                                                          count, ebus->self))
+                                                          count,
+                                                          &ebus->self->dev))
                                        count++;
                        }
                }
diff --git a/include/asm-sparc64/tlb.h b/include/asm-sparc64/tlb.h
index 7af1e1109c49..349d1d3e9c27 100644
--- a/include/asm-sparc64/tlb.h
+++ b/include/asm-sparc64/tlb.h
@@ -2,6 +2,7 @@
 #define _SPARC64_TLB_H
 #include <linux/swap.h>
+#include <linux/pagemap.h>
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
 #include <asm/mmu_context.h>
diff --git a/include/asm-um/a.out.h b/include/asm-um/a.out.h
index 50cee7b296f4..7016b893ac9d 100644
--- a/include/asm-um/a.out.h
+++ b/include/asm-um/a.out.h
@@ -5,6 +5,7 @@
 #include "choose-mode.h"
 #undef STACK_TOP
+#undef STACK_TOP_MAX
 extern unsigned long stacksizelim;
diff --git a/include/asm-um/bug.h b/include/asm-um/bug.h
index 3357c5e2468e..9e33b864c359 100644
--- a/include/asm-um/bug.h
+++ b/include/asm-um/bug.h
@@ -1,6 +1,6 @@
 #ifndef __UM_BUG_H
 #define __UM_BUG_H
-#include <asm/arch/bug.h>
+#include <asm-generic/bug.h>
 #endif
diff --git a/include/asm-um/common.lds.S b/include/asm-um/common.lds.S
index f5de80c31e88..e3f010bd12b3 100644
--- a/include/asm-um/common.lds.S
+++ b/include/asm-um/common.lds.S
@@ -20,6 +20,8 @@
  __ex_table : { *(__ex_table) }
  __stop___ex_table = .;
+  BUG_TABLE
  __uml_setup_start = .;
  .uml.setup.init : { *(.uml.setup.init) }
  __uml_setup_end = .;
diff --git a/include/asm-um/paravirt.h b/include/asm-um/paravirt.h
new file mode 100644
index 000000000000..9d6aaad80b5f
--- /dev/null
+++ b/include/asm-um/paravirt.h
@@ -0,0 +1,6 @@
+#ifndef __UM_PARAVIRT_H
+#define __UM_PARAVIRT_H
+#include "asm/arch/paravirt.h"
+#endif
diff --git a/include/asm-v850/termbits.h b/include/asm-v850/termbits.h
index f3b433032089..35412f7f3eea 100644
--- a/include/asm-v850/termbits.h
+++ b/include/asm-v850/termbits.h
@@ -17,6 +17,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h
index 08b9831f2e14..0a71e0b9a619 100644
--- a/include/asm-x86_64/pgtable.h
+++ b/include/asm-x86_64/pgtable.h
@@ -395,12 +395,14 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 * bit at the same time. */
 #define  __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-        do {                                                              \
+({                                                                        \
-                if (__dirty) {                                            \
+        int __changed = !pte_same(*(__ptep), __entry);                    \
-                        set_pte(__ptep, __entry);                         \
+        if (__changed && __dirty) {                                       \
-                        flush_tlb_page(__vma, __address);                 \
+                set_pte(__ptep, __entry);                                 \
-                }                                                         \
+                flush_tlb_page(__vma, __address);                         \
-        } while (0)
+        }                                                                 \
+        __changed;                                                        \
+})
 /* Encode and de-code a swap entry */
 #define __swp_type(x)                   (((x).val >> 1) & 0x3f)
diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h
index ae1ed05f2814..8696f8ad401e 100644
--- a/include/asm-x86_64/unistd.h
+++ b/include/asm-x86_64/unistd.h
@@ -626,9 +626,9 @@ __SYSCALL(__NR_utimensat, sys_utimensat)
 __SYSCALL(__NR_epoll_pwait, sys_epoll_pwait)
 #define __NR_signalfd           282
 __SYSCALL(__NR_signalfd, sys_signalfd)
-#define __NR_timerfd            282
+#define __NR_timerfd            283
 __SYSCALL(__NR_timerfd, sys_timerfd)
-#define __NR_eventfd            283
+#define __NR_eventfd            284
 __SYSCALL(__NR_eventfd, sys_eventfd)
 #ifndef __NO_STUBS
diff --git a/include/asm-xtensa/termbits.h b/include/asm-xtensa/termbits.h
index 057b9a3d8f83..9972c25ec86f 100644
--- a/include/asm-xtensa/termbits.h
+++ b/include/asm-xtensa/termbits.h
@@ -30,6 +30,17 @@ struct termios {
        cc_t c_cc[NCCS];                /* control characters */
 };
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
 struct ktermios {
        tcflag_t c_iflag;               /* input mode flags */
        tcflag_t c_oflag;               /* output mode flags */
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index f317c270d4bf..afae306b177c 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -49,6 +49,7 @@ header-y += consolemap.h
 header-y += const.h
 header-y += cycx_cfm.h
 header-y += dlm_device.h
+header-y += dlm_netlink.h
 header-y += dm-ioctl.h
 header-y += dn.h
 header-y += dqblk_v1.h
diff --git a/include/linux/ata.h b/include/linux/ata.h
index 703febb2df31..407dc7e098bc 100644
--- a/include/linux/ata.h
+++ b/include/linux/ata.h
@@ -126,6 +126,7 @@ enum {
        ATA_REG_IRQ             = ATA_REG_NSECT,
        /* ATA device commands */
+        ATA_CMD_DEV_RESET       = 0x08, /* ATAPI device reset */
        ATA_CMD_CHK_POWER       = 0xE5, /* check power mode */
        ATA_CMD_STANDBY         = 0xE2, /* place in standby power mode */
        ATA_CMD_IDLE            = 0xE3, /* place in idle power mode */
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index db5b00a792f5..fae138bd2207 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -868,11 +868,6 @@ void kblockd_flush_work(struct work_struct *work);
 */
 #define buffer_heads_over_limit 0
-static inline long blk_congestion_wait(int rw, long timeout)
-{
-        return io_schedule_timeout(timeout);
-}
 static inline long nr_blockdev_pages(void)
 {
        return 0;
diff --git a/include/linux/dlm.h b/include/linux/dlm.h
index 1b1dcb9a40bb..be9d278761e0 100644
--- a/include/linux/dlm.h
+++ b/include/linux/dlm.h
@@ -2,7 +2,7 @@
 *******************************************************************************
 **
 **  Copyright (C) Sistina Software, Inc.  1997-2003  All rights reserved.
-**  Copyright (C) 2004-2005 Red Hat, Inc.  All rights reserved.
+**  Copyright (C) 2004-2007 Red Hat, Inc.  All rights reserved.
 **
 **  This copyrighted material is made available to anyone wishing to use,
 **  modify, copy, or redistribute it subject to the terms and conditions
@@ -85,7 +85,11 @@
 * Only relevant to locks originating in userspace.  A persistent lock will not
 * be removed if the process holding the lock exits.
 *
- * DLM_LKF_NODLKWT
+ * DLM_LKF_NODLCKWT
+ *
+ * Do not cancel the lock if it gets into conversion deadlock.
+ * Exclude this lock from being monitored due to DLM_LSFL_TIMEWARN.
+ *
 * DLM_LKF_NODLCKBLK
 *
 * net yet implemented
@@ -149,6 +153,7 @@
 #define DLM_LKF_ALTPR           0x00008000
 #define DLM_LKF_ALTCW           0x00010000
 #define DLM_LKF_FORCEUNLOCK     0x00020000
+#define DLM_LKF_TIMEOUT         0x00040000
 /*
 * Some return codes that are not in errno.h
@@ -199,11 +204,12 @@ struct dlm_lksb {
        char *   sb_lvbptr;
 };
+#define DLM_LSFL_NODIR          0x00000001
+#define DLM_LSFL_TIMEWARN       0x00000002
+#define DLM_LSFL_FS             0x00000004
 #ifdef __KERNEL__
-#define DLM_LSFL_NODIR          0x00000001
 /*
 * dlm_new_lockspace
 *
diff --git a/include/linux/dlm_device.h b/include/linux/dlm_device.h
index c2735cab2ebf..9642277a152a 100644
--- a/include/linux/dlm_device.h
+++ b/include/linux/dlm_device.h
@@ -2,7 +2,7 @@
 *******************************************************************************
 **
 **  Copyright (C) Sistina Software, Inc.  1997-2003  All rights reserved.
-**  Copyright (C) 2004-2005 Red Hat, Inc.  All rights reserved.
+**  Copyright (C) 2004-2007 Red Hat, Inc.  All rights reserved.
 **
 **  This copyrighted material is made available to anyone wishing to use,
 **  modify, copy, or redistribute it subject to the terms and conditions
@@ -18,21 +18,24 @@
 #define DLM_USER_LVB_LEN        32
 /* Version of the device interface */
-#define DLM_DEVICE_VERSION_MAJOR 5
+#define DLM_DEVICE_VERSION_MAJOR 6
-#define DLM_DEVICE_VERSION_MINOR 1
+#define DLM_DEVICE_VERSION_MINOR 0
 #define DLM_DEVICE_VERSION_PATCH 0
 /* struct passed to the lock write */
 struct dlm_lock_params {
        __u8 mode;
        __u8 namelen;
-        __u16 flags;
+        __u16 unused;
+        __u32 flags;
        __u32 lkid;
        __u32 parent;
-        void __user *castparam;
+        __u64 xid;
+        __u64 timeout;
+        void __user *castparam;
        void __user *castaddr;
        void __user *bastparam;
-        void __user *bastaddr;
+        void __user *bastaddr;
        struct dlm_lksb __user *lksb;
        char lvb[DLM_USER_LVB_LEN];
        char name[0];
@@ -62,9 +65,15 @@ struct dlm_write_request {
        } i;
 };
+struct dlm_device_version {
+        __u32 version[3];
+};
 /* struct read from the "device" fd,
   consists mainly of userspace pointers for the library to use */
 struct dlm_lock_result {
+        __u32 version[3];
        __u32 length;
        void __user * user_astaddr;
        void __user * user_astparam;
@@ -83,6 +92,7 @@ struct dlm_lock_result {
 #define DLM_USER_CREATE_LOCKSPACE  4
 #define DLM_USER_REMOVE_LOCKSPACE  5
 #define DLM_USER_PURGE        6
+#define DLM_USER_DEADLOCK     7
 /* Arbitrary length restriction */
 #define MAX_LS_NAME_LEN 64
diff --git a/include/linux/dlm_netlink.h b/include/linux/dlm_netlink.h
new file mode 100644
index 000000000000..19276332707a
--- /dev/null
+++ b/include/linux/dlm_netlink.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2007 Red Hat, Inc.  All rights reserved.
+ *
+ * This copyrighted material is made available to anyone wishing to use,
+ * modify, copy, or redistribute it subject to the terms and conditions
+ * of the GNU General Public License v.2.
+ */
+#ifndef _DLM_NETLINK_H
+#define _DLM_NETLINK_H
+enum {
+        DLM_STATUS_WAITING = 1,
+        DLM_STATUS_GRANTED = 2,
+        DLM_STATUS_CONVERT = 3,
+};
+#define DLM_LOCK_DATA_VERSION 1
+struct dlm_lock_data {
+        uint16_t version;
+        uint32_t lockspace_id;
+        int nodeid;
+        int ownpid;
+        uint32_t id;
+        uint32_t remid;
+        uint64_t xid;
+        int8_t status;
+        int8_t grmode;
+        int8_t rqmode;
+        unsigned long timestamp;
+        int resource_namelen;
+        char resource_name[DLM_RESNAME_MAXLEN];
+};
+enum {
+        DLM_CMD_UNSPEC = 0,
+        DLM_CMD_HELLO,          /* user->kernel */
+        DLM_CMD_TIMEOUT,        /* kernel->user */
+        __DLM_CMD_MAX,
+};
+#define DLM_CMD_MAX (__DLM_CMD_MAX - 1)
+enum {
+        DLM_TYPE_UNSPEC = 0,
+        DLM_TYPE_LOCK,
+        __DLM_TYPE_MAX,
+};
+#define DLM_TYPE_MAX (__DLM_TYPE_MAX - 1)
+#define DLM_GENL_VERSION 0x1
+#define DLM_GENL_NAME "DLM"
+#endif /* _DLM_NETLINK_H */
diff --git a/include/linux/eeprom_93cx6.h b/include/linux/eeprom_93cx6.h
new file mode 100644
index 000000000000..d774b7778c91
--- /dev/null
+++ b/include/linux/eeprom_93cx6.h
@@ -0,0 +1,72 @@
+/*
+        Copyright (C) 2004 - 2006 rt2x00 SourceForge Project
+        <http://rt2x00.serialmonkey.com>
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+        GNU General Public License for more details.
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the
+        Free Software Foundation, Inc.,
+        59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+/*
+        Module: eeprom_93cx6
+        Abstract: EEPROM reader datastructures for 93cx6 chipsets.
+        Supported chipsets: 93c46 & 93c66.
+ */
+/*
+ * EEPROM operation defines.
+ */
+#define PCI_EEPROM_WIDTH_93C46  6
+#define PCI_EEPROM_WIDTH_93C66  8
+#define PCI_EEPROM_WIDTH_OPCODE 3
+#define PCI_EEPROM_WRITE_OPCODE 0x05
+#define PCI_EEPROM_READ_OPCODE  0x06
+#define PCI_EEPROM_EWDS_OPCODE  0x10
+#define PCI_EEPROM_EWEN_OPCODE  0x13
+/**
+ * struct eeprom_93cx6 - control structure for setting the commands
+ * for reading the eeprom data.
+ * @data: private pointer for the driver.
+ * @register_read(struct eeprom_93cx6 *eeprom): handler to
+ * read the eeprom register, this function should set all reg_* fields.
+ * @register_write(struct eeprom_93cx6 *eeprom): handler to
+ * write to the eeprom register by using all reg_* fields.
+ * @width: eeprom width, should be one of the PCI_EEPROM_WIDTH_* defines
+ * @reg_data_in: register field to indicate data input
+ * @reg_data_out: register field to indicate data output
+ * @reg_data_clock: register field to set the data clock
+ * @reg_chip_select: register field to set the chip select
+ *
+ * This structure is used for the communication between the driver
+ * and the eeprom_93cx6 handlers for reading the eeprom.
+ */
+struct eeprom_93cx6 {
+        void *data;
+        void (*register_read)(struct eeprom_93cx6 *eeprom);
+        void (*register_write)(struct eeprom_93cx6 *eeprom);
+        int width;
+        char reg_data_in;
+        char reg_data_out;
+        char reg_data_clock;
+        char reg_chip_select;
+};
+extern void eeprom_93cx6_read(struct eeprom_93cx6 *eeprom,
+        const u8 word, u16 *data);
+extern void eeprom_93cx6_multiread(struct eeprom_93cx6 *eeprom,
+        const u8 word, __le16 *data, const u16 words);
diff --git a/include/linux/eventfd.h b/include/linux/eventfd.h
index 0d6ecc60b94d..b489fc6d0b62 100644
--- a/include/linux/eventfd.h
+++ b/include/linux/eventfd.h
@@ -19,7 +19,8 @@ int eventfd_signal(struct file *file, int n);
 #else /* CONFIG_EVENTFD */
 #define eventfd_fget(fd) ERR_PTR(-ENOSYS)
-#define eventfd_signal(f, n) 0
+static inline int eventfd_signal(struct file *file, int n)
+{ return 0; }
 #endif /* CONFIG_EVENTFD */
diff --git a/include/linux/firewire-cdev.h b/include/linux/firewire-cdev.h
index efbe1fda1a22..1a45d6f41b09 100644
--- a/include/linux/firewire-cdev.h
+++ b/include/linux/firewire-cdev.h
@@ -30,16 +30,38 @@
 #define FW_CDEV_EVENT_REQUEST           0x02
 #define FW_CDEV_EVENT_ISO_INTERRUPT     0x03
-/* The 'closure' fields are for user space to use.  Data passed in the
+/**
- * 'closure' field for a request will be returned in the corresponding
+ * struct fw_cdev_event_common - Common part of all fw_cdev_event_ types
- * event.  It's a 64-bit type so that it's a fixed size type big
+ * @closure:    For arbitrary use by userspace
- * enough to hold a pointer on all platforms. */
+ * @type:       Discriminates the fw_cdev_event_ types
+ *
+ * This struct may be used to access generic members of all fw_cdev_event_
+ * types regardless of the specific type.
+ *
+ * Data passed in the @closure field for a request will be returned in the
+ * corresponding event.  It is big enough to hold a pointer on all platforms.
+ * The ioctl used to set @closure depends on the @type of event.
+ */
 struct fw_cdev_event_common {
        __u64 closure;
        __u32 type;
 };
+/**
+ * struct fw_cdev_event_bus_reset - Sent when a bus reset occurred
+ * @closure:    See &fw_cdev_event_common; set by %FW_CDEV_IOC_GET_INFO ioctl
+ * @type:       See &fw_cdev_event_common; always %FW_CDEV_EVENT_BUS_RESET
+ * @node_id:       New node ID of this node
+ * @local_node_id: Node ID of the local node, i.e. of the controller
+ * @bm_node_id:    Node ID of the bus manager
+ * @irm_node_id:   Node ID of the iso resource manager
+ * @root_node_id:  Node ID of the root node
+ * @generation:    New bus generation
+ *
+ * This event is sent when the bus the device belongs to goes through a bus
+ * reset.  It provides information about the new bus configuration, such as
+ * new node ID for this device, new root ID, and others.
+ */
 struct fw_cdev_event_bus_reset {
        __u64 closure;
        __u32 type;
@@ -51,6 +73,20 @@ struct fw_cdev_event_bus_reset {
        __u32 generation;
 };
+/**
+ * struct fw_cdev_event_response - Sent when a response packet was received
+ * @closure:    See &fw_cdev_event_common;
+ *              set by %FW_CDEV_IOC_SEND_REQUEST ioctl
+ * @type:       See &fw_cdev_event_common; always %FW_CDEV_EVENT_RESPONSE
+ * @rcode:      Response code returned by the remote node
+ * @length:     Data length, i.e. the response's payload size in bytes
+ * @data:       Payload data, if any
+ *
+ * This event is sent when the stack receives a response to an outgoing request
+ * sent by %FW_CDEV_IOC_SEND_REQUEST ioctl.  The payload data for responses
+ * carrying data (read and lock responses) follows immediately and can be
+ * accessed through the @data field.
+ */
 struct fw_cdev_event_response {
        __u64 closure;
        __u32 type;
@@ -59,6 +95,25 @@ struct fw_cdev_event_response {
        __u32 data[0];
 };
+/**
+ * struct fw_cdev_event_request - Sent on incoming request to an address region
+ * @closure:    See &fw_cdev_event_common; set by %FW_CDEV_IOC_ALLOCATE ioctl
+ * @type:       See &fw_cdev_event_common; always %FW_CDEV_EVENT_REQUEST
+ * @tcode:      Transaction code of the incoming request
+ * @offset:     The offset into the 48-bit per-node address space
+ * @handle:     Reference to the kernel-side pending request
+ * @length:     Data length, i.e. the request's payload size in bytes
+ * @data:       Incoming data, if any
+ *
+ * This event is sent when the stack receives an incoming request to an address
+ * region registered using the %FW_CDEV_IOC_ALLOCATE ioctl.  The request is
+ * guaranteed to be completely contained in the specified region.  Userspace is
+ * responsible for sending the response by %FW_CDEV_IOC_SEND_RESPONSE ioctl,
+ * using the same @handle.
+ *
+ * The payload data for requests carrying data (write and lock requests)
+ * follows immediately and can be accessed through the @data field.
+ */
 struct fw_cdev_event_request {
        __u64 closure;
        __u32 type;
@@ -69,14 +124,39 @@ struct fw_cdev_event_request {
        __u32 data[0];
 };
+/**
+ * struct fw_cdev_event_iso_interrupt - Sent when an iso packet was completed
+ * @closure:    See &fw_cdev_event_common;
+ *              set by %FW_CDEV_CREATE_ISO_CONTEXT ioctl
+ * @type:       See &fw_cdev_event_common; always %FW_CDEV_EVENT_ISO_INTERRUPT
+ * @cycle:      Cycle counter of the interrupt packet
+ * @header_length: Total length of following headers, in bytes
+ * @header:     Stripped headers, if any
+ *
+ * This event is sent when the controller has completed an &fw_cdev_iso_packet
+ * with the %FW_CDEV_ISO_INTERRUPT bit set.  In the receive case, the headers
+ * stripped of all packets up until and including the interrupt packet are
+ * returned in the @header field.
+ */
 struct fw_cdev_event_iso_interrupt {
        __u64 closure;
        __u32 type;
        __u32 cycle;
-        __u32 header_length;    /* Length in bytes of following headers. */
+        __u32 header_length;
        __u32 header[0];
 };
+/**
+ * union fw_cdev_event - Convenience union of fw_cdev_event_ types
+ * @common:        Valid for all types
+ * @bus_reset:     Valid if @common.type == %FW_CDEV_EVENT_BUS_RESET
+ * @response:      Valid if @common.type == %FW_CDEV_EVENT_RESPONSE
+ * @request:       Valid if @common.type == %FW_CDEV_EVENT_REQUEST
+ * @iso_interrupt: Valid if @common.type == %FW_CDEV_EVENT_ISO_INTERRUPT
+ *
+ * Convenience union for userspace use.  Events could be read(2) into a char
+ * buffer and then cast to this union for further processing.
+ */
 union fw_cdev_event {
        struct fw_cdev_event_common common;
        struct fw_cdev_event_bus_reset bus_reset;
@@ -105,35 +185,47 @@ union fw_cdev_event {
 */
 #define FW_CDEV_VERSION         1
+/**
+ * struct fw_cdev_get_info - General purpose information ioctl
+ * @version:    The version field is just a running serial number.
+ *              We never break backwards compatibility, but may add more
+ *              structs and ioctls in later revisions.
+ * @rom_length: If @rom is non-zero, at most rom_length bytes of configuration
+ *              ROM will be copied into that user space address.  In either
+ *              case, @rom_length is updated with the actual length of the
+ *              configuration ROM.
+ * @rom:        If non-zero, address of a buffer to be filled by a copy of the
+ *              local node's configuration ROM
+ * @bus_reset:  If non-zero, address of a buffer to be filled by a
+ *              &struct fw_cdev_event_bus_reset with the current state
+ *              of the bus.  This does not cause a bus reset to happen.
+ * @bus_reset_closure: Value of &closure in this and subsequent bus reset events
+ * @card:       The index of the card this device belongs to
+ */
 struct fw_cdev_get_info {
-        /* The version field is just a running serial number.  We
-         * never break backwards compatibility.  Userspace passes in
-         * the version it expects and the kernel passes back the
-         * highest version it can provide.  Even if the structs in
-         * this interface are extended in a later version, the kernel
-         * will not copy back more data than what was present in the
-         * interface version userspace expects. */
        __u32 version;
-        /* If non-zero, at most rom_length bytes of config rom will be
-         * copied into that user space address.  In either case,
-         * rom_length is updated with the actual length of the config
-         * rom. */
        __u32 rom_length;
        __u64 rom;
-        /* If non-zero, a fw_cdev_event_bus_reset struct will be
-         * copied here with the current state of the bus.  This does
-         * not cause a bus reset to happen.  The value of closure in
-         * this and sub-sequent bus reset events is set to
-         * bus_reset_closure. */
        __u64 bus_reset;
        __u64 bus_reset_closure;
-        /* The index of the card this devices belongs to. */
        __u32 card;
 };
+/**
+ * struct fw_cdev_send_request - Send an asynchronous request packet
+ * @tcode:      Transaction code of the request
+ * @length:     Length of outgoing payload, in bytes
+ * @offset:     48-bit offset at destination node
+ * @closure:    Passed back to userspace in the response event
+ * @data:       Userspace pointer to payload
+ * @generation: The bus generation where packet is valid
+ *
+ * Send a request to the device.  This ioctl implements all outgoing requests.
+ * Both quadlet and block request specify the payload as a pointer to the data
+ * in the @data field.  Once the transaction completes, the kernel writes an
+ * &fw_cdev_event_request event back.  The @closure field is passed back to
+ * user space in the response event.
+ */
 struct fw_cdev_send_request {
        __u32 tcode;
        __u32 length;
@@ -143,6 +235,19 @@ struct fw_cdev_send_request {
        __u32 generation;
 };
+/**
+ * struct fw_cdev_send_response - Send an asynchronous response packet
+ * @rcode:      Response code as determined by the userspace handler
+ * @length:     Length of outgoing payload, in bytes
+ * @data:       Userspace pointer to payload
+ * @handle:     The handle from the &fw_cdev_event_request
+ *
+ * Send a response to an incoming request.  By setting up an address range using
+ * the %FW_CDEV_IOC_ALLOCATE ioctl, userspace can listen for incoming requests.  An
+ * incoming request will generate an %FW_CDEV_EVENT_REQUEST, and userspace must
+ * send a reply using this ioctl.  The event has a handle to the kernel-side
+ * pending transaction, which should be used with this ioctl.
+ */
 struct fw_cdev_send_response {
        __u32 rcode;
        __u32 length;
@@ -150,6 +255,21 @@ struct fw_cdev_send_response {
        __u32 handle;
 };
+/**
+ * struct fw_cdev_allocate - Allocate a CSR address range
+ * @offset:     Start offset of the address range
+ * @closure:    To be passed back to userspace in request events
+ * @length:     Length of the address range, in bytes
+ * @handle:     Handle to the allocation, written by the kernel
+ *
+ * Allocate an address range in the 48-bit address space on the local node
+ * (the controller).  This allows userspace to listen for requests with an
+ * offset within that address range.  When the kernel receives a request
+ * within the range, an &fw_cdev_event_request event will be written back.
+ * The @closure field is passed back to userspace in the response event.
+ * The @handle field is an out parameter, returning a handle to the allocated
+ * range to be used for later deallocation of the range.
+ */
 struct fw_cdev_allocate {
        __u64 offset;
        __u64 closure;
@@ -157,6 +277,11 @@ struct fw_cdev_allocate {
        __u32 handle;
 };
+/**
+ * struct fw_cdev_deallocate - Free an address range allocation
+ * @handle:     Handle to the address range, as returned by the kernel when the
+ *              range was allocated
+ */
 struct fw_cdev_deallocate {
        __u32 handle;
 };
@@ -164,10 +289,41 @@ struct fw_cdev_deallocate {
 #define FW_CDEV_LONG_RESET      0
 #define FW_CDEV_SHORT_RESET     1
+/**
+ * struct fw_cdev_initiate_bus_reset - Initiate a bus reset
+ * @type:       %FW_CDEV_SHORT_RESET or %FW_CDEV_LONG_RESET
+ *
+ * Initiate a bus reset for the bus this device is on.  The bus reset can be
+ * either the original (long) bus reset or the arbitrated (short) bus reset
+ * introduced in 1394a-2000.
+ */
 struct fw_cdev_initiate_bus_reset {
-        __u32 type;
+        __u32 type;     /* FW_CDEV_SHORT_RESET or FW_CDEV_LONG_RESET */
 };
+/**
+ * struct fw_cdev_add_descriptor - Add contents to the local node's config ROM
+ * @immediate:  If non-zero, immediate key to insert before pointer
+ * @key:        Upper 8 bits of root directory pointer
+ * @data:       Userspace pointer to contents of descriptor block
+ * @length:     Length of descriptor block data, in bytes
+ * @handle:     Handle to the descriptor, written by the kernel
+ *
+ * Add a descriptor block and optionally a preceding immediate key to the local
+ * node's configuration ROM.
+ *
+ * The @key field specifies the upper 8 bits of the descriptor root directory
+ * pointer and the @data and @length fields specify the contents. The @key
+ * should be of the form 0xXX000000. The offset part of the root directory entry
+ * will be filled in by the kernel.
+ *
+ * If not 0, the @immediate field specifies an immediate key which will be
+ * inserted before the root directory pointer.
+ *
+ * If successful, the kernel adds the descriptor and writes back a handle to the
+ * kernel-side object to be used for later removal of the descriptor block and
+ * immediate key.
+ */
 struct fw_cdev_add_descriptor {
        __u32 immediate;
        __u32 key;
@@ -176,6 +332,14 @@ struct fw_cdev_add_descriptor {
        __u32 handle;
 };
+/**
+ * struct fw_cdev_remove_descriptor - Remove contents from the configuration ROM
+ * @handle:     Handle to the descriptor, as returned by the kernel when the
+ *              descriptor was added
+ *
+ * Remove a descriptor block and accompanying immediate key from the local
+ * node's configuration ROM.
+ */
 struct fw_cdev_remove_descriptor {
        __u32 handle;
 };
@@ -183,12 +347,24 @@ struct fw_cdev_remove_descriptor {
 #define FW_CDEV_ISO_CONTEXT_TRANSMIT    0
 #define FW_CDEV_ISO_CONTEXT_RECEIVE     1
-#define FW_CDEV_ISO_CONTEXT_MATCH_TAG0           1
+/**
-#define FW_CDEV_ISO_CONTEXT_MATCH_TAG1           2
+ * struct fw_cdev_create_iso_context - Create a context for isochronous IO
-#define FW_CDEV_ISO_CONTEXT_MATCH_TAG2           4
+ * @type:       %FW_CDEV_ISO_CONTEXT_TRANSMIT or %FW_CDEV_ISO_CONTEXT_RECEIVE
-#define FW_CDEV_ISO_CONTEXT_MATCH_TAG3           8
+ * @header_size: Header size to strip for receive contexts
-#define FW_CDEV_ISO_CONTEXT_MATCH_ALL_TAGS      15
+ * @channel:    Channel to bind to
+ * @speed:      Speed to transmit at
+ * @closure:    To be returned in &fw_cdev_event_iso_interrupt
+ * @handle:     Handle to context, written back by kernel
+ *
+ * Prior to sending or receiving isochronous I/O, a context must be created.
+ * The context records information about the transmit or receive configuration
+ * and typically maps to an underlying hardware resource.  A context is set up
+ * for either sending or receiving.  It is bound to a specific isochronous
+ * channel.
+ *
+ * If a context was successfully created, the kernel writes back a handle to the
+ * context, which must be passed in for subsequent operations on that context.
+ */
 struct fw_cdev_create_iso_context {
        __u32 type;
        __u32 header_size;
@@ -201,15 +377,49 @@ struct fw_cdev_create_iso_context {
 #define FW_CDEV_ISO_PAYLOAD_LENGTH(v)   (v)
 #define FW_CDEV_ISO_INTERRUPT           (1 << 16)
 #define FW_CDEV_ISO_SKIP                (1 << 17)
+#define FW_CDEV_ISO_SYNC                (1 << 17)
 #define FW_CDEV_ISO_TAG(v)              ((v) << 18)
 #define FW_CDEV_ISO_SY(v)               ((v) << 20)
 #define FW_CDEV_ISO_HEADER_LENGTH(v)    ((v) << 24)
+/**
+ * struct fw_cdev_iso_packet - Isochronous packet
+ * @control:    Contains the header length (8 uppermost bits), the sy field
+ *              (4 bits), the tag field (2 bits), a sync flag (1 bit),
+ *              a skip flag (1 bit), an interrupt flag (1 bit), and the
+ *              payload length (16 lowermost bits)
+ * @header:     Header and payload
+ *
+ * &struct fw_cdev_iso_packet is used to describe isochronous packet queues.
+ *
+ * Use the FW_CDEV_ISO_ macros to fill in @control.  The sy and tag fields are
+ * specified by IEEE 1394a and IEC 61883.
+ *
+ * FIXME - finish this documentation
+ */
 struct fw_cdev_iso_packet {
        __u32 control;
        __u32 header[0];
 };
+/**
+ * struct fw_cdev_queue_iso - Queue isochronous packets for I/O
+ * @packets:    Userspace pointer to packet data
+ * @data:       Pointer into mmap()'ed payload buffer
+ * @size:       Size of packet data in bytes
+ * @handle:     Isochronous context handle
+ *
+ * Queue a number of isochronous packets for reception or transmission.
+ * This ioctl takes a pointer to an array of &fw_cdev_iso_packet structs,
+ * which describe how to transmit from or receive into a contiguous region
+ * of a mmap()'ed payload buffer.  As part of the packet descriptors,
+ * a series of headers can be supplied, which will be prepended to the
+ * payload during DMA.
+ *
+ * The kernel may or may not queue all packets, but will write back updated
+ * values of the @packets, @data and @size fields, so the ioctl can be
+ * resubmitted easily.
+ */
 struct fw_cdev_queue_iso {
        __u64 packets;
        __u64 data;
@@ -217,6 +427,23 @@ struct fw_cdev_queue_iso {
        __u32 handle;
 };
+#define FW_CDEV_ISO_CONTEXT_MATCH_TAG0           1
+#define FW_CDEV_ISO_CONTEXT_MATCH_TAG1           2
+#define FW_CDEV_ISO_CONTEXT_MATCH_TAG2           4
+#define FW_CDEV_ISO_CONTEXT_MATCH_TAG3           8
+#define FW_CDEV_ISO_CONTEXT_MATCH_ALL_TAGS      15
+/**
+ * struct fw_cdev_start_iso - Start an isochronous transmission or reception
+ * @cycle:      Cycle in which to start I/O.  If @cycle is greater than or
+ *              equal to 0, the I/O will start on that cycle.
+ * @sync:       Determines the value to wait for for receive packets that have
+ *              the %FW_CDEV_ISO_SYNC bit set
+ * @tags:       Tag filter bit mask.  Only valid for isochronous reception.
+ *              Determines the tag values for which packets will be accepted.
+ *              Use FW_CDEV_ISO_CONTEXT_MATCH_ macros to set @tags.
+ * @handle:     Isochronous context handle within which to transmit or receive
+ */
 struct fw_cdev_start_iso {
        __s32 cycle;
        __u32 sync;
@@ -224,6 +451,10 @@ struct fw_cdev_start_iso {
        __u32 handle;
 };
+/**
+ * struct fw_cdev_stop_iso - Stop an isochronous transmission or reception
+ * @handle:     Handle of isochronous context to stop
+ */
 struct fw_cdev_stop_iso {
        __u32 handle;
 };
diff --git a/include/linux/fs.h b/include/linux/fs.h
index b3ae77cccbb6..4f0b3bf5983c 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -1054,7 +1054,7 @@ struct block_device_operations {
 };
 /*
- * "descriptor" for what we're up to with a read for sendfile().
+ * "descriptor" for what we're up to with a read.
 * This allows us to use the same read code yet
 * have multiple different users of the data that
 * we read from a file.
@@ -1105,7 +1105,6 @@ struct file_operations {
        int (*aio_fsync) (struct kiocb *, int datasync);
        int (*fasync) (int, struct file *, int);
        int (*lock) (struct file *, int, struct file_lock *);
-        ssize_t (*sendfile) (struct file *, loff_t *, size_t, read_actor_t, void *);
        ssize_t (*sendpage) (struct file *, struct page *, int, size_t, loff_t *, int);
        unsigned long (*get_unmapped_area)(struct file *, unsigned long, unsigned long, unsigned long, unsigned long);
        int (*check_flags)(int);
@@ -1211,6 +1210,14 @@ static inline void mark_inode_dirty_sync(struct inode *inode)
        __mark_inode_dirty(inode, I_DIRTY_SYNC);
 }
+/**
+ * inc_nlink - directly increment an inode's link count
+ * @inode: inode
+ *
+ * This is a low-level filesystem helper to replace any
+ * direct filesystem manipulation of i_nlink.  Currently,
+ * it is only here for parity with dec_nlink().
+ */
 static inline void inc_nlink(struct inode *inode)
 {
        inode->i_nlink++;
@@ -1222,11 +1229,30 @@ static inline void inode_inc_link_count(struct inode *inode)
        mark_inode_dirty(inode);
 }
+/**
+ * drop_nlink - directly drop an inode's link count
+ * @inode: inode
+ *
+ * This is a low-level filesystem helper to replace any
+ * direct filesystem manipulation of i_nlink.  In cases
+ * where we are attempting to track writes to the
+ * filesystem, a decrement to zero means an imminent
+ * write when the file is truncated and actually unlinked
+ * on the filesystem.
+ */
 static inline void drop_nlink(struct inode *inode)
 {
        inode->i_nlink--;
 }
+/**
+ * clear_nlink - directly zero an inode's link count
+ * @inode: inode
+ *
+ * This is a low-level filesystem helper to replace any
+ * direct filesystem manipulation of i_nlink.  See
+ * drop_nlink() for why we care about i_nlink hitting zero.
+ */
 static inline void clear_nlink(struct inode *inode)
 {
        inode->i_nlink = 0;
@@ -1735,7 +1761,6 @@ extern ssize_t generic_file_buffered_write(struct kiocb *, const struct iovec *,
                unsigned long, loff_t, loff_t *, size_t, ssize_t);
 extern ssize_t do_sync_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos);
 extern ssize_t do_sync_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos);
-extern ssize_t generic_file_sendfile(struct file *, loff_t *, size_t, read_actor_t, void *);
 extern void do_generic_mapping_read(struct address_space *mapping,
                                    struct file_ra_state *, struct file *,
                                    loff_t *, read_descriptor_t *, read_actor_t);
@@ -1765,9 +1790,6 @@ extern int nonseekable_open(struct inode * inode, struct file * filp);
 #ifdef CONFIG_FS_XIP
 extern ssize_t xip_file_read(struct file *filp, char __user *buf, size_t len,
                             loff_t *ppos);
-extern ssize_t xip_file_sendfile(struct file *in_file, loff_t *ppos,
-                                 size_t count, read_actor_t actor,
-                                 void *target);
 extern int xip_file_mmap(struct file * file, struct vm_area_struct * vma);
 extern ssize_t xip_file_write(struct file *filp, const char __user *buf,
                              size_t len, loff_t *ppos);
diff --git a/include/linux/futex.h b/include/linux/futex.h
index 899fc7f20edd..99650353adfa 100644
--- a/include/linux/futex.h
+++ b/include/linux/futex.h
@@ -17,7 +17,6 @@ union ktime;
 #define FUTEX_LOCK_PI           6
 #define FUTEX_UNLOCK_PI         7
 #define FUTEX_TRYLOCK_PI        8
-#define FUTEX_CMP_REQUEUE_PI    9
 #define FUTEX_PRIVATE_FLAG      128
 #define FUTEX_CMD_MASK          ~FUTEX_PRIVATE_FLAG
@@ -98,14 +97,9 @@ struct robust_list_head {
 #define FUTEX_OWNER_DIED        0x40000000
 /*
- * Some processes have been requeued on this PI-futex
- */
-#define FUTEX_WAITER_REQUEUED   0x20000000
-/*
 * The rest of the robust-futex field is for the TID:
 */
-#define FUTEX_TID_MASK          0x0fffffff
+#define FUTEX_TID_MASK          0x3fffffff
 /*
 * This limit protects against a deliberately circular list.
@@ -139,7 +133,6 @@ handle_futex_death(u32 __user *uaddr, struct task_struct *curr, int pi);
 #define FUT_OFF_MMSHARED 2 /* We set bit 1 if key has a reference on mm */
 union futex_key {
-        u32 __user *uaddr;
        struct {
                unsigned long pgoff;
                struct inode *inode;
diff --git a/include/linux/gfs2_ondisk.h b/include/linux/gfs2_ondisk.h
index 8b7e4c1e32ae..a44a6a078f0a 100644
--- a/include/linux/gfs2_ondisk.h
+++ b/include/linux/gfs2_ondisk.h
@@ -54,18 +54,6 @@ struct gfs2_inum {
        __be64 no_addr;
 };
-struct gfs2_inum_host {
-        __u64 no_formal_ino;
-        __u64 no_addr;
-};
-static inline int gfs2_inum_equal(const struct gfs2_inum_host *ino1,
-                                  const struct gfs2_inum_host *ino2)
-{
-        return ino1->no_formal_ino == ino2->no_formal_ino &&
-               ino1->no_addr == ino2->no_addr;
-}
 /*
 * Generic metadata head structure
 * Every inplace buffer logged in the journal must start with this.
@@ -94,12 +82,6 @@ struct gfs2_meta_header {
        __be32 __pad1;          /* Was incarnation number in gfs1 */
 };
-struct gfs2_meta_header_host {
-        __u32 mh_magic;
-        __u32 mh_type;
-        __u32 mh_format;
-};
 /*
 * super-block structure
 *
@@ -139,23 +121,6 @@ struct gfs2_sb {
        /* In gfs1, quota and license dinodes followed */
 };
-struct gfs2_sb_host {
-        struct gfs2_meta_header_host sb_header;
-        __u32 sb_fs_format;
-        __u32 sb_multihost_format;
-        __u32 sb_bsize;
-        __u32 sb_bsize_shift;
-        struct gfs2_inum_host sb_master_dir; /* Was jindex dinode in gfs1 */
-        struct gfs2_inum_host sb_root_dir;
-        char sb_lockproto[GFS2_LOCKNAME_LEN];
-        char sb_locktable[GFS2_LOCKNAME_LEN];
-        /* In gfs1, quota and license dinodes followed */
-};
 /*
 * resource index structure
 */
@@ -173,14 +138,6 @@ struct gfs2_rindex {
        __u8 ri_reserved[64];
 };
-struct gfs2_rindex_host {
-        __u64 ri_addr;  /* grp block disk address */
-        __u64 ri_data0; /* first data location */
-        __u32 ri_length;        /* length of rgrp header in fs blocks */
-        __u32 ri_data;  /* num of data blocks in rgrp */
-        __u32 ri_bitbytes;      /* number of bytes in data bitmaps */
-};
 /*
 * resource group header structure
 */
@@ -212,13 +169,6 @@ struct gfs2_rgrp {
        __u8 rg_reserved[80]; /* Several fields from gfs1 now reserved */
 };
-struct gfs2_rgrp_host {
-        __u32 rg_flags;
-        __u32 rg_free;
-        __u32 rg_dinodes;
-        __u64 rg_igeneration;
-};
 /*
 * quota structure
 */
@@ -230,12 +180,6 @@ struct gfs2_quota {
        __u8 qu_reserved[64];
 };
-struct gfs2_quota_host {
-        __u64 qu_limit;
-        __u64 qu_warn;
-        __u64 qu_value;
-};
 /*
 * dinode structure
 */
@@ -315,29 +259,11 @@ struct gfs2_dinode {
        struct gfs2_inum __pad4; /* Unused even in current gfs1 */
        __be64 di_eattr;        /* extended attribute block number */
+        __be32 di_atime_nsec;   /* nsec portion of atime */
+        __be32 di_mtime_nsec;   /* nsec portion of mtime */
+        __be32 di_ctime_nsec;   /* nsec portion of ctime */
-        __u8 di_reserved[56];
+        __u8 di_reserved[44];
-};
-struct gfs2_dinode_host {
-        __u64 di_size;  /* number of bytes in file */
-        __u64 di_blocks;        /* number of blocks in file */
-        /* This section varies from gfs1. Padding added to align with
-         * remainder of dinode
-         */
-        __u64 di_goal_meta;     /* rgrp to alloc from next */
-        __u64 di_goal_data;     /* data block goal */
-        __u64 di_generation;    /* generation number for NFS */
-        __u32 di_flags; /* GFS2_DIF_... */
-        __u16 di_height;        /* height of metadata */
-        /* These only apply to directories  */
-        __u16 di_depth; /* Number of bits in the table */
-        __u32 di_entries;       /* The number of entries in the directory */
-        __u64 di_eattr; /* extended attribute block number */
 };
 /*
@@ -414,16 +340,6 @@ struct gfs2_log_header {
        __be32 lh_hash;
 };
-struct gfs2_log_header_host {
-        struct gfs2_meta_header_host lh_header;
-        __u64 lh_sequence;      /* Sequence number of this transaction */
-        __u32 lh_flags; /* GFS2_LOG_HEAD_... */
-        __u32 lh_tail;          /* Block number of log tail */
-        __u32 lh_blkno;
-        __u32 lh_hash;
-};
 /*
 * Log type descriptor
 */
@@ -464,11 +380,6 @@ struct gfs2_inum_range {
        __be64 ir_length;
 };
-struct gfs2_inum_range_host {
-        __u64 ir_start;
-        __u64 ir_length;
-};
 /*
 * Statfs change
 * Describes an change to the pool of free and allocated
@@ -481,12 +392,6 @@ struct gfs2_statfs_change {
        __be64 sc_dinodes;
 };
-struct gfs2_statfs_change_host {
-        __u64 sc_total;
-        __u64 sc_free;
-        __u64 sc_dinodes;
-};
 /*
 * Quota change
 * Describes an allocation change for a particular
@@ -501,39 +406,12 @@ struct gfs2_quota_change {
        __be32 qc_id;
 };
-struct gfs2_quota_change_host {
+struct gfs2_quota_lvb {
-        __u64 qc_change;
+        __be32 qb_magic;
-        __u32 qc_flags; /* GFS2_QCF_... */
+        __u32 __pad;
-        __u32 qc_id;
+        __be64 qb_limit;      /* Hard limit of # blocks to alloc */
+        __be64 qb_warn;       /* Warn user when alloc is above this # */
+        __be64 qb_value;       /* Current # blocks allocated */
 };
-#ifdef __KERNEL__
-/* Translation functions */
-extern void gfs2_inum_in(struct gfs2_inum_host *no, const void *buf);
-extern void gfs2_inum_out(const struct gfs2_inum_host *no, void *buf);
-extern void gfs2_sb_in(struct gfs2_sb_host *sb, const void *buf);
-extern void gfs2_rindex_in(struct gfs2_rindex_host *ri, const void *buf);
-extern void gfs2_rindex_out(const struct gfs2_rindex_host *ri, void *buf);
-extern void gfs2_rgrp_in(struct gfs2_rgrp_host *rg, const void *buf);
-extern void gfs2_rgrp_out(const struct gfs2_rgrp_host *rg, void *buf);
-extern void gfs2_quota_in(struct gfs2_quota_host *qu, const void *buf);
-struct gfs2_inode;
-extern void gfs2_dinode_out(const struct gfs2_inode *ip, void *buf);
-extern void gfs2_ea_header_in(struct gfs2_ea_header *ea, const void *buf);
-extern void gfs2_ea_header_out(const struct gfs2_ea_header *ea, void *buf);
-extern void gfs2_log_header_in(struct gfs2_log_header_host *lh, const void *buf);
-extern void gfs2_inum_range_in(struct gfs2_inum_range_host *ir, const void *buf);
-extern void gfs2_inum_range_out(const struct gfs2_inum_range_host *ir, void *buf);
-extern void gfs2_statfs_change_in(struct gfs2_statfs_change_host *sc, const void *buf);
-extern void gfs2_statfs_change_out(const struct gfs2_statfs_change_host *sc, void *buf);
-extern void gfs2_quota_change_in(struct gfs2_quota_change_host *qc, const void *buf);
-/* Printing functions */
-extern void gfs2_rindex_print(const struct gfs2_rindex_host *ri);
-extern void gfs2_dinode_print(const struct gfs2_inode *ip);
-#endif /* __KERNEL__ */
 #endif /* __GFS2_ONDISK_DOT_H__ */
diff --git a/include/linux/gpio_mouse.h b/include/linux/gpio_mouse.h
new file mode 100644
index 000000000000..44ed7aa14d85
--- /dev/null
+++ b/include/linux/gpio_mouse.h
@@ -0,0 +1,61 @@
+/*
+ * Driver for simulating a mouse on GPIO lines.
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _GPIO_MOUSE_H
+#define _GPIO_MOUSE_H
+#define GPIO_MOUSE_POLARITY_ACT_HIGH    0x00
+#define GPIO_MOUSE_POLARITY_ACT_LOW     0x01
+#define GPIO_MOUSE_PIN_UP       0
+#define GPIO_MOUSE_PIN_DOWN     1
+#define GPIO_MOUSE_PIN_LEFT     2
+#define GPIO_MOUSE_PIN_RIGHT    3
+#define GPIO_MOUSE_PIN_BLEFT    4
+#define GPIO_MOUSE_PIN_BMIDDLE  5
+#define GPIO_MOUSE_PIN_BRIGHT   6
+#define GPIO_MOUSE_PIN_MAX      7
+/**
+ * struct gpio_mouse_platform_data
+ * @scan_ms: integer in ms specifying the scan periode.
+ * @polarity: Pin polarity, active high or low.
+ * @up: GPIO line for up value.
+ * @down: GPIO line for down value.
+ * @left: GPIO line for left value.
+ * @right: GPIO line for right value.
+ * @bleft: GPIO line for left button.
+ * @bmiddle: GPIO line for middle button.
+ * @bright: GPIO line for right button.
+ *
+ * This struct must be added to the platform_device in the board code.
+ * It is used by the gpio_mouse driver to setup GPIO lines and to
+ * calculate mouse movement.
+ */
+struct gpio_mouse_platform_data {
+        int scan_ms;
+        int polarity;
+        union {
+                struct {
+                        int up;
+                        int down;
+                        int left;
+                        int right;
+                        int bleft;
+                        int bmiddle;
+                        int bright;
+                };
+                int pins[GPIO_MOUSE_PIN_MAX];
+        };
+};
+#endif /* _GPIO_MOUSE_H */
diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h
index 7803014f3a11..8d302298a161 100644
--- a/include/linux/hardirq.h
+++ b/include/linux/hardirq.h
@@ -79,6 +79,19 @@
 #endif
 #ifdef CONFIG_PREEMPT
+# define PREEMPT_CHECK_OFFSET 1
+#else
+# define PREEMPT_CHECK_OFFSET 0
+#endif
+/*
+ * Check whether we were atomic before we did preempt_disable():
+ * (used by the scheduler)
+ */
+#define in_atomic_preempt_off() \
+                ((preempt_count() & ~PREEMPT_ACTIVE) != PREEMPT_CHECK_OFFSET)
+#ifdef CONFIG_PREEMPT
 # define preemptible()  (preempt_count() == 0 && !irqs_disabled())
 # define IRQ_EXIT_OFFSET (HARDIRQ_OFFSET-1)
 #else
diff --git a/include/linux/hid.h b/include/linux/hid.h
index 827ee748fd4c..898103b401f1 100644
--- a/include/linux/hid.h
+++ b/include/linux/hid.h
@@ -263,19 +263,28 @@ struct hid_item {
 #define HID_QUIRK_2WHEEL_MOUSE_HACK_5           0x00000100
 #define HID_QUIRK_2WHEEL_MOUSE_HACK_ON          0x00000200
 #define HID_QUIRK_MIGHTYMOUSE                   0x00000400
-#define HID_QUIRK_CYMOTION                      0x00000800
+#define HID_QUIRK_POWERBOOK_HAS_FN              0x00000800
-#define HID_QUIRK_POWERBOOK_HAS_FN              0x00001000
+#define HID_QUIRK_POWERBOOK_FN_ON               0x00001000
-#define HID_QUIRK_POWERBOOK_FN_ON               0x00002000
+#define HID_QUIRK_INVERT_HWHEEL                 0x00002000
-#define HID_QUIRK_INVERT_HWHEEL                 0x00004000
+#define HID_QUIRK_POWERBOOK_ISO_KEYBOARD        0x00004000
-#define HID_QUIRK_POWERBOOK_ISO_KEYBOARD        0x00008000
+#define HID_QUIRK_BAD_RELATIVE_KEYS             0x00008000
-#define HID_QUIRK_BAD_RELATIVE_KEYS             0x00010000
+#define HID_QUIRK_SKIP_OUTPUT_REPORTS           0x00010000
-#define HID_QUIRK_SKIP_OUTPUT_REPORTS           0x00020000
+#define HID_QUIRK_IGNORE_MOUSE                  0x00020000
-#define HID_QUIRK_IGNORE_MOUSE                  0x00040000
+#define HID_QUIRK_SONY_PS3_CONTROLLER           0x00040000
-#define HID_QUIRK_SONY_PS3_CONTROLLER           0x00080000
+#define HID_QUIRK_DUPLICATE_USAGES              0x00080000
-#define HID_QUIRK_LOGITECH_DESCRIPTOR           0x00100000
+#define HID_QUIRK_RESET_LEDS                    0x00100000
-#define HID_QUIRK_DUPLICATE_USAGES              0x00200000
+#define HID_QUIRK_HIDINPUT                      0x00200000
-#define HID_QUIRK_RESET_LEDS                    0x00400000
+#define HID_QUIRK_LOGITECH_IGNORE_DOUBLED_WHEEL 0x00400000
-#define HID_QUIRK_SWAPPED_MIN_MAX               0x00800000
+#define HID_QUIRK_LOGITECH_EXPANDED_KEYMAP      0x00800000
+/*
+ * Separate quirks for runtime report descriptor fixup
+ */
+#define HID_QUIRK_RDESC_CYMOTION                0x00000001
+#define HID_QUIRK_RDESC_LOGITECH                0x00000002
+#define HID_QUIRK_RDESC_SWAPPED_MIN_MAX         0x00000004
+#define HID_QUIRK_RDESC_PETALYNX                0x00000008
 /*
 * This is the global environment of the parser. This information is
@@ -488,6 +497,11 @@ struct hid_descriptor {
 #define IS_INPUT_APPLICATION(a) (((a >= 0x00010000) && (a <= 0x00010008)) || (a == 0x00010080) || (a == 0x000c0001))
 /* HID core API */
+#ifdef CONFIG_HID_DEBUG
+extern int hid_debug;
+#endif
 extern void hidinput_hid_event(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);
 extern void hidinput_report_event(struct hid_device *hid, struct hid_report *report);
 extern int hidinput_connect(struct hid_device *);
@@ -506,6 +520,7 @@ u32 usbhid_lookup_quirk(const u16 idVendor, const u16 idProduct);
 int usbhid_modify_dquirk(const u16 idVendor, const u16 idProduct, const u32 quirks);
 int usbhid_quirks_init(char **quirks_param);
 void usbhid_quirks_exit(void);
+void usbhid_fixup_report_descriptor(const u16, const u16, char *, unsigned, char **);
 #ifdef CONFIG_HID_FF
 int hid_ff_init(struct hid_device *hid);
@@ -523,14 +538,19 @@ static inline int hid_pidff_init(struct hid_device *hid) { return -ENODEV; }
 #else
 static inline int hid_ff_init(struct hid_device *hid) { return -1; }
 #endif
-#ifdef DEBUG
-#define dbg(format, arg...) printk(KERN_DEBUG "%s: " format "\n" , \
+#ifdef CONFIG_HID_DEBUG
-                __FILE__ , ## arg)
+#define dbg_hid(format, arg...) if (hid_debug) \
+                                printk(KERN_DEBUG "%s: " format ,\
+                                __FILE__ , ## arg)
+#define dbg_hid_line(format, arg...) if (hid_debug) \
+                                printk(format, ## arg)
 #else
-#define dbg(format, arg...) do {} while (0)
+#define dbg_hid(format, arg...) do {} while (0)
+#define dbg_hid_line dbg_hid
 #endif
-#define err(format, arg...) printk(KERN_ERR "%s: " format "\n" , \
+#define err_hid(format, arg...) printk(KERN_ERR "%s: " format "\n" , \
                __FILE__ , ## arg)
 #endif
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index b4570b62ab85..2c13715e9dde 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -163,7 +163,7 @@ static inline struct hugetlbfs_sb_info *HUGETLBFS_SB(struct super_block *sb)
 extern const struct file_operations hugetlbfs_file_operations;
 extern struct vm_operations_struct hugetlb_vm_ops;
-struct file *hugetlb_zero_setup(size_t);
+struct file *hugetlb_file_setup(const char *name, size_t);
 int hugetlb_get_quota(struct address_space *mapping);
 void hugetlb_put_quota(struct address_space *mapping);
@@ -185,7 +185,7 @@ static inline void set_file_hugepages(struct file *file)
 #define is_file_hugepages(file)         0
 #define set_file_hugepages(file)        BUG()
-#define hugetlb_zero_setup(size)        ERR_PTR(-ENOSYS)
+#define hugetlb_file_setup(name,size)   ERR_PTR(-ENOSYS)
 #endif /* !CONFIG_HUGETLBFS */
diff --git a/include/linux/ide.h b/include/linux/ide.h
index 1e365acdd369..19ab25804056 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -25,6 +25,7 @@
 #include <asm/system.h>
 #include <asm/io.h>
 #include <asm/semaphore.h>
+#include <asm/mutex.h>
 /******************************************************************************
 * IDE driver configuration options (play with these as desired):
@@ -685,6 +686,8 @@ typedef struct hwif_s {
        u8 mwdma_mask;
        u8 swdma_mask;
+        u8 cbl;         /* cable type */
        hwif_chipset_t chipset; /* sub-module for tuning.. */
        struct pci_dev  *pci_dev;       /* for pci chipsets */
@@ -735,8 +738,8 @@ typedef struct hwif_s {
        void (*ide_dma_clear_irq)(ide_drive_t *drive);
        void (*dma_host_on)(ide_drive_t *drive);
        void (*dma_host_off)(ide_drive_t *drive);
-        int (*ide_dma_lostirq)(ide_drive_t *drive);
+        void (*dma_lost_irq)(ide_drive_t *drive);
-        int (*ide_dma_timeout)(ide_drive_t *drive);
+        void (*dma_timeout)(ide_drive_t *drive);
        void (*OUTB)(u8 addr, unsigned long port);
        void (*OUTBSYNC)(ide_drive_t *drive, u8 addr, unsigned long port);
@@ -791,7 +794,6 @@ typedef struct hwif_s {
        unsigned        sharing_irq: 1; /* 1 = sharing irq with another hwif */
        unsigned        reset      : 1; /* reset after probe */
        unsigned        autodma    : 1; /* auto-attempt using DMA at boot */
-        unsigned        udma_four  : 1; /* 1=ATA-66 capable, 0=default */
        unsigned        no_lba48   : 1; /* 1 = cannot do LBA48 */
        unsigned        no_lba48_dma : 1; /* 1 = cannot do LBA48 DMA */
        unsigned        auto_poll  : 1; /* supports nop auto-poll */
@@ -863,7 +865,7 @@ typedef struct hwgroup_s {
 typedef struct ide_driver_s ide_driver_t;
-extern struct semaphore ide_setting_sem;
+extern struct mutex ide_setting_mtx;
 int set_io_32bit(ide_drive_t *, int);
 int set_pio_mode(ide_drive_t *, int);
@@ -1304,8 +1306,8 @@ extern int __ide_dma_check(ide_drive_t *);
 extern int ide_dma_setup(ide_drive_t *);
 extern void ide_dma_start(ide_drive_t *);
 extern int __ide_dma_end(ide_drive_t *);
-extern int __ide_dma_lostirq(ide_drive_t *);
+extern void ide_dma_lost_irq(ide_drive_t *);
-extern int __ide_dma_timeout(ide_drive_t *);
+extern void ide_dma_timeout(ide_drive_t *);
 #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
 #else
@@ -1382,11 +1384,11 @@ extern const ide_pio_timings_t ide_pio_timings[6];
 extern spinlock_t ide_lock;
-extern struct semaphore ide_cfg_sem;
+extern struct mutex ide_cfg_mtx;
 /*
 * Structure locking:
 *
- * ide_cfg_sem and ide_lock together protect changes to
+ * ide_cfg_mtx and ide_lock together protect changes to
 * ide_hwif_t->{next,hwgroup}
 * ide_drive_t->next
 *
diff --git a/include/linux/inetdevice.h b/include/linux/inetdevice.h
index ae04901aa09a..d83fee2dc643 100644
--- a/include/linux/inetdevice.h
+++ b/include/linux/inetdevice.h
@@ -8,6 +8,7 @@
 #include <linux/netdevice.h>
 #include <linux/rcupdate.h>
 #include <linux/timer.h>
+#include <linux/sysctl.h>
 struct ipv4_devconf
 {
diff --git a/include/linux/input.h b/include/linux/input.h
index be2bf3a2b031..18c98b543030 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -108,6 +108,13 @@ struct input_absinfo {
 /*
 * Keys and buttons
+ *
+ * Most of the keys/buttons are modeled after USB HUT 1.12
+ * (see http://www.usb.org/developers/hidpage).
+ * Abbreviations in the comments:
+ * AC - Application Control
+ * AL - Application Launch Button
+ * SC - System Control
 */
 #define KEY_RESERVED            0
@@ -226,7 +233,7 @@ struct input_absinfo {
 #define KEY_MUTE                113
 #define KEY_VOLUMEDOWN          114
 #define KEY_VOLUMEUP            115
-#define KEY_POWER               116
+#define KEY_POWER               116     /* SC System Power Down */
 #define KEY_KPEQUAL             117
 #define KEY_KPPLUSMINUS         118
 #define KEY_PAUSE               119
@@ -240,38 +247,39 @@ struct input_absinfo {
 #define KEY_RIGHTMETA           126
 #define KEY_COMPOSE             127
-#define KEY_STOP                128
+#define KEY_STOP                128     /* AC Stop */
 #define KEY_AGAIN               129
-#define KEY_PROPS               130
+#define KEY_PROPS               130     /* AC Properties */
-#define KEY_UNDO                131
+#define KEY_UNDO                131     /* AC Undo */
 #define KEY_FRONT               132
-#define KEY_COPY                133
+#define KEY_COPY                133     /* AC Copy */
-#define KEY_OPEN                134
+#define KEY_OPEN                134     /* AC Open */
-#define KEY_PASTE               135
+#define KEY_PASTE               135     /* AC Paste */
-#define KEY_FIND                136
+#define KEY_FIND                136     /* AC Search */
-#define KEY_CUT                 137
+#define KEY_CUT                 137     /* AC Cut */
-#define KEY_HELP                138
+#define KEY_HELP                138     /* AL Integrated Help Center */
-#define KEY_MENU                139
+#define KEY_MENU                139     /* Menu (show menu) */
-#define KEY_CALC                140
+#define KEY_CALC                140     /* AL Calculator */
 #define KEY_SETUP               141
-#define KEY_SLEEP               142
+#define KEY_SLEEP               142     /* SC System Sleep */
-#define KEY_WAKEUP              143
+#define KEY_WAKEUP              143     /* System Wake Up */
-#define KEY_FILE                144
+#define KEY_FILE                144     /* AL Local Machine Browser */
 #define KEY_SENDFILE            145
 #define KEY_DELETEFILE          146
 #define KEY_XFER                147
 #define KEY_PROG1               148
 #define KEY_PROG2               149
-#define KEY_WWW                 150
+#define KEY_WWW                 150     /* AL Internet Browser */
 #define KEY_MSDOS               151
-#define KEY_COFFEE              152
+#define KEY_COFFEE              152     /* AL Terminal Lock/Screensaver */
+#define KEY_SCREENLOCK          KEY_COFFEE
 #define KEY_DIRECTION           153
 #define KEY_CYCLEWINDOWS        154
 #define KEY_MAIL                155
-#define KEY_BOOKMARKS           156
+#define KEY_BOOKMARKS           156     /* AC Bookmarks */
 #define KEY_COMPUTER            157
-#define KEY_BACK                158
+#define KEY_BACK                158     /* AC Back */
-#define KEY_FORWARD             159
+#define KEY_FORWARD             159     /* AC Forward */
 #define KEY_CLOSECD             160
 #define KEY_EJECTCD             161
 #define KEY_EJECTCLOSECD        162
@@ -281,20 +289,20 @@ struct input_absinfo {
 #define KEY_STOPCD              166
 #define KEY_RECORD              167
 #define KEY_REWIND              168
-#define KEY_PHONE               169
+#define KEY_PHONE               169     /* Media Select Telephone */
 #define KEY_ISO                 170
-#define KEY_CONFIG              171
+#define KEY_CONFIG              171     /* AL Consumer Control Configuration */
-#define KEY_HOMEPAGE            172
+#define KEY_HOMEPAGE            172     /* AC Home */
-#define KEY_REFRESH             173
+#define KEY_REFRESH             173     /* AC Refresh */
-#define KEY_EXIT                174
+#define KEY_EXIT                174     /* AC Exit */
 #define KEY_MOVE                175
 #define KEY_EDIT                176
 #define KEY_SCROLLUP            177
 #define KEY_SCROLLDOWN          178
 #define KEY_KPLEFTPAREN         179
 #define KEY_KPRIGHTPAREN        180
-#define KEY_NEW                 181
+#define KEY_NEW                 181     /* AC New */
-#define KEY_REDO                182
+#define KEY_REDO                182     /* AC Redo/Repeat */
 #define KEY_F13                 183
 #define KEY_F14                 184
@@ -314,11 +322,11 @@ struct input_absinfo {
 #define KEY_PROG3               202
 #define KEY_PROG4               203
 #define KEY_SUSPEND             205
-#define KEY_CLOSE               206
+#define KEY_CLOSE               206     /* AC Close */
 #define KEY_PLAY                207
 #define KEY_FASTFORWARD         208
 #define KEY_BASSBOOST           209
-#define KEY_PRINT               210
+#define KEY_PRINT               210     /* AC Print */
 #define KEY_HP                  211
 #define KEY_CAMERA              212
 #define KEY_SOUND               213
@@ -327,11 +335,11 @@ struct input_absinfo {
 #define KEY_CHAT                216
 #define KEY_SEARCH              217
 #define KEY_CONNECT             218
-#define KEY_FINANCE             219
+#define KEY_FINANCE             219     /* AL Checkbook/Finance */
 #define KEY_SPORT               220
 #define KEY_SHOP                221
 #define KEY_ALTERASE            222
-#define KEY_CANCEL              223
+#define KEY_CANCEL              223     /* AC Cancel */
 #define KEY_BRIGHTNESSDOWN      224
 #define KEY_BRIGHTNESSUP        225
 #define KEY_MEDIA               226
@@ -341,10 +349,10 @@ struct input_absinfo {
 #define KEY_KBDILLUMDOWN        229
 #define KEY_KBDILLUMUP          230
-#define KEY_SEND                231
+#define KEY_SEND                231     /* AC Send */
-#define KEY_REPLY               232
+#define KEY_REPLY               232     /* AC Reply */
-#define KEY_FORWARDMAIL         233
+#define KEY_FORWARDMAIL         233     /* AC Forward Msg */
-#define KEY_SAVE                234
+#define KEY_SAVE                234     /* AC Save */
 #define KEY_DOCUMENTS           235
 #define KEY_BATTERY             236
@@ -433,15 +441,15 @@ struct input_absinfo {
 #define KEY_CLEAR               0x163
 #define KEY_POWER2              0x164
 #define KEY_OPTION              0x165
-#define KEY_INFO                0x166
+#define KEY_INFO                0x166   /* AL OEM Features/Tips/Tutorial */
 #define KEY_TIME                0x167
 #define KEY_VENDOR              0x168
 #define KEY_ARCHIVE             0x169
-#define KEY_PROGRAM             0x16a
+#define KEY_PROGRAM             0x16a   /* Media Select Program Guide */
 #define KEY_CHANNEL             0x16b
 #define KEY_FAVORITES           0x16c
 #define KEY_EPG                 0x16d
-#define KEY_PVR                 0x16e
+#define KEY_PVR                 0x16e   /* Media Select Home */
 #define KEY_MHP                 0x16f
 #define KEY_LANGUAGE            0x170
 #define KEY_TITLE               0x171
@@ -451,36 +459,36 @@ struct input_absinfo {
 #define KEY_MODE                0x175
 #define KEY_KEYBOARD            0x176
 #define KEY_SCREEN              0x177
-#define KEY_PC                  0x178
+#define KEY_PC                  0x178   /* Media Select Computer */
-#define KEY_TV                  0x179
+#define KEY_TV                  0x179   /* Media Select TV */
-#define KEY_TV2                 0x17a
+#define KEY_TV2                 0x17a   /* Media Select Cable */
-#define KEY_VCR                 0x17b
+#define KEY_VCR                 0x17b   /* Media Select VCR */
-#define KEY_VCR2                0x17c
+#define KEY_VCR2                0x17c   /* VCR Plus */
-#define KEY_SAT                 0x17d
+#define KEY_SAT                 0x17d   /* Media Select Satellite */
 #define KEY_SAT2                0x17e
-#define KEY_CD                  0x17f
+#define KEY_CD                  0x17f   /* Media Select CD */
-#define KEY_TAPE                0x180
+#define KEY_TAPE                0x180   /* Media Select Tape */
 #define KEY_RADIO               0x181
-#define KEY_TUNER               0x182
+#define KEY_TUNER               0x182   /* Media Select Tuner */
 #define KEY_PLAYER              0x183
 #define KEY_TEXT                0x184
-#define KEY_DVD                 0x185
+#define KEY_DVD                 0x185   /* Media Select DVD */
 #define KEY_AUX                 0x186
 #define KEY_MP3                 0x187
 #define KEY_AUDIO               0x188
 #define KEY_VIDEO               0x189
 #define KEY_DIRECTORY           0x18a
 #define KEY_LIST                0x18b
-#define KEY_MEMO                0x18c
+#define KEY_MEMO                0x18c   /* Media Select Messages */
 #define KEY_CALENDAR            0x18d
 #define KEY_RED                 0x18e
 #define KEY_GREEN               0x18f
 #define KEY_YELLOW              0x190
 #define KEY_BLUE                0x191
-#define KEY_CHANNELUP           0x192
+#define KEY_CHANNELUP           0x192   /* Channel Increment */
-#define KEY_CHANNELDOWN         0x193
+#define KEY_CHANNELDOWN         0x193   /* Channel Decrement */
 #define KEY_FIRST               0x194
-#define KEY_LAST                0x195
+#define KEY_LAST                0x195   /* Recall Last */
 #define KEY_AB                  0x196
 #define KEY_NEXT                0x197
 #define KEY_RESTART             0x198
@@ -491,21 +499,21 @@ struct input_absinfo {
 #define KEY_DIGITS              0x19d
 #define KEY_TEEN                0x19e
 #define KEY_TWEN                0x19f
-#define KEY_VIDEOPHONE          0x1a0
+#define KEY_VIDEOPHONE          0x1a0   /* Media Select Video Phone */
-#define KEY_GAMES               0x1a1
+#define KEY_GAMES               0x1a1   /* Media Select Games */
-#define KEY_ZOOMIN              0x1a2
+#define KEY_ZOOMIN              0x1a2   /* AC Zoom In */
-#define KEY_ZOOMOUT             0x1a3
+#define KEY_ZOOMOUT             0x1a3   /* AC Zoom Out */
-#define KEY_ZOOMRESET           0x1a4
+#define KEY_ZOOMRESET           0x1a4   /* AC Zoom */
-#define KEY_WORDPROCESSOR       0x1a5
+#define KEY_WORDPROCESSOR       0x1a5   /* AL Word Processor */
-#define KEY_EDITOR              0x1a6
+#define KEY_EDITOR              0x1a6   /* AL Text Editor */
-#define KEY_SPREADSHEET         0x1a7
+#define KEY_SPREADSHEET         0x1a7   /* AL Spreadsheet */
-#define KEY_GRAPHICSEDITOR      0x1a8
+#define KEY_GRAPHICSEDITOR      0x1a8   /* AL Graphics Editor */
-#define KEY_PRESENTATION        0x1a9
+#define KEY_PRESENTATION        0x1a9   /* AL Presentation App */
-#define KEY_DATABASE            0x1aa
+#define KEY_DATABASE            0x1aa   /* AL Database App */
-#define KEY_NEWS                0x1ab
+#define KEY_NEWS                0x1ab   /* AL Newsreader */
-#define KEY_VOICEMAIL           0x1ac
+#define KEY_VOICEMAIL           0x1ac   /* AL Voicemail */
-#define KEY_ADDRESSBOOK         0x1ad
+#define KEY_ADDRESSBOOK         0x1ad   /* AL Contacts/Address Book */
-#define KEY_MESSENGER           0x1ae
+#define KEY_MESSENGER           0x1ae   /* AL Instant Messaging */
 #define KEY_DISPLAYTOGGLE       0x1af   /* Turn display (LCD) on and off */
 #define KEY_DEL_EOL             0x1c0
@@ -603,6 +611,7 @@ struct input_absinfo {
 #define SW_LID                  0x00  /* set = lid shut */
 #define SW_TABLET_MODE          0x01  /* set = tablet mode */
 #define SW_HEADPHONE_INSERT     0x02  /* set = inserted */
+#define SW_RADIO                0x03  /* set = radio enabled */
 #define SW_MAX                  0x0f
 /*
@@ -972,15 +981,15 @@ struct input_dev {
        struct mutex mutex;     /* serializes open and close operations */
        unsigned int users;
-        struct class_device cdev;
+        struct device dev;
        union {                 /* temporarily so while we switching to struct device */
-                struct device *parent;
+                struct device *dev;
-        } dev;
+        } cdev;
        struct list_head        h_list;
        struct list_head        node;
 };
-#define to_input_dev(d) container_of(d, struct input_dev, cdev)
+#define to_input_dev(d) container_of(d, struct input_dev, dev)
 /*
 * Verify that we are in sync with input_device_id mod_devicetable.h #defines
@@ -1087,22 +1096,22 @@ struct input_handle {
        struct list_head        h_node;
 };
-#define to_dev(n) container_of(n,struct input_dev,node)
+#define to_dev(n) container_of(n, struct input_dev, node)
-#define to_handler(n) container_of(n,struct input_handler,node)
+#define to_handler(n) container_of(n, struct input_handler, node)
-#define to_handle(n) container_of(n,struct input_handle,d_node)
+#define to_handle(n) container_of(n, struct input_handle, d_node)
-#define to_handle_h(n) container_of(n,struct input_handle,h_node)
+#define to_handle_h(n) container_of(n, struct input_handle, h_node)
 struct input_dev *input_allocate_device(void);
 void input_free_device(struct input_dev *dev);
 static inline struct input_dev *input_get_device(struct input_dev *dev)
 {
-        return to_input_dev(class_device_get(&dev->cdev));
+        return to_input_dev(get_device(&dev->dev));
 }
 static inline void input_put_device(struct input_dev *dev)
 {
-        class_device_put(&dev->cdev);
+        put_device(&dev->dev);
 }
 static inline void *input_get_drvdata(struct input_dev *dev)
diff --git a/include/linux/ioprio.h b/include/linux/ioprio.h
index 8e2042b9d471..2eaa142cd061 100644
--- a/include/linux/ioprio.h
+++ b/include/linux/ioprio.h
@@ -47,8 +47,10 @@ enum {
 #define IOPRIO_NORM     (4)
 static inline int task_ioprio(struct task_struct *task)
 {
-        WARN_ON(!ioprio_valid(task->ioprio));
+        if (ioprio_valid(task->ioprio))
-        return IOPRIO_PRIO_DATA(task->ioprio);
+                return IOPRIO_PRIO_DATA(task->ioprio);
+        return IOPRIO_NORM;
 }
 static inline int task_nice_ioprio(struct task_struct *task)
diff --git a/include/linux/kallsyms.h b/include/linux/kallsyms.h
index 12178d2c882b..5f06527dca21 100644
--- a/include/linux/kallsyms.h
+++ b/include/linux/kallsyms.h
@@ -5,6 +5,7 @@
 #ifndef _LINUX_KALLSYMS_H
 #define _LINUX_KALLSYMS_H
+#include <linux/errno.h>
 #define KSYM_NAME_LEN 127
 #define KSYM_SYMBOL_LEN (sizeof("%s+%#lx/%#lx [%s]") + KSYM_NAME_LEN +  \
diff --git a/include/linux/ktime.h b/include/linux/ktime.h
index c762954bda14..2b139f66027f 100644
--- a/include/linux/ktime.h
+++ b/include/linux/ktime.h
@@ -261,6 +261,18 @@ static inline s64 ktime_to_ns(const ktime_t kt)
 #endif
+/**
+ * ktime_equal - Compares two ktime_t variables to see if they are equal
+ * @cmp1:       comparable1
+ * @cmp2:       comparable2
+ *
+ * Compare two ktime_t variables, returns 1 if equal
+ */
+static inline int ktime_equal(const ktime_t cmp1, const ktime_t cmp2)
+{
+        return cmp1.tv64 == cmp2.tv64;
+}
 static inline s64 ktime_to_us(const ktime_t kt)
 {
        struct timeval tv = ktime_to_timeval(kt);
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 745c4f9b4caa..a3df64677ac3 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -116,6 +116,7 @@ static inline struct device *pci_dev_to_dev(struct pci_dev *pdev)
 enum {
        /* various global constants */
        LIBATA_MAX_PRD          = ATA_MAX_PRD / 2,
+        LIBATA_DUMB_MAX_PRD     = ATA_MAX_PRD / 4,      /* Worst case */
        ATA_MAX_PORTS           = 8,
        ATA_DEF_QUEUE           = 1,
        /* tag ATA_MAX_QUEUE - 1 is reserved for internal commands */
@@ -136,6 +137,8 @@ enum {
        ATA_DFLAG_CDB_INTR      = (1 << 2), /* device asserts INTRQ when ready for CDB */
        ATA_DFLAG_NCQ           = (1 << 3), /* device supports NCQ */
        ATA_DFLAG_FLUSH_EXT     = (1 << 4), /* do FLUSH_EXT instead of FLUSH */
+        ATA_DFLAG_ACPI_PENDING  = (1 << 5), /* ACPI resume action pending */
+        ATA_DFLAG_ACPI_FAILED   = (1 << 6), /* ACPI on devcfg has failed */
        ATA_DFLAG_CFG_MASK      = (1 << 8) - 1,
        ATA_DFLAG_PIO           = (1 << 8), /* device limited to PIO mode */
@@ -196,6 +199,7 @@ enum {
        ATA_PFLAG_FLUSH_PORT_TASK = (1 << 16), /* flush port task */
        ATA_PFLAG_SUSPENDED     = (1 << 17), /* port is suspended (power) */
        ATA_PFLAG_PM_PENDING    = (1 << 18), /* PM operation pending */
+        ATA_PFLAG_GTM_VALID     = (1 << 19), /* acpi_gtm data valid */
        /* struct ata_queued_cmd flags */
        ATA_QCFLAG_ACTIVE       = (1 << 0), /* cmd not yet ack'd to scsi lyer */
@@ -298,7 +302,6 @@ enum {
        ATA_HORKAGE_NODMA       = (1 << 1),     /* DMA problems */
        ATA_HORKAGE_NONCQ       = (1 << 2),     /* Don't use NCQ */
        ATA_HORKAGE_MAX_SEC_128 = (1 << 3),     /* Limit max sects to 128 */
-        ATA_HORKAGE_DMA_RW_ONLY = (1 << 4),     /* ATAPI DMA for RW only */
 };
 enum hsm_task_states {
@@ -364,6 +367,9 @@ struct ata_host {
        void                    *private_data;
        const struct ata_port_operations *ops;
        unsigned long           flags;
+#ifdef CONFIG_ATA_ACPI
+        acpi_handle             acpi_handle;
+#endif
        struct ata_port         *simplex_claimed;       /* channel owning the DMA */
        struct ata_port         *ports[0];
 };
@@ -430,6 +436,9 @@ struct ata_device {
        unsigned int            devno;          /* 0 or 1 */
        unsigned long           flags;          /* ATA_DFLAG_xxx */
        struct scsi_device      *sdev;          /* attached SCSI device */
+#ifdef CONFIG_ATA_ACPI
+        acpi_handle             acpi_handle;
+#endif
        /* n_sector is used as CLEAR_OFFSET, read comment above CLEAR_OFFSET */
        u64                     n_sectors;      /* size of device, if ATA */
        unsigned int            class;          /* ATA_DEV_xxx */
@@ -458,10 +467,6 @@ struct ata_device {
        struct ata_ering        ering;
        int                     spdn_cnt;
        unsigned int            horkage;        /* List of broken features */
-#ifdef CONFIG_ATA_ACPI
-        /* ACPI objects info */
-        acpi_handle obj_handle;
-#endif
 };
 /* Offset into struct ata_device.  Fields above it are maintained
@@ -490,6 +495,17 @@ struct ata_eh_context {
        unsigned int            did_probe_mask;
 };
+struct ata_acpi_drive
+{
+        u32 pio;
+        u32 dma;
+} __packed;
+struct ata_acpi_gtm {
+        struct ata_acpi_drive drive[2];
+        u32 flags;
+} __packed;
 struct ata_port {
        struct Scsi_Host        *scsi_host; /* our co-allocated scsi host */
        const struct ata_port_operations *ops;
@@ -550,6 +566,10 @@ struct ata_port {
        void                    *private_data;
+#ifdef CONFIG_ATA_ACPI
+        acpi_handle             acpi_handle;
+        struct ata_acpi_gtm     acpi_gtm;
+#endif
        u8                      sector_buf[ATA_SECT_SIZE]; /* owned by EH */
 };
@@ -759,6 +779,7 @@ extern void ata_data_xfer(struct ata_device *adev, unsigned char *buf,
                          unsigned int buflen, int write_data);
 extern void ata_data_xfer_noirq(struct ata_device *adev, unsigned char *buf,
                                unsigned int buflen, int write_data);
+extern void ata_dumb_qc_prep(struct ata_queued_cmd *qc);
 extern void ata_qc_prep(struct ata_queued_cmd *qc);
 extern void ata_noop_qc_prep(struct ata_queued_cmd *qc);
 extern unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc);
@@ -1088,11 +1109,9 @@ static inline u8 ata_wait_idle(struct ata_port *ap)
 {
        u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
-        if (status != 0xff && (status & (ATA_BUSY | ATA_DRQ))) {
+        if (status != 0xff && (status & (ATA_BUSY | ATA_DRQ)))
-                if (ata_msg_warn(ap))
+                DPRINTK("ATA: abnormal status 0x%X on port 0x%p\n",
-                        printk(KERN_WARNING "ATA: abnormal status 0x%X on port 0x%p\n",
+                        status, ap->ioaddr.status_addr);
-                                status, ap->ioaddr.status_addr);
-        }
        return status;
 }
diff --git a/include/linux/lzo.h b/include/linux/lzo.h
new file mode 100644
index 000000000000..582d8b711a13
--- /dev/null
+++ b/include/linux/lzo.h
@@ -0,0 +1,44 @@
+#ifndef __LZO_H__
+#define __LZO_H__
+/*
+ *  LZO Public Kernel Interface
+ *  A mini subset of the LZO real-time data compression library
+ *
+ *  Copyright (C) 1996-2005 Markus F.X.J. Oberhumer <markus@oberhumer.com>
+ *
+ *  The full LZO package can be found at:
+ *  http://www.oberhumer.com/opensource/lzo/
+ *
+ *  Changed for kernel use by:
+ *  Nitin Gupta <nitingupta910@gmail.com>
+ *  Richard Purdie <rpurdie@openedhand.com>
+ */
+#define LZO1X_MEM_COMPRESS      (16384 * sizeof(unsigned char *))
+#define LZO1X_1_MEM_COMPRESS    LZO1X_MEM_COMPRESS
+#define lzo1x_worst_compress(x) (x + (x / 64) + 16 + 3)
+/* This requires 'workmem' of size LZO1X_1_MEM_COMPRESS */
+int lzo1x_1_compress(const unsigned char *src, size_t src_len,
+                        unsigned char *dst, size_t *dst_len, void *wrkmem);
+/* safe decompression with overrun testing */
+int lzo1x_decompress_safe(const unsigned char *src, size_t src_len,
+                        unsigned char *dst, size_t *dst_len);
+/*
+ * Return values (< 0 = Error)
+ */
+#define LZO_E_OK                        0
+#define LZO_E_ERROR                     (-1)
+#define LZO_E_OUT_OF_MEMORY             (-2)
+#define LZO_E_NOT_COMPRESSIBLE          (-3)
+#define LZO_E_INPUT_OVERRUN             (-4)
+#define LZO_E_OUTPUT_OVERRUN            (-5)
+#define LZO_E_LOOKBEHIND_OVERRUN        (-6)
+#define LZO_E_EOF_NOT_FOUND             (-7)
+#define LZO_E_INPUT_NOT_CONSUMED        (-8)
+#define LZO_E_NOT_YET_IMPLEMENTED       (-9)
+#endif
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h
index 4fb552d12f7a..7d1eaa97de13 100644
--- a/include/linux/mlx4/cmd.h
+++ b/include/linux/mlx4/cmd.h
@@ -54,6 +54,7 @@ enum {
        MLX4_CMD_INIT_PORT       = 0x9,
        MLX4_CMD_CLOSE_PORT      = 0xa,
        MLX4_CMD_QUERY_HCA       = 0xb,
+        MLX4_CMD_QUERY_PORT      = 0x43,
        MLX4_CMD_SET_PORT        = 0xc,
        MLX4_CMD_ACCESS_DDR      = 0x2e,
        MLX4_CMD_MAP_ICM         = 0xffa,
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 8c5f8fd86841..b372f5910fc1 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -41,6 +41,7 @@
 enum {
        MLX4_FLAG_MSI_X         = 1 << 0,
+        MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
 };
 enum {
@@ -131,10 +132,10 @@ enum {
 struct mlx4_caps {
        u64                     fw_ver;
        int                     num_ports;
-        int                     vl_cap;
+        int                     vl_cap[MLX4_MAX_PORTS + 1];
-        int                     mtu_cap;
+        int                     mtu_cap[MLX4_MAX_PORTS + 1];
-        int                     gid_table_len;
+        int                     gid_table_len[MLX4_MAX_PORTS + 1];
-        int                     pkey_table_len;
+        int                     pkey_table_len[MLX4_MAX_PORTS + 1];
        int                     local_ca_ack_delay;
        int                     num_uars;
        int                     bf_reg_size;
@@ -174,7 +175,7 @@ struct mlx4_caps {
        u32                     page_size_cap;
        u32                     flags;
        u16                     stat_rate_support;
-        u8                      port_width_cap;
+        u8                      port_width_cap[MLX4_MAX_PORTS + 1];
 };
 struct mlx4_buf_list {
@@ -322,7 +323,7 @@ int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
-int mlx4_INIT_PORT(struct mlx4_dev *dev, struct mlx4_init_port_param *param, int port);
+int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index 9eeb61adf6a3..10c57d279144 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -269,6 +269,10 @@ struct mlx4_wqe_data_seg {
        __be64                  addr;
 };
+enum {
+        MLX4_INLINE_ALIGN       = 64,
+};
 struct mlx4_wqe_inline_seg {
        __be32                  byte_count;
 };
diff --git a/include/linux/mm.h b/include/linux/mm.h
index e4183c6c7de3..1c1207472bb4 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -603,6 +603,10 @@ static inline struct address_space *page_mapping(struct page *page)
        if (unlikely(PageSwapCache(page)))
                mapping = &swapper_space;
+#ifdef CONFIG_SLUB
+        else if (unlikely(PageSlab(page)))
+                mapping = NULL;
+#endif
        else if (unlikely((unsigned long)mapping & PAGE_MAPPING_ANON))
                mapping = NULL;
        return mapping;
diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h
index c6d4ab86b83c..b021b3a2b65a 100644
--- a/include/linux/mv643xx.h
+++ b/include/linux/mv643xx.h
@@ -13,10 +13,6 @@
 #ifndef __ASM_MV643XX_H
 #define __ASM_MV643XX_H
-#ifdef __mips__
-#include <asm/addrspace.h>
-#include <asm/marvell.h>
-#endif
 #include <asm/types.h>
 /****************************************/
diff --git a/include/linux/pata_platform.h b/include/linux/pata_platform.h
index 2d5fd647e0e9..5799e8d50623 100644
--- a/include/linux/pata_platform.h
+++ b/include/linux/pata_platform.h
@@ -8,6 +8,11 @@ struct pata_platform_info {
         * spacing used by ata_std_ports().
         */
        unsigned int ioport_shift;
+        /* 
+         * Indicate platform specific irq types and initial
+         * IRQ flags when call request_irq()
+         */
+        unsigned int irq_flags;
 };
 #endif /* __LINUX_PATA_PLATFORM_H */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index fbf3766dac1e..086a0e5a6318 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -748,6 +748,17 @@ static inline void pci_release_regions(struct pci_dev *dev) { }
 static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
+static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
+{ return NULL; }
+static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
+                                                unsigned int devfn)
+{ return NULL; }
+static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
+                                                unsigned int devfn)
+{ return NULL; }
 #endif /* CONFIG_PCI */
 /* Include architecture-dependent settings and functions */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 9a03b47da603..75c4d4d06892 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -661,6 +661,7 @@
 #define PCI_DEVICE_ID_SI_965            0x0965
 #define PCI_DEVICE_ID_SI_966            0x0966
 #define PCI_DEVICE_ID_SI_968            0x0968
+#define PCI_DEVICE_ID_SI_1180           0x1180
 #define PCI_DEVICE_ID_SI_5511           0x5511
 #define PCI_DEVICE_ID_SI_5513           0x5513
 #define PCI_DEVICE_ID_SI_5517           0x5517
@@ -1999,6 +2000,7 @@
 #define PCI_VENDOR_ID_ENE               0x1524
 #define PCI_DEVICE_ID_ENE_CB712_SD      0x0550
+#define PCI_DEVICE_ID_ENE_CB712_SD_2    0x0551
 #define PCI_DEVICE_ID_ENE_1211          0x1211
 #define PCI_DEVICE_ID_ENE_1225          0x1225
 #define PCI_DEVICE_ID_ENE_1410          0x1410
diff --git a/include/linux/pda_power.h b/include/linux/pda_power.h
new file mode 100644
index 000000000000..1375f15797e7
--- /dev/null
+++ b/include/linux/pda_power.h
@@ -0,0 +1,31 @@
+/*
+ * Common power driver for PDAs and phones with one or two external
+ * power supplies (AC/USB) connected to main and backup batteries,
+ * and optional builtin charger.
+ *
+ * Copyright © 2007 Anton Vorontsov <cbou@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __PDA_POWER_H__
+#define __PDA_POWER_H__
+#define PDA_POWER_CHARGE_AC  (1 << 0)
+#define PDA_POWER_CHARGE_USB (1 << 1)
+struct pda_power_pdata {
+        int (*is_ac_online)(void);
+        int (*is_usb_online)(void);
+        void (*set_charge)(int flags);
+        char **supplied_to;
+        size_t num_supplicants;
+        unsigned int wait_for_status; /* msecs, default is 500 */
+        unsigned int wait_for_charger; /* msecs, default is 500 */
+};
+#endif /* __PDA_POWER_H__ */
diff --git a/include/linux/pipe_fs_i.h b/include/linux/pipe_fs_i.h
index c8884f971228..8e4120285f72 100644
--- a/include/linux/pipe_fs_i.h
+++ b/include/linux/pipe_fs_i.h
@@ -9,13 +9,39 @@
 #define PIPE_BUF_FLAG_ATOMIC    0x02    /* was atomically mapped */
 #define PIPE_BUF_FLAG_GIFT      0x04    /* page is a gift */
+/**
+ *      struct pipe_buffer - a linux kernel pipe buffer
+ *      @page: the page containing the data for the pipe buffer
+ *      @offset: offset of data inside the @page
+ *      @len: length of data inside the @page
+ *      @ops: operations associated with this buffer. See @pipe_buf_operations.
+ *      @flags: pipe buffer flags. See above.
+ *      @private: private data owned by the ops.
+ **/
 struct pipe_buffer {
        struct page *page;
        unsigned int offset, len;
        const struct pipe_buf_operations *ops;
        unsigned int flags;
+        unsigned long private;
 };
+/**
+ *      struct pipe_inode_info - a linux kernel pipe
+ *      @wait: reader/writer wait point in case of empty/full pipe
+ *      @nrbufs: the number of non-empty pipe buffers in this pipe
+ *      @curbuf: the current pipe buffer entry
+ *      @tmp_page: cached released page
+ *      @readers: number of current readers of this pipe
+ *      @writers: number of current writers of this pipe
+ *      @waiting_writers: number of writers blocked waiting for room
+ *      @r_counter: reader counter
+ *      @w_counter: writer counter
+ *      @fasync_readers: reader side fasync
+ *      @fasync_writers: writer side fasync
+ *      @inode: inode this pipe is attached to
+ *      @bufs: the circular array of pipe buffers
+ **/
 struct pipe_inode_info {
        wait_queue_head_t wait;
        unsigned int nrbufs, curbuf;
@@ -34,22 +60,73 @@ struct pipe_inode_info {
 /*
 * Note on the nesting of these functions:
 *
- * ->pin()
+ * ->confirm()
 *      ->steal()
 *      ...
 *      ->map()
 *      ...
 *      ->unmap()
 *
- * That is, ->map() must be called on a pinned buffer, same goes for ->steal().
+ * That is, ->map() must be called on a confirmed buffer,
+ * same goes for ->steal(). See below for the meaning of each
+ * operation. Also see kerneldoc in fs/pipe.c for the pipe
+ * and generic variants of these hooks.
 */
 struct pipe_buf_operations {
+        /*
+         * This is set to 1, if the generic pipe read/write may coalesce
+         * data into an existing buffer. If this is set to 0, a new pipe
+         * page segment is always used for new data.
+         */
        int can_merge;
+        /*
+         * ->map() returns a virtual address mapping of the pipe buffer.
+         * The last integer flag reflects whether this should be an atomic
+         * mapping or not. The atomic map is faster, however you can't take
+         * page faults before calling ->unmap() again. So if you need to eg
+         * access user data through copy_to/from_user(), then you must get
+         * a non-atomic map. ->map() uses the KM_USER0 atomic slot for
+         * atomic maps, so you can't map more than one pipe_buffer at once
+         * and you have to be careful if mapping another page as source
+         * or destination for a copy (IOW, it has to use something else
+         * than KM_USER0).
+         */
        void * (*map)(struct pipe_inode_info *, struct pipe_buffer *, int);
+        /*
+         * Undoes ->map(), finishes the virtual mapping of the pipe buffer.
+         */
        void (*unmap)(struct pipe_inode_info *, struct pipe_buffer *, void *);
-        int (*pin)(struct pipe_inode_info *, struct pipe_buffer *);
+        /*
+         * ->confirm() verifies that the data in the pipe buffer is there
+         * and that the contents are good. If the pages in the pipe belong
+         * to a file system, we may need to wait for IO completion in this
+         * hook. Returns 0 for good, or a negative error value in case of
+         * error.
+         */
+        int (*confirm)(struct pipe_inode_info *, struct pipe_buffer *);
+        /*
+         * When the contents of this pipe buffer has been completely
+         * consumed by a reader, ->release() is called.
+         */
        void (*release)(struct pipe_inode_info *, struct pipe_buffer *);
+        /*
+         * Attempt to take ownership of the pipe buffer and its contents.
+         * ->steal() returns 0 for success, in which case the contents
+         * of the pipe (the buf->page) is locked and now completely owned
+         * by the caller. The page may then be transferred to a different
+         * mapping, the most often used case is insertion into different
+         * file address space cache.
+         */
        int (*steal)(struct pipe_inode_info *, struct pipe_buffer *);
+        /*
+         * Get a reference to the pipe buffer.
+         */
        void (*get)(struct pipe_inode_info *, struct pipe_buffer *);
 };
@@ -68,39 +145,7 @@ void __free_pipe_info(struct pipe_inode_info *);
 void *generic_pipe_buf_map(struct pipe_inode_info *, struct pipe_buffer *, int);
 void generic_pipe_buf_unmap(struct pipe_inode_info *, struct pipe_buffer *, void *);
 void generic_pipe_buf_get(struct pipe_inode_info *, struct pipe_buffer *);
-int generic_pipe_buf_pin(struct pipe_inode_info *, struct pipe_buffer *);
+int generic_pipe_buf_confirm(struct pipe_inode_info *, struct pipe_buffer *);
 int generic_pipe_buf_steal(struct pipe_inode_info *, struct pipe_buffer *);
-/*
- * splice is tied to pipes as a transport (at least for now), so we'll just
- * add the splice flags here.
- */
-#define SPLICE_F_MOVE   (0x01)  /* move pages instead of copying */
-#define SPLICE_F_NONBLOCK (0x02) /* don't block on the pipe splicing (but */
-                                 /* we may still block on the fd we splice */
-                                 /* from/to, of course */
-#define SPLICE_F_MORE   (0x04)  /* expect more data */
-#define SPLICE_F_GIFT   (0x08)  /* pages passed in are a gift */
-/*
- * Passed to the actors
- */
-struct splice_desc {
-        unsigned int len, total_len;    /* current and remaining length */
-        unsigned int flags;             /* splice flags */
-        struct file *file;              /* file to read/write */
-        loff_t pos;                     /* file position */
-};
-typedef int (splice_actor)(struct pipe_inode_info *, struct pipe_buffer *,
-                           struct splice_desc *);
-extern ssize_t splice_from_pipe(struct pipe_inode_info *, struct file *,
-                                loff_t *, size_t, unsigned int,
-                                splice_actor *);
-extern ssize_t __splice_from_pipe(struct pipe_inode_info *, struct file *,
-                                  loff_t *, size_t, unsigned int,
-                                  splice_actor *);
 #endif
diff --git a/include/linux/pm.h b/include/linux/pm.h
index 87545e0f0b58..b2c4fde4e994 100644
--- a/include/linux/pm.h
+++ b/include/linux/pm.h
@@ -110,37 +110,67 @@ typedef int __bitwise suspend_state_t;
 #define PM_SUSPEND_MAX          ((__force suspend_state_t) 4)
 /**
- * struct pm_ops - Callbacks for managing platform dependent suspend states.
+ * struct pm_ops - Callbacks for managing platform dependent system sleep
- * @valid: Callback to determine whether the given state can be entered.
+ *      states.
- *      Valid states are advertised in /sys/power/state but can still
- *      be rejected by prepare or enter if the conditions aren't right.
- *      There is a %pm_valid_only_mem function available that can be assigned
- *      to this if you only implement mem sleep.
 *
- * @prepare: Prepare the platform for the given suspend state. Can return a
+ * @valid: Callback to determine if given system sleep state is supported by
- *      negative error code if necessary.
+ *      the platform.
+ *      Valid (ie. supported) states are advertised in /sys/power/state.  Note
+ *      that it still may be impossible to enter given system sleep state if the
+ *      conditions aren't right.
+ *      There is the %pm_valid_only_mem function available that can be assigned
+ *      to this if the platform only supports mem sleep.
 *
- * @enter: Enter the given suspend state, must be assigned. Can return a
+ * @set_target: Tell the platform which system sleep state is going to be
- *      negative error code if necessary.
+ *      entered.
+ *      @set_target() is executed right prior to suspending devices.  The
+ *      information conveyed to the platform code by @set_target() should be
+ *      disregarded by the platform as soon as @finish() is executed and if
+ *      @prepare() fails.  If @set_target() fails (ie. returns nonzero),
+ *      @prepare(), @enter() and @finish() will not be called by the PM core.
+ *      This callback is optional.  However, if it is implemented, the argument
+ *      passed to @prepare(), @enter() and @finish() is meaningless and should
+ *      be ignored.
 *
- * @finish: Called when the system has left the given state and all devices
+ * @prepare: Prepare the platform for entering the system sleep state indicated
- *      are resumed. The return value is ignored.
+ *      by @set_target() or represented by the argument if @set_target() is not
+ *      implemented.
+ *      @prepare() is called right after devices have been suspended (ie. the
+ *      appropriate .suspend() method has been executed for each device) and
+ *      before the nonboot CPUs are disabled (it is executed with IRQs enabled).
+ *      This callback is optional.  It returns 0 on success or a negative
+ *      error code otherwise, in which case the system cannot enter the desired
+ *      sleep state (@enter() and @finish() will not be called in that case).
+ *
+ * @enter: Enter the system sleep state indicated by @set_target() or
+ *      represented by the argument if @set_target() is not implemented.
+ *      This callback is mandatory.  It returns 0 on success or a negative
+ *      error code otherwise, in which case the system cannot enter the desired
+ *      sleep state.
+ *
+ * @finish: Called when the system has just left a sleep state, right after
+ *      the nonboot CPUs have been enabled and before devices are resumed (it is
+ *      executed with IRQs enabled).  If @set_target() is not implemented, the
+ *      argument represents the sleep state being left.
+ *      This callback is optional, but should be implemented by the platforms
+ *      that implement @prepare().  If implemented, it is always called after
+ *      @enter() (even if @enter() fails).
 */
 struct pm_ops {
        int (*valid)(suspend_state_t state);
+        int (*set_target)(suspend_state_t state);
        int (*prepare)(suspend_state_t state);
        int (*enter)(suspend_state_t state);
        int (*finish)(suspend_state_t state);
 };
+extern struct pm_ops *pm_ops;
 /**
 * pm_set_ops - set platform dependent power management ops
 * @pm_ops: The new power management operations to set.
 */
 extern void pm_set_ops(struct pm_ops *pm_ops);
-extern struct pm_ops *pm_ops;
-extern int pm_suspend(suspend_state_t state);
 extern int pm_valid_only_mem(suspend_state_t state);
 /**
@@ -161,6 +191,8 @@ extern void arch_suspend_disable_irqs(void);
 */
 extern void arch_suspend_enable_irqs(void);
+extern int pm_suspend(suspend_state_t state);
 /*
 * Device power management
 */
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
new file mode 100644
index 000000000000..606c0957997f
--- /dev/null
+++ b/include/linux/power_supply.h
@@ -0,0 +1,180 @@
+/*
+ *  Universal power supply monitor class
+ *
+ *  Copyright © 2007  Anton Vorontsov <cbou@mail.ru>
+ *  Copyright © 2004  Szabolcs Gyurko
+ *  Copyright © 2003  Ian Molton <spyro@f2s.com>
+ *
+ *  Modified: 2004, Oct     Szabolcs Gyurko
+ *
+ *  You may use this code as per GPL version 2
+ */
+#ifndef __LINUX_POWER_SUPPLY_H__
+#define __LINUX_POWER_SUPPLY_H__
+#include <linux/device.h>
+#include <linux/workqueue.h>
+#include <linux/leds.h>
+/*
+ * All voltages, currents, charges, energies, time and temperatures in uV,
+ * µA, µAh, µWh, seconds and tenths of degree Celsius unless otherwise
+ * stated. It's driver's job to convert its raw values to units in which
+ * this class operates.
+ */
+/*
+ * For systems where the charger determines the maximum battery capacity
+ * the min and max fields should be used to present these values to user
+ * space. Unused/unknown fields will not appear in sysfs.
+ */
+enum {
+        POWER_SUPPLY_STATUS_UNKNOWN = 0,
+        POWER_SUPPLY_STATUS_CHARGING,
+        POWER_SUPPLY_STATUS_DISCHARGING,
+        POWER_SUPPLY_STATUS_NOT_CHARGING,
+        POWER_SUPPLY_STATUS_FULL,
+};
+enum {
+        POWER_SUPPLY_HEALTH_UNKNOWN = 0,
+        POWER_SUPPLY_HEALTH_GOOD,
+        POWER_SUPPLY_HEALTH_OVERHEAT,
+        POWER_SUPPLY_HEALTH_DEAD,
+        POWER_SUPPLY_HEALTH_OVERVOLTAGE,
+        POWER_SUPPLY_HEALTH_UNSPEC_FAILURE,
+};
+enum {
+        POWER_SUPPLY_TECHNOLOGY_UNKNOWN = 0,
+        POWER_SUPPLY_TECHNOLOGY_NiMH,
+        POWER_SUPPLY_TECHNOLOGY_LION,
+        POWER_SUPPLY_TECHNOLOGY_LIPO,
+        POWER_SUPPLY_TECHNOLOGY_LiFe,
+        POWER_SUPPLY_TECHNOLOGY_NiCd,
+};
+enum {
+        POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN = 0,
+        POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL,
+        POWER_SUPPLY_CAPACITY_LEVEL_LOW,
+        POWER_SUPPLY_CAPACITY_LEVEL_NORMAL,
+        POWER_SUPPLY_CAPACITY_LEVEL_HIGH,
+        POWER_SUPPLY_CAPACITY_LEVEL_FULL,
+};
+enum power_supply_property {
+        /* Properties of type `int' */
+        POWER_SUPPLY_PROP_STATUS = 0,
+        POWER_SUPPLY_PROP_HEALTH,
+        POWER_SUPPLY_PROP_PRESENT,
+        POWER_SUPPLY_PROP_ONLINE,
+        POWER_SUPPLY_PROP_TECHNOLOGY,
+        POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+        POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+        POWER_SUPPLY_PROP_VOLTAGE_NOW,
+        POWER_SUPPLY_PROP_VOLTAGE_AVG,
+        POWER_SUPPLY_PROP_CURRENT_NOW,
+        POWER_SUPPLY_PROP_CURRENT_AVG,
+        POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
+        POWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN,
+        POWER_SUPPLY_PROP_CHARGE_FULL,
+        POWER_SUPPLY_PROP_CHARGE_EMPTY,
+        POWER_SUPPLY_PROP_CHARGE_NOW,
+        POWER_SUPPLY_PROP_CHARGE_AVG,
+        POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN,
+        POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN,
+        POWER_SUPPLY_PROP_ENERGY_FULL,
+        POWER_SUPPLY_PROP_ENERGY_EMPTY,
+        POWER_SUPPLY_PROP_ENERGY_NOW,
+        POWER_SUPPLY_PROP_ENERGY_AVG,
+        POWER_SUPPLY_PROP_CAPACITY, /* in percents! */
+        POWER_SUPPLY_PROP_CAPACITY_LEVEL,
+        POWER_SUPPLY_PROP_TEMP,
+        POWER_SUPPLY_PROP_TEMP_AMBIENT,
+        POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
+        POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
+        POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
+        POWER_SUPPLY_PROP_TIME_TO_FULL_AVG,
+        /* Properties of type `const char *' */
+        POWER_SUPPLY_PROP_MODEL_NAME,
+        POWER_SUPPLY_PROP_MANUFACTURER,
+};
+enum power_supply_type {
+        POWER_SUPPLY_TYPE_BATTERY = 0,
+        POWER_SUPPLY_TYPE_UPS,
+        POWER_SUPPLY_TYPE_MAINS,
+        POWER_SUPPLY_TYPE_USB,
+};
+union power_supply_propval {
+        int intval;
+        const char *strval;
+};
+struct power_supply {
+        const char *name;
+        enum power_supply_type type;
+        enum power_supply_property *properties;
+        size_t num_properties;
+        char **supplied_to;
+        size_t num_supplicants;
+        int (*get_property)(struct power_supply *psy,
+                            enum power_supply_property psp,
+                            union power_supply_propval *val);
+        void (*external_power_changed)(struct power_supply *psy);
+        /* For APM emulation, think legacy userspace. */
+        int use_for_apm;
+        /* private */
+        struct device *dev;
+        struct work_struct changed_work;
+#ifdef CONFIG_LEDS_TRIGGERS
+        struct led_trigger *charging_full_trig;
+        char *charging_full_trig_name;
+        struct led_trigger *charging_trig;
+        char *charging_trig_name;
+        struct led_trigger *full_trig;
+        char *full_trig_name;
+        struct led_trigger *online_trig;
+        char *online_trig_name;
+#endif
+};
+/*
+ * This is recommended structure to specify static power supply parameters.
+ * Generic one, parametrizable for different power supplies. Power supply
+ * class itself does not use it, but that's what implementing most platform
+ * drivers, should try reuse for consistency.
+ */
+struct power_supply_info {
+        const char *name;
+        int technology;
+        int voltage_max_design;
+        int voltage_min_design;
+        int charge_full_design;
+        int charge_empty_design;
+        int energy_full_design;
+        int energy_empty_design;
+        int use_for_apm;
+};
+extern void power_supply_changed(struct power_supply *psy);
+extern int power_supply_am_i_supplied(struct power_supply *psy);
+extern int power_supply_register(struct device *parent,
+                                 struct power_supply *psy);
+extern void power_supply_unregister(struct power_supply *psy);
+/* For APM emulation, think legacy userspace. */
+extern struct class *power_supply_class;
+#endif /* __LINUX_POWER_SUPPLY_H__ */
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 693f0e6c54d4..cfb680585ab8 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -34,6 +34,8 @@
 #define SCHED_FIFO              1
 #define SCHED_RR                2
 #define SCHED_BATCH             3
+/* SCHED_ISO: reserved but not implemented yet */
+#define SCHED_IDLE              5
 #ifdef __KERNEL__
@@ -130,6 +132,26 @@ extern unsigned long nr_active(void);
 extern unsigned long nr_iowait(void);
 extern unsigned long weighted_cpuload(const int cpu);
+struct seq_file;
+struct cfs_rq;
+#ifdef CONFIG_SCHED_DEBUG
+extern void proc_sched_show_task(struct task_struct *p, struct seq_file *m);
+extern void proc_sched_set_task(struct task_struct *p);
+extern void
+print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq, u64 now);
+#else
+static inline void
+proc_sched_show_task(struct task_struct *p, struct seq_file *m)
+{
+}
+static inline void proc_sched_set_task(struct task_struct *p)
+{
+}
+static inline void
+print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq, u64 now)
+{
+}
+#endif
 /*
 * Task state bitmask. NOTE! These bits are also
@@ -193,6 +215,7 @@ struct task_struct;
 extern void sched_init(void);
 extern void sched_init_smp(void);
 extern void init_idle(struct task_struct *idle, int cpu);
+extern void init_idle_bootup_task(struct task_struct *idle);
 extern cpumask_t nohz_cpu_mask;
 #if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ)
@@ -479,7 +502,7 @@ struct signal_struct {
         * from jiffies_to_ns(utime + stime) if sched_clock uses something
         * other than jiffies.)
         */
-        unsigned long long sched_time;
+        unsigned long long sum_sched_runtime;
        /*
         * We don't bother to synchronize most readers of this at all,
@@ -521,31 +544,6 @@ struct signal_struct {
 #define SIGNAL_STOP_CONTINUED   0x00000004 /* SIGCONT since WCONTINUED reap */
 #define SIGNAL_GROUP_EXIT       0x00000008 /* group exit in progress */
-/*
- * Priority of a process goes from 0..MAX_PRIO-1, valid RT
- * priority is 0..MAX_RT_PRIO-1, and SCHED_NORMAL/SCHED_BATCH
- * tasks are in the range MAX_RT_PRIO..MAX_PRIO-1. Priority
- * values are inverted: lower p->prio value means higher priority.
- *
- * The MAX_USER_RT_PRIO value allows the actual maximum
- * RT priority to be separate from the value exported to
- * user-space.  This allows kernel threads to set their
- * priority to a value higher than any user task. Note:
- * MAX_RT_PRIO must not be smaller than MAX_USER_RT_PRIO.
- */
-#define MAX_USER_RT_PRIO        100
-#define MAX_RT_PRIO             MAX_USER_RT_PRIO
-#define MAX_PRIO                (MAX_RT_PRIO + 40)
-#define rt_prio(prio)           unlikely((prio) < MAX_RT_PRIO)
-#define rt_task(p)              rt_prio((p)->prio)
-#define batch_task(p)           (unlikely((p)->policy == SCHED_BATCH))
-#define is_rt_policy(p)         ((p) != SCHED_NORMAL && (p) != SCHED_BATCH)
-#define has_rt_policy(p)        unlikely(is_rt_policy((p)->policy))
 /*
 * Some day this will be a full-fledged user tracking system..
 */
@@ -583,13 +581,13 @@ struct reclaim_state;
 #if defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT)
 struct sched_info {
        /* cumulative counters */
-        unsigned long   cpu_time,       /* time spent on the cpu */
+        unsigned long pcnt;           /* # of times run on this cpu */
-                        run_delay,      /* time spent waiting on a runqueue */
+        unsigned long long cpu_time,  /* time spent on the cpu */
-                        pcnt;           /* # of timeslices run on this cpu */
+                           run_delay; /* time spent waiting on a runqueue */
        /* timestamps */
-        unsigned long   last_arrival,   /* when we last ran on a cpu */
+        unsigned long long last_arrival,/* when we last ran on a cpu */
-                        last_queued;    /* when we were last queued to run */
+                           last_queued; /* when we were last queued to run */
 };
 #endif /* defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT) */
@@ -639,18 +637,24 @@ static inline int sched_info_on(void)
 #endif
 }
-enum idle_type
+enum cpu_idle_type {
-{
+        CPU_IDLE,
-        SCHED_IDLE,
+        CPU_NOT_IDLE,
-        NOT_IDLE,
+        CPU_NEWLY_IDLE,
-        NEWLY_IDLE,
+        CPU_MAX_IDLE_TYPES
-        MAX_IDLE_TYPES
 };
 /*
 * sched-domains (multiprocessor balancing) declarations:
 */
-#define SCHED_LOAD_SCALE        128UL   /* increase resolution of load */
+/*
+ * Increase resolution of nice-level calculations:
+ */
+#define SCHED_LOAD_SHIFT        10
+#define SCHED_LOAD_SCALE        (1L << SCHED_LOAD_SHIFT)
+#define SCHED_LOAD_SCALE_FUZZ   (SCHED_LOAD_SCALE >> 5)
 #ifdef CONFIG_SMP
 #define SD_LOAD_BALANCE         1       /* Do load balancing on this domain. */
@@ -719,14 +723,14 @@ struct sched_domain {
 #ifdef CONFIG_SCHEDSTATS
        /* load_balance() stats */
-        unsigned long lb_cnt[MAX_IDLE_TYPES];
+        unsigned long lb_cnt[CPU_MAX_IDLE_TYPES];
-        unsigned long lb_failed[MAX_IDLE_TYPES];
+        unsigned long lb_failed[CPU_MAX_IDLE_TYPES];
-        unsigned long lb_balanced[MAX_IDLE_TYPES];
+        unsigned long lb_balanced[CPU_MAX_IDLE_TYPES];
-        unsigned long lb_imbalance[MAX_IDLE_TYPES];
+        unsigned long lb_imbalance[CPU_MAX_IDLE_TYPES];
-        unsigned long lb_gained[MAX_IDLE_TYPES];
+        unsigned long lb_gained[CPU_MAX_IDLE_TYPES];
-        unsigned long lb_hot_gained[MAX_IDLE_TYPES];
+        unsigned long lb_hot_gained[CPU_MAX_IDLE_TYPES];
-        unsigned long lb_nobusyg[MAX_IDLE_TYPES];
+        unsigned long lb_nobusyg[CPU_MAX_IDLE_TYPES];
-        unsigned long lb_nobusyq[MAX_IDLE_TYPES];
+        unsigned long lb_nobusyq[CPU_MAX_IDLE_TYPES];
        /* Active load balancing */
        unsigned long alb_cnt;
@@ -753,12 +757,6 @@ struct sched_domain {
 extern int partition_sched_domains(cpumask_t *partition1,
                                    cpumask_t *partition2);
-/*
- * Maximum cache size the migration-costs auto-tuning code will
- * search from:
- */
-extern unsigned int max_cache_size;
 #endif  /* CONFIG_SMP */
@@ -809,14 +807,86 @@ struct mempolicy;
 struct pipe_inode_info;
 struct uts_namespace;
-enum sleep_type {
+struct rq;
-        SLEEP_NORMAL,
+struct sched_domain;
-        SLEEP_NONINTERACTIVE,
-        SLEEP_INTERACTIVE,
+struct sched_class {
-        SLEEP_INTERRUPTED,
+        struct sched_class *next;
+        void (*enqueue_task) (struct rq *rq, struct task_struct *p,
+                              int wakeup, u64 now);
+        void (*dequeue_task) (struct rq *rq, struct task_struct *p,
+                              int sleep, u64 now);
+        void (*yield_task) (struct rq *rq, struct task_struct *p);
+        void (*check_preempt_curr) (struct rq *rq, struct task_struct *p);
+        struct task_struct * (*pick_next_task) (struct rq *rq, u64 now);
+        void (*put_prev_task) (struct rq *rq, struct task_struct *p, u64 now);
+        int (*load_balance) (struct rq *this_rq, int this_cpu,
+                        struct rq *busiest,
+                        unsigned long max_nr_move, unsigned long max_load_move,
+                        struct sched_domain *sd, enum cpu_idle_type idle,
+                        int *all_pinned, unsigned long *total_load_moved);
+        void (*set_curr_task) (struct rq *rq);
+        void (*task_tick) (struct rq *rq, struct task_struct *p);
+        void (*task_new) (struct rq *rq, struct task_struct *p);
 };
-struct prio_array;
+struct load_weight {
+        unsigned long weight, inv_weight;
+};
+/*
+ * CFS stats for a schedulable entity (task, task-group etc)
+ *
+ * Current field usage histogram:
+ *
+ *     4 se->block_start
+ *     4 se->run_node
+ *     4 se->sleep_start
+ *     4 se->sleep_start_fair
+ *     6 se->load.weight
+ *     7 se->delta_fair
+ *    15 se->wait_runtime
+ */
+struct sched_entity {
+        long                    wait_runtime;
+        unsigned long           delta_fair_run;
+        unsigned long           delta_fair_sleep;
+        unsigned long           delta_exec;
+        s64                     fair_key;
+        struct load_weight      load;           /* for load-balancing */
+        struct rb_node          run_node;
+        unsigned int            on_rq;
+        u64                     wait_start_fair;
+        u64                     wait_start;
+        u64                     exec_start;
+        u64                     sleep_start;
+        u64                     sleep_start_fair;
+        u64                     block_start;
+        u64                     sleep_max;
+        u64                     block_max;
+        u64                     exec_max;
+        u64                     wait_max;
+        u64                     last_ran;
+        u64                     sum_exec_runtime;
+        s64                     sum_wait_runtime;
+        s64                     sum_sleep_runtime;
+        unsigned long           wait_runtime_overruns;
+        unsigned long           wait_runtime_underruns;
+#ifdef CONFIG_FAIR_GROUP_SCHED
+        struct sched_entity     *parent;
+        /* rq on which this entity is (to be) queued: */
+        struct cfs_rq           *cfs_rq;
+        /* rq "owned" by this entity/group: */
+        struct cfs_rq           *my_q;
+#endif
+};
 struct task_struct {
        volatile long state;    /* -1 unrunnable, 0 runnable, >0 stopped */
@@ -832,23 +902,20 @@ struct task_struct {
        int oncpu;
 #endif
 #endif
-        int load_weight;        /* for niceness load balancing purposes */
        int prio, static_prio, normal_prio;
        struct list_head run_list;
-        struct prio_array *array;
+        struct sched_class *sched_class;
+        struct sched_entity se;
        unsigned short ioprio;
 #ifdef CONFIG_BLK_DEV_IO_TRACE
        unsigned int btrace_seq;
 #endif
-        unsigned long sleep_avg;
-        unsigned long long timestamp, last_ran;
-        unsigned long long sched_time; /* sched_clock time spent running */
-        enum sleep_type sleep_type;
        unsigned int policy;
        cpumask_t cpus_allowed;
-        unsigned int time_slice, first_time_slice;
+        unsigned int time_slice;
 #if defined(CONFIG_SCHEDSTATS) || defined(CONFIG_TASK_DELAY_ACCT)
        struct sched_info sched_info;
@@ -1078,6 +1145,37 @@ struct task_struct {
 #endif
 };
+/*
+ * Priority of a process goes from 0..MAX_PRIO-1, valid RT
+ * priority is 0..MAX_RT_PRIO-1, and SCHED_NORMAL/SCHED_BATCH
+ * tasks are in the range MAX_RT_PRIO..MAX_PRIO-1. Priority
+ * values are inverted: lower p->prio value means higher priority.
+ *
+ * The MAX_USER_RT_PRIO value allows the actual maximum
+ * RT priority to be separate from the value exported to
+ * user-space.  This allows kernel threads to set their
+ * priority to a value higher than any user task. Note:
+ * MAX_RT_PRIO must not be smaller than MAX_USER_RT_PRIO.
+ */
+#define MAX_USER_RT_PRIO        100
+#define MAX_RT_PRIO             MAX_USER_RT_PRIO
+#define MAX_PRIO                (MAX_RT_PRIO + 40)
+#define DEFAULT_PRIO            (MAX_RT_PRIO + 20)
+static inline int rt_prio(int prio)
+{
+        if (unlikely(prio < MAX_RT_PRIO))
+                return 1;
+        return 0;
+}
+static inline int rt_task(struct task_struct *p)
+{
+        return rt_prio(p->prio);
+}
 static inline pid_t process_group(struct task_struct *tsk)
 {
        return tsk->signal->pgrp;
@@ -1223,7 +1321,7 @@ static inline int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask)
 extern unsigned long long sched_clock(void);
 extern unsigned long long
-current_sched_time(const struct task_struct *current_task);
+task_sched_runtime(struct task_struct *task);
 /* sched_exec is called by processes performing an exec */
 #ifdef CONFIG_SMP
@@ -1232,6 +1330,8 @@ extern void sched_exec(void);
 #define sched_exec()   {}
 #endif
+extern void sched_clock_unstable_event(void);
 #ifdef CONFIG_HOTPLUG_CPU
 extern void idle_task_exit(void);
 #else
@@ -1240,6 +1340,14 @@ static inline void idle_task_exit(void) {}
 extern void sched_idle_next(void);
+extern unsigned int sysctl_sched_granularity;
+extern unsigned int sysctl_sched_wakeup_granularity;
+extern unsigned int sysctl_sched_batch_wakeup_granularity;
+extern unsigned int sysctl_sched_stat_granularity;
+extern unsigned int sysctl_sched_runtime_limit;
+extern unsigned int sysctl_sched_child_runs_first;
+extern unsigned int sysctl_sched_features;
 #ifdef CONFIG_RT_MUTEXES
 extern int rt_mutex_getprio(struct task_struct *p);
 extern void rt_mutex_setprio(struct task_struct *p, int prio);
@@ -1317,8 +1425,8 @@ extern void FASTCALL(wake_up_new_task(struct task_struct * tsk,
 #else
 static inline void kick_process(struct task_struct *tsk) { }
 #endif
-extern void FASTCALL(sched_fork(struct task_struct * p, int clone_flags));
+extern void sched_fork(struct task_struct *p, int clone_flags);
-extern void FASTCALL(sched_exit(struct task_struct * p));
+extern void sched_dead(struct task_struct *p);
 extern int in_group_p(gid_t);
 extern int in_egroup_p(gid_t);
@@ -1406,7 +1514,7 @@ extern struct mm_struct * mm_alloc(void);
 extern void FASTCALL(__mmdrop(struct mm_struct *));
 static inline void mmdrop(struct mm_struct * mm)
 {
-        if (atomic_dec_and_test(&mm->mm_count))
+        if (unlikely(atomic_dec_and_test(&mm->mm_count)))
                __mmdrop(mm);
 }
@@ -1638,10 +1746,7 @@ static inline unsigned int task_cpu(const struct task_struct *p)
        return task_thread_info(p)->cpu;
 }
-static inline void set_task_cpu(struct task_struct *p, unsigned int cpu)
+extern void set_task_cpu(struct task_struct *p, unsigned int cpu);
-{
-        task_thread_info(p)->cpu = cpu;
-}
 #else
diff --git a/include/linux/seq_file.h b/include/linux/seq_file.h
index 3e3cccbb1cac..83783ab0f552 100644
--- a/include/linux/seq_file.h
+++ b/include/linux/seq_file.h
@@ -50,5 +50,16 @@ int seq_release_private(struct inode *, struct file *);
 #define SEQ_START_TOKEN ((void *)1)
+/*
+ * Helpers for iteration over list_head-s in seq_files
+ */
+extern struct list_head *seq_list_start(struct list_head *head,
+                loff_t pos);
+extern struct list_head *seq_list_start_head(struct list_head *head,
+                loff_t pos);
+extern struct list_head *seq_list_next(void *v, struct list_head *head,
+                loff_t *ppos);
 #endif
 #endif
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index e7367c74e1bb..6f0b2f7d0010 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -1579,6 +1579,10 @@ static inline ktime_t net_timedelta(ktime_t t)
        return ktime_sub(ktime_get_real(), t);
 }
+static inline ktime_t net_invalid_timestamp(void)
+{
+        return ktime_set(0, 0);
+}
 extern __sum16 __skb_checksum_complete_head(struct sk_buff *skb, int len);
 extern __sum16 __skb_checksum_complete(struct sk_buff *skb);
diff --git a/include/linux/slab.h b/include/linux/slab.h
index a015236cc572..cebcd3833c76 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -82,8 +82,8 @@ static inline void *kmem_cache_alloc_node(struct kmem_cache *cachep,
 * to do various tricks to work around compiler limitations in order to
 * ensure proper constant folding.
 */
-#define KMALLOC_SHIFT_HIGH      ((MAX_ORDER + PAGE_SHIFT) <= 25 ? \
+#define KMALLOC_SHIFT_HIGH      ((MAX_ORDER + PAGE_SHIFT - 1) <= 25 ? \
-                                (MAX_ORDER + PAGE_SHIFT) : 25)
+                                (MAX_ORDER + PAGE_SHIFT - 1) : 25)
 #define KMALLOC_MAX_SIZE        (1UL << KMALLOC_SHIFT_HIGH)
 #define KMALLOC_MAX_ORDER       (KMALLOC_SHIFT_HIGH - PAGE_SHIFT)
diff --git a/include/linux/slub_def.h b/include/linux/slub_def.h
index a0ad37463d62..6207a3d8da71 100644
--- a/include/linux/slub_def.h
+++ b/include/linux/slub_def.h
@@ -28,7 +28,7 @@ struct kmem_cache {
        int size;               /* The size of an object including meta data */
        int objsize;            /* The size of an object without meta data */
        int offset;             /* Free pointer offset. */
-        unsigned int order;
+        int order;
        /*
         * Avoid an extra cache line for UP, SMP and for the node local to
@@ -56,7 +56,13 @@ struct kmem_cache {
 /*
 * Kmalloc subsystem.
 */
-#define KMALLOC_SHIFT_LOW 3
+#if defined(ARCH_KMALLOC_MINALIGN) && ARCH_KMALLOC_MINALIGN > 8
+#define KMALLOC_MIN_SIZE ARCH_KMALLOC_MINALIGN
+#else
+#define KMALLOC_MIN_SIZE 8
+#endif
+#define KMALLOC_SHIFT_LOW ilog2(KMALLOC_MIN_SIZE)
 /*
 * We keep the general caches in an array of slab caches that are used for
@@ -76,6 +82,9 @@ static inline int kmalloc_index(size_t size)
        if (size > KMALLOC_MAX_SIZE)
                return -1;
+        if (size <= KMALLOC_MIN_SIZE)
+                return KMALLOC_SHIFT_LOW;
        if (size > 64 && size <= 96)
                return 1;
        if (size > 128 && size <= 192)
diff --git a/include/linux/sm501-regs.h b/include/linux/sm501-regs.h
index cc9be4a11861..014e73b31fc0 100644
--- a/include/linux/sm501-regs.h
+++ b/include/linux/sm501-regs.h
@@ -64,6 +64,11 @@
 #define SM501_DEBUG_CONTROL             (0x000034)
 /* power management */
+#define SM501_POWERMODE_P2X_SRC         (1<<29)
+#define SM501_POWERMODE_V2X_SRC         (1<<20)
+#define SM501_POWERMODE_M_SRC           (1<<12)
+#define SM501_POWERMODE_M1_SRC          (1<<4)
 #define SM501_CURRENT_GATE              (0x000038)
 #define SM501_CURRENT_CLOCK             (0x00003C)
 #define SM501_POWER_MODE_0_GATE         (0x000040)
@@ -104,6 +109,9 @@
 #define SM501_DEVICEID                  (0x000060)
 /* 0x050100A0 */
+#define SM501_DEVICEID_SM501            (0x05010000)
+#define SM501_DEVICEID_IDMASK           (0xffff0000)
 #define SM501_PLLCLOCK_COUNT            (0x000064)
 #define SM501_MISC_TIMING               (0x000068)
 #define SM501_CURRENT_SDRAM_CLOCK       (0x00006C)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index b6bedc3ee95c..1be5ea059477 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -341,9 +341,14 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
 * chip transactions together.
 *
 * (ii) When the transfer is the last one in the message, the chip may
- * stay selected until the next transfer.  This is purely a performance
+ * stay selected until the next transfer.  On multi-device SPI busses
- * hint; the controller driver may need to select a different device
+ * with nothing blocking messages going to other devices, this is just
- * for the next message.
+ * a performance hint; starting a message to another device deselects
+ * this one.  But in other cases, this can be used to ensure correctness.
+ * Some devices need protocol transactions to be built from a series of
+ * spi_message submissions, where the content of one message is determined
+ * by the results of previous messages and where the whole transaction
+ * ends when the chipselect goes intactive.
 *
 * The code that submits an spi_message (and its spi_transfers)
 * to the lower layers is responsible for managing its memory.
@@ -480,14 +485,15 @@ static inline void spi_message_free(struct spi_message *m)
 /**
 * spi_setup - setup SPI mode and clock rate
 * @spi: the device whose settings are being modified
- * Context: can sleep
+ * Context: can sleep, and no requests are queued to the device
 *
 * SPI protocol drivers may need to update the transfer mode if the
- * device doesn't work with the mode 0 default.  They may likewise need
+ * device doesn't work with its default.  They may likewise need
 * to update clock rates or word sizes from initial values.  This function
 * changes those settings, and must be called from a context that can sleep.
- * The changes take effect the next time the device is selected and data
+ * Except for SPI_CS_HIGH, which takes effect immediately, the changes take
- * is transferred to or from it.
+ * effect the next time the device is selected and data is transferred to
+ * or from it.  When this function returns, the spi device is deselected.
 *
 * Note that this call will fail if the protocol driver specifies an option
 * that the underlying controller or its driver does not support.  For
diff --git a/include/linux/splice.h b/include/linux/splice.h
new file mode 100644
index 000000000000..33e447f98a54
--- /dev/null
+++ b/include/linux/splice.h
@@ -0,0 +1,73 @@
+/*
+ * Function declerations and data structures related to the splice
+ * implementation.
+ *
+ * Copyright (C) 2007 Jens Axboe <jens.axboe@oracle.com>
+ *
+ */
+#ifndef SPLICE_H
+#define SPLICE_H
+#include <linux/pipe_fs_i.h>
+/*
+ * splice is tied to pipes as a transport (at least for now), so we'll just
+ * add the splice flags here.
+ */
+#define SPLICE_F_MOVE   (0x01)  /* move pages instead of copying */
+#define SPLICE_F_NONBLOCK (0x02) /* don't block on the pipe splicing (but */
+                                 /* we may still block on the fd we splice */
+                                 /* from/to, of course */
+#define SPLICE_F_MORE   (0x04)  /* expect more data */
+#define SPLICE_F_GIFT   (0x08)  /* pages passed in are a gift */
+/*
+ * Passed to the actors
+ */
+struct splice_desc {
+        unsigned int len, total_len;    /* current and remaining length */
+        unsigned int flags;             /* splice flags */
+        /*
+         * actor() private data
+         */
+        union {
+                void __user *userptr;   /* memory to write to */
+                struct file *file;      /* file to read/write */
+                void *data;             /* cookie */
+        } u;
+        loff_t pos;                     /* file position */
+};
+struct partial_page {
+        unsigned int offset;
+        unsigned int len;
+        unsigned long private;
+};
+/*
+ * Passed to splice_to_pipe
+ */
+struct splice_pipe_desc {
+        struct page **pages;            /* page map */
+        struct partial_page *partial;   /* pages[] may not be contig */
+        int nr_pages;                   /* number of pages in map */
+        unsigned int flags;             /* splice flags */
+        const struct pipe_buf_operations *ops;/* ops associated with output pipe */
+};
+typedef int (splice_actor)(struct pipe_inode_info *, struct pipe_buffer *,
+                           struct splice_desc *);
+typedef int (splice_direct_actor)(struct pipe_inode_info *,
+                                  struct splice_desc *);
+extern ssize_t splice_from_pipe(struct pipe_inode_info *, struct file *,
+                                loff_t *, size_t, unsigned int,
+                                splice_actor *);
+extern ssize_t __splice_from_pipe(struct pipe_inode_info *,
+                                  struct splice_desc *, splice_actor *);
+extern ssize_t splice_to_pipe(struct pipe_inode_info *,
+                              struct splice_pipe_desc *);
+extern ssize_t splice_direct_to_actor(struct file *, struct splice_desc *,
+                                      splice_direct_actor *);
+#endif
diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h
index 4a7ae8ab6eb8..129d50f2225c 100644
--- a/include/linux/sunrpc/svc.h
+++ b/include/linux/sunrpc/svc.h
@@ -253,7 +253,7 @@ struct svc_rqst {
                                                 * determine what device number
                                                 * to report (real or virtual)
                                                 */
-        int                     rq_sendfile_ok; /* turned off in gss privacy
+        int                     rq_splice_ok;   /* turned off in gss privacy
                                                 * to prevent encrypting page
                                                 * cache pages */
        wait_queue_head_t       rq_wait;        /* synchronization */
diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h
index b02070eac422..83d0ec11235e 100644
--- a/include/linux/syscalls.h
+++ b/include/linux/syscalls.h
@@ -598,6 +598,8 @@ asmlinkage long sys_tee(int fdin, int fdout, size_t len, unsigned int flags);
 asmlinkage long sys_sync_file_range(int fd, loff_t offset, loff_t nbytes,
                                        unsigned int flags);
+asmlinkage long sys_sync_file_range2(int fd, unsigned int flags,
+                                     loff_t offset, loff_t nbytes);
 asmlinkage long sys_get_robust_list(int pid,
                                    struct robust_list_head __user * __user *head_ptr,
                                    size_t __user *len_ptr);
diff --git a/include/linux/topology.h b/include/linux/topology.h
index a9d1f049cc15..da6c39b2d051 100644
--- a/include/linux/topology.h
+++ b/include/linux/topology.h
@@ -98,7 +98,7 @@
        .cache_nice_tries       = 0,                    \
        .busy_idx               = 0,                    \
        .idle_idx               = 0,                    \
-        .newidle_idx            = 1,                    \
+        .newidle_idx            = 0,                    \
        .wake_idx               = 0,                    \
        .forkexec_idx           = 0,                    \
        .flags                  = SD_LOAD_BALANCE       \
@@ -128,14 +128,15 @@
        .imbalance_pct          = 125,                  \
        .cache_nice_tries       = 1,                    \
        .busy_idx               = 2,                    \
-        .idle_idx               = 1,                    \
+        .idle_idx               = 0,                    \
-        .newidle_idx            = 2,                    \
+        .newidle_idx            = 0,                    \
        .wake_idx               = 1,                    \
        .forkexec_idx           = 1,                    \
        .flags                  = SD_LOAD_BALANCE       \
                                | SD_BALANCE_NEWIDLE    \
                                | SD_BALANCE_EXEC       \
                                | SD_WAKE_AFFINE        \
+                                | SD_WAKE_IDLE          \
                                | SD_SHARE_PKG_RESOURCES\
                                | BALANCE_FOR_MC_POWER, \
        .last_balance           = jiffies,              \
@@ -158,14 +159,15 @@
        .imbalance_pct          = 125,                  \
        .cache_nice_tries       = 1,                    \
        .busy_idx               = 2,                    \
-        .idle_idx               = 1,                    \
+        .idle_idx               = 0,                    \
-        .newidle_idx            = 2,                    \
+        .newidle_idx            = 0,                    \
        .wake_idx               = 1,                    \
        .forkexec_idx           = 1,                    \
        .flags                  = SD_LOAD_BALANCE       \
                                | SD_BALANCE_NEWIDLE    \
                                | SD_BALANCE_EXEC       \
                                | SD_WAKE_AFFINE        \
+                                | SD_WAKE_IDLE          \
                                | BALANCE_FOR_PKG_POWER,\
        .last_balance           = jiffies,              \
        .balance_interval       = 1,                    \
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 94bd38a6d947..56aa2ee21f1b 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -729,6 +729,22 @@ static inline int usb_endpoint_is_isoc_out(const struct usb_endpoint_descriptor
        .bcdDevice_lo = (lo), .bcdDevice_hi = (hi)
 /**
+ * USB_DEVICE_INTERFACE_PROTOCOL - macro used to describe a usb
+ *              device with a specific interface protocol
+ * @vend: the 16 bit USB Vendor ID
+ * @prod: the 16 bit USB Product ID
+ * @pr: bInterfaceProtocol value
+ *
+ * This macro is used to create a struct usb_device_id that matches a
+ * specific interface protocol of devices.
+ */
+#define USB_DEVICE_INTERFACE_PROTOCOL(vend,prod,pr) \
+        .match_flags = USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_INT_PROTOCOL, \
+        .idVendor = (vend), \
+        .idProduct = (prod), \
+        .bInterfaceProtocol = (pr)
+/**
 * USB_DEVICE_INFO - macro used to describe a class of usb devices
 * @cl: bDeviceClass value
 * @sc: bDeviceSubClass value
diff --git a/include/linux/wait.h b/include/linux/wait.h
index e820d00e1383..0e686280450b 100644
--- a/include/linux/wait.h
+++ b/include/linux/wait.h
@@ -366,15 +366,15 @@ static inline void remove_wait_queue_locked(wait_queue_head_t *q,
 /*
 * These are the old interfaces to sleep waiting for an event.
- * They are racy.  DO NOT use them, use the wait_event* interfaces above.  
+ * They are racy.  DO NOT use them, use the wait_event* interfaces above.
- * We plan to remove these interfaces during 2.7.
+ * We plan to remove these interfaces.
 */
-extern void FASTCALL(sleep_on(wait_queue_head_t *q));
+extern void sleep_on(wait_queue_head_t *q);
-extern long FASTCALL(sleep_on_timeout(wait_queue_head_t *q,
+extern long sleep_on_timeout(wait_queue_head_t *q,
-                                      signed long timeout));
+                                      signed long timeout);
-extern void FASTCALL(interruptible_sleep_on(wait_queue_head_t *q));
+extern void interruptible_sleep_on(wait_queue_head_t *q);
-extern long FASTCALL(interruptible_sleep_on_timeout(wait_queue_head_t *q,
+extern long interruptible_sleep_on_timeout(wait_queue_head_t *q,
-                                                    signed long timeout));
+                                           signed long timeout);
 /*
 * Waitqueues which are removed from the waitqueue_head at wakeup time
diff --git a/include/net/ax88796.h b/include/net/ax88796.h
new file mode 100644
index 000000000000..ee786a043b3d
--- /dev/null
+++ b/include/net/ax88796.h
@@ -0,0 +1,27 @@
+/* include/net/ax88796.h
+ *
+ * Copyright 2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#ifndef __NET_AX88796_PLAT_H
+#define __NET_AX88796_PLAT_H
+#define AXFLG_HAS_EEPROM                (1<<0)
+#define AXFLG_MAC_FROMDEV               (1<<1)  /* device already has MAC */
+struct ax_plat_data {
+        unsigned int     flags;
+        unsigned char    wordlength;            /* 1 or 2 */
+        unsigned char    dcr_val;               /* default value for DCR */
+        unsigned char    rcr_val;               /* default value for RCR */
+        unsigned char    gpoc_val;              /* default value for GPOC */
+        u32             *reg_offsets;           /* register offsets */
+};
+#endif /* __NET_AX88796_PLAT_H */
diff --git a/include/net/irda/irlap.h b/include/net/irda/irlap.h
index f0248fb8e196..a3d370efb903 100644
--- a/include/net/irda/irlap.h
+++ b/include/net/irda/irlap.h
@@ -289,4 +289,21 @@ static inline void irlap_clear_disconnect(struct irlap_cb *self)
        self->disconnect_pending = FALSE;
 }
+/*
+ * Function irlap_next_state (self, state)
+ *
+ *    Switches state and provides debug information
+ *
+ */
+static inline void irlap_next_state(struct irlap_cb *self, IRLAP_STATE state)
+{
+        /*
+        if (!self || self->magic != LAP_MAGIC)
+                return;
+        IRDA_DEBUG(4, "next LAP state = %s\n", irlap_state[state]);
+        */
+        self->state = state;
+}
 #endif
diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h
index dda72bf5b9b4..16baef4dab7e 100644
--- a/include/net/sctp/sctp.h
+++ b/include/net/sctp/sctp.h
@@ -503,6 +503,13 @@ static inline int sctp_frag_point(const struct sctp_sock *sp, int pmtu)
        return frag;
 }
+static inline void sctp_assoc_pending_pmtu(struct sctp_association *asoc)
+{
+        sctp_assoc_sync_pmtu(asoc);
+        asoc->pmtu_pending = 0;
+}
 /* Walk through a list of TLV parameters.  Don't trust the
 * individual parameter lengths and instead depend on
 * the chunk length to indicate when to stop.  Make sure
diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h
index 5e81984b8478..ee4559b11302 100644
--- a/include/net/sctp/structs.h
+++ b/include/net/sctp/structs.h
@@ -912,6 +912,9 @@ struct sctp_transport {
         */
        __u16 pathmaxrxt;
+        /* is the Path MTU update pending on this tranport */
+        __u8 pmtu_pending;
        /* PMTU       : The current known path MTU.  */
        __u32 pathmtu;
@@ -1006,6 +1009,7 @@ void sctp_transport_raise_cwnd(struct sctp_transport *, __u32, __u32);
 void sctp_transport_lower_cwnd(struct sctp_transport *, sctp_lower_cwnd_t);
 unsigned long sctp_transport_timeout(struct sctp_transport *);
 void sctp_transport_reset(struct sctp_transport *);
+void sctp_transport_update_pmtu(struct sctp_transport *, u32);
 /* This is the structure we use to queue packets as they come into
@@ -1565,6 +1569,9 @@ struct sctp_association {
         */
        __u16 pathmaxrxt;
+        /* Flag that path mtu update is pending */
+        __u8   pmtu_pending;
        /* Association : The smallest PMTU discovered for all of the
         * PMTU        : peer's transport addresses.
         */
diff --git a/include/pcmcia/ciscode.h b/include/pcmcia/ciscode.h
index eae7e2e84497..ad6e278ba7f2 100644
--- a/include/pcmcia/ciscode.h
+++ b/include/pcmcia/ciscode.h
@@ -126,4 +126,6 @@
 #define MANFID_POSSIO                   0x030c
 #define PRODID_POSSIO_GCC               0x0003
+#define MANFID_NEC                      0x0010
 #endif /* _LINUX_CISCODE_H */