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-rw-r--r--include/asm-mips/pgtable-32.h4
-rw-r--r--include/asm-mips/pgtable-bits.h6
-rw-r--r--include/asm-mips/pgtable.h6
3 files changed, 8 insertions, 8 deletions
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index ceefe027c761..4396e9ffd418 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -107,7 +107,7 @@ static inline void pmd_clear(pmd_t *pmdp)
107 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 107 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
108} 108}
109 109
110#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 110#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
111#define pte_page(x) pfn_to_page(pte_pfn(x)) 111#define pte_page(x) pfn_to_page(pte_pfn(x))
112#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) 112#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
113static inline pte_t 113static inline pte_t
@@ -130,7 +130,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
130#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) 130#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
131#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 131#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
132#endif 132#endif
133#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) */ 133#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
134 134
135#define __pgd_offset(address) pgd_index(address) 135#define __pgd_offset(address) pgd_index(address)
136#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 136#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 7494ba91112a..d23f19a3240a 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -32,7 +32,7 @@
32 * unpredictable things. The code (when it is written) to deal with 32 * unpredictable things. The code (when it is written) to deal with
33 * this problem will be in the update_mmu_cache() code for the r4k. 33 * this problem will be in the update_mmu_cache() code for the r4k.
34 */ 34 */
35#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) 35#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
36 36
37#define _PAGE_PRESENT (1<<6) /* implemented in software */ 37#define _PAGE_PRESENT (1<<6) /* implemented in software */
38#define _PAGE_READ (1<<7) /* implemented in software */ 38#define _PAGE_READ (1<<7) /* implemented in software */
@@ -122,7 +122,7 @@
122 122
123#endif 123#endif
124#endif 124#endif
125#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */ 125#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
126 126
127#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 127#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
128#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 128#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -139,7 +139,7 @@
139#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW 139#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
140#endif 140#endif
141 141
142#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) 142#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
143#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3) 143#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
144#else 144#else
145#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) 145#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 17a7703a2969..009b7b14231f 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -79,7 +79,7 @@ extern void paging_init(void);
79#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) 79#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
80#define pmd_page_vaddr(pmd) pmd_val(pmd) 80#define pmd_page_vaddr(pmd) pmd_val(pmd)
81 81
82#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 82#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
83 83
84#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) 84#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
85#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) 85#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
@@ -182,7 +182,7 @@ extern pgd_t swapper_pg_dir[];
182 * The following only work if pte_present() is true. 182 * The following only work if pte_present() is true.
183 * Undefined behaviour if not.. 183 * Undefined behaviour if not..
184 */ 184 */
185#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 185#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
186static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; } 186static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
187static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; } 187static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
188static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; } 188static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
@@ -309,7 +309,7 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
309 */ 309 */
310#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 310#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
311 311
312#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 312#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
313static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 313static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
314{ 314{
315 pte.pte_low &= _PAGE_CHG_MASK; 315 pte.pte_low &= _PAGE_CHG_MASK;