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-rw-r--r--include/asm-powerpc/fs_pd.h45
-rw-r--r--include/asm-powerpc/mpc85xx.h53
-rw-r--r--include/asm-ppc/cpm2.h63
-rw-r--r--include/asm-ppc/fs_pd.h36
-rw-r--r--include/linux/fs_enet_pd.h47
-rw-r--r--include/linux/fs_uart_pd.h14
6 files changed, 252 insertions, 6 deletions
diff --git a/include/asm-powerpc/fs_pd.h b/include/asm-powerpc/fs_pd.h
new file mode 100644
index 000000000000..3d0e819d37f1
--- /dev/null
+++ b/include/asm-powerpc/fs_pd.h
@@ -0,0 +1,45 @@
1/*
2 * Platform information definitions.
3 *
4 * 2006 (c) MontaVista Software, Inc.
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#ifndef FS_PD_H
13#define FS_PD_H
14#include <asm/cpm2.h>
15#include <sysdev/fsl_soc.h>
16#include <asm/time.h>
17
18static inline int uart_baudrate(void)
19{
20 return get_baudrate();
21}
22
23static inline int uart_clock(void)
24{
25 return ppc_proc_freq;
26}
27
28#define cpm2_map(member) \
29({ \
30 u32 offset = offsetof(cpm2_map_t, member); \
31 void *addr = ioremap (CPM_MAP_ADDR + offset, \
32 sizeof( ((cpm2_map_t*)0)->member)); \
33 addr; \
34})
35
36#define cpm2_map_size(member, size) \
37({ \
38 u32 offset = offsetof(cpm2_map_t, member); \
39 void *addr = ioremap (CPM_MAP_ADDR + offset, size); \
40 addr; \
41})
42
43#define cpm2_unmap(addr) iounmap(addr)
44
45#endif
diff --git a/include/asm-powerpc/mpc85xx.h b/include/asm-powerpc/mpc85xx.h
new file mode 100644
index 000000000000..ccdb8a21138f
--- /dev/null
+++ b/include/asm-powerpc/mpc85xx.h
@@ -0,0 +1,53 @@
1/*
2 * include/asm-powerpc/mpc85xx.h
3 *
4 * MPC85xx definitions
5 *
6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 *
8 * Copyright 2004 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_MPC85xx_H__
18#define __ASM_MPC85xx_H__
19
20#include <asm/mmu.h>
21
22#ifdef CONFIG_85xx
23
24#if defined(CONFIG_MPC8540_ADS) || defined(CONFIG_MPC8560_ADS)
25#include <platforms/85xx/mpc85xx_ads.h>
26#endif
27#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
28#include <platforms/85xx/mpc8555_cds.h>
29#endif
30#ifdef CONFIG_MPC85xx_CDS
31#include <platforms/85xx/mpc85xx_cds.h>
32#endif
33
34#define _IO_BASE isa_io_base
35#define _ISA_MEM_BASE isa_mem_base
36#ifdef CONFIG_PCI
37#define PCI_DRAM_OFFSET pci_dram_offset
38#else
39#define PCI_DRAM_OFFSET 0
40#endif
41
42/* Let modules/drivers get at CCSRBAR */
43extern phys_addr_t get_ccsrbar(void);
44
45#ifdef MODULE
46#define CCSRBAR get_ccsrbar()
47#else
48#define CCSRBAR BOARD_CCSRBAR
49#endif
50
51#endif /* CONFIG_85xx */
52#endif /* __ASM_MPC85xx_H__ */
53#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index f6a7ff04ffe5..220cc2debe08 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -42,6 +42,8 @@
42#define CPM_CR_IDMA4_SBLOCK (0x17) 42#define CPM_CR_IDMA4_SBLOCK (0x17)
43#define CPM_CR_MCC1_SBLOCK (0x1c) 43#define CPM_CR_MCC1_SBLOCK (0x1c)
44 44
45#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
46
45#define CPM_CR_SCC1_PAGE (0x00) 47#define CPM_CR_SCC1_PAGE (0x00)
46#define CPM_CR_SCC2_PAGE (0x01) 48#define CPM_CR_SCC2_PAGE (0x01)
47#define CPM_CR_SCC3_PAGE (0x02) 49#define CPM_CR_SCC3_PAGE (0x02)
@@ -62,6 +64,8 @@
62#define CPM_CR_MCC1_PAGE (0x07) 64#define CPM_CR_MCC1_PAGE (0x07)
63#define CPM_CR_MCC2_PAGE (0x08) 65#define CPM_CR_MCC2_PAGE (0x08)
64 66
67#define CPM_CR_FCC_PAGE(x) (x + 0x04)
68
65/* Some opcodes (there are more...later) 69/* Some opcodes (there are more...later)
66*/ 70*/
67#define CPM_CR_INIT_TRX ((ushort)0x0000) 71#define CPM_CR_INIT_TRX ((ushort)0x0000)
@@ -173,6 +177,10 @@ typedef struct cpm_buf_desc {
173#define PROFF_I2C_BASE ((uint)0x8afc) 177#define PROFF_I2C_BASE ((uint)0x8afc)
174#define PROFF_IDMA4_BASE ((uint)0x8afe) 178#define PROFF_IDMA4_BASE ((uint)0x8afe)
175 179
180#define PROFF_SCC_SIZE ((uint)0x100)
181#define PROFF_FCC_SIZE ((uint)0x100)
182#define PROFF_SMC_SIZE ((uint)64)
183
176/* The SMCs are relocated to any of the first eight DPRAM pages. 184/* The SMCs are relocated to any of the first eight DPRAM pages.
177 * We will fix these at the first locations of DPRAM, until we 185 * We will fix these at the first locations of DPRAM, until we
178 * get some microcode patches :-). 186 * get some microcode patches :-).
@@ -1186,7 +1194,60 @@ typedef struct im_idma {
1186#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) 1194#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1187#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) 1195#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1188#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) 1196#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1189#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(2) 1197#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1198
1199/* Clocks and GRG's */
1200
1201enum cpm_clk_dir {
1202 CPM_CLK_RX,
1203 CPM_CLK_TX,
1204 CPM_CLK_RTX
1205};
1206
1207enum cpm_clk_target {
1208 CPM_CLK_SCC1,
1209 CPM_CLK_SCC2,
1210 CPM_CLK_SCC3,
1211 CPM_CLK_SCC4,
1212 CPM_CLK_FCC1,
1213 CPM_CLK_FCC2,
1214 CPM_CLK_FCC3
1215};
1216
1217enum cpm_clk {
1218 CPM_CLK_NONE = 0,
1219 CPM_BRG1, /* Baud Rate Generator 1 */
1220 CPM_BRG2, /* Baud Rate Generator 2 */
1221 CPM_BRG3, /* Baud Rate Generator 3 */
1222 CPM_BRG4, /* Baud Rate Generator 4 */
1223 CPM_BRG5, /* Baud Rate Generator 5 */
1224 CPM_BRG6, /* Baud Rate Generator 6 */
1225 CPM_BRG7, /* Baud Rate Generator 7 */
1226 CPM_BRG8, /* Baud Rate Generator 8 */
1227 CPM_CLK1, /* Clock 1 */
1228 CPM_CLK2, /* Clock 2 */
1229 CPM_CLK3, /* Clock 3 */
1230 CPM_CLK4, /* Clock 4 */
1231 CPM_CLK5, /* Clock 5 */
1232 CPM_CLK6, /* Clock 6 */
1233 CPM_CLK7, /* Clock 7 */
1234 CPM_CLK8, /* Clock 8 */
1235 CPM_CLK9, /* Clock 9 */
1236 CPM_CLK10, /* Clock 10 */
1237 CPM_CLK11, /* Clock 11 */
1238 CPM_CLK12, /* Clock 12 */
1239 CPM_CLK13, /* Clock 13 */
1240 CPM_CLK14, /* Clock 14 */
1241 CPM_CLK15, /* Clock 15 */
1242 CPM_CLK16, /* Clock 16 */
1243 CPM_CLK17, /* Clock 17 */
1244 CPM_CLK18, /* Clock 18 */
1245 CPM_CLK19, /* Clock 19 */
1246 CPM_CLK20, /* Clock 20 */
1247 CPM_CLK_DUMMY
1248};
1249
1250extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
1190 1251
1191#endif /* __CPM2__ */ 1252#endif /* __CPM2__ */
1192#endif /* __KERNEL__ */ 1253#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/fs_pd.h b/include/asm-ppc/fs_pd.h
new file mode 100644
index 000000000000..8691327653af
--- /dev/null
+++ b/include/asm-ppc/fs_pd.h
@@ -0,0 +1,36 @@
1/*
2 * Platform information definitions.
3 *
4 * 2006 (c) MontaVista Software, Inc.
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#ifndef FS_PD_H
13#define FS_PD_H
14
15static inline int uart_baudrate(void)
16{
17 int baud;
18 bd_t *bd = (bd_t *) __res;
19
20 if (bd->bi_baudrate)
21 baud = bd->bi_baudrate;
22 else
23 baud = -1;
24 return baud;
25}
26
27static inline int uart_clock(void)
28{
29 return (((bd_t *) __res)->bi_intfreq);
30}
31
32#define cpm2_map(member) (&cpm2_immr->member)
33#define cpm2_map_size(member, size) (&cpm2_immr->member)
34#define cpm2_unmap(addr) do {} while(0)
35
36#endif
diff --git a/include/linux/fs_enet_pd.h b/include/linux/fs_enet_pd.h
index 74ed35a00a94..543cd3cd9e77 100644
--- a/include/linux/fs_enet_pd.h
+++ b/include/linux/fs_enet_pd.h
@@ -55,6 +55,30 @@ static inline int fs_get_scc_index(enum fs_id id)
55 return -1; 55 return -1;
56} 56}
57 57
58static inline int fs_fec_index2id(int index)
59{
60 int id = fsid_fec1 + index - 1;
61 if (id >= fsid_fec1 && id <= fsid_fec2)
62 return id;
63 return FS_MAX_INDEX;
64 }
65
66static inline int fs_fcc_index2id(int index)
67{
68 int id = fsid_fcc1 + index - 1;
69 if (id >= fsid_fcc1 && id <= fsid_fcc3)
70 return id;
71 return FS_MAX_INDEX;
72}
73
74static inline int fs_scc_index2id(int index)
75{
76 int id = fsid_scc1 + index - 1;
77 if (id >= fsid_scc1 && id <= fsid_scc4)
78 return id;
79 return FS_MAX_INDEX;
80}
81
58enum fs_mii_method { 82enum fs_mii_method {
59 fsmii_fixed, 83 fsmii_fixed,
60 fsmii_fec, 84 fsmii_fec,
@@ -87,18 +111,21 @@ struct fs_mii_bb_platform_info {
87}; 111};
88 112
89struct fs_platform_info { 113struct fs_platform_info {
90 114
91 void(*init_ioports)(void); 115 void(*init_ioports)(struct fs_platform_info *);
92 /* device specific information */ 116 /* device specific information */
93 int fs_no; /* controller index */ 117 int fs_no; /* controller index */
118 char fs_type[4]; /* controller type */
94 119
95 u32 cp_page; /* CPM page */ 120 u32 cp_page; /* CPM page */
96 u32 cp_block; /* CPM sblock */ 121 u32 cp_block; /* CPM sblock */
97 122
98 u32 clk_trx; /* some stuff for pins & mux configuration*/ 123 u32 clk_trx; /* some stuff for pins & mux configuration*/
124 u32 clk_rx;
125 u32 clk_tx;
99 u32 clk_route; 126 u32 clk_route;
100 u32 clk_mask; 127 u32 clk_mask;
101 128
102 u32 mem_offset; 129 u32 mem_offset;
103 u32 dpram_offset; 130 u32 dpram_offset;
104 u32 fcc_regs_c; 131 u32 fcc_regs_c;
@@ -124,4 +151,16 @@ struct fs_mii_fec_platform_info {
124 u32 irq[32]; 151 u32 irq[32];
125 u32 mii_speed; 152 u32 mii_speed;
126}; 153};
154
155static inline int fs_get_id(struct fs_platform_info *fpi)
156{
157 if(strstr(fpi->fs_type, "SCC"))
158 return fs_scc_index2id(fpi->fs_no);
159 if(strstr(fpi->fs_type, "FCC"))
160 return fs_fcc_index2id(fpi->fs_no);
161 if(strstr(fpi->fs_type, "FEC"))
162 return fs_fec_index2id(fpi->fs_no);
163 return fpi->fs_no;
164}
165
127#endif 166#endif
diff --git a/include/linux/fs_uart_pd.h b/include/linux/fs_uart_pd.h
index f5975126b712..809bb9ffc788 100644
--- a/include/linux/fs_uart_pd.h
+++ b/include/linux/fs_uart_pd.h
@@ -46,15 +46,27 @@ static inline int fs_uart_id_fsid2smc(int id)
46} 46}
47 47
48struct fs_uart_platform_info { 48struct fs_uart_platform_info {
49 void(*init_ioports)(void); 49 void(*init_ioports)(struct fs_uart_platform_info *);
50 /* device specific information */ 50 /* device specific information */
51 int fs_no; /* controller index */ 51 int fs_no; /* controller index */
52 char fs_type[4]; /* controller type */
52 u32 uart_clk; 53 u32 uart_clk;
53 u8 tx_num_fifo; 54 u8 tx_num_fifo;
54 u8 tx_buf_size; 55 u8 tx_buf_size;
55 u8 rx_num_fifo; 56 u8 rx_num_fifo;
56 u8 rx_buf_size; 57 u8 rx_buf_size;
57 u8 brg; 58 u8 brg;
59 u8 clk_rx;
60 u8 clk_tx;
58}; 61};
59 62
63static inline int fs_uart_get_id(struct fs_uart_platform_info *fpi)
64{
65 if(strstr(fpi->fs_type, "SMC"))
66 return fs_uart_id_smc2fsid(fpi->fs_no);
67 if(strstr(fpi->fs_type, "SCC"))
68 return fs_uart_id_scc2fsid(fpi->fs_no);
69 return fpi->fs_no;
70}
71
60#endif 72#endif