105 files changed, 1838 insertions, 659 deletions
diff --git a/include/asm-arm/arch-at91/at91_lcdc.h b/include/asm-arm/arch-at91/at91_lcdc.h
deleted file mode 100644
index ab040a40d37b..000000000000
--- a/include/asm-arm/arch-at91/at91_lcdc.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * include/asm-arm/arch-at91/at91_lcdc.h
- *
- * LCD Controller (LCDC).
- * Based on AT91SAM9261 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91_LCDC_H
-#define AT91_LCDC_H
-#define AT91_LCDC_DMABADDR1     0x00            /* DMA Base Address Register 1 */
-#define AT91_LCDC_DMABADDR2     0x04            /* DMA Base Address Register 2 */
-#define AT91_LCDC_DMAFRMPT1     0x08            /* DMA Frame Pointer Register 1 */
-#define AT91_LCDC_DMAFRMPT2     0x0c            /* DMA Frame Pointer Register 2 */
-#define AT91_LCDC_DMAFRMADD1    0x10            /* DMA Frame Address Register 1 */
-#define AT91_LCDC_DMAFRMADD2    0x14            /* DMA Frame Address Register 2 */
-#define AT91_LCDC_DMAFRMCFG     0x18            /* DMA Frame Configuration Register */
-#define         AT91_LCDC_FRSIZE        (0x7fffff <<  0)        /* Frame Size */
-#define         AT91_LCDC_BLENGTH       (0x7f     << 24)        /* Burst Length */
-#define AT91_LCDC_DMACON        0x1c            /* DMA Control Register */
-#define         AT91_LCDC_DMAEN         (0x1 << 0)      /* DMA Enable */
-#define         AT91_LCDC_DMARST        (0x1 << 1)      /* DMA Reset */
-#define         AT91_LCDC_DMABUSY       (0x1 << 2)      /* DMA Busy */
-#define AT91_LCDC_LCDCON1       0x0800          /* LCD Control Register 1 */
-#define         AT91_LCDC_BYPASS        (1     <<  0)   /* Bypass lcd_dotck divider */
-#define         AT91_LCDC_CLKVAL        (0x1ff << 12)   /* Clock Divider */
-#define         AT91_LCDC_LINCNT        (0x7ff << 21)   /* Line Counter */
-#define AT91_LCDC_LCDCON2       0x0804          /* LCD Control Register 2 */
-#define         AT91_LCDC_DISTYPE       (3 << 0)        /* Display Type */
-#define                 AT91_LCDC_DISTYPE_STNMONO       (0 << 0)
-#define                 AT91_LCDC_DISTYPE_STNCOLOR      (1 << 0)
-#define                 AT91_LCDC_DISTYPE_TFT           (2 << 0)
-#define         AT91_LCDC_SCANMOD       (1 << 2)        /* Scan Mode */
-#define                 AT91_LCDC_SCANMOD_SINGLE        (0 << 2)
-#define                 AT91_LCDC_SCANMOD_DUAL          (1 << 2)
-#define         AT91_LCDC_IFWIDTH       (3 << 3)        /*Interface Width */
-#define                 AT91_LCDC_IFWIDTH_4             (0 << 3)
-#define                 AT91_LCDC_IFWIDTH_8             (1 << 3)
-#define                 AT91_LCDC_IFWIDTH_16            (2 << 3)
-#define         AT91_LCDC_PIXELSIZE     (7 << 5)        /* Bits per pixel */
-#define                 AT91_LCDC_PIXELSIZE_1           (0 << 5)
-#define                 AT91_LCDC_PIXELSIZE_2           (1 << 5)
-#define                 AT91_LCDC_PIXELSIZE_4           (2 << 5)
-#define                 AT91_LCDC_PIXELSIZE_8           (3 << 5)
-#define                 AT91_LCDC_PIXELSIZE_16          (4 << 5)
-#define                 AT91_LCDC_PIXELSIZE_24          (5 << 5)
-#define         AT91_LCDC_INVVD         (1 << 8)        /* LCD Data polarity */
-#define                 AT91_LCDC_INVVD_NORMAL          (0 << 8)
-#define                 AT91_LCDC_INVVD_INVERTED        (1 << 8)
-#define         AT91_LCDC_INVFRAME      (1 << 9 )       /* LCD VSync polarity */
-#define                 AT91_LCDC_INVFRAME_NORMAL       (0 << 9)
-#define                 AT91_LCDC_INVFRAME_INVERTED     (1 << 9)
-#define         AT91_LCDC_INVLINE       (1 << 10)       /* LCD HSync polarity */
-#define                 AT91_LCDC_INVLINE_NORMAL        (0 << 10)
-#define                 AT91_LCDC_INVLINE_INVERTED      (1 << 10)
-#define         AT91_LCDC_INVCLK        (1 << 11)       /* LCD dotclk polarity */
-#define                 AT91_LCDC_INVCLK_NORMAL         (0 << 11)
-#define                 AT91_LCDC_INVCLK_INVERTED       (1 << 11)
-#define         AT91_LCDC_INVDVAL       (1 << 12)       /* LCD dval polarity */
-#define                 AT91_LCDC_INVDVAL_NORMAL        (0 << 12)
-#define                 AT91_LCDC_INVDVAL_INVERTED      (1 << 12)
-#define         AT91_LCDC_CLKMOD        (1 << 15)       /* LCD dotclk mode */
-#define                 AT91_LCDC_CLKMOD_ACTIVEDISPLAY  (0 << 15)
-#define                 AT91_LCDC_CLKMOD_ALWAYSACTIVE   (1 << 15)
-#define         AT91_LCDC_MEMOR         (1 << 31)       /* Memory Ordering Format */
-#define                 AT91_LCDC_MEMOR_BIG             (0 << 31)
-#define                 AT91_LCDC_MEMOR_LITTLE          (1 << 31)
-#define AT91_LCDC_TIM1          0x0808          /* LCD Timing Register 1 */
-#define         AT91_LCDC_VFP           (0xff <<  0)    /* Vertical Front Porch */
-#define         AT91_LCDC_VBP           (0xff <<  8)    /* Vertical Back Porch */
-#define         AT91_LCDC_VPW           (0x3f << 16)    /* Vertical Synchronization Pulse Width */
-#define         AT91_LCDC_VHDLY         (0xf  << 24)    /* Vertical to Horizontal Delay */
-#define AT91_LCDC_TIM2          0x080c          /* LCD Timing Register 2 */
-#define         AT91_LCDC_HBP           (0xff  <<  0)   /* Horizontal Back Porch */
-#define         AT91_LCDC_HPW           (0x3f  <<  8)   /* Horizontal Synchronization Pulse Width */
-#define         AT91_LCDC_HFP           (0x7ff << 21)   /* Horizontal Front Porch */
-#define AT91_LCDC_LCDFRMCFG     0x0810          /* LCD Frame Configuration Register */
-#define         AT91_LCDC_LINEVAL       (0x7ff <<  0)   /* Vertical Size of LCD Module */
-#define         AT91_LCDC_HOZVAL        (0x7ff << 21)   /* Horizontal Size of LCD Module */
-#define AT91_LCDC_FIFO          0x0814          /* LCD FIFO Register */
-#define         AT91_LCDC_FIFOTH        (0xffff)        /* FIFO Threshold */
-#define AT91_LCDC_DP1_2         0x081c          /* Dithering Pattern DP1_2 Register */
-#define AT91_LCDC_DP4_7         0x0820          /* Dithering Pattern DP4_7 Register */
-#define AT91_LCDC_DP3_5         0x0824          /* Dithering Pattern DP3_5 Register */
-#define AT91_LCDC_DP2_3         0x0828          /* Dithering Pattern DP2_3 Register */
-#define AT91_LCDC_DP5_7         0x082c          /* Dithering Pattern DP5_7 Register */
-#define AT91_LCDC_DP3_4         0x0830          /* Dithering Pattern DP3_4 Register */
-#define AT91_LCDC_DP4_5         0x0834          /* Dithering Pattern DP4_5 Register */
-#define AT91_LCDC_DP6_7         0x0838          /* Dithering Pattern DP6_7 Register */
-#define         AT91_LCDC_DP1_2_VAL     (0xff)
-#define         AT91_LCDC_DP4_7_VAL     (0xfffffff)
-#define         AT91_LCDC_DP3_5_VAL     (0xfffff)
-#define         AT91_LCDC_DP2_3_VAL     (0xfff)
-#define         AT91_LCDC_DP5_7_VAL     (0xfffffff)
-#define         AT91_LCDC_DP3_4_VAL     (0xffff)
-#define         AT91_LCDC_DP4_5_VAL     (0xfffff)
-#define         AT91_LCDC_DP6_7_VAL     (0xfffffff)
-#define AT91_LCDC_PWRCON        0x083c          /* Power Control Register */
-#define         AT91_LCDC_PWR           (1    <<  0)    /* LCD Module Power Control */
-#define         AT91_LCDC_GUARDT        (0x7f <<  1)    /* Delay in Frame Period */
-#define         AT91_LCDC_BUSY          (1    << 31)    /* LCD Busy */
-#define AT91_LCDC_CONTRAST_CTR  0x0840          /* Contrast Control Register */
-#define         AT91_LCDC_PS            (3 << 0)        /* Contrast Counter Prescaler */
-#define                 AT91_LCDC_PS_DIV1               (0 << 0)
-#define                 AT91_LCDC_PS_DIV2               (1 << 0)
-#define                 AT91_LCDC_PS_DIV4               (2 << 0)
-#define                 AT91_LCDC_PS_DIV8               (3 << 0)
-#define         AT91_LCDC_POL           (1 << 2)        /* Polarity of output Pulse */
-#define                 AT91_LCDC_POL_NEGATIVE          (0 << 2)
-#define                 AT91_LCDC_POL_POSITIVE          (1 << 2)
-#define         AT91_LCDC_ENA           (1 << 3)        /* PWM generator Control */
-#define                 AT91_LCDC_ENA_PWMDISABLE        (0 << 3)
-#define                 AT91_LCDC_ENA_PWMENABLE         (1 << 3)
-#define AT91_LCDC_CONTRAST_VAL  0x0844          /* Contrast Value Register */
-#define         AT91_LCDC_CVAL          (0xff)          /* PWM compare value */
-#define AT91_LCDC_IER           0x0848          /* Interrupt Enable Register */
-#define AT91_LCDC_IDR           0x084c          /* Interrupt Disable Register */
-#define AT91_LCDC_IMR           0x0850          /* Interrupt Mask Register */
-#define AT91_LCDC_ISR           0x0854          /* Interrupt Enable Register */
-#define AT91_LCDC_ICR           0x0858          /* Interrupt Clear Register */
-#define         AT91_LCDC_LNI           (1 << 0)        /* Line Interrupt */
-#define         AT91_LCDC_LSTLNI        (1 << 1)        /* Last Line Interrupt */
-#define         AT91_LCDC_EOFI          (1 << 2)        /* DMA End Of Frame Interrupt */
-#define         AT91_LCDC_UFLWI         (1 << 4)        /* FIFO Underflow Interrupt */
-#define         AT91_LCDC_OWRI          (1 << 5)        /* FIFO Overwrite Interrupt */
-#define         AT91_LCDC_MERI          (1 << 6)        /* DMA Memory Error Interrupt */
-#define AT91_LCDC_LUT_(n)       (0x0c00 + ((n)*4))      /* Palette Entry 0..255 */
-#endif
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 33ff5b6798ee..52cd8e5dabc9 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -25,6 +25,7 @@
 #define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
 #define         AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
 #define         AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
+#define         AT91CAP9_PMC_UHP        (1 <<  6)               /* USB Host Port Clock [AT91CAP9 only] */
 #define         AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
 #define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
 #define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
@@ -37,7 +38,9 @@
 #define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
 #define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
-#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
+#define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL, CAP9] */
+#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
 #define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
 #define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [AT91SAM926x only] */
 #define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
@@ -52,6 +55,10 @@
 #define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
 #define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define         AT91_PMC_USBDIV         (3     << 28)           /* USB Divisor (PLLB only) */
+#define                 AT91_PMC_USBDIV_1               (0 << 28)
+#define                 AT91_PMC_USBDIV_2               (1 << 28)
+#define                 AT91_PMC_USBDIV_4               (2 << 28)
 #define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
 #define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
diff --git a/include/asm-arm/arch-at91/at91_rtt.h b/include/asm-arm/arch-at91/at91_rtt.h
index bae1103fbbb2..39a32633b275 100644
--- a/include/asm-arm/arch-at91/at91_rtt.h
+++ b/include/asm-arm/arch-at91/at91_rtt.h
@@ -13,19 +13,19 @@
 #ifndef AT91_RTT_H
 #define AT91_RTT_H
-#define AT91_RTT_MR             (AT91_RTT + 0x00)       /* Real-time Mode Register */
+#define AT91_RTT_MR             0x00                    /* Real-time Mode Register */
 #define         AT91_RTT_RTPRES         (0xffff << 0)           /* Real-time Timer Prescaler Value */
 #define         AT91_RTT_ALMIEN         (1 << 16)               /* Alarm Interrupt Enable */
 #define         AT91_RTT_RTTINCIEN      (1 << 17)               /* Real Time Timer Increment Interrupt Enable */
 #define         AT91_RTT_RTTRST         (1 << 18)               /* Real Time Timer Restart */
-#define AT91_RTT_AR             (AT91_RTT + 0x04)       /* Real-time Alarm Register */
+#define AT91_RTT_AR             0x04                    /* Real-time Alarm Register */
 #define         AT91_RTT_ALMV           (0xffffffff)            /* Alarm Value */
-#define AT91_RTT_VR             (AT91_RTT + 0x08)       /* Real-time Value Register */
+#define AT91_RTT_VR             0x08                    /* Real-time Value Register */
 #define         AT91_RTT_CRTV           (0xffffffff)            /* Current Real-time Value */
-#define AT91_RTT_SR             (AT91_RTT + 0x0c)       /* Real-time Status Register */
+#define AT91_RTT_SR             0x0c                    /* Real-time Status Register */
 #define         AT91_RTT_ALMS           (1 << 0)                /* Real-time Alarm Status */
 #define         AT91_RTT_RTTINC         (1 << 1)                /* Real-time Timer Increment */
diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h
index ca9a90733456..f9f2e3cd95c5 100644
--- a/include/asm-arm/arch-at91/at91_twi.h
+++ b/include/asm-arm/arch-at91/at91_twi.h
@@ -21,6 +21,8 @@
 #define         AT91_TWI_STOP           (1 <<  1)       /* Send a Stop Condition */
 #define         AT91_TWI_MSEN           (1 <<  2)       /* Master Transfer Enable */
 #define         AT91_TWI_MSDIS          (1 <<  3)       /* Master Transfer Disable */
+#define         AT91_TWI_SVEN           (1 <<  4)       /* Slave Transfer Enable [SAM9260 only] */
+#define         AT91_TWI_SVDIS          (1 <<  5)       /* Slave Transfer Disable [SAM9260 only] */
 #define         AT91_TWI_SWRST          (1 <<  7)       /* Software Reset */
 #define AT91_TWI_MMR            0x04            /* Master Mode Register */
@@ -32,6 +34,9 @@
 #define         AT91_TWI_MREAD          (1    << 12)    /* Master Read Direction */
 #define         AT91_TWI_DADR           (0x7f << 16)    /* Device Address */
+#define AT91_TWI_SMR            0x08            /* Slave Mode Register [SAM9260 only] */
+#define         AT91_TWI_SADR           (0x7f << 16)    /* Slave Address */
 #define AT91_TWI_IADR           0x0c            /* Internal Address Register */
 #define AT91_TWI_CWGR           0x10            /* Clock Waveform Generator Register */
@@ -43,9 +48,15 @@
 #define         AT91_TWI_TXCOMP         (1 <<  0)       /* Transmission Complete */
 #define         AT91_TWI_RXRDY          (1 <<  1)       /* Receive Holding Register Ready */
 #define         AT91_TWI_TXRDY          (1 <<  2)       /* Transmit Holding Register Ready */
+#define         AT91_TWI_SVREAD         (1 <<  3)       /* Slave Read [SAM9260 only] */
+#define         AT91_TWI_SVACC          (1 <<  4)       /* Slave Access [SAM9260 only] */
+#define         AT91_TWI_GACC           (1 <<  5)       /* General Call Access [SAM9260 only] */
 #define         AT91_TWI_OVRE           (1 <<  6)       /* Overrun Error [AT91RM9200 only] */
 #define         AT91_TWI_UNRE           (1 <<  7)       /* Underrun Error [AT91RM9200 only] */
 #define         AT91_TWI_NACK           (1 <<  8)       /* Not Acknowledged */
+#define         AT91_TWI_ARBLST         (1 <<  9)       /* Arbitration Lost [SAM9260 only] */
+#define         AT91_TWI_SCLWS          (1 << 10)       /* Clock Wait State [SAM9260 only] */
+#define         AT91_TWI_EOSACC         (1 << 11)       /* End of Slave Address [SAM9260 only] */
 #define AT91_TWI_IER            0x24            /* Interrupt Enable Register */
 #define AT91_TWI_IDR            0x28            /* Interrupt Disable Register */
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
new file mode 100644
index 000000000000..73e1fcf4a0aa
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -0,0 +1,121 @@
+/*
+ * include/asm-arm/arch-at91/at91cap9.h
+ *
+ *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
+ *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
+ *  Copyright (C) 2007 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91CAP9 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91CAP9_H
+#define AT91CAP9_H
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT91CAP9_ID_PIOABCD     2       /* Parallel IO Controller A, B, C and D */
+#define AT91CAP9_ID_MPB0        3       /* MP Block Peripheral 0 */
+#define AT91CAP9_ID_MPB1        4       /* MP Block Peripheral 1 */
+#define AT91CAP9_ID_MPB2        5       /* MP Block Peripheral 2 */
+#define AT91CAP9_ID_MPB3        6       /* MP Block Peripheral 3 */
+#define AT91CAP9_ID_MPB4        7       /* MP Block Peripheral 4 */
+#define AT91CAP9_ID_US0         8       /* USART 0 */
+#define AT91CAP9_ID_US1         9       /* USART 1 */
+#define AT91CAP9_ID_US2         10      /* USART 2 */
+#define AT91CAP9_ID_MCI0        11      /* Multimedia Card Interface 0 */
+#define AT91CAP9_ID_MCI1        12      /* Multimedia Card Interface 1 */
+#define AT91CAP9_ID_CAN         13      /* CAN */
+#define AT91CAP9_ID_TWI         14      /* Two-Wire Interface */
+#define AT91CAP9_ID_SPI0        15      /* Serial Peripheral Interface 0 */
+#define AT91CAP9_ID_SPI1        16      /* Serial Peripheral Interface 0 */
+#define AT91CAP9_ID_SSC0        17      /* Serial Synchronous Controller 0 */
+#define AT91CAP9_ID_SSC1        18      /* Serial Synchronous Controller 1 */
+#define AT91CAP9_ID_AC97C       19      /* AC97 Controller */
+#define AT91CAP9_ID_TCB         20      /* Timer Counter 0, 1 and 2 */
+#define AT91CAP9_ID_PWMC        21      /* Pulse Width Modulation Controller */
+#define AT91CAP9_ID_EMAC        22      /* Ethernet */
+#define AT91CAP9_ID_AESTDES     23      /* Advanced Encryption Standard, Triple DES */
+#define AT91CAP9_ID_ADC         24      /* Analog-to-Digital Converter */
+#define AT91CAP9_ID_ISI         25      /* Image Sensor Interface */
+#define AT91CAP9_ID_LCDC        26      /* LCD Controller */
+#define AT91CAP9_ID_DMA         27      /* DMA Controller */
+#define AT91CAP9_ID_UDPHS       28      /* USB High Speed Device Port */
+#define AT91CAP9_ID_UHP         29      /* USB Host Port */
+#define AT91CAP9_ID_IRQ0        30      /* Advanced Interrupt Controller (IRQ0) */
+#define AT91CAP9_ID_IRQ1        31      /* Advanced Interrupt Controller (IRQ1) */
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91CAP9_BASE_UDPHS             0xfff78000
+#define AT91CAP9_BASE_TCB0              0xfff7c000
+#define AT91CAP9_BASE_TC0               0xfff7c000
+#define AT91CAP9_BASE_TC1               0xfff7c040
+#define AT91CAP9_BASE_TC2               0xfff7c080
+#define AT91CAP9_BASE_MCI0              0xfff80000
+#define AT91CAP9_BASE_MCI1              0xfff84000
+#define AT91CAP9_BASE_TWI               0xfff88000
+#define AT91CAP9_BASE_US0               0xfff8c000
+#define AT91CAP9_BASE_US1               0xfff90000
+#define AT91CAP9_BASE_US2               0xfff94000
+#define AT91CAP9_BASE_SSC0              0xfff98000
+#define AT91CAP9_BASE_SSC1              0xfff9c000
+#define AT91CAP9_BASE_AC97C             0xfffa0000
+#define AT91CAP9_BASE_SPI0              0xfffa4000
+#define AT91CAP9_BASE_SPI1              0xfffa8000
+#define AT91CAP9_BASE_CAN               0xfffac000
+#define AT91CAP9_BASE_PWMC              0xfffb8000
+#define AT91CAP9_BASE_EMAC              0xfffbc000
+#define AT91CAP9_BASE_ADC               0xfffc0000
+#define AT91CAP9_BASE_ISI               0xfffc4000
+#define AT91_BASE_SYS                   0xffffe200
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
+#define AT91_BCRAMC     (0xffffe400 - AT91_BASE_SYS)
+#define AT91_DDRSDRC    (0xffffe600 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_CCFG       (0xffffeb10 - AT91_BASE_SYS)
+#define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDC       (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+/*
+ * Internal Memory.
+ */
+#define AT91CAP9_SRAM_BASE      0x00100000      /* Internal SRAM base address */
+#define AT91CAP9_SRAM_SIZE      (32 * SZ_1K)    /* Internal SRAM size (32Kb) */
+#define AT91CAP9_ROM_BASE       0x00400000      /* Internal ROM base address */
+#define AT91CAP9_ROM_SIZE       (32 * SZ_1K)    /* Internal ROM size (32Kb) */
+#define AT91CAP9_LCDC_BASE      0x00500000      /* LCD Controller */
+#define AT91CAP9_UDPHS_BASE     0x00600000      /* USB High Speed Device Port */
+#define AT91CAP9_UHP_BASE       0x00700000      /* USB Host controller */
+#define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
+#endif
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
new file mode 100644
index 000000000000..a641686b6c3d
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
@@ -0,0 +1,132 @@
+/*
+ * include/asm-arm/arch-at91/at91cap9_matrix.h
+ *
+ *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
+ *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
+ *  Copyright (C) 2006 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91CAP9 datasheet revision B (Preliminary).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91CAP9_MATRIX_H
+#define AT91CAP9_MATRIX_H
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG8       (AT91_MATRIX + 0x60)    /* Slave Configuration Register 8 */
+#define AT91_MATRIX_SCFG9       (AT91_MATRIX + 0x64)    /* Slave Configuration Register 9 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS8       (AT91_MATRIX + 0xC0)    /* Priority Register A for Slave 8 */
+#define AT91_MATRIX_PRBS8       (AT91_MATRIX + 0xC4)    /* Priority Register B for Slave 8 */
+#define AT91_MATRIX_PRAS9       (AT91_MATRIX + 0xC8)    /* Priority Register A for Slave 9 */
+#define AT91_MATRIX_PRBS9       (AT91_MATRIX + 0xCC)    /* Priority Register B for Slave 9 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
+#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
+#define         AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
+#define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
+#define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define         AT91_MATRIX_RCB2                (1 << 2)
+#define         AT91_MATRIX_RCB3                (1 << 3)
+#define         AT91_MATRIX_RCB4                (1 << 4)
+#define         AT91_MATRIX_RCB5                (1 << 5)
+#define         AT91_MATRIX_RCB6                (1 << 6)
+#define         AT91_MATRIX_RCB7                (1 << 7)
+#define         AT91_MATRIX_RCB8                (1 << 8)
+#define         AT91_MATRIX_RCB9                (1 << 9)
+#define         AT91_MATRIX_RCB10               (1 << 10)
+#define         AT91_MATRIX_RCB11               (1 << 11)
+#define AT91_MPBS0_SFR          (AT91_MATRIX + 0x114)   /* MPBlock Slave 0 Special Function Register */
+#define AT91_MPBS1_SFR          (AT91_MATRIX + 0x11C)   /* MPBlock Slave 1 Special Function Register */
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define                 AT91_MATRIX_EBI_CS1A_BCRAMC             (1 << 1)
+#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define                 AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
+#define         AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
+#define                 AT91_MATRIX_EBI_CS4A_SMC_CF1            (1 << 4)
+#define         AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
+#define                 AT91_MATRIX_EBI_CS5A_SMC_CF2            (1 << 5)
+#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
+#define         AT91_MATRIX_EBI_DQSPDC          (1 << 9)        /* Data Qualifier Strobe Pull-Down Configuration */
+#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+#define AT91_MPBS2_SFR          (AT91_MATRIX + 0x12C)   /* MPBlock Slave 2 Special Function Register */
+#define AT91_MPBS3_SFR          (AT91_MATRIX + 0x130)   /* MPBlock Slave 3 Special Function Register */
+#define AT91_APB_SFR            (AT91_MATRIX + 0x134)   /* APB Bridge Special Function Register */
+#endif
diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h
index aacb1e976422..a8e9fec6c735 100644
--- a/include/asm-arm/arch-at91/at91sam9260_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h
@@ -67,7 +67,7 @@
 #define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
 #define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
 #define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define         AT91_MATRIX_CS5A                (1 << 5 )       /* Chip Select 5 Assignment */
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
 #define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
 #define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
 #define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h
index 6fc6e4be624e..72f6e668e414 100644
--- a/include/asm-arm/arch-at91/at91sam9263_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9263_matrix.h
@@ -44,7 +44,7 @@
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
 #define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
 #define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
index b15f11b7c08d..84224174e6a1 100644
--- a/include/asm-arm/arch-at91/at91sam9rl_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
@@ -38,7 +38,7 @@
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
 #define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
 #define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index 79054965baa6..55b07bd5316c 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -34,6 +34,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/device.h>
 #include <linux/i2c.h>
+#include <linux/leds.h>
 #include <linux/spi/spi.h>
 /* USB Device */
@@ -71,7 +72,7 @@ struct at91_eth_data {
 };
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263)
+#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
 #define eth_platform_data       at91_eth_data
 #endif
@@ -101,13 +102,23 @@ extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_de
 extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
 /* Serial */
+#define ATMEL_UART_CTS  0x01
+#define ATMEL_UART_RTS  0x02
+#define ATMEL_UART_DSR  0x04
+#define ATMEL_UART_DTR  0x08
+#define ATMEL_UART_DCD  0x10
+#define ATMEL_UART_RI   0x20
+extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
+extern void __init at91_set_serial_console(unsigned portnr);
 struct at91_uart_config {
        unsigned short  console_tty;    /* tty number of serial console */
        unsigned short  nr_tty;         /* number of serial tty's */
        short           tty_map[];      /* map UART to tty number */
 };
 extern struct platform_device *atmel_default_console_device;
-extern void __init at91_init_serial(struct at91_uart_config *config);
+extern void __init __deprecated at91_init_serial(struct at91_uart_config *config);
 struct atmel_uart_data {
        short           use_dma_tx;     /* use transmit DMA? */
@@ -116,6 +127,23 @@ struct atmel_uart_data {
 };
 extern void __init at91_add_device_serial(void);
+/*
+ * SSC -- accessed through ssc_request(id).  Drivers don't bind to SSC
+ * platform devices.  Their SSC ID is part of their configuration data,
+ * along with information about which SSC signals they should use.
+ */
+#define ATMEL_SSC_TK    0x01
+#define ATMEL_SSC_TF    0x02
+#define ATMEL_SSC_TD    0x04
+#define ATMEL_SSC_TX    (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
+#define ATMEL_SSC_RK    0x10
+#define ATMEL_SSC_RF    0x20
+#define ATMEL_SSC_RD    0x40
+#define ATMEL_SSC_RX    (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
+extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
 /* LCD Controller */
 struct atmel_lcdfb_info;
 extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
@@ -126,10 +154,12 @@ struct atmel_ac97_data {
 };
 extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
+ /* ISI */
+extern void __init at91_add_device_isi(void);
 /* LEDs */
-extern u8 at91_leds_cpu;
-extern u8 at91_leds_timer;
 extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
+extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 /* FIXME: this needs a better location, but gets stuff building again */
 extern int at91_suspend_entering_slow_clock(void);
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 080cbb401a87..7145166826a2 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -21,13 +21,13 @@
 #define ARCH_ID_AT91SAM9260     0x019803a0
 #define ARCH_ID_AT91SAM9261     0x019703a0
 #define ARCH_ID_AT91SAM9263     0x019607a0
+#define ARCH_ID_AT91SAM9RL64    0x019b03a0
+#define ARCH_ID_AT91CAP9        0x039A03A0
 #define ARCH_ID_AT91SAM9XE128   0x329973a0
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
 #define ARCH_ID_AT91SAM9XE512   0x329aa3a0
-#define ARCH_ID_AT91SAM9RL64    0x019b03a0
 #define ARCH_ID_AT91M40800      0x14080044
 #define ARCH_ID_AT91R40807      0x44080746
 #define ARCH_ID_AT91M40807      0x14080745
@@ -81,6 +81,11 @@ static inline unsigned long at91_arch_identify(void)
 #define cpu_is_at91sam9rl()     (0)
 #endif
+#ifdef CONFIG_ARCH_AT91CAP9
+#define cpu_is_at91cap9()       (at91_cpu_identify() == ARCH_ID_AT91CAP9)
+#else
+#define cpu_is_at91cap9()       (0)
+#endif
 /*
 * Since this is ARM, we will never run on any AVR32 CPU. But these
diff --git a/include/asm-arm/arch-at91/entry-macro.S b/include/asm-arm/arch-at91/entry-macro.S
index cc1d850a0788..1005eee6219b 100644
--- a/include/asm-arm/arch-at91/entry-macro.S
+++ b/include/asm-arm/arch-at91/entry-macro.S
@@ -17,13 +17,13 @@
        .endm
        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =(AT91_VA_BASE_SYS + AT91_AIC)           @ base virtual address of AIC peripheral
        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \base, =(AT91_VA_BASE_SYS + AT91_AIC)           @ base virtual address of AIC peripheral
        ldr     \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)]     @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
        ldr     \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)]   @ read interrupt source number
        teq     \irqstat, #0                                    @ ISR is 0 when no current interrupt, or spurious interrupt
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 8f1cdd38a969..2c826d8247a3 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -26,6 +26,8 @@
 #include <asm/arch/at91sam9263.h>
 #elif defined(CONFIG_ARCH_AT91SAM9RL)
 #include <asm/arch/at91sam9rl.h>
+#elif defined(CONFIG_ARCH_AT91CAP9)
+#include <asm/arch/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)
 #include <asm/arch/at91x40.h>
 #else
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index a310698fb4da..f1933b0fa43f 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -42,6 +42,11 @@
 #define AT91SAM9_MASTER_CLOCK   100000000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+#elif defined(CONFIG_ARCH_AT91CAP9)
+#define AT91CAP9_MASTER_CLOCK   100000000
+#define CLOCK_TICK_RATE         (AT91CAP9_MASTER_CLOCK/16)
 #elif defined(CONFIG_ARCH_AT91X40)
 #define AT91X40_MASTER_CLOCK    40000000
diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h
index 1ee14a14cba0..9b1864bbd9a8 100644
--- a/include/asm-arm/arch-ep93xx/gpio.h
+++ b/include/asm-arm/arch-ep93xx/gpio.h
@@ -5,16 +5,6 @@
 #ifndef __ASM_ARCH_GPIO_H
 #define __ASM_ARCH_GPIO_H
-#define GPIO_IN                         0
-#define GPIO_OUT                        1
-#define EP93XX_GPIO_LOW                 0
-#define EP93XX_GPIO_HIGH                1
-extern void gpio_line_config(int line, int direction);
-extern int  gpio_line_get(int line);
-extern void gpio_line_set(int line, int value);
 /* GPIO port A.  */
 #define EP93XX_GPIO_LINE_A(x)           ((x) + 0)
 #define EP93XX_GPIO_LINE_EGPIO0         EP93XX_GPIO_LINE_A(0)
@@ -38,7 +28,7 @@ extern void gpio_line_set(int line, int value);
 #define EP93XX_GPIO_LINE_EGPIO15        EP93XX_GPIO_LINE_B(7)
 /* GPIO port C.  */
-#define EP93XX_GPIO_LINE_C(x)           ((x) + 16)
+#define EP93XX_GPIO_LINE_C(x)           ((x) + 40)
 #define EP93XX_GPIO_LINE_ROW0           EP93XX_GPIO_LINE_C(0)
 #define EP93XX_GPIO_LINE_ROW1           EP93XX_GPIO_LINE_C(1)
 #define EP93XX_GPIO_LINE_ROW2           EP93XX_GPIO_LINE_C(2)
@@ -71,7 +61,7 @@ extern void gpio_line_set(int line, int value);
 #define EP93XX_GPIO_LINE_IDEDA2         EP93XX_GPIO_LINE_E(7)
 /* GPIO port F.  */
-#define EP93XX_GPIO_LINE_F(x)           ((x) + 40)
+#define EP93XX_GPIO_LINE_F(x)           ((x) + 16)
 #define EP93XX_GPIO_LINE_WP             EP93XX_GPIO_LINE_F(0)
 #define EP93XX_GPIO_LINE_MCCD1          EP93XX_GPIO_LINE_F(1)
 #define EP93XX_GPIO_LINE_MCCD2          EP93XX_GPIO_LINE_F(2)
@@ -103,5 +93,49 @@ extern void gpio_line_set(int line, int value);
 #define EP93XX_GPIO_LINE_DD6            EP93XX_GPIO_LINE_H(6)
 #define EP93XX_GPIO_LINE_DD7            EP93XX_GPIO_LINE_H(7)
+/* maximum value for gpio line identifiers */
+#define EP93XX_GPIO_LINE_MAX            EP93XX_GPIO_LINE_H(7)
+/* maximum value for irq capable line identifiers */
+#define EP93XX_GPIO_LINE_MAX_IRQ        EP93XX_GPIO_LINE_F(7)
+/* new generic GPIO API - see Documentation/gpio.txt */
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        if (gpio > EP93XX_GPIO_LINE_MAX)
+                return -EINVAL;
+        return 0;
+}
+static inline void gpio_free(unsigned gpio)
+{
+}
+int gpio_direction_input(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_value(unsigned gpio, int value);
+#include <asm-generic/gpio.h> /* cansleep wrappers */
+/*
+ * Map GPIO A0..A7  (0..7)  to irq 64..71,
+ *          B0..B7  (7..15) to irq 72..79, and
+ *          F0..F7 (16..24) to irq 80..87.
+ */
+static inline int gpio_to_irq(unsigned gpio)
+{
+        if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ)
+                return 64 + gpio;
+        return -EINVAL;
+}
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq - gpio_to_irq(0);
+}
 #endif
diff --git a/include/asm-arm/arch-ep93xx/irqs.h b/include/asm-arm/arch-ep93xx/irqs.h
index 2a8c63638c5e..53d4a68bfc88 100644
--- a/include/asm-arm/arch-ep93xx/irqs.h
+++ b/include/asm-arm/arch-ep93xx/irqs.h
@@ -67,12 +67,6 @@
 #define IRQ_EP93XX_SAI                  60
 #define EP93XX_VIC2_VALID_IRQ_MASK      0x1fffffff
-/*
- * Map GPIO A0..A7 to irq 64..71, B0..B7 to 72..79, and
- * F0..F7 to 80..87.
- */
-#define IRQ_EP93XX_GPIO(x)              (64 + (((x) + (((x) >> 2) & 8)) & 0x1f))
 #define NR_EP93XX_IRQS                  (64 + 24)
 #define EP93XX_BOARD_IRQ(x)             (NR_EP93XX_IRQS + (x))
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index eeeea90cd5a9..9c5d2357aff3 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -61,13 +61,13 @@ __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
        if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
                return __arm_ioremap(addr, size, mtype);
-        return (void *)addr;
+        return (void __iomem *)addr;
 }
 static inline void
 __ixp4xx_iounmap(void __iomem *addr)
 {
-        if ((u32)addr >= VMALLOC_START)
+        if ((__force u32)addr >= VMALLOC_START)
                __iounmap(addr);
 }
@@ -141,9 +141,9 @@ __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
 static inline void 
 __ixp4xx_writel(u32 value, volatile void __iomem *p)
 {
-        u32 addr = (u32)p;
+        u32 addr = (__force u32)p;
        if (addr >= VMALLOC_START) {
-                __raw_writel(value, addr);
+                __raw_writel(value, p);
                return;
        }
@@ -208,11 +208,11 @@ __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
 static inline unsigned long 
 __ixp4xx_readl(const volatile void __iomem *p)
 {
-        u32 addr = (u32)p;
+        u32 addr = (__force u32)p;
        u32 data;
        if (addr >= VMALLOC_START)
-                return __raw_readl(addr);
+                return __raw_readl(p);
        if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
                return 0xffffffff;
@@ -438,7 +438,7 @@ __ixp4xx_ioread32(const void __iomem *addr)
                return  (unsigned int)__ixp4xx_inl(port & PIO_MASK);
        else {
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                return le32_to_cpu(__raw_readl((u32)port));
+                return le32_to_cpu((__force __le32)__raw_readl(addr));
 #else
                return (unsigned int)__ixp4xx_readl(addr);
 #endif
@@ -523,7 +523,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr)
                __ixp4xx_outl(value, port & PIO_MASK);
        else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writel(cpu_to_le32(value), port);
+                __raw_writel((u32 __force)cpu_to_le32(value), addr);
 #else
                __ixp4xx_writel(value, addr);
 #endif
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index 2a44d3d67980..2ce28e3fd325 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -76,17 +76,6 @@ extern unsigned long ixp4xx_exp_bus_size;
 #define IXP4XX_UART_XTAL                14745600
 /*
- * The IXP4xx chips do not have an I2C unit, so GPIO lines are just
- * used to 
- * Used as platform_data to provide GPIO pin information to the ixp42x
- * I2C driver.
- */
-struct ixp4xx_i2c_pins {
-        unsigned long sda_pin;
-        unsigned long scl_pin;
-};
-/*
 * This structure provide a means for the board setup code
 * to give information to th pata_ixp4xx driver. It is
 * passed as platform_data.
diff --git a/include/asm-arm/arch-ks8695/regs-gpio.h b/include/asm-arm/arch-ks8695/regs-gpio.h
index 57fcf9fc82e4..6b95d77aea19 100644
--- a/include/asm-arm/arch-ks8695/regs-gpio.h
+++ b/include/asm-arm/arch-ks8695/regs-gpio.h
@@ -49,5 +49,7 @@
 #define IOPC_TM_FALLING         (4)             /* Falling Edge Detection */
 #define IOPC_TM_EDGE            (6)             /* Both Edge Detection */
+/* Port Data Register */
+#define IOPD_(x)                (1 << (x))      /* Signal Level of GPIO Pin x */
 #endif
diff --git a/include/asm-arm/arch-msm/board.h b/include/asm-arm/arch-msm/board.h
new file mode 100644
index 000000000000..763051f8ba14
--- /dev/null
+++ b/include/asm-arm/arch-msm/board.h
@@ -0,0 +1,37 @@
+/* linux/include/asm-arm/arch-msm/board.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARCH_MSM_BOARD_H
+#define __ASM_ARCH_MSM_BOARD_H
+#include <linux/types.h>
+/* platform device data structures */
+struct msm_mddi_platform_data
+{
+        void (*panel_power)(int on);
+        unsigned has_vsync_irq:1;
+};
+/* common init routines for use by arch/arm/mach-msm/board-*.c */
+void __init msm_add_devices(void);
+void __init msm_map_common_io(void);
+void __init msm_init_irq(void);
+void __init msm_init_gpio(void);
+#endif
diff --git a/include/asm-arm/arch-msm/debug-macro.S b/include/asm-arm/arch-msm/debug-macro.S
new file mode 100644
index 000000000000..393d5272e506
--- /dev/null
+++ b/include/asm-arm/arch-msm/debug-macro.S
@@ -0,0 +1,40 @@
+/* include/asm-arm/arch-msm7200/debug-macro.S
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <asm/hardware.h>
+#include <asm/arch/msm_iomap.h>
+        .macro  addruart,rx
+        @ see if the MMU is enabled and select appropriate base address
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1
+        ldreq   \rx, =MSM_UART1_PHYS
+        ldrne   \rx, =MSM_UART1_BASE
+        .endm
+        .macro  senduart,rd,rx
+        str     \rd, [\rx, #0x0C]
+        .endm
+        .macro  waituart,rd,rx
+        @ wait for TX_READY
+1:      ldr     \rd, [\rx, #0x08]
+        tst     \rd, #0x04
+        beq     1b
+        .endm
+        .macro  busyuart,rd,rx
+        .endm
diff --git a/include/asm-arm/arch-msm/dma.h b/include/asm-arm/arch-msm/dma.h
new file mode 100644
index 000000000000..e4b565b27b35
--- /dev/null
+++ b/include/asm-arm/arch-msm/dma.h
@@ -0,0 +1,151 @@
+/* linux/include/asm-arm/arch-msm/dma.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARCH_MSM_DMA_H
+#include <linux/list.h>
+#include <asm/arch/msm_iomap.h>
+struct msm_dmov_cmd {
+        struct list_head list;
+        unsigned int cmdptr;
+        void (*complete_func)(struct msm_dmov_cmd *cmd, unsigned int result);
+/*      void (*user_result_func)(struct msm_dmov_cmd *cmd); */
+};
+void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
+void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd);
+int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
+/* int msm_dmov_exec_cmd_etc(unsigned id, unsigned int cmdptr, int timeout, int interruptible); */
+#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
+#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
+#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
+#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
+/* only security domain 3 is available to the ARM11
+ * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM
+ */
+#define DMOV_CMD_PTR(ch)      DMOV_SD3(0x000, ch)
+#define DMOV_CMD_LIST         (0 << 29) /* does not work */
+#define DMOV_CMD_PTR_LIST     (1 << 29) /* works */
+#define DMOV_CMD_INPUT_CFG    (2 << 29) /* untested */
+#define DMOV_CMD_OUTPUT_CFG   (3 << 29) /* untested */
+#define DMOV_CMD_ADDR(addr)   ((addr) >> 3)
+#define DMOV_RSLT(ch)         DMOV_SD3(0x040, ch)
+#define DMOV_RSLT_VALID       (1 << 31) /* 0 == host has empties result fifo */
+#define DMOV_RSLT_ERROR       (1 << 3)
+#define DMOV_RSLT_FLUSH       (1 << 2)
+#define DMOV_RSLT_DONE        (1 << 1)  /* top pointer done */
+#define DMOV_RSLT_USER        (1 << 0)  /* command with FR force result */
+#define DMOV_FLUSH0(ch)       DMOV_SD3(0x080, ch)
+#define DMOV_FLUSH1(ch)       DMOV_SD3(0x0C0, ch)
+#define DMOV_FLUSH2(ch)       DMOV_SD3(0x100, ch)
+#define DMOV_FLUSH3(ch)       DMOV_SD3(0x140, ch)
+#define DMOV_FLUSH4(ch)       DMOV_SD3(0x180, ch)
+#define DMOV_FLUSH5(ch)       DMOV_SD3(0x1C0, ch)
+#define DMOV_STATUS(ch)       DMOV_SD3(0x200, ch)
+#define DMOV_STATUS_RSLT_COUNT(n)    (((n) >> 29))
+#define DMOV_STATUS_CMD_COUNT(n)     (((n) >> 27) & 3)
+#define DMOV_STATUS_RSLT_VALID       (1 << 1)
+#define DMOV_STATUS_CMD_PTR_RDY      (1 << 0)
+#define DMOV_ISR              DMOV_SD3(0x380, 0)
+#define DMOV_CONFIG(ch)       DMOV_SD3(0x300, ch)
+#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
+#define DMOV_CONFIG_FORCE_FLUSH_RSLT   (1 << 1)
+#define DMOV_CONFIG_IRQ_EN             (1 << 0)
+/* channel assignments */
+#define DMOV_NAND_CHAN        7
+#define DMOV_NAND_CRCI_CMD    5
+#define DMOV_NAND_CRCI_DATA   4
+#define DMOV_SDC1_CHAN        8
+#define DMOV_SDC1_CRCI        6
+#define DMOV_SDC2_CHAN        8
+#define DMOV_SDC2_CRCI        7
+#define DMOV_TSIF_CHAN        10
+#define DMOV_TSIF_CRCI        10
+#define DMOV_USB_CHAN         11
+/* no client rate control ifc (eg, ram) */
+#define DMOV_NONE_CRCI        0
+/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
+ * is going to walk a list of 32bit pointers as described below.  Each
+ * pointer points to a *array* of dmov_s, etc structs.  The last pointer
+ * in the list is marked with CMD_PTR_LP.  The last struct in each array
+ * is marked with CMD_LC (see below).
+ */
+#define CMD_PTR_ADDR(addr)  ((addr) >> 3)
+#define CMD_PTR_LP          (1 << 31) /* last pointer */
+#define CMD_PTR_PT          (3 << 29) /* ? */
+/* Single Item Mode */
+typedef struct {
+        unsigned cmd;
+        unsigned src;
+        unsigned dst;
+        unsigned len;
+} dmov_s;
+/* Scatter/Gather Mode */
+typedef struct {
+        unsigned cmd;
+        unsigned src_dscr;
+        unsigned dst_dscr;
+        unsigned _reserved;
+} dmov_sg;
+/* bits for the cmd field of the above structures */
+#define CMD_LC      (1 << 31)  /* last command */
+#define CMD_FR      (1 << 22)  /* force result -- does not work? */
+#define CMD_OCU     (1 << 21)  /* other channel unblock */
+#define CMD_OCB     (1 << 20)  /* other channel block */
+#define CMD_TCB     (1 << 19)  /* ? */
+#define CMD_DAH     (1 << 18)  /* destination address hold -- does not work?*/
+#define CMD_SAH     (1 << 17)  /* source address hold -- does not work? */
+#define CMD_MODE_SINGLE     (0 << 0) /* dmov_s structure used */
+#define CMD_MODE_SG         (1 << 0) /* untested */
+#define CMD_MODE_IND_SG     (2 << 0) /* untested */
+#define CMD_MODE_BOX        (3 << 0) /* untested */
+#define CMD_DST_SWAP_BYTES  (1 << 14) /* exchange each byte n with byte n+1 */
+#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
+#define CMD_DST_SWAP_WORDS  (1 << 16) /* exchange each word n with word n+1 */
+#define CMD_SRC_SWAP_BYTES  (1 << 11) /* exchange each byte n with byte n+1 */
+#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
+#define CMD_SRC_SWAP_WORDS  (1 << 13) /* exchange each word n with word n+1 */
+#define CMD_DST_CRCI(n)     (((n) & 15) << 7)
+#define CMD_SRC_CRCI(n)     (((n) & 15) << 3)
+#endif
diff --git a/include/asm-arm/arch-msm/entry-macro.S b/include/asm-arm/arch-msm/entry-macro.S
new file mode 100644
index 000000000000..ee24aece4cb0
--- /dev/null
+++ b/include/asm-arm/arch-msm/entry-macro.S
@@ -0,0 +1,38 @@
+/* include/asm-arm/arch-msm7200/entry-macro.S
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <asm/arch/msm_iomap.h>
+        .macro  disable_fiq
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        @ enable imprecise aborts
+        cpsie   a
+        mov     \base, #MSM_VIC_BASE
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ 0xD0 has irq# or old irq# if the irq has been handled
+        @ 0xD4 has irq# or -1 if none pending *but* if you just
+        @ read 0xD4 you never get the first irq for some reason
+        ldr     \irqnr, [\base, #0xD0]
+        ldr     \irqnr, [\base, #0xD4]
+        cmp     \irqnr, #0xffffffff
+        .endm
diff --git a/include/asm-arm/arch-msm/hardware.h b/include/asm-arm/arch-msm/hardware.h
new file mode 100644
index 000000000000..89af2b70182f
--- /dev/null
+++ b/include/asm-arm/arch-msm/hardware.h
@@ -0,0 +1,18 @@
+/* linux/include/asm-arm/arch-msm/hardware.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARCH_MSM_HARDWARE_H
+#endif
diff --git a/include/asm-arm/arch-msm/io.h b/include/asm-arm/arch-msm/io.h
new file mode 100644
index 000000000000..4645ae26b62a
--- /dev/null
+++ b/include/asm-arm/arch-msm/io.h
@@ -0,0 +1,33 @@
+/* include/asm-arm/arch-msm/io.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+#define __arch_ioremap __msm_ioremap
+#define __arch_iounmap __iounmap
+void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __io(a)         __io(a)
+#define __mem_pci(a)    (a)
+#endif
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h
new file mode 100644
index 000000000000..565430cfaa7e
--- /dev/null
+++ b/include/asm-arm/arch-msm/irqs.h
@@ -0,0 +1,89 @@
+/* linux/include/asm-arm/arch-msm/irqs.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARCH_MSM_IRQS_H
+/* MSM ARM11 Interrupt Numbers */
+/* See 80-VE113-1 A, pp219-221     */
+#define INT_A9_M2A_0         0
+#define INT_A9_M2A_1         1
+#define INT_A9_M2A_2         2
+#define INT_A9_M2A_3         3
+#define INT_A9_M2A_4         4
+#define INT_A9_M2A_5         5
+#define INT_A9_M2A_6         6
+#define INT_GP_TIMER_EXP     7
+#define INT_DEBUG_TIMER_EXP  8
+#define INT_UART1            9
+#define INT_UART2            10
+#define INT_UART3            11
+#define INT_UART1_RX         12
+#define INT_UART2_RX         13
+#define INT_UART3_RX         14
+#define INT_USB_OTG          15
+#define INT_MDDI_PRI         16
+#define INT_MDDI_EXT         17
+#define INT_MDDI_CLIENT      18
+#define INT_MDP              19
+#define INT_GRAPHICS         20
+#define INT_ADM_AARM         21
+#define INT_ADSP_A11         22
+#define INT_ADSP_A9_A11      23
+#define INT_SDC1_0           24
+#define INT_SDC1_1           25
+#define INT_SDC2_0           26
+#define INT_SDC2_1           27
+#define INT_KEYSENSE         28
+#define INT_TCHSCRN_SSBI     29
+#define INT_TCHSCRN1         30
+#define INT_TCHSCRN2         31
+#define INT_GPIO_GROUP1      (32 + 0)
+#define INT_GPIO_GROUP2      (32 + 1)
+#define INT_PWB_I2C          (32 + 2)
+#define INT_SOFTRESET        (32 + 3)
+#define INT_NAND_WR_ER_DONE  (32 + 4)
+#define INT_NAND_OP_DONE     (32 + 5)
+#define INT_PBUS_ARM11       (32 + 6)
+#define INT_AXI_MPU_SMI      (32 + 7)
+#define INT_AXI_MPU_EBI1     (32 + 8)
+#define INT_AD_HSSD          (32 + 9)
+#define INT_ARM11_PMU        (32 + 10)
+#define INT_ARM11_DMA        (32 + 11)
+#define INT_TSIF_IRQ         (32 + 12)
+#define INT_UART1DM_IRQ      (32 + 13)
+#define INT_UART1DM_RX       (32 + 14)
+#define INT_USB_HS           (32 + 15)
+#define INT_SDC3_0           (32 + 16)
+#define INT_SDC3_1           (32 + 17)
+#define INT_SDC4_0           (32 + 18)
+#define INT_SDC4_1           (32 + 19)
+#define INT_UART2DM_RX       (32 + 20)
+#define INT_UART2DM_IRQ      (32 + 21)
+/* 22-31 are reserved */
+#define MSM_IRQ_BIT(irq)     (1 << ((irq) & 31))
+#define NR_MSM_IRQS 64
+#define NR_GPIO_IRQS 122
+#define NR_BOARD_IRQS 64
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
+#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
+#endif
diff --git a/include/asm-arm/arch-msm/memory.h b/include/asm-arm/arch-msm/memory.h
new file mode 100644
index 000000000000..b5ce0e9ac86d
--- /dev/null
+++ b/include/asm-arm/arch-msm/memory.h
@@ -0,0 +1,27 @@
+/* linux/include/asm-arm/arch-msm/memory.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+/* physical offset of RAM */
+#define PHYS_OFFSET             UL(0x10000000)
+/* bus address and physical addresses are identical */
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+#endif
diff --git a/include/asm-arm/arch-msm/msm_iomap.h b/include/asm-arm/arch-msm/msm_iomap.h
new file mode 100644
index 000000000000..b8955cc26fec
--- /dev/null
+++ b/include/asm-arm/arch-msm/msm_iomap.h
@@ -0,0 +1,104 @@
+/* linux/include/asm-arm/arch-msm/msm_iomap.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * The MSM peripherals are spread all over across 768MB of physical
+ * space, which makes just having a simple IO_ADDRESS macro to slide
+ * them into the right virtual location rough.  Instead, we will
+ * provide a master phys->virt mapping for peripherals here.
+ *
+ */
+#ifndef __ASM_ARCH_MSM_IOMAP_H
+#define __ASM_ARCH_MSM_IOMAP_H
+#include <asm/sizes.h>
+/* Physical base address and size of peripherals.
+ * Ordered by the virtual base addresses they will be mapped at.
+ *
+ * MSM_VIC_BASE must be an value that can be loaded via a "mov"
+ * instruction, otherwise entry-macro.S will not compile.
+ *
+ * If you add or remove entries here, you'll want to edit the
+ * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
+ * changes.
+ *
+ */
+#define MSM_VIC_BASE          0xE0000000
+#define MSM_VIC_PHYS          0xC0000000
+#define MSM_VIC_SIZE          SZ_4K
+#define MSM_CSR_BASE          0xE0001000
+#define MSM_CSR_PHYS          0xC0100000
+#define MSM_CSR_SIZE          SZ_4K
+#define MSM_GPT_PHYS          MSM_CSR_PHYS
+#define MSM_GPT_BASE          MSM_CSR_BASE
+#define MSM_GPT_SIZE          SZ_4K
+#define MSM_DMOV_BASE         0xE0002000
+#define MSM_DMOV_PHYS         0xA9700000
+#define MSM_DMOV_SIZE         SZ_4K
+#define MSM_UART1_BASE        0xE0003000
+#define MSM_UART1_PHYS        0xA9A00000
+#define MSM_UART1_SIZE        SZ_4K
+#define MSM_UART2_BASE        0xE0004000
+#define MSM_UART2_PHYS        0xA9B00000
+#define MSM_UART2_SIZE        SZ_4K
+#define MSM_UART3_BASE        0xE0005000
+#define MSM_UART3_PHYS        0xA9C00000
+#define MSM_UART3_SIZE        SZ_4K
+#define MSM_I2C_BASE          0xE0006000
+#define MSM_I2C_PHYS          0xA9900000
+#define MSM_I2C_SIZE          SZ_4K
+#define MSM_GPIO1_BASE        0xE0007000
+#define MSM_GPIO1_PHYS        0xA9200000
+#define MSM_GPIO1_SIZE        SZ_4K
+#define MSM_GPIO2_BASE        0xE0008000
+#define MSM_GPIO2_PHYS        0xA9300000
+#define MSM_GPIO2_SIZE        SZ_4K
+#define MSM_HSUSB_BASE        0xE0009000
+#define MSM_HSUSB_PHYS        0xA0800000
+#define MSM_HSUSB_SIZE        SZ_4K
+#define MSM_CLK_CTL_BASE      0xE000A000
+#define MSM_CLK_CTL_PHYS      0xA8600000
+#define MSM_CLK_CTL_SIZE      SZ_4K
+#define MSM_PMDH_BASE         0xE000B000
+#define MSM_PMDH_PHYS         0xAA600000
+#define MSM_PMDH_SIZE         SZ_4K
+#define MSM_EMDH_BASE         0xE000C000
+#define MSM_EMDH_PHYS         0xAA700000
+#define MSM_EMDH_SIZE         SZ_4K
+#define MSM_MDP_BASE          0xE0010000
+#define MSM_MDP_PHYS          0xAA200000
+#define MSM_MDP_SIZE          0x000F0000
+#define MSM_SHARED_RAM_BASE   0xE0100000
+#define MSM_SHARED_RAM_PHYS   0x01F00000
+#define MSM_SHARED_RAM_SIZE   SZ_1M
+#endif
diff --git a/include/asm-arm/arch-msm/system.h b/include/asm-arm/arch-msm/system.h
new file mode 100644
index 000000000000..7c5544bdd0c7
--- /dev/null
+++ b/include/asm-arm/arch-msm/system.h
@@ -0,0 +1,23 @@
+/* linux/include/asm-arm/arch-msm/system.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <asm/hardware.h>
+void arch_idle(void);
+static inline void arch_reset(char mode)
+{
+        for (;;) ;  /* depends on IPC w/ other core */
+}
diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h
new file mode 100644
index 000000000000..154b23fb3599
--- /dev/null
+++ b/include/asm-arm/arch-msm/timex.h
@@ -0,0 +1,20 @@
+/* linux/include/asm-arm/arch-msm/timex.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARCH_MSM_TIMEX_H
+#define CLOCK_TICK_RATE         1000000
+#endif
diff --git a/include/asm-arm/arch-msm/uncompress.h b/include/asm-arm/arch-msm/uncompress.h
new file mode 100644
index 000000000000..e91ed786ffec
--- /dev/null
+++ b/include/asm-arm/arch-msm/uncompress.h
@@ -0,0 +1,36 @@
+/* linux/include/asm-arm/arch-msm/uncompress.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
+#include "hardware.h"
+static void putc(int c)
+{
+}
+static inline void flush(void)
+{
+}
+static inline void arch_decomp_setup(void)
+{
+}
+static inline void arch_decomp_wdog(void)
+{
+}
+#endif
diff --git a/include/asm-arm/arch-msm/vmalloc.h b/include/asm-arm/arch-msm/vmalloc.h
new file mode 100644
index 000000000000..60f8d910e825
--- /dev/null
+++ b/include/asm-arm/arch-msm/vmalloc.h
@@ -0,0 +1,22 @@
+/* linux/include/asm-arm/arch-msm/vmalloc.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARCH_MSM_VMALLOC_H
+#define __ASM_ARCH_MSM_VMALLOC_H
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#endif
diff --git a/include/asm-arm/arch-pxa/i2c.h b/include/asm-arm/arch-pxa/i2c.h
index e404b233d8a8..80596b013443 100644
--- a/include/asm-arm/arch-pxa/i2c.h
+++ b/include/asm-arm/arch-pxa/i2c.h
@@ -65,7 +65,13 @@ struct i2c_pxa_platform_data {
        unsigned int            slave_addr;
        struct i2c_slave_client *slave;
        unsigned int            class;
+        int                     use_pio;
 };
 extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
+#ifdef CONFIG_PXA27x
+extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info);
+#endif
 #endif
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 9c8cd9abb82b..89076c322726 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -92,11 +92,9 @@
 #if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
 #define fifo_full  fifo_full_s3c2410
 #define fifo_level fifo_level_s3c2410
-#warning 2410only
 #elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
 #define fifo_full  fifo_full_s3c24xx
 #define fifo_level fifo_level_s3c24xx
-#warning generic
 #endif
 /* include the reset of the code which will do the work */
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index c6e8d8f64938..4f291d9b7d93 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -214,6 +214,7 @@ struct s3c2410_dma_chan {
        unsigned long            dev_addr;
        unsigned long            load_timeout;
        unsigned int             flags;         /* channel flags */
+        unsigned int             hw_cfg;        /* last hw config */
        struct s3c24xx_dma_map  *map;           /* channel hw maps */
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
index 6dadf58ff984..29592c3ebf22 100644
--- a/include/asm-arm/arch-s3c2410/hardware.h
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -50,6 +50,17 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
 extern int s3c2410_gpio_getirq(unsigned int pin);
+/* s3c2410_gpio_irq2pin
+ *
+ * turn the given irq number into the corresponding GPIO number
+ *
+ * returns:
+ *      < 0 = no pin
+ *      >=0 = gpio pin number
+*/
+extern int s3c2410_gpio_irq2pin(unsigned int irq);
 #ifdef CONFIG_CPU_S3C2400
 extern int s3c2400_gpio_getirq(unsigned int pin);
@@ -87,6 +98,18 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
 extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
+/* s3c2410_gpio_getpull
+ *
+ * Read the state of the pull-up on a given pin
+ *
+ * return:
+ *      < 0 => error code
+ *        0 => enabled
+ *        1 => disabled
+*/
+extern int s3c2410_gpio_getpull(unsigned int pin);
 extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
 extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
@@ -99,6 +122,11 @@ extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
 #endif /* CONFIG_CPU_S3C2440 */
+#ifdef CONFIG_CPU_S3C2412
+extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
+#endif /* CONFIG_CPU_S3C2412 */
 #endif /* __ASSEMBLY__ */
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
index 996f65488d2d..d858b3eb5547 100644
--- a/include/asm-arm/arch-s3c2410/irqs.h
+++ b/include/asm-arm/arch-s3c2410/irqs.h
@@ -160,4 +160,7 @@
 #define NR_IRQS (IRQ_S3C2440_AC97+1)
 #endif
+/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
+#define FIQ_START               IRQ_EINT0
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index e39656b7a086..dba9df9d8713 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -138,6 +138,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
 #define S3C2412_CLKDIVN_PDIVN           (1<<2)
 #define S3C2412_CLKDIVN_HDIVN_MASK      (3<<0)
 #define S3C2421_CLKDIVN_ARMDIVN         (1<<3)
+#define S3C2412_CLKDIVN_DVSEN           (1<<4)
+#define S3C2412_CLKDIVN_HALFHCLK        (1<<5)
 #define S3C2412_CLKDIVN_USB48DIV        (1<<6)
 #define S3C2412_CLKDIVN_UARTDIV_MASK    (15<<8)
 #define S3C2412_CLKDIVN_UARTDIV_SHIFT   (8)
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
index c0748511edbc..1235df70f34e 100644
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -19,7 +19,7 @@
 #define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
 #endif
-#if defined(CONFIG_CPU_S3C2440)
+#if defined(CONFIG_CPU_S3C244X)
 #define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
 #define S3C2440_DSC1       S3C2410_GPIOREG(0xc8)
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index b693158b2d3c..0ad75d716ded 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -1133,12 +1133,16 @@
 #define S3C2412_GPBSLPCON       S3C2410_GPIOREG(0x1C)
 #define S3C2412_GPCSLPCON       S3C2410_GPIOREG(0x2C)
 #define S3C2412_GPDSLPCON       S3C2410_GPIOREG(0x3C)
-#define S3C2412_GPESLPCON       S3C2410_GPIOREG(0x4C)
 #define S3C2412_GPFSLPCON       S3C2410_GPIOREG(0x5C)
 #define S3C2412_GPGSLPCON       S3C2410_GPIOREG(0x6C)
 #define S3C2412_GPHSLPCON       S3C2410_GPIOREG(0x7C)
 /* definitions for each pin bit */
+#define S3C2412_GPIO_SLPCON_LOW  ( 0x00 )
+#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
+#define S3C2412_GPIO_SLPCON_IN   ( 0x02 )
+#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
 #define S3C2412_SLPCON_LOW(x)   ( 0x00 << ((x) * 2))
 #define S3C2412_SLPCON_HIGH(x)  ( 0x01 << ((x) * 2))
 #define S3C2412_SLPCON_IN(x)    ( 0x02 << ((x) * 2))
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
index e4d82341f7ba..312ff93b63c6 100644
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -98,16 +98,19 @@
 #define S3C2410_BANKCON_Tacp3           (0x1 << 2)
 #define S3C2410_BANKCON_Tacp4           (0x2 << 2)
 #define S3C2410_BANKCON_Tacp6           (0x3 << 2)
+#define S3C2410_BANKCON_Tacp_SHIFT      (2)
 #define S3C2410_BANKCON_Tcah0           (0x0 << 4)
 #define S3C2410_BANKCON_Tcah1           (0x1 << 4)
 #define S3C2410_BANKCON_Tcah2           (0x2 << 4)
 #define S3C2410_BANKCON_Tcah4           (0x3 << 4)
+#define S3C2410_BANKCON_Tcah_SHIFT      (4)
 #define S3C2410_BANKCON_Tcoh0           (0x0 << 6)
 #define S3C2410_BANKCON_Tcoh1           (0x1 << 6)
 #define S3C2410_BANKCON_Tcoh2           (0x2 << 6)
 #define S3C2410_BANKCON_Tcoh4           (0x3 << 6)
+#define S3C2410_BANKCON_Tcoh_SHIFT      (6)
 #define S3C2410_BANKCON_Tacc1           (0x0 << 8)
 #define S3C2410_BANKCON_Tacc2           (0x1 << 8)
@@ -117,16 +120,19 @@
 #define S3C2410_BANKCON_Tacc8           (0x5 << 8)
 #define S3C2410_BANKCON_Tacc10          (0x6 << 8)
 #define S3C2410_BANKCON_Tacc14          (0x7 << 8)
+#define S3C2410_BANKCON_Tacc_SHIFT      (8)
 #define S3C2410_BANKCON_Tcos0           (0x0 << 11)
 #define S3C2410_BANKCON_Tcos1           (0x1 << 11)
 #define S3C2410_BANKCON_Tcos2           (0x2 << 11)
 #define S3C2410_BANKCON_Tcos4           (0x3 << 11)
+#define S3C2410_BANKCON_Tcos_SHIFT      (11)
 #define S3C2410_BANKCON_Tacs0           (0x0 << 13)
 #define S3C2410_BANKCON_Tacs1           (0x1 << 13)
 #define S3C2410_BANKCON_Tacs2           (0x2 << 13)
 #define S3C2410_BANKCON_Tacs4           (0x3 << 13)
+#define S3C2410_BANKCON_Tacs_SHIFT      (13)
 #define S3C2410_BANKCON_SRAM            (0x0 << 15)
 #define S3C2400_BANKCON_EDODRAM         (0x2 << 15)
diff --git a/include/asm-arm/arch-s3c2410/regs-power.h b/include/asm-arm/arch-s3c2410/regs-power.h
index f79987be55e8..13d13b7cfe98 100644
--- a/include/asm-arm/arch-s3c2410/regs-power.h
+++ b/include/asm-arm/arch-s3c2410/regs-power.h
@@ -23,7 +23,8 @@
 #define S3C2412_INFORM2         S3C24XX_PWRREG(0x78)
 #define S3C2412_INFORM3         S3C24XX_PWRREG(0x7C)
-#define S3C2412_PWRCFG_BATF_IGNORE              (0<<0)
+#define S3C2412_PWRCFG_BATF_IRQ                 (1<<0)
+#define S3C2412_PWRCFG_BATF_IGNORE              (2<<0)
 #define S3C2412_PWRCFG_BATF_SLEEP               (3<<0)
 #define S3C2412_PWRCFG_BATF_MASK                (3<<0)
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 63891786dfa0..14de4e596f87 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -20,6 +20,9 @@
 #include <asm/plat-s3c/regs-watchdog.h>
 #include <asm/arch/regs-clock.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 void (*s3c24xx_idle)(void);
 void (*s3c24xx_reset_hook)(void);
@@ -59,6 +62,8 @@ static void arch_idle(void)
 static void
 arch_reset(char mode)
 {
+        struct clk *wdtclk;
        if (mode == 's') {
                cpu_reset(0);
        }
@@ -70,19 +75,28 @@ arch_reset(char mode)
        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
+        wdtclk = clk_get(NULL, "watchdog");
+        if (!IS_ERR(wdtclk)) {
+                clk_enable(wdtclk);
+        } else
+                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
        /* put initial values into count and data */
-        __raw_writel(0x100, S3C2410_WTCNT);
+        __raw_writel(0x80, S3C2410_WTCNT);
-        __raw_writel(0x100, S3C2410_WTDAT);
+        __raw_writel(0x80, S3C2410_WTDAT);
        /* set the watchdog to go and reset... */
        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
        /* wait for reset to assert... */
-        mdelay(5000);
+        mdelay(500);
        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+        /* delay to allow the serial port to show the message */
+        mdelay(50);
        /* we'll take a jump through zero as a poor second */
        cpu_reset(0);
 }
diff --git a/include/asm-arm/fpstate.h b/include/asm-arm/fpstate.h
index f31cda5a55ee..392eb5332323 100644
--- a/include/asm-arm/fpstate.h
+++ b/include/asm-arm/fpstate.h
@@ -17,14 +17,18 @@
 /*
 * VFP storage area has:
 *  - FPEXC, FPSCR, FPINST and FPINST2.
- *  - 16 double precision data registers
+ *  - 16 or 32 double precision data registers
- *  - an implementation-dependant word of state for FLDMX/FSTMX
+ *  - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6)
 * 
 *  FPEXC will always be non-zero once the VFP has been used in this process.
 */
 struct vfp_hard_struct {
+#ifdef CONFIG_VFPv3
+        __u64 fpregs[32];
+#else
        __u64 fpregs[16];
+#endif
 #if __LINUX_ARM_ARCH__ < 6
        __u32 fpmx_state;
 #endif
@@ -35,6 +39,7 @@ struct vfp_hard_struct {
         */
        __u32 fpinst;
        __u32 fpinst2;
 #ifdef CONFIG_SMP
        __u32 cpu;
 #endif
diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/include/asm-arm/plat-s3c24xx/dma.h
index 2c59406435e5..c78efe316fc8 100644
--- a/include/asm-arm/plat-s3c24xx/dma.h
+++ b/include/asm-arm/plat-s3c24xx/dma.h
@@ -32,6 +32,7 @@ struct s3c24xx_dma_map {
        struct s3c24xx_dma_addr  hw_addr;
        unsigned long            channels[S3C2410_DMA_CHANNELS];
+        unsigned long            channels_rx[S3C2410_DMA_CHANNELS];
 };
 struct s3c24xx_dma_selection {
@@ -41,6 +42,10 @@ struct s3c24xx_dma_selection {
        void    (*select)(struct s3c2410_dma_chan *chan,
                          struct s3c24xx_dma_map *map);
+        void    (*direction)(struct s3c2410_dma_chan *chan,
+                             struct s3c24xx_dma_map *map,
+                             enum s3c2410_dmasrc dir);
 };
 extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
diff --git a/include/asm-arm/plat-s3c24xx/irq.h b/include/asm-arm/plat-s3c24xx/irq.h
index 8af6d9579b31..45746a995343 100644
--- a/include/asm-arm/plat-s3c24xx/irq.h
+++ b/include/asm-arm/plat-s3c24xx/irq.h
@@ -15,7 +15,9 @@
 #define EXTINT_OFF (IRQ_EINT4 - 4)
+/* these are exported for arch/arm/mach-* usage */
 extern struct irq_chip s3c_irq_level_chip;
+extern struct irq_chip s3c_irq_chip;
 static inline void
 s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
diff --git a/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h b/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
new file mode 100644
index 000000000000..25d4058bcfed
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
@@ -0,0 +1,72 @@
+/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
+ *
+ * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2412 IIS register definition
+*/
+#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
+#define __ASM_ARCH_REGS_S3C2412_IIS_H
+#define S3C2412_IISCON                  (0x00)
+#define S3C2412_IISMOD                  (0x04)
+#define S3C2412_IISFIC                  (0x08)
+#define S3C2412_IISPSR                  (0x0C)
+#define S3C2412_IISTXD                  (0x10)
+#define S3C2412_IISRXD                  (0x14)
+#define S3C2412_IISCON_LRINDEX          (1 << 11)
+#define S3C2412_IISCON_TXFIFO_EMPTY     (1 << 10)
+#define S3C2412_IISCON_RXFIFO_EMPTY     (1 << 9)
+#define S3C2412_IISCON_TXFIFO_FULL      (1 << 8)
+#define S3C2412_IISCON_RXFIFO_FULL      (1 << 7)
+#define S3C2412_IISCON_TXDMA_PAUSE      (1 << 6)
+#define S3C2412_IISCON_RXDMA_PAUSE      (1 << 5)
+#define S3C2412_IISCON_TXCH_PAUSE       (1 << 4)
+#define S3C2412_IISCON_RXCH_PAUSE       (1 << 3)
+#define S3C2412_IISCON_TXDMA_ACTIVE     (1 << 2)
+#define S3C2412_IISCON_RXDMA_ACTIVE     (1 << 1)
+#define S3C2412_IISCON_IIS_ACTIVE       (1 << 0)
+#define S3C2412_IISMOD_MASTER_INTERNAL  (0 << 10)
+#define S3C2412_IISMOD_MASTER_EXTERNAL  (1 << 10)
+#define S3C2412_IISMOD_SLAVE            (2 << 10)
+#define S3C2412_IISMOD_MASTER_MASK      (3 << 10)
+#define S3C2412_IISMOD_MODE_TXONLY      (0 << 8)
+#define S3C2412_IISMOD_MODE_RXONLY      (1 << 8)
+#define S3C2412_IISMOD_MODE_TXRX        (2 << 8)
+#define S3C2412_IISMOD_MODE_MASK        (3 << 8)
+#define S3C2412_IISMOD_LR_LLOW          (0 << 7)
+#define S3C2412_IISMOD_LR_RLOW          (1 << 7)
+#define S3C2412_IISMOD_SDF_IIS          (0 << 5)
+#define S3C2412_IISMOD_SDF_MSB          (0 << 5)
+#define S3C2412_IISMOD_SDF_LSB          (0 << 5)
+#define S3C2412_IISMOD_SDF_MASK         (3 << 5)
+#define S3C2412_IISMOD_RCLK_256FS       (0 << 3)
+#define S3C2412_IISMOD_RCLK_512FS       (1 << 3)
+#define S3C2412_IISMOD_RCLK_384FS       (2 << 3)
+#define S3C2412_IISMOD_RCLK_768FS       (3 << 3)
+#define S3C2412_IISMOD_RCLK_MASK        (3 << 3)
+#define S3C2412_IISMOD_BCLK_32FS        (0 << 1)
+#define S3C2412_IISMOD_BCLK_48FS        (1 << 1)
+#define S3C2412_IISMOD_BCLK_16FS        (2 << 1)
+#define S3C2412_IISMOD_BCLK_24FS        (3 << 1)
+#define S3C2412_IISMOD_BCLK_MASK        (3 << 1)
+#define S3C2412_IISMOD_8BIT             (1 << 0)
+#define S3C2412_IISPSR_PSREN            (1 << 15)
+#define S3C2412_IISFIC_TXFLUSH          (1 << 15)
+#define S3C2412_IISFIC_RXFLUSH          (1 << 7)
+#define S3C2412_IISFIC_TXCOUNT(x)       (((x) >>  8) & 0xf)
+#define S3C2412_IISFIC_RXCOUNT(x)       (((x) >>  0) & 0xf)
+#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
index 4a499a138256..ea565b007d04 100644
--- a/include/asm-arm/plat-s3c24xx/regs-spi.h
+++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
@@ -17,6 +17,21 @@
 #define S3C2410_SPCON   (0x00)
+#define S3C2412_SPCON_RXFIFO_RB2        (0<<14)
+#define S3C2412_SPCON_RXFIFO_RB4        (1<<14)
+#define S3C2412_SPCON_RXFIFO_RB12       (2<<14)
+#define S3C2412_SPCON_RXFIFO_RB14       (3<<14)
+#define S3C2412_SPCON_TXFIFO_RB2        (0<<12)
+#define S3C2412_SPCON_TXFIFO_RB4        (1<<12)
+#define S3C2412_SPCON_TXFIFO_RB12       (2<<12)
+#define S3C2412_SPCON_TXFIFO_RB14       (3<<12)
+#define S3C2412_SPCON_RXFIFO_RESET      (1<<11) /* RxFIFO reset */
+#define S3C2412_SPCON_TXFIFO_RESET      (1<<10) /* TxFIFO reset */
+#define S3C2412_SPCON_RXFIFO_EN         (1<<9)  /* RxFIFO Enable */
+#define S3C2412_SPCON_TXFIFO_EN         (1<<8)  /* TxFIFO Enable */
+#define S3C2412_SPCON_DIRC_RX     (1<<7)
 #define S3C2410_SPCON_SMOD_DMA    (2<<5)        /* DMA mode */
 #define S3C2410_SPCON_SMOD_INT    (1<<5)        /* interrupt mode */
 #define S3C2410_SPCON_SMOD_POLL   (0<<5)        /* polling mode */
@@ -34,10 +49,19 @@
 #define S3C2410_SPSTA    (0x04)
+#define S3C2412_SPSTA_RXFIFO_AE         (1<<11)
+#define S3C2412_SPSTA_TXFIFO_AE         (1<<10)
+#define S3C2412_SPSTA_RXFIFO_ERROR      (1<<9)
+#define S3C2412_SPSTA_TXFIFO_ERROR      (1<<8)
+#define S3C2412_SPSTA_RXFIFO_FIFO       (1<<7)
+#define S3C2412_SPSTA_RXFIFO_EMPTY      (1<<6)
+#define S3C2412_SPSTA_TXFIFO_NFULL      (1<<5)
+#define S3C2412_SPSTA_TXFIFO_EMPTY      (1<<4)
 #define S3C2410_SPSTA_DCOL        (1<<2)        /* Data Collision Error */
 #define S3C2410_SPSTA_MULD        (1<<1)        /* Multi Master Error */
 #define S3C2410_SPSTA_READY       (1<<0)        /* Data Tx/Rx ready */
+#define S3C2412_SPSTA_READY_ORG   (1<<3)
 #define S3C2410_SPPIN    (0x08)
@@ -46,9 +70,13 @@
 #define S3C2400_SPPIN_nCS         (1<<1)        /* SPI Card Select */
 #define S3C2410_SPPIN_KEEP        (1<<0)        /* Master Out keep */
 #define S3C2410_SPPRE    (0x0C)
 #define S3C2410_SPTDAT   (0x10)
 #define S3C2410_SPRDAT   (0x14)
+#define S3C2412_TXFIFO   (0x18)
+#define S3C2412_RXFIFO   (0x18)
+#define S3C2412_SPFIC    (0x24)
 #endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
index bd6be9d7f772..5f9a2cb3d452 100644
--- a/include/asm-arm/vfp.h
+++ b/include/asm-arm/vfp.h
@@ -7,7 +7,11 @@
 #define FPSID                   cr0
 #define FPSCR                   cr1
+#define MVFR1                   cr6
+#define MVFR0                   cr7
 #define FPEXC                   cr8
+#define FPINST                  cr9
+#define FPINST2                 cr10
 /* FPSID bits */
 #define FPSID_IMPLEMENTER_BIT   (24)
@@ -28,6 +32,19 @@
 /* FPEXC bits */
 #define FPEXC_EX                (1 << 31)
 #define FPEXC_EN                (1 << 30)
+#define FPEXC_DEX               (1 << 29)
+#define FPEXC_FP2V              (1 << 28)
+#define FPEXC_VV                (1 << 27)
+#define FPEXC_TFV               (1 << 26)
+#define FPEXC_LENGTH_BIT        (8)
+#define FPEXC_LENGTH_MASK       (7 << FPEXC_LENGTH_BIT)
+#define FPEXC_IDF               (1 << 7)
+#define FPEXC_IXF               (1 << 4)
+#define FPEXC_UFF               (1 << 3)
+#define FPEXC_OFF               (1 << 2)
+#define FPEXC_DZF               (1 << 1)
+#define FPEXC_IOF               (1 << 0)
+#define FPEXC_TRAP_MASK         (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
 /* FPSCR bits */
 #define FPSCR_DEFAULT_NAN       (1<<25)
@@ -55,20 +72,9 @@
 #define FPSCR_IXC               (1<<4)
 #define FPSCR_IDC               (1<<7)
-/*
+/* MVFR0 bits */
- * VFP9-S specific.
+#define MVFR0_A_SIMD_BIT        (0)
- */
+#define MVFR0_A_SIMD_MASK       (0xf << MVFR0_A_SIMD_BIT)
-#define FPINST                  cr9
-#define FPINST2                 cr10
-/* FPEXC bits */
-#define FPEXC_FPV2              (1<<28)
-#define FPEXC_LENGTH_BIT        (8)
-#define FPEXC_LENGTH_MASK       (7 << FPEXC_LENGTH_BIT)
-#define FPEXC_INV               (1 << 7)
-#define FPEXC_UFC               (1 << 3)
-#define FPEXC_OFC               (1 << 2)
-#define FPEXC_IOC               (1 << 0)
 /* Bit patterns for decoding the packaged operation descriptors */
 #define VFPOPDESC_LENGTH_BIT    (9)
diff --git a/include/asm-arm/vfpmacros.h b/include/asm-arm/vfpmacros.h
index 27fe028b4e72..cccb3892e73c 100644
--- a/include/asm-arm/vfpmacros.h
+++ b/include/asm-arm/vfpmacros.h
@@ -15,19 +15,33 @@
        .endm
        @ read all the working registers back into the VFP
-        .macro  VFPFLDMIA, base
+        .macro  VFPFLDMIA, base, tmp
 #if __LINUX_ARM_ARCH__ < 6
        LDC     p11, cr0, [\base],#33*4             @ FLDMIAX \base!, {d0-d15}
 #else
        LDC     p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d0-d15}
 #endif
+#ifdef CONFIG_VFPv3
+        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
+        and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
+        cmp     \tmp, #2                            @ 32 x 64bit registers?
+        ldceql  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+        addne   \base, \base, #32*4                 @ step over unused register space
+#endif
        .endm
        @ write all the working registers out of the VFP
-        .macro  VFPFSTMIA, base
+        .macro  VFPFSTMIA, base, tmp
 #if __LINUX_ARM_ARCH__ < 6
        STC     p11, cr0, [\base],#33*4             @ FSTMIAX \base!, {d0-d15}
 #else
        STC     p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d0-d15}
 #endif
+#ifdef CONFIG_VFPv3
+        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
+        and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
+        cmp     \tmp, #2                            @ 32 x 64bit registers?
+        stceql  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+        addne   \base, \base, #32*4                 @ step over unused register space
+#endif
        .endm
diff --git a/include/asm-avr32/arch-at32ap/cpu.h b/include/asm-avr32/arch-at32ap/cpu.h
index 0dc20261c1ea..44d0bfa1f409 100644
--- a/include/asm-avr32/arch-at32ap/cpu.h
+++ b/include/asm-avr32/arch-at32ap/cpu.h
@@ -30,5 +30,6 @@
 #define cpu_is_at91sam9261()    (0)
 #define cpu_is_at91sam9263()    (0)
 #define cpu_is_at91sam9rl()     (0)
+#define cpu_is_at91cap9()       (0)
 #endif /* __ASM_ARCH_CPU_H */
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 39bdd86871cf..6ae0619d7696 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -51,7 +51,7 @@ extern unsigned long sclk_to_usecs(unsigned long sclk);
 extern unsigned long usecs_to_sclk(unsigned long usecs);
 extern void dump_bfin_process(struct pt_regs *regs);
-extern void dump_bfin_mem(void *retaddr);
+extern void dump_bfin_mem(struct pt_regs *regs);
 extern void dump_bfin_trace_buffer(void);
 extern int init_arch_irq(void);
diff --git a/include/asm-blackfin/cplb-mpu.h b/include/asm-blackfin/cplb-mpu.h
new file mode 100644
index 000000000000..75c67b99d607
--- /dev/null
+++ b/include/asm-blackfin/cplb-mpu.h
@@ -0,0 +1,61 @@
+/*
+ * File:         include/asm-blackfin/cplbinit.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#ifndef __ASM_BFIN_CPLB_MPU_H
+#define __ASM_BFIN_CPLB_MPU_H
+struct cplb_entry {
+        unsigned long data, addr;
+};
+struct mem_region {
+        unsigned long start, end;
+        unsigned long dcplb_data;
+        unsigned long icplb_data;
+};
+extern struct cplb_entry dcplb_tbl[MAX_CPLBS];
+extern struct cplb_entry icplb_tbl[MAX_CPLBS];
+extern int first_switched_icplb;
+extern int first_mask_dcplb;
+extern int first_switched_dcplb;
+extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
+extern int nr_cplb_flush;
+extern int page_mask_order;
+extern int page_mask_nelts;
+extern unsigned long *current_rwx_mask;
+extern void flush_switched_cplbs(void);
+extern void set_mask_dcplbs(unsigned long *);
+extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
+#endif /* __ASM_BFIN_CPLB_MPU_H */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 06828d77a58f..654375c2b746 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -65,7 +65,11 @@
 #define SIZE_1M 0x00100000      /* 1M */
 #define SIZE_4M 0x00400000      /* 4M */
+#ifdef CONFIG_MPU
+#define MAX_CPLBS 16
+#else
 #define MAX_CPLBS (16 * 2)
+#endif
 #define ASYNC_MEMORY_CPLB_COVERAGE      ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
                                 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index c4d0596e8e9f..0eb1c1b685a7 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -33,6 +33,12 @@
 #include <asm/blackfin.h>
 #include <asm/cplb.h>
+#ifdef CONFIG_MPU
+#include <asm/cplb-mpu.h>
+#else
 #define INITIAL_T 0x1
 #define SWITCH_T  0x2
 #define I_CPLB    0x4
@@ -79,6 +85,8 @@ extern u_long ipdt_swapcount_table[];
 extern u_long dpdt_swapcount_table[];
 #endif
+#endif /* CONFIG_MPU */
 extern unsigned long reserved_mem_dcache_on;
 extern unsigned long reserved_mem_icache_on;
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
index b469505af364..5abaa2cee8db 100644
--- a/include/asm-blackfin/dma.h
+++ b/include/asm-blackfin/dma.h
@@ -76,6 +76,9 @@ enum dma_chan_status {
 #define INTR_ON_BUF    2
 #define INTR_ON_ROW    3
+#define DMA_NOSYNC_KEEP_DMA_BUF 0
+#define DMA_SYNC_RESTART        1
 struct dmasg {
        unsigned long next_desc_addr;
        unsigned long start_addr;
@@ -157,7 +160,8 @@ void set_dma_y_count(unsigned int channel, unsigned short y_count);
 void set_dma_y_modify(unsigned int channel, short y_modify);
 void set_dma_config(unsigned int channel, unsigned short config);
 unsigned short set_bfin_dma_config(char direction, char flow_mode,
-                                   char intr_mode, char dma_mode, char width);
+                                   char intr_mode, char dma_mode, char width,
+                                   char syncmode);
 void set_dma_curr_addr(unsigned int channel, unsigned long addr);
 /* get curr status for polling */
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index 33ce98ef7e0f..d0426c108262 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -7,7 +7,7 @@
 * Description:
 *
 * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
+ *               Copyright 2004-2008 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
@@ -304,39 +304,39 @@
 **************************************************************/
 #ifndef BF548_FAMILY
-void set_gpio_dir(unsigned short, unsigned short);
+void set_gpio_dir(unsigned, unsigned short);
-void set_gpio_inen(unsigned short, unsigned short);
+void set_gpio_inen(unsigned, unsigned short);
-void set_gpio_polar(unsigned short, unsigned short);
+void set_gpio_polar(unsigned, unsigned short);
-void set_gpio_edge(unsigned short, unsigned short);
+void set_gpio_edge(unsigned, unsigned short);
-void set_gpio_both(unsigned short, unsigned short);
+void set_gpio_both(unsigned, unsigned short);
-void set_gpio_data(unsigned short, unsigned short);
+void set_gpio_data(unsigned, unsigned short);
-void set_gpio_maska(unsigned short, unsigned short);
+void set_gpio_maska(unsigned, unsigned short);
-void set_gpio_maskb(unsigned short, unsigned short);
+void set_gpio_maskb(unsigned, unsigned short);
-void set_gpio_toggle(unsigned short);
+void set_gpio_toggle(unsigned);
-void set_gpiop_dir(unsigned short, unsigned short);
+void set_gpiop_dir(unsigned, unsigned short);
-void set_gpiop_inen(unsigned short, unsigned short);
+void set_gpiop_inen(unsigned, unsigned short);
-void set_gpiop_polar(unsigned short, unsigned short);
+void set_gpiop_polar(unsigned, unsigned short);
-void set_gpiop_edge(unsigned short, unsigned short);
+void set_gpiop_edge(unsigned, unsigned short);
-void set_gpiop_both(unsigned short, unsigned short);
+void set_gpiop_both(unsigned, unsigned short);
-void set_gpiop_data(unsigned short, unsigned short);
+void set_gpiop_data(unsigned, unsigned short);
-void set_gpiop_maska(unsigned short, unsigned short);
+void set_gpiop_maska(unsigned, unsigned short);
-void set_gpiop_maskb(unsigned short, unsigned short);
+void set_gpiop_maskb(unsigned, unsigned short);
-unsigned short get_gpio_dir(unsigned short);
+unsigned short get_gpio_dir(unsigned);
-unsigned short get_gpio_inen(unsigned short);
+unsigned short get_gpio_inen(unsigned);
-unsigned short get_gpio_polar(unsigned short);
+unsigned short get_gpio_polar(unsigned);
-unsigned short get_gpio_edge(unsigned short);
+unsigned short get_gpio_edge(unsigned);
-unsigned short get_gpio_both(unsigned short);
+unsigned short get_gpio_both(unsigned);
-unsigned short get_gpio_maska(unsigned short);
+unsigned short get_gpio_maska(unsigned);
-unsigned short get_gpio_maskb(unsigned short);
+unsigned short get_gpio_maskb(unsigned);
-unsigned short get_gpio_data(unsigned short);
+unsigned short get_gpio_data(unsigned);
-unsigned short get_gpiop_dir(unsigned short);
+unsigned short get_gpiop_dir(unsigned);
-unsigned short get_gpiop_inen(unsigned short);
+unsigned short get_gpiop_inen(unsigned);
-unsigned short get_gpiop_polar(unsigned short);
+unsigned short get_gpiop_polar(unsigned);
-unsigned short get_gpiop_edge(unsigned short);
+unsigned short get_gpiop_edge(unsigned);
-unsigned short get_gpiop_both(unsigned short);
+unsigned short get_gpiop_both(unsigned);
-unsigned short get_gpiop_maska(unsigned short);
+unsigned short get_gpiop_maska(unsigned);
-unsigned short get_gpiop_maskb(unsigned short);
+unsigned short get_gpiop_maskb(unsigned);
-unsigned short get_gpiop_data(unsigned short);
+unsigned short get_gpiop_data(unsigned);
 struct gpio_port_t {
        unsigned short data;
@@ -382,8 +382,8 @@ struct gpio_port_t {
 #define PM_WAKE_LOW     0x8
 #define PM_WAKE_BOTH_EDGES      (PM_WAKE_RISING | PM_WAKE_FALLING)
-int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type);
+int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
-void gpio_pm_wakeup_free(unsigned short gpio);
+void gpio_pm_wakeup_free(unsigned gpio);
 unsigned int gpio_pm_setup(void);
 void gpio_pm_restore(void);
@@ -426,19 +426,19 @@ struct gpio_port_s {
 * MODIFICATION HISTORY :
 **************************************************************/
-int gpio_request(unsigned short, const char *);
+int gpio_request(unsigned, const char *);
-void gpio_free(unsigned short);
+void gpio_free(unsigned);
-void gpio_set_value(unsigned short gpio, unsigned short arg);
+void gpio_set_value(unsigned gpio, int arg);
-unsigned short gpio_get_value(unsigned short gpio);
+int gpio_get_value(unsigned gpio);
 #ifndef BF548_FAMILY
 #define gpio_get_value(gpio)            get_gpio_data(gpio)
 #define gpio_set_value(gpio, value)     set_gpio_data(gpio, value)
 #endif
-void gpio_direction_input(unsigned short gpio);
+int gpio_direction_input(unsigned gpio);
-void gpio_direction_output(unsigned short gpio);
+int gpio_direction_output(unsigned gpio, int value);
 #include <asm-generic/gpio.h>           /* cansleep wrappers */
 #include <asm/irq.h>
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index 0b867e6a76c4..15dbc21eed8b 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -146,7 +146,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
        if (uart->rts_pin >= 0) {
                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_output(uart->rts_pin);
+                gpio_direction_output(uart->rts_pin, 0);
        }
 #endif
 }
diff --git a/include/asm-blackfin/mach-bf527/portmux.h b/include/asm-blackfin/mach-bf527/portmux.h
index dcf001adc63c..ae4d205bfcf5 100644
--- a/include/asm-blackfin/mach-bf527/portmux.h
+++ b/include/asm-blackfin/mach-bf527/portmux.h
@@ -1,6 +1,8 @@
 #ifndef _MACH_PORTMUX_H_
 #define _MACH_PORTMUX_H_
+#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
 #define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
 #define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
 #define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index f36ff5af1b91..98209d40abba 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -7,9 +7,7 @@
 */
 /* This file shoule be up to date with:
- *  - Revision X,  March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List
+ *  - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
- *  - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List
- *  - Revision W,  March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
@@ -17,7 +15,7 @@
 /* We do not support 0.1 or 0.2 silicon - sorry */
 #if __SILICON_REVISION__ < 3
-# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2
+# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
 #endif
 #if defined(__ADSPBF531__)
@@ -251,6 +249,12 @@
 #define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
 /* Internal Voltage Regulator may not start up */
 #define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000266 (0)
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index 69b9f8e120e9..7871d4313f49 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -111,7 +111,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
        }
        if (uart->rts_pin >= 0) {
                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->rts_pin);
+                gpio_direction_input(uart->rts_pin, 0);
        }
 #endif
 }
diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h
index 137f4884acfe..685a2651dcda 100644
--- a/include/asm-blackfin/mach-bf533/portmux.h
+++ b/include/asm-blackfin/mach-bf533/portmux.h
@@ -1,6 +1,8 @@
 #ifndef _MACH_PORTMUX_H_
 #define _MACH_PORTMUX_H_
+#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
 #define P_PPI0_CLK      (P_DONTCARE)
 #define P_PPI0_FS1      (P_DONTCARE)
 #define P_PPI0_FS2      (P_DONTCARE)
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 2b66ecf489f7..746a794b3119 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,9 +7,7 @@
 */
 /* This file shoule be up to date with:
- *  - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
- *  - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
- *  - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
@@ -17,7 +15,7 @@
 /* We do not support 0.1 silicon - sorry */
 #if __SILICON_REVISION__ < 2
-# error Kernel will not work on BF537 silicon version 0.0 or 0.1
+# error will not work on BF537 silicon version 0.0 or 0.1
 #endif
 #if defined(__ADSPBF534__)
@@ -44,6 +42,8 @@
 #define ANOMALY_05000122 (1)
 /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
 #define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
+/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
+#define ANOMALY_05000167 (1)
 /* PPI_DELAY not functional in PPI modes with 0 frame syncs */
 #define ANOMALY_05000180 (1)
 /* Instruction Cache Is Not Functional */
@@ -130,6 +130,12 @@
 #define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
 /* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
 #define ANOMALY_05000322 (1)
+/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
+#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
+#define ANOMALY_05000359 (1)
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index 6fb328f5186a..86e45c379838 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -146,7 +146,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
        if (uart->rts_pin >= 0) {
                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_output(uart->rts_pin);
+                gpio_direction_output(uart->rts_pin, 0);
        }
 #endif
 }
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
index 5a3f7d3bf73d..78fee6e0f237 100644
--- a/include/asm-blackfin/mach-bf537/portmux.h
+++ b/include/asm-blackfin/mach-bf537/portmux.h
@@ -1,6 +1,8 @@
 #ifndef _MACH_PORTMUX_H_
 #define _MACH_PORTMUX_H_
+#define MAX_RESOURCES   (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE)    /* We additionally handle PORTJ */
 #define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
 #define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
 #define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index c5b63759cdee..850dc12eb7f2 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -7,7 +7,7 @@
 */
 /* This file shoule be up to date with:
- *  - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List
+ *  - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
@@ -26,47 +26,59 @@
 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
 #define ANOMALY_05000272 (1)
 /* False Hardware Error Exception when ISR context is not restored */
-#define ANOMALY_05000281 (1)
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
 /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (1)
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
 #define ANOMALY_05000310 (1)
 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
 /* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (1)
+#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
 /* External FIFO Boot Mode Is Not Functional */
-#define ANOMALY_05000325 (1)
+#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
 /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (1)
+#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (1)
+#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
 /* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (1)
+#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
 /* Host DMA Boot Mode Is Not Functional */
-#define ANOMALY_05000330 (1)
+#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
 /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (1)
+#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
 /* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (1)
+#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
 /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (1)
+#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (1)
+#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (1)
+#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
 /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (1)
+#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
 /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (1)
+#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
 /* USB Calibration Value Is Not Intialized */
-#define ANOMALY_05000346 (1)
+#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
 /* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (1)
+#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
 /* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (1)
+#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
 /* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (1)
+#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* External Memory Read Access Hangs Core With PLL Bypass */
+#define ANOMALY_05000360 (1)
+/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
+#define ANOMALY_05000365 (1)
+/* Addressing Conflict between Boot ROM and Asynchronous Memory */
+#define ANOMALY_05000369 (1)
+/* Mobile DDR Operation Not Functional */
+#define ANOMALY_05000377 (1)
+/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
+#define ANOMALY_05000378 (1)
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index f21a1620e6bd..3770aa38ee9f 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -186,7 +186,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
        if (uart->rts_pin >= 0) {
                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_output(uart->rts_pin);
+                gpio_direction_output(uart->rts_pin, 0);
        }
 #endif
 }
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index aefab3f618c1..19ddcd83c71f 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -244,39 +244,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_TWI0_RCV_DATA16()             bfin_read16(TWI0_RCV_DATA16)
 #define bfin_write_TWI0_RCV_DATA16(val)         bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI_CLKDIV()                  bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val)              bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI_CONTROL()                 bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI_CONTROL(val)             bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTRL()              bfin_read16(TWI0_SLAVE_CTRL)
-#define bfin_write_TWI_SLAVE_CTRL(val)          bfin_write16(TWI0_SLAVE_CTRL, val)
-#define bfin_read_TWI_SLAVE_STAT()              bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val)          bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR()              bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val)          bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL()              bfin_read16(TWI0_MASTER_CTRL)
-#define bfin_write_TWI_MASTER_CTL(val)          bfin_write16(TWI0_MASTER_CTRL, val)
-#define bfin_read_TWI_MASTER_STAT()             bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val)         bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR()             bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val)         bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT()                bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val)            bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK()                bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val)            bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL()                bfin_read16(TWI0_FIFO_CTRL)
-#define bfin_write_TWI_FIFO_CTL(val)            bfin_write16(TWI0_FIFO_CTRL, val)
-#define bfin_read_TWI_FIFO_STAT()               bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val)           bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8()               bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val)           bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16()              bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val)          bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8()               bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val)           bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16()              bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val)          bfin_write16(TWI0_RCV_DATA16, val)
 /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
 /* SPORT1 Registers */
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
index 32d07130200c..a7c809f29ede 100644
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ b/include/asm-blackfin/mach-bf548/defBF542.h
@@ -432,8 +432,8 @@
 #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
 #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
+#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIMEOUT  0x8        /* Data Time Out */
+#define               DAT_TIME_OUT  0x8        /* Data Time Out */
 #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
 #define                RX_OVERRUN  0x20       /* Receive Overrun */
 #define              CMD_RESP_END  0x40       /* CMD Response End */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index ecbca952985c..e46f56891e6a 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -1095,8 +1095,8 @@
 #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
 #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
+#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIMEOUT  0x8        /* Data Time Out */
+#define               DAT_TIME_OUT  0x8        /* Data Time Out */
 #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
 #define                RX_OVERRUN  0x20       /* Receive Overrun */
 #define              CMD_RESP_END  0x40       /* CMD Response End */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 319a48590c9c..08f90c21fe8a 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -1772,17 +1772,36 @@
 #define                       TRP  0x3c0000   /* Pre charge-to-active command period */
 #define                      TRAS  0x3c00000  /* Min Active-to-pre charge time */
 #define                       TRC  0x3c000000 /* Active-to-active time */
+#define DDR_TRAS(x)             ((x<<22)&TRAS)  /* DDR tRAS = (1~15) cycles */
+#define DDR_TRP(x)              ((x<<18)&TRP)   /* DDR tRP = (1~15) cycles */
+#define DDR_TRC(x)              ((x<<26)&TRC)   /* DDR tRC = (1~15) cycles */
+#define DDR_TRFC(x)             ((x<<14)&TRFC)  /* DDR tRFC = (1~15) cycles */
+#define DDR_TREFI(x)            (x&TREFI)       /* DDR tRFC = (1~15) cycles */
 /* Bit masks for EBIU_DDRCTL1 */
 #define                      TRCD  0xf        /* Active-to-Read/write delay */
-#define                       MRD  0xf0       /* Mode register set to active */
+#define                      TMRD  0xf0       /* Mode register set to active */
 #define                       TWR  0x300      /* Write Recovery time */
 #define               DDRDATWIDTH  0x3000     /* DDR data width */
 #define                  EXTBANKS  0xc000     /* External banks */
 #define               DDRDEVWIDTH  0x30000    /* DDR device width */
 #define                DDRDEVSIZE  0xc0000    /* DDR device size */
-#define                     TWWTR  0xf0000000 /* Write-to-read delay */
+#define                      TWTR  0xf0000000 /* Write-to-read delay */
+#define DDR_TWTR(x)             ((x<<28)&TWTR)  /* DDR tWTR = (1~15) cycles */
+#define DDR_TMRD(x)             ((x<<4)&TMRD)   /* DDR tMRD = (1~15) cycles */
+#define DDR_TWR(x)              ((x<<8)&TWR)    /* DDR tWR = (1~15) cycles */
+#define DDR_TRCD(x)             (x&TRCD)        /* DDR tRCD = (1~15) cycles */
+#define DDR_DATWIDTH            0x2000          /* DDR data width */
+#define EXTBANK_1               0               /* 1 external bank */
+#define EXTBANK_2               0x4000          /* 2 external banks */
+#define DEVSZ_64                0x40000         /* DDR External Bank Size = 64MB */
+#define DEVSZ_128               0x80000         /* DDR External Bank Size = 128MB */
+#define DEVSZ_256               0xc0000         /* DDR External Bank Size = 256MB */
+#define DEVSZ_512               0               /* DDR External Bank Size = 512MB */
+#define DEVWD_4                 0               /* DDR Device Width = 4 Bits    */
+#define DEVWD_8                 0x10000         /* DDR Device Width = 8 Bits    */
+#define DEVWD_16                0x20000         /* DDR Device Width = 16 Bits    */
 /* Bit masks for EBIU_DDRCTL2 */
@@ -1790,6 +1809,10 @@
 #define                CASLATENCY  0x70       /* CAS latency */
 #define                  DLLRESET  0x100      /* DLL Reset */
 #define                      REGE  0x1000     /* Register mode enable */
+#define CL_1_5                  0x50            /* DDR CAS Latency = 1.5 cycles */
+#define CL_2                    0x20            /* DDR CAS Latency = 2 cycles */
+#define CL_2_5                  0x60            /* DDR CAS Latency = 2.5 cycles */
+#define CL_3                    0x30            /* DDR CAS Latency = 3 cycles */
 /* Bit masks for EBIU_DDRCTL3 */
@@ -2257,6 +2280,10 @@
 #define                      CSEL  0x30       /* Core Select */
 #define                      SSEL  0xf        /* System Select */
+#define                 CSEL_DIV1       0x0000  /* CCLK = VCO / 1 */
+#define                 CSEL_DIV2       0x0010  /* CCLK = VCO / 2 */
+#define                 CSEL_DIV4       0x0020  /* CCLK = VCO / 4 */
+#define                 CSEL_DIV8       0x0030  /* CCLK = VCO / 8 */
 /* Bit masks for PLL_CTL */
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 9fb7bc5399a8..c34507a3f1df 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -88,7 +88,7 @@ Events         (highest priority)  EMU         0
 #define IRQ_PINT1               BFIN_IRQ(20)    /* PINT1 Interrupt */
 #define IRQ_MDMAS0              BFIN_IRQ(21)    /* MDMA Stream 0 Interrupt */
 #define IRQ_MDMAS1              BFIN_IRQ(22)    /* MDMA Stream 1 Interrupt */
-#define IRQ_WATCHDOG            BFIN_IRQ(23)    /* Watchdog Interrupt */
+#define IRQ_WATCH               BFIN_IRQ(23)    /* Watchdog Interrupt */
 #define IRQ_DMAC1_ERROR         BFIN_IRQ(24)    /* DMAC1 Status (Error) Interrupt */
 #define IRQ_SPORT2_ERROR        BFIN_IRQ(25)    /* SPORT2 Error Interrupt */
 #define IRQ_SPORT3_ERROR        BFIN_IRQ(26)    /* SPORT3 Error Interrupt */
@@ -406,7 +406,7 @@ Events         (highest priority)  EMU         0
 #define IRQ_PINT1_POS           16
 #define IRQ_MDMAS0_POS          20
 #define IRQ_MDMAS1_POS          24
-#define IRQ_WATCHDOG_POS        28
+#define IRQ_WATCH_POS           28
 /* IAR3 BIT FIELDS */
 #define IRQ_DMAC1_ERR_POS       0
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
index 0cb279e973d7..befc2903d5a5 100644
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -28,8 +28,68 @@
 * If not, write to the Free Software Foundation,
 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */
+#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
+#if (CONFIG_MEM_MT46V32M16_6T)
+#define DDR_SIZE        DEVSZ_512
+#define DDR_WIDTH       DEVWD_16
+#define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(60))
+#define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(42))
+#define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
+#define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(72))
+#define DDR_tREFI       DDR_TREFI(MIN_DDR_SCLK(7800))
+#define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
+#define DDR_tWTR        DDR_TWTR(1)
+#define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(12))
+#define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
+#endif
+#if (CONFIG_MEM_MT46V32M16_5B)
+#define DDR_SIZE        DEVSZ_512
+#define DDR_WIDTH       DEVWD_16
+#define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(55))
+#define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(40))
+#define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
+#define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(70))
+#define DDR_tREFI       DDR_TREFI(MIN_DDR_SCLK(7800))
+#define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
+#define DDR_tWTR        DDR_TWTR(2)
+#define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(10))
+#define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
+#endif
+#if (CONFIG_MEM_GENERIC_BOARD)
+#define DDR_SIZE        DEVSZ_512
+#define DDR_WIDTH       DEVWD_16
+#define DDR_tRCD        DDR_TRCD(3)
+#define DDR_tWTR        DDR_TWTR(2)
+#define DDR_tWR         DDR_TWR(2)
+#define DDR_tMRD        DDR_TMRD(2)
+#define DDR_tRP         DDR_TRP(3)
+#define DDR_tRAS        DDR_TRAS(7)
+#define DDR_tRC         DDR_TRC(10)
+#define DDR_tRFC        DDR_TRFC(12)
+#define DDR_tREFI       DDR_TREFI(1288)
+#endif
+#if (CONFIG_SCLK_HZ <= 133333333)
+#define DDR_CL          CL_2
+#elif (CONFIG_SCLK_HZ <= 166666666)
+#define DDR_CL          CL_2_5
+#else
+#define DDR_CL          CL_3
+#endif
+#define mem_DDRCTL0     (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
+#define mem_DDRCTL1     (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
+                        | DDR_tMRD | DDR_tWR | DDR_tRCD)
+#define mem_DDRCTL2     DDR_CL
-#if (CONFIG_MEM_MT46V32M16)
 #if defined CONFIG_CLKIN_HALF
 #define CLKIN_HALF       1
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
index 6b485120015f..8177a567dcdb 100644
--- a/include/asm-blackfin/mach-bf548/portmux.h
+++ b/include/asm-blackfin/mach-bf548/portmux.h
@@ -1,6 +1,8 @@
 #ifndef _MACH_PORTMUX_H_
 #define _MACH_PORTMUX_H_
+#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
 #define P_SPORT2_TFS    (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
 #define P_SPORT2_DTSEC  (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
 #define P_SPORT2_DTPRI  (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index bed956456884..0c1d46193939 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -7,7 +7,7 @@
 */
 /* This file shoule be up to date with:
- *  - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List
+ *  - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
@@ -15,7 +15,7 @@
 /* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
 #if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
+# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
 #endif
 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
@@ -208,6 +208,8 @@
 #define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
 /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
 #define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
+/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
 #define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
 /* False Hardware Error Exception When ISR Context Is Not Restored */
@@ -246,6 +248,18 @@
 #define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
 /* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
 #define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
+/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
+#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
+/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
+#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* Conflicting Column Address Widths Causes SDRAM Errors */
+#define ANOMALY_05000362 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000158 (0)
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 69b9f8e120e9..7871d4313f49 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -111,7 +111,7 @@ static void bfin_serial_hw_init(struct bfin_serial_port *uart)
        }
        if (uart->rts_pin >= 0) {
                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->rts_pin);
+                gpio_direction_input(uart->rts_pin, 0);
        }
 #endif
 }
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
index 132ad31665e3..a6ee8206efb6 100644
--- a/include/asm-blackfin/mach-bf561/portmux.h
+++ b/include/asm-blackfin/mach-bf561/portmux.h
@@ -1,6 +1,8 @@
 #ifndef _MACH_PORTMUX_H_
 #define _MACH_PORTMUX_H_
+#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
 #define P_PPI0_CLK      (P_DONTCARE)
 #define P_PPI0_FS1      (P_DONTCARE)
 #define P_PPI0_FS2      (P_DONTCARE)
diff --git a/include/asm-blackfin/mmu.h b/include/asm-blackfin/mmu.h
index 11d52f1167d0..757e43906ed4 100644
--- a/include/asm-blackfin/mmu.h
+++ b/include/asm-blackfin/mmu.h
@@ -24,7 +24,9 @@ typedef struct {
        unsigned long   exec_fdpic_loadmap;
        unsigned long   interp_fdpic_loadmap;
 #endif
+#ifdef CONFIG_MPU
+        unsigned long *page_rwx_mask;
+#endif
 } mm_context_t;
 #endif
diff --git a/include/asm-blackfin/mmu_context.h b/include/asm-blackfin/mmu_context.h
index c5c71a6aaf19..b5eb67596ad5 100644
--- a/include/asm-blackfin/mmu_context.h
+++ b/include/asm-blackfin/mmu_context.h
@@ -30,9 +30,12 @@
 #ifndef __BLACKFIN_MMU_CONTEXT_H__
 #define __BLACKFIN_MMU_CONTEXT_H__
+#include <linux/gfp.h>
+#include <linux/sched.h>
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/pgalloc.h>
+#include <asm/cplbinit.h>
 extern void *current_l1_stack_save;
 extern int nr_l1stack_tasks;
@@ -50,6 +53,12 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 static inline int
 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 {
+#ifdef CONFIG_MPU
+        unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
+        mm->context.page_rwx_mask = (unsigned long *)p;
+        memset(mm->context.page_rwx_mask, 0,
+               page_mask_nelts * 3 * sizeof(long));
+#endif
        return 0;
 }
@@ -73,6 +82,11 @@ static inline void destroy_context(struct mm_struct *mm)
                sram_free(tmp->addr);
                kfree(tmp);
        }
+#ifdef CONFIG_MPU
+        if (current_rwx_mask == mm->context.page_rwx_mask)
+                current_rwx_mask = NULL;
+        free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
+#endif
 }
 static inline unsigned long
@@ -106,9 +120,21 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
 #define deactivate_mm(tsk,mm)   do { } while (0)
-static inline void activate_mm(struct mm_struct *prev_mm,
+#define activate_mm(prev, next) switch_mm(prev, next, NULL)
-                               struct mm_struct *next_mm)
+static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
+                             struct task_struct *tsk)
 {
+        if (prev_mm == next_mm)
+                return;
+#ifdef CONFIG_MPU
+        if (prev_mm->context.page_rwx_mask == current_rwx_mask) {
+                flush_switched_cplbs();
+                set_mask_dcplbs(next_mm->context.page_rwx_mask);
+        }
+#endif
+        /* L1 stack switching.  */
        if (!next_mm->context.l1_stack_save)
                return;
        if (next_mm->context.l1_stack_save == current_l1_stack_save)
@@ -120,10 +146,36 @@ static inline void activate_mm(struct mm_struct *prev_mm,
        memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
 }
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+#ifdef CONFIG_MPU
-                             struct task_struct *tsk)
+static inline void protect_page(struct mm_struct *mm, unsigned long addr,
+                                unsigned long flags)
+{
+        unsigned long *mask = mm->context.page_rwx_mask;
+        unsigned long page = addr >> 12;
+        unsigned long idx = page >> 5;
+        unsigned long bit = 1 << (page & 31);
+        if (flags & VM_MAYREAD)
+                mask[idx] |= bit;
+        else
+                mask[idx] &= ~bit;
+        mask += page_mask_nelts;
+        if (flags & VM_MAYWRITE)
+                mask[idx] |= bit;
+        else
+                mask[idx] &= ~bit;
+        mask += page_mask_nelts;
+        if (flags & VM_MAYEXEC)
+                mask[idx] |= bit;
+        else
+                mask[idx] &= ~bit;
+}
+static inline void update_protections(struct mm_struct *mm)
 {
-        activate_mm(prev, next);
+        flush_switched_cplbs();
+        set_mask_dcplbs(mm->context.page_rwx_mask);
 }
+#endif
 #endif
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
index ee1cbf73a9ab..f0e5f940d9ca 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -45,6 +45,10 @@
 #define VEC_CPLB_I_M    (44)
 #define VEC_CPLB_I_MHIT (45)
 #define VEC_ILL_RES     (46)    /* including unvalid supervisor mode insn */
+/* The hardware reserves (63) for future use - we use it to tell our
+ * normal exception handling code we have a hardware error
+ */
+#define VEC_HWERR       (63)
 #ifndef __ASSEMBLY__
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index 2233f8f9314d..22a410b8003b 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -31,7 +31,7 @@ static inline void set_fs(mm_segment_t fs)
 #define VERIFY_READ     0
 #define VERIFY_WRITE    1
-#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size))
+#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
 static inline int is_in_rom(unsigned long addr)
 {
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
index 07ffe8b718c5..e98167358d26 100644
--- a/include/asm-blackfin/unistd.h
+++ b/include/asm-blackfin/unistd.h
@@ -369,8 +369,9 @@
 #define __NR_set_robust_list    354
 #define __NR_get_robust_list    355
 #define __NR_fallocate          356
+#define __NR_semtimedop         357
-#define __NR_syscall            357
+#define __NR_syscall            358
 #define NR_syscalls             __NR_syscall
 /* Old optional stuff no one actually uses */
diff --git a/include/asm-s390/airq.h b/include/asm-s390/airq.h
new file mode 100644
index 000000000000..41d028cb52a4
--- /dev/null
+++ b/include/asm-s390/airq.h
@@ -0,0 +1,19 @@
+/*
+ *  include/asm-s390/airq.h
+ *
+ *    Copyright IBM Corp. 2002,2007
+ *    Author(s): Ingo Adlung <adlung@de.ibm.com>
+ *               Cornelia Huck <cornelia.huck@de.ibm.com>
+ *               Arnd Bergmann <arndb@de.ibm.com>
+ *               Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
+ */
+#ifndef _ASM_S390_AIRQ_H
+#define _ASM_S390_AIRQ_H
+typedef void (*adapter_int_handler_t)(void *, void *);
+void *s390_register_adapter_interrupt(adapter_int_handler_t, void *);
+void s390_unregister_adapter_interrupt(void *);
+#endif /* _ASM_S390_AIRQ_H */
diff --git a/include/asm-s390/cio.h b/include/asm-s390/cio.h
index 2f08c16e44ad..123b557c3ff4 100644
--- a/include/asm-s390/cio.h
+++ b/include/asm-s390/cio.h
@@ -24,8 +24,8 @@
 * @fmt: format
 * @pfch: prefetch
 * @isic: initial-status interruption control
- * @alcc: adress-limit checking control
+ * @alcc: address-limit checking control
- * @ssi: supress-suspended interruption
+ * @ssi: suppress-suspended interruption
 * @zcc: zero condition code
 * @ectl: extended control
 * @pno: path not operational
diff --git a/include/asm-s390/dasd.h b/include/asm-s390/dasd.h
index 604f68fa6f56..3f002e13d024 100644
--- a/include/asm-s390/dasd.h
+++ b/include/asm-s390/dasd.h
@@ -105,7 +105,7 @@ typedef struct dasd_information_t {
 } dasd_information_t;
 /*
- * Read Subsystem Data - Perfomance Statistics
+ * Read Subsystem Data - Performance Statistics
 */ 
 typedef struct dasd_rssd_perf_stats_t {
        unsigned char  invalid:1;
diff --git a/include/asm-s390/ipl.h b/include/asm-s390/ipl.h
index 2c40fd3a137f..c1b2e50392bb 100644
--- a/include/asm-s390/ipl.h
+++ b/include/asm-s390/ipl.h
@@ -83,6 +83,8 @@ extern u32 dump_prefix_page;
 extern unsigned int zfcpdump_prefix_array[];
 extern void do_reipl(void);
+extern void do_halt(void);
+extern void do_poff(void);
 extern void ipl_save_parameters(void);
 enum {
@@ -118,7 +120,7 @@ struct ipl_info
 };
 extern struct ipl_info ipl_info;
-extern void setup_ipl_info(void);
+extern void setup_ipl(void);
 /*
 * DIAG 308 support
@@ -141,6 +143,10 @@ enum diag308_opt {
        DIAG308_IPL_OPT_DUMP    = 0x20,
 };
+enum diag308_flags {
+        DIAG308_FLAGS_LP_VALID  = 0x80,
+};
 enum diag308_rc {
        DIAG308_RC_OK   = 1,
 };
diff --git a/include/asm-s390/mmu_context.h b/include/asm-s390/mmu_context.h
index 05b842126b99..a77d4ba3c8eb 100644
--- a/include/asm-s390/mmu_context.h
+++ b/include/asm-s390/mmu_context.h
@@ -12,10 +12,15 @@
 #include <asm/pgalloc.h>
 #include <asm-generic/mm_hooks.h>
-/*
+static inline int init_new_context(struct task_struct *tsk,
- * get a new mmu context.. S390 don't know about contexts.
+                                   struct mm_struct *mm)
- */
+{
-#define init_new_context(tsk,mm)        0
+        mm->context = _ASCE_TABLE_LENGTH | _ASCE_USER_BITS;
+#ifdef CONFIG_64BIT
+        mm->context |= _ASCE_TYPE_REGION3;
+#endif
+        return 0;
+}
 #define destroy_context(mm)             do { } while (0)
@@ -27,19 +32,11 @@
 static inline void update_mm(struct mm_struct *mm, struct task_struct *tsk)
 {
-        pgd_t *pgd = mm->pgd;
+        S390_lowcore.user_asce = mm->context | __pa(mm->pgd);
-        unsigned long asce_bits;
-        /* Calculate asce bits from the first pgd table entry. */
-        asce_bits = _ASCE_TABLE_LENGTH | _ASCE_USER_BITS;
-#ifdef CONFIG_64BIT
-        asce_bits |= _ASCE_TYPE_REGION3;
-#endif
-        S390_lowcore.user_asce = asce_bits | __pa(pgd);
        if (switch_amode) {
                /* Load primary space page table origin. */
-                pgd_t *shadow_pgd = get_shadow_table(pgd) ? : pgd;
+                pgd_t *shadow_pgd = get_shadow_table(mm->pgd) ? : mm->pgd;
-                S390_lowcore.user_exec_asce = asce_bits | __pa(shadow_pgd);
+                S390_lowcore.user_exec_asce = mm->context | __pa(shadow_pgd);
                asm volatile(LCTL_OPCODE" 1,1,%0\n"
                             : : "m" (S390_lowcore.user_exec_asce) );
        } else
diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h
index 1f530f8a6280..79b9eab1a0c7 100644
--- a/include/asm-s390/pgtable.h
+++ b/include/asm-s390/pgtable.h
@@ -104,41 +104,27 @@ extern char empty_zero_page[PAGE_SIZE];
 #ifndef __ASSEMBLY__
 /*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * The vmalloc area will always be on the topmost area of the kernel
- * current 8MB value just means that there will be a 8MB "hole" after the
+ * mapping. We reserve 96MB (31bit) / 1GB (64bit) for vmalloc,
- * physical memory until the kernel virtual memory starts.  That means that
+ * which should be enough for any sane case.
- * any out-of-bounds memory accesses will hopefully be caught.
+ * By putting vmalloc at the top, we maximise the gap between physical
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * memory and vmalloc to catch misplaced memory accesses. As a side
- * area for the same reason. ;)
+ * effect, this also makes sure that 64 bit module code cannot be used
- * vmalloc area starts at 4GB to prevent syscall table entry exchanging
+ * as system call address.
- * from modules.
- */
-extern unsigned long vmalloc_end;
-#ifdef CONFIG_64BIT
-#define VMALLOC_ADDR    (max(0x100000000UL, (unsigned long) high_memory))
-#else
-#define VMALLOC_ADDR    ((unsigned long) high_memory)
-#endif
-#define VMALLOC_OFFSET  (8*1024*1024)
-#define VMALLOC_START   ((VMALLOC_ADDR + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
-#define VMALLOC_END     vmalloc_end
-/*
- * We need some free virtual space to be able to do vmalloc.
- * VMALLOC_MIN_SIZE defines the minimum size of the vmalloc
- * area. On a machine with 2GB memory we make sure that we
- * have at least 128MB free space for vmalloc. On a machine
- * with 4TB we make sure we have at least 128GB.
 */
 #ifndef __s390x__
-#define VMALLOC_MIN_SIZE        0x8000000UL
+#define VMALLOC_START   0x78000000UL
-#define VMALLOC_END_INIT        0x80000000UL
+#define VMALLOC_END     0x7e000000UL
+#define VMEM_MAP_MAX    0x80000000UL
 #else /* __s390x__ */
-#define VMALLOC_MIN_SIZE        0x2000000000UL
+#define VMALLOC_START   0x3e000000000UL
-#define VMALLOC_END_INIT        0x40000000000UL
+#define VMALLOC_END     0x3e040000000UL
+#define VMEM_MAP_MAX    0x40000000000UL
 #endif /* __s390x__ */
+#define VMEM_MAP        ((struct page *) VMALLOC_END)
+#define VMEM_MAP_SIZE   ((VMALLOC_START / PAGE_SIZE) * sizeof(struct page))
 /*
 * A 31 bit pagetable entry of S390 has following format:
 *  |   PFRA          |    |  OS  |
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
index 21d40a19355e..c86b982aef5a 100644
--- a/include/asm-s390/processor.h
+++ b/include/asm-s390/processor.h
@@ -59,9 +59,6 @@ extern void s390_adjust_jiffies(void);
 extern void print_cpu_info(struct cpuinfo_S390 *);
 extern int get_cpu_capability(unsigned int *);
-/* Lazy FPU handling on uni-processor */
-extern struct task_struct *last_task_used_math;
 /*
 * User space process size: 2GB for 31 bit, 4TB for 64 bit.
 */
@@ -95,7 +92,6 @@ struct thread_struct {
        unsigned long ksp;              /* kernel stack pointer             */
        mm_segment_t mm_segment;
        unsigned long prot_addr;        /* address of protection-excep.     */
-        unsigned int error_code;        /* error-code of last prog-excep.   */
        unsigned int trap_no;
        per_struct per_info;
        /* Used to give failing instruction back to user for ieee exceptions */
diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h
index 332ee73688fc..61f6952f2e35 100644
--- a/include/asm-s390/ptrace.h
+++ b/include/asm-s390/ptrace.h
@@ -465,6 +465,14 @@ struct user_regs_struct
 #ifdef __KERNEL__
 #define __ARCH_SYS_PTRACE       1
+/*
+ * These are defined as per linux/ptrace.h, which see.
+ */
+#define arch_has_single_step()  (1)
+struct task_struct;
+extern void user_enable_single_step(struct task_struct *);
+extern void user_disable_single_step(struct task_struct *);
 #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
 #define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
 #define regs_return_value(regs)((regs)->gprs[2])
diff --git a/include/asm-s390/qdio.h b/include/asm-s390/qdio.h
index 74db1dc10a7d..4b8ff55f680e 100644
--- a/include/asm-s390/qdio.h
+++ b/include/asm-s390/qdio.h
@@ -184,7 +184,7 @@ struct qdr {
 #endif /* QDIO_32_BIT */
        unsigned long qiba;             /* queue-information-block address */
        unsigned int  res8;             /* reserved */
-        unsigned int  qkey    :  4;     /* queue-informatio-block key */
+        unsigned int  qkey    :  4;     /* queue-information-block key */
        unsigned int  res9    : 28;     /* reserved */
 /*      union _qd {*/ /* why this? */
                struct qdesfmt0 qdf0[126];
diff --git a/include/asm-s390/rwsem.h b/include/asm-s390/rwsem.h
index 90f4eccaa290..9d2a17971805 100644
--- a/include/asm-s390/rwsem.h
+++ b/include/asm-s390/rwsem.h
@@ -91,8 +91,8 @@ struct rw_semaphore {
 #endif
 #define __RWSEM_INITIALIZER(name) \
-{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) \
+ { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait.lock), \
-  __RWSEM_DEP_MAP_INIT(name) }
+   LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) }
 #define DECLARE_RWSEM(name) \
        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
diff --git a/include/asm-s390/sclp.h b/include/asm-s390/sclp.h
index cb9faf1ea5cf..b5f2843013a3 100644
--- a/include/asm-s390/sclp.h
+++ b/include/asm-s390/sclp.h
@@ -27,7 +27,25 @@ struct sclp_ipl_info {
        char loadparm[LOADPARM_LEN];
 };
-void sclp_readinfo_early(void);
+struct sclp_cpu_entry {
+        u8 address;
+        u8 reserved0[13];
+        u8 type;
+        u8 reserved1;
+} __attribute__((packed));
+struct sclp_cpu_info {
+        unsigned int configured;
+        unsigned int standby;
+        unsigned int combined;
+        int has_cpu_type;
+        struct sclp_cpu_entry cpu[255];
+};
+int sclp_get_cpu_info(struct sclp_cpu_info *info);
+int sclp_cpu_configure(u8 cpu);
+int sclp_cpu_deconfigure(u8 cpu);
+void sclp_read_info_early(void);
 void sclp_facilities_detect(void);
 unsigned long long sclp_memory_detect(void);
 int sclp_sdias_blk_count(void);
diff --git a/include/asm-s390/smp.h b/include/asm-s390/smp.h
index 07708c07701e..c7b74326a527 100644
--- a/include/asm-s390/smp.h
+++ b/include/asm-s390/smp.h
@@ -35,8 +35,6 @@ extern void machine_restart_smp(char *);
 extern void machine_halt_smp(void);
 extern void machine_power_off_smp(void);
-extern void smp_setup_cpu_possible_map(void);
 #define NO_PROC_ID              0xFF            /* No processor magic marker */
 /*
@@ -92,6 +90,8 @@ extern void __cpu_die (unsigned int cpu);
 extern void cpu_die (void) __attribute__ ((noreturn));
 extern int __cpu_up (unsigned int cpu);
+extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *),
+        void *info, int wait);
 #endif
 #ifndef CONFIG_SMP
@@ -103,7 +103,6 @@ static inline void smp_send_stop(void)
 #define hard_smp_processor_id()         0
 #define smp_cpu_not_running(cpu)        1
-#define smp_setup_cpu_possible_map()    do { } while (0)
 #endif
 extern union save_area *zfcpdump_save_areas[NR_CPUS + 1];
diff --git a/include/asm-s390/spinlock.h b/include/asm-s390/spinlock.h
index 3fd43826fd0b..df84ae96915f 100644
--- a/include/asm-s390/spinlock.h
+++ b/include/asm-s390/spinlock.h
@@ -53,44 +53,48 @@ _raw_compare_and_swap(volatile unsigned int *lock,
 */
 #define __raw_spin_is_locked(x) ((x)->owner_cpu != 0)
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
 #define __raw_spin_unlock_wait(lock) \
        do { while (__raw_spin_is_locked(lock)) \
                 _raw_spin_relax(lock); } while (0)
-extern void _raw_spin_lock_wait(raw_spinlock_t *, unsigned int pc);
+extern void _raw_spin_lock_wait(raw_spinlock_t *);
-extern int _raw_spin_trylock_retry(raw_spinlock_t *, unsigned int pc);
+extern void _raw_spin_lock_wait_flags(raw_spinlock_t *, unsigned long flags);
+extern int _raw_spin_trylock_retry(raw_spinlock_t *);
 extern void _raw_spin_relax(raw_spinlock_t *lock);
 static inline void __raw_spin_lock(raw_spinlock_t *lp)
 {
-        unsigned long pc = 1 | (unsigned long) __builtin_return_address(0);
        int old;
        old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
-        if (likely(old == 0)) {
+        if (likely(old == 0))
-                lp->owner_pc = pc;
                return;
-        }
+        _raw_spin_lock_wait(lp);
-        _raw_spin_lock_wait(lp, pc);
+}
+static inline void __raw_spin_lock_flags(raw_spinlock_t *lp,
+                                         unsigned long flags)
+{
+        int old;
+        old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
+        if (likely(old == 0))
+                return;
+        _raw_spin_lock_wait_flags(lp, flags);
 }
 static inline int __raw_spin_trylock(raw_spinlock_t *lp)
 {
-        unsigned long pc = 1 | (unsigned long) __builtin_return_address(0);
        int old;
        old = _raw_compare_and_swap(&lp->owner_cpu, 0, ~smp_processor_id());
-        if (likely(old == 0)) {
+        if (likely(old == 0))
-                lp->owner_pc = pc;
                return 1;
-        }
+        return _raw_spin_trylock_retry(lp);
-        return _raw_spin_trylock_retry(lp, pc);
 }
 static inline void __raw_spin_unlock(raw_spinlock_t *lp)
 {
-        lp->owner_pc = 0;
        _raw_compare_and_swap(&lp->owner_cpu, lp->owner_cpu, 0);
 }
                
diff --git a/include/asm-s390/spinlock_types.h b/include/asm-s390/spinlock_types.h
index b7ac13f7aa37..654abc40de04 100644
--- a/include/asm-s390/spinlock_types.h
+++ b/include/asm-s390/spinlock_types.h
@@ -7,7 +7,6 @@
 typedef struct {
        volatile unsigned int owner_cpu;
-        volatile unsigned int owner_pc;
 } __attribute__ ((aligned (4))) raw_spinlock_t;
 #define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
diff --git a/include/asm-s390/tlbflush.h b/include/asm-s390/tlbflush.h
index a69bd2490d52..70fa5ae58180 100644
--- a/include/asm-s390/tlbflush.h
+++ b/include/asm-s390/tlbflush.h
@@ -42,11 +42,11 @@ static inline void __tlb_flush_global(void)
 /*
 * Flush all tlb entries of a page table on all cpus.
 */
-static inline void __tlb_flush_idte(pgd_t *pgd)
+static inline void __tlb_flush_idte(unsigned long asce)
 {
        asm volatile(
                "       .insn   rrf,0xb98e0000,0,%0,%1,0"
-                : : "a" (2048), "a" (__pa(pgd) & PAGE_MASK) : "cc" );
+                : : "a" (2048), "a" (asce) : "cc" );
 }
 static inline void __tlb_flush_mm(struct mm_struct * mm)
@@ -61,11 +61,11 @@ static inline void __tlb_flush_mm(struct mm_struct * mm)
         * only ran on the local cpu.
         */
        if (MACHINE_HAS_IDTE) {
-                pgd_t *shadow_pgd = get_shadow_table(mm->pgd);
+                pgd_t *shadow = get_shadow_table(mm->pgd);
-                if (shadow_pgd)
+                if (shadow)
-                        __tlb_flush_idte(shadow_pgd);
+                        __tlb_flush_idte((unsigned long) shadow | mm->context);
-                __tlb_flush_idte(mm->pgd);
+                __tlb_flush_idte((unsigned long) mm->pgd | mm->context);
                return;
        }
        preempt_disable();
@@ -106,9 +106,23 @@ static inline void __tlb_flush_mm_cond(struct mm_struct * mm)
 */
 #define flush_tlb()                             do { } while (0)
 #define flush_tlb_all()                         do { } while (0)
-#define flush_tlb_mm(mm)                        __tlb_flush_mm_cond(mm)
 #define flush_tlb_page(vma, addr)               do { } while (0)
-#define flush_tlb_range(vma, start, end)        __tlb_flush_mm_cond(mm)
-#define flush_tlb_kernel_range(start, end)      __tlb_flush_mm(&init_mm)
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+        __tlb_flush_mm_cond(mm);
+}
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+                                   unsigned long start, unsigned long end)
+{
+        __tlb_flush_mm_cond(vma->vm_mm);
+}
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                          unsigned long end)
+{
+        __tlb_flush_mm(&init_mm);
+}
 #endif /* _S390_TLBFLUSH_H */
diff --git a/include/asm-s390/zcrypt.h b/include/asm-s390/zcrypt.h
index a5dada617751..f228f1b86877 100644
--- a/include/asm-s390/zcrypt.h
+++ b/include/asm-s390/zcrypt.h
@@ -117,7 +117,7 @@ struct CPRBX {
        unsigned char   padx004[16 - sizeof (char *)];
        unsigned char * req_extb;       /* request extension block 'addr'*/
        unsigned char   padx005[16 - sizeof (char *)];
-        unsigned char * rpl_extb;       /* reply extension block 'addres'*/
+        unsigned char * rpl_extb;       /* reply extension block 'address'*/
        unsigned short  ccp_rtcode;     /* server return code            */
        unsigned short  ccp_rscode;     /* server reason code            */
        unsigned int    mac_data_len;   /* Mac Data Length               */
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index bd20a4e8663a..49b7a4c31a6d 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -143,7 +143,6 @@ enum rq_cmd_type_bits {
         * use REQ_TYPE_SPECIAL and use rq->cmd[0] with the range of driver
         * private REQ_LB opcodes to differentiate what type of request this is
         */
-        REQ_TYPE_ATA_CMD,
        REQ_TYPE_ATA_TASKFILE,
        REQ_TYPE_ATA_PC,
 };
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
index c7a51a196f51..f922b060158b 100644
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -33,23 +33,13 @@
 #define I2C_DRIVERID_MSP3400     1
 #define I2C_DRIVERID_TUNER       2
-#define I2C_DRIVERID_VIDEOTEX    3      /* please rename                */
 #define I2C_DRIVERID_TDA8425     4      /* stereo sound processor       */
 #define I2C_DRIVERID_TEA6420     5      /* audio matrix switch          */
 #define I2C_DRIVERID_TEA6415C    6      /* video matrix switch          */
 #define I2C_DRIVERID_TDA9840     7      /* stereo sound processor       */
 #define I2C_DRIVERID_SAA7111A    8      /* video input processor        */
-#define I2C_DRIVERID_SAA5281     9      /* videotext decoder            */
-#define I2C_DRIVERID_SAA7112    10      /* video decoder, image scaler  */
-#define I2C_DRIVERID_SAA7120    11      /* video encoder                */
-#define I2C_DRIVERID_SAA7121    12      /* video encoder                */
 #define I2C_DRIVERID_SAA7185B   13      /* video encoder                */
-#define I2C_DRIVERID_CH7003     14      /* digital pc to tv encoder     */
-#define I2C_DRIVERID_PCF8574A   15      /* i2c expander - 8 bit in/out  */
-#define I2C_DRIVERID_PCF8582C   16      /* eeprom                       */
-#define I2C_DRIVERID_AT24Cxx    17      /* eeprom 1/2/4/8/16 K          */
 #define I2C_DRIVERID_TEA6300    18      /* audio mixer                  */
-#define I2C_DRIVERID_BT829      19      /* pc to tv encoder             */
 #define I2C_DRIVERID_TDA9850    20      /* audio mixer                  */
 #define I2C_DRIVERID_TDA9855    21      /* audio mixer                  */
 #define I2C_DRIVERID_SAA7110    22      /* video decoder                */
@@ -60,42 +50,19 @@
 #define I2C_DRIVERID_TDA7432    27      /* Stereo sound processor       */
 #define I2C_DRIVERID_TVMIXER    28      /* Mixer driver for tv cards    */
 #define I2C_DRIVERID_TVAUDIO    29      /* Generic TV sound driver      */
-#define I2C_DRIVERID_DPL3518    30      /* Dolby decoder chip           */
 #define I2C_DRIVERID_TDA9873    31      /* TV sound decoder chip        */
 #define I2C_DRIVERID_TDA9875    32      /* TV sound decoder chip        */
 #define I2C_DRIVERID_PIC16C54_PV9 33    /* Audio mux/ir receiver        */
-#define I2C_DRIVERID_SBATT      34     /* Smart Battery Device          */
-#define I2C_DRIVERID_SBS        35     /* SB System Manager             */
-#define I2C_DRIVERID_VES1893    36     /* VLSI DVB-S decoder            */
-#define I2C_DRIVERID_VES1820    37     /* VLSI DVB-C decoder            */
-#define I2C_DRIVERID_SAA7113    38     /* video decoder                 */
-#define I2C_DRIVERID_TDA8444    39     /* octuple 6-bit DAC             */
 #define I2C_DRIVERID_BT819      40     /* video decoder                 */
 #define I2C_DRIVERID_BT856      41     /* video encoder                 */
 #define I2C_DRIVERID_VPX3220    42     /* video decoder+vbi/vtxt        */
-#define I2C_DRIVERID_DRP3510    43     /* ADR decoder (Astra Radio)     */
-#define I2C_DRIVERID_SP5055     44     /* Satellite tuner               */
-#define I2C_DRIVERID_STV0030    45     /* Multipurpose switch           */
-#define I2C_DRIVERID_SAA7108    46     /* video decoder, image scaler   */
-#define I2C_DRIVERID_DS1307     47     /* DS1307 real time clock        */
 #define I2C_DRIVERID_ADV7175    48     /* ADV 7175/7176 video encoder   */
 #define I2C_DRIVERID_SAA7114    49      /* video decoder                */
-#define I2C_DRIVERID_ZR36120    50     /* Zoran 36120 video encoder     */
-#define I2C_DRIVERID_24LC32A    51      /* Microchip 24LC32A 32k EEPROM */
-#define I2C_DRIVERID_STM41T00   52      /* real time clock              */
-#define I2C_DRIVERID_UDA1342    53      /* UDA1342 audio codec          */
 #define I2C_DRIVERID_ADV7170    54      /* video encoder                */
-#define I2C_DRIVERID_MAX1617    56      /* temp sensor                  */
 #define I2C_DRIVERID_SAA7191    57      /* video decoder                */
 #define I2C_DRIVERID_INDYCAM    58      /* SGI IndyCam                  */
-#define I2C_DRIVERID_BT832      59      /* CMOS camera video processor  */
-#define I2C_DRIVERID_TDA9887    60      /* TDA988x IF-PLL demodulator   */
 #define I2C_DRIVERID_OVCAMCHIP  61      /* OmniVision CMOS image sens.  */
-#define I2C_DRIVERID_TDA7313    62      /* TDA7313 audio processor      */
 #define I2C_DRIVERID_MAX6900    63      /* MAX6900 real-time clock      */
-#define I2C_DRIVERID_SAA7114H   64      /* video decoder                */
-#define I2C_DRIVERID_DS1374     65      /* DS1374 real time clock       */
 #define I2C_DRIVERID_TDA9874    66      /* TV sound decoder             */
 #define I2C_DRIVERID_SAA6752HS  67      /* MPEG2 encoder                */
 #define I2C_DRIVERID_TVEEPROM   68      /* TV EEPROM                    */
@@ -114,7 +81,6 @@
 #define I2C_DRIVERID_DS1672     81      /* Dallas/Maxim DS1672 RTC      */
 #define I2C_DRIVERID_X1205      82      /* Xicor/Intersil X1205 RTC     */
 #define I2C_DRIVERID_PCF8563    83      /* Philips PCF8563 RTC          */
-#define I2C_DRIVERID_RS5C372    84      /* Ricoh RS5C372 RTC            */
 #define I2C_DRIVERID_BT866      85      /* Conexant bt866 video encoder */
 #define I2C_DRIVERID_KS0127     86      /* Samsung ks0127 video decoder */
 #define I2C_DRIVERID_TLV320AIC23B 87    /* TI TLV320AIC23B audio codec  */
@@ -129,8 +95,6 @@
 #define I2C_DRIVERID_CS5345     96      /* cs5345 audio processor       */
 #define I2C_DRIVERID_I2CDEV     900
-#define I2C_DRIVERID_ARP        902    /* SMBus ARP Client              */
-#define I2C_DRIVERID_ALERT      903    /* SMBus Alert Responder Client  */
 /* IDs --   Use DRIVERIDs 1000-1999 for sensors.
   These were originally in sensors.h in the lm_sensors package */
@@ -176,24 +140,16 @@
 /* --- Bit algorithm adapters                                           */
 #define I2C_HW_B_LP             0x010000 /* Parallel port Philips style */
-#define I2C_HW_B_SER            0x010002 /* Serial line interface */
 #define I2C_HW_B_BT848          0x010005 /* BT848 video boards */
-#define I2C_HW_B_WNV            0x010006 /* Winnov Videums */
 #define I2C_HW_B_VIA            0x010007 /* Via vt82c586b */
 #define I2C_HW_B_HYDRA          0x010008 /* Apple Hydra Mac I/O */
 #define I2C_HW_B_G400           0x010009 /* Matrox G400 */
 #define I2C_HW_B_I810           0x01000a /* Intel I810 */
 #define I2C_HW_B_VOO            0x01000b /* 3dfx Voodoo 3 / Banshee */
-#define I2C_HW_B_PPORT          0x01000c /* Primitive parallel port adapter */
-#define I2C_HW_B_SAVG           0x01000d /* Savage 4 */
 #define I2C_HW_B_SCX200         0x01000e /* Nat'l Semi SCx200 I2C */
 #define I2C_HW_B_RIVA           0x010010 /* Riva based graphics cards */
 #define I2C_HW_B_IOC            0x010011 /* IOC bit-wiggling */
-#define I2C_HW_B_TSUNA          0x010012 /* DEC Tsunami chipset */
-#define I2C_HW_B_OMAHA          0x010014 /* Omaha I2C interface (ARM) */
-#define I2C_HW_B_GUIDE          0x010015 /* Guide bit-basher */
 #define I2C_HW_B_IXP2000        0x010016 /* GPIO on IXP2000 systems */
-#define I2C_HW_B_IXP4XX         0x010017 /* GPIO on IXP4XX systems */
 #define I2C_HW_B_S3VIA          0x010018 /* S3Via ProSavage adapter */
 #define I2C_HW_B_ZR36067        0x010019 /* Zoran-36057/36067 based boards */
 #define I2C_HW_B_PCILYNX        0x01001a /* TI PCILynx I2C adapter */
@@ -207,22 +163,11 @@
 #define I2C_HW_B_CX23885        0x010022 /* conexant 23885 based tv cards (bus1) */
 /* --- PCF 8584 based algorithms                                        */
-#define I2C_HW_P_LP             0x020000 /* Parallel port interface */
-#define I2C_HW_P_ISA            0x020001 /* generic ISA Bus inteface card */
 #define I2C_HW_P_ELEK           0x020002 /* Elektor ISA Bus inteface card */
 /* --- PCA 9564 based algorithms */
 #define I2C_HW_A_ISA            0x1a0000 /* generic ISA Bus interface card */
-/* --- ACPI Embedded controller algorithms                              */
-#define I2C_HW_ACPI_EC          0x1f0000
-/* --- MPC824x PowerPC adapters                                         */
-#define I2C_HW_MPC824X          0x100001 /* Motorola 8240 / 8245 */
-/* --- MPC8xx PowerPC adapters                                          */
-#define I2C_HW_MPC8XX_EPON      0x110000 /* Eponymous MPC8xx I2C adapter */
 /* --- PowerPC on-chip adapters                                         */
 #define I2C_HW_OCP              0x120000 /* IBM on-chip I2C adapter */
@@ -231,7 +176,6 @@
 /* --- SGI adapters                                                     */
 #define I2C_HW_SGI_VINO         0x160000
-#define I2C_HW_SGI_MACE         0x160001
 /* --- XSCALE on-chip adapters                          */
 #define I2C_HW_IOP3XX           0x140000
@@ -255,17 +199,10 @@
 #define I2C_HW_SMBUS_W9968CF    0x04000d
 #define I2C_HW_SMBUS_OV511      0x04000e /* OV511(+) USB 1.1 webcam ICs */
 #define I2C_HW_SMBUS_OV518      0x04000f /* OV518(+) USB 1.1 webcam ICs */
-#define I2C_HW_SMBUS_OV519      0x040010 /* OV519 USB 1.1 webcam IC */
 #define I2C_HW_SMBUS_OVFX2      0x040011 /* Cypress/OmniVision FX2 webcam */
 #define I2C_HW_SMBUS_CAFE       0x040012 /* Marvell 88ALP01 "CAFE" cam  */
 #define I2C_HW_SMBUS_ALI1563    0x040013
-/* --- ISA pseudo-adapter                                               */
-#define I2C_HW_ISA              0x050000
-/* --- IPMB adapter                                             */
-#define I2C_HW_IPMB             0x0c0000
 /* --- MCP107 adapter */
 #define I2C_HW_MPC107           0x0d0000
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index a100c9f8eb7c..76014f8f3c60 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -140,7 +140,6 @@ struct i2c_driver {
        int (*command)(struct i2c_client *client,unsigned int cmd, void *arg);
        struct device_driver driver;
-        struct list_head list;
 };
 #define to_i2c_driver(d) container_of(d, struct i2c_driver, driver)
@@ -155,12 +154,11 @@ struct i2c_driver {
 *      generic enough to hide second-sourcing and compatible revisions.
 * @adapter: manages the bus segment hosting this I2C device
 * @driver: device's driver, hence pointer to access routines
- * @usage_count: counts current number of users of this client
 * @dev: Driver model device node for the slave.
 * @irq: indicates the IRQ generated by this device (if any)
 * @driver_name: Identifies new-style driver used with this device; also
 *      used as the module name for hotplug/coldplug modprobe support.
- * @list: list of active/busy clients
+ * @list: list of active/busy clients (DEPRECATED)
 * @released: used to synchronize client releases & detaches and references
 *
 * An i2c_client identifies a single device (i.e. chip) connected to an
@@ -175,16 +173,16 @@ struct i2c_client {
        char name[I2C_NAME_SIZE];
        struct i2c_adapter *adapter;    /* the adapter we sit on        */
        struct i2c_driver *driver;      /* and our access routines      */
-        int usage_count;                /* How many accesses currently  */
-                                        /* to the client                */
        struct device dev;              /* the device structure         */
        int irq;                        /* irq issued by device (or -1) */
        char driver_name[KOBJ_NAME_LEN];
-        struct list_head list;
+        struct list_head list;          /* DEPRECATED */
        struct completion released;
 };
 #define to_i2c_client(d) container_of(d, struct i2c_client, dev)
+extern struct i2c_client *i2c_verify_client(struct device *dev);
 static inline struct i2c_client *kobj_to_i2c_client(struct kobject *kobj)
 {
        struct device * const dev = container_of(kobj, struct device, kobj);
@@ -261,6 +259,12 @@ i2c_new_probed_device(struct i2c_adapter *adap,
                      struct i2c_board_info *info,
                      unsigned short const *addr_list);
+/* For devices that use several addresses, use i2c_new_dummy() to make
+ * client handles for the extra addresses.
+ */
+extern struct i2c_client *
+i2c_new_dummy(struct i2c_adapter *adap, u16 address, const char *type);
 extern void i2c_unregister_device(struct i2c_client *);
 /* Mainboard arch_initcall() code should register all its I2C devices.
@@ -319,8 +323,7 @@ struct i2c_adapter {
        struct device dev;              /* the adapter device */
        int nr;
-        struct list_head clients;
+        struct list_head clients;       /* DEPRECATED */
-        struct list_head list;
        char name[48];
        struct completion dev_released;
 };
@@ -357,10 +360,10 @@ static inline void i2c_set_adapdata (struct i2c_adapter *dev, void *data)
 * command line
 */
 struct i2c_client_address_data {
-        unsigned short *normal_i2c;
+        const unsigned short *normal_i2c;
-        unsigned short *probe;
+        const unsigned short *probe;
-        unsigned short *ignore;
+        const unsigned short *ignore;
-        unsigned short **forces;
+        const unsigned short * const *forces;
 };
 /* Internal numbers to terminate lists */
@@ -389,11 +392,8 @@ static inline int i2c_add_driver(struct i2c_driver *driver)
 extern int i2c_attach_client(struct i2c_client *);
 extern int i2c_detach_client(struct i2c_client *);
-/* Should be used to make sure that client-struct is valid and that it
+extern struct i2c_client *i2c_use_client(struct i2c_client *client);
-   is okay to access the i2c-client.
+extern void i2c_release_client(struct i2c_client *client);
-   returns -ENODEV if client has gone in the meantime */
-extern int i2c_use_client(struct i2c_client *);
-extern int i2c_release_client(struct i2c_client *);
 /* call the i2c_client->command() of all attached clients with
 * the given arguments */
@@ -405,7 +405,7 @@ extern void i2c_clients_command(struct i2c_adapter *adap,
 * specific address (unless a 'force' matched);
 */
 extern int i2c_probe(struct i2c_adapter *adapter,
-                struct i2c_client_address_data *address_data,
+                const struct i2c_client_address_data *address_data,
                int (*found_proc) (struct i2c_adapter *, int, int));
 extern struct i2c_adapter* i2c_get_adapter(int id);
@@ -598,104 +598,93 @@ I2C_CLIENT_MODULE_PARM(probe, "List of adapter,address pairs to scan "	\
                       "additionally");                                 \
 I2C_CLIENT_MODULE_PARM(ignore, "List of adapter,address pairs not to "  \
                       "scan");                                         \
-static struct i2c_client_address_data addr_data = {                     \
+const static struct i2c_client_address_data addr_data = {               \
        .normal_i2c     = normal_i2c,                                   \
        .probe          = probe,                                        \
        .ignore         = ignore,                                       \
        .forces         = forces,                                       \
 }
+#define I2C_CLIENT_FORCE_TEXT \
+        "List of adapter,address pairs to boldly assume to be present"
 /* These are the ones you want to use in your own drivers. Pick the one
   which matches the number of devices the driver differenciates between. */
-#define I2C_CLIENT_INSMOD \
+#define I2C_CLIENT_INSMOD                                               \
-  I2C_CLIENT_MODULE_PARM(force, \
+I2C_CLIENT_MODULE_PARM(force, I2C_CLIENT_FORCE_TEXT);                   \
-                      "List of adapter,address pairs to boldly assume " \
+static const unsigned short * const forces[] = { force, NULL };         \
-                      "to be present"); \
-        static unsigned short *forces[] = {                             \
-                        force,                                          \
-                        NULL                                            \
-                };                                                      \
 I2C_CLIENT_INSMOD_COMMON
 #define I2C_CLIENT_INSMOD_1(chip1)                                      \
 enum chips { any_chip, chip1 };                                         \
-I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+I2C_CLIENT_MODULE_PARM(force, I2C_CLIENT_FORCE_TEXT);                   \
-                       "boldly assume to be present");                  \
 I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
-static unsigned short *forces[] = { force, force_##chip1, NULL };       \
+static const unsigned short * const forces[] =  { force,                \
+        force_##chip1, NULL };                                          \
 I2C_CLIENT_INSMOD_COMMON
 #define I2C_CLIENT_INSMOD_2(chip1, chip2)                               \
 enum chips { any_chip, chip1, chip2 };                                  \
-I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+I2C_CLIENT_MODULE_PARM(force, I2C_CLIENT_FORCE_TEXT);                   \
-                       "boldly assume to be present");                  \
 I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
-static unsigned short *forces[] = { force, force_##chip1,               \
+static const unsigned short * const forces[] =  { force,                \
-                                    force_##chip2, NULL };              \
+        force_##chip1, force_##chip2, NULL };                           \
 I2C_CLIENT_INSMOD_COMMON
 #define I2C_CLIENT_INSMOD_3(chip1, chip2, chip3)                        \
 enum chips { any_chip, chip1, chip2, chip3 };                           \
-I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+I2C_CLIENT_MODULE_PARM(force, I2C_CLIENT_FORCE_TEXT);                   \
-                       "boldly assume to be present");                  \
 I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
-static unsigned short *forces[] = { force, force_##chip1,               \
+static const unsigned short * const forces[] =  { force,                \
-                                    force_##chip2, force_##chip3,       \
+        force_##chip1, force_##chip2, force_##chip3, NULL };            \
-                                    NULL };                             \
 I2C_CLIENT_INSMOD_COMMON
 #define I2C_CLIENT_INSMOD_4(chip1, chip2, chip3, chip4)                 \
 enum chips { any_chip, chip1, chip2, chip3, chip4 };                    \
-I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+I2C_CLIENT_MODULE_PARM(force, I2C_CLIENT_FORCE_TEXT);                   \
-                       "boldly assume to be present");                  \
 I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip4);                                    \
-static unsigned short *forces[] = { force, force_##chip1,               \
+static const unsigned short * const forces[] =  { force,                \
-                                    force_##chip2, force_##chip3,       \
+        force_##chip1, force_##chip2, force_##chip3,                    \
-                                    force_##chip4, NULL};               \
+        force_##chip4, NULL};                                           \
 I2C_CLIENT_INSMOD_COMMON
 #define I2C_CLIENT_INSMOD_5(chip1, chip2, chip3, chip4, chip5)          \
 enum chips { any_chip, chip1, chip2, chip3, chip4, chip5 };             \
-I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+I2C_CLIENT_MODULE_PARM(force, I2C_CLIENT_FORCE_TEXT);                   \
-                       "boldly assume to be present");                  \
 I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip4);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip5);                                    \
-static unsigned short *forces[] = { force, force_##chip1,               \
+static const unsigned short * const forces[] = { force,                 \
-                                    force_##chip2, force_##chip3,       \
+        force_##chip1, force_##chip2, force_##chip3,                    \
-                                    force_##chip4, force_##chip5,       \
+        force_##chip4, force_##chip5, NULL };                           \
-                                    NULL };                             \
 I2C_CLIENT_INSMOD_COMMON
 #define I2C_CLIENT_INSMOD_6(chip1, chip2, chip3, chip4, chip5, chip6)   \
 enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6 };      \
-I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+I2C_CLIENT_MODULE_PARM(force, I2C_CLIENT_FORCE_TEXT);                   \
-                       "boldly assume to be present");                  \
 I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip4);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip5);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip6);                                    \
-static unsigned short *forces[] = { force, force_##chip1,               \
+static const unsigned short * const forces[] = { force,                 \
-                                    force_##chip2, force_##chip3,       \
+        force_##chip1, force_##chip2, force_##chip3,                    \
-                                    force_##chip4, force_##chip5,       \
+        force_##chip4, force_##chip5, force_##chip6, NULL };            \
-                                    force_##chip6, NULL };              \
 I2C_CLIENT_INSMOD_COMMON
 #define I2C_CLIENT_INSMOD_7(chip1, chip2, chip3, chip4, chip5, chip6, chip7) \
 enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6,        \
             chip7 };                                                   \
-I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+I2C_CLIENT_MODULE_PARM(force, I2C_CLIENT_FORCE_TEXT);                   \
-                       "boldly assume to be present");                  \
 I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
@@ -703,18 +692,16 @@ I2C_CLIENT_MODULE_PARM_FORCE(chip4);					\
 I2C_CLIENT_MODULE_PARM_FORCE(chip5);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip6);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip7);                                    \
-static unsigned short *forces[] = { force, force_##chip1,               \
+static const unsigned short * const forces[] = { force,                 \
-                                    force_##chip2, force_##chip3,       \
+        force_##chip1, force_##chip2, force_##chip3,                    \
-                                    force_##chip4, force_##chip5,       \
+        force_##chip4, force_##chip5, force_##chip6,                    \
-                                    force_##chip6, force_##chip7,       \
+        force_##chip7, NULL };                                          \
-                                    NULL };                             \
 I2C_CLIENT_INSMOD_COMMON
 #define I2C_CLIENT_INSMOD_8(chip1, chip2, chip3, chip4, chip5, chip6, chip7, chip8) \
 enum chips { any_chip, chip1, chip2, chip3, chip4, chip5, chip6,        \
             chip7, chip8 };                                            \
-I2C_CLIENT_MODULE_PARM(force, "List of adapter,address pairs to "       \
+I2C_CLIENT_MODULE_PARM(force, I2C_CLIENT_FORCE_TEXT);                   \
-                       "boldly assume to be present");                  \
 I2C_CLIENT_MODULE_PARM_FORCE(chip1);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip2);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip3);                                    \
@@ -723,11 +710,10 @@ I2C_CLIENT_MODULE_PARM_FORCE(chip5);					\
 I2C_CLIENT_MODULE_PARM_FORCE(chip6);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip7);                                    \
 I2C_CLIENT_MODULE_PARM_FORCE(chip8);                                    \
-static unsigned short *forces[] = { force, force_##chip1,               \
+static const unsigned short * const forces[] = { force,                 \
-                                    force_##chip2, force_##chip3,       \
+        force_##chip1, force_##chip2, force_##chip3,                    \
-                                    force_##chip4, force_##chip5,       \
+        force_##chip4, force_##chip5, force_##chip6,                    \
-                                    force_##chip6, force_##chip7,       \
+        force_##chip7, force_##chip8, NULL };                           \
-                                    force_##chip8, NULL };              \
 I2C_CLIENT_INSMOD_COMMON
 #endif /* __KERNEL__ */
 #endif /* _LINUX_I2C_H */
diff --git a/include/asm-arm/arch-omap/tps65010.h b/include/linux/i2c/tps65010.h
index b9aa2b3a3909..7021635ed6a0 100644
--- a/include/asm-arm/arch-omap/tps65010.h
+++ b/include/linux/i2c/tps65010.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/arch-omap/tps65010.h
+/* linux/i2c/tps65010.h
 *
 * Functions to access TPS65010 power management device.
 *
@@ -25,8 +25,8 @@
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */
-#ifndef __ASM_ARCH_TPS65010_H
+#ifndef __LINUX_I2C_TPS65010_H
-#define __ASM_ARCH_TPS65010_H
+#define __LINUX_I2C_TPS65010_H
 /*
 * ----------------------------------------------------------------------------
@@ -152,5 +152,5 @@ extern int tps65010_config_vregs1(unsigned value);
 */
 extern int tps65013_set_low_pwr(unsigned mode);
-#endif /*  __ASM_ARCH_TPS65010_H */
+#endif /*  __LINUX_I2C_TPS65010_H */
diff --git a/include/linux/ide.h b/include/linux/ide.h
index 1e4409937ec3..27cb39de2ae2 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -107,7 +107,6 @@ typedef unsigned char	byte;	/* used everywhere */
 #define BAD_W_STAT              (BAD_R_STAT  | WRERR_STAT)
 #define BAD_STAT                (BAD_R_STAT  | DRQ_STAT)
 #define DRIVE_READY             (READY_STAT  | SEEK_STAT)
-#define DATA_READY              (DRQ_STAT)
 #define BAD_CRC                 (ABRT_ERR    | ICRC_ERR)
@@ -198,8 +197,11 @@ typedef struct hw_regs_s {
 } hw_regs_t;
 struct hwif_s * ide_find_port(unsigned long);
+void ide_init_port_data(struct hwif_s *, unsigned int);
+void ide_init_port_hw(struct hwif_s *, hw_regs_t *);
-int ide_register_hw(hw_regs_t *, void (*)(struct hwif_s *), int,
+struct ide_drive_s;
+int ide_register_hw(hw_regs_t *, void (*)(struct ide_drive_s *),
                    struct hwif_s **);
 void ide_setup_ports(   hw_regs_t *hw,
@@ -391,7 +393,6 @@ typedef struct ide_drive_s {
        u8      state;                  /* retry state */
        u8      waiting_for_dma;        /* dma currently in progress */
        u8      unmask;                 /* okay to unmask other irqs */
-        u8      bswap;                  /* byte swap data */
        u8      noflush;                /* don't attempt flushes */
        u8      dsc_overlap;            /* DSC overlap */
        u8      nice1;                  /* give potential excess bandwidth */
@@ -527,31 +528,26 @@ typedef struct hwif_s {
        /* special host masking for drive selection */
        void    (*maskproc)(ide_drive_t *, int);
        /* check host's drive quirk list */
-        int     (*quirkproc)(ide_drive_t *);
+        void    (*quirkproc)(ide_drive_t *);
        /* driver soft-power interface */
        int     (*busproc)(ide_drive_t *, int);
 #endif
        u8 (*mdma_filter)(ide_drive_t *);
        u8 (*udma_filter)(ide_drive_t *);
-        void (*fixup)(struct hwif_s *);
        void (*ata_input_data)(ide_drive_t *, void *, u32);
        void (*ata_output_data)(ide_drive_t *, void *, u32);
        void (*atapi_input_bytes)(ide_drive_t *, void *, u32);
        void (*atapi_output_bytes)(ide_drive_t *, void *, u32);
+        void (*dma_host_set)(ide_drive_t *, int);
        int (*dma_setup)(ide_drive_t *);
        void (*dma_exec_cmd)(ide_drive_t *, u8);
        void (*dma_start)(ide_drive_t *);
        int (*ide_dma_end)(ide_drive_t *drive);
-        int (*ide_dma_on)(ide_drive_t *drive);
-        void (*dma_off_quietly)(ide_drive_t *drive);
        int (*ide_dma_test_irq)(ide_drive_t *drive);
        void (*ide_dma_clear_irq)(ide_drive_t *drive);
-        void (*dma_host_on)(ide_drive_t *drive);
-        void (*dma_host_off)(ide_drive_t *drive);
        void (*dma_lost_irq)(ide_drive_t *drive);
        void (*dma_timeout)(ide_drive_t *drive);
@@ -874,14 +870,6 @@ extern int ide_do_drive_cmd(ide_drive_t *, struct request *, ide_action_t);
 extern void ide_end_drive_cmd(ide_drive_t *, u8, u8);
-/*
- * Issue ATA command and wait for completion.
- * Use for implementing commands in kernel
- *
- *  (ide_drive_t *drive, u8 cmd, u8 nsect, u8 feature, u8 sectors, u8 *buf)
- */
-extern int ide_wait_cmd(ide_drive_t *, u8, u8, u8, u8, u8 *);
 enum {
        IDE_TFLAG_LBA48                 = (1 << 0),
        IDE_TFLAG_NO_SELECT_MASK        = (1 << 1),
@@ -934,6 +922,14 @@ enum {
        IDE_TFLAG_IN_TF                 = IDE_TFLAG_IN_NSECT |
                                          IDE_TFLAG_IN_LBA,
        IDE_TFLAG_IN_DEVICE             = (1 << 29),
+        IDE_TFLAG_HOB                   = IDE_TFLAG_OUT_HOB |
+                                          IDE_TFLAG_IN_HOB,
+        IDE_TFLAG_TF                    = IDE_TFLAG_OUT_TF |
+                                          IDE_TFLAG_IN_TF,
+        IDE_TFLAG_DEVICE                = IDE_TFLAG_OUT_DEVICE |
+                                          IDE_TFLAG_IN_DEVICE,
+        /* force 16-bit I/O operations */
+        IDE_TFLAG_IO_16BIT              = (1 << 30),
 };
 struct ide_taskfile {
@@ -988,6 +984,10 @@ void ide_pktcmd_tf_load(ide_drive_t *, u32, u16, u8);
 ide_startstop_t do_rw_taskfile(ide_drive_t *, ide_task_t *);
+void task_end_request(ide_drive_t *, struct request *, u8);
+u8 wait_drive_not_busy(ide_drive_t *);
 int ide_raw_taskfile(ide_drive_t *, ide_task_t *, u8 *, u16);
 int ide_no_data_taskfile(ide_drive_t *, ide_task_t *);
@@ -1015,10 +1015,9 @@ extern void do_ide_request(struct request_queue *);
 void ide_init_disk(struct gendisk *, ide_drive_t *);
-extern int ideprobe_init(void);
 #ifdef CONFIG_IDEPCI_PCIBUS_ORDER
-extern void ide_scan_pcibus(int scan_direction) __init;
+extern int ide_scan_direction;
+int __init ide_scan_pcibus(void);
 extern int __ide_pci_register_driver(struct pci_driver *driver, struct module *owner, const char *mod_name);
 #define ide_pci_register_driver(d) __ide_pci_register_driver(d, THIS_MODULE, KBUILD_MODNAME)
 #else
@@ -1095,6 +1094,8 @@ enum {
        /* unmask IRQs */
        IDE_HFLAG_UNMASK_IRQS           = (1 << 25),
        IDE_HFLAG_ABUSE_SET_DMA_MODE    = (1 << 26),
+        /* host is CY82C693 */
+        IDE_HFLAG_CY82C693              = (1 << 27),
 };
 #ifdef CONFIG_BLK_DEV_OFFBOARD
@@ -1109,7 +1110,6 @@ struct ide_port_info {
        void                    (*init_iops)(ide_hwif_t *);
        void                    (*init_hwif)(ide_hwif_t *);
        void                    (*init_dma)(ide_hwif_t *, unsigned long);
-        void                    (*fixup)(ide_hwif_t *);
        ide_pci_enablebit_t     enablebits[2];
        hwif_chipset_t          chipset;
        u8                      extra;
@@ -1147,7 +1147,9 @@ static inline u8 ide_max_dma_mode(ide_drive_t *drive)
        return ide_find_dma_mode(drive, XFER_UDMA_6);
 }
+void ide_dma_off_quietly(ide_drive_t *);
 void ide_dma_off(ide_drive_t *);
+void ide_dma_on(ide_drive_t *);
 int ide_set_dma(ide_drive_t *);
 ide_startstop_t ide_dma_intr(ide_drive_t *);
@@ -1158,10 +1160,7 @@ extern void ide_destroy_dmatable(ide_drive_t *);
 extern int ide_release_dma(ide_hwif_t *);
 extern void ide_setup_dma(ide_hwif_t *, unsigned long, unsigned int);
-void ide_dma_host_off(ide_drive_t *);
+void ide_dma_host_set(ide_drive_t *, int);
-void ide_dma_off_quietly(ide_drive_t *);
-void ide_dma_host_on(ide_drive_t *);
-extern int __ide_dma_on(ide_drive_t *);
 extern int ide_dma_setup(ide_drive_t *);
 extern void ide_dma_start(ide_drive_t *);
 extern int __ide_dma_end(ide_drive_t *);
@@ -1173,7 +1172,9 @@ extern void ide_dma_timeout(ide_drive_t *);
 static inline int ide_id_dma_bug(ide_drive_t *drive) { return 0; }
 static inline u8 ide_find_dma_mode(ide_drive_t *drive, u8 speed) { return 0; }
 static inline u8 ide_max_dma_mode(ide_drive_t *drive) { return 0; }
+static inline void ide_dma_off_quietly(ide_drive_t *drive) { ; }
 static inline void ide_dma_off(ide_drive_t *drive) { ; }
+static inline void ide_dma_on(ide_drive_t *drive) { ; }
 static inline void ide_dma_verbose(ide_drive_t *drive) { ; }
 static inline int ide_set_dma(ide_drive_t *drive) { return 1; }
 #endif /* CONFIG_BLK_DEV_IDEDMA */
@@ -1203,8 +1204,9 @@ extern void ide_unregister (unsigned int index);
 void ide_register_region(struct gendisk *);
 void ide_unregister_region(struct gendisk *);
-void ide_undecoded_slave(ide_hwif_t *);
+void ide_undecoded_slave(ide_drive_t *);
+int ide_device_add_all(u8 *idx);
 int ide_device_add(u8 idx[4]);
 static inline void *ide_get_hwifdata (ide_hwif_t * hwif)
@@ -1302,4 +1304,9 @@ static inline ide_drive_t *ide_get_paired_drive(ide_drive_t *drive)
        return &hwif->drives[(drive->dn ^ 1) & 1];
 }
+static inline void ide_set_irq(ide_drive_t *drive, int on)
+{
+        drive->hwif->OUTB(drive->ctl | (on ? 0 : 2), IDE_CONTROL_REG);
+}
 #endif /* _IDE_H */
diff --git a/include/linux/m41t00.h b/include/linux/m41t00.h
deleted file mode 100644
index b423360ca38e..000000000000
--- a/include/linux/m41t00.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Definitions for the ST M41T00 family of i2c rtc chips.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2005, 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef _M41T00_H
-#define _M41T00_H
-#define M41T00_DRV_NAME         "m41t00"
-#define M41T00_I2C_ADDR         0x68
-#define M41T00_TYPE_M41T00      0
-#define M41T00_TYPE_M41T81      81
-#define M41T00_TYPE_M41T85      85
-struct m41t00_platform_data {
-        u8      type;
-        u8      i2c_addr;
-        u8      sqw_freq;
-};
-/* SQW output disabled, this is default value by power on */
-#define M41T00_SQW_DISABLE      (0)
-#define M41T00_SQW_32KHZ        (1<<4)          /* 32.768 KHz */
-#define M41T00_SQW_8KHZ         (2<<4)          /* 8.192 KHz */
-#define M41T00_SQW_4KHZ         (3<<4)          /* 4.096 KHz */
-#define M41T00_SQW_2KHZ         (4<<4)          /* 2.048 KHz */
-#define M41T00_SQW_1KHZ         (5<<4)          /* 1.024 KHz */
-#define M41T00_SQW_512HZ        (6<<4)          /* 512 Hz */
-#define M41T00_SQW_256HZ        (7<<4)          /* 256 Hz */
-#define M41T00_SQW_128HZ        (8<<4)          /* 128 Hz */
-#define M41T00_SQW_64HZ         (9<<4)          /* 64 Hz */
-#define M41T00_SQW_32HZ         (10<<4)         /* 32 Hz */
-#define M41T00_SQW_16HZ         (11<<4)         /* 16 Hz */
-#define M41T00_SQW_8HZ          (12<<4)         /* 8 Hz */
-#define M41T00_SQW_4HZ          (13<<4)         /* 4 Hz */
-#define M41T00_SQW_2HZ          (14<<4)         /* 2 Hz */
-#define M41T00_SQW_1HZ          (15<<4)         /* 1 Hz */
-extern ulong m41t00_get_rtc_time(void);
-extern int m41t00_set_rtc_time(ulong nowtime);
-#endif /* _M41T00_H */
diff --git a/include/media/v4l2-i2c-drv-legacy.h b/include/media/v4l2-i2c-drv-legacy.h
index 241854229d6f..e7645578fc22 100644
--- a/include/media/v4l2-i2c-drv-legacy.h
+++ b/include/media/v4l2-i2c-drv-legacy.h
@@ -34,7 +34,7 @@ struct v4l2_i2c_driver_data {
 };
 static struct v4l2_i2c_driver_data v4l2_i2c_data;
-static struct i2c_client_address_data addr_data;
+static const struct i2c_client_address_data addr_data;
 static struct i2c_driver v4l2_i2c_driver_legacy;
 static char v4l2_i2c_drv_name_legacy[32];