diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-mips/cevt-r4k.h | 46 | ||||
-rw-r--r-- | include/asm-mips/irqflags.h | 26 | ||||
-rw-r--r-- | include/asm-mips/smtc.h | 8 |
3 files changed, 74 insertions, 6 deletions
diff --git a/include/asm-mips/cevt-r4k.h b/include/asm-mips/cevt-r4k.h new file mode 100644 index 000000000000..fa4328f9124f --- /dev/null +++ b/include/asm-mips/cevt-r4k.h | |||
@@ -0,0 +1,46 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2008 Kevin D. Kissell | ||
7 | */ | ||
8 | |||
9 | /* | ||
10 | * Definitions used for common event timer implementation | ||
11 | * for MIPS 4K-type processors and their MIPS MT variants. | ||
12 | * Avoids unsightly extern declarations in C files. | ||
13 | */ | ||
14 | #ifndef __ASM_CEVT_R4K_H | ||
15 | #define __ASM_CEVT_R4K_H | ||
16 | |||
17 | DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device); | ||
18 | |||
19 | void mips_event_handler(struct clock_event_device *dev); | ||
20 | int c0_compare_int_usable(void); | ||
21 | void mips_set_clock_mode(enum clock_event_mode, struct clock_event_device *); | ||
22 | irqreturn_t c0_compare_interrupt(int, void *); | ||
23 | |||
24 | extern struct irqaction c0_compare_irqaction; | ||
25 | extern int cp0_timer_irq_installed; | ||
26 | |||
27 | /* | ||
28 | * Possibly handle a performance counter interrupt. | ||
29 | * Return true if the timer interrupt should not be checked | ||
30 | */ | ||
31 | |||
32 | static inline int handle_perf_irq(int r2) | ||
33 | { | ||
34 | /* | ||
35 | * The performance counter overflow interrupt may be shared with the | ||
36 | * timer interrupt (cp0_perfcount_irq < 0). If it is and a | ||
37 | * performance counter has overflowed (perf_irq() == IRQ_HANDLED) | ||
38 | * and we can't reliably determine if a counter interrupt has also | ||
39 | * happened (!r2) then don't check for a timer interrupt. | ||
40 | */ | ||
41 | return (cp0_perfcount_irq < 0) && | ||
42 | perf_irq() == IRQ_HANDLED && | ||
43 | !r2; | ||
44 | } | ||
45 | |||
46 | #endif /* __ASM_CEVT_R4K_H */ | ||
diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h index 881e8866501d..701ec0ba8fa9 100644 --- a/include/asm-mips/irqflags.h +++ b/include/asm-mips/irqflags.h | |||
@@ -38,8 +38,17 @@ __asm__( | |||
38 | " .set pop \n" | 38 | " .set pop \n" |
39 | " .endm"); | 39 | " .endm"); |
40 | 40 | ||
41 | extern void smtc_ipi_replay(void); | ||
42 | |||
41 | static inline void raw_local_irq_enable(void) | 43 | static inline void raw_local_irq_enable(void) |
42 | { | 44 | { |
45 | #ifdef CONFIG_MIPS_MT_SMTC | ||
46 | /* | ||
47 | * SMTC kernel needs to do a software replay of queued | ||
48 | * IPIs, at the cost of call overhead on each local_irq_enable() | ||
49 | */ | ||
50 | smtc_ipi_replay(); | ||
51 | #endif | ||
43 | __asm__ __volatile__( | 52 | __asm__ __volatile__( |
44 | "raw_local_irq_enable" | 53 | "raw_local_irq_enable" |
45 | : /* no outputs */ | 54 | : /* no outputs */ |
@@ -47,6 +56,7 @@ static inline void raw_local_irq_enable(void) | |||
47 | : "memory"); | 56 | : "memory"); |
48 | } | 57 | } |
49 | 58 | ||
59 | |||
50 | /* | 60 | /* |
51 | * For cli() we have to insert nops to make sure that the new value | 61 | * For cli() we have to insert nops to make sure that the new value |
52 | * has actually arrived in the status register before the end of this | 62 | * has actually arrived in the status register before the end of this |
@@ -185,15 +195,14 @@ __asm__( | |||
185 | " .set pop \n" | 195 | " .set pop \n" |
186 | " .endm \n"); | 196 | " .endm \n"); |
187 | 197 | ||
188 | extern void smtc_ipi_replay(void); | ||
189 | 198 | ||
190 | static inline void raw_local_irq_restore(unsigned long flags) | 199 | static inline void raw_local_irq_restore(unsigned long flags) |
191 | { | 200 | { |
192 | unsigned long __tmp1; | 201 | unsigned long __tmp1; |
193 | 202 | ||
194 | #ifdef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY | 203 | #ifdef CONFIG_MIPS_MT_SMTC |
195 | /* | 204 | /* |
196 | * CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY does prompt replay of deferred | 205 | * SMTC kernel needs to do a software replay of queued |
197 | * IPIs, at the cost of branch and call overhead on each | 206 | * IPIs, at the cost of branch and call overhead on each |
198 | * local_irq_restore() | 207 | * local_irq_restore() |
199 | */ | 208 | */ |
@@ -208,6 +217,17 @@ static inline void raw_local_irq_restore(unsigned long flags) | |||
208 | : "memory"); | 217 | : "memory"); |
209 | } | 218 | } |
210 | 219 | ||
220 | static inline void __raw_local_irq_restore(unsigned long flags) | ||
221 | { | ||
222 | unsigned long __tmp1; | ||
223 | |||
224 | __asm__ __volatile__( | ||
225 | "raw_local_irq_restore\t%0" | ||
226 | : "=r" (__tmp1) | ||
227 | : "0" (flags) | ||
228 | : "memory"); | ||
229 | } | ||
230 | |||
211 | static inline int raw_irqs_disabled_flags(unsigned long flags) | 231 | static inline int raw_irqs_disabled_flags(unsigned long flags) |
212 | { | 232 | { |
213 | #ifdef CONFIG_MIPS_MT_SMTC | 233 | #ifdef CONFIG_MIPS_MT_SMTC |
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h index 3639b28f80db..ea60bf08dcb0 100644 --- a/include/asm-mips/smtc.h +++ b/include/asm-mips/smtc.h | |||
@@ -6,6 +6,7 @@ | |||
6 | */ | 6 | */ |
7 | 7 | ||
8 | #include <asm/mips_mt.h> | 8 | #include <asm/mips_mt.h> |
9 | #include <asm/smtc_ipi.h> | ||
9 | 10 | ||
10 | /* | 11 | /* |
11 | * System-wide SMTC status information | 12 | * System-wide SMTC status information |
@@ -38,14 +39,15 @@ struct mm_struct; | |||
38 | struct task_struct; | 39 | struct task_struct; |
39 | 40 | ||
40 | void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu); | 41 | void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu); |
41 | 42 | void self_ipi(struct smtc_ipi *); | |
42 | void smtc_flush_tlb_asid(unsigned long asid); | 43 | void smtc_flush_tlb_asid(unsigned long asid); |
43 | extern int mipsmt_build_cpu_map(int startslot); | 44 | extern int smtc_build_cpu_map(int startslot); |
44 | extern void mipsmt_prepare_cpus(void); | 45 | extern void smtc_prepare_cpus(int cpus); |
45 | extern void smtc_smp_finish(void); | 46 | extern void smtc_smp_finish(void); |
46 | extern void smtc_boot_secondary(int cpu, struct task_struct *t); | 47 | extern void smtc_boot_secondary(int cpu, struct task_struct *t); |
47 | extern void smtc_cpus_done(void); | 48 | extern void smtc_cpus_done(void); |
48 | 49 | ||
50 | |||
49 | /* | 51 | /* |
50 | * Sharing the TLB between multiple VPEs means that the | 52 | * Sharing the TLB between multiple VPEs means that the |
51 | * "random" index selection function is not allowed to | 53 | * "random" index selection function is not allowed to |