63 files changed, 390 insertions, 822 deletions
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
index 9944bb5d5330..59c0686f8be7 100644
--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
@@ -80,7 +80,7 @@
 #define OMAP24XX_CONTROL_SEC_TAP        (OMAP2_CONTROL_GENERAL + 0x0064)
 #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD        (OMAP2_CONTROL_GENERAL + 0x006c)
 #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD  (OMAP2_CONTROL_GENERAL + 0x0070)
-#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD   (OMAP2_CONTROL_GENERAL + 0x0074
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD   (OMAP2_CONTROL_GENERAL + 0x0074)
 #define OMAP24XX_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0080)
 #define OMAP24XX_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0084)
 #define OMAP24XX_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0088)
diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h
index 9d9f4b54b2ce..261e5bc958db 100644
--- a/include/asm-arm/arch-pxa/pm.h
+++ b/include/asm-arm/arch-pxa/pm.h
@@ -10,7 +10,7 @@
 #include <linux/suspend.h>
 struct pxa_cpu_pm_fns {
-        int     save_size;
+        int     save_count;
        void    (*save)(unsigned long *);
        void    (*restore)(unsigned long *);
        int     (*valid)(suspend_state_t state);
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index a758a719180f..9aa6c2e939e8 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -22,7 +22,8 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode)
 {
-        RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
+        if (cpu_is_pxa2xx())
+                RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
        if (mode == 's') {
                /* Jump into ROM at address 0 */
diff --git a/include/asm-arm/arch-sa1100/irqs.h b/include/asm-arm/arch-sa1100/irqs.h
index d7940683efb1..7bf80484bb77 100644
--- a/include/asm-arm/arch-sa1100/irqs.h
+++ b/include/asm-arm/arch-sa1100/irqs.h
@@ -141,7 +141,7 @@
 #define IRQ_LOCOMO_LT           (IRQ_BOARD_END + 17)
 #define IRQ_LOCOMO_SPI_RFR      (IRQ_BOARD_END + 18)
 #define IRQ_LOCOMO_SPI_RFW      (IRQ_BOARD_END + 19)
-#define IRQ_LOCOMO_SPI_OVRN     (IRQ_BOARD_END + 20)
+#define IRQ_LOCOMO_SPI_REND     (IRQ_BOARD_END + 20)
 #define IRQ_LOCOMO_SPI_TEND     (IRQ_BOARD_END + 21)
 /*
diff --git a/include/asm-arm/hardware/locomo.h b/include/asm-arm/hardware/locomo.h
index adab77780ed3..fb0645de6f31 100644
--- a/include/asm-arm/hardware/locomo.h
+++ b/include/asm-arm/hardware/locomo.h
@@ -58,6 +58,11 @@
 #define LOCOMO_SPIMD    0x00            /* SPI mode setting */
 #define LOCOMO_SPICT    0x04            /* SPI mode control */
 #define LOCOMO_SPIST    0x08            /* SPI status */
+#define LOCOMO_SPI_TEND (1 << 3)        /* Transfer end bit */
+#define LOCOMO_SPI_REND (1 << 2)        /* Receive end bit */
+#define LOCOMO_SPI_RFW  (1 << 1)        /* write buffer bit */
+#define LOCOMO_SPI_RFR  (1)             /* read buffer bit */
 #define LOCOMO_SPIIS    0x10            /* SPI interrupt status */
 #define LOCOMO_SPIWE    0x14            /* SPI interrupt status write enable */
 #define LOCOMO_SPIIE    0x18            /* SPI interrupt enable */
@@ -66,16 +71,12 @@
 #define LOCOMO_SPIRD    0x24            /* SPI receive data read */
 #define LOCOMO_SPITS    0x28            /* SPI transfer data shift */
 #define LOCOMO_SPIRS    0x2C            /* SPI receive data shift */
-#define LOCOMO_SPI_TEND (1 << 3)        /* Transfer end bit */
-#define LOCOMO_SPI_OVRN (1 << 2)        /* Over Run bit */
-#define LOCOMO_SPI_RFW  (1 << 1)        /* write buffer bit */
-#define LOCOMO_SPI_RFR  (1)             /* read buffer bit */
 /* GPIO */
 #define LOCOMO_GPD              0x90    /* GPIO direction */
 #define LOCOMO_GPE              0x94    /* GPIO input enable */
 #define LOCOMO_GPL              0x98    /* GPIO level */
-#define LOCOMO_GPO              0x9c    /* GPIO out data setteing */
+#define LOCOMO_GPO              0x9c    /* GPIO out data setting */
 #define LOCOMO_GRIE             0xa0    /* GPIO rise detection */
 #define LOCOMO_GFIE             0xa4    /* GPIO fall detection */
 #define LOCOMO_GIS              0xa8    /* GPIO edge detection status */
@@ -96,6 +97,9 @@
 #define LOCOMO_GPIO_DAC_SDATA   LOCOMO_GPIO(10)
 #define LOCOMO_GPIO_DAC_SCK     LOCOMO_GPIO(11)
 #define LOCOMO_GPIO_DAC_SLOAD   LOCOMO_GPIO(12)
+#define LOCOMO_GPIO_CARD_DETECT LOCOMO_GPIO(13)
+#define LOCOMO_GPIO_WRITE_PROT  LOCOMO_GPIO(14)
+#define LOCOMO_GPIO_CARD_POWER  LOCOMO_GPIO(15)
 /* Start the definitions of the devices.  Each device has an initial
 * base address and a series of offsets from that base address. */
@@ -122,7 +126,7 @@
 /* Audio controller */
 #define LOCOMO_AUDIO            0x54
 #define LOCOMO_ACC              0x00    /* Audio clock */
-#define LOCOMO_PAIF             0x7C    /* PCM audio interface */
+#define LOCOMO_PAIF             0xD0    /* PCM audio interface */
 /* Audio clock */
 #define LOCOMO_ACC_XON          0x80
 #define LOCOMO_ACC_XEN          0x40
@@ -162,7 +166,7 @@ extern struct bus_type locomo_bus_type;
 #define LOCOMO_DEVID_AUDIO      3
 #define LOCOMO_DEVID_LED        4
 #define LOCOMO_DEVID_UART       5
-#define LOCOMO_DEVID_SPI                6
+#define LOCOMO_DEVID_SPI        6
 struct locomo_dev {
        struct device   dev;
@@ -204,7 +208,6 @@ int locomo_gpio_read_level(struct device *dev, unsigned int bits);
 int locomo_gpio_read_output(struct device *dev, unsigned int bits);
 void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set);
 /* M62332 control function */
 void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h
index 686cf83a5269..7f34cd384f12 100644
--- a/include/asm-blackfin/dpmc.h
+++ b/include/asm-blackfin/dpmc.h
@@ -1,7 +1,7 @@
 /*
 * include/asm-blackfin/dpmc.h -  Miscellaneous IOCTL commands for Dynamic Power
 *                              Management Controller Driver.
- * Copyright (C) 2004 Analog Device Inc.
+ * Copyright (C) 2004-2008 Analog Device Inc.
 *
 */
 #ifndef _BLACKFIN_DPMC_H_
@@ -65,6 +65,14 @@ void disable_wdog_timer(void);
 extern unsigned long get_cclk(void);
 extern unsigned long get_sclk(void);
+struct bfin_dpmc_platform_data {
+        const unsigned int *tuple_tab;
+        unsigned short tabsize;
+        unsigned short vr_settling_time; /* in us */
+};
+#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
 #endif  /* __KERNEL__ */
 #endif  /*_BLACKFIN_DPMC_H_*/
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
index 562c6d3a3232..c4f721e0d00d 100644
--- a/include/asm-blackfin/entry.h
+++ b/include/asm-blackfin/entry.h
@@ -17,6 +17,11 @@
 #define PF_DTRACE_OFF   1
 #define PF_DTRACE_BIT   5
+/*
+ * NOTE!  The single-stepping code assumes that all interrupt handlers
+ * start by saving SYSCFG on the stack with their first instruction.
+ */
 /* This one is used for exceptions, emulation, and NMI.  It doesn't push
   RETI and doesn't do cli.  */
 #define SAVE_ALL_SYS            save_context_no_interrupts
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index f0ab2736a680..26e3c8076b4e 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
 #define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
 #define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
 #define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
+#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
 #define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
 #define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
 #define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index fbe88dee3e2d..d016603b6615 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
 #define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
 #ifdef CONFIG_BFIN_UART0_CTSRTS
 # define CONFIG_SERIAL_BFIN_CTSRTS
 # ifndef CONFIG_UART0_CTS_PIN
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 17e1548cec08..0ab4dd7494cf 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -468,6 +468,8 @@
 #define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
 #define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
 #define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
+#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
+#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
 #define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
 #define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 832e6f6122da..5aa38e5da6b7 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -66,12 +66,13 @@ Core        Emulation               **
            DMA8/9 Interrupt        IVG13       28
            DMA10/11 Interrupt      IVG13       29
            Watchdog Timer          IVG13       30
-            Software Interrupt 1    IVG14       31
-            Software Interrupt 2    --
+            Softirq                 IVG14       31
+            System Call    --
                 (lowest priority)  IVG15       32 *
 */
-#define SYS_IRQS                32
+#define SYS_IRQS        31
-#define NR_PERI_INTS    24
+#define NR_PERI_INTS    24
 /* The ABSTRACT IRQ definitions */
 /** the first seven of the following are fixed, the rest you change if you need to **/
@@ -96,7 +97,7 @@ Core        Emulation               **
 #define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
 #define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
 #define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
+#define         IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
 #define IRQ_UART_RX             21      /*DMA6 Interrupt (UART RX) */
 #define IRQ_UART_TX             22      /*DMA7 Interrupt (UART TX) */
 #define IRQ_TMR0                23      /*Timer 0 */
@@ -108,9 +109,6 @@ Core        Emulation               **
 #define IRQ_MEM_DMA1            29      /*DMA10/11 Interrupt (Memory DMA Stream 1) */
 #define IRQ_WATCH               30      /*Watch Dog Timer */
-#define IRQ_SW_INT1             31      /*Software Int 1 */
-#define IRQ_SW_INT2             32      /*Software Int 2 (reserved for SYSCALL) */
 #define IRQ_PF0                 33
 #define IRQ_PF1                 34
 #define IRQ_PF2                 35
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index fd100a415b98..f79d1a0e9129 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
 #define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index be6f2ff77f31..2e68a8a1e730 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -34,24 +34,23 @@
 /*
 * Interrupt source definitions
-             Event Source    Core Event Name
+ *            Event Source    Core Event Name
-Core        Emulation               **
+ * Core       Emulation               **
- Events         (highest priority)  EMU         0
+ * Events         (highest priority)  EMU         0
-            Reset                   RST         1
+ *            Reset                   RST         1
-            NMI                     NMI         2
+ *            NMI                     NMI         2
-            Exception               EVX         3
+ *            Exception               EVX         3
-            Reserved                --          4
+ *            Reserved                --          4
-            Hardware Error          IVHW        5
+ *            Hardware Error          IVHW        5
-            Core Timer              IVTMR       6 *
+ *            Core Timer              IVTMR       6
+ *  .....
-.....
+ *
+ *            Softirq                 IVG14
-            Software Interrupt 1    IVG14       31
+ *            System Call    --
-            Software Interrupt 2    --
+ *               (lowest priority)    IVG15
-                 (lowest priority)  IVG15       32 *
 */
-#define SYS_IRQS        41
+#define SYS_IRQS        39
 #define NR_PERI_INTS    32
 /* The ABSTRACT IRQ definitions */
@@ -95,10 +94,8 @@ Core        Emulation               **
 #define IRQ_PORTG_INTB      35  /* PF Port G (PF15:0) Interrupt B */
 #define IRQ_MEM_DMA0        36  /*(Memory DMA Stream 0) */
 #define IRQ_MEM_DMA1        37  /*(Memory DMA Stream 1) */
-#define IRQ_PROG_INTB       38  /* PF Ports F (PF15:0) Interrupt B */
+#define IRQ_PROG_INTB         38        /* PF Ports F (PF15:0) Interrupt B */
 #define IRQ_WATCH           38  /*Watch Dog Timer */
-#define IRQ_SW_INT1         40  /*Software Int 1 */
-#define IRQ_SW_INT2         41  /*Software Int 2 (reserved for SYSCALL) */
 #define IRQ_PPI_ERROR       42  /*PPI Error Interrupt */
 #define IRQ_CAN_ERROR       43  /*CAN Error Interrupt */
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index 6547027cd3e6..5eb46a77d919 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -54,6 +54,9 @@
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
 #define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
+#define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
+#define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 08f90c21fe8a..e022e896cb18 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -2329,6 +2329,26 @@
 #define                    KPADWE  0x1000     /* Keypad Wake-Up Enable */
 #define                     ROTWE  0x2000     /* Rotary Wake-Up Enable */
+#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
+#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
+#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
+#define GAIN_5                  0x0000  /* GAIN = 5*/
+#define GAIN_10                 0x0004  /* GAIN = 1*/
+#define GAIN_20                 0x0008  /* GAIN = 2*/
+#define GAIN_50                 0x000C  /* GAIN = 5*/
+#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
 /* Bit masks for NFC_CTL */
 #define                    WR_DLY  0xf        /* Write Strobe Delay */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 8a4e66d1db37..7a9628769296 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
 #define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
 #ifdef CONFIG_BFIN_UART0_CTSRTS
 # define CONFIG_SERIAL_BFIN_CTSRTS
 # ifndef CONFIG_UART0_CTS_PIN
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 366c9b9a0cb7..1ab50e906fe7 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -868,6 +868,34 @@
 #define CHIPID_FAMILY          0x0FFFF000
 #define CHIPID_MANUFACTURE     0x00000FFE
+/* VR_CTL Masks                                                                                                                                 */
+#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE               0x0000  /* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
+#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
+#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
+#define GAIN                    0x000C  /* Voltage Level Gain   */
+#define GAIN_5                  0x0000  /* GAIN = 5*/
+#define GAIN_10                 0x0004  /* GAIN = 1*/
+#define GAIN_20                 0x0008  /* GAIN = 2*/
+#define GAIN_50                 0x000C  /* GAIN = 5*/
+#define VLEV                    0x00F0  /* Internal Voltage Level */
+#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
+#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
+#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
 /* PLL_DIV Masks */
 #define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index 83f0383957d2..6698389c5564 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -118,12 +118,13 @@
            Supplemental interrupt 0            IVG7        69
            supplemental interrupt 1            IVG7        70
-            Software Interrupt 1                IVG14       71
+            Softirq                             IVG14
-            Software Interrupt 2                IVG15       72 *
+            System Call    --
-                                                (lowest priority)
+                 (lowest priority)              IVG15
 **********************************************************************/
-#define SYS_IRQS                72
+#define SYS_IRQS                71
 #define NR_PERI_INTS            64
 /*
@@ -237,9 +238,7 @@
 #define IRQ_RESERVED_2          (IVG_BASE + 61) /* Reserved interrupt       */
 #define IRQ_SUPPLE_0            (IVG_BASE + 62) /* Supplemental interrupt 0 */
 #define IRQ_SUPPLE_1            (IVG_BASE + 63) /* supplemental interrupt 1 */
-#define IRQ_SW_INT1             71      /* Software Interrupt 1     */
-#define IRQ_SW_INT2             72      /* Software Interrupt 2     */
-                                                /* reserved for SYSCALL */
 #define IRQ_PF0                 73
 #define IRQ_PF1                 74
 #define IRQ_PF2                 75
diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S
index fd0ebe1862b8..c0e630edfb9a 100644
--- a/include/asm-blackfin/mach-common/context.S
+++ b/include/asm-blackfin/mach-common/context.S
@@ -28,6 +28,11 @@
 */
 /*
+ * NOTE!  The single-stepping code assumes that all interrupt handlers
+ * start by saving SYSCFG on the stack with their first instruction.
+ */
+/*
 * Code to save processor context.
 *  We even save the register which are preserved by a function call
 *       - r4, r5, r6, r7, p3, p4, p5
diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h
index 6e5859b6ea32..ddc43ce38533 100644
--- a/include/asm-blackfin/time.h
+++ b/include/asm-blackfin/time.h
@@ -24,6 +24,8 @@
 #ifndef CONFIG_CPU_FREQ
 #define TIME_SCALE 1
+#define __bfin_cycles_off (0)
+#define __bfin_cycles_mod (0)
 #else
 /*
 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
@@ -31,6 +33,8 @@
 * adjust the Core Timer Presale Register. This way we don't lose time.
 */
 #define TIME_SCALE 4
+extern unsigned long long __bfin_cycles_off;
+extern unsigned int __bfin_cycles_mod;
 #endif
 #endif
diff --git a/include/asm-mn10300/processor.h b/include/asm-mn10300/processor.h
index f1b081f53468..73239271873d 100644
--- a/include/asm-mn10300/processor.h
+++ b/include/asm-mn10300/processor.h
@@ -58,7 +58,7 @@ extern struct mn10300_cpuinfo boot_cpu_data;
 extern void identify_cpu(struct mn10300_cpuinfo *);
 extern void print_cpu_info(struct mn10300_cpuinfo *);
 extern void dodgy_tsc(void);
-#define cpu_relax() do {} while (0)
+#define cpu_relax() barrier()
 /*
 * User space process size: 1.75GB (default).
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 7c97b5a08d08..c08e714d0c42 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -209,6 +209,13 @@ extern int icache_44x_need_flush;
 *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
 *
+ * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
+ * TLB2 storage attibute fields. Those are:
+ *
+ *   TLB2:
+ *   0...10    11   12   13   14   15   16...31
+ *   no change WL1  IL1I IL1D IL2I IL2D no change
+ *
 * There are some constrains and options, to decide mapping software bits
 * into TLB entry.
 *
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index e3c845b0f764..6abead6e681a 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -100,6 +100,7 @@
 /* Flag indicating progress during context switch. */
 #define SPU_CONTEXT_SWITCH_PENDING      0UL
+#define SPU_CONTEXT_FAULT_PENDING       1UL
 struct spu_context;
 struct spu_runqueue;
@@ -128,9 +129,11 @@ struct spu {
        unsigned int irqs[3];
        u32 node;
        u64 flags;
-        u64 dar;
-        u64 dsisr;
        u64 class_0_pending;
+        u64 class_0_dar;
+        u64 class_0_dsisr;
+        u64 class_1_dar;
+        u64 class_1_dsisr;
        size_t ls_size;
        unsigned int slb_replace;
        struct mm_struct *mm;
@@ -143,7 +146,7 @@ struct spu {
        void (* wbox_callback)(struct spu *spu);
        void (* ibox_callback)(struct spu *spu);
-        void (* stop_callback)(struct spu *spu);
+        void (* stop_callback)(struct spu *spu, int irq);
        void (* mfc_callback)(struct spu *spu);
        char irq_c0[8];
diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h
index 0ab6bff86078..129ec148d451 100644
--- a/include/asm-powerpc/spu_csa.h
+++ b/include/asm-powerpc/spu_csa.h
@@ -254,7 +254,8 @@ struct spu_state {
        u64 spu_chnldata_RW[32];
        u32 spu_mailbox_data[4];
        u32 pu_mailbox_data[1];
-        u64 dar, dsisr, class_0_pending;
+        u64 class_0_dar, class_0_dsisr, class_0_pending;
+        u64 class_1_dar, class_1_dsisr;
        unsigned long suspend_time;
        spinlock_t register_lock;
 };
diff --git a/include/asm-s390/kvm_host.h b/include/asm-s390/kvm_host.h
index f8204a4f2e02..18cbd8a39796 100644
--- a/include/asm-s390/kvm_host.h
+++ b/include/asm-s390/kvm_host.h
@@ -104,6 +104,7 @@ struct sie_block {
 struct kvm_vcpu_stat {
        u32 exit_userspace;
+        u32 exit_null;
        u32 exit_external_request;
        u32 exit_external_interrupt;
        u32 exit_stop_request;
diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h
index f0f4579eac13..12fd9c4f0f15 100644
--- a/include/asm-s390/page.h
+++ b/include/asm-s390/page.h
@@ -125,6 +125,17 @@ page_get_storage_key(unsigned long addr)
        return skey;
 }
+#ifdef CONFIG_PAGE_STATES
+struct page;
+void arch_free_page(struct page *page, int order);
+void arch_alloc_page(struct page *page, int order);
+#define HAVE_ARCH_FREE_PAGE
+#define HAVE_ARCH_ALLOC_PAGE
+#endif
 #endif /* !__ASSEMBLY__ */
 /* to align the pointer to the (next) page boundary */
diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h
index 441d7c260857..d7d4e2eb3e6f 100644
--- a/include/asm-s390/ptrace.h
+++ b/include/asm-s390/ptrace.h
@@ -471,6 +471,8 @@ struct task_struct;
 extern void user_enable_single_step(struct task_struct *);
 extern void user_disable_single_step(struct task_struct *);
+#define __ARCH_WANT_COMPAT_SYS_PTRACE
 #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
 #define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
 #define regs_return_value(regs)((regs)->gprs[2])
diff --git a/include/asm-s390/system.h b/include/asm-s390/system.h
index c819ae25a842..e0d4500d5f95 100644
--- a/include/asm-s390/system.h
+++ b/include/asm-s390/system.h
@@ -116,6 +116,12 @@ extern void pfault_fini(void);
 #define pfault_fini()           do { } while (0)
 #endif /* CONFIG_PFAULT */
+#ifdef CONFIG_PAGE_STATES
+extern void cmma_init(void);
+#else
+static inline void cmma_init(void) { }
+#endif
 #define finish_arch_switch(prev) do {                                        \
        set_fs(current->thread.mm_segment);                                  \
        account_vtime(prev);                                                 \
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index 092ff9d872c3..6813c3220a1d 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -3,19 +3,19 @@
 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
-    defined(CONFIG_CPU_SUBTYPE_SH7709)
 #define SH_DMAC_BASE    0xa4010020
+#else
+#define SH_DMAC_BASE    0xa4000020
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 #define DMTE0_IRQ       48
 #define DMTE1_IRQ       49
 #define DMTE2_IRQ       50
 #define DMTE3_IRQ       51
 #define DMTE4_IRQ       76
 #define DMTE5_IRQ       77
-#else
-#define SH_DMAC_BASE    0xa4000020
 #endif
 /* Definitions for the SuperH DMAC */
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index c958fdaa0095..7438d1e21bc9 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -79,6 +79,10 @@ struct intc_desc {
        struct intc_sense_reg *sense_regs;
        unsigned int nr_sense_regs;
        char *name;
+#ifdef CONFIG_CPU_SH3
+        struct intc_mask_reg *ack_regs;
+        unsigned int nr_ack_regs;
+#endif
 };
 #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
@@ -91,10 +95,25 @@ struct intc_desc symbol __initdata = {					\
        chipname,                                                       \
 }
+#ifdef CONFIG_CPU_SH3
+#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,        \
+        mask_regs, prio_regs, sense_regs, ack_regs)                     \
+struct intc_desc symbol __initdata = {                                  \
+        _INTC_ARRAY(vectors), _INTC_ARRAY(groups),                      \
+        _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),                 \
+        _INTC_ARRAY(sense_regs),                                        \
+        chipname,                                                       \
+        _INTC_ARRAY(ack_regs),                                          \
+}
+#endif
 void __init register_intc_controller(struct intc_desc *desc);
 int intc_set_priority(unsigned int irq, unsigned int prio);
 void __init plat_irq_setup(void);
+#ifdef CONFIG_CPU_SH3
+void __init plat_irq_setup_sh3(void);
+#endif
 enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
       IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index 356e50d06745..a4fbf0c84fb1 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -268,11 +268,6 @@ unsigned long long peek_real_address_q(unsigned long long addr);
 unsigned long long poke_real_address_q(unsigned long long addr,
                                       unsigned long long val);
-/* arch/sh/mm/ioremap_64.c */
-unsigned long onchip_remap(unsigned long addr, unsigned long size,
-                           const char *name);
-extern void onchip_unmap(unsigned long vaddr);
 #if !defined(CONFIG_MMU)
 #define virt_to_phys(address)   ((unsigned long)(address))
 #define phys_to_virt(address)   ((void *)(address))
@@ -302,9 +297,16 @@ extern void onchip_unmap(unsigned long vaddr);
 void __iomem *__ioremap(unsigned long offset, unsigned long size,
                        unsigned long flags);
 void __iounmap(void __iomem *addr);
+/* arch/sh/mm/ioremap_64.c */
+unsigned long onchip_remap(unsigned long addr, unsigned long size,
+                           const char *name);
+extern void onchip_unmap(unsigned long vaddr);
 #else
 #define __ioremap(offset, size, flags)  ((void __iomem *)(offset))
 #define __iounmap(addr)                 do { } while (0)
+#define onchip_remap(addr, size, name)  (addr)
+#define onchip_unmap(addr)              do { } while (0)
 #endif /* CONFIG_MMU */
 static inline void __iomem *
diff --git a/include/asm-sh/keyboard.h b/include/asm-sh/keyboard.h
deleted file mode 100644
index 31dcc4fa5f28..000000000000
--- a/include/asm-sh/keyboard.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_SH_KEYBOARD_H
-#define __ASM_SH_KEYBOARD_H
-/*
- *      $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
- */
-#include <linux/kd.h>
-#include <asm/machvec.h>
-#ifdef CONFIG_SH_MPC1211
-#include <asm/mpc1211/keyboard-mpc1211.h>
-#endif
-#endif
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
index fe58d00b250c..87e812f68bb0 100644
--- a/include/asm-sh/mmu_context.h
+++ b/include/asm-sh/mmu_context.h
@@ -27,6 +27,7 @@
 /* ASID is 8-bit value, so it can't be 0x100 */
 #define MMU_NO_ASID                     0x100
+#ifdef CONFIG_MMU
 #define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
 #define cpu_context(cpu, mm)    ((mm)->context.id[cpu])
@@ -38,7 +39,6 @@
 */
 #define MMU_VPN_MASK    0xfffff000
-#ifdef CONFIG_MMU
 #if defined(CONFIG_SUPERH32)
 #include "mmu_context_32.h"
 #else
@@ -129,6 +129,8 @@ static inline void switch_mm(struct mm_struct *prev,
 #define destroy_context(mm)             do { } while (0)
 #define set_asid(asid)                  do { } while (0)
 #define get_asid()                      (0)
+#define cpu_asid(cpu, mm)               ({ (void)cpu; 0; })
+#define switch_and_save_asid(asid)      (0)
 #define set_TTB(pgd)                    do { } while (0)
 #define get_TTB()                       (0)
 #define activate_context(mm,cpu)        do { } while (0)
diff --git a/include/asm-sh/mmzone.h b/include/asm-sh/mmzone.h
index 7969f381dff2..2969253c4042 100644
--- a/include/asm-sh/mmzone.h
+++ b/include/asm-sh/mmzone.h
@@ -41,6 +41,8 @@ void __init plat_mem_setup(void);
 /* arch/sh/kernel/setup.c */
 void __init setup_bootmem_allocator(unsigned long start_pfn);
+void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
+                               unsigned long end_pfn);
 #endif /* __KERNEL__ */
 #endif /* __ASM_SH_MMZONE_H */
diff --git a/include/asm-sh/mpc1211/dma.h b/include/asm-sh/mpc1211/dma.h
deleted file mode 100644
index e506d1aaa0d0..000000000000
--- a/include/asm-sh/mpc1211/dma.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- */
-#ifndef _ASM_MPC1211_DMA_H
-#define _ASM_MPC1211_DMA_H
-#include <linux/spinlock.h>     /* And spinlocks */
-#include <asm/io.h>             /* need byte IO */
-#include <linux/delay.h>
-#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
-#define dma_outb        outb_p
-#else
-#define dma_outb        outb
-#endif
-#define dma_inb         inb
-/*
- * NOTES about DMA transfers:
- *
- *  controller 1: channels 0-3, byte operations, ports 00-1F
- *  controller 2: channels 4-7, word operations, ports C0-DF
- *
- *  - ALL registers are 8 bits only, regardless of transfer size
- *  - channel 4 is not used - cascades 1 into 2.
- *  - channels 0-3 are byte - addresses/counts are for physical bytes
- *  - channels 5-7 are word - addresses/counts are for physical words
- *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- *  - transfer count loaded to registers is 1 less than actual count
- *  - controller 2 offsets are all even (2x offsets for controller 1)
- *  - page registers for 5-7 don't use data bit 0, represent 128K pages
- *  - page registers for 0-3 use bit 0, represent 64K pages
- *
- * DMA transfers are limited to the lower 16MB of _physical_ memory.  
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- *  Address mapping for channels 0-3:
- *
- *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *   P7  ...  P0  A7 ... A0  A7 ... A0   
- * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
- *
- *  Address mapping for channels 5-7:
- *
- *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
- *    |  ...  |   \   \   ... \  \  \  ... \  \
- *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
- *    |  ...  |     \   \   ... \  \  \  ... \
- *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
- * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
- * the hardware level, so odd-byte transfers aren't possible).
- *
- * Transfer count (_not # bytes_) is limited to 64K, represented as actual
- * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
- *
- */
-#define MAX_DMA_CHANNELS        8
-/* The maximum address that we can perform a DMA transfer to on this platform */
-#define MAX_DMA_ADDRESS      (PAGE_OFFSET+0x10000000)
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
-/* DMA controller registers */
-#define DMA1_CMD_REG            0x08    /* command register (w) */
-#define DMA1_STAT_REG           0x08    /* status register (r) */
-#define DMA1_REQ_REG            0x09    /* request register (w) */
-#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
-#define DMA1_MODE_REG           0x0B    /* mode register (w) */
-#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
-#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
-#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
-#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
-#define DMA2_CMD_REG            0xD0    /* command register (w) */
-#define DMA2_STAT_REG           0xD0    /* status register (r) */
-#define DMA2_REQ_REG            0xD2    /* request register (w) */
-#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
-#define DMA2_MODE_REG           0xD6    /* mode register (w) */
-#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
-#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
-#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
-#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
-#define DMA_ADDR_0              0x00    /* DMA address registers */
-#define DMA_ADDR_1              0x02
-#define DMA_ADDR_2              0x04
-#define DMA_ADDR_3              0x06
-#define DMA_ADDR_4              0xC0
-#define DMA_ADDR_5              0xC4
-#define DMA_ADDR_6              0xC8
-#define DMA_ADDR_7              0xCC
-#define DMA_CNT_0               0x01    /* DMA count registers */
-#define DMA_CNT_1               0x03
-#define DMA_CNT_2               0x05
-#define DMA_CNT_3               0x07
-#define DMA_CNT_4               0xC2
-#define DMA_CNT_5               0xC6
-#define DMA_CNT_6               0xCA
-#define DMA_CNT_7               0xCE
-#define DMA_PAGE_0              0x87    /* DMA page registers */
-#define DMA_PAGE_1              0x83
-#define DMA_PAGE_2              0x81
-#define DMA_PAGE_3              0x82
-#define DMA_PAGE_5              0x8B
-#define DMA_PAGE_6              0x89
-#define DMA_PAGE_7              0x8A
-#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
-#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
-#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
-#define DMA_AUTOINIT    0x10
-extern spinlock_t  dma_spin_lock;
-static __inline__ unsigned long claim_dma_lock(void)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&dma_spin_lock, flags);
-        return flags;
-}
-static __inline__ void release_dma_lock(unsigned long flags)
-{
-        spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(dmanr,  DMA1_MASK_REG);
-        else
-                dma_outb(dmanr & 3,  DMA2_MASK_REG);
-}
-static __inline__ void disable_dma(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(dmanr | 4,  DMA1_MASK_REG);
-        else
-                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
-}
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while holding the DMA lock ! ---
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(0,  DMA1_CLEAR_FF_REG);
-        else
-                dma_outb(0,  DMA2_CLEAR_FF_REG);
-}
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
-        if (dmanr<=3)
-                dma_outb(mode | dmanr,  DMA1_MODE_REG);
-        else
-                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
-}
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register, but a 64k boundary
- * may have been crossed.
- */
-static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
-{
-        switch(dmanr) {
-                case 0:
-                        dma_outb( pagenr       & 0xff, DMA_PAGE_0);
-                        dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
-                        break;
-                case 1:
-                        dma_outb( pagenr       & 0xff, DMA_PAGE_1);
-                        dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
-                        break;
-                case 2:
-                        dma_outb( pagenr       & 0xff, DMA_PAGE_2);
-                        dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
-                        break;
-                case 3:
-                        dma_outb( pagenr       & 0xff, DMA_PAGE_3);
-                        dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
-                        break;
-                case 5:
-                        dma_outb( pagenr       & 0xfe, DMA_PAGE_5);
-                        dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
-                        break;
-                case 6:
-                        dma_outb( pagenr       & 0xfe, DMA_PAGE_6);
-                        dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
-                        break;
-                case 7:
-                        dma_outb( pagenr       & 0xfe, DMA_PAGE_7);
-                        dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
-                        break;
-        }
-}
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
-        set_dma_page(dmanr, a>>16);
-        if (dmanr <= 3)  {
-            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-        }  else  {
-            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-        }
-}
-/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-        count--;
-        if (dmanr <= 3)  {
-            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-        } else {
-            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-        }
-}
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
-        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
-                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
-        /* using short to get 16-bit wrap around */
-        unsigned short count;
-        count = 1 + dma_inb(io_port);
-        count += dma_inb(io_port) << 8;
-        return (dmanr<=3)? count : (count<<1);
-}
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
-extern void free_dma(unsigned int dmanr);       /* release it again */
-/* From PCI */
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy    (0)
-#endif
-#endif /* _ASM_MPC1211_DMA_H */
diff --git a/include/asm-sh/mpc1211/io.h b/include/asm-sh/mpc1211/io.h
deleted file mode 100644
index 6298370bec2d..000000000000
--- a/include/asm-sh/mpc1211/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * include/asm-sh/mpc1211/io.h
- *
- * Copyright 2001 Saito.K & Jeanne
- *
- * IO functions for an Interface MPC-1211
- */
-#ifndef _ASM_SH_IO_MPC1211_H
-#define _ASM_SH_IO_MPC1211_H
-#include <linux/time.h>
-extern int mpc1211_irq_demux(int irq);
-extern void init_mpc1211_IRQ(void);
-extern void heartbeat_mpc1211(void);
-extern void mpc1211_rtc_gettimeofday(struct timeval *tv);
-extern int mpc1211_rtc_settimeofday(const struct timeval *tv);
-#endif /* _ASM_SH_IO_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/keyboard.h b/include/asm-sh/mpc1211/keyboard.h
deleted file mode 100644
index 9020feee7b4c..000000000000
--- a/include/asm-sh/mpc1211/keyboard.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *  MPC1211 specific keybord definitions
- *  Taken from the old asm-i386/keybord.h for PC/AT-style definitions
- *  created 3 Nov 1996 by Geert Uytterhoeven.
- */
-#ifdef __KERNEL__
-#include <linux/kernel.h>
-#include <linux/ioport.h>
-#include <linux/kd.h>
-#include <linux/pm.h>
-#include <asm/io.h>
-#define KEYBOARD_IRQ                    1
-#define DISABLE_KBD_DURING_INTERRUPTS   0
-extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
-extern int pckbd_getkeycode(unsigned int scancode);
-extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
-                           char raw_mode);
-extern char pckbd_unexpected_up(unsigned char keycode);
-extern void pckbd_leds(unsigned char leds);
-extern void pckbd_init_hw(void);
-extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *);
-extern pm_callback pm_kbd_request_override;
-#define kbd_setkeycode          pckbd_setkeycode
-#define kbd_getkeycode          pckbd_getkeycode
-#define kbd_translate           pckbd_translate
-#define kbd_unexpected_up       pckbd_unexpected_up
-#define kbd_leds                pckbd_leds
-#define kbd_init_hw             pckbd_init_hw
-/* resource allocation */
-#define kbd_request_region()
-#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \
-                                             "keyboard", NULL)
-/* How to access the keyboard macros on this platform.  */
-#define kbd_read_input() inb(KBD_DATA_REG)
-#define kbd_read_status() inb(KBD_STATUS_REG)
-#define kbd_write_output(val) outb(val, KBD_DATA_REG)
-#define kbd_write_command(val) outb(val, KBD_CNTL_REG)
-/* Some stoneage hardware needs delays after some operations.  */
-#define kbd_pause() do { } while(0)
-/*
- * Machine specific bits for the PS/2 driver
- */
-#define AUX_IRQ 12
-#define aux_request_irq(hand, dev_id)                                   \
-        request_irq(AUX_IRQ, hand, IRQF_SHARED, "PS2 Mouse", dev_id)
-#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id)
-#endif /* __KERNEL__ */
diff --git a/include/asm-sh/mpc1211/m1543c.h b/include/asm-sh/mpc1211/m1543c.h
deleted file mode 100644
index c95d13236c3b..000000000000
--- a/include/asm-sh/mpc1211/m1543c.h
+++ /dev/null
@@ -1,200 +0,0 @@
-#ifndef __ASM_SH_M1543C_H
-#define __ASM_SH_M1543C_H
-/*
- * linux/include/asm-sh/m1543c.h
- * Copyright (C) 2001  Nobuhiro Sakawa
- * M1543C:PCI-ISA Bus Bridge with Super IO Chip support
- *
- * from
- *
- * linux/include/asm-sh/smc37c93x.h
- *
- * Copyright (C) 2000  Kazumoto Kojima
- *
- * SMSC 37C93x Super IO Chip support
- */
-/* Default base I/O address */
-#define FDC_PRIMARY_BASE        0x3f0
-#define IDE1_PRIMARY_BASE       0x1f0
-#define IDE1_SECONDARY_BASE     0x170
-#define PARPORT_PRIMARY_BASE    0x378
-#define COM1_PRIMARY_BASE       0x2f8
-#define COM2_PRIMARY_BASE       0x3f8
-#define COM3_PRIMARY_BASE       0x3e8
-#define RTC_PRIMARY_BASE        0x070
-#define KBC_PRIMARY_BASE        0x060
-#define AUXIO_PRIMARY_BASE      0x000   /* XXX */
-#define I8259_M_CR              0x20
-#define I8259_M_MR              0x21
-#define I8259_S_CR              0xa0
-#define I8259_S_MR              0xa1
-/* Logical device number */
-#define LDN_FDC                 0
-#define LDN_IDE1                1
-#define LDN_IDE2                2
-#define LDN_PARPORT             3
-#define LDN_COM1                4
-#define LDN_COM2                5
-#define LDN_COM3                11
-#define LDN_RTC                 6
-#define LDN_KBC                 7
-/* Configuration port and key */
-#define CONFIG_PORT             0x3f0
-#define INDEX_PORT              CONFIG_PORT
-#define DATA_PORT               0x3f1
-#define CONFIG_ENTER1           0x51
-#define CONFIG_ENTER2           0x23
-#define CONFIG_EXIT             0xbb
-/* Configuration index */
-#define CURRENT_LDN_INDEX       0x07
-#define POWER_CONTROL_INDEX     0x22
-#define ACTIVATE_INDEX          0x30
-#define IO_BASE_HI_INDEX        0x60
-#define IO_BASE_LO_INDEX        0x61
-#define IRQ_SELECT_INDEX        0x70
-#define PS2_IRQ_INDEX           0x72
-#define DMA_SELECT_INDEX        0x74
-/* UART stuff. Only for debugging.  */
-/* UART Register */
-#define UART_RBR        0x0     /* Receiver Buffer Register (Read Only) */
-#define UART_THR        0x0     /* Transmitter Holding Register (Write Only) */
-#define UART_IER        0x2     /* Interrupt Enable Register */
-#define UART_IIR        0x4     /* Interrupt Ident Register (Read Only) */
-#define UART_FCR        0x4     /* FIFO Control Register (Write Only) */
-#define UART_LCR        0x6     /* Line Control Register */
-#define UART_MCR        0x8     /* MODEM Control Register */
-#define UART_LSR        0xa     /* Line Status Register */
-#define UART_MSR        0xc     /* MODEM Status Register */
-#define UART_SCR        0xe     /* Scratch Register */
-#define UART_DLL        0x0     /* Divisor Latch (LS) */
-#define UART_DLM        0x2     /* Divisor Latch (MS) */
-#ifndef __ASSEMBLY__
-typedef struct uart_reg {
-        volatile __u16 rbr;
-        volatile __u16 ier;
-        volatile __u16 iir;
-        volatile __u16 lcr;
-        volatile __u16 mcr;
-        volatile __u16 lsr;
-        volatile __u16 msr;
-        volatile __u16 scr;
-} uart_reg;
-#endif /* ! __ASSEMBLY__ */
-/* Alias for Write Only Register */
-#define thr     rbr
-#define tcr     iir
-/* Alias for Divisor Latch Register */
-#define dll     rbr
-#define dlm     ier
-#define fcr     iir
-/* Interrupt Enable Register */
-#define IER_ERDAI       0x0100  /* Enable Received Data Available Interrupt */
-#define IER_ETHREI      0x0200  /* Enable Transmitter Holding Register Empty Interrupt */
-#define IER_ELSI        0x0400  /* Enable Receiver Line Status Interrupt */
-#define IER_EMSI        0x0800  /* Enable MODEM Status Interrupt */
-/* Interrupt Ident Register */
-#define IIR_IP          0x0100  /* "0" if Interrupt Pending */
-#define IIR_IIB0        0x0200  /* Interrupt ID Bit 0 */
-#define IIR_IIB1        0x0400  /* Interrupt ID Bit 1 */
-#define IIR_IIB2        0x0800  /* Interrupt ID Bit 2 */
-#define IIR_FIFO        0xc000  /* FIFOs enabled */
-/* FIFO Control Register */
-#define FCR_FEN         0x0100  /* FIFO enable */
-#define FCR_RFRES       0x0200  /* Receiver FIFO reset */
-#define FCR_TFRES       0x0400  /* Transmitter FIFO reset */
-#define FCR_DMA         0x0800  /* DMA mode select */
-#define FCR_RTL         0x4000  /* Receiver triger (LSB) */
-#define FCR_RTM         0x8000  /* Receiver triger (MSB) */
-/* Line Control Register */
-#define LCR_WLS0        0x0100  /* Word Length Select Bit 0 */
-#define LCR_WLS1        0x0200  /* Word Length Select Bit 1 */
-#define LCR_STB         0x0400  /* Number of Stop Bits */
-#define LCR_PEN         0x0800  /* Parity Enable */
-#define LCR_EPS         0x1000  /* Even Parity Select */
-#define LCR_SP          0x2000  /* Stick Parity */
-#define LCR_SB          0x4000  /* Set Break */
-#define LCR_DLAB        0x8000  /* Divisor Latch Access Bit */
-/* MODEM Control Register */
-#define MCR_DTR         0x0100  /* Data Terminal Ready */
-#define MCR_RTS         0x0200  /* Request to Send */
-#define MCR_OUT1        0x0400  /* Out 1 */
-#define MCR_IRQEN       0x0800  /* IRQ Enable */
-#define MCR_LOOP        0x1000  /* Loop */
-/* Line Status Register */
-#define LSR_DR          0x0100  /* Data Ready */
-#define LSR_OE          0x0200  /* Overrun Error */
-#define LSR_PE          0x0400  /* Parity Error */
-#define LSR_FE          0x0800  /* Framing Error */
-#define LSR_BI          0x1000  /* Break Interrupt */
-#define LSR_THRE        0x2000  /* Transmitter Holding Register Empty */
-#define LSR_TEMT        0x4000  /* Transmitter Empty */
-#define LSR_FIFOE       0x8000  /* Receiver FIFO error */
-/* MODEM Status Register */
-#define MSR_DCTS        0x0100  /* Delta Clear to Send */
-#define MSR_DDSR        0x0200  /* Delta Data Set Ready */
-#define MSR_TERI        0x0400  /* Trailing Edge Ring Indicator */
-#define MSR_DDCD        0x0800  /* Delta Data Carrier Detect */
-#define MSR_CTS         0x1000  /* Clear to Send */
-#define MSR_DSR         0x2000  /* Data Set Ready */
-#define MSR_RI          0x4000  /* Ring Indicator */
-#define MSR_DCD         0x8000  /* Data Carrier Detect */
-/* Baud Rate Divisor */
-#define UART_CLK        (1843200)       /* 1.8432 MHz */
-#define UART_BAUD(x)    (UART_CLK / (16 * (x)))
-/* RTC register definition */
-#define RTC_SECONDS             0
-#define RTC_SECONDS_ALARM       1
-#define RTC_MINUTES             2
-#define RTC_MINUTES_ALARM       3
-#define RTC_HOURS               4
-#define RTC_HOURS_ALARM         5
-#define RTC_DAY_OF_WEEK         6
-#define RTC_DAY_OF_MONTH        7
-#define RTC_MONTH               8
-#define RTC_YEAR                9
-#define RTC_FREQ_SELECT         10
-# define RTC_UIP 0x80
-# define RTC_DIV_CTL 0x70
-/* This RTC can work under 32.768KHz clock only.  */
-# define RTC_OSC_ENABLE 0x20
-# define RTC_OSC_DISABLE 0x00
-#define RTC_CONTROL             11
-# define RTC_SET 0x80
-# define RTC_PIE 0x40
-# define RTC_AIE 0x20
-# define RTC_UIE 0x10
-# define RTC_SQWE 0x08
-# define RTC_DM_BINARY 0x04
-# define RTC_24H 0x02
-# define RTC_DST_EN 0x01
-#endif  /* __ASM_SH_M1543C_H */
diff --git a/include/asm-sh/mpc1211/mc146818rtc.h b/include/asm-sh/mpc1211/mc146818rtc.h
deleted file mode 100644
index e245f2a3cd78..000000000000
--- a/include/asm-sh/mpc1211/mc146818rtc.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- * MPC1211 uses PC/AT style RTC definitions.
- */
-#include <asm-x86/mc146818rtc_32.h>
diff --git a/include/asm-sh/mpc1211/mpc1211.h b/include/asm-sh/mpc1211/mpc1211.h
deleted file mode 100644
index fa456c3e4e01..000000000000
--- a/include/asm-sh/mpc1211/mpc1211.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __ASM_SH_MPC1211_H
-#define __ASM_SH_MPC1211_H
-/*
- * linux/include/asm-sh/mpc1211.h
- *
- * Copyright (C) 2001  Saito.K & Jeanne
- *
- * Interface MPC-1211 support
- */
-#define PA_PCI_IO       (0xa4000000)    /* PCI I/O space */
-#define PA_PCI_MEM      (0xb0000000)    /* PCI MEM space */
-#define PCIPAR          (0xa4000cf8)    /* PCI Config address */
-#define PCIPDR          (0xa4000cfc)    /* PCI Config data    */
-#endif  /* __ASM_SH_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/pci.h b/include/asm-sh/mpc1211/pci.h
deleted file mode 100644
index d9162c5ed76a..000000000000
--- a/include/asm-sh/mpc1211/pci.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *      Low-Level PCI Support for MPC-1211
- *
- *      (c) 2002 Saito.K & Jeanne
- *
- */
-#ifndef _PCI_MPC1211_H_
-#define _PCI_MPC1211_H_
-#include <linux/pci.h>
-/* set debug level 4=verbose...1=terse */
-//#define DEBUG_PCI 3
-#undef DEBUG_PCI
-#ifdef DEBUG_PCI
-#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
-#else
-#define PCIDBG(n, x...)
-#endif
-/* startup values */
-#define PCI_PROBE_BIOS    1
-#define PCI_PROBE_CONF1   2
-#define PCI_PROBE_CONF2   4
-#define PCI_NO_CHECKS     0x400
-#define PCI_ASSIGN_ROMS   0x1000
-#define PCI_BIOS_IRQ_SCAN 0x2000
-/* MPC-1211 Specific Values */
-#define PCIPAR            (0xa4000cf8)    /* PCI Config address */
-#define PCIPDR            (0xa4000cfc)    /* PCI Config data    */
-#define PA_PCI_IO         (0xa4000000)    /* PCI I/O space */
-#define PA_PCI_MEM        (0xb0000000)    /* PCI MEM space */
-#endif /* _PCI_MPC1211_H_ */
diff --git a/include/asm-sh/r7780rp.h b/include/asm-sh/r7780rp.h
index a33838f23a6d..306f7359f7d4 100644
--- a/include/asm-sh/r7780rp.h
+++ b/include/asm-sh/r7780rp.h
@@ -193,8 +193,6 @@
 #define IRQ_SCIF0               (HL_FPGA_IRQ_BASE + 15)
 #define IRQ_SCIF1               (HL_FPGA_IRQ_BASE + 16)
-unsigned char *highlander_init_irq_r7780mp(void);
+unsigned char *highlander_plat_irq_setup(void);
-unsigned char *highlander_init_irq_r7780rp(void);
-unsigned char *highlander_init_irq_r7785rp(void);
 #endif  /* __ASM_SH_RENESAS_R7780RP */
diff --git a/include/asm-sh/tlb_64.h b/include/asm-sh/tlb_64.h
index 0308e05fc57b..0a96f3af69e3 100644
--- a/include/asm-sh/tlb_64.h
+++ b/include/asm-sh/tlb_64.h
@@ -56,6 +56,7 @@ static inline void __flush_tlb_slot(unsigned long long slot)
        __asm__ __volatile__ ("putcfg %0, 0, r63\n" : : "r" (slot));
 }
+#ifdef CONFIG_MMU
 /* arch/sh64/mm/tlb.c */
 int sh64_tlb_init(void);
 unsigned long long sh64_next_free_dtlb_entry(void);
@@ -64,6 +65,13 @@ int sh64_put_wired_dtlb_entry(unsigned long long entry);
 void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
                         unsigned long asid, unsigned long paddr);
 void sh64_teardown_tlb_slot(unsigned long long config_addr);
+#else
+#define sh64_tlb_init()                                 do { } while (0)
+#define sh64_next_free_dtlb_entry()                     (0)
+#define sh64_get_wired_dtlb_entry()                     (0)
+#define sh64_put_wired_dtlb_entry(entry)                do { } while (0)
+#define sh64_setup_tlb_slot(conf, virt, asid, phys)     do { } while (0)
+#define sh64_teardown_tlb_slot(addr)                    do { } while (0)
+#endif /* CONFIG_MMU */
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_SH_TLB_64_H */
diff --git a/include/asm-sh/topology.h b/include/asm-sh/topology.h
index 34cdb28e8f44..95f0085e098a 100644
--- a/include/asm-sh/topology.h
+++ b/include/asm-sh/topology.h
@@ -29,6 +29,17 @@
        .nr_balance_failed      = 0,                    \
 }
+#define cpu_to_node(cpu)        ((void)(cpu),0)
+#define parent_node(node)       ((void)(node),0)
+#define node_to_cpumask(node)   ((void)node, cpu_online_map)
+#define node_to_first_cpu(node) ((void)(node),0)
+#define pcibus_to_node(bus)     ((void)(bus), -1)
+#define pcibus_to_cpumask(bus)  (pcibus_to_node(bus) == -1 ? \
+                                        CPU_MASK_ALL : \
+                                        node_to_cpumask(pcibus_to_node(bus)) \
+                                )
 #endif
 #include <asm-generic/topology.h>
diff --git a/include/asm-sh/uaccess_64.h b/include/asm-sh/uaccess_64.h
index f956b7b316c7..a9b68d094844 100644
--- a/include/asm-sh/uaccess_64.h
+++ b/include/asm-sh/uaccess_64.h
@@ -274,7 +274,9 @@ struct exception_table_entry
        unsigned long insn, fixup;
 };
+#ifdef CONFIG_MMU
 #define ARCH_HAS_SEARCH_EXTABLE
+#endif
 /* Returns 0 if exception not found and fixup.unit otherwise.  */
 extern unsigned long search_exception_table(unsigned long addr);
diff --git a/include/asm-x86/bitops.h b/include/asm-x86/bitops.h
index b81a4d4d3337..ee4b3ead6a43 100644
--- a/include/asm-x86/bitops.h
+++ b/include/asm-x86/bitops.h
@@ -23,13 +23,10 @@
 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
 /* Technically wrong, but this avoids compilation errors on some gcc
   versions. */
-#define ADDR "=m" (*(volatile long *)addr)
+#define ADDR "=m" (*(volatile long *) addr)
-#define BIT_ADDR "=m" (((volatile int *)addr)[nr >> 5])
 #else
 #define ADDR "+m" (*(volatile long *) addr)
-#define BIT_ADDR "+m" (((volatile int *)addr)[nr >> 5])
 #endif
-#define BASE_ADDR "m" (*(volatile int *)addr)
 /**
 * set_bit - Atomically set a bit in memory
@@ -77,7 +74,7 @@ static inline void __set_bit(int nr, volatile void *addr)
 */
 static inline void clear_bit(int nr, volatile void *addr)
 {
-        asm volatile(LOCK_PREFIX "btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
+        asm volatile(LOCK_PREFIX "btr %1,%0" : ADDR : "Ir" (nr));
 }
 /*
@@ -96,7 +93,7 @@ static inline void clear_bit_unlock(unsigned nr, volatile void *addr)
 static inline void __clear_bit(int nr, volatile void *addr)
 {
-        asm volatile("btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
+        asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
 }
 /*
@@ -131,7 +128,7 @@ static inline void __clear_bit_unlock(unsigned nr, volatile void *addr)
 */
 static inline void __change_bit(int nr, volatile void *addr)
 {
-        asm volatile("btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
+        asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
 }
 /**
@@ -145,7 +142,7 @@ static inline void __change_bit(int nr, volatile void *addr)
 */
 static inline void change_bit(int nr, volatile void *addr)
 {
-        asm volatile(LOCK_PREFIX "btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
+        asm volatile(LOCK_PREFIX "btc %1,%0" : ADDR : "Ir" (nr));
 }
 /**
@@ -191,9 +188,10 @@ static inline int __test_and_set_bit(int nr, volatile void *addr)
 {
        int oldbit;
-        asm volatile("bts %2,%3\n\t"
+        asm("bts %2,%1\n\t"
-                     "sbb %0,%0"
+            "sbb %0,%0"
-                     : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
+            : "=r" (oldbit), ADDR
+            : "Ir" (nr));
        return oldbit;
 }
@@ -229,9 +227,10 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr)
 {
        int oldbit;
-        asm volatile("btr %2,%3\n\t"
+        asm volatile("btr %2,%1\n\t"
                     "sbb %0,%0"
-                     : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
+                     : "=r" (oldbit), ADDR
+                     : "Ir" (nr));
        return oldbit;
 }
@@ -240,9 +239,10 @@ static inline int __test_and_change_bit(int nr, volatile void *addr)
 {
        int oldbit;
-        asm volatile("btc %2,%3\n\t"
+        asm volatile("btc %2,%1\n\t"
                     "sbb %0,%0"
-                     : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
+                     : "=r" (oldbit), ADDR
+                     : "Ir" (nr) : "memory");
        return oldbit;
 }
@@ -276,11 +276,10 @@ static inline int variable_test_bit(int nr, volatile const void *addr)
 {
        int oldbit;
-        asm volatile("bt %2,%3\n\t"
+        asm volatile("bt %2,%1\n\t"
                     "sbb %0,%0"
                     : "=r" (oldbit)
-                     : "m" (((volatile const int *)addr)[nr >> 5]),
+                     : "m" (*(unsigned long *)addr), "Ir" (nr));
-                       "Ir" (nr), BASE_ADDR);
        return oldbit;
 }
@@ -397,8 +396,6 @@ static inline int fls(int x)
 }
 #endif /* __KERNEL__ */
-#undef BASE_ADDR
-#undef BIT_ADDR
 #undef ADDR
 static inline void set_bit_string(unsigned long *bitmap,
diff --git a/include/asm-x86/geode.h b/include/asm-x86/geode.h
index 7154dc4de951..6e6458853a36 100644
--- a/include/asm-x86/geode.h
+++ b/include/asm-x86/geode.h
@@ -185,16 +185,14 @@ static inline int is_geode(void)
        return (is_geode_gx() || is_geode_lx());
 }
-/*
+#ifdef CONFIG_MGEODE_LX
- * The VSA has virtual registers that we can query for a signature.
+extern int geode_has_vsa2(void);
- */
+#else
 static inline int geode_has_vsa2(void)
 {
-        outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
+        return 0;
-        outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
-        return (inw(VSA_VRC_DATA) == VSA_SIG);
 }
+#endif
 /* MFGPTs */
diff --git a/include/asm-x86/i387.h b/include/asm-x86/i387.h
index da2adb45f6e3..6b722d315936 100644
--- a/include/asm-x86/i387.h
+++ b/include/asm-x86/i387.h
@@ -175,7 +175,15 @@ static inline int save_i387(struct _fpstate __user *buf)
 */
 static inline int restore_i387(struct _fpstate __user *buf)
 {
-        set_used_math();
+        struct task_struct *tsk = current;
+        int err;
+        if (!used_math()) {
+                err = init_fpu(tsk);
+                if (err)
+                        return err;
+        }
        if (!(task_thread_info(current)->status & TS_USEDFPU)) {
                clts();
                task_thread_info(current)->status |= TS_USEDFPU;
diff --git a/include/asm-x86/pat.h b/include/asm-x86/pat.h
index 8b822b5a1786..88f60cc6a227 100644
--- a/include/asm-x86/pat.h
+++ b/include/asm-x86/pat.h
@@ -4,7 +4,13 @@
 #include <linux/types.h>
+#ifdef CONFIG_X86_PAT
 extern int pat_wc_enabled;
+extern void validate_pat_support(struct cpuinfo_x86 *c);
+#else
+static const int pat_wc_enabled = 0;
+static inline void validate_pat_support(struct cpuinfo_x86 *c) { }
+#endif
 extern void pat_init(void);
@@ -12,5 +18,7 @@ extern int reserve_memtype(u64 start, u64 end,
                unsigned long req_type, unsigned long *ret_type);
 extern int free_memtype(u64 start, u64 end);
+extern void pat_disable(char *reason);
 #endif
diff --git a/include/asm-x86/spinlock.h b/include/asm-x86/spinlock.h
index bc6376f1bc5a..21e89bf92f1c 100644
--- a/include/asm-x86/spinlock.h
+++ b/include/asm-x86/spinlock.h
@@ -20,18 +20,8 @@
 */
 #ifdef CONFIG_X86_32
-typedef char _slock_t;
-# define LOCK_INS_DEC "decb"
-# define LOCK_INS_XCH "xchgb"
-# define LOCK_INS_MOV "movb"
-# define LOCK_INS_CMP "cmpb"
 # define LOCK_PTR_REG "a"
 #else
-typedef int _slock_t;
-# define LOCK_INS_DEC "decl"
-# define LOCK_INS_XCH "xchgl"
-# define LOCK_INS_MOV "movl"
-# define LOCK_INS_CMP "cmpl"
 # define LOCK_PTR_REG "D"
 #endif
@@ -66,14 +56,14 @@ typedef int _slock_t;
 #if (NR_CPUS < 256)
 static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
 {
-        int tmp = *(volatile signed int *)(&(lock)->slock);
+        int tmp = ACCESS_ONCE(lock->slock);
        return (((tmp >> 8) & 0xff) != (tmp & 0xff));
 }
 static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
 {
-        int tmp = *(volatile signed int *)(&(lock)->slock);
+        int tmp = ACCESS_ONCE(lock->slock);
        return (((tmp >> 8) & 0xff) - (tmp & 0xff)) > 1;
 }
@@ -130,14 +120,14 @@ static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
 #else
 static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
 {
-        int tmp = *(volatile signed int *)(&(lock)->slock);
+        int tmp = ACCESS_ONCE(lock->slock);
        return (((tmp >> 16) & 0xffff) != (tmp & 0xffff));
 }
 static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
 {
-        int tmp = *(volatile signed int *)(&(lock)->slock);
+        int tmp = ACCESS_ONCE(lock->slock);
        return (((tmp >> 16) & 0xffff) - (tmp & 0xffff)) > 1;
 }
diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h
index 4f35a0fb4f22..dcf3f8131d6b 100644
--- a/include/asm-x86/topology.h
+++ b/include/asm-x86/topology.h
@@ -25,6 +25,16 @@
 #ifndef _ASM_X86_TOPOLOGY_H
 #define _ASM_X86_TOPOLOGY_H
+#ifdef CONFIG_X86_32
+# ifdef CONFIG_X86_HT
+#  define ENABLE_TOPO_DEFINES
+# endif
+#else
+# ifdef CONFIG_SMP
+#  define ENABLE_TOPO_DEFINES
+# endif
+#endif
 #ifdef CONFIG_NUMA
 #include <linux/cpumask.h>
 #include <asm/mpspec.h>
@@ -130,10 +140,6 @@ extern unsigned long node_end_pfn[];
 extern unsigned long node_remap_size[];
 #define node_has_online_mem(nid) (node_start_pfn[nid] != node_end_pfn[nid])
-# ifdef CONFIG_X86_HT
-#  define ENABLE_TOPO_DEFINES
-# endif
 # define SD_CACHE_NICE_TRIES    1
 # define SD_IDLE_IDX            1
 # define SD_NEWIDLE_IDX         2
@@ -141,10 +147,6 @@ extern unsigned long node_remap_size[];
 #else
-# ifdef CONFIG_SMP
-#  define ENABLE_TOPO_DEFINES
-# endif
 # define SD_CACHE_NICE_TRIES    2
 # define SD_IDLE_IDX            2
 # define SD_NEWIDLE_IDX         2
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index dcae0c8d97e6..c8bd2daf95ec 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -182,4 +182,16 @@ extern void __chk_io_ptr(const volatile void __iomem *);
 # define __section(S) __attribute__ ((__section__(#S)))
 #endif
+/*
+ * Prevent the compiler from merging or refetching accesses.  The compiler
+ * is also forbidden from reordering successive instances of ACCESS_ONCE(),
+ * but only when the compiler is aware of some particular ordering.  One way
+ * to make the compiler aware of ordering is to put the two invocations of
+ * ACCESS_ONCE() in different C statements.
+ *
+ * This macro does absolutely -nothing- to prevent the CPU from reordering,
+ * merging, or refetching absolutely anything at any time.
+ */
+#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
 #endif /* __LINUX_COMPILER_H */
diff --git a/include/linux/exportfs.h b/include/linux/exportfs.h
index de8387b7ceb6..f5abd1306638 100644
--- a/include/linux/exportfs.h
+++ b/include/linux/exportfs.h
@@ -33,6 +33,19 @@ enum fid_type {
         * 32 bit parent directory inode number.
         */
        FILEID_INO32_GEN_PARENT = 2,
+        /*
+         * 32 bit block number, 16 bit partition reference,
+         * 16 bit unused, 32 bit generation number.
+         */
+        FILEID_UDF_WITHOUT_PARENT = 0x51,
+        /*
+         * 32 bit block number, 16 bit partition reference,
+         * 16 bit unused, 32 bit generation number,
+         * 32 bit parent block number, 32 bit parent generation number
+         */
+        FILEID_UDF_WITH_PARENT = 0x52,
 };
 struct fid {
@@ -43,6 +56,14 @@ struct fid {
                        u32 parent_ino;
                        u32 parent_gen;
                } i32;
+                struct {
+                        u32 block;
+                        u16 partref;
+                        u16 parent_partref;
+                        u32 generation;
+                        u32 parent_block;
+                        u32 parent_generation;
+                } udf;
                __u32 raw[0];
        };
 };
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 7e0fa9e64479..f413085f748e 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -1816,7 +1816,6 @@ extern void iget_failed(struct inode *);
 extern void clear_inode(struct inode *);
 extern void destroy_inode(struct inode *);
 extern struct inode *new_inode(struct super_block *);
-extern int __remove_suid(struct dentry *, int);
 extern int should_remove_suid(struct dentry *);
 extern int remove_suid(struct dentry *);
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index ecd2bf63fc84..e9874e7fcdf9 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -178,17 +178,17 @@ static inline struct hd_struct *get_part(struct gendisk *gendiskp,
 static inline void disk_stat_set_all(struct gendisk *gendiskp, int value)       {
        int i;
        for_each_possible_cpu(i)
                memset(per_cpu_ptr(gendiskp->dkstats, i), value,
-                                sizeof (struct disk_stats));
+                                sizeof(struct disk_stats));
 }               
 #define __part_stat_add(part, field, addnd)                             \
        (per_cpu_ptr(part->dkstats, smp_processor_id())->field += addnd)
-#define __all_stat_add(gendiskp, field, addnd, sector)          \
+#define __all_stat_add(gendiskp, part, field, addnd, sector)    \
 ({                                                              \
-        struct hd_struct *part = get_part(gendiskp, sector);    \
        if (part)                                               \
                __part_stat_add(part, field, addnd);            \
        __disk_stat_add(gendiskp, field, addnd);                \
@@ -203,11 +203,13 @@ static inline void disk_stat_set_all(struct gendisk *gendiskp, int value)	{
        res;                                                            \
 })
-static inline void part_stat_set_all(struct hd_struct *part, int value) {
+static inline void part_stat_set_all(struct hd_struct *part, int value)
+{
        int i;
        for_each_possible_cpu(i)
                memset(per_cpu_ptr(part->dkstats, i), value,
-                       sizeof(struct disk_stats));
+                                sizeof(struct disk_stats));
 }
                                
 #else /* !CONFIG_SMP */
@@ -223,9 +225,8 @@ static inline void disk_stat_set_all(struct gendisk *gendiskp, int value)
 #define __part_stat_add(part, field, addnd) \
        (part->dkstats.field += addnd)
-#define __all_stat_add(gendiskp, field, addnd, sector)          \
+#define __all_stat_add(gendiskp, part, field, addnd, sector)    \
 ({                                                              \
-        struct hd_struct *part = get_part(gendiskp, sector);    \
        if (part)                                               \
                part->dkstats.field += addnd;                   \
        __disk_stat_add(gendiskp, field, addnd);                \
@@ -276,10 +277,10 @@ static inline void part_stat_set_all(struct hd_struct *part, int value)
 #define part_stat_sub(gendiskp, field, subnd) \
                part_stat_add(gendiskp, field, -subnd)
-#define all_stat_add(gendiskp, field, addnd, sector)            \
+#define all_stat_add(gendiskp, part, field, addnd, sector)      \
        do {                                                    \
                preempt_disable();                              \
-                __all_stat_add(gendiskp, field, addnd, sector); \
+                __all_stat_add(gendiskp, part, field, addnd, sector);   \
                preempt_enable();                               \
        } while (0)
@@ -288,15 +289,15 @@ static inline void part_stat_set_all(struct hd_struct *part, int value)
 #define all_stat_dec(gendiskp, field, sector) \
                all_stat_add(gendiskp, field, -1, sector)
-#define __all_stat_inc(gendiskp, field, sector) \
+#define __all_stat_inc(gendiskp, part, field, sector) \
-                __all_stat_add(gendiskp, field, 1, sector)
+                __all_stat_add(gendiskp, part, field, 1, sector)
-#define all_stat_inc(gendiskp, field, sector) \
+#define all_stat_inc(gendiskp, part, field, sector) \
-                all_stat_add(gendiskp, field, 1, sector)
+                all_stat_add(gendiskp, part, field, 1, sector)
-#define __all_stat_sub(gendiskp, field, subnd, sector) \
+#define __all_stat_sub(gendiskp, part, field, subnd, sector) \
-                __all_stat_add(gendiskp, field, -subnd, sector)
+                __all_stat_add(gendiskp, part, field, -subnd, sector)
-#define all_stat_sub(gendiskp, field, subnd, sector) \
+#define all_stat_sub(gendiskp, part, field, subnd, sector) \
-                all_stat_add(gendiskp, field, -subnd, sector)
+                all_stat_add(gendiskp, part, field, -subnd, sector)
 /* Inlines to alloc and free disk stats in struct gendisk */
 #ifdef  CONFIG_SMP
diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h
index 897f723bd222..181006cc94a0 100644
--- a/include/linux/hardirq.h
+++ b/include/linux/hardirq.h
@@ -72,6 +72,14 @@
 #define in_softirq()            (softirq_count())
 #define in_interrupt()          (irq_count())
+#if defined(CONFIG_PREEMPT)
+# define PREEMPT_INATOMIC_BASE kernel_locked()
+# define PREEMPT_CHECK_OFFSET 1
+#else
+# define PREEMPT_INATOMIC_BASE 0
+# define PREEMPT_CHECK_OFFSET 0
+#endif
 /*
 * Are we running in atomic context?  WARNING: this macro cannot
 * always detect atomic context; in particular, it cannot know about
@@ -79,17 +87,11 @@
 * used in the general case to determine whether sleeping is possible.
 * Do not use in_atomic() in driver code.
 */
-#define in_atomic()             ((preempt_count() & ~PREEMPT_ACTIVE) != 0)
+#define in_atomic()     ((preempt_count() & ~PREEMPT_ACTIVE) != PREEMPT_INATOMIC_BASE)
-#ifdef CONFIG_PREEMPT
-# define PREEMPT_CHECK_OFFSET 1
-#else
-# define PREEMPT_CHECK_OFFSET 0
-#endif
 /*
 * Check whether we were atomic before we did preempt_disable():
- * (used by the scheduler)
+ * (used by the scheduler, *after* releasing the kernel lock)
 */
 #define in_atomic_preempt_off() \
                ((preempt_count() & ~PREEMPT_ACTIVE) != PREEMPT_CHECK_OFFSET)
diff --git a/include/linux/ioprio.h b/include/linux/ioprio.h
index 2a3bb1bb7433..f98a656b17e5 100644
--- a/include/linux/ioprio.h
+++ b/include/linux/ioprio.h
@@ -68,6 +68,20 @@ static inline int task_nice_ioprio(struct task_struct *task)
 }
 /*
+ * This is for the case where the task hasn't asked for a specific IO class.
+ * Check for idle and rt task process, and return appropriate IO class.
+ */
+static inline int task_nice_ioclass(struct task_struct *task)
+{
+        if (task->policy == SCHED_IDLE)
+                return IOPRIO_CLASS_IDLE;
+        else if (task->policy == SCHED_FIFO || task->policy == SCHED_RR)
+                return IOPRIO_CLASS_RT;
+        else
+                return IOPRIO_CLASS_BE;
+}
+/*
 * For inheritance, return the highest of the two given priorities
 */
 extern int ioprio_best(unsigned short aprio, unsigned short bprio);
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index 30e11aa3c1c9..a15cdd4a8e58 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -1,19 +1,31 @@
 /*
 * MV-643XX ethernet platform device data definition file.
 */
 #ifndef __LINUX_MV643XX_ETH_H
 #define __LINUX_MV643XX_ETH_H
-#define MV643XX_ETH_SHARED_NAME         "mv643xx_eth_shared"
+#include <linux/mbus.h>
-#define MV643XX_ETH_NAME                "mv643xx_eth"
+#define MV643XX_ETH_SHARED_NAME         "mv643xx_eth"
+#define MV643XX_ETH_NAME                "mv643xx_eth_port"
 #define MV643XX_ETH_SHARED_REGS         0x2000
 #define MV643XX_ETH_SHARED_REGS_SIZE    0x2000
 #define MV643XX_ETH_BAR_4               0x2220
 #define MV643XX_ETH_SIZE_REG_4          0x2224
 #define MV643XX_ETH_BASE_ADDR_ENABLE_REG        0x2290
+struct mv643xx_eth_shared_platform_data {
+        struct mbus_dram_target_info    *dram;
+        unsigned int    t_clk;
+};
 struct mv643xx_eth_platform_data {
+        struct platform_device  *shared;
        int             port_number;
+        struct platform_device  *shared_smi;
        u16             force_phy_addr; /* force override if phy_addr == 0 */
        u16             phy_addr;
diff --git a/include/linux/netfilter/nf_conntrack_sip.h b/include/linux/netfilter/nf_conntrack_sip.h
index 5da04e586a3f..23aa2ec6b7b7 100644
--- a/include/linux/netfilter/nf_conntrack_sip.h
+++ b/include/linux/netfilter/nf_conntrack_sip.h
@@ -7,6 +7,7 @@
 struct nf_ct_sip_master {
        unsigned int    register_cseq;
+        unsigned int    invite_cseq;
 };
 enum sip_expectation_classes {
diff --git a/include/linux/of_i2c.h b/include/linux/of_i2c.h
index 2e5a96732042..bd2a870ec296 100644
--- a/include/linux/of_i2c.h
+++ b/include/linux/of_i2c.h
@@ -14,11 +14,7 @@
 #include <linux/i2c.h>
-#ifdef CONFIG_OF_I2C
 void of_register_i2c_devices(struct i2c_adapter *adap,
                             struct device_node *adap_node);
-#endif /* CONFIG_OF_I2C */
 #endif /* __LINUX_OF_I2C_H */
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 02df20f085fe..7224c4099a28 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -412,6 +412,8 @@ int mdiobus_register(struct mii_bus *bus);
 void mdiobus_unregister(struct mii_bus *bus);
 void phy_sanitize_settings(struct phy_device *phydev);
 int phy_stop_interrupts(struct phy_device *phydev);
+int phy_enable_interrupts(struct phy_device *phydev);
+int phy_disable_interrupts(struct phy_device *phydev);
 static inline int phy_read_status(struct phy_device *phydev) {
        return phydev->drv->read_status(phydev);
@@ -447,5 +449,8 @@ int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
                int (*run)(struct phy_device *));
 int phy_scan_fixups(struct phy_device *phydev);
+int __init mdio_bus_init(void);
+void mdio_bus_exit(void);
 extern struct bus_type mdio_bus_type;
 #endif /* __PHY_H */
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index 8082d6587a0f..d42dbec06083 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -131,18 +131,6 @@ struct rcu_head {
 */
 #define rcu_read_unlock_bh() __rcu_read_unlock_bh()
-/*
- * Prevent the compiler from merging or refetching accesses.  The compiler
- * is also forbidden from reordering successive instances of ACCESS_ONCE(),
- * but only when the compiler is aware of some particular ordering.  One way
- * to make the compiler aware of ordering is to put the two invocations of
- * ACCESS_ONCE() in different C statements.
- *
- * This macro does absolutely -nothing- to prevent the CPU from reordering,
- * merging, or refetching absolutely anything at any time.
- */
-#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
 /**
 * rcu_dereference - fetch an RCU-protected pointer in an
 * RCU read-side critical section.  This pointer may later
diff --git a/include/linux/vermagic.h b/include/linux/vermagic.h
index 4d0909e53595..79b9837d9ca0 100644
--- a/include/linux/vermagic.h
+++ b/include/linux/vermagic.h
@@ -17,6 +17,11 @@
 #else
 #define MODULE_VERMAGIC_MODULE_UNLOAD ""
 #endif
+#ifdef CONFIG_MODVERSIONS
+#define MODULE_VERMAGIC_MODVERSIONS "modversions "
+#else
+#define MODULE_VERMAGIC_MODVERSIONS ""
+#endif
 #ifndef MODULE_ARCH_VERMAGIC
 #define MODULE_ARCH_VERMAGIC ""
 #endif
@@ -24,5 +29,6 @@
 #define VERMAGIC_STRING                                                 \
        UTS_RELEASE " "                                                 \
        MODULE_VERMAGIC_SMP MODULE_VERMAGIC_PREEMPT                     \
-        MODULE_VERMAGIC_MODULE_UNLOAD MODULE_ARCH_VERMAGIC
+        MODULE_VERMAGIC_MODULE_UNLOAD MODULE_VERMAGIC_MODVERSIONS       \
+        MODULE_ARCH_VERMAGIC