aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-ixp23xx/platform.h6
-rw-r--r--include/asm-arm/arch-ns9xxx/clock.h6
-rw-r--r--include/asm-arm/arch-ns9xxx/gpio.h47
-rw-r--r--include/asm-arm/arch-ns9xxx/hardware.h47
-rw-r--r--include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h4
-rw-r--r--include/asm-arm/arch-ns9xxx/system.h4
-rw-r--r--include/asm-arm/arch-omap/blizzard.h12
-rw-r--r--include/asm-arm/arch-omap/board-2430sdp.h44
-rw-r--r--include/asm-arm/arch-omap/board-palmte.h34
-rw-r--r--include/asm-arm/arch-omap/board-palmtt.h23
-rw-r--r--include/asm-arm/arch-omap/board-palmz71.h26
-rw-r--r--include/asm-arm/arch-omap/board-sx1.h46
-rw-r--r--include/asm-arm/arch-omap/board.h4
-rw-r--r--include/asm-arm/arch-omap/dma.h1
-rw-r--r--include/asm-arm/arch-omap/eac.h101
-rw-r--r--include/asm-arm/arch-omap/gpmc.h5
-rw-r--r--include/asm-arm/arch-omap/hardware.h20
-rw-r--r--include/asm-arm/arch-omap/io.h10
-rw-r--r--include/asm-arm/arch-omap/menelaus.h20
-rw-r--r--include/asm-arm/arch-omap/mmc.h66
-rw-r--r--include/asm-arm/arch-omap/mux.h23
-rw-r--r--include/asm-arm/arch-omap/omap24xx.h12
-rw-r--r--include/asm-arm/arch-omap/onenand.h21
-rw-r--r--include/asm-arm/arch-pxa/cm-x270.h50
-rw-r--r--include/asm-arm/arch-pxa/dma.h4
-rw-r--r--include/asm-arm/arch-pxa/gpio.h12
-rw-r--r--include/asm-arm/arch-pxa/hardware.h99
-rw-r--r--include/asm-arm/arch-pxa/irqs.h27
-rw-r--r--include/asm-arm/arch-pxa/memory.h10
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa300.h574
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa320.h446
-rw-r--r--include/asm-arm/arch-pxa/mfp.h576
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h2
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx-regs.h75
-rw-r--r--include/asm-arm/arch-pxa/timex.h2
-rw-r--r--include/asm-arm/arch-pxa/zylonite.h35
-rw-r--r--include/asm-arm/arch-rpc/uncompress.h72
-rw-r--r--include/asm-arm/arch-s3c2410/irqs.h7
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h10
-rw-r--r--include/asm-arm/arch-s3c2410/regs-power.h5
-rw-r--r--include/asm-arm/arch-s3c2410/regs-s3c2412.h2
-rw-r--r--include/asm-arm/arch-sa1100/SA-1101.h4
-rw-r--r--include/asm-arm/dma-mapping.h14
-rw-r--r--include/asm-arm/hardware/it8152.h99
-rw-r--r--include/asm-arm/kexec.h2
-rw-r--r--include/asm-arm/pci.h7
-rw-r--r--include/asm-arm/unistd.h1
-rw-r--r--include/linux/pci_ids.h1
48 files changed, 2642 insertions, 76 deletions
diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h
index 56e16d66645a..db8aa304c93d 100644
--- a/include/asm-arm/arch-ixp23xx/platform.h
+++ b/include/asm-arm/arch-ixp23xx/platform.h
@@ -14,17 +14,17 @@
14 14
15#ifndef __ASSEMBLY__ 15#ifndef __ASSEMBLY__
16 16
17extern inline unsigned long ixp2000_reg_read(volatile void *reg) 17static inline unsigned long ixp2000_reg_read(volatile void *reg)
18{ 18{
19 return *((volatile unsigned long *)reg); 19 return *((volatile unsigned long *)reg);
20} 20}
21 21
22extern inline void ixp2000_reg_write(volatile void *reg, unsigned long val) 22static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
23{ 23{
24 *((volatile unsigned long *)reg) = val; 24 *((volatile unsigned long *)reg) = val;
25} 25}
26 26
27extern inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) 27static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
28{ 28{
29 *((volatile unsigned long *)reg) = val; 29 *((volatile unsigned long *)reg) = val;
30} 30}
diff --git a/include/asm-arm/arch-ns9xxx/clock.h b/include/asm-arm/arch-ns9xxx/clock.h
index bf30cbdcc2bf..b943d3a92a1d 100644
--- a/include/asm-arm/arch-ns9xxx/clock.h
+++ b/include/asm-arm/arch-ns9xxx/clock.h
@@ -19,7 +19,7 @@
19static inline u32 ns9xxx_systemclock(void) __attribute__((const)); 19static inline u32 ns9xxx_systemclock(void) __attribute__((const));
20static inline u32 ns9xxx_systemclock(void) 20static inline u32 ns9xxx_systemclock(void)
21{ 21{
22 u32 pll = SYS_PLL; 22 u32 pll = __raw_readl(SYS_PLL);
23 23
24 /* 24 /*
25 * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in 25 * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in
@@ -46,8 +46,8 @@ static inline u32 ns9xxx_systemclock(void)
46 * 46 *
47 * Fine. 47 * Fine.
48 */ 48 */
49 return CRYSTAL * (REGGET(pll, SYS_PLL, ND) + 1) 49 return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
50 >> REGGET(pll, SYS_PLL, FS); 50 >> REGGETIM(pll, SYS_PLL, FS);
51} 51}
52 52
53static inline u32 ns9xxx_cpuclock(void) __attribute__((const)); 53static inline u32 ns9xxx_cpuclock(void) __attribute__((const));
diff --git a/include/asm-arm/arch-ns9xxx/gpio.h b/include/asm-arm/arch-ns9xxx/gpio.h
new file mode 100644
index 000000000000..adbca08583c0
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/gpio.h
@@ -0,0 +1,47 @@
1/*
2 * include/asm-arm/arch-ns9xxx/gpio.h
3 *
4 * Copyright (C) 2007 by Digi International Inc.
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10*/
11#ifndef __ASM_ARCH_GPIO_H
12#define __ASM_ARCH_GPIO_H
13
14#include <asm/errno.h>
15
16int gpio_request(unsigned gpio, const char *label);
17
18void gpio_free(unsigned gpio);
19
20int ns9xxx_gpio_configure(unsigned gpio, int inv, int func);
21
22int gpio_direction_input(unsigned gpio);
23
24int gpio_direction_output(unsigned gpio, int value);
25
26int gpio_get_value(unsigned gpio);
27
28void gpio_set_value(unsigned gpio, int value);
29
30/*
31 * ns9xxx can use gpio pins to trigger an irq, but it's not generic
32 * enough to be supported by the gpio_to_irq/irq_to_gpio interface
33 */
34static inline int gpio_to_irq(unsigned gpio)
35{
36 return -EINVAL;
37}
38
39static inline int irq_to_gpio(unsigned irq)
40{
41 return -EINVAL;
42}
43
44/* get the cansleep() stubs */
45#include <asm-generic/gpio.h>
46
47#endif /* ifndef __ASM_ARCH_GPIO_H */
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h
index 25600554c4fe..0b7b34603f1c 100644
--- a/include/asm-arm/arch-ns9xxx/hardware.h
+++ b/include/asm-arm/arch-ns9xxx/hardware.h
@@ -27,42 +27,53 @@
27#define io_v2p(x) ((((x) & 0x0f000000) << 4) \ 27#define io_v2p(x) ((((x) & 0x0f000000) << 4) \
28 + ((x) & 0x00ffffff)) 28 + ((x) & 0x00ffffff))
29 29
30#define __REGSHIFT(mask) ((mask) & (-(mask)))
31
30#define __REGBIT(bit) ((u32)1 << (bit)) 32#define __REGBIT(bit) ((u32)1 << (bit))
31#define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit)) 33#define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit))
32#define __REGVAL(mask, value) (((value) * ((mask) & (-(mask))) & (mask))) 34#define __REGVAL(mask, value) (((value) * __REGSHIFT(mask)) & (mask))
33 35
34#ifndef __ASSEMBLY__ 36#ifndef __ASSEMBLY__
35 37
36# define __REG(x) (*((volatile u32 *)io_p2v((x)))) 38# define __REG(x) ((void __iomem __force *)io_p2v((x)))
37# define __REG2(x, y) (*((volatile u32 *)io_p2v((x)) + (y))) 39# define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y)))
38 40
39# define __REGB(x) (*((volatile u8 *)io_p2v((x)))) 41# define __REGSET(var, field, value) \
40# define __REGB2(x) (*((volatile u8 *)io_p2v((x)) + (y))) 42 ((var) = (((var) & ~((field) & ~(value))) | (value)))
41 43
42# define REGSET(var, reg, field, value) \ 44# define REGSET(var, reg, field, value) \
43 ((var) = (((var) \ 45 __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value)
44 & ~(reg ## _ ## field & \ 46
45 ~ reg ## _ ## field ## _ ## value)) \ 47# define REGSET_IDX(var, reg, field, idx, value) \
46 | (reg ## _ ## field ## _ ## value))) 48 __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx)))
47 49
48# define REGSETIM(var, reg, field, value) \ 50# define REGSETIM(var, reg, field, value) \
49 ((var) = (((var) \ 51 __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value)))
50 & ~(reg ## _ ## field & \ 52
51 ~(__REGVAL(reg ## _ ## field, value)))) \ 53# define REGSETIM_IDX(var, reg, field, idx, value) \
52 | (__REGVAL(reg ## _ ## field, value)))) 54 __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value)))
55
56# define __REGGET(var, field) \
57 (((var) & (field)))
53 58
54# define REGGET(var, reg, field) \ 59# define REGGET(var, reg, field) \
55 ((var & (reg ## _ ## field)) / \ 60 __REGGET(var, reg ## _ ## field)
56 ((reg ## _ ## field) & (-(reg ## _ ## field)))) 61
62# define REGGET_IDX(var, reg, field, idx) \
63 __REGGET(var, reg ## _ ## field((idx)))
64
65# define REGGETIM(var, reg, field) \
66 __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
67
68# define REGGETIM_IDX(var, reg, field, idx) \
69 __REGGET(var, reg ## _ ## field((idx))) / \
70 __REGSHIFT(reg ## _ ## field((idx)))
57 71
58#else 72#else
59 73
60# define __REG(x) io_p2v(x) 74# define __REG(x) io_p2v(x)
61# define __REG2(x, y) io_p2v((x) + (y)) 75# define __REG2(x, y) io_p2v((x) + (y))
62 76
63# define __REGB(x) __REG((x))
64# define __REGB2(x, y) __REG2((x), (y))
65
66#endif 77#endif
67 78
68#endif /* ifndef __ASM_ARCH_HARDWARE_H */ 79#endif /* ifndef __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h b/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h
index c3dc532dd20c..afa3a9db3e1d 100644
--- a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h
+++ b/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h
@@ -18,7 +18,7 @@
18#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10) 18#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10)
19#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18) 19#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18)
20 20
21#define FPGA_IER __REGB(NS9XXX_CSxSTAT_PHYS(0) + 0x50) 21#define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
22#define FPGA_ISR __REGB(NS9XXX_CSxSTAT_PHYS(0) + 0x60) 22#define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
23 23
24#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */ 24#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */
diff --git a/include/asm-arm/arch-ns9xxx/system.h b/include/asm-arm/arch-ns9xxx/system.h
index e3cd4d31b3f3..c1082bd8977c 100644
--- a/include/asm-arm/arch-ns9xxx/system.h
+++ b/include/asm-arm/arch-ns9xxx/system.h
@@ -24,9 +24,9 @@ static inline void arch_reset(char mode)
24{ 24{
25 u32 reg; 25 u32 reg;
26 26
27 reg = SYS_PLL >> 16; 27 reg = __raw_readl(SYS_PLL) >> 16;
28 REGSET(reg, SYS_PLL, SWC, YES); 28 REGSET(reg, SYS_PLL, SWC, YES);
29 SYS_PLL = reg; 29 __raw_writel(reg, SYS_PLL);
30 30
31 BUG(); 31 BUG();
32} 32}
diff --git a/include/asm-arm/arch-omap/blizzard.h b/include/asm-arm/arch-omap/blizzard.h
new file mode 100644
index 000000000000..8d160f171372
--- /dev/null
+++ b/include/asm-arm/arch-omap/blizzard.h
@@ -0,0 +1,12 @@
1#ifndef _BLIZZARD_H
2#define _BLIZZARD_H
3
4struct blizzard_platform_data {
5 void (*power_up)(struct device *dev);
6 void (*power_down)(struct device *dev);
7 unsigned long (*get_clock_rate)(struct device *dev);
8
9 unsigned te_connected : 1;
10};
11
12#endif
diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h
new file mode 100644
index 000000000000..e9c65ce3cb12
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-2430sdp.h
@@ -0,0 +1,44 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-2430sdp.h
3 *
4 * Hardware definitions for TI OMAP2430 SDP board.
5 *
6 * Based on board-h4.h by Dirk Behme <dirk.behme@de.bosch.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_OMAP_2430SDP_H
30#define __ASM_ARCH_OMAP_2430SDP_H
31
32/* Placeholder for 2430SDP specific defines */
33#define OMAP24XX_ETHR_START 0x08000300
34#define OMAP24XX_ETHR_GPIO_IRQ 149
35#define SDP2430_CS0_BASE 0x04000000
36
37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ
38
39/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
40#define IH_TWL4030_BASE IH_BOARD_BASE
41#define IH_TWL4030_END (IH_TWL4030_BASE+8)
42#define NR_IRQS (IH_TWL4030_END)
43
44#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/include/asm-arm/arch-omap/board-palmte.h b/include/asm-arm/arch-omap/board-palmte.h
new file mode 100644
index 000000000000..cd22035a7160
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-palmte.h
@@ -0,0 +1,34 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-palmte.h
3 *
4 * Hardware definitions for the Palm Tungsten E device.
5 *
6 * Maintainters : http://palmtelinux.sf.net
7 * palmtelinux-developpers@lists.sf.net
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __OMAP_BOARD_PALMTE_H
15#define __OMAP_BOARD_PALMTE_H
16
17#include <asm/arch/gpio.h>
18
19#define PALMTE_USBDETECT_GPIO 0
20#define PALMTE_USB_OR_DC_GPIO 1
21#define PALMTE_TSC_GPIO 4
22#define PALMTE_PINTDAV_GPIO 6
23#define PALMTE_MMC_WP_GPIO 8
24#define PALMTE_MMC_POWER_GPIO 9
25#define PALMTE_HDQ_GPIO 11
26#define PALMTE_HEADPHONES_GPIO 14
27#define PALMTE_SPEAKER_GPIO 15
28#define PALMTE_DC_GPIO OMAP_MPUIO(2)
29#define PALMTE_MMC_SWITCH_GPIO OMAP_MPUIO(4)
30#define PALMTE_MMC1_GPIO OMAP_MPUIO(6)
31#define PALMTE_MMC2_GPIO OMAP_MPUIO(7)
32#define PALMTE_MMC3_GPIO OMAP_MPUIO(11)
33
34#endif /* __OMAP_BOARD_PALMTE_H */
diff --git a/include/asm-arm/arch-omap/board-palmtt.h b/include/asm-arm/arch-omap/board-palmtt.h
new file mode 100644
index 000000000000..d9590b0ec90e
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-palmtt.h
@@ -0,0 +1,23 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-palmte.h
3 *
4 * Hardware definitions for the Palm Tungsten|T device.
5 *
6 * Maintainters : Marek Vasut <marek.vasut@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __OMAP_BOARD_PALMTT_H
14#define __OMAP_BOARD_PALMTT_H
15
16#define PALMTT_USBDETECT_GPIO 0
17#define PALMTT_CABLE_GPIO 1
18#define PALMTT_LED_GPIO 3
19#define PALMTT_PENIRQ_GPIO 6
20#define PALMTT_MMC_WP_GPIO 8
21#define PALMTT_HDQ_GPIO 11
22
23#endif /* __OMAP_BOARD_PALMTT_H */
diff --git a/include/asm-arm/arch-omap/board-palmz71.h b/include/asm-arm/arch-omap/board-palmz71.h
new file mode 100644
index 000000000000..1252a859787d
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-palmz71.h
@@ -0,0 +1,26 @@
1/*
2 * linux/include/asm-arm/arch-omap/board-palmz71.h
3 *
4 * Hardware definitions for the Palm Zire71 device.
5 *
6 * Maintainters : Marek Vasut <marek.vasut@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __OMAP_BOARD_PALMZ71_H
14#define __OMAP_BOARD_PALMZ71_H
15
16#define PALMZ71_USBDETECT_GPIO 0
17#define PALMZ71_PENIRQ_GPIO 6
18#define PALMZ71_MMC_WP_GPIO 8
19#define PALMZ71_HDQ_GPIO 11
20
21#define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1)
22#define PALMZ71_CABLE_GPIO OMAP_MPUIO(2)
23#define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3)
24#define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4)
25
26#endif /* __OMAP_BOARD_PALMZ71_H */
diff --git a/include/asm-arm/arch-omap/board-sx1.h b/include/asm-arm/arch-omap/board-sx1.h
new file mode 100644
index 000000000000..2bb8dd6e2d14
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-sx1.h
@@ -0,0 +1,46 @@
1/*
2 * Siemens SX1 board definitions
3 *
4 * Copyright: Vovan888 at gmail com
5 *
6 * This package is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 */
14
15#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
16#define __ASM_ARCH_SX1_I2C_CHIPS_H
17
18#define SOFIA_MAX_LIGHT_VAL 0x2B
19
20#define SOFIA_I2C_ADDR 0x32
21/* Sofia reg 3 bits masks */
22#define SOFIA_POWER1_REG 0x03
23
24#define SOFIA_USB_POWER 0x01
25#define SOFIA_MMC_POWER 0x04
26#define SOFIA_BLUETOOTH_POWER 0x08
27#define SOFIA_MMILIGHT_POWER 0x20
28
29#define SOFIA_POWER2_REG 0x04
30#define SOFIA_BACKLIGHT_REG 0x06
31#define SOFIA_KEYLIGHT_REG 0x07
32#define SOFIA_DIMMING_REG 0x09
33
34
35/* Function Prototypes for SX1 devices control on I2C bus */
36
37int sx1_setbacklight(u8 backlight);
38int sx1_getbacklight(u8 *backlight);
39int sx1_setkeylight(u8 keylight);
40int sx1_getkeylight(u8 *keylight);
41
42int sx1_setmmipower(u8 onoff);
43int sx1_setusbpower(u8 onoff);
44int sx1_setmmcpower(u8 onoff);
45
46#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
index 031672c56377..db44c5d1f1a0 100644
--- a/include/asm-arm/arch-omap/board.h
+++ b/include/asm-arm/arch-omap/board.h
@@ -179,4 +179,8 @@ extern const void *omap_get_var_config(u16 tag, size_t *len);
179extern struct omap_board_config_kernel *omap_board_config; 179extern struct omap_board_config_kernel *omap_board_config;
180extern int omap_board_config_size; 180extern int omap_board_config_size;
181 181
182
183/* for TI reference platforms sharing the same debug card */
184extern int debug_card_init(u32 addr, unsigned gpio);
185
182#endif 186#endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index f7774192a41e..f33b467fddb7 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -417,7 +417,6 @@ extern void omap_free_lcd_dma(void);
417extern void omap_setup_lcd_dma(void); 417extern void omap_setup_lcd_dma(void);
418extern void omap_enable_lcd_dma(void); 418extern void omap_enable_lcd_dma(void);
419extern void omap_stop_lcd_dma(void); 419extern void omap_stop_lcd_dma(void);
420extern int omap_lcd_dma_ext_running(void);
421extern void omap_set_lcd_dma_ext_controller(int external); 420extern void omap_set_lcd_dma_ext_controller(int external);
422extern void omap_set_lcd_dma_single_transfer(int single); 421extern void omap_set_lcd_dma_single_transfer(int single);
423extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, 422extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
diff --git a/include/asm-arm/arch-omap/eac.h b/include/asm-arm/arch-omap/eac.h
new file mode 100644
index 000000000000..6662cb02bafc
--- /dev/null
+++ b/include/asm-arm/arch-omap/eac.h
@@ -0,0 +1,101 @@
1/*
2 * linux/include/asm-arm/arch-omap2/eac.h
3 *
4 * Defines for Enhanced Audio Controller
5 *
6 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
7 *
8 * Copyright (C) 2006 Nokia Corporation
9 * Copyright (C) 2004 Texas Instruments, Inc.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 */
26
27#ifndef __ASM_ARM_ARCH_OMAP2_EAC_H
28#define __ASM_ARM_ARCH_OMAP2_EAC_H
29
30#include <asm/arch/io.h>
31#include <asm/arch/hardware.h>
32#include <asm/irq.h>
33
34#include <sound/driver.h>
35#include <sound/core.h>
36
37/* master codec clock source */
38#define EAC_MCLK_EXT_MASK 0x100
39enum eac_mclk_src {
40 EAC_MCLK_INT_11290000, /* internal 96 MHz / 8.5 = 11.29 Mhz */
41 EAC_MCLK_EXT_11289600 = EAC_MCLK_EXT_MASK,
42 EAC_MCLK_EXT_12288000,
43 EAC_MCLK_EXT_2x11289600,
44 EAC_MCLK_EXT_2x12288000,
45};
46
47/* codec port interface mode */
48enum eac_codec_mode {
49 EAC_CODEC_PCM,
50 EAC_CODEC_AC97,
51 EAC_CODEC_I2S_MASTER, /* codec port, I.e. EAC is the master */
52 EAC_CODEC_I2S_SLAVE,
53};
54
55/* configuration structure for I2S mode */
56struct eac_i2s_conf {
57 /* if enabled, then first data slot (left channel) is signaled as
58 * positive level of frame sync EAC.AC_FS */
59 unsigned polarity_changed_mode:1;
60 /* if enabled, then serial data starts one clock cycle after the
61 * of EAC.AC_FS for first audio slot */
62 unsigned sync_delay_enable:1;
63};
64
65/* configuration structure for EAC codec port */
66struct eac_codec {
67 enum eac_mclk_src mclk_src;
68
69 enum eac_codec_mode codec_mode;
70 union {
71 struct eac_i2s_conf i2s;
72 } codec_conf;
73
74 int default_rate; /* audio sampling rate */
75
76 int (* set_power)(void *private_data, int dac, int adc);
77 int (* register_controls)(void *private_data,
78 struct snd_card *card);
79 const char *short_name;
80
81 void *private_data;
82};
83
84/* structure for passing platform dependent data to the EAC driver */
85struct eac_platform_data {
86 int (* init)(struct device *eac_dev);
87 void (* cleanup)(struct device *eac_dev);
88 /* these callbacks are used to configure & control external MCLK
89 * source. NULL if not used */
90 int (* enable_ext_clocks)(struct device *eac_dev);
91 void (* disable_ext_clocks)(struct device *eac_dev);
92};
93
94extern void omap_init_eac(struct eac_platform_data *pdata);
95
96extern int eac_register_codec(struct device *eac_dev, struct eac_codec *codec);
97extern void eac_unregister_codec(struct device *eac_dev);
98
99extern int eac_set_mode(struct device *eac_dev, int play, int rec);
100
101#endif /* __ASM_ARM_ARCH_OMAP2_EAC_H */
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h
index 995cc83482eb..6a8e07ffc2d0 100644
--- a/include/asm-arm/arch-omap/gpmc.h
+++ b/include/asm-arm/arch-omap/gpmc.h
@@ -23,9 +23,10 @@
23#define GPMC_CS_NAND_DATA 0x24 23#define GPMC_CS_NAND_DATA 0x24
24 24
25#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 25#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
26#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 20) 26#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
27#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 27#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
28#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) 28#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
29#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
29#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) 30#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
30#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) 31#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
31#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) 32#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
@@ -80,6 +81,8 @@ struct gpmc_timings {
80}; 81};
81 82
82extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); 83extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
84extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
85extern unsigned long gpmc_get_fclk_period(void);
83 86
84extern void gpmc_cs_write_reg(int cs, int idx, u32 val); 87extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
85extern u32 gpmc_cs_read_reg(int cs, int idx); 88extern u32 gpmc_cs_read_reg(int cs, int idx);
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index e225f4f39b34..da572092e255 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -318,6 +318,10 @@
318#include "board-h4.h" 318#include "board-h4.h"
319#endif 319#endif
320 320
321#ifdef CONFIG_MACH_OMAP_2430SDP
322#include "board-2430sdp.h"
323#endif
324
321#ifdef CONFIG_MACH_OMAP_APOLLON 325#ifdef CONFIG_MACH_OMAP_APOLLON
322#include "board-apollon.h" 326#include "board-apollon.h"
323#endif 327#endif
@@ -330,6 +334,22 @@
330#include "board-voiceblue.h" 334#include "board-voiceblue.h"
331#endif 335#endif
332 336
337#ifdef CONFIG_MACH_OMAP_PALMTE
338#include "board-palmte.h"
339#endif
340
341#ifdef CONFIG_MACH_OMAP_PALMZ71
342#include "board-palmz71.h"
343#endif
344
345#ifdef CONFIG_MACH_OMAP_PALMTT
346#include "board-palmtt.h"
347#endif
348
349#ifdef CONFIG_MACH_SX1
350#include "board-sx1.h"
351#endif
352
333#endif /* !__ASSEMBLER__ */ 353#endif /* !__ASSEMBLER__ */
334 354
335#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ 355#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 4aca7e3d7566..289082d07f14 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -72,6 +72,16 @@
72#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */ 72#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */
73#define L4_24XX_VIRT 0xd8000000 73#define L4_24XX_VIRT 0xd8000000
74#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 74#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
75
76#ifdef CONFIG_ARCH_OMAP2430
77#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
78#define L4_WK_243X_VIRT 0xd9000000
79#define L4_WK_243X_SIZE SZ_1M
80#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
81#define OMAP243X_GPMC_VIRT 0xFE000000
82#define OMAP243X_GPMC_SIZE SZ_1M
83#endif
84
75#define IO_OFFSET 0x90000000 85#define IO_OFFSET 0x90000000
76#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 86#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
77#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 87#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h
index 82d276a6bd95..69ed7ee40179 100644
--- a/include/asm-arm/arch-omap/menelaus.h
+++ b/include/asm-arm/arch-omap/menelaus.h
@@ -7,6 +7,12 @@
7#ifndef __ASM_ARCH_MENELAUS_H 7#ifndef __ASM_ARCH_MENELAUS_H
8#define __ASM_ARCH_MENELAUS_H 8#define __ASM_ARCH_MENELAUS_H
9 9
10struct device;
11
12struct menelaus_platform_data {
13 int (* late_init)(struct device *dev);
14};
15
10extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask), 16extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
11 void *data); 17 void *data);
12extern void menelaus_unregister_mmc_callback(void); 18extern void menelaus_unregister_mmc_callback(void);
@@ -20,6 +26,19 @@ extern int menelaus_set_vaux(unsigned int mV);
20extern int menelaus_set_vdcdc(int dcdc, unsigned int mV); 26extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
21extern int menelaus_set_slot_sel(int enable); 27extern int menelaus_set_slot_sel(int enable);
22extern int menelaus_get_slot_pin_states(void); 28extern int menelaus_get_slot_pin_states(void);
29extern int menelaus_set_vcore_sw(unsigned int mV);
30extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
31
32#define EN_VPLL_SLEEP (1 << 7)
33#define EN_VMMC_SLEEP (1 << 6)
34#define EN_VAUX_SLEEP (1 << 5)
35#define EN_VIO_SLEEP (1 << 4)
36#define EN_VMEM_SLEEP (1 << 3)
37#define EN_DC3_SLEEP (1 << 2)
38#define EN_DC2_SLEEP (1 << 1)
39#define EN_VC_SLEEP (1 << 0)
40
41extern int menelaus_set_regulator_sleep(int enable, u32 val);
23 42
24#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS) 43#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
25#define omap_has_menelaus() 1 44#define omap_has_menelaus() 1
@@ -28,4 +47,3 @@ extern int menelaus_get_slot_pin_states(void);
28#endif 47#endif
29 48
30#endif 49#endif
31
diff --git a/include/asm-arm/arch-omap/mmc.h b/include/asm-arm/arch-omap/mmc.h
new file mode 100644
index 000000000000..b70e37b61242
--- /dev/null
+++ b/include/asm-arm/arch-omap/mmc.h
@@ -0,0 +1,66 @@
1/*
2 * MMC definitions for OMAP2
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_MMC_H
12#define __OMAP2_MMC_H
13
14#include <linux/types.h>
15#include <linux/device.h>
16#include <linux/mmc/host.h>
17
18#define OMAP_MMC_MAX_SLOTS 2
19
20struct omap_mmc_platform_data {
21 unsigned enabled:1;
22 /* number of slots on board */
23 unsigned nr_slots:2;
24 /* nomux means "standard" muxing is wrong on this board, and that
25 * board-specific code handled it before common init logic.
26 */
27 unsigned nomux:1;
28 /* 4 wire signaling is optional, and is only used for SD/SDIO and
29 * MMCv4 */
30 unsigned wire4:1;
31 /* set if your board has components or wiring that limits the
32 * maximum frequency on the MMC bus */
33 unsigned int max_freq;
34
35 /* switch the bus to a new slot */
36 int (* switch_slot)(struct device *dev, int slot);
37 /* initialize board-specific MMC functionality, can be NULL if
38 * not supported */
39 int (* init)(struct device *dev);
40 void (* cleanup)(struct device *dev);
41
42 struct omap_mmc_slot_data {
43 int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
44 int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
45 int (* get_ro)(struct device *dev, int slot);
46
47 /* return MMC cover switch state, can be NULL if not supported.
48 *
49 * possible return values:
50 * 0 - open
51 * 1 - closed
52 */
53 int (* get_cover_state)(struct device *dev, int slot);
54
55 const char *name;
56 u32 ocr_mask;
57 } slots[OMAP_MMC_MAX_SLOTS];
58};
59
60extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info);
61
62/* called from board-specific card detection service routine */
63extern void omap_mmc_notify_card_detect(struct device *dev, int slot, int detected);
64extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
65
66#endif
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index f1ec2edd4040..b8fff50e6a87 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -406,6 +406,29 @@ enum omap1xxx_index {
406 V10_1610_CF_IREQ, 406 V10_1610_CF_IREQ,
407 W10_1610_CF_RESET, 407 W10_1610_CF_RESET,
408 W11_1610_CF_CD1, 408 W11_1610_CF_CD1,
409
410 /* parallel camera */
411 J15_1610_CAM_LCLK,
412 J18_1610_CAM_D7,
413 J19_1610_CAM_D6,
414 J14_1610_CAM_D5,
415 K18_1610_CAM_D4,
416 K19_1610_CAM_D3,
417 K15_1610_CAM_D2,
418 K14_1610_CAM_D1,
419 L19_1610_CAM_D0,
420 L18_1610_CAM_VS,
421 L15_1610_CAM_HS,
422 M19_1610_CAM_RSTZ,
423 Y15_1610_CAM_OUTCLK,
424
425 /* serial camera */
426 H19_1610_CAM_EXCLK,
427 Y12_1610_CCP_CLKP,
428 W13_1610_CCP_CLKM,
429 W14_1610_CCP_DATAP,
430 Y14_1610_CCP_DATAM,
431
409}; 432};
410 433
411enum omap24xx_index { 434enum omap24xx_index {
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index 708b2fac77f2..14c0f9496579 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -8,6 +8,7 @@
8 */ 8 */
9 9
10#define L4_24XX_BASE 0x48000000 10#define L4_24XX_BASE 0x48000000
11#define L4_WK_243X_BASE 0x49000000
11#define L3_24XX_BASE 0x68000000 12#define L3_24XX_BASE 0x68000000
12 13
13/* interrupt controller */ 14/* interrupt controller */
@@ -16,9 +17,20 @@
16#define OMAP24XX_IVA_INTC_BASE 0x40000000 17#define OMAP24XX_IVA_INTC_BASE 0x40000000
17#define IRQ_SIR_IRQ 0x0040 18#define IRQ_SIR_IRQ 0x0040
18 19
20#ifdef CONFIG_ARCH_OMAP2420
19#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 21#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
20#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000) 22#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000)
21#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000) 23#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000)
24#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
25#endif
26
27#ifdef CONFIG_ARCH_OMAP2430
28#define OMAP24XX_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
29#define OMAP24XX_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
30#define OMAP24XX_SDRC_BASE (0x6D000000)
31#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
32#define OMAP243X_GPMC_BASE 0x6E000000
33#endif
22 34
23/* DSP SS */ 35/* DSP SS */
24#define OMAP24XX_DSP_BASE 0x58000000 36#define OMAP24XX_DSP_BASE 0x58000000
diff --git a/include/asm-arm/arch-omap/onenand.h b/include/asm-arm/arch-omap/onenand.h
new file mode 100644
index 000000000000..6c959d0ce470
--- /dev/null
+++ b/include/asm-arm/arch-omap/onenand.h
@@ -0,0 +1,21 @@
1/*
2 * include/asm-arm/arch-omap/onenand.h
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Author: Juha Yrjola
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/mtd/partitions.h>
13
14struct omap_onenand_platform_data {
15 int cs;
16 int gpio_irq;
17 struct mtd_partition *parts;
18 int nr_parts;
19 int (*onenand_setup)(void __iomem *);
20 int dma_channel;
21};
diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h
new file mode 100644
index 000000000000..f8fac9e18009
--- /dev/null
+++ b/include/asm-arm/arch-pxa/cm-x270.h
@@ -0,0 +1,50 @@
1/*
2 * linux/include/asm/arch-pxa/cm-x270.h
3 *
4 * Copyright Compulab Ltd., 2003, 2007
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12
13/* CM-x270 device physical addresses */
14#define CMX270_CS1_PHYS (PXA_CS1_PHYS)
15#define MARATHON_PHYS (PXA_CS2_PHYS)
16#define CMX270_IDE104_PHYS (PXA_CS3_PHYS)
17#define CMX270_IT8152_PHYS (PXA_CS4_PHYS)
18
19/* Statically mapped regions */
20#define CMX270_VIRT_BASE (0xe8000000)
21#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
22#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M)
23
24/* GPIO related definitions */
25#define GPIO_IT8152_IRQ (22)
26
27#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ)
28#define PME_IRQ IRQ_GPIO(0)
29#define CMX270_IDE_IRQ IRQ_GPIO(100)
30#define CMX270_GPIRQ1 IRQ_GPIO(101)
31#define CMX270_TOUCHIRQ IRQ_GPIO(96)
32#define CMX270_ETHIRQ IRQ_GPIO(10)
33#define CMX270_GFXIRQ IRQ_GPIO(95)
34#define CMX270_NANDIRQ IRQ_GPIO(89)
35#define CMX270_MMC_IRQ IRQ_GPIO(83)
36
37/* PCMCIA related definitions */
38#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x)))
39#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x)))
40
41#define PCMCIA_S0_CD_VALID IRQ_GPIO(84)
42#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES
43
44#define PCMCIA_S1_CD_VALID IRQ_GPIO(83)
45#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES
46
47#define PCMCIA_S0_RDYINT IRQ_GPIO(82)
48#define PCMCIA_S1_RDYINT IRQ_GPIO(81)
49
50#define PCMCIA_RESET_GPIO 53
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
index 3280ee2ddfa5..dbe110ee2666 100644
--- a/include/asm-arm/arch-pxa/dma.h
+++ b/include/asm-arm/arch-pxa/dma.h
@@ -30,6 +30,10 @@ typedef enum {
30 DMA_PRIO_LOW = 2 30 DMA_PRIO_LOW = 2
31} pxa_dma_prio; 31} pxa_dma_prio;
32 32
33#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
34#define HAVE_ARCH_PCI_SET_DMA_MASK 1
35#endif
36
33/* 37/*
34 * DMA registration 38 * DMA registration
35 */ 39 */
diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h
index 9e99241f3edf..9dbc2dc794f7 100644
--- a/include/asm-arm/arch-pxa/gpio.h
+++ b/include/asm-arm/arch-pxa/gpio.h
@@ -38,16 +38,8 @@ static inline void gpio_free(unsigned gpio)
38 return; 38 return;
39} 39}
40 40
41static inline int gpio_direction_input(unsigned gpio) 41extern int gpio_direction_input(unsigned gpio);
42{ 42extern int gpio_direction_output(unsigned gpio, int value);
43 return pxa_gpio_mode(gpio | GPIO_IN);
44}
45
46static inline int gpio_direction_output(unsigned gpio, int value)
47{
48 return pxa_gpio_mode(gpio | GPIO_OUT |
49 (value ? GPIO_DFLT_HIGH : GPIO_DFLT_LOW));
50}
51 43
52static inline int __gpio_get_value(unsigned gpio) 44static inline int __gpio_get_value(unsigned gpio)
53{ 45{
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index 386121746417..ab2d963e742a 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -62,6 +62,7 @@
62 62
63#ifndef __ASSEMBLY__ 63#ifndef __ASSEMBLY__
64 64
65#ifdef CONFIG_PXA25x
65#define __cpu_is_pxa21x(id) \ 66#define __cpu_is_pxa21x(id) \
66 ({ \ 67 ({ \
67 unsigned int _id = (id) >> 4 & 0xf3f; \ 68 unsigned int _id = (id) >> 4 & 0xf3f; \
@@ -73,12 +74,50 @@
73 unsigned int _id = (id) >> 4 & 0xfff; \ 74 unsigned int _id = (id) >> 4 & 0xfff; \
74 _id == 0x2d0 || _id == 0x290; \ 75 _id == 0x2d0 || _id == 0x290; \
75 }) 76 })
77#else
78#define __cpu_is_pxa21x(id) (0)
79#define __cpu_is_pxa25x(id) (0)
80#endif
76 81
82#ifdef CONFIG_PXA27x
77#define __cpu_is_pxa27x(id) \ 83#define __cpu_is_pxa27x(id) \
78 ({ \ 84 ({ \
79 unsigned int _id = (id) >> 4 & 0xfff; \ 85 unsigned int _id = (id) >> 4 & 0xfff; \
80 _id == 0x411; \ 86 _id == 0x411; \
81 }) 87 })
88#else
89#define __cpu_is_pxa27x(id) (0)
90#endif
91
92#ifdef CONFIG_CPU_PXA300
93#define __cpu_is_pxa300(id) \
94 ({ \
95 unsigned int _id = (id) >> 4 & 0xfff; \
96 _id == 0x688; \
97 })
98#else
99#define __cpu_is_pxa300(id) (0)
100#endif
101
102#ifdef CONFIG_CPU_PXA310
103#define __cpu_is_pxa310(id) \
104 ({ \
105 unsigned int _id = (id) >> 4 & 0xfff; \
106 _id == 0x689; \
107 })
108#else
109#define __cpu_is_pxa310(id) (0)
110#endif
111
112#ifdef CONFIG_CPU_PXA320
113#define __cpu_is_pxa320(id) \
114 ({ \
115 unsigned int _id = (id) >> 4 & 0xfff; \
116 _id == 0x603 || _id == 0x682; \
117 })
118#else
119#define __cpu_is_pxa320(id) (0)
120#endif
82 121
83#define cpu_is_pxa21x() \ 122#define cpu_is_pxa21x() \
84 ({ \ 123 ({ \
@@ -98,6 +137,53 @@
98 __cpu_is_pxa27x(id); \ 137 __cpu_is_pxa27x(id); \
99 }) 138 })
100 139
140#define cpu_is_pxa300() \
141 ({ \
142 unsigned int id = read_cpuid(CPUID_ID); \
143 __cpu_is_pxa300(id); \
144 })
145
146#define cpu_is_pxa310() \
147 ({ \
148 unsigned int id = read_cpuid(CPUID_ID); \
149 __cpu_is_pxa310(id); \
150 })
151
152#define cpu_is_pxa320() \
153 ({ \
154 unsigned int id = read_cpuid(CPUID_ID); \
155 __cpu_is_pxa320(id); \
156 })
157
158/*
159 * CPUID Core Generation Bit
160 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
161 * == 0x3 for pxa300/pxa310/pxa320
162 */
163#define __cpu_is_pxa2xx(id) \
164 ({ \
165 unsigned int _id = (id) >> 13 & 0x7; \
166 _id <= 0x2; \
167 })
168
169#define __cpu_is_pxa3xx(id) \
170 ({ \
171 unsigned int _id = (id) >> 13 & 0x7; \
172 _id == 0x3; \
173 })
174
175#define cpu_is_pxa2xx() \
176 ({ \
177 unsigned int id = read_cpuid(CPUID_ID); \
178 __cpu_is_pxa2xx(id); \
179 })
180
181#define cpu_is_pxa3xx() \
182 ({ \
183 unsigned int id = read_cpuid(CPUID_ID); \
184 __cpu_is_pxa3xx(id); \
185 })
186
101/* 187/*
102 * Handy routine to set GPIO alternate functions 188 * Handy routine to set GPIO alternate functions
103 */ 189 */
@@ -116,14 +202,23 @@ extern void pxa_gpio_set_value(unsigned gpio, int value);
116/* 202/*
117 * Routine to enable or disable CKEN 203 * Routine to enable or disable CKEN
118 */ 204 */
119extern void pxa_set_cken(int clock, int enable); 205static inline void __deprecated pxa_set_cken(int clock, int enable)
206{
207 extern void __pxa_set_cken(int clock, int enable);
208 __pxa_set_cken(clock, enable);
209}
120 210
121/* 211/*
122 * return current memory and LCD clock frequency in units of 10kHz 212 * return current memory and LCD clock frequency in units of 10kHz
123 */ 213 */
124extern unsigned int get_memclk_frequency_10khz(void); 214extern unsigned int get_memclk_frequency_10khz(void);
125extern unsigned int get_lcdclk_frequency_10khz(void);
126 215
127#endif 216#endif
128 217
218#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
219#define PCIBIOS_MIN_IO 0
220#define PCIBIOS_MIN_MEM 0
221#define pcibios_assign_all_busses() 1
222#endif
223
129#endif /* _ASM_ARCH_HARDWARE_H */ 224#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index a07fe0f928cd..6238dbf7a236 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -66,12 +66,6 @@
66#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) 66#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE)
67#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) 67#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
68 68
69#if defined(CONFIG_PXA25x)
70#define PXA_LAST_GPIO 84
71#elif defined(CONFIG_PXA27x)
72#define PXA_LAST_GPIO 127
73#endif
74
75/* 69/*
76 * The next 16 interrupts are for board specific purposes. Since 70 * The next 16 interrupts are for board specific purposes. Since
77 * the kernel can only run on one machine at a time, we can re-use 71 * the kernel can only run on one machine at a time, we can re-use
@@ -216,3 +210,24 @@
216#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) 210#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1)
217#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) 211#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
218#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) 212#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
213
214/* ITE8152 irqs */
215/* add IT8152 IRQs beyond BOARD_END */
216#ifdef CONFIG_PCI_HOST_ITE8152
217#define IT8152_IRQ(x) (IRQ_GPIO(IRQ_BOARD_END) + 1 + (x))
218
219/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
220#define IT8152_LD_IRQ_COUNT 9
221#define IT8152_LP_IRQ_COUNT 16
222#define IT8152_PD_IRQ_COUNT 15
223
224/* Priorities: */
225#define IT8152_PD_IRQ(i) IT8152_IRQ(i)
226#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT)
227#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT)
228
229#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1)
230
231#undef NR_IRQS
232#define NR_IRQS (IT8152_LAST_IRQ+1)
233#endif
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index e17f9881faf0..bee81d66c184 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -39,4 +39,14 @@
39 */ 39 */
40#define NODE_MEM_SIZE_BITS 26 40#define NODE_MEM_SIZE_BITS 26
41 41
42#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
43void cmx270_pci_adjust_zones(int node, unsigned long *size,
44 unsigned long *holes);
45
46#define arch_adjust_zones(node, size, holes) \
47 cmx270_pci_adjust_zones(node, size, holes)
48
49#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
50#endif
51
42#endif 52#endif
diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h
new file mode 100644
index 000000000000..7513c7a3402d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa300.h
@@ -0,0 +1,574 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp-pxa300.h
3 *
4 * PXA300/PXA310 specific MFP configuration definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 * 2007-08-21: eric miao <eric.y.miao@gmail.com>
8 * initial version
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_MFP_PXA300_H
16#define __ASM_ARCH_MFP_PXA300_H
17
18#include <asm/arch/mfp.h>
19
20/* GPIO */
21#define GPIO46_GPIO MFP_CFG(GPIO46, AF1)
22#define GPIO49_GPIO MFP_CFG(GPIO49, AF3)
23#define GPIO50_GPIO MFP_CFG(GPIO50, AF2)
24#define GPIO51_GPIO MFP_CFG(GPIO51, AF3)
25#define GPIO52_GPIO MFP_CFG(GPIO52, AF3)
26#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
27#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
28#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
29#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
30#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
31#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
32
33#ifdef CONFIG_CPU_PXA310
34#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0)
35#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0)
36#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0)
37#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0)
38#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0)
39#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0)
40#endif
41
42/* Chip Select */
43#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1)
44
45/* AC97 */
46#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1)
47#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1)
48#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1)
49#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1)
50#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1)
51#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3)
52#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2)
53#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3)
54#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2)
55#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1)
56#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1)
57
58/* I2C */
59#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH)
60#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH)
61
62/* QCI */
63#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X)
64#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X)
65#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X)
66#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X)
67#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X)
68#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X)
69#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X)
70#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X)
71#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X)
72#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X)
73#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X)
74#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X)
75#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X)
76#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X)
77
78/* KEYPAD */
79#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT)
80#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT)
81#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT)
82#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT)
83#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT)
84#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT)
85#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT)
86#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT)
87#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT)
88#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT)
89#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT)
90#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT)
91#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT)
92#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT)
93#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT)
94#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT)
95#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT)
96#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT)
97#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT)
98#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT)
99#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT)
100#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT)
101#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT)
102#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT)
103#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT)
104#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT)
105#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT)
106#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT)
107#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT)
108#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
109#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT)
110#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
111#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
112#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
113#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT)
114
115#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT)
116#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT)
117#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT)
118#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT)
119#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT)
120#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT)
121#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT)
122#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT)
123#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT)
124#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT)
125#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT)
126#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT)
127#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT)
128#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT)
129#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT)
130#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT)
131#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT)
132#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT)
133#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT)
134
135#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
136#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH)
137#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH)
138#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
139#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH)
140#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH)
141#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH)
142#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH)
143#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH)
144#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
145#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
146#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH)
147#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH)
148#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH)
149#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH)
150#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
151#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
152#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
153#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
154#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
155#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH)
156#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
157#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH)
158#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH)
159
160/* LCD */
161#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X)
162#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X)
163#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X)
164#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X)
165#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X)
166#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X)
167#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X)
168#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X)
169#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X)
170#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X)
171#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X)
172#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X)
173#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X)
174#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X)
175#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X)
176#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X)
177#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X)
178#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X)
179#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X)
180#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X)
181#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X)
182#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS01X)
183#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X)
184#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X)
185
186#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X)
187#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X)
188#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X)
189
190/* Mini-LCD */
191#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X)
192#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X)
193#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X)
194#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X)
195#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X)
196#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X)
197#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X)
198#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X)
199#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X)
200#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X)
201#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X)
202#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X)
203#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X)
204#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X)
205#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X)
206#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X)
207#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X)
208#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X)
209#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X)
210#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X)
211
212/* MMC1 */
213#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH)
214#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH)
215#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH)
216#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH)
217#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH)
218#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH)
219#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH)
220#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH)
221
222/* MMC2 */
223#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH)
224#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH)
225#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH)
226#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH)
227#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH)
228#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH)
229#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
230#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
231#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
232#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
233#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH)
234#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH)
235
236/* SSP1 */
237#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1)
238#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1)
239#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6)
240#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2)
241#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5)
242#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5)
243#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1)
244#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1)
245#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7)
246#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2)
247#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2)
248#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7)
249#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5)
250#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4)
251#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5)
252#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6)
253#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1)
254#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6)
255#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6)
256#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1)
257
258/* SSP2 */
259#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2)
260#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2)
261#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2)
262#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2)
263#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2)
264#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6)
265#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6)
266#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2)
267#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2)
268#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2)
269#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7)
270#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5)
271#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4)
272#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2)
273#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5)
274#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5)
275#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2)
276#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7)
277#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6)
278#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4)
279#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2)
280#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2)
281#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4)
282#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7)
283
284/* SSP3 */
285#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW)
286#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT)
287#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW)
288#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT)
289#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
290#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT)
291#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW)
292#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT)
293#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW)
294#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT)
295#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW)
296#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
297
298/* SSP4 */
299#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
300#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
301#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH)
302#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH)
303#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH)
304#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH)
305
306/* UART1 */
307#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT)
308#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT)
309#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT)
310#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT)
311#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT)
312#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT)
313
314#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT)
315#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT)
316#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT)
317#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT)
318#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT)
319#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT)
320
321#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT)
322#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT)
323#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT)
324#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT)
325#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT)
326#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT)
327
328#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT)
329#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT)
330#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT)
331#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT)
332#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT)
333#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT)
334
335#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT)
336#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT)
337#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT)
338
339#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT)
340#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT)
341#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT)
342
343#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT)
344#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT)
345#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT)
346#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT)
347#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT)
348#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT)
349#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT)
350#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT)
351
352#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT)
353#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT)
354#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT)
355#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT)
356#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT)
357#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT)
358#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT)
359
360/* UART2 */
361#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT)
362#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT)
363#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT)
364#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT)
365
366#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT)
367#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT)
368#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT)
369#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT)
370
371#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT)
372#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT)
373#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT)
374#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT)
375
376#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT)
377#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT)
378#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT)
379#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT)
380
381/* UART3 */
382#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT)
383#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT)
384#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT)
385#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT)
386
387#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT)
388#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT)
389#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT)
390#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT)
391
392#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT)
393#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT)
394#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT)
395#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT)
396#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT)
397#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT)
398
399#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT)
400#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT)
401#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT)
402#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT)
403#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT)
404#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT)
405
406/* USB Host */
407#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1)
408#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1)
409
410/* USB P3 */
411#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2)
412#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2)
413#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2)
414#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2)
415#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2)
416#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2)
417
418/* PWM */
419#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1)
420#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1)
421#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1)
422#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1)
423
424/* CIR */
425#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5)
426#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3)
427
428#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5)
429#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2)
430
431#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1)
432#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7)
433#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6)
434#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6)
435#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6)
436#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6)
437#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2)
438#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3)
439#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7)
440#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6)
441
442#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1)
443
444#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1)
445#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1)
446#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1)
447#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1)
448
449#define GPIO9_SCIO MFP_CFG(GPIO9, AF1)
450#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4)
451#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1)
452
453/*
454 * PXA300 specific MFP configurations
455 */
456#ifdef CONFIG_CPU_PXA300
457#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2)
458#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3)
459#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4)
460#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4)
461#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5)
462#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2)
463#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2)
464#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2)
465#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2)
466#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2)
467#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2)
468#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2)
469
470/* U2D UTMI */
471#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1)
472#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3)
473#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1)
474#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5)
475#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3)
476#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2)
477#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5)
478#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3)
479#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2)
480#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1)
481#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5)
482#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1)
483#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3)
484#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3)
485#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3)
486#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4)
487#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3)
488#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3)
489#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3)
490#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4)
491#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2)
492#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7)
493#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4)
494#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2)
495#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3)
496#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5)
497#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1)
498#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2)
499#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3)
500#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3)
501#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2)
502#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3)
503#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5)
504#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3)
505#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5)
506#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3)
507#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4)
508#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3)
509#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7)
510#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5)
511#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3)
512#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5)
513#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3)
514#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3)
515#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3)
516#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3)
517#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3)
518#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3)
519#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3)
520#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3)
521#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3)
522#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3)
523#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3)
524#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3)
525#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3)
526#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3)
527#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3)
528#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3)
529#endif /* CONFIG_CPU_PXA300 */
530
531/*
532 * PXA310 specific MFP configurations
533 */
534#ifdef CONFIG_CPU_PXA310
535/* USB P2 */
536#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1)
537#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1)
538#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1)
539#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1)
540#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1)
541#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1)
542
543/* MMC1 */
544#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3)
545#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3)
546
547/* MMC3 */
548#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2)
549#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2)
550#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1)
551#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1)
552#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1)
553#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1)
554#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1)
555#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1)
556
557/* ULPI */
558#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1)
559#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3)
560#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3)
561#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3)
562#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3)
563#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3)
564#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3)
565#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3)
566#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3)
567#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1)
568
569#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X)
570#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X)
571#define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X)
572#endif /* CONFIG_CPU_PXA310 */
573
574#endif /* __ASM_ARCH_MFP_PXA300_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h
new file mode 100644
index 000000000000..ae8ba34194cf
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa320.h
@@ -0,0 +1,446 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp-pxa320.h
3 *
4 * PXA320 specific MFP configuration definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 * 2007-08-21: eric miao <eric.y.miao@gmail.com>
8 * initial version
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_MFP_PXA320_H
16#define __ASM_ARCH_MFP_PXA320_H
17
18#include <asm/arch/mfp.h>
19
20/* GPIO */
21#define GPIO46_GPIO MFP_CFG(GPIO6, AF0)
22#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
23#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
24#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
25#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
26
27#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0)
28#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0)
29#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0)
30#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0)
31#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0)
32#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0)
33#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0)
34#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0)
35#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0)
36#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0)
37#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0)
38
39/* Chip Select */
40#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1)
41
42/* AC97 */
43#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1)
44#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1)
45#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1)
46#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1)
47#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1)
48#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2)
49#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2)
50#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3)
51#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3)
52#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1)
53#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1)
54
55/* I2C */
56#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH)
57#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH)
58
59/* QCI */
60#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X)
61#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X)
62#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X)
63#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X)
64#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X)
65#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X)
66#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X)
67#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X)
68#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X)
69#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X)
70#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X)
71#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X)
72#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X)
73#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X)
74
75#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5)
76
77#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3)
78#define GPIO0_DRQ MFP_CFG(GPIO0, AF2)
79#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5)
80#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6)
81#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1)
82#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4)
83#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1)
84#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1)
85
86#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT)
87#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT)
88#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT)
89#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT)
90
91#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT)
92#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT)
93#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT)
94#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT)
95#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT)
96#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT)
97#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT)
98#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT)
99
100#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT)
101#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT)
102#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT)
103#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT)
104#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT)
105#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT)
106#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT)
107#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT)
108
109#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT)
110#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT)
111
112#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
113#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
114#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT)
115#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT)
116#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT)
117#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT)
118#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT)
119#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
120
121#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT)
122#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT)
123#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT)
124#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT)
125#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT)
126#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT)
127#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT)
128#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT)
129
130#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH)
131#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH)
132#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
133#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
134#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
135#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH)
136
137#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
138#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
139#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
140#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
141#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
142#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH)
143#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH)
144#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
145
146/* LCD */
147#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X)
148#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X)
149#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X)
150#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X)
151#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X)
152#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X)
153#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X)
154#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X)
155#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X)
156#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X)
157#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X)
158#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X)
159#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X)
160#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X)
161#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X)
162#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X)
163#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X)
164#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X)
165#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X)
166#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X)
167#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X)
168#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X)
169#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X)
170#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X)
171#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X)
172#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X)
173
174#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X)
175#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X)
176#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X)
177#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X)
178#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X)
179#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X)
180#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X)
181#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X)
182#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X)
183#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X)
184#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X)
185#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X)
186#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X)
187#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X)
188#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X)
189#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X)
190#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X)
191#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X)
192#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X)
193#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X)
194#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X)
195#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X)
196#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X)
197#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X)
198
199/* MMC1 */
200#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH)
201#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH)
202#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH)
203#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH)
204#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH)
205#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH)
206#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH)
207#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH)
208#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH)
209#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH)
210#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH)
211#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH)
212#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH)
213
214#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH)
215#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH)
216#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH)
217#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH)
218#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
219#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
220
221#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH)
222#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH)
223#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH)
224#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH)
225#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH)
226#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH)
227#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH)
228#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH)
229#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH)
230#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
231#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH)
232#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
233
234/* 1-Wire */
235#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT)
236#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
237
238/* SSP1 */
239#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1)
240#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1)
241#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1)
242#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1)
243#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6)
244#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1)
245#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1)
246#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6)
247
248/* SSP2 */
249#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2)
250#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2)
251#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2)
252#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2)
253#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2)
254#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5)
255#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2)
256#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2)
257#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5)
258
259#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
260#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
261#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
262#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
263#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
264#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
265#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
266#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW)
267#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT)
268#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW)
269#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT)
270#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW)
271
272#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH)
273#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH)
274#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH)
275#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH)
276#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
277#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
278#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH)
279
280/* UART1 */
281#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT)
282#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT)
283#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT)
284#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT)
285#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT)
286#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT)
287#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT)
288#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT)
289#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT)
290#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT)
291#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT)
292#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT)
293#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT)
294#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT)
295#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT)
296#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT)
297#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT)
298#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT)
299#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT)
300#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT)
301#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT)
302#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT)
303#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT)
304#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT)
305#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT)
306#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT)
307#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT)
308#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT)
309
310/* UART2 */
311#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT)
312#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT)
313#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT)
314#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT)
315#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT)
316#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT)
317#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT)
318#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT)
319
320/* UART3 */
321#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT)
322#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT)
323#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT)
324#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT)
325#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT)
326#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT)
327#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT)
328#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT)
329#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT)
330#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT)
331#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT)
332#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT)
333#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT)
334#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT)
335#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT)
336#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT)
337#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT)
338#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT)
339#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT)
340#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT)
341
342
343/* USB 2.0 UTMI */
344#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1)
345#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3)
346#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1)
347#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5)
348#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3)
349#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2)
350#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5)
351#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3)
352#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1)
353#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5)
354#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1)
355#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3)
356#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3)
357#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3)
358#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4)
359#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3)
360#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3)
361#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3)
362
363#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3)
364#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3)
365#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3)
366#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3)
367#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3)
368#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3)
369#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3)
370#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3)
371
372#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3)
373#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3)
374#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3)
375#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3)
376#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3)
377#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3)
378#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3)
379#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3)
380
381#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4)
382#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2)
383#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7)
384
385#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4)
386#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2)
387#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4)
388#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5)
389
390#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1)
391#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2)
392#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3)
393
394#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3)
395#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2)
396#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3)
397
398#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5)
399#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3)
400#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7)
401#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5)
402
403#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4)
404#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5)
405#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7)
406
407#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5)
408#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3)
409#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5)
410
411/* USB Host 1.1 */
412#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1)
413#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1)
414
415/* USB P2 */
416#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2)
417#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4)
418#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4)
419#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2)
420#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2)
421#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2)
422#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2)
423#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2)
424#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2)
425#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2)
426
427/* USB P3 */
428#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2)
429#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2)
430#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2)
431#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2)
432#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2)
433#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2)
434
435#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6)
436#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6)
437
438#define GPIO2_RDY MFP_CFG(GPIO2, AF1)
439#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3)
440
441#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1)
442#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1)
443#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1)
444#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1)
445
446#endif /* __ASM_ARCH_MFP_PXA320_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
new file mode 100644
index 000000000000..60291742ffdd
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp.h
@@ -0,0 +1,576 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp.h
3 *
4 * Multi-Function Pin Definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * 2007-8-21: eric miao <eric.y.miao@gmail.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_MFP_H
17#define __ASM_ARCH_MFP_H
18
19#define MFPR_BASE (0x40e10000)
20#define MFPR_SIZE (PAGE_SIZE)
21
22#define mfp_to_gpio(m) ((m) % 128)
23
24/* list of all the configurable MFP pins */
25enum {
26 MFP_PIN_INVALID = -1,
27
28 MFP_PIN_GPIO0 = 0,
29 MFP_PIN_GPIO1,
30 MFP_PIN_GPIO2,
31 MFP_PIN_GPIO3,
32 MFP_PIN_GPIO4,
33 MFP_PIN_GPIO5,
34 MFP_PIN_GPIO6,
35 MFP_PIN_GPIO7,
36 MFP_PIN_GPIO8,
37 MFP_PIN_GPIO9,
38 MFP_PIN_GPIO10,
39 MFP_PIN_GPIO11,
40 MFP_PIN_GPIO12,
41 MFP_PIN_GPIO13,
42 MFP_PIN_GPIO14,
43 MFP_PIN_GPIO15,
44 MFP_PIN_GPIO16,
45 MFP_PIN_GPIO17,
46 MFP_PIN_GPIO18,
47 MFP_PIN_GPIO19,
48 MFP_PIN_GPIO20,
49 MFP_PIN_GPIO21,
50 MFP_PIN_GPIO22,
51 MFP_PIN_GPIO23,
52 MFP_PIN_GPIO24,
53 MFP_PIN_GPIO25,
54 MFP_PIN_GPIO26,
55 MFP_PIN_GPIO27,
56 MFP_PIN_GPIO28,
57 MFP_PIN_GPIO29,
58 MFP_PIN_GPIO30,
59 MFP_PIN_GPIO31,
60 MFP_PIN_GPIO32,
61 MFP_PIN_GPIO33,
62 MFP_PIN_GPIO34,
63 MFP_PIN_GPIO35,
64 MFP_PIN_GPIO36,
65 MFP_PIN_GPIO37,
66 MFP_PIN_GPIO38,
67 MFP_PIN_GPIO39,
68 MFP_PIN_GPIO40,
69 MFP_PIN_GPIO41,
70 MFP_PIN_GPIO42,
71 MFP_PIN_GPIO43,
72 MFP_PIN_GPIO44,
73 MFP_PIN_GPIO45,
74 MFP_PIN_GPIO46,
75 MFP_PIN_GPIO47,
76 MFP_PIN_GPIO48,
77 MFP_PIN_GPIO49,
78 MFP_PIN_GPIO50,
79 MFP_PIN_GPIO51,
80 MFP_PIN_GPIO52,
81 MFP_PIN_GPIO53,
82 MFP_PIN_GPIO54,
83 MFP_PIN_GPIO55,
84 MFP_PIN_GPIO56,
85 MFP_PIN_GPIO57,
86 MFP_PIN_GPIO58,
87 MFP_PIN_GPIO59,
88 MFP_PIN_GPIO60,
89 MFP_PIN_GPIO61,
90 MFP_PIN_GPIO62,
91 MFP_PIN_GPIO63,
92 MFP_PIN_GPIO64,
93 MFP_PIN_GPIO65,
94 MFP_PIN_GPIO66,
95 MFP_PIN_GPIO67,
96 MFP_PIN_GPIO68,
97 MFP_PIN_GPIO69,
98 MFP_PIN_GPIO70,
99 MFP_PIN_GPIO71,
100 MFP_PIN_GPIO72,
101 MFP_PIN_GPIO73,
102 MFP_PIN_GPIO74,
103 MFP_PIN_GPIO75,
104 MFP_PIN_GPIO76,
105 MFP_PIN_GPIO77,
106 MFP_PIN_GPIO78,
107 MFP_PIN_GPIO79,
108 MFP_PIN_GPIO80,
109 MFP_PIN_GPIO81,
110 MFP_PIN_GPIO82,
111 MFP_PIN_GPIO83,
112 MFP_PIN_GPIO84,
113 MFP_PIN_GPIO85,
114 MFP_PIN_GPIO86,
115 MFP_PIN_GPIO87,
116 MFP_PIN_GPIO88,
117 MFP_PIN_GPIO89,
118 MFP_PIN_GPIO90,
119 MFP_PIN_GPIO91,
120 MFP_PIN_GPIO92,
121 MFP_PIN_GPIO93,
122 MFP_PIN_GPIO94,
123 MFP_PIN_GPIO95,
124 MFP_PIN_GPIO96,
125 MFP_PIN_GPIO97,
126 MFP_PIN_GPIO98,
127 MFP_PIN_GPIO99,
128 MFP_PIN_GPIO100,
129 MFP_PIN_GPIO101,
130 MFP_PIN_GPIO102,
131 MFP_PIN_GPIO103,
132 MFP_PIN_GPIO104,
133 MFP_PIN_GPIO105,
134 MFP_PIN_GPIO106,
135 MFP_PIN_GPIO107,
136 MFP_PIN_GPIO108,
137 MFP_PIN_GPIO109,
138 MFP_PIN_GPIO110,
139 MFP_PIN_GPIO111,
140 MFP_PIN_GPIO112,
141 MFP_PIN_GPIO113,
142 MFP_PIN_GPIO114,
143 MFP_PIN_GPIO115,
144 MFP_PIN_GPIO116,
145 MFP_PIN_GPIO117,
146 MFP_PIN_GPIO118,
147 MFP_PIN_GPIO119,
148 MFP_PIN_GPIO120,
149 MFP_PIN_GPIO121,
150 MFP_PIN_GPIO122,
151 MFP_PIN_GPIO123,
152 MFP_PIN_GPIO124,
153 MFP_PIN_GPIO125,
154 MFP_PIN_GPIO126,
155 MFP_PIN_GPIO127,
156 MFP_PIN_GPIO0_2,
157 MFP_PIN_GPIO1_2,
158 MFP_PIN_GPIO2_2,
159 MFP_PIN_GPIO3_2,
160 MFP_PIN_GPIO4_2,
161 MFP_PIN_GPIO5_2,
162 MFP_PIN_GPIO6_2,
163 MFP_PIN_GPIO7_2,
164 MFP_PIN_GPIO8_2,
165 MFP_PIN_GPIO9_2,
166 MFP_PIN_GPIO10_2,
167 MFP_PIN_GPIO11_2,
168 MFP_PIN_GPIO12_2,
169 MFP_PIN_GPIO13_2,
170 MFP_PIN_GPIO14_2,
171 MFP_PIN_GPIO15_2,
172 MFP_PIN_GPIO16_2,
173 MFP_PIN_GPIO17_2,
174
175 MFP_PIN_ULPI_STP,
176 MFP_PIN_ULPI_NXT,
177 MFP_PIN_ULPI_DIR,
178
179 MFP_PIN_nXCVREN,
180 MFP_PIN_DF_CLE_nOE,
181 MFP_PIN_DF_nADV1_ALE,
182 MFP_PIN_DF_SCLK_E,
183 MFP_PIN_DF_SCLK_S,
184 MFP_PIN_nBE0,
185 MFP_PIN_nBE1,
186 MFP_PIN_DF_nADV2_ALE,
187 MFP_PIN_DF_INT_RnB,
188 MFP_PIN_DF_nCS0,
189 MFP_PIN_DF_nCS1,
190 MFP_PIN_nLUA,
191 MFP_PIN_nLLA,
192 MFP_PIN_DF_nWE,
193 MFP_PIN_DF_ALE_nWE,
194 MFP_PIN_DF_nRE_nOE,
195 MFP_PIN_DF_ADDR0,
196 MFP_PIN_DF_ADDR1,
197 MFP_PIN_DF_ADDR2,
198 MFP_PIN_DF_ADDR3,
199 MFP_PIN_DF_IO0,
200 MFP_PIN_DF_IO1,
201 MFP_PIN_DF_IO2,
202 MFP_PIN_DF_IO3,
203 MFP_PIN_DF_IO4,
204 MFP_PIN_DF_IO5,
205 MFP_PIN_DF_IO6,
206 MFP_PIN_DF_IO7,
207 MFP_PIN_DF_IO8,
208 MFP_PIN_DF_IO9,
209 MFP_PIN_DF_IO10,
210 MFP_PIN_DF_IO11,
211 MFP_PIN_DF_IO12,
212 MFP_PIN_DF_IO13,
213 MFP_PIN_DF_IO14,
214 MFP_PIN_DF_IO15,
215
216 MFP_PIN_MAX,
217};
218
219/*
220 * Table that determines the low power modes outputs, with actual settings
221 * used in parentheses for don't-care values. Except for the float output,
222 * the configured driven and pulled levels match, so if there is a need for
223 * non-LPM pulled output, the same configuration could probably be used.
224 *
225 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
226 * (bit 7) (bit 8) (bit 14d) (bit 13d)
227 *
228 * Drive 0 0 0 0 X (1) 0
229 * Drive 1 0 1 X (1) 0 0
230 * Pull hi (1) 1 X(1) 1 0 0
231 * Pull lo (0) 1 X(0) 0 1 0
232 * Z (float) 1 X(0) 0 0 0
233 */
234#define MFP_LPM_DRIVE_LOW 0x8
235#define MFP_LPM_DRIVE_HIGH 0x6
236#define MFP_LPM_PULL_HIGH 0x7
237#define MFP_LPM_PULL_LOW 0x9
238#define MFP_LPM_FLOAT 0x1
239#define MFP_LPM_PULL_NEITHER 0x0
240
241/*
242 * The pullup and pulldown state of the MFP pin is by default determined by
243 * selected alternate function. In case some buggy devices need to override
244 * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of
245 * the following definition as the parameter.
246 *
247 * Definition pull_sel pullup_en pulldown_en
248 * MFP_PULL_HIGH 1 1 0
249 * MFP_PULL_LOW 1 0 1
250 * MFP_PULL_BOTH 1 1 1
251 * MFP_PULL_NONE 1 0 0
252 * MFP_PULL_DEFAULT 0 X X
253 *
254 * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN
255 * bits, which will cause potential conflicts with the low power mode
256 * setting, device drivers should take care of this
257 */
258#define MFP_PULL_BOTH (0x7u)
259#define MFP_PULL_HIGH (0x6u)
260#define MFP_PULL_LOW (0x5u)
261#define MFP_PULL_NONE (0x4u)
262#define MFP_PULL_DEFAULT (0x0u)
263
264#define MFP_AF0 (0)
265#define MFP_AF1 (1)
266#define MFP_AF2 (2)
267#define MFP_AF3 (3)
268#define MFP_AF4 (4)
269#define MFP_AF5 (5)
270#define MFP_AF6 (6)
271#define MFP_AF7 (7)
272
273#define MFP_DS01X (0)
274#define MFP_DS02X (1)
275#define MFP_DS03X (2)
276#define MFP_DS04X (3)
277#define MFP_DS06X (4)
278#define MFP_DS08X (5)
279#define MFP_DS10X (6)
280#define MFP_DS12X (7)
281
282#define MFP_EDGE_BOTH 0x3
283#define MFP_EDGE_RISE 0x2
284#define MFP_EDGE_FALL 0x1
285#define MFP_EDGE_NONE 0x0
286
287#define MFPR_AF_MASK 0x0007
288#define MFPR_DRV_MASK 0x1c00
289#define MFPR_RDH_MASK 0x0200
290#define MFPR_LPM_MASK 0xe180
291#define MFPR_PULL_MASK 0xe000
292#define MFPR_EDGE_MASK 0x0070
293
294#define MFPR_ALT_OFFSET 0
295#define MFPR_ERE_OFFSET 4
296#define MFPR_EFE_OFFSET 5
297#define MFPR_EC_OFFSET 6
298#define MFPR_SON_OFFSET 7
299#define MFPR_SD_OFFSET 8
300#define MFPR_SS_OFFSET 9
301#define MFPR_DRV_OFFSET 10
302#define MFPR_PD_OFFSET 13
303#define MFPR_PU_OFFSET 14
304#define MFPR_PS_OFFSET 15
305
306#define MFPR(af, drv, rdh, lpm, edge) \
307 (((af) & 0x7) | (((drv) & 0x7) << 10) |\
308 (((rdh) & 0x1) << 9) |\
309 (((lpm) & 0x3) << 7) |\
310 (((lpm) & 0x4) << 12)|\
311 (((lpm) & 0x8) << 10)|\
312 ((!(edge)) << 6) |\
313 (((edge) & 0x1) << 5) |\
314 (((edge) & 0x2) << 3))
315
316/*
317 * a possible MFP configuration is represented by a 32-bit integer
318 * bit 0..15 - MFPR value (16-bit)
319 * bit 16..31 - mfp pin index (used to obtain the MFPR offset)
320 *
321 * to facilitate the definition, the following macros are provided
322 *
323 * MFPR_DEFAULT - default MFPR value, with
324 * alternate function = 0,
325 * drive strength = fast 1mA (MFP_DS01X)
326 * low power mode = default
327 * release dalay hold = false (RDH bit)
328 * edge detection = none
329 *
330 * MFP_CFG - default MFPR value with alternate function
331 * MFP_CFG_DRV - default MFPR value with alternate function and
332 * pin drive strength
333 * MFP_CFG_LPM - default MFPR value with alternate function and
334 * low power mode
335 * MFP_CFG_X - default MFPR value with alternate function,
336 * pin drive strength and low power mode
337 *
338 * use
339 *
340 * MFP_CFG_PIN - to get the MFP pin index
341 * MFP_CFG_VAL - to get the corresponding MFPR value
342 */
343
344typedef uint32_t mfp_cfg_t;
345
346#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff)
347#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff)
348
349#define MFPR_DEFAULT (0x0000)
350
351#define MFP_CFG(pin, af) \
352 ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af))
353
354#define MFP_CFG_DRV(pin, af, drv) \
355 ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
356 ((MFP_##drv) << 10) | (MFP_##af))
357
358#define MFP_CFG_LPM(pin, af, lpm) \
359 ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af) |\
360 (((MFP_LPM_##lpm) & 0x3) << 7) |\
361 (((MFP_LPM_##lpm) & 0x4) << 12) |\
362 (((MFP_LPM_##lpm) & 0x8) << 10))
363
364#define MFP_CFG_X(pin, af, drv, lpm) \
365 ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
366 ((MFP_##drv) << 10) | (MFP_##af) |\
367 (((MFP_LPM_##lpm) & 0x3) << 7) |\
368 (((MFP_LPM_##lpm) & 0x4) << 12) |\
369 (((MFP_LPM_##lpm) & 0x8) << 10))
370
371/* common MFP configurations - processor specific ones defined
372 * in mfp-pxa3xx.h
373 */
374#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
375#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
376#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
377#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
378#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
379#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
380#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
381#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
382#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
383#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
384#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
385#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
386#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
387#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
388#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
389#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
390#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
391#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
392#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
393#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
394#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
395#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
396#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
397#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
398#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
399#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
400#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
401#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
402#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
403#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
404#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
405#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
406#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
407#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
408#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
409#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
410#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
411#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
412#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
413#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
414#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
415#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
416#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
417#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
418#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
419#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
420
421#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
422#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
423
424#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
425#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
426#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
427
428#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
429
430#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
431#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
432#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
433#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
434#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
435#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
436#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
437#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
438#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
439#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
440#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
441#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
442#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
443#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
444#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
445#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
446#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
447#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
448#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
449#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
450#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
451#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
452#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
453#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
454#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
455#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
456#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
457#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
458#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
459#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
460#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
461#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
462#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
463#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
464#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
465#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
466#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
467#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
468#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
469#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
470#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
471#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
472#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
473#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
474#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
475#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
476#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
477#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
478#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
479#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
480#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
481#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
482#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
483#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
484#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
485#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
486#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
487#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
488#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
489#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
490#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
491#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
492#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
493#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
494#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
495
496#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
497#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
498#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
499#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
500#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
501#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
502#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
503
504/*
505 * each MFP pin will have a MFPR register, since the offset of the
506 * register varies between processors, the processor specific code
507 * should initialize the pin offsets by pxa3xx_mfp_init_addr()
508 *
509 * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
510 * structure, which represents a range of MFP pins from "start" to
511 * "end", with the offset begining at "offset", to define a single
512 * pin, let "end" = -1
513 *
514 * use
515 *
516 * MFP_ADDR_X() to define a range of pins
517 * MFP_ADDR() to define a single pin
518 * MFP_ADDR_END to signal the end of pin offset definitions
519 */
520struct pxa3xx_mfp_addr_map {
521 unsigned int start;
522 unsigned int end;
523 unsigned long offset;
524};
525
526#define MFP_ADDR_X(start, end, offset) \
527 { MFP_PIN_##start, MFP_PIN_##end, offset }
528
529#define MFP_ADDR(pin, offset) \
530 { MFP_PIN_##pin, -1, offset }
531
532#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
533
534struct pxa3xx_mfp_pin {
535 unsigned long mfpr_off; /* MFPRxx register offset */
536 unsigned long mfpr_val; /* MFPRxx register value */
537};
538
539/*
540 * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
541 * to the MFPR register
542 */
543unsigned long pxa3xx_mfp_read(int mfp);
544void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
545
546/*
547 * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength
548 * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off
549 * pxa3xx_mfp_set_lpm - set MFP low power mode state
550 * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode
551 *
552 * use these functions to override/change the default configuration
553 * done by pxa3xx_mfp_set_config(s)
554 */
555void pxa3xx_mfp_set_afds(int mfp, int af, int ds);
556void pxa3xx_mfp_set_rdh(int mfp, int rdh);
557void pxa3xx_mfp_set_lpm(int mfp, int lpm);
558void pxa3xx_mfp_set_edge(int mfp, int edge);
559
560/*
561 * pxa3xx_mfp_config - configure the MFPR registers
562 *
563 * used by board specific initialization code
564 */
565void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num);
566
567/*
568 * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
569 * index and MFPR register offset
570 *
571 * used by processor specific code
572 */
573void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
574void __init pxa3xx_init_mfp(void);
575
576#endif /* __ASM_ARCH_MFP_H */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index e68b593d69da..67f53e07db86 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1177,7 +1177,7 @@
1177 1177
1178#define GPIO_bit(x) (1 << ((x) & 0x1f)) 1178#define GPIO_bit(x) (1 << ((x) & 0x1f))
1179 1179
1180#ifdef CONFIG_PXA27x 1180#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1181 1181
1182/* Interrupt Controller */ 1182/* Interrupt Controller */
1183 1183
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
new file mode 100644
index 000000000000..3900a0ca0bc0
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -0,0 +1,75 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h
3 *
4 * PXA3xx specific register definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_PXA3XX_REGS_H
14#define __ASM_ARCH_PXA3XX_REGS_H
15
16/*
17 * Application Subsystem Clock
18 */
19#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
20#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
21#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
22#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
23#define CKENB __REG(0x41340010) /* B Clock Enable Register */
24#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
25
26/*
27 * Clock Enable Bit
28 */
29#define CKEN_LCD 1 /* < LCD Clock Enable */
30#define CKEN_USBH 2 /* < USB host clock enable */
31#define CKEN_CAMERA 3 /* < Camera interface clock enable */
32#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
33#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */
34#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
35#define CKEN_SMC 9 /* < Static Memory Controller clock enable */
36#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */
37#define CKEN_BOOT 11 /* < Boot rom clock enable */
38#define CKEN_MMC1 12 /* < MMC1 Clock enable */
39#define CKEN_MMC2 13 /* < MMC2 clock enable */
40#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
41#define CKEN_CIR 15 /* < Consumer IR Clock Enable */
42#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
43#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
44#define CKEN_TPM 19 /* < TPM clock enable */
45#define CKEN_UDC 20 /* < UDC clock enable */
46#define CKEN_BTUART 21 /* < BTUART clock enable */
47#define CKEN_FFUART 22 /* < FFUART clock enable */
48#define CKEN_STUART 23 /* < STUART clock enable */
49#define CKEN_AC97 24 /* < AC97 clock enable */
50#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
51#define CKEN_SSP1 26 /* < SSP1 clock enable */
52#define CKEN_SSP2 27 /* < SSP2 clock enable */
53#define CKEN_SSP3 28 /* < SSP3 clock enable */
54#define CKEN_SSP4 29 /* < SSP4 clock enable */
55#define CKEN_MSL0 30 /* < MSL0 clock enable */
56#define CKEN_PWM0 32 /* < PWM[0] clock enable */
57#define CKEN_PWM1 33 /* < PWM[1] clock enable */
58#define CKEN_I2C 36 /* < I2C clock enable */
59#define CKEN_INTC 38 /* < Interrupt controller clock enable */
60#define CKEN_GPIO 39 /* < GPIO clock enable */
61#define CKEN_1WIRE 40 /* < 1-wire clock enable */
62#define CKEN_HSIO2 41 /* < HSIO2 clock enable */
63#define CKEN_MINI_IM 48 /* < Mini-IM */
64#define CKEN_MINI_LCD 49 /* < Mini LCD */
65
66#if defined(CONFIG_CPU_PXA310)
67#define CKEN_MMC3 5 /* < MMC3 Clock Enable */
68#define CKEN_MVED 43 /* < MVED clock enable */
69#endif
70
71/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
72#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */
73#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */
74
75#endif /* __ASM_ARCH_PXA3XX_REGS_H */
diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h
index 2473bb51d0a6..8d882f0b6a16 100644
--- a/include/asm-arm/arch-pxa/timex.h
+++ b/include/asm-arm/arch-pxa/timex.h
@@ -21,4 +21,6 @@
21#else 21#else
22#define CLOCK_TICK_RATE 3250000 22#define CLOCK_TICK_RATE 3250000
23#endif 23#endif
24#else
25#define CLOCK_TICK_RATE 3250000
24#endif 26#endif
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
new file mode 100644
index 000000000000..f58b59162b82
--- /dev/null
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -0,0 +1,35 @@
1#ifndef __ASM_ARCH_ZYLONITE_H
2#define __ASM_ARCH_ZYLONITE_H
3
4#define ZYLONITE_ETH_PHYS 0x14000000
5
6/* the following variables are processor specific and initialized
7 * by the corresponding zylonite_pxa3xx_init()
8 */
9extern int gpio_backlight;
10extern int gpio_eth_irq;
11
12extern int lcd_id;
13extern int lcd_orientation;
14
15#ifdef CONFIG_CPU_PXA300
16extern void zylonite_pxa300_init(void);
17#else
18static inline void zylonite_pxa300_init(void)
19{
20 if (cpu_is_pxa300() || cpu_is_pxa310())
21 panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__);
22}
23#endif
24
25#ifdef CONFIG_CPU_PXA320
26extern void zylonite_pxa320_init(void);
27#else
28static inline void zylonite_pxa320_init(void)
29{
30 if (cpu_is_pxa320())
31 panic("%s: PXA320 not supported\n", __FUNCTION__);
32}
33#endif
34
35#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/include/asm-arm/arch-rpc/uncompress.h b/include/asm-arm/arch-rpc/uncompress.h
index 06231ede54e5..b8e29efd8c5b 100644
--- a/include/asm-arm/arch-rpc/uncompress.h
+++ b/include/asm-arm/arch-rpc/uncompress.h
@@ -11,9 +11,11 @@
11 11
12#include <asm/hardware.h> 12#include <asm/hardware.h>
13#include <asm/io.h> 13#include <asm/io.h>
14#include <asm/setup.h>
15#include <asm/page.h>
14 16
15int video_num_columns, video_num_lines, video_size_row; 17int video_size_row;
16int white, bytes_per_char_h; 18unsigned char bytes_per_char_h;
17extern unsigned long con_charconvtable[256]; 19extern unsigned long con_charconvtable[256];
18 20
19struct param_struct { 21struct param_struct {
@@ -64,6 +66,13 @@ extern __attribute__((pure)) struct param_struct *params(void);
64#define params (params()) 66#define params (params())
65 67
66#ifndef STANDALONE_DEBUG 68#ifndef STANDALONE_DEBUG
69static unsigned long video_num_cols;
70static unsigned long video_num_rows;
71static unsigned long video_x;
72static unsigned long video_y;
73static unsigned char bytes_per_char_v;
74static int white;
75
67/* 76/*
68 * This does not append a newline 77 * This does not append a newline
69 */ 78 */
@@ -73,27 +82,27 @@ static void putc(int c)
73 int x,y; 82 int x,y;
74 char *ptr; 83 char *ptr;
75 84
76 x = params->video_x; 85 x = video_x;
77 y = params->video_y; 86 y = video_y;
78 87
79 if (c == '\n') { 88 if (c == '\n') {
80 if (++y >= video_num_lines) 89 if (++y >= video_num_rows)
81 y--; 90 y--;
82 } else if (c == '\r') { 91 } else if (c == '\r') {
83 x = 0; 92 x = 0;
84 } else { 93 } else {
85 ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h); 94 ptr = VIDMEM + ((y*video_num_cols*bytes_per_char_v+x)*bytes_per_char_h);
86 ll_write_char(ptr, c, white); 95 ll_write_char(ptr, c, white);
87 if (++x >= video_num_columns) { 96 if (++x >= video_num_cols) {
88 x = 0; 97 x = 0;
89 if ( ++y >= video_num_lines ) { 98 if ( ++y >= video_num_rows ) {
90 y--; 99 y--;
91 } 100 }
92 } 101 }
93 } 102 }
94 103
95 params->video_x = x; 104 video_x = x;
96 params->video_y = y; 105 video_y = y;
97} 106}
98 107
99static inline void flush(void) 108static inline void flush(void)
@@ -108,11 +117,44 @@ static void error(char *x);
108static void arch_decomp_setup(void) 117static void arch_decomp_setup(void)
109{ 118{
110 int i; 119 int i;
120 struct tag *t = (struct tag *)params;
121 unsigned int nr_pages = 0, page_size = PAGE_SIZE;
122
123 if (t->hdr.tag == ATAG_CORE)
124 {
125 for (; t->hdr.size; t = tag_next(t))
126 {
127 if (t->hdr.tag == ATAG_VIDEOTEXT)
128 {
129 video_num_rows = t->u.videotext.video_lines;
130 video_num_cols = t->u.videotext.video_cols;
131 bytes_per_char_h = t->u.videotext.video_points;
132 bytes_per_char_v = t->u.videotext.video_points;
133 video_x = t->u.videotext.x;
134 video_y = t->u.videotext.y;
135 }
136
137 if (t->hdr.tag == ATAG_MEM)
138 {
139 page_size = PAGE_SIZE;
140 nr_pages += (t->u.mem.size / PAGE_SIZE);
141 }
142 }
143 }
144 else
145 {
146 nr_pages = params->nr_pages;
147 page_size = params->page_size;
148 video_num_rows = params->video_num_rows;
149 video_num_cols = params->video_num_cols;
150 video_x = params->video_x;
151 video_y = params->video_y;
152 bytes_per_char_h = params->bytes_per_char_h;
153 bytes_per_char_v = params->bytes_per_char_v;
154 }
155
156 video_size_row = video_num_cols * bytes_per_char_h;
111 157
112 video_num_lines = params->video_num_rows;
113 video_num_columns = params->video_num_cols;
114 bytes_per_char_h = params->bytes_per_char_h;
115 video_size_row = video_num_columns * bytes_per_char_h;
116 if (bytes_per_char_h == 4) 158 if (bytes_per_char_h == 4)
117 for (i = 0; i < 256; i++) 159 for (i = 0; i < 256; i++)
118 con_charconvtable[i] = 160 con_charconvtable[i] =
@@ -146,7 +188,7 @@ static void arch_decomp_setup(void)
146 white = 7; 188 white = 7;
147 } 189 }
148 190
149 if (params->nr_pages * params->page_size < 4096*1024) error("<4M of mem\n"); 191 if (nr_pages * page_size < 4096*1024) error("<4M of mem\n");
150} 192}
151#endif 193#endif
152 194
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
index 3b49cd1c345c..996f65488d2d 100644
--- a/include/asm-arm/arch-s3c2410/irqs.h
+++ b/include/asm-arm/arch-s3c2410/irqs.h
@@ -112,6 +112,13 @@
112#define IRQ_TC S3C2410_IRQSUB(9) 112#define IRQ_TC S3C2410_IRQSUB(9)
113#define IRQ_ADC S3C2410_IRQSUB(10) 113#define IRQ_ADC S3C2410_IRQSUB(10)
114 114
115/* extra irqs for s3c2412 */
116
117#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21)
118
119#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
120#define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
121
115/* extra irqs for s3c2440 */ 122/* extra irqs for s3c2440 */
116 123
117#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ 124#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index dea578b8f7f6..b693158b2d3c 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -1140,10 +1140,16 @@
1140 1140
1141/* definitions for each pin bit */ 1141/* definitions for each pin bit */
1142#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) 1142#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
1143#define S3C2412_SLPCON_HI(x) ( 0x01 << ((x) * 2)) 1143#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2))
1144#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) 1144#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
1145#define S3C2412_SLPCON_PDWN(x) ( 0x03 << ((x) * 2)) 1145#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2))
1146#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */
1146#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) 1147#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
1147 1148
1149#define S3C2412_SLPCON_ALL_LOW (0x0)
1150#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
1151#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888)
1152#define S3C2412_SLPCON_ALL_PULL (0x33333333)
1153
1148#endif /* __ASM_ARCH_REGS_GPIO_H */ 1154#endif /* __ASM_ARCH_REGS_GPIO_H */
1149 1155
diff --git a/include/asm-arm/arch-s3c2410/regs-power.h b/include/asm-arm/arch-s3c2410/regs-power.h
index 94ff96505b6a..f79987be55e8 100644
--- a/include/asm-arm/arch-s3c2410/regs-power.h
+++ b/include/asm-arm/arch-s3c2410/regs-power.h
@@ -18,6 +18,11 @@
18#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) 18#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20)
19#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) 19#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24)
20 20
21#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70)
22#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74)
23#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
24#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
25
21#define S3C2412_PWRCFG_BATF_IGNORE (0<<0) 26#define S3C2412_PWRCFG_BATF_IGNORE (0<<0)
22#define S3C2412_PWRCFG_BATF_SLEEP (3<<0) 27#define S3C2412_PWRCFG_BATF_SLEEP (3<<0)
23#define S3C2412_PWRCFG_BATF_MASK (3<<0) 28#define S3C2412_PWRCFG_BATF_MASK (3<<0)
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412.h b/include/asm-arm/arch-s3c2410/regs-s3c2412.h
index 8ca6a3bc8555..783b18f5bcea 100644
--- a/include/asm-arm/arch-s3c2410/regs-s3c2412.h
+++ b/include/asm-arm/arch-s3c2410/regs-s3c2412.h
@@ -17,5 +17,7 @@
17#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) 17#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
18#define S3C2412_SWRST_RESET (0x533C2412) 18#define S3C2412_SWRST_RESET (0x533C2412)
19 19
20/* see regs-power.h for the other registers in the power block. */
21
20#endif /* __ASM_ARCH_REGS_S3C2412_H */ 22#endif /* __ASM_ARCH_REGS_S3C2412_H */
21 23
diff --git a/include/asm-arm/arch-sa1100/SA-1101.h b/include/asm-arm/arch-sa1100/SA-1101.h
index 527d887f1ee3..65ca8c79e6d2 100644
--- a/include/asm-arm/arch-sa1100/SA-1101.h
+++ b/include/asm-arm/arch-sa1100/SA-1101.h
@@ -106,7 +106,7 @@
106#define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \ 106#define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \
107 (( (x) - 8 ) << FShft (SMCR_DCAC)) 107 (( (x) - 8 ) << FShft (SMCR_DCAC))
108#define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\ 108#define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\
109 (( (x) - 9 ) << FShft (SMCR_DRAC) 109 (( (x) - 9 ) << FShft (SMCR_DRAC))
110 110
111#define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */ 111#define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */
112#define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */ 112#define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */
@@ -394,7 +394,7 @@
394#define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus))) 394#define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus)))
395#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask))) 395#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask)))
396#define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette))) 396#define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette)))
397#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl)) 397#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl)))
398#define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest))) 398#define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest)))
399 399
400#define VideoControl_VgaEn 0x00000000 400#define VideoControl_VgaEn 0x00000000
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h
index c8b5d0db0cf0..678134bf2475 100644
--- a/include/asm-arm/dma-mapping.h
+++ b/include/asm-arm/dma-mapping.h
@@ -17,7 +17,7 @@
17 * platforms with CONFIG_DMABOUNCE. 17 * platforms with CONFIG_DMABOUNCE.
18 * Use the driver DMA support - see dma-mapping.h (dma_sync_*) 18 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
19 */ 19 */
20extern void consistent_sync(const void *kaddr, size_t size, int rw); 20extern void dma_cache_maint(const void *kaddr, size_t size, int rw);
21 21
22/* 22/*
23 * Return whether the given device DMA address mask can be supported 23 * Return whether the given device DMA address mask can be supported
@@ -165,7 +165,7 @@ dma_map_single(struct device *dev, void *cpu_addr, size_t size,
165 enum dma_data_direction dir) 165 enum dma_data_direction dir)
166{ 166{
167 if (!arch_is_coherent()) 167 if (!arch_is_coherent())
168 consistent_sync(cpu_addr, size, dir); 168 dma_cache_maint(cpu_addr, size, dir);
169 169
170 return virt_to_dma(dev, (unsigned long)cpu_addr); 170 return virt_to_dma(dev, (unsigned long)cpu_addr);
171} 171}
@@ -278,7 +278,7 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
278 virt = page_address(sg->page) + sg->offset; 278 virt = page_address(sg->page) + sg->offset;
279 279
280 if (!arch_is_coherent()) 280 if (!arch_is_coherent())
281 consistent_sync(virt, sg->length, dir); 281 dma_cache_maint(virt, sg->length, dir);
282 } 282 }
283 283
284 return nents; 284 return nents;
@@ -334,7 +334,7 @@ dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size,
334 enum dma_data_direction dir) 334 enum dma_data_direction dir)
335{ 335{
336 if (!arch_is_coherent()) 336 if (!arch_is_coherent())
337 consistent_sync((void *)dma_to_virt(dev, handle), size, dir); 337 dma_cache_maint((void *)dma_to_virt(dev, handle), size, dir);
338} 338}
339 339
340static inline void 340static inline void
@@ -342,7 +342,7 @@ dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size,
342 enum dma_data_direction dir) 342 enum dma_data_direction dir)
343{ 343{
344 if (!arch_is_coherent()) 344 if (!arch_is_coherent())
345 consistent_sync((void *)dma_to_virt(dev, handle), size, dir); 345 dma_cache_maint((void *)dma_to_virt(dev, handle), size, dir);
346} 346}
347#else 347#else
348extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction); 348extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction);
@@ -373,7 +373,7 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
373 for (i = 0; i < nents; i++, sg++) { 373 for (i = 0; i < nents; i++, sg++) {
374 char *virt = page_address(sg->page) + sg->offset; 374 char *virt = page_address(sg->page) + sg->offset;
375 if (!arch_is_coherent()) 375 if (!arch_is_coherent())
376 consistent_sync(virt, sg->length, dir); 376 dma_cache_maint(virt, sg->length, dir);
377 } 377 }
378} 378}
379 379
@@ -386,7 +386,7 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
386 for (i = 0; i < nents; i++, sg++) { 386 for (i = 0; i < nents; i++, sg++) {
387 char *virt = page_address(sg->page) + sg->offset; 387 char *virt = page_address(sg->page) + sg->offset;
388 if (!arch_is_coherent()) 388 if (!arch_is_coherent())
389 consistent_sync(virt, sg->length, dir); 389 dma_cache_maint(virt, sg->length, dir);
390 } 390 }
391} 391}
392#else 392#else
diff --git a/include/asm-arm/hardware/it8152.h b/include/asm-arm/hardware/it8152.h
new file mode 100644
index 000000000000..aaebb61aca48
--- /dev/null
+++ b/include/asm-arm/hardware/it8152.h
@@ -0,0 +1,99 @@
1/*
2 * linux/include/arm/hardware/it8152.h
3 *
4 * Copyright Compulab Ltd., 2006,2007
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * ITE 8152 companion chip register definitions
8 */
9
10#ifndef __ASM_HARDWARE_IT8152_H
11#define __ASM_HARDWARE_IT8152_H
12extern unsigned long it8152_base_address;
13
14#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
15#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)
16
17#define __REG_IT8152(x) (it8152_base_address + (x))
18
19#define IT8152_PCI_CFG_ADDR __REG_IT8152(0x3f00800)
20#define IT8152_PCI_CFG_DATA __REG_IT8152(0x3f00804)
21
22#define IT8152_INTC_LDCNIRR __REG_IT8152(0x3f00300)
23#define IT8152_INTC_LDPNIRR __REG_IT8152(0x3f00304)
24#define IT8152_INTC_LDCNIMR __REG_IT8152(0x3f00308)
25#define IT8152_INTC_LDPNIMR __REG_IT8152(0x3f0030C)
26#define IT8152_INTC_LDNITR __REG_IT8152(0x3f00310)
27#define IT8152_INTC_LDNIAR __REG_IT8152(0x3f00314)
28#define IT8152_INTC_LPCNIRR __REG_IT8152(0x3f00320)
29#define IT8152_INTC_LPPNIRR __REG_IT8152(0x3f00324)
30#define IT8152_INTC_LPCNIMR __REG_IT8152(0x3f00328)
31#define IT8152_INTC_LPPNIMR __REG_IT8152(0x3f0032C)
32#define IT8152_INTC_LPNITR __REG_IT8152(0x3f00330)
33#define IT8152_INTC_LPNIAR __REG_IT8152(0x3f00334)
34#define IT8152_INTC_PDCNIRR __REG_IT8152(0x3f00340)
35#define IT8152_INTC_PDPNIRR __REG_IT8152(0x3f00344)
36#define IT8152_INTC_PDCNIMR __REG_IT8152(0x3f00348)
37#define IT8152_INTC_PDPNIMR __REG_IT8152(0x3f0034C)
38#define IT8152_INTC_PDNITR __REG_IT8152(0x3f00350)
39#define IT8152_INTC_PDNIAR __REG_IT8152(0x3f00354)
40#define IT8152_INTC_INTC_TYPER __REG_IT8152(0x3f003FC)
41
42#define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500)
43
44/*
45 Interrup contoler per register summary:
46 ---------------------------------------
47 LCDNIRR:
48 IT8152_LD_IRQ(8) PCICLK stop
49 IT8152_LD_IRQ(7) MCLK ready
50 IT8152_LD_IRQ(6) s/w
51 IT8152_LD_IRQ(5) UART
52 IT8152_LD_IRQ(4) GPIO
53 IT8152_LD_IRQ(3) TIMER 4
54 IT8152_LD_IRQ(2) TIMER 3
55 IT8152_LD_IRQ(1) TIMER 2
56 IT8152_LD_IRQ(0) TIMER 1
57
58 LPCNIRR:
59 IT8152_LP_IRQ(x) serial IRQ x
60
61 PCIDNIRR:
62 IT8152_PD_IRQ(14) PCISERR
63 IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR)
64 IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR)
65 IT8152_PD_IRQ(11) PCI INTD
66 IT8152_PD_IRQ(10) PCI INTC
67 IT8152_PD_IRQ(9) PCI INTB
68 IT8152_PD_IRQ(8) PCI INTA
69 IT8152_PD_IRQ(7) serial INTD
70 IT8152_PD_IRQ(6) serial INTC
71 IT8152_PD_IRQ(5) serial INTB
72 IT8152_PD_IRQ(4) serial INTA
73 IT8152_PD_IRQ(3) serial IRQ IOCHK (IOCHKR)
74 IT8152_PD_IRQ(2) chaining DMA (CDMAR)
75 IT8152_PD_IRQ(1) USB (USBR)
76 IT8152_PD_IRQ(0) Audio controller (ACR)
77 */
78/* frequently used interrupts */
79#define IT8152_PCISERR IT8152_PD_IRQ(14)
80#define IT8152_H2PTADR IT8152_PD_IRQ(13)
81#define IT8152_H2PMAR IT8152_PD_IRQ(12)
82#define IT8152_PCI_INTD IT8152_PD_IRQ(11)
83#define IT8152_PCI_INTC IT8152_PD_IRQ(10)
84#define IT8152_PCI_INTB IT8152_PD_IRQ(9)
85#define IT8152_PCI_INTA IT8152_PD_IRQ(8)
86#define IT8152_CDMA_INT IT8152_PD_IRQ(2)
87#define IT8152_USB_INT IT8152_PD_IRQ(1)
88#define IT8152_AUDIO_INT IT8152_PD_IRQ(0)
89
90struct pci_dev;
91struct pci_sys_data;
92
93extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
94extern void it8152_init_irq(void);
95extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
96extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
97extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
98
99#endif /* __ASM_HARDWARE_IT8152_H */
diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h
index b5b030ef633d..46dcc4d0b9bd 100644
--- a/include/asm-arm/kexec.h
+++ b/include/asm-arm/kexec.h
@@ -14,6 +14,8 @@
14 14
15#define KEXEC_ARCH KEXEC_ARCH_ARM 15#define KEXEC_ARCH KEXEC_ARCH_ARM
16 16
17#define KEXEC_BOOT_PARAMS_SIZE 1536
18
17#ifndef __ASSEMBLY__ 19#ifndef __ASSEMBLY__
18 20
19struct kimage; 21struct kimage;
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index ed3f898191f4..75feb1574a69 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -8,10 +8,17 @@
8 8
9#define pcibios_scan_all_fns(a, b) 0 9#define pcibios_scan_all_fns(a, b) 0
10 10
11#ifdef CONFIG_PCI_HOST_ITE8152
12/* ITE bridge requires setting latency timer to avoid early bus access
13 termination by PIC bus mater devices
14*/
15extern void pcibios_set_master(struct pci_dev *dev);
16#else
11static inline void pcibios_set_master(struct pci_dev *dev) 17static inline void pcibios_set_master(struct pci_dev *dev)
12{ 18{
13 /* No special bus mastering setup handling */ 19 /* No special bus mastering setup handling */
14} 20}
21#endif
15 22
16static inline void pcibios_penalize_isa_irq(int irq, int active) 23static inline void pcibios_penalize_isa_irq(int irq, int active)
17{ 24{
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index d327b25c986c..88e868b7aae0 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -378,6 +378,7 @@
378#define __NR_signalfd (__NR_SYSCALL_BASE+349) 378#define __NR_signalfd (__NR_SYSCALL_BASE+349)
379#define __NR_timerfd (__NR_SYSCALL_BASE+350) 379#define __NR_timerfd (__NR_SYSCALL_BASE+350)
380#define __NR_eventfd (__NR_SYSCALL_BASE+351) 380#define __NR_eventfd (__NR_SYSCALL_BASE+351)
381#define __NR_fallocate (__NR_SYSCALL_BASE+352)
381 382
382/* 383/*
383 * The following SWIs are ARM private. 384 * The following SWIs are ARM private.
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 2aaf1c16ce98..2c49561f9b45 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1636,6 +1636,7 @@
1636#define PCI_DEVICE_ID_ITE_8211 0x8211 1636#define PCI_DEVICE_ID_ITE_8211 0x8211
1637#define PCI_DEVICE_ID_ITE_8212 0x8212 1637#define PCI_DEVICE_ID_ITE_8212 0x8212
1638#define PCI_DEVICE_ID_ITE_8213 0x8213 1638#define PCI_DEVICE_ID_ITE_8213 0x8213
1639#define PCI_DEVICE_ID_ITE_8152 0x8152
1639#define PCI_DEVICE_ID_ITE_8872 0x8872 1640#define PCI_DEVICE_ID_ITE_8872 0x8872
1640#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 1641#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886
1641 1642
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 14:27:29 -0500