182 files changed, 4824 insertions, 2157 deletions
diff --git a/include/asm-alpha/topology.h b/include/asm-alpha/topology.h
index 420ccde6b916..149532e162c4 100644
--- a/include/asm-alpha/topology.h
+++ b/include/asm-alpha/topology.h
@@ -41,8 +41,7 @@ static inline cpumask_t node_to_cpumask(int node)
 #define pcibus_to_cpumask(bus)  (cpu_online_map)
-#else /* CONFIG_NUMA */
-# include <asm-generic/topology.h>
 #endif /* !CONFIG_NUMA */
+# include <asm-generic/topology.h>
 #endif /* _ASM_ALPHA_TOPOLOGY_H */
diff --git a/include/asm-arm/arch-at91/at91_ecc.h b/include/asm-arm/arch-at91/at91_ecc.h
index ff93df516d6d..1e5a8caca2d1 100644
--- a/include/asm-arm/arch-at91/at91_ecc.h
+++ b/include/asm-arm/arch-at91/at91_ecc.h
@@ -13,26 +13,26 @@
 #ifndef AT91_ECC_H
 #define AT91_ECC_H
-#define AT91_ECC_CR             (AT91_ECC + 0x00)       /* Control register */
+#define AT91_ECC_CR             0x00                    /* Control register */
 #define         AT91_ECC_RST            (1 << 0)                /* Reset parity */
-#define AT91_ECC_MR             (AT91_ECC + 0x04)       /* Mode register */
+#define AT91_ECC_MR             0x04                    /* Mode register */
 #define         AT91_ECC_PAGESIZE       (3 << 0)                /* Page Size */
 #define                 AT91_ECC_PAGESIZE_528           (0)
 #define                 AT91_ECC_PAGESIZE_1056          (1)
 #define                 AT91_ECC_PAGESIZE_2112          (2)
 #define                 AT91_ECC_PAGESIZE_4224          (3)
-#define AT91_ECC_SR             (AT91_ECC + 0x08)       /* Status register */
+#define AT91_ECC_SR             0x08                    /* Status register */
 #define         AT91_ECC_RECERR         (1 << 0)                /* Recoverable Error */
 #define         AT91_ECC_ECCERR         (1 << 1)                /* ECC Single Bit Error */
 #define         AT91_ECC_MULERR         (1 << 2)                /* Multiple Errors */
-#define AT91_ECC_PR             (AT91_ECC + 0x0c)       /* Parity register */
+#define AT91_ECC_PR             0x0c                    /* Parity register */
 #define         AT91_ECC_BITADDR        (0xf << 0)              /* Bit Error Address */
 #define         AT91_ECC_WORDADDR       (0xfff << 4)            /* Word Error Address */
-#define AT91_ECC_NPR            (AT91_ECC + 0x10)       /* NParity register */
+#define AT91_ECC_NPR            0x10                    /* NParity register */
 #define         AT91_ECC_NPARITY        (0xffff << 0)           /* NParity */
 #endif
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 52cd8e5dabc9..c2b13c280155 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -76,10 +76,17 @@
 #define                 AT91_PMC_PRES_32                (5 << 2)
 #define                 AT91_PMC_PRES_64                (6 << 2)
 #define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
-#define                 AT91_PMC_MDIV_1                 (0 << 8)
+#define                 AT91RM9200_PMC_MDIV_1           (0 << 8)        /* [AT91RM9200 only] */
-#define                 AT91_PMC_MDIV_2                 (1 << 8)
+#define                 AT91RM9200_PMC_MDIV_2           (1 << 8)
-#define                 AT91_PMC_MDIV_3                 (2 << 8)
+#define                 AT91RM9200_PMC_MDIV_3           (2 << 8)
-#define                 AT91_PMC_MDIV_4                 (3 << 8)
+#define                 AT91RM9200_PMC_MDIV_4           (3 << 8)
+#define                 AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9,CAP9 only] */
+#define                 AT91SAM9_PMC_MDIV_2             (1 << 8)
+#define                 AT91SAM9_PMC_MDIV_4             (2 << 8)
+#define                 AT91SAM9_PMC_MDIV_6             (3 << 8)
+#define         AT91_PMC_PDIV           (1 << 12)               /* Processor Clock Division [some SAM9 only] */
+#define                 AT91_PMC_PDIV_1                 (0 << 12)
+#define                 AT91_PMC_PDIV_2                 (1 << 12)
 #define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
diff --git a/include/asm-arm/arch-at91/at91_shdwc.h b/include/asm-arm/arch-at91/at91_shdwc.h
index 01b433de2272..581fa41d90e8 100644
--- a/include/asm-arm/arch-at91/at91_shdwc.h
+++ b/include/asm-arm/arch-at91/at91_shdwc.h
@@ -24,10 +24,12 @@
 #define                 AT91_SHDW_WKMODE0_LOW           2
 #define                 AT91_SHDW_WKMODE0_ANYLEVEL      3
 #define         AT91_SHDW_CPTWK0        (0xf << 4)              /* Counter On Wake Up 0 */
+#define                 AT91_SHDW_CPTWK0_(x)    ((x) << 4)
 #define         AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
 #define AT91_SHDW_SR            (AT91_SHDWC + 0x08)     /* Shut Down Status Register */
 #define         AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
 #define         AT91_SHDW_RTTWK         (1 << 16)               /* Real-time Timer Wake-up */
+#define         AT91_SHDW_RTCWK         (1 << 17)               /* Real-time Clock Wake-up [SAM9RL] */
 #endif
diff --git a/include/asm-arm/arch-at91/at91cap9_ddrsdr.h b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h
new file mode 100644
index 000000000000..efdb23af1ee4
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h
@@ -0,0 +1,100 @@
+/*
+ * include/asm-arm/arch-at91/at91cap9_ddrsdr.h
+ *
+ * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
+ * Based on AT91CAP9 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91CAP9_DDRSDR_H
+#define AT91CAP9_DDRSDR_H
+#define AT91_DDRSDRC_MR         (AT91_DDRSDRC + 0x00)   /* Mode Register */
+#define         AT91_DDRSDRC_MODE       (0xf << 0)              /* Command Mode */
+#define                 AT91_DDRSDRC_MODE_NORMAL                0
+#define                 AT91_DDRSDRC_MODE_NOP           1
+#define                 AT91_DDRSDRC_MODE_PRECHARGE     2
+#define                 AT91_DDRSDRC_MODE_LMR           3
+#define                 AT91_DDRSDRC_MODE_REFRESH       4
+#define                 AT91_DDRSDRC_MODE_EXT_LMR       5
+#define                 AT91_DDRSDRC_MODE_DEEP          6
+#define AT91_DDRSDRC_RTR        (AT91_DDRSDRC + 0x04)   /* Refresh Timer Register */
+#define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
+#define AT91_DDRSDRC_CR         (AT91_DDRSDRC + 0x08)   /* Configuration Register */
+#define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
+#define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
+#define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
+#define                 AT91_DDRSDRC_NC_SDR10   (2 << 0)
+#define                 AT91_DDRSDRC_NC_SDR11   (3 << 0)
+#define                 AT91_DDRSDRC_NC_DDR9    (0 << 0)
+#define                 AT91_DDRSDRC_NC_DDR10   (1 << 0)
+#define                 AT91_DDRSDRC_NC_DDR11   (2 << 0)
+#define                 AT91_DDRSDRC_NC_DDR12   (3 << 0)
+#define         AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
+#define                 AT91_DDRSDRC_NR_11      (0 << 2)
+#define                 AT91_DDRSDRC_NR_12      (1 << 2)
+#define                 AT91_DDRSDRC_NR_13      (2 << 2)
+#define         AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
+#define                 AT91_DDRSDRC_CAS_2      (2 << 4)
+#define                 AT91_DDRSDRC_CAS_3      (3 << 4)
+#define                 AT91_DDRSDRC_CAS_25     (6 << 4)
+#define         AT91_DDRSDRC_DLL        (1 << 7)                /* Reset DLL */
+#define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
+#define AT91_DDRSDRC_T0PR       (AT91_DDRSDRC + 0x0C)   /* Timing 0 Register */
+#define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
+#define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
+#define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
+#define         AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
+#define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
+#define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
+#define         AT91_DDRSDRC_TWTR       (1   << 24)             /* Internal Write to Read delay */
+#define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
+#define AT91_DDRSDRC_T1PR       (AT91_DDRSDRC + 0x10)   /* Timing 1 Register */
+#define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
+#define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
+#define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
+#define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
+#define AT91_DDRSDRC_LPR        (AT91_DDRSDRC + 0x18)   /* Low Power Register */
+#define         AT91_DDRSDRC_LPCB               (3 << 0)        /* Low-power Configurations */
+#define                 AT91_DDRSDRC_LPCB_DISABLE               0
+#define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
+#define                 AT91_DDRSDRC_LPCB_POWER_DOWN            2
+#define                 AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
+#define         AT91_DDRSDRC_CLKFR              (1 << 2)        /* Clock Frozen */
+#define         AT91_DDRSDRC_PASR               (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_DDRSDRC_TCSR               (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_DDRSDRC_DS                 (3 << 10)       /* Drive Strength */
+#define         AT91_DDRSDRC_TIMEOUT            (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
+#define AT91_DDRSDRC_MDR        (AT91_DDRSDRC + 0x1C)   /* Memory Device Register */
+#define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
+#define                 AT91_DDRSDRC_MD_SDR             0
+#define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
+#define                 AT91_DDRSDRC_MD_DDR             2
+#define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
+#define AT91_DDRSDRC_DLLR       (AT91_DDRSDRC + 0x20)   /* DLL Information Register */
+#define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
+#define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
+#define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
+#define         AT91_DDRSDRC_SDCOVF     (1 << 3)                /* Slave Delay Correction Overflow */
+#define         AT91_DDRSDRC_SDCUDF     (1 << 4)                /* Slave Delay Correction Underflow */
+#define         AT91_DDRSDRC_SDERF      (1 << 5)                /* Slave Delay Correction error */
+#define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
+#define         AT91_DDRSDRC_SDVAL      (0xff << 16)            /* Slave Delay value */
+#define         AT91_DDRSDRC_SDCVAL     (0xff << 24)            /* Slave Delay Correction value */
+#endif
diff --git a/include/asm-arm/arch-at91/at91sam926x_mc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h
index d82631c251f1..d3b8b3da6b4d 100644
--- a/include/asm-arm/arch-at91/at91sam926x_mc.h
+++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h
@@ -1,7 +1,7 @@
 /*
- * include/asm-arm/arch-at91/at91sam926x_mc.h
+ * include/asm-arm/arch-at91/at91sam9_sdramc.h
 *
- * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
+ * SDRAM Controllers (SDRAMC) - System peripherals registers.
 * Based on AT91SAM9261 datasheet revision D.
 *
 * This program is free software; you can redistribute it and/or modify
@@ -10,8 +10,8 @@
 * (at your option) any later version.
 */
-#ifndef AT91SAM926x_MC_H
+#ifndef AT91SAM9_SDRAMC_H
-#define AT91SAM926x_MC_H
+#define AT91SAM9_SDRAMC_H
 /* SDRAM Controller (SDRAMC) registers */
 #define AT91_SDRAMC_MR          (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
@@ -62,7 +62,7 @@
 #define                 AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
 #define         AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
 #define         AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
-#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strenght */
+#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strength */
 #define         AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
 #define                 AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
 #define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
@@ -80,62 +80,4 @@
 #define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
-/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
-#define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
-#define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
-#define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
-#define                 AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
-#define         AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
-#define                 AT91_SMC_NRDSETUP_(x)   ((x) << 16)
-#define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
-#define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
-#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
-#define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
-#define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
-#define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
-#define                 AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define         AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
-#define                 AT91_SMC_NRDPULSE_(x)   ((x) << 16)
-#define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
-#define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
-#define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
-#define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
-#define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
-#define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
-#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
-#define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
-#define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
-#define         AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
-#define                 AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
-#define                 AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
-#define                 AT91_SMC_EXNWMODE_READY         (3 << 4)
-#define         AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
-#define                 AT91_SMC_BAT_SELECT             (0 << 8)
-#define                 AT91_SMC_BAT_WRITE              (1 << 8)
-#define         AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
-#define                 AT91_SMC_DBW_8                  (0 << 12)
-#define                 AT91_SMC_DBW_16                 (1 << 12)
-#define                 AT91_SMC_DBW_32                 (2 << 12)
-#define         AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
-#define                 AT91_SMC_TDF_(x)                ((x) << 16)
-#define         AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
-#define         AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
-#define         AT91_SMC_PS             (3 << 28)                       /* Page Size */
-#define                 AT91_SMC_PS_4                   (0 << 28)
-#define                 AT91_SMC_PS_8                   (1 << 28)
-#define                 AT91_SMC_PS_16                  (2 << 28)
-#define                 AT91_SMC_PS_32                  (3 << 28)
-#if defined(AT91_SMC1)          /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)      (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)      (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)      (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)       (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h
new file mode 100644
index 000000000000..9e49eed31e50
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9_smc.h
@@ -0,0 +1,73 @@
+/*
+ * include/asm-arm/arch-at91/at91sam9_smc.h
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91SAM9_SMC_H
+#define AT91SAM9_SMC_H
+#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
+#define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
+#define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
+#define                 AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
+#define         AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
+#define                 AT91_SMC_NRDSETUP_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
+#define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
+#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
+#define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
+#define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
+#define                 AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define         AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
+#define                 AT91_SMC_NRDPULSE_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
+#define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
+#define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
+#define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
+#define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
+#define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
+#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
+#define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
+#define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
+#define         AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
+#define                 AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
+#define                 AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
+#define                 AT91_SMC_EXNWMODE_READY         (3 << 4)
+#define         AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
+#define                 AT91_SMC_BAT_SELECT             (0 << 8)
+#define                 AT91_SMC_BAT_WRITE              (1 << 8)
+#define         AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
+#define                 AT91_SMC_DBW_8                  (0 << 12)
+#define                 AT91_SMC_DBW_16                 (1 << 12)
+#define                 AT91_SMC_DBW_32                 (2 << 12)
+#define         AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
+#define                 AT91_SMC_TDF_(x)                ((x) << 16)
+#define         AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
+#define         AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
+#define         AT91_SMC_PS             (3 << 28)                       /* Page Size */
+#define                 AT91_SMC_PS_4                   (0 << 28)
+#define                 AT91_SMC_PS_8                   (1 << 28)
+#define                 AT91_SMC_PS_16                  (2 << 28)
+#define                 AT91_SMC_PS_32                  (3 << 28)
+#if defined(AT91_SMC1)          /* The AT91SAM9263 has 2 Static Memory contollers */
+#define AT91_SMC1_SETUP(n)      (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define AT91_SMC1_PULSE(n)      (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC1_CYCLE(n)      (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC1_MODE(n)       (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#endif
+#endif
diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h
index 9b1864bbd9a8..186e7c715f8a 100644
--- a/include/asm-arm/arch-ep93xx/gpio.h
+++ b/include/asm-arm/arch-ep93xx/gpio.h
@@ -101,30 +101,17 @@
 /* new generic GPIO API - see Documentation/gpio.txt */
-static inline int gpio_request(unsigned gpio, const char *label)
+#include <asm-generic/gpio.h>
-{
-        if (gpio > EP93XX_GPIO_LINE_MAX)
-                return -EINVAL;
-        return 0;
-}
-static inline void gpio_free(unsigned gpio)
+#define gpio_get_value  __gpio_get_value
-{
+#define gpio_set_value  __gpio_set_value
-}
+#define gpio_cansleep   __gpio_cansleep
-int gpio_direction_input(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
-void gpio_set_value(unsigned gpio, int value);
-#include <asm-generic/gpio.h> /* cansleep wrappers */
 /*
 * Map GPIO A0..A7  (0..7)  to irq 64..71,
 *          B0..B7  (7..15) to irq 72..79, and
 *          F0..F7 (16..24) to irq 80..87.
 */
 static inline int gpio_to_irq(unsigned gpio)
 {
        if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ)
diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h
index b0364dce463f..7ad2c656e162 100644
--- a/include/asm-arm/arch-ks8695/devices.h
+++ b/include/asm-arm/arch-ks8695/devices.h
@@ -18,6 +18,11 @@ extern void __init ks8695_add_device_wan(void);
 extern void __init ks8695_add_device_lan(void);
 extern void __init ks8695_add_device_hpna(void);
+ /* LEDs */
+extern short ks8695_leds_cpu;
+extern short ks8695_leds_timer;
+extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
 /* PCI */
 #define KS8695_MODE_PCI         0
 #define KS8695_MODE_MINIPCI     1
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
index be29b83ad4ae..8590127760a8 100644
--- a/include/asm-arm/arch-mxc/board-mx31ads.h
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -11,107 +11,77 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
 #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-/*!
+/* Base address of PBC controller */
- * @name PBC Controller parameters
- */
-/*! @{ */
-/*!
- * Base address of PBC controller
- */
 #define PBC_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
 /* Offsets for the PBC Controller register */
-/*!
- * PBC Board status register offset
+/* PBC Board status register offset */
- */
 #define PBC_BSTAT               0x000002
-/*!
- * PBC Board control register 1 set address.
+/* PBC Board control register 1 set address */
- */
 #define PBC_BCTRL1_SET          0x000004
-/*!
- * PBC Board control register 1 clear address.
+/* PBC Board control register 1 clear address */
- */
 #define PBC_BCTRL1_CLEAR        0x000006
-/*!
- * PBC Board control register 2 set address.
+/* PBC Board control register 2 set address */
- */
 #define PBC_BCTRL2_SET          0x000008
-/*!
- * PBC Board control register 2 clear address.
+/* PBC Board control register 2 clear address */
- */
 #define PBC_BCTRL2_CLEAR        0x00000A
-/*!
- * PBC Board control register 3 set address.
+/* PBC Board control register 3 set address */
- */
 #define PBC_BCTRL3_SET          0x00000C
-/*!
- * PBC Board control register 3 clear address.
+/* PBC Board control register 3 clear address */
- */
 #define PBC_BCTRL3_CLEAR        0x00000E
-/*!
- * PBC Board control register 4 set address.
+/* PBC Board control register 4 set address */
- */
 #define PBC_BCTRL4_SET          0x000010
-/*!
- * PBC Board control register 4 clear address.
+/* PBC Board control register 4 clear address */
- */
 #define PBC_BCTRL4_CLEAR        0x000012
-/*!
- * PBC Board status register 1.
+/* PBC Board status register 1 */
- */
 #define PBC_BSTAT1              0x000014
-/*!
- * PBC Board interrupt status register.
+/* PBC Board interrupt status register */
- */
 #define PBC_INTSTATUS           0x000016
-/*!
- * PBC Board interrupt current status register.
+/* PBC Board interrupt current status register */
- */
 #define PBC_INTCURR_STATUS      0x000018
-/*!
- * PBC Interrupt mask register set address.
+/* PBC Interrupt mask register set address */
- */
 #define PBC_INTMASK_SET         0x00001A
-/*!
- * PBC Interrupt mask register clear address.
+/* PBC Interrupt mask register clear address */
- */
 #define PBC_INTMASK_CLEAR       0x00001C
-/*!
+/* External UART A */
- * External UART A.
- */
 #define PBC_SC16C652_UARTA      0x010000
-/*!
- * External UART B.
+/* External UART B */
- */
 #define PBC_SC16C652_UARTB      0x010010
-/*!
- * Ethernet Controller IO base address.
+/* Ethernet Controller IO base address */
- */
 #define PBC_CS8900A_IOBASE      0x020000
-/*!
- * Ethernet Controller Memory base address.
+/* Ethernet Controller Memory base address */
- */
 #define PBC_CS8900A_MEMBASE     0x021000
-/*!
- * Ethernet Controller DMA base address.
+/* Ethernet Controller DMA base address */
- */
 #define PBC_CS8900A_DMABASE     0x022000
-/*!
- * External chip select 0.
+/* External chip select 0 */
- */
 #define PBC_XCS0                0x040000
-/*!
- * LCD Display enable.
+/* LCD Display enable */
- */
 #define PBC_LCD_EN_B            0x060000
-/*!
- * Code test debug enable.
+/* Code test debug enable */
- */
 #define PBC_CODE_B              0x070000
-/*!
- * PSRAM memory select.
+/* PSRAM memory select */
- */
 #define PBC_PSRAM_B             0x5000000
 #define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
@@ -139,4 +109,4 @@
 #define MXC_MAX_EXP_IO_LINES    16
-#endif                          /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h
index 65e639d51d2b..c822d569a05e 100644
--- a/include/asm-arm/arch-mxc/dma.h
+++ b/include/asm-arm/arch-mxc/dma.h
@@ -11,11 +11,4 @@
 #ifndef __ASM_ARCH_MXC_DMA_H__
 #define __ASM_ARCH_MXC_DMA_H__
-/*!
- * @file dma.h
- * @brief This file contains Unified DMA API for all MXC platforms.
- * The API is platform independent.
- *
- * @ingroup SDMA
- */
 #endif
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
index 3c09b92fef0d..e87ff0679d5e 100644
--- a/include/asm-arm/arch-mxc/hardware.h
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -8,45 +8,24 @@
 * published by the Free Software Foundation.
 */
-/*!
- * @file hardware.h
- * @brief This file contains the hardware definitions of the board.
- *
- * @ingroup System
- */
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
 #define __ASM_ARCH_MXC_HARDWARE_H__
 #include <asm/sizes.h>
-#include <asm/arch/mx31.h>
+#ifdef CONFIG_ARCH_MX3
+# include <asm/arch/mx31.h>
+#endif
 #include <asm/arch/mxc.h>
-#define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
 /*
 * ---------------------------------------------------------------------------
 * Board specific defines
 * ---------------------------------------------------------------------------
 */
-#define MXC_EXP_IO_BASE         (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES)
+#ifdef CONFIG_MACH_MX31ADS
+# include <asm/arch/board-mx31ads.h>
-#include <asm/arch/board-mx31ads.h>
-#ifndef MXC_MAX_EXP_IO_LINES
-#define MXC_MAX_EXP_IO_LINES 0
 #endif
-#define MXC_MAX_VIRTUAL_INTS    16
+#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
-#define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
-#define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
-#define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
-#define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
-#define MXC_MAX_INTS            (MXC_MAX_INT_LINES + \
-                                MXC_MAX_GPIO_LINES + \
-                                MXC_MAX_EXP_IO_LINES + \
-                                MXC_MAX_VIRTUAL_INTS)
-#endif                          /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h
index cf6c83a4b9f7..65b6810124c1 100644
--- a/include/asm-arm/arch-mxc/io.h
+++ b/include/asm-arm/arch-mxc/io.h
@@ -8,24 +8,13 @@
 * published by the Free Software Foundation.
 */
-/*!
- * @file io.h
- * @brief This file contains some memory mapping macros.
- * @note There is no real ISA or PCI buses. But have to define these macros
- * for some drivers to compile.
- *
- * @ingroup System
- */
 #ifndef __ASM_ARCH_MXC_IO_H__
 #define __ASM_ARCH_MXC_IO_H__
-/*! Allow IO space to be anywhere in the memory */
+/* Allow IO space to be anywhere in the memory */
 #define IO_SPACE_LIMIT 0xffffffff
-/*!
+/* io address mapping macro */
- * io address mapping macro
- */
 #define __io(a)                 ((void __iomem *)(a))
 #define __mem_pci(a)            (a)
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index e4686c6bc4bf..b2c5205e1962 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,26 +13,17 @@
 #include <asm/hardware.h>
-/*!
- * @file irqs.h
- * @brief This file defines the number of normal interrupts and fast interrupts
- *
- * @ingroup Interrupt
- */
 #define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
 #define MXC_IRQ_TO_GPIO(irq)    ((irq) - MXC_GPIO_INT_BASE)
 #define MXC_GPIO_TO_IRQ(x)      (MXC_GPIO_INT_BASE + x)
-/*!
+/* Number of normal interrupts */
- * Number of normal interrupts
+#define NR_IRQS         (MXC_MAX_INT_LINES + \
- */
+                        MXC_MAX_GPIO_LINES + \
-#define NR_IRQS         MXC_MAX_INTS
+                        MXC_MAX_VIRTUAL_INTS)
-/*!
+/* Number of fast interrupts */
- * Number of fast interrupts
- */
 #define NR_FIQS         MXC_MAX_INTS
-#endif                          /* __ASM_ARCH_MXC_IRQS_H__ */
+#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
index c89aac83a407..059f83023a10 100644
--- a/include/asm-arm/arch-mxc/memory.h
+++ b/include/asm-arm/arch-mxc/memory.h
@@ -13,24 +13,17 @@
 #include <asm/hardware.h>
-/*!
+/*
- * @file memory.h
- * @brief This file contains macros needed by the Linux kernel and drivers.
- *
- * @ingroup Memory
- */
-/*!
 * Virtual view <-> DMA view memory address translations
 * This macro is used to translate the virtual address to an address
 * suitable to be passed to set_dma_addr()
 */
 #define __virt_to_bus(a)        __virt_to_phys(a)
-/*!
+/*
 * Used to convert an address for DMA operations to an address that the
 * kernel can use.
 */
 #define __bus_to_virt(a)        __phys_to_virt(a)
-#endif                          /* __ASM_ARCH_MXC_MEMORY_H__ */
+#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 85c49c9e5d15..36a1af495bb3 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -317,6 +317,8 @@
 #define MXC_MAX_INT_LINES       64
 #define MXC_GPIO_INT_BASE       MXC_MAX_INT_LINES
+#define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
+#define MXC_MAX_VIRTUAL_INTS    16
 /*!
 * Number of GPIO port as defined in the IC Spec
@@ -329,7 +331,33 @@
 #define PROD_SIGNATURE          0x1     /* For MX31 */
+/* silicon revisions specific to i.MX31 */
+#define CHIP_REV_1_0            0x10
+#define CHIP_REV_1_1            0x11
+#define CHIP_REV_1_2            0x12
+#define CHIP_REV_1_3            0x13
+#define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_1            0x21
+#define CHIP_REV_2_2            0x22
+#define CHIP_REV_2_3            0x23
+#define CHIP_REV_3_0            0x30
+#define CHIP_REV_3_1            0x31
+#define CHIP_REV_3_2            0x32
 #define SYSTEM_REV_MIN          CHIP_REV_1_0
 #define SYSTEM_REV_NUM          3
-#endif                  /*  __ASM_ARCH_MXC_MX31_H__ */
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+/* this is a i.MX31 CPU */
+#define cpu_is_mx31()           (1)
+extern unsigned int system_rev;
+static inline int mx31_revision(void)
+{
+        return system_rev;
+}
+#endif
+#endif /*  __ASM_ARCH_MXC_MX31_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 0837f1f9ca31..146d3f60951a 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -15,6 +15,11 @@
 #error "Do not include directly."
 #endif
+/* clean up all things that are not used */
+#ifndef CONFIG_ARCH_MX3
+# define cpu_is_mx31() (0)
+#endif
 /*
 *****************************************
 * GPT  Register definitions             *
@@ -31,9 +36,7 @@
 #define MXC_GPT_GPTICR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
 #define MXC_GPT_GPTCNT          IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
-/*!
+/* GPT Control register bit definitions */
- * GPT Control register bit definitions
- */
 #define GPTCR_FO3                       (1 << 31)
 #define GPTCR_FO2                       (1 << 30)
 #define GPTCR_FO1                       (1 << 29)
@@ -146,4 +149,4 @@
 #define IIM_PROD_REV_SH         3
 #define IIM_PROD_REV_LEN        5
-#endif                          /*  __ASM_ARCH_MXC_H__ */
+#endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h
index 109956b41aca..bbfc37465fc5 100644
--- a/include/asm-arm/arch-mxc/system.h
+++ b/include/asm-arm/arch-mxc/system.h
@@ -21,30 +21,14 @@
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
 #define __ASM_ARCH_MXC_SYSTEM_H__
-/*!
- * @file system.h
- * @brief This file contains idle and reset functions.
- *
- * @ingroup System
- */
-/*!
- * This function puts the CPU into idle mode. It is called by default_idle()
- * in process.c file.
- */
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-/*
- * This function resets the system. It is called by machine_restart().
- *
- * @param  mode         indicates different kinds of resets
- */
 static inline void arch_reset(char mode)
 {
        cpu_reset(0);
 }
-#endif                          /* __ASM_ARCH_MXC_SYSTEM_H__ */
+#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h
index 83a73da895eb..62d97623412f 100644
--- a/include/asm-arm/arch-mxc/vmalloc.h
+++ b/include/asm-arm/arch-mxc/vmalloc.h
@@ -20,17 +20,7 @@
 #ifndef __ASM_ARCH_MXC_VMALLOC_H__
 #define __ASM_ARCH_MXC_VMALLOC_H__
-/*!
+/* vmalloc ending address */
- * @file vmalloc.h
- *
- * @brief This file contains platform specific macros for vmalloc.
- *
- * @ingroup System
- */
-/*!
- * vmalloc ending address
- */
 #define VMALLOC_END       0xF4000000
-#endif                          /* __ASM_ARCH_MXC_VMALLOC_H__ */
+#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
diff --git a/include/asm-arm/arch-ns9xxx/board.h b/include/asm-arm/arch-ns9xxx/board.h
index 716f34fdb716..e57443bdbbd9 100644
--- a/include/asm-arm/arch-ns9xxx/board.h
+++ b/include/asm-arm/arch-ns9xxx/board.h
@@ -1,7 +1,7 @@
 /*
 * include/asm-arm/arch-ns9xxx/board.h
 *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
@@ -13,8 +13,30 @@
 #include <asm/mach-types.h>
-#define board_is_a9m9750dev()   (machine_is_cc9p9360dev())
+#define board_is_a9m9750dev()   (0                      \
+                || machine_is_cc9p9360dev()             \
+                || machine_is_cc9p9750dev()             \
+                )
-#define board_is_jscc9p9360()   (machine_is_cc9p9360js())
+#define board_is_a9mvali()      (0                      \
+                || machine_is_cc9p9360val()             \
+                || machine_is_cc9p9750val()             \
+                )
+#define board_is_jscc9p9210()   (0                      \
+                || machine_is_cc9p9210js()              \
+                )
+#define board_is_jscc9p9215()   (0                      \
+                || machine_is_cc9p9215js()              \
+                )
+#define board_is_jscc9p9360()   (0                      \
+                || machine_is_cc9p9360js()              \
+                )
+#define board_is_uncbas()       (0                      \
+                || machine_is_cc7ucamry()               \
+                )
 #endif /* ifndef __ASM_ARCH_BOARD_H */
diff --git a/include/asm-arm/arch-ns9xxx/clock.h b/include/asm-arm/arch-ns9xxx/clock.h
deleted file mode 100644
index b943d3a92a1d..000000000000
--- a/include/asm-arm/arch-ns9xxx/clock.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/clock.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-#include <asm/arch-ns9xxx/regs-sys.h>
-#define CRYSTAL 29491200 /* Hz */
-/* The HRM calls this value f_vco */
-static inline u32 ns9xxx_systemclock(void) __attribute__((const));
-static inline u32 ns9xxx_systemclock(void)
-{
-        u32 pll = __raw_readl(SYS_PLL);
-        /*
-         * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in
-         * time.c).
-         *
-         * The following values are given:
-         *   - TIMERCLOCKSELECT == 2^i for an i in {0 .. 6}
-         *   - CRYSTAL == 29491200 == 2^17 * 3^2 * 5^2
-         *   - ND in {0 .. 31}
-         *   - FS in {0 .. 3}
-         *
-         * Assuming the worst, we consider:
-         *   - TIMERCLOCKSELECT == 64
-         *   - ND == 0
-         *   - FS == 3
-         *
-         * So HZ should be a divisor of:
-         *      (CRYSTAL * (ND + 1) >> FS) / TIMERCLOCKSELECT
-         *   == (2^17 * 3^2 * 5^2 * 1 >> 3) / 64
-         *   == 2^8 * 3^2 * 5^2
-         *   == 57600
-         *
-         * Currently HZ is defined to be 100 for this platform.
-         *
-         * Fine.
-         */
-        return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
-                >> REGGETIM(pll, SYS_PLL, FS);
-}
-static inline u32 ns9xxx_cpuclock(void) __attribute__((const));
-static inline u32 ns9xxx_cpuclock(void)
-{
-        return ns9xxx_systemclock() / 2;
-}
-static inline u32 ns9xxx_ahbclock(void) __attribute__((const));
-static inline u32 ns9xxx_ahbclock(void)
-{
-        return ns9xxx_systemclock() / 4;
-}
-static inline u32 ns9xxx_bbusclock(void) __attribute__((const));
-static inline u32 ns9xxx_bbusclock(void)
-{
-        return ns9xxx_systemclock() / 8;
-}
-#endif /* ifndef __ASM_ARCH_CLOCK_H */
diff --git a/include/asm-arm/arch-ns9xxx/entry-macro.S b/include/asm-arm/arch-ns9xxx/entry-macro.S
index 86aec87303e4..89a21c530468 100644
--- a/include/asm-arm/arch-ns9xxx/entry-macro.S
+++ b/include/asm-arm/arch-ns9xxx/entry-macro.S
@@ -1,7 +1,7 @@
 /*
 * include/asm-arm/arch-ns9xxx/entry-macro.S
 *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
@@ -9,16 +9,16 @@
 * the Free Software Foundation.
 */
 #include <asm/hardware.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/regs-sys-common.h>
                .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =SYS_ISRADDR
                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =SYS_ISRADDR
                ldr     \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)]
                cmp     \irqstat, #0
                ldrne   \irqnr, [\base]
diff --git a/include/asm-arm/arch-ns9xxx/irqs.h b/include/asm-arm/arch-ns9xxx/irqs.h
index 25d8d28b27f3..e83d48ec42c9 100644
--- a/include/asm-arm/arch-ns9xxx/irqs.h
+++ b/include/asm-arm/arch-ns9xxx/irqs.h
@@ -1,7 +1,7 @@
 /*
 * include/asm-arm/arch-ns9xxx/irqs.h
 *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
@@ -11,38 +11,39 @@
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
-#define IRQ_WATCHDOG    0
+/* NetSilicon 9360 */
-#define IRQ_AHBBUSERR   1
+#define IRQ_NS9XXX_WATCHDOG     0
-#define IRQ_BBUSAGG     2
+#define IRQ_NS9XXX_AHBBUSERR    1
+#define IRQ_NS9360_BBUSAGG      2
 /* irq 3 is reserved for NS9360 */
-#define IRQ_ETHRX       4
+#define IRQ_NS9XXX_ETHRX        4
-#define IRQ_ETHTX       5
+#define IRQ_NS9XXX_ETHTX        5
-#define IRQ_ETHPHY      6
+#define IRQ_NS9XXX_ETHPHY       6
-#define IRQ_LCD         7
+#define IRQ_NS9360_LCD          7
-#define IRQ_SERBRX      8
+#define IRQ_NS9360_SERBRX       8
-#define IRQ_SERBTX      9
+#define IRQ_NS9360_SERBTX       9
-#define IRQ_SERARX      10
+#define IRQ_NS9360_SERARX       10
-#define IRQ_SERATX      11
+#define IRQ_NS9360_SERATX       11
-#define IRQ_SERCRX      12
+#define IRQ_NS9360_SERCRX       12
-#define IRQ_SERCTX      13
+#define IRQ_NS9360_SERCTX       13
-#define IRQ_I2C         14
+#define IRQ_NS9360_I2C          14
-#define IRQ_BBUSDMA     15
+#define IRQ_NS9360_BBUSDMA      15
-#define IRQ_TIMER0      16
+#define IRQ_NS9360_TIMER0       16
-#define IRQ_TIMER1      17
+#define IRQ_NS9360_TIMER1       17
-#define IRQ_TIMER2      18
+#define IRQ_NS9360_TIMER2       18
-#define IRQ_TIMER3      19
+#define IRQ_NS9360_TIMER3       19
-#define IRQ_TIMER4      20
+#define IRQ_NS9360_TIMER4       20
-#define IRQ_TIMER5      21
+#define IRQ_NS9360_TIMER5       21
-#define IRQ_TIMER6      22
+#define IRQ_NS9360_TIMER6       22
-#define IRQ_TIMER7      23
+#define IRQ_NS9360_TIMER7       23
-#define IRQ_RTC         24
+#define IRQ_NS9360_RTC          24
-#define IRQ_USBHOST     25
+#define IRQ_NS9360_USBHOST      25
-#define IRQ_USBDEVICE   26
+#define IRQ_NS9360_USBDEVICE    26
-#define IRQ_IEEE1284    27
+#define IRQ_NS9360_IEEE1284     27
-#define IRQ_EXT0        28
+#define IRQ_NS9XXX_EXT0         28
-#define IRQ_EXT1        29
+#define IRQ_NS9XXX_EXT1         29
-#define IRQ_EXT2        30
+#define IRQ_NS9XXX_EXT2         30
-#define IRQ_EXT3        31
+#define IRQ_NS9XXX_EXT3         31
 #define BBUS_IRQ(irq)   (32 + irq)
@@ -67,7 +68,7 @@
 /*
 * these Interrupts are specific for the a9m9750dev board.
 * They are generated by an FPGA that interrupts the CPU on
- * IRQ_EXT2
+ * IRQ_NS9360_EXT2
 */
 #define FPGA_IRQ(irq)   (64 + irq)
diff --git a/include/asm-arm/arch-ns9xxx/module.h b/include/asm-arm/arch-ns9xxx/module.h
new file mode 100644
index 000000000000..ac08a31111e4
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/module.h
@@ -0,0 +1,60 @@
+/*
+ * include/asm-arm/arch-ns9xxx/module.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MODULE_H
+#define __ASM_ARCH_MODULE_H
+#include <asm/mach-types.h>
+#define module_is_cc7ucamry()   (0                      \
+                || machine_is_cc7ucamry()               \
+                )
+#define module_is_cc9c()        (0                      \
+                || machine_is_cc9c()                    \
+                )
+#define module_is_cc9p9210()    (0                      \
+                || machine_is_cc9p9210()                \
+                || machine_is_cc9p9210js()              \
+                )
+#define module_is_cc9p9215()    (0                      \
+                || machine_is_cc9p9215()                \
+                || machine_is_cc9p9215js()              \
+                )
+#define module_is_cc9p9360()    (0                      \
+                || machine_is_a9m9360()                 \
+                || machine_is_cc9p9360dev()             \
+                || machine_is_cc9p9360js()              \
+                || machine_is_cc9p9360val()             \
+                )
+#define module_is_cc9p9750()    (0                      \
+                || machine_is_a9m9750()                 \
+                || machine_is_cc9p9750dev()             \
+                || machine_is_cc9p9750js()              \
+                || machine_is_cc9p9750val()             \
+                )
+#define module_is_ccw9c()       (0                      \
+                || machine_is_ccw9c()                   \
+                )
+#define module_is_inc20otter()  (0                      \
+                || machine_is_inc20otter()              \
+                )
+#define module_is_otter()       (0                      \
+                || machine_is_otter()                   \
+                )
+#endif /* ifndef __ASM_ARCH_MODULE_H */
diff --git a/include/asm-arm/arch-ns9xxx/processor-ns9360.h b/include/asm-arm/arch-ns9xxx/processor-ns9360.h
new file mode 100644
index 000000000000..f3aa6c50dbe5
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/processor-ns9360.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-arm/arch-ns9xxx/processor-ns9360.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_PROCESSORNS9360_H
+#define __ASM_ARCH_PROCESSORNS9360_H
+#include <linux/init.h>
+void ns9360_reset(char mode);
+unsigned long ns9360_systemclock(void) __attribute__((const));
+static inline unsigned long ns9360_cpuclock(void) __attribute__((const));
+static inline unsigned long ns9360_cpuclock(void)
+{
+        return ns9360_systemclock() / 2;
+}
+void __init ns9360_map_io(void);
+extern struct sys_timer ns9360_timer;
+int ns9360_gpio_configure(unsigned gpio, int inv, int func);
+#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */
diff --git a/include/asm-arm/arch-ns9xxx/processor.h b/include/asm-arm/arch-ns9xxx/processor.h
index 223e51b8e104..f7b53b65de81 100644
--- a/include/asm-arm/arch-ns9xxx/processor.h
+++ b/include/asm-arm/arch-ns9xxx/processor.h
@@ -1,7 +1,7 @@
 /*
 * include/asm-arm/arch-ns9xxx/processor.h
 *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
@@ -11,9 +11,32 @@
 #ifndef __ASM_ARCH_PROCESSOR_H
 #define __ASM_ARCH_PROCESSOR_H
-#include <asm/mach-types.h>
+#include <asm/arch-ns9xxx/module.h>
-#define processor_is_ns9360()   (machine_is_cc9p9360dev()               \
+#define processor_is_ns9210()   (0                      \
-                || machine_is_cc9p9360js())
+                || module_is_cc7ucamry()                \
+                || module_is_cc9p9210()                 \
+                || module_is_inc20otter()               \
+                || module_is_otter()                    \
+                )
+#define processor_is_ns9215()   (0                      \
+                || module_is_cc9p9215()                 \
+                )
+#define processor_is_ns9360()   (0                      \
+                || module_is_cc9p9360()                 \
+                || module_is_cc9c()                     \
+                || module_is_ccw9c()                    \
+                )
+#define processor_is_ns9750()   (0                      \
+                || module_is_cc9p9750()                 \
+                )
+#define processor_is_ns921x()   (0                      \
+                || processor_is_ns9210()                \
+                || processor_is_ns9215()                \
+                )
 #endif /* ifndef __ASM_ARCH_PROCESSOR_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys-common.h b/include/asm-arm/arch-ns9xxx/regs-sys-common.h
new file mode 100644
index 000000000000..956c57cb781f
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/regs-sys-common.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-ns9xxx/regs-sys-common.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_REGSSYSCOMMON_H
+#define __ASM_ARCH_REGSSYSCOMMON_H
+#include <asm/hardware.h>
+/* Interrupt Vector Address Register Level x */
+#define SYS_IVA(x)      __REG2(0xa09000c4, (x))
+/* Interrupt Configuration registers */
+#define SYS_IC(x)       __REG2(0xa0900144, (x))
+/* ISRADDR */
+#define SYS_ISRADDR     __REG(0xa0900164)
+/* Interrupt Status Active */
+#define SYS_ISA         __REG(0xa0900168)
+/* Interrupt Status Raw */
+#define SYS_ISR         __REG(0xa090016c)
+#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h
index 749262f86204..318b6945afb6 100644
--- a/include/asm-arm/arch-ns9xxx/regs-sys.h
+++ b/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h
@@ -1,15 +1,15 @@
 /*
- * include/asm-arm/arch-ns9xxx/regs-sys.h
+ * include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h
 *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */
-#ifndef __ASM_ARCH_REGSSYS_H
+#ifndef __ASM_ARCH_REGSSYSNS9360_H
-#define __ASM_ARCH_REGSSYS_H
+#define __ASM_ARCH_REGSSYSNS9360_H
 #include <asm/hardware.h>
@@ -27,21 +27,6 @@
 /* Timer x Read register */
 #define SYS_TR(x)       __REG2(0xa0900084, (x))
-/* Interrupt Vector Address Register Level x */
-#define SYS_IVA(x)      __REG2(0xa09000c4, (x))
-/* Interrupt Configuration registers */
-#define SYS_IC(x)       __REG2(0xa0900144, (x))
-/* ISRADDR */
-#define SYS_ISRADDR     __REG(0xa0900164)
-/* Interrupt Status Active */
-#define SYS_ISA         __REG(0xa0900168)
-/* Interrupt Status Raw */
-#define SYS_ISR         __REG(0xa090016c)
 /* Timer Interrupt Status register */
 #define SYS_TIS         __REG(0xa0900170)
@@ -160,4 +145,4 @@
 #define SYS_EIC_LVEDG_LEVEL             __REGVAL(SYS_EIC_LVEDG, 0)
 #define SYS_EIC_LVEDG_EDGE              __REGVAL(SYS_EIC_LVEDG, 1)
-#endif /* ifndef __ASM_ARCH_REGSSYS_H */
+#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */
diff --git a/include/asm-arm/arch-ns9xxx/system.h b/include/asm-arm/arch-ns9xxx/system.h
index c1082bd8977c..1348073afe48 100644
--- a/include/asm-arm/arch-ns9xxx/system.h
+++ b/include/asm-arm/arch-ns9xxx/system.h
@@ -1,7 +1,7 @@
 /*
 * include/asm-arm/arch-ns9xxx/system.h
 *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
@@ -12,8 +12,8 @@
 #define __ASM_ARCH_SYSTEM_H
 #include <asm/proc-fns.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/processor.h>
-#include <asm/mach-types.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
 static inline void arch_idle(void)
 {
@@ -22,11 +22,12 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode)
 {
-        u32 reg;
+#ifdef CONFIG_PROCESSOR_NS9360
+        if (processor_is_ns9360())
-        reg = __raw_readl(SYS_PLL) >> 16;
+                ns9360_reset(mode);
-        REGSET(reg, SYS_PLL, SWC, YES);
+        else
-        __raw_writel(reg, SYS_PLL);
+#endif
+                BUG();
        BUG();
 }
diff --git a/include/asm-arm/arch-ns9xxx/uncompress.h b/include/asm-arm/arch-ns9xxx/uncompress.h
index 961ca7dc9954..71066baceab7 100644
--- a/include/asm-arm/arch-ns9xxx/uncompress.h
+++ b/include/asm-arm/arch-ns9xxx/uncompress.h
@@ -11,20 +11,149 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H
-static void putc(char c)
+#include <asm/io.h>
+#define __REG(x)        ((void __iomem __force *)(x))
+static void putc_dummy(char c, void __iomem *base)
 {
-        volatile u8 *base = (volatile u8 *)0x40000000;
+        /* nothing */
-        int t = 0x10000;
+}
+static void putc_ns9360(char c, void __iomem *base)
+{
+        static int t = 0x10000;
+        do {
+                if (t)
+                        --t;
+                if (__raw_readl(base + 8) & (1 << 3)) {
+                        __raw_writeb(c, base + 16);
+                        t = 0x10000;
+                        break;
+                }
+        } while (t);
+}
+static void putc_a9m9750dev(char c, void __iomem *base)
+{
+        static int t = 0x10000;
+        do {
+                if (t)
+                        --t;
+                if (__raw_readb(base + 5) & (1 << 5)) {
+                        __raw_writeb(c, base);
+                        t = 0x10000;
+                        break;
+                }
+        } while (t);
+}
+static void putc_ns921x(char c, void __iomem *base)
+{
+        static int t = 0x10000;
        do {
-                if (base[5] & 0x20) {
+                if (t)
-                        base[0] = c;
+                        --t;
+                if (!(__raw_readl(base) & (1 << 11))) {
+                        __raw_writeb(c, base + 0x0028);
+                        t = 0x10000;
                        break;
                }
-        } while (--t);
+        } while (t);
 }
-#define arch_decomp_setup()
+#define MSCS __REG(0xA0900184)
+#define NS9360_UARTA    __REG(0x90200040)
+#define NS9360_UARTB    __REG(0x90200000)
+#define NS9360_UARTC    __REG(0x90300000)
+#define NS9360_UARTD    __REG(0x90300040)
+#define NS9360_UART_ENABLED(base)                                       \
+                (__raw_readl(NS9360_UARTA) & (1 << 31))
+#define A9M9750DEV_UARTA        __REG(0x40000000)
+#define NS921XSYS_CLOCK __REG(0xa090017c)
+#define NS921X_UARTA    __REG(0x90010000)
+#define NS921X_UARTB    __REG(0x90018000)
+#define NS921X_UARTC    __REG(0x90020000)
+#define NS921X_UARTD    __REG(0x90028000)
+#define NS921X_UART_ENABLED(base)                                       \
+                (__raw_readl((base) + 0x1000) & (1 << 29))
+static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
+{
+        if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
+                /* ns9360 or ns9750 */
+                if (NS9360_UART_ENABLED(NS9360_UARTA)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTA;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTB)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTB;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTC)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTC;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTD)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTD;
+                        return;
+                } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) {
+                        *putc = putc_a9m9750dev;
+                        *base = A9M9750DEV_UARTA;
+                        return;
+                }
+        } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) {
+                /* ns921x */
+                u32 clock = __raw_readl(NS921XSYS_CLOCK);
+                if ((clock & (1 << 1)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTA)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTA;
+                        return;
+                } else if ((clock & (1 << 2)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTB)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTB;
+                        return;
+                } else if ((clock & (1 << 3)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTC)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTC;
+                        return;
+                } else if ((clock & (1 << 4)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTD)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTD;
+                        return;
+                }
+        }
+        *putc = putc_dummy;
+}
+void (*myputc)(char, void __iomem *);
+void __iomem *base;
+static void putc(char c)
+{
+        myputc(c, base);
+}
+static void arch_decomp_setup(void)
+{
+        autodetect(&myputc, &base);
+}
 #define arch_decomp_wdog()
 static void flush(void)
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h
index 2b1a8a4fe44e..94926090e475 100644
--- a/include/asm-arm/arch-omap/board-osk.h
+++ b/include/asm-arm/arch-omap/board-osk.h
@@ -32,5 +32,16 @@
 /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
 #define OMAP_OSK_ETHR_START             0x04800300
+/* TPS65010 has four GPIOs.  nPG and LED2 can be treated like GPIOs with
+ * alternate pin configurations for hardware-controlled blinking.
+ */
+#define OSK_TPS_GPIO_BASE               (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
+#       define OSK_TPS_GPIO_USB_PWR_EN  (OSK_TPS_GPIO_BASE + 0)
+#       define OSK_TPS_GPIO_LED_D3      (OSK_TPS_GPIO_BASE + 1)
+#       define OSK_TPS_GPIO_LAN_RESET   (OSK_TPS_GPIO_BASE + 2)
+#       define OSK_TPS_GPIO_DSP_PWR_EN  (OSK_TPS_GPIO_BASE + 3)
+#       define OSK_TPS_GPIO_LED_D9      (OSK_TPS_GPIO_BASE + 4)
+#       define OSK_TPS_GPIO_LED_D2      (OSK_TPS_GPIO_BASE + 5)
 #endif /*  __ASM_ARCH_OMAP_OSK_H */
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index fa6881049903..57523bdb642b 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -14,6 +14,35 @@
 #define __ARCH_ARM_OMAP_CLOCK_H
 struct module;
+struct clk;
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+struct clksel_rate {
+        u8                      div;
+        u32                     val;
+        u8                      flags;
+};
+struct clksel {
+        struct clk               *parent;
+        const struct clksel_rate *rates;
+};
+struct dpll_data {
+        void __iomem            *mult_div1_reg;
+        u32                     mult_mask;
+        u32                     div1_mask;
+#  if defined(CONFIG_ARCH_OMAP3)
+        void __iomem            *control_reg;
+        u32                     enable_mask;
+        u8                      auto_recal_bit;
+        u8                      recal_en_bit;
+        u8                      recal_st_bit;
+#  endif
+};
+#endif
 struct clk {
        struct list_head        node;
@@ -25,8 +54,6 @@ struct clk {
        __u32                   flags;
        void __iomem            *enable_reg;
        __u8                    enable_bit;
-        __u8                    rate_offset;
-        __u8                    src_offset;
        __s8                    usecount;
        void                    (*recalc)(struct clk *);
        int                     (*set_rate)(struct clk *, unsigned long);
@@ -34,6 +61,16 @@ struct clk {
        void                    (*init)(struct clk *);
        int                     (*enable)(struct clk *);
        void                    (*disable)(struct clk *);
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+        u8                      fixed_div;
+        void __iomem            *clksel_reg;
+        u32                     clksel_mask;
+        const struct clksel     *clksel;
+        const struct dpll_data  *dpll_data;
+#else
+        __u8                    rate_offset;
+        __u8                    src_offset;
+#endif
 };
 struct clk_functions {
@@ -54,10 +91,12 @@ extern int clk_init(struct clk_functions * custom_clocks);
 extern int clk_register(struct clk *clk);
 extern void clk_unregister(struct clk *clk);
 extern void propagate_rate(struct clk *clk);
+extern void recalculate_root_clocks(void);
 extern void followparent_recalc(struct clk * clk);
 extern void clk_allow_idle(struct clk *clk);
 extern void clk_deny_idle(struct clk *clk);
 extern int clk_get_usecount(struct clk *clk);
+extern void clk_enable_init_clocks(void);
 /* Clock flags */
 #define RATE_CKCTL              (1 << 0)        /* Main fixed ratio clocks */
@@ -71,21 +110,33 @@ extern int clk_get_usecount(struct clk *clk);
 #define CLOCK_NO_IDLE_PARENT    (1 << 8)
 #define DELAYED_APP             (1 << 9)        /* Delay application of clock */
 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
-#define CM_MPU_SEL1             (1 << 11)       /* Domain divider/source */
+#define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
-#define CM_DSP_SEL1             (1 << 12)
+#define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
-#define CM_GFX_SEL1             (1 << 13)
+/* bits 13-20 are currently free */
-#define CM_MODEM_SEL1           (1 << 14)
-#define CM_CORE_SEL1            (1 << 15)       /* Sets divider for many */
-#define CM_CORE_SEL2            (1 << 16)       /* sets parent for GPT */
-#define CM_WKUP_SEL1            (1 << 17)
-#define CM_PLL_SEL1             (1 << 18)
-#define CM_PLL_SEL2             (1 << 19)
-#define CM_SYSCLKOUT_SEL1       (1 << 20)
 #define CLOCK_IN_OMAP310        (1 << 21)
 #define CLOCK_IN_OMAP730        (1 << 22)
 #define CLOCK_IN_OMAP1510       (1 << 23)
 #define CLOCK_IN_OMAP16XX       (1 << 24)
 #define CLOCK_IN_OMAP242X       (1 << 25)
 #define CLOCK_IN_OMAP243X       (1 << 26)
+#define CLOCK_IN_OMAP343X       (1 << 27)       /* clocks common to all 343X */
+#define PARENT_CONTROLS_CLOCK   (1 << 28)
+#define CLOCK_IN_OMAP3430ES1    (1 << 29)       /* 3430ES1 clocks only */
+#define CLOCK_IN_OMAP3430ES2    (1 << 30)       /* 3430ES2 clocks only */
+/* Clksel_rate flags */
+#define DEFAULT_RATE            (1 << 0)
+#define RATE_IN_242X            (1 << 1)
+#define RATE_IN_243X            (1 << 2)
+#define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
+#define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
+#define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
+/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
+#define CORE_CLK_SRC_32K                0
+#define CORE_CLK_SRC_DPLL               1
+#define CORE_CLK_SRC_DPLL_X2            2
 #endif
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
new file mode 100644
index 000000000000..9944bb5d5330
--- /dev/null
+++ b/include/asm-arm/arch-omap/control.h
@@ -0,0 +1,191 @@
+#ifndef __ASM_ARCH_CONTROL_H
+#define __ASM_ARCH_CONTROL_H
+/*
+ * include/asm-arm/arch-omap/control.h
+ *
+ * OMAP2/3 System Control Module definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ */
+#include <asm/arch/io.h>
+#define OMAP242X_CTRL_REGADDR(reg)                                      \
+        (void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg)                                      \
+        (void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg)                                      \
+        (void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+/*
+ * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
+ * OMAP24XX and OMAP34XX.
+ */
+/* Control submodule offsets */
+#define OMAP2_CONTROL_INTERFACE         0x000
+#define OMAP2_CONTROL_PADCONFS          0x030
+#define OMAP2_CONTROL_GENERAL           0x270
+#define OMAP343X_CONTROL_MEM_WKUP       0x600
+#define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
+#define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
+/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
+#define OMAP2_CONTROL_SYSCONFIG         (OMAP2_CONTROL_INTERFACE + 0x10)
+/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
+#define OMAP2_CONTROL_DEVCONF0          (OMAP2_CONTROL_GENERAL + 0x0004)
+#define OMAP2_CONTROL_MSUSPENDMUX_0     (OMAP2_CONTROL_GENERAL + 0x0020)
+#define OMAP2_CONTROL_MSUSPENDMUX_1     (OMAP2_CONTROL_GENERAL + 0x0024)
+#define OMAP2_CONTROL_MSUSPENDMUX_2     (OMAP2_CONTROL_GENERAL + 0x0028)
+#define OMAP2_CONTROL_MSUSPENDMUX_3     (OMAP2_CONTROL_GENERAL + 0x002c)
+#define OMAP2_CONTROL_MSUSPENDMUX_4     (OMAP2_CONTROL_GENERAL + 0x0030)
+#define OMAP2_CONTROL_MSUSPENDMUX_5     (OMAP2_CONTROL_GENERAL + 0x0034)
+#define OMAP2_CONTROL_SEC_CTRL          (OMAP2_CONTROL_GENERAL + 0x0040)
+#define OMAP2_CONTROL_RPUB_KEY_H_0      (OMAP2_CONTROL_GENERAL + 0x0090)
+#define OMAP2_CONTROL_RPUB_KEY_H_1      (OMAP2_CONTROL_GENERAL + 0x0094)
+#define OMAP2_CONTROL_RPUB_KEY_H_2      (OMAP2_CONTROL_GENERAL + 0x0098)
+#define OMAP2_CONTROL_RPUB_KEY_H_3      (OMAP2_CONTROL_GENERAL + 0x009c)
+/* 242x-only CONTROL_GENERAL register offsets */
+#define OMAP242X_CONTROL_DEVCONF        OMAP2_CONTROL_DEVCONF0 /* match TRM */
+#define OMAP242X_CONTROL_OCM_RAM_PERM   (OMAP2_CONTROL_GENERAL + 0x0068)
+/* 243x-only CONTROL_GENERAL register offsets */
+/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
+#define OMAP243X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP243X_CONTROL_CSIRXFE        (OMAP2_CONTROL_GENERAL + 0x007c)
+#define OMAP243X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP243X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
+#define OMAP243X_CONTROL_IVA2_GEMCFG    (OMAP2_CONTROL_GENERAL + 0x0198)
+/* 24xx-only CONTROL_GENERAL register offsets */
+#define OMAP24XX_CONTROL_DEBOBS         (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP24XX_CONTROL_EMU_SUPPORT    (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP24XX_CONTROL_SEC_TEST       (OMAP2_CONTROL_GENERAL + 0x0044)
+#define OMAP24XX_CONTROL_PSA_CTRL       (OMAP2_CONTROL_GENERAL + 0x0048)
+#define OMAP24XX_CONTROL_PSA_CMD        (OMAP2_CONTROL_GENERAL + 0x004c)
+#define OMAP24XX_CONTROL_PSA_VALUE      (OMAP2_CONTROL_GENERAL + 0x0050)
+#define OMAP24XX_CONTROL_SEC_EMU        (OMAP2_CONTROL_GENERAL + 0x0060)
+#define OMAP24XX_CONTROL_SEC_TAP        (OMAP2_CONTROL_GENERAL + 0x0064)
+#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD        (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD  (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD   (OMAP2_CONTROL_GENERAL + 0x0074
+#define OMAP24XX_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP24XX_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP24XX_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0088)
+#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
+#define OMAP24XX_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP24XX_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00a4)
+#define OMAP24XX_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP24XX_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP24XX_CONTROL_CUST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP24XX_CONTROL_CUST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP24XX_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c0)
+#define OMAP24XX_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00c4)
+#define OMAP24XX_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP24XX_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP24XX_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP24XX_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP24XX_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP24XX_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP24XX_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP24XX_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00e4)
+/* 34xx-only CONTROL_GENERAL register offsets */
+#define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP343X_CONTROL_MEM_DFTRW0     (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP343X_CONTROL_MEM_DFTRW1     (OMAP2_CONTROL_GENERAL + 0x000c)
+#define OMAP343X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0068)
+#define OMAP343X_CONTROL_CSIRXFE                (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP343X_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0074)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG   (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP343X_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP343X_CONTROL_RPUB_KEY_H_4   (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP343X_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP343X_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP343X_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP343X_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP343X_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP343X_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP343X_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP343X_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP343X_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP343X_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP343X_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP343X_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00e4)
+#define OMAP343X_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e8)
+#define OMAP343X_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00ec)
+#define OMAP343X_CONTROL_TEST_KEY_10    (OMAP2_CONTROL_GENERAL + 0x00f0)
+#define OMAP343X_CONTROL_TEST_KEY_11    (OMAP2_CONTROL_GENERAL + 0x00f4)
+#define OMAP343X_CONTROL_TEST_KEY_12    (OMAP2_CONTROL_GENERAL + 0x00f8)
+#define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
+#define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
+/*
+ * REVISIT: This list of registers is not comprehensive - there are more
+ * that should be added.
+ */
+/*
+ * Control module register bit defines - these should eventually go into
+ * their own regbits file.  Some of these will be complicated, depending
+ * on the device type (general-purpose, emulator, test, secure, bad, other)
+ * and the security mode (secure, non-secure, don't care)
+ */
+/* CONTROL_DEVCONF0 bits */
+#define OMAP24XX_USBSTANDBYCTRL         (1 << 15)
+#define OMAP2_MCBSP2_CLKS_MASK          (1 << 6)
+#define OMAP2_MCBSP1_CLKS_MASK          (1 << 2)
+/* CONTROL_DEVCONF1 bits */
+#define OMAP2_MCBSP5_CLKS_MASK          (1 << 4) /* > 242x */
+#define OMAP2_MCBSP4_CLKS_MASK          (1 << 2) /* > 242x */
+#define OMAP2_MCBSP3_CLKS_MASK          (1 << 0) /* > 242x */
+/* CONTROL_STATUS bits */
+#define OMAP2_DEVICETYPE_MASK           (0x7 << 8)
+#define OMAP2_SYSBOOT_5_MASK            (1 << 5)
+#define OMAP2_SYSBOOT_4_MASK            (1 << 4)
+#define OMAP2_SYSBOOT_3_MASK            (1 << 3)
+#define OMAP2_SYSBOOT_2_MASK            (1 << 2)
+#define OMAP2_SYSBOOT_1_MASK            (1 << 1)
+#define OMAP2_SYSBOOT_0_MASK            (1 << 0)
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+extern void omap_ctrl_base_set(u32 base);
+extern u32 omap_ctrl_base_get(void);
+extern u8 omap_ctrl_readb(u16 offset);
+extern u16 omap_ctrl_readw(u16 offset);
+extern u32 omap_ctrl_readl(u16 offset);
+extern void omap_ctrl_writeb(u8 val, u16 offset);
+extern void omap_ctrl_writew(u16 val, u16 offset);
+extern void omap_ctrl_writel(u32 val, u16 offset);
+#else
+#define omap_ctrl_base_set(x)           WARN_ON(1)
+#define omap_ctrl_base_get()            0
+#define omap_ctrl_readb(x)              0
+#define omap_ctrl_readw(x)              0
+#define omap_ctrl_readl(x)              0
+#define omap_ctrl_writeb(x, y)          WARN_ON(1)
+#define omap_ctrl_writew(x, y)          WARN_ON(1)
+#define omap_ctrl_writel(x, y)          WARN_ON(1)
+#endif
+#endif  /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_CONTROL_H */
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
index f6967c8df323..74cd57221c8e 100644
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -68,7 +68,7 @@
                .endm
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =VA_IC_BASE
+                ldr     \base, =OMAP2_VA_IC_BASE
                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
                cmp     \irqnr, #0x0
                bne     2222f
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
index 164da09be095..86621a04cd8f 100644
--- a/include/asm-arm/arch-omap/gpio.h
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -82,62 +82,35 @@ extern void omap_set_gpio_debounce_time(int gpio, int enable);
 /*-------------------------------------------------------------------------*/
-/* wrappers for "new style" GPIO calls. the old OMAP-specfic ones should
+/* Wrappers for "new style" GPIO calls, using the new infrastructure
- * eventually be removed (along with this errno.h inclusion), and maybe
+ * which lets us plug in FPGA, I2C, and other implementations.
- * gpios should put MPUIOs last too.
+ * *
+ * The original OMAP-specfic calls should eventually be removed.
 */
-#include <asm/errno.h>
+#include <linux/errno.h>
+#include <asm-generic/gpio.h>
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        return omap_request_gpio(gpio);
-}
-static inline void gpio_free(unsigned gpio)
-{
-        omap_free_gpio(gpio);
-}
-static inline int __gpio_set_direction(unsigned gpio, int is_input)
-{
-        if (cpu_class_is_omap2()) {
-                if (gpio > OMAP_MAX_GPIO_LINES)
-                        return -EINVAL;
-        } else {
-                if (gpio > (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */))
-                        return -EINVAL;
-        }
-        omap_set_gpio_direction(gpio, is_input);
-        return 0;
-}
-static inline int gpio_direction_input(unsigned gpio)
-{
-        return __gpio_set_direction(gpio, 1);
-}
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-        omap_set_gpio_dataout(gpio, value);
-        return __gpio_set_direction(gpio, 0);
-}
 static inline int gpio_get_value(unsigned gpio)
 {
-        return omap_get_gpio_datain(gpio);
+        return __gpio_get_value(gpio);
 }
 static inline void gpio_set_value(unsigned gpio, int value)
 {
-        omap_set_gpio_dataout(gpio, value);
+        __gpio_set_value(gpio, value);
 }
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
+static inline int gpio_cansleep(unsigned gpio)
+{
+        return __gpio_cansleep(gpio);
+}
 static inline int gpio_to_irq(unsigned gpio)
 {
-        return OMAP_GPIO_IRQ(gpio);
+        if (gpio < (OMAP_MAX_GPIO_LINES + 16))
+                return OMAP_GPIO_IRQ(gpio);
+        return -EINVAL;
 }
 static inline int irq_to_gpio(unsigned irq)
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 289082d07f14..160578e1f557 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -80,6 +80,13 @@
 #define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE      /* 0x49000000 */
 #define OMAP243X_GPMC_VIRT      0xFE000000
 #define OMAP243X_GPMC_SIZE      SZ_1M
+#define OMAP243X_SDRC_PHYS      OMAP243X_SDRC_BASE
+#define OMAP243X_SDRC_VIRT      0xFD000000
+#define OMAP243X_SDRC_SIZE      SZ_1M
+#define OMAP243X_SMS_PHYS       OMAP243X_SMS_BASE
+#define OMAP243X_SMS_VIRT       0xFC000000
+#define OMAP243X_SMS_SIZE       SZ_1M
 #endif
 #define IO_OFFSET       0x90000000
@@ -88,16 +95,73 @@
 #define io_v2p(va)      ((va) - IO_OFFSET)      /* Works for L3 and L4 */
 /* DSP */
-#define DSP_MEM_24XX_PHYS       OMAP24XX_DSP_MEM_BASE   /* 0x58000000 */
+#define DSP_MEM_24XX_PHYS       OMAP2420_DSP_MEM_BASE   /* 0x58000000 */
 #define DSP_MEM_24XX_VIRT       0xe0000000
 #define DSP_MEM_24XX_SIZE       0x28000
-#define DSP_IPI_24XX_PHYS       OMAP24XX_DSP_IPI_BASE   /* 0x59000000 */
+#define DSP_IPI_24XX_PHYS       OMAP2420_DSP_IPI_BASE   /* 0x59000000 */
 #define DSP_IPI_24XX_VIRT       0xe1000000
 #define DSP_IPI_24XX_SIZE       SZ_4K
-#define DSP_MMU_24XX_PHYS       OMAP24XX_DSP_MMU_BASE   /* 0x5a000000 */
+#define DSP_MMU_24XX_PHYS       OMAP2420_DSP_MMU_BASE   /* 0x5a000000 */
 #define DSP_MMU_24XX_VIRT       0xe2000000
 #define DSP_MMU_24XX_SIZE       SZ_4K
+#elif defined(CONFIG_ARCH_OMAP3)
+/* We map both L3 and L4 on OMAP3 */
+#define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 */
+#define L3_34XX_VIRT            0xf8000000
+#define L3_34XX_SIZE            SZ_1M   /* 44kB of 128MB used, want 1MB sect */
+#define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 */
+#define L4_34XX_VIRT            0xd8000000
+#define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
+/*
+ * Need to look at the Size 4M for L4.
+ * VPOM3430 was not working for Int controller
+ */
+#define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 */
+#define L4_WK_34XX_VIRT         0xd8300000
+#define L4_WK_34XX_SIZE         SZ_1M
+#define L4_PER_34XX_PHYS        L4_PER_34XX_BASE /* 0x49000000 */
+#define L4_PER_34XX_VIRT        0xd9000000
+#define L4_PER_34XX_SIZE        SZ_1M
+#define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE /* 0x54000000 */
+#define L4_EMU_34XX_VIRT        0xe4000000
+#define L4_EMU_34XX_SIZE        SZ_64M
+#define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE /* 0x6E000000 */
+#define OMAP34XX_GPMC_VIRT      0xFE000000
+#define OMAP34XX_GPMC_SIZE      SZ_1M
+#define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE /* 0x6C000000 */
+#define OMAP343X_SMS_VIRT       0xFC000000
+#define OMAP343X_SMS_SIZE       SZ_1M
+#define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE /* 0x6D000000 */
+#define OMAP343X_SDRC_VIRT      0xFD000000
+#define OMAP343X_SDRC_SIZE      SZ_1M
+#define IO_OFFSET               0x90000000
+#define IO_ADDRESS(pa)          ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define io_p2v(pa)              ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
+/* DSP */
+#define DSP_MEM_34XX_PHYS       OMAP34XX_DSP_MEM_BASE   /* 0x58000000 */
+#define DSP_MEM_34XX_VIRT       0xe0000000
+#define DSP_MEM_34XX_SIZE       0x28000
+#define DSP_IPI_34XX_PHYS       OMAP34XX_DSP_IPI_BASE   /* 0x59000000 */
+#define DSP_IPI_34XX_VIRT       0xe1000000
+#define DSP_IPI_34XX_SIZE       SZ_4K
+#define DSP_MMU_34XX_PHYS       OMAP34XX_DSP_MMU_BASE   /* 0x5a000000 */
+#define DSP_MMU_34XX_VIRT       0xe2000000
+#define DSP_MMU_34XX_SIZE       SZ_4K
 #endif
 #ifndef __ASSEMBLER__
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index b8fff50e6a87..ff9a5b5575fd 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -4,9 +4,10 @@
 * Table of the Omap register configurations for the FUNC_MUX and
 * PULL_DWN combinations.
 *
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2003 - 2008 Nokia Corporation
 *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -27,14 +28,6 @@
 *       - W8        = ball
 *       - 1610      = 1510 or 1610, none if common for both 1510 and 1610
 *       - MMC2_DAT0 = function
- *
- * Change log:
- *   Added entry for the I2C interface. (02Feb 2004)
- *   Copyright (C) 2004 Texas Instruments
- *
- *   Added entry for the keypad and uwire CS1. (09Mar 2004)
- *   Copyright (C) 2004 Texas Instruments
- *
 */
 #ifndef __ASM_ARCH_MUX_H
@@ -469,7 +462,12 @@ enum omap24xx_index {
        AA8_242X_GPIO58,
        Y20_24XX_GPIO60,
        W4__24XX_GPIO74,
+        N15_24XX_GPIO85,
        M15_24XX_GPIO92,
+        P20_24XX_GPIO93,
+        P18_24XX_GPIO95,
+        M18_24XX_GPIO96,
+        L14_24XX_GPIO97,
        J15_24XX_GPIO99,
        V14_24XX_GPIO117,
        P14_24XX_GPIO125,
@@ -494,8 +492,6 @@ enum omap24xx_index {
        D3_242X_DMAREQ4,
        E3_242X_DMAREQ5,
-        P20_24XX_TSC_IRQ,
        /* UART3 */
        K15_24XX_UART3_TX,
        K14_24XX_UART3_RX,
@@ -557,13 +553,57 @@ enum omap24xx_index {
        B3__24XX_KBR5,
        AA4_24XX_KBC2,
        B13_24XX_KBC6,
+        /* 2430 USB */
+        AD9_2430_USB0_PUEN,
+        Y11_2430_USB0_VP,
+        AD7_2430_USB0_VM,
+        AE7_2430_USB0_RCV,
+        AD4_2430_USB0_TXEN,
+        AF9_2430_USB0_SE0,
+        AE6_2430_USB0_DAT,
+        AD24_2430_USB1_SE0,
+        AB24_2430_USB1_RCV,
+        Y25_2430_USB1_TXEN,
+        AA26_2430_USB1_DAT,
+        /* 2430 HS-USB */
+        AD9_2430_USB0HS_DATA3,
+        Y11_2430_USB0HS_DATA4,
+        AD7_2430_USB0HS_DATA5,
+        AE7_2430_USB0HS_DATA6,
+        AD4_2430_USB0HS_DATA2,
+        AF9_2430_USB0HS_DATA0,
+        AE6_2430_USB0HS_DATA1,
+        AE8_2430_USB0HS_CLK,
+        AD8_2430_USB0HS_DIR,
+        AE5_2430_USB0HS_STP,
+        AE9_2430_USB0HS_NXT,
+        AC7_2430_USB0HS_DATA7,
+        /* 2430 McBSP */
+        AC10_2430_MCBSP2_FSX,
+        AD16_2430_MCBSP2_CLX,
+        AE13_2430_MCBSP2_DX,
+        AD13_2430_MCBSP2_DR,
+        AC10_2430_MCBSP2_FSX_OFF,
+        AD16_2430_MCBSP2_CLX_OFF,
+        AE13_2430_MCBSP2_DX_OFF,
+        AD13_2430_MCBSP2_DR_OFF,
+};
+struct omap_mux_cfg {
+        struct pin_config       *pins;
+        unsigned long           size;
+        int                     (*cfg_reg)(const struct pin_config *cfg);
 };
 #ifdef  CONFIG_OMAP_MUX
 /* setup pin muxing in Linux */
 extern int omap1_mux_init(void);
 extern int omap2_mux_init(void);
-extern int omap_mux_register(struct pin_config * pins, unsigned long size);
+extern int omap_mux_register(struct omap_mux_cfg *);
 extern int omap_cfg_reg(unsigned long reg_cfg);
 #else
 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index 14c0f9496579..b9fcaae287c8 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -1,3 +1,28 @@
+/*
+ * include/asm-arm/arch-omap/omap24xx.h
+ *
+ * This file contains the processor specific definitions
+ * of the TI OMAP24XX.
+ *
+ * Copyright (C) 2007 Texas Instruments.
+ * Copyright (C) 2007 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
 #ifndef __ASM_ARCH_OMAP24XX_H
 #define __ASM_ARCH_OMAP24XX_H
@@ -13,33 +38,70 @@
 /* interrupt controller */
 #define OMAP24XX_IC_BASE        (L4_24XX_BASE + 0xfe000)
-#define VA_IC_BASE              IO_ADDRESS(OMAP24XX_IC_BASE)
 #define OMAP24XX_IVA_INTC_BASE  0x40000000
 #define IRQ_SIR_IRQ             0x0040
-#ifdef CONFIG_ARCH_OMAP2420
+#define OMAP2420_CTRL_BASE      L4_24XX_BASE
-#define OMAP24XX_32KSYNCT_BASE  (L4_24XX_BASE + 0x4000)
+#define OMAP2420_32KSYNCT_BASE  (L4_24XX_BASE + 0x4000)
-#define OMAP24XX_PRCM_BASE      (L4_24XX_BASE + 0x8000)
+#define OMAP2420_PRCM_BASE      (L4_24XX_BASE + 0x8000)
-#define OMAP24XX_SDRC_BASE      (L3_24XX_BASE + 0x9000)
+#define OMAP2420_CM_BASE        (L4_24XX_BASE + 0x8000)
-#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
+#define OMAP2420_PRM_BASE       OMAP2420_CM_BASE
-#endif
+#define OMAP2420_SDRC_BASE      (L3_24XX_BASE + 0x9000)
+#define OMAP2420_SMS_BASE       0x68008000
-#ifdef CONFIG_ARCH_OMAP2430
+#define OMAP2430_32KSYNCT_BASE  (L4_WK_243X_BASE + 0x20000)
-#define OMAP24XX_32KSYNCT_BASE  (L4_WK_243X_BASE + 0x20000)
+#define OMAP2430_PRCM_BASE      (L4_WK_243X_BASE + 0x6000)
-#define OMAP24XX_PRCM_BASE      (L4_WK_243X_BASE + 0x6000)
+#define OMAP2430_CM_BASE        (L4_WK_243X_BASE + 0x6000)
-#define OMAP24XX_SDRC_BASE      (0x6D000000)
+#define OMAP2430_PRM_BASE       OMAP2430_CM_BASE
-#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
+#define OMAP243X_SMS_BASE       0x6C000000
+#define OMAP243X_SDRC_BASE      0x6D000000
 #define OMAP243X_GPMC_BASE      0x6E000000
-#endif
+#define OMAP243X_SCM_BASE       (L4_WK_243X_BASE + 0x2000)
+#define OMAP243X_CTRL_BASE      OMAP243X_SCM_BASE
+#define OMAP243X_HS_BASE        (L4_24XX_BASE + 0x000ac000)
 /* DSP SS */
-#define OMAP24XX_DSP_BASE       0x58000000
+#define OMAP2420_DSP_BASE       0x58000000
-#define OMAP24XX_DSP_MEM_BASE   (OMAP24XX_DSP_BASE + 0x0)
+#define OMAP2420_DSP_MEM_BASE   (OMAP2420_DSP_BASE + 0x0)
-#define OMAP24XX_DSP_IPI_BASE   (OMAP24XX_DSP_BASE + 0x1000000)
+#define OMAP2420_DSP_IPI_BASE   (OMAP2420_DSP_BASE + 0x1000000)
-#define OMAP24XX_DSP_MMU_BASE   (OMAP24XX_DSP_BASE + 0x2000000)
+#define OMAP2420_DSP_MMU_BASE   (OMAP2420_DSP_BASE + 0x2000000)
+#define OMAP243X_DSP_BASE       0x5C000000
+#define OMAP243X_DSP_MEM_BASE   (OMAP243X_DSP_BASE + 0x0)
+#define OMAP243X_DSP_MMU_BASE   (OMAP243X_DSP_BASE + 0x1000000)
 /* Mailbox */
 #define OMAP24XX_MAILBOX_BASE   (L4_24XX_BASE + 0x94000)
+/* Camera */
+#define OMAP24XX_CAMERA_BASE    (L4_24XX_BASE + 0x52000)
+/* Security */
+#define OMAP24XX_SEC_BASE       (L4_24XX_BASE + 0xA0000)
+#define OMAP24XX_SEC_RNG_BASE   (OMAP24XX_SEC_BASE + 0x0000)
+#define OMAP24XX_SEC_DES_BASE   (OMAP24XX_SEC_BASE + 0x2000)
+#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
+#define OMAP24XX_SEC_AES_BASE   (OMAP24XX_SEC_BASE + 0x6000)
+#define OMAP24XX_SEC_PKA_BASE   (OMAP24XX_SEC_BASE + 0x8000)
+#if defined(CONFIG_ARCH_OMAP2420)
+#define OMAP2_32KSYNCT_BASE     OMAP2420_32KSYNCT_BASE
+#define OMAP2_PRCM_BASE         OMAP2420_PRCM_BASE
+#define OMAP2_CM_BASE           OMAP2420_CM_BASE
+#define OMAP2_PRM_BASE          OMAP2420_PRM_BASE
+#define OMAP2_VA_IC_BASE        IO_ADDRESS(OMAP24XX_IC_BASE)
+#elif defined(CONFIG_ARCH_OMAP2430)
+#define OMAP2_32KSYNCT_BASE     OMAP2430_32KSYNCT_BASE
+#define OMAP2_PRCM_BASE         OMAP2430_PRCM_BASE
+#define OMAP2_CM_BASE           OMAP2430_CM_BASE
+#define OMAP2_PRM_BASE          OMAP2430_PRM_BASE
+#define OMAP2_VA_IC_BASE        IO_ADDRESS(OMAP24XX_IC_BASE)
+#endif
 #endif /* __ASM_ARCH_OMAP24XX_H */
diff --git a/include/asm-arm/arch-omap/sdrc.h b/include/asm-arm/arch-omap/sdrc.h
new file mode 100644
index 000000000000..673b3965befc
--- /dev/null
+++ b/include/asm-arm/arch-omap/sdrc.h
@@ -0,0 +1,75 @@
+#ifndef ____ASM_ARCH_SDRC_H
+#define ____ASM_ARCH_SDRC_H
+/*
+ * OMAP2/3 SDRC/SMS register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/arch/io.h>
+/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
+#define SDRC_SYSCONFIG          0x010
+#define SDRC_DLLA_CTRL          0x060
+#define SDRC_DLLA_STATUS        0x064
+#define SDRC_DLLB_CTRL          0x068
+#define SDRC_DLLB_STATUS        0x06C
+#define SDRC_POWER              0x070
+#define SDRC_MR_0               0x084
+#define SDRC_RFR_CTRL_0         0x0a4
+/*
+ * These values represent the number of memory clock cycles between
+ * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
+ * rows per device, and include a subtraction of a 50 cycle window in the
+ * event that the autorefresh command is delayed due to other SDRC activity.
+ * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
+ * counter reaches 0.
+ *
+ * These represent optimal values for common parts, it won't work for all.
+ * As long as you scale down, most parameters are still work, they just
+ * become sub-optimal. The RFR value goes in the opposite direction. If you
+ * don't adjust it down as your clock period increases the refresh interval
+ * will not be met. Setting all parameters for complete worst case may work,
+ * but may cut memory performance by 2x. Due to errata the DLLs need to be
+ * unlocked and their value needs run time calibration. A dynamic call is
+ * need for that as no single right value exists acorss production samples.
+ *
+ * Only the FULL speed values are given. Current code is such that rate
+ * changes must be made at DPLLoutx2. The actual value adjustment for low
+ * frequency operation will be handled by omap_set_performance()
+ *
+ * By having the boot loader boot up in the fastest L4 speed available likely
+ * will result in something which you can switch between.
+ */
+#define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
+#define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
+#define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
+#define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
+#define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
+/*
+ * SMS register access
+ */
+#define OMAP242X_SMS_REGADDR(reg)       (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+#define OMAP243X_SMS_REGADDR(reg)       (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+#define OMAP343X_SMS_REGADDR(reg)       (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+/* SMS register offsets - read/write with sms_{read,write}_reg() */
+#define SMS_SYSCONFIG           0x010
+/* REVISIT: fill in other SMS registers here */
+#endif
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 99ae9eabaf71..2147d18aaeae 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -132,14 +132,11 @@
 #       define  CONF_USB_PWRDN_DP_R     (1 << 1)
 /* OMAP2 */
-#define CONTROL_DEVCONF_REG             __REG32(L4_24XX_BASE + 0x0274)
 #       define  USB_UNIDIR                      0x0
 #       define  USB_UNIDIR_TLL                  0x1
 #       define  USB_BIDIR                       0x2
 #       define  USB_BIDIR_TLL                   0x3
-#       define  USBT0WRMODEI(x)         ((x) << 22)
+#       define  USBTXWRMODEI(port, x)   ((x) << (22 - (port * 2)))
-#       define  USBT1WRMODEI(x)         ((x) << 20)
-#       define  USBT2WRMODEI(x)         ((x) << 18)
 #       define  USBT2TLL5PI             (1 << 17)
 #       define  USB0PUENACTLOI          (1 << 16)
 #       define  USBSTANDBYCTRL          (1 << 15)
diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h
deleted file mode 100644
index e0b8c39b9167..000000000000
--- a/include/asm-arm/arch-orion/io.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * include/asm-arm/arch-orion/io.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-#include "orion.h"
-#define IO_SPACE_LIMIT          0xffffffff
-#define IO_SPACE_REMAP          ORION_PCI_SYS_IO_BASE
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-#define __io(a)                 __io(a)
-#define __mem_pci(a)            (a)
-#endif
diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h
deleted file mode 100644
index eea65ca6076a..000000000000
--- a/include/asm-arm/arch-orion/irqs.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * include/asm-arm/arch-orion/irqs.h
- *
- * IRQ definitions for Orion SoC
- *
- *  Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- *  This file is licensed under the terms of the GNU General Public
- *  License version 2. This program is licensed "as is" without any
- *  warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARCH_IRQS_H__
-#define __ASM_ARCH_IRQS_H__
-#include "orion.h"      /* need GPIO_MAX */
-/*
- * Orion Main Interrupt Controller
- */
-#define IRQ_ORION_BRIDGE        0
-#define IRQ_ORION_DOORBELL_H2C  1
-#define IRQ_ORION_DOORBELL_C2H  2
-#define IRQ_ORION_UART0         3
-#define IRQ_ORION_UART1         4
-#define IRQ_ORION_I2C           5
-#define IRQ_ORION_GPIO_0_7      6
-#define IRQ_ORION_GPIO_8_15     7
-#define IRQ_ORION_GPIO_16_23    8
-#define IRQ_ORION_GPIO_24_31    9
-#define IRQ_ORION_PCIE0_ERR     10
-#define IRQ_ORION_PCIE0_INT     11
-#define IRQ_ORION_USB1_CTRL     12
-#define IRQ_ORION_DEV_BUS_ERR   14
-#define IRQ_ORION_PCI_ERR       15
-#define IRQ_ORION_USB_BR_ERR    16
-#define IRQ_ORION_USB0_CTRL     17
-#define IRQ_ORION_ETH_RX        18
-#define IRQ_ORION_ETH_TX        19
-#define IRQ_ORION_ETH_MISC      20
-#define IRQ_ORION_ETH_SUM       21
-#define IRQ_ORION_ETH_ERR       22
-#define IRQ_ORION_IDMA_ERR      23
-#define IRQ_ORION_IDMA_0        24
-#define IRQ_ORION_IDMA_1        25
-#define IRQ_ORION_IDMA_2        26
-#define IRQ_ORION_IDMA_3        27
-#define IRQ_ORION_CESA          28
-#define IRQ_ORION_SATA          29
-#define IRQ_ORION_XOR0          30
-#define IRQ_ORION_XOR1          31
-/*
- * Orion General Purpose Pins
- */
-#define IRQ_ORION_GPIO_START    32
-#define NR_GPIO_IRQS            GPIO_MAX
-#define NR_IRQS                 (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
-#endif /* __ASM_ARCH_IRQS_H__ */
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
deleted file mode 100644
index 673a418a7419..000000000000
--- a/include/asm-arm/arch-orion/orion.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * include/asm-arm/arch-orion/orion.h
- *
- * Generic definitions of Orion SoC flavors:
- *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARCH_ORION_H__
-#define __ASM_ARCH_ORION_H__
-/*****************************************************************************
- * Orion Address Map
- *
- * virt         phys            size
- * fdd00000     f1000000        1M      on-chip peripheral registers
- * fde00000     f2000000        1M      PCIe I/O space
- * fdf00000     f2100000        1M      PCI I/O space
- * fe000000     f0000000        16M     PCIe WA space (Orion-NAS only)
- ****************************************************************************/
-#define ORION_REGS_PHYS_BASE    0xf1000000
-#define ORION_REGS_VIRT_BASE    0xfdd00000
-#define ORION_REGS_SIZE         SZ_1M
-#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
-#define ORION_PCIE_IO_VIRT_BASE 0xfde00000
-#define ORION_PCIE_IO_BUS_BASE  0x00000000
-#define ORION_PCIE_IO_SIZE      SZ_1M
-#define ORION_PCI_IO_PHYS_BASE  0xf2100000
-#define ORION_PCI_IO_VIRT_BASE  0xfdf00000
-#define ORION_PCI_IO_BUS_BASE   0x00100000
-#define ORION_PCI_IO_SIZE       SZ_1M
-/* Relevant only for Orion-NAS */
-#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
-#define ORION_PCIE_WA_VIRT_BASE 0xfe000000
-#define ORION_PCIE_WA_SIZE      SZ_16M
-#define ORION_PCIE_MEM_PHYS_BASE        0xe0000000
-#define ORION_PCIE_MEM_SIZE             SZ_128M
-#define ORION_PCI_MEM_PHYS_BASE         0xe8000000
-#define ORION_PCI_MEM_SIZE              SZ_128M
-/*******************************************************************************
- * Supported Devices & Revisions
- ******************************************************************************/
-/* Orion-1 (88F5181) */
-#define MV88F5181_DEV_ID        0x5181
-#define MV88F5181_REV_B1        3
-/* Orion-NAS (88F5182) */
-#define MV88F5182_DEV_ID        0x5182
-#define MV88F5182_REV_A2        2
-/* Orion-2 (88F5281) */
-#define MV88F5281_DEV_ID        0x5281
-#define MV88F5281_REV_D1        5
-#define MV88F5281_REV_D2        6
-/*******************************************************************************
- * Orion Registers Map
- ******************************************************************************/
-#define ORION_DDR_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x00000)
-#define ORION_DDR_REG(x)                (ORION_DDR_VIRT_BASE | (x))
-#define ORION_DEV_BUS_PHYS_BASE         (ORION_REGS_PHYS_BASE | 0x10000)
-#define ORION_DEV_BUS_VIRT_BASE         (ORION_REGS_VIRT_BASE | 0x10000)
-#define ORION_DEV_BUS_REG(x)            (ORION_DEV_BUS_VIRT_BASE | (x))
-#define  I2C_PHYS_BASE                  (ORION_DEV_BUS_PHYS_BASE | 0x1000)
-#define  UART0_PHYS_BASE                (ORION_DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE                (ORION_DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE                (ORION_DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE                (ORION_DEV_BUS_VIRT_BASE | 0x2100)
-#define ORION_BRIDGE_VIRT_BASE          (ORION_REGS_VIRT_BASE | 0x20000)
-#define ORION_BRIDGE_REG(x)             (ORION_BRIDGE_VIRT_BASE | (x))
-#define ORION_PCI_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x30000)
-#define ORION_PCI_REG(x)                (ORION_PCI_VIRT_BASE | (x))
-#define ORION_PCIE_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x40000)
-#define ORION_PCIE_REG(x)               (ORION_PCIE_VIRT_BASE | (x))
-#define ORION_USB0_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0x50000)
-#define ORION_USB0_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x50000)
-#define ORION_USB0_REG(x)               (ORION_USB0_VIRT_BASE | (x))
-#define ORION_ETH_PHYS_BASE             (ORION_REGS_PHYS_BASE | 0x70000)
-#define ORION_ETH_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x70000)
-#define ORION_ETH_REG(x)                (ORION_ETH_VIRT_BASE | (x))
-#define ORION_SATA_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0x80000)
-#define ORION_SATA_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x80000)
-#define ORION_SATA_REG(x)               (ORION_SATA_VIRT_BASE | (x))
-#define ORION_USB1_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0xa0000)
-#define ORION_USB1_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0xa0000)
-#define ORION_USB1_REG(x)               (ORION_USB1_VIRT_BASE | (x))
-/*******************************************************************************
- * Device Bus Registers
- ******************************************************************************/
-#define MPP_0_7_CTRL            ORION_DEV_BUS_REG(0x000)
-#define MPP_8_15_CTRL           ORION_DEV_BUS_REG(0x004)
-#define MPP_16_19_CTRL          ORION_DEV_BUS_REG(0x050)
-#define MPP_DEV_CTRL            ORION_DEV_BUS_REG(0x008)
-#define MPP_RESET_SAMPLE        ORION_DEV_BUS_REG(0x010)
-#define GPIO_OUT                ORION_DEV_BUS_REG(0x100)
-#define GPIO_IO_CONF            ORION_DEV_BUS_REG(0x104)
-#define GPIO_BLINK_EN           ORION_DEV_BUS_REG(0x108)
-#define GPIO_IN_POL             ORION_DEV_BUS_REG(0x10c)
-#define GPIO_DATA_IN            ORION_DEV_BUS_REG(0x110)
-#define GPIO_EDGE_CAUSE         ORION_DEV_BUS_REG(0x114)
-#define GPIO_EDGE_MASK          ORION_DEV_BUS_REG(0x118)
-#define GPIO_LEVEL_MASK         ORION_DEV_BUS_REG(0x11c)
-#define DEV_BANK_0_PARAM        ORION_DEV_BUS_REG(0x45c)
-#define DEV_BANK_1_PARAM        ORION_DEV_BUS_REG(0x460)
-#define DEV_BANK_2_PARAM        ORION_DEV_BUS_REG(0x464)
-#define DEV_BANK_BOOT_PARAM     ORION_DEV_BUS_REG(0x46c)
-#define DEV_BUS_CTRL            ORION_DEV_BUS_REG(0x4c0)
-#define DEV_BUS_INT_CAUSE       ORION_DEV_BUS_REG(0x4d0)
-#define DEV_BUS_INT_MASK        ORION_DEV_BUS_REG(0x4d4)
-#define GPIO_MAX                32
-/***************************************************************************
- * Orion CPU Bridge Registers
- **************************************************************************/
-#define CPU_CONF                ORION_BRIDGE_REG(0x100)
-#define CPU_CTRL                ORION_BRIDGE_REG(0x104)
-#define CPU_RESET_MASK          ORION_BRIDGE_REG(0x108)
-#define CPU_SOFT_RESET          ORION_BRIDGE_REG(0x10c)
-#define POWER_MNG_CTRL_REG      ORION_BRIDGE_REG(0x11C)
-#define BRIDGE_CAUSE            ORION_BRIDGE_REG(0x110)
-#define BRIDGE_MASK             ORION_BRIDGE_REG(0x114)
-#define MAIN_IRQ_CAUSE          ORION_BRIDGE_REG(0x200)
-#define MAIN_IRQ_MASK           ORION_BRIDGE_REG(0x204)
-#define TIMER_CTRL              ORION_BRIDGE_REG(0x300)
-#define TIMER_VAL(x)            ORION_BRIDGE_REG(0x314 + ((x) * 8))
-#define TIMER_VAL_RELOAD(x)     ORION_BRIDGE_REG(0x310 + ((x) * 8))
-#ifndef __ASSEMBLY__
-/*******************************************************************************
- * Helpers to access Orion registers
- ******************************************************************************/
-#include <asm/types.h>
-#include <asm/io.h>
-#define orion_read(r)           __raw_readl(r)
-#define orion_write(r, val)     __raw_writel(val, r)
-/*
- * These are not preempt safe. Locks, if needed, must be taken care by caller.
- */
-#define orion_setbits(r, mask)  orion_write((r), orion_read(r) | (mask))
-#define orion_clrbits(r, mask)  orion_write((r), orion_read(r) & ~(mask))
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_ORION_H__ */
diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h
deleted file mode 100644
index 26c2c91eecf0..000000000000
--- a/include/asm-arm/arch-orion/timex.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * include/asm-arm/arch-orion/timex.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#define ORION_TCLK              166666667
-#define CLOCK_TICK_RATE         ORION_TCLK
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S
index 2746220f5d85..4f98f3ba2929 100644
--- a/include/asm-arm/arch-orion/debug-macro.S
+++ b/include/asm-arm/arch-orion5x/debug-macro.S
@@ -1,5 +1,5 @@
 /*
- * linux/include/asm-arm/arch-orion/debug-macro.S
+ * include/asm-arm/arch-orion5x/debug-macro.S
 *
 * Debugging macro include header
 *
@@ -8,13 +8,13 @@
 * published by the Free Software Foundation.
 */
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
        .macro  addruart,rx
        mrc     p15, 0, \rx, c1, c0
        tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =ORION_REGS_PHYS_BASE
+        ldreq   \rx, =ORION5X_REGS_PHYS_BASE
-        ldrne   \rx, =ORION_REGS_VIRT_BASE
+        ldrne   \rx, =ORION5X_REGS_VIRT_BASE
        orr     \rx, \rx, #0x00012000
        .endm
diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion5x/dma.h
index 40a8c178f10d..40a8c178f10d 100644
--- a/include/asm-arm/arch-orion/dma.h
+++ b/include/asm-arm/arch-orion5x/dma.h
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S
index cda096b2acfd..d8ef54c0ee9a 100644
--- a/include/asm-arm/arch-orion/entry-macro.S
+++ b/include/asm-arm/arch-orion5x/entry-macro.S
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-orion/entry-macro.S
+ * include/asm-arm/arch-orion5x/entry-macro.S
 *
 * Low-level IRQ helper macros for Orion platforms
 *
@@ -8,7 +8,7 @@
 * warranty of any kind, whether express or implied.
 */
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
        .macro  disable_fiq
        .endm
diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion5x/gpio.h
index d66284f9a14c..c85e498388b6 100644
--- a/include/asm-arm/arch-orion/gpio.h
+++ b/include/asm-arm/arch-orion5x/gpio.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-orion/gpio.h
+ * include/asm-arm/arch-orion5x/gpio.h
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
@@ -12,17 +12,17 @@ extern int gpio_direction_input(unsigned pin);
 extern int gpio_direction_output(unsigned pin, int value);
 extern int gpio_get_value(unsigned pin);
 extern void gpio_set_value(unsigned pin, int value);
-extern void orion_gpio_set_blink(unsigned pin, int blink);
+extern void orion5x_gpio_set_blink(unsigned pin, int blink);
 extern void gpio_display(void);         /* debug */
 static inline int gpio_to_irq(int pin)
 {
-        return pin + IRQ_ORION_GPIO_START;
+        return pin + IRQ_ORION5X_GPIO_START;
 }
 static inline int irq_to_gpio(int irq)
 {
-        return irq - IRQ_ORION_GPIO_START;
+        return irq - IRQ_ORION5X_GPIO_START;
 }
 #include <asm-generic/gpio.h>           /* cansleep wrappers */
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion5x/hardware.h
index 65da374de735..5d2d8e0b5630 100644
--- a/include/asm-arm/arch-orion/hardware.h
+++ b/include/asm-arm/arch-orion5x/hardware.h
@@ -1,21 +1,21 @@
 /*
- * include/asm-arm/arch-orion/hardware.h
+ * include/asm-arm/arch-orion5x/hardware.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#ifndef __ASM_ARCH_HARDWARE_H__
+#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H__
+#define __ASM_ARCH_HARDWARE_H
-#include "orion.h"
+#include "orion5x.h"
 #define pcibios_assign_all_busses()     1
 #define PCIBIOS_MIN_IO          0x00001000
 #define PCIBIOS_MIN_MEM         0x01000000
-#define PCIMEM_BASE             ORION_PCIE_MEM_PHYS_BASE
+#define PCIMEM_BASE             ORION5X_PCIE_MEM_PHYS_BASE
 #endif
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h
new file mode 100644
index 000000000000..5148ab7ad1f8
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/io.h
@@ -0,0 +1,68 @@
+/*
+ * include/asm-arm/arch-orion5x/io.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+#include "orion5x.h"
+#define IO_SPACE_LIMIT          0xffffffff
+#define IO_SPACE_REMAP          ORION5X_PCI_SYS_IO_BASE
+static inline void __iomem *
+__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
+{
+        void __iomem *retval;
+        if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE &&
+            paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) {
+                retval = (void __iomem *)ORION5X_REGS_VIRT_BASE +
+                                (paddr - ORION5X_REGS_PHYS_BASE);
+        } else {
+                retval = __arm_ioremap(paddr, size, mtype);
+        }
+        return retval;
+}
+static inline void
+__arch_iounmap(void __iomem *addr)
+{
+        if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
+            addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
+                __iounmap(addr);
+}
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
+#define __arch_iounmap(a)       __arch_iounmap(a)
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+/*****************************************************************************
+ * Helpers to access Orion registers
+ ****************************************************************************/
+#define orion5x_read(r)         __raw_readl(r)
+#define orion5x_write(r, val)   __raw_writel(val, r)
+/*
+ * These are not preempt-safe.  Locks, if needed, must be taken
+ * care of by the caller.
+ */
+#define orion5x_setbits(r, mask)        orion5x_write((r), orion5x_read(r) | (mask))
+#define orion5x_clrbits(r, mask)        orion5x_write((r), orion5x_read(r) & ~(mask))
+#endif
diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h
new file mode 100644
index 000000000000..abdd61a4833a
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/irqs.h
@@ -0,0 +1,62 @@
+/*
+ * include/asm-arm/arch-orion5x/irqs.h
+ *
+ * IRQ definitions for Orion SoC
+ *
+ *  Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ *  This file is licensed under the terms of the GNU General Public
+ *  License version 2. This program is licensed "as is" without any
+ *  warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+#include "orion5x.h"    /* need GPIO_MAX */
+/*
+ * Orion Main Interrupt Controller
+ */
+#define IRQ_ORION5X_BRIDGE              0
+#define IRQ_ORION5X_DOORBELL_H2C        1
+#define IRQ_ORION5X_DOORBELL_C2H        2
+#define IRQ_ORION5X_UART0               3
+#define IRQ_ORION5X_UART1               4
+#define IRQ_ORION5X_I2C                 5
+#define IRQ_ORION5X_GPIO_0_7            6
+#define IRQ_ORION5X_GPIO_8_15           7
+#define IRQ_ORION5X_GPIO_16_23          8
+#define IRQ_ORION5X_GPIO_24_31          9
+#define IRQ_ORION5X_PCIE0_ERR           10
+#define IRQ_ORION5X_PCIE0_INT           11
+#define IRQ_ORION5X_USB1_CTRL           12
+#define IRQ_ORION5X_DEV_BUS_ERR         14
+#define IRQ_ORION5X_PCI_ERR             15
+#define IRQ_ORION5X_USB_BR_ERR          16
+#define IRQ_ORION5X_USB0_CTRL           17
+#define IRQ_ORION5X_ETH_RX              18
+#define IRQ_ORION5X_ETH_TX              19
+#define IRQ_ORION5X_ETH_MISC            20
+#define IRQ_ORION5X_ETH_SUM             21
+#define IRQ_ORION5X_ETH_ERR             22
+#define IRQ_ORION5X_IDMA_ERR            23
+#define IRQ_ORION5X_IDMA_0              24
+#define IRQ_ORION5X_IDMA_1              25
+#define IRQ_ORION5X_IDMA_2              26
+#define IRQ_ORION5X_IDMA_3              27
+#define IRQ_ORION5X_CESA                28
+#define IRQ_ORION5X_SATA                29
+#define IRQ_ORION5X_XOR0                30
+#define IRQ_ORION5X_XOR1                31
+/*
+ * Orion General Purpose Pins
+ */
+#define IRQ_ORION5X_GPIO_START  32
+#define NR_GPIO_IRQS            GPIO_MAX
+#define NR_IRQS                 (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
+#endif
diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion5x/memory.h
index d954dba87ced..80053a7afc7a 100644
--- a/include/asm-arm/arch-orion/memory.h
+++ b/include/asm-arm/arch-orion5x/memory.h
@@ -1,15 +1,16 @@
 /*
- * include/asm-arm/arch-orion/memory.h
+ * include/asm-arm/arch-orion5x/memory.h
 *
 * Marvell Orion memory definitions
 */
-#ifndef __ASM_ARCH_MMU_H
+#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MEMORY_H
 #define PHYS_OFFSET     UL(0x00000000)
 #define __virt_to_bus(x)        __virt_to_phys(x)
 #define __bus_to_virt(x)        __phys_to_virt(x)
 #endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
new file mode 100644
index 000000000000..206ddd71e193
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -0,0 +1,159 @@
+/*
+ * include/asm-arm/arch-orion5x/orion5x.h
+ *
+ * Generic definitions of Orion SoC flavors:
+ *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_ORION5X_H
+#define __ASM_ARCH_ORION5X_H
+/*****************************************************************************
+ * Orion Address Maps
+ *
+ * phys
+ * e0000000     PCIe MEM space
+ * e8000000     PCI MEM space
+ * f0000000     PCIe WA space (Orion-1/Orion-NAS only)
+ * f1000000     on-chip peripheral registers
+ * f2000000     PCIe I/O space
+ * f2100000     PCI I/O space
+ * f4000000     device bus mappings (boot)
+ * fa000000     device bus mappings (cs0)
+ * fa800000     device bus mappings (cs2)
+ * fc000000     device bus mappings (cs0/cs1)
+ *
+ * virt         phys            size
+ * fdd00000     f1000000        1M      on-chip peripheral registers
+ * fde00000     f2000000        1M      PCIe I/O space
+ * fdf00000     f2100000        1M      PCI I/O space
+ * fe000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
+ ****************************************************************************/
+#define ORION5X_REGS_PHYS_BASE          0xf1000000
+#define ORION5X_REGS_VIRT_BASE          0xfdd00000
+#define ORION5X_REGS_SIZE               SZ_1M
+#define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
+#define ORION5X_PCIE_IO_VIRT_BASE       0xfde00000
+#define ORION5X_PCIE_IO_BUS_BASE        0x00000000
+#define ORION5X_PCIE_IO_SIZE            SZ_1M
+#define ORION5X_PCI_IO_PHYS_BASE        0xf2100000
+#define ORION5X_PCI_IO_VIRT_BASE        0xfdf00000
+#define ORION5X_PCI_IO_BUS_BASE         0x00100000
+#define ORION5X_PCI_IO_SIZE             SZ_1M
+/* Relevant only for Orion-1/Orion-NAS */
+#define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
+#define ORION5X_PCIE_WA_VIRT_BASE       0xfe000000
+#define ORION5X_PCIE_WA_SIZE            SZ_16M
+#define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
+#define ORION5X_PCIE_MEM_SIZE           SZ_128M
+#define ORION5X_PCI_MEM_PHYS_BASE       0xe8000000
+#define ORION5X_PCI_MEM_SIZE            SZ_128M
+/*******************************************************************************
+ * Supported Devices & Revisions
+ ******************************************************************************/
+/* Orion-1 (88F5181) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID        0x5182
+#define MV88F5182_REV_A2        2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID        0x5281
+#define MV88F5281_REV_D1        5
+#define MV88F5281_REV_D2        6
+/*******************************************************************************
+ * Orion Registers Map
+ ******************************************************************************/
+#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
+#define ORION5X_DDR_REG(x)              (ORION5X_DDR_VIRT_BASE | (x))
+#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
+#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
+#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
+#define ORION5X_BRIDGE_REG(x)           (ORION5X_BRIDGE_VIRT_BASE | (x))
+#define  TIMER_VIRT_BASE                (ORION5X_BRIDGE_VIRT_BASE | 0x300)
+#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_REG(x)              (ORION5X_PCI_VIRT_BASE | (x))
+#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_REG(x)             (ORION5X_PCIE_VIRT_BASE | (x))
+#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
+#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_REG(x)             (ORION5X_USB0_VIRT_BASE | (x))
+#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
+#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_REG(x)              (ORION5X_ETH_VIRT_BASE | (x))
+#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
+#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_REG(x)             (ORION5X_SATA_VIRT_BASE | (x))
+#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
+#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_REG(x)             (ORION5X_USB1_VIRT_BASE | (x))
+/*******************************************************************************
+ * Device Bus Registers
+ ******************************************************************************/
+#define MPP_0_7_CTRL            ORION5X_DEV_BUS_REG(0x000)
+#define MPP_8_15_CTRL           ORION5X_DEV_BUS_REG(0x004)
+#define MPP_16_19_CTRL          ORION5X_DEV_BUS_REG(0x050)
+#define MPP_DEV_CTRL            ORION5X_DEV_BUS_REG(0x008)
+#define MPP_RESET_SAMPLE        ORION5X_DEV_BUS_REG(0x010)
+#define GPIO_OUT                ORION5X_DEV_BUS_REG(0x100)
+#define GPIO_IO_CONF            ORION5X_DEV_BUS_REG(0x104)
+#define GPIO_BLINK_EN           ORION5X_DEV_BUS_REG(0x108)
+#define GPIO_IN_POL             ORION5X_DEV_BUS_REG(0x10c)
+#define GPIO_DATA_IN            ORION5X_DEV_BUS_REG(0x110)
+#define GPIO_EDGE_CAUSE         ORION5X_DEV_BUS_REG(0x114)
+#define GPIO_EDGE_MASK          ORION5X_DEV_BUS_REG(0x118)
+#define GPIO_LEVEL_MASK         ORION5X_DEV_BUS_REG(0x11c)
+#define DEV_BANK_0_PARAM        ORION5X_DEV_BUS_REG(0x45c)
+#define DEV_BANK_1_PARAM        ORION5X_DEV_BUS_REG(0x460)
+#define DEV_BANK_2_PARAM        ORION5X_DEV_BUS_REG(0x464)
+#define DEV_BANK_BOOT_PARAM     ORION5X_DEV_BUS_REG(0x46c)
+#define DEV_BUS_CTRL            ORION5X_DEV_BUS_REG(0x4c0)
+#define DEV_BUS_INT_CAUSE       ORION5X_DEV_BUS_REG(0x4d0)
+#define DEV_BUS_INT_MASK        ORION5X_DEV_BUS_REG(0x4d4)
+#define GPIO_MAX                32
+/***************************************************************************
+ * Orion CPU Bridge Registers
+ **************************************************************************/
+#define CPU_CONF                ORION5X_BRIDGE_REG(0x100)
+#define CPU_CTRL                ORION5X_BRIDGE_REG(0x104)
+#define CPU_RESET_MASK          ORION5X_BRIDGE_REG(0x108)
+#define CPU_SOFT_RESET          ORION5X_BRIDGE_REG(0x10c)
+#define POWER_MNG_CTRL_REG      ORION5X_BRIDGE_REG(0x11C)
+#define BRIDGE_CAUSE            ORION5X_BRIDGE_REG(0x110)
+#define BRIDGE_MASK             ORION5X_BRIDGE_REG(0x114)
+#define  BRIDGE_INT_TIMER0      0x0002
+#define  BRIDGE_INT_TIMER1      0x0004
+#define MAIN_IRQ_CAUSE          ORION5X_BRIDGE_REG(0x200)
+#define MAIN_IRQ_MASK           ORION5X_BRIDGE_REG(0x204)
+#endif
diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion5x/system.h
index 17704c68f90e..3f1d1e2d38f8 100644
--- a/include/asm-arm/arch-orion/system.h
+++ b/include/asm-arm/arch-orion5x/system.h
@@ -1,10 +1,10 @@
 /*
- * include/asm-arm/arch-orion/system.h
+ * include/asm-arm/arch-orion5x/system.h
 *
 * Tzachi Perelstein <tzachi@marvell.com>
 *
- * This file is licensed under  the terms of the GNU General Public
+ * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
@@ -12,7 +12,7 @@
 #define __ASM_ARCH_SYSTEM_H
 #include <asm/arch/hardware.h>
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
 static inline void arch_idle(void)
 {
@@ -24,8 +24,9 @@ static inline void arch_reset(char mode)
        /*
         * Enable and issue soft reset
         */
-        orion_setbits(CPU_RESET_MASK, (1 << 2));
+        orion5x_setbits(CPU_RESET_MASK, (1 << 2));
-        orion_setbits(CPU_SOFT_RESET, 1);
+        orion5x_setbits(CPU_SOFT_RESET, 1);
 }
 #endif
diff --git a/include/asm-arm/arch-orion5x/timex.h b/include/asm-arm/arch-orion5x/timex.h
new file mode 100644
index 000000000000..31c568e28cc3
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/timex.h
@@ -0,0 +1,13 @@
+/*
+ * include/asm-arm/arch-orion5x/timex.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define CLOCK_TICK_RATE         (100 * HZ)
+#define ORION5X_TCLK            166666667
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
index 59f44039909a..5c13d4fafb4e 100644
--- a/include/asm-arm/arch-orion/uncompress.h
+++ b/include/asm-arm/arch-orion5x/uncompress.h
@@ -1,14 +1,14 @@
 /*
- * include/asm-arm/arch-orion/uncompress.h
+ * include/asm-arm/arch-orion5x/uncompress.h
 *
 * Tzachi Perelstein <tzachi@marvell.com>
 *
- * This file is licensed under  the terms of the GNU General Public
+ * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
 #define MV_UART_THR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
 #define MV_UART_LSR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h
index 9d580278d2bc..2b3061e90dc1 100644
--- a/include/asm-arm/arch-orion/vmalloc.h
+++ b/include/asm-arm/arch-orion5x/vmalloc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-orion/vmalloc.h
+ * include/asm-arm/arch-orion5x/vmalloc.h
 */
 #define VMALLOC_END       0xfd800000
diff --git a/include/asm-arm/arch-pxa/camera.h b/include/asm-arm/arch-pxa/camera.h
new file mode 100644
index 000000000000..39516ced8b1f
--- /dev/null
+++ b/include/asm-arm/arch-pxa/camera.h
@@ -0,0 +1,48 @@
+/*
+    camera.h - PXA camera driver header file
+    Copyright (C) 2003, Intel Corporation
+    Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+#ifndef __ASM_ARCH_CAMERA_H_
+#define __ASM_ARCH_CAMERA_H_
+#define PXA_CAMERA_MASTER       1
+#define PXA_CAMERA_DATAWIDTH_4  2
+#define PXA_CAMERA_DATAWIDTH_5  4
+#define PXA_CAMERA_DATAWIDTH_8  8
+#define PXA_CAMERA_DATAWIDTH_9  0x10
+#define PXA_CAMERA_DATAWIDTH_10 0x20
+#define PXA_CAMERA_PCLK_EN      0x40
+#define PXA_CAMERA_MCLK_EN      0x80
+#define PXA_CAMERA_PCP          0x100
+#define PXA_CAMERA_HSP          0x200
+#define PXA_CAMERA_VSP          0x400
+struct pxacamera_platform_data {
+        int (*init)(struct device *);
+        int (*power)(struct device *, int);
+        int (*reset)(struct device *, int);
+        unsigned long flags;
+        unsigned long mclk_10khz;
+};
+extern void pxa_set_camera_info(struct pxacamera_platform_data *);
+#endif /* __ASM_ARCH_CAMERA_H_ */
diff --git a/include/asm-arm/arch-pxa/gumstix.h b/include/asm-arm/arch-pxa/gumstix.h
new file mode 100644
index 000000000000..6fa85c4f94f8
--- /dev/null
+++ b/include/asm-arm/arch-pxa/gumstix.h
@@ -0,0 +1,96 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/gumstix.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/* BTRESET - Reset line to Bluetooth module, active low signal. */
+#define GPIO_GUMSTIX_BTRESET          7
+#define GPIO_GUMSTIX_BTRESET_MD         (GPIO_GUMSTIX_BTRESET | GPIO_OUT)
+/*
+GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean
+interrupt signal for determining cable presence. On the original gumstix,
+this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F,
+this moves to GPIO17 and GPIO37. */
+/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
+has detected a cable insertion; driven low otherwise. */
+#ifdef CONFIG_ARCH_GUMSTIX_ORIG
+#define GPIO_GUMSTIX_USB_GPIOn          81
+#define GPIO_GUMSTIX_USB_GPIOx          83
+#else
+#define GPIO_GUMSTIX_USB_GPIOn          35
+#define GPIO_GUMSTIX_USB_GPIOx          41
+#endif
+/* usb state change */
+#define GUMSTIX_USB_INTR_IRQ            IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn)
+#define GPIO_GUMSTIX_USB_GPIOn_MD       (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
+#define GPIO_GUMSTIX_USB_GPIOx_CON_MD   (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
+#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD   (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN)
+/*
+ * SD/MMC definitions
+ */
+#define GUMSTIX_GPIO_nSD_WP             22 /* SD Write Protect */
+#define GUMSTIX_GPIO_nSD_DETECT         11 /* MMC/SD Card Detect */
+#define GUMSTIX_IRQ_GPIO_nSD_DETECT     IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT)
+/*
+ * SMC Ethernet definitions
+ * ETH_RST provides a hardware reset line to the ethernet chip
+ * ETH is the IRQ line in from the ethernet chip to the PXA
+ */
+#define GPIO_GUMSTIX_ETH0_RST           80
+#define GPIO_GUMSTIX_ETH0_RST_MD        (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
+#define GPIO_GUMSTIX_ETH1_RST           52
+#define GPIO_GUMSTIX_ETH1_RST_MD        (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
+#define GPIO_GUMSTIX_ETH0               36
+#define GPIO_GUMSTIX_ETH0_MD            (GPIO_GUMSTIX_ETH0 | GPIO_IN)
+#define GUMSTIX_ETH0_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH0)
+#define GPIO_GUMSTIX_ETH1               27
+#define GPIO_GUMSTIX_ETH1_MD            (GPIO_GUMSTIX_ETH1 | GPIO_IN)
+#define GUMSTIX_ETH1_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH1)
+/* CF reset line */
+#define GPIO8_RESET                     8
+/* CF slot 0 */
+#define GPIO4_nBVD1                     4
+#define GPIO4_nSTSCHG                   GPIO4_nBVD1
+#define GPIO11_nCD                      11
+#define GPIO26_PRDY_nBSY                26
+#define GUMSTIX_S0_nSTSCHG_IRQ          IRQ_GPIO(GPIO4_nSTSCHG)
+#define GUMSTIX_S0_nCD_IRQ              IRQ_GPIO(GPIO11_nCD)
+#define GUMSTIX_S0_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO26_PRDY_nBSY)
+/* CF slot 1 */
+#define GPIO18_nBVD1                    18
+#define GPIO18_nSTSCHG                  GPIO18_nBVD1
+#define GPIO36_nCD                      36
+#define GPIO27_PRDY_nBSY                27
+#define GUMSTIX_S1_nSTSCHG_IRQ          IRQ_GPIO(GPIO18_nSTSCHG)
+#define GUMSTIX_S1_nCD_IRQ              IRQ_GPIO(GPIO36_nCD)
+#define GUMSTIX_S1_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO27_PRDY_nBSY)
+/* CF GPIO line modes */
+#define GPIO4_nSTSCHG_MD                (GPIO4_nSTSCHG | GPIO_IN)
+#define GPIO8_RESET_MD                  (GPIO8_RESET | GPIO_OUT)
+#define GPIO11_nCD_MD                   (GPIO11_nCD | GPIO_IN)
+#define GPIO18_nSTSCHG_MD               (GPIO18_nSTSCHG | GPIO_IN)
+#define GPIO26_PRDY_nBSY_MD             (GPIO26_PRDY_nBSY | GPIO_IN)
+#define GPIO27_PRDY_nBSY_MD             (GPIO27_PRDY_nBSY | GPIO_IN)
+#define GPIO36_nCD_MD                   (GPIO36_nCD | GPIO_IN)
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
index 748406f384c2..99f4f423a8e1 100644
--- a/include/asm-arm/arch-pxa/irda.h
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -10,6 +10,8 @@
 struct pxaficp_platform_data {
        int transceiver_cap;
        void (*transceiver_mode)(struct device *dev, int mode);
+        int (*startup)(struct device *dev);
+        void (*shutdown)(struct device *dev);
 };
 extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index c562b972a4a6..50c77eacbd5e 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -181,7 +181,8 @@
 #elif defined(CONFIG_ARCH_LUBBOCK) || \
      defined(CONFIG_MACH_LOGICPD_PXA270) || \
      defined(CONFIG_MACH_MAINSTONE) || \
-      defined(CONFIG_MACH_PCM027)
+      defined(CONFIG_MACH_PCM027) || \
+      defined(CONFIG_MACH_MAGICIAN)
 #define NR_IRQS                 (IRQ_BOARD_END)
 #else
 #define NR_IRQS                 (IRQ_BOARD_START)
diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h
index 337f51f06b3a..b34fd5683e2d 100644
--- a/include/asm-arm/arch-pxa/magician.h
+++ b/include/asm-arm/arch-pxa/magician.h
@@ -12,7 +12,8 @@
 #ifndef _MAGICIAN_H_
 #define _MAGICIAN_H_
-#include <asm/arch/pxa-regs.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 /*
 * PXA GPIOs
@@ -34,6 +35,7 @@
 #define GPIO48_MAGICIAN_UNKNOWN                 48
 #define GPIO56_MAGICIAN_UNKNOWN                 56
 #define GPIO57_MAGICIAN_CAM_RESET               57
+#define GPIO75_MAGICIAN_SAMSUNG_POWER           75
 #define GPIO83_MAGICIAN_nIR_EN                  83
 #define GPIO86_MAGICIAN_GSM_RESET               86
 #define GPIO87_MAGICIAN_GSM_SELECT              87
@@ -81,6 +83,7 @@
 #define GPIO48_MAGICIAN_UNKNOWN_MD              (48 | GPIO_OUT)
 #define GPIO56_MAGICIAN_UNKNOWN_MD              (56 | GPIO_OUT)
 #define GPIO57_MAGICIAN_CAM_RESET_MD            (57 | GPIO_OUT)
+#define GPIO75_MAGICIAN_SAMSUNG_POWER_MD        (75 | GPIO_OUT)
 #define GPIO83_MAGICIAN_nIR_EN_MD               (83 | GPIO_OUT)
 #define GPIO86_MAGICIAN_GSM_RESET_MD            (86 | GPIO_OUT)
 #define GPIO87_MAGICIAN_GSM_SELECT_MD           (87 | GPIO_OUT)
@@ -108,4 +111,56 @@
 #define GPIO119_MAGICIAN_UNKNOWN_MD             (119 | GPIO_OUT)
 #define GPIO120_MAGICIAN_UNKNOWN_MD             (120 | GPIO_OUT)
+/*
+ * CPLD IRQs
+ */
+#define IRQ_MAGICIAN_SD         (IRQ_BOARD_START + 0)
+#define IRQ_MAGICIAN_EP         (IRQ_BOARD_START + 1)
+#define IRQ_MAGICIAN_BT         (IRQ_BOARD_START + 2)
+#define IRQ_MAGICIAN_AC         (IRQ_BOARD_START + 3)
+/*
+ * CPLD EGPIOs
+ */
+#define MAGICIAN_EGPIO_BASE                     0x80 /* GPIO_BOARD_START */
+#define MAGICIAN_EGPIO(reg,bit) \
+        (MAGICIAN_EGPIO_BASE + 8*reg + bit)
+/* output */
+#define EGPIO_MAGICIAN_TOPPOLY_POWER            MAGICIAN_EGPIO(0, 2)
+#define EGPIO_MAGICIAN_LED_POWER                MAGICIAN_EGPIO(0, 5)
+#define EGPIO_MAGICIAN_GSM_RESET                MAGICIAN_EGPIO(0, 6)
+#define EGPIO_MAGICIAN_LCD_POWER                MAGICIAN_EGPIO(0, 7)
+#define EGPIO_MAGICIAN_SPK_POWER                MAGICIAN_EGPIO(1, 0)
+#define EGPIO_MAGICIAN_EP_POWER                 MAGICIAN_EGPIO(1, 1)
+#define EGPIO_MAGICIAN_IN_SEL0                  MAGICIAN_EGPIO(1, 2)
+#define EGPIO_MAGICIAN_IN_SEL1                  MAGICIAN_EGPIO(1, 3)
+#define EGPIO_MAGICIAN_MIC_POWER                MAGICIAN_EGPIO(1, 4)
+#define EGPIO_MAGICIAN_CODEC_RESET              MAGICIAN_EGPIO(1, 5)
+#define EGPIO_MAGICIAN_CODEC_POWER              MAGICIAN_EGPIO(1, 6)
+#define EGPIO_MAGICIAN_BL_POWER                 MAGICIAN_EGPIO(1, 7)
+#define EGPIO_MAGICIAN_SD_POWER                 MAGICIAN_EGPIO(2, 0)
+#define EGPIO_MAGICIAN_CARKIT_MIC               MAGICIAN_EGPIO(2, 1)
+#define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL      MAGICIAN_EGPIO(2, 2)
+#define EGPIO_MAGICIAN_FLASH_VPP                MAGICIAN_EGPIO(2, 3)
+#define EGPIO_MAGICIAN_BL_POWER2                MAGICIAN_EGPIO(2, 4)
+#define EGPIO_MAGICIAN_CHARGE_EN                MAGICIAN_EGPIO(2, 5)
+#define EGPIO_MAGICIAN_GSM_POWER                MAGICIAN_EGPIO(2, 7)
+/* input */
+#define EGPIO_MAGICIAN_CABLE_STATE_AC           MAGICIAN_EGPIO(4, 0)
+#define EGPIO_MAGICIAN_CABLE_STATE_USB          MAGICIAN_EGPIO(4, 1)
+#define EGPIO_MAGICIAN_BOARD_ID0                MAGICIAN_EGPIO(5, 0)
+#define EGPIO_MAGICIAN_BOARD_ID1                MAGICIAN_EGPIO(5, 1)
+#define EGPIO_MAGICIAN_BOARD_ID2                MAGICIAN_EGPIO(5, 2)
+#define EGPIO_MAGICIAN_LCD_SELECT               MAGICIAN_EGPIO(5, 3)
+#define EGPIO_MAGICIAN_nSD_READONLY             MAGICIAN_EGPIO(5, 4)
+#define EGPIO_MAGICIAN_EP_INSERT                MAGICIAN_EGPIO(6, 1)
 #endif /* _MAGICIAN_H_ */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa25x.h b/include/asm-arm/arch-pxa/mfp-pxa25x.h
new file mode 100644
index 000000000000..0499323010ba
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa25x.h
@@ -0,0 +1,161 @@
+#ifndef __ASM_ARCH_MFP_PXA25X_H
+#define __ASM_ARCH_MFP_PXA25X_H
+#include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa2xx.h>
+/* GPIO */
+#define GPIO2_GPIO              MFP_CFG_IN(GPIO2, AF0)
+#define GPIO3_GPIO              MFP_CFG_IN(GPIO3, AF0)
+#define GPIO4_GPIO              MFP_CFG_IN(GPIO4, AF0)
+#define GPIO5_GPIO              MFP_CFG_IN(GPIO5, AF0)
+#define GPIO6_GPIO              MFP_CFG_IN(GPIO6, AF0)
+#define GPIO7_GPIO              MFP_CFG_IN(GPIO7, AF0)
+#define GPIO8_GPIO              MFP_CFG_IN(GPIO8, AF0)
+#define GPIO1_RST               MFP_CFG_IN(GPIO1, AF1)
+/* Crystal and Clock Signals */
+#define GPIO10_RTCCLK           MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
+#define GPIO70_RTC_CLK          MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
+#define GPIO7_48MHz             MFP_CFG_OUT(GPIO7,  AF1, DRIVE_LOW)
+#define GPIO11_3_6MHz           MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
+#define GPIO71_3_6MHz           MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW)
+#define GPIO12_32KHz            MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
+#define GPIO72_32kHz            MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW)
+/* SDRAM and Static Memory I/O Signals */
+#define GPIO15_nCS_1            MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
+#define GPIO78_nCS_2            MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
+#define GPIO79_nCS_3            MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
+#define GPIO80_nCS_4            MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
+#define GPIO33_nCS_5            MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
+/* Miscellaneous I/O and DMA Signals */
+#define GPIO18_RDY              MFP_CFG_IN(GPIO18, AF1)
+#define GPIO20_DREQ_0           MFP_CFG_IN(GPIO20, AF1)
+#define GPIO19_DREQ_1           MFP_CFG_IN(GPIO19, AF1)
+/* Alternate Bus Master Mode I/O Signals */
+#define GPIO13_MBGNT            MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW)
+#define GPIO73_MBGNT            MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW)
+#define GPIO14_MBREQ            MFP_CFG_IN(GPIO14, AF1)
+#define GPIO66_MBREQ            MFP_CFG_IN(GPIO66, AF1)
+/* PC CARD */
+#define GPIO52_nPCE_1           MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH)
+#define GPIO53_nPCE_2           MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH)
+#define GPIO55_nPREG            MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
+#define GPIO50_nPIOR            MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
+#define GPIO51_nPIOW            MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
+#define GPIO49_nPWE             MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
+#define GPIO48_nPOE             MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
+#define GPIO57_nIOIS16          MFP_CFG_IN(GPIO57, AF1)
+#define GPIO56_nPWAIT           MFP_CFG_IN(GPIO56, AF1)
+#define GPIO54_nPSKTSEL         MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
+/* FFUART */
+#define GPIO34_FFUART_RXD       MFP_CFG_IN(GPIO34, AF1)
+#define GPIO35_FFUART_CTS       MFP_CFG_IN(GPIO35, AF1)
+#define GPIO36_FFUART_DCD       MFP_CFG_IN(GPIO36, AF1)
+#define GPIO37_FFUART_DSR       MFP_CFG_IN(GPIO37, AF1)
+#define GPIO38_FFUART_RI        MFP_CFG_IN(GPIO38, AF1)
+#define GPIO39_FFUART_TXD       MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
+#define GPIO40_FFUART_DTR       MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
+#define GPIO41_FFUART_RTS       MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
+/* BTUART */
+#define GPIO42_BTUART_RXD       MFP_CFG_IN(GPIO42, AF1)
+#define GPIO43_BTUART_TXD       MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+#define GPIO44_BTUART_CTS       MFP_CFG_IN(GPIO44, AF1)
+#define GPIO45_BTUART_RTS       MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+/* STUART */
+#define GPIO46_STUART_RXD       MFP_CFG_IN(GPIO46, AF2)
+#define GPIO47_STUART_TXD       MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
+/* HWUART */
+#define GPIO42_HWUART_RXD       MFP_CFG_IN(GPIO42, AF3)
+#define GPIO43_HWUART_TXD       MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH)
+#define GPIO44_HWUART_CTS       MFP_CFG_IN(GPIO44, AF3)
+#define GPIO45_HWUART_RTS       MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH)
+#define GPIO48_HWUART_TXD       MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH)
+#define GPIO49_HWUART_RXD       MFP_CFG_IN(GPIO49, AF1)
+#define GPIO50_HWUART_CTS       MFP_CFG_IN(GPIO50, AF1)
+#define GPIO51_HWUART_RTS       MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH)
+/* FICP */
+#define GPIO46_FICP_RXD         MFP_CFG_IN(GPIO46, AF1)
+#define GPIO47_FICP_TXD         MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
+/* PWM 0/1 */
+#define GPIO16_PWM0_OUT         MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
+#define GPIO17_PWM1_OUT         MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
+/* AC97 */
+#define GPIO28_AC97_BITCLK      MFP_CFG_IN(GPIO28, AF1)
+#define GPIO29_AC97_SDATA_IN_0  MFP_CFG_IN(GPIO29, AF1)
+#define GPIO30_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
+#define GPIO31_AC97_SYNC        MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
+#define GPIO32_AC97_SDATA_IN_1  MFP_CFG_IN(GPIO32, AF1)
+/* I2S */
+#define GPIO28_I2S_BITCLK_IN    MFP_CFG_IN(GPIO28, AF2)
+#define GPIO28_I2S_BITCLK_OUT   MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
+#define GPIO29_I2S_SDATA_IN     MFP_CFG_IN(GPIO29, AF2)
+#define GPIO30_I2S_SDATA_OUT    MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
+#define GPIO31_I2S_SYNC         MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
+#define GPIO32_I2S_SYSCLK       MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
+/* SSP 1 */
+#define GPIO23_SSP1_SCLK        MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
+#define GPIO24_SSP1_SFRM        MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW)
+#define GPIO25_SSP1_TXD         MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
+#define GPIO26_SSP1_RXD         MFP_CFG_IN(GPIO26, AF1)
+#define GPIO27_SSP1_EXTCLK      MFP_CFG_IN(GPIO27, AF1)
+/* SSP 2 - NSSP */
+#define GPIO81_SSP2_CLK_OUT     MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
+#define GPIO81_SSP2_CLK_IN      MFP_CFG_IN(GPIO81, AF1)
+#define GPIO82_SSP2_FRM_OUT     MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW)
+#define GPIO82_SSP2_FRM_IN      MFP_CFG_IN(GPIO82, AF1)
+#define GPIO83_SSP2_TXD         MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW)
+#define GPIO83_SSP2_RXD         MFP_CFG_IN(GPIO83, AF2)
+#define GPIO84_SSP2_TXD         MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW)
+#define GPIO84_SSP2_RXD         MFP_CFG_IN(GPIO84, AF2)
+/* MMC */
+#define GPIO6_MMC_CLK           MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW)
+#define GPIO8_MMC_CS0           MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW)
+#define GPIO9_MMC_CS1           MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW)
+#define GPIO34_MMC_CS0          MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW)
+#define GPIO39_MMC_CS1          MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
+#define GPIO53_MMC_CLK          MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
+#define GPIO54_MMC_CLK          MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW)
+#define GPIO69_MMC_CLK          MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW)
+#define GPIO67_MMC_CS0          MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW)
+#define GPIO68_MMC_CS1          MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW)
+/* LCD */
+#define GPIO58_LCD_LDD_0        MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
+#define GPIO59_LCD_LDD_1        MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
+#define GPIO60_LCD_LDD_2        MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
+#define GPIO61_LCD_LDD_3        MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
+#define GPIO62_LCD_LDD_4        MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
+#define GPIO63_LCD_LDD_5        MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
+#define GPIO64_LCD_LDD_6        MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
+#define GPIO65_LCD_LDD_7        MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
+#define GPIO66_LCD_LDD_8        MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
+#define GPIO67_LCD_LDD_9        MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
+#define GPIO68_LCD_LDD_10       MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
+#define GPIO69_LCD_LDD_11       MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
+#define GPIO70_LCD_LDD_12       MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
+#define GPIO71_LCD_LDD_13       MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
+#define GPIO72_LCD_LDD_14       MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
+#define GPIO73_LCD_LDD_15       MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
+#define GPIO74_LCD_FCLK         MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
+#define GPIO75_LCD_LCLK         MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
+#define GPIO76_LCD_PCLK         MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
+#define GPIO77_LCD_ACBIAS       MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
+#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa27x.h b/include/asm-arm/arch-pxa/mfp-pxa27x.h
new file mode 100644
index 000000000000..eb6eaa174f8d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa27x.h
@@ -0,0 +1,432 @@
+#ifndef __ASM_ARCH_MFP_PXA27X_H
+#define __ASM_ARCH_MFP_PXA27X_H
+/*
+ * NOTE:  for those special-function bidirectional GPIOs, as described
+ * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input
+ * alternative is preserved, the direction is actually selected by the
+ * specific controller, and this should work in most cases.
+ */
+#include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa2xx.h>
+/* GPIO */
+#define GPIO85_GPIO             MFP_CFG_IN(GPIO85, AF0)
+#define GPIO86_GPIO             MFP_CFG_IN(GPIO86, AF0)
+#define GPIO87_GPIO             MFP_CFG_IN(GPIO87, AF0)
+#define GPIO88_GPIO             MFP_CFG_IN(GPIO88, AF0)
+#define GPIO89_GPIO             MFP_CFG_IN(GPIO89, AF0)
+#define GPIO90_GPIO             MFP_CFG_IN(GPIO90, AF0)
+#define GPIO91_GPIO             MFP_CFG_IN(GPIO91, AF0)
+#define GPIO92_GPIO             MFP_CFG_IN(GPIO92, AF0)
+#define GPIO93_GPIO             MFP_CFG_IN(GPIO93, AF0)
+#define GPIO94_GPIO             MFP_CFG_IN(GPIO94, AF0)
+#define GPIO95_GPIO             MFP_CFG_IN(GPIO95, AF0)
+#define GPIO96_GPIO             MFP_CFG_IN(GPIO96, AF0)
+#define GPIO97_GPIO             MFP_CFG_IN(GPIO97, AF0)
+#define GPIO98_GPIO             MFP_CFG_IN(GPIO98, AF0)
+#define GPIO99_GPIO             MFP_CFG_IN(GPIO99, AF0)
+#define GPIO100_GPIO            MFP_CFG_IN(GPIO100, AF0)
+#define GPIO101_GPIO            MFP_CFG_IN(GPIO101, AF0)
+#define GPIO102_GPIO            MFP_CFG_IN(GPIO102, AF0)
+#define GPIO103_GPIO            MFP_CFG_IN(GPIO103, AF0)
+#define GPIO104_GPIO            MFP_CFG_IN(GPIO104, AF0)
+#define GPIO105_GPIO            MFP_CFG_IN(GPIO105, AF0)
+#define GPIO106_GPIO            MFP_CFG_IN(GPIO106, AF0)
+#define GPIO107_GPIO            MFP_CFG_IN(GPIO107, AF0)
+#define GPIO108_GPIO            MFP_CFG_IN(GPIO108, AF0)
+#define GPIO109_GPIO            MFP_CFG_IN(GPIO109, AF0)
+#define GPIO110_GPIO            MFP_CFG_IN(GPIO110, AF0)
+#define GPIO111_GPIO            MFP_CFG_IN(GPIO111, AF0)
+#define GPIO112_GPIO            MFP_CFG_IN(GPIO112, AF0)
+#define GPIO113_GPIO            MFP_CFG_IN(GPIO113, AF0)
+#define GPIO114_GPIO            MFP_CFG_IN(GPIO114, AF0)
+#define GPIO115_GPIO            MFP_CFG_IN(GPIO115, AF0)
+#define GPIO116_GPIO            MFP_CFG_IN(GPIO116, AF0)
+#define GPIO117_GPIO            MFP_CFG_IN(GPIO117, AF0)
+#define GPIO118_GPIO            MFP_CFG_IN(GPIO118, AF0)
+#define GPIO119_GPIO            MFP_CFG_IN(GPIO119, AF0)
+#define GPIO120_GPIO            MFP_CFG_IN(GPIO120, AF0)
+/* Crystal and Clock Signals */
+#define GPIO9_HZ_CLK            MFP_CFG_OUT(GPIO9,  AF1, DRIVE_LOW)
+#define GPIO10_HZ_CLK           MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
+#define GPIO11_48_MHz           MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW)
+#define GPIO12_48_MHz           MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW)
+#define GPIO13_CLK_EXT          MFP_CFG_IN(GPIO13, AF1)
+/* OS Timer Signals */
+#define GPIO11_EXT_SYNC_0       MFP_CFG_IN(GPIO11, AF1)
+#define GPIO12_EXT_SYNC_1       MFP_CFG_IN(GPIO12, AF1)
+#define GPIO9_CHOUT_0           MFP_CFG_OUT(GPIO9,  AF3, DRIVE_LOW)
+#define GPIO10_CHOUT_1          MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW)
+#define GPIO11_CHOUT_0          MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
+#define GPIO12_CHOUT_1          MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
+/* SDRAM and Static Memory I/O Signals */
+#define GPIO20_nSDCS_2          MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH)
+#define GPIO21_nSDCS_3          MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH)
+#define GPIO15_nCS_1            MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
+#define GPIO78_nCS_2            MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
+#define GPIO79_nCS_3            MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
+#define GPIO80_nCS_4            MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
+#define GPIO33_nCS_5            MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
+/* Miscellaneous I/O and DMA Signals */
+#define GPIO21_DVAL_0           MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH)
+#define GPIO116_DVAL_0          MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH)
+#define GPIO33_DVAL_1           MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH)
+#define GPIO96_DVAL_1           MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH)
+#define GPIO18_RDY              MFP_CFG_IN(GPIO18, AF1)
+#define GPIO20_DREQ_0           MFP_CFG_IN(GPIO20, AF1)
+#define GPIO115_DREQ_0          MFP_CFG_IN(GPIO115, AF1)
+#define GPIO80_DREQ_1           MFP_CFG_IN(GPIO80, AF1)
+#define GPIO97_DREQ_1           MFP_CFG_IN(GPIO97, AF2)
+#define GPIO85_DREQ_2           MFP_CFG_IN(GPIO85, AF2)
+#define GPIO100_DREQ_2          MFP_CFG_IN(GPIO100, AF2)
+/* Alternate Bus Master Mode I/O Signals */
+#define GPIO20_MBREQ            MFP_CFG_IN(GPIO20, AF2)
+#define GPIO80_MBREQ            MFP_CFG_IN(GPIO80, AF2)
+#define GPIO96_MBREQ            MFP_CFG_IN(GPIO96, AF2)
+#define GPIO115_MBREQ           MFP_CFG_IN(GPIO115, AF3)
+#define GPIO21_MBGNT            MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW)
+#define GPIO33_MBGNT            MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW)
+#define GPIO97_MBGNT            MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW)
+#define GPIO116_MBGNT           MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW)
+/* PC CARD */
+#define GPIO15_nPCE_1           MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH)
+#define GPIO85_nPCE_1           MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH)
+#define GPIO86_nPCE_1           MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH)
+#define GPIO102_nPCE_1          MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH)
+#define GPIO54_nPCE_2           MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
+#define GPIO78_nPCE_2           MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH)
+#define GPIO87_nPCE_2           MFP_CFG_IN(GPIO87, AF1)
+#define GPIO55_nPREG            MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
+#define GPIO50_nPIOR            MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
+#define GPIO51_nPIOW            MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
+#define GPIO49_nPWE             MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
+#define GPIO48_nPOE             MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
+#define GPIO57_nIOIS16          MFP_CFG_IN(GPIO57, AF1)
+#define GPIO56_nPWAIT           MFP_CFG_IN(GPIO56, AF1)
+#define GPIO79_PSKTSEL          MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH)
+/* I2C */
+#define GPIO117_I2C_SCL         MFP_CFG_IN(GPIO117, AF1)
+#define GPIO118_I2C_SDA         MFP_CFG_IN(GPIO118, AF1)
+/* FFUART */
+#define GPIO9_FFUART_CTS        MFP_CFG_IN(GPIO9, AF3)
+#define GPIO26_FFUART_CTS       MFP_CFG_IN(GPIO26, AF3)
+#define GPIO35_FFUART_CTS       MFP_CFG_IN(GPIO35, AF1)
+#define GPIO100_FFUART_CTS      MFP_CFG_IN(GPIO100, AF3)
+#define GPIO10_FFUART_DCD       MFP_CFG_IN(GPIO10, AF1)
+#define GPIO36_FFUART_DCD       MFP_CFG_IN(GPIO36, AF1)
+#define GPIO33_FFUART_DSR       MFP_CFG_IN(GPIO33, AF2)
+#define GPIO37_FFUART_DSR       MFP_CFG_IN(GPIO37, AF1)
+#define GPIO38_FFUART_RI        MFP_CFG_IN(GPIO38, AF1)
+#define GPIO89_FFUART_RI        MFP_CFG_IN(GPIO89, AF3)
+#define GPIO19_FFUART_RXD       MFP_CFG_IN(GPIO19, AF3)
+#define GPIO33_FFUART_RXD       MFP_CFG_IN(GPIO33, AF1)
+#define GPIO34_FFUART_RXD       MFP_CFG_IN(GPIO34, AF1)
+#define GPIO41_FFUART_RXD       MFP_CFG_IN(GPIO41, AF1)
+#define GPIO53_FFUART_RXD       MFP_CFG_IN(GPIO53, AF1)
+#define GPIO85_FFUART_RXD       MFP_CFG_IN(GPIO85, AF1)
+#define GPIO96_FFUART_RXD       MFP_CFG_IN(GPIO96, AF3)
+#define GPIO102_FFUART_RXD      MFP_CFG_IN(GPIO102, AF3)
+#define GPIO16_FFUART_TXD       MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH)
+#define GPIO37_FFUART_TXD       MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH)
+#define GPIO39_FFUART_TXD       MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
+#define GPIO83_FFUART_TXD       MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH)
+#define GPIO99_FFUART_TXD       MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH)
+#define GPIO27_FFUART_RTS       MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH)
+#define GPIO41_FFUART_RTS       MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
+#define GPIO83_FFUART_RTS       MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH)
+#define GPIO98_FFUART_RTS       MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH)
+#define GPIO40_FFUART_DTR       MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
+#define GPIO82_FFUART_DTR       MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH)
+/* BTUART */
+#define GPIO44_BTUART_CTS       MFP_CFG_IN(GPIO44, AF1)
+#define GPIO42_BTUART_RXD       MFP_CFG_IN(GPIO42, AF1)
+#define GPIO45_BTUART_RTS       MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+#define GPIO43_BTUART_TXD       MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+/* STUART */
+#define GPIO46_STUART_RXD       MFP_CFG_IN(GPIO46, AF2)
+#define GPIO47_STUART_TXD       MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
+/* FICP */
+#define GPIO42_FICP_RXD         MFP_CFG_IN(GPIO42, AF2)
+#define GPIO46_FICP_RXD         MFP_CFG_IN(GPIO46, AF1)
+#define GPIO43_FICP_TXD         MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH)
+#define GPIO47_FICP_TXD         MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
+/* PWM 0/1/2/3 */
+#define GPIO11_PWM2_OUT         MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW)
+#define GPIO12_PWM3_OUT         MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW)
+#define GPIO16_PWM0_OUT         MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
+#define GPIO17_PWM1_OUT         MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
+#define GPIO38_PWM1_OUT         MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW)
+#define GPIO46_PWM2_OUT         MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW)
+#define GPIO47_PWM3_OUT         MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW)
+#define GPIO79_PWM2_OUT         MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW)
+#define GPIO80_PWM3_OUT         MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW)
+#define GPIO115_PWM1_OUT        MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW)
+/* AC97 */
+#define GPIO31_AC97_SYNC        MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
+#define GPIO94_AC97_SYNC        MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW)
+#define GPIO30_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
+#define GPIO93_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW)
+#define GPIO45_AC97_SYSCLK      MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW)
+#define GPIO89_AC97_SYSCLK      MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW)
+#define GPIO98_AC97_SYSCLK      MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW)
+#define GPIO95_AC97_nRESET      MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW)
+#define GPIO113_AC97_nRESET     MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW)
+#define GPIO28_AC97_BITCLK      MFP_CFG_IN(GPIO28, AF1)
+#define GPIO29_AC97_SDATA_IN_0  MFP_CFG_IN(GPIO29, AF1)
+#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2)
+#define GPIO99_AC97_SDATA_IN_1  MFP_CFG_IN(GPIO99, AF2)
+/* I2S */
+#define GPIO28_I2S_BITCLK_IN    MFP_CFG_IN(GPIO28, AF2)
+#define GPIO28_I2S_BITCLK_OUT   MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
+#define GPIO29_I2S_SDATA_IN     MFP_CFG_IN(GPIO29, AF2)
+#define GPIO30_I2S_SDATA_OUT    MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
+#define GPIO31_I2S_SYNC         MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
+#define GPIO113_I2S_SYSCLK      MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW)
+/* SSP 1 */
+#define GPIO23_SSP1_SCLK        MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
+#define GPIO29_SSP1_SCLK        MFP_CFG_IN(GPIO29, AF3)
+#define GPIO27_SSP1_SYSCLK      MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW)
+#define GPIO53_SSP1_SYSCLK      MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW)
+#define GPIO24_SSP1_SFRM        MFP_CFG_IN(GPIO24, AF2)
+#define GPIO28_SSP1_SFRM        MFP_CFG_IN(GPIO28, AF3)
+#define GPIO25_SSP1_TXD         MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
+#define GPIO57_SSP1_TXD         MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW)
+#define GPIO26_SSP1_RXD         MFP_CFG_IN(GPIO26, AF1)
+#define GPIO27_SSP1_SCLKEN      MFP_CFG_IN(GPIO27, AF2)
+/* SSP 2 */
+#define GPIO19_SSP2_SCLK        MFP_CFG_IN(GPIO19, AF1)
+#define GPIO22_SSP2_SCLK        MFP_CFG_IN(GPIO22, AF3)
+#define GPIO29_SSP2_SCLK        MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW)
+#define GPIO36_SSP2_SCLK        MFP_CFG_IN(GPIO36, AF2)
+#define GPIO50_SSP2_SCLK        MFP_CFG_IN(GPIO50, AF3)
+#define GPIO22_SSP2_SYSCLK      MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW)
+#define GPIO14_SSP2_SFRM        MFP_CFG_IN(GPIO14, AF2)
+#define GPIO37_SSP2_SFRM        MFP_CFG_IN(GPIO37, AF2)
+#define GPIO87_SSP2_SFRM        MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW)
+#define GPIO88_SSP2_SFRM        MFP_CFG_IN(GPIO88, AF3)
+#define GPIO13_SSP2_TXD         MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW)
+#define GPIO38_SSP2_TXD         MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW)
+#define GPIO87_SSP2_TXD         MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW)
+#define GPIO89_SSP2_TXD         MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW)
+#define GPIO11_SSP2_RXD         MFP_CFG_IN(GPIO11, AF2)
+#define GPIO29_SSP2_RXD         MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW)
+#define GPIO40_SSP2_RXD         MFP_CFG_IN(GPIO40, AF1)
+#define GPIO86_SSP2_RXD         MFP_CFG_IN(GPIO86, AF1)
+#define GPIO88_SSP2_RXD         MFP_CFG_IN(GPIO88, AF2)
+#define GPIO22_SSP2_EXTCLK      MFP_CFG_IN(GPIO22, AF1)
+#define GPIO27_SSP2_EXTCLK      MFP_CFG_IN(GPIO27, AF1)
+#define GPIO22_SSP2_SCLKEN      MFP_CFG_IN(GPIO22, AF2)
+#define GPIO23_SSP2_SCLKEN      MFP_CFG_IN(GPIO23, AF2)
+/* SSP 3 */
+#define GPIO34_SSP3_SCLK        MFP_CFG_IN(GPIO34, AF3)
+#define GPIO40_SSP3_SCLK        MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW)
+#define GPIO52_SSP3_SCLK        MFP_CFG_IN(GPIO52, AF2)
+#define GPIO84_SSP3_SCLK        MFP_CFG_IN(GPIO84, AF1)
+#define GPIO45_SSP3_SYSCLK      MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW)
+#define GPIO35_SSP3_SFRM        MFP_CFG_IN(GPIO35, AF3)
+#define GPIO39_SSP3_SFRM        MFP_CFG_IN(GPIO39, AF3)
+#define GPIO83_SSP3_SFRM        MFP_CFG_IN(GPIO83, AF1)
+#define GPIO35_SSP3_TXD         MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW)
+#define GPIO38_SSP3_TXD         MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW)
+#define GPIO81_SSP3_TXD         MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
+#define GPIO41_SSP3_RXD         MFP_CFG_IN(GPIO41, AF3)
+#define GPIO82_SSP3_RXD         MFP_CFG_IN(GPIO82, AF1)
+#define GPIO89_SSP3_RXD         MFP_CFG_IN(GPIO89, AF1)
+/* MMC */
+#define GPIO32_MMC_CLK          MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW)
+#define GPIO92_MMC_DAT_0        MFP_CFG_IN(GPIO92, AF1)
+#define GPIO109_MMC_DAT_1       MFP_CFG_IN(GPIO109, AF1)
+#define GPIO110_MMC_DAT_2       MFP_CFG_IN(GPIO110, AF1)
+#define GPIO111_MMC_DAT_3       MFP_CFG_IN(GPIO111, AF1)
+#define GPIO112_MMC_CMD         MFP_CFG_IN(GPIO112, AF1)
+/* LCD */
+#define GPIO58_LCD_LDD_0        MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
+#define GPIO59_LCD_LDD_1        MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
+#define GPIO60_LCD_LDD_2        MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
+#define GPIO61_LCD_LDD_3        MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
+#define GPIO62_LCD_LDD_4        MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
+#define GPIO63_LCD_LDD_5        MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
+#define GPIO64_LCD_LDD_6        MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
+#define GPIO65_LCD_LDD_7        MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
+#define GPIO66_LCD_LDD_8        MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
+#define GPIO67_LCD_LDD_9        MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
+#define GPIO68_LCD_LDD_10       MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
+#define GPIO69_LCD_LDD_11       MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
+#define GPIO70_LCD_LDD_12       MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
+#define GPIO71_LCD_LDD_13       MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
+#define GPIO72_LCD_LDD_14       MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
+#define GPIO73_LCD_LDD_15       MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
+#define GPIO86_LCD_LDD_16       MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW)
+#define GPIO87_LCD_LDD_17       MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW)
+#define GPIO74_LCD_FCLK         MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
+#define GPIO75_LCD_LCLK         MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
+#define GPIO76_LCD_PCLK         MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
+#define GPIO77_LCD_BIAS         MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
+#define GPIO14_LCD_VSYNC        MFP_CFG_IN(GPIO14, AF1)
+#define GPIO19_LCD_CS           MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW)
+/* Keypad */
+#define GPIO93_KP_DKIN_0        MFP_CFG_IN(GPIO93, AF1)
+#define GPIO94_KP_DKIN_1        MFP_CFG_IN(GPIO94, AF1)
+#define GPIO95_KP_DKIN_2        MFP_CFG_IN(GPIO95, AF1)
+#define GPIO96_KP_DKIN_3        MFP_CFG_IN(GPIO96, AF1)
+#define GPIO97_KP_DKIN_4        MFP_CFG_IN(GPIO97, AF1)
+#define GPIO98_KP_DKIN_5        MFP_CFG_IN(GPIO98, AF1)
+#define GPIO99_KP_DKIN_6        MFP_CFG_IN(GPIO99, AF1)
+#define GPIO13_KP_KDIN_7        MFP_CFG_IN(GPIO13, AF2)
+#define GPIO100_KP_MKIN_0       MFP_CFG_IN(GPIO100, AF1)
+#define GPIO101_KP_MKIN_1       MFP_CFG_IN(GPIO101, AF1)
+#define GPIO102_KP_MKIN_2       MFP_CFG_IN(GPIO102, AF1)
+#define GPIO34_KP_MKIN_3        MFP_CFG_IN(GPIO34, AF2)
+#define GPIO37_KP_MKIN_3        MFP_CFG_IN(GPIO37, AF3)
+#define GPIO97_KP_MKIN_3        MFP_CFG_IN(GPIO97, AF3)
+#define GPIO98_KP_MKIN_4        MFP_CFG_IN(GPIO98, AF3)
+#define GPIO38_KP_MKIN_4        MFP_CFG_IN(GPIO38, AF2)
+#define GPIO39_KP_MKIN_4        MFP_CFG_IN(GPIO39, AF1)
+#define GPIO16_KP_MKIN_5        MFP_CFG_IN(GPIO16, AF1)
+#define GPIO90_KP_MKIN_5        MFP_CFG_IN(GPIO90, AF1)
+#define GPIO99_KP_MKIN_5        MFP_CFG_IN(GPIO99, AF3)
+#define GPIO17_KP_MKIN_6        MFP_CFG_IN(GPIO17, AF1)
+#define GPIO91_KP_MKIN_6        MFP_CFG_IN(GPIO91, AF1)
+#define GPIO95_KP_MKIN_6        MFP_CFG_IN(GPIO95, AF3)
+#define GPIO13_KP_MKIN_7        MFP_CFG_IN(GPIO13, AF3)
+#define GPIO36_KP_MKIN_7        MFP_CFG_IN(GPIO36, AF3)
+#define GPIO103_KP_MKOUT_0      MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH)
+#define GPIO104_KP_MKOUT_1      MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH)
+#define GPIO105_KP_MKOUT_2      MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH)
+#define GPIO106_KP_MKOUT_3      MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH)
+#define GPIO107_KP_MKOUT_4      MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH)
+#define GPIO108_KP_MKOUT_5      MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH)
+#define GPIO35_KP_MKOUT_6       MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH)
+#define GPIO22_KP_MKOUT_7       MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH)
+#define GPIO40_KP_MKOUT_6       MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH)
+#define GPIO41_KP_MKOUT_7       MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH)
+#define GPIO96_KP_MKOUT_6       MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH)
+/* USB P3 */
+#define GPIO10_USB_P3_5         MFP_CFG_IN(GPIO10, AF3)
+#define GPIO11_USB_P3_1         MFP_CFG_IN(GPIO11, AF3)
+#define GPIO30_USB_P3_2         MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
+#define GPIO31_USB_P3_6         MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
+#define GPIO56_USB_P3_4         MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
+#define GPIO86_USB_P3_5         MFP_CFG_IN(GPIO86, AF3)
+#define GPIO87_USB_P3_1         MFP_CFG_IN(GPIO87, AF3)
+#define GPIO90_USB_P3_5         MFP_CFG_IN(GPIO90, AF2)
+#define GPIO91_USB_P3_1         MFP_CFG_IN(GPIO91, AF2)
+#define GPIO113_USB_P3_3        MFP_CFG_IN(GPIO113, AF3)
+/* USB P2 */
+#define GPIO34_USB_P2_2         MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW)
+#define GPIO35_USB_P2_1         MFP_CFG_IN(GPIO35, AF2)
+#define GPIO36_USB_P2_4         MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW)
+#define GPIO37_USB_P2_8         MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW)
+#define GPIO38_USB_P2_3         MFP_CFG_IN(GPIO38, AF3)
+#define GPIO39_USB_P2_6         MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
+#define GPIO40_USB_P2_5         MFP_CFG_IN(GPIO40, AF3)
+#define GPIO41_USB_P2_7         MFP_CFG_IN(GPIO41, AF2)
+#define GPIO53_USB_P2_3         MFP_CFG_IN(GPIO53, AF2)
+/* USB Host Port 1/2 */
+#define GPIO88_USBH1_PWR        MFP_CFG_IN(GPIO88, AF1)
+#define GPIO89_USBH1_PEN        MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW)
+#define GPIO119_USBH2_PWR       MFP_CFG_IN(GPIO119, AF1)
+#define GPIO120_USBH2_PEN       MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW)
+/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */
+#define GPIO115_CIF_DD_3        MFP_CFG_IN(GPIO115, AF2)
+#define GPIO116_CIF_DD_2        MFP_CFG_IN(GPIO116, AF1)
+#define GPIO12_CIF_DD_7         MFP_CFG_IN(GPIO12, AF2)
+#define GPIO17_CIF_DD_6         MFP_CFG_IN(GPIO17, AF2)
+#define GPIO23_CIF_MCLK         MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW)
+#define GPIO24_CIF_FV           MFP_CFG_IN(GPIO24, AF1)
+#define GPIO25_CIF_LV           MFP_CFG_IN(GPIO25, AF1)
+#define GPIO26_CIF_PCLK         MFP_CFG_IN(GPIO26, AF2)
+#define GPIO27_CIF_DD_0         MFP_CFG_IN(GPIO27, AF3)
+#define GPIO42_CIF_MCLK         MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW)
+#define GPIO43_CIF_FV           MFP_CFG_IN(GPIO43, AF3)
+#define GPIO44_CIF_LV           MFP_CFG_IN(GPIO44, AF3)
+#define GPIO45_CIF_PCLK         MFP_CFG_IN(GPIO45, AF3)
+#define GPIO47_CIF_DD_0         MFP_CFG_IN(GPIO47, AF1)
+#define GPIO48_CIF_DD_5         MFP_CFG_IN(GPIO48, AF1)
+#define GPIO50_CIF_DD_3         MFP_CFG_IN(GPIO50, AF1)
+#define GPIO51_CIF_DD_2         MFP_CFG_IN(GPIO51, AF1)
+#define GPIO52_CIF_DD_4         MFP_CFG_IN(GPIO52, AF1)
+#define GPIO53_CIF_MCLK         MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW)
+#define GPIO54_CIF_PCLK         MFP_CFG_IN(GPIO54, AF3)
+#define GPIO55_CIF_DD_1         MFP_CFG_IN(GPIO55, AF1)
+#define GPIO81_CIF_DD_0         MFP_CFG_IN(GPIO81, AF2)
+#define GPIO82_CIF_DD_5         MFP_CFG_IN(GPIO82, AF3)
+#define GPIO83_CIF_DD_4         MFP_CFG_IN(GPIO83, AF3)
+#define GPIO84_CIF_FV           MFP_CFG_IN(GPIO84, AF3)
+#define GPIO85_CIF_LV           MFP_CFG_IN(GPIO85, AF3)
+#define GPIO90_CIF_DD_4         MFP_CFG_IN(GPIO90, AF3)
+#define GPIO91_CIF_DD_5         MFP_CFG_IN(GPIO91, AF3)
+#define GPIO93_CIF_DD_6         MFP_CFG_IN(GPIO93, AF2)
+#define GPIO94_CIF_DD_5         MFP_CFG_IN(GPIO94, AF2)
+#define GPIO95_CIF_DD_4         MFP_CFG_IN(GPIO95, AF2)
+#define GPIO98_CIF_DD_0         MFP_CFG_IN(GPIO98, AF2)
+#define GPIO103_CIF_DD_3        MFP_CFG_IN(GPIO103, AF1)
+#define GPIO104_CIF_DD_2        MFP_CFG_IN(GPIO104, AF1)
+#define GPIO105_CIF_DD_1        MFP_CFG_IN(GPIO105, AF1)
+#define GPIO106_CIF_DD_9        MFP_CFG_IN(GPIO106, AF1)
+#define GPIO107_CIF_DD_8        MFP_CFG_IN(GPIO107, AF1)
+#define GPIO108_CIF_DD_7        MFP_CFG_IN(GPIO108, AF1)
+#define GPIO114_CIF_DD_1        MFP_CFG_IN(GPIO114, AF1)
+/* Universal Subscriber ID Interface */
+#define GPIO114_UVS0            MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW)
+#define GPIO115_nUVS1           MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW)
+#define GPIO116_nUVS2           MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW)
+#define GPIO14_UCLK             MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW)
+#define GPIO91_UCLK             MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW)
+#define GPIO19_nURST            MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW)
+#define GPIO90_nURST            MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW)
+#define GPIO116_UDET            MFP_CFG_IN(GPIO116, AF3)
+#define GPIO114_UEN             MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW)
+#define GPIO115_UEN             MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW)
+/* Mobile Scalable Link (MSL) Interface */
+#define GPIO81_BB_OB_DAT_0      MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW)
+#define GPIO48_BB_OB_DAT_1      MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW)
+#define GPIO50_BB_OB_DAT_2      MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW)
+#define GPIO51_BB_OB_DAT_3      MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW)
+#define GPIO52_BB_OB_CLK        MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW)
+#define GPIO53_BB_OB_STB        MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
+#define GPIO54_BB_OB_WAIT       MFP_CFG_IN(GPIO54, AF2)
+#define GPIO82_BB_IB_DAT_0      MFP_CFG_IN(GPIO82, AF2)
+#define GPIO55_BB_IB_DAT_1      MFP_CFG_IN(GPIO55, AF2)
+#define GPIO56_BB_IB_DAT_2      MFP_CFG_IN(GPIO56, AF2)
+#define GPIO57_BB_IB_DAT_3      MFP_CFG_IN(GPIO57, AF2)
+#define GPIO83_BB_IB_CLK        MFP_CFG_IN(GPIO83, AF2)
+#define GPIO84_BB_IB_STB        MFP_CFG_IN(GPIO84, AF2)
+#define GPIO85_BB_IB_WAIT       MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW)
+/* Memory Stick Host Controller */
+#define GPIO92_MSBS             MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW)
+#define GPIO109_MSSDIO          MFP_CFG_IN(GPIO109, AF2)
+#define GPIO112_nMSINS          MFP_CFG_IN(GPIO112, AF2)
+#define GPIO32_MSSCLK           MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
+extern int keypad_set_wake(unsigned int on);
+#endif /* __ASM_ARCH_MFP_PXA27X_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa2xx.h b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
new file mode 100644
index 000000000000..db8d890d237c
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
@@ -0,0 +1,132 @@
+#ifndef __ASM_ARCH_MFP_PXA2XX_H
+#define __ASM_ARCH_MFP_PXA2XX_H
+#include <asm/arch/mfp.h>
+/*
+ * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
+ *
+ *  MFP_PIN(x)
+ *  MFP_AFx
+ *  MFP_LPM_DRIVE_{LOW, HIGH}
+ *  MFP_LPM_EDGE_x
+ *
+ * other MFP_x bit definitions will be ignored
+ *
+ * and adds the below two bits specifically for pxa2xx:
+ *
+ * bit     23 - Input/Output (PXA2xx specific)
+ * bit     24 - Wakeup Enable(PXA2xx specific)
+ */
+#define MFP_DIR_IN              (0x0 << 23)
+#define MFP_DIR_OUT             (0x1 << 23)
+#define MFP_DIR_MASK            (0x1 << 23)
+#define MFP_DIR(x)              (((x) >> 23) & 0x1)
+#define MFP_LPM_CAN_WAKEUP      (0x1 << 24)
+#define WAKEUP_ON_EDGE_RISE     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
+#define WAKEUP_ON_EDGE_FALL     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
+#define WAKEUP_ON_EDGE_BOTH     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
+/* specifically for enabling wakeup on keypad GPIOs */
+#define WAKEUP_ON_LEVEL_HIGH    (MFP_LPM_CAN_WAKEUP)
+#define MFP_CFG_IN(pin, af)             \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN))
+/* NOTE:  pins configured as output _must_ provide a low power state,
+ * and this state should help to minimize the power dissipation.
+ */
+#define MFP_CFG_OUT(pin, af, state)     \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
+/* Common configurations for pxa25x and pxa27x
+ *
+ * Note: pins configured as GPIO are always initialized to input
+ * so not to cause any side effect
+ */
+#define GPIO0_GPIO      MFP_CFG_IN(GPIO0, AF0)
+#define GPIO1_GPIO      MFP_CFG_IN(GPIO1, AF0)
+#define GPIO9_GPIO      MFP_CFG_IN(GPIO9, AF0)
+#define GPIO10_GPIO     MFP_CFG_IN(GPIO10, AF0)
+#define GPIO11_GPIO     MFP_CFG_IN(GPIO11, AF0)
+#define GPIO12_GPIO     MFP_CFG_IN(GPIO12, AF0)
+#define GPIO13_GPIO     MFP_CFG_IN(GPIO13, AF0)
+#define GPIO14_GPIO     MFP_CFG_IN(GPIO14, AF0)
+#define GPIO15_GPIO     MFP_CFG_IN(GPIO15, AF0)
+#define GPIO16_GPIO     MFP_CFG_IN(GPIO16, AF0)
+#define GPIO17_GPIO     MFP_CFG_IN(GPIO17, AF0)
+#define GPIO18_GPIO     MFP_CFG_IN(GPIO18, AF0)
+#define GPIO19_GPIO     MFP_CFG_IN(GPIO19, AF0)
+#define GPIO20_GPIO     MFP_CFG_IN(GPIO20, AF0)
+#define GPIO21_GPIO     MFP_CFG_IN(GPIO21, AF0)
+#define GPIO22_GPIO     MFP_CFG_IN(GPIO22, AF0)
+#define GPIO23_GPIO     MFP_CFG_IN(GPIO23, AF0)
+#define GPIO24_GPIO     MFP_CFG_IN(GPIO24, AF0)
+#define GPIO25_GPIO     MFP_CFG_IN(GPIO25, AF0)
+#define GPIO26_GPIO     MFP_CFG_IN(GPIO26, AF0)
+#define GPIO27_GPIO     MFP_CFG_IN(GPIO27, AF0)
+#define GPIO28_GPIO     MFP_CFG_IN(GPIO28, AF0)
+#define GPIO29_GPIO     MFP_CFG_IN(GPIO29, AF0)
+#define GPIO30_GPIO     MFP_CFG_IN(GPIO30, AF0)
+#define GPIO31_GPIO     MFP_CFG_IN(GPIO31, AF0)
+#define GPIO32_GPIO     MFP_CFG_IN(GPIO32, AF0)
+#define GPIO33_GPIO     MFP_CFG_IN(GPIO33, AF0)
+#define GPIO34_GPIO     MFP_CFG_IN(GPIO34, AF0)
+#define GPIO35_GPIO     MFP_CFG_IN(GPIO35, AF0)
+#define GPIO36_GPIO     MFP_CFG_IN(GPIO36, AF0)
+#define GPIO37_GPIO     MFP_CFG_IN(GPIO37, AF0)
+#define GPIO38_GPIO     MFP_CFG_IN(GPIO38, AF0)
+#define GPIO39_GPIO     MFP_CFG_IN(GPIO39, AF0)
+#define GPIO40_GPIO     MFP_CFG_IN(GPIO40, AF0)
+#define GPIO41_GPIO     MFP_CFG_IN(GPIO41, AF0)
+#define GPIO42_GPIO     MFP_CFG_IN(GPIO42, AF0)
+#define GPIO43_GPIO     MFP_CFG_IN(GPIO43, AF0)
+#define GPIO44_GPIO     MFP_CFG_IN(GPIO44, AF0)
+#define GPIO45_GPIO     MFP_CFG_IN(GPIO45, AF0)
+#define GPIO46_GPIO     MFP_CFG_IN(GPIO46, AF0)
+#define GPIO47_GPIO     MFP_CFG_IN(GPIO47, AF0)
+#define GPIO48_GPIO     MFP_CFG_IN(GPIO48, AF0)
+#define GPIO49_GPIO     MFP_CFG_IN(GPIO49, AF0)
+#define GPIO50_GPIO     MFP_CFG_IN(GPIO50, AF0)
+#define GPIO51_GPIO     MFP_CFG_IN(GPIO51, AF0)
+#define GPIO52_GPIO     MFP_CFG_IN(GPIO52, AF0)
+#define GPIO53_GPIO     MFP_CFG_IN(GPIO53, AF0)
+#define GPIO54_GPIO     MFP_CFG_IN(GPIO54, AF0)
+#define GPIO55_GPIO     MFP_CFG_IN(GPIO55, AF0)
+#define GPIO56_GPIO     MFP_CFG_IN(GPIO56, AF0)
+#define GPIO57_GPIO     MFP_CFG_IN(GPIO57, AF0)
+#define GPIO58_GPIO     MFP_CFG_IN(GPIO58, AF0)
+#define GPIO59_GPIO     MFP_CFG_IN(GPIO59, AF0)
+#define GPIO60_GPIO     MFP_CFG_IN(GPIO60, AF0)
+#define GPIO61_GPIO     MFP_CFG_IN(GPIO61, AF0)
+#define GPIO62_GPIO     MFP_CFG_IN(GPIO62, AF0)
+#define GPIO63_GPIO     MFP_CFG_IN(GPIO63, AF0)
+#define GPIO64_GPIO     MFP_CFG_IN(GPIO64, AF0)
+#define GPIO65_GPIO     MFP_CFG_IN(GPIO65, AF0)
+#define GPIO66_GPIO     MFP_CFG_IN(GPIO66, AF0)
+#define GPIO67_GPIO     MFP_CFG_IN(GPIO67, AF0)
+#define GPIO68_GPIO     MFP_CFG_IN(GPIO68, AF0)
+#define GPIO69_GPIO     MFP_CFG_IN(GPIO69, AF0)
+#define GPIO70_GPIO     MFP_CFG_IN(GPIO70, AF0)
+#define GPIO71_GPIO     MFP_CFG_IN(GPIO71, AF0)
+#define GPIO72_GPIO     MFP_CFG_IN(GPIO72, AF0)
+#define GPIO73_GPIO     MFP_CFG_IN(GPIO73, AF0)
+#define GPIO74_GPIO     MFP_CFG_IN(GPIO74, AF0)
+#define GPIO75_GPIO     MFP_CFG_IN(GPIO75, AF0)
+#define GPIO76_GPIO     MFP_CFG_IN(GPIO76, AF0)
+#define GPIO77_GPIO     MFP_CFG_IN(GPIO77, AF0)
+#define GPIO78_GPIO     MFP_CFG_IN(GPIO78, AF0)
+#define GPIO79_GPIO     MFP_CFG_IN(GPIO79, AF0)
+#define GPIO80_GPIO     MFP_CFG_IN(GPIO80, AF0)
+#define GPIO81_GPIO     MFP_CFG_IN(GPIO81, AF0)
+#define GPIO82_GPIO     MFP_CFG_IN(GPIO82, AF0)
+#define GPIO83_GPIO     MFP_CFG_IN(GPIO83, AF0)
+#define GPIO84_GPIO     MFP_CFG_IN(GPIO84, AF0)
+extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
+extern int gpio_set_wake(unsigned int gpio, unsigned int on);
+#endif /* __ASM_ARCH_MFP_PXA2XX_H */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 2357a73340d4..a322012f16ac 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1129,6 +1129,11 @@
 #define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
 #define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
+#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
+#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
+#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
 /*
 * General Purpose I/O
@@ -1200,12 +1205,6 @@
 /* Interrupt Controller */
-#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
-#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
-#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
 #define _GPLR(x)        __REG2(0x40E00000, ((x) & 0x60) >> 3)
 #define _GPDR(x)        __REG2(0x40E0000C, ((x) & 0x60) >> 3)
 #define _GPSR(x)        __REG2(0x40E00018, ((x) & 0x60) >> 3)
@@ -1237,267 +1236,6 @@
 #endif
-/* GPIO alternate function assignments */
-#define GPIO1_RST               1       /* reset */
-#define GPIO6_MMCCLK            6       /* MMC Clock */
-#define GPIO7_48MHz             7       /* 48 MHz clock output */
-#define GPIO8_MMCCS0            8       /* MMC Chip Select 0 */
-#define GPIO9_MMCCS1            9       /* MMC Chip Select 1 */
-#define GPIO10_RTCCLK           10      /* real time clock (1 Hz) */
-#define GPIO11_3_6MHz           11      /* 3.6 MHz oscillator out */
-#define GPIO12_32KHz            12      /* 32 kHz out */
-#define GPIO13_MBGNT            13      /* memory controller grant */
-#define GPIO14_MBREQ            14      /* alternate bus master request */
-#define GPIO15_nCS_1            15      /* chip select 1 */
-#define GPIO16_PWM0             16      /* PWM0 output */
-#define GPIO17_PWM1             17      /* PWM1 output */
-#define GPIO18_RDY              18      /* Ext. Bus Ready */
-#define GPIO19_DREQ1            19      /* External DMA Request */
-#define GPIO20_DREQ0            20      /* External DMA Request */
-#define GPIO23_SCLK             23      /* SSP clock */
-#define GPIO24_SFRM             24      /* SSP Frame */
-#define GPIO25_STXD             25      /* SSP transmit */
-#define GPIO26_SRXD             26      /* SSP receive */
-#define GPIO27_SEXTCLK          27      /* SSP ext_clk */
-#define GPIO28_BITCLK           28      /* AC97/I2S bit_clk */
-#define GPIO29_SDATA_IN         29      /* AC97 Sdata_in0 / I2S Sdata_in */
-#define GPIO30_SDATA_OUT        30      /* AC97/I2S Sdata_out */
-#define GPIO31_SYNC             31      /* AC97/I2S sync */
-#define GPIO32_SDATA_IN1        32      /* AC97 Sdata_in1 */
-#define GPIO32_SYSCLK           32      /* I2S System Clock */
-#define GPIO32_MMCCLK           32      /* MMC Clock (PXA270) */
-#define GPIO33_nCS_5            33      /* chip select 5 */
-#define GPIO34_FFRXD            34      /* FFUART receive */
-#define GPIO34_MMCCS0           34      /* MMC Chip Select 0 */
-#define GPIO35_FFCTS            35      /* FFUART Clear to send */
-#define GPIO36_FFDCD            36      /* FFUART Data carrier detect */
-#define GPIO37_FFDSR            37      /* FFUART data set ready */
-#define GPIO38_FFRI             38      /* FFUART Ring Indicator */
-#define GPIO39_MMCCS1           39      /* MMC Chip Select 1 */
-#define GPIO39_FFTXD            39      /* FFUART transmit data */
-#define GPIO40_FFDTR            40      /* FFUART data terminal Ready */
-#define GPIO41_FFRTS            41      /* FFUART request to send */
-#define GPIO42_BTRXD            42      /* BTUART receive data */
-#define GPIO42_HWRXD            42      /* HWUART receive data */
-#define GPIO43_BTTXD            43      /* BTUART transmit data */
-#define GPIO43_HWTXD            43      /* HWUART transmit data */
-#define GPIO44_BTCTS            44      /* BTUART clear to send */
-#define GPIO44_HWCTS            44      /* HWUART clear to send */
-#define GPIO45_BTRTS            45      /* BTUART request to send */
-#define GPIO45_HWRTS            45      /* HWUART request to send */
-#define GPIO45_AC97_SYSCLK      45      /* AC97 System Clock */
-#define GPIO46_ICPRXD           46      /* ICP receive data */
-#define GPIO46_STRXD            46      /* STD_UART receive data */
-#define GPIO47_ICPTXD           47      /* ICP transmit data */
-#define GPIO47_STTXD            47      /* STD_UART transmit data */
-#define GPIO48_nPOE             48      /* Output Enable for Card Space */
-#define GPIO49_nPWE             49      /* Write Enable for Card Space */
-#define GPIO50_nPIOR            50      /* I/O Read for Card Space */
-#define GPIO51_nPIOW            51      /* I/O Write for Card Space */
-#define GPIO52_nPCE_1           52      /* Card Enable for Card Space */
-#define GPIO53_nPCE_2           53      /* Card Enable for Card Space */
-#define GPIO53_MMCCLK           53      /* MMC Clock */
-#define GPIO54_MMCCLK           54      /* MMC Clock */
-#define GPIO54_pSKTSEL          54      /* Socket Select for Card Space */
-#define GPIO54_nPCE_2           54      /* Card Enable for Card Space (PXA27x) */
-#define GPIO55_nPREG            55      /* Card Address bit 26 */
-#define GPIO56_nPWAIT           56      /* Wait signal for Card Space */
-#define GPIO57_nIOIS16          57      /* Bus Width select for I/O Card Space */
-#define GPIO58_LDD_0            58      /* LCD data pin 0 */
-#define GPIO59_LDD_1            59      /* LCD data pin 1 */
-#define GPIO60_LDD_2            60      /* LCD data pin 2 */
-#define GPIO61_LDD_3            61      /* LCD data pin 3 */
-#define GPIO62_LDD_4            62      /* LCD data pin 4 */
-#define GPIO63_LDD_5            63      /* LCD data pin 5 */
-#define GPIO64_LDD_6            64      /* LCD data pin 6 */
-#define GPIO65_LDD_7            65      /* LCD data pin 7 */
-#define GPIO66_LDD_8            66      /* LCD data pin 8 */
-#define GPIO66_MBREQ            66      /* alternate bus master req */
-#define GPIO67_LDD_9            67      /* LCD data pin 9 */
-#define GPIO67_MMCCS0           67      /* MMC Chip Select 0 */
-#define GPIO68_LDD_10           68      /* LCD data pin 10 */
-#define GPIO68_MMCCS1           68      /* MMC Chip Select 1 */
-#define GPIO69_LDD_11           69      /* LCD data pin 11 */
-#define GPIO69_MMCCLK           69      /* MMC_CLK */
-#define GPIO70_LDD_12           70      /* LCD data pin 12 */
-#define GPIO70_RTCCLK           70      /* Real Time clock (1 Hz) */
-#define GPIO71_LDD_13           71      /* LCD data pin 13 */
-#define GPIO71_3_6MHz           71      /* 3.6 MHz Oscillator clock */
-#define GPIO72_LDD_14           72      /* LCD data pin 14 */
-#define GPIO72_32kHz            72      /* 32 kHz clock */
-#define GPIO73_LDD_15           73      /* LCD data pin 15 */
-#define GPIO73_MBGNT            73      /* Memory controller grant */
-#define GPIO74_LCD_FCLK         74      /* LCD Frame clock */
-#define GPIO75_LCD_LCLK         75      /* LCD line clock */
-#define GPIO76_LCD_PCLK         76      /* LCD Pixel clock */
-#define GPIO77_LCD_ACBIAS       77      /* LCD AC Bias */
-#define GPIO78_nCS_2            78      /* chip select 2 */
-#define GPIO79_nCS_3            79      /* chip select 3 */
-#define GPIO80_nCS_4            80      /* chip select 4 */
-#define GPIO81_NSCLK            81      /* NSSP clock */
-#define GPIO82_NSFRM            82      /* NSSP Frame */
-#define GPIO83_NSTXD            83      /* NSSP transmit */
-#define GPIO84_NSRXD            84      /* NSSP receive */
-#define GPIO85_nPCE_1           85      /* Card Enable for Card Space (PXA27x) */
-#define GPIO92_MMCDAT0          92      /* MMC DAT0 (PXA27x) */
-#define GPIO102_nPCE_1          102     /* PCMCIA (PXA27x) */
-#define GPIO109_MMCDAT1         109     /* MMC DAT1 (PXA27x) */
-#define GPIO110_MMCDAT2         110     /* MMC DAT2 (PXA27x) */
-#define GPIO110_MMCCS0          110     /* MMC Chip Select 0 (PXA27x) */
-#define GPIO111_MMCDAT3         111     /* MMC DAT3 (PXA27x) */
-#define GPIO111_MMCCS1          111     /* MMC Chip Select 1 (PXA27x) */
-#define GPIO112_MMCCMD          112     /* MMC CMD (PXA27x) */
-#define GPIO113_I2S_SYSCLK      113     /* I2S System Clock (PXA27x) */
-#define GPIO113_AC97_RESET_N    113     /* AC97 NRESET on (PXA27x) */
-/* GPIO alternate function mode & direction */
-#define GPIO_IN                 0x000
-#define GPIO_OUT                0x080
-#define GPIO_ALT_FN_1_IN        0x100
-#define GPIO_ALT_FN_1_OUT       0x180
-#define GPIO_ALT_FN_2_IN        0x200
-#define GPIO_ALT_FN_2_OUT       0x280
-#define GPIO_ALT_FN_3_IN        0x300
-#define GPIO_ALT_FN_3_OUT       0x380
-#define GPIO_MD_MASK_NR         0x07f
-#define GPIO_MD_MASK_DIR        0x080
-#define GPIO_MD_MASK_FN         0x300
-#define GPIO_DFLT_LOW           0x400
-#define GPIO_DFLT_HIGH          0x800
-#define GPIO1_RTS_MD            ( 1 | GPIO_ALT_FN_1_IN)
-#define GPIO6_MMCCLK_MD         ( 6 | GPIO_ALT_FN_1_OUT)
-#define GPIO7_48MHz_MD          ( 7 | GPIO_ALT_FN_1_OUT)
-#define GPIO8_MMCCS0_MD         ( 8 | GPIO_ALT_FN_1_OUT)
-#define GPIO9_MMCCS1_MD         ( 9 | GPIO_ALT_FN_1_OUT)
-#define GPIO10_RTCCLK_MD        (10 | GPIO_ALT_FN_1_OUT)
-#define GPIO11_3_6MHz_MD        (11 | GPIO_ALT_FN_1_OUT)
-#define GPIO12_32KHz_MD         (12 | GPIO_ALT_FN_1_OUT)
-#define GPIO13_MBGNT_MD         (13 | GPIO_ALT_FN_2_OUT)
-#define GPIO14_MBREQ_MD         (14 | GPIO_ALT_FN_1_IN)
-#define GPIO15_nCS_1_MD         (15 | GPIO_ALT_FN_2_OUT)
-#define GPIO16_PWM0_MD          (16 | GPIO_ALT_FN_2_OUT)
-#define GPIO17_PWM1_MD          (17 | GPIO_ALT_FN_2_OUT)
-#define GPIO18_RDY_MD           (18 | GPIO_ALT_FN_1_IN)
-#define GPIO19_DREQ1_MD         (19 | GPIO_ALT_FN_1_IN)
-#define GPIO20_DREQ0_MD         (20 | GPIO_ALT_FN_1_IN)
-#define GPIO23_SCLK_MD          (23 | GPIO_ALT_FN_2_OUT)
-#define GPIO24_SFRM_MD          (24 | GPIO_ALT_FN_2_OUT)
-#define GPIO25_STXD_MD          (25 | GPIO_ALT_FN_2_OUT)
-#define GPIO26_SRXD_MD          (26 | GPIO_ALT_FN_1_IN)
-#define GPIO27_SEXTCLK_MD       (27 | GPIO_ALT_FN_1_IN)
-#define GPIO28_BITCLK_AC97_MD   (28 | GPIO_ALT_FN_1_IN)
-#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
-#define GPIO28_BITCLK_OUT_I2S_MD        (28 | GPIO_ALT_FN_1_OUT)
-#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
-#define GPIO29_SDATA_IN_I2S_MD  (29 | GPIO_ALT_FN_2_IN)
-#define GPIO30_SDATA_OUT_AC97_MD        (30 | GPIO_ALT_FN_2_OUT)
-#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
-#define GPIO31_SYNC_I2S_MD      (31 | GPIO_ALT_FN_1_OUT)
-#define GPIO31_SYNC_AC97_MD     (31 | GPIO_ALT_FN_2_OUT)
-#define GPIO32_SDATA_IN1_AC97_MD        (32 | GPIO_ALT_FN_1_IN)
-#define GPIO32_SYSCLK_I2S_MD    (32 | GPIO_ALT_FN_1_OUT)
-#define GPIO32_MMCCLK_MD                ( 32 | GPIO_ALT_FN_2_OUT)
-#define GPIO33_nCS_5_MD         (33 | GPIO_ALT_FN_2_OUT)
-#define GPIO34_FFRXD_MD         (34 | GPIO_ALT_FN_1_IN)
-#define GPIO34_MMCCS0_MD        (34 | GPIO_ALT_FN_2_OUT)
-#define GPIO35_FFCTS_MD         (35 | GPIO_ALT_FN_1_IN)
-#define GPIO36_FFDCD_MD         (36 | GPIO_ALT_FN_1_IN)
-#define GPIO37_FFDSR_MD         (37 | GPIO_ALT_FN_1_IN)
-#define GPIO38_FFRI_MD          (38 | GPIO_ALT_FN_1_IN)
-#define GPIO39_MMCCS1_MD        (39 | GPIO_ALT_FN_1_OUT)
-#define GPIO39_FFTXD_MD         (39 | GPIO_ALT_FN_2_OUT)
-#define GPIO40_FFDTR_MD         (40 | GPIO_ALT_FN_2_OUT)
-#define GPIO41_FFRTS_MD         (41 | GPIO_ALT_FN_2_OUT)
-#define GPIO42_BTRXD_MD         (42 | GPIO_ALT_FN_1_IN)
-#define GPIO42_HWRXD_MD         (42 | GPIO_ALT_FN_3_IN)
-#define GPIO43_BTTXD_MD         (43 | GPIO_ALT_FN_2_OUT)
-#define GPIO43_HWTXD_MD         (43 | GPIO_ALT_FN_3_OUT)
-#define GPIO44_BTCTS_MD         (44 | GPIO_ALT_FN_1_IN)
-#define GPIO44_HWCTS_MD         (44 | GPIO_ALT_FN_3_IN)
-#define GPIO45_BTRTS_MD         (45 | GPIO_ALT_FN_2_OUT)
-#define GPIO45_HWRTS_MD         (45 | GPIO_ALT_FN_3_OUT)
-#define GPIO45_SYSCLK_AC97_MD           (45 | GPIO_ALT_FN_1_OUT)
-#define GPIO46_ICPRXD_MD        (46 | GPIO_ALT_FN_1_IN)
-#define GPIO46_STRXD_MD         (46 | GPIO_ALT_FN_2_IN)
-#define GPIO47_ICPTXD_MD        (47 | GPIO_ALT_FN_2_OUT)
-#define GPIO47_STTXD_MD         (47 | GPIO_ALT_FN_1_OUT)
-#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
-#define GPIO48_HWTXD_MD         (48 | GPIO_ALT_FN_1_OUT)
-#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
-#define GPIO49_HWRXD_MD         (49 | GPIO_ALT_FN_1_IN)
-#define GPIO49_nPWE_MD          (49 | GPIO_ALT_FN_2_OUT)
-#define GPIO50_nPIOR_MD         (50 | GPIO_ALT_FN_2_OUT)
-#define GPIO50_HWCTS_MD         (50 | GPIO_ALT_FN_1_IN)
-#define GPIO51_HWRTS_MD         (51 | GPIO_ALT_FN_1_OUT)
-#define GPIO51_nPIOW_MD         (51 | GPIO_ALT_FN_2_OUT)
-#define GPIO52_nPCE_1_MD        (52 | GPIO_ALT_FN_2_OUT)
-#define GPIO53_nPCE_2_MD        (53 | GPIO_ALT_FN_2_OUT)
-#define GPIO53_MMCCLK_MD        (53 | GPIO_ALT_FN_1_OUT)
-#define GPIO54_MMCCLK_MD        (54 | GPIO_ALT_FN_1_OUT)
-#define GPIO54_nPCE_2_MD        (54 | GPIO_ALT_FN_2_OUT)
-#define GPIO54_pSKTSEL_MD       (54 | GPIO_ALT_FN_2_OUT)
-#define GPIO55_nPREG_MD         (55 | GPIO_ALT_FN_2_OUT)
-#define GPIO56_nPWAIT_MD        (56 | GPIO_ALT_FN_1_IN)
-#define GPIO57_nIOIS16_MD       (57 | GPIO_ALT_FN_1_IN)
-#define GPIO58_LDD_0_MD         (58 | GPIO_ALT_FN_2_OUT)
-#define GPIO59_LDD_1_MD         (59 | GPIO_ALT_FN_2_OUT)
-#define GPIO60_LDD_2_MD         (60 | GPIO_ALT_FN_2_OUT)
-#define GPIO61_LDD_3_MD         (61 | GPIO_ALT_FN_2_OUT)
-#define GPIO62_LDD_4_MD         (62 | GPIO_ALT_FN_2_OUT)
-#define GPIO63_LDD_5_MD         (63 | GPIO_ALT_FN_2_OUT)
-#define GPIO64_LDD_6_MD         (64 | GPIO_ALT_FN_2_OUT)
-#define GPIO65_LDD_7_MD         (65 | GPIO_ALT_FN_2_OUT)
-#define GPIO66_LDD_8_MD         (66 | GPIO_ALT_FN_2_OUT)
-#define GPIO66_MBREQ_MD         (66 | GPIO_ALT_FN_1_IN)
-#define GPIO67_LDD_9_MD         (67 | GPIO_ALT_FN_2_OUT)
-#define GPIO67_MMCCS0_MD        (67 | GPIO_ALT_FN_1_OUT)
-#define GPIO68_LDD_10_MD        (68 | GPIO_ALT_FN_2_OUT)
-#define GPIO68_MMCCS1_MD        (68 | GPIO_ALT_FN_1_OUT)
-#define GPIO69_LDD_11_MD        (69 | GPIO_ALT_FN_2_OUT)
-#define GPIO69_MMCCLK_MD        (69 | GPIO_ALT_FN_1_OUT)
-#define GPIO70_LDD_12_MD        (70 | GPIO_ALT_FN_2_OUT)
-#define GPIO70_RTCCLK_MD        (70 | GPIO_ALT_FN_1_OUT)
-#define GPIO71_LDD_13_MD        (71 | GPIO_ALT_FN_2_OUT)
-#define GPIO71_3_6MHz_MD        (71 | GPIO_ALT_FN_1_OUT)
-#define GPIO72_LDD_14_MD        (72 | GPIO_ALT_FN_2_OUT)
-#define GPIO72_32kHz_MD         (72 | GPIO_ALT_FN_1_OUT)
-#define GPIO73_LDD_15_MD        (73 | GPIO_ALT_FN_2_OUT)
-#define GPIO73_MBGNT_MD         (73 | GPIO_ALT_FN_1_OUT)
-#define GPIO74_LCD_FCLK_MD      (74 | GPIO_ALT_FN_2_OUT)
-#define GPIO75_LCD_LCLK_MD      (75 | GPIO_ALT_FN_2_OUT)
-#define GPIO76_LCD_PCLK_MD      (76 | GPIO_ALT_FN_2_OUT)
-#define GPIO77_LCD_ACBIAS_MD    (77 | GPIO_ALT_FN_2_OUT)
-#define GPIO78_nCS_2_MD         (78 | GPIO_ALT_FN_2_OUT)
-#define GPIO79_nCS_3_MD         (79 | GPIO_ALT_FN_2_OUT)
-#define GPIO79_pSKTSEL_MD       (79 | GPIO_ALT_FN_1_OUT)
-#define GPIO80_nCS_4_MD         (80 | GPIO_ALT_FN_2_OUT)
-#define GPIO81_NSSP_CLK_OUT     (81 | GPIO_ALT_FN_1_OUT)
-#define GPIO81_NSSP_CLK_IN      (81 | GPIO_ALT_FN_1_IN)
-#define GPIO82_NSSP_FRM_OUT     (82 | GPIO_ALT_FN_1_OUT)
-#define GPIO82_NSSP_FRM_IN      (82 | GPIO_ALT_FN_1_IN)
-#define GPIO83_NSSP_TX          (83 | GPIO_ALT_FN_1_OUT)
-#define GPIO83_NSSP_RX          (83 | GPIO_ALT_FN_2_IN)
-#define GPIO84_NSSP_TX          (84 | GPIO_ALT_FN_1_OUT)
-#define GPIO84_NSSP_RX          (84 | GPIO_ALT_FN_2_IN)
-#define GPIO85_nPCE_1_MD        (85 | GPIO_ALT_FN_1_OUT)
-#define GPIO92_MMCDAT0_MD       (92 | GPIO_ALT_FN_1_OUT)
-#define GPIO102_nPCE_1_MD       (102 | GPIO_ALT_FN_1_OUT)
-#define GPIO104_pSKTSEL_MD      (104 | GPIO_ALT_FN_1_OUT)
-#define GPIO109_MMCDAT1_MD      (109 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCDAT2_MD      (110 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCCS0_MD       (110 | GPIO_ALT_FN_1_OUT)
-#define GPIO111_MMCDAT3_MD      (111 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCCS1_MD       (111 | GPIO_ALT_FN_1_OUT)
-#define GPIO112_MMCCMD_MD       (112 | GPIO_ALT_FN_1_OUT)
-#define GPIO113_I2S_SYSCLK_MD   (113 | GPIO_ALT_FN_1_OUT)
-#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
-#define GPIO117_I2CSCL_MD       (117 | GPIO_ALT_FN_1_IN)
-#define GPIO118_I2CSDA_MD       (118 | GPIO_ALT_FN_1_IN)
 /*
 * Power Manager
 */
@@ -1866,62 +1604,6 @@
 #ifdef CONFIG_PXA27x
-/*
- * Keypad
- */
-#define KPC             __REG(0x41500000) /* Keypad Interface Control register */
-#define KPDK            __REG(0x41500008) /* Keypad Interface Direct Key register */
-#define KPREC           __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
-#define KPMK            __REG(0x41500018) /* Keypad Interface Matrix Key register */
-#define KPAS            __REG(0x41500020) /* Keypad Interface Automatic Scan register */
-#define KPASMKP0        __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
-#define KPASMKP1        __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
-#define KPASMKP2        __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
-#define KPASMKP3        __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
-#define KPKDI           __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
-#define KPC_AS          (0x1 << 30)  /* Automatic Scan bit */
-#define KPC_ASACT       (0x1 << 29)  /* Automatic Scan on Activity */
-#define KPC_MI          (0x1 << 22)  /* Matrix interrupt bit */
-#define KPC_IMKP        (0x1 << 21)  /* Ignore Multiple Key Press */
-#define KPC_MS7         (0x1 << 20)  /* Matrix scan line 7 */
-#define KPC_MS6         (0x1 << 19)  /* Matrix scan line 6 */
-#define KPC_MS5         (0x1 << 18)  /* Matrix scan line 5 */
-#define KPC_MS4         (0x1 << 17)  /* Matrix scan line 4 */
-#define KPC_MS3         (0x1 << 16)  /* Matrix scan line 3 */
-#define KPC_MS2         (0x1 << 15)  /* Matrix scan line 2 */
-#define KPC_MS1         (0x1 << 14)  /* Matrix scan line 1 */
-#define KPC_MS0         (0x1 << 13)  /* Matrix scan line 0 */
-#define KPC_MS_ALL      (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
-#define KPC_ME          (0x1 << 12)  /* Matrix Keypad Enable */
-#define KPC_MIE         (0x1 << 11)  /* Matrix Interrupt Enable */
-#define KPC_DK_DEB_SEL  (0x1 <<  9)  /* Direct Keypad Debounce Select */
-#define KPC_DI          (0x1 <<  5)  /* Direct key interrupt bit */
-#define KPC_RE_ZERO_DEB (0x1 <<  4)  /* Rotary Encoder Zero Debounce */
-#define KPC_REE1        (0x1 <<  3)  /* Rotary Encoder1 Enable */
-#define KPC_REE0        (0x1 <<  2)  /* Rotary Encoder0 Enable */
-#define KPC_DE          (0x1 <<  1)  /* Direct Keypad Enable */
-#define KPC_DIE         (0x1 <<  0)  /* Direct Keypad interrupt Enable */
-#define KPDK_DKP        (0x1 << 31)
-#define KPDK_DK7        (0x1 <<  7)
-#define KPDK_DK6        (0x1 <<  6)
-#define KPDK_DK5        (0x1 <<  5)
-#define KPDK_DK4        (0x1 <<  4)
-#define KPDK_DK3        (0x1 <<  3)
-#define KPDK_DK2        (0x1 <<  2)
-#define KPDK_DK1        (0x1 <<  1)
-#define KPDK_DK0        (0x1 <<  0)
-#define KPREC_OF1       (0x1 << 31)
-#define kPREC_UF1       (0x1 << 30)
-#define KPREC_OF0       (0x1 << 15)
-#define KPREC_UF0       (0x1 << 14)
-#define KPMK_MKP        (0x1 << 31)
-#define KPAS_SO         (0x1 << 31)
-#define KPASMKPx_SO     (0x1 << 31)
 /* Camera Interface */
 #define CICR0           __REG(0x50000000)
 #define CICR1           __REG(0x50000004)
@@ -1953,7 +1635,7 @@
 #define CICR0_FOM       (1 << 0)        /* FIFO-overrun mask */
 #define CICR1_TBIT      (1 << 31)       /* Transparency bit */
-#define CICR1_RGBT_CONV (0x3 << 30)     /* RGBT conversion mask */
+#define CICR1_RGBT_CONV (0x3 << 29)     /* RGBT conversion mask */
 #define CICR1_PPL       (0x7ff << 15)   /* Pixels per line mask */
 #define CICR1_RGB_CONV  (0x7 << 12)     /* RGB conversion mask */
 #define CICR1_RGB_F     (1 << 11)       /* RGB format */
diff --git a/include/asm-arm/arch-pxa/pxa27x_keypad.h b/include/asm-arm/arch-pxa/pxa27x_keypad.h
index 644f7609b523..d5a48a96dea7 100644
--- a/include/asm-arm/arch-pxa/pxa27x_keypad.h
+++ b/include/asm-arm/arch-pxa/pxa27x_keypad.h
@@ -53,4 +53,6 @@ struct pxa27x_keypad_platform_data {
 #define KEY(row, col, val)      (((row) << 28) | ((col) << 24) | (val))
+extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
 #endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
new file mode 100644
index 000000000000..763313c5e6be
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
@@ -0,0 +1,357 @@
+#ifndef __ASM_ARCH_PXA2XX_GPIO_H
+#define __ASM_ARCH_PXA2XX_GPIO_H
+/* GPIO alternate function assignments */
+#define GPIO1_RST               1       /* reset */
+#define GPIO6_MMCCLK            6       /* MMC Clock */
+#define GPIO7_48MHz             7       /* 48 MHz clock output */
+#define GPIO8_MMCCS0            8       /* MMC Chip Select 0 */
+#define GPIO9_MMCCS1            9       /* MMC Chip Select 1 */
+#define GPIO10_RTCCLK           10      /* real time clock (1 Hz) */
+#define GPIO11_3_6MHz           11      /* 3.6 MHz oscillator out */
+#define GPIO12_32KHz            12      /* 32 kHz out */
+#define GPIO12_CIF_DD_7         12      /* Camera data pin 7 */
+#define GPIO13_MBGNT            13      /* memory controller grant */
+#define GPIO14_MBREQ            14      /* alternate bus master request */
+#define GPIO15_nCS_1            15      /* chip select 1 */
+#define GPIO16_PWM0             16      /* PWM0 output */
+#define GPIO17_PWM1             17      /* PWM1 output */
+#define GPIO17_CIF_DD_6         17      /* Camera data pin 6 */
+#define GPIO18_RDY              18      /* Ext. Bus Ready */
+#define GPIO19_DREQ1            19      /* External DMA Request */
+#define GPIO20_DREQ0            20      /* External DMA Request */
+#define GPIO23_SCLK             23      /* SSP clock */
+#define GPIO23_CIF_MCLK         23      /* Camera Master Clock */
+#define GPIO24_SFRM             24      /* SSP Frame */
+#define GPIO24_CIF_FV           24      /* Camera frame start signal */
+#define GPIO25_STXD             25      /* SSP transmit */
+#define GPIO25_CIF_LV           25      /* Camera line start signal */
+#define GPIO26_SRXD             26      /* SSP receive */
+#define GPIO26_CIF_PCLK         26      /* Camera Pixel Clock */
+#define GPIO27_SEXTCLK          27      /* SSP ext_clk */
+#define GPIO27_CIF_DD_0         27      /* Camera data pin 0 */
+#define GPIO28_BITCLK           28      /* AC97/I2S bit_clk */
+#define GPIO29_SDATA_IN         29      /* AC97 Sdata_in0 / I2S Sdata_in */
+#define GPIO30_SDATA_OUT        30      /* AC97/I2S Sdata_out */
+#define GPIO31_SYNC             31      /* AC97/I2S sync */
+#define GPIO32_SDATA_IN1        32      /* AC97 Sdata_in1 */
+#define GPIO32_SYSCLK           32      /* I2S System Clock */
+#define GPIO32_MMCCLK           32      /* MMC Clock (PXA270) */
+#define GPIO33_nCS_5            33      /* chip select 5 */
+#define GPIO34_FFRXD            34      /* FFUART receive */
+#define GPIO34_MMCCS0           34      /* MMC Chip Select 0 */
+#define GPIO35_FFCTS            35      /* FFUART Clear to send */
+#define GPIO36_FFDCD            36      /* FFUART Data carrier detect */
+#define GPIO37_FFDSR            37      /* FFUART data set ready */
+#define GPIO38_FFRI             38      /* FFUART Ring Indicator */
+#define GPIO39_MMCCS1           39      /* MMC Chip Select 1 */
+#define GPIO39_FFTXD            39      /* FFUART transmit data */
+#define GPIO40_FFDTR            40      /* FFUART data terminal Ready */
+#define GPIO41_FFRTS            41      /* FFUART request to send */
+#define GPIO42_BTRXD            42      /* BTUART receive data */
+#define GPIO42_HWRXD            42      /* HWUART receive data */
+#define GPIO42_CIF_MCLK         42      /* Camera Master Clock */
+#define GPIO43_BTTXD            43      /* BTUART transmit data */
+#define GPIO43_HWTXD            43      /* HWUART transmit data */
+#define GPIO43_CIF_FV           43      /* Camera frame start signal */
+#define GPIO44_BTCTS            44      /* BTUART clear to send */
+#define GPIO44_HWCTS            44      /* HWUART clear to send */
+#define GPIO44_CIF_LV           44      /* Camera line start signal */
+#define GPIO45_BTRTS            45      /* BTUART request to send */
+#define GPIO45_HWRTS            45      /* HWUART request to send */
+#define GPIO45_AC97_SYSCLK      45      /* AC97 System Clock */
+#define GPIO45_CIF_PCLK         45      /* Camera Pixel Clock */
+#define GPIO46_ICPRXD           46      /* ICP receive data */
+#define GPIO46_STRXD            46      /* STD_UART receive data */
+#define GPIO47_ICPTXD           47      /* ICP transmit data */
+#define GPIO47_STTXD            47      /* STD_UART transmit data */
+#define GPIO47_CIF_DD_0         47      /* Camera data pin 0 */
+#define GPIO48_nPOE             48      /* Output Enable for Card Space */
+#define GPIO48_CIF_DD_5         48      /* Camera data pin 5 */
+#define GPIO49_nPWE             49      /* Write Enable for Card Space */
+#define GPIO50_nPIOR            50      /* I/O Read for Card Space */
+#define GPIO50_CIF_DD_3         50      /* Camera data pin 3 */
+#define GPIO51_nPIOW            51      /* I/O Write for Card Space */
+#define GPIO51_CIF_DD_2         51      /* Camera data pin 2 */
+#define GPIO52_nPCE_1           52      /* Card Enable for Card Space */
+#define GPIO52_CIF_DD_4         52      /* Camera data pin 4 */
+#define GPIO53_nPCE_2           53      /* Card Enable for Card Space */
+#define GPIO53_MMCCLK           53      /* MMC Clock */
+#define GPIO53_CIF_MCLK         53      /* Camera Master Clock */
+#define GPIO54_MMCCLK           54      /* MMC Clock */
+#define GPIO54_pSKTSEL          54      /* Socket Select for Card Space */
+#define GPIO54_nPCE_2           54      /* Card Enable for Card Space (PXA27x) */
+#define GPIO54_CIF_PCLK         54      /* Camera Pixel Clock */
+#define GPIO55_nPREG            55      /* Card Address bit 26 */
+#define GPIO55_CIF_DD_1         55      /* Camera data pin 1 */
+#define GPIO56_nPWAIT           56      /* Wait signal for Card Space */
+#define GPIO57_nIOIS16          57      /* Bus Width select for I/O Card Space */
+#define GPIO58_LDD_0            58      /* LCD data pin 0 */
+#define GPIO59_LDD_1            59      /* LCD data pin 1 */
+#define GPIO60_LDD_2            60      /* LCD data pin 2 */
+#define GPIO61_LDD_3            61      /* LCD data pin 3 */
+#define GPIO62_LDD_4            62      /* LCD data pin 4 */
+#define GPIO63_LDD_5            63      /* LCD data pin 5 */
+#define GPIO64_LDD_6            64      /* LCD data pin 6 */
+#define GPIO65_LDD_7            65      /* LCD data pin 7 */
+#define GPIO66_LDD_8            66      /* LCD data pin 8 */
+#define GPIO66_MBREQ            66      /* alternate bus master req */
+#define GPIO67_LDD_9            67      /* LCD data pin 9 */
+#define GPIO67_MMCCS0           67      /* MMC Chip Select 0 */
+#define GPIO68_LDD_10           68      /* LCD data pin 10 */
+#define GPIO68_MMCCS1           68      /* MMC Chip Select 1 */
+#define GPIO69_LDD_11           69      /* LCD data pin 11 */
+#define GPIO69_MMCCLK           69      /* MMC_CLK */
+#define GPIO70_LDD_12           70      /* LCD data pin 12 */
+#define GPIO70_RTCCLK           70      /* Real Time clock (1 Hz) */
+#define GPIO71_LDD_13           71      /* LCD data pin 13 */
+#define GPIO71_3_6MHz           71      /* 3.6 MHz Oscillator clock */
+#define GPIO72_LDD_14           72      /* LCD data pin 14 */
+#define GPIO72_32kHz            72      /* 32 kHz clock */
+#define GPIO73_LDD_15           73      /* LCD data pin 15 */
+#define GPIO73_MBGNT            73      /* Memory controller grant */
+#define GPIO74_LCD_FCLK         74      /* LCD Frame clock */
+#define GPIO75_LCD_LCLK         75      /* LCD line clock */
+#define GPIO76_LCD_PCLK         76      /* LCD Pixel clock */
+#define GPIO77_LCD_ACBIAS       77      /* LCD AC Bias */
+#define GPIO78_nCS_2            78      /* chip select 2 */
+#define GPIO79_nCS_3            79      /* chip select 3 */
+#define GPIO80_nCS_4            80      /* chip select 4 */
+#define GPIO81_NSCLK            81      /* NSSP clock */
+#define GPIO81_CIF_DD_0         81      /* Camera data pin 0 */
+#define GPIO82_NSFRM            82      /* NSSP Frame */
+#define GPIO82_CIF_DD_5         82      /* Camera data pin 5 */
+#define GPIO83_NSTXD            83      /* NSSP transmit */
+#define GPIO83_CIF_DD_4         83      /* Camera data pin 4 */
+#define GPIO84_NSRXD            84      /* NSSP receive */
+#define GPIO84_CIF_FV           84      /* Camera frame start signal */
+#define GPIO85_nPCE_1           85      /* Card Enable for Card Space (PXA27x) */
+#define GPIO85_CIF_LV           85      /* Camera line start signal */
+#define GPIO90_CIF_DD_4         90      /* Camera data pin 4 */
+#define GPIO91_CIF_DD_5         91      /* Camera data pin 5 */
+#define GPIO92_MMCDAT0          92      /* MMC DAT0 (PXA27x) */
+#define GPIO93_CIF_DD_6         93      /* Camera data pin 6 */
+#define GPIO94_CIF_DD_5         94      /* Camera data pin 5 */
+#define GPIO95_CIF_DD_4         95      /* Camera data pin 4 */
+#define GPIO98_CIF_DD_0         98      /* Camera data pin 0 */
+#define GPIO102_nPCE_1          102     /* PCMCIA (PXA27x) */
+#define GPIO103_CIF_DD_3        103     /* Camera data pin 3 */
+#define GPIO104_CIF_DD_2        104     /* Camera data pin 2 */
+#define GPIO105_CIF_DD_1        105     /* Camera data pin 1 */
+#define GPIO106_CIF_DD_9        106     /* Camera data pin 9 */
+#define GPIO107_CIF_DD_8        107     /* Camera data pin 8 */
+#define GPIO108_CIF_DD_7        108     /* Camera data pin 7 */
+#define GPIO109_MMCDAT1         109     /* MMC DAT1 (PXA27x) */
+#define GPIO110_MMCDAT2         110     /* MMC DAT2 (PXA27x) */
+#define GPIO110_MMCCS0          110     /* MMC Chip Select 0 (PXA27x) */
+#define GPIO111_MMCDAT3         111     /* MMC DAT3 (PXA27x) */
+#define GPIO111_MMCCS1          111     /* MMC Chip Select 1 (PXA27x) */
+#define GPIO112_MMCCMD          112     /* MMC CMD (PXA27x) */
+#define GPIO113_I2S_SYSCLK      113     /* I2S System Clock (PXA27x) */
+#define GPIO113_AC97_RESET_N    113     /* AC97 NRESET on (PXA27x) */
+#define GPIO114_CIF_DD_1        114     /* Camera data pin 1 */
+#define GPIO115_CIF_DD_3        115     /* Camera data pin 3 */
+#define GPIO116_CIF_DD_2        116     /* Camera data pin 2 */
+/* GPIO alternate function mode & direction */
+#define GPIO_IN                 0x000
+#define GPIO_OUT                0x080
+#define GPIO_ALT_FN_1_IN        0x100
+#define GPIO_ALT_FN_1_OUT       0x180
+#define GPIO_ALT_FN_2_IN        0x200
+#define GPIO_ALT_FN_2_OUT       0x280
+#define GPIO_ALT_FN_3_IN        0x300
+#define GPIO_ALT_FN_3_OUT       0x380
+#define GPIO_MD_MASK_NR         0x07f
+#define GPIO_MD_MASK_DIR        0x080
+#define GPIO_MD_MASK_FN         0x300
+#define GPIO_DFLT_LOW           0x400
+#define GPIO_DFLT_HIGH          0x800
+#define GPIO1_RTS_MD            ( 1 | GPIO_ALT_FN_1_IN)
+#define GPIO6_MMCCLK_MD         ( 6 | GPIO_ALT_FN_1_OUT)
+#define GPIO7_48MHz_MD          ( 7 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_MMCCS0_MD         ( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO9_MMCCS1_MD         ( 9 | GPIO_ALT_FN_1_OUT)
+#define GPIO10_RTCCLK_MD        (10 | GPIO_ALT_FN_1_OUT)
+#define GPIO11_3_6MHz_MD        (11 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_32KHz_MD         (12 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_CIF_DD_7_MD      (12 | GPIO_ALT_FN_2_IN)
+#define GPIO13_MBGNT_MD         (13 | GPIO_ALT_FN_2_OUT)
+#define GPIO14_MBREQ_MD         (14 | GPIO_ALT_FN_1_IN)
+#define GPIO15_nCS_1_MD         (15 | GPIO_ALT_FN_2_OUT)
+#define GPIO16_PWM0_MD          (16 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_PWM1_MD          (17 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_CIF_DD_6_MD      (17 | GPIO_ALT_FN_2_IN)
+#define GPIO18_RDY_MD           (18 | GPIO_ALT_FN_1_IN)
+#define GPIO19_DREQ1_MD         (19 | GPIO_ALT_FN_1_IN)
+#define GPIO20_DREQ0_MD         (20 | GPIO_ALT_FN_1_IN)
+#define GPIO23_CIF_MCLK_MD      (23 | GPIO_ALT_FN_1_OUT)
+#define GPIO23_SCLK_MD          (23 | GPIO_ALT_FN_2_OUT)
+#define GPIO24_CIF_FV_MD        (24 | GPIO_ALT_FN_1_OUT)
+#define GPIO24_SFRM_MD          (24 | GPIO_ALT_FN_2_OUT)
+#define GPIO25_CIF_LV_MD        (25 | GPIO_ALT_FN_1_OUT)
+#define GPIO25_STXD_MD          (25 | GPIO_ALT_FN_2_OUT)
+#define GPIO26_SRXD_MD          (26 | GPIO_ALT_FN_1_IN)
+#define GPIO26_CIF_PCLK_MD      (26 | GPIO_ALT_FN_2_IN)
+#define GPIO27_SEXTCLK_MD       (27 | GPIO_ALT_FN_1_IN)
+#define GPIO27_CIF_DD_0_MD      (27 | GPIO_ALT_FN_3_IN)
+#define GPIO28_BITCLK_AC97_MD   (28 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
+#define GPIO28_BITCLK_OUT_I2S_MD        (28 | GPIO_ALT_FN_1_OUT)
+#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
+#define GPIO29_SDATA_IN_I2S_MD  (29 | GPIO_ALT_FN_2_IN)
+#define GPIO30_SDATA_OUT_AC97_MD        (30 | GPIO_ALT_FN_2_OUT)
+#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_I2S_MD      (31 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_AC97_MD     (31 | GPIO_ALT_FN_2_OUT)
+#define GPIO32_SDATA_IN1_AC97_MD        (32 | GPIO_ALT_FN_1_IN)
+#define GPIO32_SYSCLK_I2S_MD    (32 | GPIO_ALT_FN_1_OUT)
+#define GPIO32_MMCCLK_MD        (32 | GPIO_ALT_FN_2_OUT)
+#define GPIO33_nCS_5_MD         (33 | GPIO_ALT_FN_2_OUT)
+#define GPIO34_FFRXD_MD         (34 | GPIO_ALT_FN_1_IN)
+#define GPIO34_MMCCS0_MD        (34 | GPIO_ALT_FN_2_OUT)
+#define GPIO35_FFCTS_MD         (35 | GPIO_ALT_FN_1_IN)
+#define GPIO35_KP_MKOUT6_MD     (35 | GPIO_ALT_FN_2_OUT)
+#define GPIO36_FFDCD_MD         (36 | GPIO_ALT_FN_1_IN)
+#define GPIO37_FFDSR_MD         (37 | GPIO_ALT_FN_1_IN)
+#define GPIO38_FFRI_MD          (38 | GPIO_ALT_FN_1_IN)
+#define GPIO39_MMCCS1_MD        (39 | GPIO_ALT_FN_1_OUT)
+#define GPIO39_FFTXD_MD         (39 | GPIO_ALT_FN_2_OUT)
+#define GPIO40_FFDTR_MD         (40 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_FFRTS_MD         (41 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_KP_MKOUT7_MD     (41 | GPIO_ALT_FN_1_OUT)
+#define GPIO42_BTRXD_MD         (42 | GPIO_ALT_FN_1_IN)
+#define GPIO42_HWRXD_MD         (42 | GPIO_ALT_FN_3_IN)
+#define GPIO42_CIF_MCLK_MD      (42 | GPIO_ALT_FN_3_OUT)
+#define GPIO43_BTTXD_MD         (43 | GPIO_ALT_FN_2_OUT)
+#define GPIO43_HWTXD_MD         (43 | GPIO_ALT_FN_3_OUT)
+#define GPIO43_CIF_FV_MD        (43 | GPIO_ALT_FN_3_OUT)
+#define GPIO44_BTCTS_MD         (44 | GPIO_ALT_FN_1_IN)
+#define GPIO44_HWCTS_MD         (44 | GPIO_ALT_FN_3_IN)
+#define GPIO44_CIF_LV_MD        (44 | GPIO_ALT_FN_3_OUT)
+#define GPIO45_CIF_PCLK_MD      (45 | GPIO_ALT_FN_3_IN)
+#define GPIO45_BTRTS_MD         (45 | GPIO_ALT_FN_2_OUT)
+#define GPIO45_HWRTS_MD         (45 | GPIO_ALT_FN_3_OUT)
+#define GPIO45_SYSCLK_AC97_MD   (45 | GPIO_ALT_FN_1_OUT)
+#define GPIO46_ICPRXD_MD        (46 | GPIO_ALT_FN_1_IN)
+#define GPIO46_STRXD_MD         (46 | GPIO_ALT_FN_2_IN)
+#define GPIO47_CIF_DD_0_MD      (47 | GPIO_ALT_FN_1_IN)
+#define GPIO47_ICPTXD_MD        (47 | GPIO_ALT_FN_2_OUT)
+#define GPIO47_STTXD_MD         (47 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_CIF_DD_5_MD      (48 | GPIO_ALT_FN_1_IN)
+#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO48_HWTXD_MD         (48 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_HWRXD_MD         (49 | GPIO_ALT_FN_1_IN)
+#define GPIO49_nPWE_MD          (49 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_CIF_DD_3_MD      (50 | GPIO_ALT_FN_1_IN)
+#define GPIO50_nPIOR_MD         (50 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_HWCTS_MD         (50 | GPIO_ALT_FN_1_IN)
+#define GPIO50_CIF_DD_3_MD      (50 | GPIO_ALT_FN_1_IN)
+#define GPIO51_CIF_DD_2_MD      (51 | GPIO_ALT_FN_1_IN)
+#define GPIO51_nPIOW_MD         (51 | GPIO_ALT_FN_2_OUT)
+#define GPIO51_HWRTS_MD         (51 | GPIO_ALT_FN_1_OUT)
+#define GPIO51_CIF_DD_2_MD      (51 | GPIO_ALT_FN_1_IN)
+#define GPIO52_nPCE_1_MD        (52 | GPIO_ALT_FN_2_OUT)
+#define GPIO52_CIF_DD_4_MD      (52 | GPIO_ALT_FN_1_IN)
+#define GPIO53_nPCE_2_MD        (53 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_MMCCLK_MD        (53 | GPIO_ALT_FN_1_OUT)
+#define GPIO53_CIF_MCLK_MD      (53 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_MMCCLK_MD        (54 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_nPCE_2_MD        (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_pSKTSEL_MD       (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_CIF_PCLK_MD      (54 | GPIO_ALT_FN_3_IN)
+#define GPIO55_nPREG_MD         (55 | GPIO_ALT_FN_2_OUT)
+#define GPIO55_CIF_DD_1_MD      (55 | GPIO_ALT_FN_1_IN)
+#define GPIO56_nPWAIT_MD        (56 | GPIO_ALT_FN_1_IN)
+#define GPIO57_nIOIS16_MD       (57 | GPIO_ALT_FN_1_IN)
+#define GPIO58_LDD_0_MD         (58 | GPIO_ALT_FN_2_OUT)
+#define GPIO59_LDD_1_MD         (59 | GPIO_ALT_FN_2_OUT)
+#define GPIO60_LDD_2_MD         (60 | GPIO_ALT_FN_2_OUT)
+#define GPIO61_LDD_3_MD         (61 | GPIO_ALT_FN_2_OUT)
+#define GPIO62_LDD_4_MD         (62 | GPIO_ALT_FN_2_OUT)
+#define GPIO63_LDD_5_MD         (63 | GPIO_ALT_FN_2_OUT)
+#define GPIO64_LDD_6_MD         (64 | GPIO_ALT_FN_2_OUT)
+#define GPIO65_LDD_7_MD         (65 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_LDD_8_MD         (66 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_MBREQ_MD         (66 | GPIO_ALT_FN_1_IN)
+#define GPIO67_LDD_9_MD         (67 | GPIO_ALT_FN_2_OUT)
+#define GPIO67_MMCCS0_MD        (67 | GPIO_ALT_FN_1_OUT)
+#define GPIO68_LDD_10_MD        (68 | GPIO_ALT_FN_2_OUT)
+#define GPIO68_MMCCS1_MD        (68 | GPIO_ALT_FN_1_OUT)
+#define GPIO69_LDD_11_MD        (69 | GPIO_ALT_FN_2_OUT)
+#define GPIO69_MMCCLK_MD        (69 | GPIO_ALT_FN_1_OUT)
+#define GPIO70_LDD_12_MD        (70 | GPIO_ALT_FN_2_OUT)
+#define GPIO70_RTCCLK_MD        (70 | GPIO_ALT_FN_1_OUT)
+#define GPIO71_LDD_13_MD        (71 | GPIO_ALT_FN_2_OUT)
+#define GPIO71_3_6MHz_MD        (71 | GPIO_ALT_FN_1_OUT)
+#define GPIO72_LDD_14_MD        (72 | GPIO_ALT_FN_2_OUT)
+#define GPIO72_32kHz_MD         (72 | GPIO_ALT_FN_1_OUT)
+#define GPIO73_LDD_15_MD        (73 | GPIO_ALT_FN_2_OUT)
+#define GPIO73_MBGNT_MD         (73 | GPIO_ALT_FN_1_OUT)
+#define GPIO74_LCD_FCLK_MD      (74 | GPIO_ALT_FN_2_OUT)
+#define GPIO75_LCD_LCLK_MD      (75 | GPIO_ALT_FN_2_OUT)
+#define GPIO76_LCD_PCLK_MD      (76 | GPIO_ALT_FN_2_OUT)
+#define GPIO77_LCD_ACBIAS_MD    (77 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nCS_2_MD         (78 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nPCE_2_MD        (78 | GPIO_ALT_FN_1_OUT)
+#define GPIO79_nCS_3_MD         (79 | GPIO_ALT_FN_2_OUT)
+#define GPIO79_pSKTSEL_MD       (79 | GPIO_ALT_FN_1_OUT)
+#define GPIO80_nCS_4_MD         (80 | GPIO_ALT_FN_2_OUT)
+#define GPIO81_NSSP_CLK_OUT     (81 | GPIO_ALT_FN_1_OUT)
+#define GPIO81_NSSP_CLK_IN      (81 | GPIO_ALT_FN_1_IN)
+#define GPIO81_CIF_DD_0_MD      (81 | GPIO_ALT_FN_2_IN)
+#define GPIO82_NSSP_FRM_OUT     (82 | GPIO_ALT_FN_1_OUT)
+#define GPIO82_NSSP_FRM_IN      (82 | GPIO_ALT_FN_1_IN)
+#define GPIO82_CIF_DD_5_MD      (82 | GPIO_ALT_FN_3_IN)
+#define GPIO83_NSSP_TX          (83 | GPIO_ALT_FN_1_OUT)
+#define GPIO83_NSSP_RX          (83 | GPIO_ALT_FN_2_IN)
+#define GPIO83_CIF_DD_4_MD      (83 | GPIO_ALT_FN_3_IN)
+#define GPIO84_NSSP_TX          (84 | GPIO_ALT_FN_1_OUT)
+#define GPIO84_NSSP_RX          (84 | GPIO_ALT_FN_2_IN)
+#define GPIO84_CIF_FV_MD        (84 | GPIO_ALT_FN_3_IN)
+#define GPIO85_nPCE_1_MD        (85 | GPIO_ALT_FN_1_OUT)
+#define GPIO85_CIF_LV_MD        (85 | GPIO_ALT_FN_3_IN)
+#define GPIO86_nPCE_1_MD        (86 | GPIO_ALT_FN_1_OUT)
+#define GPIO90_CIF_DD_4_MD      (90 | GPIO_ALT_FN_3_IN)
+#define GPIO91_CIF_DD_5_MD      (91 | GPIO_ALT_FN_3_IN)
+#define GPIO92_MMCDAT0_MD       (92 | GPIO_ALT_FN_1_OUT)
+#define GPIO93_CIF_DD_6_MD      (93 | GPIO_ALT_FN_2_IN)
+#define GPIO94_CIF_DD_5_MD      (94 | GPIO_ALT_FN_2_IN)
+#define GPIO95_CIF_DD_4_MD      (95 | GPIO_ALT_FN_2_IN)
+#define GPIO95_KP_MKIN6_MD      (95 | GPIO_ALT_FN_3_IN)
+#define GPIO96_KP_DKIN3_MD      (96 | GPIO_ALT_FN_1_IN)
+#define GPIO97_KP_MKIN3_MD      (97 | GPIO_ALT_FN_3_IN)
+#define GPIO98_CIF_DD_0_MD      (98 | GPIO_ALT_FN_2_IN)
+#define GPIO100_KP_MKIN0_MD     (100 | GPIO_ALT_FN_1_IN)
+#define GPIO101_KP_MKIN1_MD     (101 | GPIO_ALT_FN_1_IN)
+#define GPIO102_nPCE_1_MD       (102 | GPIO_ALT_FN_1_OUT)
+#define GPIO102_KP_MKIN2_MD     (102 | GPIO_ALT_FN_1_IN)
+#define GPIO103_CIF_DD_3_MD     (103 | GPIO_ALT_FN_1_IN)
+#define GPIO103_KP_MKOUT0_MD    (103 | GPIO_ALT_FN_2_OUT)
+#define GPIO104_CIF_DD_2_MD     (104 | GPIO_ALT_FN_1_IN)
+#define GPIO104_pSKTSEL_MD      (104 | GPIO_ALT_FN_1_OUT)
+#define GPIO104_KP_MKOUT1_MD    (104 | GPIO_ALT_FN_2_OUT)
+#define GPIO105_CIF_DD_1_MD     (105 | GPIO_ALT_FN_1_IN)
+#define GPIO105_KP_MKOUT2_MD    (105 | GPIO_ALT_FN_2_OUT)
+#define GPIO106_CIF_DD_9_MD     (106 | GPIO_ALT_FN_1_IN)
+#define GPIO106_KP_MKOUT3_MD    (106 | GPIO_ALT_FN_2_OUT)
+#define GPIO107_CIF_DD_8_MD     (107 | GPIO_ALT_FN_1_IN)
+#define GPIO107_KP_MKOUT4_MD    (107 | GPIO_ALT_FN_2_OUT)
+#define GPIO108_CIF_DD_7_MD     (108 | GPIO_ALT_FN_1_IN)
+#define GPIO108_KP_MKOUT5_MD    (108 | GPIO_ALT_FN_2_OUT)
+#define GPIO109_MMCDAT1_MD      (109 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCDAT2_MD      (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS0_MD       (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO111_MMCDAT3_MD      (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS1_MD       (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO112_MMCCMD_MD       (112 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_I2S_SYSCLK_MD   (113 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
+#define GPIO117_I2CSCL_MD       (117 | GPIO_ALT_FN_1_IN)
+#define GPIO118_I2CSDA_MD       (118 | GPIO_ALT_FN_1_IN)
+#endif /* __ASM_ARCH_PXA2XX_GPIO_H */
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
index 8e1b3ead827f..fe9364c83a28 100644
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -12,6 +12,15 @@
 #ifndef __ASM_ARCH_PXA3XX_REGS_H
 #define __ASM_ARCH_PXA3XX_REGS_H
+/*
+ * Oscillator Configuration Register (OSCC)
+ */
+#define OSCC           __REG(0x41350000)  /* Oscillator Configuration Register */
+#define OSCC_PEN       (1 << 11)       /* 13MHz POUT */
 /*
 * Service Power Management Unit (MPMU)
 */
diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h
index c05e4faf85a6..c5b6fde6907c 100644
--- a/include/asm-arm/arch-pxa/tosa.h
+++ b/include/asm-arm/arch-pxa/tosa.h
@@ -23,11 +23,12 @@
 /*
 * SCOOP2 internal GPIOs
 */
+#define TOSA_SCOOP_GPIO_BASE            NR_BUILTIN_GPIO
 #define TOSA_SCOOP_PXA_VCORE1           SCOOP_GPCR_PA11
 #define TOSA_SCOOP_TC6393_REST_IN       SCOOP_GPCR_PA12
-#define TOSA_SCOOP_IR_POWERDWN          SCOOP_GPCR_PA13
+#define TOSA_GPIO_IR_POWERDWN           (TOSA_SCOOP_GPIO_BASE + 2)
-#define TOSA_SCOOP_SD_WP                SCOOP_GPCR_PA14
+#define TOSA_GPIO_SD_WP                 (TOSA_SCOOP_GPIO_BASE + 3)
-#define TOSA_SCOOP_PWR_ON               SCOOP_GPCR_PA15
+#define TOSA_GPIO_PWR_ON                (TOSA_SCOOP_GPIO_BASE + 4)
 #define TOSA_SCOOP_AUD_PWR_ON           SCOOP_GPCR_PA16
 #define TOSA_SCOOP_BT_RESET             SCOOP_GPCR_PA17
 #define TOSA_SCOOP_BT_PWR_EN            SCOOP_GPCR_PA18
@@ -35,7 +36,7 @@
 /* GPIO Direction   1 : output mode / 0:input mode */
 #define TOSA_SCOOP_IO_DIR     ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \
-                TOSA_SCOOP_IR_POWERDWN | TOSA_SCOOP_PWR_ON | TOSA_SCOOP_AUD_PWR_ON |\
+                TOSA_SCOOP_AUD_PWR_ON |\
                TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN )
 /* GPIO out put level when init   1: Hi */
 #define TOSA_SCOOP_IO_OUT     ( TOSA_SCOOP_TC6393_REST_IN )
@@ -43,23 +44,21 @@
 /*
 * SCOOP2 jacket GPIOs
 */
-#define TOSA_SCOOP_JC_BT_LED            SCOOP_GPCR_PA11
+#define TOSA_SCOOP_JC_GPIO_BASE         (NR_BUILTIN_GPIO + 12)
-#define TOSA_SCOOP_JC_NOTE_LED          SCOOP_GPCR_PA12
+#define TOSA_GPIO_BT_LED                (TOSA_SCOOP_JC_GPIO_BASE + 0)
-#define TOSA_SCOOP_JC_CHRG_ERR_LED      SCOOP_GPCR_PA13
+#define TOSA_GPIO_NOTE_LED              (TOSA_SCOOP_JC_GPIO_BASE + 1)
-#define TOSA_SCOOP_JC_USB_PULLUP        SCOOP_GPCR_PA14
+#define TOSA_GPIO_CHRG_ERR_LED          (TOSA_SCOOP_JC_GPIO_BASE + 2)
+#define TOSA_GPIO_USB_PULLUP            (TOSA_SCOOP_JC_GPIO_BASE + 3)
 #define TOSA_SCOOP_JC_TC6393_SUSPEND    SCOOP_GPCR_PA15
 #define TOSA_SCOOP_JC_TC3693_L3V_ON     SCOOP_GPCR_PA16
 #define TOSA_SCOOP_JC_WLAN_DETECT       SCOOP_GPCR_PA17
-#define TOSA_SCOOP_JC_WLAN_LED          SCOOP_GPCR_PA18
+#define TOSA_GPIO_WLAN_LED              (TOSA_SCOOP_JC_GPIO_BASE + 7)
 #define TOSA_SCOOP_JC_CARD_LIMIT_SEL    SCOOP_GPCR_PA19
 /* GPIO Direction   1 : output mode / 0:input mode */
-#define TOSA_SCOOP_JC_IO_DIR ( TOSA_SCOOP_JC_BT_LED | TOSA_SCOOP_JC_NOTE_LED | \
+#define TOSA_SCOOP_JC_IO_DIR ( \
-                TOSA_SCOOP_JC_CHRG_ERR_LED | TOSA_SCOOP_JC_USB_PULLUP | \
                TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \
-                TOSA_SCOOP_JC_WLAN_LED | TOSA_SCOOP_JC_CARD_LIMIT_SEL )
+                TOSA_SCOOP_JC_CARD_LIMIT_SEL )
-/* GPIO out put level when init   1: Hi */
-#define TOSA_SCOOP_JC_IO_OUT ( 0 )
 /*
 * Timing Generator
@@ -74,15 +73,6 @@
 #define TG_HPOSCTL                      0x07
 /*
- * LED
- */
-#define TOSA_SCOOP_LED_BLUE             TOSA_SCOOP_GPCR_PA11
-#define TOSA_SCOOP_LED_GREEN            TOSA_SCOOP_GPCR_PA12
-#define TOSA_SCOOP_LED_ORANGE           TOSA_SCOOP_GPCR_PA13
-#define TOSA_SCOOP_LED_WLAN             TOSA_SCOOP_GPCR_PA18
-/*
 * PXA GPIOs
 */
 #define TOSA_GPIO_POWERON               (0)
@@ -161,12 +151,8 @@
 #define TOSA_IRQ_GPIO_MAIN_BAT_LOW      IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW)
-extern struct platform_device tosascoop_jc_device;
-extern struct platform_device tosascoop_device;
 #define TOSA_KEY_SYNC           KEY_102ND /* ??? */
 #ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES
 #define TOSA_KEY_RECORD         KEY_YEN
 #define TOSA_KEY_ADDRESSBOOK    KEY_KATAKANA
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index 5f717d64ea7d..4881b80f0f90 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -18,6 +18,8 @@ extern struct platform_mmc_slot zylonite_mmc_slot[];
 extern int gpio_backlight;
 extern int gpio_eth_irq;
+extern int wm9713_irq;
 extern int lcd_id;
 extern int lcd_orientation;
diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h
index 3e437b7f425a..206f7a752882 100644
--- a/include/asm-arm/arch-realview/board-eb.h
+++ b/include/asm-arm/arch-realview/board-eb.h
@@ -26,6 +26,26 @@
 /*
 * RealView EB + ARM11MPCore peripheral addresses
 */
+#define REALVIEW_EB_UART0_BASE          0x10009000      /* UART 0 */
+#define REALVIEW_EB_UART1_BASE          0x1000A000      /* UART 1 */
+#define REALVIEW_EB_UART2_BASE          0x1000B000      /* UART 2 */
+#define REALVIEW_EB_UART3_BASE          0x1000C000      /* UART 3 */
+#define REALVIEW_EB_SSP_BASE            0x1000D000      /* Synchronous Serial Port */
+#define REALVIEW_EB_WATCHDOG_BASE       0x10010000      /* watchdog interface */
+#define REALVIEW_EB_TIMER0_1_BASE       0x10011000      /* Timer 0 and 1 */
+#define REALVIEW_EB_TIMER2_3_BASE       0x10012000      /* Timer 2 and 3 */
+#define REALVIEW_EB_GPIO0_BASE          0x10013000      /* GPIO port 0 */
+#define REALVIEW_EB_RTC_BASE            0x10017000      /* Real Time Clock */
+#define REALVIEW_EB_CLCD_BASE           0x10020000      /* CLCD */
+#define REALVIEW_EB_GIC_CPU_BASE        0x10040000      /* Generic interrupt controller CPU interface */
+#define REALVIEW_EB_GIC_DIST_BASE       0x10041000      /* Generic interrupt controller distributor */
+#define REALVIEW_EB_SMC_BASE            0x10080000      /* Static memory controller */
+#define REALVIEW_EB_FLASH_BASE          0x40000000
+#define REALVIEW_EB_FLASH_SIZE          SZ_64M
+#define REALVIEW_EB_ETH_BASE            0x4E000000      /* Ethernet */
+#define REALVIEW_EB_USB_BASE            0x4F000000      /* USB */
 #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
 #define REALVIEW_EB11MP_SCU_BASE        0x10100000      /* SCU registers */
 #define REALVIEW_EB11MP_GIC_CPU_BASE    0x10100100      /* Generic interrupt controller CPU interface */
diff --git a/include/asm-arm/arch-realview/board-pb1176.h b/include/asm-arm/arch-realview/board-pb1176.h
new file mode 100644
index 000000000000..48ce9c833705
--- /dev/null
+++ b/include/asm-arm/arch-realview/board-pb1176.h
@@ -0,0 +1,152 @@
+/*
+ * include/asm-arm/arch-realview/board-pb1176.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __ASM_ARCH_BOARD_PB1176_H
+#define __ASM_ARCH_BOARD_PB1176_H
+#include <asm/arch/platform.h>
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_PB1176_SCTL_BASE               0x10100000 /* System controller */
+#define REALVIEW_PB1176_SMC_BASE                0x10111000 /* SMC */
+#define REALVIEW_PB1176_DMC_BASE                0x10109000 /* DMC configuration */
+#define REALVIEW_PB1176_SDRAM67_BASE            0x70000000 /* SDRAM banks 6 and 7 */
+#define REALVIEW_PB1176_FLASH_BASE              0x30000000
+#define REALVIEW_PB1176_FLASH_SIZE              SZ_64M
+#define REALVIEW_PB1176_TIMER0_1_BASE           0x10104000 /* Timer 0 and 1 */
+#define REALVIEW_PB1176_TIMER2_3_BASE           0x10105000 /* Timer 2 and 3 */
+#define REALVIEW_PB1176_TIMER4_5_BASE           0x10106000 /* Timer 4 and 5 */
+#define REALVIEW_PB1176_WATCHDOG_BASE           0x10107000 /* watchdog interface */
+#define REALVIEW_PB1176_RTC_BASE                0x10108000 /* Real Time Clock */
+#define REALVIEW_PB1176_GPIO0_BASE              0x1010A000 /* GPIO port 0 */
+#define REALVIEW_PB1176_SSP_BASE                0x1010B000 /* Synchronous Serial Port */
+#define REALVIEW_PB1176_UART0_BASE              0x1010C000 /* UART 0 */
+#define REALVIEW_PB1176_UART1_BASE              0x1010D000 /* UART 1 */
+#define REALVIEW_PB1176_UART2_BASE              0x1010E000 /* UART 2 */
+#define REALVIEW_PB1176_UART3_BASE              0x1010F000 /* UART 3 */
+#define REALVIEW_PB1176_CLCD_BASE               0x10112000 /* CLCD */
+#define REALVIEW_PB1176_ETH_BASE                0x3A000000 /* Ethernet */
+#define REALVIEW_PB1176_USB_BASE                0x3B000000 /* USB */
+/*
+ * PCI regions
+ */
+#define REALVIEW_PB1176_PCI_BASE                0x60000000 /* PCI self config */
+#define REALVIEW_PB1176_PCI_CFG_BASE            0x61000000 /* PCI config */
+#define REALVIEW_PB1176_PCI_IO_BASE0            0x62000000 /* PCI IO region */
+#define REALVIEW_PB1176_PCI_MEM_BASE0           0x63000000 /* Memory region 1 */
+#define REALVIEW_PB1176_PCI_MEM_BASE1           0x64000000 /* Memory region 2 */
+#define REALVIEW_PB1176_PCI_MEM_BASE2           0x68000000 /* Memory region 3 */
+#define REALVIEW_PB1176_PCI_BASE_SIZE           0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE       0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE       0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE      0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE      0x04000000 /* 64MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE      0x08000000 /* 128MB */
+#define REALVIEW_DC1176_GIC_CPU_BASE            0x10120000 /* GIC CPU interface, on devchip */
+#define REALVIEW_DC1176_GIC_DIST_BASE           0x10121000 /* GIC distributor, on devchip */
+#define REALVIEW_PB1176_GIC_CPU_BASE            0x10040000 /* GIC CPU interface, on FPGA */
+#define REALVIEW_PB1176_GIC_DIST_BASE           0x10041000 /* GIC distributor, on FPGA */
+#define REALVIEW_PB1176_L220_BASE               0x10110000 /* L220 registers */
+/*
+ * Irqs
+ */
+#define IRQ_DC1176_GIC_START                    32
+#define IRQ_PB1176_GIC_START                    64
+/*
+ * ARM1176 DevChip interrupt sources (primary GIC)
+ */
+#define IRQ_DC1176_WATCHDOG     (IRQ_DC1176_GIC_START + 0)      /* Watchdog timer */
+#define IRQ_DC1176_SOFTINT      (IRQ_DC1176_GIC_START + 1)      /* Software interrupt */
+#define IRQ_DC1176_COMMRx       (IRQ_DC1176_GIC_START + 2)      /* Debug Comm Rx interrupt */
+#define IRQ_DC1176_COMMTx       (IRQ_DC1176_GIC_START + 3)      /* Debug Comm Tx interrupt */
+#define IRQ_DC1176_TIMER0       (IRQ_DC1176_GIC_START + 8)      /* Timer 0 */
+#define IRQ_DC1176_TIMER1       (IRQ_DC1176_GIC_START + 9)      /* Timer 1 */
+#define IRQ_DC1176_TIMER2       (IRQ_DC1176_GIC_START + 10)     /* Timer 2 */
+#define IRQ_DC1176_APC          (IRQ_DC1176_GIC_START + 11)
+#define IRQ_DC1176_IEC          (IRQ_DC1176_GIC_START + 12)
+#define IRQ_DC1176_L2CC         (IRQ_DC1176_GIC_START + 13)
+#define IRQ_DC1176_RTC          (IRQ_DC1176_GIC_START + 14)
+#define IRQ_DC1176_CLCD         (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
+#define IRQ_DC1176_UART0        (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
+#define IRQ_DC1176_UART1        (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
+#define IRQ_DC1176_UART2        (IRQ_DC1176_GIC_START + 20)     /* UART 2 on development chip */
+#define IRQ_DC1176_UART3        (IRQ_DC1176_GIC_START + 21)     /* UART 3 on development chip */
+#define IRQ_DC1176_PB_IRQ2      (IRQ_DC1176_GIC_START + 30)     /* tile GIC */
+#define IRQ_DC1176_PB_IRQ1      (IRQ_DC1176_GIC_START + 31)     /* main GIC */
+/*
+ * RealView PB1176 interrupt sources (secondary GIC)
+ */
+#define IRQ_PB1176_MMCI0A       (IRQ_PB1176_GIC_START + 1)      /* Multimedia Card 0A */
+#define IRQ_PB1176_MMCI0B       (IRQ_PB1176_GIC_START + 2)      /* Multimedia Card 0A */
+#define IRQ_PB1176_KMI0         (IRQ_PB1176_GIC_START + 3)      /* Keyboard/Mouse port 0 */
+#define IRQ_PB1176_KMI1         (IRQ_PB1176_GIC_START + 4)      /* Keyboard/Mouse port 1 */
+#define IRQ_PB1176_SCI          (IRQ_PB1176_GIC_START + 5)
+#define IRQ_PB1176_UART4        (IRQ_PB1176_GIC_START + 6)      /* UART 4 on baseboard */
+#define IRQ_PB1176_CHARLCD      (IRQ_PB1176_GIC_START + 7)      /* Character LCD */
+#define IRQ_PB1176_GPIO1        (IRQ_PB1176_GIC_START + 8)
+#define IRQ_PB1176_GPIO2        (IRQ_PB1176_GIC_START + 9)
+#define IRQ_PB1176_ETH          (IRQ_PB1176_GIC_START + 10)     /* Ethernet controller */
+#define IRQ_PB1176_USB          (IRQ_PB1176_GIC_START + 11)     /* USB controller */
+#define IRQ_PB1176_PISMO        (IRQ_PB1176_GIC_START + 16)
+#define IRQ_PB1176_AACI         (IRQ_PB1176_GIC_START + 19)     /* Audio Codec */
+#define IRQ_PB1176_TIMER0_1     (IRQ_PB1176_GIC_START + 22)
+#define IRQ_PB1176_TIMER2_3     (IRQ_PB1176_GIC_START + 23)
+#define IRQ_PB1176_DMAC         (IRQ_PB1176_GIC_START + 24)     /* DMA controller */
+#define IRQ_PB1176_RTC          (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
+#define IRQ_PB1176_GPIO0        -1
+#define IRQ_PB1176_SSP          -1
+#define IRQ_PB1176_SCTL         -1
+#define NR_GIC_PB1176           2
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PB1176
+ */
+#define NR_IRQS_PB1176          (IRQ_DC1176_GIC_START + 96)
+#if defined(CONFIG_MACH_REALVIEW_PB1176)
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176)
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_PB1176
+#endif
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_PB1176
+#endif
+#endif  /* CONFIG_MACH_REALVIEW_PB1176 */
+#endif  /* __ASM_ARCH_BOARD_PB1176_H */
diff --git a/include/asm-arm/arch-realview/board-pb11mp.h b/include/asm-arm/arch-realview/board-pb11mp.h
new file mode 100644
index 000000000000..a1294d915fa8
--- /dev/null
+++ b/include/asm-arm/arch-realview/board-pb11mp.h
@@ -0,0 +1,186 @@
+/*
+ * include/asm-arm/arch-realview/board-pb11mp.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __ASM_ARCH_BOARD_PB11MP_H
+#define __ASM_ARCH_BOARD_PB11MP_H
+#include <asm/arch/platform.h>
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_PB11MP_UART0_BASE              0x10009000      /* UART 0 */
+#define REALVIEW_PB11MP_UART1_BASE              0x1000A000      /* UART 1 */
+#define REALVIEW_PB11MP_UART2_BASE              0x1000B000      /* UART 2 */
+#define REALVIEW_PB11MP_UART3_BASE              0x1000C000      /* UART 3 */
+#define REALVIEW_PB11MP_SSP_BASE                0x1000D000      /* Synchronous Serial Port */
+#define REALVIEW_PB11MP_WATCHDOG0_BASE          0x1000F000      /* Watchdog 0 */
+#define REALVIEW_PB11MP_WATCHDOG_BASE           0x10010000      /* watchdog interface */
+#define REALVIEW_PB11MP_TIMER0_1_BASE           0x10011000      /* Timer 0 and 1 */
+#define REALVIEW_PB11MP_TIMER2_3_BASE           0x10012000      /* Timer 2 and 3 */
+#define REALVIEW_PB11MP_GPIO0_BASE              0x10013000      /* GPIO port 0 */
+#define REALVIEW_PB11MP_RTC_BASE                0x10017000      /* Real Time Clock */
+#define REALVIEW_PB11MP_TIMER4_5_BASE           0x10018000      /* Timer 4/5 */
+#define REALVIEW_PB11MP_TIMER6_7_BASE           0x10019000      /* Timer 6/7 */
+#define REALVIEW_PB11MP_SCTL_BASE               0x1001A000      /* System Controller */
+#define REALVIEW_PB11MP_CLCD_BASE               0x10020000      /* CLCD */
+#define REALVIEW_PB11MP_ONB_SRAM_BASE           0x10060000      /* On-board SRAM */
+#define REALVIEW_PB11MP_DMC_BASE                0x100E0000      /* DMC configuration */
+#define REALVIEW_PB11MP_SMC_BASE                0x100E1000      /* SMC configuration */
+#define REALVIEW_PB11MP_CAN_BASE                0x100E2000      /* CAN bus */
+#define REALVIEW_PB11MP_CF_BASE                 0x18000000      /* Compact flash */
+#define REALVIEW_PB11MP_CF_MEM_BASE             0x18003000      /* SMC for Compact flash */
+#define REALVIEW_PB11MP_GIC_CPU_BASE            0x1E000000      /* Generic interrupt controller CPU interface */
+#define REALVIEW_PB11MP_FLASH0_BASE             0x40000000
+#define REALVIEW_PB11MP_FLASH0_SIZE             SZ_64M
+#define REALVIEW_PB11MP_FLASH1_BASE             0x44000000
+#define REALVIEW_PB11MP_FLASH1_SIZE             SZ_64M
+#define REALVIEW_PB11MP_ETH_BASE                0x4E000000      /* Ethernet */
+#define REALVIEW_PB11MP_USB_BASE                0x4F000000      /* USB */
+#define REALVIEW_PB11MP_GIC_DIST_BASE           0x1E001000      /* Generic interrupt controller distributor */
+#define REALVIEW_PB11MP_LT_BASE                 0xC0000000      /* Logic Tile expansion */
+#define REALVIEW_PB11MP_SDRAM6_BASE             0x70000000      /* SDRAM bank 6 256MB */
+#define REALVIEW_PB11MP_SDRAM7_BASE             0x80000000      /* SDRAM bank 7 256MB */
+#define REALVIEW_PB11MP_SYS_PLD_CTRL1           0x74
+/*
+ * PB11MPCore PCI regions
+ */
+#define REALVIEW_PB11MP_PCI_BASE                0x90040000      /* PCI-X Unit base */
+#define REALVIEW_PB11MP_PCI_IO_BASE             0x90050000      /* IO Region on AHB */
+#define REALVIEW_PB11MP_PCI_MEM_BASE            0xA0000000      /* MEM Region on AHB */
+#define REALVIEW_PB11MP_PCI_BASE_SIZE           0x10000         /* 16 Kb */
+#define REALVIEW_PB11MP_PCI_IO_SIZE             0x1000          /* 4 Kb */
+#define REALVIEW_PB11MP_PCI_MEM_SIZE            0x20000000      /* 512 MB */
+/*
+ * Testchip peripheral and fpga gic regions
+ */
+#define REALVIEW_TC11MP_SCU_BASE                0x1F000000      /* IRQ, Test chip */
+#define REALVIEW_TC11MP_GIC_CPU_BASE            0x1F000100      /* Test chip interrupt controller CPU interface */
+#define REALVIEW_TC11MP_TWD_BASE                0x1F000700
+#define REALVIEW_TC11MP_TWD_SIZE                0x00000100
+#define REALVIEW_TC11MP_GIC_DIST_BASE           0x1F001000      /* Test chip interrupt controller distributor */
+#define REALVIEW_TC11MP_L220_BASE               0x1F002000      /* L220 registers */
+/*
+ * Irqs
+ */
+#define IRQ_TC11MP_GIC_START                    32
+#define IRQ_PB11MP_GIC_START                    64
+/*
+ * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
+ */
+#define IRQ_TC11MP_AACI         (IRQ_TC11MP_GIC_START + 0)
+#define IRQ_TC11MP_TIMER0_1     (IRQ_TC11MP_GIC_START + 1)
+#define IRQ_TC11MP_TIMER2_3     (IRQ_TC11MP_GIC_START + 2)
+#define IRQ_TC11MP_USB          (IRQ_TC11MP_GIC_START + 3)
+#define IRQ_TC11MP_UART0        (IRQ_TC11MP_GIC_START + 4)
+#define IRQ_TC11MP_UART1        (IRQ_TC11MP_GIC_START + 5)
+#define IRQ_TC11MP_RTC          (IRQ_TC11MP_GIC_START + 6)
+#define IRQ_TC11MP_KMI0         (IRQ_TC11MP_GIC_START + 7)
+#define IRQ_TC11MP_KMI1         (IRQ_TC11MP_GIC_START + 8)
+#define IRQ_TC11MP_ETH          (IRQ_TC11MP_GIC_START + 9)
+#define IRQ_TC11MP_PB_IRQ1      (IRQ_TC11MP_GIC_START + 10)             /* main GIC */
+#define IRQ_TC11MP_PB_IRQ2      (IRQ_TC11MP_GIC_START + 11)             /* tile GIC */
+#define IRQ_TC11MP_PB_FIQ1      (IRQ_TC11MP_GIC_START + 12)             /* main GIC */
+#define IRQ_TC11MP_PB_FIQ2      (IRQ_TC11MP_GIC_START + 13)             /* tile GIC */
+#define IRQ_TC11MP_MMCI0A       (IRQ_TC11MP_GIC_START + 14)
+#define IRQ_TC11MP_MMCI0B       (IRQ_TC11MP_GIC_START + 15)
+#define IRQ_TC11MP_PMU_CPU0     (IRQ_TC11MP_GIC_START + 17)
+#define IRQ_TC11MP_PMU_CPU1     (IRQ_TC11MP_GIC_START + 18)
+#define IRQ_TC11MP_PMU_CPU2     (IRQ_TC11MP_GIC_START + 19)
+#define IRQ_TC11MP_PMU_CPU3     (IRQ_TC11MP_GIC_START + 20)
+#define IRQ_TC11MP_PMU_SCU0     (IRQ_TC11MP_GIC_START + 21)
+#define IRQ_TC11MP_PMU_SCU1     (IRQ_TC11MP_GIC_START + 22)
+#define IRQ_TC11MP_PMU_SCU2     (IRQ_TC11MP_GIC_START + 23)
+#define IRQ_TC11MP_PMU_SCU3     (IRQ_TC11MP_GIC_START + 24)
+#define IRQ_TC11MP_PMU_SCU4     (IRQ_TC11MP_GIC_START + 25)
+#define IRQ_TC11MP_PMU_SCU5     (IRQ_TC11MP_GIC_START + 26)
+#define IRQ_TC11MP_PMU_SCU6     (IRQ_TC11MP_GIC_START + 27)
+#define IRQ_TC11MP_PMU_SCU7     (IRQ_TC11MP_GIC_START + 28)
+#define IRQ_TC11MP_L220_EVENT   (IRQ_TC11MP_GIC_START + 29)
+#define IRQ_TC11MP_L220_SLAVE   (IRQ_TC11MP_GIC_START + 30)
+#define IRQ_TC11MP_L220_DECODE  (IRQ_TC11MP_GIC_START + 31)
+/*
+ * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
+ */
+#define IRQ_PB11MP_WATCHDOG     (IRQ_PB11MP_GIC_START + 0)      /* Watchdog timer */
+#define IRQ_PB11MP_SOFT         (IRQ_PB11MP_GIC_START + 1)      /* Software interrupt */
+#define IRQ_PB11MP_COMMRx       (IRQ_PB11MP_GIC_START + 2)      /* Debug Comm Rx interrupt */
+#define IRQ_PB11MP_COMMTx       (IRQ_PB11MP_GIC_START + 3)      /* Debug Comm Tx interrupt */
+#define IRQ_PB11MP_GPIO0        (IRQ_PB11MP_GIC_START + 6)      /* GPIO 0 */
+#define IRQ_PB11MP_GPIO1        (IRQ_PB11MP_GIC_START + 7)      /* GPIO 1 */
+#define IRQ_PB11MP_GPIO2        (IRQ_PB11MP_GIC_START + 8)      /* GPIO 2 */
+                                                                /* 9 reserved */
+#define IRQ_PB11MP_RTC_GIC1     (IRQ_PB11MP_GIC_START + 10)     /* Real Time Clock */
+#define IRQ_PB11MP_SSP          (IRQ_PB11MP_GIC_START + 11)     /* Synchronous Serial Port */
+#define IRQ_PB11MP_UART0_GIC1   (IRQ_PB11MP_GIC_START + 12)     /* UART 0 on development chip */
+#define IRQ_PB11MP_UART1_GIC1   (IRQ_PB11MP_GIC_START + 13)     /* UART 1 on development chip */
+#define IRQ_PB11MP_UART2        (IRQ_PB11MP_GIC_START + 14)     /* UART 2 on development chip */
+#define IRQ_PB11MP_UART3        (IRQ_PB11MP_GIC_START + 15)     /* UART 3 on development chip */
+#define IRQ_PB11MP_SCI          (IRQ_PB11MP_GIC_START + 16)     /* Smart Card Interface */
+#define IRQ_PB11MP_MMCI0A_GIC1  (IRQ_PB11MP_GIC_START + 17)     /* Multimedia Card 0A */
+#define IRQ_PB11MP_MMCI0B_GIC1  (IRQ_PB11MP_GIC_START + 18)     /* Multimedia Card 0B */
+#define IRQ_PB11MP_AACI_GIC1    (IRQ_PB11MP_GIC_START + 19)     /* Audio Codec */
+#define IRQ_PB11MP_KMI0_GIC1    (IRQ_PB11MP_GIC_START + 20)     /* Keyboard/Mouse port 0 */
+#define IRQ_PB11MP_KMI1_GIC1    (IRQ_PB11MP_GIC_START + 21)     /* Keyboard/Mouse port 1 */
+#define IRQ_PB11MP_CHARLCD      (IRQ_PB11MP_GIC_START + 22)     /* Character LCD */
+#define IRQ_PB11MP_CLCD         (IRQ_PB11MP_GIC_START + 23)     /* CLCD controller */
+#define IRQ_PB11MP_DMAC         (IRQ_PB11MP_GIC_START + 24)     /* DMA controller */
+#define IRQ_PB11MP_PWRFAIL      (IRQ_PB11MP_GIC_START + 25)     /* Power failure */
+#define IRQ_PB11MP_PISMO        (IRQ_PB11MP_GIC_START + 26)     /* PISMO interface */
+#define IRQ_PB11MP_DoC          (IRQ_PB11MP_GIC_START + 27)     /* Disk on Chip memory controller */
+#define IRQ_PB11MP_ETH_GIC1     (IRQ_PB11MP_GIC_START + 28)     /* Ethernet controller */
+#define IRQ_PB11MP_USB_GIC1     (IRQ_PB11MP_GIC_START + 29)     /* USB controller */
+#define IRQ_PB11MP_TSPEN        (IRQ_PB11MP_GIC_START + 30)     /* Touchscreen pen */
+#define IRQ_PB11MP_TSKPAD       (IRQ_PB11MP_GIC_START + 31)     /* Touchscreen keypad */
+#define IRQ_PB11MP_SMC          -1
+#define IRQ_PB11MP_SCTL         -1
+#define NR_GIC_PB11MP           2
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PB11MP
+ */
+#define NR_IRQS_PB11MP          (IRQ_TC11MP_GIC_START + 96)
+#if defined(CONFIG_MACH_REALVIEW_PB11MP)
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_PB11MP
+#endif
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_PB11MP
+#endif
+#endif  /* CONFIG_MACH_REALVIEW_PB11MP */
+#endif  /* __ASM_ARCH_BOARD_PB11MP_H */
diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S
index f17efc65518a..c8c860c3c26e 100644
--- a/include/asm-arm/arch-realview/debug-macro.S
+++ b/include/asm-arm/arch-realview/debug-macro.S
@@ -15,7 +15,7 @@
                mrc     p15, 0, \rx, c1, c0
                tst     \rx, #1                 @ MMU enabled?
                moveq   \rx,      #0x10000000
-                movne   \rx,      #0xf1000000   @ virtual base
+                movne   \rx,      #0xf0000000   @ virtual base
                orr     \rx, \rx, #0x00009000
                .endm
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
index bad8d7ce9bfe..1ee8313ceb6a 100644
--- a/include/asm-arm/arch-realview/hardware.h
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -25,7 +25,7 @@
 #include <asm/sizes.h>
 /* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x)           ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
+#define IO_ADDRESS(x)           (((x) & 0x0fffffff) + 0xf0000000)
 #define __io_address(n)         __io(IO_ADDRESS(n))
 #endif
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
index ad0c911002fc..ccbac59235c6 100644
--- a/include/asm-arm/arch-realview/irqs.h
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -23,6 +23,8 @@
 #define __ASM_ARCH_IRQS_H
 #include <asm/arch/board-eb.h>
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/board-pb1176.h>
 #define IRQ_LOCALTIMER          29
 #define IRQ_LOCALWDOG           30
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 4fd351b5e4a2..424c0aaf46a0 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -32,9 +32,6 @@
 #define REALVIEW_SSRAM_BASE           /* REALVIEW_SSMC_BASE ? */
 #define REALVIEW_SSRAM_SIZE           SZ_2M
-#define REALVIEW_FLASH_BASE           0x40000000
-#define REALVIEW_FLASH_SIZE           SZ_64M
 /* 
 *  SDRAM
 */
@@ -175,42 +172,20 @@
 #define REALVIEW_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
 /*
- * REALVIEW peripheral addresses
+ * RealView common peripheral addresses
 */
 #define REALVIEW_SCTL_BASE            0x10001000        /* System controller */
 #define REALVIEW_I2C_BASE             0x10002000        /* I2C control */
-        /* Reserved 0x10003000 */
 #define REALVIEW_AACI_BASE            0x10004000        /* Audio */
 #define REALVIEW_MMCI0_BASE           0x10005000        /* MMC interface */
 #define REALVIEW_KMI0_BASE            0x10006000        /* KMI interface */
 #define REALVIEW_KMI1_BASE            0x10007000        /* KMI 2nd interface */
 #define REALVIEW_CHAR_LCD_BASE        0x10008000        /* Character LCD */
-#define REALVIEW_UART0_BASE           0x10009000        /* UART 0 */
-#define REALVIEW_UART1_BASE           0x1000A000        /* UART 1 */
-#define REALVIEW_UART2_BASE           0x1000B000        /* UART 2 */
-#define REALVIEW_UART3_BASE           0x1000C000        /* UART 3 */
-#define REALVIEW_SSP_BASE             0x1000D000        /* Synchronous Serial Port */
 #define REALVIEW_SCI_BASE             0x1000E000        /* Smart card controller */
-        /* Reserved 0x1000F000 */
-#define REALVIEW_WATCHDOG_BASE        0x10010000        /* watchdog interface */
-#define REALVIEW_TIMER0_1_BASE        0x10011000        /* Timer 0 and 1 */
-#define REALVIEW_TIMER2_3_BASE        0x10012000        /* Timer 2 and 3 */
-#define REALVIEW_GPIO0_BASE           0x10013000        /* GPIO port 0 */
 #define REALVIEW_GPIO1_BASE           0x10014000        /* GPIO port 1 */
 #define REALVIEW_GPIO2_BASE           0x10015000        /* GPIO port 2 */
-        /* Reserved 0x10016000 */
-#define REALVIEW_RTC_BASE             0x10017000        /* Real Time Clock */
 #define REALVIEW_DMC_BASE             0x10018000        /* DMC configuration */
-#define REALVIEW_PCI_CORE_BASE        0x10019000        /* PCI configuration */
-        /* Reserved 0x1001A000 - 0x1001FFFF */
-#define REALVIEW_CLCD_BASE            0x10020000        /* CLCD */
 #define REALVIEW_DMAC_BASE            0x10030000        /* DMA controller */
-#define REALVIEW_GIC_CPU_BASE         0x10040000        /* Generic interrupt controller CPU interface */
-#define REALVIEW_GIC_DIST_BASE        0x10041000        /* Generic interrupt controller distributor */
-#define REALVIEW_SMC_BASE             0x10080000        /* SMC */
-        /* Reserved 0x10090000 - 0x100EFFFF */
-#define REALVIEW_ETH_BASE             0x4E000000        /* Ethernet */
 /* PCI space */
 #define REALVIEW_PCI_BASE             0x41000000        /* PCI Interface */
diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h
index 08b3db883c36..d55802d645af 100644
--- a/include/asm-arm/arch-realview/scu.h
+++ b/include/asm-arm/arch-realview/scu.h
@@ -1,8 +1,13 @@
 #ifndef __ASMARM_ARCH_SCU_H
 #define __ASMARM_ARCH_SCU_H
-#include <asm/arch/board-eb.h>
+/*
+ * SCU registers
-#define SCU_BASE        REALVIEW_EB11MP_SCU_BASE
+ */
+#define SCU_CTRL                0x00
+#define SCU_CONFIG              0x04
+#define SCU_CPU_STATUS          0x08
+#define SCU_INVALIDATE          0x0c
+#define SCU_FPGA_REVISION       0x10
 #endif
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
index 3d5c2db07a26..4c905d7a13a1 100644
--- a/include/asm-arm/arch-realview/uncompress.h
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -18,28 +18,50 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 #include <asm/hardware.h>
+#include <asm/mach-types.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/board-eb.h>
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/board-pb1176.h>
-#define AMBA_UART_DR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
+#define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
-#define AMBA_UART_LCRH  (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
+#define AMBA_UART_LCRH(base)    (*(volatile unsigned char *)((base) + 0x2c))
-#define AMBA_UART_CR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
+#define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
-#define AMBA_UART_FR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18))
+#define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
+/*
+ * Return the UART base address
+ */
+static inline unsigned long get_uart_base(void)
+{
+        if (machine_is_realview_eb())
+                return REALVIEW_EB_UART0_BASE;
+        else if (machine_is_realview_pb11mp())
+                return REALVIEW_PB11MP_UART0_BASE;
+        else if (machine_is_realview_pb1176())
+                return REALVIEW_PB1176_UART0_BASE;
+        else
+                return 0;
+}
 /*
 * This does not append a newline
 */
 static inline void putc(int c)
 {
-        while (AMBA_UART_FR & (1 << 5))
+        unsigned long base = get_uart_base();
+        while (AMBA_UART_FR(base) & (1 << 5))
                barrier();
-        AMBA_UART_DR = c;
+        AMBA_UART_DR(base) = c;
 }
 static inline void flush(void)
 {
-        while (AMBA_UART_FR & (1 << 3))
+        unsigned long base = get_uart_base();
+        while (AMBA_UART_FR(base) & (1 << 3))
                barrier();
 }
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index dba9df9d8713..ecae9e7f5e45 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -137,7 +137,7 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
 #define S3C2412_CLKDIVN_PDIVN           (1<<2)
 #define S3C2412_CLKDIVN_HDIVN_MASK      (3<<0)
-#define S3C2421_CLKDIVN_ARMDIVN         (1<<3)
+#define S3C2412_CLKDIVN_ARMDIVN         (1<<3)
 #define S3C2412_CLKDIVN_DVSEN           (1<<4)
 #define S3C2412_CLKDIVN_HALFHCLK        (1<<5)
 #define S3C2412_CLKDIVN_USB48DIV        (1<<6)
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 0ad75d716ded..497dd06e2c99 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -529,11 +529,13 @@
 #define S3C2410_GPD14_INP       (0x00 << 28)
 #define S3C2410_GPD14_OUTP      (0x01 << 28)
 #define S3C2410_GPD14_VD22      (0x02 << 28)
+#define S3C2410_GPD14_nSS1      (0x03 << 28)
 #define S3C2410_GPD15           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
 #define S3C2410_GPD15_INP       (0x00 << 30)
 #define S3C2410_GPD15_OUTP      (0x01 << 30)
 #define S3C2410_GPD15_VD23      (0x02 << 30)
+#define S3C2410_GPD15_nSS0      (0x03 << 30)
 #define S3C2410_GPD_PUPDIS(x)  (1<<(x))
@@ -801,12 +803,14 @@
 #define S3C2410_GPG2_INP      (0x00 << 4)
 #define S3C2410_GPG2_OUTP     (0x01 << 4)
 #define S3C2410_GPG2_EINT10   (0x02 << 4)
+#define S3C2410_GPG2_nSS0     (0x03 << 4)
 #define S3C2400_GPG2_CDCLK    (0x02 << 4)
 #define S3C2410_GPG3          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
 #define S3C2410_GPG3_INP      (0x00 << 6)
 #define S3C2410_GPG3_OUTP     (0x01 << 6)
 #define S3C2410_GPG3_EINT11   (0x02 << 6)
+#define S3C2410_GPG3_nSS1     (0x03 << 6)
 #define S3C2400_GPG3_I2SSDO   (0x02 << 6)
 #define S3C2400_GPG3_I2SSDI   (0x03 << 6)
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h b/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h
new file mode 100644
index 000000000000..c8c793e78936
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h
@@ -0,0 +1,29 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-s3c2412-mem.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2412 memory register definitions
+*/
+#ifndef __ASM_ARM_REGS_S3C2412_MEM
+#define __ASM_ARM_REGS_S3C2412_MEM
+#ifndef S3C2412_MEMREG
+#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
+#endif
+#define S3C2412_BANKCFG                 S3C2412_MEMREG(0x00)
+#define S3C2412_BANKCON1                S3C2412_MEMREG(0x04)
+#define S3C2412_BANKCON2                S3C2412_MEMREG(0x08)
+#define S3C2412_BANKCON3                S3C2412_MEMREG(0x0C)
+#define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
+#define S3C2412_TIMEOUT                 S3C2412_MEMREG(0x14)
+#endif /*  __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/include/asm-arm/arch-s3c2410/system-reset.h b/include/asm-arm/arch-s3c2410/system-reset.h
new file mode 100644
index 000000000000..1615bce0c026
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/system-reset.h
@@ -0,0 +1,64 @@
+/* linux/include/asm-arm/arch-s3c2410/system-reset.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - System define for arch_reset() function
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/plat-s3c/regs-watchdog.h>
+#include <asm/arch/regs-clock.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+extern void (*s3c24xx_reset_hook)(void);
+static void
+arch_reset(char mode)
+{
+        struct clk *wdtclk;
+        if (mode == 's') {
+                cpu_reset(0);
+        }
+        if (s3c24xx_reset_hook)
+                s3c24xx_reset_hook();
+        printk("arch_reset: attempting watchdog reset\n");
+        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
+        wdtclk = clk_get(NULL, "watchdog");
+        if (!IS_ERR(wdtclk)) {
+                clk_enable(wdtclk);
+        } else
+                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
+        /* put initial values into count and data */
+        __raw_writel(0x80, S3C2410_WTCNT);
+        __raw_writel(0x80, S3C2410_WTDAT);
+        /* set the watchdog to go and reset... */
+        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
+                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
+        /* wait for reset to assert... */
+        mdelay(500);
+        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+        /* delay to allow the serial port to show the message */
+        mdelay(50);
+        /* we'll take a jump through zero as a poor second */
+        cpu_reset(0);
+}
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 14de4e596f87..ad258085e53b 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -17,12 +17,8 @@
 #include <asm/arch/idle.h>
 #include <asm/arch/reset.h>
-#include <asm/plat-s3c/regs-watchdog.h>
 #include <asm/arch/regs-clock.h>
-#include <linux/clk.h>
-#include <linux/err.h>
 void (*s3c24xx_idle)(void);
 void (*s3c24xx_reset_hook)(void);
@@ -59,44 +55,4 @@ static void arch_idle(void)
                s3c24xx_default_idle();
 }
-static void
+#include <asm/arch/system-reset.h>
-arch_reset(char mode)
-{
-        struct clk *wdtclk;
-        if (mode == 's') {
-                cpu_reset(0);
-        }
-        if (s3c24xx_reset_hook)
-                s3c24xx_reset_hook();
-        printk("arch_reset: attempting watchdog reset\n");
-        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
-        wdtclk = clk_get(NULL, "watchdog");
-        if (!IS_ERR(wdtclk)) {
-                clk_enable(wdtclk);
-        } else
-                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
-        /* put initial values into count and data */
-        __raw_writel(0x80, S3C2410_WTCNT);
-        __raw_writel(0x80, S3C2410_WTDAT);
-        /* set the watchdog to go and reset... */
-        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
-                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
-        /* wait for reset to assert... */
-        mdelay(500);
-        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
-        /* delay to allow the serial port to show the message */
-        mdelay(50);
-        /* we'll take a jump through zero as a poor second */
-        cpu_reset(0);
-}
diff --git a/include/asm-arm/arch-sa1100/gpio.h b/include/asm-arm/arch-sa1100/gpio.h
index e7a9d26e22a8..93d3395b102d 100644
--- a/include/asm-arm/arch-sa1100/gpio.h
+++ b/include/asm-arm/arch-sa1100/gpio.h
@@ -26,35 +26,28 @@
 #include <asm/hardware.h>
 #include <asm/irq.h>
+#include <asm-generic/gpio.h>
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        return 0;
-}
-static inline void gpio_free(unsigned gpio)
-{
-        return;
-}
-extern int gpio_direction_input(unsigned gpio);
-extern int gpio_direction_output(unsigned gpio, int value);
 static inline int gpio_get_value(unsigned gpio)
 {
-        return GPLR & GPIO_GPIO(gpio);
+        if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
+                return GPLR & GPIO_GPIO(gpio);
+        else
+                return __gpio_get_value(gpio);
 }
 static inline void gpio_set_value(unsigned gpio, int value)
 {
-        if (value)
+        if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
-                GPSR = GPIO_GPIO(gpio);
+                if (value)
+                        GPSR = GPIO_GPIO(gpio);
+                else
+                        GPCR = GPIO_GPIO(gpio);
        else
-                GPCR = GPIO_GPIO(gpio);
+                __gpio_set_value(gpio, value);
 }
-#include <asm-generic/gpio.h>                   /* cansleep wrappers */
+#define gpio_cansleep   __gpio_cansleep
 static inline unsigned gpio_to_irq(unsigned gpio)
 {
diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h
index 715e18a4add1..3479de9266e5 100644
--- a/include/asm-arm/cpu-multi32.h
+++ b/include/asm-arm/cpu-multi32.h
@@ -21,6 +21,10 @@ extern struct processor {
         */
        void (*_data_abort)(unsigned long pc);
        /*
+         * Retrieve prefetch fault address
+         */
+        unsigned long (*_prefetch_abort)(unsigned long lr);
+        /*
         * Set up any processor specifics
         */
        void (*_proc_init)(void);
diff --git a/include/asm-arm/glue.h b/include/asm-arm/glue.h
index 22274ce81375..a97a182ba287 100644
--- a/include/asm-arm/glue.h
+++ b/include/asm-arm/glue.h
@@ -40,83 +40,110 @@
 *        v6_early      - ARMv6 generic early abort handler
 *        v7_early      - ARMv7 generic early abort handler
 */
-#undef CPU_ABORT_HANDLER
+#undef CPU_DABORT_HANDLER
-#undef MULTI_ABORT
+#undef MULTI_DABORT
 #if defined(CONFIG_CPU_ARM610)
-# ifdef CPU_ABORT_HANDLER
+# ifdef CPU_DABORT_HANDLER
-#  define MULTI_ABORT 1
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER cpu_arm6_data_abort
+#  define CPU_DABORT_HANDLER cpu_arm6_data_abort
 # endif
 #endif
 #if defined(CONFIG_CPU_ARM710)
-# ifdef CPU_ABORT_HANDLER
+# ifdef CPU_DABORT_HANDLER
-#  define MULTI_ABORT 1
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER cpu_arm7_data_abort
+#  define CPU_DABORT_HANDLER cpu_arm7_data_abort
 # endif
 #endif
 #ifdef CONFIG_CPU_ABRT_LV4T
-# ifdef CPU_ABORT_HANDLER
+# ifdef CPU_DABORT_HANDLER
-#  define MULTI_ABORT 1
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v4t_late_abort
+#  define CPU_DABORT_HANDLER v4t_late_abort
 # endif
 #endif
 #ifdef CONFIG_CPU_ABRT_EV4
-# ifdef CPU_ABORT_HANDLER
+# ifdef CPU_DABORT_HANDLER
-#  define MULTI_ABORT 1
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v4_early_abort
+#  define CPU_DABORT_HANDLER v4_early_abort
 # endif
 #endif
 #ifdef CONFIG_CPU_ABRT_EV4T
-# ifdef CPU_ABORT_HANDLER
+# ifdef CPU_DABORT_HANDLER
-#  define MULTI_ABORT 1
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v4t_early_abort
+#  define CPU_DABORT_HANDLER v4t_early_abort
 # endif
 #endif
 #ifdef CONFIG_CPU_ABRT_EV5TJ
-# ifdef CPU_ABORT_HANDLER
+# ifdef CPU_DABORT_HANDLER
-#  define MULTI_ABORT 1
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v5tj_early_abort
+#  define CPU_DABORT_HANDLER v5tj_early_abort
 # endif
 #endif
 #ifdef CONFIG_CPU_ABRT_EV5T
-# ifdef CPU_ABORT_HANDLER
+# ifdef CPU_DABORT_HANDLER
-#  define MULTI_ABORT 1
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v5t_early_abort
+#  define CPU_DABORT_HANDLER v5t_early_abort
 # endif
 #endif
 #ifdef CONFIG_CPU_ABRT_EV6
-# ifdef CPU_ABORT_HANDLER
+# ifdef CPU_DABORT_HANDLER
-#  define MULTI_ABORT 1
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v6_early_abort
+#  define CPU_DABORT_HANDLER v6_early_abort
 # endif
 #endif
 #ifdef CONFIG_CPU_ABRT_EV7
-# ifdef CPU_ABORT_HANDLER
+# ifdef CPU_DABORT_HANDLER
-#  define MULTI_ABORT 1
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v7_early_abort
+#  define CPU_DABORT_HANDLER v7_early_abort
 # endif
 #endif
-#ifndef CPU_ABORT_HANDLER
+#ifndef CPU_DABORT_HANDLER
 #error Unknown data abort handler type
 #endif
+/*
+ * Prefetch abort handler.  If the CPU has an IFAR use that, otherwise
+ * use the address of the aborted instruction
+ */
+#undef CPU_PABORT_HANDLER
+#undef MULTI_PABORT
+#ifdef CONFIG_CPU_PABRT_IFAR
+# ifdef CPU_PABORT_HANDLER
+#  define MULTI_PABORT 1
+# else
+#  define CPU_PABORT_HANDLER(reg, insn) mrc p15, 0, reg, cr6, cr0, 2
+# endif
+#endif
+#ifdef CONFIG_CPU_PABRT_NOIFAR
+# ifdef CPU_PABORT_HANDLER
+#  define MULTI_PABORT 1
+# else
+#  define CPU_PABORT_HANDLER(reg, insn) mov reg, insn
+# endif
+#endif
+#ifndef CPU_PABORT_HANDLER
+#error Unknown prefetch abort handler type
+#endif
 #endif
diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h
deleted file mode 100644
index 7d28eb5a1758..000000000000
--- a/include/asm-arm/hardware/arm_scu.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef ASMARM_HARDWARE_ARM_SCU_H
-#define ASMARM_HARDWARE_ARM_SCU_H
-#include <asm/arch/scu.h>
-/*
- * SCU registers
- */
-#define SCU_CTRL                0x00
-#define SCU_CONFIG              0x04
-#define SCU_CPU_STATUS          0x08
-#define SCU_INVALIDATE          0x0c
-#define SCU_FPGA_REVISION       0x10
-#endif
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index ede377ec9147..18f6937f5010 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -29,6 +29,7 @@ extern void gpio_line_config(int line, int direction);
 extern int  gpio_line_get(int line);
 extern void gpio_line_set(int line, int value);
 extern int init_atu;
+extern int iop3xx_get_init_atu(void);
 #endif
@@ -112,14 +113,6 @@ extern int init_atu;
 #define IOP3XX_INIT_ATU_DISABLE -1
 #define IOP3XX_INIT_ATU_ENABLE   1
-#ifdef CONFIG_IOP3XX_ATU
-#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
-                                IOP3XX_INIT_ATU_ENABLE : init_atu)
-#else
-#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
-                                IOP3XX_INIT_ATU_DISABLE : init_atu)
-#endif
 /* Messaging Unit  */
 #define IOP3XX_IMR0             (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
 #define IOP3XX_IMR1             (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h
index d37bf7443264..dfb8330599f9 100644
--- a/include/asm-arm/hardware/scoop.h
+++ b/include/asm-arm/hardware/scoop.h
@@ -40,6 +40,7 @@ struct scoop_config {
        unsigned short io_dir;
        unsigned short suspend_clr;
        unsigned short suspend_set;
+        int gpio_base;
 };
 /* Structure for linking scoop devices to PCMCIA sockets */
@@ -62,7 +63,7 @@ struct scoop_pcmcia_config {
 extern struct scoop_pcmcia_config *platform_scoop_config;
 void reset_scoop(struct device *dev);
-unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
+unsigned short __deprecated set_scoop_gpio(struct device *dev, unsigned short bit);
-unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit);
+unsigned short __deprecated reset_scoop_gpio(struct device *dev, unsigned short bit);
 unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
 void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);
diff --git a/include/asm-arm/hwcap.h b/include/asm-arm/hwcap.h
index 01a1391d3014..81f4c899a555 100644
--- a/include/asm-arm/hwcap.h
+++ b/include/asm-arm/hwcap.h
@@ -15,6 +15,7 @@
 #define HWCAP_JAVA      256
 #define HWCAP_IWMMXT    512
 #define HWCAP_CRUNCH    1024
+#define HWCAP_THUMBEE   2048
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*
diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h
index 24621c49a0c7..9d4f6b5ea419 100644
--- a/include/asm-arm/mach/pci.h
+++ b/include/asm-arm/mach/pci.h
@@ -55,6 +55,7 @@ void pci_common_init(struct hw_pci *);
 extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
 extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
 extern void iop3xx_pci_preinit(void);
+extern void iop3xx_pci_preinit_cond(void);
 extern int dc21285_setup(int nr, struct pci_sys_data *);
 extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index d9bfb39adabf..9ba4d7136e6b 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -217,7 +217,10 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #ifndef CONFIG_DISCONTIGMEM
 #define ARCH_PFN_OFFSET         PHYS_PFN_OFFSET
+#ifndef CONFIG_SPARSEMEM
 #define pfn_valid(pfn)          ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
+#endif
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr)  ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
diff --git a/include/asm-arm/plat-orion/ehci-orion.h b/include/asm-arm/plat-orion/ehci-orion.h
new file mode 100644
index 000000000000..785705651e24
--- /dev/null
+++ b/include/asm-arm/plat-orion/ehci-orion.h
@@ -0,0 +1,19 @@
+/*
+ * include/asm-arm/plat-orion/ehci-orion.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_PLAT_ORION_EHCI_ORION_H
+#define __ASM_PLAT_ORION_EHCI_ORION_H
+#include <linux/mbus.h>
+struct orion_ehci_data {
+        struct mbus_dram_target_info    *dram;
+};
+#endif
diff --git a/include/asm-arm/plat-orion/irq.h b/include/asm-arm/plat-orion/irq.h
new file mode 100644
index 000000000000..94aeed919d5b
--- /dev/null
+++ b/include/asm-arm/plat-orion/irq.h
@@ -0,0 +1,17 @@
+/*
+ * include/asm-arm/plat-orion/irq.h
+ *
+ * Marvell Orion SoC IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_PLAT_ORION_IRQ_H
+#define __ASM_PLAT_ORION_IRQ_H
+void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
+#endif
diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/plat-orion/orion_nand.h
index 143c38e2fa0b..ffd3852a0dd7 100644
--- a/include/asm-arm/arch-orion/platform.h
+++ b/include/asm-arm/plat-orion/orion_nand.h
@@ -1,15 +1,13 @@
 /*
- * asm-arm/arch-orion/platform.h
+ * include/asm-arm/plat-orion/orion_nand.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#ifndef __ASM_ARCH_PLATFORM_H__
+#ifndef __ASM_PLAT_ORION_ORION_NAND_H
-#define __ASM_ARCH_PLATFORM_H__
+#define __ASM_PLAT_ORION_ORION_NAND_H
 /*
 * Device bus NAND private data
@@ -22,4 +20,5 @@ struct orion_nand_data {
        u8 width;       /* buswidth */
 };
 #endif
diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h
new file mode 100644
index 000000000000..6434ac685d21
--- /dev/null
+++ b/include/asm-arm/plat-orion/pcie.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/plat-orion/pcie.h
+ *
+ * Marvell Orion SoC PCIe handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_PLAT_ORION_PCIE_H
+#define __ASM_PLAT_ORION_PCIE_H
+u32 orion_pcie_dev_id(void __iomem *base);
+u32 orion_pcie_rev(void __iomem *base);
+int orion_pcie_link_up(void __iomem *base);
+int orion_pcie_get_local_bus_nr(void __iomem *base);
+void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
+void orion_pcie_setup(void __iomem *base,
+                      struct mbus_dram_target_info *dram);
+int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
+                       u32 devfn, int where, int size, u32 *val);
+int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
+                           u32 devfn, int where, int size, u32 *val);
+int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
+                          u32 devfn, int where, int size, u32 *val);
+int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
+                       u32 devfn, int where, int size, u32 val);
+#endif
diff --git a/include/asm-arm/plat-orion/time.h b/include/asm-arm/plat-orion/time.h
new file mode 100644
index 000000000000..0e85cc8f44d9
--- /dev/null
+++ b/include/asm-arm/plat-orion/time.h
@@ -0,0 +1,17 @@
+/*
+ * include/asm-arm/plat-orion/time.h
+ *
+ * Marvell Orion SoC time handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_PLAT_ORION_TIME_H
+#define __ASM_PLAT_ORION_TIME_H
+void orion_time_init(unsigned int irq, unsigned int tclk);
+#endif
diff --git a/include/asm-arm/sparsemem.h b/include/asm-arm/sparsemem.h
new file mode 100644
index 000000000000..277158191a0d
--- /dev/null
+++ b/include/asm-arm/sparsemem.h
@@ -0,0 +1,10 @@
+#ifndef ASMARM_SPARSEMEM_H
+#define ASMARM_SPARSEMEM_H
+#include <asm/memory.h>
+#define MAX_PHYSADDR_BITS       32
+#define MAX_PHYSMEM_BITS        32
+#define SECTION_SIZE_BITS       NODE_MEM_SIZE_BITS
+#endif
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index 41784357a204..f5a664786311 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -62,6 +62,9 @@ struct thread_info {
        struct crunch_state     crunchstate;
        union fp_state          fpstate __attribute__((aligned(8)));
        union vfp_state         vfpstate;
+#ifdef CONFIG_ARM_THUMBEE
+        unsigned long           thumbee_state;  /* ThumbEE Handler Base register */
+#endif
        struct restart_block    restart_block;
 };
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index 88e868b7aae0..7c570082b1e0 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -376,9 +376,11 @@
 #define __NR_kexec_load                 (__NR_SYSCALL_BASE+347)
 #define __NR_utimensat                  (__NR_SYSCALL_BASE+348)
 #define __NR_signalfd                   (__NR_SYSCALL_BASE+349)
-#define __NR_timerfd                    (__NR_SYSCALL_BASE+350)
+#define __NR_timerfd_create             (__NR_SYSCALL_BASE+350)
 #define __NR_eventfd                    (__NR_SYSCALL_BASE+351)
 #define __NR_fallocate                  (__NR_SYSCALL_BASE+352)
+#define __NR_timerfd_settime            (__NR_SYSCALL_BASE+353)
+#define __NR_timerfd_gettime            (__NR_SYSCALL_BASE+354)
 /*
 * The following SWIs are ARM private.
diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h
index 7597b0bd2f01..a4e2d28bfb58 100644
--- a/include/asm-avr32/arch-at32ap/board.h
+++ b/include/asm-avr32/arch-at32ap/board.h
@@ -38,9 +38,7 @@ struct platform_device *
 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
                     unsigned long fbmem_start, unsigned long fbmem_len);
-struct usba_platform_data {
+struct usba_platform_data;
-        int vbus_pin;
-};
 struct platform_device *
 at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
@@ -68,7 +66,10 @@ struct platform_device *at32_add_device_pwm(u32 mask);
 struct platform_device *
 at32_add_device_ssc(unsigned int id, unsigned int flags);
-struct platform_device *at32_add_device_twi(unsigned int id);
+struct i2c_board_info;
+struct platform_device *at32_add_device_twi(unsigned int id,
+                                            struct i2c_board_info *b,
+                                            unsigned int n);
 struct platform_device *at32_add_device_mci(unsigned int id);
 struct platform_device *at32_add_device_ac97c(unsigned int id);
 struct platform_device *at32_add_device_abdac(unsigned int id);
diff --git a/include/asm-avr32/arch-at32ap/pm.h b/include/asm-avr32/arch-at32ap/pm.h
new file mode 100644
index 000000000000..356e43064903
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/pm.h
@@ -0,0 +1,48 @@
+/*
+ * AVR32 AP Power Management.
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_AVR32_ARCH_PM_H
+#define __ASM_AVR32_ARCH_PM_H
+/* Possible arguments to the "sleep" instruction */
+#define CPU_SLEEP_IDLE          0
+#define CPU_SLEEP_FROZEN        1
+#define CPU_SLEEP_STANDBY       2
+#define CPU_SLEEP_STOP          3
+#define CPU_SLEEP_STATIC        5
+#ifndef __ASSEMBLY__
+extern void cpu_enter_idle(void);
+extern bool disable_idle_sleep;
+static inline void cpu_disable_idle_sleep(void)
+{
+        disable_idle_sleep = true;
+}
+static inline void cpu_enable_idle_sleep(void)
+{
+        disable_idle_sleep = false;
+}
+static inline void cpu_idle_sleep(void)
+{
+        /*
+         * If we're using the COUNT and COMPARE registers for
+         * timekeeping, we can't use the IDLE state.
+         */
+        if (disable_idle_sleep)
+                cpu_relax();
+        else
+                cpu_enter_idle();
+}
+#endif
+#endif /* __ASM_AVR32_ARCH_PM_H */
diff --git a/include/asm-avr32/arch-at32ap/time.h b/include/asm-avr32/arch-at32ap/time.h
deleted file mode 100644
index cc8a43418a4d..000000000000
--- a/include/asm-avr32/arch-at32ap/time.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (C) 2007 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
-#define _ASM_AVR32_ARCH_AT32AP_TIME_H
-#include <linux/platform_device.h>
-extern struct irqaction timer_irqaction;
-extern struct platform_device at32_systc0_device;
-extern void local_timer_interrupt(int irq, void *dev_id);
-#define TIMER_BCR                                       0x000000c0
-#define TIMER_BCR_SYNC                                           0
-#define TIMER_BMR                                       0x000000c4
-#define TIMER_BMR_TC0XC0S                                        0
-#define TIMER_BMR_TC1XC1S                                        2
-#define TIMER_BMR_TC2XC2S                                        4
-#define TIMER_CCR                                       0x00000000
-#define TIMER_CCR_CLKDIS                                         1
-#define TIMER_CCR_CLKEN                                          0
-#define TIMER_CCR_SWTRG                                          2
-#define TIMER_CMR                                       0x00000004
-#define TIMER_CMR_ABETRG                                        10
-#define TIMER_CMR_ACPA                                          16
-#define TIMER_CMR_ACPC                                          18
-#define TIMER_CMR_AEEVT                                         20
-#define TIMER_CMR_ASWTRG                                        22
-#define TIMER_CMR_BCPB                                          24
-#define TIMER_CMR_BCPC                                          26
-#define TIMER_CMR_BEEVT                                         28
-#define TIMER_CMR_BSWTRG                                        30
-#define TIMER_CMR_BURST                                          4
-#define TIMER_CMR_CLKI                                           3
-#define TIMER_CMR_CPCDIS                                         7
-#define TIMER_CMR_CPCSTOP                                        6
-#define TIMER_CMR_CPCTRG                                        14
-#define TIMER_CMR_EEVT                                          10
-#define TIMER_CMR_EEVTEDG                                        8
-#define TIMER_CMR_ENETRG                                        12
-#define TIMER_CMR_ETRGEDG                                        8
-#define TIMER_CMR_LDBDIS                                         7
-#define TIMER_CMR_LDBSTOP                                        6
-#define TIMER_CMR_LDRA                                          16
-#define TIMER_CMR_LDRB                                          18
-#define TIMER_CMR_TCCLKS                                         0
-#define TIMER_CMR_WAVE                                          15
-#define TIMER_CMR_WAVSEL                                        13
-#define TIMER_CV                                        0x00000010
-#define TIMER_CV_CV                                              0
-#define TIMER_IDR                                       0x00000028
-#define TIMER_IDR_COVFS                                          0
-#define TIMER_IDR_CPAS                                           2
-#define TIMER_IDR_CPBS                                           3
-#define TIMER_IDR_CPCS                                           4
-#define TIMER_IDR_ETRGS                                          7
-#define TIMER_IDR_LDRAS                                          5
-#define TIMER_IDR_LDRBS                                          6
-#define TIMER_IDR_LOVRS                                          1
-#define TIMER_IER                                       0x00000024
-#define TIMER_IER_COVFS                                          0
-#define TIMER_IER_CPAS                                           2
-#define TIMER_IER_CPBS                                           3
-#define TIMER_IER_CPCS                                           4
-#define TIMER_IER_ETRGS                                          7
-#define TIMER_IER_LDRAS                                          5
-#define TIMER_IER_LDRBS                                          6
-#define TIMER_IER_LOVRS                                          1
-#define TIMER_IMR                                       0x0000002c
-#define TIMER_IMR_COVFS                                          0
-#define TIMER_IMR_CPAS                                           2
-#define TIMER_IMR_CPBS                                           3
-#define TIMER_IMR_CPCS                                           4
-#define TIMER_IMR_ETRGS                                          7
-#define TIMER_IMR_LDRAS                                          5
-#define TIMER_IMR_LDRBS                                          6
-#define TIMER_IMR_LOVRS                                          1
-#define TIMER_RA                                        0x00000014
-#define TIMER_RA_RA                                              0
-#define TIMER_RB                                        0x00000018
-#define TIMER_RB_RB                                              0
-#define TIMER_RC                                        0x0000001c
-#define TIMER_RC_RC                                              0
-#define TIMER_SR                                        0x00000020
-#define TIMER_SR_CLKSTA                                         16
-#define TIMER_SR_COVFS                                           0
-#define TIMER_SR_CPAS                                            2
-#define TIMER_SR_CPBS                                            3
-#define TIMER_SR_CPCS                                            4
-#define TIMER_SR_ETRGS                                           7
-#define TIMER_SR_LDRAS                                           5
-#define TIMER_SR_LDRBS                                           6
-#define TIMER_SR_LOVRS                                           1
-#define TIMER_SR_MTIOA                                          17
-#define TIMER_SR_MTIOB                                          18
-/* Bit manipulation macros */
-#define TIMER_BIT(name)         (1 << TIMER_##name)
-#define TIMER_BF(name,value)    ((value) << TIMER_##name)
-/* Register access macros */
-#define timer_read(port,instance,reg) \
-        __raw_readl(port + (0x40 * instance) + TIMER_##reg)
-#define timer_write(port,instance,reg,value) \
-        __raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
-#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
diff --git a/include/asm-avr32/asm.h b/include/asm-avr32/asm.h
index 515c7618952b..a2c64f404b98 100644
--- a/include/asm-avr32/asm.h
+++ b/include/asm-avr32/asm.h
@@ -12,10 +12,10 @@
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
-#define mask_interrupts         ssrf    SR_GM_BIT
+#define mask_interrupts         ssrf    SYSREG_GM_OFFSET
-#define mask_exceptions         ssrf    SR_EM_BIT
+#define mask_exceptions         ssrf    SYSREG_EM_OFFSET
-#define unmask_interrupts       csrf    SR_GM_BIT
+#define unmask_interrupts       csrf    SYSREG_GM_OFFSET
-#define unmask_exceptions       csrf    SR_EM_BIT
+#define unmask_exceptions       csrf    SYSREG_EM_OFFSET
 #ifdef CONFIG_FRAME_POINTER
        .macro  save_fp
diff --git a/include/asm-avr32/intc.h b/include/asm-avr32/intc.h
deleted file mode 100644
index 1ac9ca75e8fd..000000000000
--- a/include/asm-avr32/intc.h
+++ /dev/null
@@ -1,128 +0,0 @@
-#ifndef __ASM_AVR32_INTC_H
-#define __ASM_AVR32_INTC_H
-#include <linux/sysdev.h>
-#include <linux/interrupt.h>
-struct irq_controller;
-struct irqaction;
-struct pt_regs;
-struct platform_device;
-/* Information about the internal interrupt controller */
-struct intc_device {
-        /* ioremapped address of configuration block */
-        void __iomem *regs;
-        /* the physical device */
-        struct platform_device *pdev;
-        /* Number of interrupt lines per group. */
-        unsigned int irqs_per_group;
-        /* The highest group ID + 1 */
-        unsigned int nr_groups;
-        /*
-         * Bitfield indicating which groups are actually in use.  The
-         * size of the array is
-         * ceil(group_max / (8 * sizeof(unsigned int))).
-         */
-        unsigned int group_mask[];
-};
-struct irq_controller_class {
-        /*
-         * A short name identifying this kind of controller.
-         */
-        const char *typename;
-        /*
-         * Handle the IRQ.  Must do any necessary acking and masking.
-         */
-        irqreturn_t (*handle)(int irq, void *dev_id, struct pt_regs *regs);
-        /*
-         * Register a new IRQ handler.
-         */
-        int (*setup)(struct irq_controller *ctrl, unsigned int irq,
-                     struct irqaction *action);
-        /*
-         * Unregister a IRQ handler.
-         */
-        void (*free)(struct irq_controller *ctrl, unsigned int irq,
-                     void *dev_id);
-        /*
-         * Mask the IRQ in the interrupt controller.
-         */
-        void (*mask)(struct irq_controller *ctrl, unsigned int irq);
-        /*
-         * Unmask the IRQ in the interrupt controller.
-         */
-        void (*unmask)(struct irq_controller *ctrl, unsigned int irq);
-        /*
-         * Set the type of the IRQ. See below for possible types.
-         * Return -EINVAL if a given type is not supported
-         */
-        int (*set_type)(struct irq_controller *ctrl, unsigned int irq,
-                        unsigned int type);
-        /*
-         * Return the IRQ type currently set
-         */
-        unsigned int (*get_type)(struct irq_controller *ctrl, unsigned int irq);
-};
-struct irq_controller {
-        struct irq_controller_class *class;
-        unsigned int irq_group;
-        unsigned int first_irq;
-        unsigned int nr_irqs;
-        struct list_head list;
-};
-struct intc_group_desc {
-        struct irq_controller *ctrl;
-        irqreturn_t (*handle)(int, void *, struct pt_regs *);
-        unsigned long flags;
-        void *dev_id;
-        const char *devname;
-};
-/*
- * The internal interrupt controller.  Defined in board/part-specific
- * devices.c.
- * TODO: Should probably be defined per-cpu.
- */
-extern struct intc_device intc;
-extern int request_internal_irq(unsigned int irq,
-                                irqreturn_t (*handler)(int, void *, struct pt_regs *),
-                                unsigned long irqflags,
-                                const char *devname, void *dev_id);
-extern void free_internal_irq(unsigned int irq);
-/* Only used by time_init() */
-extern int setup_internal_irq(unsigned int irq, struct intc_group_desc *desc);
-/*
- * Set interrupt priority for a given group. `group' can be found by
- * using irq_to_group(irq). Priority can be from 0 (lowest) to 3
- * (highest). Higher-priority interrupts will preempt lower-priority
- * interrupts (unless interrupts are masked globally).
- *
- * This function does not check for conflicts within a group.
- */
-extern int intc_set_priority(unsigned int group,
-                             unsigned int priority);
-/*
- * Returns a bitmask of pending interrupts in a group.
- */
-extern unsigned long intc_get_pending(unsigned int group);
-/*
- * Register a new external interrupt controller.  Returns the first
- * external IRQ number that is assigned to the new controller.
- */
-extern int intc_register_controller(struct irq_controller *ctrl);
-#endif /* __ASM_AVR32_INTC_H */
diff --git a/include/asm-avr32/irq.h b/include/asm-avr32/irq.h
index 9315724c0596..c563b7720c1a 100644
--- a/include/asm-avr32/irq.h
+++ b/include/asm-avr32/irq.h
@@ -14,6 +14,11 @@
 #ifndef __ASSEMBLER__
 int nmi_enable(void);
 void nmi_disable(void);
+/*
+ * Returns a bitmask of pending interrupts in a group.
+ */
+extern unsigned long intc_get_pending(unsigned int group);
 #endif
 #endif /* __ASM_AVR32_IOCTLS_H */
diff --git a/include/asm-avr32/page.h b/include/asm-avr32/page.h
index 5582968feee8..cbbc5ca9728b 100644
--- a/include/asm-avr32/page.h
+++ b/include/asm-avr32/page.h
@@ -8,13 +8,11 @@
 #ifndef __ASM_AVR32_PAGE_H
 #define __ASM_AVR32_PAGE_H
+#include <linux/const.h>
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT      12
-#ifdef __ASSEMBLY__
+#define PAGE_SIZE       (_AC(1, UL) << PAGE_SHIFT)
-#define PAGE_SIZE       (1 << PAGE_SHIFT)
-#else
-#define PAGE_SIZE       (1UL << PAGE_SHIFT)
-#endif
 #define PAGE_MASK       (~(PAGE_SIZE-1))
 #define PTE_MASK        PAGE_MASK
diff --git a/include/asm-avr32/serial.h b/include/asm-avr32/serial.h
new file mode 100644
index 000000000000..5ecaebc22b02
--- /dev/null
+++ b/include/asm-avr32/serial.h
@@ -0,0 +1,13 @@
+#ifndef _ASM_SERIAL_H
+#define _ASM_SERIAL_H
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD (1843200 / 16)
+#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-avr32/xor.h b/include/asm-avr32/xor.h
new file mode 100644
index 000000000000..99c87aa0af4f
--- /dev/null
+++ b/include/asm-avr32/xor.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_XOR_H
+#define _ASM_XOR_H
+#include <asm-generic/xor.h>
+#endif
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
index 5abaa2cee8db..16d493574ba8 100644
--- a/include/asm-blackfin/dma.h
+++ b/include/asm-blackfin/dma.h
@@ -33,7 +33,6 @@
 #include <linux/slab.h>
 #include <asm/irq.h>
 #include <asm/signal.h>
-#include <asm/semaphore.h>
 #include <linux/kernel.h>
 #include <asm/mach/dma.h>
diff --git a/include/asm-frv/topology.h b/include/asm-frv/topology.h
index abe7298742ac..942724352705 100644
--- a/include/asm-frv/topology.h
+++ b/include/asm-frv/topology.h
@@ -5,10 +5,8 @@
 #error NUMA not supported yet
-#else /* !CONFIG_NUMA */
+#endif /* CONFIG_NUMA */
 #include <asm-generic/topology.h>
-#endif /* CONFIG_NUMA */
 #endif /* _ASM_TOPOLOGY_H */
diff --git a/include/asm-generic/topology.h b/include/asm-generic/topology.h
index 342a2a0105c4..a6aea79bca4f 100644
--- a/include/asm-generic/topology.h
+++ b/include/asm-generic/topology.h
@@ -27,6 +27,8 @@
 #ifndef _ASM_GENERIC_TOPOLOGY_H
 #define _ASM_GENERIC_TOPOLOGY_H
+#ifndef CONFIG_NUMA
 /* Other architectures wishing to use this simple topology API should fill
   in the below functions as appropriate in their own <asm/topology.h> file. */
 #ifndef cpu_to_node
@@ -52,4 +54,16 @@
                                )
 #endif
+#endif  /* CONFIG_NUMA */
+/* returns pointer to cpumask for specified node */
+#ifndef node_to_cpumask_ptr
+#define node_to_cpumask_ptr(v, node)                                    \
+                cpumask_t _##v = node_to_cpumask(node), *v = &_##v
+#define node_to_cpumask_ptr_next(v, node)                               \
+                          _##v = node_to_cpumask(node)
+#endif
 #endif /* _ASM_GENERIC_TOPOLOGY_H */
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
index 6f6d69e39ff5..ee118b901de4 100644
--- a/include/asm-ia64/sn/nodepda.h
+++ b/include/asm-ia64/sn/nodepda.h
@@ -9,7 +9,6 @@
 #define _ASM_IA64_SN_NODEPDA_H
-#include <asm/semaphore.h>
 #include <asm/irq.h>
 #include <asm/sn/arch.h>
 #include <asm/sn/intr.h>
diff --git a/include/asm-ia64/topology.h b/include/asm-ia64/topology.h
index 2d67b72b18d0..f2f72ef2a897 100644
--- a/include/asm-ia64/topology.h
+++ b/include/asm-ia64/topology.h
@@ -93,7 +93,7 @@ void build_cpu_to_node_map(void);
        .cache_nice_tries       = 2,                    \
        .busy_idx               = 3,                    \
        .idle_idx               = 2,                    \
-        .newidle_idx            = 0, /* unused */       \
+        .newidle_idx            = 2,                    \
        .wake_idx               = 1,                    \
        .forkexec_idx           = 1,                    \
        .flags                  = SD_LOAD_BALANCE       \
@@ -116,6 +116,11 @@ void build_cpu_to_node_map(void);
 #define smt_capable()                           (smp_num_siblings > 1)
 #endif
+#define pcibus_to_cpumask(bus)  (pcibus_to_node(bus) == -1 ? \
+                                        CPU_MASK_ALL : \
+                                        node_to_cpumask(pcibus_to_node(bus)) \
+                                )
 #include <asm-generic/topology.h>
 #endif /* _ASM_IA64_TOPOLOGY_H */
diff --git a/include/asm-powerpc/topology.h b/include/asm-powerpc/topology.h
index ca23b681ad05..100c6fbfc587 100644
--- a/include/asm-powerpc/topology.h
+++ b/include/asm-powerpc/topology.h
@@ -96,11 +96,10 @@ static inline void sysfs_remove_device_from_node(struct sys_device *dev,
 {
 }
+#endif /* CONFIG_NUMA */
 #include <asm-generic/topology.h>
-#endif /* CONFIG_NUMA */
 #ifdef CONFIG_SMP
 #include <asm/cputable.h>
 #define smt_capable()           (cpu_has_feature(CPU_FTR_SMT))
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
index 1379a4f76de3..3909a2eec286 100644
--- a/include/asm-ppc/ocp.h
+++ b/include/asm-ppc/ocp.h
@@ -31,7 +31,6 @@
 #include <asm/mmu.h>
 #include <asm/ocp_ids.h>
-#include <asm/semaphore.h>
 #ifdef CONFIG_PPC_OCP
diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index cfda7d5bf026..121b2ecddfc3 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -25,7 +25,7 @@ static void __init check_bugs(void)
        case CPU_SH7619:
                *p++ = '2';
                break;
-        case CPU_SH7203 ... CPU_SH7263:
+        case CPU_SH7203 ... CPU_MXG:
                *p++ = '2';
                *p++ = 'a';
                break;
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
index ec028c649215..da46e67ae26d 100644
--- a/include/asm-sh/cpu-sh4/freq.h
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -10,14 +10,14 @@
 #ifndef __ASM_CPU_SH4_FREQ_H
 #define __ASM_CPU_SH4_FREQ_H
-#if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366)
+#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7723) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7366)
 #define FRQCR                   0xa4150000
 #define VCLKCR                  0xa4150004
 #define SCLKACR                 0xa4150008
 #define SCLKBCR                 0xa415000c
-#if defined(CONFIG_CPU_SUBTYPE_SH7722)
 #define IrDACLKCR               0xa4150010
-#endif
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
      defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define FRQCR                   0xffc80000
diff --git a/include/asm-sh/cpu-sh4/rtc.h b/include/asm-sh/cpu-sh4/rtc.h
index f3d0f53275e4..25b1e6adfe8c 100644
--- a/include/asm-sh/cpu-sh4/rtc.h
+++ b/include/asm-sh/cpu-sh4/rtc.h
@@ -1,7 +1,12 @@
 #ifndef __ASM_SH_CPU_SH4_RTC_H
 #define __ASM_SH_CPU_SH4_RTC_H
+#ifdef CONFIG_CPU_SUBTYPE_SH7723
+#define rtc_reg_size            sizeof(u16)
+#else
 #define rtc_reg_size            sizeof(u32)
+#endif
 #define RTC_BIT_INVERTED        0x40    /* bug on SH7750, SH7750S */
 #define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR
diff --git a/include/asm-sh/migor.h b/include/asm-sh/migor.h
new file mode 100644
index 000000000000..2329363afdc3
--- /dev/null
+++ b/include/asm-sh/migor.h
@@ -0,0 +1,58 @@
+#ifndef __ASM_SH_MIGOR_H
+#define __ASM_SH_MIGOR_H
+/*
+ * linux/include/asm-sh/migor.h
+ *
+ * Copyright (C) 2008 Renesas Solutions
+ *
+ * Portions Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+/* GPIO */
+#define MSTPCR0 0xa4150030
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+#define PORT_PACR 0xa4050100
+#define PORT_PDCR 0xa4050106
+#define PORT_PECR 0xa4050108
+#define PORT_PHCR 0xa405010e
+#define PORT_PJCR 0xa4050110
+#define PORT_PKCR 0xa4050112
+#define PORT_PLCR 0xa4050114
+#define PORT_PMCR 0xa4050116
+#define PORT_PRCR 0xa405011c
+#define PORT_PWCR 0xa4050146
+#define PORT_PXCR 0xa4050148
+#define PORT_PYCR 0xa405014a
+#define PORT_PZCR 0xa405014c
+#define PORT_PADR 0xa4050120
+#define PORT_PWDR 0xa4050166
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRC 0xa405015c
+#define PORT_MSELCRB 0xa4050182
+#define MSTPCR1 0xa4150034
+#define MSTPCR2 0xa4150038
+#define PORT_PSELA 0xa405014e
+#define PORT_PSELB 0xa4050150
+#define PORT_PSELC 0xa4050152
+#define PORT_PSELD 0xa4050154
+#define PORT_HIZCRA 0xa4050158
+#define PORT_HIZCRB 0xa405015a
+#define PORT_HIZCRC 0xa405015c
+#define BSC_CS6ABCR 0xfec1001c
+#endif /* __ASM_SH_MIGOR_H */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index ec707b98e5b9..b7c7ce80f03e 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -16,7 +16,7 @@ enum cpu_type {
        CPU_SH7619,
        /* SH-2A types */
-        CPU_SH7203, CPU_SH7206, CPU_SH7263,
+        CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
        /* SH-3 types */
        CPU_SH7705, CPU_SH7706, CPU_SH7707,
@@ -29,7 +29,8 @@ enum cpu_type {
        CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
        /* SH-4A types */
-        CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
+        CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
+        CPU_SH7723, CPU_SHX3,
        /* SH4AL-DSP types */
        CPU_SH7343, CPU_SH7722, CPU_SH7366,
diff --git a/include/asm-sh/r7780rp.h b/include/asm-sh/r7780rp.h
index 1770460a4616..a33838f23a6d 100644
--- a/include/asm-sh/r7780rp.h
+++ b/include/asm-sh/r7780rp.h
@@ -55,11 +55,11 @@
 #define PA_SCSPTR1      (PA_BCR+0x0524) /* SCIF1 Serial Port control */
 #define PA_SCLSR1       (PA_BCR+0x0528) /* SCIF1 Line Status control */
 #define PA_SCRER1       (PA_BCR+0x052c) /* SCIF1 Serial Error control */
-#define PA_ICCR         (PA_BCR+0x0600) /* Serial control */
+#define PA_SMCR         (PA_BCR+0x0600) /* 2-wire Serial control */
-#define PA_SAR          (PA_BCR+0x0602) /* Serial Slave control */
+#define PA_SMSMADR      (PA_BCR+0x0602) /* 2-wire Serial Slave control */
-#define PA_MDR          (PA_BCR+0x0604) /* Serial Mode control */
+#define PA_SMMR         (PA_BCR+0x0604) /* 2-wire Serial Mode control */
-#define PA_ADR1         (PA_BCR+0x0606) /* Serial Address1 control */
+#define PA_SMSADR1      (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
-#define PA_DAR1         (PA_BCR+0x0646) /* Serial Data1 control */
+#define PA_SMTRDR1      (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
 #define PA_VERREG       (PA_BCR+0x0700) /* FPGA Version Register */
 #define PA_POFF         (PA_BCR+0x0800) /* System Power Off control */
 #define PA_PMR          (PA_BCR+0x0900) /*  */
@@ -107,11 +107,11 @@
 #define PA_SCFCR        (PA_BCR+0x040c) /* SCIF FIFO control */
 #define PA_SCFDR        (PA_BCR+0x040e) /* SCIF FIFO data control */
 #define PA_SCLSR        (PA_BCR+0x0412) /* SCIF Line Status control */
-#define PA_ICCR         (PA_BCR+0x0500) /* Serial control */
+#define PA_SMCR         (PA_BCR+0x0500) /* 2-wire Serial control */
-#define PA_SAR          (PA_BCR+0x0502) /* Serial Slave control */
+#define PA_SMSMADR      (PA_BCR+0x0502) /* 2-wire Serial Slave control */
-#define PA_MDR          (PA_BCR+0x0504) /* Serial Mode control */
+#define PA_SMMR         (PA_BCR+0x0504) /* 2-wire Serial Mode control */
-#define PA_ADR1         (PA_BCR+0x0506) /* Serial Address1 control */
+#define PA_SMSADR1      (PA_BCR+0x0506) /* 2-wire Serial Address1 control */
-#define PA_DAR1         (PA_BCR+0x0546) /* Serial Data1 control */
+#define PA_SMTRDR1      (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
 #define PA_VERREG       (PA_BCR+0x0600) /* FPGA Version Register */
 #define PA_AX88796L     0xa5800400      /* AX88796L Area */
@@ -190,6 +190,8 @@
 #define IRQ_TP                  (HL_FPGA_IRQ_BASE + 12)
 #define IRQ_RTC                 (HL_FPGA_IRQ_BASE + 13)
 #define IRQ_TH_ALERT            (HL_FPGA_IRQ_BASE + 14)
+#define IRQ_SCIF0               (HL_FPGA_IRQ_BASE + 15)
+#define IRQ_SCIF1               (HL_FPGA_IRQ_BASE + 16)
 unsigned char *highlander_init_irq_r7780mp(void);
 unsigned char *highlander_init_irq_r7780rp(void);
diff --git a/include/asm-sh/se7721.h b/include/asm-sh/se7721.h
new file mode 100644
index 000000000000..b957f6041193
--- /dev/null
+++ b/include/asm-sh/se7721.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * Hitachi UL SolutionEngine 7721 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef __ASM_SH_SE7721_H
+#define __ASM_SH_SE7721_H
+#include <asm/addrspace.h>
+/* Box specific addresses. */
+#define SE_AREA0_WIDTH  2               /* Area0: 32bit */
+#define PA_ROM          0xa0000000      /* EPROM */
+#define PA_ROM_SIZE     0x00200000      /* EPROM size 2M byte */
+#define PA_FROM         0xa1000000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x01000000      /* Flash-ROM size 16M byte */
+#define PA_EXT1         0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SDRAM        0xaC000000      /* SDRAM(Area3) 64MB */
+#define PA_SDRAM_SIZE   0x04000000
+#define PA_EXT4         0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+#define PA_PERIPHERAL   0xB8000000
+#define PA_PCIC         PA_PERIPHERAL
+#define PA_MRSHPC       (PA_PERIPHERAL + 0x003fffe0)
+#define PA_MRSHPC_MW1   (PA_PERIPHERAL + 0x00400000)
+#define PA_MRSHPC_MW2   (PA_PERIPHERAL + 0x00500000)
+#define PA_MRSHPC_IO    (PA_PERIPHERAL + 0x00600000)
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO        (PA_MRSHPC + 30)
+#define PA_LED          0xB6800000      /* 8bit LED */
+#define PA_FPGA         0xB7000000      /* FPGA base address */
+#define MRSHPC_IRQ0     10
+#define FPGA_ILSR1      (PA_FPGA + 0x02)
+#define FPGA_ILSR2      (PA_FPGA + 0x03)
+#define FPGA_ILSR3      (PA_FPGA + 0x04)
+#define FPGA_ILSR4      (PA_FPGA + 0x05)
+#define FPGA_ILSR5      (PA_FPGA + 0x06)
+#define FPGA_ILSR6      (PA_FPGA + 0x07)
+#define FPGA_ILSR7      (PA_FPGA + 0x08)
+#define FPGA_ILSR8      (PA_FPGA + 0x09)
+void init_se7721_IRQ(void);
+#define __IO_PREFIX             se7721
+#include <asm/io_generic.h>
+#endif  /* __ASM_SH_SE7721_H */
diff --git a/include/asm-sh/se7722.h b/include/asm-sh/se7722.h
index e0e89fcb8388..3690fe5857a4 100644
--- a/include/asm-sh/se7722.h
+++ b/include/asm-sh/se7722.h
@@ -77,6 +77,8 @@
 #define PORT_PSELA      0xA405014EUL
 #define PORT_PYCR       0xA405014AUL
 #define PORT_PZCR       0xA405014CUL
+#define PORT_HIZCRA     0xA4050158UL
+#define PORT_HIZCRC     0xA405015CUL
 /* IRQ */
 #define IRQ0_IRQ        32
diff --git a/include/asm-sh/sh_keysc.h b/include/asm-sh/sh_keysc.h
new file mode 100644
index 000000000000..b5a4dd5a9729
--- /dev/null
+++ b/include/asm-sh/sh_keysc.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_KEYSC_H__
+#define __ASM_KEYSC_H__
+#define SH_KEYSC_MAXKEYS 30
+struct sh_keysc_info {
+        enum { SH_KEYSC_MODE_1, SH_KEYSC_MODE_2, SH_KEYSC_MODE_3 } mode;
+        int scan_timing; /* 0 -> 7, see KYCR1, SCN[2:0] */
+        int delay;
+        int keycodes[SH_KEYSC_MAXKEYS];
+};
+#endif /* __ASM_KEYSC_H__ */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index 5145aa2a0ce9..e65b6b822cb3 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -146,6 +146,8 @@ extern unsigned int instruction_size(unsigned int insn);
 extern unsigned long cached_to_uncached;
+extern struct dentry *sh_debugfs_root;
 /* XXX
 * disable hlt during certain critical i/o operations
 */
diff --git a/include/asm-sh/topology.h b/include/asm-sh/topology.h
index f402a3b1cfa4..34cdb28e8f44 100644
--- a/include/asm-sh/topology.h
+++ b/include/asm-sh/topology.h
@@ -16,7 +16,7 @@
        .cache_nice_tries       = 2,                    \
        .busy_idx               = 3,                    \
        .idle_idx               = 2,                    \
-        .newidle_idx            = 0,                    \
+        .newidle_idx            = 2,                    \
        .wake_idx               = 1,                    \
        .forkexec_idx           = 1,                    \
        .flags                  = SD_LOAD_BALANCE       \
diff --git a/include/asm-sh/uaccess_32.h b/include/asm-sh/uaccess_32.h
index c0318b608893..1e41fda74bd3 100644
--- a/include/asm-sh/uaccess_32.h
+++ b/include/asm-sh/uaccess_32.h
@@ -55,13 +55,10 @@ static inline void set_fs(mm_segment_t s)
 * If we don't have an MMU (or if its disabled) the only thing we really have
 * to look out for is if the address resides somewhere outside of what
 * available RAM we have.
- *
- * TODO: This check could probably also stand to be restricted somewhat more..
- * though it still does the Right Thing(tm) for the time being.
 */
 static inline int __access_ok(unsigned long addr, unsigned long size)
 {
-        return ((addr >= memory_start) && ((addr + size) < memory_end));
+        return 1;
 }
 #else /* CONFIG_MMU */
 #define __addr_ok(addr) \
diff --git a/include/asm-x86/boot.h b/include/asm-x86/boot.h
index ed8affbf96cb..2faed7ecb092 100644
--- a/include/asm-x86/boot.h
+++ b/include/asm-x86/boot.h
@@ -17,4 +17,12 @@
                                + (CONFIG_PHYSICAL_ALIGN - 1)) \
                                & ~(CONFIG_PHYSICAL_ALIGN - 1))
+#ifdef CONFIG_X86_64
+#define BOOT_HEAP_SIZE  0x7000
+#define BOOT_STACK_SIZE 0x4000
+#else
+#define BOOT_HEAP_SIZE  0x4000
+#define BOOT_STACK_SIZE 0x1000
+#endif
 #endif /* _ASM_BOOT_H */
diff --git a/include/asm-x86/dma-mapping.h b/include/asm-x86/dma-mapping.h
index 58f790f4df52..a1a4dc7fe6ec 100644
--- a/include/asm-x86/dma-mapping.h
+++ b/include/asm-x86/dma-mapping.h
@@ -1,5 +1,237 @@
+#ifndef _ASM_DMA_MAPPING_H_
+#define _ASM_DMA_MAPPING_H_
+/*
+ * IOMMU interface. See Documentation/DMA-mapping.txt and DMA-API.txt for
+ * documentation.
+ */
+#include <linux/scatterlist.h>
+#include <asm/io.h>
+#include <asm/swiotlb.h>
+extern dma_addr_t bad_dma_address;
+extern int iommu_merge;
+extern struct device fallback_dev;
+extern int panic_on_overflow;
+extern int forbid_dac;
+extern int force_iommu;
+struct dma_mapping_ops {
+        int             (*mapping_error)(dma_addr_t dma_addr);
+        void*           (*alloc_coherent)(struct device *dev, size_t size,
+                                dma_addr_t *dma_handle, gfp_t gfp);
+        void            (*free_coherent)(struct device *dev, size_t size,
+                                void *vaddr, dma_addr_t dma_handle);
+        dma_addr_t      (*map_single)(struct device *hwdev, phys_addr_t ptr,
+                                size_t size, int direction);
+        /* like map_single, but doesn't check the device mask */
+        dma_addr_t      (*map_simple)(struct device *hwdev, phys_addr_t ptr,
+                                size_t size, int direction);
+        void            (*unmap_single)(struct device *dev, dma_addr_t addr,
+                                size_t size, int direction);
+        void            (*sync_single_for_cpu)(struct device *hwdev,
+                                dma_addr_t dma_handle, size_t size,
+                                int direction);
+        void            (*sync_single_for_device)(struct device *hwdev,
+                                dma_addr_t dma_handle, size_t size,
+                                int direction);
+        void            (*sync_single_range_for_cpu)(struct device *hwdev,
+                                dma_addr_t dma_handle, unsigned long offset,
+                                size_t size, int direction);
+        void            (*sync_single_range_for_device)(struct device *hwdev,
+                                dma_addr_t dma_handle, unsigned long offset,
+                                size_t size, int direction);
+        void            (*sync_sg_for_cpu)(struct device *hwdev,
+                                struct scatterlist *sg, int nelems,
+                                int direction);
+        void            (*sync_sg_for_device)(struct device *hwdev,
+                                struct scatterlist *sg, int nelems,
+                                int direction);
+        int             (*map_sg)(struct device *hwdev, struct scatterlist *sg,
+                                int nents, int direction);
+        void            (*unmap_sg)(struct device *hwdev,
+                                struct scatterlist *sg, int nents,
+                                int direction);
+        int             (*dma_supported)(struct device *hwdev, u64 mask);
+        int             is_phys;
+};
+extern const struct dma_mapping_ops *dma_ops;
+static inline int dma_mapping_error(dma_addr_t dma_addr)
+{
+        if (dma_ops->mapping_error)
+                return dma_ops->mapping_error(dma_addr);
+        return (dma_addr == bad_dma_address);
+}
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, gfp_t flag);
+void dma_free_coherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle);
+extern int dma_supported(struct device *hwdev, u64 mask);
+extern int dma_set_mask(struct device *dev, u64 mask);
+static inline dma_addr_t
+dma_map_single(struct device *hwdev, void *ptr, size_t size,
+               int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        return dma_ops->map_single(hwdev, virt_to_phys(ptr), size, direction);
+}
+static inline void
+dma_unmap_single(struct device *dev, dma_addr_t addr, size_t size,
+                 int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        if (dma_ops->unmap_single)
+                dma_ops->unmap_single(dev, addr, size, direction);
+}
+static inline int
+dma_map_sg(struct device *hwdev, struct scatterlist *sg,
+           int nents, int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        return dma_ops->map_sg(hwdev, sg, nents, direction);
+}
+static inline void
+dma_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nents,
+             int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        if (dma_ops->unmap_sg)
+                dma_ops->unmap_sg(hwdev, sg, nents, direction);
+}
+static inline void
+dma_sync_single_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
+                        size_t size, int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        if (dma_ops->sync_single_for_cpu)
+                dma_ops->sync_single_for_cpu(hwdev, dma_handle, size,
+                                             direction);
+        flush_write_buffers();
+}
+static inline void
+dma_sync_single_for_device(struct device *hwdev, dma_addr_t dma_handle,
+                           size_t size, int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        if (dma_ops->sync_single_for_device)
+                dma_ops->sync_single_for_device(hwdev, dma_handle, size,
+                                                direction);
+        flush_write_buffers();
+}
+static inline void
+dma_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
+                              unsigned long offset, size_t size, int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        if (dma_ops->sync_single_range_for_cpu)
+                dma_ops->sync_single_range_for_cpu(hwdev, dma_handle, offset,
+                                                   size, direction);
+        flush_write_buffers();
+}
+static inline void
+dma_sync_single_range_for_device(struct device *hwdev, dma_addr_t dma_handle,
+                                 unsigned long offset, size_t size,
+                                 int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        if (dma_ops->sync_single_range_for_device)
+                dma_ops->sync_single_range_for_device(hwdev, dma_handle,
+                                                      offset, size, direction);
+        flush_write_buffers();
+}
+static inline void
+dma_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
+                    int nelems, int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        if (dma_ops->sync_sg_for_cpu)
+                dma_ops->sync_sg_for_cpu(hwdev, sg, nelems, direction);
+        flush_write_buffers();
+}
+static inline void
+dma_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
+                       int nelems, int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        if (dma_ops->sync_sg_for_device)
+                dma_ops->sync_sg_for_device(hwdev, sg, nelems, direction);
+        flush_write_buffers();
+}
+static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                                      size_t offset, size_t size,
+                                      int direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+        return dma_ops->map_single(dev, page_to_phys(page)+offset,
+                                   size, direction);
+}
+static inline void dma_unmap_page(struct device *dev, dma_addr_t addr,
+                                  size_t size, int direction)
+{
+        dma_unmap_single(dev, addr, size, direction);
+}
+static inline void
+dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+        enum dma_data_direction dir)
+{
+        flush_write_buffers();
+}
+static inline int dma_get_cache_alignment(void)
+{
+        /* no easy way to get cache size on all x86, so return the
+         * maximum possible, to be safe */
+        return boot_cpu_data.x86_clflush_size;
+}
+#define dma_is_consistent(d, h) (1)
 #ifdef CONFIG_X86_32
-# include "dma-mapping_32.h"
+#  define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
-#else
+struct dma_coherent_mem {
-# include "dma-mapping_64.h"
+        void            *virt_base;
+        u32             device_base;
+        int             size;
+        int             flags;
+        unsigned long   *bitmap;
+};
+extern int
+dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+                            dma_addr_t device_addr, size_t size, int flags);
+extern void
+dma_release_declared_memory(struct device *dev);
+extern void *
+dma_mark_declared_memory_occupied(struct device *dev,
+                                  dma_addr_t device_addr, size_t size);
+#endif /* CONFIG_X86_32 */
 #endif
diff --git a/include/asm-x86/dma-mapping_32.h b/include/asm-x86/dma-mapping_32.h
deleted file mode 100644
index 55f01bd9e556..000000000000
--- a/include/asm-x86/dma-mapping_32.h
+++ /dev/null
@@ -1,187 +0,0 @@
-#ifndef _ASM_I386_DMA_MAPPING_H
-#define _ASM_I386_DMA_MAPPING_H
-#include <linux/mm.h>
-#include <linux/scatterlist.h>
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <asm/bug.h>
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t flag);
-void dma_free_coherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle);
-static inline dma_addr_t
-dma_map_single(struct device *dev, void *ptr, size_t size,
-               enum dma_data_direction direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        WARN_ON(size == 0);
-        flush_write_buffers();
-        return virt_to_phys(ptr);
-}
-static inline void
-dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-                 enum dma_data_direction direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-}
-static inline int
-dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
-           enum dma_data_direction direction)
-{
-        struct scatterlist *sg;
-        int i;
-        BUG_ON(!valid_dma_direction(direction));
-        WARN_ON(nents == 0 || sglist[0].length == 0);
-        for_each_sg(sglist, sg, nents, i) {
-                BUG_ON(!sg_page(sg));
-                sg->dma_address = sg_phys(sg);
-        }
-        flush_write_buffers();
-        return nents;
-}
-static inline dma_addr_t
-dma_map_page(struct device *dev, struct page *page, unsigned long offset,
-             size_t size, enum dma_data_direction direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        return page_to_phys(page) + offset;
-}
-static inline void
-dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
-               enum dma_data_direction direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-}
-static inline void
-dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
-             enum dma_data_direction direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-}
-static inline void
-dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
-                        enum dma_data_direction direction)
-{
-}
-static inline void
-dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
-                        enum dma_data_direction direction)
-{
-        flush_write_buffers();
-}
-static inline void
-dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
-                              unsigned long offset, size_t size,
-                              enum dma_data_direction direction)
-{
-}
-static inline void
-dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
-                                 unsigned long offset, size_t size,
-                                 enum dma_data_direction direction)
-{
-        flush_write_buffers();
-}
-static inline void
-dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
-                    enum dma_data_direction direction)
-{
-}
-static inline void
-dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
-                    enum dma_data_direction direction)
-{
-        flush_write_buffers();
-}
-static inline int
-dma_mapping_error(dma_addr_t dma_addr)
-{
-        return 0;
-}
-extern int forbid_dac;
-static inline int
-dma_supported(struct device *dev, u64 mask)
-{
-        /*
-         * we fall back to GFP_DMA when the mask isn't all 1s,
-         * so we can't guarantee allocations that must be
-         * within a tighter range than GFP_DMA..
-         */
-        if(mask < 0x00ffffff)
-                return 0;
-        /* Work around chipset bugs */
-        if (forbid_dac > 0 && mask > 0xffffffffULL)
-                return 0;
-        return 1;
-}
-static inline int
-dma_set_mask(struct device *dev, u64 mask)
-{
-        if(!dev->dma_mask || !dma_supported(dev, mask))
-                return -EIO;
-        *dev->dma_mask = mask;
-        return 0;
-}
-static inline int
-dma_get_cache_alignment(void)
-{
-        /* no easy way to get cache size on all x86, so return the
-         * maximum possible, to be safe */
-        return (1 << INTERNODE_CACHE_SHIFT);
-}
-#define dma_is_consistent(d, h) (1)
-static inline void
-dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-               enum dma_data_direction direction)
-{
-        flush_write_buffers();
-}
-#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
-extern int
-dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
-                            dma_addr_t device_addr, size_t size, int flags);
-extern void
-dma_release_declared_memory(struct device *dev);
-extern void *
-dma_mark_declared_memory_occupied(struct device *dev,
-                                  dma_addr_t device_addr, size_t size);
-#endif
diff --git a/include/asm-x86/dma-mapping_64.h b/include/asm-x86/dma-mapping_64.h
deleted file mode 100644
index ecd0f6125ba3..000000000000
--- a/include/asm-x86/dma-mapping_64.h
+++ /dev/null
@@ -1,202 +0,0 @@
-#ifndef _X8664_DMA_MAPPING_H
-#define _X8664_DMA_MAPPING_H 1
-/*
- * IOMMU interface. See Documentation/DMA-mapping.txt and DMA-API.txt for
- * documentation.
- */
-#include <linux/scatterlist.h>
-#include <asm/io.h>
-#include <asm/swiotlb.h>
-struct dma_mapping_ops {
-        int             (*mapping_error)(dma_addr_t dma_addr);
-        void*           (*alloc_coherent)(struct device *dev, size_t size,
-                                dma_addr_t *dma_handle, gfp_t gfp);
-        void            (*free_coherent)(struct device *dev, size_t size,
-                                void *vaddr, dma_addr_t dma_handle);
-        dma_addr_t      (*map_single)(struct device *hwdev, void *ptr,
-                                size_t size, int direction);
-        /* like map_single, but doesn't check the device mask */
-        dma_addr_t      (*map_simple)(struct device *hwdev, char *ptr,
-                                size_t size, int direction);
-        void            (*unmap_single)(struct device *dev, dma_addr_t addr,
-                                size_t size, int direction);
-        void            (*sync_single_for_cpu)(struct device *hwdev,
-                                dma_addr_t dma_handle, size_t size,
-                                int direction);
-        void            (*sync_single_for_device)(struct device *hwdev,
-                                dma_addr_t dma_handle, size_t size,
-                                int direction);
-        void            (*sync_single_range_for_cpu)(struct device *hwdev,
-                                dma_addr_t dma_handle, unsigned long offset,
-                                size_t size, int direction);
-        void            (*sync_single_range_for_device)(struct device *hwdev,
-                                dma_addr_t dma_handle, unsigned long offset,
-                                size_t size, int direction);
-        void            (*sync_sg_for_cpu)(struct device *hwdev,
-                                struct scatterlist *sg, int nelems,
-                                int direction);
-        void            (*sync_sg_for_device)(struct device *hwdev,
-                                struct scatterlist *sg, int nelems,
-                                int direction);
-        int             (*map_sg)(struct device *hwdev, struct scatterlist *sg,
-                                int nents, int direction);
-        void            (*unmap_sg)(struct device *hwdev,
-                                struct scatterlist *sg, int nents,
-                                int direction);
-        int             (*dma_supported)(struct device *hwdev, u64 mask);
-        int             is_phys;
-};
-extern dma_addr_t bad_dma_address;
-extern const struct dma_mapping_ops* dma_ops;
-extern int iommu_merge;
-static inline int dma_mapping_error(dma_addr_t dma_addr)
-{
-        if (dma_ops->mapping_error)
-                return dma_ops->mapping_error(dma_addr);
-        return (dma_addr == bad_dma_address);
-}
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-extern void *dma_alloc_coherent(struct device *dev, size_t size,
-                                dma_addr_t *dma_handle, gfp_t gfp);
-extern void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
-                              dma_addr_t dma_handle);
-static inline dma_addr_t
-dma_map_single(struct device *hwdev, void *ptr, size_t size,
-               int direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        return dma_ops->map_single(hwdev, ptr, size, direction);
-}
-static inline void
-dma_unmap_single(struct device *dev, dma_addr_t addr,size_t size,
-                 int direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        dma_ops->unmap_single(dev, addr, size, direction);
-}
-#define dma_map_page(dev,page,offset,size,dir) \
-        dma_map_single((dev), page_address(page)+(offset), (size), (dir))
-#define dma_unmap_page dma_unmap_single
-static inline void
-dma_sync_single_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
-                        size_t size, int direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        if (dma_ops->sync_single_for_cpu)
-                dma_ops->sync_single_for_cpu(hwdev, dma_handle, size,
-                                             direction);
-        flush_write_buffers();
-}
-static inline void
-dma_sync_single_for_device(struct device *hwdev, dma_addr_t dma_handle,
-                           size_t size, int direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        if (dma_ops->sync_single_for_device)
-                dma_ops->sync_single_for_device(hwdev, dma_handle, size,
-                                                direction);
-        flush_write_buffers();
-}
-static inline void
-dma_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dma_handle,
-                              unsigned long offset, size_t size, int direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        if (dma_ops->sync_single_range_for_cpu) {
-                dma_ops->sync_single_range_for_cpu(hwdev, dma_handle, offset, size, direction);
-        }
-        flush_write_buffers();
-}
-static inline void
-dma_sync_single_range_for_device(struct device *hwdev, dma_addr_t dma_handle,
-                                 unsigned long offset, size_t size, int direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        if (dma_ops->sync_single_range_for_device)
-                dma_ops->sync_single_range_for_device(hwdev, dma_handle,
-                                                      offset, size, direction);
-        flush_write_buffers();
-}
-static inline void
-dma_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
-                    int nelems, int direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        if (dma_ops->sync_sg_for_cpu)
-                dma_ops->sync_sg_for_cpu(hwdev, sg, nelems, direction);
-        flush_write_buffers();
-}
-static inline void
-dma_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
-                       int nelems, int direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        if (dma_ops->sync_sg_for_device) {
-                dma_ops->sync_sg_for_device(hwdev, sg, nelems, direction);
-        }
-        flush_write_buffers();
-}
-static inline int
-dma_map_sg(struct device *hwdev, struct scatterlist *sg, int nents, int direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        return dma_ops->map_sg(hwdev, sg, nents, direction);
-}
-static inline void
-dma_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nents,
-             int direction)
-{
-        BUG_ON(!valid_dma_direction(direction));
-        dma_ops->unmap_sg(hwdev, sg, nents, direction);
-}
-extern int dma_supported(struct device *hwdev, u64 mask);
-/* same for gart, swiotlb, and nommu */
-static inline int dma_get_cache_alignment(void)
-{
-        return boot_cpu_data.x86_clflush_size;
-}
-#define dma_is_consistent(d, h) 1
-extern int dma_set_mask(struct device *dev, u64 mask);
-static inline void
-dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-        enum dma_data_direction dir)
-{
-        flush_write_buffers();
-}
-extern struct device fallback_dev;
-extern int panic_on_overflow;
-#endif /* _X8664_DMA_MAPPING_H */
diff --git a/include/asm-x86/e820_32.h b/include/asm-x86/e820_32.h
index 43b1a8bd4b34..a9f7c6ec32bf 100644
--- a/include/asm-x86/e820_32.h
+++ b/include/asm-x86/e820_32.h
@@ -24,7 +24,7 @@ extern void update_e820(void);
 extern int e820_all_mapped(unsigned long start, unsigned long end,
                           unsigned type);
 extern int e820_any_mapped(u64 start, u64 end, unsigned type);
-extern void find_max_pfn(void);
+extern void propagate_e820_map(void);
 extern void register_bootmem_low_pages(unsigned long max_low_pfn);
 extern void add_memory_region(unsigned long long start,
                              unsigned long long size, int type);
diff --git a/include/asm-x86/genapic_32.h b/include/asm-x86/genapic_32.h
index f1b96932746b..b02ea6e17de8 100644
--- a/include/asm-x86/genapic_32.h
+++ b/include/asm-x86/genapic_32.h
@@ -117,6 +117,7 @@ extern struct genapic *genapic;
 enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};
 #define get_uv_system_type()            UV_NONE
 #define is_uv_system()                  0
+#define uv_wakeup_secondary(a, b)       1
 #endif
diff --git a/include/asm-x86/i387.h b/include/asm-x86/i387.h
index 54522b814f1c..da2adb45f6e3 100644
--- a/include/asm-x86/i387.h
+++ b/include/asm-x86/i387.h
@@ -21,8 +21,9 @@
 extern void fpu_init(void);
 extern void mxcsr_feature_mask_init(void);
-extern void init_fpu(struct task_struct *child);
+extern int init_fpu(struct task_struct *child);
 extern asmlinkage void math_state_restore(void);
+extern void init_thread_xstate(void);
 extern user_regset_active_fn fpregs_active, xfpregs_active;
 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
@@ -117,24 +118,22 @@ static inline void __save_init_fpu(struct task_struct *tsk)
        /* Using "fxsaveq %0" would be the ideal choice, but is only supported
           starting with gas 2.16. */
        __asm__ __volatile__("fxsaveq %0"
-                             : "=m" (tsk->thread.i387.fxsave));
+                             : "=m" (tsk->thread.xstate->fxsave));
 #elif 0
        /* Using, as a workaround, the properly prefixed form below isn't
           accepted by any binutils version so far released, complaining that
           the same type of prefix is used twice if an extended register is
           needed for addressing (fix submitted to mainline 2005-11-21). */
        __asm__ __volatile__("rex64/fxsave %0"
-                             : "=m" (tsk->thread.i387.fxsave));
+                             : "=m" (tsk->thread.xstate->fxsave));
 #else
        /* This, however, we can work around by forcing the compiler to select
           an addressing mode that doesn't require extended registers. */
-        __asm__ __volatile__("rex64/fxsave %P2(%1)"
+        __asm__ __volatile__("rex64/fxsave (%1)"
-                             : "=m" (tsk->thread.i387.fxsave)
+                             : "=m" (tsk->thread.xstate->fxsave)
-                             : "cdaSDb" (tsk),
+                             : "cdaSDb" (&tsk->thread.xstate->fxsave));
-                                "i" (offsetof(__typeof__(*tsk),
-                                              thread.i387.fxsave)));
 #endif
-        clear_fpu_state(&tsk->thread.i387.fxsave);
+        clear_fpu_state(&tsk->thread.xstate->fxsave);
        task_thread_info(tsk)->status &= ~TS_USEDFPU;
 }
@@ -148,7 +147,7 @@ static inline int save_i387(struct _fpstate __user *buf)
        int err = 0;
        BUILD_BUG_ON(sizeof(struct user_i387_struct) !=
-                        sizeof(tsk->thread.i387.fxsave));
+                        sizeof(tsk->thread.xstate->fxsave));
        if ((unsigned long)buf % 16)
                printk("save_i387: bad fpstate %p\n", buf);
@@ -164,7 +163,7 @@ static inline int save_i387(struct _fpstate __user *buf)
                task_thread_info(tsk)->status &= ~TS_USEDFPU;
                stts();
        } else {
-                if (__copy_to_user(buf, &tsk->thread.i387.fxsave,
+                if (__copy_to_user(buf, &tsk->thread.xstate->fxsave,
                                   sizeof(struct i387_fxsave_struct)))
                        return -1;
        }
@@ -201,7 +200,7 @@ static inline void restore_fpu(struct task_struct *tsk)
                "nop ; frstor %1",
                "fxrstor %1",
                X86_FEATURE_FXSR,
-                "m" ((tsk)->thread.i387.fxsave));
+                "m" (tsk->thread.xstate->fxsave));
 }
 /* We need a safe address that is cheap to find and that is already
@@ -225,8 +224,8 @@ static inline void __save_init_fpu(struct task_struct *tsk)
                "fxsave %[fx]\n"
                "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
                X86_FEATURE_FXSR,
-                [fx] "m" (tsk->thread.i387.fxsave),
+                [fx] "m" (tsk->thread.xstate->fxsave),
-                [fsw] "m" (tsk->thread.i387.fxsave.swd) : "memory");
+                [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
        /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
           is pending.  Clear the x87 state here by setting it to fixed
           values. safe_address is a random variable that should be in L1 */
@@ -327,25 +326,25 @@ static inline void clear_fpu(struct task_struct *tsk)
 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
 {
        if (cpu_has_fxsr) {
-                return tsk->thread.i387.fxsave.cwd;
+                return tsk->thread.xstate->fxsave.cwd;
        } else {
-                return (unsigned short)tsk->thread.i387.fsave.cwd;
+                return (unsigned short)tsk->thread.xstate->fsave.cwd;
        }
 }
 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
 {
        if (cpu_has_fxsr) {
-                return tsk->thread.i387.fxsave.swd;
+                return tsk->thread.xstate->fxsave.swd;
        } else {
-                return (unsigned short)tsk->thread.i387.fsave.swd;
+                return (unsigned short)tsk->thread.xstate->fsave.swd;
        }
 }
 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
 {
        if (cpu_has_xmm) {
-                return tsk->thread.i387.fxsave.mxcsr;
+                return tsk->thread.xstate->fxsave.mxcsr;
        } else {
                return MXCSR_DEFAULT;
        }
diff --git a/include/asm-x86/numa_64.h b/include/asm-x86/numa_64.h
index 32c22ae0709f..22e87c9f6a80 100644
--- a/include/asm-x86/numa_64.h
+++ b/include/asm-x86/numa_64.h
@@ -9,7 +9,8 @@ struct bootnode {
        u64 end;
 };
-extern int compute_hash_shift(struct bootnode *nodes, int numnodes);
+extern int compute_hash_shift(struct bootnode *nodes, int numblks,
+                              int *nodeids);
 #define ZONE_ALIGN (1UL << (MAX_ORDER+PAGE_SHIFT))
diff --git a/include/asm-x86/pci_64.h b/include/asm-x86/pci_64.h
index df867e5d80b1..f330234ffa5c 100644
--- a/include/asm-x86/pci_64.h
+++ b/include/asm-x86/pci_64.h
@@ -22,6 +22,7 @@ extern int (*pci_config_read)(int seg, int bus, int dev, int fn,
 extern int (*pci_config_write)(int seg, int bus, int dev, int fn,
                               int reg, int len, u32 value);
+extern void dma32_reserve_bootmem(void);
 extern void pci_iommu_alloc(void);
 /* The PCI address space does equal the physical memory
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 6e26c7c717a2..e6bf92ddeb21 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -354,7 +354,7 @@ struct i387_soft_struct {
        u32                     entry_eip;
 };
-union i387_union {
+union thread_xstate {
        struct i387_fsave_struct        fsave;
        struct i387_fxsave_struct       fxsave;
        struct i387_soft_struct         soft;
@@ -365,6 +365,9 @@ DECLARE_PER_CPU(struct orig_ist, orig_ist);
 #endif
 extern void print_cpu_info(struct cpuinfo_x86 *);
+extern unsigned int xstate_size;
+extern void free_thread_xstate(struct task_struct *);
+extern struct kmem_cache *task_xstate_cachep;
 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern unsigned short num_cache_leaves;
@@ -397,8 +400,8 @@ struct thread_struct {
        unsigned long           cr2;
        unsigned long           trap_no;
        unsigned long           error_code;
-        /* Floating point info: */
+        /* floating point and extended processor state */
-        union i387_union        i387 __attribute__((aligned(16)));;
+        union thread_xstate     *xstate;
 #ifdef CONFIG_X86_32
        /* Virtual 86 mode info */
        struct vm86_struct __user *vm86_info;
@@ -918,4 +921,11 @@ extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
+/* Get/set a process' ability to use the timestamp counter instruction */
+#define GET_TSC_CTL(adr)        get_tsc_mode((adr))
+#define SET_TSC_CTL(val)        set_tsc_mode((val))
+extern int get_tsc_mode(unsigned long adr);
+extern int set_tsc_mode(unsigned int val);
 #endif
diff --git a/include/asm-x86/scatterlist.h b/include/asm-x86/scatterlist.h
index d13c197866d6..c0432061f81a 100644
--- a/include/asm-x86/scatterlist.h
+++ b/include/asm-x86/scatterlist.h
@@ -11,9 +11,7 @@ struct scatterlist {
        unsigned int    offset;
        unsigned int    length;
        dma_addr_t      dma_address;
-#ifdef CONFIG_X86_64
        unsigned int    dma_length;
-#endif
 };
 #define ARCH_HAS_SG_CHAIN
diff --git a/include/asm-x86/thread_info.h b/include/asm-x86/thread_info.h
index d5fd12f2abdb..77244f17993f 100644
--- a/include/asm-x86/thread_info.h
+++ b/include/asm-x86/thread_info.h
@@ -1,5 +1,14 @@
+#ifndef _ASM_X86_THREAD_INFO_H
 #ifdef CONFIG_X86_32
 # include "thread_info_32.h"
 #else
 # include "thread_info_64.h"
 #endif
+#ifndef __ASSEMBLY__
+extern void arch_task_cache_init(void);
+extern void free_thread_info(struct thread_info *ti);
+extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
+#define arch_task_cache_init arch_task_cache_init
+#endif
+#endif /* _ASM_X86_THREAD_INFO_H */
diff --git a/include/asm-x86/thread_info_32.h b/include/asm-x86/thread_info_32.h
index 4e053fa561a9..531859962096 100644
--- a/include/asm-x86/thread_info_32.h
+++ b/include/asm-x86/thread_info_32.h
@@ -102,8 +102,6 @@ static inline struct thread_info *current_thread_info(void)
        __get_free_pages(GFP_KERNEL, get_order(THREAD_SIZE)))
 #endif
-#define free_thread_info(info)  free_pages((unsigned long)(info), get_order(THREAD_SIZE))
 #else /* !__ASSEMBLY__ */
 /* how to get the thread information struct from ASM */
diff --git a/include/asm-x86/thread_info_64.h b/include/asm-x86/thread_info_64.h
index 1e5c6f6152cd..ed664e874dec 100644
--- a/include/asm-x86/thread_info_64.h
+++ b/include/asm-x86/thread_info_64.h
@@ -85,8 +85,6 @@ static inline struct thread_info *stack_thread_info(void)
 #define alloc_thread_info(tsk)                                          \
        ((struct thread_info *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER))
-#define free_thread_info(ti) free_pages((unsigned long) (ti), THREAD_ORDER)
 #else /* !__ASSEMBLY__ */
 /* how to get the thread information struct from ASM */
@@ -126,6 +124,7 @@ static inline struct thread_info *stack_thread_info(void)
 #define TIF_DEBUGCTLMSR         25      /* uses thread_struct.debugctlmsr */
 #define TIF_DS_AREA_MSR         26      /* uses thread_struct.ds_area_msr */
 #define TIF_BTS_TRACE_TS        27      /* record scheduling event timestamps */
+#define TIF_NOTSC               28      /* TSC is not accessible in userland */
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
@@ -147,6 +146,7 @@ static inline struct thread_info *stack_thread_info(void)
 #define _TIF_DEBUGCTLMSR        (1 << TIF_DEBUGCTLMSR)
 #define _TIF_DS_AREA_MSR        (1 << TIF_DS_AREA_MSR)
 #define _TIF_BTS_TRACE_TS       (1 << TIF_BTS_TRACE_TS)
+#define _TIF_NOTSC              (1 << TIF_NOTSC)
 /* work to do on interrupt/exception return */
 #define _TIF_WORK_MASK                                                  \
@@ -160,7 +160,7 @@ static inline struct thread_info *stack_thread_info(void)
 /* flags to check in __switch_to() */
 #define _TIF_WORK_CTXSW                                                 \
-        (_TIF_IO_BITMAP|_TIF_DEBUGCTLMSR|_TIF_DS_AREA_MSR|_TIF_BTS_TRACE_TS)
+        (_TIF_IO_BITMAP|_TIF_DEBUGCTLMSR|_TIF_DS_AREA_MSR|_TIF_BTS_TRACE_TS|_TIF_NOTSC)
 #define _TIF_WORK_CTXSW_PREV _TIF_WORK_CTXSW
 #define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW|_TIF_DEBUG)
diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h
index 81a29eb08ac4..22073268b481 100644
--- a/include/asm-x86/topology.h
+++ b/include/asm-x86/topology.h
@@ -88,6 +88,17 @@ static inline int cpu_to_node(int cpu)
 #endif
        return per_cpu(x86_cpu_to_node_map, cpu);
 }
+#ifdef  CONFIG_NUMA
+/* Returns a pointer to the cpumask of CPUs on Node 'node'. */
+#define node_to_cpumask_ptr(v, node)            \
+                cpumask_t *v = &(node_to_cpumask_map[node])
+#define node_to_cpumask_ptr_next(v, node)       \
+                           v = &(node_to_cpumask_map[node])
+#endif
 #endif /* CONFIG_X86_64 */
 /*
@@ -136,17 +147,13 @@ extern unsigned long node_remap_size[];
 # define SD_CACHE_NICE_TRIES    2
 # define SD_IDLE_IDX            2
-# define SD_NEWIDLE_IDX         0
+# define SD_NEWIDLE_IDX         2
 # define SD_FORKEXEC_IDX        1
 #endif
 /* sched_domains SD_NODE_INIT for NUMAQ machines */
 #define SD_NODE_INIT (struct sched_domain) {            \
-        .span                   = CPU_MASK_NONE,        \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
        .min_interval           = 8,                    \
        .max_interval           = 32,                   \
        .busy_factor            = 32,                   \
@@ -164,7 +171,6 @@ extern unsigned long node_remap_size[];
                                | SD_WAKE_BALANCE,      \
        .last_balance           = jiffies,              \
        .balance_interval       = 1,                    \
-        .nr_balance_failed      = 0,                    \
 }
 #ifdef CONFIG_X86_64_ACPI_NUMA
@@ -174,10 +180,10 @@ extern int __node_distance(int, int);
 #else /* CONFIG_NUMA */
-#include <asm-generic/topology.h>
 #endif
+#include <asm-generic/topology.h>
 extern cpumask_t cpu_coregroup_map(int cpu);
 #ifdef ENABLE_TOPO_DEFINES
diff --git a/include/asm-x86/tsc.h b/include/asm-x86/tsc.h
index d2d8eb5b55f5..0434bd8349a7 100644
--- a/include/asm-x86/tsc.h
+++ b/include/asm-x86/tsc.h
@@ -18,6 +18,7 @@ extern unsigned int cpu_khz;
 extern unsigned int tsc_khz;
 extern void disable_TSC(void);
+extern void enable_TSC(void);
 static inline cycles_t get_cycles(void)
 {
diff --git a/include/linux/ata_platform.h b/include/linux/ata_platform.h
index b856a2a590d9..9a26c83a2c9e 100644
--- a/include/linux/ata_platform.h
+++ b/include/linux/ata_platform.h
@@ -27,7 +27,10 @@ extern int __devexit __pata_platform_remove(struct device *dev);
 /*
 * Marvell SATA private data
 */
+struct mbus_dram_target_info;
 struct mv_sata_platform_data {
+        struct mbus_dram_target_info    *dram;
        int     n_ports; /* number of sata ports */
 };
diff --git a/include/linux/atmel_tc.h b/include/linux/atmel_tc.h
new file mode 100644
index 000000000000..53ba65e30caa
--- /dev/null
+++ b/include/linux/atmel_tc.h
@@ -0,0 +1,252 @@
+/*
+ * Timer/Counter Unit (TC) registers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef ATMEL_TC_H
+#define ATMEL_TC_H
+#include <linux/compiler.h>
+#include <linux/list.h>
+/*
+ * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
+ * three general-purpose 16-bit timers.  These timers share one register bank.
+ * Depending on the SOC, each timer may have its own clock and IRQ, or those
+ * may be shared by the whole TC block.
+ *
+ * These TC blocks may have up to nine external pins:  TCLK0..2 signals for
+ * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
+ * or triggering.  Those pins need to be set up for use with the TC block,
+ * else they will be used as GPIOs or for a different controller.
+ *
+ * Although we expect each TC block to have a platform_device node, those
+ * nodes are not what drivers bind to.  Instead, they ask for a specific
+ * TC block, by number ... which is a common approach on systems with many
+ * timers.  Then they use clk_get() and platform_get_irq() to get clock and
+ * IRQ resources.
+ */
+struct clk;
+/**
+ * struct atmel_tc - information about a Timer/Counter Block
+ * @pdev: physical device
+ * @iomem: resource associated with the I/O register
+ * @regs: mapping through which the I/O registers can be accessed
+ * @irq: irq for each of the three channels
+ * @clk: internal clock source for each of the three channels
+ * @node: list node, for tclib internal use
+ *
+ * On some platforms, each TC channel has its own clocks and IRQs,
+ * while on others, all TC channels share the same clock and IRQ.
+ * Drivers should clk_enable() all the clocks they need even though
+ * all the entries in @clk may point to the same physical clock.
+ * Likewise, drivers should request irqs independently for each
+ * channel, but they must use IRQF_SHARED in case some of the entries
+ * in @irq are actually the same IRQ.
+ */
+struct atmel_tc {
+        struct platform_device  *pdev;
+        struct resource         *iomem;
+        void __iomem            *regs;
+        int                     irq[3];
+        struct clk              *clk[3];
+        struct list_head        node;
+};
+extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
+extern void atmel_tc_free(struct atmel_tc *tc);
+/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
+extern const u8 atmel_tc_divisors[5];
+/*
+ * Two registers have block-wide controls.  These are: configuring the three
+ * "external" clocks (or event sources) used by the timer channels; and
+ * synchronizing the timers by resetting them all at once.
+ *
+ * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
+ * signals.  Or, it can mean "external to timer", using the TIOA output from
+ * one of the other two timers that's being run in waveform mode.
+ */
+#define ATMEL_TC_BCR    0xc0            /* TC Block Control Register */
+#define     ATMEL_TC_SYNC       (1 << 0)        /* synchronize timers */
+#define ATMEL_TC_BMR    0xc4            /* TC Block Mode Register */
+#define     ATMEL_TC_TC0XC0S    (3 << 0)        /* external clock 0 source */
+#define        ATMEL_TC_TC0XC0S_TCLK0   (0 << 0)
+#define        ATMEL_TC_TC0XC0S_NONE    (1 << 0)
+#define        ATMEL_TC_TC0XC0S_TIOA1   (2 << 0)
+#define        ATMEL_TC_TC0XC0S_TIOA2   (3 << 0)
+#define     ATMEL_TC_TC1XC1S    (3 << 2)        /* external clock 1 source */
+#define        ATMEL_TC_TC1XC1S_TCLK1   (0 << 2)
+#define        ATMEL_TC_TC1XC1S_NONE    (1 << 2)
+#define        ATMEL_TC_TC1XC1S_TIOA0   (2 << 2)
+#define        ATMEL_TC_TC1XC1S_TIOA2   (3 << 2)
+#define     ATMEL_TC_TC2XC2S    (3 << 4)        /* external clock 2 source */
+#define        ATMEL_TC_TC2XC2S_TCLK2   (0 << 4)
+#define        ATMEL_TC_TC2XC2S_NONE    (1 << 4)
+#define        ATMEL_TC_TC2XC2S_TIOA0   (2 << 4)
+#define        ATMEL_TC_TC2XC2S_TIOA1   (3 << 4)
+/*
+ * Each TC block has three "channels", each with one counter and controls.
+ *
+ * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
+ * when it's not "external") is silicon-specific.  AT91 platforms use one
+ * set of definitions; AVR32 platforms use a different set.  Don't hard-wire
+ * such knowledge into your code, use the global "atmel_tc_divisors" ...
+ * where index N is the divisor for clock N+1, else zero to indicate it uses
+ * the 32 KiHz clock.
+ *
+ * The timers can be chained in various ways, and operated in "waveform"
+ * generation mode (including PWM) or "capture" mode (to time events).  In
+ * both modes, behavior can be configured in many ways.
+ *
+ * Each timer has two I/O pins, TIOA and TIOB.  Waveform mode uses TIOA as a
+ * PWM output, and TIOB as either another PWM or as a trigger.  Capture mode
+ * uses them only as inputs.
+ */
+#define ATMEL_TC_CHAN(idx)      ((idx)*0x40)
+#define ATMEL_TC_REG(idx, reg)  (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
+#define ATMEL_TC_CCR    0x00            /* Channel Control Register */
+#define     ATMEL_TC_CLKEN      (1 << 0)        /* clock enable */
+#define     ATMEL_TC_CLKDIS     (1 << 1)        /* clock disable */
+#define     ATMEL_TC_SWTRG      (1 << 2)        /* software trigger */
+#define ATMEL_TC_CMR    0x04            /* Channel Mode Register */
+/* Both modes share some CMR bits */
+#define     ATMEL_TC_TCCLKS     (7 << 0)        /* clock source */
+#define        ATMEL_TC_TIMER_CLOCK1    (0 << 0)
+#define        ATMEL_TC_TIMER_CLOCK2    (1 << 0)
+#define        ATMEL_TC_TIMER_CLOCK3    (2 << 0)
+#define        ATMEL_TC_TIMER_CLOCK4    (3 << 0)
+#define        ATMEL_TC_TIMER_CLOCK5    (4 << 0)
+#define        ATMEL_TC_XC0             (5 << 0)
+#define        ATMEL_TC_XC1             (6 << 0)
+#define        ATMEL_TC_XC2             (7 << 0)
+#define     ATMEL_TC_CLKI       (1 << 3)        /* clock invert */
+#define     ATMEL_TC_BURST      (3 << 4)        /* clock gating */
+#define        ATMEL_TC_GATE_NONE       (0 << 4)
+#define        ATMEL_TC_GATE_XC0        (1 << 4)
+#define        ATMEL_TC_GATE_XC1        (2 << 4)
+#define        ATMEL_TC_GATE_XC2        (3 << 4)
+#define     ATMEL_TC_WAVE       (1 << 15)       /* true = Waveform mode */
+/* CAPTURE mode CMR bits */
+#define     ATMEL_TC_LDBSTOP    (1 << 6)        /* counter stops on RB load */
+#define     ATMEL_TC_LDBDIS     (1 << 7)        /* counter disable on RB load */
+#define     ATMEL_TC_ETRGEDG    (3 << 8)        /* external trigger edge */
+#define        ATMEL_TC_ETRGEDG_NONE    (0 << 8)
+#define        ATMEL_TC_ETRGEDG_RISING  (1 << 8)
+#define        ATMEL_TC_ETRGEDG_FALLING (2 << 8)
+#define        ATMEL_TC_ETRGEDG_BOTH    (3 << 8)
+#define     ATMEL_TC_ABETRG     (1 << 10)       /* external trigger is TIOA? */
+#define     ATMEL_TC_CPCTRG     (1 << 14)       /* RC compare trigger enable */
+#define     ATMEL_TC_LDRA       (3 << 16)       /* RA loading edge (of TIOA) */
+#define        ATMEL_TC_LDRA_NONE       (0 << 16)
+#define        ATMEL_TC_LDRA_RISING     (1 << 16)
+#define        ATMEL_TC_LDRA_FALLING    (2 << 16)
+#define        ATMEL_TC_LDRA_BOTH       (3 << 16)
+#define     ATMEL_TC_LDRB       (3 << 18)       /* RB loading edge (of TIOA) */
+#define        ATMEL_TC_LDRB_NONE       (0 << 18)
+#define        ATMEL_TC_LDRB_RISING     (1 << 18)
+#define        ATMEL_TC_LDRB_FALLING    (2 << 18)
+#define        ATMEL_TC_LDRB_BOTH       (3 << 18)
+/* WAVEFORM mode CMR bits */
+#define     ATMEL_TC_CPCSTOP    (1 <<  6)       /* RC compare stops counter */
+#define     ATMEL_TC_CPCDIS     (1 <<  7)       /* RC compare disables counter */
+#define     ATMEL_TC_EEVTEDG    (3 <<  8)       /* external event edge */
+#define        ATMEL_TC_EEVTEDG_NONE    (0 << 8)
+#define        ATMEL_TC_EEVTEDG_RISING  (1 << 8)
+#define        ATMEL_TC_EEVTEDG_FALLING (2 << 8)
+#define        ATMEL_TC_EEVTEDG_BOTH    (3 << 8)
+#define     ATMEL_TC_EEVT       (3 << 10)       /* external event source */
+#define        ATMEL_TC_EEVT_TIOB       (0 << 10)
+#define        ATMEL_TC_EEVT_XC0        (1 << 10)
+#define        ATMEL_TC_EEVT_XC1        (2 << 10)
+#define        ATMEL_TC_EEVT_XC2        (3 << 10)
+#define     ATMEL_TC_ENETRG     (1 << 12)       /* external event is trigger */
+#define     ATMEL_TC_WAVESEL    (3 << 13)       /* waveform type */
+#define        ATMEL_TC_WAVESEL_UP      (0 << 13)
+#define        ATMEL_TC_WAVESEL_UPDOWN  (1 << 13)
+#define        ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
+#define        ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
+#define     ATMEL_TC_ACPA       (3 << 16)       /* RA compare changes TIOA */
+#define        ATMEL_TC_ACPA_NONE       (0 << 16)
+#define        ATMEL_TC_ACPA_SET        (1 << 16)
+#define        ATMEL_TC_ACPA_CLEAR      (2 << 16)
+#define        ATMEL_TC_ACPA_TOGGLE     (3 << 16)
+#define     ATMEL_TC_ACPC       (3 << 18)       /* RC compare changes TIOA */
+#define        ATMEL_TC_ACPC_NONE       (0 << 18)
+#define        ATMEL_TC_ACPC_SET        (1 << 18)
+#define        ATMEL_TC_ACPC_CLEAR      (2 << 18)
+#define        ATMEL_TC_ACPC_TOGGLE     (3 << 18)
+#define     ATMEL_TC_AEEVT      (3 << 20)       /* external event changes TIOA */
+#define        ATMEL_TC_AEEVT_NONE      (0 << 20)
+#define        ATMEL_TC_AEEVT_SET       (1 << 20)
+#define        ATMEL_TC_AEEVT_CLEAR     (2 << 20)
+#define        ATMEL_TC_AEEVT_TOGGLE    (3 << 20)
+#define     ATMEL_TC_ASWTRG     (3 << 22)       /* software trigger changes TIOA */
+#define        ATMEL_TC_ASWTRG_NONE     (0 << 22)
+#define        ATMEL_TC_ASWTRG_SET      (1 << 22)
+#define        ATMEL_TC_ASWTRG_CLEAR    (2 << 22)
+#define        ATMEL_TC_ASWTRG_TOGGLE   (3 << 22)
+#define     ATMEL_TC_BCPB       (3 << 24)       /* RB compare changes TIOB */
+#define        ATMEL_TC_BCPB_NONE       (0 << 24)
+#define        ATMEL_TC_BCPB_SET        (1 << 24)
+#define        ATMEL_TC_BCPB_CLEAR      (2 << 24)
+#define        ATMEL_TC_BCPB_TOGGLE     (3 << 24)
+#define     ATMEL_TC_BCPC       (3 << 26)       /* RC compare changes TIOB */
+#define        ATMEL_TC_BCPC_NONE       (0 << 26)
+#define        ATMEL_TC_BCPC_SET        (1 << 26)
+#define        ATMEL_TC_BCPC_CLEAR      (2 << 26)
+#define        ATMEL_TC_BCPC_TOGGLE     (3 << 26)
+#define     ATMEL_TC_BEEVT      (3 << 28)       /* external event changes TIOB */
+#define        ATMEL_TC_BEEVT_NONE      (0 << 28)
+#define        ATMEL_TC_BEEVT_SET       (1 << 28)
+#define        ATMEL_TC_BEEVT_CLEAR     (2 << 28)
+#define        ATMEL_TC_BEEVT_TOGGLE    (3 << 28)
+#define     ATMEL_TC_BSWTRG     (3 << 30)       /* software trigger changes TIOB */
+#define        ATMEL_TC_BSWTRG_NONE     (0 << 30)
+#define        ATMEL_TC_BSWTRG_SET      (1 << 30)
+#define        ATMEL_TC_BSWTRG_CLEAR    (2 << 30)
+#define        ATMEL_TC_BSWTRG_TOGGLE   (3 << 30)
+#define ATMEL_TC_CV     0x10            /* counter Value */
+#define ATMEL_TC_RA     0x14            /* register A */
+#define ATMEL_TC_RB     0x18            /* register B */
+#define ATMEL_TC_RC     0x1c            /* register C */
+#define ATMEL_TC_SR     0x20            /* status (read-only) */
+/* Status-only flags */
+#define     ATMEL_TC_CLKSTA     (1 << 16)       /* clock enabled */
+#define     ATMEL_TC_MTIOA      (1 << 17)       /* TIOA mirror */
+#define     ATMEL_TC_MTIOB      (1 << 18)       /* TIOB mirror */
+#define ATMEL_TC_IER    0x24            /* interrupt enable (write-only) */
+#define ATMEL_TC_IDR    0x28            /* interrupt disable (write-only) */
+#define ATMEL_TC_IMR    0x2c            /* interrupt mask (read-only) */
+/* Status and IRQ flags */
+#define     ATMEL_TC_COVFS      (1 <<  0)       /* counter overflow */
+#define     ATMEL_TC_LOVRS      (1 <<  1)       /* load overrun */
+#define     ATMEL_TC_CPAS       (1 <<  2)       /* RA compare */
+#define     ATMEL_TC_CPBS       (1 <<  3)       /* RB compare */
+#define     ATMEL_TC_CPCS       (1 <<  4)       /* RC compare */
+#define     ATMEL_TC_LDRAS      (1 <<  5)       /* RA loading */
+#define     ATMEL_TC_LDRBS      (1 <<  6)       /* RB loading */
+#define     ATMEL_TC_ETRGS      (1 <<  7)       /* external trigger */
+#endif
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index acad1105d942..1dbe074f1c64 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -108,6 +108,7 @@ extern int __bitmap_weight(const unsigned long *bitmap, int bits);
 extern int bitmap_scnprintf(char *buf, unsigned int len,
                        const unsigned long *src, int nbits);
+extern int bitmap_scnprintf_len(unsigned int len);
 extern int __bitmap_parse(const char *buf, unsigned int buflen, int is_user,
                        unsigned long *dst, int nbits);
 extern int bitmap_parse_user(const char __user *ubuf, unsigned int ulen,
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 0be8d65bc3c8..f212fa98283e 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -23,7 +23,6 @@
 #include <linux/node.h>
 #include <linux/compiler.h>
 #include <linux/cpumask.h>
-#include <asm/semaphore.h>
 #include <linux/mutex.h>
 struct cpu {
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index 7047f58306a7..259c8051155d 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -222,8 +222,13 @@ int __next_cpu(int n, const cpumask_t *srcp);
 #define next_cpu(n, src)        ({ (void)(src); 1; })
 #endif
+#ifdef CONFIG_HAVE_CPUMASK_OF_CPU_MAP
+extern cpumask_t *cpumask_of_cpu_map;
+#define cpumask_of_cpu(cpu)    (cpumask_of_cpu_map[cpu])
+#else
 #define cpumask_of_cpu(cpu)                                             \
-({                                                                      \
+(*({                                                                    \
        typeof(_unused_cpumask_arg_) m;                                 \
        if (sizeof(m) == sizeof(unsigned long)) {                       \
                m.bits[0] = 1UL<<(cpu);                                 \
@@ -231,8 +236,9 @@ int __next_cpu(int n, const cpumask_t *srcp);
                cpus_clear(m);                                          \
                cpu_set((cpu), m);                                      \
        }                                                               \
-        m;                                                              \
+        &m;                                                             \
-})
+}))
+#endif
 #define CPU_MASK_LAST_WORD BITMAP_LAST_WORD_MASK(NR_CPUS)
@@ -243,6 +249,8 @@ int __next_cpu(int n, const cpumask_t *srcp);
        [BITS_TO_LONGS(NR_CPUS)-1] = CPU_MASK_LAST_WORD                 \
 } }
+#define CPU_MASK_ALL_PTR        (&CPU_MASK_ALL)
 #else
 #define CPU_MASK_ALL                                                    \
@@ -251,6 +259,10 @@ int __next_cpu(int n, const cpumask_t *srcp);
        [BITS_TO_LONGS(NR_CPUS)-1] = CPU_MASK_LAST_WORD                 \
 } }
+/* cpu_mask_all is in init/main.c */
+extern cpumask_t cpu_mask_all;
+#define CPU_MASK_ALL_PTR        (&cpu_mask_all)
 #endif
 #define CPU_MASK_NONE                                                   \
@@ -273,6 +285,13 @@ static inline int __cpumask_scnprintf(char *buf, int len,
        return bitmap_scnprintf(buf, len, srcp->bits, nbits);
 }
+#define cpumask_scnprintf_len(len) \
+                        __cpumask_scnprintf_len((len))
+static inline int __cpumask_scnprintf_len(int len)
+{
+        return bitmap_scnprintf_len(len);
+}
 #define cpumask_parse_user(ubuf, ulen, dst) \
                        __cpumask_parse_user((ubuf), (ulen), &(dst), NR_CPUS)
 static inline int __cpumask_parse_user(const char __user *buf, int len,
diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h
index 0a26be353cb3..726761e24003 100644
--- a/include/linux/cpuset.h
+++ b/include/linux/cpuset.h
@@ -20,8 +20,8 @@ extern int number_of_cpusets;	/* How many cpusets are defined in system? */
 extern int cpuset_init_early(void);
 extern int cpuset_init(void);
 extern void cpuset_init_smp(void);
-extern cpumask_t cpuset_cpus_allowed(struct task_struct *p);
+extern void cpuset_cpus_allowed(struct task_struct *p, cpumask_t *mask);
-extern cpumask_t cpuset_cpus_allowed_locked(struct task_struct *p);
+extern void cpuset_cpus_allowed_locked(struct task_struct *p, cpumask_t *mask);
 extern nodemask_t cpuset_mems_allowed(struct task_struct *p);
 #define cpuset_current_mems_allowed (current->mems_allowed)
 void cpuset_init_current_mems_allowed(void);
@@ -84,13 +84,14 @@ static inline int cpuset_init_early(void) { return 0; }
 static inline int cpuset_init(void) { return 0; }
 static inline void cpuset_init_smp(void) {}
-static inline cpumask_t cpuset_cpus_allowed(struct task_struct *p)
+static inline void cpuset_cpus_allowed(struct task_struct *p, cpumask_t *mask)
 {
-        return cpu_possible_map;
+        *mask = cpu_possible_map;
 }
-static inline cpumask_t cpuset_cpus_allowed_locked(struct task_struct *p)
+static inline void cpuset_cpus_allowed_locked(struct task_struct *p,
+                                                                cpumask_t *mask)
 {
-        return cpu_possible_map;
+        *mask = cpu_possible_map;
 }
 static inline nodemask_t cpuset_mems_allowed(struct task_struct *p)
diff --git a/include/linux/device.h b/include/linux/device.h
index dc3429e2eb0f..1a060265acea 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -20,7 +20,7 @@
 #include <linux/types.h>
 #include <linux/module.h>
 #include <linux/pm.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
 #include <asm/atomic.h>
 #include <asm/device.h>
diff --git a/include/linux/efi.h b/include/linux/efi.h
index 14813b595802..a5f359a7ad0e 100644
--- a/include/linux/efi.h
+++ b/include/linux/efi.h
@@ -18,6 +18,7 @@
 #include <linux/proc_fs.h>
 #include <linux/rtc.h>
 #include <linux/ioport.h>
+#include <linux/pfn.h>
 #include <asm/page.h>
 #include <asm/system.h>
@@ -394,4 +395,10 @@ struct efi_generic_dev_path {
        u16 length;
 } __attribute ((packed));
+static inline void memrange_efi_to_native(u64 *addr, u64 *npages)
+{
+        *npages = PFN_UP(*addr + (*npages<<EFI_PAGE_SHIFT)) - PFN_DOWN(*addr);
+        *addr &= PAGE_MASK;
+}
 #endif /* _LINUX_EFI_H */
diff --git a/include/linux/file.h b/include/linux/file.h
index 7239baac81a9..653477021e4c 100644
--- a/include/linux/file.h
+++ b/include/linux/file.h
@@ -61,6 +61,7 @@ extern struct kmem_cache *filp_cachep;
 extern void __fput(struct file *);
 extern void fput(struct file *);
+extern void drop_file_write_access(struct file *file);
 struct file_operations;
 struct vfsmount;
diff --git a/include/linux/fs.h b/include/linux/fs.h
index b84b848431f2..0c609e71c379 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -287,9 +287,9 @@ extern int dir_notify_enable;
 #include <linux/pid.h>
 #include <linux/mutex.h>
 #include <linux/capability.h>
+#include <linux/semaphore.h>
 #include <asm/atomic.h>
-#include <asm/semaphore.h>
 #include <asm/byteorder.h>
 struct export_operations;
@@ -776,6 +776,9 @@ static inline int ra_has_index(struct file_ra_state *ra, pgoff_t index)
                index <  ra->start + ra->size);
 }
+#define FILE_MNT_WRITE_TAKEN    1
+#define FILE_MNT_WRITE_RELEASED 2
 struct file {
        /*
         * fu_list becomes invalid after file_free is called and queued via
@@ -810,6 +813,9 @@ struct file {
        spinlock_t              f_ep_lock;
 #endif /* #ifdef CONFIG_EPOLL */
        struct address_space    *f_mapping;
+#ifdef CONFIG_DEBUG_WRITECOUNT
+        unsigned long f_mnt_write_state;
+#endif
 };
 extern spinlock_t files_lock;
 #define file_list_lock() spin_lock(&files_lock);
@@ -818,6 +824,49 @@ extern spinlock_t files_lock;
 #define get_file(x)     atomic_inc(&(x)->f_count)
 #define file_count(x)   atomic_read(&(x)->f_count)
+#ifdef CONFIG_DEBUG_WRITECOUNT
+static inline void file_take_write(struct file *f)
+{
+        WARN_ON(f->f_mnt_write_state != 0);
+        f->f_mnt_write_state = FILE_MNT_WRITE_TAKEN;
+}
+static inline void file_release_write(struct file *f)
+{
+        f->f_mnt_write_state |= FILE_MNT_WRITE_RELEASED;
+}
+static inline void file_reset_write(struct file *f)
+{
+        f->f_mnt_write_state = 0;
+}
+static inline void file_check_state(struct file *f)
+{
+        /*
+         * At this point, either both or neither of these bits
+         * should be set.
+         */
+        WARN_ON(f->f_mnt_write_state == FILE_MNT_WRITE_TAKEN);
+        WARN_ON(f->f_mnt_write_state == FILE_MNT_WRITE_RELEASED);
+}
+static inline int file_check_writeable(struct file *f)
+{
+        if (f->f_mnt_write_state == FILE_MNT_WRITE_TAKEN)
+                return 0;
+        printk(KERN_WARNING "writeable file with no "
+                            "mnt_want_write()\n");
+        WARN_ON(1);
+        return -EINVAL;
+}
+#else /* !CONFIG_DEBUG_WRITECOUNT */
+static inline void file_take_write(struct file *filp) {}
+static inline void file_release_write(struct file *filp) {}
+static inline void file_reset_write(struct file *filp) {}
+static inline void file_check_state(struct file *filp) {}
+static inline int file_check_writeable(struct file *filp)
+{
+        return 0;
+}
+#endif /* CONFIG_DEBUG_WRITECOUNT */
 #define MAX_NON_LFS     ((1UL<<31) - 1)
 /* Page cache limit. The filesystems should put that into their s_maxbytes 
@@ -1735,7 +1784,8 @@ extern struct file *create_read_pipe(struct file *f);
 extern struct file *create_write_pipe(void);
 extern void free_write_pipe(struct file *);
-extern int open_namei(int dfd, const char *, int, int, struct nameidata *);
+extern struct file *do_filp_open(int dfd, const char *pathname,
+                int open_flag, int mode);
 extern int may_open(struct nameidata *, int, int);
 extern int kernel_read(struct file *, unsigned long, char *, unsigned long);
diff --git a/include/linux/hil_mlc.h b/include/linux/hil_mlc.h
index 8df29ca48a13..394a8405dd74 100644
--- a/include/linux/hil_mlc.h
+++ b/include/linux/hil_mlc.h
@@ -34,7 +34,7 @@
 #include <linux/hil.h>
 #include <linux/time.h>
 #include <linux/interrupt.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
 #include <linux/serio.h>
 #include <linux/list.h>
diff --git a/include/linux/i2c/tps65010.h b/include/linux/i2c/tps65010.h
index 7021635ed6a0..918c5354d9b8 100644
--- a/include/linux/i2c/tps65010.h
+++ b/include/linux/i2c/tps65010.h
@@ -152,5 +152,35 @@ extern int tps65010_config_vregs1(unsigned value);
 */
 extern int tps65013_set_low_pwr(unsigned mode);
+struct i2c_client;
+/**
+ * struct tps65010_board - packages GPIO and LED lines
+ * @base: the GPIO number to assign to GPIO-1
+ * @outmask: bit (N-1) is set to allow GPIO-N to be used as an
+ *      (open drain) output
+ * @setup: optional callback issued once the GPIOs are valid
+ * @teardown: optional callback issued before the GPIOs are invalidated
+ * @context: optional parameter passed to setup() and teardown()
+ *
+ * Board data may be used to package the GPIO (and LED) lines for use
+ * in by the generic GPIO and LED frameworks.  The first four GPIOs
+ * starting at gpio_base are GPIO1..GPIO4.  The next two are LED1/nPG
+ * and LED2 (with hardware blinking capability, not currently exposed).
+ *
+ * The @setup callback may be used with the kind of board-specific glue
+ * which hands the (now-valid) GPIOs to other drivers, or which puts
+ * devices in their initial states using these GPIOs.
+ */
+struct tps65010_board {
+        int                             base;
+        unsigned                        outmask;
+        int             (*setup)(struct i2c_client *client, void *context);
+        int             (*teardown)(struct i2c_client *client, void *context);
+        void            *context;
+};
 #endif /*  __LINUX_I2C_TPS65010_H */
diff --git a/include/linux/i2o.h b/include/linux/i2o.h
index 7da5b98d90e6..e92170dda245 100644
--- a/include/linux/i2o.h
+++ b/include/linux/i2o.h
@@ -33,9 +33,9 @@
 #include <linux/mempool.h>
 #include <linux/mutex.h>
 #include <linux/scatterlist.h>
+#include <linux/semaphore.h>    /* Needed for MUTEX init macros */
 #include <asm/io.h>
-#include <asm/semaphore.h>      /* Needed for MUTEX init macros */
 /* message queue empty */
 #define I2O_QUEUE_EMPTY         0xffffffff
diff --git a/include/linux/ide.h b/include/linux/ide.h
index 6c39482fd1a1..5f3e82ae901a 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -23,7 +23,6 @@
 #include <asm/byteorder.h>
 #include <asm/system.h>
 #include <asm/io.h>
-#include <asm/semaphore.h>
 #include <asm/mutex.h>
 #if defined(CONFIG_CRIS) || defined(CONFIG_FRV)
diff --git a/include/linux/if_pppox.h b/include/linux/if_pppox.h
index 40743e032845..6fb7f1788570 100644
--- a/include/linux/if_pppox.h
+++ b/include/linux/if_pppox.h
@@ -24,7 +24,6 @@
 #include <linux/if_ether.h>
 #include <linux/if.h>
 #include <linux/netdevice.h>
-#include <asm/semaphore.h>
 #include <linux/ppp_channel.h>
 #endif /* __KERNEL__ */
 #include <linux/if_pppol2tp.h>
diff --git a/include/linux/init_task.h b/include/linux/init_task.h
index 1f74e1d7415f..37a6f5bc4a92 100644
--- a/include/linux/init_task.h
+++ b/include/linux/init_task.h
@@ -151,6 +151,9 @@ extern struct group_info init_groups;
        .cpus_allowed   = CPU_MASK_ALL,                                 \
        .mm             = NULL,                                         \
        .active_mm      = &init_mm,                                     \
+        .se             = {                                             \
+                .group_node     = LIST_HEAD_INIT(tsk.se.group_node),    \
+        },                                                              \
        .rt             = {                                             \
                .run_list       = LIST_HEAD_INIT(tsk.rt.run_list),      \
                .time_slice     = HZ,                                   \
diff --git a/include/linux/irqflags.h b/include/linux/irqflags.h
index 412e025bc5c7..e600c4e9b8c5 100644
--- a/include/linux/irqflags.h
+++ b/include/linux/irqflags.h
@@ -84,10 +84,10 @@
 #define irqs_disabled()                                         \
 ({                                                              \
-        unsigned long flags;                                    \
+        unsigned long _flags;                                   \
                                                                \
-        raw_local_save_flags(flags);                            \
+        raw_local_save_flags(_flags);                           \
-        raw_irqs_disabled_flags(flags);                         \
+        raw_irqs_disabled_flags(_flags);                        \
 })
 #define irqs_disabled_flags(flags)      raw_irqs_disabled_flags(flags)
diff --git a/include/linux/jbd.h b/include/linux/jbd.h
index 423f58272188..07a9b52a2654 100644
--- a/include/linux/jbd.h
+++ b/include/linux/jbd.h
@@ -32,8 +32,6 @@
 #include <linux/timer.h>
 #include <linux/lockdep.h>
-#include <asm/semaphore.h>
 #define journal_oom_retry 1
 /*
diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h
index 2cbf6fdb1799..05e2b307161a 100644
--- a/include/linux/jbd2.h
+++ b/include/linux/jbd2.h
@@ -30,8 +30,6 @@
 #include <linux/bit_spinlock.h>
 #include <linux/mutex.h>
 #include <linux/timer.h>
-#include <asm/semaphore.h>
 #endif
 #define journal_oom_retry 1
diff --git a/include/linux/jiffies.h b/include/linux/jiffies.h
index e0b5b684d83f..e377e34e589e 100644
--- a/include/linux/jiffies.h
+++ b/include/linux/jiffies.h
@@ -135,6 +135,22 @@ static inline u64 get_jiffies_64(void)
 #define time_before_eq64(a,b)   time_after_eq64(b,a)
 /*
+ * These four macros compare jiffies and 'a' for convenience.
+ */
+/* time_is_before_jiffies(a) return true if a is before jiffies */
+#define time_is_before_jiffies(a) time_after(jiffies, a)
+/* time_is_after_jiffies(a) return true if a is after jiffies */
+#define time_is_after_jiffies(a) time_before(jiffies, a)
+/* time_is_before_eq_jiffies(a) return true if a is before or equal to jiffies*/
+#define time_is_before_eq_jiffies(a) time_after_eq(jiffies, a)
+/* time_is_after_eq_jiffies(a) return true if a is after or equal to jiffies*/
+#define time_is_after_eq_jiffies(a) time_before_eq(jiffies, a)
+/*
 * Have the 32 bit jiffies value wrap 5 minutes after boot
 * so jiffies wrap bugs show up earlier.
 */
diff --git a/include/linux/kernelcapi.h b/include/linux/kernelcapi.h
index 8c4350a9ed87..a53e932f80fb 100644
--- a/include/linux/kernelcapi.h
+++ b/include/linux/kernelcapi.h
@@ -48,7 +48,6 @@ typedef struct kcapi_carddef {
 #include <linux/list.h>
 #include <linux/skbuff.h>
 #include <linux/workqueue.h>
-#include <asm/semaphore.h>
 #define KCI_CONTRUP     0       /* arg: struct capi_profile */
 #define KCI_CONTRDOWN   1       /* arg: NULL */
diff --git a/include/linux/ktime.h b/include/linux/ktime.h
index 2cd7fa73d1af..ce5983225be4 100644
--- a/include/linux/ktime.h
+++ b/include/linux/ktime.h
@@ -327,4 +327,10 @@ extern void ktime_get_ts(struct timespec *ts);
 /* Get the real (wall-) time in timespec format: */
 #define ktime_get_real_ts(ts)   getnstimeofday(ts)
+static inline ktime_t ns_to_ktime(u64 ns)
+{
+        static const ktime_t ktime_zero = { .tv64 = 0 };
+        return ktime_add_ns(ktime_zero, ns);
+}
 #endif
diff --git a/include/linux/list.h b/include/linux/list.h
index 75ce2cb4ff6e..dac16f99c701 100644
--- a/include/linux/list.h
+++ b/include/linux/list.h
@@ -631,31 +631,14 @@ static inline void list_splice_init_rcu(struct list_head *list,
 * as long as the traversal is guarded by rcu_read_lock().
 */
 #define list_for_each_rcu(pos, head) \
-        for (pos = (head)->next; \
+        for (pos = rcu_dereference((head)->next); \
-                prefetch(rcu_dereference(pos)->next), pos != (head); \
+                prefetch(pos->next), pos != (head); \
-                pos = pos->next)
+                pos = rcu_dereference(pos->next))
 #define __list_for_each_rcu(pos, head) \
-        for (pos = (head)->next; \
+        for (pos = rcu_dereference((head)->next); \
-                rcu_dereference(pos) != (head); \
+                pos != (head); \
-                pos = pos->next)
+                pos = rcu_dereference(pos->next))
-/**
- * list_for_each_safe_rcu
- * @pos:        the &struct list_head to use as a loop cursor.
- * @n:          another &struct list_head to use as temporary storage
- * @head:       the head for your list.
- *
- * Iterate over an rcu-protected list, safe against removal of list entry.
- *
- * This list-traversal primitive may safely run concurrently with
- * the _rcu list-mutation primitives such as list_add_rcu()
- * as long as the traversal is guarded by rcu_read_lock().
- */
-#define list_for_each_safe_rcu(pos, n, head) \
-        for (pos = (head)->next; \
-                n = rcu_dereference(pos)->next, pos != (head); \
-                pos = n)
 /**
 * list_for_each_entry_rcu      -       iterate over rcu list of given type
@@ -668,10 +651,9 @@ static inline void list_splice_init_rcu(struct list_head *list,
 * as long as the traversal is guarded by rcu_read_lock().
 */
 #define list_for_each_entry_rcu(pos, head, member) \
-        for (pos = list_entry((head)->next, typeof(*pos), member); \
+        for (pos = list_entry(rcu_dereference((head)->next), typeof(*pos), member); \
-                prefetch(rcu_dereference(pos)->member.next), \
+                prefetch(pos->member.next), &pos->member != (head); \
-                        &pos->member != (head); \
+                pos = list_entry(rcu_dereference(pos->member.next), typeof(*pos), member))
-                pos = list_entry(pos->member.next, typeof(*pos), member))
 /**
@@ -686,9 +668,9 @@ static inline void list_splice_init_rcu(struct list_head *list,
 * as long as the traversal is guarded by rcu_read_lock().
 */
 #define list_for_each_continue_rcu(pos, head) \
-        for ((pos) = (pos)->next; \
+        for ((pos) = rcu_dereference((pos)->next); \
-                prefetch(rcu_dereference((pos))->next), (pos) != (head); \
+                prefetch((pos)->next), (pos) != (head); \
-                (pos) = (pos)->next)
+                (pos) = rcu_dereference((pos)->next))
 /*
 * Double linked lists with a single pointer list head.
@@ -986,10 +968,10 @@ static inline void hlist_add_after_rcu(struct hlist_node *prev,
 * as long as the traversal is guarded by rcu_read_lock().
 */
 #define hlist_for_each_entry_rcu(tpos, pos, head, member)                \
-        for (pos = (head)->first;                                        \
+        for (pos = rcu_dereference((head)->first);                       \
-             rcu_dereference(pos) && ({ prefetch(pos->next); 1;}) &&     \
+                pos && ({ prefetch(pos->next); 1;}) &&                   \
                ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
-             pos = pos->next)
+             pos = rcu_dereference(pos->next))
 #else
 #warning "don't include kernel headers in userspace"
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
new file mode 100644
index 000000000000..c11ff2932549
--- /dev/null
+++ b/include/linux/mbus.h
@@ -0,0 +1,36 @@
+/*
+ * Marvell MBUS common definitions.
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __LINUX_MBUS_H
+#define __LINUX_MBUS_H
+struct mbus_dram_target_info
+{
+        /*
+         * The 4-bit MBUS target ID of the DRAM controller.
+         */
+        u8              mbus_dram_target_id;
+        /*
+         * The base address, size, and MBUS attribute ID for each
+         * of the possible DRAM chip selects.  Peripherals are
+         * required to support at least 4 decode windows.
+         */
+        int             num_cs;
+        struct mbus_dram_window {
+                u8      cs_index;
+                u8      mbus_attr;
+                u32     base;
+                u32     size;
+        } cs[4];
+};
+#endif
diff --git a/include/linux/mfd/htc-egpio.h b/include/linux/mfd/htc-egpio.h
new file mode 100644
index 000000000000..b4201c971367
--- /dev/null
+++ b/include/linux/mfd/htc-egpio.h
@@ -0,0 +1,57 @@
+/*
+ * HTC simple EGPIO irq and gpio extender
+ */
+#ifndef __HTC_EGPIO_H__
+#define __HTC_EGPIO_H__
+#include <linux/gpio.h>
+/* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */
+#define HTC_EGPIO_OUTPUT (~0)
+#define HTC_EGPIO_INPUT  0
+/**
+ * struct htc_egpio_chip - descriptor to create gpio_chip for register range
+ * @reg_start: index of first register
+ * @gpio_base: gpio number of first pin in this register range
+ * @num_gpios: number of gpios in this register range, max BITS_PER_LONG
+ *    (number of registers = DIV_ROUND_UP(num_gpios, reg_width))
+ * @direction: bitfield, '0' = input, '1' = output,
+ */
+struct htc_egpio_chip {
+        int           reg_start;
+        int           gpio_base;
+        int           num_gpios;
+        unsigned long direction;
+        unsigned long initial_values;
+};
+/**
+ * struct htc_egpio_platform_data - description provided by the arch
+ * @irq_base: beginning of available IRQs (eg, IRQ_BOARD_START)
+ * @num_irqs: number of irqs
+ * @reg_width: number of bits per register, either 8 or 16 bit
+ * @bus_width: alignment of the registers, either 16 or 32 bit
+ * @invert_acks: set if chip requires writing '0' to ack an irq, instead of '1'
+ * @ack_register: location of the irq/ack register
+ * @chip: pointer to array of htc_egpio_chip descriptors
+ * @num_chips: number of egpio chip descriptors
+ */
+struct htc_egpio_platform_data {
+        int                   bus_width;
+        int                   reg_width;
+        int                   irq_base;
+        int                   num_irqs;
+        int                   invert_acks;
+        int                   ack_register;
+        struct htc_egpio_chip *chip;
+        int                   num_chips;
+};
+/* Determine the wakeup irq, to be called during early resume */
+extern int htc_egpio_get_wakeup_irq(struct device *dev);
+#endif
diff --git a/include/linux/mfd/htc-pasic3.h b/include/linux/mfd/htc-pasic3.h
new file mode 100644
index 000000000000..b4294f12c4f8
--- /dev/null
+++ b/include/linux/mfd/htc-pasic3.h
@@ -0,0 +1,55 @@
+/*
+ * HTC PASIC3 driver - LEDs and DS1WM
+ *
+ * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ *
+ */
+#ifndef __PASIC3_H
+#define __PASIC3_H
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+extern void pasic3_write_register(struct device *dev, u32 reg, u8 val);
+extern u8 pasic3_read_register(struct device *dev, u32 reg);
+/*
+ * mask for registers 0x20,0x21,0x22
+ */
+#define PASIC3_MASK_LED0 0x04
+#define PASIC3_MASK_LED1 0x08
+#define PASIC3_MASK_LED2 0x40
+/*
+ * bits in register 0x06
+ */
+#define PASIC3_BIT2_LED0 0x08
+#define PASIC3_BIT2_LED1 0x10
+#define PASIC3_BIT2_LED2 0x20
+struct pasic3_led {
+        struct led_classdev         led;
+        unsigned int                hw_num;
+        unsigned int                bit2;
+        unsigned int                mask;
+        struct pasic3_leds_machinfo *pdata;
+};
+struct pasic3_leds_machinfo {
+        unsigned int      num_leds;
+        unsigned int      power_gpio;
+        struct pasic3_led *leds;
+};
+struct pasic3_platform_data {
+        struct pasic3_leds_machinfo *led_pdata;
+        unsigned int                 bus_shift;
+        unsigned int                 clock_rate;
+};
+#endif
diff --git a/include/linux/mount.h b/include/linux/mount.h
index 5ee2df217cdf..d6600e3f7e45 100644
--- a/include/linux/mount.h
+++ b/include/linux/mount.h
@@ -14,6 +14,7 @@
 #include <linux/types.h>
 #include <linux/list.h>
+#include <linux/nodemask.h>
 #include <linux/spinlock.h>
 #include <asm/atomic.h>
@@ -28,8 +29,10 @@ struct mnt_namespace;
 #define MNT_NOATIME     0x08
 #define MNT_NODIRATIME  0x10
 #define MNT_RELATIME    0x20
+#define MNT_READONLY    0x40    /* does the user want this to be r/o? */
 #define MNT_SHRINKABLE  0x100
+#define MNT_IMBALANCED_WRITE_COUNT      0x200 /* just for debugging */
 #define MNT_SHARED      0x1000  /* if the vfsmount is a shared mount */
 #define MNT_UNBINDABLE  0x2000  /* if the vfsmount is a unbindable mount */
@@ -62,6 +65,11 @@ struct vfsmount {
        int mnt_expiry_mark;            /* true if marked for expiry */
        int mnt_pinned;
        int mnt_ghosts;
+        /*
+         * This value is not stable unless all of the mnt_writers[] spinlocks
+         * are held, and all mnt_writer[]s on this mount have 0 as their ->count
+         */
+        atomic_t __mnt_writers;
 };
 static inline struct vfsmount *mntget(struct vfsmount *mnt)
@@ -71,9 +79,12 @@ static inline struct vfsmount *mntget(struct vfsmount *mnt)
        return mnt;
 }
+extern int mnt_want_write(struct vfsmount *mnt);
+extern void mnt_drop_write(struct vfsmount *mnt);
 extern void mntput_no_expire(struct vfsmount *mnt);
 extern void mnt_pin(struct vfsmount *mnt);
 extern void mnt_unpin(struct vfsmount *mnt);
+extern int __mnt_is_readonly(struct vfsmount *mnt);
 static inline void mntput(struct vfsmount *mnt)
 {
diff --git a/include/linux/parport.h b/include/linux/parport.h
index d1ad546c8c9e..dcb9e01a69ca 100644
--- a/include/linux/parport.h
+++ b/include/linux/parport.h
@@ -101,9 +101,9 @@ typedef enum {
 #include <linux/spinlock.h>
 #include <linux/wait.h>
 #include <linux/irqreturn.h>
+#include <linux/semaphore.h>
 #include <asm/system.h>
 #include <asm/ptrace.h>
-#include <asm/semaphore.h>
 /* Define this later. */
 struct parport;
diff --git a/include/linux/prctl.h b/include/linux/prctl.h
index 3800639775ae..5c80b1939636 100644
--- a/include/linux/prctl.h
+++ b/include/linux/prctl.h
@@ -67,4 +67,10 @@
 #define PR_CAPBSET_READ 23
 #define PR_CAPBSET_DROP 24
+/* Get/set the process' ability to use the timestamp counter instruction */
+#define PR_GET_TSC 25
+#define PR_SET_TSC 26
+# define PR_TSC_ENABLE          1       /* allow the use of the timestamp counter */
+# define PR_TSC_SIGSEGV         2       /* throw a SIGSEGV instead of reading the TSC */
 #endif /* _LINUX_PRCTL_H */
diff --git a/include/linux/raid/md.h b/include/linux/raid/md.h
index fbaeda79b2e9..8ab630b67fcc 100644
--- a/include/linux/raid/md.h
+++ b/include/linux/raid/md.h
@@ -19,7 +19,6 @@
 #define _MD_H
 #include <linux/blkdev.h>
-#include <asm/semaphore.h>
 #include <linux/major.h>
 #include <linux/ioctl.h>
 #include <linux/types.h>
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 6a1e7afb099b..311380e5fe89 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -61,7 +61,6 @@ struct sched_param {
 #include <linux/mm_types.h>
 #include <asm/system.h>
-#include <asm/semaphore.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include <asm/cputime.h>
@@ -704,6 +703,7 @@ enum cpu_idle_type {
 #define SD_POWERSAVINGS_BALANCE 256     /* Balance for power savings */
 #define SD_SHARE_PKG_RESOURCES  512     /* Domain members share cpu pkg resources */
 #define SD_SERIALIZE            1024    /* Only a single load balancing instance */
+#define SD_WAKE_IDLE_FAR        2048    /* Gain latency sacrificing cache hit */
 #define BALANCE_FOR_MC_POWER    \
        (sched_smt_power_savings ? SD_POWERSAVINGS_BALANCE : 0)
@@ -733,12 +733,31 @@ struct sched_group {
        u32 reciprocal_cpu_power;
 };
+enum sched_domain_level {
+        SD_LV_NONE = 0,
+        SD_LV_SIBLING,
+        SD_LV_MC,
+        SD_LV_CPU,
+        SD_LV_NODE,
+        SD_LV_ALLNODES,
+        SD_LV_MAX
+};
+struct sched_domain_attr {
+        int relax_domain_level;
+};
+#define SD_ATTR_INIT    (struct sched_domain_attr) {    \
+        .relax_domain_level = -1,                       \
+}
 struct sched_domain {
        /* These fields must be setup */
        struct sched_domain *parent;    /* top domain must be null terminated */
        struct sched_domain *child;     /* bottom domain must be null terminated */
        struct sched_group *groups;     /* the balancing groups of the domain */
        cpumask_t span;                 /* span of all CPUs in this domain */
+        int first_cpu;                  /* cache of the first cpu in this domain */
        unsigned long min_interval;     /* Minimum balance interval ms */
        unsigned long max_interval;     /* Maximum balance interval ms */
        unsigned int busy_factor;       /* less balancing by factor if busy */
@@ -750,6 +769,7 @@ struct sched_domain {
        unsigned int wake_idx;
        unsigned int forkexec_idx;
        int flags;                      /* See SD_* */
+        enum sched_domain_level level;
        /* Runtime fields. */
        unsigned long last_balance;     /* init to jiffies. units in jiffies */
@@ -789,7 +809,8 @@ struct sched_domain {
 #endif
 };
-extern void partition_sched_domains(int ndoms_new, cpumask_t *doms_new);
+extern void partition_sched_domains(int ndoms_new, cpumask_t *doms_new,
+                                    struct sched_domain_attr *dattr_new);
 extern int arch_reinit_sched_domains(void);
 #endif  /* CONFIG_SMP */
@@ -889,7 +910,8 @@ struct sched_class {
        void (*set_curr_task) (struct rq *rq);
        void (*task_tick) (struct rq *rq, struct task_struct *p, int queued);
        void (*task_new) (struct rq *rq, struct task_struct *p);
-        void (*set_cpus_allowed)(struct task_struct *p, cpumask_t *newmask);
+        void (*set_cpus_allowed)(struct task_struct *p,
+                                 const cpumask_t *newmask);
        void (*join_domain)(struct rq *rq);
        void (*leave_domain)(struct rq *rq);
@@ -923,6 +945,7 @@ struct load_weight {
 struct sched_entity {
        struct load_weight      load;           /* for load-balancing */
        struct rb_node          run_node;
+        struct list_head        group_node;
        unsigned int            on_rq;
        u64                     exec_start;
@@ -982,6 +1005,7 @@ struct sched_rt_entity {
        unsigned long timeout;
        int nr_cpus_allowed;
+        struct sched_rt_entity *back;
 #ifdef CONFIG_RT_GROUP_SCHED
        struct sched_rt_entity  *parent;
        /* rq on which this entity is (to be) queued: */
@@ -1502,15 +1526,21 @@ static inline void put_task_struct(struct task_struct *t)
 #define used_math() tsk_used_math(current)
 #ifdef CONFIG_SMP
-extern int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask);
+extern int set_cpus_allowed_ptr(struct task_struct *p,
+                                const cpumask_t *new_mask);
 #else
-static inline int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask)
+static inline int set_cpus_allowed_ptr(struct task_struct *p,
+                                       const cpumask_t *new_mask)
 {
-        if (!cpu_isset(0, new_mask))
+        if (!cpu_isset(0, *new_mask))
                return -EINVAL;
        return 0;
 }
 #endif
+static inline int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask)
+{
+        return set_cpus_allowed_ptr(p, &new_mask);
+}
 extern unsigned long long sched_clock(void);
@@ -1551,7 +1581,6 @@ static inline void wake_up_idle_cpu(int cpu) { }
 extern unsigned int sysctl_sched_latency;
 extern unsigned int sysctl_sched_min_granularity;
 extern unsigned int sysctl_sched_wakeup_granularity;
-extern unsigned int sysctl_sched_batch_wakeup_granularity;
 extern unsigned int sysctl_sched_child_runs_first;
 extern unsigned int sysctl_sched_features;
 extern unsigned int sysctl_sched_migration_cost;
@@ -1564,6 +1593,10 @@ int sched_nr_latency_handler(struct ctl_table *table, int write,
 extern unsigned int sysctl_sched_rt_period;
 extern int sysctl_sched_rt_runtime;
+int sched_rt_handler(struct ctl_table *table, int write,
+                struct file *filp, void __user *buffer, size_t *lenp,
+                loff_t *ppos);
 extern unsigned int sysctl_sched_compat_yield;
 #ifdef CONFIG_RT_MUTEXES
@@ -2031,7 +2064,7 @@ static inline void arch_pick_mmap_layout(struct mm_struct *mm)
 }
 #endif
-extern long sched_setaffinity(pid_t pid, cpumask_t new_mask);
+extern long sched_setaffinity(pid_t pid, const cpumask_t *new_mask);
 extern long sched_getaffinity(pid_t pid, cpumask_t *mask);
 extern int sched_mc_power_savings, sched_smt_power_savings;
@@ -2041,8 +2074,11 @@ extern void normalize_rt_tasks(void);
 #ifdef CONFIG_GROUP_SCHED
 extern struct task_group init_task_group;
+#ifdef CONFIG_USER_SCHED
+extern struct task_group root_task_group;
+#endif
-extern struct task_group *sched_create_group(void);
+extern struct task_group *sched_create_group(struct task_group *parent);
 extern void sched_destroy_group(struct task_group *tg);
 extern void sched_move_task(struct task_struct *tsk);
 #ifdef CONFIG_FAIR_GROUP_SCHED
@@ -2053,6 +2089,9 @@ extern unsigned long sched_group_shares(struct task_group *tg);
 extern int sched_group_set_rt_runtime(struct task_group *tg,
                                      long rt_runtime_us);
 extern long sched_group_rt_runtime(struct task_group *tg);
+extern int sched_group_set_rt_period(struct task_group *tg,
+                                      long rt_period_us);
+extern long sched_group_rt_period(struct task_group *tg);
 #endif
 #endif
diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h
index 4c2577bd1c85..8df6d1382ac8 100644
--- a/include/linux/syscalls.h
+++ b/include/linux/syscalls.h
@@ -60,7 +60,6 @@ struct getcpu_cache;
 #include <linux/capability.h>
 #include <linux/list.h>
 #include <linux/sem.h>
-#include <asm/semaphore.h>
 #include <asm/siginfo.h>
 #include <asm/signal.h>
 #include <linux/quota.h>
diff --git a/include/linux/sysdev.h b/include/linux/sysdev.h
index f752e73bf977..f2767bc6b735 100644
--- a/include/linux/sysdev.h
+++ b/include/linux/sysdev.h
@@ -45,12 +45,16 @@ struct sysdev_class_attribute {
        ssize_t (*store)(struct sysdev_class *, const char *, size_t);
 };
-#define SYSDEV_CLASS_ATTR(_name,_mode,_show,_store)             \
+#define _SYSDEV_CLASS_ATTR(_name,_mode,_show,_store)            \
-struct sysdev_class_attribute attr_##_name = {                  \
+{                                                               \
        .attr = {.name = __stringify(_name), .mode = _mode },   \
        .show   = _show,                                        \
        .store  = _store,                                       \
-};
+}
+#define SYSDEV_CLASS_ATTR(_name,_mode,_show,_store)             \
+        struct sysdev_class_attribute attr_##_name =            \
+                _SYSDEV_CLASS_ATTR(_name,_mode,_show,_store)
 extern int sysdev_class_register(struct sysdev_class *);
@@ -100,15 +104,16 @@ struct sysdev_attribute {
 };
-#define _SYSDEV_ATTR(_name,_mode,_show,_store)                  \
+#define _SYSDEV_ATTR(_name, _mode, _show, _store)               \
 {                                                               \
        .attr = { .name = __stringify(_name), .mode = _mode },  \
        .show   = _show,                                        \
        .store  = _store,                                       \
 }
-#define SYSDEV_ATTR(_name,_mode,_show,_store)           \
+#define SYSDEV_ATTR(_name, _mode, _show, _store)                \
-struct sysdev_attribute attr_##_name = _SYSDEV_ATTR(_name,_mode,_show,_store);
+        struct sysdev_attribute attr_##_name =                  \
+                _SYSDEV_ATTR(_name, _mode, _show, _store);
 extern int sysdev_create_file(struct sys_device *, struct sysdev_attribute *);
 extern void sysdev_remove_file(struct sys_device *, struct sysdev_attribute *);
diff --git a/include/linux/topology.h b/include/linux/topology.h
index bd14f8b30f09..4bb7074a2c3a 100644
--- a/include/linux/topology.h
+++ b/include/linux/topology.h
@@ -38,16 +38,15 @@
 #endif
 #ifndef nr_cpus_node
-#define nr_cpus_node(node)                                                      \
+#define nr_cpus_node(node)                              \
-        ({                                                                      \
+        ({                                              \
-                cpumask_t __tmp__;                                              \
+                node_to_cpumask_ptr(__tmp__, node);     \
-                __tmp__ = node_to_cpumask(node);                                \
+                cpus_weight(*__tmp__);                  \
-                cpus_weight(__tmp__);                                           \
        })
 #endif
-#define for_each_node_with_cpus(node)                                           \
+#define for_each_node_with_cpus(node)                   \
-        for_each_online_node(node)                                              \
+        for_each_online_node(node)                      \
                if (nr_cpus_node(node))
 void arch_update_cpu_topology(void);
@@ -80,7 +79,9 @@ void arch_update_cpu_topology(void);
 * by defining their own arch-specific initializer in include/asm/topology.h.
 * A definition there will automagically override these default initializers
 * and allow arch-specific performance tuning of sched_domains.
+ * (Only non-zero and non-null fields need be specified.)
 */
 #ifdef CONFIG_SCHED_SMT
 /* MCD - Do we really need this?  It is always on if CONFIG_SCHED_SMT is,
 * so can't we drop this in favor of CONFIG_SCHED_SMT?
@@ -89,20 +90,10 @@ void arch_update_cpu_topology(void);
 /* Common values for SMT siblings */
 #ifndef SD_SIBLING_INIT
 #define SD_SIBLING_INIT (struct sched_domain) {         \
-        .span                   = CPU_MASK_NONE,        \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
        .min_interval           = 1,                    \
        .max_interval           = 2,                    \
        .busy_factor            = 64,                   \
        .imbalance_pct          = 110,                  \
-        .cache_nice_tries       = 0,                    \
-        .busy_idx               = 0,                    \
-        .idle_idx               = 0,                    \
-        .newidle_idx            = 0,                    \
-        .wake_idx               = 0,                    \
-        .forkexec_idx           = 0,                    \
        .flags                  = SD_LOAD_BALANCE       \
                                | SD_BALANCE_NEWIDLE    \
                                | SD_BALANCE_FORK       \
@@ -112,7 +103,6 @@ void arch_update_cpu_topology(void);
                                | SD_SHARE_CPUPOWER,    \
        .last_balance           = jiffies,              \
        .balance_interval       = 1,                    \
-        .nr_balance_failed      = 0,                    \
 }
 #endif
 #endif /* CONFIG_SCHED_SMT */
@@ -121,18 +111,12 @@ void arch_update_cpu_topology(void);
 /* Common values for MC siblings. for now mostly derived from SD_CPU_INIT */
 #ifndef SD_MC_INIT
 #define SD_MC_INIT (struct sched_domain) {              \
-        .span                   = CPU_MASK_NONE,        \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
        .min_interval           = 1,                    \
        .max_interval           = 4,                    \
        .busy_factor            = 64,                   \
        .imbalance_pct          = 125,                  \
        .cache_nice_tries       = 1,                    \
        .busy_idx               = 2,                    \
-        .idle_idx               = 0,                    \
-        .newidle_idx            = 0,                    \
        .wake_idx               = 1,                    \
        .forkexec_idx           = 1,                    \
        .flags                  = SD_LOAD_BALANCE       \
@@ -144,7 +128,6 @@ void arch_update_cpu_topology(void);
                                | BALANCE_FOR_MC_POWER, \
        .last_balance           = jiffies,              \
        .balance_interval       = 1,                    \
-        .nr_balance_failed      = 0,                    \
 }
 #endif
 #endif /* CONFIG_SCHED_MC */
@@ -152,10 +135,6 @@ void arch_update_cpu_topology(void);
 /* Common values for CPUs */
 #ifndef SD_CPU_INIT
 #define SD_CPU_INIT (struct sched_domain) {             \
-        .span                   = CPU_MASK_NONE,        \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
        .min_interval           = 1,                    \
        .max_interval           = 4,                    \
        .busy_factor            = 64,                   \
@@ -174,16 +153,11 @@ void arch_update_cpu_topology(void);
                                | BALANCE_FOR_PKG_POWER,\
        .last_balance           = jiffies,              \
        .balance_interval       = 1,                    \
-        .nr_balance_failed      = 0,                    \
 }
 #endif
 /* sched_domains SD_ALLNODES_INIT for NUMA machines */
 #define SD_ALLNODES_INIT (struct sched_domain) {        \
-        .span                   = CPU_MASK_NONE,        \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
        .min_interval           = 64,                   \
        .max_interval           = 64*num_online_cpus(), \
        .busy_factor            = 128,                  \
@@ -191,14 +165,10 @@ void arch_update_cpu_topology(void);
        .cache_nice_tries       = 1,                    \
        .busy_idx               = 3,                    \
        .idle_idx               = 3,                    \
-        .newidle_idx            = 0, /* unused */       \
-        .wake_idx               = 0, /* unused */       \
-        .forkexec_idx           = 0, /* unused */       \
        .flags                  = SD_LOAD_BALANCE       \
                                | SD_SERIALIZE, \
        .last_balance           = jiffies,              \
        .balance_interval       = 64,                   \
-        .nr_balance_failed      = 0,                    \
 }
 #ifdef CONFIG_NUMA
diff --git a/include/linux/usb/atmel_usba_udc.h b/include/linux/usb/atmel_usba_udc.h
new file mode 100644
index 000000000000..6311fa2d9f82
--- /dev/null
+++ b/include/linux/usb/atmel_usba_udc.h
@@ -0,0 +1,22 @@
+/*
+ * Platform data definitions for Atmel USBA gadget driver.
+ */
+#ifndef __LINUX_USB_USBA_H
+#define __LINUX_USB_USBA_H
+struct usba_ep_data {
+        char    *name;
+        int     index;
+        int     fifo_size;
+        int     nr_banks;
+        int     can_dma;
+        int     can_isoc;
+};
+struct usba_platform_data {
+        int                     vbus_pin;
+        int                     num_ep;
+        struct usba_ep_data     ep[0];
+};
+#endif /* __LINUX_USB_USBA_H */
diff --git a/include/scsi/libsas.h b/include/scsi/libsas.h
index 98724ba65a79..e78d3b62d8ec 100644
--- a/include/scsi/libsas.h
+++ b/include/scsi/libsas.h
@@ -32,7 +32,6 @@
 #include <scsi/sas.h>
 #include <linux/libata.h>
 #include <linux/list.h>
-#include <asm/semaphore.h>
 #include <scsi/scsi_device.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_transport_sas.h>