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-rw-r--r--include/asm-arm/arch-at91rm9200/at91_ecc.h8
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_pmc.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/at91_rtc.h16
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h2
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h4
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam926x_mc.h8
7 files changed, 21 insertions, 21 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91_ecc.h b/include/asm-arm/arch-at91rm9200/at91_ecc.h
index fddf256a98d3..5c564ede5c5d 100644
--- a/include/asm-arm/arch-at91rm9200/at91_ecc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_ecc.h
@@ -14,7 +14,7 @@
14#define AT91_ECC_H 14#define AT91_ECC_H
15 15
16#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */ 16#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
17#define AT91_ECC_RST (1 << 0) /* Reset parity */ 17#define AT91_ECC_RST (1 << 0) /* Reset parity */
18 18
19#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */ 19#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
20#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */ 20#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
@@ -23,16 +23,16 @@
23#define AT91_ECC_PAGESIZE_2112 (2) 23#define AT91_ECC_PAGESIZE_2112 (2)
24#define AT91_ECC_PAGESIZE_4224 (3) 24#define AT91_ECC_PAGESIZE_4224 (3)
25 25
26#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */ 26#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
27#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */ 27#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
28#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ 28#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
29#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */ 29#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
30 30
31#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */ 31#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
32#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */ 32#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
33#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ 33#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
34 34
35#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */ 35#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
36#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */ 36#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
37 37
38#endif 38#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91_pmc.h b/include/asm-arm/arch-at91rm9200/at91_pmc.h
index de8c3da74a01..c3b489d09b6c 100644
--- a/include/asm-arm/arch-at91rm9200/at91_pmc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_pmc.h
@@ -61,7 +61,7 @@
61#define AT91_PMC_CSS_PLLA (2 << 0) 61#define AT91_PMC_CSS_PLLA (2 << 0)
62#define AT91_PMC_CSS_PLLB (3 << 0) 62#define AT91_PMC_CSS_PLLB (3 << 0)
63#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ 63#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
64#define AT91_PMC_PRES_1 (0 << 2) 64#define AT91_PMC_PRES_1 (0 << 2)
65#define AT91_PMC_PRES_2 (1 << 2) 65#define AT91_PMC_PRES_2 (1 << 2)
66#define AT91_PMC_PRES_4 (2 << 2) 66#define AT91_PMC_PRES_4 (2 << 2)
67#define AT91_PMC_PRES_8 (3 << 2) 67#define AT91_PMC_PRES_8 (3 << 2)
diff --git a/include/asm-arm/arch-at91rm9200/at91_rtc.h b/include/asm-arm/arch-at91rm9200/at91_rtc.h
index 6e5065d56260..095fe0883102 100644
--- a/include/asm-arm/arch-at91rm9200/at91_rtc.h
+++ b/include/asm-arm/arch-at91rm9200/at91_rtc.h
@@ -21,21 +21,21 @@
21#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ 21#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
22#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ 22#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
23#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) 23#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
24#define AT91_RTC_TIMEVSEL_HOUR (1 << 8) 24#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
25#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) 25#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
26#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) 26#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
27#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ 27#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
28#define AT91_RTC_CALEVSEL_WEEK (0 << 16) 28#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
29#define AT91_RTC_CALEVSEL_MONTH (1 << 16) 29#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
30#define AT91_RTC_CALEVSEL_YEAR (2 << 16) 30#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
31 31
32#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ 32#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
33#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ 33#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
34 34
35#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ 35#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
36#define AT91_RTC_SEC (0x7f << 0) /* Current Second */ 36#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
37#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ 37#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
38#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ 38#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
39#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ 39#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
40 40
41#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ 41#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
index 4d51177efddd..c569b6a21a42 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -274,7 +274,7 @@
274#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */ 274#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */
275#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */ 275#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */
276#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */ 276#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */
277#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */ 277#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
278#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */ 278#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */
279#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */ 279#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */
280#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */ 280#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
index 746d973705bf..78f6b4917b8b 100644
--- a/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
+++ b/include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
@@ -58,7 +58,7 @@
58#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 58#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
59 59
60#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ 60#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
61#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 61#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
62#define AT91_MATRIX_CS1A_SMC (0 << 1) 62#define AT91_MATRIX_CS1A_SMC (0 << 1)
63#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 63#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
64#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ 64#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
index ab25f9e94d69..ec88efabbe6c 100644
--- a/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
+++ b/include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
@@ -43,8 +43,8 @@
43 43
44#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ 44#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
45#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 45#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
46#define AT91_MATRIX_CS1A_SMC (0 << 1) 46#define AT91_MATRIX_CS1A_SMC (0 << 1)
47#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 47#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
48#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ 48#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
49#define AT91_MATRIX_CS3A_SMC (0 << 3) 49#define AT91_MATRIX_CS3A_SMC (0 << 3)
50#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) 50#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
index 8ac797e39a14..972e7531c7f4 100644
--- a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
+++ b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
@@ -33,14 +33,14 @@
33#define AT91_SDRAMC_NC_9 (1 << 0) 33#define AT91_SDRAMC_NC_9 (1 << 0)
34#define AT91_SDRAMC_NC_10 (2 << 0) 34#define AT91_SDRAMC_NC_10 (2 << 0)
35#define AT91_SDRAMC_NC_11 (3 << 0) 35#define AT91_SDRAMC_NC_11 (3 << 0)
36#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ 36#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
37#define AT91_SDRAMC_NR_11 (0 << 2) 37#define AT91_SDRAMC_NR_11 (0 << 2)
38#define AT91_SDRAMC_NR_12 (1 << 2) 38#define AT91_SDRAMC_NR_12 (1 << 2)
39#define AT91_SDRAMC_NR_13 (2 << 2) 39#define AT91_SDRAMC_NR_13 (2 << 2)
40#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ 40#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
41#define AT91_SDRAMC_NB_2 (0 << 4) 41#define AT91_SDRAMC_NB_2 (0 << 4)
42#define AT91_SDRAMC_NB_4 (1 << 4) 42#define AT91_SDRAMC_NB_4 (1 << 4)
43#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ 43#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
44#define AT91_SDRAMC_CAS_1 (1 << 5) 44#define AT91_SDRAMC_CAS_1 (1 << 5)
45#define AT91_SDRAMC_CAS_2 (2 << 5) 45#define AT91_SDRAMC_CAS_2 (2 << 5)
46#define AT91_SDRAMC_CAS_3 (3 << 5) 46#define AT91_SDRAMC_CAS_3 (3 << 5)