diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-ppc/pgtable.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index c41c7958ea1f..92f30b28b252 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h | |||
@@ -227,21 +227,21 @@ extern unsigned long ioremap_bot, ioremap_base; | |||
227 | * doesn't support SMP. So we can use this as software bit, like | 227 | * doesn't support SMP. So we can use this as software bit, like |
228 | * DIRTY. | 228 | * DIRTY. |
229 | * | 229 | * |
230 | * PPC Book-E Linux implementation uses PPC HW PTE bit field definition, | 230 | * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used |
231 | * even it doesn't have HW PTE. 0-11th LSB of PTE stand for memory | 231 | * for memory protection related functions (see PTE structure in |
232 | * protection-related function. (See PTE structure in include/asm-ppc/mmu.h) | 232 | * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the |
233 | * Definition of _PAGE_XXX in "include/asm-ppc/pagetable.h" stands for | 233 | * above bits. Note that the bit values are CPU specific, not architecture |
234 | * above bits. Note that those bits values are CPU dependent, not | 234 | * specific. |
235 | * architecture. | ||
236 | * | 235 | * |
237 | * Kernel PTE entry holds arch-dependent swp_entry structure under certain | 236 | * The kernel PTE entry holds an arch-dependent swp_entry structure under |
238 | * situation. In other words, in such situation, some portion of PTE bits | 237 | * certain situations. In other words, in such situations some portion of |
239 | * are used as swp_entry. In PPC implementation, 3-24th LSB are shared with | 238 | * the PTE bits are used as a swp_entry. In the PPC implementation, the |
240 | * swp_entry, however 0-2nd three LSB still hold protection values. | 239 | * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still |
241 | * That means three protection bits are reserved for both PTE and SWAP | 240 | * hold protection values. That means the three protection bits are |
242 | * entry at the most three LSBs. | 241 | * reserved for both PTE and SWAP entry at the most significant three |
242 | * LSBs. | ||
243 | * | 243 | * |
244 | * There are three protection bits available for SWAP entry; | 244 | * There are three protection bits available for SWAP entry: |
245 | * _PAGE_PRESENT | 245 | * _PAGE_PRESENT |
246 | * _PAGE_FILE | 246 | * _PAGE_FILE |
247 | * _PAGE_HASHPTE (if HW has) | 247 | * _PAGE_HASHPTE (if HW has) |