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-rw-r--r--include/asm-arm/.gitignore2
-rw-r--r--include/asm-arm/arch-ep93xx/ep93xx-regs.h5
-rw-r--r--include/asm-arm/arch-ep93xx/irqs.h8
-rw-r--r--include/asm-arm/arch-ep93xx/platform.h1
-rw-r--r--include/asm-arm/arch-imx/entry-macro.S18
-rw-r--r--include/asm-arm/arch-ixp4xx/udc.h22
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h24
-rw-r--r--include/asm-arm/arch-pxa/udc.h30
-rw-r--r--include/asm-arm/arch-realview/hardware.h2
-rw-r--r--include/asm-arm/arch-realview/irqs.h5
-rw-r--r--include/asm-arm/arch-realview/platform.h18
-rw-r--r--include/asm-arm/arch-realview/scu.h8
-rw-r--r--include/asm-arm/arch-s3c2410/dma.h36
-rw-r--r--include/asm-arm/arch-s3c2410/irqs.h74
-rw-r--r--include/asm-arm/arch-s3c2410/regs-adc.h2
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h32
-rw-r--r--include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h194
-rw-r--r--include/asm-arm/arch-s3c2410/regs-serial.h13
-rw-r--r--include/asm-arm/arch-s3c2410/reset.h22
-rw-r--r--include/asm-arm/arch-s3c2410/system.h15
-rw-r--r--include/asm-arm/arch-s3c2410/udc.h36
-rw-r--r--include/asm-arm/cacheflush.h49
-rw-r--r--include/asm-arm/device.h10
-rw-r--r--include/asm-arm/dma-mapping.h18
-rw-r--r--include/asm-arm/domain.h1
-rw-r--r--include/asm-arm/hardware/arm_scu.h2
-rw-r--r--include/asm-arm/hardware/cache-l2x0.h56
-rw-r--r--include/asm-arm/hardware/gic.h5
-rw-r--r--include/asm-arm/hardware/sa1111.h93
-rw-r--r--include/asm-arm/kexec.h30
-rw-r--r--include/asm-arm/pgtable.h54
-rw-r--r--include/asm-arm/plat-s3c24xx/clock.h63
-rw-r--r--include/asm-arm/plat-s3c24xx/common-smdk.h15
-rw-r--r--include/asm-arm/plat-s3c24xx/cpu.h70
-rw-r--r--include/asm-arm/plat-s3c24xx/devs.h51
-rw-r--r--include/asm-arm/plat-s3c24xx/dma.h77
-rw-r--r--include/asm-arm/plat-s3c24xx/irq.h107
-rw-r--r--include/asm-arm/plat-s3c24xx/pm.h73
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2400.h31
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2410.h31
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2412.h29
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2440.h17
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2442.h17
-rw-r--r--include/asm-arm/plat-s3c24xx/s3c2443.h32
-rw-r--r--include/asm-arm/system.h62
-rw-r--r--include/asm-arm/tlbflush.h50
-rw-r--r--include/asm-arm/unistd.h1
-rw-r--r--include/linux/kexec.h1
48 files changed, 1424 insertions, 188 deletions
diff --git a/include/asm-arm/.gitignore b/include/asm-arm/.gitignore
new file mode 100644
index 000000000000..e02c15d158fc
--- /dev/null
+++ b/include/asm-arm/.gitignore
@@ -0,0 +1,2 @@
1arch
2mach-types.h
diff --git a/include/asm-arm/arch-ep93xx/ep93xx-regs.h b/include/asm-arm/arch-ep93xx/ep93xx-regs.h
index 593f562f85c3..625c6f0abc03 100644
--- a/include/asm-arm/arch-ep93xx/ep93xx-regs.h
+++ b/include/asm-arm/arch-ep93xx/ep93xx-regs.h
@@ -73,6 +73,11 @@
73 73
74#define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) 74#define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000)
75#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) 75#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
76#define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c)
77#define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50)
78#define EP93XX_GPIO_F_INT_ACK EP93XX_GPIO_REG(0x54)
79#define EP93XX_GPIO_F_INT_ENABLE EP93XX_GPIO_REG(0x58)
80#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c)
76#define EP93XX_GPIO_A_INT_TYPE1 EP93XX_GPIO_REG(0x90) 81#define EP93XX_GPIO_A_INT_TYPE1 EP93XX_GPIO_REG(0x90)
77#define EP93XX_GPIO_A_INT_TYPE2 EP93XX_GPIO_REG(0x94) 82#define EP93XX_GPIO_A_INT_TYPE2 EP93XX_GPIO_REG(0x94)
78#define EP93XX_GPIO_A_INT_ACK EP93XX_GPIO_REG(0x98) 83#define EP93XX_GPIO_A_INT_ACK EP93XX_GPIO_REG(0x98)
diff --git a/include/asm-arm/arch-ep93xx/irqs.h b/include/asm-arm/arch-ep93xx/irqs.h
index ae532e304bf1..2a8c63638c5e 100644
--- a/include/asm-arm/arch-ep93xx/irqs.h
+++ b/include/asm-arm/arch-ep93xx/irqs.h
@@ -67,9 +67,13 @@
67#define IRQ_EP93XX_SAI 60 67#define IRQ_EP93XX_SAI 60
68#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff 68#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
69 69
70#define IRQ_EP93XX_GPIO(x) (64 + (x)) 70/*
71 * Map GPIO A0..A7 to irq 64..71, B0..B7 to 72..79, and
72 * F0..F7 to 80..87.
73 */
74#define IRQ_EP93XX_GPIO(x) (64 + (((x) + (((x) >> 2) & 8)) & 0x1f))
71 75
72#define NR_EP93XX_IRQS IRQ_EP93XX_GPIO(16) 76#define NR_EP93XX_IRQS (64 + 24)
73 77
74#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) 78#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
75#define EP93XX_BOARD_IRQS 32 79#define EP93XX_BOARD_IRQS 32
diff --git a/include/asm-arm/arch-ep93xx/platform.h b/include/asm-arm/arch-ep93xx/platform.h
index b4a8deb8bdef..44eccec2cba4 100644
--- a/include/asm-arm/arch-ep93xx/platform.h
+++ b/include/asm-arm/arch-ep93xx/platform.h
@@ -8,7 +8,6 @@ void ep93xx_map_io(void);
8void ep93xx_init_irq(void); 8void ep93xx_init_irq(void);
9void ep93xx_init_time(unsigned long); 9void ep93xx_init_time(unsigned long);
10void ep93xx_init_devices(void); 10void ep93xx_init_devices(void);
11void ep93xx_clock_init(void);
12extern struct sys_timer ep93xx_timer; 11extern struct sys_timer ep93xx_timer;
13 12
14struct ep93xx_eth_data 13struct ep93xx_eth_data
diff --git a/include/asm-arm/arch-imx/entry-macro.S b/include/asm-arm/arch-imx/entry-macro.S
index 3b9ef6914627..61bb0bdc1b16 100644
--- a/include/asm-arm/arch-imx/entry-macro.S
+++ b/include/asm-arm/arch-imx/entry-macro.S
@@ -13,19 +13,13 @@
13 .endm 13 .endm
14#define AITC_NIVECSR 0x40 14#define AITC_NIVECSR 0x40
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16 ldr \irqstat, =IO_ADDRESS(IMX_AITC_BASE) 16 ldr \base, =IO_ADDRESS(IMX_AITC_BASE)
17 @ Load offset & priority of the highest priority 17 @ Load offset & priority of the highest priority
18 @ interrupt pending. 18 @ interrupt pending.
19 ldr \irqnr, [\irqstat, #AITC_NIVECSR] 19 ldr \irqstat, [\base, #AITC_NIVECSR]
20 @ Shift off the priority leaving the offset or 20 @ Shift off the priority leaving the offset or
21 @ "interrupt number" 21 @ "interrupt number", use arithmetic shift to
22 mov \irqnr, \irqnr, lsr #16 22 @ transform illegal source (0xffff) as -1
23 ldr \irqstat, =1 @ dummy compare 23 mov \irqnr, \irqstat, asr #16
24 ldr \base, =0xFFFF // invalid interrupt 24 adds \tmp, \irqnr, #1
25 cmp \irqnr, \base
26 bne 1001f
27 ldr \irqstat, =0
281001:
29 tst \irqstat, #1 @ to make the condition code = TRUE
30 .endm 25 .endm
31
diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h
index dbdec36ff0d1..79b850a3be47 100644
--- a/include/asm-arm/arch-ixp4xx/udc.h
+++ b/include/asm-arm/arch-ixp4xx/udc.h
@@ -6,3 +6,25 @@
6 6
7extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info); 7extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
8 8
9static inline int udc_gpio_to_irq(unsigned gpio)
10{
11 return 0;
12}
13
14static inline void udc_gpio_init_vbus(unsigned gpio)
15{
16}
17
18static inline void udc_gpio_init_pullup(unsigned gpio)
19{
20}
21
22static inline int udc_gpio_get(unsigned gpio)
23{
24 return 0;
25}
26
27static inline void udc_gpio_set(unsigned gpio, int is_on)
28{
29}
30
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index e24f6b6c79ae..aec835b6f057 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -463,9 +463,6 @@
463 * Serial Audio Controller 463 * Serial Audio Controller
464 */ 464 */
465 465
466/* FIXME: This clash with SA1111 defines */
467#ifndef _ASM_ARCH_SA1111
468
469#define SACR0 __REG(0x40400000) /* Global Control Register */ 466#define SACR0 __REG(0x40400000) /* Global Control Register */
470#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ 467#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
471#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ 468#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
@@ -474,8 +471,8 @@
474#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ 471#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
475#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ 472#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
476 473
477#define SACR0_RFTH(x) (x << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ 474#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
478#define SACR0_TFTH(x) (x << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ 475#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
479#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ 476#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
480#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ 477#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
481#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ 478#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
@@ -503,8 +500,6 @@
503#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ 500#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
504#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ 501#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
505 502
506#endif
507
508/* 503/*
509 * AC97 Controller registers 504 * AC97 Controller registers
510 */ 505 */
@@ -1682,15 +1677,18 @@
1682#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ 1677#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
1683 1678
1684#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ 1679#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
1685#define SSPSP_DMYSTOP(x) (x << 23) /* Dummy Stop */ 1680#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
1686#define SSPSP_SFRMWDTH(x) (x << 16) /* Serial Frame Width */ 1681#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
1687#define SSPSP_SFRMDLY(x) (x << 9) /* Serial Frame Delay */ 1682#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
1688#define SSPSP_DMYSTRT(x) (x << 7) /* Dummy Start */ 1683#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
1689#define SSPSP_STRTDLY(x) (x << 4) /* Start Delay */ 1684#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
1690#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ 1685#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
1691#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ 1686#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
1692#define SSPSP_SCMODE(x) (x << 0) /* Serial Bit Rate Clock Mode */ 1687#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
1693 1688
1689#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
1690#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
1691#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
1694 1692
1695#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */ 1693#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
1696#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */ 1694#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
diff --git a/include/asm-arm/arch-pxa/udc.h b/include/asm-arm/arch-pxa/udc.h
index 646480d37256..8bc6f9c3e3ea 100644
--- a/include/asm-arm/arch-pxa/udc.h
+++ b/include/asm-arm/arch-pxa/udc.h
@@ -9,3 +9,33 @@
9 9
10extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); 10extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info);
11 11
12static inline int udc_gpio_to_irq(unsigned gpio)
13{
14 return IRQ_GPIO(gpio & GPIO_MD_MASK_NR);
15}
16
17static inline void udc_gpio_init_vbus(unsigned gpio)
18{
19 pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_IN);
20}
21
22static inline void udc_gpio_init_pullup(unsigned gpio)
23{
24 pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_OUT | GPIO_DFLT_LOW);
25}
26
27static inline int udc_gpio_get(unsigned gpio)
28{
29 return (GPLR(gpio) & GPIO_bit(gpio)) != 0;
30}
31
32static inline void udc_gpio_set(unsigned gpio, int is_on)
33{
34 int mask = GPIO_bit(gpio);
35
36 if (is_on)
37 GPSR(gpio) = mask;
38 else
39 GPCR(gpio) = mask;
40}
41
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
index 9ca76dc3a7af..aa78fe087ab2 100644
--- a/include/asm-arm/arch-realview/hardware.h
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -26,7 +26,7 @@
26#include <asm/arch/platform.h> 26#include <asm/arch/platform.h>
27 27
28/* macro to get at IO space when running virtually */ 28/* macro to get at IO space when running virtually */
29#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) 29#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
30#define __io_address(n) __io(IO_ADDRESS(n)) 30#define __io_address(n) __io(IO_ADDRESS(n))
31 31
32#endif 32#endif
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
index 76b498eb20a6..5a5db56f86b8 100644
--- a/include/asm-arm/arch-realview/irqs.h
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -78,6 +78,9 @@
78#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6) 78#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6)
79#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7) 79#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7)
80 80
81#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1)
82#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2)
83
81#define IRQMASK_WDOGINT INTMASK_WDOGINT 84#define IRQMASK_WDOGINT INTMASK_WDOGINT
82#define IRQMASK_SOFTINT INTMASK_SOFTINT 85#define IRQMASK_SOFTINT INTMASK_SOFTINT
83#define IRQMASK_COMMRx INTMASK_COMMRx 86#define IRQMASK_COMMRx INTMASK_COMMRx
@@ -115,4 +118,4 @@
115#define IRQMASK_ETH INTMASK_ETH 118#define IRQMASK_ETH INTMASK_ETH
116#define IRQMASK_USB INTMASK_USB 119#define IRQMASK_USB INTMASK_USB
117 120
118#define NR_IRQS (IRQ_GIC_START + 64) 121#define NR_IRQS (IRQ_GIC_START + 96)
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 18d7c18b738c..6e0eab95a3a2 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -207,11 +207,25 @@
207#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ 207#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
208#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ 208#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
209#else 209#else
210#ifdef CONFIG_REALVIEW_MPCORE_REVB
210#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */ 211#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
211#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ 212#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
212#define REALVIEW_TWD_BASE 0x10100700 213#define REALVIEW_TWD_BASE 0x10100700
213#define REALVIEW_TWD_SIZE 0x00000100 214#define REALVIEW_TWD_SIZE 0x00000100
214#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ 215#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
216#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */
217#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
218#else
219#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
220#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
221#define REALVIEW_TWD_BASE 0x1F000700
222#define REALVIEW_TWD_SIZE 0x00000100
223#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
224#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */
225#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
226#endif
227#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
228#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
215#endif 229#endif
216#define REALVIEW_SMC_BASE 0x10080000 /* SMC */ 230#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
217 /* Reserved 0x10090000 - 0x100EFFFF */ 231 /* Reserved 0x10090000 - 0x100EFFFF */
@@ -306,7 +320,11 @@
306#define INT_USB 29 /* USB controller */ 320#define INT_USB 29 /* USB controller */
307#define INT_TSPENINT 30 /* Touchscreen pen */ 321#define INT_TSPENINT 30 /* Touchscreen pen */
308#define INT_TSKPADINT 31 /* Touchscreen keypad */ 322#define INT_TSKPADINT 31 /* Touchscreen keypad */
323
309#else 324#else
325
326#define MAX_GIC_NR 2
327
310#define INT_AACI 0 328#define INT_AACI 0
311#define INT_TIMERINT0_1 1 329#define INT_TIMERINT0_1 1
312#define INT_TIMERINT2_3 2 330#define INT_TIMERINT2_3 2
diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h
new file mode 100644
index 000000000000..cc293640178e
--- /dev/null
+++ b/include/asm-arm/arch-realview/scu.h
@@ -0,0 +1,8 @@
1#ifndef __ASMARM_ARCH_SCU_H
2#define __ASMARM_ARCH_SCU_H
3
4#include <asm/arch/platform.h>
5
6#define SCU_BASE REALVIEW_MPCORE_SCU_BASE
7
8#endif
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index 58ffa7ba3c88..c6e8d8f64938 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -51,13 +51,19 @@ enum dma_ch {
51 DMACH_UART0_SRC2, /* s3c2412 second uart sources */ 51 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
52 DMACH_UART1_SRC2, 52 DMACH_UART1_SRC2,
53 DMACH_UART2_SRC2, 53 DMACH_UART2_SRC2,
54 DMACH_UART3, /* s3c2443 has extra uart */
55 DMACH_UART3_SRC2,
54 DMACH_MAX, /* the end entry */ 56 DMACH_MAX, /* the end entry */
55}; 57};
56 58
57#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ 59#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
58 60
59/* we have 4 dma channels */ 61/* we have 4 dma channels */
60#define S3C2410_DMA_CHANNELS (4) 62#ifndef CONFIG_CPU_S3C2443
63#define S3C2410_DMA_CHANNELS (4)
64#else
65#define S3C2410_DMA_CHANNELS (6)
66#endif
61 67
62/* types */ 68/* types */
63 69
@@ -321,6 +327,7 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
321#define S3C2410_DMA_DCDST (0x1C) 327#define S3C2410_DMA_DCDST (0x1C)
322#define S3C2410_DMA_DMASKTRIG (0x20) 328#define S3C2410_DMA_DMASKTRIG (0x20)
323#define S3C2412_DMA_DMAREQSEL (0x24) 329#define S3C2412_DMA_DMAREQSEL (0x24)
330#define S3C2443_DMA_DMAREQSEL (0x24)
324 331
325#define S3C2410_DISRCC_INC (1<<0) 332#define S3C2410_DISRCC_INC (1<<0)
326#define S3C2410_DISRCC_APB (1<<1) 333#define S3C2410_DISRCC_APB (1<<1)
@@ -415,4 +422,31 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
415#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) 422#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
416 423
417#endif 424#endif
425
426#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
427
428#define S3C2443_DMAREQSEL_HW (1)
429
430#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
431#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
432#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
433#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
434#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
435#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
436#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
437#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
438#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
439#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
440#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
441#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
442#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
443#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
444#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
445#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
446#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
447#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
448#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
449#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
450#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
451
418#endif /* __ASM_ARCH_DMA_H */ 452#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
index 4b7cff456c4e..c79cb1819913 100644
--- a/include/asm-arm/arch-s3c2410/irqs.h
+++ b/include/asm-arm/arch-s3c2410/irqs.h
@@ -34,10 +34,10 @@
34#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ 34#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
35#define IRQ_EINT8t23 S3C2410_IRQ(5) 35#define IRQ_EINT8t23 S3C2410_IRQ(5)
36#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ 36#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
37#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440 */ 37#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */
38#define IRQ_BATT_FLT S3C2410_IRQ(7) 38#define IRQ_BATT_FLT S3C2410_IRQ(7)
39#define IRQ_TICK S3C2410_IRQ(8) /* 24 */ 39#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
40#define IRQ_WDT S3C2410_IRQ(9) 40#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */
41#define IRQ_TIMER0 S3C2410_IRQ(10) 41#define IRQ_TIMER0 S3C2410_IRQ(10)
42#define IRQ_TIMER1 S3C2410_IRQ(11) 42#define IRQ_TIMER1 S3C2410_IRQ(11)
43#define IRQ_TIMER2 S3C2410_IRQ(12) 43#define IRQ_TIMER2 S3C2410_IRQ(12)
@@ -45,7 +45,7 @@
45#define IRQ_TIMER4 S3C2410_IRQ(14) 45#define IRQ_TIMER4 S3C2410_IRQ(14)
46#define IRQ_UART2 S3C2410_IRQ(15) 46#define IRQ_UART2 S3C2410_IRQ(15)
47#define IRQ_LCD S3C2410_IRQ(16) /* 32 */ 47#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
48#define IRQ_DMA0 S3C2410_IRQ(17) 48#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */
49#define IRQ_DMA1 S3C2410_IRQ(18) 49#define IRQ_DMA1 S3C2410_IRQ(18)
50#define IRQ_DMA2 S3C2410_IRQ(19) 50#define IRQ_DMA2 S3C2410_IRQ(19)
51#define IRQ_DMA3 S3C2410_IRQ(20) 51#define IRQ_DMA3 S3C2410_IRQ(20)
@@ -94,29 +94,63 @@
94 * these need to be ordered in number of appearance in the 94 * these need to be ordered in number of appearance in the
95 * SUBSRC mask register 95 * SUBSRC mask register
96*/ 96*/
97#define IRQ_S3CUART_RX0 S3C2410_IRQ(54) /* 70 */
98#define IRQ_S3CUART_TX0 S3C2410_IRQ(55) /* 71 */
99#define IRQ_S3CUART_ERR0 S3C2410_IRQ(56)
100 97
101#define IRQ_S3CUART_RX1 S3C2410_IRQ(57) 98#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54)
102#define IRQ_S3CUART_TX1 S3C2410_IRQ(58)
103#define IRQ_S3CUART_ERR1 S3C2410_IRQ(59)
104 99
105#define IRQ_S3CUART_RX2 S3C2410_IRQ(60) 100#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */
106#define IRQ_S3CUART_TX2 S3C2410_IRQ(61) 101#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
107#define IRQ_S3CUART_ERR2 S3C2410_IRQ(62) 102#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
108 103
109#define IRQ_TC S3C2410_IRQ(63) 104#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */
110#define IRQ_ADC S3C2410_IRQ(64) 105#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
106#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
111 107
112/* extra irqs for s3c2440 */ 108#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */
109#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
110#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
113 111
114#define IRQ_S3C2440_CAM_C S3C2410_IRQ(65) 112#define IRQ_TC S3C2410_IRQSUB(9)
115#define IRQ_S3C2440_CAM_P S3C2410_IRQ(66) 113#define IRQ_ADC S3C2410_IRQSUB(10)
116#define IRQ_S3C2440_WDT S3C2410_IRQ(67)
117#define IRQ_S3C2440_AC97 S3C2410_IRQ(68)
118 114
119#define NR_IRQS (IRQ_S3C2440_AC97+1) 115/* extra irqs for s3c2440 */
120 116
117#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
118#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */
119#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13)
120#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14)
121
122/* irqs for s3c2443 */
123
124#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
125#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
126#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
127#define IRQ_S3C2443_SDI1 S3C2410_IRQ(20) /* IRQ_SDI */
128#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
129
130#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
131#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
132#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
133#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17)
134
135#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18)
136#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19)
137#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20)
138#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21)
139#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22)
140#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23)
141
142/* UART3 */
143#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24)
144#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25)
145#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26)
146
147#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
148#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
149
150#ifdef CONFIG_CPU_S3C2443
151#define NR_IRQS (IRQ_S3C2443_AC97+1)
152#else
153#define NR_IRQS (IRQ_S3C2440_AC97+1)
154#endif
121 155
122#endif /* __ASM_ARCH_IRQ_H */ 156#endif /* __ASM_ARCH_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h b/include/asm-arm/arch-s3c2410/regs-adc.h
index 3196a2849e8a..c7f231963e76 100644
--- a/include/asm-arm/arch-s3c2410/regs-adc.h
+++ b/include/asm-arm/arch-s3c2410/regs-adc.h
@@ -41,7 +41,7 @@
41#define S3C2410_ADCTSC_XP_SEN (1<<4) 41#define S3C2410_ADCTSC_XP_SEN (1<<4)
42#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3) 42#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
43#define S3C2410_ADCTSC_AUTO_PST (1<<2) 43#define S3C2410_ADCTSC_AUTO_PST (1<<2)
44#define S3C2410_ADCTSC_XY_PST (0x3<<0) 44#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
45 45
46/* ADCDAT0 Bits */ 46/* ADCDAT0 Bits */
47#define S3C2410_ADCDAT0_UPDOWN (1<<15) 47#define S3C2410_ADCDAT0_UPDOWN (1<<15)
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index eae91694edcd..dea578b8f7f6 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -201,7 +201,7 @@
201#define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) 201#define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C)
202#define S3C2400_GPBUP S3C2410_GPIOREG(0x10) 202#define S3C2400_GPBUP S3C2410_GPIOREG(0x10)
203 203
204/* no i/o pin in port b can have value 3! */ 204/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
205 205
206#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) 206#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
207#define S3C2410_GPB0_INP (0x00 << 0) 207#define S3C2410_GPB0_INP (0x00 << 0)
@@ -242,6 +242,7 @@
242#define S3C2410_GPB5_INP (0x00 << 10) 242#define S3C2410_GPB5_INP (0x00 << 10)
243#define S3C2410_GPB5_OUTP (0x01 << 10) 243#define S3C2410_GPB5_OUTP (0x01 << 10)
244#define S3C2410_GPB5_nXBACK (0x02 << 10) 244#define S3C2410_GPB5_nXBACK (0x02 << 10)
245#define S3C2443_GPB5_XBACK (0x03 << 10)
245#define S3C2400_GPB5_DATA21 (0x02 << 10) 246#define S3C2400_GPB5_DATA21 (0x02 << 10)
246#define S3C2400_GPB5_nCTS1 (0x03 << 10) 247#define S3C2400_GPB5_nCTS1 (0x03 << 10)
247 248
@@ -249,6 +250,7 @@
249#define S3C2410_GPB6_INP (0x00 << 12) 250#define S3C2410_GPB6_INP (0x00 << 12)
250#define S3C2410_GPB6_OUTP (0x01 << 12) 251#define S3C2410_GPB6_OUTP (0x01 << 12)
251#define S3C2410_GPB6_nXBREQ (0x02 << 12) 252#define S3C2410_GPB6_nXBREQ (0x02 << 12)
253#define S3C2443_GPB6_XBREQ (0x03 << 12)
252#define S3C2400_GPB6_DATA22 (0x02 << 12) 254#define S3C2400_GPB6_DATA22 (0x02 << 12)
253#define S3C2400_GPB6_nRTS1 (0x03 << 12) 255#define S3C2400_GPB6_nRTS1 (0x03 << 12)
254 256
@@ -256,6 +258,7 @@
256#define S3C2410_GPB7_INP (0x00 << 14) 258#define S3C2410_GPB7_INP (0x00 << 14)
257#define S3C2410_GPB7_OUTP (0x01 << 14) 259#define S3C2410_GPB7_OUTP (0x01 << 14)
258#define S3C2410_GPB7_nXDACK1 (0x02 << 14) 260#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
261#define S3C2443_GPB7_XDACK1 (0x03 << 14)
259#define S3C2400_GPB7_DATA23 (0x02 << 14) 262#define S3C2400_GPB7_DATA23 (0x02 << 14)
260 263
261#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) 264#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
@@ -268,6 +271,7 @@
268#define S3C2410_GPB9_INP (0x00 << 18) 271#define S3C2410_GPB9_INP (0x00 << 18)
269#define S3C2410_GPB9_OUTP (0x01 << 18) 272#define S3C2410_GPB9_OUTP (0x01 << 18)
270#define S3C2410_GPB9_nXDACK0 (0x02 << 18) 273#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
274#define S3C2443_GPB9_XDACK0 (0x03 << 18)
271#define S3C2400_GPB9_DATA25 (0x02 << 18) 275#define S3C2400_GPB9_DATA25 (0x02 << 18)
272#define S3C2400_GPB9_I2SSDI (0x03 << 18) 276#define S3C2400_GPB9_I2SSDI (0x03 << 18)
273 277
@@ -275,6 +279,7 @@
275#define S3C2410_GPB10_INP (0x00 << 20) 279#define S3C2410_GPB10_INP (0x00 << 20)
276#define S3C2410_GPB10_OUTP (0x01 << 20) 280#define S3C2410_GPB10_OUTP (0x01 << 20)
277#define S3C2410_GPB10_nXDRE0 (0x02 << 20) 281#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
282#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
278#define S3C2400_GPB10_DATA26 (0x02 << 20) 283#define S3C2400_GPB10_DATA26 (0x02 << 20)
279#define S3C2400_GPB10_nSS (0x03 << 20) 284#define S3C2400_GPB10_nSS (0x03 << 20)
280 285
@@ -556,6 +561,7 @@
556#define S3C2410_GPE0_INP (0x00 << 0) 561#define S3C2410_GPE0_INP (0x00 << 0)
557#define S3C2410_GPE0_OUTP (0x01 << 0) 562#define S3C2410_GPE0_OUTP (0x01 << 0)
558#define S3C2410_GPE0_I2SLRCK (0x02 << 0) 563#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
564#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
559#define S3C2400_GPE0_EINT0 (0x02 << 0) 565#define S3C2400_GPE0_EINT0 (0x02 << 0)
560#define S3C2410_GPE0_MASK (0x03 << 0) 566#define S3C2410_GPE0_MASK (0x03 << 0)
561 567
@@ -563,6 +569,7 @@
563#define S3C2410_GPE1_INP (0x00 << 2) 569#define S3C2410_GPE1_INP (0x00 << 2)
564#define S3C2410_GPE1_OUTP (0x01 << 2) 570#define S3C2410_GPE1_OUTP (0x01 << 2)
565#define S3C2410_GPE1_I2SSCLK (0x02 << 2) 571#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
572#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
566#define S3C2400_GPE1_EINT1 (0x02 << 2) 573#define S3C2400_GPE1_EINT1 (0x02 << 2)
567#define S3C2400_GPE1_nSS (0x03 << 2) 574#define S3C2400_GPE1_nSS (0x03 << 2)
568#define S3C2410_GPE1_MASK (0x03 << 2) 575#define S3C2410_GPE1_MASK (0x03 << 2)
@@ -571,6 +578,7 @@
571#define S3C2410_GPE2_INP (0x00 << 4) 578#define S3C2410_GPE2_INP (0x00 << 4)
572#define S3C2410_GPE2_OUTP (0x01 << 4) 579#define S3C2410_GPE2_OUTP (0x01 << 4)
573#define S3C2410_GPE2_CDCLK (0x02 << 4) 580#define S3C2410_GPE2_CDCLK (0x02 << 4)
581#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
574#define S3C2400_GPE2_EINT2 (0x02 << 4) 582#define S3C2400_GPE2_EINT2 (0x02 << 4)
575#define S3C2400_GPE2_I2SSDI (0x03 << 4) 583#define S3C2400_GPE2_I2SSDI (0x03 << 4)
576 584
@@ -578,6 +586,7 @@
578#define S3C2410_GPE3_INP (0x00 << 6) 586#define S3C2410_GPE3_INP (0x00 << 6)
579#define S3C2410_GPE3_OUTP (0x01 << 6) 587#define S3C2410_GPE3_OUTP (0x01 << 6)
580#define S3C2410_GPE3_I2SSDI (0x02 << 6) 588#define S3C2410_GPE3_I2SSDI (0x02 << 6)
589#define S3C2443_GPE3_AC_SDI (0x03 << 6)
581#define S3C2400_GPE3_EINT3 (0x02 << 6) 590#define S3C2400_GPE3_EINT3 (0x02 << 6)
582#define S3C2400_GPE3_nCTS1 (0x03 << 6) 591#define S3C2400_GPE3_nCTS1 (0x03 << 6)
583#define S3C2410_GPE3_nSS0 (0x03 << 6) 592#define S3C2410_GPE3_nSS0 (0x03 << 6)
@@ -587,6 +596,7 @@
587#define S3C2410_GPE4_INP (0x00 << 8) 596#define S3C2410_GPE4_INP (0x00 << 8)
588#define S3C2410_GPE4_OUTP (0x01 << 8) 597#define S3C2410_GPE4_OUTP (0x01 << 8)
589#define S3C2410_GPE4_I2SSDO (0x02 << 8) 598#define S3C2410_GPE4_I2SSDO (0x02 << 8)
599#define S3C2443_GPE4_AC_SDO (0x03 << 8)
590#define S3C2400_GPE4_EINT4 (0x02 << 8) 600#define S3C2400_GPE4_EINT4 (0x02 << 8)
591#define S3C2400_GPE4_nRTS1 (0x03 << 8) 601#define S3C2400_GPE4_nRTS1 (0x03 << 8)
592#define S3C2410_GPE4_I2SSDI (0x03 << 8) 602#define S3C2410_GPE4_I2SSDI (0x03 << 8)
@@ -596,6 +606,7 @@
596#define S3C2410_GPE5_INP (0x00 << 10) 606#define S3C2410_GPE5_INP (0x00 << 10)
597#define S3C2410_GPE5_OUTP (0x01 << 10) 607#define S3C2410_GPE5_OUTP (0x01 << 10)
598#define S3C2410_GPE5_SDCLK (0x02 << 10) 608#define S3C2410_GPE5_SDCLK (0x02 << 10)
609#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
599#define S3C2400_GPE5_EINT5 (0x02 << 10) 610#define S3C2400_GPE5_EINT5 (0x02 << 10)
600#define S3C2400_GPE5_TCLK1 (0x03 << 10) 611#define S3C2400_GPE5_TCLK1 (0x03 << 10)
601 612
@@ -603,24 +614,32 @@
603#define S3C2410_GPE6_INP (0x00 << 12) 614#define S3C2410_GPE6_INP (0x00 << 12)
604#define S3C2410_GPE6_OUTP (0x01 << 12) 615#define S3C2410_GPE6_OUTP (0x01 << 12)
605#define S3C2410_GPE6_SDCMD (0x02 << 12) 616#define S3C2410_GPE6_SDCMD (0x02 << 12)
617#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
618#define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
606#define S3C2400_GPE6_EINT6 (0x02 << 12) 619#define S3C2400_GPE6_EINT6 (0x02 << 12)
607 620
608#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) 621#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
609#define S3C2410_GPE7_INP (0x00 << 14) 622#define S3C2410_GPE7_INP (0x00 << 14)
610#define S3C2410_GPE7_OUTP (0x01 << 14) 623#define S3C2410_GPE7_OUTP (0x01 << 14)
611#define S3C2410_GPE7_SDDAT0 (0x02 << 14) 624#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
625#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
626#define S3C2443_GPE7_AC_SDI (0x03 << 14)
612#define S3C2400_GPE7_EINT7 (0x02 << 14) 627#define S3C2400_GPE7_EINT7 (0x02 << 14)
613 628
614#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) 629#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
615#define S3C2410_GPE8_INP (0x00 << 16) 630#define S3C2410_GPE8_INP (0x00 << 16)
616#define S3C2410_GPE8_OUTP (0x01 << 16) 631#define S3C2410_GPE8_OUTP (0x01 << 16)
617#define S3C2410_GPE8_SDDAT1 (0x02 << 16) 632#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
633#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
634#define S3C2443_GPE8_AC_SDO (0x03 << 16)
618#define S3C2400_GPE8_nXDACK0 (0x02 << 16) 635#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
619 636
620#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) 637#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
621#define S3C2410_GPE9_INP (0x00 << 18) 638#define S3C2410_GPE9_INP (0x00 << 18)
622#define S3C2410_GPE9_OUTP (0x01 << 18) 639#define S3C2410_GPE9_OUTP (0x01 << 18)
623#define S3C2410_GPE9_SDDAT2 (0x02 << 18) 640#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
641#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
642#define S3C2443_GPE9_AC_SYNC (0x03 << 18)
624#define S3C2400_GPE9_nXDACK1 (0x02 << 18) 643#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
625#define S3C2400_GPE9_nXBACK (0x03 << 18) 644#define S3C2400_GPE9_nXBACK (0x03 << 18)
626 645
@@ -628,6 +647,8 @@
628#define S3C2410_GPE10_INP (0x00 << 20) 647#define S3C2410_GPE10_INP (0x00 << 20)
629#define S3C2410_GPE10_OUTP (0x01 << 20) 648#define S3C2410_GPE10_OUTP (0x01 << 20)
630#define S3C2410_GPE10_SDDAT3 (0x02 << 20) 649#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
650#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
651#define S3C2443_GPE10_AC_nRESET (0x03 << 20)
631#define S3C2400_GPE10_nXDREQ0 (0x02 << 20) 652#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
632 653
633#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) 654#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
@@ -796,6 +817,7 @@
796#define S3C2400_GPG4_MMCCLK (0x02 << 8) 817#define S3C2400_GPG4_MMCCLK (0x02 << 8)
797#define S3C2400_GPG4_I2SSDI (0x03 << 8) 818#define S3C2400_GPG4_I2SSDI (0x03 << 8)
798#define S3C2410_GPG4_LCDPWREN (0x03 << 8) 819#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
820#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
799 821
800#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) 822#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
801#define S3C2410_GPG5_INP (0x00 << 10) 823#define S3C2410_GPG5_INP (0x00 << 10)
@@ -803,7 +825,7 @@
803#define S3C2410_GPG5_EINT13 (0x02 << 10) 825#define S3C2410_GPG5_EINT13 (0x02 << 10)
804#define S3C2400_GPG5_MMCCMD (0x02 << 10) 826#define S3C2400_GPG5_MMCCMD (0x02 << 10)
805#define S3C2400_GPG5_IICSDA (0x03 << 10) 827#define S3C2400_GPG5_IICSDA (0x03 << 10)
806#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) 828#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
807 829
808#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) 830#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
809#define S3C2410_GPG6_INP (0x00 << 12) 831#define S3C2410_GPG6_INP (0x00 << 12)
@@ -845,6 +867,7 @@
845#define S3C2410_GPG11_OUTP (0x01 << 22) 867#define S3C2410_GPG11_OUTP (0x01 << 22)
846#define S3C2410_GPG11_EINT19 (0x02 << 22) 868#define S3C2410_GPG11_EINT19 (0x02 << 22)
847#define S3C2410_GPG11_TCLK1 (0x03 << 22) 869#define S3C2410_GPG11_TCLK1 (0x03 << 22)
870#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
848 871
849#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) 872#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
850#define S3C2410_GPG12_INP (0x00 << 24) 873#define S3C2410_GPG12_INP (0x00 << 24)
@@ -852,25 +875,28 @@
852#define S3C2410_GPG12_EINT20 (0x02 << 24) 875#define S3C2410_GPG12_EINT20 (0x02 << 24)
853#define S3C2410_GPG12_XMON (0x03 << 24) 876#define S3C2410_GPG12_XMON (0x03 << 24)
854#define S3C2442_GPG12_nSPICS0 (0x03 << 24) 877#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
878#define S3C2443_GPG12_nINPACK (0x03 << 24)
855 879
856#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) 880#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
857#define S3C2410_GPG13_INP (0x00 << 26) 881#define S3C2410_GPG13_INP (0x00 << 26)
858#define S3C2410_GPG13_OUTP (0x01 << 26) 882#define S3C2410_GPG13_OUTP (0x01 << 26)
859#define S3C2410_GPG13_EINT21 (0x02 << 26) 883#define S3C2410_GPG13_EINT21 (0x02 << 26)
860#define S3C2410_GPG13_nXPON (0x03 << 26) 884#define S3C2410_GPG13_nXPON (0x03 << 26)
885#define S3C2443_GPG13_CF_nREG (0x03 << 26)
861 886
862#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) 887#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
863#define S3C2410_GPG14_INP (0x00 << 28) 888#define S3C2410_GPG14_INP (0x00 << 28)
864#define S3C2410_GPG14_OUTP (0x01 << 28) 889#define S3C2410_GPG14_OUTP (0x01 << 28)
865#define S3C2410_GPG14_EINT22 (0x02 << 28) 890#define S3C2410_GPG14_EINT22 (0x02 << 28)
866#define S3C2410_GPG14_YMON (0x03 << 28) 891#define S3C2410_GPG14_YMON (0x03 << 28)
892#define S3C2443_GPG14_CF_RESET (0x03 << 28)
867 893
868#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) 894#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
869#define S3C2410_GPG15_INP (0x00 << 30) 895#define S3C2410_GPG15_INP (0x00 << 30)
870#define S3C2410_GPG15_OUTP (0x01 << 30) 896#define S3C2410_GPG15_OUTP (0x01 << 30)
871#define S3C2410_GPG15_EINT23 (0x02 << 30) 897#define S3C2410_GPG15_EINT23 (0x02 << 30)
872#define S3C2410_GPG15_nYPON (0x03 << 30) 898#define S3C2410_GPG15_nYPON (0x03 << 30)
873 899#define S3C2443_GPG15_CF_PWR (0x03 << 30)
874 900
875#define S3C2410_GPG_PUPDIS(x) (1<<(x)) 901#define S3C2410_GPG_PUPDIS(x) (1<<(x))
876 902
diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
new file mode 100644
index 000000000000..ff0536d2de42
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h
@@ -0,0 +1,194 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-clock.h
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2443 clock register definitions
12*/
13
14#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
15#define __ASM_ARM_REGS_S3C2443_CLOCK
16
17#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
18
19#define S3C2443_PLLCON_MDIVSHIFT 16
20#define S3C2443_PLLCON_PDIVSHIFT 8
21#define S3C2443_PLLCON_SDIVSHIFT 0
22#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
23#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
24#define S3C2443_PLLCON_SDIVMASK (3)
25
26#define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
27#define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
28#define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
29#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
30#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
31#define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
32#define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
33#define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
34#define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
35#define S3C2443_SWRST S3C2443_CLKREG(0x44)
36#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
37#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
38#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
39#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
40
41#define S3C2443_SWRST_RESET (0x533c2443)
42
43#define S3C2443_PLLCON_OFF (1<<24)
44
45#define S3C2443_CLKSRC_I2S_EXT (1<<14)
46#define S3C2443_CLKSRC_I2S_EPLLDIV (0<<14)
47#define S3C2443_CLKSRC_I2S_EPLLREF (2<<14)
48#define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14)
49#define S3C2443_CLKSRC_I2S_MASK (3<<14)
50
51#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<8)
52#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<8)
53#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<8)
54#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<8)
55#define S3C2443_CLKSRC_EPLLREF_MASK (3<<8)
56
57#define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6)
58#define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4)
59#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
60
61#define S3C2443_CLKDIV0_DVS (1<<13)
62#define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
63#define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
64
65#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
66
67#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
68#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
69
70#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
71#define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
72
73#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
74#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
75#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
76#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
77#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
78#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
79#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
80#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
81#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
82#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
83
84/* S3C2443_CLKDIV1 */
85
86#define S3C2443_CLKDIV1_CAMDIV_MASK (15<<26)
87#define S3C2443_CLKDIV1_CAMDIV_SHIFT (26)
88
89#define S3C2443_CLKDIV1_HSSPIDIV_MASK (3<<24)
90#define S3C2443_CLKDIV1_HSSPIDIV_SHIFT (24)
91
92#define S3C2443_CLKDIV1_DISPDIV_MASK (0xff<<16)
93#define S3C2443_CLKDIV1_DISPDIV_SHIFT (16)
94
95#define S3C2443_CLKDIV1_I2SDIV_MASK (15<<12)
96#define S3C2443_CLKDIV1_I2SDIV_SHIFT (12)
97
98#define S3C2443_CLKDIV1_UARTDIV_MASK (15<<8)
99#define S3C2443_CLKDIV1_UARTDIV_SHIFT (8)
100
101#define S3C2443_CLKDIV1_HSMMCDIV_MASK (3<<6)
102#define S3C2443_CLKDIV1_HSMMCDIV_SHIFT (6)
103
104#define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4)
105#define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4)
106
107#define S3C2443_CLKCON_NAND
108
109#define S3C2443_HCLKCON_DMA0 (1<<0)
110#define S3C2443_HCLKCON_DMA1 (1<<1)
111#define S3C2443_HCLKCON_DMA2 (1<<2)
112#define S3C2443_HCLKCON_DMA3 (1<<3)
113#define S3C2443_HCLKCON_DMA4 (1<<4)
114#define S3C2443_HCLKCON_DMA5 (1<<5)
115#define S3C2443_HCLKCON_CAMIF (1<<8)
116#define S3C2443_HCLKCON_DISP (1<<9)
117#define S3C2443_HCLKCON_LCDC (1<<10)
118#define S3C2443_HCLKCON_USBH (1<<11)
119#define S3C2443_HCLKCON_USBD (1<<12)
120#define S3C2443_HCLKCON_HSMMC (1<<16)
121#define S3C2443_HCLKCON_CFC (1<<17)
122#define S3C2443_HCLKCON_SSMC (1<<18)
123#define S3C2443_HCLKCON_DRAMC (1<<19)
124
125#define S3C2443_PCLKCON_UART0 (1<<0)
126#define S3C2443_PCLKCON_UART1 (1<<1)
127#define S3C2443_PCLKCON_UART2 (1<<2)
128#define S3C2443_PCLKCON_UART3 (1<<3)
129#define S3C2443_PCLKCON_IIC (1<<4)
130#define S3C2443_PCLKCON_SDI (1<<5)
131#define S3C2443_PCLKCON_ADC (1<<7)
132#define S3C2443_PCLKCON_IIS (1<<9)
133#define S3C2443_PCLKCON_PWMT (1<<10)
134#define S3C2443_PCLKCON_WDT (1<<11)
135#define S3C2443_PCLKCON_RTC (1<<12)
136#define S3C2443_PCLKCON_GPIO (1<<13)
137#define S3C2443_PCLKCON_SPI0 (1<<14)
138#define S3C2443_PCLKCON_SPI1 (1<<15)
139
140#define S3C2443_SCLKCON_DDRCLK (1<<16)
141#define S3C2443_SCLKCON_SSMCCLK (1<<15)
142#define S3C2443_SCLKCON_HSSPICLK (1<<14)
143#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
144#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
145#define S3C2443_SCLKCON_CAMCLK (1<<11)
146#define S3C2443_SCLKCON_DISPCLK (1<<10)
147#define S3C2443_SCLKCON_I2SCLK (1<<9)
148#define S3C2443_SCLKCON_UARTCLK (1<<8)
149#define S3C2443_SCLKCON_USBHOST (1<<1)
150
151#include <asm/div64.h>
152
153static inline unsigned int
154s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
155{
156 unsigned int mdiv, pdiv, sdiv;
157 uint64_t fvco;
158
159 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
160 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
161 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
162
163 mdiv &= S3C2443_PLLCON_MDIVMASK;
164 pdiv &= S3C2443_PLLCON_PDIVMASK;
165 sdiv &= S3C2443_PLLCON_SDIVMASK;
166
167 fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
168 do_div(fvco, pdiv << sdiv);
169
170 return (unsigned int)fvco;
171}
172
173static inline unsigned int
174s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
175{
176 unsigned int mdiv, pdiv, sdiv;
177 uint64_t fvco;
178
179 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
180 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
181 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
182
183 mdiv &= S3C2443_PLLCON_MDIVMASK;
184 pdiv &= S3C2443_PLLCON_PDIVMASK;
185 sdiv &= S3C2443_PLLCON_SDIVMASK;
186
187 fvco = (uint64_t)baseclk * (mdiv + 8);
188 do_div(fvco, (pdiv + 2) << sdiv);
189
190 return (unsigned int)fvco;
191}
192
193#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
194
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
index 46f52401d132..8946702a87f5 100644
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ b/include/asm-arm/arch-s3c2410/regs-serial.h
@@ -35,10 +35,12 @@
35#define S3C24XX_VA_UART0 (S3C24XX_VA_UART) 35#define S3C24XX_VA_UART0 (S3C24XX_VA_UART)
36#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 ) 36#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 )
37#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 ) 37#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 )
38#define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC000 )
38 39
39#define S3C2410_PA_UART0 (S3C24XX_PA_UART) 40#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
40#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) 41#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
41#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) 42#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
43#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
42 44
43#define S3C2410_URXH (0x24) 45#define S3C2410_URXH (0x24)
44#define S3C2410_UTXH (0x20) 46#define S3C2410_UTXH (0x20)
@@ -73,6 +75,8 @@
73#define S3C2440_UCON_UCLK (1<<10) 75#define S3C2440_UCON_UCLK (1<<10)
74#define S3C2440_UCON_PCLK2 (2<<10) 76#define S3C2440_UCON_PCLK2 (2<<10)
75#define S3C2440_UCON_FCLK (3<<10) 77#define S3C2440_UCON_FCLK (3<<10)
78#define S3C2443_UCON_EPLL (3<<10)
79
76#define S3C2440_UCON2_FCLK_EN (1<<15) 80#define S3C2440_UCON2_FCLK_EN (1<<15)
77#define S3C2440_UCON0_DIVMASK (15 << 12) 81#define S3C2440_UCON0_DIVMASK (15 << 12)
78#define S3C2440_UCON1_DIVMASK (15 << 12) 82#define S3C2440_UCON1_DIVMASK (15 << 12)
@@ -93,6 +97,8 @@
93#define S3C2410_UCON_TXIRQMODE (1<<2) 97#define S3C2410_UCON_TXIRQMODE (1<<2)
94#define S3C2410_UCON_RXIRQMODE (1<<0) 98#define S3C2410_UCON_RXIRQMODE (1<<0)
95#define S3C2410_UCON_RXFIFO_TOI (1<<7) 99#define S3C2410_UCON_RXFIFO_TOI (1<<7)
100#define S3C2443_UCON_RXERR_IRQEN (1<<6)
101#define S3C2443_UCON_LOOPBACK (1<<5)
96 102
97#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 103#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
98 S3C2410_UCON_RXILEVEL | \ 104 S3C2410_UCON_RXILEVEL | \
@@ -127,7 +133,7 @@
127#define S3C2410_UMCOM_AFC (1<<4) 133#define S3C2410_UMCOM_AFC (1<<4)
128#define S3C2410_UMCOM_RTS_LOW (1<<0) 134#define S3C2410_UMCOM_RTS_LOW (1<<0)
129 135
130#define S3C2412_UMCON_AFC_63 (0<<5) 136#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
131#define S3C2412_UMCON_AFC_56 (1<<5) 137#define S3C2412_UMCON_AFC_56 (1<<5)
132#define S3C2412_UMCON_AFC_48 (2<<5) 138#define S3C2412_UMCON_AFC_48 (2<<5)
133#define S3C2412_UMCON_AFC_40 (3<<5) 139#define S3C2412_UMCON_AFC_40 (3<<5)
@@ -143,6 +149,7 @@
143#define S3C2410_UFSTAT_RXMASK (15<<0) 149#define S3C2410_UFSTAT_RXMASK (15<<0)
144#define S3C2410_UFSTAT_RXSHIFT (0) 150#define S3C2410_UFSTAT_RXSHIFT (0)
145 151
152/* UFSTAT S3C2443 same as S3C2440 */
146#define S3C2440_UFSTAT_TXFULL (1<<14) 153#define S3C2440_UFSTAT_TXFULL (1<<14)
147#define S3C2440_UFSTAT_RXFULL (1<<6) 154#define S3C2440_UFSTAT_RXFULL (1<<6)
148#define S3C2440_UFSTAT_TXSHIFT (8) 155#define S3C2440_UFSTAT_TXSHIFT (8)
@@ -157,6 +164,8 @@
157#define S3C2410_UERSTAT_OVERRUN (1<<0) 164#define S3C2410_UERSTAT_OVERRUN (1<<0)
158#define S3C2410_UERSTAT_FRAME (1<<2) 165#define S3C2410_UERSTAT_FRAME (1<<2)
159#define S3C2410_UERSTAT_BREAK (1<<3) 166#define S3C2410_UERSTAT_BREAK (1<<3)
167#define S3C2443_UERSTAT_PARITY (1<<1)
168
160#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \ 169#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
161 S3C2410_UERSTAT_FRAME | \ 170 S3C2410_UERSTAT_FRAME | \
162 S3C2410_UERSTAT_BREAK) 171 S3C2410_UERSTAT_BREAK)
@@ -164,6 +173,8 @@
164#define S3C2410_UMSTAT_CTS (1<<0) 173#define S3C2410_UMSTAT_CTS (1<<0)
165#define S3C2410_UMSTAT_DeltaCTS (1<<2) 174#define S3C2410_UMSTAT_DeltaCTS (1<<2)
166 175
176#define S3C2443_DIVSLOT (0x2C)
177
167#ifndef __ASSEMBLY__ 178#ifndef __ASSEMBLY__
168 179
169/* struct s3c24xx_uart_clksrc 180/* struct s3c24xx_uart_clksrc
diff --git a/include/asm-arm/arch-s3c2410/reset.h b/include/asm-arm/arch-s3c2410/reset.h
new file mode 100644
index 000000000000..4f866cdecab0
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/reset.h
@@ -0,0 +1,22 @@
1/* linux/include/asm-arm/arch-s3c2410/reset.h
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2410 CPU reset controls
12*/
13
14#ifndef __ASM_ARCH_RESET_H
15#define __ASM_ARCH_RESET_H __FILE__
16
17/* This allows the over-ride of the default reset code
18*/
19
20extern void (*s3c24xx_reset_hook)(void);
21
22#endif /* __ASM_ARCH_RESET_H */
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index ecf250db45fb..1c74ef17da33 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -15,15 +15,16 @@
15 15
16#include <asm/arch/map.h> 16#include <asm/arch/map.h>
17#include <asm/arch/idle.h> 17#include <asm/arch/idle.h>
18#include <asm/arch/reset.h>
18 19
19#include <asm/arch/regs-watchdog.h> 20#include <asm/arch/regs-watchdog.h>
20#include <asm/arch/regs-clock.h> 21#include <asm/arch/regs-clock.h>
21 22
22void (*s3c24xx_idle)(void); 23void (*s3c24xx_idle)(void);
24void (*s3c24xx_reset_hook)(void);
23 25
24void s3c24xx_default_idle(void) 26void s3c24xx_default_idle(void)
25{ 27{
26 void __iomem *reg = S3C2410_CLKCON;
27 unsigned long tmp; 28 unsigned long tmp;
28 int i; 29 int i;
29 30
@@ -33,16 +34,18 @@ void s3c24xx_default_idle(void)
33 34
34 /* Warning: going into idle state upsets jtag scanning */ 35 /* Warning: going into idle state upsets jtag scanning */
35 36
36 __raw_writel(__raw_readl(reg) | (1<<2), reg); 37 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
38 S3C2410_CLKCON);
37 39
38 /* the samsung port seems to do a loop and then unset idle.. */ 40 /* the samsung port seems to do a loop and then unset idle.. */
39 for (i = 0; i < 50; i++) { 41 for (i = 0; i < 50; i++) {
40 tmp += __raw_readl(reg); /* ensure loop not optimised out */ 42 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
41 } 43 }
42 44
43 /* this bit is not cleared on re-start... */ 45 /* this bit is not cleared on re-start... */
44 46
45 __raw_writel(__raw_readl(reg) & ~(1<<2), reg); 47 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
48 S3C2410_CLKCON);
46} 49}
47 50
48static void arch_idle(void) 51static void arch_idle(void)
@@ -53,7 +56,6 @@ static void arch_idle(void)
53 s3c24xx_default_idle(); 56 s3c24xx_default_idle();
54} 57}
55 58
56
57static void 59static void
58arch_reset(char mode) 60arch_reset(char mode)
59{ 61{
@@ -61,6 +63,9 @@ arch_reset(char mode)
61 cpu_reset(0); 63 cpu_reset(0);
62 } 64 }
63 65
66 if (s3c24xx_reset_hook)
67 s3c24xx_reset_hook();
68
64 printk("arch_reset: attempting watchdog reset\n"); 69 printk("arch_reset: attempting watchdog reset\n");
65 70
66 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ 71 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
diff --git a/include/asm-arm/arch-s3c2410/udc.h b/include/asm-arm/arch-s3c2410/udc.h
new file mode 100644
index 000000000000..e59ec339d614
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/udc.h
@@ -0,0 +1,36 @@
1/* linux/include/asm/arch-s3c2410/udc.h
2 *
3 * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *
11 * Changelog:
12 * 14-Mar-2005 RTP Created file
13 * 02-Aug-2005 RTP File rename
14 * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
15 * 18-Jan-2007 HMW Add per-platform vbus_draw function
16*/
17
18#ifndef __ASM_ARM_ARCH_UDC_H
19#define __ASM_ARM_ARCH_UDC_H
20
21enum s3c2410_udc_cmd_e {
22 S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
23 S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
24 S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
25};
26
27struct s3c2410_udc_mach_info {
28 void (*udc_command)(enum s3c2410_udc_cmd_e);
29 void (*vbus_draw)(unsigned int ma);
30 unsigned int vbus_pin;
31 unsigned char vbus_pin_inverted;
32};
33
34extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
35
36#endif /* __ASM_ARM_ARCH_UDC_H */
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 5f531ea03059..afad32c76e6c 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -185,9 +185,15 @@ struct cpu_cache_fns {
185 void (*coherent_user_range)(unsigned long, unsigned long); 185 void (*coherent_user_range)(unsigned long, unsigned long);
186 void (*flush_kern_dcache_page)(void *); 186 void (*flush_kern_dcache_page)(void *);
187 187
188 void (*dma_inv_range)(unsigned long, unsigned long); 188 void (*dma_inv_range)(const void *, const void *);
189 void (*dma_clean_range)(unsigned long, unsigned long); 189 void (*dma_clean_range)(const void *, const void *);
190 void (*dma_flush_range)(unsigned long, unsigned long); 190 void (*dma_flush_range)(const void *, const void *);
191};
192
193struct outer_cache_fns {
194 void (*inv_range)(unsigned long, unsigned long);
195 void (*clean_range)(unsigned long, unsigned long);
196 void (*flush_range)(unsigned long, unsigned long);
191}; 197};
192 198
193/* 199/*
@@ -240,9 +246,40 @@ extern void __cpuc_flush_dcache_page(void *);
240#define dmac_clean_range __glue(_CACHE,_dma_clean_range) 246#define dmac_clean_range __glue(_CACHE,_dma_clean_range)
241#define dmac_flush_range __glue(_CACHE,_dma_flush_range) 247#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
242 248
243extern void dmac_inv_range(unsigned long, unsigned long); 249extern void dmac_inv_range(const void *, const void *);
244extern void dmac_clean_range(unsigned long, unsigned long); 250extern void dmac_clean_range(const void *, const void *);
245extern void dmac_flush_range(unsigned long, unsigned long); 251extern void dmac_flush_range(const void *, const void *);
252
253#endif
254
255#ifdef CONFIG_OUTER_CACHE
256
257extern struct outer_cache_fns outer_cache;
258
259static inline void outer_inv_range(unsigned long start, unsigned long end)
260{
261 if (outer_cache.inv_range)
262 outer_cache.inv_range(start, end);
263}
264static inline void outer_clean_range(unsigned long start, unsigned long end)
265{
266 if (outer_cache.clean_range)
267 outer_cache.clean_range(start, end);
268}
269static inline void outer_flush_range(unsigned long start, unsigned long end)
270{
271 if (outer_cache.flush_range)
272 outer_cache.flush_range(start, end);
273}
274
275#else
276
277static inline void outer_inv_range(unsigned long start, unsigned long end)
278{ }
279static inline void outer_clean_range(unsigned long start, unsigned long end)
280{ }
281static inline void outer_flush_range(unsigned long start, unsigned long end)
282{ }
246 283
247#endif 284#endif
248 285
diff --git a/include/asm-arm/device.h b/include/asm-arm/device.h
index d8f9872b0e2d..c61642b40603 100644
--- a/include/asm-arm/device.h
+++ b/include/asm-arm/device.h
@@ -3,5 +3,13 @@
3 * 3 *
4 * This file is released under the GPLv2 4 * This file is released under the GPLv2
5 */ 5 */
6#include <asm-generic/device.h> 6#ifndef ASMARM_DEVICE_H
7#define ASMARM_DEVICE_H
7 8
9struct dev_archdata {
10#ifdef CONFIG_DMABOUNCE
11 struct dmabounce_device_info *dmabounce;
12#endif
13};
14
15#endif
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h
index 9bc46b486afb..abfb75b654c7 100644
--- a/include/asm-arm/dma-mapping.h
+++ b/include/asm-arm/dma-mapping.h
@@ -17,7 +17,7 @@
17 * platforms with CONFIG_DMABOUNCE. 17 * platforms with CONFIG_DMABOUNCE.
18 * Use the driver DMA support - see dma-mapping.h (dma_sync_*) 18 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
19 */ 19 */
20extern void consistent_sync(void *kaddr, size_t size, int rw); 20extern void consistent_sync(const void *kaddr, size_t size, int rw);
21 21
22/* 22/*
23 * Return whether the given device DMA address mask can be supported 23 * Return whether the given device DMA address mask can be supported
@@ -61,6 +61,22 @@ static inline int dma_mapping_error(dma_addr_t dma_addr)
61 return dma_addr == ~0; 61 return dma_addr == ~0;
62} 62}
63 63
64/*
65 * Dummy noncoherent implementation. We don't provide a dma_cache_sync
66 * function so drivers using this API are highlighted with build warnings.
67 */
68static inline void *
69dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp)
70{
71 return NULL;
72}
73
74static inline void
75dma_free_noncoherent(struct device *dev, size_t size, void *cpu_addr,
76 dma_addr_t handle)
77{
78}
79
64/** 80/**
65 * dma_alloc_coherent - allocate consistent memory for DMA 81 * dma_alloc_coherent - allocate consistent memory for DMA
66 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices 82 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
diff --git a/include/asm-arm/domain.h b/include/asm-arm/domain.h
index 4c2885abbe6c..3c12a7625304 100644
--- a/include/asm-arm/domain.h
+++ b/include/asm-arm/domain.h
@@ -57,6 +57,7 @@
57 __asm__ __volatile__( \ 57 __asm__ __volatile__( \
58 "mcr p15, 0, %0, c3, c0 @ set domain" \ 58 "mcr p15, 0, %0, c3, c0 @ set domain" \
59 : : "r" (x)); \ 59 : : "r" (x)); \
60 isb(); \
60 } while (0) 61 } while (0)
61 62
62#define modify_domain(dom,type) \ 63#define modify_domain(dom,type) \
diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h
index 9903f60c84b7..7d28eb5a1758 100644
--- a/include/asm-arm/hardware/arm_scu.h
+++ b/include/asm-arm/hardware/arm_scu.h
@@ -1,6 +1,8 @@
1#ifndef ASMARM_HARDWARE_ARM_SCU_H 1#ifndef ASMARM_HARDWARE_ARM_SCU_H
2#define ASMARM_HARDWARE_ARM_SCU_H 2#define ASMARM_HARDWARE_ARM_SCU_H
3 3
4#include <asm/arch/scu.h>
5
4/* 6/*
5 * SCU registers 7 * SCU registers
6 */ 8 */
diff --git a/include/asm-arm/hardware/cache-l2x0.h b/include/asm-arm/hardware/cache-l2x0.h
new file mode 100644
index 000000000000..54029a740396
--- /dev/null
+++ b/include/asm-arm/hardware/cache-l2x0.h
@@ -0,0 +1,56 @@
1/*
2 * include/asm-arm/hardware/cache-l2x0.h
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __ASM_ARM_HARDWARE_L2X0_H
21#define __ASM_ARM_HARDWARE_L2X0_H
22
23#define L2X0_CACHE_ID 0x000
24#define L2X0_CACHE_TYPE 0x004
25#define L2X0_CTRL 0x100
26#define L2X0_AUX_CTRL 0x104
27#define L2X0_EVENT_CNT_CTRL 0x200
28#define L2X0_EVENT_CNT1_CFG 0x204
29#define L2X0_EVENT_CNT0_CFG 0x208
30#define L2X0_EVENT_CNT1_VAL 0x20C
31#define L2X0_EVENT_CNT0_VAL 0x210
32#define L2X0_INTR_MASK 0x214
33#define L2X0_MASKED_INTR_STAT 0x218
34#define L2X0_RAW_INTR_STAT 0x21C
35#define L2X0_INTR_CLEAR 0x220
36#define L2X0_CACHE_SYNC 0x730
37#define L2X0_INV_LINE_PA 0x770
38#define L2X0_INV_WAY 0x77C
39#define L2X0_CLEAN_LINE_PA 0x7B0
40#define L2X0_CLEAN_LINE_IDX 0x7B8
41#define L2X0_CLEAN_WAY 0x7BC
42#define L2X0_CLEAN_INV_LINE_PA 0x7F0
43#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
44#define L2X0_CLEAN_INV_WAY 0x7FC
45#define L2X0_LOCKDOWN_WAY_D 0x900
46#define L2X0_LOCKDOWN_WAY_I 0x904
47#define L2X0_TEST_OPERATION 0xF00
48#define L2X0_LINE_DATA 0xF10
49#define L2X0_LINE_TAG 0xF30
50#define L2X0_DEBUG_CTRL 0xF40
51
52#ifndef __ASSEMBLY__
53extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
54#endif
55
56#endif
diff --git a/include/asm-arm/hardware/gic.h b/include/asm-arm/hardware/gic.h
index 3fa5eb70f64e..966e428ad32c 100644
--- a/include/asm-arm/hardware/gic.h
+++ b/include/asm-arm/hardware/gic.h
@@ -33,8 +33,9 @@
33#define GIC_DIST_SOFTINT 0xf00 33#define GIC_DIST_SOFTINT 0xf00
34 34
35#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
36void gic_dist_init(void __iomem *base); 36void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start);
37void gic_cpu_init(void __iomem *base); 37void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
38void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
38void gic_raise_softirq(cpumask_t cpumask, unsigned int irq); 39void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
39#endif 40#endif
40 41
diff --git a/include/asm-arm/hardware/sa1111.h b/include/asm-arm/hardware/sa1111.h
index 6aa0a5b75b69..61b1d05c7df7 100644
--- a/include/asm-arm/hardware/sa1111.h
+++ b/include/asm-arm/hardware/sa1111.h
@@ -29,6 +29,9 @@
29#define _SA1111(x) ((x) + sa1111->resource.start) 29#define _SA1111(x) ((x) + sa1111->resource.start)
30#endif 30#endif
31 31
32#define sa1111_writel(val,addr) __raw_writel(val, addr)
33#define sa1111_readl(addr) __raw_readl(addr)
34
32/* 35/*
33 * 26 bits of the SA-1110 address bus are available to the SA-1111. 36 * 26 bits of the SA-1110 address bus are available to the SA-1111.
34 * Use these when feeding target addresses to the DMA engines. 37 * Use these when feeding target addresses to the DMA engines.
@@ -45,14 +48,6 @@
45#define SA1111_SAC_DMA_MIN_XFER (0x800) 48#define SA1111_SAC_DMA_MIN_XFER (0x800)
46 49
47/* 50/*
48 * SA1111 register definitions.
49 */
50#define __CCREG(x) __REGP(SA1111_VBASE + (x))
51
52#define sa1111_writel(val,addr) __raw_writel(val, addr)
53#define sa1111_readl(addr) __raw_readl(addr)
54
55/*
56 * System Bus Interface (SBI) 51 * System Bus Interface (SBI)
57 * 52 *
58 * Registers 53 * Registers
@@ -194,55 +189,37 @@
194 * SADR Serial Audio Data Register (16 x 32-bit) 189 * SADR Serial Audio Data Register (16 x 32-bit)
195 */ 190 */
196 191
197#define _SACR0 _SA1111( 0x0600 ) 192#define SA1111_SERAUDIO 0x0600
198#define _SACR1 _SA1111( 0x0604 ) 193
199#define _SACR2 _SA1111( 0x0608 ) 194/*
200#define _SASR0 _SA1111( 0x060c ) 195 * These are offsets from the above base.
201#define _SASR1 _SA1111( 0x0610 ) 196 */
202#define _SASCR _SA1111( 0x0618 ) 197#define SA1111_SACR0 0x00
203#define _L3_CAR _SA1111( 0x061c ) 198#define SA1111_SACR1 0x04
204#define _L3_CDR _SA1111( 0x0620 ) 199#define SA1111_SACR2 0x08
205#define _ACCAR _SA1111( 0x0624 ) 200#define SA1111_SASR0 0x0c
206#define _ACCDR _SA1111( 0x0628 ) 201#define SA1111_SASR1 0x10
207#define _ACSAR _SA1111( 0x062c ) 202#define SA1111_SASCR 0x18
208#define _ACSDR _SA1111( 0x0630 ) 203#define SA1111_L3_CAR 0x1c
209#define _SADTCS _SA1111( 0x0634 ) 204#define SA1111_L3_CDR 0x20
210#define _SADTSA _SA1111( 0x0638 ) 205#define SA1111_ACCAR 0x24
211#define _SADTCA _SA1111( 0x063c ) 206#define SA1111_ACCDR 0x28
212#define _SADTSB _SA1111( 0x0640 ) 207#define SA1111_ACSAR 0x2c
213#define _SADTCB _SA1111( 0x0644 ) 208#define SA1111_ACSDR 0x30
214#define _SADRCS _SA1111( 0x0648 ) 209#define SA1111_SADTCS 0x34
215#define _SADRSA _SA1111( 0x064c ) 210#define SA1111_SADTSA 0x38
216#define _SADRCA _SA1111( 0x0650 ) 211#define SA1111_SADTCA 0x3c
217#define _SADRSB _SA1111( 0x0654 ) 212#define SA1111_SADTSB 0x40
218#define _SADRCB _SA1111( 0x0658 ) 213#define SA1111_SADTCB 0x44
219#define _SAITR _SA1111( 0x065c ) 214#define SA1111_SADRCS 0x48
220#define _SADR _SA1111( 0x0680 ) 215#define SA1111_SADRSA 0x4c
221 216#define SA1111_SADRCA 0x50
222#define SACR0 __CCREG(0x0600) 217#define SA1111_SADRSB 0x54
223#define SACR1 __CCREG(0x0604) 218#define SA1111_SADRCB 0x58
224#define SACR2 __CCREG(0x0608) 219#define SA1111_SAITR 0x5c
225#define SASR0 __CCREG(0x060c) 220#define SA1111_SADR 0x80
226#define SASR1 __CCREG(0x0610) 221
227#define SASCR __CCREG(0x0618) 222#ifndef CONFIG_ARCH_PXA
228#define L3_CAR __CCREG(0x061c)
229#define L3_CDR __CCREG(0x0620)
230#define ACCAR __CCREG(0x0624)
231#define ACCDR __CCREG(0x0628)
232#define ACSAR __CCREG(0x062c)
233#define ACSDR __CCREG(0x0630)
234#define SADTCS __CCREG(0x0634)
235#define SADTSA __CCREG(0x0638)
236#define SADTCA __CCREG(0x063c)
237#define SADTSB __CCREG(0x0640)
238#define SADTCB __CCREG(0x0644)
239#define SADRCS __CCREG(0x0648)
240#define SADRSA __CCREG(0x064c)
241#define SADRCA __CCREG(0x0650)
242#define SADRSB __CCREG(0x0654)
243#define SADRCB __CCREG(0x0658)
244#define SAITR __CCREG(0x065c)
245#define SADR __CCREG(0x0680)
246 223
247#define SACR0_ENB (1<<0) 224#define SACR0_ENB (1<<0)
248#define SACR0_BCKD (1<<2) 225#define SACR0_BCKD (1<<2)
@@ -330,6 +307,8 @@
330#define SAITR_RDBDA (1<<10) 307#define SAITR_RDBDA (1<<10)
331#define SAITR_RDBDB (1<<11) 308#define SAITR_RDBDB (1<<11)
332 309
310#endif /* !CONFIG_ARCH_PXA */
311
333/* 312/*
334 * General-Purpose I/O Interface 313 * General-Purpose I/O Interface
335 * 314 *
diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h
new file mode 100644
index 000000000000..8c1c6162a80c
--- /dev/null
+++ b/include/asm-arm/kexec.h
@@ -0,0 +1,30 @@
1#ifndef _ARM_KEXEC_H
2#define _ARM_KEXEC_H
3
4#ifdef CONFIG_KEXEC
5
6/* Maximum physical address we can use pages from */
7#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
8/* Maximum address we can reach in physical address mode */
9#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
10/* Maximum address we can use for the control code buffer */
11#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
12
13#define KEXEC_CONTROL_CODE_SIZE 4096
14
15#define KEXEC_ARCH KEXEC_ARCH_ARM
16
17#ifndef __ASSEMBLY__
18
19#define MAX_NOTE_BYTES 1024
20
21struct kimage;
22/* Provide a dummy definition to avoid build failures. */
23static inline void crash_setup_regs(struct pt_regs *newregs,
24 struct pt_regs *oldregs) { }
25
26#endif /* __ASSEMBLY__ */
27
28#endif /* CONFIG_KEXEC */
29
30#endif /* _ARM_KEXEC_H */
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index b8cf2d5ec304..7b2bafce21a2 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -175,19 +175,29 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
175#ifndef __ASSEMBLY__ 175#ifndef __ASSEMBLY__
176 176
177/* 177/*
178 * The following macros handle the cache and bufferable bits... 178 * The pgprot_* and protection_map entries will be fixed up in runtime
179 * to include the cachable and bufferable bits based on memory policy,
180 * as well as any architecture dependent bits like global/ASID and SMP
181 * shared mapping bits.
179 */ 182 */
180#define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_CACHEABLE | L_PTE_BUFFERABLE 183#define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_CACHEABLE | L_PTE_BUFFERABLE
181#define _L_PTE_READ L_PTE_USER | L_PTE_EXEC 184#define _L_PTE_READ L_PTE_USER | L_PTE_EXEC
182 185
186extern pgprot_t pgprot_user;
183extern pgprot_t pgprot_kernel; 187extern pgprot_t pgprot_kernel;
184 188
185#define PAGE_NONE __pgprot(_L_PTE_DEFAULT) 189#define PAGE_NONE pgprot_user
186#define PAGE_COPY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ) 190#define PAGE_COPY __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ)
187#define PAGE_SHARED __pgprot(_L_PTE_DEFAULT | _L_PTE_READ | L_PTE_WRITE) 191#define PAGE_SHARED __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ | \
188#define PAGE_READONLY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ) 192 L_PTE_WRITE)
193#define PAGE_READONLY __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ)
189#define PAGE_KERNEL pgprot_kernel 194#define PAGE_KERNEL pgprot_kernel
190 195
196#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT)
197#define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
198#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | _L_PTE_READ | L_PTE_WRITE)
199#define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
200
191#endif /* __ASSEMBLY__ */ 201#endif /* __ASSEMBLY__ */
192 202
193/* 203/*
@@ -198,23 +208,23 @@ extern pgprot_t pgprot_kernel;
198 * 2) If we could do execute protection, then read is implied 208 * 2) If we could do execute protection, then read is implied
199 * 3) write implies read permissions 209 * 3) write implies read permissions
200 */ 210 */
201#define __P000 PAGE_NONE 211#define __P000 __PAGE_NONE
202#define __P001 PAGE_READONLY 212#define __P001 __PAGE_READONLY
203#define __P010 PAGE_COPY 213#define __P010 __PAGE_COPY
204#define __P011 PAGE_COPY 214#define __P011 __PAGE_COPY
205#define __P100 PAGE_READONLY 215#define __P100 __PAGE_READONLY
206#define __P101 PAGE_READONLY 216#define __P101 __PAGE_READONLY
207#define __P110 PAGE_COPY 217#define __P110 __PAGE_COPY
208#define __P111 PAGE_COPY 218#define __P111 __PAGE_COPY
209 219
210#define __S000 PAGE_NONE 220#define __S000 __PAGE_NONE
211#define __S001 PAGE_READONLY 221#define __S001 __PAGE_READONLY
212#define __S010 PAGE_SHARED 222#define __S010 __PAGE_SHARED
213#define __S011 PAGE_SHARED 223#define __S011 __PAGE_SHARED
214#define __S100 PAGE_READONLY 224#define __S100 __PAGE_READONLY
215#define __S101 PAGE_READONLY 225#define __S101 __PAGE_READONLY
216#define __S110 PAGE_SHARED 226#define __S110 __PAGE_SHARED
217#define __S111 PAGE_SHARED 227#define __S111 __PAGE_SHARED
218 228
219#ifndef __ASSEMBLY__ 229#ifndef __ASSEMBLY__
220/* 230/*
diff --git a/include/asm-arm/plat-s3c24xx/clock.h b/include/asm-arm/plat-s3c24xx/clock.h
new file mode 100644
index 000000000000..f6135dbb9fa9
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/clock.h
@@ -0,0 +1,63 @@
1/* linux/include/asm-arm/plat-s3c24xx/clock.h
2 * linux/arch/arm/mach-s3c2410/clock.h
3 *
4 * Copyright (c) 2004-2005 Simtec Electronics
5 * http://www.simtec.co.uk/products/SWLINUX/
6 * Written by Ben Dooks, <ben@simtec.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct clk {
14 struct list_head list;
15 struct module *owner;
16 struct clk *parent;
17 const char *name;
18 int id;
19 int usage;
20 unsigned long rate;
21 unsigned long ctrlbit;
22
23 int (*enable)(struct clk *, int enable);
24 int (*set_rate)(struct clk *c, unsigned long rate);
25 unsigned long (*get_rate)(struct clk *c);
26 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
27 int (*set_parent)(struct clk *c, struct clk *parent);
28};
29
30/* other clocks which may be registered by board support */
31
32extern struct clk s3c24xx_dclk0;
33extern struct clk s3c24xx_dclk1;
34extern struct clk s3c24xx_clkout0;
35extern struct clk s3c24xx_clkout1;
36extern struct clk s3c24xx_uclk;
37
38extern struct clk clk_usb_bus;
39
40/* core clock support */
41
42extern struct clk clk_f;
43extern struct clk clk_h;
44extern struct clk clk_p;
45extern struct clk clk_mpll;
46extern struct clk clk_upll;
47extern struct clk clk_xtal;
48
49/* exports for arch/arm/mach-s3c2410
50 *
51 * Please DO NOT use these outside of arch/arm/mach-s3c2410
52*/
53
54extern struct mutex clocks_mutex;
55
56extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
57
58extern int s3c24xx_register_clock(struct clk *clk);
59
60extern int s3c24xx_setup_clocks(unsigned long xtal,
61 unsigned long fclk,
62 unsigned long hclk,
63 unsigned long pclk);
diff --git a/include/asm-arm/plat-s3c24xx/common-smdk.h b/include/asm-arm/plat-s3c24xx/common-smdk.h
new file mode 100644
index 000000000000..58d9094c935c
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/common-smdk.h
@@ -0,0 +1,15 @@
1/* linux/include/asm-arm/plat-s3c24xx/common-smdk.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Common code for SMDK2410 and SMDK2440 boards
7 *
8 * http://www.fluff.org/ben/smdk2440/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern void smdk_machine_init(void);
diff --git a/include/asm-arm/plat-s3c24xx/cpu.h b/include/asm-arm/plat-s3c24xx/cpu.h
new file mode 100644
index 000000000000..15dd18810905
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/cpu.h
@@ -0,0 +1,70 @@
1/* linux/include/asm-arm/plat-s3c24xx/cpu.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* todo - fix when rmk changes iodescs to use `void __iomem *` */
14
15#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
16
17#ifndef MHZ
18#define MHZ (1000*1000)
19#endif
20
21#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
22
23/* forward declaration */
24struct s3c24xx_uart_resources;
25struct platform_device;
26struct s3c2410_uartcfg;
27struct map_desc;
28
29/* core initialisation functions */
30
31extern void s3c24xx_init_irq(void);
32
33extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
34
35extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
36
37extern void s3c24xx_init_clocks(int xtal);
38
39extern void s3c24xx_init_uartdevs(char *name,
40 struct s3c24xx_uart_resources *res,
41 struct s3c2410_uartcfg *cfg, int no);
42
43/* the board structure is used at first initialsation time
44 * to get info such as the devices to register for this
45 * board. This is done because platfrom_add_devices() cannot
46 * be called from the map_io entry.
47*/
48
49struct s3c24xx_board {
50 struct platform_device **devices;
51 unsigned int devices_count;
52
53 struct clk **clocks;
54 unsigned int clocks_count;
55};
56
57extern void s3c24xx_set_board(struct s3c24xx_board *board);
58
59/* timer for 2410/2440 */
60
61struct sys_timer;
62extern struct sys_timer s3c24xx_timer;
63
64/* system device classes */
65
66extern struct sysdev_class s3c2410_sysclass;
67extern struct sysdev_class s3c2412_sysclass;
68extern struct sysdev_class s3c2440_sysclass;
69extern struct sysdev_class s3c2442_sysclass;
70extern struct sysdev_class s3c2443_sysclass;
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
new file mode 100644
index 000000000000..dddf485fc067
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/devs.h
@@ -0,0 +1,51 @@
1/* linux/include/asm-arm/plat-s3c24xx/devs.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2410 standard platform devices
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12#include <linux/platform_device.h>
13
14struct s3c24xx_uart_resources {
15 struct resource *resources;
16 unsigned long nr_resources;
17};
18
19extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
20
21extern struct platform_device *s3c24xx_uart_devs[];
22extern struct platform_device *s3c24xx_uart_src[];
23
24extern struct platform_device s3c_device_usb;
25extern struct platform_device s3c_device_lcd;
26extern struct platform_device s3c_device_wdt;
27extern struct platform_device s3c_device_i2c;
28extern struct platform_device s3c_device_iis;
29extern struct platform_device s3c_device_rtc;
30extern struct platform_device s3c_device_adc;
31extern struct platform_device s3c_device_sdi;
32
33extern struct platform_device s3c_device_spi0;
34extern struct platform_device s3c_device_spi1;
35
36extern struct platform_device s3c_device_nand;
37
38extern struct platform_device s3c_device_timer0;
39extern struct platform_device s3c_device_timer1;
40extern struct platform_device s3c_device_timer2;
41extern struct platform_device s3c_device_timer3;
42
43extern struct platform_device s3c_device_usbgadget;
44
45/* s3c2440 specific devices */
46
47#ifdef CONFIG_CPU_S3C2440
48
49extern struct platform_device s3c_device_camif;
50
51#endif
diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/include/asm-arm/plat-s3c24xx/dma.h
new file mode 100644
index 000000000000..2c59406435e5
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/dma.h
@@ -0,0 +1,77 @@
1/* linux/include/asm-arm/plat-s3c24xx/dma.h
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern struct sysdev_class dma_sysclass;
14extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
15
16#define DMA_CH_VALID (1<<31)
17#define DMA_CH_NEVER (1<<30)
18
19struct s3c24xx_dma_addr {
20 unsigned long from;
21 unsigned long to;
22};
23
24/* struct s3c24xx_dma_map
25 *
26 * this holds the mapping information for the channel selected
27 * to be connected to the specified device
28*/
29
30struct s3c24xx_dma_map {
31 const char *name;
32 struct s3c24xx_dma_addr hw_addr;
33
34 unsigned long channels[S3C2410_DMA_CHANNELS];
35};
36
37struct s3c24xx_dma_selection {
38 struct s3c24xx_dma_map *map;
39 unsigned long map_size;
40 unsigned long dcon_mask;
41
42 void (*select)(struct s3c2410_dma_chan *chan,
43 struct s3c24xx_dma_map *map);
44};
45
46extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
47
48/* struct s3c24xx_dma_order_ch
49 *
50 * channel map for one of the `enum dma_ch` dma channels. the list
51 * entry contains a set of low-level channel numbers, orred with
52 * DMA_CH_VALID, which are checked in the order in the array.
53*/
54
55struct s3c24xx_dma_order_ch {
56 unsigned int list[S3C2410_DMA_CHANNELS]; /* list of channels */
57 unsigned int flags; /* flags */
58};
59
60/* struct s3c24xx_dma_order
61 *
62 * information provided by either the core or the board to give the
63 * dma system a hint on how to allocate channels
64*/
65
66struct s3c24xx_dma_order {
67 struct s3c24xx_dma_order_ch channels[DMACH_MAX];
68};
69
70extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
71
72/* DMA init code, called from the cpu support code */
73
74extern int s3c2410_dma_init(void);
75
76extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
77 unsigned int stride);
diff --git a/include/asm-arm/plat-s3c24xx/irq.h b/include/asm-arm/plat-s3c24xx/irq.h
new file mode 100644
index 000000000000..8af6d9579b31
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/irq.h
@@ -0,0 +1,107 @@
1/* linux/include/asm-arm/plat-s3c24xx/irq.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#define irqdbf(x...)
14#define irqdbf2(x...)
15
16#define EXTINT_OFF (IRQ_EINT4 - 4)
17
18extern struct irq_chip s3c_irq_level_chip;
19
20static inline void
21s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
22 int subcheck)
23{
24 unsigned long mask;
25 unsigned long submask;
26
27 submask = __raw_readl(S3C2410_INTSUBMSK);
28 mask = __raw_readl(S3C2410_INTMSK);
29
30 submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
31
32 /* check to see if we need to mask the parent IRQ */
33
34 if ((submask & subcheck) == subcheck) {
35 __raw_writel(mask | parentbit, S3C2410_INTMSK);
36 }
37
38 /* write back masks */
39 __raw_writel(submask, S3C2410_INTSUBMSK);
40
41}
42
43static inline void
44s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
45{
46 unsigned long mask;
47 unsigned long submask;
48
49 submask = __raw_readl(S3C2410_INTSUBMSK);
50 mask = __raw_readl(S3C2410_INTMSK);
51
52 submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
53 mask &= ~parentbit;
54
55 /* write back masks */
56 __raw_writel(submask, S3C2410_INTSUBMSK);
57 __raw_writel(mask, S3C2410_INTMSK);
58}
59
60
61static inline void
62s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
63{
64 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
65
66 s3c_irqsub_mask(irqno, parentmask, group);
67
68 __raw_writel(bit, S3C2410_SUBSRCPND);
69
70 /* only ack parent if we've got all the irqs (seems we must
71 * ack, all and hope that the irq system retriggers ok when
72 * the interrupt goes off again)
73 */
74
75 if (1) {
76 __raw_writel(parentmask, S3C2410_SRCPND);
77 __raw_writel(parentmask, S3C2410_INTPND);
78 }
79}
80
81static inline void
82s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
83{
84 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
85
86 __raw_writel(bit, S3C2410_SUBSRCPND);
87
88 /* only ack parent if we've got all the irqs (seems we must
89 * ack, all and hope that the irq system retriggers ok when
90 * the interrupt goes off again)
91 */
92
93 if (1) {
94 __raw_writel(parentmask, S3C2410_SRCPND);
95 __raw_writel(parentmask, S3C2410_INTPND);
96 }
97}
98
99/* exported for use in arch/arm/mach-s3c2410 */
100
101#ifdef CONFIG_PM
102extern int s3c_irq_wake(unsigned int irqno, unsigned int state);
103#else
104#define s3c_irq_wake NULL
105#endif
106
107extern int s3c_irqext_type(unsigned int irq, unsigned int type);
diff --git a/include/asm-arm/plat-s3c24xx/pm.h b/include/asm-arm/plat-s3c24xx/pm.h
new file mode 100644
index 000000000000..cc623667e48a
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/pm.h
@@ -0,0 +1,73 @@
1/* linux/include/asm-arm/plat-s3c24xx/pm.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Written by Ben Dooks, <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* s3c2410_pm_init
12 *
13 * called from board at initialisation time to setup the power
14 * management
15*/
16
17#ifdef CONFIG_PM
18
19extern __init int s3c2410_pm_init(void);
20
21#else
22
23static inline int s3c2410_pm_init(void)
24{
25 return 0;
26}
27#endif
28
29/* configuration for the IRQ mask over sleep */
30extern unsigned long s3c_irqwake_intmask;
31extern unsigned long s3c_irqwake_eintmask;
32
33/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
34extern unsigned long s3c_irqwake_intallow;
35extern unsigned long s3c_irqwake_eintallow;
36
37/* per-cpu sleep functions */
38
39extern void (*pm_cpu_prep)(void);
40extern void (*pm_cpu_sleep)(void);
41
42/* Flags for PM Control */
43
44extern unsigned long s3c_pm_flags;
45
46/* from sleep.S */
47
48extern int s3c2410_cpu_save(unsigned long *saveblk);
49extern void s3c2410_cpu_suspend(void);
50extern void s3c2410_cpu_resume(void);
51
52extern unsigned long s3c2410_sleep_save_phys;
53
54/* sleep save info */
55
56struct sleep_save {
57 void __iomem *reg;
58 unsigned long val;
59};
60
61#define SAVE_ITEM(x) \
62 { .reg = (x) }
63
64extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
65extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
66
67#ifdef CONFIG_PM
68extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
69extern int s3c24xx_irq_resume(struct sys_device *dev);
70#else
71#define s3c24xx_irq_suspend NULL
72#define s3c24xx_irq_resume NULL
73#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2400.h b/include/asm-arm/plat-s3c24xx/s3c2400.h
new file mode 100644
index 000000000000..3a5a16821af8
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/s3c2400.h
@@ -0,0 +1,31 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2400.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C2400 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13 * 09-Fev-2006 LCVR First version, based on s3c2410.h
14*/
15
16#ifdef CONFIG_CPU_S3C2400
17
18extern int s3c2400_init(void);
19
20extern void s3c2400_map_io(struct map_desc *mach_desc, int size);
21
22extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
23
24extern void s3c2400_init_clocks(int xtal);
25
26#else
27#define s3c2400_init_clocks NULL
28#define s3c2400_init_uarts NULL
29#define s3c2400_map_io NULL
30#define s3c2400_init NULL
31#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2410.h b/include/asm-arm/plat-s3c24xx/s3c2410.h
new file mode 100644
index 000000000000..36de0b835873
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/s3c2410.h
@@ -0,0 +1,31 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2410.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2410 machine directory
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#ifdef CONFIG_CPU_S3C2410
15
16extern int s3c2410_init(void);
17
18extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
19
20extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
21
22extern void s3c2410_init_clocks(int xtal);
23
24extern int s3c2410_baseclk_add(void);
25
26#else
27#define s3c2410_init_clocks NULL
28#define s3c2410_init_uarts NULL
29#define s3c2410_map_io NULL
30#define s3c2410_init NULL
31#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2412.h b/include/asm-arm/plat-s3c24xx/s3c2412.h
new file mode 100644
index 000000000000..3ec97685e781
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/s3c2412.h
@@ -0,0 +1,29 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2412.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2412 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2412
14
15extern int s3c2412_init(void);
16
17extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
18
19extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
20
21extern void s3c2412_init_clocks(int xtal);
22
23extern int s3c2412_baseclk_add(void);
24#else
25#define s3c2412_init_clocks NULL
26#define s3c2412_init_uarts NULL
27#define s3c2412_map_io NULL
28#define s3c2412_init NULL
29#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2440.h b/include/asm-arm/plat-s3c24xx/s3c2440.h
new file mode 100644
index 000000000000..107853bf9481
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/s3c2440.h
@@ -0,0 +1,17 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2440.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2440 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2440
14extern int s3c2440_init(void);
15#else
16#define s3c2440_init NULL
17#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2442.h b/include/asm-arm/plat-s3c24xx/s3c2442.h
new file mode 100644
index 000000000000..451a23a2092a
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/s3c2442.h
@@ -0,0 +1,17 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2442.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2442 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2442
14extern int s3c2442_init(void);
15#else
16#define s3c2442_init NULL
17#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2443.h b/include/asm-arm/plat-s3c24xx/s3c2443.h
new file mode 100644
index 000000000000..11d83b5c84e6
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/s3c2443.h
@@ -0,0 +1,32 @@
1/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2443 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2443
14
15struct s3c2410_uartcfg;
16
17extern int s3c2443_init(void);
18
19extern void s3c2443_map_io(struct map_desc *mach_desc, int size);
20
21extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
22
23extern void s3c2443_init_clocks(int xtal);
24
25extern int s3c2443_baseclk_add(void);
26
27#else
28#define s3c2443_init_clocks NULL
29#define s3c2443_init_uarts NULL
30#define s3c2443_map_io NULL
31#define s3c2443_init NULL
32#endif
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index aa223fc546af..f4386906b200 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -140,6 +140,40 @@ static inline int cpu_is_xsc3(void)
140#define cpu_is_xscale() 1 140#define cpu_is_xscale() 1
141#endif 141#endif
142 142
143#define UDBG_UNDEFINED (1 << 0)
144#define UDBG_SYSCALL (1 << 1)
145#define UDBG_BADABORT (1 << 2)
146#define UDBG_SEGV (1 << 3)
147#define UDBG_BUS (1 << 4)
148
149extern unsigned int user_debug;
150
151#if __LINUX_ARM_ARCH__ >= 4
152#define vectors_high() (cr_alignment & CR_V)
153#else
154#define vectors_high() (0)
155#endif
156
157#if __LINUX_ARM_ARCH__ >= 6
158#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
159 : : "r" (0) : "memory")
160#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
161 : : "r" (0) : "memory")
162#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
163 : : "r" (0) : "memory")
164#else
165#define isb() __asm__ __volatile__ ("" : : : "memory")
166#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
167 : : "r" (0) : "memory")
168#define dmb() __asm__ __volatile__ ("" : : : "memory")
169#endif
170#define mb() dmb()
171#define rmb() mb()
172#define wmb() mb()
173#define read_barrier_depends() do { } while(0)
174#define set_mb(var, value) do { var = value; mb(); } while (0)
175#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
176
143extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ 177extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
144extern unsigned long cr_alignment; /* defined in entry-armv.S */ 178extern unsigned long cr_alignment; /* defined in entry-armv.S */
145 179
@@ -154,6 +188,7 @@ static inline void set_cr(unsigned int val)
154{ 188{
155 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" 189 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
156 : : "r" (val) : "cc"); 190 : : "r" (val) : "cc");
191 isb();
157} 192}
158 193
159#ifndef CONFIG_SMP 194#ifndef CONFIG_SMP
@@ -176,34 +211,9 @@ static inline void set_copro_access(unsigned int val)
176{ 211{
177 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access" 212 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
178 : : "r" (val) : "cc"); 213 : : "r" (val) : "cc");
214 isb();
179} 215}
180 216
181#define UDBG_UNDEFINED (1 << 0)
182#define UDBG_SYSCALL (1 << 1)
183#define UDBG_BADABORT (1 << 2)
184#define UDBG_SEGV (1 << 3)
185#define UDBG_BUS (1 << 4)
186
187extern unsigned int user_debug;
188
189#if __LINUX_ARM_ARCH__ >= 4
190#define vectors_high() (cr_alignment & CR_V)
191#else
192#define vectors_high() (0)
193#endif
194
195#if __LINUX_ARM_ARCH__ >= 6
196#define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
197 : : "r" (0) : "memory")
198#else
199#define mb() __asm__ __volatile__ ("" : : : "memory")
200#endif
201#define rmb() mb()
202#define wmb() mb()
203#define read_barrier_depends() do { } while(0)
204#define set_mb(var, value) do { var = value; mb(); } while (0)
205#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
206
207/* 217/*
208 * switch_mm() may do a full cache flush over the context switch, 218 * switch_mm() may do a full cache flush over the context switch,
209 * so enable interrupts over the context switch to avoid high 219 * so enable interrupts over the context switch to avoid high
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index cd10a0b5f8ae..08c6991dc9c9 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -247,7 +247,7 @@ static inline void local_flush_tlb_all(void)
247 const unsigned int __tlb_flag = __cpu_tlb_flags; 247 const unsigned int __tlb_flag = __cpu_tlb_flags;
248 248
249 if (tlb_flag(TLB_WB)) 249 if (tlb_flag(TLB_WB))
250 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); 250 dsb();
251 251
252 if (tlb_flag(TLB_V3_FULL)) 252 if (tlb_flag(TLB_V3_FULL))
253 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); 253 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
@@ -257,6 +257,15 @@ static inline void local_flush_tlb_all(void)
257 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); 257 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
258 if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) 258 if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
259 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); 259 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
260
261 if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
262 TLB_V6_I_PAGE | TLB_V6_D_PAGE |
263 TLB_V6_I_ASID | TLB_V6_D_ASID)) {
264 /* flush the branch target cache */
265 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
266 dsb();
267 isb();
268 }
260} 269}
261 270
262static inline void local_flush_tlb_mm(struct mm_struct *mm) 271static inline void local_flush_tlb_mm(struct mm_struct *mm)
@@ -266,7 +275,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
266 const unsigned int __tlb_flag = __cpu_tlb_flags; 275 const unsigned int __tlb_flag = __cpu_tlb_flags;
267 276
268 if (tlb_flag(TLB_WB)) 277 if (tlb_flag(TLB_WB))
269 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); 278 dsb();
270 279
271 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) { 280 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
272 if (tlb_flag(TLB_V3_FULL)) 281 if (tlb_flag(TLB_V3_FULL))
@@ -285,6 +294,14 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
285 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); 294 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
286 if (tlb_flag(TLB_V6_I_ASID)) 295 if (tlb_flag(TLB_V6_I_ASID))
287 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); 296 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
297
298 if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
299 TLB_V6_I_PAGE | TLB_V6_D_PAGE |
300 TLB_V6_I_ASID | TLB_V6_D_ASID)) {
301 /* flush the branch target cache */
302 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
303 dsb();
304 }
288} 305}
289 306
290static inline void 307static inline void
@@ -296,7 +313,7 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
296 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); 313 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
297 314
298 if (tlb_flag(TLB_WB)) 315 if (tlb_flag(TLB_WB))
299 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero)); 316 dsb();
300 317
301 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { 318 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
302 if (tlb_flag(TLB_V3_PAGE)) 319 if (tlb_flag(TLB_V3_PAGE))
@@ -317,6 +334,14 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
317 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); 334 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
318 if (tlb_flag(TLB_V6_I_PAGE)) 335 if (tlb_flag(TLB_V6_I_PAGE))
319 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); 336 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
337
338 if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
339 TLB_V6_I_PAGE | TLB_V6_D_PAGE |
340 TLB_V6_I_ASID | TLB_V6_D_ASID)) {
341 /* flush the branch target cache */
342 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
343 dsb();
344 }
320} 345}
321 346
322static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 347static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
@@ -327,7 +352,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
327 kaddr &= PAGE_MASK; 352 kaddr &= PAGE_MASK;
328 353
329 if (tlb_flag(TLB_WB)) 354 if (tlb_flag(TLB_WB))
330 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); 355 dsb();
331 356
332 if (tlb_flag(TLB_V3_PAGE)) 357 if (tlb_flag(TLB_V3_PAGE))
333 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc"); 358 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
@@ -347,11 +372,14 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
347 if (tlb_flag(TLB_V6_I_PAGE)) 372 if (tlb_flag(TLB_V6_I_PAGE))
348 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); 373 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
349 374
350 /* The ARM ARM states that the completion of a TLB maintenance 375 if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
351 * operation is only guaranteed by a DSB instruction 376 TLB_V6_I_PAGE | TLB_V6_D_PAGE |
352 */ 377 TLB_V6_I_ASID | TLB_V6_D_ASID)) {
353 if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE)) 378 /* flush the branch target cache */
354 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); 379 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
380 dsb();
381 isb();
382 }
355} 383}
356 384
357/* 385/*
@@ -369,15 +397,13 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
369 */ 397 */
370static inline void flush_pmd_entry(pmd_t *pmd) 398static inline void flush_pmd_entry(pmd_t *pmd)
371{ 399{
372 const unsigned int zero = 0;
373 const unsigned int __tlb_flag = __cpu_tlb_flags; 400 const unsigned int __tlb_flag = __cpu_tlb_flags;
374 401
375 if (tlb_flag(TLB_DCLEAN)) 402 if (tlb_flag(TLB_DCLEAN))
376 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" 403 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
377 : : "r" (pmd) : "cc"); 404 : : "r" (pmd) : "cc");
378 if (tlb_flag(TLB_WB)) 405 if (tlb_flag(TLB_WB))
379 asm("mcr p15, 0, %0, c7, c10, 4 @ flush_pmd" 406 dsb();
380 : : "r" (zero) : "cc");
381} 407}
382 408
383static inline void clean_pmd_entry(pmd_t *pmd) 409static inline void clean_pmd_entry(pmd_t *pmd)
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index 97e7060000cf..0991b7bc3f78 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -372,6 +372,7 @@
372#define __NR_move_pages (__NR_SYSCALL_BASE+344) 372#define __NR_move_pages (__NR_SYSCALL_BASE+344)
373#define __NR_getcpu (__NR_SYSCALL_BASE+345) 373#define __NR_getcpu (__NR_SYSCALL_BASE+345)
374 /* 346 for epoll_pwait */ 374 /* 346 for epoll_pwait */
375#define __NR_sys_kexec_load (__NR_SYSCALL_BASE+347)
375 376
376/* 377/*
377 * The following SWIs are ARM private. 378 * The following SWIs are ARM private.
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index d02425cdd801..696e5ec63f77 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -125,6 +125,7 @@ extern struct kimage *kexec_crash_image;
125#define KEXEC_ARCH_PPC (20 << 16) 125#define KEXEC_ARCH_PPC (20 << 16)
126#define KEXEC_ARCH_PPC64 (21 << 16) 126#define KEXEC_ARCH_PPC64 (21 << 16)
127#define KEXEC_ARCH_IA_64 (50 << 16) 127#define KEXEC_ARCH_IA_64 (50 << 16)
128#define KEXEC_ARCH_ARM (40 << 16)
128#define KEXEC_ARCH_S390 (22 << 16) 129#define KEXEC_ARCH_S390 (22 << 16)
129#define KEXEC_ARCH_SH (42 << 16) 130#define KEXEC_ARCH_SH (42 << 16)
130#define KEXEC_ARCH_MIPS_LE (10 << 16) 131#define KEXEC_ARCH_MIPS_LE (10 << 16)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 12:24:40 -0500